diff --git a/CHANGELOG.md b/CHANGELOG.md index f0837aa2ee..95612901ad 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,13 @@ # Changelog +## Release 550 Entries + +### [550.40.07] 2024-01-24 + +#### Fixed + +- Set INSTALL_MOD_DIR only if it's not defined, [#570](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/570) by @keelung-yang + ## Release 545 Entries ### [545.29.06] 2023-11-22 diff --git a/README.md b/README.md index b5f19a1adf..a87546b806 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 545.29.06. +version 550.40.07. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -545.29.06 driver release. This can be achieved by installing +550.40.07 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -188,7 +188,7 @@ encountered specific to them. For details on feature support and limitations, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/545.29.06/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/550.40.07/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI @@ -683,6 +683,7 @@ Subsystem Device ID. | NVIDIA A800 40GB Active | 20F6 103C 180A | | NVIDIA A800 40GB Active | 20F6 10DE 180A | | NVIDIA A800 40GB Active | 20F6 17AA 180A | +| NVIDIA AX800 | 20FD 10DE 17F8 | | NVIDIA GeForce GTX 1660 Ti | 2182 | | NVIDIA GeForce GTX 1660 | 2184 | | NVIDIA GeForce GTX 1650 SUPER | 2187 | @@ -836,6 +837,7 @@ Subsystem Device ID. | NVIDIA RTX A2000 Embedded GPU | 25FA | | NVIDIA RTX A500 Embedded GPU | 25FB | | NVIDIA GeForce RTX 4090 | 2684 | +| NVIDIA GeForce RTX 4090 D | 2685 | | NVIDIA RTX 6000 Ada Generation | 26B1 1028 16A1 | | NVIDIA RTX 6000 Ada Generation | 26B1 103C 16A1 | | NVIDIA RTX 6000 Ada Generation | 26B1 10DE 16A1 | @@ -844,16 +846,22 @@ Subsystem Device ID. | NVIDIA RTX 5000 Ada Generation | 26B2 103C 17FA | | NVIDIA RTX 5000 Ada Generation | 26B2 10DE 17FA | | NVIDIA RTX 5000 Ada Generation | 26B2 17AA 17FA | +| NVIDIA RTX 5880 Ada Generation | 26B3 103C 1934 | +| NVIDIA RTX 5880 Ada Generation | 26B3 10DE 1934 | +| NVIDIA RTX 5880 Ada Generation | 26B3 17AA 1934 | | NVIDIA L40 | 26B5 10DE 169D | | NVIDIA L40 | 26B5 10DE 17DA | | NVIDIA L40S | 26B9 10DE 1851 | | NVIDIA L40S | 26B9 10DE 18CF | +| NVIDIA L20 | 26BA 10DE 1957 | | NVIDIA GeForce RTX 4080 | 2704 | +| NVIDIA GeForce RTX 4070 Ti SUPER | 2705 | | NVIDIA GeForce RTX 4090 Laptop GPU | 2717 | | NVIDIA RTX 5000 Ada Generation Laptop GPU | 2730 | | NVIDIA GeForce RTX 4090 Laptop GPU | 2757 | | NVIDIA RTX 5000 Ada Generation Embedded GPU | 2770 | | NVIDIA GeForce RTX 4070 Ti | 2782 | +| NVIDIA GeForce RTX 4070 SUPER | 2783 | | NVIDIA GeForce RTX 4070 | 2786 | | NVIDIA GeForce RTX 4080 Laptop GPU | 27A0 | | NVIDIA RTX 4000 SFF Ada Generation | 27B0 1028 16FA | @@ -868,6 +876,7 @@ Subsystem Device ID. | NVIDIA RTX 4000 Ada Generation | 27B2 103C 181B | | NVIDIA RTX 4000 Ada Generation | 27B2 10DE 181B | | NVIDIA RTX 4000 Ada Generation | 27B2 17AA 181B | +| NVIDIA L2 | 27B6 10DE 1933 | | NVIDIA L4 | 27B8 10DE 16CA | | NVIDIA L4 | 27B8 10DE 16EE | | NVIDIA RTX 4000 Ada Generation Laptop GPU | 27BA | diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index 117faf6de7..c7620a251e 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -70,9 +70,9 @@ $(foreach _module, $(NV_KERNEL_MODULES), \ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) -EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args +EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"545.29.06\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.40.07\" ifneq ($(SYSSRCHOST1X),) EXTRA_CFLAGS += -I$(SYSSRCHOST1X) @@ -134,6 +134,16 @@ ifneq ($(wildcard /proc/sgi_uv),) EXTRA_CFLAGS += -DNV_CONFIG_X86_UV endif +ifdef VGX_FORCE_VFIO_PCI_CORE + EXTRA_CFLAGS += -DNV_VGPU_FORCE_VFIO_PCI_CORE +endif + +WARNINGS_AS_ERRORS ?= +ifeq ($(WARNINGS_AS_ERRORS),1) + ccflags-y += -Werror +else + ccflags-y += -Wno-error +endif # # The conftest.sh script tests various aspects of the target kernel. @@ -160,6 +170,7 @@ NV_CONFTEST_CMD := /bin/sh $(NV_CONFTEST_SCRIPT) \ NV_CFLAGS_FROM_CONFTEST := $(shell $(NV_CONFTEST_CMD) build_cflags) NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(EXTRA_CFLAGS) -fno-pie +NV_CONFTEST_CFLAGS += -Wno-error NV_CONFTEST_COMPILE_TEST_HEADERS := $(obj)/conftest/macros.h NV_CONFTEST_COMPILE_TEST_HEADERS += $(obj)/conftest/functions.h @@ -219,106 +230,7 @@ $(obj)/conftest/patches.h: $(NV_CONFTEST_SCRIPT) @mkdir -p $(obj)/conftest @$(NV_CONFTEST_CMD) patch_check > $@ - -# Each of these headers is checked for presence with a test #include; a -# corresponding #define will be generated in conftest/headers.h. -NV_HEADER_PRESENCE_TESTS = \ - asm/system.h \ - drm/drmP.h \ - drm/drm_aperture.h \ - drm/drm_auth.h \ - drm/drm_gem.h \ - drm/drm_crtc.h \ - drm/drm_color_mgmt.h \ - drm/drm_atomic.h \ - drm/drm_atomic_helper.h \ - drm/drm_atomic_state_helper.h \ - drm/drm_encoder.h \ - drm/drm_atomic_uapi.h \ - drm/drm_drv.h \ - drm/drm_fbdev_generic.h \ - drm/drm_framebuffer.h \ - drm/drm_connector.h \ - drm/drm_probe_helper.h \ - drm/drm_blend.h \ - drm/drm_fourcc.h \ - drm/drm_prime.h \ - drm/drm_plane.h \ - drm/drm_vblank.h \ - drm/drm_file.h \ - drm/drm_ioctl.h \ - drm/drm_device.h \ - drm/drm_mode_config.h \ - drm/drm_modeset_lock.h \ - dt-bindings/interconnect/tegra_icc_id.h \ - generated/autoconf.h \ - generated/compile.h \ - generated/utsrelease.h \ - linux/efi.h \ - linux/kconfig.h \ - linux/platform/tegra/mc_utils.h \ - linux/printk.h \ - linux/ratelimit.h \ - linux/prio_tree.h \ - linux/log2.h \ - linux/of.h \ - linux/bug.h \ - linux/sched.h \ - linux/sched/mm.h \ - linux/sched/signal.h \ - linux/sched/task.h \ - linux/sched/task_stack.h \ - xen/ioemu.h \ - linux/fence.h \ - linux/dma-fence.h \ - linux/dma-resv.h \ - soc/tegra/chip-id.h \ - soc/tegra/fuse.h \ - soc/tegra/tegra_bpmp.h \ - video/nv_internal.h \ - linux/platform/tegra/dce/dce-client-ipc.h \ - linux/nvhost.h \ - linux/nvhost_t194.h \ - linux/host1x-next.h \ - asm/book3s/64/hash-64k.h \ - asm/set_memory.h \ - asm/prom.h \ - asm/powernv.h \ - linux/atomic.h \ - asm/barrier.h \ - asm/opal-api.h \ - sound/hdaudio.h \ - asm/pgtable_types.h \ - asm/page.h \ - linux/stringhash.h \ - linux/dma-map-ops.h \ - rdma/peer_mem.h \ - sound/hda_codec.h \ - linux/dma-buf.h \ - linux/time.h \ - linux/platform_device.h \ - linux/mutex.h \ - linux/reset.h \ - linux/of_platform.h \ - linux/of_device.h \ - linux/of_gpio.h \ - linux/gpio.h \ - linux/gpio/consumer.h \ - linux/interconnect.h \ - linux/pm_runtime.h \ - linux/clk.h \ - linux/clk-provider.h \ - linux/ioasid.h \ - linux/stdarg.h \ - linux/iosys-map.h \ - asm/coco.h \ - linux/vfio_pci_core.h \ - linux/mdev.h \ - soc/tegra/bpmp-abi.h \ - soc/tegra/bpmp.h \ - linux/sync_file.h \ - linux/cc_platform.h \ - asm/cpufeature.h +include $(src)/header-presence-tests.mk # Filename to store the define for the header in $(1); this is only consumed by # the rule below that concatenates all of these together. diff --git a/kernel-open/Makefile b/kernel-open/Makefile index e0ed5e955a..cee56f1061 100644 --- a/kernel-open/Makefile +++ b/kernel-open/Makefile @@ -57,12 +57,15 @@ else -e 's/armv[0-7]\w\+/arm/' \ -e 's/aarch64/arm64/' \ -e 's/ppc64le/powerpc/' \ + -e 's/riscv64/riscv/' \ ) endif NV_KERNEL_MODULES ?= $(wildcard nvidia nvidia-uvm nvidia-vgpu-vfio nvidia-modeset nvidia-drm nvidia-peermem) NV_KERNEL_MODULES := $(filter-out $(NV_EXCLUDE_KERNEL_MODULES), \ $(NV_KERNEL_MODULES)) + INSTALL_MOD_DIR ?= kernel/drivers/video + NV_VERBOSE ?= SPECTRE_V2_RETPOLINE ?= 0 @@ -74,7 +77,7 @@ else KBUILD_PARAMS += NV_KERNEL_SOURCES=$(KERNEL_SOURCES) KBUILD_PARAMS += NV_KERNEL_OUTPUT=$(KERNEL_OUTPUT) KBUILD_PARAMS += NV_KERNEL_MODULES="$(NV_KERNEL_MODULES)" - KBUILD_PARAMS += INSTALL_MOD_DIR=kernel/drivers/video + KBUILD_PARAMS += INSTALL_MOD_DIR="$(INSTALL_MOD_DIR)" KBUILD_PARAMS += NV_SPECTRE_V2=$(SPECTRE_V2_RETPOLINE) .PHONY: modules module clean clean_conftest modules_install diff --git a/kernel-open/common/inc/nv-ioctl-numbers.h b/kernel-open/common/inc/nv-ioctl-numbers.h index cb0b6a246c..d0efa6fd5b 100644 --- a/kernel-open/common/inc/nv-ioctl-numbers.h +++ b/kernel-open/common/inc/nv-ioctl-numbers.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,5 +39,6 @@ #define NV_ESC_QUERY_DEVICE_INTR (NV_IOCTL_BASE + 13) #define NV_ESC_SYS_PARAMS (NV_IOCTL_BASE + 14) #define NV_ESC_EXPORT_TO_DMABUF_FD (NV_IOCTL_BASE + 17) +#define NV_ESC_WAIT_OPEN_COMPLETE (NV_IOCTL_BASE + 18) #endif diff --git a/kernel-open/common/inc/nv-ioctl.h b/kernel-open/common/inc/nv-ioctl.h index f2c1aab627..a049b42a28 100644 --- a/kernel-open/common/inc/nv-ioctl.h +++ b/kernel-open/common/inc/nv-ioctl.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -142,4 +142,10 @@ typedef struct nv_ioctl_export_to_dma_buf_fd NvU32 status; } nv_ioctl_export_to_dma_buf_fd_t; +typedef struct nv_ioctl_wait_open_complete +{ + int rc; + NvU32 adapterStatus; +} nv_ioctl_wait_open_complete_t; + #endif diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h index d46d1123ee..893d9317ca 100644 --- a/kernel-open/common/inc/nv-linux.h +++ b/kernel-open/common/inc/nv-linux.h @@ -35,6 +35,7 @@ #include "os-interface.h" #include "nv-timer.h" #include "nv-time.h" +#include "nv-chardev-numbers.h" #define NV_KERNEL_NAME "Linux" @@ -406,37 +407,6 @@ extern int nv_pat_mode; #define NV_GFP_DMA32 (NV_GFP_KERNEL) #endif -extern NvBool nvos_is_chipset_io_coherent(void); - -#if defined(NVCPU_X86_64) -#define CACHE_FLUSH() asm volatile("wbinvd":::"memory") -#define WRITE_COMBINE_FLUSH() asm volatile("sfence":::"memory") -#elif defined(NVCPU_AARCH64) - static inline void nv_flush_cache_cpu(void *info) - { - if (!nvos_is_chipset_io_coherent()) - { -#if defined(NV_FLUSH_CACHE_ALL_PRESENT) - flush_cache_all(); -#else - WARN_ONCE(0, "NVRM: kernel does not support flush_cache_all()\n"); -#endif - } - } -#define CACHE_FLUSH() nv_flush_cache_cpu(NULL) -#define CACHE_FLUSH_ALL() on_each_cpu(nv_flush_cache_cpu, NULL, 1) -#define WRITE_COMBINE_FLUSH() mb() -#elif defined(NVCPU_PPC64LE) -#define CACHE_FLUSH() asm volatile("sync; \n" \ - "isync; \n" ::: "memory") -#define WRITE_COMBINE_FLUSH() CACHE_FLUSH() -#elif defined(NVCPU_RISCV64) -#define CACHE_FLUSH() mb() -#define WRITE_COMBINE_FLUSH() CACHE_FLUSH() -#else -#error "CACHE_FLUSH() and WRITE_COMBINE_FLUSH() need to be defined for this architecture." -#endif - typedef enum { NV_MEMORY_TYPE_SYSTEM, /* Memory mapped for ROM, SBIOS and physical RAM. */ @@ -1380,7 +1350,19 @@ typedef struct nv_dma_map_s { i < dm->mapping.discontig.submap_count; \ i++, sm = &dm->mapping.discontig.submaps[i]) +/* + * On 4K ARM kernels, use max submap size a multiple of 64K to keep nv-p2p happy. + * Despite 4K OS pages, we still use 64K P2P pages due to dependent modules still using 64K. + * Instead of using (4G-4K), use max submap size as (4G-64K) since the mapped IOVA range + * must be aligned at 64K boundary. + */ +#if defined(CONFIG_ARM64_4K_PAGES) +#define NV_DMA_U32_MAX_4K_PAGES ((NvU32)((NV_U32_MAX >> PAGE_SHIFT) + 1)) +#define NV_DMA_SUBMAP_MAX_PAGES ((NvU32)(NV_DMA_U32_MAX_4K_PAGES - 16)) +#else #define NV_DMA_SUBMAP_MAX_PAGES ((NvU32)(NV_U32_MAX >> PAGE_SHIFT)) +#endif + #define NV_DMA_SUBMAP_IDX_TO_PAGE_IDX(s) (s * NV_DMA_SUBMAP_MAX_PAGES) /* @@ -1460,6 +1442,11 @@ typedef struct coherent_link_info_s { * baremetal OS environment it is System Physical Address(SPA) and in the case * of virutalized OS environment it is Intermediate Physical Address(IPA) */ NvU64 gpu_mem_pa; + + /* Physical address of the reserved portion of the GPU memory, applicable + * only in Grace Hopper self hosted passthrough virtualizatioan platform. */ + NvU64 rsvd_mem_pa; + /* Bitmap of NUMA node ids, corresponding to the reserved PXMs, * available for adding GPU memory to the kernel as system RAM */ DECLARE_BITMAP(free_node_bitmap, MAX_NUMNODES); @@ -1607,6 +1594,26 @@ typedef struct nv_linux_state_s { struct nv_dma_device dma_dev; struct nv_dma_device niso_dma_dev; + + /* + * Background kthread for handling deferred open operations + * (e.g. from O_NONBLOCK). + * + * Adding to open_q and reading/writing is_accepting_opens + * are protected by nvl->open_q_lock (not nvl->ldata_lock). + * This allows new deferred open operations to be enqueued without + * blocking behind previous ones (which hold nvl->ldata_lock). + * + * Adding to open_q is only safe if is_accepting_opens is true. + * This prevents open operations from racing with device removal. + * + * Stopping open_q is only safe after setting is_accepting_opens to false. + * This ensures that the open_q (and the larger nvl structure) will + * outlive any of the open operations enqueued. + */ + nv_kthread_q_t open_q; + NvBool is_accepting_opens; + struct semaphore open_q_lock; } nv_linux_state_t; extern nv_linux_state_t *nv_linux_devices; @@ -1656,7 +1663,7 @@ typedef struct nvidia_stack_t *sp; nv_alloc_t *free_list; - void *nvptr; + nv_linux_state_t *nvptr; nvidia_event_t *event_data_head, *event_data_tail; NvBool dataless_event_pending; nv_spinlock_t fp_lock; @@ -1667,6 +1674,12 @@ typedef struct nv_alloc_mapping_context_t mmap_context; struct address_space mapping; + nv_kthread_q_item_t open_q_item; + struct completion open_complete; + nv_linux_state_t *deferred_open_nvl; + int open_rc; + NV_STATUS adapter_status; + struct list_head entry; } nv_linux_file_private_t; @@ -1675,6 +1688,21 @@ static inline nv_linux_file_private_t *nv_get_nvlfp_from_nvfp(nv_file_private_t return container_of(nvfp, nv_linux_file_private_t, nvfp); } +static inline int nv_wait_open_complete_interruptible(nv_linux_file_private_t *nvlfp) +{ + return wait_for_completion_interruptible(&nvlfp->open_complete); +} + +static inline void nv_wait_open_complete(nv_linux_file_private_t *nvlfp) +{ + wait_for_completion(&nvlfp->open_complete); +} + +static inline NvBool nv_is_open_complete(nv_linux_file_private_t *nvlfp) +{ + return completion_done(&nvlfp->open_complete); +} + #define NV_SET_FILE_PRIVATE(filep,data) ((filep)->private_data = (data)) #define NV_GET_LINUX_FILE_PRIVATE(filep) ((nv_linux_file_private_t *)(filep)->private_data) @@ -1756,12 +1784,18 @@ static inline NV_STATUS nv_check_gpu_state(nv_state_t *nv) extern NvU32 NVreg_EnableUserNUMAManagement; extern NvU32 NVreg_RegisterPCIDriver; extern NvU32 NVreg_EnableResizableBar; +extern NvU32 NVreg_EnableNonblockingOpen; extern NvU32 num_probed_nv_devices; extern NvU32 num_nv_devices; #define NV_FILE_INODE(file) (file)->f_inode +static inline int nv_is_control_device(struct inode *inode) +{ + return (minor((inode)->i_rdev) == NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE); +} + #if defined(NV_DOM0_KERNEL_PRESENT) || defined(NV_VGPU_KVM_BUILD) #define NV_VGX_HYPER #if defined(NV_XEN_IOEMU_INJECT_MSI) @@ -2040,4 +2074,7 @@ typedef enum #include #endif +#define NV_EXPORT_SYMBOL(symbol) EXPORT_SYMBOL_GPL(symbol) +#define NV_CHECK_EXPORT_SYMBOL(symbol) NV_IS_EXPORT_SYMBOL_PRESENT_##symbol + #endif /* _NV_LINUX_H_ */ diff --git a/kernel-open/common/inc/nv-lock.h b/kernel-open/common/inc/nv-lock.h index 030422948a..5d58b73a92 100644 --- a/kernel-open/common/inc/nv-lock.h +++ b/kernel-open/common/inc/nv-lock.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -37,6 +37,7 @@ #if defined(CONFIG_PREEMPT_RT) || defined(CONFIG_PREEMPT_RT_FULL) typedef raw_spinlock_t nv_spinlock_t; +#define NV_DEFINE_SPINLOCK(lock) DEFINE_RAW_SPINLOCK(lock) #define NV_SPIN_LOCK_INIT(lock) raw_spin_lock_init(lock) #define NV_SPIN_LOCK_IRQ(lock) raw_spin_lock_irq(lock) #define NV_SPIN_UNLOCK_IRQ(lock) raw_spin_unlock_irq(lock) @@ -47,6 +48,7 @@ typedef raw_spinlock_t nv_spinlock_t; #define NV_SPIN_UNLOCK_WAIT(lock) raw_spin_unlock_wait(lock) #else typedef spinlock_t nv_spinlock_t; +#define NV_DEFINE_SPINLOCK(lock) DEFINE_SPINLOCK(lock) #define NV_SPIN_LOCK_INIT(lock) spin_lock_init(lock) #define NV_SPIN_LOCK_IRQ(lock) spin_lock_irq(lock) #define NV_SPIN_UNLOCK_IRQ(lock) spin_unlock_irq(lock) diff --git a/kernel-open/common/inc/nv-mm.h b/kernel-open/common/inc/nv-mm.h index fbdf237120..83363fa12d 100644 --- a/kernel-open/common/inc/nv-mm.h +++ b/kernel-open/common/inc/nv-mm.h @@ -44,12 +44,18 @@ typedef int vm_fault_t; #include #include -#if defined(NV_PIN_USER_PAGES_PRESENT) + +/* + * FreeBSD's pin_user_pages's conftest breaks since pin_user_pages is an inline + * function. Because it simply maps to get_user_pages, we can just replace + * NV_PIN_USER_PAGES with NV_GET_USER_PAGES on FreeBSD + */ +#if defined(NV_PIN_USER_PAGES_PRESENT) && !defined(NV_BSD) #if defined(NV_PIN_USER_PAGES_HAS_ARGS_VMAS) - #define NV_PIN_USER_PAGES pin_user_pages + #define NV_PIN_USER_PAGES(start, nr_pages, gup_flags, pages) \ + pin_user_pages(start, nr_pages, gup_flags, pages, NULL) #else - #define NV_PIN_USER_PAGES(start, nr_pages, gup_flags, pages, vmas) \ - pin_user_pages(start, nr_pages, gup_flags, pages) + #define NV_PIN_USER_PAGES pin_user_pages #endif // NV_PIN_USER_PAGES_HAS_ARGS_VMAS #define NV_UNPIN_USER_PAGE unpin_user_page #else @@ -80,29 +86,28 @@ typedef int vm_fault_t; */ #if defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS) - #define NV_GET_USER_PAGES(start, nr_pages, flags, pages, vmas) \ - get_user_pages(start, nr_pages, flags, pages) -#elif defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS) #define NV_GET_USER_PAGES get_user_pages +#elif defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS) + #define NV_GET_USER_PAGES(start, nr_pages, flags, pages) \ + get_user_pages(start, nr_pages, flags, pages, NULL) #elif defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS_VMAS) - #define NV_GET_USER_PAGES(start, nr_pages, flags, pages, vmas) \ - get_user_pages(current, current->mm, start, nr_pages, flags, pages, vmas) + #define NV_GET_USER_PAGES(start, nr_pages, flags, pages) \ + get_user_pages(current, current->mm, start, nr_pages, flags, pages, NULL) #else static inline long NV_GET_USER_PAGES(unsigned long start, unsigned long nr_pages, unsigned int flags, - struct page **pages, - struct vm_area_struct **vmas) + struct page **pages) { int write = flags & FOLL_WRITE; int force = flags & FOLL_FORCE; #if defined(NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS) - return get_user_pages(start, nr_pages, write, force, pages, vmas); + return get_user_pages(start, nr_pages, write, force, pages, NULL); #else // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS return get_user_pages(current, current->mm, start, nr_pages, write, - force, pages, vmas); + force, pages, NULL); #endif // NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS } #endif // NV_GET_USER_PAGES_HAS_ARGS_FLAGS @@ -124,13 +129,13 @@ typedef int vm_fault_t; #if defined(NV_PIN_USER_PAGES_REMOTE_PRESENT) #if defined(NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS) - #define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ - pin_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas, locked) + #define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \ + pin_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, NULL, locked) #elif defined(NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_VMAS) - #define NV_PIN_USER_PAGES_REMOTE pin_user_pages_remote + #define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \ + pin_user_pages_remote(mm, start, nr_pages, flags, pages, NULL, locked) #else - #define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ - pin_user_pages_remote(mm, start, nr_pages, flags, pages, locked) + #define NV_PIN_USER_PAGES_REMOTE pin_user_pages_remote #endif // NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS #else #define NV_PIN_USER_PAGES_REMOTE NV_GET_USER_PAGES_REMOTE @@ -166,19 +171,19 @@ typedef int vm_fault_t; #if defined(NV_GET_USER_PAGES_REMOTE_PRESENT) #if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED) - #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ - get_user_pages_remote(mm, start, nr_pages, flags, pages, locked) + #define NV_GET_USER_PAGES_REMOTE get_user_pages_remote #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED_VMAS) - #define NV_GET_USER_PAGES_REMOTE get_user_pages_remote + #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \ + get_user_pages_remote(mm, start, nr_pages, flags, pages, NULL, locked) #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED_VMAS) - #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ - get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas, locked) + #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \ + get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, NULL, locked) #elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_VMAS) - #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ - get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas) + #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \ + get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, NULL) #else // NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE_VMAS @@ -187,14 +192,13 @@ typedef int vm_fault_t; unsigned long nr_pages, unsigned int flags, struct page **pages, - struct vm_area_struct **vmas, int *locked) { int write = flags & FOLL_WRITE; int force = flags & FOLL_FORCE; return get_user_pages_remote(NULL, mm, start, nr_pages, write, force, - pages, vmas); + pages, NULL); } #endif // NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED #else @@ -204,18 +208,17 @@ typedef int vm_fault_t; unsigned long nr_pages, unsigned int flags, struct page **pages, - struct vm_area_struct **vmas, int *locked) { int write = flags & FOLL_WRITE; int force = flags & FOLL_FORCE; - return get_user_pages(NULL, mm, start, nr_pages, write, force, pages, vmas); + return get_user_pages(NULL, mm, start, nr_pages, write, force, pages, NULL); } #else - #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \ - get_user_pages(NULL, mm, start, nr_pages, flags, pages, vmas) + #define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \ + get_user_pages(NULL, mm, start, nr_pages, flags, pages, NULL) #endif // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS #endif // NV_GET_USER_PAGES_REMOTE_PRESENT diff --git a/kernel-open/common/inc/nv-pgprot.h b/kernel-open/common/inc/nv-pgprot.h index 5054997c65..589226e32e 100644 --- a/kernel-open/common/inc/nv-pgprot.h +++ b/kernel-open/common/inc/nv-pgprot.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -60,6 +60,7 @@ static inline pgprot_t pgprot_modify_writecombine(pgprot_t old_prot) #endif /* !defined(NV_VMWARE) */ #if defined(NVCPU_AARCH64) +extern NvBool nvos_is_chipset_io_coherent(void); /* * Don't rely on the kernel's definition of pgprot_noncached(), as on 64-bit * ARM that's not for system memory, but device memory instead. For I/O cache diff --git a/kernel-open/common/inc/nv-procfs-utils.h b/kernel-open/common/inc/nv-procfs-utils.h index c4035ec4f9..6ae773e85a 100644 --- a/kernel-open/common/inc/nv-procfs-utils.h +++ b/kernel-open/common/inc/nv-procfs-utils.h @@ -92,6 +92,24 @@ typedef struct file_operations nv_proc_ops_t; #endif #define NV_DEFINE_SINGLE_PROCFS_FILE_HELPER(name, lock) \ + static ssize_t nv_procfs_read_lock_##name( \ + struct file *file, \ + char __user *buf, \ + size_t size, \ + loff_t *ppos \ + ) \ + { \ + int ret; \ + ret = nv_down_read_interruptible(&lock); \ + if (ret < 0) \ + { \ + return ret; \ + } \ + size = seq_read(file, buf, size, ppos); \ + up_read(&lock); \ + return size; \ + } \ + \ static int nv_procfs_open_##name( \ struct inode *inode, \ struct file *filep \ @@ -104,11 +122,6 @@ typedef struct file_operations nv_proc_ops_t; { \ return ret; \ } \ - ret = nv_down_read_interruptible(&lock); \ - if (ret < 0) \ - { \ - single_release(inode, filep); \ - } \ return ret; \ } \ \ @@ -117,7 +130,6 @@ typedef struct file_operations nv_proc_ops_t; struct file *filep \ ) \ { \ - up_read(&lock); \ return single_release(inode, filep); \ } @@ -127,46 +139,7 @@ typedef struct file_operations nv_proc_ops_t; static const nv_proc_ops_t nv_procfs_##name##_fops = { \ NV_PROC_OPS_SET_OWNER() \ .NV_PROC_OPS_OPEN = nv_procfs_open_##name, \ - .NV_PROC_OPS_READ = seq_read, \ - .NV_PROC_OPS_LSEEK = seq_lseek, \ - .NV_PROC_OPS_RELEASE = nv_procfs_release_##name, \ - }; - - -#define NV_DEFINE_SINGLE_PROCFS_FILE_READ_WRITE(name, lock, \ -write_callback) \ - NV_DEFINE_SINGLE_PROCFS_FILE_HELPER(name, lock) \ - \ - static ssize_t nv_procfs_write_##name( \ - struct file *file, \ - const char __user *buf, \ - size_t size, \ - loff_t *ppos \ - ) \ - { \ - ssize_t ret; \ - struct seq_file *s; \ - \ - s = file->private_data; \ - if (s == NULL) \ - { \ - return -EIO; \ - } \ - \ - ret = write_callback(s, buf + *ppos, size - *ppos); \ - if (ret == 0) \ - { \ - /* avoid infinite loop */ \ - ret = -EIO; \ - } \ - return ret; \ - } \ - \ - static const nv_proc_ops_t nv_procfs_##name##_fops = { \ - NV_PROC_OPS_SET_OWNER() \ - .NV_PROC_OPS_OPEN = nv_procfs_open_##name, \ - .NV_PROC_OPS_READ = seq_read, \ - .NV_PROC_OPS_WRITE = nv_procfs_write_##name, \ + .NV_PROC_OPS_READ = nv_procfs_read_lock_##name, \ .NV_PROC_OPS_LSEEK = seq_lseek, \ .NV_PROC_OPS_RELEASE = nv_procfs_release_##name, \ }; diff --git a/kernel-open/common/inc/nv-proto.h b/kernel-open/common/inc/nv-proto.h index 580d12a5cd..353e8a5b8d 100644 --- a/kernel-open/common/inc/nv-proto.h +++ b/kernel-open/common/inc/nv-proto.h @@ -88,4 +88,7 @@ int nv_linux_add_device_locked(nv_linux_state_t *); void nv_linux_remove_device_locked(nv_linux_state_t *); NvBool nv_acpi_power_resource_method_present(struct pci_dev *); +int nv_linux_init_open_q(nv_linux_state_t *); +void nv_linux_stop_open_q(nv_linux_state_t *); + #endif /* _NV_PROTO_H_ */ diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index f3f32ee88b..5e0f726d79 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -221,7 +221,6 @@ typedef struct #define NV_RM_PAGE_MASK (NV_RM_PAGE_SIZE - 1) #define NV_RM_TO_OS_PAGE_SHIFT (os_page_shift - NV_RM_PAGE_SHIFT) -#define NV_RM_PAGES_PER_OS_PAGE (1U << NV_RM_TO_OS_PAGE_SHIFT) #define NV_RM_PAGES_TO_OS_PAGES(count) \ ((((NvUPtr)(count)) >> NV_RM_TO_OS_PAGE_SHIFT) + \ ((((count) & ((1 << NV_RM_TO_OS_PAGE_SHIFT) - 1)) != 0) ? 1 : 0)) @@ -467,12 +466,6 @@ typedef struct nv_state_t NvHandle hDisp; } rmapi; - /* Bool to check if ISO iommu enabled */ - NvBool iso_iommu_present; - - /* Bool to check if NISO iommu enabled */ - NvBool niso_iommu_present; - /* Bool to check if dma-buf is supported */ NvBool dma_buf_supported; @@ -484,6 +477,22 @@ typedef struct nv_state_t /* Bool to check if the GPU has a coherent sysmem link */ NvBool coherent; + + /* + * NUMA node ID of the CPU to which the GPU is attached. + * Holds NUMA_NO_NODE on platforms that don't support NUMA configuration. + */ + NvS32 cpu_numa_node_id; + + struct { + /* Bool to check if ISO iommu enabled */ + NvBool iso_iommu_present; + /* Bool to check if NISO iommu enabled */ + NvBool niso_iommu_present; + /* Display SMMU Stream IDs */ + NvU32 dispIsoStreamId; + NvU32 dispNisoStreamId; + } iommus; } nv_state_t; // These define need to be in sync with defines in system.h @@ -613,10 +622,10 @@ typedef enum (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0) #define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ - ((nv)->iso_iommu_present) + ((nv)->iommus.iso_iommu_present) #define NV_SOC_IS_NISO_IOMMU_PRESENT(nv) \ - ((nv)->niso_iommu_present) + ((nv)->iommus.niso_iommu_present) /* * GPU add/remove events */ @@ -779,8 +788,6 @@ NV_STATUS NV_API_CALL nv_register_phys_pages (nv_state_t *, NvU64 *, NvU64, void NV_API_CALL nv_unregister_phys_pages (nv_state_t *, void *); NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, void **); -NV_STATUS NV_API_CALL nv_dma_map_pages (nv_dma_device_t *, NvU64, NvU64 *, NvBool, NvU32, void **); -NV_STATUS NV_API_CALL nv_dma_unmap_pages (nv_dma_device_t *, NvU64, NvU64 *, void **); NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, void **); NV_STATUS NV_API_CALL nv_dma_unmap_alloc (nv_dma_device_t *, NvU64, NvU64 *, void **); @@ -830,7 +837,7 @@ void NV_API_CALL nv_put_firmware(const void *); nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); void NV_API_CALL nv_put_file_private(void *); -NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); @@ -877,9 +884,9 @@ struct drm_gem_object; NV_STATUS NV_API_CALL nv_dma_import_sgt (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *); void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *); -NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **); -NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **); -void NV_API_CALL nv_dma_release_dma_buf (void *, nv_dma_buf_t *); +NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, struct sg_table **, nv_dma_buf_t **); +NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, struct sg_table **, nv_dma_buf_t **); +void NV_API_CALL nv_dma_release_dma_buf (nv_dma_buf_t *); void NV_API_CALL nv_schedule_uvm_isr (nv_state_t *); @@ -895,6 +902,8 @@ typedef void (*nvTegraDceClientIpcCallback)(NvU32, NvU32, NvU32, void *, void *) NV_STATUS NV_API_CALL nv_get_num_phys_pages (void *, NvU32 *); NV_STATUS NV_API_CALL nv_get_phys_pages (void *, void *, NvU32 *); +void NV_API_CALL nv_get_disp_smmu_stream_ids (nv_state_t *, NvU32 *, NvU32 *); + /* * --------------------------------------------------------------------------- * @@ -921,6 +930,7 @@ NV_STATUS NV_API_CALL rm_ioctl (nvidia_stack_t *, nv_state_t * NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *); void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t); NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *); @@ -940,6 +950,7 @@ void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char * char* NV_API_CALL rm_remove_spaces (const char *); char* NV_API_CALL rm_string_token (char **, const char); void NV_API_CALL rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool); +NV_STATUS NV_API_CALL rm_get_adapter_status_external(nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *); diff --git a/kernel-open/common/inc/nv_uvm_interface.h b/kernel-open/common/inc/nv_uvm_interface.h index 7117a81c73..e83c6c3b1c 100644 --- a/kernel-open/common/inc/nv_uvm_interface.h +++ b/kernel-open/common/inc/nv_uvm_interface.h @@ -62,10 +62,10 @@ typedef struct /******************************************************************************* nvUvmInterfaceRegisterGpu - Registers the GPU with the provided UUID for use. A GPU must be registered - before its UUID can be used with any other API. This call is ref-counted so - every nvUvmInterfaceRegisterGpu must be paired with a corresponding - nvUvmInterfaceUnregisterGpu. + Registers the GPU with the provided physical UUID for use. A GPU must be + registered before its UUID can be used with any other API. This call is + ref-counted so every nvUvmInterfaceRegisterGpu must be paired with a + corresponding nvUvmInterfaceUnregisterGpu. You don't need to call nvUvmInterfaceSessionCreate before calling this. @@ -79,12 +79,13 @@ NV_STATUS nvUvmInterfaceRegisterGpu(const NvProcessorUuid *gpuUuid, UvmGpuPlatfo /******************************************************************************* nvUvmInterfaceUnregisterGpu - Unregisters the GPU with the provided UUID. This drops the ref count from - nvUvmInterfaceRegisterGpu. Once the reference count goes to 0 the device may - no longer be accessible until the next nvUvmInterfaceRegisterGpu call. No - automatic resource freeing is performed, so only make the last unregister - call after destroying all your allocations associated with that UUID (such - as those from nvUvmInterfaceAddressSpaceCreate). + Unregisters the GPU with the provided physical UUID. This drops the ref + count from nvUvmInterfaceRegisterGpu. Once the reference count goes to 0 + the device may no longer be accessible until the next + nvUvmInterfaceRegisterGpu call. No automatic resource freeing is performed, + so only make the last unregister call after destroying all your allocations + associated with that UUID (such as those from + nvUvmInterfaceAddressSpaceCreate). If the UUID is not found, no operation is performed. */ @@ -121,10 +122,10 @@ NV_STATUS nvUvmInterfaceSessionDestroy(uvmGpuSessionHandle session); nvUvmInterfaceDeviceCreate Creates a device object under the given session for the GPU with the given - UUID. Also creates a partition object for the device iff bCreateSmcPartition - is true and pGpuInfo->smcEnabled is true. pGpuInfo->smcUserClientInfo will - be used to determine the SMC partition in this case. A device handle is - returned in the device output parameter. + physical UUID. Also creates a partition object for the device iff + bCreateSmcPartition is true and pGpuInfo->smcEnabled is true. + pGpuInfo->smcUserClientInfo will be used to determine the SMC partition in + this case. A device handle is returned in the device output parameter. Error codes: NV_ERR_GENERIC @@ -161,6 +162,7 @@ void nvUvmInterfaceDeviceDestroy(uvmGpuDeviceHandle device); NV_STATUS nvUvmInterfaceAddressSpaceCreate(uvmGpuDeviceHandle device, unsigned long long vaBase, unsigned long long vaSize, + NvBool enableAts, uvmGpuAddressSpaceHandle *vaSpace, UvmGpuAddressSpaceInfo *vaSpaceInfo); @@ -422,33 +424,6 @@ NV_STATUS nvUvmInterfacePmaPinPages(void *pPma, NvU64 pageSize, NvU32 flags); -/******************************************************************************* - nvUvmInterfacePmaUnpinPages - - This function will unpin the physical memory allocated using PMA. The pages - passed as input must be already pinned, else this function will return an - error and rollback any change if any page is not previously marked "pinned". - Behaviour is undefined if any blacklisted pages are unpinned. - - Arguments: - pPma[IN] - Pointer to PMA object. - pPages[IN] - Array of pointers, containing the PA base - address of each page to be unpinned. - pageCount [IN] - Number of pages required to be unpinned. - pageSize [IN] - Page size of each page to be unpinned. - - Error codes: - NV_ERR_INVALID_ARGUMENT - Invalid input arguments. - NV_ERR_GENERIC - Unexpected error. We try hard to avoid - returning this error code as is not very - informative. - NV_ERR_NOT_SUPPORTED - Operation not supported on broken FB -*/ -NV_STATUS nvUvmInterfacePmaUnpinPages(void *pPma, - NvU64 *pPages, - NvLength pageCount, - NvU64 pageSize); - /******************************************************************************* nvUvmInterfaceMemoryFree @@ -638,6 +613,8 @@ NV_STATUS nvUvmInterfaceQueryCopyEnginesCaps(uvmGpuDeviceHandle device, nvUvmInterfaceGetGpuInfo Return various gpu info, refer to the UvmGpuInfo struct for details. + The input UUID is for the physical GPU and the pGpuClientInfo identifies + the SMC partition if SMC is enabled and the partition exists. If no gpu matching the uuid is found, an error will be returned. On Ampere+ GPUs, pGpuClientInfo contains SMC information provided by the @@ -645,6 +622,9 @@ NV_STATUS nvUvmInterfaceQueryCopyEnginesCaps(uvmGpuDeviceHandle device, Error codes: NV_ERR_GENERIC + NV_ERR_NO_MEMORY + NV_ERR_GPU_UUID_NOT_FOUND + NV_ERR_INSUFFICIENT_PERMISSIONS NV_ERR_INSUFFICIENT_RESOURCES */ NV_STATUS nvUvmInterfaceGetGpuInfo(const NvProcessorUuid *gpuUuid, @@ -857,7 +837,7 @@ NV_STATUS nvUvmInterfaceGetEccInfo(uvmGpuDeviceHandle device, UVM GPU UNLOCK Arguments: - gpuUuid[IN] - UUID of the GPU to operate on + device[IN] - Device handle associated with the gpu bOwnInterrupts - Set to NV_TRUE for UVM to take ownership of the replayable page fault interrupts. Set to NV_FALSE to return ownership of the page fault interrupts @@ -973,6 +953,7 @@ NV_STATUS nvUvmInterfaceGetNonReplayableFaults(UvmGpuFaultInfo *pFaultInfo, NOTES: - This function DOES NOT acquire the RM API or GPU locks. That is because it is called during fault servicing, which could produce deadlocks. + - This function should not be called when interrupts are disabled. Arguments: device[IN] - Device handle associated with the gpu @@ -982,6 +963,27 @@ NV_STATUS nvUvmInterfaceGetNonReplayableFaults(UvmGpuFaultInfo *pFaultInfo, */ NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(uvmGpuDeviceHandle device); +/******************************************************************************* + nvUvmInterfaceTogglePrefetchFaults + + This function sends an RPC to GSP in order to toggle the prefetch fault PRI. + + NOTES: + - This function DOES NOT acquire the RM API or GPU locks. That is because + it is called during fault servicing, which could produce deadlocks. + - This function should not be called when interrupts are disabled. + + Arguments: + pFaultInfo[IN] - Information provided by RM for fault handling. + Used for obtaining the device handle without locks. + bEnable[IN] - Instructs RM whether to toggle generating faults on + prefetch on/off. + + Error codes: + NV_ERR_INVALID_ARGUMENT +*/ +NV_STATUS nvUvmInterfaceTogglePrefetchFaults(UvmGpuFaultInfo *pFaultInfo, NvBool bEnable); + /******************************************************************************* nvUvmInterfaceInitAccessCntrInfo @@ -1087,7 +1089,8 @@ void nvUvmInterfaceDeRegisterUvmOps(void); Error codes: NV_ERR_INVALID_ARGUMENT - NV_ERR_OBJECT_NOT_FOUND : If device object associated with the uuids aren't found. + NV_ERR_OBJECT_NOT_FOUND : If device object associated with the device + handles isn't found. */ NV_STATUS nvUvmInterfaceP2pObjectCreate(uvmGpuDeviceHandle device1, uvmGpuDeviceHandle device2, @@ -1140,6 +1143,8 @@ void nvUvmInterfaceP2pObjectDestroy(uvmGpuSessionHandle session, NV_ERR_NOT_READY - Returned when querying the PTEs requires a deferred setup which has not yet completed. It is expected that the caller will reattempt the call until a different code is returned. + As an example, multi-node systems which require querying + PTEs from the Fabric Manager may return this code. */ NV_STATUS nvUvmInterfaceGetExternalAllocPtes(uvmGpuAddressSpaceHandle vaSpace, NvHandle hMemory, @@ -1449,18 +1454,7 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe NvU32 methodStreamSize); /******************************************************************************* - CSL Interface and Locking - - The following functions do not acquire the RM API or GPU locks and must not be called - concurrently with the same UvmCslContext parameter in different threads. The caller must - guarantee this exclusion. - - * nvUvmInterfaceCslRotateIv - * nvUvmInterfaceCslEncrypt - * nvUvmInterfaceCslDecrypt - * nvUvmInterfaceCslSign - * nvUvmInterfaceCslQueryMessagePool - * nvUvmInterfaceCslIncrementIv + Cryptography Services Library (CSL) Interface */ /******************************************************************************* @@ -1471,8 +1465,11 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe The lifetime of the context is the same as the lifetime of the secure channel it is paired with. + Locking: This function acquires an API lock. + Memory : This function dynamically allocates memory. + Arguments: - uvmCslContext[IN/OUT] - The CSL context. + uvmCslContext[IN/OUT] - The CSL context associated with a channel. channel[IN] - Handle to a secure channel. Error codes: @@ -1490,11 +1487,33 @@ NV_STATUS nvUvmInterfaceCslInitContext(UvmCslContext *uvmCslContext, If context is already deinitialized then function returns immediately. + Locking: This function does not acquire an API or GPU lock. + Memory : This function may free memory. + Arguments: - uvmCslContext[IN] - The CSL context. + uvmCslContext[IN] - The CSL context associated with a channel. */ void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext); +/******************************************************************************* + nvUvmInterfaceCslUpdateContext + + Updates a context after a key rotation event and can only be called once per + key rotation event. Following a key rotation event, and before + nvUvmInterfaceCslUpdateContext is called, data encrypted by the GPU with the + previous key can be decrypted with nvUvmInterfaceCslDecrypt. + + Locking: This function acquires an API lock. + Memory : This function does not dynamically allocate memory. + + Arguments: + uvmCslContext[IN] - The CSL context associated with a channel. + + Error codes: + NV_ERR_INVALID_ARGUMENT - The CSL context is not associated with a channel. +*/ +NV_STATUS nvUvmInterfaceCslUpdateContext(UvmCslContext *uvmCslContext); + /******************************************************************************* nvUvmInterfaceCslRotateIv @@ -1509,11 +1528,13 @@ void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext); the channel must be idle before calling this function. This function can be called regardless of the value of the IV's message counter. - See "CSL Interface and Locking" for locking requirements. - This function does not perform dynamic memory allocation. + Locking: This function attempts to acquire the GPU lock. + In case of failure to acquire the return code + is NV_ERR_STATE_IN_USE. + Memory : This function does not dynamically allocate memory. Arguments: - uvmCslContext[IN/OUT] - The CSL context. + uvmCslContext[IN/OUT] - The CSL context associated with a channel. operation[IN] - Either - UVM_CSL_OPERATION_ENCRYPT - UVM_CSL_OPERATION_DECRYPT @@ -1521,7 +1542,11 @@ void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext); Error codes: NV_ERR_INSUFFICIENT_RESOURCES - The rotate operation would cause a counter to overflow. + NV_ERR_STATE_IN_USE - Unable to acquire lock / resource. Caller + can retry at a later time. NV_ERR_INVALID_ARGUMENT - Invalid value for operation. + NV_ERR_GENERIC - A failure other than _STATE_IN_USE occurred + when attempting to acquire a lock. */ NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext, UvmCslOperation operation); @@ -1538,11 +1563,13 @@ NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext, The encryptIV can be obtained from nvUvmInterfaceCslIncrementIv. However, it is optional. If it is NULL, the next IV in line will be used. - See "CSL Interface and Locking" for locking requirements. - This function does not perform dynamic memory allocation. + Locking: This function does not acquire an API or GPU lock. + If called concurrently in different threads with the same UvmCslContext + the caller must guarantee exclusion. + Memory : This function does not dynamically allocate memory. Arguments: - uvmCslContext[IN/OUT] - The CSL context. + uvmCslContext[IN/OUT] - The CSL context associated with a channel. bufferSize[IN] - Size of the input and output buffers in units of bytes. Value can range from 1 byte to (2^32) - 1 bytes. @@ -1553,8 +1580,9 @@ NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext, Its size is UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES. Error codes: - NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes. - - The encryptIv has already been used. + NV_ERR_INVALID_ARGUMENT - The CSL context is not associated with a channel. + - The size of the data is 0 bytes. + - The encryptIv has already been used. */ NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext, NvU32 bufferSize, @@ -1573,8 +1601,10 @@ NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext, maximized when the input and output buffers are 16-byte aligned. This is natural alignment for AES block. - See "CSL Interface and Locking" for locking requirements. - This function does not perform dynamic memory allocation. + Locking: This function does not acquire an API or GPU lock. + If called concurrently in different threads with the same UvmCslContext + the caller must guarantee exclusion. + Memory : This function does not dynamically allocate memory. Arguments: uvmCslContext[IN/OUT] - The CSL context. @@ -1616,11 +1646,13 @@ NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext, Auth and input buffers must not overlap. If they do then calling this function produces undefined behavior. - See "CSL Interface and Locking" for locking requirements. - This function does not perform dynamic memory allocation. + Locking: This function does not acquire an API or GPU lock. + If called concurrently in different threads with the same UvmCslContext + the caller must guarantee exclusion. + Memory : This function does not dynamically allocate memory. Arguments: - uvmCslContext[IN/OUT] - The CSL context. + uvmCslContext[IN/OUT] - The CSL context associated with a channel. bufferSize[IN] - Size of the input buffer in units of bytes. Value can range from 1 byte to (2^32) - 1 bytes. inputBuffer[IN] - Address of plaintext input buffer. @@ -1629,7 +1661,8 @@ NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext, Error codes: NV_ERR_INSUFFICIENT_RESOURCES - The signing operation would cause a counter overflow to occur. - NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes. + NV_ERR_INVALID_ARGUMENT - The CSL context is not associated with a channel. + - The size of the data is 0 bytes. */ NV_STATUS nvUvmInterfaceCslSign(UvmCslContext *uvmCslContext, NvU32 bufferSize, @@ -1641,8 +1674,10 @@ NV_STATUS nvUvmInterfaceCslSign(UvmCslContext *uvmCslContext, Returns the number of messages that can be encrypted before the message counter will overflow. - See "CSL Interface and Locking" for locking requirements. - This function does not perform dynamic memory allocation. + Locking: This function does not acquire an API or GPU lock. + Memory : This function does not dynamically allocate memory. + If called concurrently in different threads with the same UvmCslContext + the caller must guarantee exclusion. Arguments: uvmCslContext[IN/OUT] - The CSL context. @@ -1666,8 +1701,10 @@ NV_STATUS nvUvmInterfaceCslQueryMessagePool(UvmCslContext *uvmCslContext, can be used in nvUvmInterfaceCslEncrypt. If operation is UVM_CSL_OPERATION_DECRYPT then the returned IV can be used in nvUvmInterfaceCslDecrypt. - See "CSL Interface and Locking" for locking requirements. - This function does not perform dynamic memory allocation. + Locking: This function does not acquire an API or GPU lock. + If called concurrently in different threads with the same UvmCslContext + the caller must guarantee exclusion. + Memory : This function does not dynamically allocate memory. Arguments: uvmCslContext[IN/OUT] - The CSL context. @@ -1675,7 +1712,7 @@ NV_STATUS nvUvmInterfaceCslQueryMessagePool(UvmCslContext *uvmCslContext, - UVM_CSL_OPERATION_ENCRYPT - UVM_CSL_OPERATION_DECRYPT increment[IN] - The amount by which the IV is incremented. Can be 0. - iv[out] - If non-NULL, a buffer to store the incremented IV. + iv[OUT] - If non-NULL, a buffer to store the incremented IV. Error codes: NV_ERR_INVALID_ARGUMENT - The value of the operation parameter is illegal. @@ -1687,4 +1724,29 @@ NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext, NvU64 increment, UvmCslIv *iv); +/******************************************************************************* + nvUvmInterfaceCslLogExternalEncryption + + Checks and logs information about non-CSL encryptions, such as those that + originate from the GPU. + + This function does not modify elements of the UvmCslContext. + + Locking: This function does not acquire an API or GPU lock. + Memory : This function does not dynamically allocate memory. + If called concurrently in different threads with the same UvmCslContext + the caller must guarantee exclusion. + + Arguments: + uvmCslContext[IN/OUT] - The CSL context. + bufferSize[OUT] - The size of the buffer encrypted by the + external entity in units of bytes. + + Error codes: + NV_ERR_INSUFFICIENT_RESOURCES - The device encryption would cause a counter + to overflow. +*/ +NV_STATUS nvUvmInterfaceCslLogExternalEncryption(UvmCslContext *uvmCslContext, + NvU32 bufferSize); + #endif // _NV_UVM_INTERFACE_H_ diff --git a/kernel-open/common/inc/nv_uvm_types.h b/kernel-open/common/inc/nv_uvm_types.h index 4cdbf9db3a..18ad3f0a90 100644 --- a/kernel-open/common/inc/nv_uvm_types.h +++ b/kernel-open/common/inc/nv_uvm_types.h @@ -131,6 +131,8 @@ typedef struct UvmGpuMemoryInfo_tag // This is only valid if deviceDescendant is NV_TRUE. // When egm is NV_TRUE, this is also the UUID of the GPU // for which EGM is local. + // If the GPU has SMC enabled, the UUID is the GI UUID. + // Otherwise, it is the UUID for the physical GPU. // Note: If the allocation is owned by a device in // an SLI group and the allocation is broadcast // across the SLI group, this UUID will be any one @@ -544,6 +546,10 @@ typedef struct UvmGpuP2PCapsParams_tag // the GPUs are direct peers. NvU32 peerIds[2]; + // Out: peerId[i] contains gpu[i]'s EGM peer id of gpu[1 - i]. Only defined + // if the GPUs are direct peers and EGM enabled in the system. + NvU32 egmPeerIds[2]; + // Out: UVM_LINK_TYPE NvU32 p2pLink; @@ -572,8 +578,11 @@ typedef struct UvmPlatformInfo_tag // Out: ATS (Address Translation Services) is supported NvBool atsSupported; - // Out: AMD SEV (Secure Encrypted Virtualization) is enabled - NvBool sevEnabled; + // Out: True if HW trusted execution, such as AMD's SEV-SNP or Intel's TDX, + // is enabled in the VM, indicating that Confidential Computing must be + // also enabled in the GPU(s); these two security features are either both + // enabled, or both disabled. + NvBool confComputingEnabled; } UvmPlatformInfo; typedef struct UvmGpuClientInfo_tag @@ -604,7 +613,8 @@ typedef struct UvmGpuInfo_tag // Printable gpu name char name[UVM_GPU_NAME_LENGTH]; - // Uuid of this gpu + // Uuid of the physical GPU or GI UUID if nvUvmInterfaceGetGpuInfo() + // requested information for a valid SMC partition. NvProcessorUuid uuid; // Gpu architecture; NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_* @@ -688,8 +698,12 @@ typedef struct UvmGpuInfo_tag NvU64 nvswitchMemoryWindowStart; // local EGM properties + // NV_TRUE if EGM is enabled NvBool egmEnabled; + // Peer ID to reach local EGM when EGM is enabled NvU8 egmPeerId; + // EGM base address to offset in the GMMU PTE entry for EGM mappings + NvU64 egmBaseAddr; } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag @@ -778,14 +792,14 @@ typedef NV_STATUS (*uvmEventResume_t) (void); /******************************************************************************* uvmEventStartDevice This function will be called by the GPU driver once it has finished its - initialization to tell the UVM driver that this GPU has come up. + initialization to tell the UVM driver that this physical GPU has come up. */ typedef NV_STATUS (*uvmEventStartDevice_t) (const NvProcessorUuid *pGpuUuidStruct); /******************************************************************************* uvmEventStopDevice - This function will be called by the GPU driver to let UVM know that a GPU - is going down. + This function will be called by the GPU driver to let UVM know that a + physical GPU is going down. */ typedef NV_STATUS (*uvmEventStopDevice_t) (const NvProcessorUuid *pGpuUuidStruct); @@ -816,7 +830,7 @@ typedef NV_STATUS (*uvmEventServiceInterrupt_t) (void *pDeviceObject, /******************************************************************************* uvmEventIsrTopHalf_t This function will be called by the GPU driver to let UVM know - that an interrupt has occurred. + that an interrupt has occurred on the given physical GPU. Returns: NV_OK if the UVM driver handled the interrupt @@ -923,11 +937,6 @@ typedef struct UvmGpuFaultInfo_tag // CSL context used for performing decryption of replayable faults when // Confidential Computing is enabled. UvmCslContext cslCtx; - - // Indicates whether UVM owns the replayable fault buffer. - // The value of this field is always NV_TRUE When Confidential Computing - // is disabled. - NvBool bUvmOwnsHwFaultBuffer; } replayable; struct { diff --git a/kernel-open/common/inc/nvkms-api-types.h b/kernel-open/common/inc/nvkms-api-types.h index f56195c193..686599c615 100644 --- a/kernel-open/common/inc/nvkms-api-types.h +++ b/kernel-open/common/inc/nvkms-api-types.h @@ -58,6 +58,7 @@ typedef NvU32 NvKmsFrameLockHandle; typedef NvU32 NvKmsDeferredRequestFifoHandle; typedef NvU32 NvKmsSwapGroupHandle; typedef NvU32 NvKmsVblankSyncObjectHandle; +typedef NvU32 NvKmsVblankSemControlHandle; struct NvKmsSize { NvU16 width; diff --git a/kernel-open/common/inc/nvkms-kapi.h b/kernel-open/common/inc/nvkms-kapi.h index c487b4b786..f31f68101c 100644 --- a/kernel-open/common/inc/nvkms-kapi.h +++ b/kernel-open/common/inc/nvkms-kapi.h @@ -490,6 +490,8 @@ typedef enum NvKmsKapiRegisterWaiterResultRec { NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED, } NvKmsKapiRegisterWaiterResult; +typedef void NvKmsKapiSuspendResumeCallbackFunc(NvBool suspend); + struct NvKmsKapiFunctionsTable { /*! @@ -1399,6 +1401,15 @@ struct NvKmsKapiFunctionsTable { NvU64 index, NvU64 new_value ); + + /*! + * Set the callback function for suspending and resuming the display system. + */ + void + (*setSuspendResumeCallback) + ( + NvKmsKapiSuspendResumeCallbackFunc *function + ); }; /** @} */ diff --git a/kernel-open/common/inc/nvmisc.h b/kernel-open/common/inc/nvmisc.h index fa33a9ffd9..6c47b6d3e1 100644 --- a/kernel-open/common/inc/nvmisc.h +++ b/kernel-open/common/inc/nvmisc.h @@ -919,6 +919,9 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address) // #define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); } +// Get the number of elements the specified fixed-size array +#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) + #ifdef __cplusplus } #endif //__cplusplus diff --git a/kernel-open/common/inc/nvstatuscodes.h b/kernel-open/common/inc/nvstatuscodes.h index 3b11ee9eeb..be7e7a8265 100644 --- a/kernel-open/common/inc/nvstatuscodes.h +++ b/kernel-open/common/inc/nvstatuscodes.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -150,6 +150,7 @@ NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Confi NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt") NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded") NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value") +NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event") // Warnings: NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") diff --git a/kernel-open/common/inc/nvtypes.h b/kernel-open/common/inc/nvtypes.h index 84d72a0079..98a9323e3d 100644 --- a/kernel-open/common/inc/nvtypes.h +++ b/kernel-open/common/inc/nvtypes.h @@ -145,7 +145,12 @@ typedef signed short NvS16; /* -32768 to 32767 */ #endif // Macro to build an NvU32 from four bytes, listed from msb to lsb -#define NvU32_BUILD(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) +#define NvU32_BUILD(a, b, c, d) \ + ((NvU32)( \ + (((NvU32)(a) & 0xff) << 24) | \ + (((NvU32)(b) & 0xff) << 16) | \ + (((NvU32)(c) & 0xff) << 8) | \ + (((NvU32)(d) & 0xff)))) #if NVTYPES_USE_STDINT typedef uint32_t NvV32; /* "void": enumerated or multiple fields */ diff --git a/kernel-open/common/inc/os-interface.h b/kernel-open/common/inc/os-interface.h index ffbf4e1f5a..9f7b8046ff 100644 --- a/kernel-open/common/inc/os-interface.h +++ b/kernel-open/common/inc/os-interface.h @@ -67,7 +67,6 @@ typedef struct os_wait_queue os_wait_queue; * --------------------------------------------------------------------------- */ -NvU64 NV_API_CALL os_get_num_phys_pages (void); NV_STATUS NV_API_CALL os_alloc_mem (void **, NvU64); void NV_API_CALL os_free_mem (void *); NV_STATUS NV_API_CALL os_get_current_time (NvU32 *, NvU32 *); @@ -105,7 +104,6 @@ void* NV_API_CALL os_map_kernel_space (NvU64, NvU64, NvU32); void NV_API_CALL os_unmap_kernel_space (void *, NvU64); void* NV_API_CALL os_map_user_space (NvU64, NvU64, NvU32, NvU32, void **); void NV_API_CALL os_unmap_user_space (void *, NvU64, void *); -NV_STATUS NV_API_CALL os_flush_cpu_cache (void); NV_STATUS NV_API_CALL os_flush_cpu_cache_all (void); NV_STATUS NV_API_CALL os_flush_user_cache (void); void NV_API_CALL os_flush_cpu_write_combine_buffer(void); @@ -230,14 +228,12 @@ extern NvBool os_dma_buf_enabled; * --------------------------------------------------------------------------- */ -#define NV_DBG_INFO 0x1 -#define NV_DBG_SETUP 0x2 +#define NV_DBG_INFO 0x0 +#define NV_DBG_SETUP 0x1 +#define NV_DBG_USERERRORS 0x2 #define NV_DBG_WARNINGS 0x3 #define NV_DBG_ERRORS 0x4 -#define NV_DBG_HW_ERRORS 0x5 -#define NV_DBG_FATAL 0x6 -#define NV_DBG_FORCE_LEVEL(level) ((level) | (1 << 8)) void NV_API_CALL out_string(const char *str); int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...); diff --git a/kernel-open/common/inc/rm-gpu-ops.h b/kernel-open/common/inc/rm-gpu-ops.h index 9b7e38a2ba..0765b6539f 100644 --- a/kernel-open/common/inc/rm-gpu-ops.h +++ b/kernel-open/common/inc/rm-gpu-ops.h @@ -37,7 +37,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_create_session (nvidia_stack_t *, nvgpuSessio NV_STATUS NV_API_CALL rm_gpu_ops_destroy_session (nvidia_stack_t *, nvgpuSessionHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_device_create (nvidia_stack_t *, nvgpuSessionHandle_t, const nvgpuInfo_t *, const NvProcessorUuid *, nvgpuDeviceHandle_t *, NvBool); NV_STATUS NV_API_CALL rm_gpu_ops_device_destroy (nvidia_stack_t *, nvgpuDeviceHandle_t); -NV_STATUS NV_API_CALL rm_gpu_ops_address_space_create(nvidia_stack_t *, nvgpuDeviceHandle_t, unsigned long long, unsigned long long, nvgpuAddressSpaceHandle_t *, nvgpuAddressSpaceInfo_t); +NV_STATUS NV_API_CALL rm_gpu_ops_address_space_create(nvidia_stack_t *, nvgpuDeviceHandle_t, unsigned long long, unsigned long long, NvBool, nvgpuAddressSpaceHandle_t *, nvgpuAddressSpaceInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_dup_address_space(nvidia_stack_t *, nvgpuDeviceHandle_t, NvHandle, NvHandle, nvgpuAddressSpaceHandle_t *, nvgpuAddressSpaceInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_address_space_destroy(nvidia_stack_t *, nvgpuAddressSpaceHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_fb(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvLength, NvU64 *, nvgpuAllocInfo_t); @@ -45,7 +45,6 @@ NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_fb(nvidia_stack_t *, nvgpuAddres NV_STATUS NV_API_CALL rm_gpu_ops_pma_alloc_pages(nvidia_stack_t *, void *, NvLength, NvU32 , nvgpuPmaAllocationOptions_t, NvU64 *); NV_STATUS NV_API_CALL rm_gpu_ops_pma_free_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32, NvU32); NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32, NvU32); -NV_STATUS NV_API_CALL rm_gpu_ops_pma_unpin_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32); NV_STATUS NV_API_CALL rm_gpu_ops_get_pma_object(nvidia_stack_t *, nvgpuDeviceHandle_t, void **, const nvgpuPmaStatistics_t *); NV_STATUS NV_API_CALL rm_gpu_ops_pma_register_callbacks(nvidia_stack_t *sp, void *, nvPmaEvictPagesCallback, nvPmaEvictRangeCallback, void *); void NV_API_CALL rm_gpu_ops_pma_unregister_callbacks(nvidia_stack_t *sp, void *); @@ -77,6 +76,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_init_fault_info(nvidia_stack_t *, nvgpuDeviceH NV_STATUS NV_API_CALL rm_gpu_ops_destroy_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t); NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, void *, NvU32 *); NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *, nvgpuDeviceHandle_t); +NV_STATUS NV_API_CALL rm_gpu_ops_toggle_prefetch_faults(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool); NV_STATUS NV_API_CALL rm_gpu_ops_has_pending_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool *); NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, NvU32); NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t); @@ -103,6 +103,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *, n NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *, struct ccslContext_t **, nvgpuChannelHandle_t); NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *, struct ccslContext_t *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_update(nvidia_stack_t *, struct ccslContext_t *); NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8); NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *, NvU8 *); NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt_with_iv(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8*, NvU8 *, NvU8 *); @@ -110,5 +111,6 @@ NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *, struct ccslCont NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_sign(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *); NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_query_message_pool(nvidia_stack_t *, struct ccslContext_t *, NvU8, NvU64 *); NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_increment_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8, NvU64, NvU8 *); +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_log_device_encryption(nvidia_stack_t *, struct ccslContext_t *, NvU32); #endif diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index f36e1f4d14..3b33a862d3 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -14,6 +14,13 @@ OUTPUT=$4 XEN_PRESENT=1 PREEMPT_RT_PRESENT=0 +# We also use conftest.sh on FreeBSD to check for which symbols are provided +# by the linux kernel programming interface (linuxkpi) when compiling nvidia-drm.ko +OS_FREEBSD=0 +if [ "$OS" = "FreeBSD" ] ; then + OS_FREEBSD=1 +fi + # VGX_BUILD parameter defined only for VGX builds (vGPU Host driver) # VGX_KVM_BUILD parameter defined only vGPU builds on KVM hypervisor # GRID_BUILD parameter defined only for GRID builds (GRID Guest driver) @@ -205,11 +212,6 @@ CONFTEST_PREAMBLE="#include \"conftest/headers.h\" #if defined(NV_LINUX_KCONFIG_H_PRESENT) #include #endif - #if defined(NV_GENERATED_AUTOCONF_H_PRESENT) - #include - #else - #include - #endif #if defined(CONFIG_XEN) && \ defined(CONFIG_XEN_INTERFACE_VERSION) && !defined(__XEN_INTERFACE_VERSION__) #define __XEN_INTERFACE_VERSION__ CONFIG_XEN_INTERFACE_VERSION @@ -222,6 +224,17 @@ CONFTEST_PREAMBLE="#include \"conftest/headers.h\" #endif #endif" +# FreeBSD's Linux compatibility does not have autoconf.h defined +# anywhere yet, only add this part on Linux +if [ ${OS_FREEBSD} -ne 1 ] ; then + CONFTEST_PREAMBLE="${CONFTEST_PREAMBLE} + #if defined(NV_GENERATED_AUTOCONF_H_PRESENT) + #include + #else + #include + #endif" +fi + test_configuration_option() { # # Check to see if the given configuration option is defined @@ -308,16 +321,57 @@ compile_check_conftest() { fi } -export_symbol_present_conftest() { - # - # Check Module.symvers to see whether the given symbol is present. - # +check_symbol_exists() { + # Check that the given symbol is available SYMBOL="$1" TAB=' ' - if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL\(_GPL\)\?\s*\$" \ - "$OUTPUT/Module.symvers" >/dev/null 2>&1; then + if [ ${OS_FREEBSD} -ne 1 ] ; then + # Linux: + # ------ + # + # Check Module.symvers to see whether the given symbol is present. + # + if grep -e "${TAB}${SYMBOL}${TAB}.*${TAB}EXPORT_SYMBOL.*\$" \ + "$OUTPUT/Module.symvers" >/dev/null 2>&1; then + return 0 + fi + else + # FreeBSD: + # ------ + # + # Check if any of the linuxkpi or drm kernel module files contain + # references to this symbol. + + # Get the /boot/kernel/ and /boot/modules paths, convert the list to a + # space separated list instead of semicolon separated so we can iterate + # over it. + if [ -z "${CONFTEST_BSD_KMODPATHS}" ] ; then + KMODPATHS=`sysctl -n kern.module_path | sed -e "s/;/ /g"` + else + KMODPATHS="${CONFTEST_BSD_KMODPATHS}" + fi + + for KMOD in linuxkpi.ko linuxkpi_gplv2.ko drm.ko dmabuf.ko ; do + for KMODPATH in $KMODPATHS; do + if [ -e "$KMODPATH/$KMOD" ] ; then + if nm "$KMODPATH/$KMOD" | grep "$SYMBOL" >/dev/null 2>&1 ; then + return 0 + fi + fi + done + done + fi + + return 1 +} + +export_symbol_present_conftest() { + + SYMBOL="$1" + + if check_symbol_exists $SYMBOL; then echo "#define NV_IS_EXPORT_SYMBOL_PRESENT_$SYMBOL 1" | append_conftest "symbols" else @@ -1206,6 +1260,36 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_DEVICE_OPS_HAS_BIND_IOMMUFD" "" "types" ;; + vfio_device_ops_has_detach_ioas) + # + # Determine if 'vfio_device_ops' struct has 'detach_ioas' field. + # + # Added by commit 9048c7341c4df9cae04c154a8b0f556dbe913358 ("vfio-iommufd: Add detach_ioas + # support for physical VFIO devices + # + CODE=" + #include + #include + int conftest_vfio_device_ops_has_detach_ioas(void) { + return offsetof(struct vfio_device_ops, detach_ioas); + }" + + compile_check_conftest "$CODE" "NV_VFIO_DEVICE_OPS_HAS_DETACH_IOAS" "" "types" + ;; + + pfn_address_space) + # + # Determine if 'struct pfn_address_space' structure is present or not. + # + CODE=" + #include + void conftest_pfn_address_space() { + struct pfn_address_space pfn_address_space; + }" + + compile_check_conftest "$CODE" "NV_PFN_ADDRESS_SPACE_STRUCT_PRESENT" "" "types" + ;; + pci_irq_vector_helpers) # # Determine if pci_alloc_irq_vectors(), pci_free_irq_vectors() @@ -1343,7 +1427,7 @@ compile_test() { #include #endif - #if !defined(CONFIG_DRM) && !defined(CONFIG_DRM_MODULE) + #if !defined(CONFIG_DRM) && !defined(CONFIG_DRM_MODULE) && !defined(__FreeBSD__) #error DRM not enabled #endif @@ -1807,7 +1891,7 @@ compile_test() { #include #endif #include - #if !defined(CONFIG_DRM) && !defined(CONFIG_DRM_MODULE) + #if !defined(CONFIG_DRM) && !defined(CONFIG_DRM_MODULE) && !defined(__FreeBSD__) #error DRM not enabled #endif void conftest_drm_atomic_modeset_available(void) { @@ -5203,10 +5287,16 @@ compile_test() { # Added by commit 7b7b27214bba ("mm/memory_hotplug: introduce # add_memory_driver_managed()") in v5.8. # + # Before commit 3a0aaefe4134 ("mm/memory_hotplug: guard more + # declarations by CONFIG_MEMORY_HOTPLUG") in v5.10, the + # add_memory_driver_managed() was not guarded. + # CODE=" #include void conftest_add_memory_driver_managed() { + #if defined(CONFIG_MEMORY_HOTPLUG) add_memory_driver_managed(); + #endif }" compile_check_conftest "$CODE" "NV_ADD_MEMORY_DRIVER_MANAGED_PRESENT" "" "functions" @@ -5669,22 +5759,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_GPIO_TO_IRQ_PRESENT" "" "functions" ;; - migrate_vma_setup) - # - # Determine if migrate_vma_setup() function is present - # - # Added by commit a7d1f22bb74f ("mm: turn migrate_vma upside - # down") in v5.4. - # - CODE=" - #include - int conftest_migrate_vma_setup(void) { - migrate_vma_setup(); - }" - - compile_check_conftest "$CODE" "NV_MIGRATE_VMA_SETUP_PRESENT" "" "functions" - ;; - migrate_vma_added_flags) # # Determine if migrate_vma structure has flags @@ -5795,6 +5869,24 @@ compile_test() { compile_check_conftest "$CODE" "NV_MM_PASID_DROP_PRESENT" "" "functions" ;; + iommu_is_dma_domain) + # + # Determine if iommu_is_dma_domain() function is present + # this also assumes that iommu_get_domain_for_dev() function is + # present. + # + # Added by commit bf3aed4660c6 ("iommu: Introduce explicit type + # for non-strict DMA domains") in v5.15 + # + CODE=" + #include + void conftest_iommu_is_dma_domain(void) { + iommu_is_dma_domain(); + }" + + compile_check_conftest "$CODE" "NV_IOMMU_IS_DMA_DOMAIN_PRESENT" "" "functions" + ;; + drm_crtc_state_has_no_vblank) # # Determine if the 'drm_crtc_state' structure has 'no_vblank'. @@ -6483,6 +6575,21 @@ compile_test() { compile_check_conftest "$CODE" "NV_FIND_NEXT_BIT_WRAP_PRESENT" "" "functions" ;; + crypto_tfm_ctx_aligned) + # Determine if 'crypto_tfm_ctx_aligned' is defined. + # + # Removed by commit 25c74a39e0f6 ("crypto: hmac - remove unnecessary + # alignment logic") in v6.7. + # + CODE=" + #include + void conftest_crypto_tfm_ctx_aligned(void) { + (void)crypto_tfm_ctx_aligned(); + }" + + compile_check_conftest "$CODE" "NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT" "" "functions" + ;; + crypto) # # Determine if we support various crypto functions. @@ -6604,9 +6711,9 @@ compile_test() { # 'supported_colorspaces' argument. # # The 'u32 supported_colorspaces' argument was added to - # drm_mode_create_dp_colorspace_property() by linux-next commit + # drm_mode_create_dp_colorspace_property() by commit # c265f340eaa8 ("drm/connector: Allow drivers to pass list of - # supported colorspaces"). + # supported colorspaces") in v6.5. # # To test if drm_mode_create_dp_colorspace_property() has the # 'supported_colorspaces' argument, declare a function prototype @@ -6634,6 +6741,27 @@ compile_test() { compile_check_conftest "$CODE" "NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG" "" "types" ;; + drm_unlocked_ioctl_flag_present) + # Determine if DRM_UNLOCKED IOCTL flag is present. + # + # DRM_UNLOCKED was removed by commit 2798ffcc1d6a ("drm: Remove + # locking for legacy ioctls and DRM_UNLOCKED") in Linux + # next-20231208. + # + # DRM_UNLOCKED definition was moved from drmP.h to drm_ioctl.h by + # commit 2640981f3600 ("drm: document drm_ioctl.[hc]") in v4.12. + CODE=" + #if defined(NV_DRM_DRM_IOCTL_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRMP_H_PRESENT) + #include + #endif + int flags = DRM_UNLOCKED;" + + compile_check_conftest "$CODE" "NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. Please # avoid specifying -rc kernels, and only use SHAs that actually exist @@ -6935,10 +7063,12 @@ case "$5" in # VERBOSE=$6 iommu=CONFIG_VFIO_IOMMU_TYPE1 + iommufd_vfio_container=CONFIG_IOMMUFD_VFIO_CONTAINER mdev=CONFIG_VFIO_MDEV kvm=CONFIG_KVM_VFIO vfio_pci_core=CONFIG_VFIO_PCI_CORE VFIO_IOMMU_PRESENT=0 + VFIO_IOMMUFD_VFIO_CONTAINER_PRESENT=0 VFIO_MDEV_PRESENT=0 KVM_PRESENT=0 VFIO_PCI_CORE_PRESENT=0 @@ -6948,6 +7078,10 @@ case "$5" in VFIO_IOMMU_PRESENT=1 fi + if (test_configuration_option ${iommufd_vfio_container} || test_configuration_option ${iommufd_vfio_container}_MODULE); then + VFIO_IOMMUFD_VFIO_CONTAINER_PRESENT=1 + fi + if (test_configuration_option ${mdev} || test_configuration_option ${mdev}_MODULE); then VFIO_MDEV_PRESENT=1 fi @@ -6960,36 +7094,23 @@ case "$5" in VFIO_PCI_CORE_PRESENT=1 fi - # When this sanity check is run via nvidia-installer, it sets ARCH as aarch64. - # But, when it is run via Kbuild, ARCH is set as arm64 - if [ "$ARCH" = "aarch64" ]; then - ARCH="arm64" - fi - - if [ "$VFIO_IOMMU_PRESENT" != "0" ] && [ "$KVM_PRESENT" != "0" ] ; then - - # On x86_64, vGPU requires MDEV framework to be present. - # On aarch64, vGPU requires MDEV or vfio-pci-core framework to be present. - if ([ "$ARCH" = "arm64" ] && ([ "$VFIO_MDEV_PRESENT" != "0" ] || [ "$VFIO_PCI_CORE_PRESENT" != "0" ])) || - ([ "$ARCH" = "x86_64" ] && [ "$VFIO_MDEV_PRESENT" != "0" ];) then + if ([ "$VFIO_IOMMU_PRESENT" != "0" ] || [ "$VFIO_IOMMUFD_VFIO_CONTAINER_PRESENT" != "0" ])&& [ "$KVM_PRESENT" != "0" ] ; then + # vGPU requires either MDEV or vfio-pci-core framework to be present. + if [ "$VFIO_MDEV_PRESENT" != "0" ] || [ "$VFIO_PCI_CORE_PRESENT" != "0" ]; then exit 0 fi fi echo "Below CONFIG options are missing on the kernel for installing"; echo "NVIDIA vGPU driver on KVM host"; - if [ "$VFIO_IOMMU_PRESENT" = "0" ]; then - echo "CONFIG_VFIO_IOMMU_TYPE1"; + if [ "$VFIO_IOMMU_PRESENT" = "0" ] && [ "$VFIO_IOMMUFD_VFIO_CONTAINER_PRESENT" = "0" ]; then + echo "either CONFIG_VFIO_IOMMU_TYPE1 or CONFIG_IOMMUFD_VFIO_CONTAINER"; fi - if [ "$ARCH" = "arm64" ] && [ "$VFIO_MDEV_PRESENT" = "0" ] && [ "$VFIO_PCI_CORE_PRESENT" = "0" ]; then + if [ "$VFIO_MDEV_PRESENT" = "0" ] && [ "$VFIO_PCI_CORE_PRESENT" = "0" ]; then echo "either CONFIG_VFIO_MDEV or CONFIG_VFIO_PCI_CORE"; fi - if [ "$ARCH" = "x86_64" ] && [ "$VFIO_MDEV_PRESENT" = "0" ]; then - echo "CONFIG_VFIO_MDEV"; - fi - if [ "$KVM_PRESENT" = "0" ]; then echo "CONFIG_KVM"; fi diff --git a/kernel-open/header-presence-tests.mk b/kernel-open/header-presence-tests.mk new file mode 100644 index 0000000000..dc90689fdd --- /dev/null +++ b/kernel-open/header-presence-tests.mk @@ -0,0 +1,100 @@ +# Each of these headers is checked for presence with a test #include; a +# corresponding #define will be generated in conftest/headers.h. +NV_HEADER_PRESENCE_TESTS = \ + asm/system.h \ + drm/drmP.h \ + drm/drm_aperture.h \ + drm/drm_auth.h \ + drm/drm_gem.h \ + drm/drm_crtc.h \ + drm/drm_color_mgmt.h \ + drm/drm_atomic.h \ + drm/drm_atomic_helper.h \ + drm/drm_atomic_state_helper.h \ + drm/drm_encoder.h \ + drm/drm_atomic_uapi.h \ + drm/drm_drv.h \ + drm/drm_fbdev_generic.h \ + drm/drm_framebuffer.h \ + drm/drm_connector.h \ + drm/drm_probe_helper.h \ + drm/drm_blend.h \ + drm/drm_fourcc.h \ + drm/drm_prime.h \ + drm/drm_plane.h \ + drm/drm_vblank.h \ + drm/drm_file.h \ + drm/drm_ioctl.h \ + drm/drm_device.h \ + drm/drm_mode_config.h \ + drm/drm_modeset_lock.h \ + dt-bindings/interconnect/tegra_icc_id.h \ + generated/autoconf.h \ + generated/compile.h \ + generated/utsrelease.h \ + linux/efi.h \ + linux/kconfig.h \ + linux/platform/tegra/mc_utils.h \ + linux/printk.h \ + linux/ratelimit.h \ + linux/prio_tree.h \ + linux/log2.h \ + linux/of.h \ + linux/bug.h \ + linux/sched.h \ + linux/sched/mm.h \ + linux/sched/signal.h \ + linux/sched/task.h \ + linux/sched/task_stack.h \ + xen/ioemu.h \ + linux/fence.h \ + linux/dma-fence.h \ + linux/dma-resv.h \ + soc/tegra/chip-id.h \ + soc/tegra/fuse.h \ + soc/tegra/tegra_bpmp.h \ + video/nv_internal.h \ + linux/platform/tegra/dce/dce-client-ipc.h \ + linux/nvhost.h \ + linux/nvhost_t194.h \ + linux/host1x-next.h \ + asm/book3s/64/hash-64k.h \ + asm/set_memory.h \ + asm/prom.h \ + asm/powernv.h \ + linux/atomic.h \ + asm/barrier.h \ + asm/opal-api.h \ + sound/hdaudio.h \ + asm/pgtable_types.h \ + asm/page.h \ + linux/stringhash.h \ + linux/dma-map-ops.h \ + rdma/peer_mem.h \ + sound/hda_codec.h \ + linux/dma-buf.h \ + linux/time.h \ + linux/platform_device.h \ + linux/mutex.h \ + linux/reset.h \ + linux/of_platform.h \ + linux/of_device.h \ + linux/of_gpio.h \ + linux/gpio.h \ + linux/gpio/consumer.h \ + linux/interconnect.h \ + linux/pm_runtime.h \ + linux/clk.h \ + linux/clk-provider.h \ + linux/ioasid.h \ + linux/stdarg.h \ + linux/iosys-map.h \ + asm/coco.h \ + linux/vfio_pci_core.h \ + linux/mdev.h \ + soc/tegra/bpmp-abi.h \ + soc/tegra/bpmp.h \ + linux/sync_file.h \ + linux/cc_platform.h \ + asm/cpufeature.h + diff --git a/kernel-open/nvidia-drm/nv-pci-table.c b/kernel-open/nvidia-drm/nv-pci-table.c index e3494735a5..ac730d5710 100644 --- a/kernel-open/nvidia-drm/nv-pci-table.c +++ b/kernel-open/nvidia-drm/nv-pci-table.c @@ -25,6 +25,15 @@ #include #include "nv-pci-table.h" +#include "cpuopsys.h" + +#if defined(NV_BSD) +/* Define PCI classes that FreeBSD's linuxkpi is missing */ +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 +#endif /* Devices supported by RM */ struct pci_device_id nv_pci_table[] = { @@ -48,7 +57,7 @@ struct pci_device_id nv_pci_table[] = { }; /* Devices supported by all drivers in nvidia.ko */ -struct pci_device_id nv_module_device_table[] = { +struct pci_device_id nv_module_device_table[4] = { { .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_ANY_ID, @@ -76,4 +85,6 @@ struct pci_device_id nv_module_device_table[] = { { } }; +#if defined(NV_LINUX) MODULE_DEVICE_TABLE(pci, nv_module_device_table); +#endif diff --git a/kernel-open/nvidia-drm/nv-pci-table.h b/kernel-open/nvidia-drm/nv-pci-table.h index b28483bb61..25daaf420f 100644 --- a/kernel-open/nvidia-drm/nv-pci-table.h +++ b/kernel-open/nvidia-drm/nv-pci-table.h @@ -27,5 +27,6 @@ #include extern struct pci_device_id nv_pci_table[]; +extern struct pci_device_id nv_module_device_table[4]; #endif /* _NV_PCI_TABLE_H_ */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-conftest.h b/kernel-open/nvidia-drm/nvidia-drm-conftest.h index fd389f1099..552c2c9709 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-conftest.h +++ b/kernel-open/nvidia-drm/nvidia-drm-conftest.h @@ -24,6 +24,7 @@ #define __NVIDIA_DRM_CONFTEST_H__ #include "conftest.h" +#include "nvtypes.h" /* * NOTE: This file is expected to get included at the top before including any @@ -72,4 +73,121 @@ #undef NV_DRM_COLOR_MGMT_AVAILABLE #endif +/* + * Adapt to quirks in FreeBSD's Linux kernel compatibility layer. + */ +#if defined(NV_BSD) + +#include +#include +#include +#include + +/* For nv_drm_gem_prime_force_fence_signal */ +#ifndef spin_is_locked +#define spin_is_locked(lock) mtx_owned(lock.m) +#endif + +#ifndef rwsem_is_locked +#define rwsem_is_locked(sem) (((sem)->sx.sx_lock & (SX_LOCK_SHARED)) \ + || ((sem)->sx.sx_lock & ~(SX_LOCK_FLAGMASK & ~SX_LOCK_SHARED))) +#endif + +/* + * FreeBSD does not define vm_flags_t in its linuxkpi, since there is already + * a FreeBSD vm_flags_t (of a different size) and they don't want the names to + * collide. Temporarily redefine it when including nv-mm.h + */ +#define vm_flags_t unsigned long +#include "nv-mm.h" +#undef vm_flags_t + +/* + * sys/nv.h and nvidia/nv.h have the same header guard + * we need to clear it for nvlist_t to get loaded + */ +#undef _NV_H_ +#include + +/* + * For now just use set_page_dirty as the lock variant + * is not ported for FreeBSD. (in progress). This calls + * vm_page_dirty. Used in nv-mm.h + */ +#define set_page_dirty_lock set_page_dirty + +/* + * FreeBSD does not implement drm_atomic_state_free, simply + * default to drm_atomic_state_put + */ +#define drm_atomic_state_free drm_atomic_state_put + +#if __FreeBSD_version < 1300000 +/* redefine LIST_HEAD_INIT to the linux version */ +#include +#define LIST_HEAD_INIT(name) LINUX_LIST_HEAD_INIT(name) +#endif + +/* + * FreeBSD currently has only vmf_insert_pfn_prot defined, and it has a + * static assert warning not to use it since all of DRM's usages are in + * loops with the vm obj lock(s) held. Instead we should use the lkpi + * function itself directly. For us none of this applies so we can just + * wrap it in our own definition of vmf_insert_pfn + */ +#ifndef NV_VMF_INSERT_PFN_PRESENT +#define NV_VMF_INSERT_PFN_PRESENT 1 + +#if __FreeBSD_version < 1300000 +#define VM_SHARED (1 << 17) + +/* Not present in 12.2 */ +static inline vm_fault_t +lkpi_vmf_insert_pfn_prot_locked(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t prot) +{ + vm_object_t vm_obj = vma->vm_obj; + vm_page_t page; + vm_pindex_t pindex; + + VM_OBJECT_ASSERT_WLOCKED(vm_obj); + pindex = OFF_TO_IDX(addr - vma->vm_start); + if (vma->vm_pfn_count == 0) + vma->vm_pfn_first = pindex; + MPASS(pindex <= OFF_TO_IDX(vma->vm_end)); + + page = vm_page_grab(vm_obj, pindex, VM_ALLOC_NORMAL); + if (page == NULL) { + page = PHYS_TO_VM_PAGE(IDX_TO_OFF(pfn)); + vm_page_xbusy(page); + if (vm_page_insert(page, vm_obj, pindex)) { + vm_page_xunbusy(page); + return (VM_FAULT_OOM); + } + page->valid = VM_PAGE_BITS_ALL; + } + pmap_page_set_memattr(page, pgprot2cachemode(prot)); + vma->vm_pfn_count++; + + return (VM_FAULT_NOPAGE); +} +#endif + +static inline vm_fault_t +vmf_insert_pfn(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn) +{ + vm_fault_t ret; + + VM_OBJECT_WLOCK(vma->vm_obj); + ret = lkpi_vmf_insert_pfn_prot_locked(vma, addr, pfn, vma->vm_page_prot); + VM_OBJECT_WUNLOCK(vma->vm_obj); + + return (ret); +} + +#endif + +#endif /* defined(NV_BSD) */ + #endif /* defined(__NVIDIA_DRM_CONFTEST_H__) */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-crtc.c b/kernel-open/nvidia-drm/nvidia-drm-crtc.c index 8a12da70ba..6c8f082c25 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-crtc.c +++ b/kernel-open/nvidia-drm/nvidia-drm-crtc.c @@ -92,11 +92,22 @@ static void nv_drm_plane_destroy(struct drm_plane *plane) nv_drm_free(nv_plane); } +static inline void +plane_config_clear(struct NvKmsKapiLayerConfig *layerConfig) +{ + if (layerConfig == NULL) { + return; + } + + memset(layerConfig, 0, sizeof(*layerConfig)); + layerConfig->csc = NVKMS_IDENTITY_CSC_MATRIX; +} + static inline void plane_req_config_disable(struct NvKmsKapiLayerRequestedConfig *req_config) { /* Clear layer config */ - memset(&req_config->config, 0, sizeof(req_config->config)); + plane_config_clear(&req_config->config); /* Set flags to get cleared layer config applied */ req_config->flags.surfaceChanged = NV_TRUE; @@ -113,6 +124,45 @@ cursor_req_config_disable(struct NvKmsKapiCursorRequestedConfig *req_config) req_config->flags.surfaceChanged = NV_TRUE; } +#if defined(NV_DRM_COLOR_MGMT_AVAILABLE) +static void color_mgmt_config_ctm_to_csc(struct NvKmsCscMatrix *nvkms_csc, + struct drm_color_ctm *drm_ctm) +{ + int y; + + /* CTM is a 3x3 matrix while ours is 3x4. Zero out the last column. */ + nvkms_csc->m[0][3] = nvkms_csc->m[1][3] = nvkms_csc->m[2][3] = 0; + + for (y = 0; y < 3; y++) { + int x; + + for (x = 0; x < 3; x++) { + /* + * Values in the CTM are encoded in S31.32 sign-magnitude fixed- + * point format, while NvKms CSC values are signed 2's-complement + * S15.16 (Ssign-extend12-3.16?) fixed-point format. + */ + NvU64 ctmVal = drm_ctm->matrix[y*3 + x]; + NvU64 signBit = ctmVal & (1ULL << 63); + NvU64 magnitude = ctmVal & ~signBit; + + /* + * Drop the low 16 bits of the fractional part and the high 17 bits + * of the integral part. Drop 17 bits to avoid corner cases where + * the highest resulting bit is a 1, causing the `cscVal = -cscVal` + * line to result in a positive number. + */ + NvS32 cscVal = (magnitude >> 16) & ((1ULL << 31) - 1); + if (signBit) { + cscVal = -cscVal; + } + + nvkms_csc->m[y][x] = cscVal; + } + } +} +#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */ + static void cursor_plane_req_config_update(struct drm_plane *plane, struct drm_plane_state *plane_state, @@ -239,6 +289,8 @@ plane_req_config_update(struct drm_plane *plane, .dstY = plane_state->crtc_y, .dstWidth = plane_state->crtc_w, .dstHeight = plane_state->crtc_h, + + .csc = old_config.csc }, }; @@ -578,6 +630,24 @@ static int nv_drm_plane_atomic_check(struct drm_plane *plane, return ret; } +#if defined(NV_DRM_COLOR_MGMT_AVAILABLE) + if (crtc_state->color_mgmt_changed) { + /* + * According to the comment in the Linux kernel's + * drivers/gpu/drm/drm_color_mgmt.c, if this property is NULL, + * the CTM needs to be changed to the identity matrix + */ + if (crtc_state->ctm) { + color_mgmt_config_ctm_to_csc(&plane_requested_config->config.csc, + (struct drm_color_ctm *)crtc_state->ctm->data); + } else { + plane_requested_config->config.csc = NVKMS_IDENTITY_CSC_MATRIX; + } + plane_requested_config->config.cscUseMain = NV_FALSE; + plane_requested_config->flags.cscChanged = NV_TRUE; + } +#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */ + if (__is_async_flip_requested(plane, crtc_state)) { /* * Async flip requests that the flip happen 'as soon as @@ -668,6 +738,38 @@ static int nv_drm_plane_atomic_get_property( return -EINVAL; } +/** + * nv_drm_plane_atomic_reset - plane state reset hook + * @plane: DRM plane + * + * Allocate an empty DRM plane state. + */ +static void nv_drm_plane_atomic_reset(struct drm_plane *plane) +{ + struct nv_drm_plane_state *nv_plane_state = + nv_drm_calloc(1, sizeof(*nv_plane_state)); + + if (!nv_plane_state) { + return; + } + + drm_atomic_helper_plane_reset(plane); + + /* + * The drm atomic helper function allocates a state object that is the wrong + * size. Copy its contents into the one we allocated above and replace the + * pointer. + */ + if (plane->state) { + nv_plane_state->base = *plane->state; + kfree(plane->state); + plane->state = &nv_plane_state->base; + } else { + kfree(nv_plane_state); + } +} + + static struct drm_plane_state * nv_drm_plane_atomic_duplicate_state(struct drm_plane *plane) { @@ -727,7 +829,7 @@ static const struct drm_plane_funcs nv_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = nv_drm_plane_destroy, - .reset = drm_atomic_helper_plane_reset, + .reset = nv_drm_plane_atomic_reset, .atomic_get_property = nv_drm_plane_atomic_get_property, .atomic_set_property = nv_drm_plane_atomic_set_property, .atomic_duplicate_state = nv_drm_plane_atomic_duplicate_state, @@ -784,6 +886,52 @@ static inline void nv_drm_crtc_duplicate_req_head_modeset_config( } } +static inline struct nv_drm_crtc_state *nv_drm_crtc_state_alloc(void) +{ + struct nv_drm_crtc_state *nv_state = nv_drm_calloc(1, sizeof(*nv_state)); + int i; + + if (nv_state == NULL) { + return NULL; + } + + for (i = 0; i < ARRAY_SIZE(nv_state->req_config.layerRequestedConfig); i++) { + plane_config_clear(&nv_state->req_config.layerRequestedConfig[i].config); + } + return nv_state; +} + + +/** + * nv_drm_atomic_crtc_reset - crtc state reset hook + * @crtc: DRM crtc + * + * Allocate an empty DRM crtc state. + */ +static void nv_drm_atomic_crtc_reset(struct drm_crtc *crtc) +{ + struct nv_drm_crtc_state *nv_state = nv_drm_crtc_state_alloc(); + + if (!nv_state) { + return; + } + + drm_atomic_helper_crtc_reset(crtc); + + /* + * The drm atomic helper function allocates a state object that is the wrong + * size. Copy its contents into the one we allocated above and replace the + * pointer. + */ + if (crtc->state) { + nv_state->base = *crtc->state; + kfree(crtc->state); + crtc->state = &nv_state->base; + } else { + kfree(nv_state); + } +} + /** * nv_drm_atomic_crtc_duplicate_state - crtc state duplicate hook * @crtc: DRM crtc @@ -795,7 +943,7 @@ static inline void nv_drm_crtc_duplicate_req_head_modeset_config( static struct drm_crtc_state* nv_drm_atomic_crtc_duplicate_state(struct drm_crtc *crtc) { - struct nv_drm_crtc_state *nv_state = nv_drm_calloc(1, sizeof(*nv_state)); + struct nv_drm_crtc_state *nv_state = nv_drm_crtc_state_alloc(); if (nv_state == NULL) { return NULL; @@ -851,7 +999,7 @@ static void nv_drm_atomic_crtc_destroy_state(struct drm_crtc *crtc, static struct drm_crtc_funcs nv_crtc_funcs = { .set_config = drm_atomic_helper_set_config, .page_flip = drm_atomic_helper_page_flip, - .reset = drm_atomic_helper_crtc_reset, + .reset = nv_drm_atomic_crtc_reset, .destroy = nv_drm_crtc_destroy, .atomic_duplicate_state = nv_drm_atomic_crtc_duplicate_state, .atomic_destroy_state = nv_drm_atomic_crtc_destroy_state, @@ -914,70 +1062,25 @@ static int color_mgmt_config_copy_lut(struct NvKmsLutRamps *nvkms_lut, return 0; } -static void color_mgmt_config_ctm_to_csc(struct NvKmsCscMatrix *nvkms_csc, - struct drm_color_ctm *drm_ctm) -{ - int y; - - /* CTM is a 3x3 matrix while ours is 3x4. Zero out the last column. */ - nvkms_csc->m[0][3] = nvkms_csc->m[1][3] = nvkms_csc->m[2][3] = 0; - - for (y = 0; y < 3; y++) { - int x; - - for (x = 0; x < 3; x++) { - /* - * Values in the CTM are encoded in S31.32 sign-magnitude fixed- - * point format, while NvKms CSC values are signed 2's-complement - * S15.16 (Ssign-extend12-3.16?) fixed-point format. - */ - NvU64 ctmVal = drm_ctm->matrix[y*3 + x]; - NvU64 signBit = ctmVal & (1ULL << 63); - NvU64 magnitude = ctmVal & ~signBit; - - /* - * Drop the low 16 bits of the fractional part and the high 17 bits - * of the integral part. Drop 17 bits to avoid corner cases where - * the highest resulting bit is a 1, causing the `cscVal = -cscVal` - * line to result in a positive number. - */ - NvS32 cscVal = (magnitude >> 16) & ((1ULL << 31) - 1); - if (signBit) { - cscVal = -cscVal; - } - - nvkms_csc->m[y][x] = cscVal; - } - } -} - -static int color_mgmt_config_set(struct nv_drm_crtc_state *nv_crtc_state, - struct NvKmsKapiHeadRequestedConfig *req_config) +static int color_mgmt_config_set_luts(struct nv_drm_crtc_state *nv_crtc_state, + struct NvKmsKapiHeadRequestedConfig *req_config) { struct NvKmsKapiHeadModeSetConfig *modeset_config = &req_config->modeSetConfig; struct drm_crtc_state *crtc_state = &nv_crtc_state->base; int ret = 0; - struct drm_color_lut *degamma_lut = NULL; - struct drm_color_ctm *ctm = NULL; - struct drm_color_lut *gamma_lut = NULL; - uint64_t degamma_len = 0; - uint64_t gamma_len = 0; - - int i; - struct drm_plane *plane; - struct drm_plane_state *plane_state; - /* * According to the comment in the Linux kernel's - * drivers/gpu/drm/drm_color_mgmt.c, if any of these properties are NULL, - * that LUT or CTM needs to be changed to a linear LUT or identity matrix - * respectively. + * drivers/gpu/drm/drm_color_mgmt.c, if either property is NULL, that LUT + * needs to be changed to a linear LUT */ req_config->flags.lutChanged = NV_TRUE; if (crtc_state->degamma_lut) { + struct drm_color_lut *degamma_lut = NULL; + uint64_t degamma_len = 0; + nv_crtc_state->ilut_ramps = nv_drm_calloc(1, sizeof(*nv_crtc_state->ilut_ramps)); if (!nv_crtc_state->ilut_ramps) { ret = -ENOMEM; @@ -1007,34 +1110,13 @@ static int color_mgmt_config_set(struct nv_drm_crtc_state *nv_crtc_state, modeset_config->lut.input.start = 0; modeset_config->lut.input.end = 0; modeset_config->lut.input.pRamps = NULL; - } - - nv_drm_for_each_new_plane_in_state(crtc_state->state, plane, - plane_state, i) { - struct nv_drm_plane *nv_plane = to_nv_plane(plane); - uint32_t layer = nv_plane->layer_idx; - struct NvKmsKapiLayerRequestedConfig *layer_config; - - if (layer == NVKMS_KAPI_LAYER_INVALID_IDX || plane_state->crtc != crtc_state->crtc) { - continue; - } - layer_config = &req_config->layerRequestedConfig[layer]; - if (layer == NVKMS_KAPI_LAYER_PRIMARY_IDX && crtc_state->ctm) { - ctm = (struct drm_color_ctm *)crtc_state->ctm->data; - - color_mgmt_config_ctm_to_csc(&layer_config->config.csc, ctm); - layer_config->config.cscUseMain = NV_FALSE; - } else { - /* When crtc_state->ctm is unset, this also sets the main layer to - * the identity matrix. - */ - layer_config->config.csc = NVKMS_IDENTITY_CSC_MATRIX; - } - layer_config->flags.cscChanged = NV_TRUE; } if (crtc_state->gamma_lut) { + struct drm_color_lut *gamma_lut = NULL; + uint64_t gamma_len = 0; + nv_crtc_state->olut_ramps = nv_drm_calloc(1, sizeof(*nv_crtc_state->olut_ramps)); if (!nv_crtc_state->olut_ramps) { ret = -ENOMEM; @@ -1158,7 +1240,7 @@ static int nv_drm_crtc_atomic_check(struct drm_crtc *crtc, crtc_state->color_mgmt_changed = NV_TRUE; } if (crtc_state->color_mgmt_changed) { - if ((ret = color_mgmt_config_set(nv_crtc_state, req_config)) != 0) { + if ((ret = color_mgmt_config_set_luts(nv_crtc_state, req_config)) != 0) { return ret; } } @@ -1428,7 +1510,7 @@ static struct drm_crtc *__nv_drm_crtc_create(struct nv_drm_device *nv_dev, goto failed; } - nv_state = nv_drm_calloc(1, sizeof(*nv_state)); + nv_state = nv_drm_crtc_state_alloc(); if (nv_state == NULL) { goto failed_state_alloc; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index e0ddb6cb27..7c8ee7ccbf 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -74,6 +74,7 @@ #endif #include +#include /* * Commit fcd70cd36b9b ("drm: Split out drm_probe_helper.h") @@ -405,6 +406,27 @@ static int nv_drm_create_properties(struct nv_drm_device *nv_dev) return 0; } +#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) +/* + * We can't just call drm_kms_helper_hotplug_event directly because + * fbdev_generic may attempt to set a mode from inside the hotplug event + * handler. Because kapi event handling runs on nvkms_kthread_q, this blocks + * other event processing including the flip completion notifier expected by + * nv_drm_atomic_commit. + * + * Defer hotplug event handling to a work item so that nvkms_kthread_q can + * continue processing events while a DRM modeset is in progress. + */ +static void nv_drm_handle_hotplug_event(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct nv_drm_device *nv_dev = + container_of(dwork, struct nv_drm_device, hotplug_event_work); + + drm_kms_helper_hotplug_event(nv_dev->dev); +} +#endif + static int nv_drm_load(struct drm_device *dev, unsigned long flags) { #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) @@ -540,6 +562,7 @@ static int nv_drm_load(struct drm_device *dev, unsigned long flags) /* Enable event handling */ + INIT_DELAYED_WORK(&nv_dev->hotplug_event_work, nv_drm_handle_hotplug_event); atomic_set(&nv_dev->enable_event_handling, true); init_waitqueue_head(&nv_dev->flip_event_wq); @@ -567,6 +590,7 @@ static void __nv_drm_unload(struct drm_device *dev) return; } + cancel_delayed_work_sync(&nv_dev->hotplug_event_work); mutex_lock(&nv_dev->lock); WARN_ON(nv_dev->subOwnershipGranted); @@ -1523,9 +1547,21 @@ static const struct drm_ioctl_desc nv_drm_ioctls[] = { DRM_RENDER_ALLOW|DRM_UNLOCKED), #endif + /* + * DRM_UNLOCKED is implicit for all non-legacy DRM driver IOCTLs since Linux + * v4.10 commit fa5386459f06 "drm: Used DRM_LEGACY for all legacy functions" + * (Linux v4.4 commit ea487835e887 "drm: Enforce unlocked ioctl operation + * for kms driver ioctls" previously did it only for drivers that set the + * DRM_MODESET flag), so this will race with SET_CLIENT_CAP. Linux v4.11 + * commit dcf727ab5d17 "drm: setclientcap doesn't need the drm BKL" also + * removed locking from SET_CLIENT_CAP so there is no use attempting to lock + * manually. The latter commit acknowledges that this can expose userspace + * to inconsistent behavior when racing with itself, but accepts that risk. + */ DRM_IOCTL_DEF_DRV(NVIDIA_GET_CLIENT_CAPABILITY, nv_drm_get_client_capability_ioctl, 0), + #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) DRM_IOCTL_DEF_DRV(NVIDIA_GET_CRTC_CRC32, nv_drm_get_crtc_crc32_ioctl, @@ -1647,7 +1683,7 @@ static struct drm_driver nv_drm_driver = { * kernel supports atomic modeset and the 'modeset' kernel module * parameter is true. */ -static void nv_drm_update_drm_driver_features(void) +void nv_drm_update_drm_driver_features(void) { #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) @@ -1673,7 +1709,7 @@ static void nv_drm_update_drm_driver_features(void) /* * Helper function for allocate/register DRM device for given NVIDIA GPU ID. */ -static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info) +void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info) { struct nv_drm_device *nv_dev = NULL; struct drm_device *dev = NULL; @@ -1711,8 +1747,15 @@ static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info) dev->dev_private = nv_dev; nv_dev->dev = dev; + bool bus_is_pci = +#if defined(NV_LINUX) + device->bus == &pci_bus_type; +#elif defined(NV_BSD) + devclass_find("pci"); +#endif + #if defined(NV_DRM_DEVICE_HAS_PDEV) - if (device->bus == &pci_bus_type) { + if (bus_is_pci) { dev->pdev = to_pci_dev(device); } #endif @@ -1733,7 +1776,7 @@ static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info) goto failed_grab_ownership; } - if (device->bus == &pci_bus_type) { + if (bus_is_pci) { struct pci_dev *pdev = to_pci_dev(device); #if defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_HAS_DRIVER_ARG) @@ -1773,6 +1816,7 @@ static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info) /* * Enumerate NVIDIA GPUs and allocate/register DRM device for each of them. */ +#if defined(NV_LINUX) int nv_drm_probe_devices(void) { nv_gpu_info_t *gpu_info = NULL; @@ -1815,6 +1859,7 @@ int nv_drm_probe_devices(void) return ret; } +#endif /* * Unregister all NVIDIA DRM devices. @@ -1840,4 +1885,51 @@ void nv_drm_remove_devices(void) } } +/* + * Handle system suspend and resume. + * + * Normally, a DRM driver would use drm_mode_config_helper_suspend() to save the + * current state on suspend and drm_mode_config_helper_resume() to restore it + * after resume. This works for upstream drivers because user-mode tasks are + * frozen before the suspend hook is called. + * + * In the case of nvidia-drm, the suspend hook is also called when 'suspend' is + * written to /proc/driver/nvidia/suspend, before user-mode tasks are frozen. + * However, we don't actually need to save and restore the display state because + * the driver requires a VT switch to an unused VT before suspending and a + * switch back to the application (or fbdev console) on resume. The DRM client + * (or fbdev helper functions) will restore the appropriate mode on resume. + * + */ +void nv_drm_suspend_resume(NvBool suspend) +{ +#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) + struct nv_drm_device *nv_dev = dev_list; + + /* + * NVKMS shuts down all heads on suspend. Update DRM state accordingly. + */ + for (nv_dev = dev_list; nv_dev; nv_dev = nv_dev->next) { + struct drm_device *dev = nv_dev->dev; + + if (!drm_core_check_feature(dev, DRIVER_MODESET)) { + continue; + } + + if (suspend) { + drm_kms_helper_poll_disable(dev); +#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 1); +#endif + drm_mode_config_reset(dev); + } else { +#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 0); +#endif + drm_kms_helper_poll_enable(dev); + } + } +#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */ +} + #endif /* NV_DRM_AVAILABLE */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.h b/kernel-open/nvidia-drm/nvidia-drm-drv.h index cd20ec93fe..08445caf8a 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.h +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.h @@ -31,6 +31,12 @@ int nv_drm_probe_devices(void); void nv_drm_remove_devices(void); +void nv_drm_suspend_resume(NvBool suspend); + +void nv_drm_register_drm_device(const nv_gpu_info_t *); + +void nv_drm_update_drm_driver_features(void); + #endif /* defined(NV_DRM_AVAILABLE) */ #endif /* __NVIDIA_DRM_DRV_H__ */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-encoder.c b/kernel-open/nvidia-drm/nvidia-drm-encoder.c index b5ef5a2829..7c0c119b93 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-encoder.c +++ b/kernel-open/nvidia-drm/nvidia-drm-encoder.c @@ -300,7 +300,7 @@ void nv_drm_handle_display_change(struct nv_drm_device *nv_dev, nv_drm_connector_mark_connection_status_dirty(nv_encoder->nv_connector); - drm_kms_helper_hotplug_event(dev); + schedule_delayed_work(&nv_dev->hotplug_event_work, 0); } void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev, @@ -347,6 +347,6 @@ void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev, drm_reinit_primary_mode_group(dev); #endif - drm_kms_helper_hotplug_event(dev); + schedule_delayed_work(&nv_dev->hotplug_event_work, 0); } #endif diff --git a/kernel-open/nvidia-drm/nvidia-drm-fb.c b/kernel-open/nvidia-drm/nvidia-drm-fb.c index 2747123ff5..1c84201552 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-fb.c +++ b/kernel-open/nvidia-drm/nvidia-drm-fb.c @@ -240,7 +240,7 @@ struct drm_framebuffer *nv_drm_internal_framebuffer_create( if (nv_dev->modifiers[i] == DRM_FORMAT_MOD_INVALID) { NV_DRM_DEV_DEBUG_DRIVER( nv_dev, - "Invalid format modifier for framebuffer object: 0x%016llx", + "Invalid format modifier for framebuffer object: 0x%016" NvU64_fmtx, modifier); return ERR_PTR(-EINVAL); } diff --git a/kernel-open/nvidia-drm/nvidia-drm-fence.c b/kernel-open/nvidia-drm/nvidia-drm-fence.c index 23298ad12c..e6621178f4 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-fence.c +++ b/kernel-open/nvidia-drm/nvidia-drm-fence.c @@ -1638,7 +1638,7 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev, if (p->pre_wait_value >= p->post_wait_value) { NV_DRM_DEV_LOG_ERR( nv_dev, - "Non-monotonic wait values specified to fence wait: 0x%llu, 0x%llu", + "Non-monotonic wait values specified to fence wait: 0x%" NvU64_fmtu ", 0x%" NvU64_fmtu, p->pre_wait_value, p->post_wait_value); goto done; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c b/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c index fccde05d01..08c6c12c06 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c @@ -71,12 +71,42 @@ static int __nv_drm_gem_dma_buf_create_mmap_offset( static int __nv_drm_gem_dma_buf_mmap(struct nv_drm_gem_object *nv_gem, struct vm_area_struct *vma) { +#if defined(NV_LINUX) struct dma_buf_attachment *attach = nv_gem->base.import_attach; struct dma_buf *dma_buf = attach->dmabuf; +#endif struct file *old_file; int ret; /* check if buffer supports mmap */ +#if defined(NV_BSD) + /* + * Most of the FreeBSD DRM code refers to struct file*, which is actually + * a struct linux_file*. The dmabuf code in FreeBSD is not actually plumbed + * through the same linuxkpi bits it seems (probably so it can be used + * elsewhere), so dma_buf->file really is a native FreeBSD struct file... + */ + if (!nv_gem->base.filp->f_op->mmap) + return -EINVAL; + + /* readjust the vma */ + get_file(nv_gem->base.filp); + old_file = vma->vm_file; + vma->vm_file = nv_gem->base.filp; + vma->vm_pgoff -= drm_vma_node_start(&nv_gem->base.vma_node); + + ret = nv_gem->base.filp->f_op->mmap(nv_gem->base.filp, vma); + + if (ret) { + /* restore old parameters on failure */ + vma->vm_file = old_file; + vma->vm_pgoff += drm_vma_node_start(&nv_gem->base.vma_node); + fput(nv_gem->base.filp); + } else { + if (old_file) + fput(old_file); + } +#else if (!dma_buf->file->f_op->mmap) return -EINVAL; @@ -84,18 +114,20 @@ static int __nv_drm_gem_dma_buf_mmap(struct nv_drm_gem_object *nv_gem, get_file(dma_buf->file); old_file = vma->vm_file; vma->vm_file = dma_buf->file; - vma->vm_pgoff -= drm_vma_node_start(&nv_gem->base.vma_node);; + vma->vm_pgoff -= drm_vma_node_start(&nv_gem->base.vma_node); ret = dma_buf->file->f_op->mmap(dma_buf->file, vma); if (ret) { /* restore old parameters on failure */ vma->vm_file = old_file; + vma->vm_pgoff += drm_vma_node_start(&nv_gem->base.vma_node); fput(dma_buf->file); } else { if (old_file) fput(old_file); } +#endif return ret; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c index 7d66c432ec..468a9c2bcb 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c @@ -37,6 +37,9 @@ #endif #include +#if defined(NV_BSD) +#include +#endif #include "nv-mm.h" @@ -93,7 +96,17 @@ static vm_fault_t __nv_drm_gem_nvkms_handle_vma_fault( if (nv_nvkms_memory->pages_count == 0) { pfn = (unsigned long)(uintptr_t)nv_nvkms_memory->pPhysicalAddress; pfn >>= PAGE_SHIFT; +#if defined(NV_LINUX) + /* + * FreeBSD doesn't set pgoff. We instead have pfn be the base physical + * address, and we will calculate the index pidx from the virtual address. + * + * This only works because linux_cdev_pager_populate passes the pidx as + * vmf->virtual_address. Then we turn the virtual address + * into a physical page number. + */ pfn += page_offset; +#endif } else { BUG_ON(page_offset >= nv_nvkms_memory->pages_count); pfn = page_to_pfn(nv_nvkms_memory->pages[page_offset]); @@ -243,6 +256,15 @@ static int __nv_drm_nvkms_gem_obj_init( NvU64 *pages = NULL; NvU32 numPages = 0; + if ((size % PAGE_SIZE) != 0) { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "NvKmsKapiMemory 0x%p size should be in a multiple of page size to " + "create a gem object", + pMemory); + return -EINVAL; + } + nv_nvkms_memory->pPhysicalAddress = NULL; nv_nvkms_memory->pWriteCombinedIORemapAddress = NULL; nv_nvkms_memory->physically_mapped = false; @@ -314,7 +336,7 @@ int nv_drm_dumb_create( ret = -ENOMEM; NV_DRM_DEV_LOG_ERR( nv_dev, - "Failed to allocate NvKmsKapiMemory for dumb object of size %llu", + "Failed to allocate NvKmsKapiMemory for dumb object of size %" NvU64_fmtu, args->size); goto nvkms_alloc_memory_failed; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c b/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c index 9382409879..9d2a0512ac 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c +++ b/kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c @@ -36,6 +36,10 @@ #include "linux/mm.h" #include "nv-mm.h" +#if defined(NV_BSD) +#include +#endif + static inline void __nv_drm_gem_user_memory_free(struct nv_drm_gem_object *nv_gem) { @@ -113,6 +117,10 @@ static vm_fault_t __nv_drm_gem_user_memory_handle_vma_fault( page_offset = vmf->pgoff - drm_vma_node_start(&gem->vma_node); BUG_ON(page_offset >= nv_user_memory->pages_count); + +#if !defined(NV_LINUX) + ret = vmf_insert_pfn(vma, address, page_to_pfn(nv_user_memory->pages[page_offset])); +#else /* !defined(NV_LINUX) */ ret = vm_insert_page(vma, address, nv_user_memory->pages[page_offset]); switch (ret) { case 0: @@ -131,6 +139,7 @@ static vm_fault_t __nv_drm_gem_user_memory_handle_vma_fault( ret = VM_FAULT_SIGBUS; break; } +#endif /* !defined(NV_LINUX) */ return ret; } @@ -170,7 +179,7 @@ int nv_drm_gem_import_userspace_memory_ioctl(struct drm_device *dev, if ((params->size % PAGE_SIZE) != 0) { NV_DRM_DEV_LOG_ERR( nv_dev, - "Userspace memory 0x%llx size should be in a multiple of page " + "Userspace memory 0x%" NvU64_fmtx " size should be in a multiple of page " "size to create a gem object", params->address); return -EINVAL; @@ -183,7 +192,7 @@ int nv_drm_gem_import_userspace_memory_ioctl(struct drm_device *dev, if (ret != 0) { NV_DRM_DEV_LOG_ERR( nv_dev, - "Failed to lock user pages for address 0x%llx: %d", + "Failed to lock user pages for address 0x%" NvU64_fmtx ": %d", params->address, ret); return ret; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-helper.h b/kernel-open/nvidia-drm/nvidia-drm-helper.h index 6bb966059e..94d48db9fd 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-helper.h +++ b/kernel-open/nvidia-drm/nvidia-drm-helper.h @@ -612,6 +612,19 @@ static inline int nv_drm_format_num_planes(uint32_t format) #endif /* defined(NV_DRM_FORMAT_MODIFIERS_PRESENT) */ +/* + * DRM_UNLOCKED was removed with linux-next commit 2798ffcc1d6a ("drm: Remove + * locking for legacy ioctls and DRM_UNLOCKED"), but it was previously made + * implicit for all non-legacy DRM driver IOCTLs since Linux v4.10 commit + * fa5386459f06 "drm: Used DRM_LEGACY for all legacy functions" (Linux v4.4 + * commit ea487835e887 "drm: Enforce unlocked ioctl operation for kms driver + * ioctls" previously did it only for drivers that set the DRM_MODESET flag), so + * it was effectively a no-op anyway. + */ +#if !defined(NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT) +#define DRM_UNLOCKED 0 +#endif + /* * drm_vma_offset_exact_lookup_locked() were added * by kernel commit 2225cfe46bcc which was Signed-off-by: diff --git a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h index 45e9b06486..98b8bdd4ac 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-ioctl.h +++ b/kernel-open/nvidia-drm/nvidia-drm-ioctl.h @@ -71,7 +71,7 @@ * * 'warning: suggest parentheses around arithmetic in operand of |' */ -#if defined(NV_LINUX) +#if defined(NV_LINUX) || defined(NV_BSD) #define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED \ DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_SUPPORTED) #define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED \ diff --git a/kernel-open/nvidia-drm/nvidia-drm-linux.c b/kernel-open/nvidia-drm/nvidia-drm-linux.c index 17daa88b78..8c59b7cb2e 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-linux.c +++ b/kernel-open/nvidia-drm/nvidia-drm-linux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -21,8 +21,6 @@ */ #include -#include -#include #include "nvidia-drm-os-interface.h" #include "nvidia-drm.h" @@ -31,261 +29,18 @@ #if defined(NV_DRM_AVAILABLE) -#if defined(NV_DRM_DRMP_H_PRESENT) -#include -#endif - -#if defined(NV_LINUX_SYNC_FILE_H_PRESENT) -#include -#include -#endif - -#include -#include - -#include "nv-mm.h" - MODULE_PARM_DESC( modeset, "Enable atomic kernel modesetting (1 = enable, 0 = disable (default))"); -bool nv_drm_modeset_module_param = false; module_param_named(modeset, nv_drm_modeset_module_param, bool, 0400); #if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) MODULE_PARM_DESC( fbdev, "Create a framebuffer device (1 = enable, 0 = disable (default)) (EXPERIMENTAL)"); -bool nv_drm_fbdev_module_param = false; module_param_named(fbdev, nv_drm_fbdev_module_param, bool, 0400); #endif -void *nv_drm_calloc(size_t nmemb, size_t size) -{ - size_t total_size = nmemb * size; - // - // Check for overflow. - // - if ((nmemb != 0) && ((total_size / nmemb) != size)) - { - return NULL; - } - return kzalloc(nmemb * size, GFP_KERNEL); -} - -void nv_drm_free(void *ptr) -{ - if (IS_ERR(ptr)) { - return; - } - - kfree(ptr); -} - -char *nv_drm_asprintf(const char *fmt, ...) -{ - va_list ap; - char *p; - - va_start(ap, fmt); - p = kvasprintf(GFP_KERNEL, fmt, ap); - va_end(ap); - - return p; -} - -#if defined(NVCPU_X86) || defined(NVCPU_X86_64) - #define WRITE_COMBINE_FLUSH() asm volatile("sfence":::"memory") -#elif defined(NVCPU_PPC64LE) - #define WRITE_COMBINE_FLUSH() asm volatile("sync":::"memory") -#else - #define WRITE_COMBINE_FLUSH() mb() -#endif - -void nv_drm_write_combine_flush(void) -{ - WRITE_COMBINE_FLUSH(); -} - -int nv_drm_lock_user_pages(unsigned long address, - unsigned long pages_count, struct page ***pages) -{ - struct mm_struct *mm = current->mm; - struct page **user_pages; - int pages_pinned; - - user_pages = nv_drm_calloc(pages_count, sizeof(*user_pages)); - - if (user_pages == NULL) { - return -ENOMEM; - } - - nv_mmap_read_lock(mm); - - pages_pinned = NV_PIN_USER_PAGES(address, pages_count, FOLL_WRITE, - user_pages, NULL); - nv_mmap_read_unlock(mm); - - if (pages_pinned < 0 || (unsigned)pages_pinned < pages_count) { - goto failed; - } - - *pages = user_pages; - - return 0; - -failed: - - if (pages_pinned > 0) { - int i; - - for (i = 0; i < pages_pinned; i++) { - NV_UNPIN_USER_PAGE(user_pages[i]); - } - } - - nv_drm_free(user_pages); - - return (pages_pinned < 0) ? pages_pinned : -EINVAL; -} - -void nv_drm_unlock_user_pages(unsigned long pages_count, struct page **pages) -{ - unsigned long i; - - for (i = 0; i < pages_count; i++) { - set_page_dirty_lock(pages[i]); - NV_UNPIN_USER_PAGE(pages[i]); - } - - nv_drm_free(pages); -} - -void *nv_drm_vmap(struct page **pages, unsigned long pages_count) -{ - return vmap(pages, pages_count, VM_USERMAP, PAGE_KERNEL); -} - -void nv_drm_vunmap(void *address) -{ - vunmap(address); -} - -bool nv_drm_workthread_init(nv_drm_workthread *worker, const char *name) -{ - worker->shutting_down = false; - if (nv_kthread_q_init(&worker->q, name)) { - return false; - } - - spin_lock_init(&worker->lock); - - return true; -} - -void nv_drm_workthread_shutdown(nv_drm_workthread *worker) -{ - unsigned long flags; - - spin_lock_irqsave(&worker->lock, flags); - worker->shutting_down = true; - spin_unlock_irqrestore(&worker->lock, flags); - - nv_kthread_q_stop(&worker->q); -} - -void nv_drm_workthread_work_init(nv_drm_work *work, - void (*callback)(void *), - void *arg) -{ - nv_kthread_q_item_init(work, callback, arg); -} - -int nv_drm_workthread_add_work(nv_drm_workthread *worker, nv_drm_work *work) -{ - unsigned long flags; - int ret = 0; - - spin_lock_irqsave(&worker->lock, flags); - if (!worker->shutting_down) { - ret = nv_kthread_q_schedule_q_item(&worker->q, work); - } - spin_unlock_irqrestore(&worker->lock, flags); - - return ret; -} - -void nv_drm_timer_setup(nv_drm_timer *timer, void (*callback)(nv_drm_timer *nv_drm_timer)) -{ - nv_timer_setup(timer, callback); -} - -void nv_drm_mod_timer(nv_drm_timer *timer, unsigned long timeout_native) -{ - mod_timer(&timer->kernel_timer, timeout_native); -} - -unsigned long nv_drm_timer_now(void) -{ - return jiffies; -} - -unsigned long nv_drm_timeout_from_ms(NvU64 relative_timeout_ms) -{ - return jiffies + msecs_to_jiffies(relative_timeout_ms); -} - -bool nv_drm_del_timer_sync(nv_drm_timer *timer) -{ - if (del_timer_sync(&timer->kernel_timer)) { - return true; - } else { - return false; - } -} - -#if defined(NV_DRM_FENCE_AVAILABLE) -int nv_drm_create_sync_file(nv_dma_fence_t *fence) -{ -#if defined(NV_LINUX_SYNC_FILE_H_PRESENT) - struct sync_file *sync; - int fd = get_unused_fd_flags(O_CLOEXEC); - - if (fd < 0) { - return fd; - } - - /* sync_file_create() generates its own reference to the fence */ - sync = sync_file_create(fence); - - if (IS_ERR(sync)) { - put_unused_fd(fd); - return PTR_ERR(sync); - } - - fd_install(fd, sync->file); - - return fd; -#else /* defined(NV_LINUX_SYNC_FILE_H_PRESENT) */ - return -EINVAL; -#endif /* defined(NV_LINUX_SYNC_FILE_H_PRESENT) */ -} - -nv_dma_fence_t *nv_drm_sync_file_get_fence(int fd) -{ -#if defined(NV_SYNC_FILE_GET_FENCE_PRESENT) - return sync_file_get_fence(fd); -#else /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */ - return NULL; -#endif /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */ -} -#endif /* defined(NV_DRM_FENCE_AVAILABLE) */ - -void nv_drm_yield(void) -{ - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(1); -} - #endif /* NV_DRM_AVAILABLE */ /************************************************************************* diff --git a/kernel-open/nvidia-drm/nvidia-drm-modeset.c b/kernel-open/nvidia-drm/nvidia-drm-modeset.c index 85ea28778f..a8112825f8 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-modeset.c +++ b/kernel-open/nvidia-drm/nvidia-drm-modeset.c @@ -321,6 +321,24 @@ int nv_drm_atomic_check(struct drm_device *dev, { int ret = 0; +#if defined(NV_DRM_COLOR_MGMT_AVAILABLE) + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + int i; + + nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) { + /* + * if the color management changed on the crtc, we need to update the + * crtc's plane's CSC matrices, so add the crtc's planes to the commit + */ + if (crtc_state->color_mgmt_changed) { + if ((ret = drm_atomic_add_affected_planes(state, crtc)) != 0) { + goto done; + } + } + } +#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */ + if ((ret = drm_atomic_helper_check(dev, state)) != 0) { goto done; } diff --git a/kernel-open/nvidia-drm/nvidia-drm-os-interface.c b/kernel-open/nvidia-drm/nvidia-drm-os-interface.c new file mode 100644 index 0000000000..473004b57a --- /dev/null +++ b/kernel-open/nvidia-drm/nvidia-drm-os-interface.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "nvidia-drm-os-interface.h" + +#if defined(NV_DRM_AVAILABLE) + +#if defined(NV_LINUX_SYNC_FILE_H_PRESENT) +#include +#include +#endif + +#include +#include +#include + +#include "nv-mm.h" + +#if defined(NV_DRM_DRMP_H_PRESENT) +#include +#endif + +bool nv_drm_modeset_module_param = false; +bool nv_drm_fbdev_module_param = false; + +void *nv_drm_calloc(size_t nmemb, size_t size) +{ + size_t total_size = nmemb * size; + // + // Check for overflow. + // + if ((nmemb != 0) && ((total_size / nmemb) != size)) + { + return NULL; + } + return kzalloc(nmemb * size, GFP_KERNEL); +} + +void nv_drm_free(void *ptr) +{ + if (IS_ERR(ptr)) { + return; + } + + kfree(ptr); +} + +char *nv_drm_asprintf(const char *fmt, ...) +{ + va_list ap; + char *p; + + va_start(ap, fmt); + p = kvasprintf(GFP_KERNEL, fmt, ap); + va_end(ap); + + return p; +} + +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) + #define WRITE_COMBINE_FLUSH() asm volatile("sfence":::"memory") +#elif defined(NVCPU_PPC64LE) + #define WRITE_COMBINE_FLUSH() asm volatile("sync":::"memory") +#else + #define WRITE_COMBINE_FLUSH() mb() +#endif + +void nv_drm_write_combine_flush(void) +{ + WRITE_COMBINE_FLUSH(); +} + +int nv_drm_lock_user_pages(unsigned long address, + unsigned long pages_count, struct page ***pages) +{ + struct mm_struct *mm = current->mm; + struct page **user_pages; + int pages_pinned; + + user_pages = nv_drm_calloc(pages_count, sizeof(*user_pages)); + + if (user_pages == NULL) { + return -ENOMEM; + } + + nv_mmap_read_lock(mm); + + pages_pinned = NV_PIN_USER_PAGES(address, pages_count, FOLL_WRITE, + user_pages); + nv_mmap_read_unlock(mm); + + if (pages_pinned < 0 || (unsigned)pages_pinned < pages_count) { + goto failed; + } + + *pages = user_pages; + + return 0; + +failed: + + if (pages_pinned > 0) { + int i; + + for (i = 0; i < pages_pinned; i++) { + NV_UNPIN_USER_PAGE(user_pages[i]); + } + } + + nv_drm_free(user_pages); + + return (pages_pinned < 0) ? pages_pinned : -EINVAL; +} + +void nv_drm_unlock_user_pages(unsigned long pages_count, struct page **pages) +{ + unsigned long i; + + for (i = 0; i < pages_count; i++) { + set_page_dirty_lock(pages[i]); + NV_UNPIN_USER_PAGE(pages[i]); + } + + nv_drm_free(pages); +} + +/* + * linuxkpi vmap doesn't use the flags argument as it + * doesn't seem to be needed. Define VM_USERMAP to 0 + * to make errors go away + * + * vmap: sys/compat/linuxkpi/common/src/linux_compat.c + */ +#if defined(NV_BSD) +#define VM_USERMAP 0 +#endif + +void *nv_drm_vmap(struct page **pages, unsigned long pages_count) +{ + return vmap(pages, pages_count, VM_USERMAP, PAGE_KERNEL); +} + +void nv_drm_vunmap(void *address) +{ + vunmap(address); +} + +bool nv_drm_workthread_init(nv_drm_workthread *worker, const char *name) +{ + worker->shutting_down = false; + if (nv_kthread_q_init(&worker->q, name)) { + return false; + } + + spin_lock_init(&worker->lock); + + return true; +} + +void nv_drm_workthread_shutdown(nv_drm_workthread *worker) +{ + unsigned long flags; + + spin_lock_irqsave(&worker->lock, flags); + worker->shutting_down = true; + spin_unlock_irqrestore(&worker->lock, flags); + + nv_kthread_q_stop(&worker->q); +} + +void nv_drm_workthread_work_init(nv_drm_work *work, + void (*callback)(void *), + void *arg) +{ + nv_kthread_q_item_init(work, callback, arg); +} + +int nv_drm_workthread_add_work(nv_drm_workthread *worker, nv_drm_work *work) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&worker->lock, flags); + if (!worker->shutting_down) { + ret = nv_kthread_q_schedule_q_item(&worker->q, work); + } + spin_unlock_irqrestore(&worker->lock, flags); + + return ret; +} + +void nv_drm_timer_setup(nv_drm_timer *timer, void (*callback)(nv_drm_timer *nv_drm_timer)) +{ + nv_timer_setup(timer, callback); +} + +void nv_drm_mod_timer(nv_drm_timer *timer, unsigned long timeout_native) +{ + mod_timer(&timer->kernel_timer, timeout_native); +} + +unsigned long nv_drm_timer_now(void) +{ + return jiffies; +} + +unsigned long nv_drm_timeout_from_ms(NvU64 relative_timeout_ms) +{ + return jiffies + msecs_to_jiffies(relative_timeout_ms); +} + +bool nv_drm_del_timer_sync(nv_drm_timer *timer) +{ + if (del_timer_sync(&timer->kernel_timer)) { + return true; + } else { + return false; + } +} + +#if defined(NV_DRM_FENCE_AVAILABLE) +int nv_drm_create_sync_file(nv_dma_fence_t *fence) +{ +#if defined(NV_LINUX_SYNC_FILE_H_PRESENT) + struct sync_file *sync; + int fd = get_unused_fd_flags(O_CLOEXEC); + + if (fd < 0) { + return fd; + } + + /* sync_file_create() generates its own reference to the fence */ + sync = sync_file_create(fence); + + if (IS_ERR(sync)) { + put_unused_fd(fd); + return PTR_ERR(sync); + } + + fd_install(fd, sync->file); + + return fd; +#else /* defined(NV_LINUX_SYNC_FILE_H_PRESENT) */ + return -EINVAL; +#endif /* defined(NV_LINUX_SYNC_FILE_H_PRESENT) */ +} + +nv_dma_fence_t *nv_drm_sync_file_get_fence(int fd) +{ +#if defined(NV_SYNC_FILE_GET_FENCE_PRESENT) + return sync_file_get_fence(fd); +#else /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */ + return NULL; +#endif /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */ +} +#endif /* defined(NV_DRM_FENCE_AVAILABLE) */ + +void nv_drm_yield(void) +{ + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(1); +} + +#endif /* NV_DRM_AVAILABLE */ diff --git a/kernel-open/nvidia-drm/nvidia-drm-os-interface.h b/kernel-open/nvidia-drm/nvidia-drm-os-interface.h index 51c7a7fda3..6f8cfea917 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-os-interface.h +++ b/kernel-open/nvidia-drm/nvidia-drm-os-interface.h @@ -33,7 +33,7 @@ #include "nvidia-dma-fence-helper.h" #endif -#if defined(NV_LINUX) +#if defined(NV_LINUX) || defined(NV_BSD) #include "nv-kthread-q.h" #include "linux/spinlock.h" @@ -45,18 +45,18 @@ typedef struct nv_drm_workthread { typedef nv_kthread_q_item_t nv_drm_work; -#else /* defined(NV_LINUX) */ +#else #error "Need to define deferred work primitives for this OS" -#endif /* else defined(NV_LINUX) */ +#endif -#if defined(NV_LINUX) +#if defined(NV_LINUX) || defined(NV_BSD) #include "nv-timer.h" typedef struct nv_timer nv_drm_timer; -#else /* defined(NV_LINUX) */ +#else #error "Need to define kernel timer callback primitives for this OS" -#endif /* else defined(NV_LINUX) */ +#endif #if defined(NV_DRM_FBDEV_GENERIC_SETUP_PRESENT) && defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT) #define NV_DRM_FBDEV_GENERIC_AVAILABLE diff --git a/kernel-open/nvidia-drm/nvidia-drm-priv.h b/kernel-open/nvidia-drm/nvidia-drm-priv.h index 253155f6d4..c9ce727ac5 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-priv.h +++ b/kernel-open/nvidia-drm/nvidia-drm-priv.h @@ -126,6 +126,7 @@ struct nv_drm_device { NvU64 modifiers[6 /* block linear */ + 1 /* linear */ + 1 /* terminator */]; #endif + struct delayed_work hotplug_event_work; atomic_t enable_event_handling; /** diff --git a/kernel-open/nvidia-drm/nvidia-drm-sources.mk b/kernel-open/nvidia-drm/nvidia-drm-sources.mk new file mode 100644 index 0000000000..9eea228577 --- /dev/null +++ b/kernel-open/nvidia-drm/nvidia-drm-sources.mk @@ -0,0 +1,131 @@ +########################################################################### +# Kbuild fragment for nvidia-drm.ko +########################################################################### + +# +# Define NVIDIA_DRM_SOURCES +# + +NVIDIA_DRM_SOURCES = +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-drv.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-utils.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-crtc.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-encoder.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-connector.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fb.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-modeset.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fence.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-helper.c +NVIDIA_DRM_SOURCES += nvidia-drm/nv-kthread-q.c +NVIDIA_DRM_SOURCES += nvidia-drm/nv-pci-table.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-nvkms-memory.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-user-memory.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-dma-buf.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-format.c +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-os-interface.c + +# +# Register the conftests needed by nvidia-drm.ko +# + +NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available +NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_atomic_available +NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_inc +NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_dec_and_test +NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_alpha_blending_available +NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_fd_to_handle +NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_handle_to_fd + +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group +NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages_remote +NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages +NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages_remote +NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_lookup +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_state_ref_counting +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_driver_has_gem_prime_res_obj +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_connector_dpms +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_funcs_have_mode_in_name +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_has_vrr_capable_property +NV_CONFTEST_FUNCTION_COMPILE_TESTS += vmf_insert_pfn +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_framebuffer_get +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_put +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_format_num_planes +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_for_each_possible_encoder +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_rotation_available +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_vma_offset_exact_lookup_locked +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_put_unlocked +NV_CONFTEST_FUNCTION_COMPILE_TESTS += nvhost_dma_fence_unpack +NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first +NV_CONFTEST_FUNCTION_COMPILE_TESTS += timer_setup +NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_fence_set_error +NV_CONFTEST_FUNCTION_COMPILE_TESTS += fence_set_error +NV_CONFTEST_FUNCTION_COMPILE_TESTS += sync_file_get_fence +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_fbdev_generic_setup +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_attach_hdr_output_metadata_property +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_helper_crtc_enable_color_mgmt +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_crtc_enable_color_mgmt +NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_legacy_gamma_set + +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_present +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_bus_type +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_get_irq +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_get_name +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_device_list +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_legacy_dev_list +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_set_busid +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_connectors_changed +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_init_function_args +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_helper_mode_fill_fb_struct +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_drop_has_from_release_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_unload_has_int_return_type +NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_has_address +NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_crtc_destroy_state_has_crtc_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_plane_destroy_state_has_plane_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_object_find_has_file_priv_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += dma_buf_owner +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_list_iter +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_swap_state_has_stall_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_prime_flag_present +NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_gem_object_has_resv +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_async_flip +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_pageflip_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_vrr_enabled +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_format_modifiers_present +NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_node_is_allowed_has_tag_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_offset_node_has_readonly +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_display_mode_has_vrefresh +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_master_set_has_int_return_type +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_gem_free_object +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_prime_pages_to_sg_has_drm_device_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_gem_prime_callbacks +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_atomic_check_has_atomic_state_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_gem_object_vmap_has_map_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_plane_atomic_check_has_atomic_state_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_device_has_pdev +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_no_vblank +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_config_has_allow_fb_modifiers +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_has_hdr_output_metadata +NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_add_fence +NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences +NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_has_override_edid +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_has_leases +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_file_get_master +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_modeset_lock_all_end +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put +NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy +NV_CONFTEST_TYPE_COMPILE_TESTS += fence_ops_use_64bit_seqno +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers_has_driver_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index b8cc5e23d6..892fa4dab5 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -2,30 +2,16 @@ # Kbuild fragment for nvidia-drm.ko ########################################################################### +# Get our source file list and conftest list from the common file +include $(src)/nvidia-drm/nvidia-drm-sources.mk + +# Linux-specific sources +NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-linux.c + # # Define NVIDIA_DRM_{SOURCES,OBJECTS} # -NVIDIA_DRM_SOURCES = -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-drv.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-utils.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-crtc.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-encoder.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-connector.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fb.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-modeset.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-fence.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-linux.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-helper.c -NVIDIA_DRM_SOURCES += nvidia-drm/nv-kthread-q.c -NVIDIA_DRM_SOURCES += nvidia-drm/nv-pci-table.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-nvkms-memory.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-user-memory.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-gem-dma-buf.c -NVIDIA_DRM_SOURCES += nvidia-drm/nvidia-drm-format.c - NVIDIA_DRM_OBJECTS = $(patsubst %.c,%.o,$(NVIDIA_DRM_SOURCES)) obj-m += nvidia-drm.o @@ -44,107 +30,4 @@ NVIDIA_DRM_CFLAGS += -UDEBUG -U_DEBUG -DNDEBUG -DNV_BUILD_MODULE_INSTANCES=0 $(call ASSIGN_PER_OBJ_CFLAGS, $(NVIDIA_DRM_OBJECTS), $(NVIDIA_DRM_CFLAGS)) -# -# Register the conftests needed by nvidia-drm.ko -# - NV_OBJECTS_DEPEND_ON_CONFTEST += $(NVIDIA_DRM_OBJECTS) - -NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available -NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_atomic_available -NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_inc -NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_dec_and_test -NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_alpha_blending_available -NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_fd_to_handle -NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_handle_to_fd - -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group -NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages_remote -NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_user_pages -NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages_remote -NV_CONFTEST_FUNCTION_COMPILE_TESTS += pin_user_pages -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_lookup -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_state_ref_counting -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_driver_has_gem_prime_res_obj -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_connector_dpms -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_funcs_have_mode_in_name -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_has_vrr_capable_property -NV_CONFTEST_FUNCTION_COMPILE_TESTS += vmf_insert_pfn -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_framebuffer_get -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_put -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_format_num_planes -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_for_each_possible_encoder -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_rotation_available -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_vma_offset_exact_lookup_locked -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_put_unlocked -NV_CONFTEST_FUNCTION_COMPILE_TESTS += nvhost_dma_fence_unpack -NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first -NV_CONFTEST_FUNCTION_COMPILE_TESTS += timer_setup -NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_fence_set_error -NV_CONFTEST_FUNCTION_COMPILE_TESTS += fence_set_error -NV_CONFTEST_FUNCTION_COMPILE_TESTS += sync_file_get_fence -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_fbdev_generic_setup -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_connector_attach_hdr_output_metadata_property -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_helper_crtc_enable_color_mgmt -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_crtc_enable_color_mgmt -NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_atomic_helper_legacy_gamma_set - -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_present -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_bus_type -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_get_irq -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_get_name -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_device_list -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_legacy_dev_list -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_set_busid -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_connectors_changed -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_init_function_args -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_helper_mode_fill_fb_struct -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_drop_has_from_release_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_unload_has_int_return_type -NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_has_address -NV_CONFTEST_TYPE_COMPILE_TESTS += vm_ops_fault_removed_vma_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_crtc_destroy_state_has_crtc_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_plane_destroy_state_has_plane_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_object_find_has_file_priv_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += dma_buf_owner -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_list_iter -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_atomic_helper_swap_state_has_stall_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_prime_flag_present -NV_CONFTEST_TYPE_COMPILE_TESTS += vm_fault_t -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_gem_object_has_resv -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_async_flip -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_pageflip_flags -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_vrr_enabled -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_format_modifiers_present -NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_node_is_allowed_has_tag_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_vma_offset_node_has_readonly -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_display_mode_has_vrefresh -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_master_set_has_int_return_type -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_gem_free_object -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_prime_pages_to_sg_has_drm_device_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_gem_prime_callbacks -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_atomic_check_has_atomic_state_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_gem_object_vmap_has_map_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_plane_atomic_check_has_atomic_state_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_device_has_pdev -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_no_vblank -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_config_has_allow_fb_modifiers -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_has_hdr_output_metadata -NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_add_fence -NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences -NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_has_override_edid -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_master_has_leases -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_file_get_master -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_modeset_lock_all_end -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put -NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy -NV_CONFTEST_TYPE_COMPILE_TESTS += fence_ops_use_64bit_seqno -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers_has_driver_arg -NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg diff --git a/kernel-open/nvidia-drm/nvidia-drm.c b/kernel-open/nvidia-drm/nvidia-drm.c index a191ccf7c6..e42496a029 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.c +++ b/kernel-open/nvidia-drm/nvidia-drm.c @@ -45,6 +45,7 @@ int nv_drm_init(void) return -EINVAL; } + nvKms->setSuspendResumeCallback(nv_drm_suspend_resume); return nv_drm_probe_devices(); #else return 0; @@ -54,6 +55,7 @@ int nv_drm_init(void) void nv_drm_exit(void) { #if defined(NV_DRM_AVAILABLE) + nvKms->setSuspendResumeCallback(NULL); nv_drm_remove_devices(); #endif } diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index a1ab88577b..db6f059b60 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -35,12 +35,13 @@ #include #include #include +#include +#include #include #include "nvstatus.h" -#include "nv-register-module.h" #include "nv-modeset-interface.h" #include "nv-kref.h" @@ -53,6 +54,7 @@ #include "nv-kthread-q.h" #include "nv-time.h" #include "nv-lock.h" +#include "nv-chardev-numbers.h" #if !defined(CONFIG_RETPOLINE) #include "nv-retpoline.h" @@ -74,6 +76,12 @@ module_param_named(disable_vrr_memclk_switch, disable_vrr_memclk_switch, bool, 0 static bool hdmi_deepcolor = false; module_param_named(hdmi_deepcolor, hdmi_deepcolor, bool, 0400); +static bool vblank_sem_control = false; +module_param_named(vblank_sem_control, vblank_sem_control, bool, 0400); + +static bool opportunistic_display_sync = true; +module_param_named(opportunistic_display_sync, opportunistic_display_sync, bool, 0400); + /* These parameters are used for fault injection tests. Normally the defaults * should be used. */ MODULE_PARM_DESC(fail_malloc, "Fail the Nth call to nvkms_alloc"); @@ -117,6 +125,16 @@ NvBool nvkms_hdmi_deepcolor(void) return hdmi_deepcolor; } +NvBool nvkms_vblank_sem_control(void) +{ + return vblank_sem_control; +} + +NvBool nvkms_opportunistic_display_sync(void) +{ + return opportunistic_display_sync; +} + #define NVKMS_SYNCPT_STUBS_NEEDED /************************************************************************* @@ -482,6 +500,7 @@ nvkms_event_queue_changed(nvkms_per_open_handle_t *pOpenKernel, static void nvkms_suspend(NvU32 gpuId) { if (gpuId == 0) { + nvKmsKapiSuspendResume(NV_TRUE /* suspend */); nvkms_write_lock_pm_lock(); } @@ -498,6 +517,7 @@ static void nvkms_resume(NvU32 gpuId) if (gpuId == 0) { nvkms_write_unlock_pm_lock(); + nvKmsKapiSuspendResume(NV_FALSE /* suspend */); } } @@ -827,49 +847,6 @@ void nvkms_free_timer(nvkms_timer_handle_t *handle) timer->cancel = NV_TRUE; } -void* nvkms_get_per_open_data(int fd) -{ - struct file *filp = fget(fd); - struct nvkms_per_open *popen = NULL; - dev_t rdev = 0; - void *data = NULL; - - if (filp == NULL) { - return NULL; - } - - if (filp->f_inode == NULL) { - goto done; - } - rdev = filp->f_inode->i_rdev; - - if ((MAJOR(rdev) != NVKMS_MAJOR_DEVICE_NUMBER) || - (MINOR(rdev) != NVKMS_MINOR_DEVICE_NUMBER)) { - goto done; - } - - popen = filp->private_data; - if (popen == NULL) { - goto done; - } - - data = popen->data; - -done: - /* - * fget() incremented the struct file's reference count, which - * needs to be balanced with a call to fput(). It is safe to - * decrement the reference count before returning - * filp->private_data because core NVKMS is currently holding the - * nvkms_lock, which prevents the nvkms_close() => nvKmsClose() - * call chain from freeing the file out from under the caller of - * nvkms_get_per_open_data(). - */ - fput(filp); - - return data; -} - NvBool nvkms_fd_is_nvidia_chardev(int fd) { struct file *filp = fget(fd); @@ -1621,6 +1598,12 @@ static int nvkms_ioctl(struct inode *inode, struct file *filp, return status; } +static long nvkms_unlocked_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + return nvkms_ioctl(filp->f_inode, filp, cmd, arg); +} + static unsigned int nvkms_poll(struct file *filp, poll_table *wait) { unsigned int mask = 0; @@ -1648,17 +1631,73 @@ static unsigned int nvkms_poll(struct file *filp, poll_table *wait) * Module loading support code. *************************************************************************/ -static nvidia_module_t nvidia_modeset_module = { +#define NVKMS_RDEV (MKDEV(NV_MAJOR_DEVICE_NUMBER, \ + NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE)) + +static struct file_operations nvkms_fops = { .owner = THIS_MODULE, - .module_name = "nvidia-modeset", - .instance = 1, /* minor number: 255-1=254 */ - .open = nvkms_open, - .close = nvkms_close, - .mmap = nvkms_mmap, - .ioctl = nvkms_ioctl, .poll = nvkms_poll, + .unlocked_ioctl = nvkms_unlocked_ioctl, +#if NVCPU_IS_X86_64 || NVCPU_IS_AARCH64 + .compat_ioctl = nvkms_unlocked_ioctl, +#endif + .mmap = nvkms_mmap, + .open = nvkms_open, + .release = nvkms_close, }; +static struct cdev nvkms_device_cdev; + +static int __init nvkms_register_chrdev(void) +{ + int ret; + + ret = register_chrdev_region(NVKMS_RDEV, 1, "nvidia-modeset"); + if (ret < 0) { + return ret; + } + + cdev_init(&nvkms_device_cdev, &nvkms_fops); + ret = cdev_add(&nvkms_device_cdev, NVKMS_RDEV, 1); + if (ret < 0) { + unregister_chrdev_region(NVKMS_RDEV, 1); + return ret; + } + + return ret; +} + +static void nvkms_unregister_chrdev(void) +{ + cdev_del(&nvkms_device_cdev); + unregister_chrdev_region(NVKMS_RDEV, 1); +} + +void* nvkms_get_per_open_data(int fd) +{ + struct file *filp = fget(fd); + void *data = NULL; + + if (filp) { + if (filp->f_op == &nvkms_fops && filp->private_data) { + struct nvkms_per_open *popen = filp->private_data; + data = popen->data; + } + + /* + * fget() incremented the struct file's reference count, which needs to + * be balanced with a call to fput(). It is safe to decrement the + * reference count before returning filp->private_data because core + * NVKMS is currently holding the nvkms_lock, which prevents the + * nvkms_close() => nvKmsClose() call chain from freeing the file out + * from under the caller of nvkms_get_per_open_data(). + */ + fput(filp); + } + + return data; +} + static int __init nvkms_init(void) { int ret; @@ -1689,10 +1728,9 @@ static int __init nvkms_init(void) INIT_LIST_HEAD(&nvkms_timers.list); spin_lock_init(&nvkms_timers.lock); - ret = nvidia_register_module(&nvidia_modeset_module); - + ret = nvkms_register_chrdev(); if (ret != 0) { - goto fail_register_module; + goto fail_register_chrdev; } down(&nvkms_lock); @@ -1711,8 +1749,8 @@ static int __init nvkms_init(void) return 0; fail_module_load: - nvidia_unregister_module(&nvidia_modeset_module); -fail_register_module: + nvkms_unregister_chrdev(); +fail_register_chrdev: nv_kthread_q_stop(&nvkms_deferred_close_kthread_q); fail_deferred_close_kthread: nv_kthread_q_stop(&nvkms_kthread_q); @@ -1776,7 +1814,7 @@ static void __exit nvkms_exit(void) nv_kthread_q_stop(&nvkms_deferred_close_kthread_q); nv_kthread_q_stop(&nvkms_kthread_q); - nvidia_unregister_module(&nvidia_modeset_module); + nvkms_unregister_chrdev(); nvkms_free_rm(); if (malloc_verbose) { diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h index 9f1a2f5428..af8d501417 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h +++ b/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h @@ -100,6 +100,8 @@ NvBool nvkms_output_rounding_fix(void); NvBool nvkms_disable_hdmi_frl(void); NvBool nvkms_disable_vrr_memclk_switch(void); NvBool nvkms_hdmi_deepcolor(void); +NvBool nvkms_vblank_sem_control(void); +NvBool nvkms_opportunistic_display_sync(void); void nvkms_call_rm (void *ops); void* nvkms_alloc (size_t size, diff --git a/kernel-open/nvidia-modeset/nvkms.h b/kernel-open/nvidia-modeset/nvkms.h index b64fbb098e..25e4923b63 100644 --- a/kernel-open/nvidia-modeset/nvkms.h +++ b/kernel-open/nvidia-modeset/nvkms.h @@ -103,6 +103,8 @@ NvBool nvKmsKapiGetFunctionsTableInternal struct NvKmsKapiFunctionsTable *funcsTable ); +void nvKmsKapiSuspendResume(NvBool suspend); + NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness); NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness); diff --git a/kernel-open/nvidia-peermem/nvidia-peermem.c b/kernel-open/nvidia-peermem/nvidia-peermem.c index e1d5f37494..bb462d612c 100644 --- a/kernel-open/nvidia-peermem/nvidia-peermem.c +++ b/kernel-open/nvidia-peermem/nvidia-peermem.c @@ -1,20 +1,25 @@ -/* SPDX-License-Identifier: Linux-OpenIB */ /* * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF @@ -43,7 +48,9 @@ MODULE_AUTHOR("Yishai Hadas"); MODULE_DESCRIPTION("NVIDIA GPU memory plug-in"); -MODULE_LICENSE("Linux-OpenIB"); + +MODULE_LICENSE("Dual BSD/GPL"); + MODULE_VERSION(DRV_VERSION); enum { NV_MEM_PEERDIRECT_SUPPORT_DEFAULT = 0, @@ -53,7 +60,13 @@ static int peerdirect_support = NV_MEM_PEERDIRECT_SUPPORT_DEFAULT; module_param(peerdirect_support, int, S_IRUGO); MODULE_PARM_DESC(peerdirect_support, "Set level of support for Peer-direct, 0 [default] or 1 [legacy, for example MLNX_OFED 4.9 LTS]"); -#define peer_err(FMT, ARGS...) printk(KERN_ERR "nvidia-peermem" " %s:%d " FMT, __FUNCTION__, __LINE__, ## ARGS) + +#define peer_err(FMT, ARGS...) printk(KERN_ERR "nvidia-peermem" " %s:%d ERROR " FMT, __FUNCTION__, __LINE__, ## ARGS) +#ifdef NV_MEM_DEBUG +#define peer_trace(FMT, ARGS...) printk(KERN_DEBUG "nvidia-peermem" " %s:%d TRACE " FMT, __FUNCTION__, __LINE__, ## ARGS) +#else +#define peer_trace(FMT, ARGS...) do {} while (0) +#endif #if defined(NV_MLNX_IB_PEER_MEM_SYMBOLS_PRESENT) @@ -74,7 +87,10 @@ invalidate_peer_memory mem_invalidate_callback; static void *reg_handle = NULL; static void *reg_handle_nc = NULL; +#define NV_MEM_CONTEXT_MAGIC ((u64)0xF1F4F1D0FEF0DAD0ULL) + struct nv_mem_context { + u64 pad1; struct nvidia_p2p_page_table *page_table; struct nvidia_p2p_dma_mapping *dma_mapping; u64 core_context; @@ -86,8 +102,22 @@ struct nv_mem_context { struct task_struct *callback_task; int sg_allocated; struct sg_table sg_head; + u64 pad2; }; +#define NV_MEM_CONTEXT_CHECK_OK(MC) ({ \ + struct nv_mem_context *mc = (MC); \ + int rc = ((0 != mc) && \ + (READ_ONCE(mc->pad1) == NV_MEM_CONTEXT_MAGIC) && \ + (READ_ONCE(mc->pad2) == NV_MEM_CONTEXT_MAGIC)); \ + if (!rc) { \ + peer_trace("invalid nv_mem_context=%px pad1=%016llx pad2=%016llx\n", \ + mc, \ + mc?mc->pad1:0, \ + mc?mc->pad2:0); \ + } \ + rc; \ +}) static void nv_get_p2p_free_callback(void *data) { @@ -97,8 +127,9 @@ static void nv_get_p2p_free_callback(void *data) struct nvidia_p2p_dma_mapping *dma_mapping = NULL; __module_get(THIS_MODULE); - if (!nv_mem_context) { - peer_err("nv_get_p2p_free_callback -- invalid nv_mem_context\n"); + + if (!NV_MEM_CONTEXT_CHECK_OK(nv_mem_context)) { + peer_err("detected invalid context, skipping further processing\n"); goto out; } @@ -169,9 +200,11 @@ static int nv_mem_acquire(unsigned long addr, size_t size, void *peer_mem_privat /* Error case handled as not mine */ return 0; + nv_mem_context->pad1 = NV_MEM_CONTEXT_MAGIC; nv_mem_context->page_virt_start = addr & GPU_PAGE_MASK; nv_mem_context->page_virt_end = (addr + size + GPU_PAGE_SIZE - 1) & GPU_PAGE_MASK; nv_mem_context->mapped_size = nv_mem_context->page_virt_end - nv_mem_context->page_virt_start; + nv_mem_context->pad2 = NV_MEM_CONTEXT_MAGIC; ret = nvidia_p2p_get_pages(0, 0, nv_mem_context->page_virt_start, nv_mem_context->mapped_size, &nv_mem_context->page_table, nv_mem_dummy_callback, nv_mem_context); @@ -195,6 +228,7 @@ static int nv_mem_acquire(unsigned long addr, size_t size, void *peer_mem_privat return 1; err: + memset(nv_mem_context, 0, sizeof(*nv_mem_context)); kfree(nv_mem_context); /* Error case handled as not mine */ @@ -347,6 +381,7 @@ static void nv_mem_release(void *context) sg_free_table(&nv_mem_context->sg_head); nv_mem_context->sg_allocated = 0; } + memset(nv_mem_context, 0, sizeof(*nv_mem_context)); kfree(nv_mem_context); module_put(THIS_MODULE); return; diff --git a/kernel-open/nvidia-uvm/ctrl2080mc.h b/kernel-open/nvidia-uvm/ctrl2080mc.h index f41af44f6d..7ea90adc66 100644 --- a/kernel-open/nvidia-uvm/ctrl2080mc.h +++ b/kernel-open/nvidia-uvm/ctrl2080mc.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2013-2022 NVIDIA Corporation + Copyright (c) 2013-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to diff --git a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild index 8da0c7efe9..683aece10d 100644 --- a/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild +++ b/kernel-open/nvidia-uvm/nvidia-uvm.Kbuild @@ -82,12 +82,12 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_uc NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64 NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get NV_CONFTEST_FUNCTION_COMPILE_TESTS += mm_pasid_drop -NV_CONFTEST_FUNCTION_COMPILE_TESTS += migrate_vma_setup NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmgrab NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_sva_bind_device_has_drvdata_arg NV_CONFTEST_FUNCTION_COMPILE_TESTS += vm_fault_to_errno NV_CONFTEST_FUNCTION_COMPILE_TESTS += find_next_bit_wrap +NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_is_dma_domain NV_CONFTEST_TYPE_COMPILE_TESTS += backing_dev_info NV_CONFTEST_TYPE_COMPILE_TESTS += mm_context_t @@ -116,3 +116,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += mpol_preferred_many_present NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_interval_notifier NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup diff --git a/kernel-open/nvidia-uvm/nvstatus.c b/kernel-open/nvidia-uvm/nvstatus.c index 92c5d7af8f..c01f4ea004 100644 --- a/kernel-open/nvidia-uvm/nvstatus.c +++ b/kernel-open/nvidia-uvm/nvstatus.c @@ -25,7 +25,8 @@ #if !defined(NV_PRINTF_STRING_SECTION) #if defined(NVRM) && NVOS_IS_LIBOS -#define NV_PRINTF_STRING_SECTION __attribute__ ((section (".logging"))) +#include "libos_log.h" +#define NV_PRINTF_STRING_SECTION LIBOS_SECTION_LOGGING #else // defined(NVRM) && NVOS_IS_LIBOS #define NV_PRINTF_STRING_SECTION #endif // defined(NVRM) && NVOS_IS_LIBOS @@ -33,7 +34,7 @@ /* * Include nvstatuscodes.h twice. Once for creating constant strings in the - * the NV_PRINTF_STRING_SECTION section of the ececutable, and once to build + * the NV_PRINTF_STRING_SECTION section of the executable, and once to build * the g_StatusCodeList table. */ #undef NV_STATUS_CODE diff --git a/kernel-open/nvidia-uvm/uvm.c b/kernel-open/nvidia-uvm/uvm.c index 6f95f17cb4..f0f70e39c1 100644 --- a/kernel-open/nvidia-uvm/uvm.c +++ b/kernel-open/nvidia-uvm/uvm.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -1053,7 +1053,7 @@ NV_STATUS uvm_test_register_unload_state_buffer(UVM_TEST_REGISTER_UNLOAD_STATE_B // are not used because unload_state_buf may be a managed memory pointer and // therefore a locking assertion from the CPU fault handler could be fired. nv_mmap_read_lock(current->mm); - ret = NV_PIN_USER_PAGES(params->unload_state_buf, 1, FOLL_WRITE, &page, NULL); + ret = NV_PIN_USER_PAGES(params->unload_state_buf, 1, FOLL_WRITE, &page); nv_mmap_read_unlock(current->mm); if (ret < 0) diff --git a/kernel-open/nvidia-uvm/uvm.h b/kernel-open/nvidia-uvm/uvm.h index c1b54b9ed6..04a075f51a 100644 --- a/kernel-open/nvidia-uvm/uvm.h +++ b/kernel-open/nvidia-uvm/uvm.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2013-2022 NVIDIA Corporation + Copyright (c) 2013-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -45,16 +45,20 @@ // #endif // 3) Do the same thing for the function definition, and for any structs that // are taken as arguments to these functions. -// 4) Let this change propagate over to cuda_a, so that the CUDA driver can -// start using the new API by bumping up the API version number its using. -// This can be found in gpgpu/cuda/cuda.nvmk. -// 5) Once the cuda_a changes have made it back into chips_a, remove the old API -// declaration, definition, and any old structs that were in use. +// 4) Let this change propagate over to cuda_a and dev_a, so that the CUDA and +// nvidia-cfg libraries can start using the new API by bumping up the API +// version number it's using. +// Places where UVM_API_REVISION is defined are: +// drivers/gpgpu/cuda/cuda.nvmk (cuda_a) +// drivers/setup/linux/nvidia-cfg/makefile.nvmk (dev_a) +// 5) Once the dev_a and cuda_a changes have made it back into chips_a, +// remove the old API declaration, definition, and any old structs that were +// in use. #ifndef _UVM_H_ #define _UVM_H_ -#define UVM_API_LATEST_REVISION 8 +#define UVM_API_LATEST_REVISION 9 #if !defined(UVM_API_REVISION) #error "please define UVM_API_REVISION macro to a desired version number or UVM_API_LATEST_REVISION macro" @@ -180,12 +184,8 @@ NV_STATUS UvmSetDriverVersion(NvU32 major, NvU32 changelist); // because it is not very informative. // //------------------------------------------------------------------------------ -#if UVM_API_REV_IS_AT_MOST(4) -NV_STATUS UvmInitialize(UvmFileDescriptor fd); -#else NV_STATUS UvmInitialize(UvmFileDescriptor fd, NvU64 flags); -#endif //------------------------------------------------------------------------------ // UvmDeinitialize @@ -329,7 +329,11 @@ NV_STATUS UvmIsPageableMemoryAccessSupportedOnGpu(const NvProcessorUuid *gpuUuid // // Arguments: // gpuUuid: (INPUT) -// UUID of the GPU to register. +// UUID of the physical GPU to register. +// +// platformParams: (INPUT) +// User handles identifying the GPU partition to register. +// This should be NULL if the GPU is not SMC capable or SMC enabled. // // Error codes: // NV_ERR_NO_MEMORY: @@ -364,27 +368,31 @@ NV_STATUS UvmIsPageableMemoryAccessSupportedOnGpu(const NvProcessorUuid *gpuUuid // OS state required to register the GPU is not present. // // NV_ERR_INVALID_STATE: -// OS state required to register the GPU is malformed. +// OS state required to register the GPU is malformed, or the partition +// identified by the user handles or its configuration changed. // // NV_ERR_GENERIC: // Unexpected error. We try hard to avoid returning this error code, // because it is not very informative. // //------------------------------------------------------------------------------ +#if UVM_API_REV_IS_AT_MOST(8) NV_STATUS UvmRegisterGpu(const NvProcessorUuid *gpuUuid); +#else +NV_STATUS UvmRegisterGpu(const NvProcessorUuid *gpuUuid, + const UvmGpuPlatformParams *platformParams); +#endif +#if UVM_API_REV_IS_AT_MOST(8) //------------------------------------------------------------------------------ // UvmRegisterGpuSmc // // The same as UvmRegisterGpu, but takes additional parameters to specify the // GPU partition being registered if SMC is enabled. // -// TODO: Bug 2844714: Merge UvmRegisterGpuSmc() with UvmRegisterGpu() once -// the initial SMC support is in place. -// // Arguments: // gpuUuid: (INPUT) -// UUID of the parent GPU of the SMC partition to register. +// UUID of the physical GPU of the SMC partition to register. // // platformParams: (INPUT) // User handles identifying the partition to register. @@ -397,6 +405,7 @@ NV_STATUS UvmRegisterGpu(const NvProcessorUuid *gpuUuid); // NV_STATUS UvmRegisterGpuSmc(const NvProcessorUuid *gpuUuid, const UvmGpuPlatformParams *platformParams); +#endif //------------------------------------------------------------------------------ // UvmUnregisterGpu @@ -1416,8 +1425,7 @@ NV_STATUS UvmAllocSemaphorePool(void *base, // // preferredCpuMemoryNode: (INPUT) // Preferred CPU NUMA memory node used if the destination processor is -// the CPU. This argument is ignored if the given virtual address range -// corresponds to managed memory. +// the CPU. // // Error codes: // NV_ERR_INVALID_ADDRESS: @@ -1456,16 +1464,10 @@ NV_STATUS UvmAllocSemaphorePool(void *base, // pages were associated with a non-migratable range group. // //------------------------------------------------------------------------------ -#if UVM_API_REV_IS_AT_MOST(5) -NV_STATUS UvmMigrate(void *base, - NvLength length, - const NvProcessorUuid *destinationUuid); -#else NV_STATUS UvmMigrate(void *base, NvLength length, const NvProcessorUuid *destinationUuid, NvS32 preferredCpuMemoryNode); -#endif //------------------------------------------------------------------------------ // UvmMigrateAsync @@ -1547,20 +1549,12 @@ NV_STATUS UvmMigrate(void *base, // pages were associated with a non-migratable range group. // //------------------------------------------------------------------------------ -#if UVM_API_REV_IS_AT_MOST(5) -NV_STATUS UvmMigrateAsync(void *base, - NvLength length, - const NvProcessorUuid *destinationUuid, - void *semaphoreAddress, - NvU32 semaphorePayload); -#else NV_STATUS UvmMigrateAsync(void *base, NvLength length, const NvProcessorUuid *destinationUuid, NvS32 preferredCpuMemoryNode, void *semaphoreAddress, NvU32 semaphorePayload); -#endif //------------------------------------------------------------------------------ // UvmMigrateRangeGroup @@ -1568,9 +1562,7 @@ NV_STATUS UvmMigrateAsync(void *base, // Migrates the backing of all virtual address ranges associated with the given // range group to the specified destination processor. The behavior of this API // is equivalent to calling UvmMigrate on each VA range associated with this -// range group. The value for the preferredCpuMemoryNode is irrelevant in this -// case as it only applies to migrations of pageable address, which cannot be -// used to create range groups. +// range group. // // Any errors encountered during migration are returned immediately. No attempt // is made to migrate the remaining unmigrated ranges and the ranges that are @@ -2303,13 +2295,10 @@ NV_STATUS UvmDisableReadDuplication(void *base, // preferredLocationUuid: (INPUT) // UUID of the preferred location. // -// preferredCpuNumaNode: (INPUT) +// preferredCpuMemoryNode: (INPUT) // Preferred CPU NUMA memory node used if preferredLocationUuid is the // UUID of the CPU. -1 is a special value which indicates all CPU nodes -// allowed by the global and thread memory policies. This argument is -// ignored if preferredLocationUuid refers to a GPU or the given virtual -// address range corresponds to managed memory. If NUMA is not enabled, -// only 0 or -1 is allowed. +// allowed by the global and thread memory policies. // // Errors: // NV_ERR_INVALID_ADDRESS: @@ -2339,10 +2328,11 @@ NV_STATUS UvmDisableReadDuplication(void *base, // // NV_ERR_INVALID_ARGUMENT: // One of the following occured: -// - preferredLocationUuid is the UUID of a CPU and preferredCpuNumaNode -// refers to a registered GPU. -// - preferredCpuNumaNode is invalid and preferredLocationUuid is the -// UUID of the CPU. +// - preferredLocationUuid is the UUID of the CPU and +// preferredCpuMemoryNode is either: +// - not a valid NUMA node, +// - not a possible NUMA node, or +// - a NUMA node ID corresponding to a registered GPU. // // NV_ERR_NOT_SUPPORTED: // The UVM file descriptor is associated with another process and the @@ -2353,16 +2343,10 @@ NV_STATUS UvmDisableReadDuplication(void *base, // because it is not very informative. // //------------------------------------------------------------------------------ -#if UVM_API_REV_IS_AT_MOST(7) -NV_STATUS UvmSetPreferredLocation(void *base, - NvLength length, - const NvProcessorUuid *preferredLocationUuid); -#else NV_STATUS UvmSetPreferredLocation(void *base, NvLength length, const NvProcessorUuid *preferredLocationUuid, - NvS32 preferredCpuNumaNode); -#endif + NvS32 preferredCpuMemoryNode); //------------------------------------------------------------------------------ // UvmUnsetPreferredLocation diff --git a/kernel-open/nvidia-uvm/uvm_ada.c b/kernel-open/nvidia-uvm/uvm_ada.c index 8852c44abf..c7dff51706 100644 --- a/kernel-open/nvidia-uvm/uvm_ada.c +++ b/kernel-open/nvidia-uvm/uvm_ada.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -79,6 +79,8 @@ void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counters_supported = true; + parent_gpu->access_counters_can_use_physical_addresses = false; + parent_gpu->fault_cancel_va_supported = true; parent_gpu->scoped_atomics_supported = true; @@ -94,4 +96,6 @@ void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_ampere.c b/kernel-open/nvidia-uvm/uvm_ampere.c index d4af699e42..50b8a53762 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere.c +++ b/kernel-open/nvidia-uvm/uvm_ampere.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-20221 NVIDIA Corporation + Copyright (c) 2018-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -38,10 +38,12 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->utlb_per_gpc_count = uvm_ampere_get_utlbs_per_gpc(parent_gpu); - parent_gpu->fault_buffer_info.replayable.utlb_count = parent_gpu->rm_info.maxGpcCount * parent_gpu->utlb_per_gpc_count; + parent_gpu->fault_buffer_info.replayable.utlb_count = parent_gpu->rm_info.maxGpcCount * + parent_gpu->utlb_per_gpc_count; { uvm_fault_buffer_entry_t *dummy; - UVM_ASSERT(parent_gpu->fault_buffer_info.replayable.utlb_count <= (1 << (sizeof(dummy->fault_source.utlb_id) * 8))); + UVM_ASSERT(parent_gpu->fault_buffer_info.replayable.utlb_count <= (1 << + (sizeof(dummy->fault_source.utlb_id) * 8))); } // A single top level PDE on Ampere covers 128 TB and that's the minimum @@ -53,7 +55,7 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; // See uvm_mmu.h for mapping placement - parent_gpu->flat_vidmem_va_base = 136 * UVM_SIZE_1TB; + parent_gpu->flat_vidmem_va_base = 160 * UVM_SIZE_1TB; parent_gpu->flat_sysmem_va_base = 256 * UVM_SIZE_1TB; parent_gpu->ce_phys_vidmem_write_supported = true; @@ -81,6 +83,8 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counters_supported = true; + parent_gpu->access_counters_can_use_physical_addresses = false; + parent_gpu->fault_cancel_va_supported = true; parent_gpu->scoped_atomics_supported = true; @@ -101,4 +105,6 @@ void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_ampere_ce.c b/kernel-open/nvidia-uvm/uvm_ampere_ce.c index 623cc276a4..ac13a16d7d 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere_ce.c +++ b/kernel-open/nvidia-uvm/uvm_ampere_ce.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2022 NVIDIA Corporation + Copyright (c) 2018-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -117,7 +117,7 @@ bool uvm_hal_ampere_ce_memcopy_is_valid_c6b5(uvm_push_t *push, uvm_gpu_address_t NvU64 push_begin_gpu_va; uvm_gpu_t *gpu = uvm_push_get_gpu(push); - if (!uvm_gpu_is_virt_mode_sriov_heavy(gpu)) + if (!uvm_parent_gpu_is_virt_mode_sriov_heavy(gpu->parent)) return true; if (uvm_channel_is_proxy(push->channel)) { @@ -196,7 +196,7 @@ bool uvm_hal_ampere_ce_memset_is_valid_c6b5(uvm_push_t *push, { uvm_gpu_t *gpu = uvm_push_get_gpu(push); - if (!uvm_gpu_is_virt_mode_sriov_heavy(gpu)) + if (!uvm_parent_gpu_is_virt_mode_sriov_heavy(gpu->parent)) return true; if (uvm_channel_is_proxy(push->channel)) { diff --git a/kernel-open/nvidia-uvm/uvm_ampere_host.c b/kernel-open/nvidia-uvm/uvm_ampere_host.c index dbf7a06a86..d0817b54cc 100644 --- a/kernel-open/nvidia-uvm/uvm_ampere_host.c +++ b/kernel-open/nvidia-uvm/uvm_ampere_host.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2022 NVIDIA Corporation + Copyright (c) 2018-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,7 +33,7 @@ bool uvm_hal_ampere_host_method_is_valid(uvm_push_t *push, NvU32 method_address, { uvm_gpu_t *gpu = uvm_push_get_gpu(push); - if (!uvm_gpu_is_virt_mode_sriov_heavy(gpu)) + if (!uvm_parent_gpu_is_virt_mode_sriov_heavy(gpu->parent)) return true; if (uvm_channel_is_privileged(push->channel)) { diff --git a/kernel-open/nvidia-uvm/uvm_ats_faults.c b/kernel-open/nvidia-uvm/uvm_ats_faults.c index 88f654f198..d3c61725d4 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_faults.c +++ b/kernel-open/nvidia-uvm/uvm_ats_faults.c @@ -34,19 +34,32 @@ #include #endif -static NV_STATUS service_ats_faults(uvm_gpu_va_space_t *gpu_va_space, - struct vm_area_struct *vma, - NvU64 start, - size_t length, - uvm_fault_access_type_t access_type, - uvm_ats_fault_context_t *ats_context) +typedef enum +{ + UVM_ATS_SERVICE_TYPE_FAULTS = 0, + UVM_ATS_SERVICE_TYPE_ACCESS_COUNTERS, + UVM_ATS_SERVICE_TYPE_COUNT +} uvm_ats_service_type_t; + +static NV_STATUS service_ats_requests(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 start, + size_t length, + uvm_fault_access_type_t access_type, + uvm_ats_service_type_t service_type, + uvm_ats_fault_context_t *ats_context) { uvm_va_space_t *va_space = gpu_va_space->va_space; struct mm_struct *mm = va_space->va_space_mm.mm; - bool write = (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE); NV_STATUS status; NvU64 user_space_start; NvU64 user_space_length; + bool write = (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE); + bool fault_service_type = (service_type == UVM_ATS_SERVICE_TYPE_FAULTS); + uvm_populate_permissions_t populate_permissions = fault_service_type ? + (write ? UVM_POPULATE_PERMISSIONS_WRITE : UVM_POPULATE_PERMISSIONS_ANY) : + UVM_POPULATE_PERMISSIONS_INHERIT; + // Request uvm_migrate_pageable() to touch the corresponding page after // population. @@ -83,10 +96,10 @@ static NV_STATUS service_ats_faults(uvm_gpu_va_space_t *gpu_va_space, .dst_node_id = ats_context->residency_node, .start = start, .length = length, - .populate_permissions = write ? UVM_POPULATE_PERMISSIONS_WRITE : UVM_POPULATE_PERMISSIONS_ANY, - .touch = true, - .skip_mapped = true, - .populate_on_cpu_alloc_failures = true, + .populate_permissions = populate_permissions, + .touch = fault_service_type, + .skip_mapped = fault_service_type, + .populate_on_cpu_alloc_failures = fault_service_type, .user_space_start = &user_space_start, .user_space_length = &user_space_length, }; @@ -107,26 +120,24 @@ static NV_STATUS service_ats_faults(uvm_gpu_va_space_t *gpu_va_space, return status; } -static void flush_tlb_write_faults(uvm_gpu_va_space_t *gpu_va_space, - NvU64 addr, - size_t size, - uvm_fault_client_type_t client_type) +static void flush_tlb_va_region(uvm_gpu_va_space_t *gpu_va_space, + NvU64 addr, + size_t size, + uvm_fault_client_type_t client_type) { uvm_ats_fault_invalidate_t *ats_invalidate; - uvm_ats_smmu_invalidate_tlbs(gpu_va_space, addr, size); - if (client_type == UVM_FAULT_CLIENT_TYPE_GPC) ats_invalidate = &gpu_va_space->gpu->parent->fault_buffer_info.replayable.ats_invalidate; else ats_invalidate = &gpu_va_space->gpu->parent->fault_buffer_info.non_replayable.ats_invalidate; - if (!ats_invalidate->write_faults_in_batch) { - uvm_tlb_batch_begin(&gpu_va_space->page_tables, &ats_invalidate->write_faults_tlb_batch); - ats_invalidate->write_faults_in_batch = true; + if (!ats_invalidate->tlb_batch_pending) { + uvm_tlb_batch_begin(&gpu_va_space->page_tables, &ats_invalidate->tlb_batch); + ats_invalidate->tlb_batch_pending = true; } - uvm_tlb_batch_invalidate(&ats_invalidate->write_faults_tlb_batch, addr, size, PAGE_SIZE, UVM_MEMBAR_NONE); + uvm_tlb_batch_invalidate(&ats_invalidate->tlb_batch, addr, size, PAGE_SIZE, UVM_MEMBAR_NONE); } static void ats_batch_select_residency(uvm_gpu_va_space_t *gpu_va_space, @@ -192,7 +203,7 @@ static void ats_batch_select_residency(uvm_gpu_va_space_t *gpu_va_space, ats_context->prefetch_state.has_preferred_location = false; #endif - ats_context->residency_id = gpu ? gpu->parent->id : UVM_ID_CPU; + ats_context->residency_id = gpu ? gpu->id : UVM_ID_CPU; ats_context->residency_node = residency; } @@ -364,51 +375,43 @@ static NV_STATUS ats_compute_residency_mask(uvm_gpu_va_space_t *gpu_va_space, return status; } -static void ats_expand_fault_region(uvm_gpu_va_space_t *gpu_va_space, - struct vm_area_struct *vma, - uvm_ats_fault_context_t *ats_context, - uvm_va_block_region_t max_prefetch_region, - uvm_page_mask_t *faulted_mask) +static void ats_compute_prefetch_mask(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + uvm_ats_fault_context_t *ats_context, + uvm_va_block_region_t max_prefetch_region) { - uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; - uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + uvm_page_mask_t *accessed_mask = &ats_context->accessed_mask; uvm_page_mask_t *residency_mask = &ats_context->prefetch_state.residency_mask; uvm_page_mask_t *prefetch_mask = &ats_context->prefetch_state.prefetch_pages_mask; uvm_perf_prefetch_bitmap_tree_t *bitmap_tree = &ats_context->prefetch_state.bitmap_tree; - if (uvm_page_mask_empty(faulted_mask)) + if (uvm_page_mask_empty(accessed_mask)) return; uvm_perf_prefetch_compute_ats(gpu_va_space->va_space, - faulted_mask, - uvm_va_block_region_from_mask(NULL, faulted_mask), + accessed_mask, + uvm_va_block_region_from_mask(NULL, accessed_mask), max_prefetch_region, residency_mask, bitmap_tree, prefetch_mask); - - uvm_page_mask_or(read_fault_mask, read_fault_mask, prefetch_mask); - - if (vma->vm_flags & VM_WRITE) - uvm_page_mask_or(write_fault_mask, write_fault_mask, prefetch_mask); } -static NV_STATUS ats_fault_prefetch(uvm_gpu_va_space_t *gpu_va_space, - struct vm_area_struct *vma, - NvU64 base, - uvm_ats_fault_context_t *ats_context) +static NV_STATUS ats_compute_prefetch(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_service_type_t service_type, + uvm_ats_fault_context_t *ats_context) { NV_STATUS status = NV_OK; - uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; - uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; - uvm_page_mask_t *faulted_mask = &ats_context->faulted_mask; + uvm_page_mask_t *accessed_mask = &ats_context->accessed_mask; uvm_page_mask_t *prefetch_mask = &ats_context->prefetch_state.prefetch_pages_mask; uvm_va_block_region_t max_prefetch_region = uvm_ats_region_from_vma(vma, base); if (!uvm_perf_prefetch_enabled(gpu_va_space->va_space)) return status; - if (uvm_page_mask_empty(faulted_mask)) + if (uvm_page_mask_empty(accessed_mask)) return status; status = ats_compute_residency_mask(gpu_va_space, vma, base, ats_context); @@ -418,19 +421,27 @@ static NV_STATUS ats_fault_prefetch(uvm_gpu_va_space_t *gpu_va_space, // Prefetch the entire region if none of the pages are resident on any node // and if preferred_location is the faulting GPU. if (ats_context->prefetch_state.has_preferred_location && - ats_context->prefetch_state.first_touch && - uvm_id_equal(ats_context->residency_id, gpu_va_space->gpu->parent->id)) { + (ats_context->prefetch_state.first_touch || (service_type == UVM_ATS_SERVICE_TYPE_ACCESS_COUNTERS)) && + uvm_id_equal(ats_context->residency_id, gpu_va_space->gpu->id)) { uvm_page_mask_init_from_region(prefetch_mask, max_prefetch_region, NULL); + } + else { + ats_compute_prefetch_mask(gpu_va_space, vma, ats_context, max_prefetch_region); + } + + if (service_type == UVM_ATS_SERVICE_TYPE_FAULTS) { + uvm_page_mask_t *read_fault_mask = &ats_context->read_fault_mask; + uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; + uvm_page_mask_or(read_fault_mask, read_fault_mask, prefetch_mask); if (vma->vm_flags & VM_WRITE) uvm_page_mask_or(write_fault_mask, write_fault_mask, prefetch_mask); - - return status; } - - ats_expand_fault_region(gpu_va_space, vma, ats_context, max_prefetch_region, faulted_mask); + else { + uvm_page_mask_or(accessed_mask, accessed_mask, prefetch_mask); + } return status; } @@ -448,6 +459,7 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, uvm_page_mask_t *faults_serviced_mask = &ats_context->faults_serviced_mask; uvm_page_mask_t *reads_serviced_mask = &ats_context->reads_serviced_mask; uvm_fault_client_type_t client_type = ats_context->client_type; + uvm_ats_service_type_t service_type = UVM_ATS_SERVICE_TYPE_FAULTS; UVM_ASSERT(vma); UVM_ASSERT(IS_ALIGNED(base, UVM_VA_BLOCK_SIZE)); @@ -456,6 +468,9 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, UVM_ASSERT(gpu_va_space->ats.enabled); UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); + uvm_assert_mmap_lock_locked(vma->vm_mm); + uvm_assert_rwsem_locked(&gpu_va_space->va_space->lock); + uvm_page_mask_zero(faults_serviced_mask); uvm_page_mask_zero(reads_serviced_mask); @@ -481,7 +496,7 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, ats_batch_select_residency(gpu_va_space, vma, ats_context); - ats_fault_prefetch(gpu_va_space, vma, base, ats_context); + ats_compute_prefetch(gpu_va_space, vma, base, service_type, ats_context); for_each_va_block_subregion_in_mask(subregion, write_fault_mask, region) { NvU64 start = base + (subregion.first * PAGE_SIZE); @@ -493,12 +508,13 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, UVM_ASSERT(start >= vma->vm_start); UVM_ASSERT((start + length) <= vma->vm_end); - status = service_ats_faults(gpu_va_space, vma, start, length, access_type, ats_context); + status = service_ats_requests(gpu_va_space, vma, start, length, access_type, service_type, ats_context); if (status != NV_OK) return status; if (vma->vm_flags & VM_WRITE) { uvm_page_mask_region_fill(faults_serviced_mask, subregion); + uvm_ats_smmu_invalidate_tlbs(gpu_va_space, start, length); // The Linux kernel never invalidates TLB entries on mapping // permission upgrade. This is a problem if the GPU has cached @@ -509,7 +525,7 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, // infinite loop because we just forward the fault to the Linux // kernel and it will see that the permissions in the page table are // correct. Therefore, we flush TLB entries on ATS write faults. - flush_tlb_write_faults(gpu_va_space, start, length, client_type); + flush_tlb_va_region(gpu_va_space, start, length, client_type); } else { uvm_page_mask_region_fill(reads_serviced_mask, subregion); @@ -527,11 +543,20 @@ NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, UVM_ASSERT(start >= vma->vm_start); UVM_ASSERT((start + length) <= vma->vm_end); - status = service_ats_faults(gpu_va_space, vma, start, length, access_type, ats_context); + status = service_ats_requests(gpu_va_space, vma, start, length, access_type, service_type, ats_context); if (status != NV_OK) return status; uvm_page_mask_region_fill(faults_serviced_mask, subregion); + + // Similarly to permission upgrade scenario, discussed above, GPU + // will not re-fetch the entry if the PTE is invalid and page size + // is 4K. To avoid infinite faulting loop, invalidate TLB for every + // new translation written explicitly like in the case of permission + // upgrade. + if (PAGE_SIZE == UVM_PAGE_SIZE_4K) + flush_tlb_va_region(gpu_va_space, start, length, client_type); + } return status; @@ -566,7 +591,7 @@ NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NV_STATUS status; uvm_push_t push; - if (!ats_invalidate->write_faults_in_batch) + if (!ats_invalidate->tlb_batch_pending) return NV_OK; UVM_ASSERT(gpu_va_space); @@ -578,7 +603,7 @@ NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, "Invalidate ATS entries"); if (status == NV_OK) { - uvm_tlb_batch_end(&ats_invalidate->write_faults_tlb_batch, &push, UVM_MEMBAR_NONE); + uvm_tlb_batch_end(&ats_invalidate->tlb_batch, &push, UVM_MEMBAR_NONE); uvm_push_end(&push); // Add this push to the GPU's tracker so that fault replays/clears can @@ -586,7 +611,47 @@ NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, status = uvm_tracker_add_push_safe(out_tracker, &push); } - ats_invalidate->write_faults_in_batch = false; + ats_invalidate->tlb_batch_pending = false; return status; } + +NV_STATUS uvm_ats_service_access_counters(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_fault_context_t *ats_context) +{ + uvm_va_block_region_t subregion; + uvm_va_block_region_t region = uvm_va_block_region(0, PAGES_PER_UVM_VA_BLOCK); + uvm_ats_service_type_t service_type = UVM_ATS_SERVICE_TYPE_ACCESS_COUNTERS; + + UVM_ASSERT(vma); + UVM_ASSERT(IS_ALIGNED(base, UVM_VA_BLOCK_SIZE)); + UVM_ASSERT(g_uvm_global.ats.enabled); + UVM_ASSERT(gpu_va_space); + UVM_ASSERT(gpu_va_space->ats.enabled); + UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); + + uvm_assert_mmap_lock_locked(vma->vm_mm); + uvm_assert_rwsem_locked(&gpu_va_space->va_space->lock); + + ats_batch_select_residency(gpu_va_space, vma, ats_context); + + ats_compute_prefetch(gpu_va_space, vma, base, service_type, ats_context); + + for_each_va_block_subregion_in_mask(subregion, &ats_context->accessed_mask, region) { + NV_STATUS status; + NvU64 start = base + (subregion.first * PAGE_SIZE); + size_t length = uvm_va_block_region_num_pages(subregion) * PAGE_SIZE; + uvm_fault_access_type_t access_type = UVM_FAULT_ACCESS_TYPE_COUNT; + + UVM_ASSERT(start >= vma->vm_start); + UVM_ASSERT((start + length) <= vma->vm_end); + + status = service_ats_requests(gpu_va_space, vma, start, length, access_type, service_type, ats_context); + if (status != NV_OK) + return status; + } + + return NV_OK; +} diff --git a/kernel-open/nvidia-uvm/uvm_ats_faults.h b/kernel-open/nvidia-uvm/uvm_ats_faults.h index ca67387e74..71f109a8f1 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_faults.h +++ b/kernel-open/nvidia-uvm/uvm_ats_faults.h @@ -42,17 +42,37 @@ // corresponding bit in read_fault_mask. These returned masks are only valid if // the return status is NV_OK. Status other than NV_OK indicate system global // fault servicing failures. +// +// LOCKING: The caller must retain and hold the mmap_lock and hold the va_space +// lock. NV_STATUS uvm_ats_service_faults(uvm_gpu_va_space_t *gpu_va_space, struct vm_area_struct *vma, NvU64 base, uvm_ats_fault_context_t *ats_context); +// Service access counter notifications on ATS regions in the range (base, base +// + UVM_VA_BLOCK_SIZE) for individual pages in the range requested by page_mask +// set in ats_context->accessed_mask. base must be aligned to UVM_VA_BLOCK_SIZE. +// The caller is responsible for ensuring that the addresses in the +// accessed_mask is completely covered by the VMA. The caller is also +// responsible for handling any errors returned by this function. +// +// Returns NV_OK if servicing was successful. Any other error indicates an error +// while servicing the range. +// +// LOCKING: The caller must retain and hold the mmap_lock and hold the va_space +// lock. +NV_STATUS uvm_ats_service_access_counters(uvm_gpu_va_space_t *gpu_va_space, + struct vm_area_struct *vma, + NvU64 base, + uvm_ats_fault_context_t *ats_context); + // Return whether there are any VA ranges (and thus GMMU mappings) within the // UVM_GMMU_ATS_GRANULARITY-aligned region containing address. bool uvm_ats_check_in_gmmu_region(uvm_va_space_t *va_space, NvU64 address, uvm_va_range_t *next); // This function performs pending TLB invalidations for ATS and clears the -// ats_invalidate->write_faults_in_batch flag +// ats_invalidate->tlb_batch_pending flag NV_STATUS uvm_ats_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, uvm_ats_fault_invalidate_t *ats_invalidate, uvm_tracker_t *out_tracker); diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.c b/kernel-open/nvidia-uvm/uvm_ats_sva.c index 5cfcb3e766..d4b9e2c4e9 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_sva.c +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.c @@ -30,6 +30,7 @@ #include "uvm_va_space_mm.h" #include +#include #include #include #include @@ -50,6 +51,12 @@ #define UVM_IOMMU_SVA_BIND_DEVICE(dev, mm) iommu_sva_bind_device(dev, mm) #endif +// Type to represent a 128-bit SMMU command queue command. +struct smmu_cmd { + NvU64 low; + NvU64 high; +}; + // Base address of SMMU CMDQ-V for GSMMU0. #define SMMU_CMDQV_BASE_ADDR(smmu_base) (smmu_base + 0x200000) #define SMMU_CMDQV_BASE_LEN 0x00830000 @@ -101,9 +108,9 @@ // Base address offset for the VCMDQ registers. #define SMMU_VCMDQ_CMDQ_BASE 0x10000 -// Size of the command queue. Each command is 8 bytes and we can't -// have a command queue greater than one page. -#define SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE 9 +// Size of the command queue. Each command is 16 bytes and we can't +// have a command queue greater than one page in size. +#define SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE (PAGE_SHIFT - ilog2(sizeof(struct smmu_cmd))) #define SMMU_VCMDQ_CMDQ_ENTRIES (1UL << SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE) // We always use VINTF63 for the WAR @@ -175,7 +182,6 @@ static NV_STATUS uvm_ats_smmu_war_init(uvm_parent_gpu_t *parent_gpu) iowrite32((VINTF << SMMU_CMDQV_CMDQ_ALLOC_MAP_VIRT_INTF_INDX_SHIFT) | SMMU_CMDQV_CMDQ_ALLOC_MAP_ALLOC, smmu_cmdqv_base + SMMU_CMDQV_CMDQ_ALLOC_MAP(VCMDQ)); - BUILD_BUG_ON((SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE + 3) > PAGE_SHIFT); smmu_vcmdq_write64(smmu_cmdqv_base, SMMU_VCMDQ_CMDQ_BASE, page_to_phys(parent_gpu->smmu_war.smmu_cmdq) | SMMU_VCMDQ_CMDQ_BASE_LOG2SIZE); smmu_vcmdq_write32(smmu_cmdqv_base, SMMU_VCMDQ_CONS, 0); diff --git a/kernel-open/nvidia-uvm/uvm_ats_sva.h b/kernel-open/nvidia-uvm/uvm_ats_sva.h index 1466c6e472..293c563b4b 100644 --- a/kernel-open/nvidia-uvm/uvm_ats_sva.h +++ b/kernel-open/nvidia-uvm/uvm_ats_sva.h @@ -53,10 +53,11 @@ #define UVM_ATS_SVA_SUPPORTED() 0 #endif -// If NV_ARCH_INVALIDATE_SECONDARY_TLBS is defined it means the upstream fix is -// in place so no need for the WAR from Bug 4130089: [GH180][r535] WAR for -// kernel not issuing SMMU TLB invalidates on read-only -#if defined(NV_ARCH_INVALIDATE_SECONDARY_TLBS) +// If NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS is defined it +// means the upstream fix is in place so no need for the WAR from +// Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU TLB +// invalidates on read-only +#if defined(NV_MMU_NOTIFIER_OPS_HAS_ARCH_INVALIDATE_SECONDARY_TLBS) #define UVM_ATS_SMMU_WAR_REQUIRED() 0 #elif NVCPU_IS_AARCH64 #define UVM_ATS_SMMU_WAR_REQUIRED() 1 diff --git a/kernel-open/nvidia-uvm/uvm_ce_test.c b/kernel-open/nvidia-uvm/uvm_ce_test.c index 90e7c2dbc6..735edc0626 100644 --- a/kernel-open/nvidia-uvm/uvm_ce_test.c +++ b/kernel-open/nvidia-uvm/uvm_ce_test.c @@ -56,7 +56,7 @@ static NV_STATUS test_non_pipelined(uvm_gpu_t *gpu) // TODO: Bug 3839176: the test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, CE_TEST_MEM_SIZE, 0, &host_mem); @@ -176,7 +176,7 @@ static NV_STATUS test_membar(uvm_gpu_t *gpu) // TODO: Bug 3839176: the test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; status = uvm_rm_mem_alloc_and_map_cpu(gpu, UVM_RM_MEM_TYPE_SYS, sizeof(NvU32), 0, &host_mem); @@ -411,10 +411,11 @@ static NV_STATUS test_memcpy_and_memset(uvm_gpu_t *gpu) size_t i, j, k, s; uvm_mem_alloc_params_t mem_params = {0}; - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(size, gpu, current->mm, &verif_mem), done); else TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, &verif_mem), done); + TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, gpu), done); gpu_verif_addr = uvm_mem_gpu_address_virtual_kernel(verif_mem, gpu); @@ -436,7 +437,7 @@ static NV_STATUS test_memcpy_and_memset(uvm_gpu_t *gpu) TEST_NV_CHECK_GOTO(uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_SYS, size, 0, &sys_rm_mem), done); gpu_addresses[0] = uvm_rm_mem_get_gpu_va(sys_rm_mem, gpu, is_proxy_va_space); - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { for (i = 0; i < iterations; ++i) { for (s = 0; s < ARRAY_SIZE(element_sizes); s++) { TEST_NV_CHECK_GOTO(test_memcpy_and_memset_inner(gpu, @@ -559,7 +560,7 @@ static NV_STATUS test_semaphore_reduction_inc(uvm_gpu_t *gpu) // TODO: Bug 3839176: the test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; status = test_semaphore_alloc_sem(gpu, size, &mem); @@ -611,7 +612,7 @@ static NV_STATUS test_semaphore_release(uvm_gpu_t *gpu) // TODO: Bug 3839176: the test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; status = test_semaphore_alloc_sem(gpu, size, &mem); @@ -665,7 +666,7 @@ static NV_STATUS test_semaphore_timestamp(uvm_gpu_t *gpu) // TODO: Bug 3839176: the test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; status = test_semaphore_alloc_sem(gpu, size, &mem); @@ -1153,7 +1154,7 @@ static NV_STATUS test_encryption_decryption(uvm_gpu_t *gpu, } small_sizes[] = {{1, 1}, {3, 1}, {8, 1}, {2, 2}, {8, 4}, {UVM_PAGE_SIZE_4K - 8, 8}, {UVM_PAGE_SIZE_4K + 8, 8}}; // Only Confidential Computing uses CE encryption/decryption - if (!uvm_conf_computing_mode_enabled(gpu)) + if (!g_uvm_global.conf_computing_enabled) return NV_OK; // Use a size, and copy size, that are not a multiple of common page sizes. diff --git a/kernel-open/nvidia-uvm/uvm_channel.c b/kernel-open/nvidia-uvm/uvm_channel.c index 5474e8a466..ac8b54ce69 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.c +++ b/kernel-open/nvidia-uvm/uvm_channel.c @@ -83,7 +83,7 @@ bool uvm_channel_pool_uses_mutex(uvm_channel_pool_t *pool) // submission uses UVM_SPIN_LOOP, which can call 'schedule', to wait for // LCIC completion. Indirect submission is synchronous, calling // uvm_push_wait which again uses UVM_SPIN_LOOP. - if (uvm_conf_computing_mode_enabled(pool->manager->gpu)) + if (g_uvm_global.conf_computing_enabled) return true; // Unless the mutex is required, the spinlock is preferred when work @@ -95,7 +95,7 @@ static void channel_pool_lock_init(uvm_channel_pool_t *pool) { uvm_lock_order_t order = UVM_LOCK_ORDER_CHANNEL; - if (uvm_conf_computing_mode_enabled(pool->manager->gpu) && uvm_channel_pool_is_wlc(pool)) + if (g_uvm_global.conf_computing_enabled && uvm_channel_pool_is_wlc(pool)) order = UVM_LOCK_ORDER_WLC_CHANNEL; if (uvm_channel_pool_uses_mutex(pool)) @@ -137,7 +137,7 @@ static NvU32 uvm_channel_update_progress_with_max(uvm_channel_t *channel, // Completed value should never exceed the queued value UVM_ASSERT_MSG_RELEASE(completed_value <= channel->tracking_sem.queued_value, "GPU %s channel %s unexpected completed_value 0x%llx > queued_value 0x%llx\n", - channel->pool->manager->gpu->parent->name, + uvm_gpu_name(uvm_channel_get_gpu(channel)), channel->name, completed_value, channel->tracking_sem.queued_value); @@ -273,9 +273,8 @@ static bool try_claim_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) static void unlock_channel_for_push(uvm_channel_t *channel) { NvU32 index; - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - if (!uvm_conf_computing_mode_enabled(gpu)) + if (!g_uvm_global.conf_computing_enabled) return; index = uvm_channel_index_in_pool(channel); @@ -287,25 +286,22 @@ static void unlock_channel_for_push(uvm_channel_t *channel) uvm_up_out_of_order(&channel->pool->push_sem); } -static bool is_channel_locked_for_push(uvm_channel_t *channel) +bool uvm_channel_is_locked_for_push(uvm_channel_t *channel) { - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return test_bit(uvm_channel_index_in_pool(channel), channel->pool->push_locks); // For CE and proxy channels, we always return that the channel is locked, // which has no functional impact in the UVM channel code-flow, this is only - // used on UVM_ASSERTs. + // used in UVM_ASSERTs. return true; } static void lock_channel_for_push(uvm_channel_t *channel) { - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); NvU32 index = uvm_channel_index_in_pool(channel); - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); uvm_channel_pool_assert_locked(channel->pool); UVM_ASSERT(!test_bit(index, channel->pool->push_locks)); @@ -314,10 +310,9 @@ static void lock_channel_for_push(uvm_channel_t *channel) static bool test_claim_and_lock_channel(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); NvU32 index = uvm_channel_index_in_pool(channel); - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); uvm_channel_pool_assert_locked(channel->pool); if (!test_bit(index, channel->pool->push_locks) && try_claim_channel_locked(channel, num_gpfifo_entries)) { @@ -337,7 +332,7 @@ static NV_STATUS channel_reserve_and_lock_in_pool(uvm_channel_pool_t *pool, uvm_ NvU32 index; UVM_ASSERT(pool); - UVM_ASSERT(uvm_conf_computing_mode_enabled(pool->manager->gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); // This semaphore is uvm_up() in unlock_channel_for_push() as part of the // uvm_channel_end_push() routine. @@ -399,7 +394,7 @@ static NV_STATUS channel_reserve_in_pool(uvm_channel_pool_t *pool, uvm_channel_t UVM_ASSERT(pool); - if (uvm_conf_computing_mode_enabled(pool->manager->gpu)) + if (g_uvm_global.conf_computing_enabled) return channel_reserve_and_lock_in_pool(pool, channel_out); uvm_for_each_channel_in_pool(channel, pool) { @@ -509,7 +504,7 @@ static void channel_semaphore_gpu_encrypt_payload(uvm_push_t *push, NvU64 semaph NvU32 payload_size = sizeof(*semaphore->payload); NvU32 *last_pushed_notifier = &semaphore->conf_computing.last_pushed_notifier; - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); UVM_ASSERT(uvm_channel_is_ce(channel)); encrypted_payload_gpu_va = uvm_rm_mem_get_gpu_va(semaphore->conf_computing.encrypted_payload, gpu, false); @@ -540,29 +535,97 @@ static void push_reserve_csl_sign_buf(uvm_push_t *push) UVM_ASSERT((buf - UVM_METHOD_SIZE / sizeof(*buf)) == push->begin); } -NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push) +static uvm_channel_t *get_paired_channel(uvm_channel_t *channel) +{ + unsigned index; + uvm_channel_pool_t *paired_pool; + uvm_channel_type_t paired_channel_type; + + UVM_ASSERT(channel); + UVM_ASSERT(uvm_channel_is_wlc(channel) || uvm_channel_is_lcic(channel)); + + index = uvm_channel_index_in_pool(channel); + paired_channel_type = uvm_channel_is_wlc(channel) ? UVM_CHANNEL_TYPE_LCIC : UVM_CHANNEL_TYPE_WLC; + paired_pool = channel->pool->manager->pool_to_use.default_for_type[paired_channel_type]; + return paired_pool->channels + index; +} + +uvm_channel_t *uvm_channel_lcic_get_paired_wlc(uvm_channel_t *lcic_channel) +{ + UVM_ASSERT(lcic_channel); + UVM_ASSERT(uvm_channel_is_lcic(lcic_channel)); + + return get_paired_channel(lcic_channel); +} + +uvm_channel_t *uvm_channel_wlc_get_paired_lcic(uvm_channel_t *wlc_channel) { + UVM_ASSERT(wlc_channel); + UVM_ASSERT(uvm_channel_is_wlc(wlc_channel)); + + return get_paired_channel(wlc_channel); +} + +static NV_STATUS channel_rotate_and_reserve_launch_channel(uvm_channel_t *channel, uvm_channel_t **launch_channel) +{ + uvm_channel_manager_t *manager = channel->pool->manager; NV_STATUS status; + + status = uvm_conf_computing_maybe_rotate_channel_ivs(channel); + if (status != NV_OK) + return status; + + // CE channels, other than WLC fix launch schedule setup, need a launch + // channel that needs to be reserved + if (uvm_channel_is_ce(channel) && + !(uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(manager))) { + uvm_channel_t *local_launch_channel = NULL; + uvm_channel_type_t indirect_channel_type = uvm_channel_manager_is_wlc_ready(manager) ? + UVM_CHANNEL_TYPE_WLC : + UVM_CHANNEL_TYPE_SEC2; + status = uvm_channel_reserve_type(manager, indirect_channel_type, &local_launch_channel); + if (status != NV_OK) + return status; + + // Indirect launch relies on pre-allocated resources to avoid failure + // paths. This includes pre-allocating IV space. There's no way to + // undo the launch channel reservation, so just return an error. + status = uvm_conf_computing_maybe_rotate_channel_ivs(local_launch_channel); + if (status != NV_OK) { + uvm_channel_release(local_launch_channel, 1); + return status; + } + + if (uvm_channel_is_wlc(local_launch_channel)) { + status = uvm_conf_computing_maybe_rotate_channel_ivs(uvm_channel_wlc_get_paired_lcic(local_launch_channel)); + if (status != NV_OK) { + uvm_channel_release(local_launch_channel, 1); + return status; + } + } + *launch_channel = local_launch_channel; + } + + + return NV_OK; +} + +NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push) +{ + NV_STATUS status = NV_OK; uvm_channel_manager_t *manager; - uvm_gpu_t *gpu; UVM_ASSERT(channel); UVM_ASSERT(push); manager = channel->pool->manager; - gpu = uvm_channel_get_gpu(channel); - // Only SEC2 and WLC with set up fixed schedule can use direct push // submission. All other cases (including WLC pre-schedule) need to // reserve a launch channel that will be used to submit this push // indirectly. - if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel) && - !(uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(manager))) { - uvm_channel_type_t indirect_channel_type = uvm_channel_manager_is_wlc_ready(manager) ? - UVM_CHANNEL_TYPE_WLC : - UVM_CHANNEL_TYPE_SEC2; - status = uvm_channel_reserve_type(manager, indirect_channel_type, &push->launch_channel); + if (g_uvm_global.conf_computing_enabled) { + status = channel_rotate_and_reserve_launch_channel(channel, &push->launch_channel); if (status != NV_OK) return status; } @@ -570,7 +633,7 @@ NV_STATUS uvm_channel_begin_push(uvm_channel_t *channel, uvm_push_t *push) // When the Confidential Computing feature is enabled, the channel's lock // should have already been acquired in uvm_channel_reserve() or // channel_reserve_and_lock_in_pool(). - UVM_ASSERT(is_channel_locked_for_push(channel)); + UVM_ASSERT(uvm_channel_is_locked_for_push(channel)); push->channel = channel; push->channel_tracking_value = 0; @@ -603,7 +666,7 @@ static void internal_channel_submit_work(uvm_push_t *push, NvU32 push_size, NvU3 gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + channel->cpu_put; pushbuffer_va = uvm_pushbuffer_get_gpu_va_for_push(pushbuffer, push); - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { void *unprotected_pb = uvm_pushbuffer_get_unprotected_cpu_va_for_push(pushbuffer, push); UVM_ASSERT(uvm_channel_is_sec2(channel)); @@ -674,45 +737,14 @@ static void uvm_channel_tracking_semaphore_release(uvm_push_t *push, NvU64 semap // needs to be scheduled to get an encrypted shadow copy in unprotected // sysmem. This allows UVM to later decrypt it and observe the new // semaphore value. - if (uvm_conf_computing_mode_enabled(push->gpu) && uvm_channel_is_ce(push->channel)) + if (g_uvm_global.conf_computing_enabled && uvm_channel_is_ce(push->channel)) channel_semaphore_gpu_encrypt_payload(push, semaphore_va); } -static uvm_channel_t *get_paired_channel(uvm_channel_t *channel) -{ - unsigned index; - uvm_channel_pool_t *paired_pool; - uvm_channel_type_t paired_channel_type; - - UVM_ASSERT(channel); - UVM_ASSERT(uvm_channel_is_wlc(channel) || uvm_channel_is_lcic(channel)); - - index = uvm_channel_index_in_pool(channel); - paired_channel_type = uvm_channel_is_wlc(channel) ? UVM_CHANNEL_TYPE_LCIC : UVM_CHANNEL_TYPE_WLC; - paired_pool = channel->pool->manager->pool_to_use.default_for_type[paired_channel_type]; - return paired_pool->channels + index; -} - -static uvm_channel_t *wlc_get_paired_lcic(uvm_channel_t *wlc_channel) -{ - UVM_ASSERT(wlc_channel); - UVM_ASSERT(uvm_channel_is_wlc(wlc_channel)); - - return get_paired_channel(wlc_channel); -} - -static uvm_channel_t *lcic_get_paired_wlc(uvm_channel_t *lcic_channel) -{ - UVM_ASSERT(lcic_channel); - UVM_ASSERT(uvm_channel_is_lcic(lcic_channel)); - - return get_paired_channel(lcic_channel); -} - static void internal_channel_submit_work_wlc(uvm_push_t *push) { uvm_channel_t *wlc_channel = push->channel; - uvm_channel_t *lcic_channel = wlc_get_paired_lcic(wlc_channel); + uvm_channel_t *lcic_channel = uvm_channel_wlc_get_paired_lcic(wlc_channel); UvmCslIv *iv_cpu_addr = lcic_channel->tracking_sem.semaphore.conf_computing.ivs; NvU32 *last_pushed_notifier; NvU32 iv_index; @@ -926,7 +958,7 @@ static void set_gpfifo_via_sec2(uvm_push_t *sec2_push, uvm_channel_t *channel, N uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); NvU64 prev_pb_va = uvm_pushbuffer_get_gpu_va_base(pushbuffer) + previous_gpfifo->pushbuffer_offset; - // Reconstruct the previous gpfifo entry. UVM_GPFIFO_SYNC_WAIT is + // Reconstruct the previous GPFIFO entry. UVM_GPFIFO_SYNC_WAIT is // used only in static WLC schedule. // Overwriting the previous entry with the same value doesn't hurt, // whether the previous entry has been processed or not @@ -1053,7 +1085,7 @@ static void encrypt_push(uvm_push_t *push) uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); unsigned auth_tag_offset = UVM_CONF_COMPUTING_AUTH_TAG_SIZE * push->push_info_index; - if (!uvm_conf_computing_mode_enabled(gpu)) + if (!g_uvm_global.conf_computing_enabled) return; if (!push_info->on_complete) @@ -1111,7 +1143,7 @@ void uvm_channel_end_push(uvm_push_t *push) uvm_channel_tracking_semaphore_release(push, semaphore_va, new_payload); if (uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(channel_manager)) { - uvm_channel_t *paired_lcic = wlc_get_paired_lcic(channel); + uvm_channel_t *paired_lcic = uvm_channel_wlc_get_paired_lcic(channel); gpu->parent->ce_hal->semaphore_reduction_inc(push, paired_lcic->channel_info.gpPutGpuVa, @@ -1125,7 +1157,7 @@ void uvm_channel_end_push(uvm_push_t *push) // The UVM_MAX_WLC_PUSH_SIZE is set to fit indirect work launch // pushes. However, direct pushes to WLC can be smaller than this // size. This is used e.g. by indirect submission of control - // gpfifo entries. + // GPFIFO entries. gpu->parent->host_hal->noop(push, UVM_MAX_WLC_PUSH_SIZE - uvm_push_get_size(push)); } } @@ -1144,8 +1176,9 @@ void uvm_channel_end_push(uvm_push_t *push) // Indirect submission via SEC2/WLC needs pushes to be aligned for // encryption/decryption. The pushbuffer_size of this push // influences starting address of the next push. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) entry->pushbuffer_size = UVM_ALIGN_UP(push_size, UVM_CONF_COMPUTING_BUF_ALIGNMENT); + entry->push_info = &channel->push_infos[push->push_info_index]; entry->type = UVM_GPFIFO_ENTRY_TYPE_NORMAL; @@ -1158,7 +1191,7 @@ void uvm_channel_end_push(uvm_push_t *push) else if (uvm_channel_is_wlc(channel) && uvm_channel_manager_is_wlc_ready(channel_manager)) { internal_channel_submit_work_wlc(push); } - else if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel)) { + else if (g_uvm_global.conf_computing_enabled && uvm_channel_is_ce(channel)) { if (uvm_channel_manager_is_wlc_ready(channel_manager)) { internal_channel_submit_work_indirect_wlc(push, cpu_put, new_cpu_put); } @@ -1209,7 +1242,7 @@ static void submit_ctrl_gpfifo(uvm_channel_t *channel, uvm_gpfifo_entry_t *entry UVM_ASSERT(entry == &channel->gpfifo_entries[cpu_put]); - if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel)) + if (g_uvm_global.conf_computing_enabled && uvm_channel_is_ce(channel)) return; gpfifo_entry = (NvU64*)channel->channel_info.gpFifoEntries + cpu_put; @@ -1291,8 +1324,6 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu uvm_gpfifo_entry_t *entry; NvU32 cpu_put; NvU32 new_cpu_put; - bool needs_indirect_submit = false; - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); channel_pool_lock(channel->pool); @@ -1315,8 +1346,6 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu --channel->current_gpfifo_count; submit_ctrl_gpfifo(channel, entry, new_cpu_put); - if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel)) - needs_indirect_submit = true; channel->cpu_put = new_cpu_put; @@ -1327,7 +1356,8 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu // semaphore release, where the channel is unlocked. channel_pool_unlock(channel->pool); - if (needs_indirect_submit) { + // Trigger indirect submission when needed. + if (g_uvm_global.conf_computing_enabled && uvm_channel_is_ce(channel)) { NV_STATUS status = submit_ctrl_gpfifo_indirect(channel, entry, cpu_put, new_cpu_put); // All failures are globally fatal. There's nothing we do to recover. @@ -1344,12 +1374,11 @@ static void write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_valu NV_STATUS uvm_channel_write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_entry_value) { NV_STATUS status; - uvm_gpu_t *gpu = channel->pool->manager->gpu; uvm_push_t push; UVM_ASSERT(!uvm_channel_is_proxy(channel)); - // WLC/LCIC channels can only process custom gpfifo entries before + // WLC/LCIC channels can only process custom GPFIFO entries before // their schedule is set up. UVM_ASSERT(!uvm_channel_is_lcic(channel) || !uvm_channel_manager_is_wlc_ready(channel->pool->manager)); UVM_ASSERT(!uvm_channel_is_wlc(channel) || !uvm_channel_manager_is_wlc_ready(channel->pool->manager)); @@ -1373,10 +1402,28 @@ NV_STATUS uvm_channel_write_ctrl_gpfifo(uvm_channel_t *channel, NvU64 ctrl_fifo_ if (status != NV_OK) return status; + if (g_uvm_global.conf_computing_enabled) { + // Rotating IV needs to idle the channel. However, there's no semaphore + // release after submitting a control entry. It is not possible to wait + // for in-flight entries after the GPFIFO submission. + // Instead, check for IV rotation early. Secure channels are locked for + // pushes after reservation so the IV space gained here can't be used + // up by concurrent pushes. + status = uvm_conf_computing_maybe_rotate_channel_ivs_retry_busy(channel); + if (status != NV_OK) { + uvm_channel_release(channel, 2); + return status; + } + } + write_ctrl_gpfifo(channel, ctrl_fifo_entry_value); status = uvm_push_begin_on_reserved_channel(channel, &push, "write_ctrl_GPFIFO"); if (status != NV_OK) { + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + + // One entry was consumed by GPFIFO entry + uvm_channel_release(channel, 1); UVM_ERR_PRINT("Failed to begin push on channel: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); return status; } @@ -1440,9 +1487,8 @@ NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries) { NV_STATUS status = NV_OK; uvm_spin_loop_t spin; - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return channel_reserve_and_lock(channel, num_gpfifo_entries); if (try_claim_channel(channel, num_gpfifo_entries)) @@ -1460,6 +1506,18 @@ NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries) return status; } +void uvm_channel_release(uvm_channel_t *channel, NvU32 num_gpfifo_entries) +{ + channel_pool_lock(channel->pool); + + UVM_ASSERT(uvm_channel_is_locked_for_push(channel)); + unlock_channel_for_push(channel); + + UVM_ASSERT(channel->current_gpfifo_count >= num_gpfifo_entries); + channel->current_gpfifo_count -= num_gpfifo_entries; + channel_pool_unlock(channel->pool); +} + // Get the first pending GPFIFO entry, if any. // This doesn't stop the entry from being reused. static uvm_gpfifo_entry_t *uvm_channel_get_first_pending_entry(uvm_channel_t *channel) @@ -1580,26 +1638,46 @@ NvU64 uvm_channel_update_completed_value(uvm_channel_t *channel) return uvm_gpu_tracking_semaphore_update_completed_value(&channel->tracking_sem); } +NV_STATUS uvm_channel_wait(uvm_channel_t *channel) +{ + NV_STATUS status = uvm_global_get_status(); + uvm_spin_loop_t spin; + + if (uvm_channel_update_progress(channel) == 0 && status == NV_OK) + return uvm_channel_check_errors(channel); + + uvm_spin_loop_init(&spin); + while (uvm_channel_update_progress(channel) > 0 && status == NV_OK) { + UVM_SPIN_LOOP(&spin); + status = uvm_global_get_status(); + + if (status == NV_OK) + status = uvm_channel_check_errors(channel); + } + + return status; +} + static NV_STATUS csl_init(uvm_channel_t *channel) { NV_STATUS status; - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); - uvm_mutex_init(&channel->csl.ctx_lock, UVM_LOCK_ORDER_LEAF); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); status = uvm_rm_locked_call(nvUvmInterfaceCslInitContext(&channel->csl.ctx, channel->handle)); - if (status == NV_OK) { - channel->csl.is_ctx_initialized = true; - } - else { + if (status != NV_OK) { + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); + UVM_DBG_PRINT("nvUvmInterfaceCslInitContext() failed: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); + return status; } - return status; + uvm_mutex_init(&channel->csl.ctx_lock, UVM_LOCK_ORDER_CSL_CTX); + channel->csl.is_ctx_initialized = true; + + return NV_OK; } static void csl_destroy(uvm_channel_t *channel) @@ -1608,7 +1686,7 @@ static void csl_destroy(uvm_channel_t *channel) return; uvm_assert_mutex_unlocked(&channel->csl.ctx_lock); - UVM_ASSERT(!is_channel_locked_for_push(channel)); + UVM_ASSERT(!uvm_channel_is_locked_for_push(channel)); uvm_rm_locked_call_void(nvUvmInterfaceDeinitCslContext(&channel->csl.ctx)); channel->csl.is_ctx_initialized = false; @@ -1616,9 +1694,7 @@ static void csl_destroy(uvm_channel_t *channel) static void free_conf_computing_buffers(uvm_channel_t *channel) { - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); UVM_ASSERT(uvm_channel_is_ce(channel)); uvm_rm_mem_free(channel->conf_computing.static_pb_protected_vidmem); @@ -1650,7 +1726,7 @@ static NV_STATUS alloc_conf_computing_buffers_semaphore(uvm_channel_t *channel) uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); NV_STATUS status; - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); UVM_ASSERT(uvm_channel_is_ce(channel)); status = uvm_rm_mem_alloc_and_map_cpu(gpu, @@ -1770,9 +1846,8 @@ static NV_STATUS alloc_conf_computing_buffers_lcic(uvm_channel_t *channel) static NV_STATUS alloc_conf_computing_buffers(uvm_channel_t *channel) { NV_STATUS status; - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); UVM_ASSERT(uvm_channel_is_ce(channel)); status = alloc_conf_computing_buffers_semaphore(channel); @@ -1786,6 +1861,7 @@ static NV_STATUS alloc_conf_computing_buffers(uvm_channel_t *channel) status = alloc_conf_computing_buffers_lcic(channel); } else { + uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); void *push_crypto_bundles = uvm_kvmalloc_zero(sizeof(*channel->conf_computing.push_crypto_bundles) * channel->num_gpfifo_entries); @@ -1806,8 +1882,6 @@ static NV_STATUS alloc_conf_computing_buffers(uvm_channel_t *channel) static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) { - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - UVM_ASSERT(pool->num_channels > 0); if (channel->tracking_sem.queued_value > 0) { @@ -1831,7 +1905,7 @@ static void channel_destroy(uvm_channel_pool_t *pool, uvm_channel_t *channel) uvm_kvfree(channel->gpfifo_entries); - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { csl_destroy(channel); if (uvm_channel_is_ce(channel)) @@ -1889,7 +1963,7 @@ static uvmGpuTsgHandle channel_get_tsg(uvm_channel_t *channel) if (uvm_channel_pool_is_wlc(pool) || uvm_channel_pool_is_lcic(pool)) { if (uvm_channel_pool_is_lcic(pool)) { - channel = lcic_get_paired_wlc(channel); + channel = uvm_channel_lcic_get_paired_wlc(channel); pool = channel->pool; } @@ -1906,7 +1980,6 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel) UvmGpuChannelAllocParams channel_alloc_params; UvmGpuChannelInfo *channel_info = &channel->channel_info; uvm_channel_manager_t *manager = channel->pool->manager; - uvm_gpu_t *gpu = manager->gpu; memset(&channel_alloc_params, 0, sizeof(channel_alloc_params)); channel_alloc_params.numGpFifoEntries = channel_pool_type_num_gpfifo_entries(manager, channel->pool->pool_type); @@ -1914,7 +1987,7 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel) channel_alloc_params.gpPutLoc = manager->conf.gpput_loc; if (uvm_channel_is_sec2(channel)) { - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); // SEC2 channels' GPPUT and GPFIFO must be allocated in sysmem. channel_alloc_params.gpFifoLoc = UVM_BUFFER_LOCATION_SYS; @@ -1928,7 +2001,7 @@ static NV_STATUS internal_channel_create(uvm_channel_t *channel) if (status != NV_OK) { UVM_ERR_PRINT("nvUvmInterfaceChannelAllocate() failed: %s, GPU %s, type %s\n", nvstatusToString(status), - uvm_gpu_name(gpu), + uvm_gpu_name(manager->gpu), uvm_channel_pool_type_to_string(channel->pool->pool_type)); return status; } @@ -1994,7 +2067,7 @@ static NV_STATUS channel_create(uvm_channel_pool_t *pool, uvm_channel_t *channel channel->tools.pending_event_count = 0; INIT_LIST_HEAD(&channel->tools.channel_list_node); - if (uvm_conf_computing_mode_enabled(gpu) && uvm_channel_is_ce(channel)) + if (g_uvm_global.conf_computing_enabled && uvm_channel_is_ce(channel)) semaphore_pool = gpu->secure_semaphore_pool; status = uvm_gpu_tracking_semaphore_alloc(semaphore_pool, &channel->tracking_sem); @@ -2020,7 +2093,7 @@ static NV_STATUS channel_create(uvm_channel_pool_t *pool, uvm_channel_t *channel goto error; } - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { status = csl_init(channel); if (status != NV_OK) goto error; @@ -2079,14 +2152,14 @@ static NV_STATUS channel_init(uvm_channel_t *channel) NV_STATUS status; NvU32 num_entries = 1; - if (uvm_gpu_has_pushbuffer_segments(gpu)) + if (uvm_parent_gpu_needs_pushbuffer_segments(gpu->parent)) num_entries++; status = uvm_channel_reserve(channel, num_entries); if (status != NV_OK) return status; - if (uvm_gpu_has_pushbuffer_segments(gpu)) { + if (uvm_parent_gpu_needs_pushbuffer_segments(gpu->parent)) { NvU64 gpfifo_entry; uvm_pushbuffer_t *pushbuffer = uvm_channel_get_pushbuffer(channel); NvU64 pb_base = uvm_pushbuffer_get_gpu_va_base(pushbuffer); @@ -2102,6 +2175,10 @@ static NV_STATUS channel_init(uvm_channel_t *channel) status = uvm_push_begin_on_reserved_channel(channel, &push, "Init channel"); if (status != NV_OK) { + + // One entry was consumed by control GPFIFO entry above, release the + // second one. + uvm_channel_release(channel, 1); UVM_ERR_PRINT("Failed to begin push on channel: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); return status; } @@ -2126,7 +2203,7 @@ static NV_STATUS channel_init(uvm_channel_t *channel) static bool channel_manager_uses_proxy_pool(uvm_channel_manager_t *manager) { - return uvm_gpu_is_virt_mode_sriov_heavy(manager->gpu); + return uvm_parent_gpu_is_virt_mode_sriov_heavy(manager->gpu->parent); } // Number of channels to create in a pool of the given type. @@ -2266,7 +2343,7 @@ static NV_STATUS channel_pool_add(uvm_channel_manager_t *channel_manager, num_channels = channel_pool_type_num_channels(pool_type); UVM_ASSERT(num_channels <= UVM_CHANNEL_MAX_NUM_CHANNELS_PER_POOL); - if (uvm_conf_computing_mode_enabled(channel_manager->gpu)) { + if (g_uvm_global.conf_computing_enabled) { // Use different order lock for SEC2 and WLC channels. // This allows reserving a SEC2 or WLC channel for indirect work // submission while holding a reservation for a channel. @@ -2721,11 +2798,11 @@ static unsigned channel_manager_get_max_pools(uvm_channel_manager_t *manager) num_channel_pools = bitmap_weight(manager->ce_mask, UVM_COPY_ENGINE_COUNT_MAX); // CE proxy channel pool. - if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) + if (uvm_parent_gpu_needs_proxy_channel_pool(manager->gpu->parent)) num_channel_pools++; // SEC2 pool, WLC pool, LCIC pool - if (uvm_conf_computing_mode_enabled(manager->gpu)) + if (g_uvm_global.conf_computing_enabled) num_channel_pools += 3; return num_channel_pools; @@ -3093,7 +3170,7 @@ static NV_STATUS channel_manager_create_conf_computing_pools(uvm_channel_manager uvm_channel_pool_t *wlc_pool = NULL; uvm_channel_pool_t *lcic_pool = NULL; - if (!uvm_conf_computing_mode_enabled(manager->gpu)) + if (!g_uvm_global.conf_computing_enabled) return NV_OK; status = uvm_rm_mem_alloc(manager->gpu, @@ -3173,7 +3250,7 @@ static NV_STATUS channel_manager_create_pools(uvm_channel_manager_t *manager) // In SR-IOV heavy, add an additional, single-channel, pool that is // dedicated to the MEMOPS type. - if (uvm_gpu_uses_proxy_channel_pool(manager->gpu)) { + if (uvm_parent_gpu_needs_proxy_channel_pool(manager->gpu->parent)) { uvm_channel_pool_t *proxy_pool = NULL; uvm_channel_type_t channel_type = uvm_channel_proxy_channel_type(); @@ -3295,7 +3372,7 @@ void uvm_channel_manager_destroy(uvm_channel_manager_t *channel_manager) bool uvm_channel_is_privileged(uvm_channel_t *channel) { - if (uvm_gpu_is_virt_mode_sriov_heavy(uvm_channel_get_gpu(channel))) + if (uvm_parent_gpu_is_virt_mode_sriov_heavy(uvm_channel_get_gpu(channel)->parent)) return uvm_channel_is_proxy(channel); return true; diff --git a/kernel-open/nvidia-uvm/uvm_channel.h b/kernel-open/nvidia-uvm/uvm_channel.h index b61239ba1b..854b8c6d90 100644 --- a/kernel-open/nvidia-uvm/uvm_channel.h +++ b/kernel-open/nvidia-uvm/uvm_channel.h @@ -497,6 +497,10 @@ static bool uvm_channel_is_lcic(uvm_channel_t *channel) return uvm_channel_pool_is_lcic(channel->pool); } +uvm_channel_t *uvm_channel_lcic_get_paired_wlc(uvm_channel_t *lcic_channel); + +uvm_channel_t *uvm_channel_wlc_get_paired_lcic(uvm_channel_t *wlc_channel); + static bool uvm_channel_pool_is_proxy(uvm_channel_pool_t *pool) { UVM_ASSERT(uvm_pool_type_is_valid(pool->pool_type)); @@ -603,6 +607,11 @@ bool uvm_channel_is_value_completed(uvm_channel_t *channel, NvU64 value); // Update and get the latest completed value by the channel NvU64 uvm_channel_update_completed_value(uvm_channel_t *channel); +// Wait for the channel to idle +// It waits for anything that is running, but doesn't prevent new work from +// beginning. +NV_STATUS uvm_channel_wait(uvm_channel_t *channel); + // Select and reserve a channel with the specified type for a push NV_STATUS uvm_channel_reserve_type(uvm_channel_manager_t *manager, uvm_channel_type_t type, @@ -617,6 +626,9 @@ NV_STATUS uvm_channel_reserve_gpu_to_gpu(uvm_channel_manager_t *channel_manager, // Reserve a specific channel for a push or for a control GPFIFO entry. NV_STATUS uvm_channel_reserve(uvm_channel_t *channel, NvU32 num_gpfifo_entries); +// Release reservation on a specific channel +void uvm_channel_release(uvm_channel_t *channel, NvU32 num_gpfifo_entries); + // Set optimal CE for P2P transfers between manager->gpu and peer void uvm_channel_manager_set_p2p_ce(uvm_channel_manager_t *manager, uvm_gpu_t *peer, NvU32 optimal_ce); @@ -648,6 +660,8 @@ NvU32 uvm_channel_get_available_gpfifo_entries(uvm_channel_t *channel); void uvm_channel_print_pending_pushes(uvm_channel_t *channel); +bool uvm_channel_is_locked_for_push(uvm_channel_t *channel); + static uvm_gpu_t *uvm_channel_get_gpu(uvm_channel_t *channel) { return channel->pool->manager->gpu; diff --git a/kernel-open/nvidia-uvm/uvm_channel_test.c b/kernel-open/nvidia-uvm/uvm_channel_test.c index c4521d2284..88641e20a3 100644 --- a/kernel-open/nvidia-uvm/uvm_channel_test.c +++ b/kernel-open/nvidia-uvm/uvm_channel_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -24,6 +24,7 @@ #include "uvm_global.h" #include "uvm_channel.h" #include "uvm_hal.h" +#include "uvm_mem.h" #include "uvm_push.h" #include "uvm_test.h" #include "uvm_test_rng.h" @@ -57,14 +58,14 @@ static NV_STATUS test_ordering(uvm_va_space_t *va_space) const NvU32 values_count = iters_per_channel_type_per_gpu; const size_t buffer_size = sizeof(NvU32) * values_count; - gpu = uvm_va_space_find_first_gpu(va_space); - TEST_CHECK_RET(gpu != NULL); - // TODO: Bug 3839176: the test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; + gpu = uvm_va_space_find_first_gpu(va_space); + TEST_CHECK_RET(gpu != NULL); + status = uvm_rm_mem_alloc_and_map_all(gpu, UVM_RM_MEM_TYPE_SYS, buffer_size, 0, &mem); TEST_CHECK_GOTO(status == NV_OK, done); @@ -84,7 +85,7 @@ static NV_STATUS test_ordering(uvm_va_space_t *va_space) TEST_NV_CHECK_GOTO(uvm_tracker_add_push(&tracker, &push), done); - exclude_proxy_channel_type = uvm_gpu_uses_proxy_channel_pool(gpu); + exclude_proxy_channel_type = uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent); for (i = 0; i < iters_per_channel_type_per_gpu; ++i) { for (j = 0; j < UVM_CHANNEL_TYPE_CE_COUNT; ++j) { @@ -222,7 +223,7 @@ static NV_STATUS uvm_test_rc_for_gpu(uvm_gpu_t *gpu) // Check RC on a proxy channel (SR-IOV heavy) or internal channel (any other // mode). It is not allowed to use a virtual address in a memset pushed to // a proxy channel, so we use a physical address instead. - if (uvm_gpu_uses_proxy_channel_pool(gpu)) { + if (uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)) { uvm_gpu_address_t dst_address; // Save the line number the push that's supposed to fail was started on @@ -314,6 +315,110 @@ static NV_STATUS test_rc(uvm_va_space_t *va_space) return NV_OK; } +static NV_STATUS uvm_test_iommu_rc_for_gpu(uvm_gpu_t *gpu) +{ + NV_STATUS status = NV_OK; + +#if defined(NV_IOMMU_IS_DMA_DOMAIN_PRESENT) && defined(CONFIG_IOMMU_DEFAULT_DMA_STRICT) + // This test needs the DMA API to immediately invalidate IOMMU mappings on + // DMA unmap (as apposed to lazy invalidation). The policy can be changed + // on boot (e.g. iommu.strict=1), but there isn't a good way to check for + // the runtime setting. CONFIG_IOMMU_DEFAULT_DMA_STRICT checks for the + // default value. + + uvm_push_t push; + uvm_mem_t *sysmem; + uvm_gpu_address_t sysmem_dma_addr; + char *cpu_ptr = NULL; + const size_t data_size = PAGE_SIZE; + size_t i; + + struct device *dev = &gpu->parent->pci_dev->dev; + struct iommu_domain *domain = iommu_get_domain_for_dev(dev); + + // Check that the iommu domain is controlled by linux DMA API + if (!domain || !iommu_is_dma_domain(domain)) + return NV_OK; + + // Only run if ATS is enabled. Otherwise the CE doesn't get response on + // writing to unmapped location. + if (!g_uvm_global.ats.enabled) + return NV_OK; + + status = uvm_mem_alloc_sysmem_and_map_cpu_kernel(data_size, NULL, &sysmem); + TEST_NV_CHECK_RET(status); + + status = uvm_mem_map_gpu_phys(sysmem, gpu); + TEST_NV_CHECK_GOTO(status, done); + + cpu_ptr = uvm_mem_get_cpu_addr_kernel(sysmem); + sysmem_dma_addr = uvm_mem_gpu_address_physical(sysmem, gpu, 0, data_size); + + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, &push, "Test memset to IOMMU mapped sysmem"); + TEST_NV_CHECK_GOTO(status, done); + + gpu->parent->ce_hal->memset_8(&push, sysmem_dma_addr, 0, data_size); + + status = uvm_push_end_and_wait(&push); + TEST_NV_CHECK_GOTO(status, done); + + // Check that we have zeroed the memory + for (i = 0; i < data_size; ++i) + TEST_CHECK_GOTO(cpu_ptr[i] == 0, done); + + // Unmap the buffer and try write again to the same address + uvm_mem_unmap_gpu_phys(sysmem, gpu); + + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, &push, "Test memset after IOMMU unmap"); + TEST_NV_CHECK_GOTO(status, done); + + gpu->parent->ce_hal->memset_4(&push, sysmem_dma_addr, 0xffffffff, data_size); + + status = uvm_push_end_and_wait(&push); + + TEST_CHECK_GOTO(status == NV_ERR_RC_ERROR, done); + TEST_CHECK_GOTO(uvm_channel_get_status(push.channel) == NV_ERR_RC_ERROR, done); + TEST_CHECK_GOTO(uvm_global_reset_fatal_error() == NV_ERR_RC_ERROR, done); + + // Check that writes after unmap did not succeed + for (i = 0; i < data_size; ++i) + TEST_CHECK_GOTO(cpu_ptr[i] == 0, done); + + status = NV_OK; + +done: + uvm_mem_free(sysmem); +#endif + return status; +} + +static NV_STATUS test_iommu(uvm_va_space_t *va_space) +{ + uvm_gpu_t *gpu; + + uvm_assert_mutex_locked(&g_uvm_global.global_lock); + + for_each_va_space_gpu(gpu, va_space) { + NV_STATUS test_status, create_status; + + // The GPU channel manager is destroyed and then re-created after + // testing ATS RC fault, so this test requires exclusive access to the GPU. + TEST_CHECK_RET(uvm_gpu_retained_count(gpu) == 1); + + g_uvm_global.disable_fatal_error_assert = true; + test_status = uvm_test_iommu_rc_for_gpu(gpu); + g_uvm_global.disable_fatal_error_assert = false; + + uvm_channel_manager_destroy(gpu->channel_manager); + create_status = uvm_channel_manager_create(gpu, &gpu->channel_manager); + + TEST_NV_CHECK_RET(test_status); + TEST_NV_CHECK_RET(create_status); + } + + return NV_OK; +} + typedef struct { uvm_push_t push; @@ -403,7 +508,7 @@ static uvm_channel_type_t random_ce_channel_type_except(uvm_test_rng_t *rng, uvm static uvm_channel_type_t gpu_random_internal_ce_channel_type(uvm_gpu_t *gpu, uvm_test_rng_t *rng) { - if (uvm_gpu_uses_proxy_channel_pool(gpu)) + if (uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)) return random_ce_channel_type_except(rng, uvm_channel_proxy_channel_type()); return random_ce_channel_type(rng); @@ -693,9 +798,7 @@ NV_STATUS test_conf_computing_channel_selection(uvm_va_space_t *va_space) NvU32 i; NvU32 num_pushes; - gpu = uvm_va_space_find_first_gpu(va_space); - - if (!uvm_conf_computing_mode_enabled(gpu)) + if (!g_uvm_global.conf_computing_enabled) return NV_OK; uvm_thread_context_lock_disable_tracking(); @@ -746,6 +849,101 @@ NV_STATUS test_conf_computing_channel_selection(uvm_va_space_t *va_space) return status; } +NV_STATUS test_channel_iv_rotation(uvm_va_space_t *va_space) +{ + uvm_gpu_t *gpu; + + if (!g_uvm_global.conf_computing_enabled) + return NV_OK; + + for_each_va_space_gpu(gpu, va_space) { + uvm_channel_pool_t *pool; + + uvm_for_each_pool(pool, gpu->channel_manager) { + NvU64 before_rotation_enc, before_rotation_dec, after_rotation_enc, after_rotation_dec; + NV_STATUS status = NV_OK; + + // Check one (the first) channel per pool + uvm_channel_t *channel = pool->channels; + + // Create a dummy encrypt/decrypt push to use few IVs. + // SEC2 used encrypt during initialization, no need to use a dummy + // push. + if (!uvm_channel_is_sec2(channel)) { + uvm_push_t push; + size_t data_size; + uvm_conf_computing_dma_buffer_t *cipher_text; + void *cipher_cpu_va, *plain_cpu_va, *tag_cpu_va; + uvm_gpu_address_t cipher_gpu_address, plain_gpu_address, tag_gpu_address; + uvm_channel_t *work_channel = uvm_channel_is_lcic(channel) ? uvm_channel_lcic_get_paired_wlc(channel) : channel; + + plain_cpu_va = &status; + data_size = sizeof(status); + + TEST_NV_CHECK_RET(uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, + &cipher_text, + NULL)); + cipher_cpu_va = uvm_mem_get_cpu_addr_kernel(cipher_text->alloc); + tag_cpu_va = uvm_mem_get_cpu_addr_kernel(cipher_text->auth_tag); + + cipher_gpu_address = uvm_mem_gpu_address_virtual_kernel(cipher_text->alloc, gpu); + tag_gpu_address = uvm_mem_gpu_address_virtual_kernel(cipher_text->auth_tag, gpu); + + TEST_NV_CHECK_GOTO(uvm_push_begin_on_channel(work_channel, &push, "Dummy push for IV rotation"), free); + + (void)uvm_push_get_single_inline_buffer(&push, + data_size, + UVM_CONF_COMPUTING_BUF_ALIGNMENT, + &plain_gpu_address); + + uvm_conf_computing_cpu_encrypt(work_channel, cipher_cpu_va, plain_cpu_va, NULL, data_size, tag_cpu_va); + gpu->parent->ce_hal->decrypt(&push, plain_gpu_address, cipher_gpu_address, data_size, tag_gpu_address); + + TEST_NV_CHECK_GOTO(uvm_push_end_and_wait(&push), free); + +free: + uvm_conf_computing_dma_buffer_free(&gpu->conf_computing.dma_buffer_pool, cipher_text, NULL); + + if (status != NV_OK) + return status; + } + + // Reserve a channel to hold the push lock during rotation + if (!uvm_channel_is_lcic(channel)) + TEST_NV_CHECK_RET(uvm_channel_reserve(channel, 1)); + + uvm_conf_computing_query_message_pools(channel, &before_rotation_enc, &before_rotation_dec); + TEST_NV_CHECK_GOTO(uvm_conf_computing_rotate_channel_ivs_below_limit(channel, -1, true), release); + uvm_conf_computing_query_message_pools(channel, &after_rotation_enc, &after_rotation_dec); + +release: + if (!uvm_channel_is_lcic(channel)) + uvm_channel_release(channel, 1); + + if (status != NV_OK) + return status; + + // All channels except SEC2 used at least a single IV to release tracking. + // SEC2 doesn't support decrypt direction. + if (uvm_channel_is_sec2(channel)) + TEST_CHECK_RET(before_rotation_dec == after_rotation_dec); + else + TEST_CHECK_RET(before_rotation_dec < after_rotation_dec); + + // All channels used one CPU encrypt/GPU decrypt, either during + // initialization or in the push above, with the exception of LCIC. + // LCIC is used in tandem with WLC, but it never uses CPU encrypt/ + // GPU decrypt ops. + if (uvm_channel_is_lcic(channel)) + TEST_CHECK_RET(before_rotation_enc == after_rotation_enc); + else + TEST_CHECK_RET(before_rotation_enc < after_rotation_enc); + } + } + + return NV_OK; +} + NV_STATUS test_write_ctrl_gpfifo_noop(uvm_va_space_t *va_space) { uvm_gpu_t *gpu; @@ -845,11 +1043,9 @@ NV_STATUS test_write_ctrl_gpfifo_tight(uvm_va_space_t *va_space) NvU64 entry; uvm_push_t push; - gpu = uvm_va_space_find_first_gpu(va_space); - // TODO: Bug 3839176: the test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; for_each_va_space_gpu(gpu, va_space) { @@ -924,7 +1120,7 @@ static NV_STATUS test_channel_pushbuffer_extension_base(uvm_va_space_t *va_space uvm_channel_manager_t *manager; uvm_channel_pool_t *pool; - if (!uvm_gpu_has_pushbuffer_segments(gpu)) + if (!uvm_parent_gpu_needs_pushbuffer_segments(gpu->parent)) continue; // The GPU channel manager pushbuffer is destroyed and then re-created @@ -999,6 +1195,10 @@ NV_STATUS uvm_test_channel_sanity(UVM_TEST_CHANNEL_SANITY_PARAMS *params, struct if (status != NV_OK) goto done; + status = test_channel_iv_rotation(va_space); + if (status != NV_OK) + goto done; + // The following tests have side effects, they reset the GPU's // channel_manager. status = test_channel_pushbuffer_extension_base(va_space); @@ -1019,6 +1219,10 @@ NV_STATUS uvm_test_channel_sanity(UVM_TEST_CHANNEL_SANITY_PARAMS *params, struct goto done; } + status = test_iommu(va_space); + if (status != NV_OK) + goto done; + done: uvm_va_space_up_read_rm(va_space); uvm_mutex_unlock(&g_uvm_global.global_lock); @@ -1034,23 +1238,22 @@ static NV_STATUS uvm_test_channel_stress_stream(uvm_va_space_t *va_space, if (params->iterations == 0 || params->num_streams == 0) return NV_ERR_INVALID_PARAMETER; + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (g_uvm_global.conf_computing_enabled) + return NV_OK; + // TODO: Bug 1764963: Rework the test to not rely on the global lock as that // serializes all the threads calling this at the same time. uvm_mutex_lock(&g_uvm_global.global_lock); uvm_va_space_down_read_rm(va_space); - // TODO: Bug 3839176: the test is waived on Confidential Computing because - // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(uvm_va_space_find_first_gpu(va_space))) - goto done; - status = stress_test_all_gpus_in_va(va_space, params->num_streams, params->iterations, params->seed, params->verbose); -done: uvm_va_space_up_read_rm(va_space); uvm_mutex_unlock(&g_uvm_global.global_lock); diff --git a/kernel-open/nvidia-uvm/uvm_common.h b/kernel-open/nvidia-uvm/uvm_common.h index cfc58b6fb1..a0c0d5a707 100644 --- a/kernel-open/nvidia-uvm/uvm_common.h +++ b/kernel-open/nvidia-uvm/uvm_common.h @@ -21,8 +21,8 @@ *******************************************************************************/ -#ifndef _UVM_COMMON_H -#define _UVM_COMMON_H +#ifndef __UVM_COMMON_H__ +#define __UVM_COMMON_H__ #ifdef DEBUG #define UVM_IS_DEBUG() 1 @@ -204,13 +204,6 @@ extern bool uvm_release_asserts_set_global_error_for_tests; #define UVM_ASSERT_MSG_RELEASE(expr, fmt, ...) _UVM_ASSERT_MSG_RELEASE(expr, #expr, ": " fmt, ##__VA_ARGS__) #define UVM_ASSERT_RELEASE(expr) _UVM_ASSERT_MSG_RELEASE(expr, #expr, "\n") -// Provide a short form of UUID's, typically for use in debug printing: -#define ABBREV_UUID(uuid) (unsigned)(uuid) - -static inline NvBool uvm_uuid_is_cpu(const NvProcessorUuid *uuid) -{ - return memcmp(uuid, &NV_PROCESSOR_UUID_CPU_DEFAULT, sizeof(*uuid)) == 0; -} #define UVM_SIZE_1KB (1024ULL) #define UVM_SIZE_1MB (1024 * UVM_SIZE_1KB) #define UVM_SIZE_1GB (1024 * UVM_SIZE_1MB) @@ -409,4 +402,40 @@ static inline void uvm_touch_page(struct page *page) // Return true if the VMA is one used by UVM managed allocations. bool uvm_vma_is_managed(struct vm_area_struct *vma); -#endif /* _UVM_COMMON_H */ +static bool uvm_platform_uses_canonical_form_address(void) +{ + if (NVCPU_IS_PPC64LE) + return false; + + return true; +} + +// Similar to the GPU MMU HAL num_va_bits(), it returns the CPU's num_va_bits(). +static NvU32 uvm_cpu_num_va_bits(void) +{ + return fls64(TASK_SIZE - 1) + 1; +} + +// Return the unaddressable range in a num_va_bits-wide VA space, [first, outer) +static void uvm_get_unaddressable_range(NvU32 num_va_bits, NvU64 *first, NvU64 *outer) +{ + UVM_ASSERT(num_va_bits < 64); + UVM_ASSERT(first); + UVM_ASSERT(outer); + + if (uvm_platform_uses_canonical_form_address()) { + *first = 1ULL << (num_va_bits - 1); + *outer = (NvU64)((NvS64)(1ULL << 63) >> (64 - num_va_bits)); + } + else { + *first = 1ULL << num_va_bits; + *outer = ~0Ull; + } +} + +static void uvm_cpu_get_unaddressable_range(NvU64 *first, NvU64 *outer) +{ + return uvm_get_unaddressable_range(uvm_cpu_num_va_bits(), first, outer); +} + +#endif /* __UVM_COMMON_H__ */ diff --git a/kernel-open/nvidia-uvm/uvm_conf_computing.c b/kernel-open/nvidia-uvm/uvm_conf_computing.c index 4927948d90..556eb9ed31 100644 --- a/kernel-open/nvidia-uvm/uvm_conf_computing.c +++ b/kernel-open/nvidia-uvm/uvm_conf_computing.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2021 NVIDIA Corporation + Copyright (c) 2021-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,20 +33,32 @@ #include "nv_uvm_interface.h" #include "uvm_va_block.h" +// The maximum number of secure operations per push is: +// UVM_MAX_PUSH_SIZE / min(CE encryption size, CE decryption size) +// + 1 (tracking semaphore) = 128 * 1024 / 56 + 1 = 2342 +#define UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_MIN 2342lu -static UvmGpuConfComputeMode uvm_conf_computing_get_mode(const uvm_parent_gpu_t *parent) -{ - return parent->rm_info.gpuConfComputeCaps.mode; -} +// Channels use 32-bit counters so the value after rotation is 0xffffffff. +// setting the limit to this value (or higher) will result in rotation +// on every check. However, pre-emptive rotation when submitting control +// GPFIFO entries relies on the fact that multiple successive checks after +// rotation do not trigger more rotations if there was no IV used in between. +#define UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_MAX 0xfffffffelu -bool uvm_conf_computing_mode_enabled_parent(const uvm_parent_gpu_t *parent) -{ - return uvm_conf_computing_get_mode(parent) != UVM_GPU_CONF_COMPUTE_MODE_NONE; -} +// Attempt rotation when two billion IVs are left. IV rotation call can fail if +// the necessary locks are not available, so multiple attempts may be need for +// IV rotation to succeed. +#define UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_DEFAULT (1lu << 31) + +// Start rotating after 500 encryption/decryptions when running tests. +#define UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_TESTS ((1lu << 32) - 500lu) +static ulong uvm_conf_computing_channel_iv_rotation_limit = UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_DEFAULT; -bool uvm_conf_computing_mode_enabled(const uvm_gpu_t *gpu) +module_param(uvm_conf_computing_channel_iv_rotation_limit, ulong, S_IRUGO); + +static UvmGpuConfComputeMode uvm_conf_computing_get_mode(const uvm_parent_gpu_t *parent) { - return uvm_conf_computing_mode_enabled_parent(gpu->parent); + return parent->rm_info.gpuConfComputeCaps.mode; } bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu) @@ -54,23 +66,22 @@ bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu) return uvm_conf_computing_get_mode(gpu->parent) == UVM_GPU_CONF_COMPUTE_MODE_HCC; } -NV_STATUS uvm_conf_computing_init_parent_gpu(const uvm_parent_gpu_t *parent) +void uvm_conf_computing_check_parent_gpu(const uvm_parent_gpu_t *parent) { - UvmGpuConfComputeMode cc, sys_cc; - uvm_gpu_t *first; + uvm_parent_gpu_t *other_parent; + UvmGpuConfComputeMode parent_mode = uvm_conf_computing_get_mode(parent); uvm_assert_mutex_locked(&g_uvm_global.global_lock); - // TODO: Bug 2844714: since we have no routine to traverse parent GPUs, - // find first child GPU and get its parent. - first = uvm_global_processor_mask_find_first_gpu(&g_uvm_global.retained_gpus); - if (!first) - return NV_OK; - - sys_cc = uvm_conf_computing_get_mode(first->parent); - cc = uvm_conf_computing_get_mode(parent); + // The Confidential Computing state of the GPU should match that of the + // system. + UVM_ASSERT((parent_mode != UVM_GPU_CONF_COMPUTE_MODE_NONE) == g_uvm_global.conf_computing_enabled); - return cc == sys_cc ? NV_OK : NV_ERR_NOT_SUPPORTED; + // All GPUs derive Confidential Computing status from their parent. By + // current policy all parent GPUs have identical Confidential Computing + // status. + for_each_parent_gpu(other_parent) + UVM_ASSERT(parent_mode == uvm_conf_computing_get_mode(other_parent)); } static void dma_buffer_destroy_locked(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool, @@ -184,15 +195,11 @@ static void dma_buffer_pool_add(uvm_conf_computing_dma_buffer_pool_t *dma_buffer static NV_STATUS conf_computing_dma_buffer_pool_init(uvm_conf_computing_dma_buffer_pool_t *dma_buffer_pool) { size_t i; - uvm_gpu_t *gpu; size_t num_dma_buffers = 32; NV_STATUS status = NV_OK; UVM_ASSERT(dma_buffer_pool->num_dma_buffers == 0); - - gpu = dma_buffer_pool_to_gpu(dma_buffer_pool); - - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); INIT_LIST_HEAD(&dma_buffer_pool->free_dma_buffers); uvm_mutex_init(&dma_buffer_pool->lock, UVM_LOCK_ORDER_CONF_COMPUTING_DMA_BUFFER_POOL); @@ -349,7 +356,7 @@ NV_STATUS uvm_conf_computing_gpu_init(uvm_gpu_t *gpu) { NV_STATUS status; - if (!uvm_conf_computing_mode_enabled(gpu)) + if (!g_uvm_global.conf_computing_enabled) return NV_OK; status = conf_computing_dma_buffer_pool_init(&gpu->conf_computing.dma_buffer_pool); @@ -360,6 +367,20 @@ NV_STATUS uvm_conf_computing_gpu_init(uvm_gpu_t *gpu) if (status != NV_OK) goto error; + if (uvm_enable_builtin_tests && uvm_conf_computing_channel_iv_rotation_limit == UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_DEFAULT) + uvm_conf_computing_channel_iv_rotation_limit = UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_TESTS; + + if (uvm_conf_computing_channel_iv_rotation_limit < UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_MIN || + uvm_conf_computing_channel_iv_rotation_limit > UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_MAX) { + UVM_ERR_PRINT("Value of uvm_conf_computing_channel_iv_rotation_limit: %lu is outside of the safe " + "range: <%lu, %lu>. Using the default value instead (%lu)\n", + uvm_conf_computing_channel_iv_rotation_limit, + UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_MIN, + UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_MAX, + UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_DEFAULT); + uvm_conf_computing_channel_iv_rotation_limit = UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_DEFAULT; + } + return NV_OK; error: @@ -381,9 +402,8 @@ void uvm_conf_computing_log_gpu_encryption(uvm_channel_t *channel, UvmCslIv *iv) status = nvUvmInterfaceCslIncrementIv(&channel->csl.ctx, UVM_CSL_OPERATION_DECRYPT, 1, iv); uvm_mutex_unlock(&channel->csl.ctx_lock); - // TODO: Bug 4014720: If nvUvmInterfaceCslIncrementIv returns with - // NV_ERR_INSUFFICIENT_RESOURCES then the IV needs to be rotated via - // nvUvmInterfaceCslRotateIv. + // IV rotation is done preemptively as needed, so the above + // call cannot return failure. UVM_ASSERT(status == NV_OK); } @@ -395,9 +415,8 @@ void uvm_conf_computing_acquire_encryption_iv(uvm_channel_t *channel, UvmCslIv * status = nvUvmInterfaceCslIncrementIv(&channel->csl.ctx, UVM_CSL_OPERATION_ENCRYPT, 1, iv); uvm_mutex_unlock(&channel->csl.ctx_lock); - // TODO: Bug 4014720: If nvUvmInterfaceCslIncrementIv returns with - // NV_ERR_INSUFFICIENT_RESOURCES then the IV needs to be rotated via - // nvUvmInterfaceCslRotateIv. + // IV rotation is done preemptively as needed, so the above + // call cannot return failure. UVM_ASSERT(status == NV_OK); } @@ -421,8 +440,8 @@ void uvm_conf_computing_cpu_encrypt(uvm_channel_t *channel, (NvU8 *) auth_tag_buffer); uvm_mutex_unlock(&channel->csl.ctx_lock); - // nvUvmInterfaceCslEncrypt fails when a 64-bit encryption counter - // overflows. This is not supposed to happen on CC. + // IV rotation is done preemptively as needed, so the above + // call cannot return failure. UVM_ASSERT(status == NV_OK); } @@ -435,6 +454,16 @@ NV_STATUS uvm_conf_computing_cpu_decrypt(uvm_channel_t *channel, { NV_STATUS status; + // The CSL context associated with a channel can be used by multiple + // threads. The IV sequence is thus guaranteed only while the channel is + // "locked for push". The channel/push lock is released in + // "uvm_channel_end_push", and at that time the GPU encryption operations + // have not executed, yet. Therefore the caller has to use + // "uvm_conf_computing_log_gpu_encryption" to explicitly store IVs needed + // to perform CPU decryption and pass those IVs to this function after the + // push that did the encryption completes. + UVM_ASSERT(src_iv); + uvm_mutex_lock(&channel->csl.ctx_lock); status = nvUvmInterfaceCslDecrypt(&channel->csl.ctx, size, @@ -463,7 +492,7 @@ NV_STATUS uvm_conf_computing_fault_decrypt(uvm_parent_gpu_t *parent_gpu, // decryption is invoked as part of fault servicing. UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); - UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); status = nvUvmInterfaceCslDecrypt(&parent_gpu->fault_buffer_info.rm_info.replayable.cslCtx, parent_gpu->fault_buffer_hal->entry_size(parent_gpu), @@ -475,7 +504,9 @@ NV_STATUS uvm_conf_computing_fault_decrypt(uvm_parent_gpu_t *parent_gpu, (const NvU8 *) auth_tag_buffer); if (status != NV_OK) - UVM_ERR_PRINT("nvUvmInterfaceCslDecrypt() failed: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); + UVM_ERR_PRINT("nvUvmInterfaceCslDecrypt() failed: %s, GPU %s\n", + nvstatusToString(status), + uvm_parent_gpu_name(parent_gpu)); return status; } @@ -487,7 +518,7 @@ void uvm_conf_computing_fault_increment_decrypt_iv(uvm_parent_gpu_t *parent_gpu, // See comment in uvm_conf_computing_fault_decrypt UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); - UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); status = nvUvmInterfaceCslIncrementIv(&parent_gpu->fault_buffer_info.rm_info.replayable.cslCtx, UVM_CSL_OPERATION_DECRYPT, @@ -496,3 +527,101 @@ void uvm_conf_computing_fault_increment_decrypt_iv(uvm_parent_gpu_t *parent_gpu, UVM_ASSERT(status == NV_OK); } + +void uvm_conf_computing_query_message_pools(uvm_channel_t *channel, + NvU64 *remaining_encryptions, + NvU64 *remaining_decryptions) +{ + NV_STATUS status; + + UVM_ASSERT(channel); + UVM_ASSERT(remaining_encryptions); + UVM_ASSERT(remaining_decryptions); + + uvm_mutex_lock(&channel->csl.ctx_lock); + status = nvUvmInterfaceCslQueryMessagePool(&channel->csl.ctx, UVM_CSL_OPERATION_ENCRYPT, remaining_encryptions); + UVM_ASSERT(status == NV_OK); + UVM_ASSERT(*remaining_encryptions <= NV_U32_MAX); + + status = nvUvmInterfaceCslQueryMessagePool(&channel->csl.ctx, UVM_CSL_OPERATION_DECRYPT, remaining_decryptions); + UVM_ASSERT(status == NV_OK); + UVM_ASSERT(*remaining_decryptions <= NV_U32_MAX); + + // LCIC channels never use CPU encrypt/GPU decrypt + if (uvm_channel_is_lcic(channel)) + UVM_ASSERT(*remaining_encryptions == NV_U32_MAX); + + uvm_mutex_unlock(&channel->csl.ctx_lock); +} + +static NV_STATUS uvm_conf_computing_rotate_channel_ivs_below_limit_internal(uvm_channel_t *channel, NvU64 limit) +{ + NV_STATUS status = NV_OK; + NvU64 remaining_encryptions, remaining_decryptions; + bool rotate_encryption_iv, rotate_decryption_iv; + + UVM_ASSERT(uvm_channel_is_locked_for_push(channel) || + (uvm_channel_is_lcic(channel) && uvm_channel_manager_is_wlc_ready(channel->pool->manager))); + + uvm_conf_computing_query_message_pools(channel, &remaining_encryptions, &remaining_decryptions); + + // Ignore decryption limit for SEC2, only CE channels support + // GPU encrypt/CPU decrypt. However, RM reports _some_ decrementing + // value for SEC2 decryption counter. + rotate_decryption_iv = (remaining_decryptions <= limit) && uvm_channel_is_ce(channel); + rotate_encryption_iv = remaining_encryptions <= limit; + + if (!rotate_encryption_iv && !rotate_decryption_iv) + return NV_OK; + + // Wait for all in-flight pushes. The caller needs to guarantee that there + // are no concurrent pushes created, e.g. by only calling rotate after + // a channel is locked_for_push. + status = uvm_channel_wait(channel); + if (status != NV_OK) + return status; + + uvm_mutex_lock(&channel->csl.ctx_lock); + + if (rotate_encryption_iv) + status = nvUvmInterfaceCslRotateIv(&channel->csl.ctx, UVM_CSL_OPERATION_ENCRYPT); + + if (status == NV_OK && rotate_decryption_iv) + status = nvUvmInterfaceCslRotateIv(&channel->csl.ctx, UVM_CSL_OPERATION_DECRYPT); + + uvm_mutex_unlock(&channel->csl.ctx_lock); + + // Change the error to out of resources if the available IVs are running + // too low + if (status == NV_ERR_STATE_IN_USE && + (remaining_encryptions < UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_MIN || + remaining_decryptions < UVM_CONF_COMPUTING_IV_REMAINING_LIMIT_MIN)) + return NV_ERR_INSUFFICIENT_RESOURCES; + + return status; +} + +NV_STATUS uvm_conf_computing_rotate_channel_ivs_below_limit(uvm_channel_t *channel, NvU64 limit, bool retry_if_busy) +{ + NV_STATUS status; + + do { + status = uvm_conf_computing_rotate_channel_ivs_below_limit_internal(channel, limit); + } while (retry_if_busy && status == NV_ERR_STATE_IN_USE); + + // Hide "busy" error. The rotation will be retried at the next opportunity. + if (!retry_if_busy && status == NV_ERR_STATE_IN_USE) + status = NV_OK; + + return status; +} + +NV_STATUS uvm_conf_computing_maybe_rotate_channel_ivs(uvm_channel_t *channel) +{ + return uvm_conf_computing_rotate_channel_ivs_below_limit(channel, uvm_conf_computing_channel_iv_rotation_limit, false); +} + +NV_STATUS uvm_conf_computing_maybe_rotate_channel_ivs_retry_busy(uvm_channel_t *channel) +{ + return uvm_conf_computing_rotate_channel_ivs_below_limit(channel, uvm_conf_computing_channel_iv_rotation_limit, true); +} diff --git a/kernel-open/nvidia-uvm/uvm_conf_computing.h b/kernel-open/nvidia-uvm/uvm_conf_computing.h index 99b6d96276..f464d83814 100644 --- a/kernel-open/nvidia-uvm/uvm_conf_computing.h +++ b/kernel-open/nvidia-uvm/uvm_conf_computing.h @@ -60,12 +60,8 @@ // UVM_METHOD_SIZE * 2 * 10 = 80. #define UVM_CONF_COMPUTING_SIGN_BUF_MAX_SIZE 80 -// All GPUs derive confidential computing status from their parent. -// By current policy all parent GPUs have identical confidential -// computing status. -NV_STATUS uvm_conf_computing_init_parent_gpu(const uvm_parent_gpu_t *parent); -bool uvm_conf_computing_mode_enabled_parent(const uvm_parent_gpu_t *parent); -bool uvm_conf_computing_mode_enabled(const uvm_gpu_t *gpu); +void uvm_conf_computing_check_parent_gpu(const uvm_parent_gpu_t *parent); + bool uvm_conf_computing_mode_is_hcc(const uvm_gpu_t *gpu); typedef struct @@ -201,4 +197,21 @@ NV_STATUS uvm_conf_computing_fault_decrypt(uvm_parent_gpu_t *parent_gpu, // // Locking: this function must be invoked while holding the replayable ISR lock. void uvm_conf_computing_fault_increment_decrypt_iv(uvm_parent_gpu_t *parent_gpu, NvU64 increment); + +// Query the number of remaining messages before IV needs to be rotated. +void uvm_conf_computing_query_message_pools(uvm_channel_t *channel, + NvU64 *remaining_encryptions, + NvU64 *remaining_decryptions); + +// Check if there are more than uvm_conf_computing_channel_iv_rotation_limit +// messages available in the channel and try to rotate if not. +NV_STATUS uvm_conf_computing_maybe_rotate_channel_ivs(uvm_channel_t *channel); + +// Check if there are more than uvm_conf_computing_channel_iv_rotation_limit +// messages available in the channel and rotate if not. +NV_STATUS uvm_conf_computing_maybe_rotate_channel_ivs_retry_busy(uvm_channel_t *channel); + +// Check if there are fewer than 'limit' messages available in either direction +// and rotate if not. +NV_STATUS uvm_conf_computing_rotate_channel_ivs_below_limit(uvm_channel_t *channel, NvU64 limit, bool retry_if_busy); #endif // __UVM_CONF_COMPUTING_H__ diff --git a/kernel-open/nvidia-uvm/uvm_fault_buffer_flush_test.c b/kernel-open/nvidia-uvm/uvm_fault_buffer_flush_test.c index d300650cef..d3739afdf9 100644 --- a/kernel-open/nvidia-uvm/uvm_fault_buffer_flush_test.c +++ b/kernel-open/nvidia-uvm/uvm_fault_buffer_flush_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -34,23 +34,24 @@ NV_STATUS uvm_test_fault_buffer_flush(UVM_TEST_FAULT_BUFFER_FLUSH_PARAMS *params NV_STATUS status = NV_OK; uvm_va_space_t *va_space = uvm_va_space_get(filp); uvm_gpu_t *gpu; - uvm_global_processor_mask_t retained_gpus; + uvm_processor_mask_t *retained_gpus; NvU64 i; - uvm_global_processor_mask_zero(&retained_gpus); + retained_gpus = uvm_processor_mask_cache_alloc(); + if (!retained_gpus) + return NV_ERR_NO_MEMORY; + + uvm_processor_mask_zero(retained_gpus); uvm_va_space_down_read(va_space); - for_each_va_space_gpu(gpu, va_space) { - if (gpu->parent->replayable_faults_supported) - uvm_global_processor_mask_set(&retained_gpus, gpu->global_id); - } + uvm_processor_mask_and(retained_gpus, &va_space->faultable_processors, &va_space->registered_gpus); - uvm_global_mask_retain(&retained_gpus); + uvm_global_gpu_retain(retained_gpus); uvm_va_space_up_read(va_space); - if (uvm_global_processor_mask_empty(&retained_gpus)) + if (uvm_processor_mask_empty(retained_gpus)) return NV_ERR_INVALID_DEVICE; for (i = 0; i < params->iterations; i++) { @@ -59,11 +60,12 @@ NV_STATUS uvm_test_fault_buffer_flush(UVM_TEST_FAULT_BUFFER_FLUSH_PARAMS *params break; } - for_each_global_gpu_in_mask(gpu, &retained_gpus) + for_each_gpu_in_mask(gpu, retained_gpus) TEST_CHECK_GOTO(uvm_gpu_fault_buffer_flush(gpu) == NV_OK, out); } out: - uvm_global_mask_release(&retained_gpus); + uvm_global_gpu_release(retained_gpus); + uvm_processor_mask_cache_free(retained_gpus); return status; } diff --git a/kernel-open/nvidia-uvm/uvm_get_rm_ptes_test.c b/kernel-open/nvidia-uvm/uvm_get_rm_ptes_test.c index b92b039b3f..2dbe1b3053 100644 --- a/kernel-open/nvidia-uvm/uvm_get_rm_ptes_test.c +++ b/kernel-open/nvidia-uvm/uvm_get_rm_ptes_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVidia Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -151,6 +151,22 @@ static NV_STATUS verify_mapping_info(uvm_va_space_t *va_space, return NV_OK; } +static void fix_memory_info_uuid(uvm_va_space_t *va_space, UvmGpuMemoryInfo *mem_info) +{ + uvm_gpu_t *gpu; + + // TODO: Bug 4351121: RM will return the GI UUID, but + // uvm_va_space_get_gpu_by_uuid() currently matches on physical GPU UUIDs. + // Match on GI UUID until the UVM user level API has been updated to use + // the GI UUID. + for_each_va_space_gpu(gpu, va_space) { + if (uvm_uuid_eq(&gpu->uuid, &mem_info->uuid)) { + mem_info->uuid = gpu->parent->uuid; + break; + } + } +} + static NV_STATUS test_get_rm_ptes_single_gpu(uvm_va_space_t *va_space, UVM_TEST_GET_RM_PTES_PARAMS *params) { NV_STATUS status = NV_OK; @@ -168,7 +184,8 @@ static NV_STATUS test_get_rm_ptes_single_gpu(uvm_va_space_t *va_space, UVM_TEST_ client = params->hClient; memory = params->hMemory; - // Note: This check is safe as single GPU test does not run on SLI enabled devices. + // Note: This check is safe as single GPU test does not run on SLI enabled + // devices. memory_mapping_gpu = uvm_va_space_get_gpu_by_uuid_with_gpu_va_space(va_space, ¶ms->gpu_uuid); if (!memory_mapping_gpu) return NV_ERR_INVALID_DEVICE; @@ -180,7 +197,12 @@ static NV_STATUS test_get_rm_ptes_single_gpu(uvm_va_space_t *va_space, UVM_TEST_ if (status != NV_OK) return status; - TEST_CHECK_GOTO(uvm_processor_uuid_eq(&memory_info.uuid, ¶ms->gpu_uuid), done); + // TODO: Bug 4351121: RM will return the GI UUID. Replace it with the + // physical GPU UUID until the UVM user level has been updated to use + // the GI UUID. + fix_memory_info_uuid(va_space, &memory_info); + + TEST_CHECK_GOTO(uvm_uuid_eq(&memory_info.uuid, ¶ms->gpu_uuid), done); TEST_CHECK_GOTO((memory_info.size == params->size), done); @@ -287,6 +309,11 @@ static NV_STATUS test_get_rm_ptes_multi_gpu(uvm_va_space_t *va_space, UVM_TEST_G if (status != NV_OK) return status; + // TODO: Bug 4351121: RM will return the GI UUID. Replace it with the + // physical GPU UUID until the UVM user level has been updated to use + // the GI UUID. + fix_memory_info_uuid(va_space, &memory_info); + memset(&ext_mapping_info, 0, sizeof(ext_mapping_info)); memset(pte_buffer, 0, sizeof(pte_buffer)); diff --git a/kernel-open/nvidia-uvm/uvm_global.c b/kernel-open/nvidia-uvm/uvm_global.c index 42af70ef71..44de7f495a 100644 --- a/kernel-open/nvidia-uvm/uvm_global.c +++ b/kernel-open/nvidia-uvm/uvm_global.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -27,6 +27,7 @@ #include "uvm_gpu_replayable_faults.h" #include "uvm_mem.h" #include "uvm_perf_events.h" +#include "uvm_processors.h" #include "uvm_procfs.h" #include "uvm_thread_context.h" #include "uvm_va_range.h" @@ -71,11 +72,6 @@ static void uvm_unregister_callbacks(void) } } -static void sev_init(const UvmPlatformInfo *platform_info) -{ - g_uvm_global.sev_enabled = platform_info->sevEnabled; -} - NV_STATUS uvm_global_init(void) { NV_STATUS status; @@ -124,8 +120,13 @@ NV_STATUS uvm_global_init(void) uvm_ats_init(&platform_info); g_uvm_global.num_simulated_devices = 0; + g_uvm_global.conf_computing_enabled = platform_info.confComputingEnabled; - sev_init(&platform_info); + status = uvm_processor_mask_cache_init(); + if (status != NV_OK) { + UVM_ERR_PRINT("uvm_processor_mask_cache_init() failed: %s\n", nvstatusToString(status)); + goto error; + } status = uvm_gpu_init(); if (status != NV_OK) { @@ -229,6 +230,7 @@ void uvm_global_exit(void) uvm_mem_global_exit(); uvm_pmm_sysmem_exit(); uvm_gpu_exit(); + uvm_processor_mask_cache_exit(); if (g_uvm_global.rm_session_handle != 0) uvm_rm_locked_call_void(nvUvmInterfaceSessionDestroy(g_uvm_global.rm_session_handle)); @@ -247,19 +249,19 @@ void uvm_global_exit(void) // Signal to the top-half ISR whether calls from the RM's top-half ISR are to // be completed without processing. -static void uvm_gpu_set_isr_suspended(uvm_gpu_t *gpu, bool is_suspended) +static void uvm_parent_gpu_set_isr_suspended(uvm_parent_gpu_t *parent_gpu, bool is_suspended) { - uvm_spin_lock_irqsave(&gpu->parent->isr.interrupts_lock); + uvm_spin_lock_irqsave(&parent_gpu->isr.interrupts_lock); - gpu->parent->isr.is_suspended = is_suspended; + parent_gpu->isr.is_suspended = is_suspended; - uvm_spin_unlock_irqrestore(&gpu->parent->isr.interrupts_lock); + uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); } static NV_STATUS uvm_suspend(void) { uvm_va_space_t *va_space = NULL; - uvm_global_gpu_id_t gpu_id; + uvm_gpu_id_t gpu_id; uvm_gpu_t *gpu; // Upon entry into this function, the following is true: @@ -293,7 +295,7 @@ static NV_STATUS uvm_suspend(void) // Though global_lock isn't held here, pm.lock indirectly prevents the // addition and removal of GPUs, since these operations can currently // only occur in response to ioctl() calls. - for_each_global_gpu_id_in_mask(gpu_id, &g_uvm_global.retained_gpus) { + for_each_gpu_id_in_mask(gpu_id, &g_uvm_global.retained_gpus) { gpu = uvm_gpu_get(gpu_id); // Since fault buffer state may be lost across sleep cycles, UVM must @@ -314,7 +316,7 @@ static NV_STATUS uvm_suspend(void) // notifications have been handled. uvm_gpu_access_counters_set_ignore(gpu, true); - uvm_gpu_set_isr_suspended(gpu, true); + uvm_parent_gpu_set_isr_suspended(gpu->parent, true); nv_kthread_q_flush(&gpu->parent->isr.bottom_half_q); @@ -347,7 +349,7 @@ NV_STATUS uvm_suspend_entry(void) static NV_STATUS uvm_resume(void) { uvm_va_space_t *va_space = NULL; - uvm_global_gpu_id_t gpu_id; + uvm_gpu_id_t gpu_id; uvm_gpu_t *gpu; g_uvm_global.pm.is_suspended = false; @@ -366,14 +368,14 @@ static NV_STATUS uvm_resume(void) uvm_mutex_unlock(&g_uvm_global.va_spaces.lock); // pm.lock is held in lieu of global_lock to prevent GPU addition/removal - for_each_global_gpu_id_in_mask(gpu_id, &g_uvm_global.retained_gpus) { + for_each_gpu_id_in_mask(gpu_id, &g_uvm_global.retained_gpus) { gpu = uvm_gpu_get(gpu_id); // Bring the fault buffer software state back in sync with the // hardware state. uvm_gpu_fault_buffer_resume(gpu->parent); - uvm_gpu_set_isr_suspended(gpu, false); + uvm_parent_gpu_set_isr_suspended(gpu->parent, false); // Reenable access counter interrupt processing unless notifications // have been set to be suppressed. @@ -431,35 +433,36 @@ NV_STATUS uvm_global_reset_fatal_error(void) return nv_atomic_xchg(&g_uvm_global.fatal_error, NV_OK); } -void uvm_global_mask_retain(const uvm_global_processor_mask_t *mask) +void uvm_global_gpu_retain(const uvm_processor_mask_t *mask) { uvm_gpu_t *gpu; - for_each_global_gpu_in_mask(gpu, mask) + + for_each_gpu_in_mask(gpu, mask) uvm_gpu_retain(gpu); } -void uvm_global_mask_release(const uvm_global_processor_mask_t *mask) +void uvm_global_gpu_release(const uvm_processor_mask_t *mask) { - uvm_global_gpu_id_t gpu_id; + uvm_gpu_id_t gpu_id; - if (uvm_global_processor_mask_empty(mask)) + if (uvm_processor_mask_empty(mask)) return; uvm_mutex_lock(&g_uvm_global.global_lock); - // Do not use for_each_global_gpu_in_mask as it reads the GPU state and it - // might get destroyed - for_each_global_gpu_id_in_mask(gpu_id, mask) + // Do not use for_each_gpu_in_mask as it reads the GPU state and it + // might get destroyed. + for_each_gpu_id_in_mask(gpu_id, mask) uvm_gpu_release_locked(uvm_gpu_get(gpu_id)); uvm_mutex_unlock(&g_uvm_global.global_lock); } -NV_STATUS uvm_global_mask_check_ecc_error(uvm_global_processor_mask_t *gpus) +NV_STATUS uvm_global_gpu_check_ecc_error(uvm_processor_mask_t *gpus) { uvm_gpu_t *gpu; - for_each_global_gpu_in_mask(gpu, gpus) { + for_each_gpu_in_mask(gpu, gpus) { NV_STATUS status = uvm_gpu_check_ecc_error(gpu); if (status != NV_OK) return status; diff --git a/kernel-open/nvidia-uvm/uvm_global.h b/kernel-open/nvidia-uvm/uvm_global.h index 8c92bbc067..3c0ed7a3e1 100644 --- a/kernel-open/nvidia-uvm/uvm_global.h +++ b/kernel-open/nvidia-uvm/uvm_global.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2021 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -40,13 +40,13 @@ struct uvm_global_struct // Note that GPUs are added to this mask as the last step of add_gpu() and // removed from it as the first step of remove_gpu() implying that a GPU // that's being initialized or deinitialized will not be in it. - uvm_global_processor_mask_t retained_gpus; + uvm_processor_mask_t retained_gpus; // Array of the parent GPUs registered with UVM. Note that GPUs will have - // ids offset by 1 to accomodate the UVM_GLOBAL_ID_CPU so e.g. - // parent_gpus[0] will have GPU id = 1. A GPU entry is unused iff it does - // not exist (is a NULL pointer) in this table. - uvm_parent_gpu_t *parent_gpus[UVM_MAX_GPUS]; + // ids offset by 1 to accomodate the UVM_ID_CPU so e.g., parent_gpus[0] + // will have GPU id = 1. A GPU entry is unused iff it does not exist + // (is a NULL pointer) in this table. + uvm_parent_gpu_t *parent_gpus[UVM_PARENT_ID_MAX_GPUS]; // A global RM session (RM client) // Created on module load and destroyed on module unload @@ -143,11 +143,16 @@ struct uvm_global_struct struct page *page; } unload_state; - // AMD Secure Encrypted Virtualization (SEV) status. True if VM has SEV - // enabled. This field is set once during global initialization - // (uvm_global_init), and can be read afterwards without acquiring any - // locks. - bool sev_enabled; + // True if the VM has AMD's SEV, or equivalent HW security extensions such + // as Intel's TDX, enabled. The flag is always false on the host. + // + // This value moves in tandem with that of Confidential Computing in the + // GPU(s) in all supported configurations, so it is used as a proxy for the + // Confidential Computing state. + // + // This field is set once during global initialization (uvm_global_init), + // and can be read afterwards without acquiring any locks. + bool conf_computing_enabled; }; // Initialize global uvm state @@ -167,7 +172,7 @@ NV_STATUS uvm_resume_entry(void); // LOCKING: requires that you hold the global lock and gpu_table_lock static void uvm_global_add_parent_gpu(uvm_parent_gpu_t *parent_gpu) { - NvU32 gpu_index = uvm_id_gpu_index(parent_gpu->id); + NvU32 gpu_index = uvm_parent_id_gpu_index(parent_gpu->id); uvm_assert_mutex_locked(&g_uvm_global.global_lock); uvm_assert_spinlock_locked(&g_uvm_global.gpu_table_lock); @@ -181,7 +186,7 @@ static void uvm_global_add_parent_gpu(uvm_parent_gpu_t *parent_gpu) // LOCKING: requires that you hold the global lock and gpu_table_lock static void uvm_global_remove_parent_gpu(uvm_parent_gpu_t *parent_gpu) { - NvU32 gpu_index = uvm_id_gpu_index(parent_gpu->id); + NvU32 gpu_index = uvm_parent_id_gpu_index(parent_gpu->id); uvm_assert_mutex_locked(&g_uvm_global.global_lock); uvm_assert_spinlock_locked(&g_uvm_global.gpu_table_lock); @@ -196,41 +201,25 @@ static void uvm_global_remove_parent_gpu(uvm_parent_gpu_t *parent_gpu) // // LOCKING: requires that you hold the gpu_table_lock, the global lock, or have // retained at least one of the child GPUs. -static uvm_parent_gpu_t *uvm_parent_gpu_get(uvm_gpu_id_t id) +static uvm_parent_gpu_t *uvm_parent_gpu_get(uvm_parent_gpu_id_t id) { - return g_uvm_global.parent_gpus[uvm_id_gpu_index(id)]; + return g_uvm_global.parent_gpus[uvm_parent_id_gpu_index(id)]; } -// Get a gpu by its global id. +// Get a gpu by its GPU id. // Returns a pointer to the GPU object, or NULL if not found. // // LOCKING: requires that you hold the gpu_table_lock, the global_lock, or have // retained the gpu. -static uvm_gpu_t *uvm_gpu_get(uvm_global_gpu_id_t global_gpu_id) +static uvm_gpu_t *uvm_gpu_get(uvm_gpu_id_t gpu_id) { uvm_parent_gpu_t *parent_gpu; - parent_gpu = g_uvm_global.parent_gpus[uvm_id_gpu_index_from_global_gpu_id(global_gpu_id)]; + parent_gpu = g_uvm_global.parent_gpus[uvm_parent_id_gpu_index_from_gpu_id(gpu_id)]; if (!parent_gpu) return NULL; - return parent_gpu->gpus[uvm_global_id_sub_processor_index(global_gpu_id)]; -} - -// Get a gpu by its processor id. -// Returns a pointer to the GPU object, or NULL if not found. -// -// LOCKING: requires that you hold the gpu_table_lock, the global_lock, or have -// retained the gpu. -static uvm_gpu_t *uvm_gpu_get_by_processor_id(uvm_processor_id_t id) -{ - uvm_global_gpu_id_t global_id = uvm_global_gpu_id_from_gpu_id(id); - uvm_gpu_t *gpu = uvm_gpu_get(global_id); - - if (gpu) - UVM_ASSERT(!gpu->parent->smc.enabled); - - return gpu; + return parent_gpu->gpus[uvm_id_sub_processor_index(gpu_id)]; } static uvmGpuSessionHandle uvm_global_session_handle(void) @@ -287,56 +276,57 @@ static NV_STATUS uvm_global_get_status(void) // reset call was made. NV_STATUS uvm_global_reset_fatal_error(void); -static uvm_gpu_t *uvm_global_processor_mask_find_first_gpu(const uvm_global_processor_mask_t *global_gpus) +static uvm_gpu_t *uvm_processor_mask_find_first_gpu(const uvm_processor_mask_t *gpus) { uvm_gpu_t *gpu; - uvm_global_gpu_id_t gpu_id = uvm_global_processor_mask_find_first_gpu_id(global_gpus); + uvm_gpu_id_t gpu_id = uvm_processor_mask_find_first_gpu_id(gpus); - if (UVM_GLOBAL_ID_IS_INVALID(gpu_id)) + if (UVM_ID_IS_INVALID(gpu_id)) return NULL; gpu = uvm_gpu_get(gpu_id); // If there is valid GPU id in the mask, assert that the corresponding // uvm_gpu_t is present. Otherwise it would stop a - // for_each_global_gpu_in_mask() loop pre-maturely. Today, this could only + // for_each_gpu_in_mask() loop pre-maturely. Today, this could only // happen in remove_gpu() because the GPU being removed is deleted from the // global table very early. - UVM_ASSERT_MSG(gpu, "gpu_id %u\n", uvm_global_id_value(gpu_id)); + UVM_ASSERT_MSG(gpu, "gpu_id %u\n", uvm_id_value(gpu_id)); return gpu; } -static uvm_gpu_t *__uvm_global_processor_mask_find_next_gpu(const uvm_global_processor_mask_t *global_gpus, uvm_gpu_t *gpu) +static uvm_gpu_t *__uvm_processor_mask_find_next_gpu(const uvm_processor_mask_t *gpus, uvm_gpu_t *gpu) { - uvm_global_gpu_id_t gpu_id; + uvm_gpu_id_t gpu_id; UVM_ASSERT(gpu); - gpu_id = uvm_global_processor_mask_find_next_id(global_gpus, uvm_global_gpu_id_next(gpu->global_id)); - if (UVM_GLOBAL_ID_IS_INVALID(gpu_id)) + gpu_id = uvm_processor_mask_find_next_id(gpus, uvm_gpu_id_next(gpu->id)); + if (UVM_ID_IS_INVALID(gpu_id)) return NULL; gpu = uvm_gpu_get(gpu_id); - // See comment in uvm_global_processor_mask_find_first_gpu(). - UVM_ASSERT_MSG(gpu, "gpu_id %u\n", uvm_global_id_value(gpu_id)); + // See comment in uvm_processor_mask_find_first_gpu(). + UVM_ASSERT_MSG(gpu, "gpu_id %u\n", uvm_id_value(gpu_id)); return gpu; } // Helper to iterate over all GPUs in the input mask -#define for_each_global_gpu_in_mask(gpu, global_mask) \ - for (gpu = uvm_global_processor_mask_find_first_gpu(global_mask); \ - gpu != NULL; \ - gpu = __uvm_global_processor_mask_find_next_gpu(global_mask, gpu)) - -// Helper to iterate over all GPUs retained by the UVM driver (across all va spaces) -#define for_each_global_gpu(gpu) \ - for (({uvm_assert_mutex_locked(&g_uvm_global.global_lock); \ - gpu = uvm_global_processor_mask_find_first_gpu(&g_uvm_global.retained_gpus);}); \ - gpu != NULL; \ - gpu = __uvm_global_processor_mask_find_next_gpu(&g_uvm_global.retained_gpus, gpu)) +#define for_each_gpu_in_mask(gpu, mask) \ + for (gpu = uvm_processor_mask_find_first_gpu(mask); \ + gpu != NULL; \ + gpu = __uvm_processor_mask_find_next_gpu(mask, gpu)) + +// Helper to iterate over all GPUs retained by the UVM driver +// (across all va spaces). +#define for_each_gpu(gpu) \ + for (({uvm_assert_mutex_locked(&g_uvm_global.global_lock); \ + gpu = uvm_processor_mask_find_first_gpu(&g_uvm_global.retained_gpus);}); \ + gpu != NULL; \ + gpu = __uvm_processor_mask_find_next_gpu(&g_uvm_global.retained_gpus, gpu)) // LOCKING: Must hold either the global_lock or the gpu_table_lock static uvm_parent_gpu_t *uvm_global_find_next_parent_gpu(uvm_parent_gpu_t *parent_gpu) @@ -344,7 +334,7 @@ static uvm_parent_gpu_t *uvm_global_find_next_parent_gpu(uvm_parent_gpu_t *paren NvU32 i; if (parent_gpu) { - NvU32 gpu_index = uvm_id_gpu_index(parent_gpu->id); + NvU32 gpu_index = uvm_parent_id_gpu_index(parent_gpu->id); i = gpu_index + 1; } else { @@ -353,7 +343,7 @@ static uvm_parent_gpu_t *uvm_global_find_next_parent_gpu(uvm_parent_gpu_t *paren parent_gpu = NULL; - while (i < UVM_MAX_GPUS) { + while (i < UVM_PARENT_ID_MAX_GPUS) { if (g_uvm_global.parent_gpus[i]) { parent_gpu = g_uvm_global.parent_gpus[i]; break; @@ -369,18 +359,18 @@ static uvm_parent_gpu_t *uvm_global_find_next_parent_gpu(uvm_parent_gpu_t *paren static uvm_gpu_t *uvm_gpu_find_next_valid_gpu_in_parent(uvm_parent_gpu_t *parent_gpu, uvm_gpu_t *cur_gpu) { uvm_gpu_t *gpu = NULL; - uvm_global_gpu_id_t global_gpu_id; + uvm_gpu_id_t gpu_id; NvU32 sub_processor_index; NvU32 cur_sub_processor_index; UVM_ASSERT(parent_gpu); - global_gpu_id = uvm_global_gpu_id_from_gpu_id(parent_gpu->id); - cur_sub_processor_index = cur_gpu ? uvm_global_id_sub_processor_index(cur_gpu->global_id) : -1; + gpu_id = uvm_gpu_id_from_parent_gpu_id(parent_gpu->id); + cur_sub_processor_index = cur_gpu ? uvm_id_sub_processor_index(cur_gpu->id) : -1; - sub_processor_index = find_next_bit(parent_gpu->valid_gpus, UVM_ID_MAX_SUB_PROCESSORS, cur_sub_processor_index + 1); - if (sub_processor_index < UVM_ID_MAX_SUB_PROCESSORS) { - gpu = uvm_gpu_get(uvm_global_id_from_value(uvm_global_id_value(global_gpu_id) + sub_processor_index)); + sub_processor_index = find_next_bit(parent_gpu->valid_gpus, UVM_PARENT_ID_MAX_SUB_PROCESSORS, cur_sub_processor_index + 1); + if (sub_processor_index < UVM_PARENT_ID_MAX_SUB_PROCESSORS) { + gpu = uvm_gpu_get(uvm_id_from_value(uvm_id_value(gpu_id) + sub_processor_index)); UVM_ASSERT(gpu != NULL); } @@ -400,18 +390,18 @@ static uvm_gpu_t *uvm_gpu_find_next_valid_gpu_in_parent(uvm_parent_gpu_t *parent (gpu) != NULL; \ (gpu) = uvm_gpu_find_next_valid_gpu_in_parent((parent_gpu), (gpu))) -// Helper which calls uvm_gpu_retain on each GPU in mask -void uvm_global_mask_retain(const uvm_global_processor_mask_t *mask); +// Helper which calls uvm_gpu_retain() on each GPU in mask. +void uvm_global_gpu_retain(const uvm_processor_mask_t *mask); // Helper which calls uvm_gpu_release_locked on each GPU in mask. // // LOCKING: this function takes and releases the global lock if the input mask // is not empty -void uvm_global_mask_release(const uvm_global_processor_mask_t *mask); +void uvm_global_gpu_release(const uvm_processor_mask_t *mask); // Check for ECC errors for all GPUs in a mask // Notably this check cannot be performed where it's not safe to call into RM. -NV_STATUS uvm_global_mask_check_ecc_error(uvm_global_processor_mask_t *gpus); +NV_STATUS uvm_global_gpu_check_ecc_error(uvm_processor_mask_t *gpus); // Pre-allocate fault service contexts. NV_STATUS uvm_service_block_context_init(void); diff --git a/kernel-open/nvidia-uvm/uvm_gpu.c b/kernel-open/nvidia-uvm/uvm_gpu.c index 0967281b3c..2a992cfb64 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_gpu.c @@ -87,7 +87,7 @@ static uvm_gpu_link_type_t get_gpu_link_type(UVM_LINK_TYPE link_type) } } -static void fill_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo *gpu_info) +static void fill_parent_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo *gpu_info) { char uuid_buffer[UVM_GPU_UUID_TEXT_BUFFER_LENGTH]; @@ -119,7 +119,7 @@ static void fill_gpu_info(uvm_parent_gpu_t *parent_gpu, const UvmGpuInfo *gpu_in snprintf(parent_gpu->name, sizeof(parent_gpu->name), "ID %u: %s: %s", - uvm_id_value(parent_gpu->id), + uvm_parent_id_value(parent_gpu->id), parent_gpu->rm_info.name, uuid_buffer); } @@ -147,6 +147,62 @@ static NV_STATUS get_gpu_caps(uvm_gpu_t *gpu) return NV_OK; } + +// Return a PASID to use with the internal address space (AS), or -1 if not +// supported. This PASID is needed to enable ATS in the internal AS, but it is +// not used in address translation requests, which only translate GPA->SPA. +// The buffer management thus remains the same: DMA mapped GPA addresses can +// be accessed by the GPU, while unmapped addresses can not and any access is +// blocked and potentially unrecoverable to the engine that made it. +static int gpu_get_internal_pasid(const uvm_gpu_t *gpu) +{ +#if UVM_ATS_SVA_SUPPORTED() && defined(NV_IOMMU_IS_DMA_DOMAIN_PRESENT) +// iommu_is_dma_domain() was added in Linux 5.15 by commit bf3aed4660c6 +// ("iommu: Introduce explicit type for non-strict DMA domains") +// +// SVA is not required for enabling ATS for internal UVM address spaces. +// However, it conveniently combines the necessary check for permissive license +// and the special behaviour of PASID 0 on SMMUv3 described below. +// +// PASID 0 is reserved on aarch64 SMMUv3 (see section 3.3.2 of the SMMU spec) +// because the corresponding page table is used to translate requests and +// transactions without an associated PASID. +// Linux 6.6+ generalized this value as IOMMU_NO_PASID for all architectures +// commit 4298780126c2 ("iommu: Generalize PASID 0 for normal DMA w/o PASID") +#ifdef IOMMU_NO_PASID +#define UVM_INTERNAL_PASID IOMMU_NO_PASID +#else +#define UVM_INTERNAL_PASID 0 +#endif + + // Enable internal ATS only if ATS is enabled in general and we are using + // 64kB base page size. The base page size limitation is needed to avoid + // GH180 MMU behaviour which does not refetch invalid 4K ATS translations + // on access (see bug 3949400). This also works in virtualized environments + // because the entire 64kB guest page has to be mapped and pinned by the + // hypervisor for device access. + if (g_uvm_global.ats.enabled && PAGE_SIZE == UVM_PAGE_SIZE_64K) { + struct device *dev = &gpu->parent->pci_dev->dev; + struct iommu_domain *domain = iommu_get_domain_for_dev(dev); + + // Check that the iommu domain is controlled by linux DMA API and + // return a valid reserved PASID. Using a reserved PASID is OK since + // this value is only used for the internal UVM address space that + // uses ATS only for GPA->SPA translations that don't use PASID. + // + // If a general reserved PASID is not available (e.g. non-smmuv3, <6.6) + // we'd need to to reserve a PASID from the IOMMU driver here, or risk + // PASID collision. Note that since the PASID should not be used during + // normal operation, the collision would only manifest in error paths. + if (domain && iommu_is_dma_domain(domain)) + return UVM_INTERNAL_PASID; + } +#endif + + /* Invalid PASID for internal RM address space */ + return -1; +} + static NV_STATUS alloc_and_init_address_space(uvm_gpu_t *gpu) { NV_STATUS status; @@ -155,6 +211,7 @@ static NV_STATUS alloc_and_init_address_space(uvm_gpu_t *gpu) status = uvm_rm_locked_call(nvUvmInterfaceAddressSpaceCreate(uvm_gpu_device_handle(gpu), gpu->parent->rm_va_base, gpu->parent->rm_va_size, + gpu_get_internal_pasid(gpu) != -1, &gpu->rm_address_space, &gpu_address_space_info)); if (status != NV_OK) @@ -218,19 +275,12 @@ static bool gpu_supports_uvm(uvm_parent_gpu_t *parent_gpu) return parent_gpu->rm_info.subdeviceCount == 1; } -static bool platform_uses_canonical_form_address(void) -{ - if (NVCPU_IS_PPC64LE) - return false; - - return true; -} - bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) { // Lower and upper address spaces are typically found in platforms that use // the canonical address form. NvU64 max_va_lower; + NvU64 min_va_upper; NvU64 addr_end = addr + size - 1; NvU8 gpu_addr_shift; NvU8 cpu_addr_shift; @@ -243,7 +293,7 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) UVM_ASSERT(size > 0); gpu_addr_shift = gpu->address_space_tree.hal->num_va_bits(); - cpu_addr_shift = fls64(TASK_SIZE - 1) + 1; + cpu_addr_shift = uvm_cpu_num_va_bits(); addr_shift = gpu_addr_shift; // Pascal+ GPUs are capable of accessing kernel pointers in various modes @@ -279,9 +329,7 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) // 0 +----------------+ 0 +----------------+ // On canonical form address platforms and Pascal+ GPUs. - if (platform_uses_canonical_form_address() && gpu_addr_shift > 40) { - NvU64 min_va_upper; - + if (uvm_platform_uses_canonical_form_address() && gpu_addr_shift > 40) { // On x86, when cpu_addr_shift > gpu_addr_shift, it means the CPU uses // 5-level paging and the GPU is pre-Hopper. On Pascal-Ada GPUs (49b // wide VA) we set addr_shift to match a 4-level paging x86 (48b wide). @@ -292,15 +340,11 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size) addr_shift = gpu_addr_shift; else addr_shift = cpu_addr_shift; - - min_va_upper = (NvU64)((NvS64)(1ULL << 63) >> (64 - addr_shift)); - max_va_lower = 1ULL << (addr_shift - 1); - return (addr_end < max_va_lower) || (addr >= min_va_upper); - } - else { - max_va_lower = 1ULL << addr_shift; - return addr_end < max_va_lower; } + + uvm_get_unaddressable_range(addr_shift, &max_va_lower, &min_va_upper); + + return (addr_end < max_va_lower) || (addr >= min_va_upper); } // The internal UVM VAS does not use canonical form addresses. @@ -326,14 +370,14 @@ NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr) NvU8 addr_shift; NvU64 input_addr = addr; - if (platform_uses_canonical_form_address()) { + if (uvm_platform_uses_canonical_form_address()) { // When the CPU VA width is larger than GPU's, it means that: // On ARM: the CPU is on LVA mode and the GPU is pre-Hopper. // On x86: the CPU uses 5-level paging and the GPU is pre-Hopper. // We sign-extend on the 48b on ARM and on the 47b on x86 to mirror the // behavior of CPUs with smaller (than GPU) VA widths. gpu_addr_shift = parent_gpu->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K)->num_va_bits(); - cpu_addr_shift = fls64(TASK_SIZE - 1) + 1; + cpu_addr_shift = uvm_cpu_num_va_bits(); if (cpu_addr_shift > gpu_addr_shift) addr_shift = NVCPU_IS_X86_64 ? 48 : 49; @@ -567,7 +611,7 @@ static void gpu_info_print_common(uvm_gpu_t *gpu, struct seq_file *s) gpu_info_print_ce_caps(gpu, s); - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { UVM_SEQ_OR_DBG_PRINT(s, "dma_buffer_pool_num_buffers %lu\n", gpu->conf_computing.dma_buffer_pool.num_dma_buffers); } @@ -792,7 +836,7 @@ static void deinit_parent_procfs_files(uvm_parent_gpu_t *parent_gpu) static NV_STATUS init_procfs_dirs(uvm_gpu_t *gpu) { struct proc_dir_entry *gpu_base_dir_entry; - char symlink_name[16]; // Hold a global_gpu_id_t value in decimal. + char symlink_name[16]; // Hold a uvm_gpu_id_t value in decimal. char uuid_text_buffer[UVM_GPU_UUID_TEXT_BUFFER_LENGTH]; char gpu_dir_name[sizeof(symlink_name) + sizeof(uuid_text_buffer) + 1]; @@ -804,20 +848,20 @@ static NV_STATUS init_procfs_dirs(uvm_gpu_t *gpu) gpu_base_dir_entry = uvm_procfs_get_gpu_base_dir(); // Create UVM-GPU-${UUID}/${sub_processor_index} directory - snprintf(gpu_dir_name, sizeof(gpu_dir_name), "%u", uvm_global_id_sub_processor_index(gpu->global_id)); + snprintf(gpu_dir_name, sizeof(gpu_dir_name), "%u", uvm_id_sub_processor_index(gpu->id)); gpu->procfs.dir = NV_CREATE_PROC_DIR(gpu_dir_name, gpu->parent->procfs.dir); if (gpu->procfs.dir == NULL) return NV_ERR_OPERATING_SYSTEM; - // Create symlink from ${global_gpu_id} to + // Create symlink from ${gpu_id} to // gpus/UVM-GPU-${UUID}/${sub_processor_index} - snprintf(symlink_name, sizeof(symlink_name), "%u", uvm_global_id_value(gpu->global_id)); + snprintf(symlink_name, sizeof(symlink_name), "%u", uvm_id_value(gpu->id)); snprintf(gpu_dir_name, sizeof(gpu_dir_name), "%s/%u", uuid_text_buffer, - uvm_global_id_sub_processor_index(gpu->global_id)); + uvm_id_sub_processor_index(gpu->id)); gpu->procfs.dir_symlink = proc_symlink(symlink_name, gpu_base_dir_entry, gpu_dir_name); if (gpu->procfs.dir_symlink == NULL) @@ -875,15 +919,10 @@ static NV_STATUS init_semaphore_pools(uvm_gpu_t *gpu) // When the Confidential Computing feature is enabled, a separate secure // pool is created that holds page allocated in the CPR of vidmem. - if (uvm_conf_computing_mode_enabled(gpu)) { - status = uvm_gpu_semaphore_secure_pool_create(gpu, &gpu->secure_semaphore_pool); - if (status != NV_OK) - return status; - } + if (g_uvm_global.conf_computing_enabled) + return uvm_gpu_semaphore_secure_pool_create(gpu, &gpu->secure_semaphore_pool); - for_each_global_gpu(other_gpu) { - if (uvm_conf_computing_mode_enabled(gpu)) - break; + for_each_gpu(other_gpu) { if (other_gpu == gpu) continue; status = uvm_gpu_semaphore_pool_map_gpu(other_gpu->semaphore_pool, gpu); @@ -898,7 +937,7 @@ static void deinit_semaphore_pools(uvm_gpu_t *gpu) { uvm_gpu_t *other_gpu; - for_each_global_gpu(other_gpu) { + for_each_gpu(other_gpu) { if (other_gpu == gpu) continue; uvm_gpu_semaphore_pool_unmap_gpu(other_gpu->semaphore_pool, gpu); @@ -908,24 +947,26 @@ static void deinit_semaphore_pools(uvm_gpu_t *gpu) uvm_gpu_semaphore_pool_destroy(gpu->secure_semaphore_pool); } -static NV_STATUS find_unused_global_gpu_id(uvm_parent_gpu_t *parent_gpu, uvm_global_gpu_id_t *out_id) +static NV_STATUS find_unused_gpu_id(uvm_parent_gpu_t *parent_gpu, uvm_gpu_id_t *out_id) { NvU32 i; uvm_assert_mutex_locked(&g_uvm_global.global_lock); if (!parent_gpu) { - for (i = 0; i < UVM_MAX_GPUS; i++) { + for (i = 0; i < UVM_PARENT_ID_MAX_GPUS; i++) { if (!g_uvm_global.parent_gpus[i]) { - *out_id = uvm_global_gpu_id_from_parent_index(i); + *out_id = uvm_gpu_id_from_sub_processor_index(i, 0); return NV_OK; } } } else { - NvU32 sub_processor_index = find_first_zero_bit(parent_gpu->valid_gpus, UVM_ID_MAX_SUB_PROCESSORS); - if (sub_processor_index < UVM_ID_MAX_SUB_PROCESSORS) { - *out_id = uvm_global_gpu_id_from_sub_processor_index(parent_gpu->id, sub_processor_index); + NvU32 sub_processor_index = find_first_zero_bit(parent_gpu->valid_gpus, UVM_PARENT_ID_MAX_SUB_PROCESSORS); + + if (sub_processor_index < UVM_PARENT_ID_MAX_SUB_PROCESSORS) { + i = uvm_parent_id_gpu_index(parent_gpu->id); + *out_id = uvm_gpu_id_from_sub_processor_index(i, sub_processor_index); return NV_OK; } } @@ -936,7 +977,7 @@ static NV_STATUS find_unused_global_gpu_id(uvm_parent_gpu_t *parent_gpu, uvm_glo // Allocates a uvm_parent_gpu_t, assigns the GPU ID, and sets up basic data // structures, but leaves all other initialization up to the caller. static NV_STATUS alloc_parent_gpu(const NvProcessorUuid *gpu_uuid, - uvm_gpu_id_t gpu_id, + uvm_parent_gpu_id_t gpu_id, uvm_parent_gpu_t **parent_gpu_out) { uvm_parent_gpu_t *parent_gpu; @@ -948,7 +989,7 @@ static NV_STATUS alloc_parent_gpu(const NvProcessorUuid *gpu_uuid, parent_gpu->id = gpu_id; - uvm_processor_uuid_copy(&parent_gpu->uuid, gpu_uuid); + uvm_uuid_copy(&parent_gpu->uuid, gpu_uuid); uvm_sema_init(&parent_gpu->isr.replayable_faults.service_lock, 1, UVM_LOCK_ORDER_ISR); uvm_sema_init(&parent_gpu->isr.non_replayable_faults.service_lock, 1, UVM_LOCK_ORDER_ISR); uvm_sema_init(&parent_gpu->isr.access_counters.service_lock, 1, UVM_LOCK_ORDER_ISR); @@ -969,7 +1010,7 @@ static NV_STATUS alloc_parent_gpu(const NvProcessorUuid *gpu_uuid, // Allocates a uvm_gpu_t struct and initializes the basic fields and leaves all // other initialization up to the caller. -static uvm_gpu_t *alloc_gpu(uvm_parent_gpu_t *parent_gpu, uvm_global_gpu_id_t global_gpu_id) +static uvm_gpu_t *alloc_gpu(uvm_parent_gpu_t *parent_gpu, uvm_gpu_id_t gpu_id) { NvU32 sub_processor_index; uvm_gpu_t *gpu; @@ -978,15 +1019,14 @@ static uvm_gpu_t *alloc_gpu(uvm_parent_gpu_t *parent_gpu, uvm_global_gpu_id_t gl if (!gpu) return gpu; - gpu->id = parent_gpu->id; - gpu->global_id = global_gpu_id; + gpu->id = gpu_id; gpu->parent = parent_gpu; // Initialize enough of the gpu struct for remove_gpu to be called gpu->magic = UVM_GPU_MAGIC_VALUE; uvm_spin_lock_init(&gpu->peer_info.peer_gpus_lock, UVM_LOCK_ORDER_LEAF); - sub_processor_index = uvm_global_id_sub_processor_index(global_gpu_id); + sub_processor_index = uvm_id_sub_processor_index(gpu_id); parent_gpu->gpus[sub_processor_index] = gpu; return gpu; @@ -1003,7 +1043,7 @@ static NV_STATUS configure_address_space(uvm_gpu_t *gpu) NULL, UVM_PAGE_TREE_TYPE_KERNEL, gpu->big_page.internal_size, - uvm_gpu_page_tree_init_location(gpu), + uvm_get_page_tree_location(gpu->parent), &gpu->address_space_tree); if (status != NV_OK) { UVM_ERR_PRINT("Initializing the page tree failed: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); @@ -1026,7 +1066,7 @@ static NV_STATUS configure_address_space(uvm_gpu_t *gpu) status = uvm_rm_locked_call(nvUvmInterfaceSetPageDirectory(gpu->rm_address_space, uvm_page_tree_pdb(&gpu->address_space_tree)->addr.address, num_entries, uvm_page_tree_pdb(&gpu->address_space_tree)->addr.aperture == UVM_APERTURE_VID, - -1U /* Invalid PASID for internal RM address space */)); + gpu_get_internal_pasid(gpu))); if (status != NV_OK) { UVM_ERR_PRINT("nvUvmInterfaceSetPageDirectory() failed: %s, GPU %s\n", nvstatusToString(status), @@ -1095,16 +1135,13 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, &parent_gpu->rm_device, NV_FALSE)); if (status != NV_OK) { - UVM_ERR_PRINT("Creating RM device failed: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); + UVM_ERR_PRINT("Creating RM device failed: %s, GPU %s\n", + nvstatusToString(status), + uvm_parent_gpu_name(parent_gpu)); return status; } - status = uvm_conf_computing_init_parent_gpu(parent_gpu); - if (status != NV_OK) { - UVM_ERR_PRINT("Confidential computing: %s, GPU %s\n", - nvstatusToString(status), parent_gpu->name); - return status; - } + uvm_conf_computing_check_parent_gpu(parent_gpu); parent_gpu->pci_dev = gpu_platform_info->pci_dev; parent_gpu->closest_cpu_numa_node = dev_to_node(&parent_gpu->pci_dev->dev); @@ -1115,7 +1152,8 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, parent_gpu->virt_mode = gpu_info->virtMode; if (parent_gpu->virt_mode == UVM_VIRT_MODE_LEGACY) { - UVM_ERR_PRINT("Failed to init GPU %s. UVM is not supported in legacy virtualization mode\n", parent_gpu->name); + UVM_ERR_PRINT("Failed to init GPU %s. UVM is not supported in legacy virtualization mode\n", + uvm_parent_gpu_name(parent_gpu)); return NV_ERR_NOT_SUPPORTED; } @@ -1124,13 +1162,17 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, status = init_parent_procfs_dir(parent_gpu); if (status != NV_OK) { - UVM_ERR_PRINT("Failed to init parent procfs dir: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); + UVM_ERR_PRINT("Failed to init parent procfs dir: %s, GPU %s\n", + nvstatusToString(status), + uvm_parent_gpu_name(parent_gpu)); return status; } status = uvm_hal_init_gpu(parent_gpu); if (status != NV_OK) { - UVM_ERR_PRINT("Failed to init GPU hal: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); + UVM_ERR_PRINT("Failed to init GPU hal: %s, GPU %s\n", + nvstatusToString(status), + uvm_parent_gpu_name(parent_gpu)); return status; } @@ -1143,19 +1185,25 @@ static NV_STATUS init_parent_gpu(uvm_parent_gpu_t *parent_gpu, status = uvm_ats_add_gpu(parent_gpu); if (status != NV_OK) { - UVM_ERR_PRINT("uvm_ats_add_gpu failed: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); + UVM_ERR_PRINT("uvm_ats_add_gpu failed: %s, GPU %s\n", + nvstatusToString(status), + uvm_parent_gpu_name(parent_gpu)); return status; } status = init_parent_procfs_files(parent_gpu); if (status != NV_OK) { - UVM_ERR_PRINT("Failed to init parent procfs files: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); + UVM_ERR_PRINT("Failed to init parent procfs files: %s, GPU %s\n", + nvstatusToString(status), + uvm_parent_gpu_name(parent_gpu)); return status; } - status = uvm_gpu_init_isr(parent_gpu); + status = uvm_parent_gpu_init_isr(parent_gpu); if (status != NV_OK) { - UVM_ERR_PRINT("Failed to init ISR: %s, GPU %s\n", nvstatusToString(status), parent_gpu->name); + UVM_ERR_PRINT("Failed to init ISR: %s, GPU %s\n", + nvstatusToString(status), + uvm_parent_gpu_name(parent_gpu)); return status; } @@ -1169,7 +1217,7 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info) if (gpu->parent->smc.enabled) { status = uvm_rm_locked_call(nvUvmInterfaceDeviceCreate(uvm_global_session_handle(), gpu_info, - uvm_gpu_uuid(gpu), + &gpu->parent->uuid, &gpu->smc.rm_device, NV_TRUE)); if (status != NV_OK) { @@ -1178,6 +1226,7 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info) } } + uvm_uuid_copy(&gpu->uuid, &gpu_info->uuid); gpu->smc.swizz_id = gpu_info->smcSwizzId; // Initialize the per-GPU procfs dirs as early as possible so that other @@ -1283,12 +1332,13 @@ static NV_STATUS init_gpu(uvm_gpu_t *gpu, const UvmGpuInfo *gpu_info) // TODO: Bug 2844714: Split parent-specific parts of this function out into a // separate add_parent_gpu() function. static NV_STATUS add_gpu(const NvProcessorUuid *gpu_uuid, - const uvm_global_gpu_id_t global_gpu_id, + const uvm_gpu_id_t gpu_id, const UvmGpuInfo *gpu_info, const UvmGpuPlatformInfo *gpu_platform_info, uvm_parent_gpu_t *parent_gpu, uvm_gpu_t **gpu_out) { + char uuid_buffer[UVM_GPU_UUID_TEXT_BUFFER_LENGTH]; NV_STATUS status; bool alloc_parent = (parent_gpu == NULL); uvm_gpu_t *gpu = NULL; @@ -1296,12 +1346,12 @@ static NV_STATUS add_gpu(const NvProcessorUuid *gpu_uuid, uvm_assert_mutex_locked(&g_uvm_global.global_lock); if (alloc_parent) { - status = alloc_parent_gpu(gpu_uuid, uvm_gpu_id_from_global_gpu_id(global_gpu_id), &parent_gpu); + status = alloc_parent_gpu(gpu_uuid, uvm_parent_gpu_id_from_gpu_id(gpu_id), &parent_gpu); if (status != NV_OK) return status; } - gpu = alloc_gpu(parent_gpu, global_gpu_id); + gpu = alloc_gpu(parent_gpu, gpu_id); if (!gpu) { if (alloc_parent) uvm_parent_gpu_kref_put(parent_gpu); @@ -1312,7 +1362,14 @@ static NV_STATUS add_gpu(const NvProcessorUuid *gpu_uuid, parent_gpu->num_retained_gpus++; if (alloc_parent) - fill_gpu_info(parent_gpu, gpu_info); + fill_parent_gpu_info(parent_gpu, gpu_info); + + format_uuid_to_buffer(uuid_buffer, sizeof(uuid_buffer), &parent_gpu->uuid); + snprintf(gpu->name, + sizeof(gpu->name), + "ID %u: %s", + uvm_id_value(gpu->id), + uuid_buffer); // After this point all error clean up should be handled by remove_gpu() @@ -1337,7 +1394,7 @@ static NV_STATUS add_gpu(const NvProcessorUuid *gpu_uuid, goto error; atomic64_set(&gpu->retained_count, 1); - uvm_global_processor_mask_set(&g_uvm_global.retained_gpus, gpu->global_id); + uvm_processor_mask_set(&g_uvm_global.retained_gpus, gpu->id); uvm_spin_lock_irqsave(&g_uvm_global.gpu_table_lock); @@ -1345,8 +1402,8 @@ static NV_STATUS add_gpu(const NvProcessorUuid *gpu_uuid, uvm_global_add_parent_gpu(parent_gpu); // Mark the GPU as valid in the parent GPU's GPU table. - UVM_ASSERT(!test_bit(uvm_global_id_sub_processor_index(gpu->global_id), parent_gpu->valid_gpus)); - __set_bit(uvm_global_id_sub_processor_index(gpu->global_id), parent_gpu->valid_gpus); + UVM_ASSERT(!test_bit(uvm_id_sub_processor_index(gpu->id), parent_gpu->valid_gpus)); + __set_bit(uvm_id_sub_processor_index(gpu->id), parent_gpu->valid_gpus); // Although locking correctness does not, at this early point (before the // GPU is visible in the table) strictly require holding the gpu_table_lock @@ -1407,9 +1464,9 @@ static void sync_parent_gpu_trackers(uvm_parent_gpu_t *parent_gpu, // Sync the replay tracker since it inherits dependencies from the VA block // trackers. if (sync_replay_tracker) { - uvm_gpu_replayable_faults_isr_lock(parent_gpu); + uvm_parent_gpu_replayable_faults_isr_lock(parent_gpu); status = uvm_tracker_wait(&parent_gpu->fault_buffer_info.replayable.replay_tracker); - uvm_gpu_replayable_faults_isr_unlock(parent_gpu); + uvm_parent_gpu_replayable_faults_isr_unlock(parent_gpu); if (status != NV_OK) UVM_ASSERT(status == uvm_global_get_status()); @@ -1418,9 +1475,9 @@ static void sync_parent_gpu_trackers(uvm_parent_gpu_t *parent_gpu, // Sync the clear_faulted tracker since it inherits dependencies from the // VA block trackers, too. if (sync_clear_faulted_tracker) { - uvm_gpu_non_replayable_faults_isr_lock(parent_gpu); + uvm_parent_gpu_non_replayable_faults_isr_lock(parent_gpu); status = uvm_tracker_wait(&parent_gpu->fault_buffer_info.non_replayable.clear_faulted_tracker); - uvm_gpu_non_replayable_faults_isr_unlock(parent_gpu); + uvm_parent_gpu_non_replayable_faults_isr_unlock(parent_gpu); if (status != NV_OK) UVM_ASSERT(status == uvm_global_get_status()); @@ -1467,7 +1524,7 @@ static void deinit_parent_gpu(uvm_parent_gpu_t *parent_gpu) UVM_ASSERT(parent_gpu->isr.access_counters.handling_ref_count == 0); // Return ownership to RM - uvm_gpu_deinit_isr(parent_gpu); + uvm_parent_gpu_deinit_isr(parent_gpu); deinit_parent_procfs_files(parent_gpu); @@ -1495,7 +1552,7 @@ static void deinit_gpu(uvm_gpu_t *gpu) uvm_gpu_t *other_gpu; // Remove any pointers to this GPU from other GPUs' trackers. - for_each_global_gpu(other_gpu) { + for_each_gpu(other_gpu) { UVM_ASSERT(other_gpu != gpu); remove_gpus_from_gpu(other_gpu); } @@ -1552,7 +1609,7 @@ static void remove_gpu(uvm_gpu_t *gpu) uvm_assert_mutex_locked(&g_uvm_global.global_lock); - sub_processor_index = uvm_global_id_sub_processor_index(gpu->global_id); + sub_processor_index = uvm_id_sub_processor_index(gpu->id); parent_gpu = gpu->parent; UVM_ASSERT_MSG(uvm_gpu_retained_count(gpu) == 0, @@ -1597,15 +1654,15 @@ static void remove_gpu(uvm_gpu_t *gpu) uvm_spin_unlock_irqrestore(&g_uvm_global.gpu_table_lock); - uvm_global_processor_mask_clear(&g_uvm_global.retained_gpus, gpu->global_id); + uvm_processor_mask_clear(&g_uvm_global.retained_gpus, gpu->id); // If the parent is being freed, stop scheduling new bottom halves and // update relevant software state. Else flush any pending bottom halves // before continuing. if (free_parent) - uvm_gpu_disable_isr(parent_gpu); + uvm_parent_gpu_disable_isr(parent_gpu); else - uvm_gpu_flush_bottom_halves(parent_gpu); + uvm_parent_gpu_flush_bottom_halves(parent_gpu); deinit_gpu(gpu); @@ -1625,11 +1682,11 @@ static void uvm_parent_gpu_destroy(nv_kref_t *nv_kref) NvU32 sub_processor_index; UVM_ASSERT(parent_gpu->num_retained_gpus == 0); - UVM_ASSERT(bitmap_empty(parent_gpu->valid_gpus, UVM_ID_MAX_SUB_PROCESSORS)); + UVM_ASSERT(bitmap_empty(parent_gpu->valid_gpus, UVM_PARENT_ID_MAX_SUB_PROCESSORS)); nv_kthread_q_stop(&parent_gpu->lazy_free_q); - for (sub_processor_index = 0; sub_processor_index < UVM_ID_MAX_SUB_PROCESSORS; sub_processor_index++) + for (sub_processor_index = 0; sub_processor_index < UVM_PARENT_ID_MAX_SUB_PROCESSORS; sub_processor_index++) UVM_ASSERT(!parent_gpu->gpus[sub_processor_index]); uvm_kvfree(parent_gpu); @@ -1640,22 +1697,22 @@ void uvm_parent_gpu_kref_put(uvm_parent_gpu_t *parent_gpu) nv_kref_put(&parent_gpu->gpu_kref, uvm_parent_gpu_destroy); } -static void update_stats_gpu_fault_instance(uvm_gpu_t *gpu, - const uvm_fault_buffer_entry_t *fault_entry, - bool is_duplicate) +static void update_stats_parent_gpu_fault_instance(uvm_parent_gpu_t *parent_gpu, + const uvm_fault_buffer_entry_t *fault_entry, + bool is_duplicate) { if (!fault_entry->is_replayable) { switch (fault_entry->fault_access_type) { case UVM_FAULT_ACCESS_TYPE_READ: - ++gpu->parent->fault_buffer_info.non_replayable.stats.num_read_faults; + ++parent_gpu->fault_buffer_info.non_replayable.stats.num_read_faults; break; case UVM_FAULT_ACCESS_TYPE_WRITE: - ++gpu->parent->fault_buffer_info.non_replayable.stats.num_write_faults; + ++parent_gpu->fault_buffer_info.non_replayable.stats.num_write_faults; break; case UVM_FAULT_ACCESS_TYPE_ATOMIC_WEAK: case UVM_FAULT_ACCESS_TYPE_ATOMIC_STRONG: - ++gpu->parent->fault_buffer_info.non_replayable.stats.num_atomic_faults; + ++parent_gpu->fault_buffer_info.non_replayable.stats.num_atomic_faults; break; default: UVM_ASSERT_MSG(false, "Invalid access type for non-replayable faults\n"); @@ -1663,9 +1720,9 @@ static void update_stats_gpu_fault_instance(uvm_gpu_t *gpu, } if (!fault_entry->is_virtual) - ++gpu->parent->fault_buffer_info.non_replayable.stats.num_physical_faults; + ++parent_gpu->fault_buffer_info.non_replayable.stats.num_physical_faults; - ++gpu->parent->stats.num_non_replayable_faults; + ++parent_gpu->stats.num_non_replayable_faults; return; } @@ -1675,30 +1732,30 @@ static void update_stats_gpu_fault_instance(uvm_gpu_t *gpu, switch (fault_entry->fault_access_type) { case UVM_FAULT_ACCESS_TYPE_PREFETCH: - ++gpu->parent->fault_buffer_info.replayable.stats.num_prefetch_faults; + ++parent_gpu->fault_buffer_info.replayable.stats.num_prefetch_faults; break; case UVM_FAULT_ACCESS_TYPE_READ: - ++gpu->parent->fault_buffer_info.replayable.stats.num_read_faults; + ++parent_gpu->fault_buffer_info.replayable.stats.num_read_faults; break; case UVM_FAULT_ACCESS_TYPE_WRITE: - ++gpu->parent->fault_buffer_info.replayable.stats.num_write_faults; + ++parent_gpu->fault_buffer_info.replayable.stats.num_write_faults; break; case UVM_FAULT_ACCESS_TYPE_ATOMIC_WEAK: case UVM_FAULT_ACCESS_TYPE_ATOMIC_STRONG: - ++gpu->parent->fault_buffer_info.replayable.stats.num_atomic_faults; + ++parent_gpu->fault_buffer_info.replayable.stats.num_atomic_faults; break; default: break; } if (is_duplicate || fault_entry->filtered) - ++gpu->parent->fault_buffer_info.replayable.stats.num_duplicate_faults; + ++parent_gpu->fault_buffer_info.replayable.stats.num_duplicate_faults; - ++gpu->parent->stats.num_replayable_faults; + ++parent_gpu->stats.num_replayable_faults; } static void update_stats_fault_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data) { - uvm_gpu_t *gpu; + uvm_parent_gpu_t *parent_gpu; const uvm_fault_buffer_entry_t *fault_entry, *fault_instance; UVM_ASSERT(event_id == UVM_PERF_EVENT_FAULT); @@ -1709,16 +1766,16 @@ static void update_stats_fault_cb(uvm_perf_event_t event_id, uvm_perf_event_data // The reported fault entry must be the "representative" fault entry UVM_ASSERT(!event_data->fault.gpu.buffer_entry->filtered); - gpu = uvm_va_space_get_gpu(event_data->fault.space, event_data->fault.proc_id); + parent_gpu = uvm_va_space_get_gpu(event_data->fault.space, event_data->fault.proc_id)->parent; fault_entry = event_data->fault.gpu.buffer_entry; // Update the stats using the representative fault entry and the rest of // instances - update_stats_gpu_fault_instance(gpu, fault_entry, event_data->fault.gpu.is_duplicate); + update_stats_parent_gpu_fault_instance(parent_gpu, fault_entry, event_data->fault.gpu.is_duplicate); list_for_each_entry(fault_instance, &fault_entry->merged_instances_list, merged_instances_list) - update_stats_gpu_fault_instance(gpu, fault_instance, event_data->fault.gpu.is_duplicate); + update_stats_parent_gpu_fault_instance(parent_gpu, fault_instance, event_data->fault.gpu.is_duplicate); } static void update_stats_migration_cb(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data) @@ -1812,10 +1869,10 @@ void uvm_gpu_exit(void) uvm_parent_gpu_t *parent_gpu; for_each_parent_gpu(parent_gpu) - UVM_ASSERT_MSG(false, "GPU still present: %s\n", parent_gpu->name); + UVM_ASSERT_MSG(false, "GPU still present: %s\n", uvm_parent_gpu_name(parent_gpu)); // CPU should never be in the retained GPUs mask - UVM_ASSERT(!uvm_global_processor_mask_test(&g_uvm_global.retained_gpus, UVM_GLOBAL_ID_CPU)); + UVM_ASSERT(!uvm_processor_mask_test(&g_uvm_global.retained_gpus, UVM_ID_CPU)); } NV_STATUS uvm_gpu_init_va_space(uvm_va_space_t *va_space) @@ -1844,7 +1901,7 @@ uvm_parent_gpu_t *uvm_parent_gpu_get_by_uuid_locked(const NvProcessorUuid *gpu_u uvm_parent_gpu_t *parent_gpu; for_each_parent_gpu(parent_gpu) { - if (uvm_processor_uuid_eq(&parent_gpu->uuid, gpu_uuid)) + if (uvm_uuid_eq(&parent_gpu->uuid, gpu_uuid)) return parent_gpu; } @@ -1858,17 +1915,15 @@ uvm_parent_gpu_t *uvm_parent_gpu_get_by_uuid(const NvProcessorUuid *gpu_uuid) return uvm_parent_gpu_get_by_uuid_locked(gpu_uuid); } -static uvm_gpu_t *uvm_gpu_get_by_uuid_locked(const NvProcessorUuid *gpu_uuid) +static uvm_gpu_t *gpu_get_by_uuid_locked(const NvProcessorUuid *gpu_uuid) { uvm_gpu_id_t gpu_id; - uvm_global_gpu_id_t global_gpu_id; - uvm_gpu_t *gpu; for_each_gpu_id(gpu_id) { - global_gpu_id = uvm_global_gpu_id_from_gpu_id(gpu_id); - gpu = uvm_gpu_get(global_gpu_id); + uvm_gpu_t *gpu = uvm_gpu_get(gpu_id); + if (gpu) { - if (uvm_processor_uuid_eq(uvm_gpu_uuid(gpu), gpu_uuid)) { + if (uvm_uuid_eq(uvm_gpu_uuid(gpu), gpu_uuid)) { UVM_ASSERT(!gpu->parent->smc.enabled); return gpu; } @@ -1882,14 +1937,15 @@ uvm_gpu_t *uvm_gpu_get_by_uuid(const NvProcessorUuid *gpu_uuid) { uvm_assert_mutex_locked(&g_uvm_global.global_lock); - return uvm_gpu_get_by_uuid_locked(gpu_uuid); + return gpu_get_by_uuid_locked(gpu_uuid); } -uvm_gpu_t *uvm_gpu_get_by_parent_and_swizz_id_locked(uvm_parent_gpu_t *parent_gpu, NvU32 swizz_id) +uvm_gpu_t *uvm_gpu_get_by_parent_and_swizz_id(uvm_parent_gpu_t *parent_gpu, NvU32 swizz_id) { uvm_gpu_t *gpu; UVM_ASSERT(parent_gpu); + uvm_assert_mutex_locked(&g_uvm_global.global_lock); for_each_gpu_in_parent(parent_gpu, gpu) { if (gpu->smc.swizz_id == swizz_id) @@ -1899,20 +1955,13 @@ uvm_gpu_t *uvm_gpu_get_by_parent_and_swizz_id_locked(uvm_parent_gpu_t *parent_gp return NULL; } -uvm_gpu_t *uvm_gpu_get_by_parent_and_swizz_id(uvm_parent_gpu_t *parent_gpu, NvU32 swizz_id) -{ - uvm_assert_mutex_locked(&g_uvm_global.global_lock); - - return uvm_gpu_get_by_parent_and_swizz_id_locked(parent_gpu, swizz_id); -} - // Increment the refcount for the GPU with the given UUID. If this is the first // time that this UUID is retained, the GPU is added to UVM. // When SMC partitioning is enabled, user_rm_device contains the user handles // that were created by the caller, and that can be used to identify and // obtain information about the partition. nvUvmInterfaceGetGpuInfo returns, in -// gpu_info, whether SMC is enabled and the swizzId corresponding to the -// partition. +// gpu_info, whether SMC is enabled, the swizzId, and GI UUID corresponding to +// the partition. static NV_STATUS gpu_retain_by_uuid_locked(const NvProcessorUuid *gpu_uuid, const uvm_rm_user_object_t *user_rm_device, uvm_gpu_t **gpu_out) @@ -1923,7 +1972,7 @@ static NV_STATUS gpu_retain_by_uuid_locked(const NvProcessorUuid *gpu_uuid, UvmGpuInfo *gpu_info = NULL; UvmGpuClientInfo client_info = {0}; UvmGpuPlatformInfo gpu_platform_info = {0}; - uvm_global_gpu_id_t global_gpu_id; + uvm_gpu_id_t gpu_id; client_info.hClient = user_rm_device->user_client; client_info.hSmcPartRef = user_rm_device->user_object; @@ -1934,7 +1983,7 @@ static NV_STATUS gpu_retain_by_uuid_locked(const NvProcessorUuid *gpu_uuid, uvm_assert_mutex_locked(&g_uvm_global.global_lock); - parent_gpu = uvm_parent_gpu_get_by_uuid(gpu_uuid); + parent_gpu = uvm_parent_gpu_get_by_uuid_locked(gpu_uuid); if (parent_gpu == NULL) { // If this is the first time the UUID is seen, register it on RM @@ -1962,11 +2011,11 @@ static NV_STATUS gpu_retain_by_uuid_locked(const NvProcessorUuid *gpu_uuid, } if (gpu == NULL) { - status = find_unused_global_gpu_id(parent_gpu, &global_gpu_id); + status = find_unused_gpu_id(parent_gpu, &gpu_id); if (status != NV_OK) goto error_unregister; - status = add_gpu(gpu_uuid, global_gpu_id, gpu_info, &gpu_platform_info, parent_gpu, &gpu); + status = add_gpu(gpu_uuid, gpu_id, gpu_info, &gpu_platform_info, parent_gpu, &gpu); if (status != NV_OK) goto error_unregister; } @@ -2304,8 +2353,8 @@ static NV_STATUS init_peer_access(uvm_gpu_t *gpu0, set_optimal_p2p_write_ces(p2p_caps_params, peer_caps, gpu0, gpu1); - UVM_ASSERT(uvm_gpu_get(gpu0->global_id) == gpu0); - UVM_ASSERT(uvm_gpu_get(gpu1->global_id) == gpu1); + UVM_ASSERT(uvm_gpu_get(gpu0->id) == gpu0); + UVM_ASSERT(uvm_gpu_get(gpu1->id) == gpu1); // In the case of NVLINK peers, this initialization will happen during // add_gpu. As soon as the peer info table is assigned below, the access @@ -2444,7 +2493,7 @@ static NV_STATUS discover_nvlink_peers(uvm_gpu_t *gpu) if (gpu->parent->smc.enabled) return NV_OK; - for_each_global_gpu(other_gpu) { + for_each_gpu(other_gpu) { UvmGpuP2PCapsParams p2p_caps_params; if ((other_gpu == gpu) || other_gpu->parent->smc.enabled) @@ -2486,7 +2535,7 @@ static void destroy_nvlink_peers(uvm_gpu_t *gpu) if (gpu->parent->smc.enabled) return; - for_each_global_gpu(other_gpu) { + for_each_gpu(other_gpu) { uvm_gpu_peer_t *peer_caps; if ((other_gpu == gpu) || other_gpu->parent->smc.enabled) @@ -2568,8 +2617,8 @@ static void disable_peer_access(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1) uvm_rm_locked_call_void(nvUvmInterfaceP2pObjectDestroy(uvm_global_session_handle(), p2p_handle)); - UVM_ASSERT(uvm_gpu_get(gpu0->global_id) == gpu0); - UVM_ASSERT(uvm_gpu_get(gpu1->global_id) == gpu1); + UVM_ASSERT(uvm_gpu_get(gpu0->id) == gpu0); + UVM_ASSERT(uvm_gpu_get(gpu1->id) == gpu1); uvm_spin_lock(&gpu0->peer_info.peer_gpus_lock); uvm_processor_mask_clear(&gpu0->peer_info.peer_gpu_mask, gpu1->id); @@ -2639,13 +2688,13 @@ uvm_aperture_t uvm_gpu_peer_aperture(uvm_gpu_t *local_gpu, uvm_gpu_t *remote_gpu return uvm_gpu_peer_caps_aperture(peer_caps, local_gpu, remote_gpu); } -uvm_aperture_t uvm_gpu_page_tree_init_location(const uvm_gpu_t *gpu) +uvm_aperture_t uvm_get_page_tree_location(const uvm_parent_gpu_t *parent_gpu) { // See comment in page_tree_set_location - if (uvm_gpu_is_virt_mode_sriov_heavy(gpu)) + if (uvm_parent_gpu_is_virt_mode_sriov_heavy(parent_gpu)) return UVM_APERTURE_VID; - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return UVM_APERTURE_VID; return UVM_APERTURE_DEFAULT; @@ -2714,7 +2763,8 @@ static NvU64 instance_ptr_to_key(uvm_gpu_phys_address_t instance_ptr) return key; } -static NV_STATUS gpu_add_user_channel_subctx_info(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel) +static NV_STATUS parent_gpu_add_user_channel_subctx_info(uvm_parent_gpu_t *parent_gpu, + uvm_user_channel_t *user_channel) { uvm_gpu_phys_address_t instance_ptr = user_channel->instance_ptr.addr; NV_STATUS status = NV_OK; @@ -2738,10 +2788,10 @@ static NV_STATUS gpu_add_user_channel_subctx_info(uvm_gpu_t *gpu, uvm_user_chann uvm_kvmalloc_zero(sizeof(*new_channel_subctx_info->subctxs) * user_channel->tsg.max_subctx_count); } - uvm_spin_lock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_lock(&parent_gpu->instance_ptr_table_lock); // Check if the subcontext information for the channel already exists - channel_tree_node = uvm_rb_tree_find(&gpu->parent->tsg_table, user_channel->tsg.id); + channel_tree_node = uvm_rb_tree_find(&parent_gpu->tsg_table, user_channel->tsg.id); if (!channel_tree_node) { // We could not allocate the descriptor before taking the lock. Exiting @@ -2752,7 +2802,7 @@ static NV_STATUS gpu_add_user_channel_subctx_info(uvm_gpu_t *gpu, uvm_user_chann // Insert the new subcontext information descriptor new_channel_subctx_info->node.key = user_channel->tsg.id; - status = uvm_rb_tree_insert(&gpu->parent->tsg_table, &new_channel_subctx_info->node); + status = uvm_rb_tree_insert(&parent_gpu->tsg_table, &new_channel_subctx_info->node); UVM_ASSERT(status == NV_OK); channel_subctx_info = new_channel_subctx_info; @@ -2812,7 +2862,7 @@ static NV_STATUS gpu_add_user_channel_subctx_info(uvm_gpu_t *gpu, uvm_user_chann ++channel_subctx_info->total_refcount; exit_unlock: - uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_unlock(&parent_gpu->instance_ptr_table_lock); // Remove the pre-allocated per-TSG subctx information struct if there was // some error or it was not used @@ -2826,12 +2876,13 @@ static NV_STATUS gpu_add_user_channel_subctx_info(uvm_gpu_t *gpu, uvm_user_chann return status; } -static void gpu_remove_user_channel_subctx_info_locked(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel) +static void parent_gpu_remove_user_channel_subctx_info_locked(uvm_parent_gpu_t *parent_gpu, + uvm_user_channel_t *user_channel) { uvm_gpu_phys_address_t instance_ptr = user_channel->instance_ptr.addr; uvm_va_space_t *va_space = user_channel->gpu_va_space->va_space; - uvm_assert_spinlock_locked(&gpu->parent->instance_ptr_table_lock); + uvm_assert_spinlock_locked(&parent_gpu->instance_ptr_table_lock); // Channel subcontext info descriptor may not have been registered in // tsg_table since this function is called in some teardown paths during @@ -2840,7 +2891,7 @@ static void gpu_remove_user_channel_subctx_info_locked(uvm_gpu_t *gpu, uvm_user_ return; UVM_ASSERT_MSG(&user_channel->subctx_info->node == - uvm_rb_tree_find(&gpu->parent->tsg_table, user_channel->subctx_info->node.key), + uvm_rb_tree_find(&parent_gpu->tsg_table, user_channel->subctx_info->node.key), "CH %u:%u instance_ptr {0x%llx:%s} SubCTX %u in TSG %u: SubCTX not found in TSG table\n", user_channel->hw_runlist_id, user_channel->hw_channel_id, @@ -2883,7 +2934,7 @@ static void gpu_remove_user_channel_subctx_info_locked(uvm_gpu_t *gpu, uvm_user_ user_channel->subctx_info->subctxs[user_channel->subctx_id].va_space = NULL; if (--user_channel->subctx_info->total_refcount == 0) { - uvm_rb_tree_remove(&gpu->parent->tsg_table, &user_channel->subctx_info->node); + uvm_rb_tree_remove(&parent_gpu->tsg_table, &user_channel->subctx_info->node); uvm_kvfree(user_channel->subctx_info->subctxs); uvm_kvfree(user_channel->subctx_info); } @@ -2891,26 +2942,20 @@ static void gpu_remove_user_channel_subctx_info_locked(uvm_gpu_t *gpu, uvm_user_ user_channel->subctx_info = NULL; } -static void gpu_remove_user_channel_subctx_info(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel) -{ - uvm_spin_lock(&gpu->parent->instance_ptr_table_lock); - gpu_remove_user_channel_subctx_info_locked(gpu, user_channel); - uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); -} - -static void gpu_add_user_channel_instance_ptr(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel) +static void parent_gpu_add_user_channel_instance_ptr(uvm_parent_gpu_t *parent_gpu, + uvm_user_channel_t *user_channel) { uvm_gpu_phys_address_t instance_ptr = user_channel->instance_ptr.addr; NvU64 instance_ptr_key = instance_ptr_to_key(instance_ptr); NV_STATUS status; - uvm_spin_lock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_lock(&parent_gpu->instance_ptr_table_lock); // Insert the instance_ptr -> user_channel mapping user_channel->instance_ptr.node.key = instance_ptr_key; - status = uvm_rb_tree_insert(&gpu->parent->instance_ptr_table, &user_channel->instance_ptr.node); + status = uvm_rb_tree_insert(&parent_gpu->instance_ptr_table, &user_channel->instance_ptr.node); - uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_unlock(&parent_gpu->instance_ptr_table_lock); UVM_ASSERT_MSG(status == NV_OK, "CH %u:%u instance_ptr {0x%llx:%s} SubCTX %u in TSG %u: error %s\n", user_channel->hw_runlist_id, @@ -2922,17 +2967,18 @@ static void gpu_add_user_channel_instance_ptr(uvm_gpu_t *gpu, uvm_user_channel_t nvstatusToString(status)); } -static void gpu_remove_user_channel_instance_ptr_locked(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel) +static void parent_gpu_remove_user_channel_instance_ptr_locked(uvm_parent_gpu_t *parent_gpu, + uvm_user_channel_t *user_channel) { - uvm_assert_spinlock_locked(&gpu->parent->instance_ptr_table_lock); + uvm_assert_spinlock_locked(&parent_gpu->instance_ptr_table_lock); if (UVM_RB_TREE_EMPTY_NODE(&user_channel->instance_ptr.node)) return; - uvm_rb_tree_remove(&gpu->parent->instance_ptr_table, &user_channel->instance_ptr.node); + uvm_rb_tree_remove(&parent_gpu->instance_ptr_table, &user_channel->instance_ptr.node); } -NV_STATUS uvm_gpu_add_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel) +NV_STATUS uvm_parent_gpu_add_user_channel(uvm_parent_gpu_t *parent_gpu, uvm_user_channel_t *user_channel) { uvm_va_space_t *va_space; uvm_gpu_va_space_t *gpu_va_space = user_channel->gpu_va_space; @@ -2944,23 +2990,24 @@ NV_STATUS uvm_gpu_add_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_chan va_space = gpu_va_space->va_space; uvm_assert_rwsem_locked(&va_space->lock); - status = gpu_add_user_channel_subctx_info(gpu, user_channel); + status = parent_gpu_add_user_channel_subctx_info(parent_gpu, user_channel); if (status != NV_OK) return status; - gpu_add_user_channel_instance_ptr(gpu, user_channel); + parent_gpu_add_user_channel_instance_ptr(parent_gpu, user_channel); return NV_OK; } -static uvm_user_channel_t *instance_ptr_to_user_channel(uvm_gpu_t *gpu, uvm_gpu_phys_address_t instance_ptr) +static uvm_user_channel_t *instance_ptr_to_user_channel(uvm_parent_gpu_t *parent_gpu, + uvm_gpu_phys_address_t instance_ptr) { NvU64 key = instance_ptr_to_key(instance_ptr); uvm_rb_tree_node_t *instance_node; - uvm_assert_spinlock_locked(&gpu->parent->instance_ptr_table_lock); + uvm_assert_spinlock_locked(&parent_gpu->instance_ptr_table_lock); - instance_node = uvm_rb_tree_find(&gpu->parent->instance_ptr_table, key); + instance_node = uvm_rb_tree_find(&parent_gpu->instance_ptr_table, key); if (!instance_node) return NULL; @@ -3009,18 +3056,18 @@ static uvm_va_space_t *user_channel_and_subctx_to_va_space(uvm_user_channel_t *u return channel_subctx_info->subctxs[subctx_id].va_space; } -NV_STATUS uvm_gpu_fault_entry_to_va_space(uvm_gpu_t *gpu, - uvm_fault_buffer_entry_t *fault, - uvm_va_space_t **out_va_space) +NV_STATUS uvm_parent_gpu_fault_entry_to_va_space(uvm_parent_gpu_t *parent_gpu, + uvm_fault_buffer_entry_t *fault, + uvm_va_space_t **out_va_space) { uvm_user_channel_t *user_channel; NV_STATUS status = NV_OK; *out_va_space = NULL; - uvm_spin_lock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_lock(&parent_gpu->instance_ptr_table_lock); - user_channel = instance_ptr_to_user_channel(gpu, fault->instance_ptr); + user_channel = instance_ptr_to_user_channel(parent_gpu, fault->instance_ptr); if (!user_channel) { status = NV_ERR_INVALID_CHANNEL; goto exit_unlock; @@ -3057,14 +3104,14 @@ NV_STATUS uvm_gpu_fault_entry_to_va_space(uvm_gpu_t *gpu, } exit_unlock: - uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_unlock(&parent_gpu->instance_ptr_table_lock); return status; } -NV_STATUS uvm_gpu_access_counter_entry_to_va_space(uvm_gpu_t *gpu, - uvm_access_counter_buffer_entry_t *entry, - uvm_va_space_t **out_va_space) +NV_STATUS uvm_parent_gpu_access_counter_entry_to_va_space(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t *entry, + uvm_va_space_t **out_va_space) { uvm_user_channel_t *user_channel; NV_STATUS status = NV_OK; @@ -3072,9 +3119,9 @@ NV_STATUS uvm_gpu_access_counter_entry_to_va_space(uvm_gpu_t *gpu, *out_va_space = NULL; UVM_ASSERT(entry->address.is_virtual); - uvm_spin_lock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_lock(&parent_gpu->instance_ptr_table_lock); - user_channel = instance_ptr_to_user_channel(gpu, entry->virtual_info.instance_ptr); + user_channel = instance_ptr_to_user_channel(parent_gpu, entry->virtual_info.instance_ptr); if (!user_channel) { status = NV_ERR_INVALID_CHANNEL; goto exit_unlock; @@ -3095,12 +3142,12 @@ NV_STATUS uvm_gpu_access_counter_entry_to_va_space(uvm_gpu_t *gpu, } exit_unlock: - uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_unlock(&parent_gpu->instance_ptr_table_lock); return status; } -void uvm_gpu_remove_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel) +void uvm_parent_gpu_remove_user_channel(uvm_parent_gpu_t *parent_gpu, uvm_user_channel_t *user_channel) { uvm_va_space_t *va_space; uvm_gpu_va_space_t *gpu_va_space = user_channel->gpu_va_space; @@ -3111,10 +3158,10 @@ void uvm_gpu_remove_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channe va_space = gpu_va_space->va_space; uvm_assert_rwsem_locked_write(&va_space->lock); - uvm_spin_lock(&gpu->parent->instance_ptr_table_lock); - gpu_remove_user_channel_subctx_info_locked(gpu, user_channel); - gpu_remove_user_channel_instance_ptr_locked(gpu, user_channel); - uvm_spin_unlock(&gpu->parent->instance_ptr_table_lock); + uvm_spin_lock(&parent_gpu->instance_ptr_table_lock); + parent_gpu_remove_user_channel_subctx_info_locked(parent_gpu, user_channel); + parent_gpu_remove_user_channel_instance_ptr_locked(parent_gpu, user_channel); + uvm_spin_unlock(&parent_gpu->instance_ptr_table_lock); } static NvU64 gpu_addr_to_dma_addr(uvm_parent_gpu_t *parent_gpu, NvU64 gpu_addr) @@ -3147,7 +3194,7 @@ static NvU64 dma_addr_to_gpu_addr(uvm_parent_gpu_t *parent_gpu, NvU64 dma_addr) return gpu_addr; } -void *uvm_gpu_dma_alloc_page(uvm_parent_gpu_t *parent_gpu, gfp_t gfp_flags, NvU64 *dma_address_out) +void *uvm_parent_gpu_dma_alloc_page(uvm_parent_gpu_t *parent_gpu, gfp_t gfp_flags, NvU64 *dma_address_out) { NvU64 dma_addr; void *cpu_addr; @@ -3162,14 +3209,14 @@ void *uvm_gpu_dma_alloc_page(uvm_parent_gpu_t *parent_gpu, gfp_t gfp_flags, NvU6 return cpu_addr; } -void uvm_gpu_dma_free_page(uvm_parent_gpu_t *parent_gpu, void *va, NvU64 dma_address) +void uvm_parent_gpu_dma_free_page(uvm_parent_gpu_t *parent_gpu, void *va, NvU64 dma_address) { dma_address = gpu_addr_to_dma_addr(parent_gpu, dma_address); dma_free_coherent(&parent_gpu->pci_dev->dev, PAGE_SIZE, va, dma_address); atomic64_sub(PAGE_SIZE, &parent_gpu->mapped_cpu_pages_size); } -NV_STATUS uvm_gpu_map_cpu_pages(uvm_parent_gpu_t *parent_gpu, struct page *page, size_t size, NvU64 *dma_address_out) +NV_STATUS uvm_parent_gpu_map_cpu_pages(uvm_parent_gpu_t *parent_gpu, struct page *page, size_t size, NvU64 *dma_address_out) { NvU64 dma_addr; @@ -3187,7 +3234,7 @@ NV_STATUS uvm_gpu_map_cpu_pages(uvm_parent_gpu_t *parent_gpu, struct page *page, dma_addr + (NvU64)size, parent_gpu->dma_addressable_start, parent_gpu->dma_addressable_limit + 1, - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); return NV_ERR_INVALID_ADDRESS; } @@ -3197,7 +3244,7 @@ NV_STATUS uvm_gpu_map_cpu_pages(uvm_parent_gpu_t *parent_gpu, struct page *page, return NV_OK; } -void uvm_gpu_unmap_cpu_pages(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address, size_t size) +void uvm_parent_gpu_unmap_cpu_pages(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address, size_t size) { UVM_ASSERT(PAGE_ALIGNED(size)); diff --git a/kernel-open/nvidia-uvm/uvm_gpu.h b/kernel-open/nvidia-uvm/uvm_gpu.h index 03c9a0ba8b..7ce810ed05 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_gpu.h @@ -57,14 +57,16 @@ typedef struct { - // Number of faults from this uTLB that have been fetched but have not been serviced yet + // Number of faults from this uTLB that have been fetched but have not been + // serviced yet. NvU32 num_pending_faults; // Whether the uTLB contains fatal faults bool has_fatal_faults; - // We have issued a replay of type START_ACK_ALL while containing fatal faults. This puts - // the uTLB in lockdown mode and no new translations are accepted + // We have issued a replay of type START_ACK_ALL while containing fatal + // faults. This puts the uTLB in lockdown mode and no new translations are + // accepted. bool in_lockdown; // We have issued a cancel on this uTLB @@ -126,8 +128,8 @@ struct uvm_service_block_context_struct struct list_head service_context_list; // A mask of GPUs that need to be checked for ECC errors before the CPU - // fault handler returns, but after the VA space lock has been unlocked to - // avoid the RM/UVM VA space lock deadlocks. + // fault handler returns, but after the VA space lock has been unlocked + // to avoid the RM/UVM VA space lock deadlocks. uvm_processor_mask_t gpus_to_check_for_ecc; // This is set to throttle page fault thrashing. @@ -160,9 +162,9 @@ struct uvm_service_block_context_struct struct { - // Per-processor mask with the pages that will be resident after servicing. - // We need one mask per processor because we may coalesce faults that - // trigger migrations to different processors. + // Per-processor mask with the pages that will be resident after + // servicing. We need one mask per processor because we may coalesce + // faults that trigger migrations to different processors. uvm_page_mask_t new_residency; } per_processor_masks[UVM_ID_MAX_PROCESSORS]; @@ -179,23 +181,28 @@ struct uvm_service_block_context_struct typedef struct { // Mask of read faulted pages in a UVM_VA_BLOCK_SIZE aligned region of a SAM - // VMA. Used for batching ATS faults in a vma. + // VMA. Used for batching ATS faults in a vma. This is unused for access + // counter service requests. uvm_page_mask_t read_fault_mask; // Mask of write faulted pages in a UVM_VA_BLOCK_SIZE aligned region of a - // SAM VMA. Used for batching ATS faults in a vma. + // SAM VMA. Used for batching ATS faults in a vma. This is unused for access + // counter service requests. uvm_page_mask_t write_fault_mask; // Mask of successfully serviced pages in a UVM_VA_BLOCK_SIZE aligned region - // of a SAM VMA. Used to return ATS fault status. + // of a SAM VMA. Used to return ATS fault status. This is unused for access + // counter service requests. uvm_page_mask_t faults_serviced_mask; // Mask of successfully serviced read faults on pages in write_fault_mask. + // This is unused for access counter service requests. uvm_page_mask_t reads_serviced_mask; - // Mask of all faulted pages in a UVM_VA_BLOCK_SIZE aligned region of a - // SAM VMA. This is used as input to the prefetcher. - uvm_page_mask_t faulted_mask; + // Mask of all accessed pages in a UVM_VA_BLOCK_SIZE aligned region of a SAM + // VMA. This is used as input for access counter service requests and output + // of fault service requests. + uvm_page_mask_t accessed_mask; // Client type of the service requestor. uvm_fault_client_type_t client_type; @@ -294,11 +301,8 @@ struct uvm_fault_service_batch_context_struct struct uvm_ats_fault_invalidate_struct { - // Whether the TLB batch contains any information - bool write_faults_in_batch; - - // Batch of TLB entries to be invalidated - uvm_tlb_batch_t write_faults_tlb_batch; + bool tlb_batch_pending; + uvm_tlb_batch_t tlb_batch; }; typedef struct @@ -443,20 +447,9 @@ struct uvm_access_counter_service_batch_context_struct NvU32 num_notifications; // Boolean used to avoid sorting the fault batch by instance_ptr if we - // determine at fetch time that all the access counter notifications in the - // batch report the same instance_ptr + // determine at fetch time that all the access counter notifications in + // the batch report the same instance_ptr bool is_single_instance_ptr; - - // Scratch space, used to generate artificial physically addressed notifications. - // Virtual address notifications are always aligned to 64k. This means up to 16 - // different physical locations could have been accessed to trigger one notification. - // The sub-granularity mask can correspond to any of them. - struct - { - uvm_processor_id_t resident_processors[16]; - uvm_gpu_phys_address_t phys_addresses[16]; - uvm_access_counter_buffer_entry_t phys_entry; - } scratch; } virt; struct @@ -467,8 +460,8 @@ struct uvm_access_counter_service_batch_context_struct NvU32 num_notifications; // Boolean used to avoid sorting the fault batch by aperture if we - // determine at fetch time that all the access counter notifications in the - // batch report the same aperture + // determine at fetch time that all the access counter notifications in + // the batch report the same aperture bool is_single_aperture; } phys; @@ -478,6 +471,9 @@ struct uvm_access_counter_service_batch_context_struct // Structure used to coalesce access counter servicing in a VA block uvm_service_block_context_t block_service_context; + // Structure used to service access counter migrations in an ATS block. + uvm_ats_fault_context_t ats_context; + // Unique id (per-GPU) generated for tools events recording NvU32 batch_id; }; @@ -610,10 +606,22 @@ typedef enum UVM_GPU_PEER_COPY_MODE_COUNT } uvm_gpu_peer_copy_mode_t; +// In order to support SMC/MIG GPU partitions, we split UVM GPUs into two +// parts: parent GPUs (uvm_parent_gpu_t) which represent unique PCIe devices +// (including VFs), and sub/child GPUs (uvm_gpu_t) which represent individual +// partitions within the parent. The parent GPU and partition GPU have +// different "id" and "uuid". struct uvm_gpu_struct { uvm_parent_gpu_t *parent; + // The gpu's GI uuid if SMC is enabled; otherwise, a copy of parent->uuid. + NvProcessorUuid uuid; + + // Nice printable name in the format: ID: 999: UVM-GPU-. + // UVM_GPU_UUID_TEXT_BUFFER_LENGTH includes the null character. + char name[9 + UVM_GPU_UUID_TEXT_BUFFER_LENGTH]; + // Refcount of the gpu, i.e. how many times it has been retained. This is // roughly a count of how many times it has been registered with a VA space, // except that some paths retain the GPU temporarily without a VA space. @@ -632,13 +640,9 @@ struct uvm_gpu_struct // user can create a lot of va spaces and register the gpu with them). atomic64_t retained_count; - // A unique uvm gpu id in range [1, UVM_ID_MAX_PROCESSORS); this is a copy - // of the parent's id. + // A unique uvm gpu id in range [1, UVM_ID_MAX_PROCESSORS). uvm_gpu_id_t id; - // A unique uvm global_gpu id in range [1, UVM_GLOBAL_ID_MAX_PROCESSORS) - uvm_global_gpu_id_t global_id; - // Should be UVM_GPU_MAGIC_VALUE. Used for memory checking. NvU64 magic; @@ -664,8 +668,8 @@ struct uvm_gpu_struct struct { // Big page size used by the internal UVM VA space - // Notably it may be different than the big page size used by a user's VA - // space in general. + // Notably it may be different than the big page size used by a user's + // VA space in general. NvU32 internal_size; } big_page; @@ -691,8 +695,8 @@ struct uvm_gpu_struct // lazily-populated array of peer GPUs, indexed by the peer's GPU index uvm_gpu_t *peer_gpus[UVM_ID_MAX_GPUS]; - // Leaf spinlock used to synchronize access to the peer_gpus table so that - // it can be safely accessed from the access counters bottom half + // Leaf spinlock used to synchronize access to the peer_gpus table so + // that it can be safely accessed from the access counters bottom half uvm_spinlock_t peer_gpus_lock; } peer_info; @@ -852,6 +856,11 @@ struct uvm_gpu_struct bool uvm_test_force_upper_pushbuffer_segment; }; +// In order to support SMC/MIG GPU partitions, we split UVM GPUs into two +// parts: parent GPUs (uvm_parent_gpu_t) which represent unique PCIe devices +// (including VFs), and sub/child GPUs (uvm_gpu_t) which represent individual +// partitions within the parent. The parent GPU and partition GPU have +// different "id" and "uuid". struct uvm_parent_gpu_struct { // Reference count for how many places are holding on to a parent GPU @@ -864,11 +873,11 @@ struct uvm_parent_gpu_struct // The number of uvm_gpu_ts referencing this uvm_parent_gpu_t. NvU32 num_retained_gpus; - uvm_gpu_t *gpus[UVM_ID_MAX_SUB_PROCESSORS]; + uvm_gpu_t *gpus[UVM_PARENT_ID_MAX_SUB_PROCESSORS]; // Bitmap of valid child entries in the gpus[] table. Used to retrieve a // usable child GPU in bottom-halves. - DECLARE_BITMAP(valid_gpus, UVM_ID_MAX_SUB_PROCESSORS); + DECLARE_BITMAP(valid_gpus, UVM_PARENT_ID_MAX_SUB_PROCESSORS); // The gpu's uuid NvProcessorUuid uuid; @@ -880,8 +889,8 @@ struct uvm_parent_gpu_struct // hardware classes, etc.). UvmGpuInfo rm_info; - // A unique uvm gpu id in range [1, UVM_ID_MAX_PROCESSORS) - uvm_gpu_id_t id; + // A unique uvm gpu id in range [1, UVM_PARENT_ID_MAX_PROCESSORS) + uvm_parent_gpu_id_t id; // Reference to the Linux PCI device // @@ -916,12 +925,13 @@ struct uvm_parent_gpu_struct // dma_addressable_start (in bifSetupDmaWindow_IMPL()) and hence when // referencing sysmem from the GPU, dma_addressable_start should be // subtracted from the physical address. The DMA mapping helpers like - // uvm_gpu_map_cpu_pages() and uvm_gpu_dma_alloc_page() take care of that. + // uvm_parent_gpu_map_cpu_pages() and uvm_parent_gpu_dma_alloc_page() take + // care of that. NvU64 dma_addressable_start; NvU64 dma_addressable_limit; - // Total size (in bytes) of physically mapped (with uvm_gpu_map_cpu_pages) - // sysmem pages, used for leak detection. + // Total size (in bytes) of physically mapped (with + // uvm_parent_gpu_map_cpu_pages) sysmem pages, used for leak detection. atomic64_t mapped_cpu_pages_size; // Hardware Abstraction Layer @@ -940,7 +950,11 @@ struct uvm_parent_gpu_struct // Virtualization mode of the GPU. UVM_VIRT_MODE virt_mode; - // Whether the GPU can trigger faults on prefetch instructions + // Pascal+ GPUs can trigger faults on prefetch instructions. If false, this + // feature must be disabled at all times in GPUs of the given architecture. + // If true, the feature can be toggled at will by SW. + // + // The field should not be used unless the GPU supports replayable faults. bool prefetch_fault_supported; // Number of membars required to flush out HSHUB following a TLB invalidate @@ -955,6 +969,11 @@ struct uvm_parent_gpu_struct bool access_counters_supported; + // If this is true, physical address based access counter notifications are + // potentially generated. If false, only virtual address based notifications + // are generated (assuming access_counters_supported is true too). + bool access_counters_can_use_physical_addresses; + bool fault_cancel_va_supported; // True if the GPU has hardware support for scoped atomics @@ -981,6 +1000,10 @@ struct uvm_parent_gpu_struct bool plc_supported; + // If true, page_tree initialization pre-populates no_ats_ranges. It only + // affects ATS systems. + bool no_ats_range_required; + // Parameters used by the TLB batching API struct { @@ -1052,14 +1075,16 @@ struct uvm_parent_gpu_struct // Interrupt handling state and locks uvm_isr_info_t isr; - // Fault buffer info. This is only valid if supports_replayable_faults is set to true + // Fault buffer info. This is only valid if supports_replayable_faults is + // set to true. uvm_fault_buffer_info_t fault_buffer_info; // PMM lazy free processing queue. // TODO: Bug 3881835: revisit whether to use nv_kthread_q_t or workqueue. nv_kthread_q_t lazy_free_q; - // Access counter buffer info. This is only valid if supports_access_counters is set to true + // Access counter buffer info. This is only valid if + // supports_access_counters is set to true. uvm_access_counter_buffer_info_t access_counter_buffer_info; // Number of uTLBs per GPC. This information is only valid on Pascal+ GPUs. @@ -1109,7 +1134,7 @@ struct uvm_parent_gpu_struct uvm_rb_tree_t instance_ptr_table; uvm_spinlock_t instance_ptr_table_lock; - // This is set to true if the GPU belongs to an SLI group. Else, set to false. + // This is set to true if the GPU belongs to an SLI group. bool sli_enabled; struct @@ -1136,8 +1161,8 @@ struct uvm_parent_gpu_struct // environment, rather than using the peer-id field of the PTE (which can // only address 8 gpus), all gpus are assigned a 47-bit physical address // space by the fabric manager. Any physical address access to these - // physical address spaces are routed through the switch to the corresponding - // peer. + // physical address spaces are routed through the switch to the + // corresponding peer. struct { bool is_nvswitch_connected; @@ -1175,9 +1200,14 @@ struct uvm_parent_gpu_struct } smmu_war; }; +static const char *uvm_parent_gpu_name(uvm_parent_gpu_t *parent_gpu) +{ + return parent_gpu->name; +} + static const char *uvm_gpu_name(uvm_gpu_t *gpu) { - return gpu->parent->name; + return gpu->name; } static const NvProcessorUuid *uvm_gpu_uuid(uvm_gpu_t *gpu) @@ -1362,7 +1392,8 @@ void uvm_gpu_release_pcie_peer_access(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1); // They must not be the same gpu. uvm_aperture_t uvm_gpu_peer_aperture(uvm_gpu_t *local_gpu, uvm_gpu_t *remote_gpu); -// Get the processor id accessible by the given GPU for the given physical address +// Get the processor id accessible by the given GPU for the given physical +// address. uvm_processor_id_t uvm_gpu_get_processor_id_by_address(uvm_gpu_t *gpu, uvm_gpu_phys_address_t addr); // Get the P2P capabilities between the gpus with the given indexes @@ -1407,10 +1438,11 @@ static bool uvm_gpus_are_indirect_peers(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1) // mapping covering the passed address, has been previously created. static uvm_gpu_address_t uvm_gpu_address_virtual_from_vidmem_phys(uvm_gpu_t *gpu, NvU64 pa) { - UVM_ASSERT(uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)); + UVM_ASSERT(uvm_mmu_parent_gpu_needs_static_vidmem_mapping(gpu->parent) || + uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(gpu->parent)); UVM_ASSERT(pa <= gpu->mem_info.max_allocatable_address); - if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu)) + if (uvm_mmu_parent_gpu_needs_static_vidmem_mapping(gpu->parent)) UVM_ASSERT(gpu->static_flat_mapping.ready); return uvm_gpu_address_virtual(gpu->parent->flat_vidmem_va_base + pa); @@ -1422,12 +1454,12 @@ static uvm_gpu_address_t uvm_gpu_address_virtual_from_vidmem_phys(uvm_gpu_t *gpu // // The actual GPU mapping only exists if a linear mapping covering the passed // address has been previously created. -static uvm_gpu_address_t uvm_gpu_address_virtual_from_sysmem_phys(uvm_gpu_t *gpu, NvU64 pa) +static uvm_gpu_address_t uvm_parent_gpu_address_virtual_from_sysmem_phys(uvm_parent_gpu_t *parent_gpu, NvU64 pa) { - UVM_ASSERT(uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)); - UVM_ASSERT(pa <= (gpu->parent->dma_addressable_limit - gpu->parent->dma_addressable_start)); + UVM_ASSERT(uvm_mmu_parent_gpu_needs_dynamic_sysmem_mapping(parent_gpu)); + UVM_ASSERT(pa <= (parent_gpu->dma_addressable_limit - parent_gpu->dma_addressable_start)); - return uvm_gpu_address_virtual(gpu->parent->flat_sysmem_va_base + pa); + return uvm_gpu_address_virtual(parent_gpu->flat_sysmem_va_base + pa); } // Given a GPU or CPU physical address (not peer), retrieve an address suitable @@ -1437,11 +1469,12 @@ static uvm_gpu_address_t uvm_gpu_address_copy(uvm_gpu_t *gpu, uvm_gpu_phys_addre UVM_ASSERT(phys_addr.aperture == UVM_APERTURE_VID || phys_addr.aperture == UVM_APERTURE_SYS); if (phys_addr.aperture == UVM_APERTURE_VID) { - if (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) + if (uvm_mmu_parent_gpu_needs_static_vidmem_mapping(gpu->parent) || + uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(gpu->parent)) return uvm_gpu_address_virtual_from_vidmem_phys(gpu, phys_addr.address); } - else if (uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) { - return uvm_gpu_address_virtual_from_sysmem_phys(gpu, phys_addr.address); + else if (uvm_mmu_parent_gpu_needs_dynamic_sysmem_mapping(gpu->parent)) { + return uvm_parent_gpu_address_virtual_from_sysmem_phys(gpu->parent, phys_addr.address); } return uvm_gpu_address_from_phys(phys_addr); @@ -1459,9 +1492,9 @@ NV_STATUS uvm_gpu_check_ecc_error(uvm_gpu_t *gpu); // Check for ECC errors without calling into RM // -// Calling into RM is problematic in many places, this check is always safe to do. -// Returns NV_WARN_MORE_PROCESSING_REQUIRED if there might be an ECC error and -// it's required to call uvm_gpu_check_ecc_error() to be sure. +// Calling into RM is problematic in many places, this check is always safe to +// do. Returns NV_WARN_MORE_PROCESSING_REQUIRED if there might be an ECC error +// and it's required to call uvm_gpu_check_ecc_error() to be sure. NV_STATUS uvm_gpu_check_ecc_error_no_rm(uvm_gpu_t *gpu); // Map size bytes of contiguous sysmem on the GPU for physical access @@ -1470,19 +1503,19 @@ NV_STATUS uvm_gpu_check_ecc_error_no_rm(uvm_gpu_t *gpu); // // Returns the physical address of the pages that can be used to access them on // the GPU. -NV_STATUS uvm_gpu_map_cpu_pages(uvm_parent_gpu_t *parent_gpu, struct page *page, size_t size, NvU64 *dma_address_out); +NV_STATUS uvm_parent_gpu_map_cpu_pages(uvm_parent_gpu_t *parent_gpu, struct page *page, size_t size, NvU64 *dma_address_out); -// Unmap num_pages pages previously mapped with uvm_gpu_map_cpu_pages(). -void uvm_gpu_unmap_cpu_pages(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address, size_t size); +// Unmap num_pages pages previously mapped with uvm_parent_gpu_map_cpu_pages(). +void uvm_parent_gpu_unmap_cpu_pages(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address, size_t size); -static NV_STATUS uvm_gpu_map_cpu_page(uvm_parent_gpu_t *parent_gpu, struct page *page, NvU64 *dma_address_out) +static NV_STATUS uvm_parent_gpu_map_cpu_page(uvm_parent_gpu_t *parent_gpu, struct page *page, NvU64 *dma_address_out) { - return uvm_gpu_map_cpu_pages(parent_gpu, page, PAGE_SIZE, dma_address_out); + return uvm_parent_gpu_map_cpu_pages(parent_gpu, page, PAGE_SIZE, dma_address_out); } -static void uvm_gpu_unmap_cpu_page(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address) +static void uvm_parent_gpu_unmap_cpu_page(uvm_parent_gpu_t *parent_gpu, NvU64 dma_address) { - uvm_gpu_unmap_cpu_pages(parent_gpu, dma_address, PAGE_SIZE); + uvm_parent_gpu_unmap_cpu_pages(parent_gpu, dma_address, PAGE_SIZE); } // Allocate and map a page of system DMA memory on the GPU for physical access @@ -1491,13 +1524,13 @@ static void uvm_gpu_unmap_cpu_page(uvm_parent_gpu_t *parent_gpu, NvU64 dma_addre // - the address of the page that can be used to access them on // the GPU in the dma_address_out parameter. // - the address of allocated memory in CPU virtual address space. -void *uvm_gpu_dma_alloc_page(uvm_parent_gpu_t *parent_gpu, - gfp_t gfp_flags, - NvU64 *dma_address_out); +void *uvm_parent_gpu_dma_alloc_page(uvm_parent_gpu_t *parent_gpu, + gfp_t gfp_flags, + NvU64 *dma_address_out); // Unmap and free size bytes of contiguous sysmem DMA previously allocated -// with uvm_gpu_map_cpu_pages(). -void uvm_gpu_dma_free_page(uvm_parent_gpu_t *parent_gpu, void *va, NvU64 dma_address); +// with uvm_parent_gpu_map_cpu_pages(). +void uvm_parent_gpu_dma_free_page(uvm_parent_gpu_t *parent_gpu, void *va, NvU64 dma_address); // Returns whether the given range is within the GPU's addressable VA ranges. // It requires the input 'addr' to be in canonical form for platforms compliant @@ -1518,6 +1551,8 @@ bool uvm_gpu_can_address(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); // The GPU must be initialized before calling this function. bool uvm_gpu_can_address_kernel(uvm_gpu_t *gpu, NvU64 addr, NvU64 size); +bool uvm_platform_uses_canonical_form_address(void); + // Returns addr's canonical form for host systems that use canonical form // addresses. NvU64 uvm_parent_gpu_canonical_address(uvm_parent_gpu_t *parent_gpu, NvU64 addr); @@ -1527,47 +1562,49 @@ static bool uvm_parent_gpu_is_coherent(const uvm_parent_gpu_t *parent_gpu) return parent_gpu->system_bus.memory_window_end > parent_gpu->system_bus.memory_window_start; } -static bool uvm_gpu_has_pushbuffer_segments(uvm_gpu_t *gpu) +static bool uvm_parent_gpu_needs_pushbuffer_segments(uvm_parent_gpu_t *parent_gpu) { - return gpu->parent->max_host_va > (1ull << 40); + return parent_gpu->max_host_va > (1ull << 40); } -static bool uvm_gpu_supports_eviction(uvm_gpu_t *gpu) +static bool uvm_parent_gpu_supports_eviction(uvm_parent_gpu_t *parent_gpu) { // Eviction is supported only if the GPU supports replayable faults - return gpu->parent->replayable_faults_supported; + return parent_gpu->replayable_faults_supported; } -static bool uvm_gpu_is_virt_mode_sriov_heavy(const uvm_gpu_t *gpu) +static bool uvm_parent_gpu_is_virt_mode_sriov_heavy(const uvm_parent_gpu_t *parent_gpu) { - return gpu->parent->virt_mode == UVM_VIRT_MODE_SRIOV_HEAVY; + return parent_gpu->virt_mode == UVM_VIRT_MODE_SRIOV_HEAVY; } -static bool uvm_gpu_is_virt_mode_sriov_standard(const uvm_gpu_t *gpu) +static bool uvm_parent_gpu_is_virt_mode_sriov_standard(const uvm_parent_gpu_t *parent_gpu) { - return gpu->parent->virt_mode == UVM_VIRT_MODE_SRIOV_STANDARD; + return parent_gpu->virt_mode == UVM_VIRT_MODE_SRIOV_STANDARD; } // Returns true if the virtualization mode is SR-IOV heavy or SR-IOV standard. -static bool uvm_gpu_is_virt_mode_sriov(const uvm_gpu_t *gpu) +static bool uvm_parent_gpu_is_virt_mode_sriov(const uvm_parent_gpu_t *parent_gpu) { - return uvm_gpu_is_virt_mode_sriov_heavy(gpu) || uvm_gpu_is_virt_mode_sriov_standard(gpu); + return uvm_parent_gpu_is_virt_mode_sriov_heavy(parent_gpu) || + uvm_parent_gpu_is_virt_mode_sriov_standard(parent_gpu); } -static bool uvm_gpu_uses_proxy_channel_pool(const uvm_gpu_t *gpu) +static bool uvm_parent_gpu_needs_proxy_channel_pool(const uvm_parent_gpu_t *parent_gpu) { - return uvm_gpu_is_virt_mode_sriov_heavy(gpu); + return uvm_parent_gpu_is_virt_mode_sriov_heavy(parent_gpu); } -uvm_aperture_t uvm_gpu_page_tree_init_location(const uvm_gpu_t *gpu); +uvm_aperture_t uvm_get_page_tree_location(const uvm_parent_gpu_t *parent_gpu); // Debug print of GPU properties void uvm_gpu_print(uvm_gpu_t *gpu); -// Add the given instance pointer -> user_channel mapping to this GPU. The bottom -// half GPU page fault handler uses this to look up the VA space for GPU faults. -NV_STATUS uvm_gpu_add_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel); -void uvm_gpu_remove_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channel); +// Add the given instance pointer -> user_channel mapping to this GPU. The +// bottom half GPU page fault handler uses this to look up the VA space for GPU +// faults. +NV_STATUS uvm_parent_gpu_add_user_channel(uvm_parent_gpu_t *parent_gpu, uvm_user_channel_t *user_channel); +void uvm_parent_gpu_remove_user_channel(uvm_parent_gpu_t *parent_gpu, uvm_user_channel_t *user_channel); // Looks up an entry added by uvm_gpu_add_user_channel. Return codes: // NV_OK Translation successful @@ -1578,13 +1615,13 @@ void uvm_gpu_remove_user_channel(uvm_gpu_t *gpu, uvm_user_channel_t *user_channe // out_va_space is valid if NV_OK is returned, otherwise it's NULL. The caller // is responsibile for ensuring that the returned va_space can't be destroyed, // so these functions should only be called from the bottom half. -NV_STATUS uvm_gpu_fault_entry_to_va_space(uvm_gpu_t *gpu, - uvm_fault_buffer_entry_t *fault, - uvm_va_space_t **out_va_space); +NV_STATUS uvm_parent_gpu_fault_entry_to_va_space(uvm_parent_gpu_t *parent_gpu, + uvm_fault_buffer_entry_t *fault, + uvm_va_space_t **out_va_space); -NV_STATUS uvm_gpu_access_counter_entry_to_va_space(uvm_gpu_t *gpu, - uvm_access_counter_buffer_entry_t *entry, - uvm_va_space_t **out_va_space); +NV_STATUS uvm_parent_gpu_access_counter_entry_to_va_space(uvm_parent_gpu_t *parent_gpu, + uvm_access_counter_buffer_entry_t *entry, + uvm_va_space_t **out_va_space); typedef enum { diff --git a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c index e0d40a2ce8..8b58d99554 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_access_counters.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2022 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,17 +33,18 @@ #include "uvm_va_space_mm.h" #include "uvm_pmm_sysmem.h" #include "uvm_perf_module.h" +#include "uvm_ats_ibm.h" +#include "uvm_ats_faults.h" #define UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_MIN 1 #define UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_DEFAULT 256 -#define UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT "2m" +#define UVM_PERF_ACCESS_COUNTER_GRANULARITY UVM_ACCESS_COUNTER_GRANULARITY_2M #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_MIN 1 #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_MAX ((1 << 16) - 1) #define UVM_PERF_ACCESS_COUNTER_THRESHOLD_DEFAULT 256 -#define UVM_ACCESS_COUNTER_ACTION_NOTIFY 0x1 -#define UVM_ACCESS_COUNTER_ACTION_CLEAR 0x2 -#define UVM_ACCESS_COUNTER_ON_MANAGED 0x4 +#define UVM_ACCESS_COUNTER_ACTION_CLEAR 0x1 +#define UVM_ACCESS_COUNTER_PHYS_ON_MANAGED 0x2 // Each page in a tracked physical range may belong to a different VA Block. We // preallocate an array of reverse map translations. However, access counter @@ -54,12 +55,6 @@ #define UVM_MAX_TRANSLATION_SIZE (2 * 1024 * 1024ULL) #define UVM_SUB_GRANULARITY_REGIONS 32 -// The GPU offers the following tracking granularities: 64K, 2M, 16M, 16G -// -// Use the largest granularity to minimize the number of access counter -// notifications. This is fine because we simply drop the notifications during -// normal operation, and tests override these values. -static UVM_ACCESS_COUNTER_GRANULARITY g_uvm_access_counter_granularity; static unsigned g_uvm_access_counter_threshold; // Per-VA space access counters information @@ -87,7 +82,6 @@ static int uvm_perf_access_counter_momc_migration_enable = -1; static unsigned uvm_perf_access_counter_batch_count = UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_DEFAULT; // See module param documentation below -static char *uvm_perf_access_counter_granularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT; static unsigned uvm_perf_access_counter_threshold = UVM_PERF_ACCESS_COUNTER_THRESHOLD_DEFAULT; // Module parameters for the tunables @@ -100,10 +94,6 @@ MODULE_PARM_DESC(uvm_perf_access_counter_momc_migration_enable, "Whether MOMC access counters will trigger migrations." "Valid values: <= -1 (default policy), 0 (off), >= 1 (on)"); module_param(uvm_perf_access_counter_batch_count, uint, S_IRUGO); -module_param(uvm_perf_access_counter_granularity, charp, S_IRUGO); -MODULE_PARM_DESC(uvm_perf_access_counter_granularity, - "Size of the physical memory region tracked by each counter. Valid values as" - "of Volta: 64k, 2m, 16m, 16g"); module_param(uvm_perf_access_counter_threshold, uint, S_IRUGO); MODULE_PARM_DESC(uvm_perf_access_counter_threshold, "Number of remote accesses on a region required to trigger a notification." @@ -136,7 +126,7 @@ static va_space_access_counters_info_t *va_space_access_counters_info_get(uvm_va // Whether access counter migrations are enabled or not. The policy is as // follows: -// - MIMC migrations are enabled by default on P9 systems with ATS support +// - MIMC migrations are disabled by default on all systems except P9. // - MOMC migrations are disabled by default on all systems // - Users can override this policy by specifying on/off static bool is_migration_enabled(uvm_access_counter_type_t type) @@ -159,7 +149,10 @@ static bool is_migration_enabled(uvm_access_counter_type_t type) if (type == UVM_ACCESS_COUNTER_TYPE_MOMC) return false; - return g_uvm_global.ats.supported; + if (UVM_ATS_IBM_SUPPORTED()) + return g_uvm_global.ats.supported; + + return false; } // Create the access counters tracking struct for the given VA space @@ -225,30 +218,18 @@ static NV_STATUS config_granularity_to_bytes(UVM_ACCESS_COUNTER_GRANULARITY gran return NV_OK; } -// Clear the given access counter and add it to the per-GPU clear tracker -static NV_STATUS access_counter_clear_targeted(uvm_gpu_t *gpu, - const uvm_access_counter_buffer_entry_t *entry) +// Clear the access counter notifications and add it to the per-GPU clear +// tracker. +static NV_STATUS access_counter_clear_notifications(uvm_gpu_t *gpu, + uvm_access_counter_buffer_entry_t **notification_start, + NvU32 num_notifications) { + NvU32 i; NV_STATUS status; uvm_push_t push; uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; - if (entry->address.is_virtual) { - status = uvm_push_begin(gpu->channel_manager, - UVM_CHANNEL_TYPE_MEMOPS, - &push, - "Clear access counter with virtual address: 0x%llx", - entry->address.address); - } - else { - status = uvm_push_begin(gpu->channel_manager, - UVM_CHANNEL_TYPE_MEMOPS, - &push, - "Clear access counter with physical address: 0x%llx:%s", - entry->address.address, - uvm_aperture_string(entry->address.aperture)); - } - + status = uvm_push_begin(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, &push, "Clear access counter batch"); if (status != NV_OK) { UVM_ERR_PRINT("Error creating push to clear access counters: %s, GPU %s\n", nvstatusToString(status), @@ -256,7 +237,8 @@ static NV_STATUS access_counter_clear_targeted(uvm_gpu_t *gpu, return status; } - gpu->parent->host_hal->access_counter_clear_targeted(&push, entry); + for (i = 0; i < num_notifications; i++) + gpu->parent->host_hal->access_counter_clear_targeted(&push, notification_start[i]); uvm_push_end(&push); @@ -381,25 +363,6 @@ NV_STATUS uvm_gpu_init_access_counters(uvm_parent_gpu_t *parent_gpu) g_uvm_access_counter_threshold = uvm_perf_access_counter_threshold; } - if (strcmp(uvm_perf_access_counter_granularity, "64k") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_64K; - } - else if (strcmp(uvm_perf_access_counter_granularity, "2m") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_2M; - } - else if (strcmp(uvm_perf_access_counter_granularity, "16m") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_16M; - } - else if (strcmp(uvm_perf_access_counter_granularity, "16g") == 0) { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_16G; - } - else { - g_uvm_access_counter_granularity = UVM_ACCESS_COUNTER_GRANULARITY_2M; - pr_info("Invalid value '%s' for uvm_perf_access_counter_granularity, using '%s' instead", - uvm_perf_access_counter_granularity, - UVM_PERF_ACCESS_COUNTER_GRANULARITY_DEFAULT); - } - uvm_assert_mutex_locked(&g_uvm_global.global_lock); UVM_ASSERT(parent_gpu->access_counter_buffer_hal != NULL); @@ -409,7 +372,7 @@ NV_STATUS uvm_gpu_init_access_counters(uvm_parent_gpu_t *parent_gpu) if (status != NV_OK) { UVM_ERR_PRINT("Failed to init notify buffer info from RM: %s, GPU %s\n", nvstatusToString(status), - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); // nvUvmInterfaceInitAccessCntrInfo may leave fields in rm_info // populated when it returns an error. Set the buffer handle to zero as @@ -422,7 +385,7 @@ NV_STATUS uvm_gpu_init_access_counters(uvm_parent_gpu_t *parent_gpu) UVM_ASSERT(access_counters->rm_info.bufferSize % parent_gpu->access_counter_buffer_hal->entry_size(parent_gpu) == 0); - status = config_granularity_to_bytes(g_uvm_access_counter_granularity, &granularity_bytes); + status = config_granularity_to_bytes(UVM_PERF_ACCESS_COUNTER_GRANULARITY, &granularity_bytes); UVM_ASSERT(status == NV_OK); if (granularity_bytes > UVM_MAX_TRANSLATION_SIZE) UVM_ASSERT(granularity_bytes % UVM_MAX_TRANSLATION_SIZE == 0); @@ -443,7 +406,7 @@ NV_STATUS uvm_gpu_init_access_counters(uvm_parent_gpu_t *parent_gpu) if (access_counters->max_batch_size != uvm_perf_access_counter_batch_count) { pr_info("Invalid uvm_perf_access_counter_batch_count value on GPU %s: %u. Valid range [%u:%u] Using %u instead\n", - parent_gpu->name, + uvm_parent_gpu_name(parent_gpu), uvm_perf_access_counter_batch_count, UVM_PERF_ACCESS_COUNTER_BATCH_COUNT_MIN, access_counters->max_notifications, @@ -633,7 +596,7 @@ NV_STATUS uvm_gpu_access_counters_enable(uvm_gpu_t *gpu, uvm_va_space_t *va_spac UVM_ASSERT(gpu->parent->access_counters_supported); - uvm_gpu_access_counters_isr_lock(gpu->parent); + uvm_parent_gpu_access_counters_isr_lock(gpu->parent); if (uvm_processor_mask_test(&va_space->access_counters_enabled_processors, gpu->id)) { status = NV_ERR_INVALID_DEVICE; @@ -641,8 +604,8 @@ NV_STATUS uvm_gpu_access_counters_enable(uvm_gpu_t *gpu, uvm_va_space_t *va_spac else { UvmGpuAccessCntrConfig default_config = { - .mimcGranularity = g_uvm_access_counter_granularity, - .momcGranularity = g_uvm_access_counter_granularity, + .mimcGranularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY, + .momcGranularity = UVM_PERF_ACCESS_COUNTER_GRANULARITY, .mimcUseLimit = UVM_ACCESS_COUNTER_USE_LIMIT_FULL, .momcUseLimit = UVM_ACCESS_COUNTER_USE_LIMIT_FULL, .threshold = g_uvm_access_counter_threshold, @@ -658,7 +621,7 @@ NV_STATUS uvm_gpu_access_counters_enable(uvm_gpu_t *gpu, uvm_va_space_t *va_spac // If this is the first reference taken on access counters, dropping the // ISR lock will enable interrupts. - uvm_gpu_access_counters_isr_unlock(gpu->parent); + uvm_parent_gpu_access_counters_isr_unlock(gpu->parent); return status; } @@ -667,7 +630,7 @@ void uvm_gpu_access_counters_disable(uvm_gpu_t *gpu, uvm_va_space_t *va_space) { UVM_ASSERT(gpu->parent->access_counters_supported); - uvm_gpu_access_counters_isr_lock(gpu->parent); + uvm_parent_gpu_access_counters_isr_lock(gpu->parent); if (uvm_processor_mask_test_and_clear_atomic(&va_space->access_counters_enabled_processors, gpu->id)) { gpu_access_counters_disable(gpu); @@ -678,7 +641,7 @@ void uvm_gpu_access_counters_disable(uvm_gpu_t *gpu, uvm_va_space_t *va_space) gpu->parent->access_counter_buffer_info.reconfiguration_owner = NULL; } - uvm_gpu_access_counters_isr_unlock(gpu->parent); + uvm_parent_gpu_access_counters_isr_unlock(gpu->parent); } static void write_get(uvm_parent_gpu_t *parent_gpu, NvU32 get) @@ -733,12 +696,12 @@ void uvm_gpu_access_counter_buffer_flush(uvm_gpu_t *gpu) UVM_ASSERT(gpu->parent->access_counters_supported); // Disables access counter interrupts and notification servicing - uvm_gpu_access_counters_isr_lock(gpu->parent); + uvm_parent_gpu_access_counters_isr_lock(gpu->parent); if (gpu->parent->isr.access_counters.handling_ref_count > 0) access_counter_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_UPDATE_PUT); - uvm_gpu_access_counters_isr_unlock(gpu->parent); + uvm_parent_gpu_access_counters_isr_unlock(gpu->parent); } static inline int cmp_access_counter_instance_ptr(const uvm_access_counter_buffer_entry_t *a, @@ -767,6 +730,22 @@ static int cmp_sort_virt_notifications_by_instance_ptr(const void *_a, const voi return cmp_access_counter_instance_ptr(a, b); } +// Sort comparator for pointers to GVA access counter notification buffer +// entries that sorts by va_space, and fault address. +static int cmp_sort_virt_notifications_by_va_space_address(const void *_a, const void *_b) +{ + const uvm_access_counter_buffer_entry_t **a = (const uvm_access_counter_buffer_entry_t **)_a; + const uvm_access_counter_buffer_entry_t **b = (const uvm_access_counter_buffer_entry_t **)_b; + + int result; + + result = UVM_CMP_DEFAULT((*a)->virtual_info.va_space, (*b)->virtual_info.va_space); + if (result != 0) + return result; + + return UVM_CMP_DEFAULT((*a)->address.address, (*b)->address.address); +} + // Sort comparator for pointers to GPA access counter notification buffer // entries that sorts by physical address' aperture static int cmp_sort_phys_notifications_by_processor_id(const void *_a, const void *_b) @@ -896,7 +875,7 @@ static NvU32 fetch_access_counter_buffer_entries(uvm_gpu_t *gpu, return notification_index; } -static void translate_virt_notifications_instance_ptrs(uvm_gpu_t *gpu, +static void translate_virt_notifications_instance_ptrs(uvm_parent_gpu_t *parent_gpu, uvm_access_counter_service_batch_context_t *batch_context) { NvU32 i; @@ -910,9 +889,9 @@ static void translate_virt_notifications_instance_ptrs(uvm_gpu_t *gpu, // If instance_ptr is different, make a new translation. If the // translation fails then va_space will be NULL and the entry will // simply be ignored in subsequent processing. - status = uvm_gpu_access_counter_entry_to_va_space(gpu, - current_entry, - ¤t_entry->virtual_info.va_space); + status = uvm_parent_gpu_access_counter_entry_to_va_space(parent_gpu, + current_entry, + ¤t_entry->virtual_info.va_space); if (status != NV_OK) UVM_ASSERT(current_entry->virtual_info.va_space == NULL); } @@ -924,12 +903,11 @@ static void translate_virt_notifications_instance_ptrs(uvm_gpu_t *gpu, // GVA notifications provide an instance_ptr and ve_id that can be directly // translated to a VA space. In order to minimize translations, we sort the -// entries by instance_ptr. -static void preprocess_virt_notifications(uvm_gpu_t *gpu, +// entries by instance_ptr, va_space and notification address in that order. +static void preprocess_virt_notifications(uvm_parent_gpu_t *parent_gpu, uvm_access_counter_service_batch_context_t *batch_context) { if (!batch_context->virt.is_single_instance_ptr) { - // Sort by instance_ptr sort(batch_context->virt.notifications, batch_context->virt.num_notifications, sizeof(*batch_context->virt.notifications), @@ -937,7 +915,13 @@ static void preprocess_virt_notifications(uvm_gpu_t *gpu, NULL); } - translate_virt_notifications_instance_ptrs(gpu, batch_context); + translate_virt_notifications_instance_ptrs(parent_gpu, batch_context); + + sort(batch_context->virt.notifications, + batch_context->virt.num_notifications, + sizeof(*batch_context->virt.notifications), + cmp_sort_virt_notifications_by_va_space_address, + NULL); } // GPA notifications provide a physical address and an aperture. Sort @@ -946,7 +930,6 @@ static void preprocess_virt_notifications(uvm_gpu_t *gpu, static void preprocess_phys_notifications(uvm_access_counter_service_batch_context_t *batch_context) { if (!batch_context->phys.is_single_aperture) { - // Sort by instance_ptr sort(batch_context->phys.notifications, batch_context->phys.num_notifications, sizeof(*batch_context->phys.notifications), @@ -955,6 +938,28 @@ static void preprocess_phys_notifications(uvm_access_counter_service_batch_conte } } +static NV_STATUS notify_tools_and_process_flags(uvm_gpu_t *gpu, + uvm_access_counter_buffer_entry_t **notification_start, + NvU32 num_entries, + NvU32 flags) +{ + NV_STATUS status = NV_OK; + + if (uvm_enable_builtin_tests) { + // TODO: Bug 4310744: [UVM][TOOLS] Attribute access counter tools events + // to va_space instead of broadcasting. + NvU32 i; + + for (i = 0; i < num_entries; i++) + uvm_tools_broadcast_access_counter(gpu, notification_start[i], flags & UVM_ACCESS_COUNTER_PHYS_ON_MANAGED); + } + + if (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR) + status = access_counter_clear_notifications(gpu, notification_start, num_entries); + + return status; +} + static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, @@ -969,6 +974,7 @@ static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, uvm_page_index_t last_page_index; NvU32 page_count = 0; const uvm_page_mask_t *residency_mask; + const bool hmm_migratable = true; uvm_assert_mutex_locked(&va_block->lock); @@ -1055,6 +1061,7 @@ static NV_STATUS service_va_block_locked(uvm_processor_id_t processor, policy, &thrashing_hint, UVM_SERVICE_OPERATION_ACCESS_COUNTERS, + hmm_migratable, &read_duplicate); if (!uvm_processor_mask_test_and_set(&service_context->resident_processors, new_residency)) @@ -1163,7 +1170,7 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *current_entry, const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { size_t index; uvm_va_block_t *va_block = reverse_mappings[0].va_block; @@ -1190,7 +1197,6 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, // If an mm is registered with the VA space, we have to retain it // in order to lock it before locking the VA space. mm = uvm_va_space_mm_retain_lock(va_space); - uvm_va_space_down_read(va_space); // Re-check that the VA block is valid after taking the VA block lock. @@ -1208,10 +1214,8 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, service_context->num_retries = 0; service_context->block_context->mm = mm; - if (uvm_va_block_is_hmm(va_block)) { - uvm_hmm_service_context_init(service_context); + if (uvm_va_block_is_hmm(va_block)) uvm_hmm_migrate_begin_wait(va_block); - } uvm_mutex_lock(&va_block->lock); @@ -1226,9 +1230,15 @@ static NV_STATUS service_phys_single_va_block(uvm_gpu_t *gpu, uvm_mutex_unlock(&va_block->lock); - if (uvm_va_block_is_hmm(va_block)) + if (uvm_va_block_is_hmm(va_block)) { uvm_hmm_migrate_finish(va_block); + // If the pages could not be migrated, no need to try again, + // this is best effort only. + if (status == NV_WARN_MORE_PROCESSING_REQUIRED || status == NV_WARN_MISMATCHED_TARGET) + status = NV_OK; + } + if (status == NV_OK) *out_flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; } @@ -1251,7 +1261,7 @@ static NV_STATUS service_phys_va_blocks(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *current_entry, const uvm_reverse_map_t *reverse_mappings, size_t num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { NV_STATUS status = NV_OK; size_t index; @@ -1259,7 +1269,7 @@ static NV_STATUS service_phys_va_blocks(uvm_gpu_t *gpu, *out_flags &= ~UVM_ACCESS_COUNTER_ACTION_CLEAR; for (index = 0; index < num_reverse_mappings; ++index) { - unsigned out_flags_local = 0; + NvU32 out_flags_local = 0; status = service_phys_single_va_block(gpu, batch_context, current_entry, @@ -1318,7 +1328,7 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, NvU64 address, unsigned long sub_granularity, size_t *num_reverse_mappings, - unsigned *out_flags) + NvU32 *out_flags) { NV_STATUS status; NvU32 region_start, region_end; @@ -1327,7 +1337,10 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, // Get the reverse_map translations for all the regions set in the // sub_granularity field of the counter. - for_each_sub_granularity_region(region_start, region_end, sub_granularity, config->sub_granularity_regions_per_translation) { + for_each_sub_granularity_region(region_start, + region_end, + sub_granularity, + config->sub_granularity_regions_per_translation) { NvU64 local_address = address + region_start * config->sub_granularity_region_size; NvU32 local_translation_size = (region_end - region_start) * config->sub_granularity_region_size; uvm_reverse_map_t *local_reverse_mappings = batch_context->phys.translations + *num_reverse_mappings; @@ -1376,7 +1389,7 @@ static NV_STATUS service_phys_notification_translation(uvm_gpu_t *gpu, static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context, const uvm_access_counter_buffer_entry_t *current_entry, - unsigned *out_flags) + NvU32 *out_flags) { NvU64 address; NvU64 translation_index; @@ -1387,7 +1400,7 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, size_t total_reverse_mappings = 0; uvm_gpu_t *resident_gpu = NULL; NV_STATUS status = NV_OK; - unsigned flags = 0; + NvU32 flags = 0; address = current_entry->address.address; UVM_ASSERT(address % config->translation_size == 0); @@ -1397,7 +1410,7 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, sub_granularity = 1; if (UVM_ID_IS_GPU(current_entry->physical_info.resident_id)) { - resident_gpu = uvm_gpu_get_by_processor_id(current_entry->physical_info.resident_id); + resident_gpu = uvm_gpu_get(current_entry->physical_info.resident_id); UVM_ASSERT(resident_gpu != NULL); if (gpu != resident_gpu && uvm_gpus_are_nvswitch_connected(gpu, resident_gpu)) { @@ -1415,7 +1428,7 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, for (translation_index = 0; translation_index < config->translations_per_counter; ++translation_index) { size_t num_reverse_mappings; - unsigned out_flags_local = 0; + NvU32 out_flags_local = 0; status = service_phys_notification_translation(gpu, resident_gpu, batch_context, @@ -1437,11 +1450,8 @@ static NV_STATUS service_phys_notification(uvm_gpu_t *gpu, sub_granularity = sub_granularity >> config->sub_granularity_regions_per_translation; } - // Currently we only report events for our tests, not for tools - if (uvm_enable_builtin_tests) { - *out_flags |= UVM_ACCESS_COUNTER_ACTION_NOTIFY; - *out_flags |= ((total_reverse_mappings != 0) ? UVM_ACCESS_COUNTER_ON_MANAGED : 0); - } + if (uvm_enable_builtin_tests) + *out_flags |= ((total_reverse_mappings != 0) ? UVM_ACCESS_COUNTER_PHYS_ON_MANAGED : 0); if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) *out_flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; @@ -1454,22 +1464,23 @@ static NV_STATUS service_phys_notifications(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context) { NvU32 i; + uvm_access_counter_buffer_entry_t **notifications = batch_context->phys.notifications; + + UVM_ASSERT(gpu->parent->access_counters_can_use_physical_addresses); + preprocess_phys_notifications(batch_context); for (i = 0; i < batch_context->phys.num_notifications; ++i) { NV_STATUS status; - uvm_access_counter_buffer_entry_t *current_entry = batch_context->phys.notifications[i]; - unsigned flags = 0; + uvm_access_counter_buffer_entry_t *current_entry = notifications[i]; + NvU32 flags = 0; if (!UVM_ID_IS_VALID(current_entry->physical_info.resident_id)) continue; status = service_phys_notification(gpu, batch_context, current_entry, &flags); - if (flags & UVM_ACCESS_COUNTER_ACTION_NOTIFY) - uvm_tools_broadcast_access_counter(gpu, current_entry, flags & UVM_ACCESS_COUNTER_ON_MANAGED); - if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) - status = access_counter_clear_targeted(gpu, current_entry); + notify_tools_and_process_flags(gpu, ¬ifications[i], 1, flags); if (status != NV_OK) return status; @@ -1478,152 +1489,304 @@ static NV_STATUS service_phys_notifications(uvm_gpu_t *gpu, return NV_OK; } -static int cmp_sort_gpu_phys_addr(const void *_a, const void *_b) +static NV_STATUS service_notification_va_block_helper(struct mm_struct *mm, + uvm_va_block_t *va_block, + uvm_processor_id_t processor, + uvm_access_counter_service_batch_context_t *batch_context) { - return uvm_gpu_phys_addr_cmp(*(uvm_gpu_phys_address_t*)_a, - *(uvm_gpu_phys_address_t*)_b); + uvm_va_block_retry_t va_block_retry; + uvm_page_mask_t *accessed_pages = &batch_context->accessed_pages; + uvm_service_block_context_t *service_context = &batch_context->block_service_context; + + if (uvm_page_mask_empty(accessed_pages)) + return NV_OK; + + uvm_assert_mutex_locked(&va_block->lock); + + service_context->operation = UVM_SERVICE_OPERATION_ACCESS_COUNTERS; + service_context->num_retries = 0; + + uvm_va_block_context_init(service_context->block_context, mm); + + return UVM_VA_BLOCK_RETRY_LOCKED(va_block, + &va_block_retry, + service_va_block_locked(processor, + va_block, + &va_block_retry, + service_context, + accessed_pages)); } -static bool gpu_phys_same_region(uvm_gpu_phys_address_t a, uvm_gpu_phys_address_t b, NvU64 granularity) +static void expand_notification_block(uvm_gpu_va_space_t *gpu_va_space, + uvm_va_block_t *va_block, + uvm_page_mask_t *accessed_pages, + const uvm_access_counter_buffer_entry_t *current_entry) { - if (a.aperture != b.aperture) - return false; + NvU64 addr; + NvU64 granularity = 0; + uvm_gpu_t *resident_gpu = NULL; + uvm_processor_id_t resident_id; + uvm_page_index_t page_index; + uvm_gpu_t *gpu = gpu_va_space->gpu; + const uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; + const uvm_gpu_access_counter_type_config_t *config = get_config_for_type(access_counters, + UVM_ACCESS_COUNTER_TYPE_MIMC); + + config_granularity_to_bytes(config->rm.granularity, &granularity); + + // Granularities other than 2MB can only be enabled by UVM tests. Do nothing + // in that case. + if (granularity != UVM_PAGE_SIZE_2M) + return; + + addr = current_entry->address.address; + + uvm_assert_rwsem_locked(&gpu_va_space->va_space->lock); + uvm_assert_mutex_locked(&va_block->lock); + + page_index = uvm_va_block_cpu_page_index(va_block, addr); - UVM_ASSERT(is_power_of_2(granularity)); + resident_id = uvm_va_block_page_get_closest_resident(va_block, page_index, gpu->id); - return UVM_ALIGN_DOWN(a.address, granularity) == UVM_ALIGN_DOWN(b.address, granularity); + // resident_id might be invalid or might already be the same as the GPU + // which received the notification if the memory was already migrated before + // acquiring the locks either during the servicing of previous notifications + // or during faults or because of explicit migrations or if the VA range was + // freed after receiving the notification. Return NV_OK in such cases. + if (!UVM_ID_IS_VALID(resident_id) || uvm_id_equal(resident_id, gpu->id)) + return; + + if (UVM_ID_IS_GPU(resident_id)) + resident_gpu = uvm_va_space_get_gpu(gpu_va_space->va_space, resident_id); + + if (uvm_va_block_get_physical_size(va_block, resident_id, page_index) != granularity) { + uvm_page_mask_set(accessed_pages, page_index); + } + else { + NvU32 region_start; + NvU32 region_end; + unsigned long sub_granularity = current_entry->sub_granularity; + NvU32 num_regions = config->sub_granularity_regions_per_translation; + NvU32 num_sub_pages = config->sub_granularity_region_size / PAGE_SIZE; + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, resident_id, NUMA_NO_NODE); + + UVM_ASSERT(num_sub_pages >= 1); + + // region_start and region_end refer to sub_granularity indices, not + // page_indices. + for_each_sub_granularity_region(region_start, region_end, sub_granularity, num_regions) { + uvm_page_mask_region_fill(accessed_pages, + uvm_va_block_region(region_start * num_sub_pages, + region_end * num_sub_pages)); + } + + // Remove pages in the va_block which are not resident on resident_id. + // If the GPU is heavily accessing those pages, future access counter + // migrations will migrate them to the GPU. + uvm_page_mask_and(accessed_pages, accessed_pages, resident_mask); + } } -static bool phys_address_in_accessed_sub_region(uvm_gpu_phys_address_t address, - NvU64 region_size, - NvU64 sub_region_size, - NvU32 accessed_mask) +static NV_STATUS service_virt_notifications_in_block(uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm, + uvm_va_block_t *va_block, + uvm_access_counter_service_batch_context_t *batch_context, + NvU32 index, + NvU32 *out_index) { - const unsigned accessed_index = (address.address % region_size) / sub_region_size; + NvU32 i; + NvU32 flags = 0; + NV_STATUS status = NV_OK; + NV_STATUS flags_status; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_va_space_t *va_space = gpu_va_space->va_space; + uvm_page_mask_t *accessed_pages = &batch_context->accessed_pages; + uvm_access_counter_buffer_entry_t **notifications = batch_context->virt.notifications; - // accessed_mask is only filled for tracking granularities larger than 64K - if (region_size == UVM_PAGE_SIZE_64K) - return true; + UVM_ASSERT(va_block); + UVM_ASSERT(index < batch_context->virt.num_notifications); + + uvm_assert_rwsem_locked(&va_space->lock); + + uvm_page_mask_zero(accessed_pages); + + uvm_mutex_lock(&va_block->lock); + + for (i = index; i < batch_context->virt.num_notifications; i++) { + uvm_access_counter_buffer_entry_t *current_entry = notifications[i]; + NvU64 address = current_entry->address.address; + + if ((current_entry->virtual_info.va_space == va_space) && (address <= va_block->end)) + expand_notification_block(gpu_va_space, va_block, accessed_pages, current_entry); + else + break; + } + + *out_index = i; - UVM_ASSERT(accessed_index < 32); - return ((1 << accessed_index) & accessed_mask) != 0; + // Atleast one notification should have been processed. + UVM_ASSERT(index < *out_index); + + status = service_notification_va_block_helper(mm, va_block, gpu->id, batch_context); + + uvm_mutex_unlock(&va_block->lock); + + if (status == NV_OK) + flags |= UVM_ACCESS_COUNTER_ACTION_CLEAR; + + flags_status = notify_tools_and_process_flags(gpu, ¬ifications[index], *out_index - index, flags); + + if ((status == NV_OK) && (flags_status != NV_OK)) + status = flags_status; + + return status; } -static NV_STATUS service_virt_notification(uvm_gpu_t *gpu, - uvm_access_counter_service_batch_context_t *batch_context, - const uvm_access_counter_buffer_entry_t *current_entry, - unsigned *out_flags) +static NV_STATUS service_virt_notification_ats(uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm, + uvm_access_counter_service_batch_context_t *batch_context, + NvU32 index, + NvU32 *out_index) { - NV_STATUS status = NV_OK; - NvU64 notification_size; + + NvU32 i; + NvU64 base; + NvU64 end; NvU64 address; - uvm_processor_id_t *resident_processors = batch_context->virt.scratch.resident_processors; - uvm_gpu_phys_address_t *phys_addresses = batch_context->virt.scratch.phys_addresses; - int num_addresses = 0; - int i; + NvU32 flags = UVM_ACCESS_COUNTER_ACTION_CLEAR; + NV_STATUS status = NV_OK; + NV_STATUS flags_status; + struct vm_area_struct *vma = NULL; + uvm_gpu_t *gpu = gpu_va_space->gpu; + uvm_va_space_t *va_space = gpu_va_space->va_space; + uvm_ats_fault_context_t *ats_context = &batch_context->ats_context; + uvm_access_counter_buffer_entry_t **notifications = batch_context->virt.notifications; + + UVM_ASSERT(index < batch_context->virt.num_notifications); + + uvm_assert_mmap_lock_locked(mm); + uvm_assert_rwsem_locked(&va_space->lock); + + address = notifications[index]->address.address; + + vma = find_vma_intersection(mm, address, address + 1); + if (!vma) { + // Clear the notification entry to continue receiving access counter + // notifications when a new VMA is allocated in this range. + status = notify_tools_and_process_flags(gpu, ¬ifications[index], 1, flags); + *out_index = index + 1; + return status; + } - // Virtual address notifications are always 64K aligned - NvU64 region_start = current_entry->address.address; - NvU64 region_end = current_entry->address.address + UVM_PAGE_SIZE_64K; - + base = UVM_VA_BLOCK_ALIGN_DOWN(address); + end = min(base + UVM_VA_BLOCK_SIZE, (NvU64)vma->vm_end); - uvm_access_counter_buffer_info_t *access_counters = &gpu->parent->access_counter_buffer_info; - uvm_access_counter_type_t counter_type = current_entry->counter_type; + uvm_page_mask_zero(&ats_context->accessed_mask); - const uvm_gpu_access_counter_type_config_t *config = get_config_for_type(access_counters, counter_type); + for (i = index; i < batch_context->virt.num_notifications; i++) { + uvm_access_counter_buffer_entry_t *current_entry = notifications[i]; + address = current_entry->address.address; - uvm_va_space_t *va_space = current_entry->virtual_info.va_space; + if ((current_entry->virtual_info.va_space == va_space) && (address < end)) + uvm_page_mask_set(&ats_context->accessed_mask, (address - base) / PAGE_SIZE); + else + break; + } - UVM_ASSERT(counter_type == UVM_ACCESS_COUNTER_TYPE_MIMC); + *out_index = i; - // Entries with NULL va_space are simply dropped. - if (!va_space) - return NV_OK; + // Atleast one notification should have been processed. + UVM_ASSERT(index < *out_index); - status = config_granularity_to_bytes(config->rm.granularity, ¬ification_size); + status = uvm_ats_service_access_counters(gpu_va_space, vma, base, ats_context); if (status != NV_OK) - return status; + flags &= ~UVM_ACCESS_COUNTER_ACTION_CLEAR; - // Collect physical locations that could have been touched - // in the reported 64K VA region. The notification mask can - // correspond to any of them. - uvm_va_space_down_read(va_space); - for (address = region_start; address < region_end;) { - uvm_va_block_t *va_block; + flags_status = notify_tools_and_process_flags(gpu, ¬ifications[index], *out_index - index, flags); + if ((status == NV_OK) && (flags_status != NV_OK)) + status = flags_status; - NV_STATUS local_status = uvm_va_block_find(va_space, address, &va_block); - if (local_status == NV_ERR_INVALID_ADDRESS || local_status == NV_ERR_OBJECT_NOT_FOUND) { - address += PAGE_SIZE; - continue; - } + return status; +} - uvm_mutex_lock(&va_block->lock); - while (address < va_block->end && address < region_end) { - const unsigned page_index = uvm_va_block_cpu_page_index(va_block, address); - - // UVM va_block always maps the closest resident location to processor - const uvm_processor_id_t res_id = uvm_va_block_page_get_closest_resident(va_block, page_index, gpu->id); - - // Add physical location if it's valid and not local vidmem - if (UVM_ID_IS_VALID(res_id) && !uvm_id_equal(res_id, gpu->id)) { - uvm_gpu_phys_address_t phys_address = uvm_va_block_res_phys_page_address(va_block, page_index, res_id, gpu); - if (phys_address_in_accessed_sub_region(phys_address, - notification_size, - config->sub_granularity_region_size, - current_entry->sub_granularity)) { - resident_processors[num_addresses] = res_id; - phys_addresses[num_addresses] = phys_address; - ++num_addresses; - } - else { - UVM_DBG_PRINT_RL("Skipping phys address %llx:%s, because it couldn't have been accessed in mask %x", - phys_address.address, - uvm_aperture_string(phys_address.aperture), - current_entry->sub_granularity); - } - } +static NV_STATUS service_virt_notifications_batch(uvm_gpu_va_space_t *gpu_va_space, + struct mm_struct *mm, + uvm_access_counter_service_batch_context_t *batch_context, + NvU32 index, + NvU32 *out_index) +{ + NV_STATUS status; + uvm_va_range_t *va_range; + uvm_va_space_t *va_space = gpu_va_space->va_space; + uvm_access_counter_buffer_entry_t *current_entry = batch_context->virt.notifications[index]; + NvU64 address = current_entry->address.address; + + UVM_ASSERT(va_space); + + if (mm) + uvm_assert_mmap_lock_locked(mm); + + uvm_assert_rwsem_locked(&va_space->lock); + + // Virtual address notifications are always 64K aligned + UVM_ASSERT(IS_ALIGNED(address, UVM_PAGE_SIZE_64K)); + + va_range = uvm_va_range_find(va_space, address); + if (va_range) { + // Avoid clearing the entry by default. + NvU32 flags = 0; + uvm_va_block_t *va_block = NULL; + + if (va_range->type == UVM_VA_RANGE_TYPE_MANAGED) { + size_t index = uvm_va_range_block_index(va_range, address); + + va_block = uvm_va_range_block(va_range, index); - address += PAGE_SIZE; + // If the va_range is a managed range, the notification belongs to a + // recently freed va_range if va_block is NULL. If va_block is not + // NULL, service_virt_notifications_in_block will process flags. + // Clear the notification entry to continue receiving notifications + // when a new va_range is allocated in that region. + flags = UVM_ACCESS_COUNTER_ACTION_CLEAR; } - uvm_mutex_unlock(&va_block->lock); + + if (va_block) { + status = service_virt_notifications_in_block(gpu_va_space, mm, va_block, batch_context, index, out_index); + } + else { + status = notify_tools_and_process_flags(gpu_va_space->gpu, batch_context->virt.notifications, 1, flags); + *out_index = index + 1; + } + } + else if (uvm_ats_can_service_faults(gpu_va_space, mm)) { + status = service_virt_notification_ats(gpu_va_space, mm, batch_context, index, out_index); } - uvm_va_space_up_read(va_space); + else { + NvU32 flags; + uvm_va_block_t *va_block = NULL; - // The addresses need to be sorted to aid coalescing. - sort(phys_addresses, - num_addresses, - sizeof(*phys_addresses), - cmp_sort_gpu_phys_addr, - NULL); + status = uvm_hmm_va_block_find(va_space, address, &va_block); - for (i = 0; i < num_addresses; ++i) { - uvm_access_counter_buffer_entry_t *fake_entry = &batch_context->virt.scratch.phys_entry; + // TODO: Bug 4309292: [UVM][HMM] Re-enable access counter HMM block + // migrations for virtual notifications + // + // - If the va_block is HMM, don't clear the notification since HMM + // migrations are currently disabled. + // + // - If the va_block isn't HMM, the notification belongs to a recently + // freed va_range. Clear the notification entry to continue receiving + // notifications when a new va_range is allocated in this region. + flags = va_block ? 0 : UVM_ACCESS_COUNTER_ACTION_CLEAR; - // Skip the current pointer if the physical region was already handled - if (i > 0 && gpu_phys_same_region(phys_addresses[i - 1], phys_addresses[i], notification_size)) { - UVM_ASSERT(uvm_id_equal(resident_processors[i - 1], resident_processors[i])); - continue; - } - UVM_DBG_PRINT_RL("Faking MIMC address[%i/%i]: %llx (granularity mask: %llx) in aperture %s on device %s\n", - i, - num_addresses, - phys_addresses[i].address, - notification_size - 1, - uvm_aperture_string(phys_addresses[i].aperture), - uvm_gpu_name(gpu)); - - // Construct a fake phys addr AC entry - fake_entry->counter_type = current_entry->counter_type; - fake_entry->address.address = UVM_ALIGN_DOWN(phys_addresses[i].address, notification_size); - fake_entry->address.aperture = phys_addresses[i].aperture; - fake_entry->address.is_virtual = false; - fake_entry->physical_info.resident_id = resident_processors[i]; - fake_entry->counter_value = current_entry->counter_value; - fake_entry->sub_granularity = current_entry->sub_granularity; - - status = service_phys_notification(gpu, batch_context, fake_entry, out_flags); - if (status != NV_OK) - break; + UVM_ASSERT((status == NV_ERR_OBJECT_NOT_FOUND) || + (status == NV_ERR_INVALID_ADDRESS) || + uvm_va_block_is_hmm(va_block)); + + // Clobber status to continue processing the rest of the notifications + // in the batch. + status = notify_tools_and_process_flags(gpu_va_space->gpu, batch_context->virt.notifications, 1, flags); + + *out_index = index + 1; } return status; @@ -1632,33 +1795,67 @@ static NV_STATUS service_virt_notification(uvm_gpu_t *gpu, static NV_STATUS service_virt_notifications(uvm_gpu_t *gpu, uvm_access_counter_service_batch_context_t *batch_context) { - NvU32 i; + NvU32 i = 0; NV_STATUS status = NV_OK; - preprocess_virt_notifications(gpu, batch_context); + struct mm_struct *mm = NULL; + uvm_va_space_t *va_space = NULL; + uvm_va_space_t *prev_va_space = NULL; + uvm_gpu_va_space_t *gpu_va_space = NULL; - for (i = 0; i < batch_context->virt.num_notifications; ++i) { - unsigned flags = 0; + // TODO: Bug 4299018 : Add support for virtual access counter migrations on + // 4K page sizes. + if (PAGE_SIZE == UVM_PAGE_SIZE_4K) { + return notify_tools_and_process_flags(gpu, + batch_context->virt.notifications, + batch_context->virt.num_notifications, + 0); + } + + preprocess_virt_notifications(gpu->parent, batch_context); + + while (i < batch_context->virt.num_notifications) { uvm_access_counter_buffer_entry_t *current_entry = batch_context->virt.notifications[i]; + va_space = current_entry->virtual_info.va_space; - status = service_virt_notification(gpu, batch_context, current_entry, &flags); + if (va_space != prev_va_space) { - UVM_DBG_PRINT_RL("Processed virt access counter (%d/%d): %sMANAGED (status: %d) clear: %s\n", - i + 1, - batch_context->virt.num_notifications, - (flags & UVM_ACCESS_COUNTER_ON_MANAGED) ? "" : "NOT ", - status, - (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR) ? "YES" : "NO"); + // New va_space detected, drop locks of the old va_space. + if (prev_va_space) { + uvm_va_space_up_read(prev_va_space); + uvm_va_space_mm_release_unlock(prev_va_space, mm); - if (uvm_enable_builtin_tests) - uvm_tools_broadcast_access_counter(gpu, current_entry, flags & UVM_ACCESS_COUNTER_ON_MANAGED); + mm = NULL; + gpu_va_space = NULL; + } - if (status == NV_OK && (flags & UVM_ACCESS_COUNTER_ACTION_CLEAR)) - status = access_counter_clear_targeted(gpu, current_entry); + // Acquire locks for the new va_space. + if (va_space) { + mm = uvm_va_space_mm_retain_lock(va_space); + uvm_va_space_down_read(va_space); + + gpu_va_space = uvm_gpu_va_space_get_by_parent_gpu(va_space, gpu->parent); + } + + prev_va_space = va_space; + } + + if (va_space && gpu_va_space && uvm_va_space_has_access_counter_migrations(va_space)) { + status = service_virt_notifications_batch(gpu_va_space, mm, batch_context, i, &i); + } + else { + status = notify_tools_and_process_flags(gpu, &batch_context->virt.notifications[i], 1, 0); + i++; + } if (status != NV_OK) break; } + if (va_space) { + uvm_va_space_up_read(va_space); + uvm_va_space_mm_release_unlock(va_space, mm); + } + return status; } @@ -1682,13 +1879,17 @@ void uvm_gpu_service_access_counters(uvm_gpu_t *gpu) ++batch_context->batch_id; - status = service_virt_notifications(gpu, batch_context); - if (status != NV_OK) - break; + if (batch_context->virt.num_notifications) { + status = service_virt_notifications(gpu, batch_context); + if (status != NV_OK) + break; + } - status = service_phys_notifications(gpu, batch_context); - if (status != NV_OK) - break; + if (batch_context->phys.num_notifications) { + status = service_phys_notifications(gpu, batch_context); + if (status != NV_OK) + break; + } } if (status != NV_OK) { @@ -1816,7 +2017,7 @@ NV_STATUS uvm_test_reconfigure_access_counters(UVM_TEST_RECONFIGURE_ACCESS_COUNT // ISR lock ensures that we own GET/PUT registers. It disables interrupts // and ensures that no other thread (nor the top half) will be able to // re-enable interrupts during reconfiguration. - uvm_gpu_access_counters_isr_lock(gpu->parent); + uvm_parent_gpu_access_counters_isr_lock(gpu->parent); uvm_va_space_down_read_rm(va_space); @@ -1896,7 +2097,7 @@ NV_STATUS uvm_test_reconfigure_access_counters(UVM_TEST_RECONFIGURE_ACCESS_COUNT if (status != NV_OK) uvm_va_space_up_read_rm(va_space); - uvm_gpu_access_counters_isr_unlock(gpu->parent); + uvm_parent_gpu_access_counters_isr_unlock(gpu->parent); exit_release_gpu: uvm_gpu_release(gpu); @@ -1928,7 +2129,7 @@ NV_STATUS uvm_test_reset_access_counters(UVM_TEST_RESET_ACCESS_COUNTERS_PARAMS * goto exit_release_gpu; } - uvm_gpu_access_counters_isr_lock(gpu->parent); + uvm_parent_gpu_access_counters_isr_lock(gpu->parent); // Access counters not enabled. Nothing to reset if (gpu->parent->isr.access_counters.handling_ref_count == 0) @@ -1941,6 +2142,7 @@ NV_STATUS uvm_test_reset_access_counters(UVM_TEST_RESET_ACCESS_COUNTERS_PARAMS * } else { uvm_access_counter_buffer_entry_t entry = { 0 }; + uvm_access_counter_buffer_entry_t *notification = &entry; if (params->counter_type == UVM_TEST_ACCESS_COUNTER_TYPE_MIMC) entry.counter_type = UVM_ACCESS_COUNTER_TYPE_MIMC; @@ -1950,14 +2152,14 @@ NV_STATUS uvm_test_reset_access_counters(UVM_TEST_RESET_ACCESS_COUNTERS_PARAMS * entry.bank = params->bank; entry.tag = params->tag; - status = access_counter_clear_targeted(gpu, &entry); + status = access_counter_clear_notifications(gpu, ¬ification, 1); } if (status == NV_OK) status = uvm_tracker_wait(&access_counters->clear_tracker); exit_isr_unlock: - uvm_gpu_access_counters_isr_unlock(gpu->parent); + uvm_parent_gpu_access_counters_isr_unlock(gpu->parent); exit_release_gpu: uvm_gpu_release(gpu); @@ -1972,7 +2174,7 @@ void uvm_gpu_access_counters_set_ignore(uvm_gpu_t *gpu, bool do_ignore) if (!gpu->parent->access_counters_supported) return; - uvm_gpu_access_counters_isr_lock(gpu->parent); + uvm_parent_gpu_access_counters_isr_lock(gpu->parent); if (do_ignore) { if (gpu->parent->access_counter_buffer_info.notifications_ignored_count++ == 0) @@ -1990,9 +2192,9 @@ void uvm_gpu_access_counters_set_ignore(uvm_gpu_t *gpu, bool do_ignore) uvm_spin_lock_irqsave(&gpu->parent->isr.interrupts_lock); if (do_ignore) - uvm_gpu_access_counters_intr_disable(gpu->parent); + uvm_parent_gpu_access_counters_intr_disable(gpu->parent); else - uvm_gpu_access_counters_intr_enable(gpu->parent); + uvm_parent_gpu_access_counters_intr_enable(gpu->parent); uvm_spin_unlock_irqrestore(&gpu->parent->isr.interrupts_lock); @@ -2000,7 +2202,7 @@ void uvm_gpu_access_counters_set_ignore(uvm_gpu_t *gpu, bool do_ignore) access_counter_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_CACHED_PUT); } - uvm_gpu_access_counters_isr_unlock(gpu->parent); + uvm_parent_gpu_access_counters_isr_unlock(gpu->parent); } NV_STATUS uvm_test_set_ignore_access_counters(UVM_TEST_SET_IGNORE_ACCESS_COUNTERS_PARAMS *params, struct file *filp) diff --git a/kernel-open/nvidia-uvm/uvm_gpu_isr.c b/kernel-open/nvidia-uvm/uvm_gpu_isr.c index 33e7142d21..295ae2f802 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_isr.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_isr.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -67,21 +67,21 @@ static void access_counters_isr_bottom_half_entry(void *args); // interrupts should be disabled. The caller is guaranteed that replayable page // faults are disabled upon return. Interrupts might already be disabled prior // to making this call. Each call is ref-counted, so this must be paired with a -// call to uvm_gpu_replayable_faults_intr_enable(). +// call to uvm_parent_gpu_replayable_faults_intr_enable(). // // parent_gpu->isr.interrupts_lock must be held to call this function. -static void uvm_gpu_replayable_faults_intr_disable(uvm_parent_gpu_t *parent_gpu); +static void uvm_parent_gpu_replayable_faults_intr_disable(uvm_parent_gpu_t *parent_gpu); // Decrements the reference count tracking whether replayable page fault // interrupts should be disabled. Only once the count reaches 0 are the HW // interrupts actually enabled, so this call does not guarantee that the // interrupts have been re-enabled upon return. // -// uvm_gpu_replayable_faults_intr_disable() must have been called prior to -// calling this function. +// uvm_parent_gpu_replayable_faults_intr_disable() must have been called prior +// to calling this function. // // parent_gpu->isr.interrupts_lock must be held to call this function. -static void uvm_gpu_replayable_faults_intr_enable(uvm_parent_gpu_t *parent_gpu); +static void uvm_parent_gpu_replayable_faults_intr_enable(uvm_parent_gpu_t *parent_gpu); static unsigned schedule_replayable_faults_handler(uvm_parent_gpu_t *parent_gpu) { @@ -108,7 +108,7 @@ static unsigned schedule_replayable_faults_handler(uvm_parent_gpu_t *parent_gpu) nv_kref_get(&parent_gpu->gpu_kref); // Interrupts need to be disabled here to avoid an interrupt storm - uvm_gpu_replayable_faults_intr_disable(parent_gpu); + uvm_parent_gpu_replayable_faults_intr_disable(parent_gpu); // Schedule a bottom half, but do *not* release the GPU ISR lock. The bottom // half releases the GPU ISR lock as part of its cleanup. @@ -175,7 +175,7 @@ static unsigned schedule_access_counters_handler(uvm_parent_gpu_t *parent_gpu) nv_kref_get(&parent_gpu->gpu_kref); // Interrupts need to be disabled to avoid an interrupt storm - uvm_gpu_access_counters_intr_disable(parent_gpu); + uvm_parent_gpu_access_counters_intr_disable(parent_gpu); nv_kthread_q_schedule_q_item(&parent_gpu->isr.bottom_half_q, &parent_gpu->isr.access_counters.bottom_half_q_item); @@ -288,7 +288,7 @@ static NV_STATUS init_queue_on_node(nv_kthread_q_t *queue, const char *name, int return errno_to_nv_status(nv_kthread_q_init(queue, name)); } -NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) +NV_STATUS uvm_parent_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) { NV_STATUS status = NV_OK; char kthread_name[TASK_COMM_LEN + 1]; @@ -299,7 +299,7 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) if (status != NV_OK) { UVM_ERR_PRINT("Failed to initialize GPU fault buffer: %s, GPU: %s\n", nvstatusToString(status), - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); return status; } @@ -320,12 +320,12 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) parent_gpu->isr.replayable_faults.handling = true; - snprintf(kthread_name, sizeof(kthread_name), "UVM GPU%u BH", uvm_id_value(parent_gpu->id)); + snprintf(kthread_name, sizeof(kthread_name), "UVM GPU%u BH", uvm_parent_id_value(parent_gpu->id)); status = init_queue_on_node(&parent_gpu->isr.bottom_half_q, kthread_name, parent_gpu->closest_cpu_numa_node); if (status != NV_OK) { UVM_ERR_PRINT("Failed in nv_kthread_q_init for bottom_half_q: %s, GPU %s\n", nvstatusToString(status), - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); return status; } @@ -348,14 +348,14 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) parent_gpu->isr.non_replayable_faults.handling = true; - snprintf(kthread_name, sizeof(kthread_name), "UVM GPU%u KC", uvm_id_value(parent_gpu->id)); + snprintf(kthread_name, sizeof(kthread_name), "UVM GPU%u KC", uvm_parent_id_value(parent_gpu->id)); status = init_queue_on_node(&parent_gpu->isr.kill_channel_q, kthread_name, parent_gpu->closest_cpu_numa_node); if (status != NV_OK) { UVM_ERR_PRINT("Failed in nv_kthread_q_init for kill_channel_q: %s, GPU %s\n", nvstatusToString(status), - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); return status; } } @@ -365,7 +365,7 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) if (status != NV_OK) { UVM_ERR_PRINT("Failed to initialize GPU access counters: %s, GPU: %s\n", nvstatusToString(status), - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); return status; } @@ -393,13 +393,13 @@ NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu) return NV_OK; } -void uvm_gpu_flush_bottom_halves(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_flush_bottom_halves(uvm_parent_gpu_t *parent_gpu) { nv_kthread_q_flush(&parent_gpu->isr.bottom_half_q); nv_kthread_q_flush(&parent_gpu->isr.kill_channel_q); } -void uvm_gpu_disable_isr(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_disable_isr(uvm_parent_gpu_t *parent_gpu) { UVM_ASSERT(parent_gpu->isr.access_counters.handling_ref_count == 0); @@ -408,7 +408,7 @@ void uvm_gpu_disable_isr(uvm_parent_gpu_t *parent_gpu) // any more bottom halves. uvm_spin_lock_irqsave(&parent_gpu->isr.interrupts_lock); - uvm_gpu_replayable_faults_intr_disable(parent_gpu); + uvm_parent_gpu_replayable_faults_intr_disable(parent_gpu); parent_gpu->isr.replayable_faults.was_handling = parent_gpu->isr.replayable_faults.handling; parent_gpu->isr.non_replayable_faults.was_handling = parent_gpu->isr.non_replayable_faults.handling; @@ -428,7 +428,7 @@ void uvm_gpu_disable_isr(uvm_parent_gpu_t *parent_gpu) nv_kthread_q_stop(&parent_gpu->isr.kill_channel_q); } -void uvm_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu) { uvm_va_block_context_t *block_context; @@ -436,22 +436,23 @@ void uvm_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu) if (parent_gpu->isr.replayable_faults.was_handling) { // No user threads could have anything left on // replayable_faults.disable_intr_ref_count since they must retain the - // GPU across uvm_gpu_replayable_faults_isr_lock/ - // uvm_gpu_replayable_faults_isr_unlock. This means the + // GPU across uvm_parent_gpu_replayable_faults_isr_lock/ + // uvm_parent_gpu_replayable_faults_isr_unlock. This means the // uvm_gpu_replayable_faults_disable_intr above could only have raced // with bottom halves. // // If we cleared replayable_faults.handling before the bottom half got - // to its uvm_gpu_replayable_faults_isr_unlock, when it eventually - // reached uvm_gpu_replayable_faults_isr_unlock it would have skipped - // the disable, leaving us with extra ref counts here. + // to its uvm_parent_gpu_replayable_faults_isr_unlock, when it + // eventually reached uvm_parent_gpu_replayable_faults_isr_unlock it + // would have skipped the disable, leaving us with extra ref counts + // here. // // In any case we're guaranteed that replayable faults interrupts are // disabled and can't get re-enabled, so we can safely ignore the ref // count value and just clean things up. UVM_ASSERT_MSG(parent_gpu->isr.replayable_faults.disable_intr_ref_count > 0, "%s replayable_faults.disable_intr_ref_count: %llu\n", - parent_gpu->name, + uvm_parent_gpu_name(parent_gpu), parent_gpu->isr.replayable_faults.disable_intr_ref_count); uvm_gpu_fault_buffer_deinit(parent_gpu); @@ -480,7 +481,6 @@ void uvm_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu) static uvm_gpu_t *find_first_valid_gpu(uvm_parent_gpu_t *parent_gpu) { - uvm_global_gpu_id_t global_gpu_id = uvm_global_gpu_id_from_gpu_id(parent_gpu->id); uvm_gpu_t *gpu; // When SMC is enabled, there's no longer a 1:1 relationship between the @@ -495,10 +495,10 @@ static uvm_gpu_t *find_first_valid_gpu(uvm_parent_gpu_t *parent_gpu) uvm_spin_lock_irqsave(&g_uvm_global.gpu_table_lock); - sub_processor_index = find_first_bit(parent_gpu->valid_gpus, UVM_ID_MAX_SUB_PROCESSORS); + sub_processor_index = find_first_bit(parent_gpu->valid_gpus, UVM_PARENT_ID_MAX_SUB_PROCESSORS); - if (sub_processor_index < UVM_ID_MAX_SUB_PROCESSORS) { - gpu = uvm_gpu_get(uvm_global_id_from_value(uvm_global_id_value(global_gpu_id) + sub_processor_index)); + if (sub_processor_index < UVM_PARENT_ID_MAX_SUB_PROCESSORS) { + gpu = parent_gpu->gpus[sub_processor_index]; UVM_ASSERT(gpu != NULL); } else { @@ -508,7 +508,7 @@ static uvm_gpu_t *find_first_valid_gpu(uvm_parent_gpu_t *parent_gpu) uvm_spin_unlock_irqrestore(&g_uvm_global.gpu_table_lock); } else { - gpu = uvm_gpu_get(global_gpu_id); + gpu = parent_gpu->gpus[0]; UVM_ASSERT(gpu != NULL); } @@ -547,12 +547,12 @@ static void replayable_faults_isr_bottom_half(void *args) uvm_gpu_service_replayable_faults(gpu); - uvm_gpu_replayable_faults_isr_unlock(parent_gpu); + uvm_parent_gpu_replayable_faults_isr_unlock(parent_gpu); put_kref: // It is OK to drop a reference on the parent GPU if a bottom half has - // been retriggered within uvm_gpu_replayable_faults_isr_unlock, because the - // rescheduling added an additional reference. + // been retriggered within uvm_parent_gpu_replayable_faults_isr_unlock, + // because the rescheduling added an additional reference. uvm_parent_gpu_kref_put(parent_gpu); } @@ -573,7 +573,7 @@ static void non_replayable_faults_isr_bottom_half(void *args) UVM_ASSERT(parent_gpu->non_replayable_faults_supported); - uvm_gpu_non_replayable_faults_isr_lock(parent_gpu); + uvm_parent_gpu_non_replayable_faults_isr_lock(parent_gpu); // Multiple bottom halves for non-replayable faults can be running // concurrently, but only one can enter this section for a given GPU @@ -586,7 +586,7 @@ static void non_replayable_faults_isr_bottom_half(void *args) uvm_gpu_service_non_replayable_fault_buffer(gpu); - uvm_gpu_non_replayable_faults_isr_unlock(parent_gpu); + uvm_parent_gpu_non_replayable_faults_isr_unlock(parent_gpu); put_kref: uvm_parent_gpu_kref_put(parent_gpu); @@ -622,7 +622,7 @@ static void access_counters_isr_bottom_half(void *args) uvm_gpu_service_access_counters(gpu); - uvm_gpu_access_counters_isr_unlock(parent_gpu); + uvm_parent_gpu_access_counters_isr_unlock(parent_gpu); put_kref: uvm_parent_gpu_kref_put(parent_gpu); @@ -651,7 +651,7 @@ static void replayable_faults_retrigger_bottom_half(uvm_parent_gpu_t *parent_gpu // // (1) UVM didn't process all the entries up to cached PUT // - // (2) UVM did process all the entries up to cached PUT, but GPS-RM + // (2) UVM did process all the entries up to cached PUT, but GSP-RM // added new entries such that cached PUT is out-of-date // // In both cases, re-enablement of interrupts would have caused the @@ -663,7 +663,7 @@ static void replayable_faults_retrigger_bottom_half(uvm_parent_gpu_t *parent_gpu // While in the typical case the retriggering happens within a replayable // fault bottom half, it can also happen within a non-interrupt path such as // uvm_gpu_fault_buffer_flush. - if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + if (g_uvm_global.conf_computing_enabled) retrigger = true; if (!retrigger) @@ -678,7 +678,7 @@ static void replayable_faults_retrigger_bottom_half(uvm_parent_gpu_t *parent_gpu uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); } -void uvm_gpu_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) { UVM_ASSERT(nv_kref_read(&parent_gpu->gpu_kref) > 0); @@ -687,7 +687,7 @@ void uvm_gpu_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) // Bump the disable ref count. This guarantees that the bottom half or // another thread trying to take the replayable_faults.service_lock won't // inadvertently re-enable interrupts during this locking sequence. - uvm_gpu_replayable_faults_intr_disable(parent_gpu); + uvm_parent_gpu_replayable_faults_intr_disable(parent_gpu); uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); @@ -696,7 +696,7 @@ void uvm_gpu_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) uvm_down(&parent_gpu->isr.replayable_faults.service_lock); } -void uvm_gpu_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu) { UVM_ASSERT(nv_kref_read(&parent_gpu->gpu_kref) > 0); @@ -733,9 +733,10 @@ void uvm_gpu_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu) // Note that if we're in the bottom half and the GPU was removed before // we checked replayable_faults.handling, we won't drop our interrupt // disable ref count from the corresponding top-half call to - // uvm_gpu_replayable_faults_intr_disable. That's ok because remove_gpu - // ignores the refcount after waiting for the bottom half to finish. - uvm_gpu_replayable_faults_intr_enable(parent_gpu); + // uvm_parent_gpu_replayable_faults_intr_disable. That's ok because + // remove_gpu ignores the refcount after waiting for the bottom half to + // finish. + uvm_parent_gpu_replayable_faults_intr_enable(parent_gpu); // Rearm pulse interrupts. This guarantees that the state of the pending // interrupt is current and the top level rearm performed by RM is only @@ -762,42 +763,42 @@ void uvm_gpu_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu) replayable_faults_retrigger_bottom_half(parent_gpu); } -void uvm_gpu_non_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_non_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu) { UVM_ASSERT(nv_kref_read(&parent_gpu->gpu_kref) > 0); uvm_down(&parent_gpu->isr.non_replayable_faults.service_lock); } -void uvm_gpu_non_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_non_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu) { UVM_ASSERT(nv_kref_read(&parent_gpu->gpu_kref) > 0); uvm_up(&parent_gpu->isr.non_replayable_faults.service_lock); } -void uvm_gpu_access_counters_isr_lock(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_access_counters_isr_lock(uvm_parent_gpu_t *parent_gpu) { - // See comments in uvm_gpu_replayable_faults_isr_lock + // See comments in uvm_parent_gpu_replayable_faults_isr_lock uvm_spin_lock_irqsave(&parent_gpu->isr.interrupts_lock); - uvm_gpu_access_counters_intr_disable(parent_gpu); + uvm_parent_gpu_access_counters_intr_disable(parent_gpu); uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); uvm_down(&parent_gpu->isr.access_counters.service_lock); } -void uvm_gpu_access_counters_isr_unlock(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_access_counters_isr_unlock(uvm_parent_gpu_t *parent_gpu) { UVM_ASSERT(nv_kref_read(&parent_gpu->gpu_kref) > 0); - // See comments in uvm_gpu_replayable_faults_isr_unlock + // See comments in uvm_parent_gpu_replayable_faults_isr_unlock uvm_spin_lock_irqsave(&parent_gpu->isr.interrupts_lock); - uvm_gpu_access_counters_intr_enable(parent_gpu); + uvm_parent_gpu_access_counters_intr_enable(parent_gpu); if (parent_gpu->isr.access_counters.handling_ref_count > 0) { parent_gpu->access_counter_buffer_hal->clear_access_counter_notifications(parent_gpu, @@ -811,7 +812,7 @@ void uvm_gpu_access_counters_isr_unlock(uvm_parent_gpu_t *parent_gpu) uvm_spin_unlock_irqrestore(&parent_gpu->isr.interrupts_lock); } -static void uvm_gpu_replayable_faults_intr_disable(uvm_parent_gpu_t *parent_gpu) +static void uvm_parent_gpu_replayable_faults_intr_disable(uvm_parent_gpu_t *parent_gpu) { uvm_assert_spinlock_locked(&parent_gpu->isr.interrupts_lock); @@ -821,7 +822,7 @@ static void uvm_gpu_replayable_faults_intr_disable(uvm_parent_gpu_t *parent_gpu) ++parent_gpu->isr.replayable_faults.disable_intr_ref_count; } -static void uvm_gpu_replayable_faults_intr_enable(uvm_parent_gpu_t *parent_gpu) +static void uvm_parent_gpu_replayable_faults_intr_enable(uvm_parent_gpu_t *parent_gpu) { uvm_assert_spinlock_locked(&parent_gpu->isr.interrupts_lock); UVM_ASSERT(parent_gpu->isr.replayable_faults.disable_intr_ref_count > 0); @@ -831,7 +832,7 @@ static void uvm_gpu_replayable_faults_intr_enable(uvm_parent_gpu_t *parent_gpu) parent_gpu->fault_buffer_hal->enable_replayable_faults(parent_gpu); } -void uvm_gpu_access_counters_intr_disable(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_access_counters_intr_disable(uvm_parent_gpu_t *parent_gpu) { uvm_assert_spinlock_locked(&parent_gpu->isr.interrupts_lock); @@ -848,7 +849,7 @@ void uvm_gpu_access_counters_intr_disable(uvm_parent_gpu_t *parent_gpu) ++parent_gpu->isr.access_counters.disable_intr_ref_count; } -void uvm_gpu_access_counters_intr_enable(uvm_parent_gpu_t *parent_gpu) +void uvm_parent_gpu_access_counters_intr_enable(uvm_parent_gpu_t *parent_gpu) { uvm_assert_spinlock_locked(&parent_gpu->isr.interrupts_lock); UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.access_counters.service_lock)); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_isr.h b/kernel-open/nvidia-uvm/uvm_gpu_isr.h index e11f2bdda0..ad35d657a9 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_isr.h +++ b/kernel-open/nvidia-uvm/uvm_gpu_isr.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2019 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -131,19 +131,19 @@ typedef struct NV_STATUS uvm_isr_top_half_entry(const NvProcessorUuid *gpu_uuid); // Initialize ISR handling state -NV_STATUS uvm_gpu_init_isr(uvm_parent_gpu_t *parent_gpu); +NV_STATUS uvm_parent_gpu_init_isr(uvm_parent_gpu_t *parent_gpu); // Flush any currently scheduled bottom halves. This is called during GPU // removal. -void uvm_gpu_flush_bottom_halves(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_flush_bottom_halves(uvm_parent_gpu_t *parent_gpu); // Prevent new bottom halves from being scheduled. This is called during parent // GPU removal. -void uvm_gpu_disable_isr(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_disable_isr(uvm_parent_gpu_t *parent_gpu); // Destroy ISR handling state and return interrupt ownership to RM. This is // called during parent GPU removal -void uvm_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu); // Take parent_gpu->isr.replayable_faults.service_lock from a non-top/bottom // half thread. This will also disable replayable page fault interrupts (if @@ -151,46 +151,46 @@ void uvm_gpu_deinit_isr(uvm_parent_gpu_t *parent_gpu); // would cause an interrupt storm if we didn't disable them first. // // At least one GPU under the parent must have been previously retained. -void uvm_gpu_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu); // Unlock parent_gpu->isr.replayable_faults.service_lock. This call may // re-enable replayable page fault interrupts. Unlike -// uvm_gpu_replayable_faults_isr_lock(), which should only called from +// uvm_parent_gpu_replayable_faults_isr_lock(), which should only called from // non-top/bottom half threads, this can be called by any thread. -void uvm_gpu_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu); // Lock/unlock routines for non-replayable faults. These do not need to prevent // interrupt storms since the GPU fault buffers for non-replayable faults are -// managed by RM. Unlike uvm_gpu_replayable_faults_isr_lock, no GPUs under -// the parent need to have been previously retained. -void uvm_gpu_non_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu); -void uvm_gpu_non_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu); +// managed by RM. Unlike uvm_parent_gpu_replayable_faults_isr_lock, no GPUs +// under the parent need to have been previously retained. +void uvm_parent_gpu_non_replayable_faults_isr_lock(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_non_replayable_faults_isr_unlock(uvm_parent_gpu_t *parent_gpu); -// See uvm_gpu_replayable_faults_isr_lock/unlock -void uvm_gpu_access_counters_isr_lock(uvm_parent_gpu_t *parent_gpu); -void uvm_gpu_access_counters_isr_unlock(uvm_parent_gpu_t *parent_gpu); +// See uvm_parent_gpu_replayable_faults_isr_lock/unlock +void uvm_parent_gpu_access_counters_isr_lock(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_access_counters_isr_unlock(uvm_parent_gpu_t *parent_gpu); // Increments the reference count tracking whether access counter interrupts // should be disabled. The caller is guaranteed that access counter interrupts // are disabled upon return. Interrupts might already be disabled prior to // making this call. Each call is ref-counted, so this must be paired with a -// call to uvm_gpu_access_counters_intr_enable(). +// call to uvm_parent_gpu_access_counters_intr_enable(). // // parent_gpu->isr.interrupts_lock must be held to call this function. -void uvm_gpu_access_counters_intr_disable(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_access_counters_intr_disable(uvm_parent_gpu_t *parent_gpu); // Decrements the reference count tracking whether access counter interrupts // should be disabled. Only once the count reaches 0 are the HW interrupts // actually enabled, so this call does not guarantee that the interrupts have // been re-enabled upon return. // -// uvm_gpu_access_counters_intr_disable() must have been called prior to calling -// this function. +// uvm_parent_gpu_access_counters_intr_disable() must have been called prior to +// calling this function. // // NOTE: For pulse-based interrupts, the caller is responsible for re-arming // the interrupt. // // parent_gpu->isr.interrupts_lock must be held to call this function. -void uvm_gpu_access_counters_intr_enable(uvm_parent_gpu_t *parent_gpu); +void uvm_parent_gpu_access_counters_intr_enable(uvm_parent_gpu_t *parent_gpu); #endif // __UVM_GPU_ISR_H__ diff --git a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c index 2f3d10f1e9..46551afb6c 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_non_replayable_faults.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2022 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -196,7 +196,7 @@ static NV_STATUS fetch_non_replayable_fault_buffer_entries(uvm_parent_gpu_t *par if (status != NV_OK) { UVM_ERR_PRINT("nvUvmInterfaceGetNonReplayableFaults() failed: %s, GPU %s\n", nvstatusToString(status), - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); uvm_global_set_fatal_error(status); return status; @@ -235,17 +235,27 @@ static NV_STATUS fetch_non_replayable_fault_buffer_entries(uvm_parent_gpu_t *par return NV_OK; } -// In SRIOV, the UVM (guest) driver does not have access to the privileged -// registers used to clear the faulted bit. Instead, UVM requests host RM to do -// the clearing on its behalf, using a SW method. static bool use_clear_faulted_channel_sw_method(uvm_gpu_t *gpu) { - if (uvm_gpu_is_virt_mode_sriov(gpu)) { + // If true, UVM uses a SW method to request RM to do the clearing on its + // behalf. + bool use_sw_method = false; + + // In SRIOV, the UVM (guest) driver does not have access to the privileged + // registers used to clear the faulted bit. + if (uvm_parent_gpu_is_virt_mode_sriov(gpu->parent)) + use_sw_method = true; + + // In Confidential Computing access to the privileged registers is blocked, + // in order to prevent interference between guests, or between the + // (untrusted) host and the guests. + if (g_uvm_global.conf_computing_enabled) + use_sw_method = true; + + if (use_sw_method) UVM_ASSERT(gpu->parent->has_clear_faulted_channel_sw_method); - return true; - } - return false; + return use_sw_method; } static NV_STATUS clear_faulted_method_on_gpu(uvm_gpu_t *gpu, @@ -334,7 +344,8 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_fault_buffer_entry_t *fault_entry, - uvm_service_block_context_t *service_context) + uvm_service_block_context_t *service_context, + const bool hmm_migratable) { NV_STATUS status = NV_OK; uvm_page_index_t page_index; @@ -400,6 +411,7 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, policy, &thrashing_hint, UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS, + hmm_migratable, &read_duplicate); // Initialize the minimum necessary state in the fault service context @@ -431,7 +443,8 @@ static NV_STATUS service_managed_fault_in_block_locked(uvm_gpu_t *gpu, static NV_STATUS service_managed_fault_in_block(uvm_gpu_t *gpu, uvm_va_block_t *va_block, - uvm_fault_buffer_entry_t *fault_entry) + uvm_fault_buffer_entry_t *fault_entry, + const bool hmm_migratable) { NV_STATUS status, tracker_status; uvm_va_block_retry_t va_block_retry; @@ -440,10 +453,8 @@ static NV_STATUS service_managed_fault_in_block(uvm_gpu_t *gpu, service_context->operation = UVM_SERVICE_OPERATION_NON_REPLAYABLE_FAULTS; service_context->num_retries = 0; - if (uvm_va_block_is_hmm(va_block)) { - uvm_hmm_service_context_init(service_context); + if (uvm_va_block_is_hmm(va_block)) uvm_hmm_migrate_begin_wait(va_block); - } uvm_mutex_lock(&va_block->lock); @@ -452,7 +463,8 @@ static NV_STATUS service_managed_fault_in_block(uvm_gpu_t *gpu, va_block, &va_block_retry, fault_entry, - service_context)); + service_context, + hmm_migratable)); tracker_status = uvm_tracker_add_tracker_safe(&gpu->parent->fault_buffer_info.non_replayable.fault_service_tracker, &va_block->tracker); @@ -570,7 +582,7 @@ static NV_STATUS service_non_managed_fault(uvm_gpu_va_space_t *gpu_va_space, ats_context->client_type = UVM_FAULT_CLIENT_TYPE_HUB; - ats_invalidate->write_faults_in_batch = false; + ats_invalidate->tlb_batch_pending = false; va_range_next = uvm_va_space_iter_first(gpu_va_space->va_space, fault_entry->fault_address, ~0ULL); @@ -619,7 +631,7 @@ static NV_STATUS service_non_managed_fault(uvm_gpu_va_space_t *gpu_va_space, return status; } -static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_entry) +static NV_STATUS service_fault_once(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_entry, const bool hmm_migratable) { NV_STATUS status; uvm_user_channel_t *user_channel; @@ -631,7 +643,7 @@ static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_e uvm_va_block_context_t *va_block_context = gpu->parent->fault_buffer_info.non_replayable.block_service_context.block_context; - status = uvm_gpu_fault_entry_to_va_space(gpu, fault_entry, &va_space); + status = uvm_parent_gpu_fault_entry_to_va_space(gpu->parent, fault_entry, &va_space); if (status != NV_OK) { // The VA space lookup will fail if we're running concurrently with // removal of the channel from the VA space (channel unregister, GPU VA @@ -691,7 +703,7 @@ static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_e &va_block); } if (status == NV_OK) - status = service_managed_fault_in_block(gpu_va_space->gpu, va_block, fault_entry); + status = service_managed_fault_in_block(gpu_va_space->gpu, va_block, fault_entry, hmm_migratable); else status = service_non_managed_fault(gpu_va_space, mm, fault_entry, status); @@ -708,21 +720,46 @@ static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_e } if (fault_entry->is_fatal) - uvm_tools_record_gpu_fatal_fault(gpu->parent->id, fault_entry->va_space, fault_entry, fault_entry->fatal_reason); + uvm_tools_record_gpu_fatal_fault(gpu->id, fault_entry->va_space, fault_entry, fault_entry->fatal_reason); - if (status != NV_OK || fault_entry->is_fatal) + if (fault_entry->is_fatal || + (status != NV_OK && + status != NV_WARN_MORE_PROCESSING_REQUIRED && + status != NV_WARN_MISMATCHED_TARGET)) schedule_kill_channel(gpu, fault_entry, user_channel); exit_no_channel: uvm_va_space_up_read(va_space); uvm_va_space_mm_release_unlock(va_space, mm); - if (status != NV_OK) + if (status != NV_OK && + status != NV_WARN_MORE_PROCESSING_REQUIRED && + status != NV_WARN_MISMATCHED_TARGET) UVM_DBG_PRINT("Error servicing non-replayable faults on GPU: %s\n", uvm_gpu_name(gpu)); return status; } +static NV_STATUS service_fault(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t *fault_entry) +{ + uvm_service_block_context_t *service_context = + &gpu->parent->fault_buffer_info.non_replayable.block_service_context; + NV_STATUS status; + bool hmm_migratable = true; + + service_context->num_retries = 0; + + do { + status = service_fault_once(gpu, fault_entry, hmm_migratable); + if (status == NV_WARN_MISMATCHED_TARGET) { + hmm_migratable = false; + status = NV_WARN_MORE_PROCESSING_REQUIRED; + } + } while (status == NV_WARN_MORE_PROCESSING_REQUIRED); + + return status; +} + void uvm_gpu_service_non_replayable_fault_buffer(uvm_gpu_t *gpu) { NvU32 cached_faults; diff --git a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c index 5b8a6d57f3..19851ee6e6 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c @@ -139,7 +139,7 @@ static NV_STATUS fault_buffer_init_replayable_faults(uvm_parent_gpu_t *parent_gp if (parent_gpu->fault_buffer_info.max_batch_size != uvm_perf_fault_batch_count) { pr_info("Invalid uvm_perf_fault_batch_count value on GPU %s: %u. Valid range [%u:%u] Using %u instead\n", - parent_gpu->name, + uvm_parent_gpu_name(parent_gpu), uvm_perf_fault_batch_count, UVM_PERF_FAULT_BATCH_COUNT_MIN, replayable_faults->max_faults, @@ -171,7 +171,7 @@ static NV_STATUS fault_buffer_init_replayable_faults(uvm_parent_gpu_t *parent_gp if (status != NV_OK) { UVM_ERR_PRINT("Failed to take page fault ownership from RM: %s, GPU %s\n", nvstatusToString(status), - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); return status; } @@ -181,7 +181,7 @@ static NV_STATUS fault_buffer_init_replayable_faults(uvm_parent_gpu_t *parent_gp if (replayable_faults->replay_policy != uvm_perf_fault_replay_policy) { pr_info("Invalid uvm_perf_fault_replay_policy value on GPU %s: %d. Using %d instead\n", - parent_gpu->name, + uvm_parent_gpu_name(parent_gpu), uvm_perf_fault_replay_policy, replayable_faults->replay_policy); } @@ -189,7 +189,7 @@ static NV_STATUS fault_buffer_init_replayable_faults(uvm_parent_gpu_t *parent_gp replayable_faults->replay_update_put_ratio = min(uvm_perf_fault_replay_update_put_ratio, 100u); if (replayable_faults->replay_update_put_ratio != uvm_perf_fault_replay_update_put_ratio) { pr_info("Invalid uvm_perf_fault_replay_update_put_ratio value on GPU %s: %u. Using %u instead\n", - parent_gpu->name, + uvm_parent_gpu_name(parent_gpu), uvm_perf_fault_replay_update_put_ratio, replayable_faults->replay_update_put_ratio); } @@ -238,7 +238,7 @@ NV_STATUS uvm_gpu_fault_buffer_init(uvm_parent_gpu_t *parent_gpu) if (status != NV_OK) { UVM_ERR_PRINT("Failed to init fault buffer info from RM: %s, GPU %s\n", nvstatusToString(status), - parent_gpu->name); + uvm_parent_gpu_name(parent_gpu)); // nvUvmInterfaceInitFaultInfo may leave fields in rm_info populated // when it returns an error. Set the buffer handle to zero as it is @@ -297,19 +297,6 @@ void uvm_gpu_fault_buffer_deinit(uvm_parent_gpu_t *parent_gpu) } } -// TODO: Bug 4098289: this function can be removed, and the calls to it replaced -// with calls to uvm_conf_computing_mode_enabled_parent, once UVM ownership is -// dictated by Confidential Computing enablement. Currently we support a -// non-production scenario in which Confidential Computing is enabled, but -// UVM still owns the replayable fault buffer. -bool uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(uvm_parent_gpu_t *parent_gpu) -{ - if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) - return parent_gpu->fault_buffer_info.rm_info.replayable.bUvmOwnsHwFaultBuffer; - - return true; -} - bool uvm_gpu_replayable_faults_pending(uvm_parent_gpu_t *parent_gpu) { uvm_replayable_fault_buffer_info_t *replayable_faults = &parent_gpu->fault_buffer_info.replayable; @@ -362,7 +349,8 @@ static NV_STATUS push_cancel_on_gpu(uvm_gpu_t *gpu, "Cancel targeting instance_ptr {0x%llx:%s}\n", instance_ptr.address, uvm_aperture_string(instance_ptr.aperture)); - } else { + } + else { status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_MEMOPS, &replayable_faults->replay_tracker, @@ -559,13 +547,9 @@ static NV_STATUS hw_fault_buffer_flush_locked(uvm_parent_gpu_t *parent_gpu) // fault_buffer_flush_locked is called, are now either flushed from the HW // buffer, or are present in the shadow buffer and are about to be discarded // too. - if (!uvm_conf_computing_mode_enabled_parent(parent_gpu)) + if (!g_uvm_global.conf_computing_enabled) return NV_OK; - // nvUvmInterfaceFlushReplayableFaultBuffer relies on the caller to ensure - // serialization for a given GPU. - UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock)); - // Flush the HW replayable buffer owned by GSP-RM. status = nvUvmInterfaceFlushReplayableFaultBuffer(parent_gpu->rm_device); @@ -581,7 +565,7 @@ static void fault_buffer_skip_replayable_entry(uvm_parent_gpu_t *parent_gpu, NvU // Flushed faults are never decrypted, but the decryption IV associated with // replayable faults still requires manual adjustment so it is kept in sync // with the encryption IV on the GSP-RM's side. - if (!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) + if (g_uvm_global.conf_computing_enabled) uvm_conf_computing_fault_increment_decrypt_iv(parent_gpu, 1); parent_gpu->fault_buffer_hal->entry_clear_valid(parent_gpu, index); @@ -644,7 +628,7 @@ NV_STATUS uvm_gpu_fault_buffer_flush(uvm_gpu_t *gpu) UVM_ASSERT(gpu->parent->replayable_faults_supported); // Disables replayable fault interrupts and fault servicing - uvm_gpu_replayable_faults_isr_lock(gpu->parent); + uvm_parent_gpu_replayable_faults_isr_lock(gpu->parent); status = fault_buffer_flush_locked(gpu, UVM_GPU_BUFFER_FLUSH_MODE_WAIT_UPDATE_PUT, @@ -653,7 +637,7 @@ NV_STATUS uvm_gpu_fault_buffer_flush(uvm_gpu_t *gpu) // This will trigger the top half to start servicing faults again, if the // replay brought any back in - uvm_gpu_replayable_faults_isr_unlock(gpu->parent); + uvm_parent_gpu_replayable_faults_isr_unlock(gpu->parent); return status; } @@ -990,7 +974,7 @@ static NV_STATUS translate_instance_ptrs(uvm_gpu_t *gpu, continue; } - status = uvm_gpu_fault_entry_to_va_space(gpu, current_entry, ¤t_entry->va_space); + status = uvm_parent_gpu_fault_entry_to_va_space(gpu->parent, current_entry, ¤t_entry->va_space); if (status != NV_OK) { if (status == NV_ERR_PAGE_TABLE_NOT_AVAIL) { // The channel is valid but the subcontext is not. This can only @@ -1310,6 +1294,7 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, uvm_va_block_retry_t *va_block_retry, uvm_fault_service_batch_context_t *batch_context, NvU32 first_fault_index, + const bool hmm_migratable, NvU32 *block_faults) { NV_STATUS status = NV_OK; @@ -1480,6 +1465,7 @@ static NV_STATUS service_fault_batch_block_locked(uvm_gpu_t *gpu, policy, &thrashing_hint, UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS, + hmm_migratable, &read_duplicate); if (!uvm_processor_mask_test_and_set(&block_context->resident_processors, new_residency)) @@ -1532,6 +1518,7 @@ static NV_STATUS service_fault_batch_block(uvm_gpu_t *gpu, uvm_va_block_t *va_block, uvm_fault_service_batch_context_t *batch_context, NvU32 first_fault_index, + const bool hmm_migratable, NvU32 *block_faults) { NV_STATUS status; @@ -1553,6 +1540,7 @@ static NV_STATUS service_fault_batch_block(uvm_gpu_t *gpu, &va_block_retry, batch_context, first_fault_index, + hmm_migratable, block_faults)); tracker_status = uvm_tracker_add_tracker_safe(&batch_context->tracker, &va_block->tracker); @@ -1631,23 +1619,23 @@ static NV_STATUS service_fault_batch_ats_sub_vma(uvm_gpu_va_space_t *gpu_va_spac const uvm_page_mask_t *write_fault_mask = &ats_context->write_fault_mask; const uvm_page_mask_t *reads_serviced_mask = &ats_context->reads_serviced_mask; uvm_page_mask_t *faults_serviced_mask = &ats_context->faults_serviced_mask; - uvm_page_mask_t *faulted_mask = &ats_context->faulted_mask; + uvm_page_mask_t *accessed_mask = &ats_context->accessed_mask; UVM_ASSERT(vma); ats_context->client_type = UVM_FAULT_CLIENT_TYPE_GPC; - uvm_page_mask_or(faulted_mask, write_fault_mask, read_fault_mask); + uvm_page_mask_or(accessed_mask, write_fault_mask, read_fault_mask); status = uvm_ats_service_faults(gpu_va_space, vma, base, &batch_context->ats_context); // Remove prefetched pages from the serviced mask since fault servicing // failures belonging to prefetch pages need to be ignored. - uvm_page_mask_and(faults_serviced_mask, faults_serviced_mask, faulted_mask); + uvm_page_mask_and(faults_serviced_mask, faults_serviced_mask, accessed_mask); - UVM_ASSERT(uvm_page_mask_subset(faults_serviced_mask, faulted_mask)); + UVM_ASSERT(uvm_page_mask_subset(faults_serviced_mask, accessed_mask)); - if ((status != NV_OK) || uvm_page_mask_equal(faults_serviced_mask, faulted_mask)) { + if ((status != NV_OK) || uvm_page_mask_equal(faults_serviced_mask, accessed_mask)) { (*block_faults) += (fault_index_end - fault_index_start); return status; } @@ -1679,7 +1667,8 @@ static NV_STATUS service_fault_batch_ats_sub_vma(uvm_gpu_va_space_t *gpu_va_spac if (access_type <= UVM_FAULT_ACCESS_TYPE_READ) { cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; } - else if (access_type >= UVM_FAULT_ACCESS_TYPE_WRITE) { + else { + UVM_ASSERT(access_type >= UVM_FAULT_ACCESS_TYPE_WRITE); if (uvm_fault_access_type_mask_test(current_entry->access_type_mask, UVM_FAULT_ACCESS_TYPE_READ) && !uvm_page_mask_test(reads_serviced_mask, page_index)) cancel_va_mode = UVM_FAULT_CANCEL_VA_MODE_ALL; @@ -1856,7 +1845,8 @@ static NV_STATUS service_fault_batch_dispatch(uvm_va_space_t *va_space, uvm_fault_service_batch_context_t *batch_context, NvU32 fault_index, NvU32 *block_faults, - bool replay_per_va_block) + bool replay_per_va_block, + const bool hmm_migratable) { NV_STATUS status; uvm_va_range_t *va_range = NULL; @@ -1887,7 +1877,7 @@ static NV_STATUS service_fault_batch_dispatch(uvm_va_space_t *va_space, status = NV_ERR_INVALID_ADDRESS; if (status == NV_OK) { - status = service_fault_batch_block(gpu, va_block, batch_context, fault_index, block_faults); + status = service_fault_batch_block(gpu, va_block, batch_context, fault_index, hmm_migratable, block_faults); } else if ((status == NV_ERR_INVALID_ADDRESS) && uvm_ats_can_service_faults(gpu_va_space, mm)) { NvU64 outer = ~0ULL; @@ -1991,9 +1981,6 @@ static NV_STATUS service_fault_batch_for_cancel(uvm_gpu_t *gpu, uvm_fault_servic // in the HW buffer. When GSP owns the HW buffer, we also have to wait for // GSP to copy all available faults from the HW buffer into the shadow // buffer. - // - // TODO: Bug 2533557: This flush does not actually guarantee that GSP will - // copy over all faults. status = hw_fault_buffer_flush_locked(gpu->parent); if (status != NV_OK) goto done; @@ -2064,19 +2051,19 @@ static NV_STATUS service_fault_batch_for_cancel(uvm_gpu_t *gpu, uvm_fault_servic else { uvm_ats_fault_invalidate_t *ats_invalidate = &gpu->parent->fault_buffer_info.replayable.ats_invalidate; NvU32 block_faults; + const bool hmm_migratable = true; - ats_invalidate->write_faults_in_batch = false; - uvm_hmm_service_context_init(service_context); + ats_invalidate->tlb_batch_pending = false; // Service all the faults that we can. We only really need to search // for fatal faults, but attempting to service all is the easiest // way to do that. - status = service_fault_batch_dispatch(va_space, gpu_va_space, batch_context, i, &block_faults, false); + status = service_fault_batch_dispatch(va_space, gpu_va_space, batch_context, i, &block_faults, false, hmm_migratable); if (status != NV_OK) { // TODO: Bug 3900733: clean up locking in service_fault_batch(). // We need to drop lock and retry. That means flushing and // starting over. - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) + if (status == NV_WARN_MORE_PROCESSING_REQUIRED || status == NV_WARN_MISMATCHED_TARGET) status = NV_OK; break; @@ -2148,11 +2135,11 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, uvm_service_block_context_t *service_context = &gpu->parent->fault_buffer_info.replayable.block_service_context; uvm_va_block_context_t *va_block_context = service_context->block_context; + bool hmm_migratable = true; UVM_ASSERT(gpu->parent->replayable_faults_supported); - ats_invalidate->write_faults_in_batch = false; - uvm_hmm_service_context_init(service_context); + ats_invalidate->tlb_batch_pending = false; for (i = 0; i < batch_context->num_coalesced_faults;) { NvU32 block_faults; @@ -2215,9 +2202,12 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, batch_context, i, &block_faults, - replay_per_va_block); + replay_per_va_block, + hmm_migratable); // TODO: Bug 3900733: clean up locking in service_fault_batch(). - if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + if (status == NV_WARN_MORE_PROCESSING_REQUIRED || status == NV_WARN_MISMATCHED_TARGET) { + if (status == NV_WARN_MISMATCHED_TARGET) + hmm_migratable = false; uvm_va_space_up_read(va_space); uvm_va_space_mm_release_unlock(va_space, mm); mm = NULL; @@ -2229,6 +2219,7 @@ static NV_STATUS service_fault_batch(uvm_gpu_t *gpu, if (status != NV_OK) goto fail; + hmm_migratable = true; i += block_faults; // Don't issue replays in cancel mode @@ -2348,7 +2339,7 @@ static void record_fatal_fault_helper(uvm_gpu_t *gpu, uvm_fault_buffer_entry_t * UVM_ASSERT(va_space); uvm_va_space_down_read(va_space); // Record fatal fault event - uvm_tools_record_gpu_fatal_fault(gpu->parent->id, va_space, entry, reason); + uvm_tools_record_gpu_fatal_fault(gpu->id, va_space, entry, reason); uvm_va_space_up_read(va_space); } @@ -2538,10 +2529,10 @@ static void cancel_fault_batch_tlb(uvm_gpu_t *gpu, // The list iteration below skips the entry used as 'head'. // Report the 'head' entry explicitly. uvm_va_space_down_read(current_entry->va_space); - uvm_tools_record_gpu_fatal_fault(gpu->parent->id, current_entry->va_space, current_entry, reason); + uvm_tools_record_gpu_fatal_fault(gpu->id, current_entry->va_space, current_entry, reason); list_for_each_entry(coalesced_entry, ¤t_entry->merged_instances_list, merged_instances_list) - uvm_tools_record_gpu_fatal_fault(gpu->parent->id, current_entry->va_space, coalesced_entry, reason); + uvm_tools_record_gpu_fatal_fault(gpu->id, current_entry->va_space, coalesced_entry, reason); uvm_va_space_up_read(current_entry->va_space); // We need to cancel each instance pointer to correctly handle faults from multiple contexts. @@ -2948,9 +2939,9 @@ NV_STATUS uvm_test_drain_replayable_faults(UVM_TEST_DRAIN_REPLAYABLE_FAULTS_PARA uvm_spin_loop_init(&spin); do { - uvm_gpu_replayable_faults_isr_lock(gpu->parent); + uvm_parent_gpu_replayable_faults_isr_lock(gpu->parent); pending = uvm_gpu_replayable_faults_pending(gpu->parent); - uvm_gpu_replayable_faults_isr_unlock(gpu->parent); + uvm_parent_gpu_replayable_faults_isr_unlock(gpu->parent); if (!pending) break; diff --git a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h index a052e1195c..3fb27c30ef 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h +++ b/kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.h @@ -74,8 +74,4 @@ void uvm_gpu_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu); // Service pending replayable faults on the given GPU. This function must be // only called from the ISR bottom half void uvm_gpu_service_replayable_faults(uvm_gpu_t *gpu); - -// Returns true if UVM owns the hardware replayable fault buffer -bool uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(uvm_parent_gpu_t *parent_gpu); - #endif // __UVM_GPU_PAGE_FAULT_H__ diff --git a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c index f014dfada7..ef7e78fbfd 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_semaphore.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -72,7 +72,7 @@ struct uvm_gpu_semaphore_pool_page_struct static bool gpu_semaphore_pool_is_secure(uvm_gpu_semaphore_pool_t *pool) { - return uvm_conf_computing_mode_enabled(pool->gpu) && (pool->aperture == UVM_APERTURE_VID); + return g_uvm_global.conf_computing_enabled && (pool->aperture == UVM_APERTURE_VID); } static bool gpu_semaphore_is_secure(uvm_gpu_semaphore_t *semaphore) @@ -366,7 +366,7 @@ NV_STATUS uvm_gpu_semaphore_secure_pool_create(uvm_gpu_t *gpu, uvm_gpu_semaphore { NV_STATUS status; - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); status = uvm_gpu_semaphore_pool_create(gpu, pool_out); if (status == NV_OK) @@ -498,7 +498,7 @@ static bool tracking_semaphore_check_gpu(uvm_gpu_tracking_semaphore_t *tracking_ // those cases. // // But if a pointer is in the table it must match. - table_gpu = uvm_gpu_get(gpu->global_id); + table_gpu = uvm_gpu_get(gpu->id); if (table_gpu) UVM_ASSERT(table_gpu == gpu); @@ -509,16 +509,11 @@ static bool tracking_semaphore_check_gpu(uvm_gpu_tracking_semaphore_t *tracking_ bool tracking_semaphore_uses_mutex(uvm_gpu_tracking_semaphore_t *tracking_semaphore) { - uvm_gpu_t *gpu = tracking_semaphore->semaphore.page->pool->gpu; - UVM_ASSERT(tracking_semaphore_check_gpu(tracking_semaphore)); - if (uvm_conf_computing_mode_enabled(gpu)) - return true; - return false; + return g_uvm_global.conf_computing_enabled; } - NV_STATUS uvm_gpu_tracking_semaphore_alloc(uvm_gpu_semaphore_pool_t *pool, uvm_gpu_tracking_semaphore_t *tracking_sem) { NV_STATUS status; @@ -532,7 +527,7 @@ NV_STATUS uvm_gpu_tracking_semaphore_alloc(uvm_gpu_semaphore_pool_t *pool, uvm_g UVM_ASSERT(uvm_gpu_semaphore_get_payload(&tracking_sem->semaphore) == 0); - if (uvm_conf_computing_mode_enabled(pool->gpu)) + if (g_uvm_global.conf_computing_enabled) order = UVM_LOCK_ORDER_SECURE_SEMAPHORE; if (tracking_semaphore_uses_mutex(tracking_sem)) @@ -579,9 +574,8 @@ static void uvm_gpu_semaphore_encrypted_payload_update(uvm_channel_t *channel, u void *auth_tag_cpu_addr = uvm_rm_mem_get_cpu_va(semaphore->conf_computing.auth_tag); NvU32 *gpu_notifier_cpu_addr = (NvU32 *)uvm_rm_mem_get_cpu_va(semaphore->conf_computing.notifier); NvU32 *payload_cpu_addr = (NvU32 *)uvm_rm_mem_get_cpu_va(semaphore->conf_computing.encrypted_payload); - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); UVM_ASSERT(uvm_channel_is_ce(channel)); last_observed_notifier = semaphore->conf_computing.last_observed_notifier; @@ -695,7 +689,7 @@ static NvU64 update_completed_value_locked(uvm_gpu_tracking_semaphore_t *trackin // Check for unexpected large jumps of the semaphore value UVM_ASSERT_MSG_RELEASE(new_value - old_value <= UVM_GPU_SEMAPHORE_MAX_JUMP, "GPU %s unexpected semaphore (CPU VA 0x%llx) jump from 0x%llx to 0x%llx\n", - tracking_semaphore->semaphore.page->pool->gpu->parent->name, + uvm_gpu_name(tracking_semaphore->semaphore.page->pool->gpu), (NvU64)(uintptr_t)tracking_semaphore->semaphore.payload, old_value, new_value); diff --git a/kernel-open/nvidia-uvm/uvm_gpu_semaphore_test.c b/kernel-open/nvidia-uvm/uvm_gpu_semaphore_test.c index b8a8d28741..a7b68a12ae 100644 --- a/kernel-open/nvidia-uvm/uvm_gpu_semaphore_test.c +++ b/kernel-open/nvidia-uvm/uvm_gpu_semaphore_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2019 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -185,7 +185,7 @@ static NV_STATUS test_alloc(uvm_va_space_t *va_space) // In SR-IOV heavy, there should be a mapping in the proxy VA space // too. - if (uvm_gpu_uses_proxy_channel_pool(gpu)) { + if (uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)) { gpu_va = uvm_gpu_semaphore_get_gpu_proxy_va(&semaphores[i], gpu); TEST_CHECK_GOTO(gpu_va != 0, done); } diff --git a/kernel-open/nvidia-uvm/uvm_hal.c b/kernel-open/nvidia-uvm/uvm_hal.c index eb59fb7e3d..84b8d09933 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.c +++ b/kernel-open/nvidia-uvm/uvm_hal.c @@ -22,6 +22,7 @@ *******************************************************************************/ #include "uvm_hal.h" +#include "uvm_global.h" #include "uvm_kvmalloc.h" #include "cla16f.h" @@ -680,7 +681,9 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) class_ops = ops_find_by_id(ce_table, ARRAY_SIZE(ce_table), gpu_info->ceClass); if (class_ops == NULL) { - UVM_ERR_PRINT("Unsupported ce class: 0x%X, GPU %s\n", gpu_info->ceClass, parent_gpu->name); + UVM_ERR_PRINT("Unsupported ce class: 0x%X, GPU %s\n", + gpu_info->ceClass, + uvm_parent_gpu_name(parent_gpu)); return NV_ERR_INVALID_CLASS; } @@ -688,7 +691,9 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) class_ops = ops_find_by_id(host_table, ARRAY_SIZE(host_table), gpu_info->hostClass); if (class_ops == NULL) { - UVM_ERR_PRINT("Unsupported host class: 0x%X, GPU %s\n", gpu_info->hostClass, parent_gpu->name); + UVM_ERR_PRINT("Unsupported host class: 0x%X, GPU %s\n", + gpu_info->hostClass, + uvm_parent_gpu_name(parent_gpu)); return NV_ERR_INVALID_CLASS; } @@ -696,7 +701,9 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) class_ops = ops_find_by_id(arch_table, ARRAY_SIZE(arch_table), gpu_info->gpuArch); if (class_ops == NULL) { - UVM_ERR_PRINT("Unsupported GPU architecture: 0x%X, GPU %s\n", gpu_info->gpuArch, parent_gpu->name); + UVM_ERR_PRINT("Unsupported GPU architecture: 0x%X, GPU %s\n", + gpu_info->gpuArch, + uvm_parent_gpu_name(parent_gpu)); return NV_ERR_INVALID_CLASS; } @@ -704,7 +711,9 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) class_ops = ops_find_by_id(fault_buffer_table, ARRAY_SIZE(fault_buffer_table), gpu_info->gpuArch); if (class_ops == NULL) { - UVM_ERR_PRINT("Fault buffer HAL not found, GPU %s, arch: 0x%X\n", parent_gpu->name, gpu_info->gpuArch); + UVM_ERR_PRINT("Fault buffer HAL not found, GPU %s, arch: 0x%X\n", + uvm_parent_gpu_name(parent_gpu), + gpu_info->gpuArch); return NV_ERR_INVALID_CLASS; } @@ -714,7 +723,9 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) ARRAY_SIZE(access_counter_buffer_table), gpu_info->gpuArch); if (class_ops == NULL) { - UVM_ERR_PRINT("Access counter HAL not found, GPU %s, arch: 0x%X\n", parent_gpu->name, gpu_info->gpuArch); + UVM_ERR_PRINT("Access counter HAL not found, GPU %s, arch: 0x%X\n", + uvm_parent_gpu_name(parent_gpu), + gpu_info->gpuArch); return NV_ERR_INVALID_CLASS; } @@ -722,7 +733,9 @@ NV_STATUS uvm_hal_init_gpu(uvm_parent_gpu_t *parent_gpu) class_ops = ops_find_by_id(sec2_table, ARRAY_SIZE(sec2_table), gpu_info->gpuArch); if (class_ops == NULL) { - UVM_ERR_PRINT("SEC2 HAL not found, GPU %s, arch: 0x%X\n", parent_gpu->name, gpu_info->gpuArch); + UVM_ERR_PRINT("SEC2 HAL not found, GPU %s, arch: 0x%X\n", + uvm_parent_gpu_name(parent_gpu), + gpu_info->gpuArch); return NV_ERR_INVALID_CLASS; } @@ -736,11 +749,16 @@ static void hal_override_properties(uvm_parent_gpu_t *parent_gpu) // Access counters are currently not supported in vGPU. // // TODO: Bug 200692962: Add support for access counters in vGPU - if (parent_gpu->virt_mode != UVM_VIRT_MODE_NONE) + if (parent_gpu->virt_mode != UVM_VIRT_MODE_NONE) { parent_gpu->access_counters_supported = false; - // Access counters are not supported in CC. - else if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + parent_gpu->access_counters_can_use_physical_addresses = false; + } + + // Access counters are not supported in Confidential Computing. + else if (g_uvm_global.conf_computing_enabled) { parent_gpu->access_counters_supported = false; + parent_gpu->access_counters_can_use_physical_addresses = false; + } } void uvm_hal_init_properties(uvm_parent_gpu_t *parent_gpu) diff --git a/kernel-open/nvidia-uvm/uvm_hal.h b/kernel-open/nvidia-uvm/uvm_hal.h index 69b0953359..0b46caa35a 100644 --- a/kernel-open/nvidia-uvm/uvm_hal.h +++ b/kernel-open/nvidia-uvm/uvm_hal.h @@ -292,9 +292,9 @@ typedef NvU32 (*uvm_hal_ce_plc_mode_t)(void); NvU32 uvm_hal_maxwell_ce_plc_mode(void); NvU32 uvm_hal_ampere_ce_plc_mode_c7b5(void); -typedef NvU32 (*uvm_hal_ce_memcopy_type_t)(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); -NvU32 uvm_hal_maxwell_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); -NvU32 uvm_hal_hopper_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src); +typedef NvU32 (*uvm_hal_ce_memcopy_type_t)(uvm_gpu_address_t dst, uvm_gpu_address_t src); +NvU32 uvm_hal_maxwell_ce_memcopy_copy_type(uvm_gpu_address_t dst, uvm_gpu_address_t src); +NvU32 uvm_hal_hopper_ce_memcopy_copy_type(uvm_gpu_address_t dst, uvm_gpu_address_t src); // CE method validation typedef bool (*uvm_hal_ce_method_is_valid)(uvm_push_t *push, NvU32 method_address, NvU32 method_data); diff --git a/kernel-open/nvidia-uvm/uvm_hmm.c b/kernel-open/nvidia-uvm/uvm_hmm.c index 5a3acf5409..7a0fb86903 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.c +++ b/kernel-open/nvidia-uvm/uvm_hmm.c @@ -112,7 +112,20 @@ typedef struct bool uvm_hmm_is_enabled_system_wide(void) { - return !uvm_disable_hmm && !g_uvm_global.ats.enabled && uvm_va_space_mm_enabled_system(); + if (uvm_disable_hmm) + return false; + + if (g_uvm_global.ats.enabled) + return false; + + // Confidential Computing and HMM impose mutually exclusive constraints. In + // Confidential Computing the GPU can only access pages resident in vidmem, + // but in HMM pages may be required to be resident in sysmem: file backed + // VMAs, huge pages, etc. + if (g_uvm_global.conf_computing_enabled) + return false; + + return uvm_va_space_mm_enabled_system(); } bool uvm_hmm_is_enabled(uvm_va_space_t *va_space) @@ -132,8 +145,9 @@ static uvm_va_block_t *hmm_va_block_from_node(uvm_range_tree_node_t *node) // Copies the contents of the source device-private page to the // destination CPU page. This will invalidate mappings, so cannot be // called while holding any va_block locks. -static NV_STATUS uvm_hmm_copy_devmem_page(struct page *dst_page, struct page *src_page, uvm_tracker_t *tracker) +static void hmm_copy_devmem_page(struct page *dst_page, struct page *src_page) { + uvm_tracker_t tracker = UVM_TRACKER_INIT(); uvm_gpu_phys_address_t src_addr; uvm_gpu_phys_address_t dst_addr; uvm_gpu_chunk_t *gpu_chunk; @@ -152,9 +166,9 @@ static NV_STATUS uvm_hmm_copy_devmem_page(struct page *dst_page, struct page *sr gpu = uvm_gpu_chunk_get_gpu(gpu_chunk); status = uvm_mmu_chunk_map(gpu_chunk); if (status != NV_OK) - return status; + goto out_zero; - status = uvm_gpu_map_cpu_pages(gpu->parent, dst_page, PAGE_SIZE, &dma_addr); + status = uvm_parent_gpu_map_cpu_pages(gpu->parent, dst_page, PAGE_SIZE, &dma_addr); if (status != NV_OK) goto out_unmap_gpu; @@ -162,7 +176,7 @@ static NV_STATUS uvm_hmm_copy_devmem_page(struct page *dst_page, struct page *sr src_addr = uvm_gpu_phys_address(UVM_APERTURE_VID, gpu_chunk->address); status = uvm_push_begin_acquire(gpu->channel_manager, UVM_CHANNEL_TYPE_GPU_TO_CPU, - tracker, + &tracker, &push, "Copy for remote process fault"); if (status != NV_OK) @@ -173,15 +187,23 @@ static NV_STATUS uvm_hmm_copy_devmem_page(struct page *dst_page, struct page *sr uvm_gpu_address_copy(gpu, src_addr), PAGE_SIZE); uvm_push_end(&push); - status = uvm_tracker_add_push_safe(tracker, &push); + status = uvm_tracker_add_push_safe(&tracker, &push); + if (status == NV_OK) + uvm_tracker_wait_deinit(&tracker); out_unmap_cpu: - uvm_gpu_unmap_cpu_pages(gpu->parent, dma_addr, PAGE_SIZE); + uvm_parent_gpu_unmap_cpu_pages(gpu->parent, dma_addr, PAGE_SIZE); out_unmap_gpu: uvm_mmu_chunk_unmap(gpu_chunk, NULL); - return status; +out_zero: + // We can't fail eviction because we need to free the device-private pages + // so the GPU can be unregistered. So the best we can do is warn on any + // failures and zero the uninitialised page. This could result in data loss + // in the application but failures are not expected. + if (WARN_ON(status != NV_OK)) + memzero_page(dst_page, 0, PAGE_SIZE); } static NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) @@ -197,7 +219,6 @@ static NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) return errno_to_nv_status(ret); if (src_pfn & MIGRATE_PFN_MIGRATE) { - uvm_tracker_t tracker = UVM_TRACKER_INIT(); dst_page = alloc_page(GFP_HIGHUSER_MOVABLE); if (!dst_page) { @@ -206,12 +227,9 @@ static NV_STATUS uvm_hmm_pmm_gpu_evict_pfn(unsigned long pfn) } lock_page(dst_page); - if (WARN_ON(uvm_hmm_copy_devmem_page(dst_page, migrate_pfn_to_page(src_pfn), &tracker) != NV_OK)) - memzero_page(dst_page, 0, PAGE_SIZE); - + hmm_copy_devmem_page(dst_page, migrate_pfn_to_page(src_pfn)); dst_pfn = migrate_pfn(page_to_pfn(dst_page)); migrate_device_pages(&src_pfn, &dst_pfn, 1); - uvm_tracker_wait_deinit(&tracker); } out: @@ -674,12 +692,6 @@ bool uvm_hmm_check_context_vma_is_valid(uvm_va_block_t *va_block, return true; } -void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context) -{ - // TODO: Bug 4050579: Remove this when swap cached pages can be migrated. - service_context->block_context->hmm.swap_cached = false; -} - NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block) { if (uvm_mutex_trylock(&va_block->hmm.migrate_lock)) @@ -1072,6 +1084,7 @@ NV_STATUS uvm_hmm_split_as_needed(uvm_va_space_t *va_space, static NV_STATUS hmm_set_preferred_location_locked(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t preferred_location, + int preferred_cpu_nid, NvU64 addr, NvU64 end, uvm_tracker_t *out_tracker) @@ -1085,10 +1098,10 @@ static NV_STATUS hmm_set_preferred_location_locked(uvm_va_block_t *va_block, // Note that we can't just call uvm_va_policy_set_range() for the whole // range [addr end] because we need to examine the old value of - // policy->preferred_location before setting it. Thus we iterate over - // the existing policy nodes. + // policy->preferred_location and policy->preferred_nid before setting it. + // Thus we iterate over the existing policy nodes. uvm_for_each_va_policy_in(old_policy, va_block, addr, end, node, region) { - if (uvm_id_equal(old_policy->preferred_location, preferred_location)) + if (uvm_va_policy_preferred_location_equal(old_policy, preferred_location, preferred_cpu_nid)) continue; // If the old preferred location is a valid processor ID, remote @@ -1100,7 +1113,11 @@ static NV_STATUS hmm_set_preferred_location_locked(uvm_va_block_t *va_block, uvm_processor_mask_test(&old_policy->accessed_by, old_policy->preferred_location)) uvm_processor_mask_set(&set_accessed_by_processors, old_policy->preferred_location); - if (!uvm_va_policy_set_preferred_location(va_block, region, preferred_location, old_policy)) + if (!uvm_va_policy_set_preferred_location(va_block, + region, + preferred_location, + preferred_cpu_nid, + old_policy)) return NV_ERR_NO_MEMORY; // Establish new remote mappings if the old preferred location had @@ -1134,6 +1151,7 @@ static NV_STATUS hmm_set_preferred_location_locked(uvm_va_block_t *va_block, NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, + int preferred_cpu_nid, NvU64 base, NvU64 last_address, uvm_tracker_t *out_tracker) @@ -1170,6 +1188,7 @@ NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, status = hmm_set_preferred_location_locked(va_block, va_block_context, preferred_location, + preferred_cpu_nid, addr, end, out_tracker); @@ -1259,6 +1278,7 @@ NV_STATUS uvm_hmm_set_accessed_by(uvm_va_space_t *va_space, UVM_VA_POLICY_ACCESSED_BY, !set_bit, processor_id, + NUMA_NO_NODE, UVM_READ_DUPLICATION_MAX); if (status == NV_OK && set_bit) { @@ -1968,28 +1988,74 @@ static void fill_dst_pfns(uvm_va_block_t *va_block, } } -static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, - struct vm_area_struct *vma, - const unsigned long *src_pfns, - unsigned long *dst_pfns, - uvm_va_block_region_t region, - uvm_page_mask_t *page_mask, - uvm_page_mask_t *same_devmem_page_mask, - uvm_processor_id_t processor_id, - uvm_service_block_context_t *service_context) +static NV_STATUS alloc_page_on_cpu(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_page_mask_t *same_devmem_page_mask, + uvm_va_block_context_t *block_context) +{ + NV_STATUS status; + struct page *src_page; + struct page *dst_page; + + // This is the page that will be copied to system memory. + src_page = migrate_pfn_to_page(src_pfns[page_index]); + + if (src_page) { + // mremap may have caused us to lose the gpu_chunk associated with + // this va_block/page_index so make sure we have the correct chunk. + if (is_device_private_page(src_page)) + gpu_chunk_add(va_block, page_index, src_page); + + if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { + lock_block_cpu_page(va_block, page_index, src_page, dst_pfns, same_devmem_page_mask); + return NV_OK; + } + } + + UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || + !uvm_va_block_cpu_is_page_resident_on(va_block, NUMA_NO_NODE, page_index)); + + status = uvm_va_block_populate_page_cpu(va_block, page_index, block_context); + if (status != NV_OK) + return status; + + // TODO: Bug 3368756: add support for transparent huge pages + // Support for large CPU pages means the page_index may need fixing + dst_page = migrate_pfn_to_page(block_context->hmm.dst_pfns[page_index]); + + // Note that we don't call get_page(dst_page) since alloc_page_vma() + // returns with a page reference count of one and we are passing + // ownership to Linux. Also, uvm_va_block_cpu_page_populate() recorded + // the page as "mirrored" so that migrate_vma_finalize() and + // hmm_va_block_cpu_page_unpopulate() don't double free the page. + lock_page(dst_page); + dst_pfns[page_index] = migrate_pfn(page_to_pfn(dst_page)); + + return NV_OK; +} + +// Allocates pages on the CPU to handle migration due to a page fault +static NV_STATUS fault_alloc_on_cpu(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_page_mask_t *same_devmem_page_mask, + uvm_processor_id_t fault_processor_id, + uvm_service_block_context_t *service_context) { uvm_page_index_t page_index; NV_STATUS status = NV_OK; - for_each_va_block_page_in_region_mask(page_index, page_mask, region) { - struct page *src_page; - struct page *dst_page; - gfp_t gfp; + UVM_ASSERT(service_context); + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { if (!(src_pfns[page_index] & MIGRATE_PFN_MIGRATE)) { // Device exclusive PTEs are not selected but we still want to // process the page so record it as such. - if (service_context && !UVM_ID_IS_CPU(processor_id) && + if (!UVM_ID_IS_CPU(fault_processor_id) && service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_ATOMIC_STRONG) { uvm_page_mask_set(same_devmem_page_mask, page_index); continue; @@ -2004,74 +2070,20 @@ static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, goto clr_mask; } - // This is the page that will be copied to system memory. - src_page = migrate_pfn_to_page(src_pfns[page_index]); - - if (src_page) { - // mremap may have caused us to loose the gpu_chunk associated with - // this va_block/page_index so make sure we have the correct chunk. - if (is_device_private_page(src_page)) - gpu_chunk_add(va_block, page_index, src_page); - - if (uvm_page_mask_test(&va_block->cpu.allocated, page_index)) { - lock_block_cpu_page(va_block, page_index, src_page, dst_pfns, same_devmem_page_mask); - continue; - } - } - - UVM_ASSERT(!uvm_processor_mask_test(&va_block->resident, UVM_ID_CPU) || - !uvm_va_block_cpu_is_page_resident_on(va_block, NUMA_NO_NODE, page_index)); - - // Allocate a user system memory page for the destination. - // This is the typical case since Linux will free the source page when - // migrating to device private memory. - // If there is no source page, it means the page is pte_none() or the - // zero page. This case "shouldn't happen" because we asked - // migrate_vma_setup() only for device private pages but - // migrate_vma_collect_hole() doesn't check the - // MIGRATE_VMA_SELECT_SYSTEM flag. - gfp = GFP_HIGHUSER_MOVABLE; - if (!src_page) - gfp |= __GFP_ZERO; - - dst_page = alloc_page_vma(gfp, - vma, - va_block->start + (page_index << PAGE_SHIFT)); - if (!dst_page) { - // Ignore errors if the page is only for prefetching. - if (service_context && - service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_PREFETCH) - goto clr_mask; - UVM_ERR_PRINT("cannot allocate page %u (addr 0x%llx)\n", - page_index, va_block->start + (page_index << PAGE_SHIFT)); - status = NV_ERR_NO_MEMORY; - break; - } - - status = hmm_va_block_cpu_page_populate(va_block, page_index, dst_page); + status = alloc_page_on_cpu(va_block, page_index, src_pfns, dst_pfns, same_devmem_page_mask, service_context->block_context); if (status != NV_OK) { - __free_page(dst_page); // Ignore errors if the page is only for prefetching. if (service_context && service_context->access_type[page_index] == UVM_FAULT_ACCESS_TYPE_PREFETCH) goto clr_mask; break; } - - // Note that we don't call get_page(dst_page) since alloc_page_vma() - // returns with a page reference count of one and we are passing - // ownership to Linux. Also, uvm_va_block_cpu_page_populate() recorded - // the page as "mirrored" so that migrate_vma_finalize() and - // hmm_va_block_cpu_page_unpopulate() don't double free the page. - lock_page(dst_page); - dst_pfns[page_index] = migrate_pfn(page_to_pfn(dst_page)); continue; clr_mask: // TODO: Bug 3900774: clean up murky mess of mask clearing. uvm_page_mask_clear(page_mask, page_index); - if (service_context) - clear_service_context_masks(service_context, UVM_ID_CPU, page_index); + clear_service_context_masks(service_context, UVM_ID_CPU, page_index); } if (status != NV_OK) @@ -2082,6 +2094,40 @@ static NV_STATUS alloc_and_copy_to_cpu(uvm_va_block_t *va_block, return status; } +// Allocates pages on the CPU for explicit migration calls. +static NV_STATUS migrate_alloc_on_cpu(uvm_va_block_t *va_block, + const unsigned long *src_pfns, + unsigned long *dst_pfns, + uvm_va_block_region_t region, + uvm_page_mask_t *page_mask, + uvm_page_mask_t *same_devmem_page_mask, + uvm_va_block_context_t *block_context) +{ + uvm_page_index_t page_index; + NV_STATUS status = NV_OK; + + for_each_va_block_page_in_region_mask(page_index, page_mask, region) { + if (!(src_pfns[page_index] & MIGRATE_PFN_MIGRATE)) { + // We have previously found a page that is CPU resident which can't + // be migrated (probably a shared mapping) so make sure we establish + // a remote mapping for it. + if (uvm_page_mask_test(same_devmem_page_mask, page_index)) + continue; + + uvm_page_mask_clear(page_mask, page_index); + continue; + } + + status = alloc_page_on_cpu(va_block, page_index, src_pfns, dst_pfns, same_devmem_page_mask, block_context); + } + + if (status != NV_OK) + clean_up_non_migrating_pages(va_block, src_pfns, dst_pfns, region, page_mask); + else if (uvm_page_mask_empty(page_mask)) + return NV_WARN_MORE_PROCESSING_REQUIRED; + + return status; +} static NV_STATUS uvm_hmm_devmem_fault_alloc_and_copy(uvm_hmm_devmem_fault_context_t *devmem_fault_context) { uvm_processor_id_t processor_id; @@ -2107,15 +2153,14 @@ static NV_STATUS uvm_hmm_devmem_fault_alloc_and_copy(uvm_hmm_devmem_fault_contex page_mask = &devmem_fault_context->page_mask; uvm_page_mask_copy(page_mask, &service_context->per_processor_masks[UVM_ID_CPU_VALUE].new_residency); - status = alloc_and_copy_to_cpu(va_block, - service_context->block_context->hmm.vma, - src_pfns, - dst_pfns, - service_context->region, - page_mask, - same_devmem_page_mask, - processor_id, - service_context); + status = fault_alloc_on_cpu(va_block, + src_pfns, + dst_pfns, + service_context->region, + page_mask, + same_devmem_page_mask, + processor_id, + service_context); if (status != NV_OK) return status; @@ -2640,12 +2685,8 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, if (PageSwapCache(src_page)) { // TODO: Bug 4050579: Remove this when swap cached pages can be // migrated. - if (service_context) { - service_context->block_context->hmm.swap_cached = true; - break; - } - - goto clr_mask; + status = NV_WARN_MISMATCHED_TARGET; + break; } // If the page is already allocated, it is most likely a mirrored @@ -2699,8 +2740,7 @@ static NV_STATUS dmamap_src_sysmem_pages(uvm_va_block_t *va_block, clear_service_context_masks(service_context, dest_id, page_index); } - if (uvm_page_mask_empty(page_mask) || - (service_context && service_context->block_context->hmm.swap_cached)) + if (uvm_page_mask_empty(page_mask)) status = NV_WARN_MORE_PROCESSING_REQUIRED; if (status != NV_OK) @@ -2945,15 +2985,13 @@ static NV_STATUS uvm_hmm_migrate_alloc_and_copy(struct vm_area_struct *vma, uvm_assert_mutex_locked(&va_block->lock); if (UVM_ID_IS_CPU(dest_id)) { - status = alloc_and_copy_to_cpu(va_block, - vma, - src_pfns, - dst_pfns, - region, - page_mask, - &uvm_hmm_migrate_event->same_devmem_page_mask, - UVM_ID_INVALID, - NULL); + status = migrate_alloc_on_cpu(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + &uvm_hmm_migrate_event->same_devmem_page_mask, + va_block_context); } else { status = dmamap_src_sysmem_pages(va_block, @@ -3154,7 +3192,7 @@ NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, migrate_vma_finalize(args); - if (status == NV_WARN_NOTHING_TO_DO) + if (status == NV_WARN_NOTHING_TO_DO || status == NV_WARN_MISMATCHED_TARGET) status = NV_OK; return status; @@ -3288,15 +3326,13 @@ static NV_STATUS hmm_va_block_evict_chunks(uvm_va_block_t *va_block, // TODO: Bug 3660922: Need to handle read duplication at some point. UVM_ASSERT(uvm_page_mask_region_empty(cpu_resident_mask, region)); - status = alloc_and_copy_to_cpu(va_block, - NULL, - src_pfns, - dst_pfns, - region, - page_mask, - NULL, - UVM_ID_INVALID, - NULL); + status = migrate_alloc_on_cpu(va_block, + src_pfns, + dst_pfns, + region, + page_mask, + NULL, + va_block_context); if (status != NV_OK) goto err; @@ -3392,7 +3428,6 @@ NV_STATUS uvm_hmm_remote_cpu_fault(struct vm_fault *vmf) unsigned long dst_pfn; struct migrate_vma args; struct page *src_page = vmf->page; - uvm_tracker_t tracker = UVM_TRACKER_INIT(); int ret; args.vma = vmf->vma; @@ -3421,9 +3456,7 @@ NV_STATUS uvm_hmm_remote_cpu_fault(struct vm_fault *vmf) lock_page(dst_page); dst_pfn = migrate_pfn(page_to_pfn(dst_page)); - status = uvm_hmm_copy_devmem_page(dst_page, src_page, &tracker); - if (status == NV_OK) - status = uvm_tracker_wait_deinit(&tracker); + hmm_copy_devmem_page(dst_page, src_page); } migrate_vma_pages(&args); @@ -3591,6 +3624,7 @@ NV_STATUS uvm_hmm_va_range_info(uvm_va_space_t *va_space, params->va_range_end = ULONG_MAX; params->read_duplication = UVM_TEST_READ_DUPLICATION_UNSET; memset(¶ms->preferred_location, 0, sizeof(params->preferred_location)); + params->preferred_cpu_nid = NUMA_NO_NODE; params->accessed_by_count = 0; params->managed.vma_start = 0; params->managed.vma_end = 0; @@ -3633,8 +3667,10 @@ NV_STATUS uvm_hmm_va_range_info(uvm_va_space_t *va_space, params->read_duplication = node->policy.read_duplication; - if (!UVM_ID_IS_INVALID(node->policy.preferred_location)) + if (!UVM_ID_IS_INVALID(node->policy.preferred_location)) { uvm_va_space_processor_uuid(va_space, ¶ms->preferred_location, node->policy.preferred_location); + params->preferred_cpu_nid = node->policy.preferred_nid; + } for_each_id_in_mask(processor_id, &node->policy.accessed_by) uvm_va_space_processor_uuid(va_space, ¶ms->accessed_by[params->accessed_by_count++], processor_id); @@ -3652,22 +3688,16 @@ NV_STATUS uvm_hmm_va_range_info(uvm_va_space_t *va_space, // TODO: Bug 3660968: Remove this hack as soon as HMM migration is implemented // for VMAs other than anonymous private memory. bool uvm_hmm_must_use_sysmem(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context) + struct vm_area_struct *vma) { - struct vm_area_struct *vma = va_block_context->hmm.vma; - uvm_assert_mutex_locked(&va_block->lock); if (!uvm_va_block_is_hmm(va_block)) return false; UVM_ASSERT(vma); - UVM_ASSERT(va_block_context->mm == vma->vm_mm); - uvm_assert_mmap_lock_locked(va_block_context->mm); - - // TODO: Bug 4050579: Remove this when swap cached pages can be migrated. - if (va_block_context->hmm.swap_cached) - return true; + UVM_ASSERT(va_block->hmm.va_space->va_space_mm.mm == vma->vm_mm); + uvm_assert_mmap_lock_locked(vma->vm_mm); // migrate_vma_setup() can't migrate VM_SPECIAL so we have to force GPU // remote mapping. diff --git a/kernel-open/nvidia-uvm/uvm_hmm.h b/kernel-open/nvidia-uvm/uvm_hmm.h index 9983c5dc98..8c6a4f58d3 100644 --- a/kernel-open/nvidia-uvm/uvm_hmm.h +++ b/kernel-open/nvidia-uvm/uvm_hmm.h @@ -114,11 +114,6 @@ typedef struct struct vm_area_struct *vma, uvm_va_block_region_t region); - // Initialize the HMM portion of the service_context. - // This should be called one time before any retry loops calling - // uvm_va_block_service_locked(). - void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context); - // Begin a migration critical section. When calling into the kernel it is // sometimes necessary to drop the va_block lock. This function returns // NV_OK when no other thread has started a migration critical section. @@ -183,6 +178,7 @@ typedef struct // and the va_space lock must be held in write mode. NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, + int preferred_cpu_nid, NvU64 base, NvU64 last_address, uvm_tracker_t *out_tracker); @@ -271,6 +267,18 @@ typedef struct NvU64 addr); // This is called to service a GPU fault. + // processor_id is the faulting processor. + // new_residency is the processor where the data should be migrated to. + // Special return values (besides things like NV_ERR_NO_MEMORY): + // NV_WARN_MORE_PROCESSING_REQUIRED indicates that one or more pages could + // not be migrated and that a retry might succeed after unlocking the + // va_block lock, va_space lock, and mmap lock. + // NV_WARN_MISMATCHED_TARGET is a special case of GPU fault handling when a + // GPU is chosen as the destination and the source is a HMM CPU page that + // can't be migrated (i.e., must remain in system memory). In that case, + // uvm_va_block_select_residency() should be called with 'hmm_migratable' + // set to false so that system memory will be selected. Then this call can + // be retried to service the GPU fault by migrating to system memory. // Locking: the va_space->va_space_mm.mm mmap_lock must be locked, // the va_space read lock must be held, and the va_block lock held. NV_STATUS uvm_hmm_va_block_service_locked(uvm_processor_id_t processor_id, @@ -282,8 +290,10 @@ typedef struct // This is called to migrate a region within a HMM va_block. // va_block_context must not be NULL and va_block_context->hmm.vma // must be valid. - // Locking: the va_space->va_space_mm.mm must be retained, mmap_lock must be - // locked, and the va_block lock held. + // Special return values (besides things like NV_ERR_NO_MEMORY): + // NV_WARN_MORE_PROCESSING_REQUIRED indicates that one or more pages could + // not be migrated and that a retry might succeed after unlocking the + // va_block lock, va_space lock, and mmap lock. NV_STATUS uvm_hmm_va_block_migrate_locked(uvm_va_block_t *va_block, uvm_va_block_retry_t *va_block_retry, uvm_va_block_context_t *va_block_context, @@ -382,7 +392,7 @@ typedef struct // va_block, the va_block_context->mm must be retained and locked for least // read. bool uvm_hmm_must_use_sysmem(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context); + struct vm_area_struct *vma); #else // UVM_IS_CONFIG_HMM() @@ -441,10 +451,6 @@ typedef struct return true; } - static void uvm_hmm_service_context_init(uvm_service_block_context_t *service_context) - { - } - static NV_STATUS uvm_hmm_migrate_begin(uvm_va_block_t *va_block) { return NV_OK; @@ -485,6 +491,7 @@ typedef struct static NV_STATUS uvm_hmm_set_preferred_location(uvm_va_space_t *va_space, uvm_processor_id_t preferred_location, + int preferred_cpu_nid, NvU64 base, NvU64 last_address, uvm_tracker_t *out_tracker) @@ -648,7 +655,7 @@ typedef struct } static bool uvm_hmm_must_use_sysmem(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context) + struct vm_area_struct *vma) { return false; } diff --git a/kernel-open/nvidia-uvm/uvm_hopper.c b/kernel-open/nvidia-uvm/uvm_hopper.c index c2457d9af8..fdda409875 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper.c +++ b/kernel-open/nvidia-uvm/uvm_hopper.c @@ -55,7 +55,7 @@ void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE; // See uvm_mmu.h for mapping placement - parent_gpu->flat_vidmem_va_base = (64 * UVM_SIZE_1PB) + (8 * UVM_SIZE_1TB); + parent_gpu->flat_vidmem_va_base = (64 * UVM_SIZE_1PB) + (32 * UVM_SIZE_1TB); // Physical CE writes to vidmem are non-coherent with respect to the CPU on // GH180. @@ -88,6 +88,8 @@ void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counters_supported = true; + parent_gpu->access_counters_can_use_physical_addresses = false; + parent_gpu->fault_cancel_va_supported = true; parent_gpu->scoped_atomics_supported = true; @@ -103,5 +105,6 @@ void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->map_remap_larger_page_promotion = false; parent_gpu->plc_supported = true; -} + parent_gpu->no_ats_range_required = true; +} diff --git a/kernel-open/nvidia-uvm/uvm_hopper_ce.c b/kernel-open/nvidia-uvm/uvm_hopper_ce.c index dc185c6f74..320205402f 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper_ce.c +++ b/kernel-open/nvidia-uvm/uvm_hopper_ce.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020-2022 NVIDIA Corporation + Copyright (c) 2020-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -22,6 +22,7 @@ *******************************************************************************/ #include "uvm_hal.h" +#include "uvm_global.h" #include "uvm_push.h" #include "uvm_mem.h" #include "uvm_conf_computing.h" @@ -154,7 +155,8 @@ static NvU32 hopper_memset_push_phys_mode(uvm_push_t *push, uvm_gpu_address_t ds static bool va_is_flat_vidmem(uvm_gpu_t *gpu, NvU64 va) { - return (uvm_mmu_gpu_needs_static_vidmem_mapping(gpu) || uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) && + return (uvm_mmu_parent_gpu_needs_static_vidmem_mapping(gpu->parent) || + uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(gpu->parent)) && va >= gpu->parent->flat_vidmem_va_base && va < gpu->parent->flat_vidmem_va_base + UVM_GPU_MAX_PHYS_MEM; } @@ -180,17 +182,18 @@ static bool hopper_scrub_enable(uvm_gpu_t *gpu, uvm_gpu_address_t *dst, size_t s return !dst->is_virtual && dst->aperture == UVM_APERTURE_VID; } -static NvU32 hopper_memset_copy_type(uvm_push_t *push, uvm_gpu_address_t dst) +static NvU32 hopper_memset_copy_type(uvm_gpu_address_t dst) { - if (uvm_conf_computing_mode_enabled(uvm_push_get_gpu(push)) && dst.is_unprotected) + if (g_uvm_global.conf_computing_enabled && dst.is_unprotected) return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, NONPROT2NONPROT); return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, DEFAULT); } -NvU32 uvm_hal_hopper_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +NvU32 uvm_hal_hopper_ce_memcopy_copy_type(uvm_gpu_address_t dst, uvm_gpu_address_t src) { - if (uvm_conf_computing_mode_enabled(uvm_push_get_gpu(push)) && dst.is_unprotected && src.is_unprotected) + if (g_uvm_global.conf_computing_enabled && dst.is_unprotected && src.is_unprotected) return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, NONPROT2NONPROT); + return HWCONST(C8B5, LAUNCH_DMA, COPY_TYPE, DEFAULT); } @@ -210,7 +213,7 @@ static void hopper_memset_common(uvm_push_t *push, NvU32 launch_dma_remap_enable; NvU32 launch_dma_scrub_enable; NvU32 flush_value = HWCONST(C8B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); - NvU32 copy_type_value = hopper_memset_copy_type(push, dst); + NvU32 copy_type_value = hopper_memset_copy_type(dst); bool is_scrub = hopper_scrub_enable(gpu, &dst, num_elements * memset_element_size); UVM_ASSERT_MSG(gpu->parent->ce_hal->memset_is_valid(push, dst, num_elements, memset_element_size), diff --git a/kernel-open/nvidia-uvm/uvm_hopper_mmu.c b/kernel-open/nvidia-uvm/uvm_hopper_mmu.c index 092a7e2ba5..025343d25b 100644 --- a/kernel-open/nvidia-uvm/uvm_hopper_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_hopper_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2020-2022 NVIDIA Corporation + Copyright (c) 2020-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,6 +33,7 @@ #include "uvm_types.h" #include "uvm_global.h" +#include "uvm_common.h" #include "uvm_hal.h" #include "uvm_hal_types.h" #include "uvm_hopper_fault_buffer.h" @@ -42,6 +43,10 @@ #define MMU_BIG 0 #define MMU_SMALL 1 +// Used in pde_pcf(). +#define ATS_ALLOWED 0 +#define ATS_NOT_ALLOWED 1 + uvm_mmu_engine_type_t uvm_hal_hopper_mmu_engine_id_to_type(NvU16 mmu_engine_id) { if (mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_HOST0 && mmu_engine_id <= NV_PFAULT_MMU_ENG_ID_HOST44) @@ -260,7 +265,108 @@ static NvU64 poisoned_pte_hopper(void) return WRITE_HWCONST64(pte_bits, _MMU_VER3, PTE, PCF, PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD); } -static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, NvU32 depth) +typedef enum +{ + PDE_TYPE_SINGLE, + PDE_TYPE_DUAL_BIG, + PDE_TYPE_DUAL_SMALL, + PDE_TYPE_COUNT, +} pde_type_t; + +static const NvU8 valid_pcf[][2] = { { NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED } }; + +static const NvU8 invalid_pcf[][2] = { { NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED, + NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED }, + { NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED, + NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED } }; + +static const NvU8 va_base[] = { 56, 47, 38, 29, 21 }; + +static bool is_ats_range_valid(uvm_page_directory_t *dir, NvU32 child_index) +{ + NvU64 pde_base_va; + NvU64 min_va_upper; + NvU64 max_va_lower; + NvU32 index_in_dir; + + uvm_cpu_get_unaddressable_range(&max_va_lower, &min_va_upper); + + UVM_ASSERT(dir->depth < ARRAY_SIZE(va_base)); + + // We can use UVM_PAGE_SIZE_AGNOSTIC because page_size is only used in + // index_bits_hopper() for PTE table, i.e., depth 5+, which does not use a + // PDE PCF or an ATS_ALLOWED/NOT_ALLOWED setting. + UVM_ASSERT(child_index < (1ull << index_bits_hopper(dir->depth, UVM_PAGE_SIZE_AGNOSTIC))); + + pde_base_va = 0; + index_in_dir = child_index; + while (dir) { + pde_base_va += index_in_dir * (1ull << va_base[dir->depth]); + index_in_dir = dir->index_in_parent; + dir = dir->host_parent; + } + pde_base_va = (NvU64)((NvS64)(pde_base_va << (64 - num_va_bits_hopper())) >> (64 - num_va_bits_hopper())); + + if (pde_base_va < max_va_lower || pde_base_va >= min_va_upper) + return true; + + return false; +} + +// PDE Permission Control Flags +static NvU32 pde_pcf(bool valid, pde_type_t pde_type, uvm_page_directory_t *dir, NvU32 child_index) +{ + const NvU8 (*pcf)[2] = valid ? valid_pcf : invalid_pcf; + NvU8 depth = dir->depth; + + UVM_ASSERT(pde_type < PDE_TYPE_COUNT); + UVM_ASSERT(depth < 5); + + // On non-ATS systems, PDE PCF only sets the valid and volatile/cache bits. + if (!g_uvm_global.ats.enabled) + return pcf[pde_type][ATS_ALLOWED]; + + // We assume all supported ATS platforms use canonical form address. + // See comments in uvm_gpu.c:uvm_gpu_can_address() and in + // uvm_mmu.c:page_tree_ats_init(); + UVM_ASSERT(uvm_platform_uses_canonical_form_address()); + + // Hopper GPUs on ATS-enabled systems, perform a parallel lookup on both + // ATS and GMMU page tables. For managed memory we need to prevent this + // parallel lookup since we would not get any GPU fault if the CPU has + // a valid mapping. Also, for external ranges that are known to be + // mapped entirely on the GMMU page table we can skip the ATS lookup + // for performance reasons. Parallel ATS lookup is disabled in PDE1 + // (depth 3) and, therefore, it applies to the underlying 512MB VA + // range. + // + // UVM sets ATS_NOT_ALLOWED for all Hopper+ mappings on ATS systems. + // This is fine because CUDA ensures that all managed and external + // allocations are properly compartmentalized in 512MB-aligned VA + // regions. For cudaHostRegister CUDA cannot control the VA range, but + // we rely on ATS for those allocations so they can't choose the + // ATS_NOT_ALLOWED mode. + // TODO: Bug 3254055: Relax the NO_ATS setting from 512MB (pde1) range to + // PTEs. + // HW complies with the leaf PDE's ATS_ALLOWED/ATS_NOT_ALLOWED settings, + // enabling us to treat any upper-level PDE as a don't care as long as there + // are leaf PDEs for the entire upper-level PDE range. We assume PDE4 + // entries (depth == 0) are always ATS enabled, and the no_ats_range is in + // PDE3 or lower. + if (depth == 0 || (!valid && is_ats_range_valid(dir, child_index))) + return pcf[pde_type][ATS_ALLOWED]; + + return pcf[pde_type][ATS_NOT_ALLOWED]; +} + +static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -280,38 +386,17 @@ static NvU64 single_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, NvU32 dep break; } - // PCF (permission control flags) 5:3 - // Hopper GPUs on ATS-enabled systems, perform a parallel lookup on both - // ATS and GMMU page tables. For managed memory we need to prevent this - // parallel lookup since we would not get any GPU fault if the CPU has - // a valid mapping. Also, for external ranges that are known to be - // mapped entirely on the GMMU page table we can skip the ATS lookup - // for performance reasons. Parallel ATS lookup is disabled in PDE1 - // (depth 3) and, therefore, it applies to the underlying 512MB VA - // range. - // - // UVM sets ATS_NOT_ALLOWED for all Hopper+ mappings on ATS systems. - // This is fine because CUDA ensures that all managed and external - // allocations are properly compartmentalized in 512MB-aligned VA - // regions. For cudaHostRegister CUDA cannot control the VA range, but - // we rely on ATS for those allocations so they can't choose the - // ATS_NOT_ALLOWED mode. - // - // TODO: Bug 3254055: Relax the NO_ATS setting from 512MB (pde1) range - // to PTEs. - if (depth == 3 && g_uvm_global.ats.enabled) - pde_bits |= HWCONST64(_MMU_VER3, PDE, PCF, VALID_UNCACHED_ATS_NOT_ALLOWED); - else - pde_bits |= HWCONST64(_MMU_VER3, PDE, PCF, VALID_UNCACHED_ATS_ALLOWED); - // address 51:12 pde_bits |= HWVALUE64(_MMU_VER3, PDE, ADDRESS, address); } + // PCF (permission control flags) 5:3 + pde_bits |= HWVALUE64(_MMU_VER3, PDE, PCF, pde_pcf(phys_alloc != NULL, PDE_TYPE_SINGLE, dir, child_index)); + return pde_bits; } -static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) +static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -330,17 +415,20 @@ static NvU64 big_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) break; } - // PCF (permission control flags) 5:3 - pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, PCF_BIG, VALID_UNCACHED_ATS_NOT_ALLOWED); - // address 51:8 pde_bits |= HWVALUE64(_MMU_VER3, DUAL_PDE, ADDRESS_BIG, address); } + // PCF (permission control flags) 5:3 + pde_bits |= HWVALUE64(_MMU_VER3, + DUAL_PDE, + PCF_BIG, + pde_pcf(phys_alloc != NULL, PDE_TYPE_DUAL_BIG, dir, child_index)); + return pde_bits; } -static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) +static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc, uvm_page_directory_t *dir, NvU32 child_index) { NvU64 pde_bits = 0; @@ -359,29 +447,40 @@ static NvU64 small_half_pde_hopper(uvm_mmu_page_table_alloc_t *phys_alloc) break; } - // PCF (permission control flags) 69:67 [5:3] - pde_bits |= HWCONST64(_MMU_VER3, DUAL_PDE, PCF_SMALL, VALID_UNCACHED_ATS_NOT_ALLOWED); - // address 115:76 [51:12] pde_bits |= HWVALUE64(_MMU_VER3, DUAL_PDE, ADDRESS_SMALL, address); } + + // PCF (permission control flags) 69:67 [5:3] + pde_bits |= HWVALUE64(_MMU_VER3, + DUAL_PDE, + PCF_SMALL, + pde_pcf(phys_alloc != NULL, PDE_TYPE_DUAL_SMALL, dir, child_index)); + return pde_bits; } -static void make_pde_hopper(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_hopper(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_hopper(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_hopper(dir->depth); + if (entry_count == 1) { - *entry_bits = single_pde_hopper(*phys_allocs, depth); + *entry_bits = single_pde_hopper(*phys_allocs, dir, child_index); } else if (entry_count == 2) { - entry_bits[MMU_BIG] = big_half_pde_hopper(phys_allocs[MMU_BIG]); - entry_bits[MMU_SMALL] = small_half_pde_hopper(phys_allocs[MMU_SMALL]); + entry_bits[MMU_BIG] = big_half_pde_hopper(phys_allocs[MMU_BIG], dir, child_index); + entry_bits[MMU_SMALL] = small_half_pde_hopper(phys_allocs[MMU_SMALL], dir, child_index); // This entry applies to the whole dual PDE but is stored in the lower - // bits + // bits. entry_bits[MMU_BIG] |= HWCONST64(_MMU_VER3, DUAL_PDE, IS_PTE, FALSE); } else { diff --git a/kernel-open/nvidia-uvm/uvm_ioctl.h b/kernel-open/nvidia-uvm/uvm_ioctl.h index b0f291b421..873b8ddb0c 100644 --- a/kernel-open/nvidia-uvm/uvm_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_ioctl.h @@ -633,6 +633,7 @@ typedef struct NvU64 requestedBase NV_ALIGN_BYTES(8); // IN NvU64 length NV_ALIGN_BYTES(8); // IN NvProcessorUuid preferredLocation; // IN + NvS32 preferredCpuNumaNode; // IN NV_STATUS rmStatus; // OUT } UVM_SET_PREFERRED_LOCATION_PARAMS; @@ -766,8 +767,19 @@ typedef struct #define UVM_MIGRATE_FLAGS_ALL (UVM_MIGRATE_FLAG_ASYNC | \ UVM_MIGRATE_FLAGS_TEST_ALL) -// For pageable migrations, cpuNumaNode is used as the destination NUMA node if -// destinationUuid is the CPU. +// If NV_ERR_INVALID_ARGUMENT is returned it is because cpuMemoryNode is not +// valid and the destination processor is the CPU. cpuMemoryNode is considered +// invalid if: +// * it is less than -1, +// * it is equal to or larger than the maximum number of nodes, or +// * it corresponds to a registered GPU. +// * it is not in the node_possible_map set of nodes, +// * it does not have onlined memory +// +// For pageable migrations: +// +// In addition to the above, in the case of pageable memory, the +// cpuMemoryNode is considered invalid if it's -1. // // If NV_WARN_NOTHING_TO_DO is returned, user-space is responsible for // completing the migration of the VA range described by userSpaceStart and @@ -775,6 +787,7 @@ typedef struct // // If NV_ERR_MORE_PROCESSING_REQUIRED is returned, user-space is responsible // for re-trying with a different cpuNumaNode, starting at userSpaceStart. +// #define UVM_MIGRATE UVM_IOCTL_BASE(51) typedef struct { @@ -784,7 +797,7 @@ typedef struct NvU32 flags; // IN NvU64 semaphoreAddress NV_ALIGN_BYTES(8); // IN NvU32 semaphorePayload; // IN - NvU32 cpuNumaNode; // IN + NvS32 cpuNumaNode; // IN NvU64 userSpaceStart NV_ALIGN_BYTES(8); // OUT NvU64 userSpaceLength NV_ALIGN_BYTES(8); // OUT NV_STATUS rmStatus; // OUT diff --git a/kernel-open/nvidia-uvm/uvm_kvmalloc.c b/kernel-open/nvidia-uvm/uvm_kvmalloc.c index 69e0b30b98..2285a479b3 100644 --- a/kernel-open/nvidia-uvm/uvm_kvmalloc.c +++ b/kernel-open/nvidia-uvm/uvm_kvmalloc.c @@ -36,7 +36,7 @@ typedef struct { size_t alloc_size; - uint8_t ptr[0]; + uint8_t ptr[]; } uvm_vmalloc_hdr_t; typedef struct diff --git a/kernel-open/nvidia-uvm/uvm_lock.c b/kernel-open/nvidia-uvm/uvm_lock.c index 4b6c846d56..1ecca816cc 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.c +++ b/kernel-open/nvidia-uvm/uvm_lock.c @@ -27,7 +27,7 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) { - BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 33); + BUILD_BUG_ON(UVM_LOCK_ORDER_COUNT != 34); switch (lock_order) { UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_INVALID); @@ -62,6 +62,7 @@ const char *uvm_lock_order_to_string(uvm_lock_order_t lock_order) UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_VA_SPACE_TOOLS); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_SEMA_POOL_TRACKER); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_SECURE_SEMAPHORE); + UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_CSL_CTX); UVM_ENUM_STRING_CASE(UVM_LOCK_ORDER_LEAF); UVM_ENUM_STRING_DEFAULT(); } @@ -362,10 +363,7 @@ NV_STATUS uvm_bit_locks_init(uvm_bit_locks_t *bit_locks, size_t count, uvm_lock_ if (!bit_locks->bits) return NV_ERR_NO_MEMORY; -#if UVM_IS_DEBUG() - uvm_locking_assert_initialized(); - bit_locks->lock_order = lock_order; -#endif + uvm_lock_debug_init(bit_locks, lock_order); return NV_OK; } diff --git a/kernel-open/nvidia-uvm/uvm_lock.h b/kernel-open/nvidia-uvm/uvm_lock.h index 3242f94dce..b1a6164cdf 100644 --- a/kernel-open/nvidia-uvm/uvm_lock.h +++ b/kernel-open/nvidia-uvm/uvm_lock.h @@ -448,6 +448,12 @@ // // CE semaphore payloads are encrypted, and require to take the CSL lock // (UVM_LOCK_ORDER_LEAF) to decrypt the payload. + +// - CSL Context +// Order: UVM_LOCK_ORDER_CSL_CTX +// When the Confidential Computing feature is enabled, encrypt/decrypt +// operations to communicate with GPU are handled by the CSL context. +// This lock protects RM calls that use this context. // // - Leaf locks // Order: UVM_LOCK_ORDER_LEAF @@ -492,6 +498,11 @@ typedef enum UVM_LOCK_ORDER_VA_SPACE_TOOLS, UVM_LOCK_ORDER_SEMA_POOL_TRACKER, UVM_LOCK_ORDER_SECURE_SEMAPHORE, + + // TODO: Bug 4184836: [uvm][hcc] Remove UVM_LOCK_ORDER_CSL_CTX + // This lock order can be removed after RM no longer relies on RPC event + // notifications. + UVM_LOCK_ORDER_CSL_CTX, UVM_LOCK_ORDER_LEAF, UVM_LOCK_ORDER_COUNT, } uvm_lock_order_t; @@ -648,6 +659,15 @@ bool __uvm_locking_initialized(void); #define uvm_assert_lockable_order(order) UVM_ASSERT(__uvm_check_lockable_order(order, UVM_LOCK_FLAGS_MODE_ANY)) #define uvm_assert_unlocked_order(order) UVM_ASSERT(__uvm_check_unlocked_order(order)) +#if UVM_IS_DEBUG() +#define uvm_lock_debug_init(lock, order) ({ \ + uvm_locking_assert_initialized(); \ + (lock)->lock_order = (order); \ + }) +#else +#define uvm_lock_debug_init(lock, order) ((void) order) +#endif + // Helpers for locking mmap_lock (mmap_sem in kernels < 5.8) // and recording its usage #define uvm_assert_mmap_lock_locked_mode(mm, flags) ({ \ @@ -738,15 +758,12 @@ typedef struct #define uvm_assert_rwsem_unlocked(uvm_sem) UVM_ASSERT(!rwsem_is_locked(&(uvm_sem)->sem)) -static void uvm_init_rwsem(uvm_rw_semaphore_t *uvm_sem, uvm_lock_order_t lock_order) -{ - init_rwsem(&uvm_sem->sem); -#if UVM_IS_DEBUG() - uvm_locking_assert_initialized(); - uvm_sem->lock_order = lock_order; -#endif - uvm_assert_rwsem_unlocked(uvm_sem); -} +#define uvm_init_rwsem(uvm_sem, order) ({ \ + uvm_rw_semaphore_t *uvm_sem_ ## order = (uvm_sem); \ + init_rwsem(&uvm_sem_ ## order->sem); \ + uvm_lock_debug_init(uvm_sem, order); \ + uvm_assert_rwsem_unlocked(uvm_sem); \ + }) #define uvm_down_read(uvm_sem) ({ \ typeof(uvm_sem) _sem = (uvm_sem); \ @@ -874,15 +891,12 @@ typedef struct UVM_ASSERT_MSG(!irqs_disabled() && !in_interrupt(), "Mutexes cannot be used with interrupts disabled"); \ }) -static void uvm_mutex_init(uvm_mutex_t *mutex, uvm_lock_order_t lock_order) -{ - mutex_init(&mutex->m); -#if UVM_IS_DEBUG() - uvm_locking_assert_initialized(); - mutex->lock_order = lock_order; -#endif - uvm_assert_mutex_unlocked(mutex); -} +#define uvm_mutex_init(mutex, order) ({ \ + uvm_mutex_t *mutex_ ## order = (mutex); \ + mutex_init(&mutex_ ## order->m); \ + uvm_lock_debug_init(mutex, order); \ + uvm_assert_mutex_unlocked(mutex); \ + }) #define uvm_mutex_lock(mutex) ({ \ typeof(mutex) _mutex = (mutex); \ @@ -892,11 +906,14 @@ static void uvm_mutex_init(uvm_mutex_t *mutex, uvm_lock_order_t lock_order) uvm_assert_mutex_locked(_mutex); \ }) -// Lock w/o any tracking. This should be extremely rare and *_no_tracking -// helpers will be added only as needed. -#define uvm_mutex_lock_no_tracking(mutex) ({ \ +// Lock while already holding a lock of the same order taken with +// uvm_mutex_lock() variant. Note this shouldn't be used if the held lock was +// taken with uvm_mutex_lock_nested() because we only support a single level of +// nesting. This should be extremely rare and *_nested helpers will only be +// added as needed. +#define uvm_mutex_lock_nested(mutex) ({ \ uvm_assert_mutex_interrupts(); \ - mutex_lock(&(mutex)->m); \ + mutex_lock_nested(&(mutex)->m, 1); \ }) #define uvm_mutex_trylock(mutex) ({ \ @@ -926,9 +943,8 @@ static void uvm_mutex_init(uvm_mutex_t *mutex, uvm_lock_order_t lock_order) uvm_record_unlock_out_of_order(_mutex, UVM_LOCK_FLAGS_MODE_EXCLUSIVE); \ }) -// Unlock w/o any tracking. This should be extremely rare and *_no_tracking -// helpers will be added only as needed. -#define uvm_mutex_unlock_no_tracking(mutex) ({ \ +// Unlock w/o any tracking. +#define uvm_mutex_unlock_nested(mutex) ({ \ uvm_assert_mutex_interrupts(); \ mutex_unlock(&(mutex)->m); \ }) @@ -941,14 +957,11 @@ typedef struct #endif } uvm_semaphore_t; -static void uvm_sema_init(uvm_semaphore_t *semaphore, int val, uvm_lock_order_t lock_order) -{ - sema_init(&semaphore->sem, val); -#if UVM_IS_DEBUG() - uvm_locking_assert_initialized(); - semaphore->lock_order = lock_order; -#endif -} +#define uvm_sema_init(semaphore, val, order) ({ \ + uvm_semaphore_t *sem_ ## order = (semaphore); \ + sema_init(&sem_ ## order->sem, (val)); \ + uvm_lock_debug_init(semaphore, order); \ + }) #define uvm_sem_is_locked(uvm_sem) uvm_check_locked(uvm_sem, UVM_LOCK_FLAGS_MODE_SHARED) @@ -1012,15 +1025,12 @@ typedef struct #define uvm_assert_spinlock_unlocked(spinlock) UVM_ASSERT(!spin_is_locked(&(spinlock)->lock)) -static void uvm_spin_lock_init(uvm_spinlock_t *spinlock, uvm_lock_order_t lock_order) -{ - spin_lock_init(&spinlock->lock); -#if UVM_IS_DEBUG() - uvm_locking_assert_initialized(); - spinlock->lock_order = lock_order; -#endif - uvm_assert_spinlock_unlocked(spinlock); -} +#define uvm_spin_lock_init(spinlock, order) ({ \ + uvm_spinlock_t *spinlock_ ## order = (spinlock); \ + spin_lock_init(&spinlock_ ## order->lock); \ + uvm_lock_debug_init(spinlock, order); \ + uvm_assert_spinlock_unlocked(spinlock); \ + }) #define uvm_spin_lock(uvm_lock) ({ \ typeof(uvm_lock) _lock = (uvm_lock); \ @@ -1036,15 +1046,12 @@ static void uvm_spin_lock_init(uvm_spinlock_t *spinlock, uvm_lock_order_t lock_o uvm_record_unlock(_lock, UVM_LOCK_FLAGS_MODE_EXCLUSIVE); \ }) -static void uvm_spin_lock_irqsave_init(uvm_spinlock_irqsave_t *spinlock, uvm_lock_order_t lock_order) -{ - spin_lock_init(&spinlock->lock); -#if UVM_IS_DEBUG() - uvm_locking_assert_initialized(); - spinlock->lock_order = lock_order; -#endif - uvm_assert_spinlock_unlocked(spinlock); -} +#define uvm_spin_lock_irqsave_init(spinlock, order) ({ \ + uvm_spinlock_irqsave_t *spinlock_ ## order = (spinlock); \ + spin_lock_init(&spinlock_ ## order->lock); \ + uvm_lock_debug_init(spinlock, order); \ + uvm_assert_spinlock_unlocked(spinlock); \ + }) // Use a temp to not rely on flags being written after acquiring the lock. #define uvm_spin_lock_irqsave(uvm_lock) ({ \ @@ -1119,16 +1126,12 @@ static void uvm_rwlock_irqsave_dec(uvm_rwlock_irqsave_t *rwlock) #define uvm_assert_rwlock_unlocked(uvm_rwlock) #endif -static void uvm_rwlock_irqsave_init(uvm_rwlock_irqsave_t *rwlock, uvm_lock_order_t lock_order) -{ - rwlock_init(&rwlock->lock); -#if UVM_IS_DEBUG() - uvm_locking_assert_initialized(); - rwlock->lock_order = lock_order; - atomic_set(&rwlock->lock_count, 0); -#endif - uvm_assert_rwlock_unlocked(rwlock); -} +#define uvm_rwlock_irqsave_init(rwlock, order) ({ \ + uvm_rwlock_irqsave_t *rwlock_ ## order = rwlock; \ + rwlock_init(&rwlock_ ## order->lock); \ + uvm_lock_debug_init(rwlock, order); \ + uvm_assert_rwlock_unlocked(rwlock); \ + }) // We can't store the irq_flags within the lock itself for readers, so they must // pass in their flags. diff --git a/kernel-open/nvidia-uvm/uvm_map_external.c b/kernel-open/nvidia-uvm/uvm_map_external.c index a360328648..7b18fdd720 100644 --- a/kernel-open/nvidia-uvm/uvm_map_external.c +++ b/kernel-open/nvidia-uvm/uvm_map_external.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -633,10 +633,17 @@ static NV_STATUS set_ext_gpu_map_location(uvm_ext_gpu_map_t *ext_gpu_map, uvm_gpu_t *mapping_gpu, const UvmGpuMemoryInfo *mem_info) { - uvm_gpu_t *owning_gpu; + uvm_gpu_t *owning_gpu = NULL; + uvm_gpu_t *gpu; + if (mem_info->egm) UVM_ASSERT(mem_info->sysmem); + // !mem_info->deviceDescendant && !mem_info->sysmem imply fabric allocation. + // !mem_info->deviceDescendant also means that mem_info->uuid is invalid. In + // this case the owning GPU is NULL, meaning that UVM is oblivious to the + // topology and relies on RM and/or the fabric manager (FM) for memory + // lifetime management and GPU ref counting. if (!mem_info->deviceDescendant && !mem_info->sysmem) { ext_gpu_map->owning_gpu = NULL; ext_gpu_map->is_sysmem = false; @@ -645,7 +652,17 @@ static NV_STATUS set_ext_gpu_map_location(uvm_ext_gpu_map_t *ext_gpu_map, // This is a local or peer allocation, so the owning GPU must have been // registered. // This also checks for if EGM owning GPU is registered. - owning_gpu = uvm_va_space_get_gpu_by_uuid(va_space, &mem_info->uuid); + + // TODO: Bug 4351121: RM will return the GI UUID, but + // uvm_va_space_get_gpu_by_uuid() currently matches on physical GPU UUIDs. + // Match on GI UUID until the UVM user level API has been updated to use + // the GI UUID. + for_each_va_space_gpu(gpu, va_space) { + if (uvm_uuid_eq(&gpu->uuid, &mem_info->uuid)) { + owning_gpu = gpu; + break; + } + } if (!owning_gpu) return NV_ERR_INVALID_DEVICE; @@ -1343,7 +1360,9 @@ static NV_STATUS uvm_free(uvm_va_space_t *va_space, NvU64 base, NvU64 length) { uvm_va_range_t *va_range; NV_STATUS status = NV_OK; - uvm_global_processor_mask_t retained_mask; + // TODO: Bug 4351121: retained_mask should be pre-allocated, not on the + // stack. + uvm_processor_mask_t retained_mask; LIST_HEAD(deferred_free_list); if (uvm_api_range_invalid_4k(base, length)) @@ -1379,14 +1398,14 @@ static NV_STATUS uvm_free(uvm_va_space_t *va_space, NvU64 base, NvU64 length) // External ranges may have deferred free work, so the GPUs may have to // be retained. Construct the mask of all the GPUs that need to be // retained. - uvm_va_space_global_gpus_in_mask(va_space, &retained_mask, &va_range->external.mapped_gpus); + uvm_processor_mask_and(&retained_mask, &va_range->external.mapped_gpus, &va_space->registered_gpus); } uvm_va_range_destroy(va_range, &deferred_free_list); // If there is deferred work, retain the required GPUs. if (!list_empty(&deferred_free_list)) - uvm_global_mask_retain(&retained_mask); + uvm_global_gpu_retain(&retained_mask); out: uvm_va_space_up_write(va_space); @@ -1394,7 +1413,7 @@ static NV_STATUS uvm_free(uvm_va_space_t *va_space, NvU64 base, NvU64 length) if (!list_empty(&deferred_free_list)) { UVM_ASSERT(status == NV_OK); uvm_deferred_free_object_list(&deferred_free_list); - uvm_global_mask_release(&retained_mask); + uvm_global_gpu_release(&retained_mask); } return status; diff --git a/kernel-open/nvidia-uvm/uvm_maxwell.c b/kernel-open/nvidia-uvm/uvm_maxwell.c index b6ccf39626..9b5cd49afb 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -60,6 +60,8 @@ void uvm_hal_maxwell_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counters_supported = false; + parent_gpu->access_counters_can_use_physical_addresses = false; + parent_gpu->fault_cancel_va_supported = false; parent_gpu->scoped_atomics_supported = false; @@ -71,4 +73,6 @@ void uvm_hal_maxwell_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_access_counter_buffer.c b/kernel-open/nvidia-uvm/uvm_maxwell_access_counter_buffer.c index 519ae0daa4..3de82b697a 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_access_counter_buffer.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_access_counter_buffer.c @@ -26,39 +26,53 @@ void uvm_hal_maxwell_enable_access_counter_notifications_unsupported(uvm_parent_gpu_t *parent_gpu) { - UVM_ASSERT_MSG(false, "enable_access_counter_notifications is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "enable_access_counter_notifications is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } void uvm_hal_maxwell_disable_access_counter_notifications_unsupported(uvm_parent_gpu_t *parent_gpu) { - UVM_ASSERT_MSG(false, "disable_access_counter_notifications is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "disable_access_counter_notifications is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } void uvm_hal_maxwell_clear_access_counter_notifications_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 get) { - UVM_ASSERT_MSG(false, "clear_access_counter_notifications is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "clear_access_counter_notifications is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } NvU32 uvm_hal_maxwell_access_counter_buffer_entry_size_unsupported(uvm_parent_gpu_t *parent_gpu) { - UVM_ASSERT_MSG(false, "access_counter_buffer_entry_size is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "access_counter_buffer_entry_size is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); return 0; } bool uvm_hal_maxwell_access_counter_buffer_entry_is_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - UVM_ASSERT_MSG(false, "access_counter_buffer_entry_is_valid is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "access_counter_buffer_entry_is_valid is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); return false; } void uvm_hal_maxwell_access_counter_buffer_entry_clear_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - UVM_ASSERT_MSG(false, "access_counter_buffer_entry_clear_valid is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "access_counter_buffer_entry_clear_valid is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } void uvm_hal_maxwell_access_counter_buffer_parse_entry_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index, uvm_access_counter_buffer_entry_t *buffer_entry) { - UVM_ASSERT_MSG(false, "access_counter_buffer_parse_entry is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "access_counter_buffer_parse_entry is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_ce.c b/kernel-open/nvidia-uvm/uvm_maxwell_ce.c index 6e052b8235..51f40e0d4b 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_ce.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_ce.c @@ -186,7 +186,7 @@ NvU32 uvm_hal_maxwell_ce_plc_mode(void) } // Noop, since COPY_TYPE doesn't exist in Maxwell. -NvU32 uvm_hal_maxwell_ce_memcopy_copy_type(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_address_t src) +NvU32 uvm_hal_maxwell_ce_memcopy_copy_type(uvm_gpu_address_t dst, uvm_gpu_address_t src) { return 0; } @@ -212,7 +212,7 @@ void uvm_hal_maxwell_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu launch_dma_src_dst_type = gpu->parent->ce_hal->phys_mode(push, dst, src); launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode(); - copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(push, dst, src); + copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(dst, src); if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)) pipelined_value = HWCONST(B0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, PIPELINED); diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c b/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c index f0c1ec28a9..c090c45bd5 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_fault_buffer.c @@ -26,34 +26,46 @@ void uvm_hal_maxwell_enable_replayable_faults_unsupported(uvm_parent_gpu_t *parent_gpu) { - UVM_ASSERT_MSG(false, "enable_replayable_faults is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "enable_replayable_faults is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } void uvm_hal_maxwell_disable_replayable_faults_unsupported(uvm_parent_gpu_t *parent_gpu) { - UVM_ASSERT_MSG(false, "disable_replayable_faults is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "disable_replayable_faults is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } void uvm_hal_maxwell_clear_replayable_faults_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 get) { - UVM_ASSERT_MSG(false, "clear_replayable_faults is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "clear_replayable_faults is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } NvU32 uvm_hal_maxwell_fault_buffer_read_put_unsupported(uvm_parent_gpu_t *parent_gpu) { - UVM_ASSERT_MSG(false, "fault_buffer_read_put is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "fault_buffer_read_put is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); return 0; } NvU32 uvm_hal_maxwell_fault_buffer_read_get_unsupported(uvm_parent_gpu_t *parent_gpu) { - UVM_ASSERT_MSG(false, "fault_buffer_read_get is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "fault_buffer_read_get is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); return 0; } void uvm_hal_maxwell_fault_buffer_write_get_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - UVM_ASSERT_MSG(false, "fault_buffer_write_get is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "fault_buffer_write_get is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } NvU8 uvm_hal_maxwell_fault_buffer_get_ve_id_unsupported(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type) @@ -72,24 +84,32 @@ NV_STATUS uvm_hal_maxwell_fault_buffer_parse_replayable_entry_unsupported(uvm_pa NvU32 index, uvm_fault_buffer_entry_t *buffer_entry) { - UVM_ASSERT_MSG(false, "fault_buffer_parse_entry is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "fault_buffer_parse_entry is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); return NV_ERR_NOT_SUPPORTED; } bool uvm_hal_maxwell_fault_buffer_entry_is_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - UVM_ASSERT_MSG(false, "fault_buffer_entry_is_valid is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "fault_buffer_entry_is_valid is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); return false; } void uvm_hal_maxwell_fault_buffer_entry_clear_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - UVM_ASSERT_MSG(false, "fault_buffer_entry_clear_valid is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "fault_buffer_entry_clear_valid is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } NvU32 uvm_hal_maxwell_fault_buffer_entry_size_unsupported(uvm_parent_gpu_t *parent_gpu) { - UVM_ASSERT_MSG(false, "fault_buffer_entry_size is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "fault_buffer_entry_size is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); return 0; } @@ -97,6 +117,8 @@ void uvm_hal_maxwell_fault_buffer_parse_non_replayable_entry_unsupported(uvm_par void *fault_packet, uvm_fault_buffer_entry_t *buffer_entry) { - UVM_ASSERT_MSG(false, "fault_buffer_parse_non_replayable_entry is not supported on GPU: %s.\n", parent_gpu->name); + UVM_ASSERT_MSG(false, + "fault_buffer_parse_non_replayable_entry is not supported on GPU: %s.\n", + uvm_parent_gpu_name(parent_gpu)); } diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c b/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c index 4f3e055529..d2107844d0 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -106,10 +106,16 @@ static NvU64 small_half_pde_maxwell(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_maxwell(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_maxwell(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { NvU64 pde_bits = 0; - UVM_ASSERT(depth == 0); + + UVM_ASSERT(dir); + UVM_ASSERT(dir->depth == 0); + pde_bits |= HWCONST64(_MMU, PDE, SIZE, FULL); pde_bits |= big_half_pde_maxwell(phys_allocs[MMU_BIG]) | small_half_pde_maxwell(phys_allocs[MMU_SMALL]); diff --git a/kernel-open/nvidia-uvm/uvm_mem.c b/kernel-open/nvidia-uvm/uvm_mem.c index 5ba285c4b6..b80af4fa83 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_mem.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -93,8 +93,9 @@ static bool sysmem_can_be_mapped_on_gpu(uvm_mem_t *sysmem) { UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); - // If SEV is enabled, only unprotected memory can be mapped - if (g_uvm_global.sev_enabled) + // In Confidential Computing, only unprotected memory can be mapped on the + // GPU + if (g_uvm_global.conf_computing_enabled) return uvm_mem_is_sysmem_dma(sysmem); return true; @@ -126,12 +127,12 @@ bool uvm_mem_mapped_on_gpu_user(uvm_mem_t *mem, uvm_gpu_t *gpu) if (mem->user == NULL) return false; - return uvm_global_processor_mask_test(&mem->user->mapped_on, gpu->global_id); + return uvm_processor_mask_test(&mem->user->mapped_on, gpu->id); } bool uvm_mem_mapped_on_gpu_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) { - return uvm_global_processor_mask_test(&mem->kernel.mapped_on, gpu->global_id); + return uvm_processor_mask_test(&mem->kernel.mapped_on, gpu->id); } bool uvm_mem_mapped_on_cpu_user(uvm_mem_t *mem) @@ -139,12 +140,12 @@ bool uvm_mem_mapped_on_cpu_user(uvm_mem_t *mem) if (mem->user == NULL) return false; - return uvm_global_processor_mask_test(&mem->user->mapped_on, UVM_GLOBAL_ID_CPU); + return uvm_processor_mask_test(&mem->user->mapped_on, UVM_ID_CPU); } bool uvm_mem_mapped_on_cpu_kernel(uvm_mem_t *mem) { - return uvm_global_processor_mask_test(&mem->kernel.mapped_on, UVM_GLOBAL_ID_CPU); + return uvm_processor_mask_test(&mem->kernel.mapped_on, UVM_ID_CPU); } static void mem_set_mapped_on_gpu_user(uvm_mem_t *mem, uvm_gpu_t *gpu) @@ -153,7 +154,7 @@ static void mem_set_mapped_on_gpu_user(uvm_mem_t *mem, uvm_gpu_t *gpu) UVM_ASSERT(mem_can_be_mapped_on_gpu_user(mem, gpu)); UVM_ASSERT(!uvm_mem_mapped_on_gpu_user(mem, gpu)); - uvm_global_processor_mask_set(&mem->user->mapped_on, gpu->global_id); + uvm_processor_mask_set(&mem->user->mapped_on, gpu->id); } static void mem_set_mapped_on_gpu_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) @@ -161,7 +162,7 @@ static void mem_set_mapped_on_gpu_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) UVM_ASSERT(mem_can_be_mapped_on_gpu_kernel(mem, gpu)); UVM_ASSERT(!uvm_mem_mapped_on_gpu_kernel(mem, gpu)); - uvm_global_processor_mask_set(&mem->kernel.mapped_on, gpu->global_id); + uvm_processor_mask_set(&mem->kernel.mapped_on, gpu->id); } static void mem_set_mapped_on_cpu_user(uvm_mem_t *mem) @@ -170,7 +171,7 @@ static void mem_set_mapped_on_cpu_user(uvm_mem_t *mem) UVM_ASSERT(mem_can_be_mapped_on_cpu_user(mem)); UVM_ASSERT(!uvm_mem_mapped_on_cpu_user(mem)); - uvm_global_processor_mask_set(&mem->user->mapped_on, UVM_GLOBAL_ID_CPU); + uvm_processor_mask_set(&mem->user->mapped_on, UVM_ID_CPU); } static void mem_set_mapped_on_cpu_kernel(uvm_mem_t *mem) @@ -178,38 +179,38 @@ static void mem_set_mapped_on_cpu_kernel(uvm_mem_t *mem) UVM_ASSERT(mem_can_be_mapped_on_cpu_kernel(mem)); UVM_ASSERT(!uvm_mem_mapped_on_cpu_kernel(mem)); - uvm_global_processor_mask_set(&mem->kernel.mapped_on, UVM_GLOBAL_ID_CPU); + uvm_processor_mask_set(&mem->kernel.mapped_on, UVM_ID_CPU); } static void mem_clear_mapped_on_gpu_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) { - uvm_global_processor_mask_clear(&mem->kernel.mapped_on, gpu->global_id); + uvm_processor_mask_clear(&mem->kernel.mapped_on, gpu->id); } static void mem_clear_mapped_on_gpu_user(uvm_mem_t *mem, uvm_gpu_t *gpu) { UVM_ASSERT(mem->user != NULL); - uvm_global_processor_mask_clear(&mem->user->mapped_on, gpu->global_id); + uvm_processor_mask_clear(&mem->user->mapped_on, gpu->id); } static void mem_clear_mapped_on_cpu_user(uvm_mem_t *mem) { UVM_ASSERT(mem->user != NULL); - uvm_global_processor_mask_clear(&mem->user->mapped_on, UVM_GLOBAL_ID_CPU); + uvm_processor_mask_clear(&mem->user->mapped_on, UVM_ID_CPU); } static void mem_clear_mapped_on_cpu_kernel(uvm_mem_t *mem) { - uvm_global_processor_mask_clear(&mem->kernel.mapped_on, UVM_GLOBAL_ID_CPU); + uvm_processor_mask_clear(&mem->kernel.mapped_on, UVM_ID_CPU); } static bool sysmem_mapped_on_gpu_phys(uvm_mem_t *sysmem, uvm_gpu_t *gpu) { UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); - return uvm_global_processor_mask_test(&sysmem->sysmem.mapped_on_phys, gpu->global_id); + return uvm_processor_mask_test(&sysmem->sysmem.mapped_on_phys, gpu->id); } static void sysmem_set_mapped_on_gpu_phys(uvm_mem_t *sysmem, uvm_gpu_t *gpu) @@ -217,14 +218,14 @@ static void sysmem_set_mapped_on_gpu_phys(uvm_mem_t *sysmem, uvm_gpu_t *gpu) UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); UVM_ASSERT(!sysmem_mapped_on_gpu_phys(sysmem, gpu)); - uvm_global_processor_mask_set(&sysmem->sysmem.mapped_on_phys, gpu->global_id); + uvm_processor_mask_set(&sysmem->sysmem.mapped_on_phys, gpu->id); } static void sysmem_clear_mapped_on_gpu_phys(uvm_mem_t *sysmem, uvm_gpu_t *gpu) { UVM_ASSERT(uvm_mem_is_sysmem(sysmem)); - uvm_global_processor_mask_clear(&sysmem->sysmem.mapped_on_phys, gpu->global_id); + uvm_processor_mask_clear(&sysmem->sysmem.mapped_on_phys, gpu->id); } NV_STATUS uvm_mem_translate_gpu_attributes(const UvmGpuMappingAttributes *attrs, @@ -365,7 +366,7 @@ static void mem_free_sysmem_dma_chunks(uvm_mem_t *mem) NvU32 gpu_index; UVM_ASSERT(uvm_mem_is_sysmem_dma(mem)); - gpu_index = uvm_global_id_gpu_index(mem->dma_owner->global_id); + gpu_index = uvm_id_gpu_index(mem->dma_owner->id); if (!mem->sysmem.pages || !mem->sysmem.va) goto end; @@ -374,9 +375,9 @@ static void mem_free_sysmem_dma_chunks(uvm_mem_t *mem) if (!mem->sysmem.va[i]) break; - uvm_gpu_dma_free_page(mem->dma_owner->parent, - mem->sysmem.va[i], - mem->sysmem.dma_addrs[gpu_index][i]); + uvm_parent_gpu_dma_free_page(mem->dma_owner->parent, + mem->sysmem.va[i], + mem->sysmem.dma_addrs[gpu_index][i]); } end: @@ -424,7 +425,7 @@ static void mem_free_chunks(uvm_mem_t *mem) static NV_STATUS mem_alloc_dma_addrs(uvm_mem_t *mem, const uvm_gpu_t *gpu) { NvU64 *dma_addrs = NULL; - NvU32 gpu_index = uvm_global_id_gpu_index(gpu->global_id); + NvU32 gpu_index = uvm_id_gpu_index(gpu->id); dma_addrs = uvm_kvmalloc_zero(sizeof(*dma_addrs) * mem->chunks_count); if (!dma_addrs) @@ -479,10 +480,10 @@ static NV_STATUS mem_alloc_sysmem_dma_chunks(uvm_mem_t *mem, gfp_t gfp_flags) if (status != NV_OK) goto error; - dma_addrs = mem->sysmem.dma_addrs[uvm_global_id_gpu_index(mem->dma_owner->global_id)]; + dma_addrs = mem->sysmem.dma_addrs[uvm_id_gpu_index(mem->dma_owner->id)]; for (i = 0; i < mem->chunks_count; ++i) { - mem->sysmem.va[i] = uvm_gpu_dma_alloc_page(mem->dma_owner->parent, gfp_flags, &dma_addrs[i]); + mem->sysmem.va[i] = uvm_parent_gpu_dma_alloc_page(mem->dma_owner->parent, gfp_flags, &dma_addrs[i]); if (!mem->sysmem.va[i]) goto err_no_mem; @@ -598,7 +599,7 @@ static NV_STATUS mem_alloc_chunks(uvm_mem_t *mem, struct mm_struct *mm, bool zer return mem_alloc_vidmem_chunks(mem, zero, is_unprotected); } -NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_global_processor_mask_t *mask) +NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_processor_mask_t *mask) { uvm_gpu_t *gpu; NV_STATUS status; @@ -606,13 +607,13 @@ NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_global_processor_mask_t * if (!mask) return NV_OK; - if (uvm_global_processor_mask_test(mask, UVM_GLOBAL_ID_CPU)) { + if (uvm_processor_mask_test(mask, UVM_ID_CPU)) { status = uvm_mem_map_cpu_kernel(mem); if (status != NV_OK) return status; } - for_each_global_gpu_in_mask(gpu, mask) { + for_each_gpu_in_mask(gpu, mask) { status = uvm_mem_map_gpu_kernel(mem, gpu); if (status != NV_OK) return status; @@ -694,7 +695,7 @@ static void mem_deinit_user_mapping(uvm_mem_t *mem) if (mem->user == NULL) return; - if (!uvm_global_processor_mask_empty(&mem->user->mapped_on)) + if (!uvm_processor_mask_empty(&mem->user->mapped_on)) return; uvm_kvfree(mem->user); @@ -737,7 +738,7 @@ static NV_STATUS mem_map_cpu_to_sysmem_kernel(uvm_mem_t *mem) pages[page_index] = mem_cpu_page(mem, page_index * PAGE_SIZE); } - if (g_uvm_global.sev_enabled && uvm_mem_is_sysmem_dma(mem)) + if (g_uvm_global.conf_computing_enabled && uvm_mem_is_sysmem_dma(mem)) prot = uvm_pgprot_decrypted(PAGE_KERNEL_NOENC); mem->kernel.cpu_addr = vmap(pages, num_pages, VM_MAP, prot); @@ -893,7 +894,7 @@ NV_STATUS uvm_mem_map_cpu_kernel(uvm_mem_t *mem) static void sysmem_unmap_gpu_phys(uvm_mem_t *mem, uvm_gpu_t *gpu) { - NvU64 *dma_addrs = mem->sysmem.dma_addrs[uvm_global_id_gpu_index(gpu->global_id)]; + NvU64 *dma_addrs = mem->sysmem.dma_addrs[uvm_id_gpu_index(gpu->id)]; NvU32 i; UVM_ASSERT(uvm_mem_is_sysmem(mem)); @@ -906,12 +907,12 @@ static void sysmem_unmap_gpu_phys(uvm_mem_t *mem, uvm_gpu_t *gpu) // partial map_gpu_sysmem_iommu() operation. break; } - uvm_gpu_unmap_cpu_pages(gpu->parent, dma_addrs[i], mem->chunk_size); + uvm_parent_gpu_unmap_cpu_pages(gpu->parent, dma_addrs[i], mem->chunk_size); dma_addrs[i] = 0; } uvm_kvfree(dma_addrs); - mem->sysmem.dma_addrs[uvm_global_id_gpu_index(gpu->global_id)] = NULL; + mem->sysmem.dma_addrs[uvm_id_gpu_index(gpu->id)] = NULL; } static NV_STATUS sysmem_map_gpu_phys(uvm_mem_t *mem, uvm_gpu_t *gpu) @@ -927,10 +928,10 @@ static NV_STATUS sysmem_map_gpu_phys(uvm_mem_t *mem, uvm_gpu_t *gpu) return status; for (i = 0; i < mem->chunks_count; ++i) { - status = uvm_gpu_map_cpu_pages(gpu->parent, - mem->sysmem.pages[i], - mem->chunk_size, - &mem->sysmem.dma_addrs[uvm_global_id_gpu_index(gpu->global_id)][i]); + status = uvm_parent_gpu_map_cpu_pages(gpu->parent, + mem->sysmem.pages[i], + mem->chunk_size, + &mem->sysmem.dma_addrs[uvm_id_gpu_index(gpu->id)][i]); if (status != NV_OK) goto error; } @@ -962,7 +963,7 @@ static uvm_gpu_phys_address_t mem_gpu_physical_vidmem(uvm_mem_t *mem, size_t off static uvm_gpu_phys_address_t mem_gpu_physical_sysmem(uvm_mem_t *mem, uvm_gpu_t *gpu, size_t offset) { - NvU64 *dma_addrs = mem->sysmem.dma_addrs[uvm_global_id_gpu_index(gpu->global_id)]; + NvU64 *dma_addrs = mem->sysmem.dma_addrs[uvm_id_gpu_index(gpu->id)]; NvU64 dma_addr = dma_addrs[offset / mem->chunk_size]; UVM_ASSERT(uvm_mem_is_sysmem(mem)); @@ -1120,7 +1121,7 @@ static void mem_deinit_gpu_kernel_range(uvm_mem_t *mem) // Do not remove the range allocation if there is any GPU where the memory // is still mapped on kernel space. - if (UVM_GLOBAL_ID_IS_VALID(uvm_global_processor_mask_find_first_gpu_id(&mem->kernel.mapped_on))) + if (UVM_ID_IS_VALID(uvm_processor_mask_find_first_gpu_id(&mem->kernel.mapped_on))) return; uvm_range_allocator_free(&g_free_ranges, &mem->kernel.range_alloc); @@ -1150,7 +1151,7 @@ NV_STATUS uvm_mem_map_gpu_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) return status; gpu_va = reserved_gpu_va(mem, gpu); - range_vec = &mem->kernel.range_vecs[uvm_global_id_gpu_index(gpu->global_id)]; + range_vec = &mem->kernel.range_vecs[uvm_id_gpu_index(gpu->id)]; status = mem_map_gpu(mem, gpu, gpu_va, &gpu->address_space_tree, &attrs, range_vec); if (status != NV_OK) @@ -1196,7 +1197,7 @@ NV_STATUS uvm_mem_map_gpu_user(uvm_mem_t *mem, return status; gpu_va_space = uvm_gpu_va_space_get(mem->user->va_space, gpu); - range_vec = &mem->user->range_vecs[uvm_global_id_gpu_index(gpu->global_id)]; + range_vec = &mem->user->range_vecs[uvm_id_gpu_index(gpu->id)]; status = mem_map_gpu(mem, gpu, gpu_va, &gpu_va_space->page_tables, attrs, range_vec); if (status != NV_OK) @@ -1216,7 +1217,7 @@ void uvm_mem_unmap_gpu_user(uvm_mem_t *mem, uvm_gpu_t *gpu) if (!uvm_mem_mapped_on_gpu_user(mem, gpu)) return; - mem_unmap_gpu(mem, gpu, &mem->user->range_vecs[uvm_global_id_gpu_index(gpu->global_id)]); + mem_unmap_gpu(mem, gpu, &mem->user->range_vecs[uvm_id_gpu_index(gpu->id)]); mem_clear_mapped_on_gpu_user(mem, gpu); mem_deinit_user_mapping(mem); } @@ -1226,7 +1227,7 @@ void uvm_mem_unmap_gpu_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) if (!uvm_mem_mapped_on_gpu_kernel(mem, gpu)) return; - mem_unmap_gpu(mem, gpu, &mem->kernel.range_vecs[uvm_global_id_gpu_index(gpu->global_id)]); + mem_unmap_gpu(mem, gpu, &mem->kernel.range_vecs[uvm_id_gpu_index(gpu->id)]); mem_clear_mapped_on_gpu_kernel(mem, gpu); mem_deinit_gpu_kernel_range(mem); } @@ -1296,7 +1297,7 @@ void uvm_mem_free(uvm_mem_t *mem) uvm_mem_unmap_cpu_kernel(mem); if (mem->user != NULL) { - for_each_global_gpu_in_mask(gpu, &mem->user->mapped_on) { + for_each_gpu_in_mask(gpu, &mem->user->mapped_on) { uvm_mem_unmap_gpu_user(mem, gpu); // If we unmapped the last device, the user mapping is freed, so @@ -1306,11 +1307,11 @@ void uvm_mem_free(uvm_mem_t *mem) } } - for_each_global_gpu_in_mask(gpu, &mem->kernel.mapped_on) + for_each_gpu_in_mask(gpu, &mem->kernel.mapped_on) uvm_mem_unmap_gpu_kernel(mem, gpu); if (uvm_mem_is_sysmem(mem)) { - for_each_global_gpu_in_mask(gpu, &mem->sysmem.mapped_on_phys) + for_each_gpu_in_mask(gpu, &mem->sysmem.mapped_on_phys) uvm_mem_unmap_gpu_phys(mem, gpu); } @@ -1336,15 +1337,19 @@ NvU64 uvm_mem_get_gpu_va_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) uvm_gpu_address_t uvm_mem_gpu_address_virtual_kernel(uvm_mem_t *mem, uvm_gpu_t *gpu) { uvm_gpu_address_t addr = uvm_gpu_address_virtual(uvm_mem_get_gpu_va_kernel(mem, gpu)); - if (uvm_conf_computing_mode_enabled(gpu) && mem->dma_owner) + + if (g_uvm_global.conf_computing_enabled && mem->dma_owner) addr.is_unprotected = true; + return addr; } uvm_gpu_address_t uvm_mem_gpu_address_physical(uvm_mem_t *mem, uvm_gpu_t *gpu, NvU64 offset, NvU64 size) { uvm_gpu_address_t addr = uvm_gpu_address_from_phys(uvm_mem_gpu_physical(mem, gpu, offset, size)); - if (uvm_conf_computing_mode_enabled(gpu) && mem->dma_owner) + + if (g_uvm_global.conf_computing_enabled && mem->dma_owner) addr.is_unprotected = true; + return addr; } diff --git a/kernel-open/nvidia-uvm/uvm_mem.h b/kernel-open/nvidia-uvm/uvm_mem.h index ec55435e90..65e37ef811 100644 --- a/kernel-open/nvidia-uvm/uvm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_mem.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2020 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -147,10 +147,10 @@ typedef struct typedef struct { // Mask of processors the memory is virtually mapped on - uvm_global_processor_mask_t mapped_on; + uvm_processor_mask_t mapped_on; // Page table ranges for all GPUs - uvm_page_table_range_vec_t *range_vecs[UVM_GLOBAL_ID_MAX_GPUS]; + uvm_page_table_range_vec_t *range_vecs[UVM_ID_MAX_GPUS]; uvm_va_space_t *va_space; @@ -185,13 +185,13 @@ struct uvm_mem_struct // GPU can physical access the memory // // TODO: Bug 3723779: Share DMA mappings within a single parent GPU - uvm_global_processor_mask_t mapped_on_phys; + uvm_processor_mask_t mapped_on_phys; struct page **pages; void **va; // Per GPU IOMMU mappings of the pages - NvU64 *dma_addrs[UVM_GLOBAL_ID_MAX_GPUS]; + NvU64 *dma_addrs[UVM_ID_MAX_GPUS]; } sysmem; }; @@ -210,10 +210,10 @@ struct uvm_mem_struct struct { // Mask of processors the memory is virtually mapped on - uvm_global_processor_mask_t mapped_on; + uvm_processor_mask_t mapped_on; // Page table ranges for all GPUs - uvm_page_table_range_vec_t *range_vecs[UVM_GLOBAL_ID_MAX_GPUS]; + uvm_page_table_range_vec_t *range_vecs[UVM_ID_MAX_GPUS]; // Range allocation for the GPU VA uvm_range_allocation_t range_alloc; @@ -441,6 +441,6 @@ static NV_STATUS uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(NvU64 size, } // Helper to map an allocation on the specified processors in the UVM VA space. -NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_global_processor_mask_t *mask); +NV_STATUS uvm_mem_map_kernel(uvm_mem_t *mem, const uvm_processor_mask_t *mask); #endif // __UVM_MEM_H__ diff --git a/kernel-open/nvidia-uvm/uvm_mem_test.c b/kernel-open/nvidia-uvm/uvm_mem_test.c index 0c7fd7a1eb..0c3d6d2894 100644 --- a/kernel-open/nvidia-uvm/uvm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_mem_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -21,6 +21,7 @@ *******************************************************************************/ #include "uvm_hal.h" +#include "uvm_global.h" #include "uvm_gpu.h" #include "uvm_kvmalloc.h" #include "uvm_mem.h" @@ -44,10 +45,10 @@ static NvU32 first_page_size(NvU32 page_sizes) static inline NV_STATUS __alloc_map_sysmem(NvU64 size, uvm_gpu_t *gpu, uvm_mem_t **sys_mem) { - if (g_uvm_global.sev_enabled) + if (g_uvm_global.conf_computing_enabled) return uvm_mem_alloc_sysmem_dma_and_map_cpu_kernel(size, gpu, current->mm, sys_mem); - else - return uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, sys_mem); + + return uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, sys_mem); } static NV_STATUS check_accessible_from_gpu(uvm_gpu_t *gpu, uvm_mem_t *mem) @@ -335,9 +336,6 @@ static NV_STATUS test_alloc_vidmem(uvm_gpu_t *gpu, NvU32 page_size, size_t size, static bool should_test_page_size(size_t alloc_size, NvU32 page_size) { - if (g_uvm_global.sev_enabled) - return false; - if (g_uvm_global.num_simulated_devices == 0) return true; @@ -371,7 +369,7 @@ static NV_STATUS test_all(uvm_va_space_t *va_space) // TODO: Bug 3839176: the test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(uvm_va_space_find_first_gpu(va_space))) + if (g_uvm_global.conf_computing_enabled) return NV_OK; gpu_count = uvm_processor_mask_get_gpu_count(&va_space->registered_gpus); @@ -522,7 +520,7 @@ static NV_STATUS test_basic_vidmem_unprotected(uvm_gpu_t *gpu) // If CC is disabled, the behavior should be identical to that of a // protected allocation. params.is_unprotected = true; - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) TEST_CHECK_RET(uvm_mem_alloc(¶ms, &mem) == NV_ERR_NO_MEMORY); else TEST_NV_CHECK_RET(uvm_mem_alloc(¶ms, &mem)); @@ -578,7 +576,7 @@ static NV_STATUS test_basic_dma_pool(uvm_gpu_t *gpu) // If the Confidential Computing feature is disabled, the DMA buffers // pool is not initialized. - if (!uvm_conf_computing_mode_enabled(gpu)) + if (!g_uvm_global.conf_computing_enabled) return NV_OK; // We're going to reclaim one more chunks that the pool have. Triggerring diff --git a/kernel-open/nvidia-uvm/uvm_migrate.c b/kernel-open/nvidia-uvm/uvm_migrate.c index 1be4b1ddfa..f955dd8ea5 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate.c +++ b/kernel-open/nvidia-uvm/uvm_migrate.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,6 +33,7 @@ #include "uvm_tracker.h" #include "uvm_api.h" #include "uvm_channel.h" +#include "uvm_processors.h" #include "uvm_push.h" #include "uvm_hal.h" #include "uvm_tools.h" @@ -565,6 +566,8 @@ static NV_STATUS uvm_migrate_ranges(uvm_va_space_t *va_space, va_range_last = NULL; uvm_for_each_va_range_in_contig_from(va_range, va_space, first_va_range, end) { uvm_range_group_range_iter_t iter; + uvm_va_policy_t *policy = uvm_va_range_get_policy(va_range); + va_range_last = va_range; // Only managed ranges can be migrated @@ -584,11 +587,11 @@ static NV_STATUS uvm_migrate_ranges(uvm_va_space_t *va_space, if (!iter.migratable) { // Only return NV_WARN_MORE_PROCESSING_REQUIRED if the pages aren't // already resident at dest_id. - if (!uvm_id_equal(uvm_va_range_get_policy(va_range)->preferred_location, dest_id)) + if (!uvm_va_policy_preferred_location_equal(policy, dest_id, va_block_context->make_resident.dest_nid)) skipped_migrate = true; } else if (uvm_processor_mask_test(&va_range->uvm_lite_gpus, dest_id) && - !uvm_id_equal(dest_id, uvm_va_range_get_policy(va_range)->preferred_location)) { + !uvm_id_equal(dest_id, policy->preferred_location)) { // Don't migrate to a non-faultable GPU that is in UVM-Lite mode, // unless it's the preferred location status = NV_ERR_INVALID_DEVICE; @@ -627,6 +630,7 @@ static NV_STATUS uvm_migrate(uvm_va_space_t *va_space, NvU64 base, NvU64 length, uvm_processor_id_t dest_id, + int dest_nid, NvU32 migrate_flags, uvm_va_range_t *first_va_range, uvm_tracker_t *out_tracker) @@ -654,6 +658,8 @@ static NV_STATUS uvm_migrate(uvm_va_space_t *va_space, if (!va_block_context) return NV_ERR_NO_MEMORY; + va_block_context->make_resident.dest_nid = dest_nid; + // We perform two passes (unless the migration only covers a single VA // block or UVM_MIGRATE_FLAG_SKIP_CPU_MAP is passed). This helps in the // following scenarios: @@ -742,7 +748,7 @@ static NV_STATUS semaphore_release_from_gpu(uvm_gpu_t *gpu, // In SR-IOV heavy, the user semaphore release is functionally forbidden // from being pushed to a UVM_CHANNEL_TYPE_MEMOPS channel, because it is not // a page tree operation. - if (uvm_gpu_is_virt_mode_sriov_heavy(gpu)) + if (uvm_parent_gpu_is_virt_mode_sriov_heavy(gpu->parent)) channel_type = UVM_CHANNEL_TYPE_GPU_INTERNAL; else channel_type = UVM_CHANNEL_TYPE_MEMOPS; @@ -820,7 +826,7 @@ static NV_STATUS semaphore_release(NvU64 semaphore_address, // // Note that the GPU selected for the release may not be the same device // that prevented the tracker from being complete. - gpu = uvm_global_processor_mask_find_first_gpu(&semaphore_pool->mem->kernel.mapped_on); + gpu = uvm_processor_mask_find_first_gpu(&semaphore_pool->mem->kernel.mapped_on); UVM_ASSERT(gpu != NULL); } @@ -873,6 +879,7 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) NV_STATUS status = NV_OK; bool flush_events = false; const bool synchronous = !(params->flags & UVM_MIGRATE_FLAG_ASYNC); + int cpu_numa_node = (int)params->cpuNumaNode; // We temporarily allow 0 length in the IOCTL parameters as a signal to // only release the semaphore. This is because user-space is in charge of @@ -937,6 +944,24 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) goto done; } } + else { + // If cpu_numa_node is not -1, we only check that it is a valid node in + // the system, it has memory, and it doesn't correspond to a GPU node. + // + // For pageable memory, this is fine because alloc_pages_node will clamp + // the allocation to cpuset_current_mems_allowed when uvm_migrate + //_pageable is called from process context (uvm_migrate) when dst_id is + // CPU. UVM bottom half calls uvm_migrate_pageable with CPU dst_id only + // when the VMA memory policy is set to dst_node_id and dst_node_id is + // not NUMA_NO_NODE. + if (cpu_numa_node != -1 && + (!nv_numa_node_has_memory(cpu_numa_node) || + !node_isset(cpu_numa_node, node_possible_map) || + uvm_va_space_find_gpu_with_memory_node_id(va_space, cpu_numa_node))) { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + } UVM_ASSERT(status == NV_OK); @@ -946,6 +971,7 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) if (params->length > 0) { uvm_api_range_type_t type; + uvm_processor_id_t dest_id = dest_gpu ? dest_gpu->id : UVM_ID_CPU; type = uvm_api_range_type_check(va_space, mm, params->base, params->length); if (type == UVM_API_RANGE_TYPE_INVALID) { @@ -960,8 +986,8 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) .mm = mm, .start = params->base, .length = params->length, - .dst_id = (dest_gpu ? dest_gpu->id : UVM_ID_CPU), - .dst_node_id = (int)params->cpuNumaNode, + .dst_id = dest_id, + .dst_node_id = cpu_numa_node, .populate_permissions = UVM_POPULATE_PERMISSIONS_INHERIT, .touch = false, .skip_mapped = false, @@ -977,11 +1003,10 @@ NV_STATUS uvm_api_migrate(UVM_MIGRATE_PARAMS *params, struct file *filp) mm, params->base, params->length, - (dest_gpu ? dest_gpu->id : UVM_ID_CPU), + dest_id, + (UVM_ID_IS_CPU(dest_id) ? cpu_numa_node : NUMA_NO_NODE), params->flags, - uvm_va_space_iter_first(va_space, - params->base, - params->base), + uvm_va_space_iter_first(va_space, params->base, params->base), tracker_ptr); } } @@ -1093,6 +1118,7 @@ NV_STATUS uvm_api_migrate_range_group(UVM_MIGRATE_RANGE_GROUP_PARAMS *params, st start, length, dest_id, + NUMA_NO_NODE, migrate_flags, first_va_range, &local_tracker); diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c index e16053755c..ddeb76f3e8 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.c +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2022 NVIDIA Corporation + Copyright (c) 2018-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -74,7 +74,7 @@ static NV_STATUS migrate_vma_page_copy_address(struct page *page, } else { // Sysmem/Indirect Peer - NV_STATUS status = uvm_gpu_map_cpu_page(copying_gpu->parent, page, &state->dma.addrs[page_index]); + NV_STATUS status = uvm_parent_gpu_map_cpu_page(copying_gpu->parent, page, &state->dma.addrs[page_index]); if (status != NV_OK) return status; @@ -636,7 +636,7 @@ void uvm_migrate_vma_finalize_and_map(struct migrate_vma *args, migrate_vma_stat if (state->dma.num_pages > 0) { for_each_set_bit(i, state->dma.page_mask, state->num_pages) - uvm_gpu_unmap_cpu_page(state->dma.addrs_gpus[i]->parent, state->dma.addrs[i]); + uvm_parent_gpu_unmap_cpu_page(state->dma.addrs_gpus[i]->parent, state->dma.addrs[i]); } UVM_ASSERT(!bitmap_intersects(state->populate_pages_mask, state->allocation_failed_mask, state->num_pages)); @@ -836,6 +836,17 @@ static NV_STATUS migrate_pageable_vma_region(struct vm_area_struct *vma, return NV_OK; } +NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + uvm_va_space_down_write(va_space); + va_space->test.skip_migrate_vma = params->skip; + uvm_va_space_up_write(va_space); + + return NV_OK; +} + static NV_STATUS migrate_pageable_vma(struct vm_area_struct *vma, unsigned long start, unsigned long outer, @@ -858,6 +869,9 @@ static NV_STATUS migrate_pageable_vma(struct vm_area_struct *vma, start = max(start, vma->vm_start); outer = min(outer, vma->vm_end); + if (va_space->test.skip_migrate_vma) + return NV_WARN_NOTHING_TO_DO; + // TODO: Bug 2419180: support file-backed pages in migrate_vma, when // support for it is added to the Linux kernel if (!vma_is_anonymous(vma)) @@ -920,7 +934,9 @@ static NV_STATUS migrate_pageable(migrate_vma_state_t *state) bool touch = uvm_migrate_args->touch; uvm_populate_permissions_t populate_permissions = uvm_migrate_args->populate_permissions; - UVM_ASSERT(!vma_is_anonymous(vma) || uvm_processor_mask_empty(&va_space->registered_gpus)); + UVM_ASSERT(va_space->test.skip_migrate_vma || + !vma_is_anonymous(vma) || + uvm_processor_mask_empty(&va_space->registered_gpus)); // We can't use migrate_vma to move the pages as desired. Normally // this fallback path is supposed to populate the memory then inform @@ -971,22 +987,13 @@ NV_STATUS uvm_migrate_pageable(uvm_migrate_args_t *uvm_migrate_args) NV_STATUS status; uvm_va_space_t *va_space = uvm_migrate_args->va_space; uvm_processor_id_t dst_id = uvm_migrate_args->dst_id; - int dst_node_id = uvm_migrate_args->dst_node_id; UVM_ASSERT(PAGE_ALIGNED(uvm_migrate_args->start)); UVM_ASSERT(PAGE_ALIGNED(uvm_migrate_args->length)); uvm_assert_mmap_lock_locked(uvm_migrate_args->mm); if (UVM_ID_IS_CPU(dst_id)) { - // We only check that dst_node_id is a valid node in the system and it - // doesn't correspond to a GPU node. This is fine because - // alloc_pages_node will clamp the allocation to - // cpuset_current_mems_allowed when uvm_migrate_pageable is called from - // process context (uvm_migrate) when dst_id is CPU. UVM bottom half - // calls uvm_migrate_pageable with CPU dst_id only when the VMA memory - // policy is set to dst_node_id and dst_node_id is not NUMA_NO_NODE. - if (!nv_numa_node_has_memory(dst_node_id) || - uvm_va_space_find_gpu_with_memory_node_id(va_space, dst_node_id) != NULL) + if (uvm_migrate_args->dst_node_id == -1) return NV_ERR_INVALID_ARGUMENT; } else { diff --git a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h index 41c01b2375..85956de46f 100644 --- a/kernel-open/nvidia-uvm/uvm_migrate_pageable.h +++ b/kernel-open/nvidia-uvm/uvm_migrate_pageable.h @@ -51,7 +51,7 @@ typedef struct #if defined(CONFIG_MIGRATE_VMA_HELPER) #define UVM_MIGRATE_VMA_SUPPORTED 1 #else -#if defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MIGRATE_VMA_SETUP_PRESENT) +#if NV_IS_EXPORT_SYMBOL_PRESENT_migrate_vma_setup #define UVM_MIGRATE_VMA_SUPPORTED 1 #endif #endif @@ -218,6 +218,9 @@ NV_STATUS uvm_migrate_pageable(uvm_migrate_args_t *uvm_migrate_args); NV_STATUS uvm_migrate_pageable_init(void); void uvm_migrate_pageable_exit(void); + +NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp); + #else // UVM_MIGRATE_VMA_SUPPORTED static NV_STATUS uvm_migrate_pageable(uvm_migrate_args_t *uvm_migrate_args) @@ -251,6 +254,10 @@ static void uvm_migrate_pageable_exit(void) { } +static inline NV_STATUS uvm_test_skip_migrate_vma(UVM_TEST_SKIP_MIGRATE_VMA_PARAMS *params, struct file *filp) +{ + return NV_OK; +} #endif // UVM_MIGRATE_VMA_SUPPORTED #endif diff --git a/kernel-open/nvidia-uvm/uvm_mmu.c b/kernel-open/nvidia-uvm/uvm_mmu.c index e3d5e1b425..78fdb21972 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_mmu.c @@ -24,6 +24,7 @@ #include "uvm_common.h" #include "uvm_types.h" #include "uvm_forward_decl.h" +#include "uvm_global.h" #include "uvm_gpu.h" #include "uvm_mmu.h" #include "uvm_hal.h" @@ -55,7 +56,7 @@ \ if (manager == NULL) \ status = uvm_push_begin_fake((tree)->gpu, (push)); \ - else if (uvm_gpu_is_virt_mode_sriov_heavy((tree)->gpu)) \ + else if (uvm_parent_gpu_is_virt_mode_sriov_heavy((tree)->gpu->parent)) \ status = uvm_push_begin_acquire(manager, UVM_CHANNEL_TYPE_MEMOPS, (tracker), (push), (format), ##__VA_ARGS__); \ else \ status = uvm_push_begin_acquire(manager, UVM_CHANNEL_TYPE_GPU_INTERNAL, (tracker), (push), (format), ##__VA_ARGS__);\ @@ -133,7 +134,7 @@ static NV_STATUS phys_mem_allocate_sysmem(uvm_page_tree_t *tree, NvLength size, // Check for fake GPUs from the unit test if (tree->gpu->parent->pci_dev) - status = uvm_gpu_map_cpu_pages(tree->gpu->parent, out->handle.page, UVM_PAGE_ALIGN_UP(size), &dma_addr); + status = uvm_parent_gpu_map_cpu_pages(tree->gpu->parent, out->handle.page, UVM_PAGE_ALIGN_UP(size), &dma_addr); else dma_addr = page_to_phys(out->handle.page); @@ -218,7 +219,7 @@ static void phys_mem_deallocate_sysmem(uvm_page_tree_t *tree, uvm_mmu_page_table UVM_ASSERT(ptr->addr.aperture == UVM_APERTURE_SYS); if (tree->gpu->parent->pci_dev) - uvm_gpu_unmap_cpu_pages(tree->gpu->parent, ptr->addr.address, UVM_PAGE_ALIGN_UP(ptr->size)); + uvm_parent_gpu_unmap_cpu_pages(tree->gpu->parent, ptr->addr.address, UVM_PAGE_ALIGN_UP(ptr->size)); __free_pages(ptr->handle.page, get_order(ptr->size)); } @@ -323,37 +324,156 @@ static void uvm_mmu_page_table_cpu_memset_16(uvm_gpu_t *gpu, uvm_mmu_page_table_cpu_unmap(gpu, phys_alloc); } -static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_directory_t *dir, uvm_push_t *push) +static void pde_fill_cpu(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr) { - NvU64 clear_bits[2]; - uvm_mmu_mode_hal_t *hal = tree->hal; + NvU64 pde_data[2], entry_size; + NvU32 i; + + UVM_ASSERT(uvm_mmu_use_cpu(tree)); + + entry_size = tree->hal->entry_size(directory->depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + for (i = 0; i < pde_count; i++) { + tree->hal->make_pde(pde_data, phys_addr, directory, start_index + i); - if (dir->depth == tree->hal->page_table_depth(page_size)) { - *clear_bits = 0; // Invalid PTE + if (entry_size == sizeof(pde_data[0])) + uvm_mmu_page_table_cpu_memset_8(tree->gpu, &directory->phys_alloc, start_index + i, pde_data[0], 1); + else + uvm_mmu_page_table_cpu_memset_16(tree->gpu, &directory->phys_alloc, start_index + i, pde_data, 1); } - else { - // passing in NULL for the phys_allocs will mark the child entries as invalid - uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; - hal->make_pde(clear_bits, phys_allocs, dir->depth); +} - // Make sure that using only clear_bits[0] will work - UVM_ASSERT(hal->entry_size(dir->depth) == sizeof(clear_bits[0]) || clear_bits[0] == clear_bits[1]); +static void pde_fill_gpu(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + NvU64 pde_data[2], entry_size; + uvm_gpu_address_t pde_entry_addr = uvm_mmu_gpu_address(tree->gpu, directory->phys_alloc.addr); + NvU32 max_inline_entries; + uvm_push_flag_t push_membar_flag = UVM_PUSH_FLAG_COUNT; + uvm_gpu_address_t inline_data_addr; + uvm_push_inline_data_t inline_data; + NvU32 entry_count, i, j; + + UVM_ASSERT(!uvm_mmu_use_cpu(tree)); + + entry_size = tree->hal->entry_size(directory->depth); + UVM_ASSERT(sizeof(pde_data) >= entry_size); + + max_inline_entries = UVM_PUSH_INLINE_DATA_MAX_SIZE / entry_size; + + if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; + else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) + push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; + + pde_entry_addr.address += start_index * entry_size; + + for (i = 0; i < pde_count;) { + // All but the first memory operation can be pipelined. We respect the + // caller's pipelining settings for the first push. + if (i != 0) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + + entry_count = min(pde_count - i, max_inline_entries); + + // No membar is needed until the last memory operation. Otherwise, + // use caller's membar flag. + if ((i + entry_count) < pde_count) + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); + else if (push_membar_flag != UVM_PUSH_FLAG_COUNT) + uvm_push_set_flag(push, push_membar_flag); + + uvm_push_inline_data_begin(push, &inline_data); + for (j = 0; j < entry_count; j++) { + tree->hal->make_pde(pde_data, phys_addr, directory, start_index + i + j); + uvm_push_inline_data_add(&inline_data, pde_data, entry_size); + } + inline_data_addr = uvm_push_inline_data_end(&inline_data); + + tree->gpu->parent->ce_hal->memcopy(push, pde_entry_addr, inline_data_addr, entry_count * entry_size); + + i += entry_count; + pde_entry_addr.address += entry_size * entry_count; } +} - // initialize the memory to a reasonable value - if (push) { - tree->gpu->parent->ce_hal->memset_8(push, - uvm_mmu_gpu_address(tree->gpu, dir->phys_alloc.addr), +// pde_fill() populates pde_count PDE entries (starting at start_index) with +// the same mapping, i.e., with the same physical address (phys_addr). +// pde_fill() is optimized for pde_count == 1, which is the common case. +static void pde_fill(uvm_page_tree_t *tree, + uvm_page_directory_t *directory, + NvU32 start_index, + NvU32 pde_count, + uvm_mmu_page_table_alloc_t **phys_addr, + uvm_push_t *push) +{ + UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, directory->depth, UVM_PAGE_SIZE_AGNOSTIC)); + + if (push) + pde_fill_gpu(tree, directory, start_index, pde_count, phys_addr, push); + else + pde_fill_cpu(tree, directory, start_index, pde_count, phys_addr); +} + +static void phys_mem_init(uvm_page_tree_t *tree, NvU32 page_size, uvm_page_directory_t *dir, uvm_push_t *push) +{ + NvU32 entries_count = uvm_mmu_page_tree_entries(tree, dir->depth, page_size); + NvU8 max_pde_depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_AGNOSTIC) - 1; + + // Passing in NULL for the phys_allocs will mark the child entries as + // invalid. + uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; + + // Init with an invalid PTE or clean PDE. Only Maxwell PDEs can have more + // than 512 entries. In this case, we initialize them all with the same + // clean PDE. ATS systems may require clean PDEs with + // ATS_ALLOWED/ATS_NOT_ALLOWED bit settings based on the mapping VA. + // We only clean_bits to 0 at the lowest page table level (PTE table), i.e., + // when depth is greater than the max_pde_depth. + if ((dir->depth > max_pde_depth) || (entries_count > 512 && !g_uvm_global.ats.enabled)) { + NvU64 clear_bits[2]; + + // If it is not a PTE, make a clean PDE. + if (dir->depth != tree->hal->page_table_depth(page_size)) { + // make_pde() child index is zero/ignored, since it is only used in + // PDEs on ATS-enabled systems where pde_fill() is preferred. + tree->hal->make_pde(clear_bits, phys_allocs, dir, 0); + + // Make sure that using only clear_bits[0] will work. + UVM_ASSERT(tree->hal->entry_size(dir->depth) == sizeof(clear_bits[0]) || clear_bits[0] == clear_bits[1]); + } + else { + *clear_bits = 0; + } + + // Initialize the memory to a reasonable value. + if (push) { + tree->gpu->parent->ce_hal->memset_8(push, + uvm_mmu_gpu_address(tree->gpu, dir->phys_alloc.addr), + *clear_bits, + dir->phys_alloc.size); + } + else { + uvm_mmu_page_table_cpu_memset_8(tree->gpu, + &dir->phys_alloc, + 0, *clear_bits, - dir->phys_alloc.size); + dir->phys_alloc.size / sizeof(*clear_bits)); + } } else { - uvm_mmu_page_table_cpu_memset_8(tree->gpu, - &dir->phys_alloc, - 0, - *clear_bits, - dir->phys_alloc.size / sizeof(*clear_bits)); + pde_fill(tree, dir, 0, entries_count, phys_allocs, push); } + } static uvm_page_directory_t *allocate_directory(uvm_page_tree_t *tree, @@ -367,8 +487,10 @@ static uvm_page_directory_t *allocate_directory(uvm_page_tree_t *tree, NvLength phys_alloc_size = hal->allocation_size(depth, page_size); uvm_page_directory_t *dir; - // The page tree doesn't cache PTEs so space is not allocated for entries that are always PTEs. - // 2M PTEs may later become PDEs so pass UVM_PAGE_SIZE_AGNOSTIC, not page_size. + // The page tree doesn't cache PTEs so space is not allocated for entries + // that are always PTEs. + // 2M PTEs may later become PDEs so pass UVM_PAGE_SIZE_AGNOSTIC, not + // page_size. if (depth == hal->page_table_depth(UVM_PAGE_SIZE_AGNOSTIC)) entry_count = 0; else @@ -409,108 +531,6 @@ static inline NvU32 index_to_entry(uvm_mmu_mode_hal_t *hal, NvU32 entry_index, N return hal->entries_per_index(depth) * entry_index + hal->entry_offset(depth, page_size); } -static void pde_fill_cpu(uvm_page_tree_t *tree, - NvU32 depth, - uvm_mmu_page_table_alloc_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr) -{ - NvU64 pde_data[2], entry_size; - - UVM_ASSERT(uvm_mmu_use_cpu(tree)); - entry_size = tree->hal->entry_size(depth); - UVM_ASSERT(sizeof(pde_data) >= entry_size); - - tree->hal->make_pde(pde_data, phys_addr, depth); - - if (entry_size == sizeof(pde_data[0])) - uvm_mmu_page_table_cpu_memset_8(tree->gpu, directory, start_index, pde_data[0], pde_count); - else - uvm_mmu_page_table_cpu_memset_16(tree->gpu, directory, start_index, pde_data, pde_count); -} - -static void pde_fill_gpu(uvm_page_tree_t *tree, - NvU32 depth, - uvm_mmu_page_table_alloc_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr, - uvm_push_t *push) -{ - NvU64 pde_data[2], entry_size; - uvm_gpu_address_t pde_entry_addr = uvm_mmu_gpu_address(tree->gpu, directory->addr); - - UVM_ASSERT(!uvm_mmu_use_cpu(tree)); - - entry_size = tree->hal->entry_size(depth); - UVM_ASSERT(sizeof(pde_data) >= entry_size); - - tree->hal->make_pde(pde_data, phys_addr, depth); - pde_entry_addr.address += start_index * entry_size; - - if (entry_size == sizeof(pde_data[0])) { - tree->gpu->parent->ce_hal->memset_8(push, pde_entry_addr, pde_data[0], sizeof(pde_data[0]) * pde_count); - } - else { - NvU32 max_inline_entries = UVM_PUSH_INLINE_DATA_MAX_SIZE / sizeof(pde_data); - uvm_gpu_address_t inline_data_addr; - uvm_push_inline_data_t inline_data; - uvm_push_flag_t push_membar_flag = UVM_PUSH_FLAG_COUNT; - NvU32 i; - - if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) - push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_NONE; - else if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) - push_membar_flag = UVM_PUSH_FLAG_NEXT_MEMBAR_GPU; - - for (i = 0; i < pde_count;) { - NvU32 j; - NvU32 entry_count = min(pde_count - i, max_inline_entries); - - uvm_push_inline_data_begin(push, &inline_data); - for (j = 0; j < entry_count; j++) - uvm_push_inline_data_add(&inline_data, pde_data, sizeof(pde_data)); - inline_data_addr = uvm_push_inline_data_end(&inline_data); - - // All but the first memcopy can be pipelined. We respect the - // caller's pipelining settings for the first push. - if (i != 0) - uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); - - // No membar is needed until the last copy. Otherwise, use - // caller's membar flag. - if (i + entry_count < pde_count) - uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - else if (push_membar_flag != UVM_PUSH_FLAG_COUNT) - uvm_push_set_flag(push, push_membar_flag); - - tree->gpu->parent->ce_hal->memcopy(push, pde_entry_addr, inline_data_addr, entry_count * sizeof(pde_data)); - - i += entry_count; - pde_entry_addr.address += sizeof(pde_data) * entry_count; - } - } -} - -// pde_fill() populates pde_count PDE entries (starting at start_index) with -// the same mapping, i.e., with the same physical address (phys_addr). -static void pde_fill(uvm_page_tree_t *tree, - NvU32 depth, - uvm_mmu_page_table_alloc_t *directory, - NvU32 start_index, - NvU32 pde_count, - uvm_mmu_page_table_alloc_t **phys_addr, - uvm_push_t *push) -{ - UVM_ASSERT(start_index + pde_count <= uvm_mmu_page_tree_entries(tree, depth, UVM_PAGE_SIZE_AGNOSTIC)); - - if (push) - pde_fill_gpu(tree, depth, directory, start_index, pde_count, phys_addr, push); - else - pde_fill_cpu(tree, depth, directory, start_index, pde_count, phys_addr); -} - static uvm_page_directory_t *host_pde_write(uvm_page_directory_t *dir, uvm_page_directory_t *parent, NvU32 index_in_parent) @@ -540,7 +560,7 @@ static void pde_write(uvm_page_tree_t *tree, phys_allocs[i] = &entry->phys_alloc; } - pde_fill(tree, dir->depth, &dir->phys_alloc, entry_index, 1, phys_allocs, push); + pde_fill(tree, dir, entry_index, 1, phys_allocs, push); } static void host_pde_clear(uvm_page_tree_t *tree, uvm_page_directory_t *dir, NvU32 entry_index, NvU32 page_size) @@ -800,7 +820,6 @@ static void free_unused_directories(uvm_page_tree_t *tree, } } } - } static NV_STATUS allocate_page_table(uvm_page_tree_t *tree, NvU32 page_size, uvm_mmu_page_table_alloc_t *out) @@ -811,10 +830,93 @@ static NV_STATUS allocate_page_table(uvm_page_tree_t *tree, NvU32 page_size, uvm return phys_mem_allocate(tree, alloc_size, tree->location, UVM_PMM_ALLOC_FLAGS_EVICT, out); } +static bool page_tree_ats_init_required(uvm_page_tree_t *tree) +{ + // We have full control of the kernel page tables mappings, no ATS address + // aliases is expected. + if (tree->type == UVM_PAGE_TREE_TYPE_KERNEL) + return false; + + // Enable uvm_page_tree_init() from the page_tree test. + if (uvm_enable_builtin_tests && tree->gpu_va_space == NULL) + return false; + + if (!tree->gpu_va_space->ats.enabled) + return false; + + return tree->gpu->parent->no_ats_range_required; +} + +static NV_STATUS page_tree_ats_init(uvm_page_tree_t *tree) +{ + NV_STATUS status; + NvU64 min_va_upper, max_va_lower; + NvU32 page_size; + + if (!page_tree_ats_init_required(tree)) + return NV_OK; + + page_size = uvm_mmu_biggest_page_size(tree); + + uvm_cpu_get_unaddressable_range(&max_va_lower, &min_va_upper); + + // Potential violation of the UVM internal get/put_ptes contract. get_ptes() + // creates and initializes enough PTEs to populate all PDEs covering the + // no_ats_ranges. We store the no_ats_ranges in the tree, so they can be + // put_ptes()'ed on deinit(). It doesn't preclude the range to be used by a + // future get_ptes(), since we don't write to the PTEs (range->table) from + // the tree->no_ats_ranges. + // + // Lower half + status = uvm_page_tree_get_ptes(tree, + page_size, + max_va_lower, + page_size, + UVM_PMM_ALLOC_FLAGS_EVICT, + &tree->no_ats_ranges[0]); + if (status != NV_OK) + return status; + + UVM_ASSERT(tree->no_ats_ranges[0].entry_count == 1); + + if (uvm_platform_uses_canonical_form_address()) { + // Upper half + status = uvm_page_tree_get_ptes(tree, + page_size, + min_va_upper - page_size, + page_size, + UVM_PMM_ALLOC_FLAGS_EVICT, + &tree->no_ats_ranges[1]); + if (status != NV_OK) + return status; + + UVM_ASSERT(tree->no_ats_ranges[1].entry_count == 1); + } + + return NV_OK; +} + +static void page_tree_ats_deinit(uvm_page_tree_t *tree) +{ + size_t i; + + if (page_tree_ats_init_required(tree)) { + for (i = 0; i < ARRAY_SIZE(tree->no_ats_ranges); i++) { + if (tree->no_ats_ranges[i].entry_count) + uvm_page_tree_put_ptes(tree, &tree->no_ats_ranges[i]); + } + + memset(tree->no_ats_ranges, 0, sizeof(tree->no_ats_ranges)); + } +} + static void map_remap_deinit(uvm_page_tree_t *tree) { - if (tree->map_remap.pde0.size) - phys_mem_deallocate(tree, &tree->map_remap.pde0); + if (tree->map_remap.pde0) { + phys_mem_deallocate(tree, &tree->map_remap.pde0->phys_alloc); + uvm_kvfree(tree->map_remap.pde0); + tree->map_remap.pde0 = NULL; + } if (tree->map_remap.ptes_invalid_4k.size) phys_mem_deallocate(tree, &tree->map_remap.ptes_invalid_4k); @@ -839,10 +941,16 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // PDE1-depth(512M) PTE. We first map it to the pde0 directory, then we // return the PTE for the get_ptes()'s caller. if (tree->hal->page_sizes() & UVM_PAGE_SIZE_512M) { - status = allocate_page_table(tree, UVM_PAGE_SIZE_2M, &tree->map_remap.pde0); - if (status != NV_OK) + tree->map_remap.pde0 = allocate_directory(tree, + UVM_PAGE_SIZE_2M, + tree->hal->page_table_depth(UVM_PAGE_SIZE_2M), + UVM_PMM_ALLOC_FLAGS_EVICT); + if (tree->map_remap.pde0 == NULL) { + status = NV_ERR_NO_MEMORY; goto error; + } } + status = page_tree_begin_acquire(tree, &tree->tracker, &push, "map remap init"); if (status != NV_OK) goto error; @@ -864,22 +972,23 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; NvU32 depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_4K) - 1; size_t index_4k = tree->hal->entry_offset(depth, UVM_PAGE_SIZE_4K); - - // pde0 depth equals UVM_PAGE_SIZE_2M. - NvU32 pde0_depth = tree->hal->page_table_depth(UVM_PAGE_SIZE_2M); - NvU32 pde0_entries = tree->map_remap.pde0.size / tree->hal->entry_size(pde0_depth); + NvU32 pde0_entries = tree->map_remap.pde0->phys_alloc.size / tree->hal->entry_size(tree->map_remap.pde0->depth); // The big-page entry is NULL which makes it an invalid entry. phys_allocs[index_4k] = &tree->map_remap.ptes_invalid_4k; // By default CE operations include a MEMBAR_SYS. MEMBAR_GPU is // sufficient when pde0 is allocated in VIDMEM. - if (tree->map_remap.pde0.addr.aperture == UVM_APERTURE_VID) + if (tree->map_remap.pde0->phys_alloc.addr.aperture == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); + // This is an orphan directory, make_pde() requires a directory to + // compute the VA. The UVM depth map_remap() operates on is not in the + // range make_pde() must operate. We only need to supply the fields used + // by make_pde() to not access invalid memory addresses. + pde_fill(tree, - pde0_depth, - &tree->map_remap.pde0, + tree->map_remap.pde0, 0, pde0_entries, (uvm_mmu_page_table_alloc_t **)&phys_allocs, @@ -906,11 +1015,10 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // --------------|-------------------------||----------------|---------------- // vidmem | - || vidmem | false // sysmem | - || sysmem | false -// default | || vidmem | true (1) +// default | || vidmem | true // default | vidmem || vidmem | false // default | sysmem || sysmem | false // -// (1) When SEV mode is enabled, the fallback path is disabled. // // In SR-IOV heavy the the page tree must be in vidmem, to prevent guest drivers // from updating GPU page tables without hypervisor knowledge. @@ -926,28 +1034,27 @@ static NV_STATUS map_remap_init(uvm_page_tree_t *tree) // static void page_tree_set_location(uvm_page_tree_t *tree, uvm_aperture_t location) { - bool should_location_be_vidmem; UVM_ASSERT(tree->gpu != NULL); UVM_ASSERT_MSG((location == UVM_APERTURE_VID) || (location == UVM_APERTURE_SYS) || (location == UVM_APERTURE_DEFAULT), "Invalid location %s (%d)\n", uvm_aperture_string(location), (int)location); - should_location_be_vidmem = uvm_gpu_is_virt_mode_sriov_heavy(tree->gpu) - || uvm_conf_computing_mode_enabled(tree->gpu); - // The page tree of a "fake" GPU used during page tree testing can be in - // sysmem even if should_location_be_vidmem is true. A fake GPU can be - // identified by having no channel manager. - if ((tree->gpu->channel_manager != NULL) && should_location_be_vidmem) - UVM_ASSERT(location == UVM_APERTURE_VID); + // sysmem in scenarios where a "real" GPU must be in vidmem. Fake GPUs can + // be identified by having no channel manager. + if (tree->gpu->channel_manager != NULL) { + + if (uvm_parent_gpu_is_virt_mode_sriov_heavy(tree->gpu->parent)) + UVM_ASSERT(location == UVM_APERTURE_VID); + else if (g_uvm_global.conf_computing_enabled) + UVM_ASSERT(location == UVM_APERTURE_VID); + } if (location == UVM_APERTURE_DEFAULT) { if (page_table_aperture == UVM_APERTURE_DEFAULT) { tree->location = UVM_APERTURE_VID; - - // See the comment (1) above. - tree->location_sys_fallback = !g_uvm_global.sev_enabled; + tree->location_sys_fallback = true; } else { tree->location = page_table_aperture; @@ -1008,11 +1115,22 @@ NV_STATUS uvm_page_tree_init(uvm_gpu_t *gpu, return status; phys_mem_init(tree, UVM_PAGE_SIZE_AGNOSTIC, tree->root, &push); - return page_tree_end_and_wait(tree, &push); + + status = page_tree_end_and_wait(tree, &push); + if (status != NV_OK) + return status; + + status = page_tree_ats_init(tree); + if (status != NV_OK) + return status; + + return NV_OK; } void uvm_page_tree_deinit(uvm_page_tree_t *tree) { + page_tree_ats_deinit(tree); + UVM_ASSERT(tree->root->ref_count == 0); // Take the tree lock only to avoid assertions. It is not required for @@ -1251,7 +1369,6 @@ static NV_STATUS try_get_ptes(uvm_page_tree_t *tree, UVM_ASSERT(uvm_gpu_can_address_kernel(tree->gpu, start, size)); while (true) { - // index of the entry, for the first byte of the range, within its // containing directory NvU32 start_index; @@ -1283,7 +1400,8 @@ static NV_STATUS try_get_ptes(uvm_page_tree_t *tree, if (dir_cache[dir->depth] == NULL) { *cur_depth = dir->depth; - // Undo the changes to the tree so that the dir cache remains private to the thread + // Undo the changes to the tree so that the dir cache + // remains private to the thread. for (i = 0; i < used_count; i++) host_pde_clear(tree, dirs_used[i]->host_parent, dirs_used[i]->index_in_parent, page_size); @@ -1334,10 +1452,9 @@ static NV_STATUS map_remap(uvm_page_tree_t *tree, NvU64 start, NvLength size, uv if (uvm_page_table_range_aperture(range) == UVM_APERTURE_VID) uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU); - phys_alloc[0] = &tree->map_remap.pde0; + phys_alloc[0] = &tree->map_remap.pde0->phys_alloc; pde_fill(tree, - range->table->depth, - &range->table->phys_alloc, + range->table, range->start_index, range->entry_count, (uvm_mmu_page_table_alloc_t **)&phys_alloc, @@ -1382,7 +1499,8 @@ NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, dir_cache)) == NV_ERR_MORE_PROCESSING_REQUIRED) { uvm_mutex_unlock(&tree->lock); - // try_get_ptes never needs depth 0, so store a directory at its parent's depth + // try_get_ptes never needs depth 0, so store a directory at its + // parent's depth. // TODO: Bug 1766655: Allocate everything below cur_depth instead of // retrying for every level. dir_cache[cur_depth] = allocate_directory(tree, page_size, cur_depth + 1, pmm_flags); @@ -1665,8 +1783,12 @@ NV_STATUS uvm_page_table_range_vec_init(uvm_page_tree_t *tree, range); if (status != NV_OK) { UVM_ERR_PRINT("Failed to get PTEs for subrange %zd [0x%llx, 0x%llx) size 0x%llx, part of [0x%llx, 0x%llx)\n", - i, range_start, range_start + range_size, range_size, - start, size); + i, + range_start, + range_start + range_size, + range_size, + start, + size); goto out; } } @@ -2151,19 +2273,19 @@ static void destroy_identity_mapping(uvm_gpu_identity_mapping_t *mapping) mapping->range_vec = NULL; } -bool uvm_mmu_gpu_needs_static_vidmem_mapping(uvm_gpu_t *gpu) +bool uvm_mmu_parent_gpu_needs_static_vidmem_mapping(uvm_parent_gpu_t *parent_gpu) { - return !gpu->parent->ce_phys_vidmem_write_supported; + return !parent_gpu->ce_phys_vidmem_write_supported; } -bool uvm_mmu_gpu_needs_dynamic_vidmem_mapping(uvm_gpu_t *gpu) +bool uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(uvm_parent_gpu_t *parent_gpu) { - return uvm_gpu_is_virt_mode_sriov_heavy(gpu); + return uvm_parent_gpu_is_virt_mode_sriov_heavy(parent_gpu); } -bool uvm_mmu_gpu_needs_dynamic_sysmem_mapping(uvm_gpu_t *gpu) +bool uvm_mmu_parent_gpu_needs_dynamic_sysmem_mapping(uvm_parent_gpu_t *parent_gpu) { - return uvm_gpu_is_virt_mode_sriov_heavy(gpu); + return uvm_parent_gpu_is_virt_mode_sriov_heavy(parent_gpu); } NV_STATUS create_static_vidmem_mapping(uvm_gpu_t *gpu) @@ -2174,10 +2296,10 @@ NV_STATUS create_static_vidmem_mapping(uvm_gpu_t *gpu) NvU64 phys_offset = 0; uvm_gpu_identity_mapping_t *flat_mapping = &gpu->static_flat_mapping; - if (!uvm_mmu_gpu_needs_static_vidmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_static_vidmem_mapping(gpu->parent)) return NV_OK; - UVM_ASSERT(!uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)); + UVM_ASSERT(!uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(gpu->parent)); page_size = uvm_mmu_biggest_page_size(&gpu->address_space_tree); size = UVM_ALIGN_UP(gpu->mem_info.max_allocatable_address + 1, page_size); @@ -2199,7 +2321,7 @@ NV_STATUS create_static_vidmem_mapping(uvm_gpu_t *gpu) static void destroy_static_vidmem_mapping(uvm_gpu_t *gpu) { - if (!uvm_mmu_gpu_needs_static_vidmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_static_vidmem_mapping(gpu->parent)) return; destroy_identity_mapping(&gpu->static_flat_mapping); @@ -2324,7 +2446,7 @@ static void destroy_dynamic_vidmem_mapping(uvm_gpu_t *gpu) { size_t i; - if (!uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(gpu->parent)) return; if (gpu->root_chunk_mappings.array == NULL) @@ -2348,10 +2470,10 @@ static NV_STATUS create_dynamic_vidmem_mapping(uvm_gpu_t *gpu) NV_STATUS status; size_t count; - if (!uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(gpu->parent)) return NV_OK; - UVM_ASSERT(!uvm_mmu_gpu_needs_static_vidmem_mapping(gpu)); + UVM_ASSERT(!uvm_mmu_parent_gpu_needs_static_vidmem_mapping(gpu->parent)); BUILD_BUG_ON(UVM_PAGE_SIZE_2M != UVM_CHUNK_SIZE_MAX); UVM_ASSERT(uvm_mmu_page_size_supported(&gpu->address_space_tree, UVM_PAGE_SIZE_2M)); UVM_ASSERT(gpu->pmm.initialized); @@ -2497,7 +2619,7 @@ NV_STATUS uvm_mmu_chunk_map(uvm_gpu_chunk_t *chunk) NV_STATUS status = NV_OK; uvm_gpu_t *gpu = uvm_gpu_chunk_get_gpu(chunk); - if (!uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(gpu->parent)) return NV_OK; chunk_size = uvm_gpu_chunk_get_size(chunk); @@ -2550,7 +2672,7 @@ void uvm_mmu_chunk_unmap(uvm_gpu_chunk_t *chunk, uvm_tracker_t *tracker) return; gpu = uvm_gpu_chunk_get_gpu(chunk); - if (!uvm_mmu_gpu_needs_dynamic_vidmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(gpu->parent)) return; if (tracker != NULL) @@ -2614,7 +2736,7 @@ static void destroy_dynamic_sysmem_mapping(uvm_gpu_t *gpu) { size_t i; - if (!uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_dynamic_sysmem_mapping(gpu->parent)) return; if (gpu->sysmem_mappings.array == NULL) @@ -2636,7 +2758,7 @@ static NV_STATUS create_dynamic_sysmem_mapping(uvm_gpu_t *gpu) NvU64 mapping_size; NvU64 flat_sysmem_va_size; - if (!uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_dynamic_sysmem_mapping(gpu->parent)) return NV_OK; UVM_ASSERT(gpu->parent->flat_sysmem_va_base != 0); @@ -2692,7 +2814,7 @@ NV_STATUS uvm_mmu_sysmem_map(uvm_gpu_t *gpu, NvU64 pa, NvU64 size) { NvU64 curr_pa; - if (!uvm_mmu_gpu_needs_dynamic_sysmem_mapping(gpu)) + if (!uvm_mmu_parent_gpu_needs_dynamic_sysmem_mapping(gpu->parent)) return NV_OK; curr_pa = UVM_ALIGN_DOWN(pa, gpu->sysmem_mappings.mapping_size); @@ -2704,7 +2826,7 @@ NV_STATUS uvm_mmu_sysmem_map(uvm_gpu_t *gpu, NvU64 pa, NvU64 size) sysmem_mapping_lock(gpu, sysmem_mapping); if (sysmem_mapping->range_vec == NULL) { - uvm_gpu_address_t virtual_address = uvm_gpu_address_virtual_from_sysmem_phys(gpu, curr_pa); + uvm_gpu_address_t virtual_address = uvm_parent_gpu_address_virtual_from_sysmem_phys(gpu->parent, curr_pa); NvU64 phys_offset = curr_pa; NvU32 page_size = uvm_mmu_biggest_page_size(&gpu->address_space_tree); uvm_pmm_alloc_flags_t pmm_flags; diff --git a/kernel-open/nvidia-uvm/uvm_mmu.h b/kernel-open/nvidia-uvm/uvm_mmu.h index 2f21b6ee78..8a164db404 100644 --- a/kernel-open/nvidia-uvm/uvm_mmu.h +++ b/kernel-open/nvidia-uvm/uvm_mmu.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -50,13 +50,13 @@ // | | // | (not used) | // | | -// ------------------ 64PB + 8TB + 256GB (UVM_GPU_MAX_PHYS_MEM) +// ------------------ 64PB + 33TB (UVM_GPU_MAX_PHYS_MEM) // | vidmem | // | flat mapping | ==> UVM_GPU_MAX_PHYS_MEM -// | (256GB) | -// ------------------ 64PB + 8TB (flat_vidmem_va_base) +// | (up to 1TB) | +// ------------------ 64PB + 32TB (flat_vidmem_va_base) // |peer ident. maps| -// |32 * 256GB = 8TB| ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE +// |32 * 1TB = 32TB | ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE // ------------------ 64PB // | | // | rm_mem(64PB) | (rm_va_size) @@ -78,13 +78,13 @@ // | | // | (not used) | // | | -// ------------------ 136TB + 256GB (UVM_GPU_MAX_PHYS_MEM) +// ------------------ 161TB // | vidmem | // | flat mapping | ==> UVM_GPU_MAX_PHYS_MEM -// | (256GB) | -// ------------------ 136TB (flat_vidmem_va_base) +// | (up to 1TB) | +// ------------------ 160TB (flat_vidmem_va_base) // |peer ident. maps| -// |32 * 256GB = 8TB| ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE +// |32 * 1TB = 32TB | ==> NV_MAX_DEVICES * UVM_PEER_IDENTITY_VA_SIZE // ------------------ 128TB // | | // | rm_mem(128TB) | (rm_va_size) @@ -109,7 +109,7 @@ // +----------------+ 0 (rm_va_base) // Maximum memory of any GPU. -#define UVM_GPU_MAX_PHYS_MEM (256 * UVM_SIZE_1GB) +#define UVM_GPU_MAX_PHYS_MEM (UVM_SIZE_1TB) // The size of VA that should be reserved per peer identity mapping. // This should be at least the maximum amount of memory of any GPU. @@ -162,7 +162,7 @@ struct uvm_page_directory_struct // pointers to child directories on the host. // this array is variable length, so it needs to be last to allow it to // take up extra space - uvm_page_directory_t *entries[0]; + uvm_page_directory_t *entries[]; }; enum @@ -215,11 +215,14 @@ struct uvm_mmu_mode_hal_struct // memory out-of-range error so we can immediately identify bad PTE usage. NvU64 (*poisoned_pte)(void); - // write a PDE bit-pattern to entry based on the data in entries (which may + // Write a PDE bit-pattern to entry based on the data in allocs (which may // point to two items for dual PDEs). - // any of allocs are allowed to be NULL, in which case they are to be - // treated as empty. - void (*make_pde)(void *entry, uvm_mmu_page_table_alloc_t **allocs, NvU32 depth); + // Any of allocs are allowed to be NULL, in which case they are to be + // treated as empty. make_pde() uses dir and child_index to compute the + // mapping PDE VA. On ATS-enabled systems, we may set PDE's PCF as + // ATS_ALLOWED or ATS_NOT_ALLOWED based on the mapping PDE VA, even for + // invalid/clean PDE entries. + void (*make_pde)(void *entry, uvm_mmu_page_table_alloc_t **allocs, uvm_page_directory_t *dir, NvU32 child_index); // size of an entry in a directory/table. Generally either 8 or 16 bytes. // (in the case of Pascal dual PDEs) @@ -229,7 +232,7 @@ struct uvm_mmu_mode_hal_struct NvU32 (*entries_per_index)(NvU32 depth); // For dual PDEs, this is ether 1 or 0, depending on the page size. - // This is used to index the host copy only. GPU PDEs are always entirely + // This is used to index the host copy only. GPU PDEs are always entirely // re-written using make_pde. NvLength (*entry_offset)(NvU32 depth, NvU32 page_size); @@ -295,11 +298,16 @@ struct uvm_page_tree_struct // PDE0 where all big-page entries are invalid, and small-page entries // point to ptes_invalid_4k. - // pde0 is only used on Pascal-Ampere, i.e., they have the same PDE - // format. - uvm_mmu_page_table_alloc_t pde0; + // pde0 is used on Pascal+ GPUs, i.e., they have the same PDE format. + uvm_page_directory_t *pde0; } map_remap; + // On ATS-enabled systems where the CPU VA width is smaller than the GPU VA + // width, the excess address range is set with ATS_NOT_ALLOWED on all leaf + // PDEs covering that range. We have at most 2 no_ats_ranges, due to + // canonical form address systems. + uvm_page_table_range_t no_ats_ranges[2]; + // Tracker for all GPU operations on the tree uvm_tracker_t tracker; }; @@ -365,21 +373,32 @@ void uvm_page_tree_deinit(uvm_page_tree_t *tree); // the same page size without an intervening put_ptes. To duplicate a subset of // an existing range or change the size of an existing range, use // uvm_page_table_range_get_upper() and/or uvm_page_table_range_shrink(). -NV_STATUS uvm_page_tree_get_ptes(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *range); +NV_STATUS uvm_page_tree_get_ptes(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + NvLength size, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *range); // Same as uvm_page_tree_get_ptes(), but doesn't synchronize the GPU work. // // All pending operations can be waited on with uvm_page_tree_wait(). -NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, NvLength size, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *range); +NV_STATUS uvm_page_tree_get_ptes_async(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + NvLength size, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *range); // Returns a single-entry page table range for the addresses passed. // The size parameter must be a page size supported by this tree. // This is equivalent to calling uvm_page_tree_get_ptes() with size equal to // page_size. -NV_STATUS uvm_page_tree_get_entry(uvm_page_tree_t *tree, NvU32 page_size, NvU64 start, - uvm_pmm_alloc_flags_t pmm_flags, uvm_page_table_range_t *single); +NV_STATUS uvm_page_tree_get_entry(uvm_page_tree_t *tree, + NvU32 page_size, + NvU64 start, + uvm_pmm_alloc_flags_t pmm_flags, + uvm_page_table_range_t *single); // For a single-entry page table range, write the PDE (which could be a dual // PDE) to the GPU. @@ -478,8 +497,8 @@ NV_STATUS uvm_page_table_range_vec_create(uvm_page_tree_t *tree, // new_range_vec will contain the upper portion of range_vec, starting at // new_end + 1. // -// new_end + 1 is required to be within the address range of range_vec and be aligned to -// range_vec's page_size. +// new_end + 1 is required to be within the address range of range_vec and be +// aligned to range_vec's page_size. // // On failure, the original range vector is left unmodified. NV_STATUS uvm_page_table_range_vec_split_upper(uvm_page_table_range_vec_t *range_vec, @@ -501,18 +520,22 @@ void uvm_page_table_range_vec_destroy(uvm_page_table_range_vec_t *range_vec); // for each offset. // The caller_data pointer is what the caller passed in as caller_data to // uvm_page_table_range_vec_write_ptes(). -typedef NvU64 (*uvm_page_table_range_pte_maker_t)(uvm_page_table_range_vec_t *range_vec, NvU64 offset, - void *caller_data); +typedef NvU64 (*uvm_page_table_range_pte_maker_t)(uvm_page_table_range_vec_t *range_vec, + NvU64 offset, + void *caller_data); -// Write all PTEs covered by the range vector using the given PTE making function. +// Write all PTEs covered by the range vector using the given PTE making +// function. // // After writing all the PTEs a TLB invalidate operation is performed including // the passed in tlb_membar. // // See comments about uvm_page_table_range_pte_maker_t for details about the // PTE making callback. -NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, uvm_membar_t tlb_membar, - uvm_page_table_range_pte_maker_t pte_maker, void *caller_data); +NV_STATUS uvm_page_table_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec, + uvm_membar_t tlb_membar, + uvm_page_table_range_pte_maker_t pte_maker, + void *caller_data); // Set all PTEs covered by the range vector to an empty PTE // @@ -536,15 +559,15 @@ void uvm_mmu_destroy_flat_mappings(uvm_gpu_t *gpu); // Returns true if a static flat mapping covering the entire vidmem is required // for the given GPU. -bool uvm_mmu_gpu_needs_static_vidmem_mapping(uvm_gpu_t *gpu); +bool uvm_mmu_parent_gpu_needs_static_vidmem_mapping(uvm_parent_gpu_t *parent_gpu); // Returns true if an on-demand flat mapping partially covering the GPU memory // is required for the given device. -bool uvm_mmu_gpu_needs_dynamic_vidmem_mapping(uvm_gpu_t *gpu); +bool uvm_mmu_parent_gpu_needs_dynamic_vidmem_mapping(uvm_parent_gpu_t *parent_gpu); // Returns true if an on-demand flat mapping partially covering the sysmem // address space is required for the given device. -bool uvm_mmu_gpu_needs_dynamic_sysmem_mapping(uvm_gpu_t *gpu); +bool uvm_mmu_parent_gpu_needs_dynamic_sysmem_mapping(uvm_parent_gpu_t *parent_gpu); // Add or remove a (linear) mapping to the root chunk containing the given // chunk. The mapping is added to UVM's internal address space in the GPU @@ -567,15 +590,15 @@ void uvm_mmu_chunk_unmap(uvm_gpu_chunk_t *chunk, uvm_tracker_t *tracker); // Map a system physical address interval. The mapping is added to UVM's // internal address space in the given GPU. The resulting virtual address can be -// queried via uvm_gpu_address_virtual_from_sysmem_phys. +// queried via uvm_parent_gpu_address_virtual_from_sysmem_phys. // // The mapping persists until GPU deinitialization, such that no unmap // functionality is exposed. The map operation is synchronous, and internally // uses a large mapping granularity that in the common case exceeds the input // size. // -// The input address must be a GPU address as returned by uvm_gpu_map_cpu_pages -// for the given GPU. +// The input address must be a GPU address as returned by +// uvm_parent_gpu_map_cpu_pages for the given GPU. NV_STATUS uvm_mmu_sysmem_map(uvm_gpu_t *gpu, NvU64 pa, NvU64 size); static NvU64 uvm_mmu_page_tree_entries(uvm_page_tree_t *tree, NvU32 depth, NvU32 page_size) @@ -636,8 +659,9 @@ static NvU64 uvm_page_table_range_size(uvm_page_table_range_t *range) // Get the physical address of the entry at entry_index within the range // (counted from range->start_index). -static uvm_gpu_phys_address_t uvm_page_table_range_entry_address(uvm_page_tree_t *tree, uvm_page_table_range_t *range, - size_t entry_index) +static uvm_gpu_phys_address_t uvm_page_table_range_entry_address(uvm_page_tree_t *tree, + uvm_page_table_range_t *range, + size_t entry_index) { NvU32 entry_size = uvm_mmu_pte_size(tree, range->page_size); uvm_gpu_phys_address_t entry = range->table->phys_alloc.addr; diff --git a/kernel-open/nvidia-uvm/uvm_page_tree_test.c b/kernel-open/nvidia-uvm/uvm_page_tree_test.c index a5710e582f..782ac51138 100644 --- a/kernel-open/nvidia-uvm/uvm_page_tree_test.c +++ b/kernel-open/nvidia-uvm/uvm_page_tree_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -146,9 +146,15 @@ static void fake_tlb_invals_disable(void) g_fake_tlb_invals_tracking_enabled = false; } -// Fake TLB invalidate VA that just saves off the parameters so that they can be verified later -static void fake_tlb_invalidate_va(uvm_push_t *push, uvm_gpu_phys_address_t pdb, - NvU32 depth, NvU64 base, NvU64 size, NvU32 page_size, uvm_membar_t membar) +// Fake TLB invalidate VA that just saves off the parameters so that they can be +// verified later. +static void fake_tlb_invalidate_va(uvm_push_t *push, + uvm_gpu_phys_address_t pdb, + NvU32 depth, + NvU64 base, + NvU64 size, + NvU32 page_size, + uvm_membar_t membar) { if (!g_fake_tlb_invals_tracking_enabled) return; @@ -210,8 +216,8 @@ static bool assert_and_reset_last_invalidate(NvU32 expected_depth, bool expected } if ((g_last_fake_inval->membar == UVM_MEMBAR_NONE) == expected_membar) { UVM_TEST_PRINT("Expected %s membar, got %s instead\n", - expected_membar ? "a" : "no", - uvm_membar_string(g_last_fake_inval->membar)); + expected_membar ? "a" : "no", + uvm_membar_string(g_last_fake_inval->membar)); result = false; } @@ -230,7 +236,8 @@ static bool assert_last_invalidate_all(NvU32 expected_depth, bool expected_memba } if (g_last_fake_inval->base != 0 || g_last_fake_inval->size != -1) { UVM_TEST_PRINT("Expected invalidate all but got range [0x%llx, 0x%llx) instead\n", - g_last_fake_inval->base, g_last_fake_inval->base + g_last_fake_inval->size); + g_last_fake_inval->base, + g_last_fake_inval->base + g_last_fake_inval->size); return false; } if (g_last_fake_inval->depth != expected_depth) { @@ -247,15 +254,16 @@ static bool assert_invalidate_range_specific(fake_tlb_invalidate_t *inval, UVM_ASSERT(g_fake_tlb_invals_tracking_enabled); if (g_fake_invals_count == 0) { - UVM_TEST_PRINT("Expected an invalidate for range [0x%llx, 0x%llx), but got none\n", - base, base + size); + UVM_TEST_PRINT("Expected an invalidate for range [0x%llx, 0x%llx), but got none\n", base, base + size); return false; } if ((inval->base != base || inval->size != size) && inval->base != 0 && inval->size != -1) { UVM_TEST_PRINT("Expected invalidate range [0x%llx, 0x%llx), but got range [0x%llx, 0x%llx) instead\n", - base, base + size, - inval->base, inval->base + inval->size); + base, + base + size, + inval->base, + inval->base + inval->size); return false; } if (inval->depth != expected_depth) { @@ -270,7 +278,13 @@ static bool assert_invalidate_range_specific(fake_tlb_invalidate_t *inval, return true; } -static bool assert_invalidate_range(NvU64 base, NvU64 size, NvU32 page_size, bool allow_inval_all, NvU32 range_depth, NvU32 all_depth, bool expected_membar) +static bool assert_invalidate_range(NvU64 base, + NvU64 size, + NvU32 page_size, + bool allow_inval_all, + NvU32 range_depth, + NvU32 all_depth, + bool expected_membar) { NvU32 i; @@ -488,7 +502,6 @@ static NV_STATUS alloc_adjacent_pde_64k_memory(uvm_gpu_t *gpu) return NV_OK; } - static NV_STATUS alloc_nearby_pde_64k_memory(uvm_gpu_t *gpu) { uvm_page_tree_t tree; @@ -842,6 +855,7 @@ static NV_STATUS get_two_free_apart(uvm_gpu_t *gpu) TEST_CHECK_RET(range2.entry_count == 256); TEST_CHECK_RET(range2.table->ref_count == 512); TEST_CHECK_RET(range1.table == range2.table); + // 4k page is second entry in a dual PDE TEST_CHECK_RET(range1.table == tree.root->entries[0]->entries[0]->entries[0]->entries[1]); TEST_CHECK_RET(range1.start_index == 256); @@ -871,6 +885,7 @@ static NV_STATUS get_overlapping_dual_pdes(uvm_gpu_t *gpu) MEM_NV_CHECK_RET(test_page_tree_get_ptes(&tree, UVM_PAGE_SIZE_64K, size, size, &range64k), NV_OK); TEST_CHECK_RET(range64k.entry_count == 16); TEST_CHECK_RET(range64k.table->ref_count == 16); + // 4k page is second entry in a dual PDE TEST_CHECK_RET(range64k.table == tree.root->entries[0]->entries[0]->entries[0]->entries[0]); TEST_CHECK_RET(range64k.start_index == 16); @@ -1030,10 +1045,13 @@ static NV_STATUS test_tlb_invalidates(uvm_gpu_t *gpu) // Depth 4 NvU64 extent_pte = UVM_PAGE_SIZE_2M; + // Depth 3 NvU64 extent_pde0 = extent_pte * (1ull << 8); + // Depth 2 NvU64 extent_pde1 = extent_pde0 * (1ull << 9); + // Depth 1 NvU64 extent_pde2 = extent_pde1 * (1ull << 9); @@ -1081,7 +1099,11 @@ static NV_STATUS test_tlb_invalidates(uvm_gpu_t *gpu) return status; } -static NV_STATUS test_tlb_batch_invalidates_case(uvm_page_tree_t *tree, NvU64 base, NvU64 size, NvU32 min_page_size, NvU32 max_page_size) +static NV_STATUS test_tlb_batch_invalidates_case(uvm_page_tree_t *tree, + NvU64 base, + NvU64 size, + NvU32 min_page_size, + NvU32 max_page_size) { NV_STATUS status = NV_OK; uvm_push_t push; @@ -1205,7 +1227,11 @@ static bool assert_range_vec_ptes(uvm_page_table_range_vec_t *range_vec, bool ex NvU64 expected_pte = expecting_cleared ? 0 : range_vec->size + offset; if (*pte != expected_pte) { UVM_TEST_PRINT("PTE is 0x%llx instead of 0x%llx for offset 0x%llx within range [0x%llx, 0x%llx)\n", - *pte, expected_pte, offset, range_vec->start, range_vec->size); + *pte, + expected_pte, + offset, + range_vec->start, + range_vec->size); return false; } offset += range_vec->page_size; @@ -1226,7 +1252,11 @@ static NV_STATUS test_range_vec_write_ptes(uvm_page_table_range_vec_t *range_vec TEST_CHECK_RET(data.status == NV_OK); TEST_CHECK_RET(data.count == range_vec->size / range_vec->page_size); TEST_CHECK_RET(assert_invalidate_range_specific(g_last_fake_inval, - range_vec->start, range_vec->size, range_vec->page_size, page_table_depth, membar != UVM_MEMBAR_NONE)); + range_vec->start, + range_vec->size, + range_vec->page_size, + page_table_depth, + membar != UVM_MEMBAR_NONE)); TEST_CHECK_RET(assert_range_vec_ptes(range_vec, false)); fake_tlb_invals_disable(); @@ -1249,7 +1279,11 @@ static NV_STATUS test_range_vec_clear_ptes(uvm_page_table_range_vec_t *range_vec return NV_OK; } -static NV_STATUS test_range_vec_create(uvm_page_tree_t *tree, NvU64 start, NvU64 size, NvU32 page_size, uvm_page_table_range_vec_t **range_vec_out) +static NV_STATUS test_range_vec_create(uvm_page_tree_t *tree, + NvU64 start, + NvU64 size, + NvU32 page_size, + uvm_page_table_range_vec_t **range_vec_out) { uvm_page_table_range_vec_t *range_vec; uvm_pmm_alloc_flags_t pmm_flags = UVM_PMM_ALLOC_FLAGS_EVICT; @@ -1544,25 +1578,28 @@ static NV_STATUS entry_test_maxwell(uvm_gpu_t *gpu) uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); uvm_mmu_mode_hal_t *hal; + uvm_page_directory_t dir; NvU32 i, j, big_page_size, page_size; + dir.depth = 0; + for (i = 0; i < ARRAY_SIZE(big_page_sizes); i++) { big_page_size = big_page_sizes[i]; hal = gpu->parent->arch_hal->mmu_mode_hal(big_page_size); memset(phys_allocs, 0, sizeof(phys_allocs)); - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x0L); phys_allocs[0] = &alloc_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x1BBBBBBD99999992LL); phys_allocs[0] = &alloc_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(&pde_bits, phys_allocs, 0); + hal->make_pde(&pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits == 0x9999999E1BBBBBB1LL); for (j = 0; j <= 2; j++) { @@ -1632,38 +1669,47 @@ static NV_STATUS entry_test_pascal(uvm_gpu_t *gpu, entry_test_page_size_func ent uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); + uvm_page_directory_t dir; + // big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999900LL); uvm_mmu_page_table_alloc_t alloc_big_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBBB00LL); uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + dir.index_in_parent = 0; + dir.host_parent = NULL; + dir.depth = 0; + // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0); memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); + dir.depth = 0; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999990C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB0A); // Dual PDEs phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999999C && pde_bits[1] == 0x1BBBBBB0A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 3); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBBBA && pde_bits[1] == 0x3999999999990C); // uncached, i.e., the sysmem data is not cached in GPU's L2 cache. Clear @@ -1719,6 +1765,7 @@ static NV_STATUS entry_test_volta(uvm_gpu_t *gpu, entry_test_page_size_func entr uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0x1BBBBBB000LL); + uvm_page_directory_t dir; // big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x399999999999900LL); @@ -1726,37 +1773,45 @@ static NV_STATUS entry_test_volta(uvm_gpu_t *gpu, entry_test_page_size_func entr uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); + dir.index_in_parent = 0; + dir.host_parent = NULL; + dir.depth = 0; + // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0); memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); // Sys and vidmem PDEs phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); + dir.depth = 0; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999990C); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB0A); // Dual PDEs phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 3); + dir.depth = 3; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x3999999999999C && pde_bits[1] == 0x1BBBBBB0A); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 3); + hal->make_pde(pde_bits, phys_allocs, &dir, 0); TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBBBA && pde_bits[1] == 0x3999999999990C); // NO_ATS PDE1 (depth 2) phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 2); + dir.depth = 2; + hal->make_pde(pde_bits, phys_allocs, &dir, 0); if (g_uvm_global.ats.enabled) TEST_CHECK_RET(pde_bits[0] == 0x1BBBBBB2A); else @@ -1791,104 +1846,203 @@ static NV_STATUS entry_test_ampere(uvm_gpu_t *gpu, entry_test_page_size_func ent static NV_STATUS entry_test_hopper(uvm_gpu_t *gpu, entry_test_page_size_func entry_test_page_size) { + NV_STATUS status = NV_OK; NvU32 page_sizes[MAX_NUM_PAGE_SIZES]; NvU64 pde_bits[2]; + uvm_page_directory_t *dirs[5]; size_t i, num_page_sizes; uvm_mmu_page_table_alloc_t *phys_allocs[2] = {NULL, NULL}; uvm_mmu_page_table_alloc_t alloc_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999999000LL); uvm_mmu_page_table_alloc_t alloc_vid = fake_table_alloc(UVM_APERTURE_VID, 0xBBBBBBB000LL); - // big versions have [11:8] set as well to test the page table merging + // Big versions have [11:8] set as well to test the page table merging uvm_mmu_page_table_alloc_t alloc_big_sys = fake_table_alloc(UVM_APERTURE_SYS, 0x9999999999900LL); uvm_mmu_page_table_alloc_t alloc_big_vid = fake_table_alloc(UVM_APERTURE_VID, 0xBBBBBBBB00LL); uvm_mmu_mode_hal_t *hal = gpu->parent->arch_hal->mmu_mode_hal(UVM_PAGE_SIZE_64K); - // Make sure cleared PDEs work as expected - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0); + memset(dirs, 0, sizeof(dirs)); + // Fake directory tree. + for (i = 0; i < ARRAY_SIZE(dirs); i++) { + dirs[i] = uvm_kvmalloc_zero(sizeof(uvm_page_directory_t) + sizeof(dirs[i]->entries[0]) * 512); + TEST_CHECK_GOTO(dirs[i] != NULL, cleanup); + + dirs[i]->depth = i; + dirs[i]->index_in_parent = 0; + + if (i == 0) + dirs[i]->host_parent = NULL; + else + dirs[i]->host_parent = dirs[i - 1]; + } + + // Make sure cleared PDEs work as expected. + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0, cleanup); // Cleared PDEs work as expected for big and small PDEs. memset(pde_bits, 0xFF, sizeof(pde_bits)); - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0 && pde_bits[1] == 0); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0 && pde_bits[1] == 0, cleanup); // Sys and vidmem PDEs, uncached ATS allowed. phys_allocs[0] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0x999999999900C); + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); phys_allocs[0] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 0); - TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBB00A); + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBB00A, cleanup); - // Dual PDEs, uncached. + // Dual PDEs, uncached. We don't use child_dir in the depth 4 checks because + // our policy decides the PDE's PCF without using it. phys_allocs[0] = &alloc_big_sys; phys_allocs[1] = &alloc_vid; - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0x999999999991C && pde_bits[1] == 0xBBBBBBB01A); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + if (g_uvm_global.ats.enabled) + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999991C && pde_bits[1] == 0xBBBBBBB01A, cleanup); + else + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999990C && pde_bits[1] == 0xBBBBBBB00A, cleanup); phys_allocs[0] = &alloc_big_vid; phys_allocs[1] = &alloc_sys; - hal->make_pde(pde_bits, phys_allocs, 4); - TEST_CHECK_RET(pde_bits[0] == 0xBBBBBBBB1A && pde_bits[1] == 0x999999999901C); + hal->make_pde(pde_bits, phys_allocs, dirs[4], 0); + if (g_uvm_global.ats.enabled) + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBBB1A && pde_bits[1] == 0x999999999901C, cleanup); + else + TEST_CHECK_GOTO(pde_bits[0] == 0xBBBBBBBB0A && pde_bits[1] == 0x999999999900C, cleanup); + + // We only need to test make_pde() on ATS when the CPU VA width < GPU's. + if (g_uvm_global.ats.enabled && uvm_cpu_num_va_bits() < hal->num_va_bits()) { + phys_allocs[0] = &alloc_sys; + + dirs[1]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 1; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 1); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 2; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 2); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 511; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 511); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[1]->index_in_parent = 1; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 1); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999900C, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 509; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 509); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + dirs[2]->index_in_parent = 510; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 510); + TEST_CHECK_GOTO(pde_bits[0] == 0x999999999901C, cleanup); + + phys_allocs[0] = NULL; + + dirs[1]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[0], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + + dirs[2]->index_in_parent = 0; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 0); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + + dirs[2]->index_in_parent = 2; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 2); + TEST_CHECK_GOTO(pde_bits[0] == 0x10, cleanup); + + dirs[1]->index_in_parent = 1; + dirs[2]->index_in_parent = 509; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 509); + TEST_CHECK_GOTO(pde_bits[0] == 0x10, cleanup); + + dirs[2]->index_in_parent = 510; + hal->make_pde(pde_bits, phys_allocs, dirs[1], 510); + TEST_CHECK_GOTO(pde_bits[0] == 0x0, cleanup); + } // uncached, i.e., the sysmem data is not cached in GPU's L2 cache, and // access counters disabled. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == 0x999999999968D); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == 0x999999999968D, + cleanup); // change to cached. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_CACHED | UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == - 0x9999999999685); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_CACHED | UVM_MMU_PTE_FLAGS_ACCESS_COUNTERS_DISABLED) == + 0x9999999999685, + cleanup); // enable access counters. - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE_ATOMIC, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999605); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE_ATOMIC, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999605, + cleanup); // remove atomic - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_WRITE, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999645); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_WRITE, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999645, + cleanup); // read only - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_SYS, - 0x9999999999000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999665); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_SYS, + 0x9999999999000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0x9999999999665, + cleanup); // local video - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_VID, - 0xBBBBBBB000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0xBBBBBBB661); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_VID, + 0xBBBBBBB000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0xBBBBBBB661, + cleanup); // peer 1 - TEST_CHECK_RET(hal->make_pte(UVM_APERTURE_PEER_1, - 0xBBBBBBB000LL, - UVM_PROT_READ_ONLY, - UVM_MMU_PTE_FLAGS_CACHED) == 0x200000BBBBBBB663); + TEST_CHECK_GOTO(hal->make_pte(UVM_APERTURE_PEER_1, + 0xBBBBBBB000LL, + UVM_PROT_READ_ONLY, + UVM_MMU_PTE_FLAGS_CACHED) == 0x200000BBBBBBB663, + cleanup); // sparse - TEST_CHECK_RET(hal->make_sparse_pte() == 0x8); + TEST_CHECK_GOTO(hal->make_sparse_pte() == 0x8, cleanup); // sked reflected - TEST_CHECK_RET(hal->make_sked_reflected_pte() == 0xF09); + TEST_CHECK_GOTO(hal->make_sked_reflected_pte() == 0xF09, cleanup); num_page_sizes = get_page_sizes(gpu, page_sizes); for (i = 0; i < num_page_sizes; i++) - TEST_NV_CHECK_RET(entry_test_page_size(gpu, page_sizes[i])); + TEST_NV_CHECK_GOTO(entry_test_page_size(gpu, page_sizes[i]), cleanup); - return NV_OK; +cleanup: + for (i = 0; i < ARRAY_SIZE(dirs); i++) + uvm_kvfree(dirs[i]); + + return status; } static NV_STATUS alloc_4k_maxwell(uvm_gpu_t *gpu) @@ -2303,7 +2457,8 @@ NV_STATUS uvm_test_page_tree(UVM_TEST_PAGE_TREE_PARAMS *params, struct file *fil gpu->parent = parent_gpu; // At least test_tlb_invalidates() relies on global state - // (g_tlb_invalidate_*) so make sure only one test instance can run at a time. + // (g_tlb_invalidate_*) so make sure only one test instance can run at a + // time. uvm_mutex_lock(&g_uvm_global.global_lock); // Allocate the fake TLB tracking state. Notably tests still need to enable @@ -2311,7 +2466,13 @@ NV_STATUS uvm_test_page_tree(UVM_TEST_PAGE_TREE_PARAMS *params, struct file *fil // calls. TEST_NV_CHECK_GOTO(fake_tlb_invals_alloc(), done); - TEST_NV_CHECK_GOTO(maxwell_test_page_tree(gpu), done); + // We prevent the maxwell_test_page_tree test from running on ATS-enabled + // systems. On "fake" Maxwell-based ATS systems pde_fill() may push more + // methods than what we support in UVM. Specifically, on + // uvm_page_tree_init() which eventually calls phys_mem_init(). On Maxwell, + // upper PDE levels have more than 512 entries. + if (!g_uvm_global.ats.enabled) + TEST_NV_CHECK_GOTO(maxwell_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(pascal_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(volta_test_page_tree(gpu), done); TEST_NV_CHECK_GOTO(ampere_test_page_tree(gpu), done); diff --git a/kernel-open/nvidia-uvm/uvm_pascal.c b/kernel-open/nvidia-uvm/uvm_pascal.c index 83c675a273..8533220050 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal.c +++ b/kernel-open/nvidia-uvm/uvm_pascal.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2020 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -89,6 +89,8 @@ void uvm_hal_pascal_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counters_supported = false; + parent_gpu->access_counters_can_use_physical_addresses = false; + parent_gpu->fault_cancel_va_supported = false; parent_gpu->scoped_atomics_supported = false; @@ -100,4 +102,6 @@ void uvm_hal_pascal_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c b/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c index fb02ef28a1..f78caba65e 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c +++ b/kernel-open/nvidia-uvm/uvm_pascal_fault_buffer.c @@ -206,7 +206,7 @@ static UvmFaultMetadataPacket *get_fault_buffer_entry_metadata(uvm_parent_gpu_t UvmFaultMetadataPacket *fault_entry_metadata; UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults); - UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); fault_entry_metadata = parent_gpu->fault_buffer_info.rm_info.replayable.bufferMetadata; UVM_ASSERT(fault_entry_metadata != NULL); @@ -286,12 +286,9 @@ NV_STATUS uvm_hal_pascal_fault_buffer_parse_replayable_entry(uvm_parent_gpu_t *p bool uvm_hal_pascal_fault_buffer_entry_is_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - if (uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) { - NvU32 *fault_entry = get_fault_buffer_entry(parent_gpu, index); + NvU32 *fault_entry; - return READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID); - } - else { + if (g_uvm_global.conf_computing_enabled) { // Use the valid bit present in the encryption metadata, which is // unencrypted, instead of the valid bit present in the (encrypted) // fault itself. @@ -300,25 +297,26 @@ bool uvm_hal_pascal_fault_buffer_entry_is_valid(uvm_parent_gpu_t *parent_gpu, Nv return fault_entry_metadata->valid; } - UVM_ASSERT_MSG(false, "Invalid path"); - return false; + fault_entry = get_fault_buffer_entry(parent_gpu, index); + return READ_HWVALUE_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID); } void uvm_hal_pascal_fault_buffer_entry_clear_valid(uvm_parent_gpu_t *parent_gpu, NvU32 index) { - if (uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) { - NvU32 *fault_entry = get_fault_buffer_entry(parent_gpu, index); + NvU32 *fault_entry; - WRITE_HWCONST_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID, FALSE); - } - else { + if (g_uvm_global.conf_computing_enabled) { // Use the valid bit present in the encryption metadata, which is // unencrypted, instead of the valid bit present in the (encrypted) // fault itself. UvmFaultMetadataPacket *fault_entry_metadata = get_fault_buffer_entry_metadata(parent_gpu, index); fault_entry_metadata->valid = false; + return; } + + fault_entry = get_fault_buffer_entry(parent_gpu, index); + WRITE_HWCONST_MW(fault_entry, B069, FAULT_BUF_ENTRY, VALID, FALSE); } NvU32 uvm_hal_pascal_fault_buffer_entry_size(uvm_parent_gpu_t *parent_gpu) diff --git a/kernel-open/nvidia-uvm/uvm_pascal_mmu.c b/kernel-open/nvidia-uvm/uvm_pascal_mmu.c index 8b17319e9a..a1d8cd9040 100644 --- a/kernel-open/nvidia-uvm/uvm_pascal_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_pascal_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2020 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -33,6 +33,7 @@ #include "uvm_types.h" #include "uvm_forward_decl.h" +#include "nv_uvm_interface.h" #include "uvm_global.h" #include "uvm_gpu.h" #include "uvm_mmu.h" @@ -140,11 +141,18 @@ static NvU64 small_half_pde_pascal(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_pascal(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_pascal(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_pascal(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_pascal(dir->depth); + if (entry_count == 1) { *entry_bits = single_pde_pascal(*phys_allocs); } @@ -152,7 +160,8 @@ static void make_pde_pascal(void *entry, uvm_mmu_page_table_alloc_t **phys_alloc entry_bits[MMU_BIG] = big_half_pde_pascal(phys_allocs[MMU_BIG]); entry_bits[MMU_SMALL] = small_half_pde_pascal(phys_allocs[MMU_SMALL]); - // This entry applies to the whole dual PDE but is stored in the lower bits + // This entry applies to the whole dual PDE but is stored in the lower + // bits. entry_bits[MMU_BIG] |= HWCONST64(_MMU_VER2, DUAL_PDE, IS_PDE, TRUE); } else { @@ -365,28 +374,44 @@ uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_pascal(NvU32 big_page_size) return &pascal_mmu_mode_hal; } -void uvm_hal_pascal_mmu_enable_prefetch_faults(uvm_parent_gpu_t *parent_gpu) +static void mmu_set_prefetch_faults(uvm_parent_gpu_t *parent_gpu, bool enable) { - volatile NvU32 *prefetch_control; - NvU32 prefetch_control_value; + volatile NvU32 *prefetch_ctrl = parent_gpu->fault_buffer_info.rm_info.replayable.pPrefetchCtrl; + + // A null prefetch control mapping indicates that UVM should toggle the + // register's value using the RM API, instead of performing a direct access. + if (prefetch_ctrl == NULL) { + NV_STATUS status; + + // Access to the register is currently blocked only in Confidential + // Computing. + UVM_ASSERT(g_uvm_global.conf_computing_enabled); + status = nvUvmInterfaceTogglePrefetchFaults(&parent_gpu->fault_buffer_info.rm_info, (NvBool)enable); + + UVM_ASSERT(status == NV_OK); + } + else { + NvU32 prefetch_ctrl_value = UVM_GPU_READ_ONCE(*prefetch_ctrl); - prefetch_control = parent_gpu->fault_buffer_info.rm_info.replayable.pPrefetchCtrl; + if (enable) + prefetch_ctrl_value = WRITE_HWCONST(prefetch_ctrl_value, _PFB_PRI_MMU_PAGE, FAULT_CTRL, PRF_FILTER, SEND_ALL); + else + prefetch_ctrl_value = WRITE_HWCONST(prefetch_ctrl_value, _PFB_PRI_MMU_PAGE, FAULT_CTRL, PRF_FILTER, SEND_NONE); - prefetch_control_value = UVM_GPU_READ_ONCE(*prefetch_control); - prefetch_control_value = WRITE_HWCONST(prefetch_control_value, _PFB_PRI_MMU_PAGE, FAULT_CTRL, PRF_FILTER, SEND_ALL); - UVM_GPU_WRITE_ONCE(*prefetch_control, prefetch_control_value); + UVM_GPU_WRITE_ONCE(*prefetch_ctrl, prefetch_ctrl_value); + } } -void uvm_hal_pascal_mmu_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu) +void uvm_hal_pascal_mmu_enable_prefetch_faults(uvm_parent_gpu_t *parent_gpu) { - volatile NvU32 *prefetch_control; - NvU32 prefetch_control_value; + UVM_ASSERT(parent_gpu->prefetch_fault_supported); - prefetch_control = parent_gpu->fault_buffer_info.rm_info.replayable.pPrefetchCtrl; + mmu_set_prefetch_faults(parent_gpu, true); +} - prefetch_control_value = UVM_GPU_READ_ONCE(*prefetch_control); - prefetch_control_value = WRITE_HWCONST(prefetch_control_value, _PFB_PRI_MMU_PAGE, FAULT_CTRL, PRF_FILTER, SEND_NONE); - UVM_GPU_WRITE_ONCE(*prefetch_control, prefetch_control_value); +void uvm_hal_pascal_mmu_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu) +{ + mmu_set_prefetch_faults(parent_gpu, false); } NvU16 uvm_hal_pascal_mmu_client_id_to_utlb_id(NvU16 client_id) diff --git a/kernel-open/nvidia-uvm/uvm_perf_events.h b/kernel-open/nvidia-uvm/uvm_perf_events.h index 43e0047eb5..0d46192277 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_events.h +++ b/kernel-open/nvidia-uvm/uvm_perf_events.h @@ -162,7 +162,15 @@ typedef union // stale. Do not rely on them in the callbacks. struct { - uvm_push_t *push; + // CPU-to-CPU migrations do not use a push. Instead, such migrations + // need to record the migration start time, which for other migrations + // is recorded by the push. + union + { + uvm_push_t *push; + NvU64 cpu_start_timestamp; + }; + uvm_va_block_t *block; // ID of the destination processor of the migration @@ -171,6 +179,11 @@ typedef union // ID of the source processor of the migration uvm_processor_id_t src; + // For CPU-to-CPU migrations, these two fields indicate the source + // and destination NUMA node IDs. + NvU16 dst_nid; + NvU16 src_nid; + // Start address of the memory range being migrated NvU64 address; @@ -304,6 +317,40 @@ static inline void uvm_perf_event_notify_migration(uvm_perf_va_space_events_t *v uvm_perf_event_notify(va_space_events, UVM_PERF_EVENT_MIGRATION, &event_data); } +static inline void uvm_perf_event_notify_migration_cpu(uvm_perf_va_space_events_t *va_space_events, + uvm_va_block_t *va_block, + int dst_nid, + int src_nid, + NvU64 address, + NvU64 bytes, + NvU64 begin_timestamp, + uvm_va_block_transfer_mode_t transfer_mode, + uvm_make_resident_cause_t cause, + uvm_make_resident_context_t *make_resident_context) +{ + uvm_perf_event_data_t event_data = + { + .migration = + { + .cpu_start_timestamp = begin_timestamp, + .block = va_block, + .dst = UVM_ID_CPU, + .src = UVM_ID_CPU, + .src_nid = (NvU16)src_nid, + .dst_nid = (NvU16)dst_nid, + .address = address, + .bytes = bytes, + .transfer_mode = transfer_mode, + .cause = cause, + .make_resident_context = make_resident_context, + } + }; + + BUILD_BUG_ON(MAX_NUMNODES > (NvU16)-1); + + uvm_perf_event_notify(va_space_events, UVM_PERF_EVENT_MIGRATION, &event_data); +} + // Helper to notify gpu fault events static inline void uvm_perf_event_notify_gpu_fault(uvm_perf_va_space_events_t *va_space_events, uvm_va_block_t *va_block, diff --git a/kernel-open/nvidia-uvm/uvm_perf_heuristics.c b/kernel-open/nvidia-uvm/uvm_perf_heuristics.c index 309bc90ded..de3b4e5766 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_heuristics.c +++ b/kernel-open/nvidia-uvm/uvm_perf_heuristics.c @@ -81,11 +81,11 @@ NV_STATUS uvm_perf_heuristics_load(uvm_va_space_t *va_space) return NV_OK; } -NV_STATUS uvm_perf_heuristics_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu) +void uvm_perf_heuristics_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu) { uvm_assert_rwsem_locked_write(&va_space->lock); - return uvm_perf_thrashing_register_gpu(va_space, gpu); + uvm_perf_thrashing_register_gpu(va_space, gpu); } void uvm_perf_heuristics_stop(uvm_va_space_t *va_space) diff --git a/kernel-open/nvidia-uvm/uvm_perf_heuristics.h b/kernel-open/nvidia-uvm/uvm_perf_heuristics.h index b6e63883d7..51ea0ccb61 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_heuristics.h +++ b/kernel-open/nvidia-uvm/uvm_perf_heuristics.h @@ -44,7 +44,7 @@ void uvm_perf_heuristics_remove_gpu(uvm_gpu_t *gpu); NV_STATUS uvm_perf_heuristics_load(uvm_va_space_t *va_space); // This function is called when a GPU is registered on a VA space -NV_STATUS uvm_perf_heuristics_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu); +void uvm_perf_heuristics_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu); // The following two functions are called during VA space teardown. // uvm_perf_heuristics_stop is called first with no lock taken on the VA space. diff --git a/kernel-open/nvidia-uvm/uvm_perf_prefetch.c b/kernel-open/nvidia-uvm/uvm_perf_prefetch.c index fd3e003a64..16380db4e4 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_prefetch.c +++ b/kernel-open/nvidia-uvm/uvm_perf_prefetch.c @@ -15,7 +15,7 @@ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN hint OF CONTRACT, TORT OR OTHERWISE, ARISING + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -25,6 +25,7 @@ #include "uvm_perf_events.h" #include "uvm_perf_module.h" #include "uvm_perf_prefetch.h" +#include "uvm_perf_utils.h" #include "uvm_kvmalloc.h" #include "uvm_va_block.h" #include "uvm_va_range.h" diff --git a/kernel-open/nvidia-uvm/uvm_perf_prefetch.h b/kernel-open/nvidia-uvm/uvm_perf_prefetch.h index 0e9d5680a4..6fdedf42dc 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_prefetch.h +++ b/kernel-open/nvidia-uvm/uvm_perf_prefetch.h @@ -15,7 +15,7 @@ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN hint OF CONTRACT, TORT OR OTHERWISE, ARISING + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c index 8eb27f0483..2f6285b0a1 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.c +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.c @@ -15,14 +15,14 @@ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN hint OF CONTRACT, TORT OR OTHERWISE, ARISING + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *******************************************************************************/ #include "uvm_api.h" -#include "uvm_conf_computing.h" +#include "uvm_global.h" #include "uvm_perf_events.h" #include "uvm_perf_module.h" #include "uvm_perf_thrashing.h" @@ -263,7 +263,6 @@ static unsigned uvm_perf_thrashing_pin_threshold = UVM_PERF_THRASHING_PIN_THRESH // detection/prevention parameters #define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT 500 #define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_EMULATION (UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT * 800) -#define UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_HCC (UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT * 10) // Lapse of time in microseconds that determines if two consecutive events on // the same page can be considered thrashing @@ -1951,30 +1950,14 @@ void uvm_perf_thrashing_unload(uvm_va_space_t *va_space) } } -NV_STATUS uvm_perf_thrashing_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu) +void uvm_perf_thrashing_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu) { + va_space_thrashing_info_t *va_space_thrashing = va_space_thrashing_info_get(va_space); + // If a simulated GPU is registered, re-initialize thrashing parameters in // case they need to be adjusted. - bool params_need_readjusting = g_uvm_global.num_simulated_devices > 0; - - // Likewise, when the Confidential Computing feature is enabled, the DMA - // path is slower due to cryptographic operations & other associated - // overhead. Enforce a larger window to allow the thrashing mitigation - // mechanisms to work properly. - params_need_readjusting = params_need_readjusting || uvm_conf_computing_mode_enabled(gpu); - - if (params_need_readjusting) { - va_space_thrashing_info_t *va_space_thrashing = va_space_thrashing_info_get(va_space); - - if (!va_space_thrashing->params.test_overrides) { - if (uvm_conf_computing_mode_enabled(gpu)) - g_uvm_perf_thrashing_lapse_usec = UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT_HCC; - - va_space_thrashing_info_init_params(va_space_thrashing); - } - } - - return NV_OK; + if ((g_uvm_global.num_simulated_devices > 0) && !va_space_thrashing->params.test_overrides) + va_space_thrashing_info_init_params(va_space_thrashing); } NV_STATUS uvm_perf_thrashing_init(void) @@ -1999,7 +1982,15 @@ NV_STATUS uvm_perf_thrashing_init(void) UVM_PERF_THRASHING_PIN_THRESHOLD_DEFAULT, UVM_PERF_THRASHING_PIN_THRESHOLD_MAX); - INIT_THRASHING_PARAMETER_NONZERO(uvm_perf_thrashing_lapse_usec, UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT); + + + // In Confidential Computing, the DMA path is slower due to cryptographic + // operations & other associated overhead. Enforce a larger window to allow + // the thrashing mitigation mechanisms to work properly. + if (g_uvm_global.conf_computing_enabled) + INIT_THRASHING_PARAMETER_NONZERO(uvm_perf_thrashing_lapse_usec, UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT * 10); + else + INIT_THRASHING_PARAMETER_NONZERO(uvm_perf_thrashing_lapse_usec, UVM_PERF_THRASHING_LAPSE_USEC_DEFAULT); INIT_THRASHING_PARAMETER_NONZERO_MAX(uvm_perf_thrashing_nap, UVM_PERF_THRASHING_NAP_DEFAULT, diff --git a/kernel-open/nvidia-uvm/uvm_perf_thrashing.h b/kernel-open/nvidia-uvm/uvm_perf_thrashing.h index 23f05e82cd..56b60c9a63 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_thrashing.h +++ b/kernel-open/nvidia-uvm/uvm_perf_thrashing.h @@ -96,7 +96,7 @@ void uvm_perf_thrashing_remove_gpu(uvm_gpu_t *gpu); // VA space Initialization/cleanup functions. See comments in // uvm_perf_heuristics.h NV_STATUS uvm_perf_thrashing_load(uvm_va_space_t *va_space); -NV_STATUS uvm_perf_thrashing_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu); +void uvm_perf_thrashing_register_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu); void uvm_perf_thrashing_stop(uvm_va_space_t *va_space); void uvm_perf_thrashing_unload(uvm_va_space_t *va_space); diff --git a/kernel-open/nvidia-uvm/uvm_perf_utils.h b/kernel-open/nvidia-uvm/uvm_perf_utils.h index 01f011901f..fd2c7ef81b 100644 --- a/kernel-open/nvidia-uvm/uvm_perf_utils.h +++ b/kernel-open/nvidia-uvm/uvm_perf_utils.h @@ -145,11 +145,14 @@ static size_t uvm_perf_tree_iter_leaf_to_index_in_level(const uvm_perf_tree_t *t } // Computes the number of nodes in the given level -static size_t uvm_perf_tree_level_node_count(const uvm_perf_tree_t *tree, size_t level_idx) +static size_t uvm_perf_tree_level_node_count(const uvm_perf_tree_t *tree, s8 level_idx) { size_t level_pow2_node_count; size_t level_missing_nodes_to_pow2; + if ((level_idx < 0) || (level_idx >= tree->level_count)) + return 0; + level_pow2_node_count = (size_t)1 << level_idx; level_missing_nodes_to_pow2 = (tree->pow2_leaf_count - tree->leaf_count) >> ((tree->level_count - 1) - level_idx); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c index 9ff2d63f73..c9e8244b3d 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.c @@ -172,7 +172,6 @@ #include "uvm_va_block.h" #include "uvm_test.h" #include "uvm_linux.h" -#include "uvm_conf_computing.h" static int uvm_global_oversubscription = 1; module_param(uvm_global_oversubscription, int, S_IRUGO); @@ -221,7 +220,7 @@ struct uvm_pmm_gpu_chunk_suballoc_struct // Array of all child subchunks // TODO: Bug 1765461: Can the array be inlined? It could save the parent // pointer. - uvm_gpu_chunk_t *subchunks[0]; + uvm_gpu_chunk_t *subchunks[]; }; typedef enum @@ -345,7 +344,7 @@ static void root_chunk_unlock(uvm_pmm_gpu_t *pmm, uvm_gpu_root_chunk_t *root_chu // have an opt-out. static bool gpu_supports_pma_eviction(uvm_gpu_t *gpu) { - return uvm_global_oversubscription && uvm_gpu_supports_eviction(gpu); + return uvm_global_oversubscription && uvm_parent_gpu_supports_eviction(gpu->parent); } uvm_gpu_t *uvm_pmm_to_gpu(uvm_pmm_gpu_t *pmm) @@ -492,7 +491,7 @@ static bool chunk_is_in_eviction(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) uvm_gpu_t *uvm_gpu_chunk_get_gpu(const uvm_gpu_chunk_t *chunk) { - uvm_gpu_t *gpu = uvm_gpu_get(uvm_global_gpu_id_from_index(chunk->gpu_global_index)); + uvm_gpu_t *gpu = uvm_gpu_get(uvm_gpu_id_from_index(chunk->gpu_index)); UVM_ASSERT(gpu); return gpu; @@ -533,9 +532,9 @@ void uvm_pmm_gpu_sync(uvm_pmm_gpu_t *pmm) } } -static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_parent_gpu_t *parent_gpu, uvm_pmm_gpu_memory_type_t type) +static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_pmm_gpu_memory_type_t type) { - if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + if (g_uvm_global.conf_computing_enabled) return type; // Enforce the contract that when the Confidential Computing feature is @@ -571,7 +570,7 @@ NV_STATUS uvm_pmm_gpu_alloc(uvm_pmm_gpu_t *pmm, uvm_assert_lockable_order(UVM_LOCK_ORDER_VA_BLOCK); } - mem_type = pmm_squash_memory_type(gpu->parent, mem_type); + mem_type = pmm_squash_memory_type(mem_type); for (i = 0; i < num_chunks; i++) { uvm_gpu_root_chunk_t *root_chunk; @@ -1218,7 +1217,7 @@ static void root_chunk_unmap_indirect_peer(uvm_pmm_gpu_t *pmm, uvm_gpu_root_chun if (status != NV_OK) UVM_ASSERT(uvm_global_get_status() != NV_OK); - uvm_gpu_unmap_cpu_pages(other_gpu->parent, indirect_peer->dma_addrs[index], UVM_CHUNK_SIZE_MAX); + uvm_parent_gpu_unmap_cpu_pages(other_gpu->parent, indirect_peer->dma_addrs[index], UVM_CHUNK_SIZE_MAX); uvm_processor_mask_clear(&root_chunk->indirect_peers_mapped, other_gpu->id); new_count = atomic64_dec_return(&indirect_peer->map_count); UVM_ASSERT(new_count >= 0); @@ -1233,7 +1232,7 @@ static void root_chunk_unmap_indirect_peers(uvm_pmm_gpu_t *pmm, uvm_gpu_root_chu // partitioning is enabled and, therefore, we can obtain the uvm_gpu_t // object directly from the uvm_parent_gpu_t object's id. for_each_gpu_id_in_mask(other_gpu_id, &root_chunk->indirect_peers_mapped) { - uvm_gpu_t *other_gpu = uvm_gpu_get_by_processor_id(other_gpu_id); + uvm_gpu_t *other_gpu = uvm_gpu_get(other_gpu_id); root_chunk_unmap_indirect_peer(pmm, root_chunk, other_gpu); } } @@ -1348,10 +1347,10 @@ NV_STATUS uvm_pmm_gpu_indirect_peer_map(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chu root_chunk_lock(pmm, root_chunk); if (!uvm_processor_mask_test(&root_chunk->indirect_peers_mapped, accessing_gpu->id)) { - status = uvm_gpu_map_cpu_pages(accessing_gpu->parent, - uvm_gpu_chunk_to_page(pmm, &root_chunk->chunk), - UVM_CHUNK_SIZE_MAX, - &indirect_peer->dma_addrs[index]); + status = uvm_parent_gpu_map_cpu_pages(accessing_gpu->parent, + uvm_gpu_chunk_to_page(pmm, &root_chunk->chunk), + UVM_CHUNK_SIZE_MAX, + &indirect_peer->dma_addrs[index]); if (status == NV_OK) { uvm_processor_mask_set(&root_chunk->indirect_peers_mapped, accessing_gpu->id); atomic64_inc(&indirect_peer->map_count); @@ -1763,7 +1762,7 @@ static NV_STATUS pick_and_evict_root_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk; uvm_gpu_root_chunk_t *root_chunk; - UVM_ASSERT(uvm_gpu_supports_eviction(gpu)); + UVM_ASSERT(uvm_parent_gpu_supports_eviction(gpu->parent)); uvm_assert_mutex_locked(&pmm->lock); @@ -1926,7 +1925,7 @@ static NV_STATUS alloc_or_evict_root_chunk(uvm_pmm_gpu_t *pmm, status = alloc_root_chunk(pmm, type, flags, &chunk); if (status != NV_OK) { - if ((flags & UVM_PMM_ALLOC_FLAGS_EVICT) && uvm_gpu_supports_eviction(gpu)) + if ((flags & UVM_PMM_ALLOC_FLAGS_EVICT) && uvm_parent_gpu_supports_eviction(gpu->parent)) status = pick_and_evict_root_chunk_retry(pmm, type, PMM_CONTEXT_DEFAULT, chunk_out); return status; @@ -1948,7 +1947,7 @@ static NV_STATUS alloc_or_evict_root_chunk_unlocked(uvm_pmm_gpu_t *pmm, status = alloc_root_chunk(pmm, type, flags, &chunk); if (status != NV_OK) { - if ((flags & UVM_PMM_ALLOC_FLAGS_EVICT) && uvm_gpu_supports_eviction(gpu)) { + if ((flags & UVM_PMM_ALLOC_FLAGS_EVICT) && uvm_parent_gpu_supports_eviction(gpu->parent)) { uvm_mutex_lock(&pmm->lock); status = pick_and_evict_root_chunk_retry(pmm, type, PMM_CONTEXT_DEFAULT, chunk_out); uvm_mutex_unlock(&pmm->lock); @@ -2183,9 +2182,9 @@ NV_STATUS alloc_root_chunk(uvm_pmm_gpu_t *pmm, if (gpu->mem_info.numa.enabled) flags |= UVM_PMM_ALLOC_FLAGS_DONT_BATCH; - // When the confidential computing feature is enabled, allocate GPU memory + // When the Confidential Computing feature is enabled, allocate GPU memory // in the protected region, unless specified otherwise. - if (uvm_conf_computing_mode_enabled(gpu) && memory_type_is_protected(type)) + if (g_uvm_global.conf_computing_enabled && memory_type_is_protected(type)) options.flags |= UVM_PMA_ALLOCATE_PROTECTED_REGION; if (!gpu->parent->rm_info.isSimulated && @@ -2363,7 +2362,7 @@ NV_STATUS split_gpu_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) } suballoc->subchunks[i] = subchunk; - subchunk->gpu_global_index = chunk->gpu_global_index; + subchunk->gpu_index = chunk->gpu_index; subchunk->address = chunk->address + i * subchunk_size; subchunk->type = chunk->type; uvm_gpu_chunk_set_size(subchunk, subchunk_size); @@ -2438,14 +2437,12 @@ static bool check_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) UVM_ASSERT(chunk_size & chunk_sizes); UVM_ASSERT(IS_ALIGNED(chunk->address, chunk_size)); - UVM_ASSERT(uvm_global_id_equal(uvm_global_gpu_id_from_index(chunk->gpu_global_index), gpu->global_id)); + UVM_ASSERT(uvm_id_equal(uvm_gpu_id_from_index(chunk->gpu_index), gpu->id)); // See pmm_squash_memory_type(). - if (!uvm_conf_computing_mode_enabled(gpu)) { - UVM_ASSERT(chunk->type == UVM_PMM_GPU_MEMORY_TYPE_USER || - chunk->type == UVM_PMM_GPU_MEMORY_TYPE_KERNEL); - } + if (!g_uvm_global.conf_computing_enabled) + UVM_ASSERT((chunk->type == UVM_PMM_GPU_MEMORY_TYPE_USER) || (chunk->type == UVM_PMM_GPU_MEMORY_TYPE_KERNEL)); if (chunk->state == UVM_PMM_GPU_CHUNK_STATE_IS_SPLIT) UVM_ASSERT(chunk_size > uvm_chunk_find_first_size(chunk_sizes)); @@ -2477,7 +2474,7 @@ static bool check_chunk(uvm_pmm_gpu_t *pmm, uvm_gpu_chunk_t *chunk) // See root_chunk_unmap_indirect_peers for the usage of uvm_gpu_get for_each_gpu_id_in_mask(other_gpu_id, &root_chunk->indirect_peers_mapped) { - uvm_gpu_t *other_gpu = uvm_gpu_get_by_processor_id(other_gpu_id); + uvm_gpu_t *other_gpu = uvm_gpu_get(other_gpu_id); NvU64 peer_addr = uvm_pmm_gpu_indirect_peer_addr(pmm, chunk, other_gpu); uvm_reverse_map_t reverse_map; size_t num_mappings; @@ -2781,7 +2778,7 @@ static NV_STATUS uvm_pmm_gpu_pma_evict_pages(void *void_pmm, // Currently, when the Confidential Computing feature is enabled, the // entirety of vidmem is protected. - if (uvm_conf_computing_mode_enabled(uvm_pmm_to_gpu(pmm)) && (mem_type != UVM_PMA_GPU_MEMORY_TYPE_PROTECTED)) + if (g_uvm_global.conf_computing_enabled && (mem_type != UVM_PMA_GPU_MEMORY_TYPE_PROTECTED)) return NV_ERR_INVALID_ARGUMENT; while (num_pages_left_to_evict > 0) { @@ -3650,7 +3647,7 @@ NV_STATUS uvm_pmm_gpu_init(uvm_pmm_gpu_t *pmm) uvm_gpu_chunk_t *chunk = &pmm->root_chunks.array[i].chunk; INIT_LIST_HEAD(&chunk->list); - chunk->gpu_global_index = uvm_global_id_gpu_index(gpu->global_id); + chunk->gpu_index = uvm_id_gpu_index(gpu->id); chunk->state = UVM_PMM_GPU_CHUNK_STATE_PMA_OWNED; uvm_gpu_chunk_set_size(chunk, UVM_CHUNK_SIZE_MAX); chunk->address = i * UVM_CHUNK_SIZE_MAX; @@ -3779,7 +3776,7 @@ NV_STATUS uvm_test_evict_chunk(UVM_TEST_EVICT_CHUNK_PARAMS *params, struct file uvm_va_space_down_read(va_space); gpu = uvm_va_space_get_gpu_by_uuid(va_space, ¶ms->gpu_uuid); - if (!gpu || !uvm_gpu_supports_eviction(gpu)) { + if (!gpu || !uvm_parent_gpu_supports_eviction(gpu->parent)) { uvm_va_space_up_read(va_space); uvm_va_space_mm_or_current_release_unlock(va_space, mm); return NV_ERR_INVALID_DEVICE; diff --git a/kernel-open/nvidia-uvm/uvm_pmm_gpu.h b/kernel-open/nvidia-uvm/uvm_pmm_gpu.h index 6337f8575c..c28e2e2de0 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_gpu.h +++ b/kernel-open/nvidia-uvm/uvm_pmm_gpu.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -271,7 +271,7 @@ struct uvm_gpu_chunk_struct // This allows determining what PMM owns the chunk. Users of this field // must only use it if the owning GPU is retained. // TODO: Bug 2008200: Enforce single PMM instance per GPU - NvU32 gpu_global_index : order_base_2(UVM_GLOBAL_ID_MAX_PROCESSORS); + NvU32 gpu_index : order_base_2(UVM_ID_MAX_PROCESSORS); }; // List entry. diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c index f6a48c2e5b..deae45704f 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -106,7 +106,7 @@ NV_STATUS uvm_pmm_sysmem_mappings_add_gpu_mapping(uvm_pmm_sysmem_mappings_t *sys UVM_ASSERT(uvm_va_block_contains_address(va_block, virt_addr + region_size - 1)); uvm_assert_mutex_locked(&va_block->lock); - if (!sysmem_mappings->gpu->parent->access_counters_supported) + if (!sysmem_mappings->gpu->parent->access_counters_can_use_physical_addresses) return NV_OK; new_reverse_map = nv_kmem_cache_zalloc(g_reverse_page_map_cache, NV_UVM_GFP_FLAGS); @@ -151,7 +151,7 @@ static void pmm_sysmem_mappings_remove_gpu_mapping(uvm_pmm_sysmem_mappings_t *sy NvU64 key; const NvU64 base_key = dma_addr / PAGE_SIZE; - if (!sysmem_mappings->gpu->parent->access_counters_supported) + if (!sysmem_mappings->gpu->parent->access_counters_can_use_physical_addresses) return; uvm_mutex_lock(&sysmem_mappings->reverse_map_lock); @@ -200,7 +200,7 @@ void uvm_pmm_sysmem_mappings_reparent_gpu_mapping(uvm_pmm_sysmem_mappings_t *sys UVM_ASSERT(va_block); UVM_ASSERT(!uvm_va_block_is_dead(va_block)); - if (!sysmem_mappings->gpu->parent->access_counters_supported) + if (!sysmem_mappings->gpu->parent->access_counters_can_use_physical_addresses) return; uvm_mutex_lock(&sysmem_mappings->reverse_map_lock); @@ -238,7 +238,7 @@ NV_STATUS uvm_pmm_sysmem_mappings_split_gpu_mappings(uvm_pmm_sysmem_mappings_t * UVM_ASSERT(new_region_size <= UVM_VA_BLOCK_SIZE); UVM_ASSERT(is_power_of_2(new_region_size)); - if (!sysmem_mappings->gpu->parent->access_counters_supported) + if (!sysmem_mappings->gpu->parent->access_counters_can_use_physical_addresses) return NV_OK; uvm_mutex_lock(&sysmem_mappings->reverse_map_lock); @@ -319,7 +319,7 @@ void uvm_pmm_sysmem_mappings_merge_gpu_mappings(uvm_pmm_sysmem_mappings_t *sysme UVM_ASSERT(new_region_size <= UVM_VA_BLOCK_SIZE); UVM_ASSERT(is_power_of_2(new_region_size)); - if (!sysmem_mappings->gpu->parent->access_counters_supported) + if (!sysmem_mappings->gpu->parent->access_counters_can_use_physical_addresses) return; uvm_mutex_lock(&sysmem_mappings->reverse_map_lock); @@ -392,7 +392,7 @@ size_t uvm_pmm_sysmem_mappings_dma_to_virt(uvm_pmm_sysmem_mappings_t *sysmem_map UVM_ASSERT(region_size >= PAGE_SIZE); UVM_ASSERT(PAGE_ALIGNED(region_size)); - UVM_ASSERT(sysmem_mappings->gpu->parent->access_counters_supported); + UVM_ASSERT(sysmem_mappings->gpu->parent->access_counters_can_use_physical_addresses); UVM_ASSERT(max_out_mappings > 0); uvm_mutex_lock(&sysmem_mappings->reverse_map_lock); @@ -447,25 +447,25 @@ uvm_chunk_size_t uvm_cpu_chunk_get_size(uvm_cpu_chunk_t *chunk) return ((uvm_chunk_size_t)1) << chunk->log2_size; } -static NvU32 compute_gpu_mappings_entry_index(uvm_processor_mask_t *dma_addrs_mask, uvm_gpu_id_t id) +static NvU32 compute_gpu_mappings_entry_index(uvm_parent_processor_mask_t *dma_addrs_mask, uvm_parent_gpu_id_t id) { - uvm_processor_mask_t subset_mask; + uvm_parent_processor_mask_t subset_mask; // Compute the array index for the given GPU ID by masking off all bits // above and including the id and then counting the number of bits // remaining. - uvm_processor_mask_zero(&subset_mask); - bitmap_set(subset_mask.bitmap, UVM_ID_GPU0_VALUE, uvm_id_gpu_index(id)); - uvm_processor_mask_and(&subset_mask, dma_addrs_mask, &subset_mask); + uvm_parent_processor_mask_zero(&subset_mask); + bitmap_set(subset_mask.bitmap, UVM_PARENT_ID_GPU0_VALUE, uvm_parent_id_gpu_index(id)); + uvm_parent_processor_mask_and(&subset_mask, dma_addrs_mask, &subset_mask); - return uvm_processor_mask_get_gpu_count(&subset_mask); + return uvm_parent_processor_mask_get_gpu_count(&subset_mask); } static void cpu_chunk_release(nv_kref_t *kref) { uvm_cpu_chunk_t *chunk = container_of(kref, uvm_cpu_chunk_t, refcount); - uvm_processor_mask_t *mapping_mask; - uvm_processor_id_t id; + uvm_parent_processor_mask_t *mapping_mask; + uvm_parent_processor_id_t id; uvm_cpu_physical_chunk_t *phys_chunk = NULL; uvm_cpu_logical_chunk_t *logical_chunk = NULL; @@ -479,9 +479,9 @@ static void cpu_chunk_release(nv_kref_t *kref) mapping_mask = &logical_chunk->mapped_gpus; } - for_each_id_in_mask(id, mapping_mask) { + for_each_parent_id_in_mask(id, mapping_mask) { uvm_parent_gpu_t *parent_gpu = uvm_parent_gpu_get(id); - uvm_cpu_chunk_unmap_gpu_phys(chunk, parent_gpu); + uvm_cpu_chunk_unmap_parent_gpu_phys(chunk, parent_gpu); } if (uvm_cpu_chunk_is_physical(chunk)) { @@ -537,9 +537,9 @@ static uvm_page_index_t cpu_chunk_get_phys_index(uvm_cpu_logical_chunk_t *chunk) return (uvm_page_index_t)(chunk->common.page - phys_chunk->common.page); } -static uvm_cpu_phys_mapping_t *chunk_phys_mapping_alloc(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) +static uvm_cpu_phys_mapping_t *chunk_phys_mapping_alloc(uvm_cpu_physical_chunk_t *chunk, uvm_parent_gpu_id_t id) { - NvU32 num_active_entries = uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); + NvU32 num_active_entries = uvm_parent_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); uvm_cpu_phys_mapping_t *new_entries; NvU32 array_index; @@ -578,10 +578,10 @@ static uvm_cpu_phys_mapping_t *chunk_phys_mapping_alloc(uvm_cpu_physical_chunk_t return &chunk->gpu_mappings.dynamic_entries[array_index]; } -static uvm_cpu_phys_mapping_t *chunk_phys_mapping_get(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) +static uvm_cpu_phys_mapping_t *chunk_phys_mapping_get(uvm_cpu_physical_chunk_t *chunk, uvm_parent_gpu_id_t id) { uvm_assert_mutex_locked(&chunk->lock); - if (uvm_processor_mask_test(&chunk->gpu_mappings.dma_addrs_mask, id)) { + if (uvm_parent_processor_mask_test(&chunk->gpu_mappings.dma_addrs_mask, id)) { if (chunk->gpu_mappings.max_entries == 1) { return &chunk->gpu_mappings.static_entry; } @@ -594,7 +594,7 @@ static uvm_cpu_phys_mapping_t *chunk_phys_mapping_get(uvm_cpu_physical_chunk_t * return NULL; } -static void chunk_inc_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) +static void chunk_inc_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_parent_gpu_id_t id) { uvm_cpu_phys_mapping_t *mapping; @@ -604,7 +604,7 @@ static void chunk_inc_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t mapping->map_count++; } -static void chunk_dec_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t id) +static void chunk_dec_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_parent_gpu_id_t id) { uvm_cpu_phys_mapping_t *mapping; @@ -616,10 +616,10 @@ static void chunk_dec_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t if (mapping->map_count == 0) { uvm_parent_gpu_t *parent_gpu = uvm_parent_gpu_get(id); - uvm_gpu_unmap_cpu_pages(parent_gpu, mapping->dma_addr, uvm_cpu_chunk_get_size(&chunk->common)); + uvm_parent_gpu_unmap_cpu_pages(parent_gpu, mapping->dma_addr, uvm_cpu_chunk_get_size(&chunk->common)); mapping->dma_addr = 0; if (chunk->gpu_mappings.max_entries > 1) { - NvU32 num_active_entries = uvm_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); + NvU32 num_active_entries = uvm_parent_processor_mask_get_gpu_count(&chunk->gpu_mappings.dma_addrs_mask); NvU32 array_index = compute_gpu_mappings_entry_index(&chunk->gpu_mappings.dma_addrs_mask, id); // Shift any GPU mappings above this one down in the mappings array. @@ -627,11 +627,11 @@ static void chunk_dec_gpu_mapping(uvm_cpu_physical_chunk_t *chunk, uvm_gpu_id_t chunk->gpu_mappings.dynamic_entries[array_index] = chunk->gpu_mappings.dynamic_entries[array_index+1]; } - uvm_processor_mask_clear(&chunk->gpu_mappings.dma_addrs_mask, id); + uvm_parent_processor_mask_clear(&chunk->gpu_mappings.dma_addrs_mask, id); } } -NvU64 uvm_cpu_chunk_get_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) +NvU64 uvm_cpu_chunk_get_parent_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) { uvm_cpu_physical_chunk_t *phys_chunk = get_physical_parent(chunk); uvm_cpu_phys_mapping_t *mapping; @@ -641,7 +641,7 @@ NvU64 uvm_cpu_chunk_get_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t * if (uvm_cpu_chunk_is_logical(chunk)) { uvm_cpu_logical_chunk_t *logical_chunk = uvm_cpu_chunk_to_logical(chunk); - if (!uvm_processor_mask_test(&logical_chunk->mapped_gpus, parent_gpu->id)) + if (!uvm_parent_processor_mask_test(&logical_chunk->mapped_gpus, parent_gpu->id)) return 0; parent_offset = cpu_chunk_get_phys_index(logical_chunk); @@ -660,9 +660,9 @@ NvU64 uvm_cpu_chunk_get_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t * // entire parent physical chunk on the GPU. // // Returns NV_OK on success. On error, any of the errors returned by -// uvm_gpu_map_cpu_pages() can be returned. In the case that the DMA mapping -// structure could not be allocated, NV_ERR_NO_MEMORY is returned. -static NV_STATUS cpu_chunk_map_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) +// uvm_parent_gpu_map_cpu_pages() can be returned. In the case that the DMA +// mapping structure could not be allocated, NV_ERR_NO_MEMORY is returned. +static NV_STATUS cpu_chunk_map_parent_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) { uvm_cpu_physical_chunk_t *phys_chunk; uvm_cpu_logical_chunk_t *logical_chunk = NULL; @@ -670,32 +670,32 @@ static NV_STATUS cpu_chunk_map_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t if (uvm_cpu_chunk_is_logical(chunk)) { logical_chunk = uvm_cpu_chunk_to_logical(chunk); - if (uvm_processor_mask_test(&logical_chunk->mapped_gpus, parent_gpu->id)) + if (uvm_parent_processor_mask_test(&logical_chunk->mapped_gpus, parent_gpu->id)) return status; } phys_chunk = get_physical_parent(chunk); uvm_mutex_lock(&phys_chunk->lock); - if (!uvm_processor_mask_test(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id)) { + if (!uvm_parent_processor_mask_test(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id)) { uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(&phys_chunk->common); uvm_cpu_phys_mapping_t *mapping; NvU64 dma_addr; - status = uvm_gpu_map_cpu_pages(parent_gpu, phys_chunk->common.page, chunk_size, &dma_addr); + status = uvm_parent_gpu_map_cpu_pages(parent_gpu, phys_chunk->common.page, chunk_size, &dma_addr); if (status != NV_OK) goto done; mapping = chunk_phys_mapping_alloc(phys_chunk, parent_gpu->id); if (!mapping) { - uvm_gpu_unmap_cpu_pages(parent_gpu, dma_addr, chunk_size); + uvm_parent_gpu_unmap_cpu_pages(parent_gpu, dma_addr, chunk_size); status = NV_ERR_NO_MEMORY; goto done; } mapping->dma_addr = dma_addr; mapping->map_count = 1; - uvm_processor_mask_set(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id); + uvm_parent_processor_mask_set(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id); } else { // The mapping count on the physical chunk is only increased when @@ -708,25 +708,25 @@ static NV_STATUS cpu_chunk_map_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t uvm_mutex_unlock(&phys_chunk->lock); if (status == NV_OK && uvm_cpu_chunk_is_logical(chunk)) - uvm_processor_mask_set(&logical_chunk->mapped_gpus, parent_gpu->id); + uvm_parent_processor_mask_set(&logical_chunk->mapped_gpus, parent_gpu->id); return status; } -void uvm_cpu_chunk_unmap_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) +void uvm_cpu_chunk_unmap_parent_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu) { uvm_cpu_physical_chunk_t *phys_chunk; uvm_cpu_logical_chunk_t *logical_chunk; if (uvm_cpu_chunk_is_logical(chunk)) { logical_chunk = uvm_cpu_chunk_to_logical(chunk); - if (!uvm_processor_mask_test_and_clear(&logical_chunk->mapped_gpus, parent_gpu->id)) + if (!uvm_parent_processor_mask_test_and_clear(&logical_chunk->mapped_gpus, parent_gpu->id)) return; } phys_chunk = get_physical_parent(chunk); uvm_mutex_lock(&phys_chunk->lock); - if (uvm_processor_mask_test(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id)) + if (uvm_parent_processor_mask_test(&phys_chunk->gpu_mappings.dma_addrs_mask, parent_gpu->id)) chunk_dec_gpu_mapping(phys_chunk, parent_gpu->id); uvm_mutex_unlock(&phys_chunk->lock); @@ -737,13 +737,13 @@ NV_STATUS uvm_cpu_chunk_map_gpu(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) NV_STATUS status; uvm_chunk_size_t chunk_size = uvm_cpu_chunk_get_size(chunk); - status = cpu_chunk_map_gpu_phys(chunk, gpu->parent); + status = cpu_chunk_map_parent_gpu_phys(chunk, gpu->parent); if (status != NV_OK) return status; - status = uvm_mmu_sysmem_map(gpu, uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), chunk_size); + status = uvm_mmu_sysmem_map(gpu, uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent), chunk_size); if (status != NV_OK) - uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); + uvm_cpu_chunk_unmap_parent_gpu_phys(chunk, gpu->parent); return status; } @@ -763,7 +763,13 @@ static struct page *uvm_cpu_chunk_alloc_page(uvm_chunk_size_t alloc_size, else kernel_alloc_flags = NV_UVM_GFP_FLAGS; - kernel_alloc_flags |= GFP_HIGHUSER; + if ((alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT) && nid != NUMA_NO_NODE) + kernel_alloc_flags |= __GFP_THISNODE; + + if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ALLOW_MOVABLE) + kernel_alloc_flags |= GFP_HIGHUSER_MOVABLE; + else + kernel_alloc_flags |= GFP_HIGHUSER; // For allocation sizes higher than PAGE_SIZE, use __GFP_NORETRY in order // to avoid higher allocation latency from the kernel compacting memory to @@ -776,15 +782,20 @@ static struct page *uvm_cpu_chunk_alloc_page(uvm_chunk_size_t alloc_size, if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) kernel_alloc_flags |= __GFP_ZERO; - UVM_ASSERT(nid < num_online_nodes()); - if (nid == NUMA_NO_NODE) + if (nid == NUMA_NO_NODE) { page = alloc_pages(kernel_alloc_flags, get_order(alloc_size)); - else + } + else { + UVM_ASSERT(node_isset(nid, node_online_map)); page = alloc_pages_node(nid, kernel_alloc_flags, get_order(alloc_size)); + } if (page) { if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO) SetPageDirty(page); + + if (alloc_flags & UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT) + UVM_ASSERT(page_to_nid(page) == nid); } return page; @@ -871,8 +882,8 @@ NV_STATUS uvm_cpu_chunk_split(uvm_cpu_chunk_t *chunk, uvm_cpu_chunk_t **new_chun uvm_cpu_logical_chunk_t *new_chunk; uvm_cpu_physical_chunk_t *phys_chunk = get_physical_parent(chunk); uvm_cpu_logical_chunk_t *logical_chunk = NULL; - uvm_processor_id_t id; - uvm_processor_mask_t *dma_map_mask; + uvm_parent_processor_id_t id; + uvm_parent_processor_mask_t *dma_map_mask; uvm_chunk_size_t new_size; size_t num_new_chunks; size_t num_subchunk_pages; @@ -918,19 +929,19 @@ NV_STATUS uvm_cpu_chunk_split(uvm_cpu_chunk_t *chunk, uvm_cpu_chunk_t **new_chun nv_kref_init(&new_chunk->common.refcount); new_chunk->parent = chunk; uvm_cpu_chunk_get(new_chunk->parent); - for_each_id_in_mask(id, dma_map_mask) + for_each_parent_id_in_mask(id, dma_map_mask) chunk_inc_gpu_mapping(phys_chunk, id); - uvm_processor_mask_copy(&new_chunk->mapped_gpus, dma_map_mask); + uvm_parent_processor_mask_copy(&new_chunk->mapped_gpus, dma_map_mask); new_chunks[i] = &new_chunk->common; } // Release the references that are held by the chunk being split. - for_each_id_in_mask(id, dma_map_mask) + for_each_parent_id_in_mask(id, dma_map_mask) chunk_dec_gpu_mapping(phys_chunk, id); // If the chunk being split is a logical chunk clear it's mapped_gpus mask. if (uvm_cpu_chunk_is_logical(chunk)) - uvm_processor_mask_zero(&logical_chunk->mapped_gpus); + uvm_parent_processor_mask_zero(&logical_chunk->mapped_gpus); uvm_mutex_unlock(&phys_chunk->lock); @@ -952,7 +963,7 @@ static bool verify_merging_chunks(uvm_cpu_chunk_t **chunks, size_t num_chunks) { uvm_cpu_logical_chunk_t *logical_chunk; uvm_cpu_chunk_t *first_chunk_parent; - uvm_processor_mask_t *first_chunk_mapped_gpus; + uvm_parent_processor_mask_t *first_chunk_mapped_gpus; uvm_chunk_size_t first_chunk_size; size_t i; @@ -983,7 +994,7 @@ static bool verify_merging_chunks(uvm_cpu_chunk_t **chunks, size_t num_chunks) // 2.1 All mappings to GPUs in each of child chunks' masks that are // not also present in the parent chunk's mask are destroyed. // 2.2 mapped_gpus mask of the parent chunk remains unmodified. - UVM_ASSERT(uvm_processor_mask_equal(&logical_chunk->mapped_gpus, first_chunk_mapped_gpus)); + UVM_ASSERT(uvm_parent_processor_mask_equal(&logical_chunk->mapped_gpus, first_chunk_mapped_gpus)); } return true; @@ -994,7 +1005,7 @@ uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_cpu_chunk_t **chunks) uvm_cpu_chunk_t *parent; uvm_cpu_logical_chunk_t *logical_chunk; uvm_cpu_physical_chunk_t *phys_chunk; - uvm_processor_id_t id; + uvm_parent_processor_id_t id; uvm_chunk_size_t chunk_size; uvm_chunk_size_t parent_chunk_size; size_t num_merge_chunks; @@ -1022,11 +1033,11 @@ uvm_cpu_chunk_t *uvm_cpu_chunk_merge(uvm_cpu_chunk_t **chunks) phys_chunk = get_physical_parent(chunks[0]); uvm_mutex_lock(&phys_chunk->lock); - for_each_id_in_mask(id, &logical_chunk->mapped_gpus) + for_each_parent_id_in_mask(id, &logical_chunk->mapped_gpus) chunk_inc_gpu_mapping(phys_chunk, id); if (!uvm_cpu_chunk_is_physical(parent)) - uvm_processor_mask_copy(&uvm_cpu_chunk_to_logical(parent)->mapped_gpus, &logical_chunk->mapped_gpus); + uvm_parent_processor_mask_copy(&uvm_cpu_chunk_to_logical(parent)->mapped_gpus, &logical_chunk->mapped_gpus); uvm_mutex_unlock(&phys_chunk->lock); diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h index f2fd4d90bf..1f9c122069 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -188,6 +188,14 @@ typedef enum // Account for the chunk in the cgroup context. UVM_CPU_CHUNK_ALLOC_FLAGS_ACCOUNT = (1 << 1), + + // Be strict about NUMA locality of the allocation. + // Attempt the allocation only on the requested NUMA + // node. + UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT = (1 << 2), + + // Allow chunk allocations from ZONE_MOVABLE. + UVM_CPU_CHUNK_ALLOC_FLAGS_ALLOW_MOVABLE = (1 << 3), } uvm_cpu_chunk_alloc_flags_t; typedef enum @@ -260,7 +268,7 @@ typedef struct uvm_cpu_phys_mapping_t *dynamic_entries; }; - // Miximum number of physical mapping entries available. + // Maximum number of physical mapping entries available. // The initial value is 1 since the static_entry is always // available. // When using the dynamic_entries, it holds the size of the @@ -269,10 +277,10 @@ typedef struct // is the number of set bits in dma_addrs_mask. size_t max_entries; - // The set of GPU ID's that have an active physical mapping. + // The set of GPU parent ID's that have an active physical mapping. // Since physical mappings are shared by all GPUs under a // parent GPU, this mask only needs to track uvm_parent_gpu_t. - uvm_processor_mask_t dma_addrs_mask; + uvm_parent_processor_mask_t dma_addrs_mask; } gpu_mappings; // A dynamically allocated bitmap (one per PAGE_SIZE page) used @@ -296,7 +304,7 @@ typedef struct // Pointer to the parent chunk (which could also be a logical chunk). uvm_cpu_chunk_t *parent; - uvm_processor_mask_t mapped_gpus; + uvm_parent_processor_mask_t mapped_gpus; } uvm_cpu_logical_chunk_t; // Return the set of allowed CPU chunk allocation sizes. @@ -403,24 +411,21 @@ void uvm_cpu_chunk_free(uvm_cpu_chunk_t *chunk); // referenced using its physical address. There needs to be a kernel virtual // mapping created. // -// This helper function creates a DMA mapping on the GPU (see -// uvm_cpu_chunk_map_gpu()) and if necessary a kernel virtual mapping for the -// chunk. The virtual mapping persists until GPU deinitialization, such that no -// unmap functionality is exposed. For more details see uvm_mmu_sysmem_map(). -// -// Note that unlike uvm_cpu_chunk_map_gpu(), this helper requires the GPU -// object instead of the parent GPU object. +// This helper function creates a DMA mapping on the GPU and if necessary, +// a kernel virtual mapping for the chunk. The virtual mapping persists until +// GPU deinitialization, such that no unmap functionality is exposed. +// For more details see uvm_mmu_sysmem_map(). NV_STATUS uvm_cpu_chunk_map_gpu(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu); // Destroy a CPU chunk's DMA mapping for the parent GPU. -// If chunk is a logical chunk, this call may not necessary destroy the DMA +// If chunk is a logical chunk, this call may not necessarily destroy the DMA // mapping of the parent physical chunk since all logical chunks share the // parent's DMA mapping. -void uvm_cpu_chunk_unmap_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu); +void uvm_cpu_chunk_unmap_parent_gpu_phys(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu); // Get the CPU chunk's DMA mapping address for the specified GPU ID. // If there is no mapping for the GPU, 0 is returned. -NvU64 uvm_cpu_chunk_get_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu); +NvU64 uvm_cpu_chunk_get_parent_gpu_phys_addr(uvm_cpu_chunk_t *chunk, uvm_parent_gpu_t *parent_gpu); // Split a CPU chunk into a set of CPU chunks of the next size down from the set // of enabled CPU chunk sizes. diff --git a/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c b/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c index 71e06020c3..66a9837a48 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_sysmem_test.c @@ -42,8 +42,6 @@ static uvm_reverse_map_t g_sysmem_translations[PAGES_PER_UVM_VA_BLOCK]; // address ranges static uvm_pmm_sysmem_mappings_t g_reverse_map; -static uvm_gpu_t *g_volta_plus_gpu; - // Check that the DMA addresses in the range defined by // [base_dma_addr:base_dma_addr + uvm_va_block_size(va_block)] and page_mask // are registered in the reverse map, using one call per entry. The returned @@ -515,25 +513,25 @@ static NV_STATUS test_pmm_sysmem_reverse_map_remove_on_eviction(uvm_va_space_t * static NV_STATUS test_pmm_sysmem_reverse_map(uvm_va_space_t *va_space, NvU64 addr1, NvU64 addr2) { NV_STATUS status = NV_OK; + uvm_gpu_t *volta_gpu = NULL; uvm_gpu_t *gpu; - g_volta_plus_gpu = NULL; - - // Find a GPU with support for access counters, since it is required to add - // or remove entries to the reverse map. + // Find a GPU with support for access counters with physical address + // notifications, since it is required to add or remove entries to the + // reverse map. for_each_va_space_gpu(gpu, va_space) { - if (gpu->parent->access_counters_supported) { + if (gpu->parent->access_counters_can_use_physical_addresses) { // Initialize the reverse map. status = uvm_pmm_sysmem_mappings_init(gpu, &g_reverse_map); if (status != NV_OK) return status; - g_volta_plus_gpu = gpu; + volta_gpu = gpu; break; } } - if (!g_volta_plus_gpu) + if (!volta_gpu) return NV_ERR_INVALID_DEVICE; status = test_pmm_sysmem_reverse_map_single_whole(va_space, addr1); @@ -628,7 +626,7 @@ static NV_STATUS test_cpu_chunk_mapping_access(uvm_cpu_chunk_t *chunk, uvm_gpu_t TEST_NV_CHECK_RET(cpu_chunk_map_on_cpu(chunk, (void **)&cpu_addr)); memset(cpu_addr, 0, chunk_size); - dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + dma_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent); gpu_addr = uvm_gpu_address_copy(gpu, uvm_gpu_phys_address(UVM_APERTURE_SYS, dma_addr)); TEST_NV_CHECK_GOTO(uvm_push_begin_acquire(gpu->channel_manager, @@ -734,22 +732,22 @@ static NV_STATUS test_cpu_chunk_mapping_basic_verify(uvm_gpu_t *gpu, // - gpu_mappings.dma_addrs_mask should be 0. // - no GPU mapping address. TEST_CHECK_GOTO(phys_chunk->gpu_mappings.max_entries == 1, done); - TEST_CHECK_GOTO(uvm_processor_mask_get_gpu_count(&phys_chunk->gpu_mappings.dma_addrs_mask) == 0, done); - TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, done); + TEST_CHECK_GOTO(uvm_parent_processor_mask_get_gpu_count(&phys_chunk->gpu_mappings.dma_addrs_mask) == 0, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent) == 0, done); TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); // Test basic access. TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); // Test double map is harmless. - dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + dma_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent); TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); - TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == dma_addr, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent) == dma_addr, done); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); // Test unmap, remap. - uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); - TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, done); + uvm_cpu_chunk_unmap_parent_gpu_phys(chunk, gpu->parent); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent) == 0, done); TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done); @@ -785,8 +783,8 @@ static NV_STATUS test_cpu_chunk_mapping_array(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1, TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu2), done); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu1), done); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu2), done); - dma_addr_gpu1 = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu1->parent); - uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu2->parent); + dma_addr_gpu1 = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu1->parent); + uvm_cpu_chunk_unmap_parent_gpu_phys(chunk, gpu2->parent); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu1), done); TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu0), done); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu0), done); @@ -800,7 +798,7 @@ static NV_STATUS test_cpu_chunk_mapping_array(uvm_gpu_t *gpu0, uvm_gpu_t *gpu1, // GPU1. It's true that we may get a false negative if both addresses // happened to alias and we had a bug in how the addresses are shifted in // the dense array, but that's better than intermittent failure. - TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu1->parent) == dma_addr_gpu1, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu1->parent) == dma_addr_gpu1, done); done: uvm_cpu_chunk_free(chunk); @@ -830,7 +828,7 @@ static NV_STATUS do_test_cpu_chunk_split_and_merge(uvm_cpu_chunk_t *chunk, uvm_g TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(chunk, gpu), done_free); TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(chunk, gpu), done_free); - uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); + uvm_cpu_chunk_unmap_parent_gpu_phys(chunk, gpu->parent); TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); TEST_CHECK_GOTO(nv_kref_read(&chunk->refcount) == num_split_chunks, done); @@ -853,7 +851,7 @@ static NV_STATUS do_test_cpu_chunk_split_and_merge(uvm_cpu_chunk_t *chunk, uvm_g TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(merged_chunk, gpu), done_free); // Test that GPU mappings are transferred after a split - phys_dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + phys_dma_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent); TEST_NV_CHECK_GOTO(uvm_cpu_chunk_split(chunk, split_chunks), done_free); @@ -861,9 +859,9 @@ static NV_STATUS do_test_cpu_chunk_split_and_merge(uvm_cpu_chunk_t *chunk, uvm_g NvU64 dma_addr; TEST_NV_CHECK_GOTO(test_cpu_chunk_mapping_access(split_chunks[i], gpu), done); - dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[i], gpu->parent); + dma_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(split_chunks[i], gpu->parent); TEST_CHECK_GOTO(dma_addr == phys_dma_addr + (i * split_size), done); - uvm_cpu_chunk_unmap_gpu_phys(split_chunks[i], gpu->parent); + uvm_cpu_chunk_unmap_parent_gpu_phys(split_chunks[i], gpu->parent); } // Test that mapping one logical chunk does not affect others. @@ -873,7 +871,7 @@ static NV_STATUS do_test_cpu_chunk_split_and_merge(uvm_cpu_chunk_t *chunk, uvm_g for (i = 0; i < num_split_chunks; i++) { if (i != map_chunk) - TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[i], gpu->parent) == 0, done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_parent_gpu_phys_addr(split_chunks[i], gpu->parent) == 0, done); } if (split_size > PAGE_SIZE) { @@ -1101,9 +1099,9 @@ NV_STATUS do_test_cpu_chunk_free(uvm_cpu_chunk_t *chunk, uvm_va_space_t *va_spac chunk = NULL; // Map every other chunk. - // The call to uvm_cpu_chunk_unmap_gpu_phys() is here in case this is part - // of a double split (see below). In that case, the parent chunk would be - // either mapped or unmapped. + // The call to uvm_cpu_chunk_unmap_parent_gpu_phys() is here in case this + // is part of a double split (see below). In that case, the parent chunk + // would be either mapped or unmapped. // // If it is mapped, we have to unmap the subchunks in // order for the mapping check below to succeed. If it is unmapped, the @@ -1113,7 +1111,7 @@ NV_STATUS do_test_cpu_chunk_free(uvm_cpu_chunk_t *chunk, uvm_va_space_t *va_spac if (i & (1 << uvm_id_gpu_index(gpu->id))) TEST_NV_CHECK_GOTO(uvm_cpu_chunk_map_gpu(split_chunks[i], gpu), done); else - uvm_cpu_chunk_unmap_gpu_phys(split_chunks[i], gpu->parent); + uvm_cpu_chunk_unmap_parent_gpu_phys(split_chunks[i], gpu->parent); } } @@ -1149,9 +1147,9 @@ NV_STATUS do_test_cpu_chunk_free(uvm_cpu_chunk_t *chunk, uvm_va_space_t *va_spac TEST_CHECK_GOTO(uvm_cpu_chunk_get_size(split_chunks[j]) == split_size, done); for_each_va_space_gpu_in_mask(gpu, va_space, test_gpus) { if (j & (1 << uvm_id_gpu_index(gpu->id))) - TEST_CHECK_GOTO(uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[j], gpu->parent), done); + TEST_CHECK_GOTO(uvm_cpu_chunk_get_parent_gpu_phys_addr(split_chunks[j], gpu->parent), done); else - TEST_CHECK_GOTO(!uvm_cpu_chunk_get_gpu_phys_addr(split_chunks[j], gpu->parent), done); + TEST_CHECK_GOTO(!uvm_cpu_chunk_get_parent_gpu_phys_addr(split_chunks[j], gpu->parent), done); } } } diff --git a/kernel-open/nvidia-uvm/uvm_pmm_test.c b/kernel-open/nvidia-uvm/uvm_pmm_test.c index ec49caada6..290e5cc736 100644 --- a/kernel-open/nvidia-uvm/uvm_pmm_test.c +++ b/kernel-open/nvidia-uvm/uvm_pmm_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -98,39 +98,29 @@ typedef enum // This helper needs to stay in sync with the one in uvm_pmm_gpu.c // It is duplicated because we do not want to expose it as an API. -static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_parent_gpu_t *parent_gpu, uvm_pmm_gpu_memory_type_t type) +static uvm_pmm_gpu_memory_type_t pmm_squash_memory_type(uvm_pmm_gpu_memory_type_t type) { - if (uvm_conf_computing_mode_enabled_parent(parent_gpu)) + if (g_uvm_global.conf_computing_enabled) return type; // Enforce the contract that when the Confidential Computing feature is // disabled, all user types are alike, as well as all kernel types, // respectively. See uvm_pmm_gpu_memory_type_t. - switch (type) { - case UVM_PMM_GPU_MEMORY_TYPE_USER: // Alias UVM_PMM_GPU_MEMORY_TYPE_USER_PROTECTED - case UVM_PMM_GPU_MEMORY_TYPE_USER_UNPROTECTED: - return UVM_PMM_GPU_MEMORY_TYPE_USER; - case UVM_PMM_GPU_MEMORY_TYPE_KERNEL: // Alias UVM_PMM_GPU_MEMORY_TYPE_KERNEL_PROTECTED - case UVM_PMM_GPU_MEMORY_TYPE_KERNEL_UNPROTECTED: - return UVM_PMM_GPU_MEMORY_TYPE_KERNEL; - default: - UVM_ASSERT(0); - } + if (uvm_pmm_gpu_memory_type_is_user(type)) + return UVM_PMM_GPU_MEMORY_TYPE_USER; - return type; + return UVM_PMM_GPU_MEMORY_TYPE_KERNEL; } // Verify that the input chunks are in the correct state following alloc -static NV_STATUS check_chunks(uvm_pmm_gpu_t *pmm, - uvm_gpu_chunk_t **chunks, +static NV_STATUS check_chunks(uvm_gpu_chunk_t **chunks, size_t num_chunks, uvm_chunk_size_t chunk_size, uvm_pmm_gpu_memory_type_t mem_type) { - uvm_gpu_t *gpu = uvm_pmm_to_gpu(pmm); size_t i; - mem_type = pmm_squash_memory_type(gpu->parent, mem_type); + mem_type = pmm_squash_memory_type(mem_type); for (i = 0; i < num_chunks; i++) { TEST_CHECK_RET(chunks[i]); TEST_CHECK_RET(chunks[i]->suballoc == NULL); @@ -187,7 +177,7 @@ static NV_STATUS chunk_alloc_check_common(uvm_pmm_gpu_t *pmm, if (check_status != NV_OK) return check_status; - return check_chunks(pmm, chunks, num_chunks, chunk_size, mem_type); + return check_chunks(chunks, num_chunks, chunk_size, mem_type); } static NV_STATUS chunk_alloc_check(uvm_pmm_gpu_t *pmm, @@ -324,10 +314,10 @@ static NV_STATUS gpu_mem_check(uvm_gpu_t *gpu, // TODO: Bug 3839176: [UVM][HCC][uvm_test] Update tests that assume GPU // engines can directly access sysmem - // Skip this test for now. To enable this test under SEV, + // Skip this test for now. To enable this test in Confidential Computing, // The GPU->CPU CE copy needs to be updated so it uses encryption when // CC is enabled. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; UVM_ASSERT(verif_mem->size >= size); memset(verif_cpu_addr, 0, size); @@ -561,7 +551,8 @@ static NV_STATUS basic_test(uvm_va_space_t *va_space, uvm_gpu_t *gpu, // In SR-IOV heavy, virtual mappings will be created for each chunk // this test allocates before accessing it on the GPU. But currently // it is not allowed to map a kernel chunk, so skip those. - if (uvm_gpu_is_virt_mode_sriov_heavy(gpu) && uvm_pmm_gpu_memory_type_is_kernel(test_state.type)) + if (uvm_parent_gpu_is_virt_mode_sriov_heavy(gpu->parent) && + uvm_pmm_gpu_memory_type_is_kernel(test_state.type)) continue; chunk_sizes = gpu->pmm.chunk_sizes[test_state.type]; @@ -791,7 +782,8 @@ static NV_STATUS split_test(uvm_va_space_t *va_space, uvm_gpu_t *gpu) // In SR-IOV heavy, virtual mappings will be created for each chunk // this test allocates before accessing it on the GPU. But currently // it is not allowed to map a kernel chunk, so skip those. - if (uvm_gpu_is_virt_mode_sriov_heavy(gpu) && uvm_pmm_gpu_memory_type_is_kernel(type)) + if (uvm_parent_gpu_is_virt_mode_sriov_heavy(gpu->parent) && + uvm_pmm_gpu_memory_type_is_kernel(type)) continue; // Test every available parent size except the smallest, which obviously @@ -922,7 +914,6 @@ NV_STATUS __test_pmm_async_alloc_type(uvm_va_space_t *va_space, uvm_tracker_t tracker = UVM_TRACKER_INIT(); uvm_push_t push; NvU32 i; - uvm_global_processor_mask_t global_mask; chunks = uvm_kvmalloc_zero(num_chunks * sizeof(chunks[0])); if (!chunks) @@ -936,9 +927,7 @@ NV_STATUS __test_pmm_async_alloc_type(uvm_va_space_t *va_space, if (status != NV_OK) goto out; - uvm_va_space_global_gpus(va_space, &global_mask); - - status = uvm_mem_map_kernel(dummy_buffer, &global_mask); + status = uvm_mem_map_kernel(dummy_buffer, &va_space->registered_gpus); if (status != NV_OK) goto out; @@ -1223,8 +1212,6 @@ static NV_STATUS test_indirect_peers(uvm_gpu_t *owning_gpu, uvm_gpu_t *accessing if (!chunks) return NV_ERR_NO_MEMORY; - UVM_ASSERT(!g_uvm_global.sev_enabled); - TEST_NV_CHECK_GOTO(uvm_mem_alloc_sysmem_and_map_cpu_kernel(UVM_CHUNK_SIZE_MAX, current->mm, &verif_mem), out); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, owning_gpu), out); TEST_NV_CHECK_GOTO(uvm_mem_map_gpu_kernel(verif_mem, accessing_gpu), out); diff --git a/kernel-open/nvidia-uvm/uvm_policy.c b/kernel-open/nvidia-uvm/uvm_policy.c index 17c0dabd82..38c53eeb6e 100644 --- a/kernel-open/nvidia-uvm/uvm_policy.c +++ b/kernel-open/nvidia-uvm/uvm_policy.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -29,6 +29,7 @@ #include "uvm_tracker.h" #include "uvm_gpu.h" #include "uvm_va_space_mm.h" +#include "uvm_processors.h" static bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length) { @@ -143,14 +144,19 @@ static NV_STATUS split_span_as_needed(uvm_va_space_t *va_space, return split_as_needed(va_space, end_addr, split_needed_cb, data); } -static bool preferred_location_is_split_needed(const uvm_va_policy_t *policy, void *data) +typedef struct { uvm_processor_id_t processor_id; + int nid; +} preferred_location_split_params_t; - UVM_ASSERT(data); +static bool preferred_location_is_split_needed(const uvm_va_policy_t *policy, void *data) +{ + preferred_location_split_params_t *params = (preferred_location_split_params_t *)data; + + UVM_ASSERT(params); - processor_id = *(uvm_processor_id_t*)data; - return !uvm_id_equal(processor_id, policy->preferred_location); + return !uvm_va_policy_preferred_location_equal(policy, params->processor_id, params->nid); } static NV_STATUS preferred_location_unmap_remote_pages(uvm_va_block_t *va_block, @@ -221,12 +227,14 @@ static NV_STATUS preferred_location_set(uvm_va_space_t *va_space, NvU64 base, NvU64 length, uvm_processor_id_t preferred_location, + int preferred_cpu_nid, uvm_va_range_t **first_va_range_to_migrate, uvm_tracker_t *out_tracker) { uvm_va_range_t *va_range, *va_range_last; const NvU64 last_address = base + length - 1; bool preferred_location_is_faultable_gpu = false; + preferred_location_split_params_t split_params; NV_STATUS status; uvm_assert_rwsem_locked_write(&va_space->lock); @@ -238,11 +246,13 @@ static NV_STATUS preferred_location_set(uvm_va_space_t *va_space, preferred_location); } + split_params.processor_id = preferred_location; + split_params.nid = preferred_cpu_nid; status = split_span_as_needed(va_space, base, last_address + 1, preferred_location_is_split_needed, - &preferred_location); + &split_params); if (status != NV_OK) return status; @@ -266,7 +276,7 @@ static NV_STATUS preferred_location_set(uvm_va_space_t *va_space, return NV_ERR_INVALID_DEVICE; } - status = uvm_va_range_set_preferred_location(va_range, preferred_location, mm, out_tracker); + status = uvm_va_range_set_preferred_location(va_range, preferred_location, preferred_cpu_nid, mm, out_tracker); if (status != NV_OK) return status; @@ -284,7 +294,12 @@ static NV_STATUS preferred_location_set(uvm_va_space_t *va_space, if (!mm) return NV_ERR_INVALID_ADDRESS; - return uvm_hmm_set_preferred_location(va_space, preferred_location, base, last_address, out_tracker); + return uvm_hmm_set_preferred_location(va_space, + preferred_location, + preferred_cpu_nid, + base, + last_address, + out_tracker); } NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS *params, struct file *filp) @@ -297,6 +312,7 @@ NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS uvm_va_range_t *first_va_range_to_migrate = NULL; struct mm_struct *mm; uvm_processor_id_t preferred_location_id; + int preferred_cpu_nid = NUMA_NO_NODE; bool has_va_space_write_lock; const NvU64 start = params->requestedBase; const NvU64 length = params->length; @@ -318,6 +334,15 @@ NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS // If the CPU is the preferred location, we don't have to find the associated uvm_gpu_t if (uvm_uuid_is_cpu(¶ms->preferredLocation)) { preferred_location_id = UVM_ID_CPU; + preferred_cpu_nid = params->preferredCpuNumaNode; + + if (preferred_cpu_nid != -1 && + (!nv_numa_node_has_memory(preferred_cpu_nid) || + !node_isset(preferred_cpu_nid, node_possible_map) || + uvm_va_space_find_gpu_with_memory_node_id(va_space, preferred_cpu_nid))) { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } } else { // Translate preferredLocation into a live GPU ID, and check that this @@ -355,7 +380,14 @@ NV_STATUS uvm_api_set_preferred_location(const UVM_SET_PREFERRED_LOCATION_PARAMS goto done; } - status = preferred_location_set(va_space, mm, start, length, preferred_location_id, &first_va_range_to_migrate, &local_tracker); + status = preferred_location_set(va_space, + mm, + start, + length, + preferred_location_id, + preferred_cpu_nid, + &first_va_range_to_migrate, + &local_tracker); if (status != NV_OK) goto done; @@ -429,6 +461,7 @@ NV_STATUS uvm_api_unset_preferred_location(const UVM_UNSET_PREFERRED_LOCATION_PA params->requestedBase, params->length, UVM_ID_INVALID, + NUMA_NO_NODE, NULL, &local_tracker); diff --git a/kernel-open/nvidia-uvm/uvm_populate_pageable.c b/kernel-open/nvidia-uvm/uvm_populate_pageable.c index 1967e1bdf8..ea5207a3c6 100644 --- a/kernel-open/nvidia-uvm/uvm_populate_pageable.c +++ b/kernel-open/nvidia-uvm/uvm_populate_pageable.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2022 NVIDIA Corporation + Copyright (c) 2018-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -138,9 +138,9 @@ NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma, goto out; if (touch) - ret = NV_PIN_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL, NULL); + ret = NV_PIN_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL); else - ret = NV_GET_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL, NULL); + ret = NV_GET_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL); if (uvm_managed_vma) uvm_record_lock_mmap_lock_read(mm); diff --git a/kernel-open/nvidia-uvm/uvm_processors.c b/kernel-open/nvidia-uvm/uvm_processors.c index 6938959cc8..f377faa3ae 100644 --- a/kernel-open/nvidia-uvm/uvm_processors.c +++ b/kernel-open/nvidia-uvm/uvm_processors.c @@ -21,8 +21,36 @@ *******************************************************************************/ +#include "uvm_linux.h" #include "uvm_processors.h" +static struct kmem_cache *g_uvm_processor_mask_cache __read_mostly; + +NV_STATUS uvm_processor_mask_cache_init(void) +{ + g_uvm_processor_mask_cache = NV_KMEM_CACHE_CREATE("uvm_processor_mask_t", uvm_processor_mask_t); + if (!g_uvm_processor_mask_cache) + return NV_ERR_NO_MEMORY; + + return NV_OK; +} + +void uvm_processor_mask_cache_exit(void) +{ + kmem_cache_destroy_safe(&g_uvm_processor_mask_cache); +} + +uvm_processor_mask_t *uvm_processor_mask_cache_alloc(void) +{ + return kmem_cache_alloc(g_uvm_processor_mask_cache, NV_UVM_GFP_FLAGS); +} + +void uvm_processor_mask_cache_free(uvm_processor_mask_t *mask) +{ + if (mask) + kmem_cache_free(g_uvm_processor_mask_cache, mask); +} + int uvm_find_closest_node_mask(int src, const nodemask_t *mask) { int nid; @@ -38,3 +66,48 @@ int uvm_find_closest_node_mask(int src, const nodemask_t *mask) return closest_nid; } + +// This implementation avoids having to dynamically allocate a temporary +// uvm_processor_mask_t on the stack (due to size) or the heap (due to possible +// allocation failures). +bool uvm_processor_mask_gpu_subset(const uvm_processor_mask_t *subset, + const uvm_processor_mask_t *mask) +{ + DECLARE_BITMAP(first_word, BITS_PER_LONG); + + BUILD_BUG_ON(UVM_ID_CPU_VALUE > BITS_PER_LONG); + BUILD_BUG_ON(BITS_PER_LONG > UVM_ID_MAX_PROCESSORS); + + bitmap_copy(first_word, subset->bitmap, BITS_PER_LONG); + __clear_bit(UVM_ID_CPU_VALUE, first_word); + + return bitmap_subset(first_word, mask->bitmap, BITS_PER_LONG) && + bitmap_subset(subset->bitmap + 1, mask->bitmap + 1, UVM_ID_MAX_PROCESSORS - BITS_PER_LONG); +} + +void uvm_parent_gpus_from_processor_mask(uvm_parent_processor_mask_t *parent_mask, + const uvm_processor_mask_t *mask) +{ + uvm_gpu_id_t gpu_id; + + uvm_parent_processor_mask_zero(parent_mask); + + for_each_gpu_id_in_mask(gpu_id, mask) + uvm_parent_processor_mask_set(parent_mask, uvm_parent_gpu_id_from_gpu_id(gpu_id)); +} + +bool uvm_numa_id_eq(int nid0, int nid1) +{ + UVM_ASSERT(nid0 == -1 || nid0 < MAX_NUMNODES); + UVM_ASSERT(nid1 == -1 || nid1 < MAX_NUMNODES); + + if ((nid0 == NUMA_NO_NODE || nid1 == NUMA_NO_NODE) && nodes_weight(node_possible_map) == 1) { + if (nid0 == NUMA_NO_NODE) + nid0 = first_node(node_possible_map); + + if (nid1 == NUMA_NO_NODE) + nid1 = first_node(node_possible_map); + } + + return nid0 == nid1; +} diff --git a/kernel-open/nvidia-uvm/uvm_processors.h b/kernel-open/nvidia-uvm/uvm_processors.h index f6d2a5ed4f..516dbca4b1 100644 --- a/kernel-open/nvidia-uvm/uvm_processors.h +++ b/kernel-open/nvidia-uvm/uvm_processors.h @@ -28,22 +28,21 @@ #include "uvm_common.h" #include -#define UVM_MAX_UNIQUE_GPU_PAIRS SUM_FROM_0_TO_N(UVM_MAX_GPUS - 1) - // Processor identifiers // ===================== // // UVM uses its own identifiers to refer to the processors in the system. For // simplicity (and performance), integers are used. However, in order to -// provide type safety, they are wrapped within the uvm_processor_id_t struct. +// provide type safety, they are wrapped within the uvm_parent_processor_id_t +// struct. // The range of valid identifiers needs to cover the maximum number of // supported GPUs on a system plus the CPU. CPU is assigned value 0, and GPUs // range: [1, UVM_PARENT_ID_MAX_GPUS]. // // There are some functions that only expect GPU identifiers and, in order to // make it clearer, the uvm_parent_gpu_id_t alias type is provided. However, as -// this type is just a typedef of uvm_processor_id_t, there is no type checking -// performed by the compiler. +// this type is just a typedef of uvm_parent_processor_id_t, there is no type +// checking performed by the compiler. // // Identifier value vs index // ------------------------- @@ -63,40 +62,30 @@ // In the diagram below, MAX_SUB is used to abbreviate // UVM_PARENT_ID_MAX_SUB_PROCESSORS. // -// TODO: Bug 4195538: uvm_parent_processor_id_t is currently but temporarily the -// same as uvm_processor_id_t. -// -// |-------------------------- uvm_parent_processor_id_t ----------------------| -// | | -// | |----------------------- uvm_parent_gpu_id_t ------------------------|| -// | | || -// Proc type | CPU | GPU ... GPU ... GPU || -// | | || -// ID values | 0 | 1 ... i+1 ... UVM_PARENT_ID_MAX_PROCESSORS-1 || -// -// GPU index 0 ... i ... UVM_PARENT_ID_MAX_GPUS-1 -// | | | | -// | | | | -// | |-------------| | |------------------------------------| -// | | | | -// | | | | -// GPU index 0 ... MAX_SUB-1 ... i*MAX_SUB ... (i+1)*MAX_SUB-1 ... UVM_GLOBAL_ID_MAX_GPUS-1 -// -// ID values | 0 | 1 ... MAX_SUB ... (i*MAX_SUB)+1 ... (i+1)*MAX_SUB ... UVM_GLOBAL_ID_MAX_PROCESSORS-1 || -// | | || -// Proc type | CPU | GPU ... GPU ... GPU ... GPU ... GPU || -// | | || -// | |-------------------------------------- uvm_global_gpu_id_t ---------------------------------------|| -// | | -// |----------------------------------------- uvm_global_processor_id_t -------------------------------------| +// |-------------------------- uvm_parent_processor_id_t ---------------------------------------------| +// | | +// | |----------------------- uvm_parent_gpu_id_t -----------------------------------------------|| +// | | || +// Proc type | CPU | GPU | ... | GPU | ... GPU || +// | | | | | || +// ID values | 0 | 1 | ... | i+1 | ... UVM_PARENT_ID_MAX_PROCESSORS-1 || +// | | | | | || +// GPU index | | 0 | ... | i | ... UVM_PARENT_ID_MAX_GPUS-1 || +// | | | | | || +// + + + + + ++ +// | | |-------------| | |-----------------------------| || +// | | | | | || +// GPU index | | 0 ... MAX_SUB-1 | ... | i*MAX_SUB ... (i+1)*MAX_SUB-1 | ... UVM_ID_MAX_GPUS-1 || +// | | | | | || +// ID values | 0 | 1 ... MAX_SUB | ... | (i*MAX_SUB)+1 ... (i+1)*MAX_SUB | ... UVM_ID_MAX_PROCESSORS-1 || +// | | | | | || +// Proc type | CPU | GPU ... GPU | ... | GPU ... GPU | ... GPU || +// | | || +// | |-------------------------------------- uvm_gpu_id_t ---------------------------------------|| +// | | +// |----------------------------------------- uvm_processor_id_t -------------------------------------| // // When SMC is enabled, each GPU partition gets its own uvm_gpu_t object. -// However, there can only be a single partition per GPU in a VA space, so -// uvm_processor_id_t/uvm_processor_mask_t can still be used when operating -// in the context of a VA space. In the global context, types that can refer -// to all individual partitions need to be used, though. Therefore, we -// provide the uvm_global_gpu_id_t/uvm_global_processor_mask_t types and the -// corresponding uvm_global_gpu_id*/uvm_global_processor_mask* helpers. #define UVM_PROCESSOR_MASK(mask_t, \ prefix_fn_mask, \ @@ -232,7 +221,7 @@ static proc_id_t prefix_fn_mask##_find_first_unset_id(const mask_t *mask) return proc_id_ctor(find_first_zero_bit(mask->bitmap, (maxval))); \ } \ \ -static proc_id_t prefix_fn_mask##_find_next_unset_id(const mask_t *mask, proc_id_t min_id) \ +static proc_id_t prefix_fn_mask##_find_next_unset_id(const mask_t *mask, proc_id_t min_id) \ { \ return proc_id_ctor(find_next_zero_bit(mask->bitmap, (maxval), min_id.val)); \ } \ @@ -270,10 +259,10 @@ typedef struct typedef struct { NvU32 val; -} uvm_global_processor_id_t; +} uvm_processor_id_t; typedef uvm_parent_processor_id_t uvm_parent_gpu_id_t; -typedef uvm_global_processor_id_t uvm_global_gpu_id_t; +typedef uvm_processor_id_t uvm_gpu_id_t; // Static value assigned to the CPU #define UVM_PARENT_ID_CPU_VALUE 0 @@ -281,26 +270,27 @@ typedef uvm_global_processor_id_t uvm_global_gpu_id_t; // ID values for the CPU and first GPU, respectively; the values for both types // of IDs must match to enable sharing of UVM_PROCESSOR_MASK(). -#define UVM_GLOBAL_ID_CPU_VALUE UVM_PARENT_ID_CPU_VALUE -#define UVM_GLOBAL_ID_GPU0_VALUE UVM_PARENT_ID_GPU0_VALUE +#define UVM_ID_CPU_VALUE UVM_PARENT_ID_CPU_VALUE +#define UVM_ID_GPU0_VALUE UVM_PARENT_ID_GPU0_VALUE // Maximum number of GPUs/processors that can be represented with the id types -#define UVM_PARENT_ID_MAX_GPUS UVM_MAX_GPUS -#define UVM_PARENT_ID_MAX_PROCESSORS UVM_MAX_PROCESSORS +#define UVM_PARENT_ID_MAX_GPUS NV_MAX_DEVICES +#define UVM_PARENT_ID_MAX_PROCESSORS (UVM_PARENT_ID_MAX_GPUS + 1) #define UVM_PARENT_ID_MAX_SUB_PROCESSORS 8 -#define UVM_GLOBAL_ID_MAX_GPUS (UVM_PARENT_ID_MAX_GPUS * UVM_PARENT_ID_MAX_SUB_PROCESSORS) -#define UVM_GLOBAL_ID_MAX_PROCESSORS (UVM_GLOBAL_ID_MAX_GPUS + 1) +#define UVM_ID_MAX_GPUS (UVM_PARENT_ID_MAX_GPUS * UVM_PARENT_ID_MAX_SUB_PROCESSORS) +#define UVM_ID_MAX_PROCESSORS (UVM_ID_MAX_GPUS + 1) +#define UVM_MAX_UNIQUE_GPU_PAIRS SUM_FROM_0_TO_N(UVM_ID_MAX_GPUS - 1) #define UVM_PARENT_ID_CPU ((uvm_parent_processor_id_t) { .val = UVM_PARENT_ID_CPU_VALUE }) #define UVM_PARENT_ID_INVALID ((uvm_parent_processor_id_t) { .val = UVM_PARENT_ID_MAX_PROCESSORS }) -#define UVM_GLOBAL_ID_CPU ((uvm_global_processor_id_t) { .val = UVM_GLOBAL_ID_CPU_VALUE }) -#define UVM_GLOBAL_ID_INVALID ((uvm_global_processor_id_t) { .val = UVM_GLOBAL_ID_MAX_PROCESSORS }) +#define UVM_ID_CPU ((uvm_processor_id_t) { .val = UVM_ID_CPU_VALUE }) +#define UVM_ID_INVALID ((uvm_processor_id_t) { .val = UVM_ID_MAX_PROCESSORS }) #define UVM_PARENT_ID_CHECK_BOUNDS(id) UVM_ASSERT_MSG(id.val <= UVM_PARENT_ID_MAX_PROCESSORS, "id %u\n", id.val) -#define UVM_GLOBAL_ID_CHECK_BOUNDS(id) UVM_ASSERT_MSG(id.val <= UVM_GLOBAL_ID_MAX_PROCESSORS, "id %u\n", id.val) +#define UVM_ID_CHECK_BOUNDS(id) UVM_ASSERT_MSG(id.val <= UVM_ID_MAX_PROCESSORS, "id %u\n", id.val) static int uvm_parent_id_cmp(uvm_parent_processor_id_t id1, uvm_parent_processor_id_t id2) { @@ -318,18 +308,18 @@ static bool uvm_parent_id_equal(uvm_parent_processor_id_t id1, uvm_parent_proces return id1.val == id2.val; } -static int uvm_global_id_cmp(uvm_global_processor_id_t id1, uvm_global_processor_id_t id2) +static int uvm_id_cmp(uvm_processor_id_t id1, uvm_processor_id_t id2) { - UVM_GLOBAL_ID_CHECK_BOUNDS(id1); - UVM_GLOBAL_ID_CHECK_BOUNDS(id2); + UVM_ID_CHECK_BOUNDS(id1); + UVM_ID_CHECK_BOUNDS(id2); return UVM_CMP_DEFAULT(id1.val, id2.val); } -static bool uvm_global_id_equal(uvm_global_processor_id_t id1, uvm_global_processor_id_t id2) +static bool uvm_id_equal(uvm_processor_id_t id1, uvm_processor_id_t id2) { - UVM_GLOBAL_ID_CHECK_BOUNDS(id1); - UVM_GLOBAL_ID_CHECK_BOUNDS(id2); + UVM_ID_CHECK_BOUNDS(id1); + UVM_ID_CHECK_BOUNDS(id2); return id1.val == id2.val; } @@ -339,10 +329,10 @@ static bool uvm_global_id_equal(uvm_global_processor_id_t id1, uvm_global_proces #define UVM_PARENT_ID_IS_VALID(id) (!UVM_PARENT_ID_IS_INVALID(id)) #define UVM_PARENT_ID_IS_GPU(id) (!UVM_PARENT_ID_IS_CPU(id) && !UVM_PARENT_ID_IS_INVALID(id)) -#define UVM_GLOBAL_ID_IS_CPU(id) uvm_global_id_equal(id, UVM_GLOBAL_ID_CPU) -#define UVM_GLOBAL_ID_IS_INVALID(id) uvm_global_id_equal(id, UVM_GLOBAL_ID_INVALID) -#define UVM_GLOBAL_ID_IS_VALID(id) (!UVM_GLOBAL_ID_IS_INVALID(id)) -#define UVM_GLOBAL_ID_IS_GPU(id) (!UVM_GLOBAL_ID_IS_CPU(id) && !UVM_GLOBAL_ID_IS_INVALID(id)) +#define UVM_ID_IS_CPU(id) uvm_id_equal(id, UVM_ID_CPU) +#define UVM_ID_IS_INVALID(id) uvm_id_equal(id, UVM_ID_INVALID) +#define UVM_ID_IS_VALID(id) (!UVM_ID_IS_INVALID(id)) +#define UVM_ID_IS_GPU(id) (!UVM_ID_IS_CPU(id) && !UVM_ID_IS_INVALID(id)) static uvm_parent_processor_id_t uvm_parent_id_from_value(NvU32 val) { @@ -362,20 +352,20 @@ static uvm_parent_gpu_id_t uvm_parent_gpu_id_from_value(NvU32 val) return ret; } -static uvm_global_processor_id_t uvm_global_id_from_value(NvU32 val) +static uvm_processor_id_t uvm_id_from_value(NvU32 val) { - uvm_global_processor_id_t ret = { .val = val }; + uvm_processor_id_t ret = { .val = val }; - UVM_GLOBAL_ID_CHECK_BOUNDS(ret); + UVM_ID_CHECK_BOUNDS(ret); return ret; } -static uvm_global_gpu_id_t uvm_global_gpu_id_from_value(NvU32 val) +static uvm_gpu_id_t uvm_gpu_id_from_value(NvU32 val) { - uvm_global_gpu_id_t ret = uvm_global_id_from_value(val); + uvm_gpu_id_t ret = uvm_id_from_value(val); - UVM_ASSERT(!UVM_GLOBAL_ID_IS_CPU(ret)); + UVM_ASSERT(!UVM_ID_IS_CPU(ret)); return ret; } @@ -407,28 +397,28 @@ static uvm_parent_gpu_id_t uvm_parent_gpu_id_next(uvm_parent_gpu_id_t id) return id; } -// Same as uvm_parent_gpu_id_from_index but for uvm_global_processor_id_t -static uvm_global_gpu_id_t uvm_global_gpu_id_from_index(NvU32 index) +// Same as uvm_parent_gpu_id_from_index but for uvm_processor_id_t +static uvm_gpu_id_t uvm_gpu_id_from_index(NvU32 index) { - return uvm_global_gpu_id_from_value(index + UVM_GLOBAL_ID_GPU0_VALUE); + return uvm_gpu_id_from_value(index + UVM_ID_GPU0_VALUE); } -static uvm_global_processor_id_t uvm_global_id_next(uvm_global_processor_id_t id) +static uvm_processor_id_t uvm_id_next(uvm_processor_id_t id) { ++id.val; - UVM_GLOBAL_ID_CHECK_BOUNDS(id); + UVM_ID_CHECK_BOUNDS(id); return id; } -static uvm_global_gpu_id_t uvm_global_gpu_id_next(uvm_global_gpu_id_t id) +static uvm_gpu_id_t uvm_gpu_id_next(uvm_gpu_id_t id) { - UVM_ASSERT(UVM_GLOBAL_ID_IS_GPU(id)); + UVM_ASSERT(UVM_ID_IS_GPU(id)); ++id.val; - UVM_GLOBAL_ID_CHECK_BOUNDS(id); + UVM_ID_CHECK_BOUNDS(id); return id; } @@ -443,10 +433,10 @@ static NvU32 uvm_parent_id_value(uvm_parent_processor_id_t id) } // This function returns the numerical value within -// [0, UVM_GLOBAL_ID_MAX_PROCESSORS) of the given processor id -static NvU32 uvm_global_id_value(uvm_global_processor_id_t id) +// [0, UVM_ID_MAX_PROCESSORS) of the given processor id +static NvU32 uvm_id_value(uvm_processor_id_t id) { - UVM_ASSERT(UVM_GLOBAL_ID_IS_VALID(id)); + UVM_ASSERT(UVM_ID_IS_VALID(id)); return id.val; } @@ -461,122 +451,124 @@ static NvU32 uvm_parent_id_gpu_index(uvm_parent_gpu_id_t id) } // This function returns the index of the given GPU id within the GPU id space -// [0, UVM_GLOBAL_ID_MAX_GPUS) -static NvU32 uvm_global_id_gpu_index(const uvm_global_gpu_id_t id) +// [0, UVM_ID_MAX_GPUS) +static NvU32 uvm_id_gpu_index(const uvm_gpu_id_t id) { - UVM_ASSERT(UVM_GLOBAL_ID_IS_GPU(id)); + UVM_ASSERT(UVM_ID_IS_GPU(id)); - return id.val - UVM_GLOBAL_ID_GPU0_VALUE; + return id.val - UVM_ID_GPU0_VALUE; } -static NvU32 uvm_global_id_gpu_index_from_parent_gpu_id(const uvm_parent_gpu_id_t id) +static NvU32 uvm_id_gpu_index_from_parent_gpu_id(const uvm_parent_gpu_id_t id) { UVM_ASSERT(UVM_PARENT_ID_IS_GPU(id)); return uvm_parent_id_gpu_index(id) * UVM_PARENT_ID_MAX_SUB_PROCESSORS; } -static NvU32 uvm_parent_id_gpu_index_from_global_gpu_id(const uvm_global_gpu_id_t id) +// This function returns the numerical value of the parent processor ID from the +// given processor id. +static NvU32 uvm_parent_id_value_from_processor_id(const uvm_processor_id_t id) { - UVM_ASSERT(UVM_GLOBAL_ID_IS_GPU(id)); + if (UVM_ID_IS_CPU(id)) + return UVM_PARENT_ID_CPU_VALUE; - return uvm_global_id_gpu_index(id) / UVM_PARENT_ID_MAX_SUB_PROCESSORS; + return (uvm_id_gpu_index(id) / UVM_PARENT_ID_MAX_SUB_PROCESSORS) + UVM_PARENT_ID_GPU0_VALUE; } -static uvm_global_gpu_id_t uvm_global_gpu_id_from_parent_gpu_id(const uvm_parent_gpu_id_t id) +static NvU32 uvm_parent_id_gpu_index_from_gpu_id(const uvm_gpu_id_t id) { - UVM_ASSERT(UVM_PARENT_ID_IS_GPU(id)); + UVM_ASSERT(UVM_ID_IS_GPU(id)); - return uvm_global_gpu_id_from_index(uvm_global_id_gpu_index_from_parent_gpu_id(id)); + return uvm_id_gpu_index(id) / UVM_PARENT_ID_MAX_SUB_PROCESSORS; } -static uvm_global_gpu_id_t uvm_global_gpu_id_from_parent_index(NvU32 index) +static uvm_gpu_id_t uvm_gpu_id_from_parent_gpu_id(const uvm_parent_gpu_id_t id) { - UVM_ASSERT(index < UVM_PARENT_ID_MAX_GPUS); + UVM_ASSERT(UVM_PARENT_ID_IS_GPU(id)); - return uvm_global_gpu_id_from_parent_gpu_id(uvm_parent_gpu_id_from_value(index + UVM_GLOBAL_ID_GPU0_VALUE)); + return uvm_gpu_id_from_index(uvm_id_gpu_index_from_parent_gpu_id(id)); } -static uvm_global_gpu_id_t uvm_global_gpu_id_from_sub_processor_index(const uvm_parent_gpu_id_t id, NvU32 sub_index) +static uvm_gpu_id_t uvm_gpu_id_from_sub_processor_index(NvU32 index, NvU32 sub_index) { - NvU32 index; - + UVM_ASSERT(index < UVM_PARENT_ID_MAX_GPUS); UVM_ASSERT(sub_index < UVM_PARENT_ID_MAX_SUB_PROCESSORS); - index = uvm_global_id_gpu_index_from_parent_gpu_id(id) + sub_index; - return uvm_global_gpu_id_from_index(index); + return uvm_gpu_id_from_index(index * UVM_PARENT_ID_MAX_SUB_PROCESSORS + sub_index); } -static uvm_parent_gpu_id_t uvm_parent_gpu_id_from_global_gpu_id(const uvm_global_gpu_id_t id) +static uvm_parent_gpu_id_t uvm_parent_gpu_id_from_gpu_id(const uvm_gpu_id_t id) { - UVM_ASSERT(UVM_GLOBAL_ID_IS_GPU(id)); + UVM_ASSERT(UVM_ID_IS_GPU(id)); - return uvm_parent_gpu_id_from_index(uvm_parent_id_gpu_index_from_global_gpu_id(id)); + return uvm_parent_gpu_id_from_index(uvm_parent_id_gpu_index_from_gpu_id(id)); } -static NvU32 uvm_global_id_sub_processor_index(const uvm_global_gpu_id_t id) +static NvU32 uvm_id_sub_processor_index(const uvm_gpu_id_t id) { - return uvm_global_id_gpu_index(id) % UVM_PARENT_ID_MAX_SUB_PROCESSORS; + return uvm_id_gpu_index(id) % UVM_PARENT_ID_MAX_SUB_PROCESSORS; } -UVM_PROCESSOR_MASK(uvm_processor_mask_t, \ - uvm_processor_mask, \ +UVM_PROCESSOR_MASK(uvm_parent_processor_mask_t, \ + uvm_parent_processor_mask, \ UVM_PARENT_ID_MAX_PROCESSORS, \ uvm_parent_processor_id_t, \ uvm_parent_id_from_value) -UVM_PROCESSOR_MASK(uvm_global_processor_mask_t, \ - uvm_global_processor_mask, \ - UVM_GLOBAL_ID_MAX_PROCESSORS, \ - uvm_global_processor_id_t, \ - uvm_global_id_from_value) - -// Like uvm_processor_mask_subset but ignores the CPU in both masks. Returns -// whether the GPUs in subset are a subset of the GPUs in mask. -static bool uvm_processor_mask_gpu_subset(const uvm_processor_mask_t *subset, const uvm_processor_mask_t *mask) -{ - uvm_processor_mask_t subset_gpus; - uvm_processor_mask_copy(&subset_gpus, subset); - uvm_processor_mask_clear(&subset_gpus, UVM_PARENT_ID_CPU); - return uvm_processor_mask_subset(&subset_gpus, mask); -} - -#define for_each_id_in_mask(id, mask) \ - for ((id) = uvm_processor_mask_find_first_id(mask); \ +UVM_PROCESSOR_MASK(uvm_processor_mask_t, \ + uvm_processor_mask, \ + UVM_ID_MAX_PROCESSORS, \ + uvm_processor_id_t, \ + uvm_id_from_value) + +// Like uvm_processor_mask_subset() but ignores the CPU in the subset mask. +// Returns whether the GPUs in subset are a subset of the GPUs in mask. +bool uvm_processor_mask_gpu_subset(const uvm_processor_mask_t *subset, + const uvm_processor_mask_t *mask); + +// Compress a uvm_processor_mask_t down to a uvm_parent_processor_mask_t +// by only copying the first subprocessor bit and ignoring the CPU bit. +void uvm_parent_gpus_from_processor_mask(uvm_parent_processor_mask_t *parent_mask, + const uvm_processor_mask_t *mask); + +#define for_each_parent_id_in_mask(id, mask) \ + for ((id) = uvm_parent_processor_mask_find_first_id(mask); \ UVM_PARENT_ID_IS_VALID(id); \ - (id) = uvm_processor_mask_find_next_id((mask), uvm_parent_id_next(id))) + (id) = uvm_parent_processor_mask_find_next_id((mask), uvm_parent_id_next(id))) -#define for_each_gpu_id_in_mask(gpu_id, mask) \ - for ((gpu_id) = uvm_processor_mask_find_first_gpu_id((mask)); \ +#define for_each_parent_gpu_id_in_mask(gpu_id, mask) \ + for ((gpu_id) = uvm_parent_processor_mask_find_first_gpu_id((mask)); \ UVM_PARENT_ID_IS_VALID(gpu_id); \ - (gpu_id) = uvm_processor_mask_find_next_id((mask), uvm_parent_gpu_id_next(gpu_id))) + (gpu_id) = uvm_parent_processor_mask_find_next_id((mask), uvm_parent_gpu_id_next(gpu_id))) -#define for_each_global_id_in_mask(id, mask) \ - for ((id) = uvm_global_processor_mask_find_first_id(mask); \ - UVM_GLOBAL_ID_IS_VALID(id); \ - (id) = uvm_global_processor_mask_find_next_id((mask), uvm_global_id_next(id))) +#define for_each_id_in_mask(id, mask) \ + for ((id) = uvm_processor_mask_find_first_id(mask); \ + UVM_ID_IS_VALID(id); \ + (id) = uvm_processor_mask_find_next_id((mask), uvm_id_next(id))) -#define for_each_global_gpu_id_in_mask(gpu_id, mask) \ - for ((gpu_id) = uvm_global_processor_mask_find_first_gpu_id((mask)); \ - UVM_GLOBAL_ID_IS_VALID(gpu_id); \ - (gpu_id) = uvm_global_processor_mask_find_next_id((mask), uvm_global_gpu_id_next(gpu_id))) +#define for_each_gpu_id_in_mask(gpu_id, mask) \ + for ((gpu_id) = uvm_processor_mask_find_first_gpu_id((mask)); \ + UVM_ID_IS_VALID(gpu_id); \ + (gpu_id) = uvm_processor_mask_find_next_id((mask), uvm_gpu_id_next(gpu_id))) -// Helper to iterate over all valid gpu ids -#define for_each_gpu_id(i) \ +// Helper to iterate over all valid parent gpu ids. +#define for_each_parent_gpu_id(i) \ for (i = uvm_parent_gpu_id_from_value(UVM_PARENT_ID_GPU0_VALUE); UVM_PARENT_ID_IS_VALID(i); i = uvm_parent_gpu_id_next(i)) -#define for_each_global_gpu_id(i) \ - for (i = uvm_global_gpu_id_from_value(UVM_GLOBAL_ID_GPU0_VALUE); UVM_GLOBAL_ID_IS_VALID(i); i = uvm_global_gpu_id_next(i)) -#define for_each_global_sub_processor_id_in_gpu(id, i) \ - for (i = uvm_global_gpu_id_from_parent_gpu_id(id); \ - UVM_GLOBAL_ID_IS_VALID(i) && \ - (uvm_global_id_value(i) < uvm_global_id_value(uvm_global_gpu_id_from_parent_gpu_id(id)) + UVM_PARENT_ID_MAX_SUB_PROCESSORS); \ - i = uvm_global_gpu_id_next(i)) +// Helper to iterate over all valid gpu ids. +#define for_each_gpu_id(i) \ + for (i = uvm_gpu_id_from_value(UVM_ID_GPU0_VALUE); UVM_ID_IS_VALID(i); i = uvm_gpu_id_next(i)) -// Helper to iterate over all valid gpu ids -#define for_each_processor_id(i) for (i = UVM_PARENT_ID_CPU; UVM_PARENT_ID_IS_VALID(i); i = uvm_parent_id_next(i)) +// Helper to iterate over all gpu ids in a given parent id. +#define for_each_sub_processor_id_in_parent_gpu(i, id) \ + for (i = uvm_gpu_id_from_parent_gpu_id(id); \ + UVM_ID_IS_VALID(i) && \ + (uvm_id_value(i) < uvm_id_value(uvm_gpu_id_from_parent_gpu_id(id)) + UVM_PARENT_ID_MAX_SUB_PROCESSORS); \ + i = uvm_gpu_id_next(i)) -#define for_each_global_id(i) for (i = UVM_GLOBAL_ID_CPU; UVM_GLOBAL_ID_IS_VALID(i); i = uvm_global_id_next(i)) +// Helper to iterate over all valid processor ids. +#define for_each_id(i) for (i = UVM_ID_CPU; UVM_ID_IS_VALID(i); i = uvm_id_next(i)) // Find the node in mask with the shorted distance (as returned by // node_distance) for src. @@ -593,89 +585,32 @@ int uvm_find_closest_node_mask(int src, const nodemask_t *mask); #define for_each_possible_uvm_node(nid) for_each_node_mask((nid), node_possible_map) -static bool uvm_processor_uuid_eq(const NvProcessorUuid *uuid1, const NvProcessorUuid *uuid2) +// Compare two NUMA node IDs for equality. +// The main purpose of this helper is to correctly compare +// in situations when the system has only a single NUMA node +// (which is also the case when NUMA support is disabled). +bool uvm_numa_id_eq(int nid0, int nid1); + +static bool uvm_uuid_eq(const NvProcessorUuid *uuid0, const NvProcessorUuid *uuid1) { - return memcmp(uuid1, uuid2, sizeof(*uuid1)) == 0; + return memcmp(uuid0, uuid1, sizeof(*uuid0)) == 0; } // Copies a UUID from source (src) to destination (dst). -static void uvm_processor_uuid_copy(NvProcessorUuid *dst, const NvProcessorUuid *src) +static void uvm_uuid_copy(NvProcessorUuid *dst, const NvProcessorUuid *src) { memcpy(dst, src, sizeof(*dst)); } -// TODO: Bug 4195538: [uvm][multi-SMC] Get UVM internal data structures ready to -// meet multi-SMC requirements. Temporary aliases, they must be removed once -// the data structures are converted. -typedef uvm_parent_processor_id_t uvm_processor_id_t; -typedef uvm_parent_gpu_id_t uvm_gpu_id_t; - -#define UVM_ID_CPU_VALUE UVM_PARENT_ID_CPU_VALUE -#define UVM_ID_GPU0_VALUE UVM_PARENT_ID_GPU0_VALUE -#define UVM_ID_MAX_GPUS UVM_PARENT_ID_MAX_GPUS -#define UVM_ID_MAX_PROCESSORS UVM_PARENT_ID_MAX_PROCESSORS -#define UVM_ID_MAX_SUB_PROCESSORS UVM_PARENT_ID_MAX_SUB_PROCESSORS -#define UVM_ID_CPU UVM_PARENT_ID_CPU -#define UVM_ID_INVALID UVM_PARENT_ID_INVALID - -static int uvm_id_cmp(uvm_parent_processor_id_t id1, uvm_parent_processor_id_t id2) +static inline NvBool uvm_uuid_is_cpu(const NvProcessorUuid *uuid) { - return UVM_CMP_DEFAULT(id1.val, id2.val); -} - -static bool uvm_id_equal(uvm_parent_processor_id_t id1, uvm_parent_processor_id_t id2) -{ - return uvm_parent_id_equal(id1, id2); + return memcmp(uuid, &NV_PROCESSOR_UUID_CPU_DEFAULT, sizeof(*uuid)) == 0; } -#define UVM_ID_IS_CPU(id) uvm_id_equal(id, UVM_ID_CPU) -#define UVM_ID_IS_INVALID(id) uvm_id_equal(id, UVM_ID_INVALID) -#define UVM_ID_IS_VALID(id) (!UVM_ID_IS_INVALID(id)) -#define UVM_ID_IS_GPU(id) (!UVM_ID_IS_CPU(id) && !UVM_ID_IS_INVALID(id)) - -static uvm_parent_gpu_id_t uvm_gpu_id_from_value(NvU32 val) -{ - return uvm_parent_gpu_id_from_value(val); -} - -static NvU32 uvm_id_value(uvm_parent_processor_id_t id) -{ - return uvm_parent_id_value(id); -} - -static NvU32 uvm_id_gpu_index(uvm_parent_gpu_id_t id) -{ - return uvm_parent_id_gpu_index(id); -} - -static NvU32 uvm_id_gpu_index_from_global_gpu_id(const uvm_global_gpu_id_t id) -{ - return uvm_parent_id_gpu_index_from_global_gpu_id(id); -} - -static uvm_parent_gpu_id_t uvm_gpu_id_from_index(NvU32 index) -{ - return uvm_parent_gpu_id_from_index(index); -} - -static uvm_parent_gpu_id_t uvm_gpu_id_next(uvm_parent_gpu_id_t id) -{ - return uvm_parent_gpu_id_next(id); -} - -static uvm_parent_gpu_id_t uvm_gpu_id_from_global_gpu_id(const uvm_global_gpu_id_t id) -{ - return uvm_parent_gpu_id_from_global_gpu_id(id); -} - -static NvU32 uvm_global_id_gpu_index_from_gpu_id(const uvm_parent_gpu_id_t id) -{ - return uvm_global_id_gpu_index_from_parent_gpu_id(id); -} - -static uvm_global_gpu_id_t uvm_global_gpu_id_from_gpu_id(const uvm_parent_gpu_id_t id) -{ - return uvm_global_gpu_id_from_parent_gpu_id(id); -} +// Dynamic uvm_processor_mask_t object allocation/maintenance. +NV_STATUS uvm_processor_mask_cache_init(void); +void uvm_processor_mask_cache_exit(void); +uvm_processor_mask_t *uvm_processor_mask_cache_alloc(void); +void uvm_processor_mask_cache_free(uvm_processor_mask_t *mask); #endif diff --git a/kernel-open/nvidia-uvm/uvm_push.c b/kernel-open/nvidia-uvm/uvm_push.c index 6bc040b663..4445e520ee 100644 --- a/kernel-open/nvidia-uvm/uvm_push.c +++ b/kernel-open/nvidia-uvm/uvm_push.c @@ -244,6 +244,9 @@ NV_STATUS __uvm_push_begin_acquire_with_info(uvm_channel_manager_t *manager, status = push_begin_acquire_with_info(channel, tracker, push, filename, function, line, format, args); va_end(args); + if (status != NV_OK) + uvm_channel_release(channel, 1); + return status; } @@ -267,6 +270,9 @@ NV_STATUS __uvm_push_begin_acquire_on_channel_with_info(uvm_channel_t *channel, status = push_begin_acquire_with_info(channel, tracker, push, filename, function, line, format, args); va_end(args); + if (status != NV_OK) + uvm_channel_release(channel, 1); + return status; } diff --git a/kernel-open/nvidia-uvm/uvm_push.h b/kernel-open/nvidia-uvm/uvm_push.h index e8ce06de79..b94af0b372 100644 --- a/kernel-open/nvidia-uvm/uvm_push.h +++ b/kernel-open/nvidia-uvm/uvm_push.h @@ -334,6 +334,14 @@ static void uvm_push_set_flag(uvm_push_t *push, uvm_push_flag_t flag) __set_bit(flag, push->flags); } +// Check if a push flag is set +static bool uvm_push_test_flag(uvm_push_t *push, uvm_push_flag_t flag) +{ + UVM_ASSERT_MSG(flag < UVM_PUSH_FLAG_COUNT, "flag %u\n", (unsigned)flag); + + return test_bit(flag, push->flags); +} + // Get and reset (if set) a push flag static bool uvm_push_get_and_reset_flag(uvm_push_t *push, uvm_push_flag_t flag) { diff --git a/kernel-open/nvidia-uvm/uvm_push_test.c b/kernel-open/nvidia-uvm/uvm_push_test.c index 67fb55d1fc..dafe49205b 100644 --- a/kernel-open/nvidia-uvm/uvm_push_test.c +++ b/kernel-open/nvidia-uvm/uvm_push_test.c @@ -50,9 +50,7 @@ static NvU32 get_push_begin_size(uvm_channel_t *channel) // This is the storage required by a semaphore release. static NvU32 get_push_end_min_size(uvm_channel_t *channel) { - uvm_gpu_t *gpu = uvm_channel_get_gpu(channel); - - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { if (uvm_channel_is_ce(channel)) { // Space (in bytes) used by uvm_push_end() on a CE channel when // the Confidential Computing feature is enabled. @@ -132,11 +130,11 @@ static NV_STATUS test_push_end_size(uvm_va_space_t *va_space) NvU32 push_end_size_expected[2]; // SEC2 is only available when Confidential Computing is enabled - if ((type == UVM_CHANNEL_TYPE_SEC2) && !uvm_conf_computing_mode_enabled(gpu)) + if ((type == UVM_CHANNEL_TYPE_SEC2) && !g_uvm_global.conf_computing_enabled) continue; // WLC is only available when Confidential Computing is enabled - if ((type == UVM_CHANNEL_TYPE_WLC) && !uvm_conf_computing_mode_enabled(gpu)) + if ((type == UVM_CHANNEL_TYPE_WLC) && !g_uvm_global.conf_computing_enabled) continue; // LCIC doesn't accept pushes @@ -195,7 +193,7 @@ static NV_STATUS test_push_inline_data_gpu(uvm_gpu_t *gpu) // TODO: Bug 3839176: test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; status = uvm_mem_alloc_sysmem_and_map_cpu_kernel(UVM_PUSH_INLINE_DATA_MAX_SIZE, current->mm, &mem); @@ -305,9 +303,7 @@ static NV_STATUS test_concurrent_pushes(uvm_va_space_t *va_space) // the start of a push cannot be reserved again until that push ends. The // test is waived, because the number of pushes it starts per pool exceeds // the number of channels in the pool, so it would block indefinitely. - gpu = uvm_va_space_find_first_gpu(va_space); - - if ((gpu != NULL) && uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; uvm_tracker_init(&tracker); @@ -384,7 +380,7 @@ static NV_STATUS test_push_interleaving_on_gpu(uvm_gpu_t* gpu) // TODO: Bug 3839176: test is waived on Confidential Computing because // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; // This test issues virtual memcopies/memsets, which in SR-IOV heavy cannot @@ -602,13 +598,12 @@ static NV_STATUS test_max_pushes_on_gpu(uvm_gpu_t *gpu) TEST_CHECK_GOTO(status == NV_OK, done); uvm_gpu_semaphore_set_payload(&sema, 0); - if (uvm_conf_computing_mode_enabled(gpu)) { - // Use SEC2 channel when Confidential Compute is enabled - // since all other channel types need extra space for - // work launch, and the channel type really doesn't - // matter for this test. + + // Use SEC2 channel when Confidential Compute is enabled since all other + // channel types need extra space for work launch, and the channel type + // really doesn't matter for this test. + if (g_uvm_global.conf_computing_enabled) channel_type = UVM_CHANNEL_TYPE_SEC2; - } // Need to wait for all channels to completely idle so that the pushbuffer // is in completely idle state when we begin. @@ -681,13 +676,11 @@ static NV_STATUS test_idle_chunks_on_gpu(uvm_gpu_t *gpu) NvU32 i; uvm_channel_type_t channel_type = UVM_CHANNEL_TYPE_GPU_INTERNAL; - if (uvm_conf_computing_mode_enabled(gpu)) { - // Use SEC2 channel when Confidential Compute is enabled - // since all other channel types need extra space for - // work launch, and the channel type really doesn't - // matter for this test. + // Use SEC2 channel when Confidential Compute is enabled since all other + // channel types need extra space for work launch, and the channel type + // really doesn't matter for this test. + if (g_uvm_global.conf_computing_enabled) channel_type = UVM_CHANNEL_TYPE_SEC2; - } uvm_tracker_init(&tracker); @@ -880,17 +873,17 @@ static NV_STATUS test_push_gpu_to_gpu(uvm_va_space_t *va_space) NvU32 i; NV_STATUS status; uvm_gpu_t *gpu, *gpu_a, *gpu_b; - uvm_mem_t *mem[UVM_ID_MAX_PROCESSORS] = {NULL}; + uvm_mem_t **mem; NvU32 *host_ptr; const size_t size = 1024 * 1024; bool waive = true; - for_each_va_space_gpu(gpu_a, va_space) { + // TODO: Bug 3839176: the test is waived on Confidential Computing because + // it assumes that GPU can access system memory without using encryption. + if (g_uvm_global.conf_computing_enabled) + return NV_OK; - // TODO: Bug 3839176: the test is waived on Confidential Computing because - // it assumes that GPU can access system memory without using encryption. - if (uvm_conf_computing_mode_enabled(gpu_a)) - return NV_OK; + for_each_va_space_gpu(gpu_a, va_space) { for_each_va_space_gpu(gpu_b, va_space) { if (can_do_peer_copies(va_space, gpu_a, gpu_b)) { waive = false; @@ -902,6 +895,10 @@ static NV_STATUS test_push_gpu_to_gpu(uvm_va_space_t *va_space) if (waive) return NV_OK; + mem = uvm_kvmalloc_zero(sizeof(*mem) * UVM_ID_MAX_PROCESSORS); + if (!mem) + return NV_ERR_NO_MEMORY; + // Alloc and initialize host buffer status = uvm_mem_alloc_sysmem_and_map_cpu_kernel(size, current->mm, &mem[UVM_ID_CPU_VALUE]); TEST_CHECK_GOTO(status == NV_OK, done); @@ -969,6 +966,7 @@ static NV_STATUS test_push_gpu_to_gpu(uvm_va_space_t *va_space) uvm_mem_free(mem[uvm_id_value(gpu->id)]); uvm_mem_free(mem[UVM_ID_CPU_VALUE]); + uvm_kvfree(mem); return status; } diff --git a/kernel-open/nvidia-uvm/uvm_pushbuffer.c b/kernel-open/nvidia-uvm/uvm_pushbuffer.c index 492b1ff3bc..01abcdd110 100644 --- a/kernel-open/nvidia-uvm/uvm_pushbuffer.c +++ b/kernel-open/nvidia-uvm/uvm_pushbuffer.c @@ -121,7 +121,7 @@ NV_STATUS uvm_pushbuffer_create(uvm_channel_manager_t *channel_manager, uvm_push if (status != NV_OK) goto error; - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { UVM_ASSERT(channel_manager->conf.pushbuffer_loc == UVM_BUFFER_LOCATION_SYS); // Move the above allocation to unprotected_sysmem @@ -137,7 +137,6 @@ NV_STATUS uvm_pushbuffer_create(uvm_channel_manager_t *channel_manager, uvm_push goto error; } - status = uvm_rm_mem_alloc(gpu, UVM_RM_MEM_TYPE_GPU, UVM_PUSHBUFFER_SIZE, @@ -263,12 +262,12 @@ static char *get_base_cpu_va(uvm_pushbuffer_t *pushbuffer) // Confidential Computing pushes are assembled in protected sysmem // and safely (through encrypt/decrypt) moved to protected vidmem. // Or signed and moved to unprotected sysmem. - if (uvm_conf_computing_mode_enabled(pushbuffer->channel_manager->gpu)) { - // Align protected sysmem base to 4kB. This should be enough to give - // the same alignment behaviour for inline buffers as the other two - // backing memory locations. + // + // The protected sysmem base is aligned to 4kB. This is enough to give + // the same alignment behaviour for inline buffers as the other two + // backing memory locations. + if (g_uvm_global.conf_computing_enabled) return (char*)(UVM_ALIGN_UP((uintptr_t)pushbuffer->memory_protected_sysmem, UVM_PAGE_SIZE_4K)); - } return (char *)uvm_rm_mem_get_cpu_va(pushbuffer->memory); } @@ -682,7 +681,7 @@ NvU64 uvm_pushbuffer_get_gpu_va_base(uvm_pushbuffer_t *pushbuffer) NvU64 uvm_pushbuffer_get_sec2_gpu_va_base(uvm_pushbuffer_t *pushbuffer) { - UVM_ASSERT(uvm_conf_computing_mode_enabled(pushbuffer->channel_manager->gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); return uvm_rm_mem_get_gpu_uvm_va(pushbuffer->memory_unprotected_sysmem, pushbuffer->channel_manager->gpu); } diff --git a/kernel-open/nvidia-uvm/uvm_range_group.c b/kernel-open/nvidia-uvm/uvm_range_group.c index 0af1673df1..0509c62c99 100644 --- a/kernel-open/nvidia-uvm/uvm_range_group.c +++ b/kernel-open/nvidia-uvm/uvm_range_group.c @@ -183,6 +183,10 @@ static NV_STATUS uvm_range_group_va_range_migrate_block_locked(uvm_va_range_t *v NV_STATUS tracker_status; uvm_gpu_id_t gpu_id; uvm_processor_mask_t map_mask; + uvm_va_policy_t *policy = uvm_va_range_get_policy(va_range); + + // Set the migration CPU NUMA node from the policy. + va_block_context->make_resident.dest_nid = policy->preferred_nid; // Unmapping UVM_ID_CPU is guaranteed to never fail status = uvm_va_block_unmap(va_block, va_block_context, UVM_ID_CPU, region, NULL, NULL); @@ -192,7 +196,7 @@ static NV_STATUS uvm_range_group_va_range_migrate_block_locked(uvm_va_range_t *v status = uvm_va_block_make_resident_read_duplicate(va_block, va_block_retry, va_block_context, - uvm_va_range_get_policy(va_range)->preferred_location, + policy->preferred_location, region, NULL, NULL, @@ -202,7 +206,7 @@ static NV_STATUS uvm_range_group_va_range_migrate_block_locked(uvm_va_range_t *v status = uvm_va_block_make_resident(va_block, va_block_retry, va_block_context, - uvm_va_range_get_policy(va_range)->preferred_location, + policy->preferred_location, region, NULL, NULL, @@ -226,7 +230,7 @@ static NV_STATUS uvm_range_group_va_range_migrate_block_locked(uvm_va_range_t *v // 2- Map faultable SetAccessedBy GPUs. uvm_processor_mask_and(&map_mask, &uvm_va_range_get_policy(va_range)->accessed_by, - &va_range->va_space->can_access[uvm_id_value(uvm_va_range_get_policy(va_range)->preferred_location)]); + &va_range->va_space->can_access[uvm_id_value(policy->preferred_location)]); uvm_processor_mask_andnot(&map_mask, &map_mask, &va_range->uvm_lite_gpus); for_each_gpu_id_in_mask(gpu_id, &map_mask) { diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem.c b/kernel-open/nvidia-uvm/uvm_rm_mem.c index a88dcff484..9a5678393d 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -30,7 +30,7 @@ bool uvm_rm_mem_mapped_on_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) { - return uvm_global_processor_mask_test(&rm_mem->mapped_on, gpu->global_id); + return uvm_processor_mask_test(&rm_mem->mapped_on, gpu->id); } bool uvm_rm_mem_mapped_on_gpu_proxy(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) @@ -38,68 +38,68 @@ bool uvm_rm_mem_mapped_on_gpu_proxy(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) if (rm_mem->proxy_vas == NULL) return false; - if (rm_mem->proxy_vas[uvm_global_id_value(gpu->global_id)] == 0) + if (rm_mem->proxy_vas[uvm_id_value(gpu->id)] == 0) return false; UVM_ASSERT(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); - UVM_ASSERT(uvm_gpu_uses_proxy_channel_pool(gpu)); + UVM_ASSERT(uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)); return true; } bool uvm_rm_mem_mapped_on_cpu(uvm_rm_mem_t *rm_mem) { - return uvm_global_processor_mask_test(&rm_mem->mapped_on, UVM_GLOBAL_ID_CPU); + return uvm_processor_mask_test(&rm_mem->mapped_on, UVM_ID_CPU); } static void rm_mem_set_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 va) { - rm_mem->vas[uvm_global_id_value(gpu->global_id)] = va; - uvm_global_processor_mask_set(&rm_mem->mapped_on, gpu->global_id); + rm_mem->vas[uvm_id_value(gpu->id)] = va; + uvm_processor_mask_set(&rm_mem->mapped_on, gpu->id); } static void rm_mem_set_gpu_proxy_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, NvU64 va) { - rm_mem->proxy_vas[uvm_global_id_value(gpu->global_id)] = va; + rm_mem->proxy_vas[uvm_id_value(gpu->id)] = va; } static void rm_mem_set_cpu_va(uvm_rm_mem_t *rm_mem, void *va) { - rm_mem->vas[UVM_GLOBAL_ID_CPU_VALUE] = (uintptr_t) va; - uvm_global_processor_mask_set(&rm_mem->mapped_on, UVM_GLOBAL_ID_CPU); + rm_mem->vas[UVM_ID_CPU_VALUE] = (uintptr_t) va; + uvm_processor_mask_set(&rm_mem->mapped_on, UVM_ID_CPU); } static void rm_mem_clear_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) { UVM_ASSERT(!uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); - uvm_global_processor_mask_clear(&rm_mem->mapped_on, gpu->global_id); - rm_mem->vas[uvm_global_id_value(gpu->global_id)] = 0; + uvm_processor_mask_clear(&rm_mem->mapped_on, gpu->id); + rm_mem->vas[uvm_id_value(gpu->id)] = 0; } static void rm_mem_clear_gpu_proxy_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) { - rm_mem->proxy_vas[uvm_global_id_value(gpu->global_id)] = 0; + rm_mem->proxy_vas[uvm_id_value(gpu->id)] = 0; } static void rm_mem_clear_cpu_va(uvm_rm_mem_t *rm_mem) { - uvm_global_processor_mask_clear(&rm_mem->mapped_on, UVM_GLOBAL_ID_CPU); - rm_mem->vas[UVM_GLOBAL_ID_CPU_VALUE] = 0; + uvm_processor_mask_clear(&rm_mem->mapped_on, UVM_ID_CPU); + rm_mem->vas[UVM_ID_CPU_VALUE] = 0; } NvU64 uvm_rm_mem_get_gpu_uvm_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) { UVM_ASSERT_MSG(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu), "GPU %s\n", uvm_gpu_name(gpu)); - return rm_mem->vas[uvm_global_id_value(gpu->global_id)]; + return rm_mem->vas[uvm_id_value(gpu->id)]; } NvU64 uvm_rm_mem_get_gpu_proxy_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) { UVM_ASSERT(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); - return rm_mem->proxy_vas[uvm_global_id_value(gpu->global_id)]; + return rm_mem->proxy_vas[uvm_id_value(gpu->id)]; } uvm_gpu_address_t uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bool is_proxy_va_space) @@ -108,7 +108,8 @@ uvm_gpu_address_t uvm_rm_mem_get_gpu_va(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu, bo gpu_va.aperture = UVM_APERTURE_MAX; gpu_va.is_virtual = true; - if (uvm_conf_computing_mode_enabled(gpu) && (rm_mem->type == UVM_RM_MEM_TYPE_SYS)) + + if (g_uvm_global.conf_computing_enabled && (rm_mem->type == UVM_RM_MEM_TYPE_SYS)) gpu_va.is_unprotected = true; if (is_proxy_va_space) @@ -123,7 +124,7 @@ void *uvm_rm_mem_get_cpu_va(uvm_rm_mem_t *rm_mem) { UVM_ASSERT(uvm_rm_mem_mapped_on_cpu(rm_mem)); - return (void *)(uintptr_t)rm_mem->vas[UVM_GLOBAL_ID_CPU_VALUE]; + return (void *)(uintptr_t)rm_mem->vas[UVM_ID_CPU_VALUE]; } static NV_STATUS rm_mem_map_gpu_proxy(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) @@ -135,7 +136,7 @@ static NV_STATUS rm_mem_map_gpu_proxy(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) UVM_ASSERT(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); - if (!uvm_gpu_uses_proxy_channel_pool(gpu)) + if (!uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)) return NV_OK; if (uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)) @@ -208,7 +209,7 @@ NV_STATUS uvm_rm_mem_alloc(uvm_gpu_t *gpu, if (rm_mem == NULL) return NV_ERR_NO_MEMORY; - if (!uvm_conf_computing_mode_enabled(gpu) || type == UVM_RM_MEM_TYPE_SYS) + if (!g_uvm_global.conf_computing_enabled || type == UVM_RM_MEM_TYPE_SYS) alloc_info.bUnprotected = NV_TRUE; alloc_info.alignment = gpu_alignment; @@ -255,10 +256,11 @@ NV_STATUS uvm_rm_mem_map_cpu(uvm_rm_mem_t *rm_mem) if (uvm_rm_mem_mapped_on_cpu(rm_mem)) return NV_OK; + if (g_uvm_global.conf_computing_enabled) + UVM_ASSERT(rm_mem->type == UVM_RM_MEM_TYPE_SYS); + gpu = rm_mem->gpu_owner; gpu_va = uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu); - if (uvm_conf_computing_mode_enabled(gpu)) - UVM_ASSERT(rm_mem->type == UVM_RM_MEM_TYPE_SYS); status = uvm_rm_locked_call(nvUvmInterfaceMemoryCpuMap(gpu->rm_address_space, gpu_va, @@ -357,7 +359,7 @@ void uvm_rm_mem_unmap_gpu(uvm_rm_mem_t *rm_mem, uvm_gpu_t *gpu) void uvm_rm_mem_free(uvm_rm_mem_t *rm_mem) { - uvm_global_gpu_id_t gpu_id; + uvm_gpu_id_t gpu_id; uvm_gpu_t *gpu_owner; if (rm_mem == NULL) @@ -372,19 +374,19 @@ void uvm_rm_mem_free(uvm_rm_mem_t *rm_mem) uvm_rm_mem_unmap_cpu(rm_mem); - // Don't use for_each_global_gpu_in_mask() as the owning GPU might be being - // destroyed and already removed from the global GPU array causing the iteration - // to stop prematurely. - for_each_global_gpu_id_in_mask(gpu_id, &rm_mem->mapped_on) { - if (!uvm_global_id_equal(gpu_id, gpu_owner->global_id)) + // Don't use for_each_gpu_in_mask() as the owning GPU might be being + // destroyed and already removed from the global GPU array causing the + // iteration to stop prematurely. + for_each_gpu_id_in_mask(gpu_id, &rm_mem->mapped_on) { + if (!uvm_id_equal(gpu_id, gpu_owner->id)) uvm_rm_mem_unmap_gpu(rm_mem, uvm_gpu_get(gpu_id)); } rm_mem_unmap_gpu(rm_mem, gpu_owner); - UVM_ASSERT_MSG(uvm_global_processor_mask_empty(&rm_mem->mapped_on), + UVM_ASSERT_MSG(uvm_processor_mask_empty(&rm_mem->mapped_on), "Left-over %u mappings in rm_mem\n", - uvm_global_processor_mask_get_count(&rm_mem->mapped_on)); + uvm_processor_mask_get_count(&rm_mem->mapped_on)); uvm_kvfree(rm_mem->proxy_vas); uvm_kvfree(rm_mem); @@ -422,7 +424,7 @@ NV_STATUS uvm_rm_mem_map_all_gpus(uvm_rm_mem_t *rm_mem, NvU64 gpu_alignment) UVM_ASSERT(rm_mem); - for_each_global_gpu(gpu) { + for_each_gpu(gpu) { NV_STATUS status = uvm_rm_mem_map_gpu(rm_mem, gpu, gpu_alignment); if (status != NV_OK) return status; diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem.h b/kernel-open/nvidia-uvm/uvm_rm_mem.h index 736c0c59d2..f684e029b9 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem.h +++ b/kernel-open/nvidia-uvm/uvm_rm_mem.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -42,11 +42,11 @@ struct uvm_rm_mem_struct uvm_rm_mem_type_t type; // Mask of processors the memory is mapped on - uvm_global_processor_mask_t mapped_on; + uvm_processor_mask_t mapped_on; // VA of the memory on the UVM internal address space of each processor. If // the memory has not been mapped on a given processor, the VA is zero. - NvU64 vas[UVM_GLOBAL_ID_MAX_PROCESSORS]; + NvU64 vas[UVM_ID_MAX_PROCESSORS]; // VA of the memory in the proxy address space of each processor. If // the memory has not been mapped on a given processor, the VA is zero. diff --git a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c index 306cecf6b8..e817b9610f 100644 --- a/kernel-open/nvidia-uvm/uvm_rm_mem_test.c +++ b/kernel-open/nvidia-uvm/uvm_rm_mem_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -22,6 +22,7 @@ *******************************************************************************/ #include "uvm_rm_mem.h" +#include "uvm_global.h" #include "uvm_test.h" #include "uvm_test_ioctl.h" #include "uvm_va_space.h" @@ -86,7 +87,7 @@ static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem, NvU64 alignment) // In SR-IOV heavy, there are two VA spaces per GPU, so there are two // mappings for a single rm_mem object on a GPU, even if the memory is // located in vidmem. - if (uvm_gpu_uses_proxy_channel_pool(gpu)) { + if (uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)) { TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); gpu_proxy_va = uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu); @@ -103,7 +104,7 @@ static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem, NvU64 alignment) TEST_CHECK_RET(gpu_uvm_va == uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu)); - if (uvm_gpu_uses_proxy_channel_pool(gpu)) + if (uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)) TEST_CHECK_RET(gpu_proxy_va == uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu)); // Unmapping the GPU owner is a no-op @@ -112,7 +113,7 @@ static NV_STATUS map_gpu_owner(uvm_rm_mem_t *rm_mem, NvU64 alignment) TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); TEST_CHECK_RET(gpu_uvm_va == uvm_rm_mem_get_gpu_uvm_va(rm_mem, gpu)); - if (uvm_gpu_uses_proxy_channel_pool(gpu)) { + if (uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)) { TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu)); TEST_CHECK_RET(gpu_proxy_va == uvm_rm_mem_get_gpu_proxy_va(rm_mem, gpu)); } @@ -140,7 +141,8 @@ static NV_STATUS map_other_gpus(uvm_rm_mem_t *rm_mem, uvm_va_space_t *va_space, // The previous GPU map calls added mappings to the proxy VA space // when in SR-IOV heavy mode - TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == uvm_gpu_uses_proxy_channel_pool(gpu)); + TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == + uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)); // Unmapping removes all mappings uvm_rm_mem_unmap_gpu(rm_mem, gpu); @@ -156,7 +158,8 @@ static NV_STATUS map_other_gpus(uvm_rm_mem_t *rm_mem, uvm_va_space_t *va_space, TEST_NV_CHECK_RET(uvm_rm_mem_map_gpu(rm_mem, gpu, alignment)); TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu(rm_mem, gpu)); - TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == uvm_gpu_uses_proxy_channel_pool(gpu)); + TEST_CHECK_RET(uvm_rm_mem_mapped_on_gpu_proxy(rm_mem, gpu) == + uvm_parent_gpu_needs_proxy_channel_pool(gpu->parent)); TEST_NV_CHECK_RET(check_alignment(rm_mem, gpu, alignment)); } @@ -194,14 +197,13 @@ static NV_STATUS test_all_gpus_in_va(uvm_va_space_t *va_space) for (i = 0; i < ARRAY_SIZE(sizes); ++i) { for (j = 0; j < ARRAY_SIZE(mem_types); ++j) { + bool test_cpu_mappings = (mem_types[j] == UVM_RM_MEM_TYPE_SYS) || !g_uvm_global.conf_computing_enabled; + for (k = 0; k < ARRAY_SIZE(alignments); ++k) { - bool test_cpu_mappings = true; // Create an allocation in the GPU's address space TEST_NV_CHECK_RET(uvm_rm_mem_alloc(gpu, mem_types[j], sizes[i], alignments[k], &rm_mem)); - test_cpu_mappings = mem_types[j] == UVM_RM_MEM_TYPE_SYS || - !uvm_conf_computing_mode_enabled(gpu); // Test CPU mappings if (test_cpu_mappings) TEST_NV_CHECK_GOTO(map_cpu(rm_mem), error); diff --git a/kernel-open/nvidia-uvm/uvm_sec2_test.c b/kernel-open/nvidia-uvm/uvm_sec2_test.c index adc397038c..3ed075729d 100644 --- a/kernel-open/nvidia-uvm/uvm_sec2_test.c +++ b/kernel-open/nvidia-uvm/uvm_sec2_test.c @@ -21,14 +21,15 @@ *******************************************************************************/ -#include -#include -#include -#include -#include -#include -#include -#include +#include "uvm_common.h" +#include "uvm_global.h" +#include "uvm_gpu.h" +#include "uvm_mem.h" +#include "uvm_push.h" +#include "uvm_hal.h" +#include "uvm_test.h" +#include "uvm_va_space.h" +#include "uvm_kvmalloc.h" #include #include "nv_uvm_interface.h" @@ -514,8 +515,6 @@ static NV_STATUS test_sec2(uvm_va_space_t *va_space) uvm_gpu_t *gpu; for_each_va_space_gpu(gpu, va_space) { - TEST_CHECK_RET(uvm_conf_computing_mode_enabled(gpu)); - TEST_NV_CHECK_RET(test_semaphore_release(gpu)); TEST_NV_CHECK_RET(test_semaphore_timestamp(gpu)); TEST_NV_CHECK_RET(test_encryption_decryption(gpu)); @@ -529,13 +528,12 @@ NV_STATUS uvm_test_sec2_sanity(UVM_TEST_SEC2_SANITY_PARAMS *params, struct file NV_STATUS status; uvm_va_space_t *va_space = uvm_va_space_get(filp); + TEST_CHECK_RET(g_uvm_global.conf_computing_enabled); + uvm_va_space_down_read_rm(va_space); status = test_sec2(va_space); - if (status != NV_OK) - goto done; -done: uvm_va_space_up_read_rm(va_space); return status; @@ -547,11 +545,11 @@ NV_STATUS uvm_test_sec2_cpu_gpu_roundtrip(UVM_TEST_SEC2_CPU_GPU_ROUNDTRIP_PARAMS uvm_va_space_t *va_space = uvm_va_space_get(filp); uvm_gpu_t *gpu; + TEST_CHECK_RET(g_uvm_global.conf_computing_enabled); + uvm_va_space_down_read(va_space); for_each_va_space_gpu(gpu, va_space) { - TEST_CHECK_RET(uvm_conf_computing_mode_enabled(gpu)); - // To exercise certain SEC2 context save/restore races, do a looped // decrypt with smaller copy sizes instead of larger copy sizes since we // need SEC2 to context switch with pending work in different channels diff --git a/kernel-open/nvidia-uvm/uvm_test.c b/kernel-open/nvidia-uvm/uvm_test.c index 47bba3512e..3a7cb98ef8 100644 --- a/kernel-open/nvidia-uvm/uvm_test.c +++ b/kernel-open/nvidia-uvm/uvm_test.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -36,6 +36,7 @@ #include "uvm_mmu.h" #include "uvm_gpu_access_counters.h" #include "uvm_pmm_sysmem.h" +#include "uvm_migrate_pageable.h" static NV_STATUS uvm_test_get_gpu_ref_count(UVM_TEST_GET_GPU_REF_COUNT_PARAMS *params, struct file *filp) { @@ -148,27 +149,27 @@ static NV_STATUS uvm_test_numa_check_affinity(UVM_TEST_NUMA_CHECK_AFFINITY_PARAM } if (gpu->parent->replayable_faults_supported) { - uvm_gpu_replayable_faults_isr_lock(gpu->parent); + uvm_parent_gpu_replayable_faults_isr_lock(gpu->parent); status = uvm_test_verify_bh_affinity(&gpu->parent->isr.replayable_faults, gpu->parent->closest_cpu_numa_node); - uvm_gpu_replayable_faults_isr_unlock(gpu->parent); + uvm_parent_gpu_replayable_faults_isr_unlock(gpu->parent); if (status != NV_OK) goto release; if (gpu->parent->non_replayable_faults_supported) { - uvm_gpu_non_replayable_faults_isr_lock(gpu->parent); + uvm_parent_gpu_non_replayable_faults_isr_lock(gpu->parent); status = uvm_test_verify_bh_affinity(&gpu->parent->isr.non_replayable_faults, gpu->parent->closest_cpu_numa_node); - uvm_gpu_non_replayable_faults_isr_unlock(gpu->parent); + uvm_parent_gpu_non_replayable_faults_isr_unlock(gpu->parent); if (status != NV_OK) goto release; } if (gpu->parent->access_counters_supported) { - uvm_gpu_access_counters_isr_lock(gpu->parent); + uvm_parent_gpu_access_counters_isr_lock(gpu->parent); status = uvm_test_verify_bh_affinity(&gpu->parent->isr.access_counters, gpu->parent->closest_cpu_numa_node); - uvm_gpu_access_counters_isr_unlock(gpu->parent); + uvm_parent_gpu_access_counters_isr_unlock(gpu->parent); } } release: @@ -309,6 +310,10 @@ long uvm_test_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) UVM_ROUTE_CMD_STACK_NO_INIT_CHECK(UVM_TEST_CGROUP_ACCOUNTING_SUPPORTED, uvm_test_cgroup_accounting_supported); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SPLIT_INVALIDATE_DELAY, uvm_test_split_invalidate_delay); UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_CPU_CHUNK_API, uvm_test_cpu_chunk_api); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_FORCE_CPU_TO_CPU_COPY_WITH_CE, uvm_test_force_cpu_to_cpu_copy_with_ce); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_VA_SPACE_ALLOW_MOVABLE_ALLOCATIONS, + uvm_test_va_space_allow_movable_allocations); + UVM_ROUTE_CMD_STACK_INIT_CHECK(UVM_TEST_SKIP_MIGRATE_VMA, uvm_test_skip_migrate_vma); } return -EINVAL; diff --git a/kernel-open/nvidia-uvm/uvm_test_ioctl.h b/kernel-open/nvidia-uvm/uvm_test_ioctl.h index 91619ca5a6..2392eab99c 100644 --- a/kernel-open/nvidia-uvm/uvm_test_ioctl.h +++ b/kernel-open/nvidia-uvm/uvm_test_ioctl.h @@ -191,6 +191,7 @@ typedef struct NvU64 va_range_end NV_ALIGN_BYTES(8); // Out, inclusive NvU32 read_duplication; // Out (UVM_TEST_READ_DUPLICATION_POLICY) NvProcessorUuid preferred_location; // Out + NvS32 preferred_cpu_nid; // Out NvProcessorUuid accessed_by[UVM_MAX_PROCESSORS]; // Out NvU32 accessed_by_count; // Out NvU32 type; // Out (UVM_TEST_VA_RANGE_TYPE) @@ -1443,6 +1444,28 @@ typedef struct { NV_STATUS rmStatus; // Out } UVM_TEST_CPU_CHUNK_API_PARAMS; + +#define UVM_TEST_FORCE_CPU_TO_CPU_COPY_WITH_CE UVM_TEST_IOCTL_BASE(101) +typedef struct +{ + NvBool force_copy_with_ce; // In + NV_STATUS rmStatus; // Out +} UVM_TEST_FORCE_CPU_TO_CPU_COPY_WITH_CE_PARAMS; + +#define UVM_TEST_VA_SPACE_ALLOW_MOVABLE_ALLOCATIONS UVM_TEST_IOCTL_BASE(102) +typedef struct +{ + NvBool allow_movable; // In + NV_STATUS rmStatus; // Out +} UVM_TEST_VA_SPACE_ALLOW_MOVABLE_ALLOCATIONS_PARAMS; + +#define UVM_TEST_SKIP_MIGRATE_VMA UVM_TEST_IOCTL_BASE(103) +typedef struct +{ + NvBool skip; // In + NV_STATUS rmStatus; // Out +} UVM_TEST_SKIP_MIGRATE_VMA_PARAMS; + #ifdef __cplusplus } #endif diff --git a/kernel-open/nvidia-uvm/uvm_tools.c b/kernel-open/nvidia-uvm/uvm_tools.c index 607ace44a4..c7f92e435e 100644 --- a/kernel-open/nvidia-uvm/uvm_tools.c +++ b/kernel-open/nvidia-uvm/uvm_tools.c @@ -22,6 +22,7 @@ *******************************************************************************/ #include "uvm_common.h" #include "uvm_ioctl.h" +#include "uvm_global.h" #include "uvm_gpu.h" #include "uvm_hal.h" #include "uvm_tools.h" @@ -285,7 +286,7 @@ static NV_STATUS map_user_pages(NvU64 user_va, NvU64 size, void **addr, struct p nv_mmap_read_unlock(current->mm); goto fail; } - ret = NV_PIN_USER_PAGES(user_va, num_pages, FOLL_WRITE, *pages, NULL); + ret = NV_PIN_USER_PAGES(user_va, num_pages, FOLL_WRITE, *pages); nv_mmap_read_unlock(current->mm); if (ret != num_pages) { @@ -517,7 +518,7 @@ static bool counter_matches_processor(UvmCounterName counter, const NvProcessorU // for their preferred location as well as for the CPU device itself. // This check prevents double counting in the aggregate count. if (counter == UvmCounterNameCpuPageFaultCount) - return uvm_processor_uuid_eq(processor, &NV_PROCESSOR_UUID_CPU_DEFAULT); + return uvm_uuid_eq(processor, &NV_PROCESSOR_UUID_CPU_DEFAULT); return true; } @@ -542,7 +543,7 @@ static void uvm_tools_inc_counter(uvm_va_space_t *va_space, list_for_each_entry(counters, va_space->tools.counters + counter, counter_nodes[counter]) { if ((counters->all_processors && counter_matches_processor(counter, processor)) || - uvm_processor_uuid_eq(&counters->processor, processor)) { + uvm_uuid_eq(&counters->processor, processor)) { atomic64_add(amount, (atomic64_t *)(counters->counters + counter)); } } @@ -747,7 +748,7 @@ static void record_gpu_fault_instance(uvm_gpu_t *gpu, memset(&entry, 0, sizeof(entry)); info->eventType = UvmEventTypeGpuFault; - info->gpuIndex = uvm_id_value(gpu->id); + info->gpuIndex = uvm_parent_id_value_from_processor_id(gpu->id); info->faultType = g_hal_to_tools_fault_type_table[fault_entry->fault_type]; info->accessType = g_hal_to_tools_fault_access_type_table[fault_entry->fault_access_type]; info->clientType = g_hal_to_tools_fault_client_type_table[fault_entry->fault_source.client_type]; @@ -869,8 +870,8 @@ static void record_migration_events(void *args) // Initialize fields that are constant throughout the whole block memset(&entry, 0, sizeof(entry)); info->eventType = UvmEventTypeMigration; - info->srcIndex = uvm_id_value(block_mig->src); - info->dstIndex = uvm_id_value(block_mig->dst); + info->srcIndex = uvm_parent_id_value_from_processor_id(block_mig->src); + info->dstIndex = uvm_parent_id_value_from_processor_id(block_mig->dst); info->beginTimeStamp = block_mig->start_timestamp_cpu; info->endTimeStamp = block_mig->end_timestamp_cpu; info->rangeGroupId = block_mig->range_group_id; @@ -934,7 +935,7 @@ static void record_replay_event_helper(uvm_gpu_id_t gpu_id, memset(&entry, 0, sizeof(entry)); entry.eventData.gpuFaultReplay.eventType = UvmEventTypeGpuFaultReplay; - entry.eventData.gpuFaultReplay.gpuIndex = uvm_id_value(gpu_id); + entry.eventData.gpuFaultReplay.gpuIndex = uvm_parent_id_value_from_processor_id(gpu_id); entry.eventData.gpuFaultReplay.batchId = batch_id; entry.eventData.gpuFaultReplay.clientType = g_hal_to_tools_fault_client_type_table[client_type]; entry.eventData.gpuFaultReplay.timeStamp = timestamp; @@ -987,9 +988,11 @@ static UvmEventMigrationCause g_make_resident_to_tools_migration_cause[UVM_MAKE_ [UVM_MAKE_RESIDENT_CAUSE_API_HINT] = UvmEventMigrationCauseUser, }; -// This event is notified asynchronously when all the migrations pushed to the -// same uvm_push_t object in a call to block_copy_resident_pages_between have -// finished +// For non-CPU-to-CPU migrations (or CPU-to-CPU copies using CEs), this event is +// notified asynchronously when all the migrations pushed to the same uvm_push_t +// object in a call to block_copy_resident_pages_between have finished. +// For CPU-to-CPU copies using memcpy, this event is notified when all of the +// page copies does by block_copy_resident_pages have finished. static void uvm_tools_record_migration(uvm_perf_event_t event_id, uvm_perf_event_data_t *event_data) { uvm_va_block_t *va_block = event_data->migration.block; @@ -1005,24 +1008,60 @@ static void uvm_tools_record_migration(uvm_perf_event_t event_id, uvm_perf_event UVM_ASSERT(tools_is_migration_callback_needed(va_space)); if (tools_is_event_enabled(va_space, UvmEventTypeMigration)) { - migration_data_t *mig; - uvm_push_info_t *push_info = uvm_push_info_from_push(event_data->migration.push); - block_migration_data_t *block_mig = (block_migration_data_t *)push_info->on_complete_data; - - if (push_info->on_complete != NULL) { - mig = kmem_cache_alloc(g_tools_migration_data_cache, NV_UVM_GFP_FLAGS); - if (mig == NULL) - goto done_unlock; + if (!UVM_ID_IS_CPU(event_data->migration.src) || !UVM_ID_IS_CPU(event_data->migration.dst)) { + migration_data_t *mig; + uvm_push_info_t *push_info = uvm_push_info_from_push(event_data->migration.push); + block_migration_data_t *block_mig = (block_migration_data_t *)push_info->on_complete_data; + + if (push_info->on_complete != NULL) { + mig = kmem_cache_alloc(g_tools_migration_data_cache, NV_UVM_GFP_FLAGS); + if (mig == NULL) + goto done_unlock; + + mig->address = event_data->migration.address; + mig->bytes = event_data->migration.bytes; + mig->end_timestamp_gpu_addr = uvm_push_timestamp(event_data->migration.push); + mig->cause = g_make_resident_to_tools_migration_cause[event_data->migration.cause]; + + list_add_tail(&mig->events_node, &block_mig->events); + } + } + else { + UvmEventEntry entry; + UvmEventMigrationInfo *info = &entry.eventData.migration; + uvm_va_space_t *va_space = uvm_va_block_get_va_space(event_data->migration.block); - mig->address = event_data->migration.address; - mig->bytes = event_data->migration.bytes; - mig->end_timestamp_gpu_addr = uvm_push_timestamp(event_data->migration.push); - mig->cause = g_make_resident_to_tools_migration_cause[event_data->migration.cause]; + // CPU-to-CPU migration events can be added directly to the queue. + memset(&entry, 0, sizeof(entry)); + info->eventType = UvmEventTypeMigration; + info->srcIndex = uvm_parent_id_value_from_processor_id(event_data->migration.src); + info->dstIndex = uvm_parent_id_value_from_processor_id(event_data->migration.dst); + // TODO: Bug 4232310: Add src and dst NUMA node IDS to event data. + //info->srcNid = event_data->migration.src_nid; + //info->dstNid = event_data->migration.dst_nid; + info->address = event_data->migration.address; + info->migratedBytes = event_data->migration.bytes; + info->beginTimeStamp = event_data->migration.cpu_start_timestamp; + info->endTimeStamp = NV_GETTIME(); + info->migrationCause = event_data->migration.cause; + info->rangeGroupId = UVM_RANGE_GROUP_ID_NONE; + + // During evictions, it is not safe to uvm_range_group_range_find() because the va_space lock is not held. + if (event_data->migration.cause != UVM_MAKE_RESIDENT_CAUSE_EVICTION) { + uvm_range_group_range_t *range = uvm_range_group_range_find(va_space, event_data->migration.address); + if (range != NULL) + info->rangeGroupId = range->range_group->id; + } - list_add_tail(&mig->events_node, &block_mig->events); + uvm_tools_record_event(va_space, &entry); } } + // We don't want to increment neither UvmCounterNameBytesXferDtH nor + // UvmCounterNameBytesXferHtD in a CPU-to-CPU migration. + if (UVM_ID_IS_CPU(event_data->migration.src) && UVM_ID_IS_CPU(event_data->migration.dst)) + goto done_unlock; + // Increment counters if (UVM_ID_IS_CPU(event_data->migration.src) && tools_is_counter_enabled(va_space, UvmCounterNameBytesXferHtD)) { @@ -1082,25 +1121,19 @@ void uvm_tools_broadcast_replay(uvm_gpu_t *gpu, } -void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, - NvU32 batch_id, - uvm_fault_client_type_t client_type) +void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, NvU32 batch_id, uvm_fault_client_type_t client_type) { UVM_ASSERT(!gpu->parent->has_clear_faulted_channel_method); if (!tools_is_event_enabled_in_any_va_space(UvmEventTypeGpuFaultReplay)) return; - record_replay_event_helper(gpu->id, - batch_id, - client_type, - NV_GETTIME(), - gpu->parent->host_hal->get_time(gpu)); + record_replay_event_helper(gpu->id, batch_id, client_type, NV_GETTIME(), gpu->parent->host_hal->get_time(gpu)); } void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *buffer_entry, - bool on_managed) + bool on_managed_phys) { UvmEventEntry entry; UvmEventTestAccessCounterInfo *info = &entry.testEventData.accessCounter; @@ -1116,9 +1149,10 @@ void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, memset(&entry, 0, sizeof(entry)); info->eventType = UvmEventTypeTestAccessCounter; - info->srcIndex = uvm_id_value(gpu->id); + info->srcIndex = uvm_parent_id_value_from_processor_id(gpu->id); info->address = buffer_entry->address.address; info->isVirtual = buffer_entry->address.is_virtual? 1: 0; + if (buffer_entry->address.is_virtual) { info->instancePtr = buffer_entry->virtual_info.instance_ptr.address; info->instancePtrAperture = g_hal_to_tools_aperture_table[buffer_entry->virtual_info.instance_ptr.aperture]; @@ -1126,9 +1160,10 @@ void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, } else { info->aperture = g_hal_to_tools_aperture_table[buffer_entry->address.aperture]; + info->physOnManaged = on_managed_phys? 1 : 0; } + info->isFromCpu = buffer_entry->counter_type == UVM_ACCESS_COUNTER_TYPE_MOMC? 1: 0; - info->onManaged = on_managed? 1 : 0; info->value = buffer_entry->counter_value; info->subGranularity = buffer_entry->sub_granularity; info->bank = buffer_entry->bank; @@ -1248,7 +1283,7 @@ void uvm_tools_record_read_duplicate(uvm_va_block_t *va_block, uvm_va_block_page_resident_processors(va_block, page_index, &resident_processors); for_each_id_in_mask(id, &resident_processors) - info_read_duplicate->processors |= (1 << uvm_id_value(id)); + info_read_duplicate->processors |= (1 << uvm_parent_id_value_from_processor_id(id)); uvm_tools_record_event(va_space, &entry); } @@ -1274,7 +1309,7 @@ void uvm_tools_record_read_duplicate_invalidate(uvm_va_block_t *va_block, memset(&entry, 0, sizeof(entry)); info->eventType = UvmEventTypeReadDuplicateInvalidate; - info->residentIndex = uvm_id_value(dst); + info->residentIndex = uvm_parent_id_value_from_processor_id(dst); info->size = PAGE_SIZE; info->timeStamp = NV_GETTIME(); @@ -1373,7 +1408,7 @@ void uvm_tools_record_gpu_fatal_fault(uvm_gpu_id_t gpu_id, memset(&entry, 0, sizeof(entry)); info->eventType = UvmEventTypeFatalFault; - info->processorIndex = uvm_id_value(gpu_id); + info->processorIndex = uvm_parent_id_value_from_processor_id(gpu_id); info->timeStamp = NV_GETTIME(); info->address = buffer_entry->fault_address; info->accessType = g_hal_to_tools_fault_access_type_table[buffer_entry->fault_access_type]; @@ -1401,6 +1436,7 @@ void uvm_tools_record_thrashing(uvm_va_space_t *va_space, uvm_down_read(&va_space->tools.lock); if (tools_is_event_enabled(va_space, UvmEventTypeThrashingDetected)) { + uvm_processor_id_t id; UvmEventEntry entry; UvmEventThrashingDetectedInfo *info = &entry.eventData.thrashing; memset(&entry, 0, sizeof(entry)); @@ -1409,7 +1445,10 @@ void uvm_tools_record_thrashing(uvm_va_space_t *va_space, info->address = address; info->size = region_size; info->timeStamp = NV_GETTIME(); - bitmap_copy((long unsigned *)&info->processors, processors->bitmap, UVM_ID_MAX_PROCESSORS); + + for_each_id_in_mask(id, processors) + __set_bit(uvm_parent_id_value_from_processor_id(id), + (unsigned long *)&info->processors); uvm_tools_record_event(va_space, &entry); } @@ -1434,7 +1473,7 @@ void uvm_tools_record_throttling_start(uvm_va_space_t *va_space, NvU64 address, memset(&entry, 0, sizeof(entry)); info->eventType = UvmEventTypeThrottlingStart; - info->processorIndex = uvm_id_value(processor); + info->processorIndex = uvm_parent_id_value_from_processor_id(processor); info->address = address; info->timeStamp = NV_GETTIME(); @@ -1461,7 +1500,7 @@ void uvm_tools_record_throttling_end(uvm_va_space_t *va_space, NvU64 address, uv memset(&entry, 0, sizeof(entry)); info->eventType = UvmEventTypeThrottlingEnd; - info->processorIndex = uvm_id_value(processor); + info->processorIndex = uvm_parent_id_value_from_processor_id(processor); info->address = address; info->timeStamp = NV_GETTIME(); @@ -1480,8 +1519,8 @@ static void record_map_remote_events(void *args) memset(&entry, 0, sizeof(entry)); entry.eventData.mapRemote.eventType = UvmEventTypeMapRemote; - entry.eventData.mapRemote.srcIndex = uvm_id_value(block_map_remote->src); - entry.eventData.mapRemote.dstIndex = uvm_id_value(block_map_remote->dst); + entry.eventData.mapRemote.srcIndex = uvm_parent_id_value_from_processor_id(block_map_remote->src); + entry.eventData.mapRemote.dstIndex = uvm_parent_id_value_from_processor_id(block_map_remote->dst); entry.eventData.mapRemote.mapRemoteCause = block_map_remote->cause; entry.eventData.mapRemote.timeStamp = block_map_remote->timestamp; @@ -1553,8 +1592,8 @@ void uvm_tools_record_map_remote(uvm_va_block_t *va_block, memset(&entry, 0, sizeof(entry)); entry.eventData.mapRemote.eventType = UvmEventTypeMapRemote; - entry.eventData.mapRemote.srcIndex = uvm_id_value(processor); - entry.eventData.mapRemote.dstIndex = uvm_id_value(residency); + entry.eventData.mapRemote.srcIndex = uvm_parent_id_value_from_processor_id(processor); + entry.eventData.mapRemote.dstIndex = uvm_parent_id_value_from_processor_id(residency); entry.eventData.mapRemote.mapRemoteCause = cause; entry.eventData.mapRemote.timeStamp = NV_GETTIME(); entry.eventData.mapRemote.address = address; @@ -2015,22 +2054,15 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, NV_STATUS status; uvm_mem_t *stage_mem = NULL; void *stage_addr; - uvm_global_processor_mask_t *retained_global_gpus = NULL; - uvm_global_processor_mask_t *global_gpus = NULL; + uvm_processor_mask_t *retained_gpus = NULL; uvm_va_block_context_t *block_context = NULL; struct mm_struct *mm = NULL; - retained_global_gpus = uvm_kvmalloc(sizeof(*retained_global_gpus)); - if (retained_global_gpus == NULL) + retained_gpus = uvm_processor_mask_cache_alloc(); + if (!retained_gpus) return NV_ERR_NO_MEMORY; - uvm_global_processor_mask_zero(retained_global_gpus); - - global_gpus = uvm_kvmalloc(sizeof(*global_gpus)); - if (global_gpus == NULL) { - status = NV_ERR_NO_MEMORY; - goto exit; - } + uvm_processor_mask_zero(retained_gpus); mm = uvm_va_space_mm_or_current_retain(va_space); @@ -2055,6 +2087,7 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, NvU64 bytes_left = size - *bytes; NvU64 page_offset = target_va_start & (PAGE_SIZE - 1); NvU64 bytes_now = min(bytes_left, (NvU64)(PAGE_SIZE - page_offset)); + bool map_stage_mem_on_gpus = true; if (is_write) { NvU64 remaining = nv_copy_from_user(stage_addr, user_va_start, bytes_now); @@ -2077,34 +2110,34 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, if (status != NV_OK) goto unlock_and_exit; - uvm_va_space_global_gpus(va_space, global_gpus); - - for_each_global_gpu_in_mask(gpu, global_gpus) { - - // When CC is enabled, the staging memory cannot be mapped on the - // GPU (it is protected sysmem), but it is still used to store the - // unencrypted version of the page contents when the page is - // resident on vidmem. - if (uvm_conf_computing_mode_enabled(gpu)) { - UVM_ASSERT(uvm_global_processor_mask_empty(retained_global_gpus)); - - break; + // When CC is enabled, the staging memory cannot be mapped on the GPU + // (it is protected sysmem), but it is still used to store the + // unencrypted version of the page contents when the page is resident + // on vidmem. + if (g_uvm_global.conf_computing_enabled) + map_stage_mem_on_gpus = false; + + if (map_stage_mem_on_gpus) { + for_each_gpu_in_mask(gpu, &va_space->registered_gpus) { + if (uvm_processor_mask_test_and_set(retained_gpus, gpu->id)) + continue; + + // The retention of each GPU ensures that the staging memory is + // freed before the unregistration of any of the GPUs is mapped + // on. Each GPU is retained once. + uvm_gpu_retain(gpu); + + // Accessing the VA block may result in copying data between the + // CPU and a GPU. Conservatively add virtual mappings to all the + // GPUs (even if those mappings may never be used) as tools + // read/write is not on a performance critical path. + status = uvm_mem_map_gpu_kernel(stage_mem, gpu); + if (status != NV_OK) + goto unlock_and_exit; } - if (uvm_global_processor_mask_test_and_set(retained_global_gpus, gpu->global_id)) - continue; - - // The retention of each GPU ensures that the staging memory is - // freed before the unregistration of any of the GPUs is mapped on. - // Each GPU is retained once. - uvm_gpu_retain(gpu); - - // Accessing the VA block may result in copying data between the CPU - // and a GPU. Conservatively add virtual mappings to all the GPUs - // (even if those mappings may never be used) as tools read/write is - // not on a performance critical path. - status = uvm_mem_map_gpu_kernel(stage_mem, gpu); - if (status != NV_OK) - goto unlock_and_exit; + } + else { + UVM_ASSERT(uvm_processor_mask_empty(retained_gpus)); } // Make sure a CPU resident page has an up to date struct page pointer. @@ -2119,7 +2152,7 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, // For simplicity, check for ECC errors on all GPUs registered in the VA // space if (status == NV_OK) - status = uvm_global_mask_check_ecc_error(global_gpus); + status = uvm_global_gpu_check_ecc_error(&va_space->registered_gpus); uvm_va_space_up_read_rm(va_space); if (mm) @@ -2162,12 +2195,11 @@ static NV_STATUS tools_access_process_memory(uvm_va_space_t *va_space, uvm_mem_free(stage_mem); - uvm_global_mask_release(retained_global_gpus); + uvm_global_gpu_release(retained_gpus); uvm_va_space_mm_or_current_release(va_space, mm); - uvm_kvfree(global_gpus); - uvm_kvfree(retained_global_gpus); + uvm_processor_mask_cache_free(retained_gpus); return status; } @@ -2228,24 +2260,42 @@ NV_STATUS uvm_api_tools_get_processor_uuid_table(UVM_TOOLS_GET_PROCESSOR_UUID_TA NvProcessorUuid *uuids; NvU64 remaining; uvm_gpu_t *gpu; + NvU32 count = params->count; uvm_va_space_t *va_space = uvm_va_space_get(filp); - uuids = uvm_kvmalloc_zero(sizeof(NvProcessorUuid) * UVM_ID_MAX_PROCESSORS); + // Prior to Multi-MIG support, params->count was always zero meaning the + // input array was size UVM_MAX_PROCESSORS or 33 at that time. + if (count == 0) + count = 33; + else if (count > UVM_ID_MAX_PROCESSORS) + count = UVM_ID_MAX_PROCESSORS; + + uuids = uvm_kvmalloc_zero(sizeof(NvProcessorUuid) * count); if (uuids == NULL) return NV_ERR_NO_MEMORY; - uvm_processor_uuid_copy(&uuids[UVM_ID_CPU_VALUE], &NV_PROCESSOR_UUID_CPU_DEFAULT); + uvm_uuid_copy(&uuids[UVM_ID_CPU_VALUE], &NV_PROCESSOR_UUID_CPU_DEFAULT); params->count = 1; uvm_va_space_down_read(va_space); for_each_va_space_gpu(gpu, va_space) { - uvm_processor_uuid_copy(&uuids[uvm_id_value(gpu->id)], uvm_gpu_uuid(gpu)); - if (uvm_id_value(gpu->id) + 1 > params->count) - params->count = uvm_id_value(gpu->id) + 1; + NvU32 id_value; + const NvProcessorUuid *uuid; + + id_value = uvm_parent_id_value(gpu->parent->id); + uuid = &gpu->parent->uuid; + + if (id_value < count) + uvm_uuid_copy(&uuids[id_value], uuid); + + // Return the actual count even if the UUID isn't returned due to + // limited input array size. + if (id_value + 1 > params->count) + params->count = id_value + 1; } uvm_va_space_up_read(va_space); - remaining = nv_copy_to_user((void *)params->tablePtr, uuids, sizeof(NvProcessorUuid) * params->count); + remaining = nv_copy_to_user((void *)params->tablePtr, uuids, sizeof(NvProcessorUuid) * count); uvm_kvfree(uuids); if (remaining != 0) @@ -2279,8 +2329,8 @@ NV_STATUS uvm_test_tools_flush_replay_events(UVM_TEST_TOOLS_FLUSH_REPLAY_EVENTS_ // Wait for register-based fault clears to queue the replay event if (!gpu->parent->has_clear_faulted_channel_method) { - uvm_gpu_non_replayable_faults_isr_lock(gpu->parent); - uvm_gpu_non_replayable_faults_isr_unlock(gpu->parent); + uvm_parent_gpu_non_replayable_faults_isr_lock(gpu->parent); + uvm_parent_gpu_non_replayable_faults_isr_unlock(gpu->parent); } // Wait for pending fault replay methods to complete (replayable faults on diff --git a/kernel-open/nvidia-uvm/uvm_tools.h b/kernel-open/nvidia-uvm/uvm_tools.h index 988b10f461..0a8d4f847c 100644 --- a/kernel-open/nvidia-uvm/uvm_tools.h +++ b/kernel-open/nvidia-uvm/uvm_tools.h @@ -102,18 +102,13 @@ void uvm_tools_record_read_duplicate_invalidate(uvm_va_block_t *va_block, uvm_va_block_region_t region, const uvm_page_mask_t *page_mask); -void uvm_tools_broadcast_replay(uvm_gpu_t *gpu, - uvm_push_t *push, - NvU32 batch_id, - uvm_fault_client_type_t client_type); +void uvm_tools_broadcast_replay(uvm_gpu_t *gpu, uvm_push_t *push, NvU32 batch_id, uvm_fault_client_type_t client_type); -void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, - NvU32 batch_id, - uvm_fault_client_type_t client_type); +void uvm_tools_broadcast_replay_sync(uvm_gpu_t *gpu, NvU32 batch_id, uvm_fault_client_type_t client_type); void uvm_tools_broadcast_access_counter(uvm_gpu_t *gpu, const uvm_access_counter_buffer_entry_t *buffer_entry, - bool on_managed); + bool on_managed_phys); void uvm_tools_test_hmm_split_invalidate(uvm_va_space_t *va_space); diff --git a/kernel-open/nvidia-uvm/uvm_tracker_test.c b/kernel-open/nvidia-uvm/uvm_tracker_test.c index 08a31c9d82..af490efa28 100644 --- a/kernel-open/nvidia-uvm/uvm_tracker_test.c +++ b/kernel-open/nvidia-uvm/uvm_tracker_test.c @@ -66,17 +66,17 @@ static NV_STATUS test_tracker_completion(uvm_va_space_t *va_space) NV_STATUS status = NV_OK; uvm_spin_loop_t spin; - gpu = uvm_va_space_find_first_gpu(va_space); - TEST_CHECK_RET(gpu != NULL); - // TODO: Bug 4008734: [UVM][HCC] Extend secure tracking semaphore mechanism // to all semaphore // This test allocates semaphore in vidmem and then releases it from the CPU // SEC2 channels cannot target semaphores in vidmem. Moreover, CPU cannot // directly release values to vidmem for CE channels. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; + gpu = uvm_va_space_find_first_gpu(va_space); + TEST_CHECK_RET(gpu != NULL); + TEST_NV_CHECK_RET(uvm_gpu_semaphore_alloc(gpu->semaphore_pool, &sema)); uvm_tracker_init(&tracker); diff --git a/kernel-open/nvidia-uvm/uvm_turing.c b/kernel-open/nvidia-uvm/uvm_turing.c index 29a1fa68df..32eb5e76c0 100644 --- a/kernel-open/nvidia-uvm/uvm_turing.c +++ b/kernel-open/nvidia-uvm/uvm_turing.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -76,6 +76,8 @@ void uvm_hal_turing_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counters_supported = true; + parent_gpu->access_counters_can_use_physical_addresses = false; + parent_gpu->fault_cancel_va_supported = true; parent_gpu->scoped_atomics_supported = true; @@ -93,4 +95,6 @@ void uvm_hal_turing_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->smc.supported = false; parent_gpu->plc_supported = true; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_types.h b/kernel-open/nvidia-uvm/uvm_types.h index da3e6da7a1..56f42f9b64 100644 --- a/kernel-open/nvidia-uvm/uvm_types.h +++ b/kernel-open/nvidia-uvm/uvm_types.h @@ -967,8 +967,10 @@ typedef struct NvU8 isFromCpu; NvU8 veId; - NvU8 onManaged; // The access counter notification was triggered on - // a managed memory region + + // The physical access counter notification was triggered on a managed + // memory region. This is not set for virtual access counter notifications. + NvU8 physOnManaged; NvU32 value; NvU32 subGranularity; diff --git a/kernel-open/nvidia-uvm/uvm_user_channel.c b/kernel-open/nvidia-uvm/uvm_user_channel.c index 757a263be8..fa150114fe 100644 --- a/kernel-open/nvidia-uvm/uvm_user_channel.c +++ b/kernel-open/nvidia-uvm/uvm_user_channel.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -670,7 +670,7 @@ static NV_STATUS uvm_register_channel(uvm_va_space_t *va_space, // Tell the GPU page fault handler about this instance_ptr -> user_channel // mapping - status = uvm_gpu_add_user_channel(gpu, user_channel); + status = uvm_parent_gpu_add_user_channel(gpu->parent, user_channel); if (status != NV_OK) goto error_under_read; @@ -806,7 +806,7 @@ void uvm_user_channel_detach(uvm_user_channel_t *user_channel, struct list_head // that this only prevents new faults from being serviced. It doesn't // flush out faults currently being serviced, nor prior faults still // pending in the fault buffer. Those are handled separately. - uvm_gpu_remove_user_channel(user_channel->gpu_va_space->gpu, user_channel); + uvm_parent_gpu_remove_user_channel(user_channel->gpu->parent, user_channel); // We can't release the channel back to RM here because leftover state // for this channel (such as the instance pointer) could still be in the @@ -1035,7 +1035,7 @@ NV_STATUS uvm_test_check_channel_va_space(UVM_TEST_CHECK_CHANNEL_VA_SPACE_PARAMS // the provided channel + VEID matches the provided VA space. In all of the // non-NV_OK cases the translation will fail and we should return // NV_ERR_INVALID_CHANNEL. channel_va_space == NULL for all such cases. - (void)uvm_gpu_fault_entry_to_va_space(gpu, &fault_entry, &channel_va_space); + (void)uvm_parent_gpu_fault_entry_to_va_space(gpu->parent, &fault_entry, &channel_va_space); if (channel_va_space == va_space) status = NV_OK; diff --git a/kernel-open/nvidia-uvm/uvm_user_channel.h b/kernel-open/nvidia-uvm/uvm_user_channel.h index 76f8175b46..bc6aadb8fb 100644 --- a/kernel-open/nvidia-uvm/uvm_user_channel.h +++ b/kernel-open/nvidia-uvm/uvm_user_channel.h @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2022 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -131,7 +131,7 @@ struct uvm_user_channel_struct // If in_subctx is true, subctx_info will point at a per-TSG data structure // that contains the VA spaces of all the subcontexts in the TSG. This value - // is assigned in uvm_gpu_add_user_channel. + // is assigned in uvm_parent_gpu_add_user_channel. uvm_user_channel_subctx_info_t *subctx_info; // Number of resources reported by RM. This is the size of both the diff --git a/kernel-open/nvidia-uvm/uvm_va_block.c b/kernel-open/nvidia-uvm/uvm_va_block.c index cd7a2d7287..1eb9a63f43 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.c +++ b/kernel-open/nvidia-uvm/uvm_va_block.c @@ -24,6 +24,7 @@ #include "uvm_linux.h" #include "uvm_common.h" #include "uvm_api.h" +#include "uvm_global.h" #include "uvm_gpu.h" #include "uvm_va_space.h" #include "uvm_va_range.h" @@ -31,6 +32,7 @@ #include "uvm_hal_types.h" #include "uvm_kvmalloc.h" #include "uvm_tools.h" +#include "uvm_processors.h" #include "uvm_push.h" #include "uvm_hal.h" #include "uvm_perf_thrashing.h" @@ -63,6 +65,10 @@ MODULE_PARM_DESC(uvm_fault_force_sysmem, "Force (1) using sysmem storage for pag static int uvm_perf_map_remote_on_eviction __read_mostly = 1; module_param(uvm_perf_map_remote_on_eviction, int, S_IRUGO); +static int uvm_block_cpu_to_cpu_copy_with_ce __read_mostly = 0; +module_param(uvm_block_cpu_to_cpu_copy_with_ce, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(uvm_block_cpu_to_cpu_copy_with_ce, "Use GPU CEs for CPU-to-CPU migrations."); + // Caching is always disabled for mappings to remote memory. The following two // module parameters can be used to force caching for GPU peer/sysmem mappings. // @@ -194,6 +200,13 @@ static uvm_va_block_cpu_node_state_t *block_node_state_get(uvm_va_block_t *block return block->cpu.node_state[index]; } +static uvm_page_mask_t *block_tracking_node_mask_get(uvm_va_block_context_t *va_block_context, int nid) +{ + size_t index = node_to_index(nid); + UVM_ASSERT(va_block_context->make_resident.cpu_pages_used.node_masks[index]); + return va_block_context->make_resident.cpu_pages_used.node_masks[index]; +} + // The bottom bit of uvm_va_block_t::chunks is used to indicate how CPU chunks // are stored. // @@ -613,9 +626,9 @@ static void uvm_va_block_cpu_set_resident_all_chunks(uvm_va_block_t *va_block, uvm_page_mask_copy(page_mask_copy, page_mask); for_each_node_mask(nid, tracking->nodes) { - size_t index = node_to_index(nid); + uvm_page_mask_t *node_mask = block_tracking_node_mask_get(va_block_context, nid); - if (uvm_page_mask_and(node_pages_mask, page_mask_copy, tracking->node_masks[index])) { + if (uvm_page_mask_and(node_pages_mask, page_mask_copy, node_mask)) { uvm_va_block_cpu_set_resident_mask(va_block, nid, node_pages_mask); uvm_page_mask_andnot(page_mask_copy, page_mask_copy, node_pages_mask); } @@ -646,6 +659,41 @@ static void uvm_va_block_cpu_clear_resident_region(uvm_va_block_t *va_block, int block_update_cpu_resident_mask(va_block); } +// Clear residency bits from any/all processors that might have had pages resident. +// Note that both the destination processor and any CPU NUMA nodes where pages are +// migrating to need to be skipped as the block logic sets the new page residency +// before clearing the old ones (see uvm_va_block_make_resident_finish()). +static void uvm_va_block_cpu_clear_resident_all_chunks(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_page_mask_t *page_mask) +{ + int nid; + + if (UVM_ID_IS_CPU(va_block_context->make_resident.dest_id) && + nodes_empty(va_block_context->make_resident.cpu_pages_used.nodes)) + return; + + for_each_possible_uvm_node(nid) { + // If the destination is the CPU and pages were allocated on this node + // for the migration, clear residency on the node only for pages that + // are in the page_mask but not in the node's allocated mask. + if (UVM_ID_IS_CPU(va_block_context->make_resident.dest_id) && + node_isset(nid, va_block_context->make_resident.cpu_pages_used.nodes)) { + uvm_page_mask_t *node_pages_mask = &va_block_context->make_resident.node_pages_mask; + uvm_page_mask_t *node_alloc_mask = block_tracking_node_mask_get(va_block_context, nid); + uvm_page_mask_t *nid_resident = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, nid); + uvm_page_mask_t *migrated_pages = &va_block_context->make_resident.pages_migrated; + + uvm_page_mask_andnot(node_pages_mask, nid_resident, node_alloc_mask); + if (uvm_page_mask_and(node_pages_mask, migrated_pages, node_pages_mask)) + uvm_va_block_cpu_clear_resident_mask(va_block, nid, node_pages_mask); + } + else { + uvm_va_block_cpu_clear_resident_mask(va_block, nid, page_mask); + } + } +} + bool uvm_va_block_cpu_is_page_resident_on(uvm_va_block_t *va_block, int nid, uvm_page_index_t page_index) { uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(va_block, UVM_ID_CPU, nid); @@ -931,6 +979,7 @@ void uvm_va_block_context_init(uvm_va_block_context_t *va_block_context, struct va_block_context->mm = mm; va_block_context->make_resident.dest_nid = NUMA_NO_NODE; + nodes_clear(va_block_context->make_resident.cpu_pages_used.nodes); } void uvm_va_block_context_free(uvm_va_block_context_t *va_block_context) @@ -1242,11 +1291,13 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, return NV_OK; error: - for_each_possible_uvm_node(nid) { - size_t index = node_to_index(nid); + if (block->cpu.node_state) { + for_each_possible_uvm_node(nid) { + size_t index = node_to_index(nid); - if (block->cpu.node_state[index]) - kmem_cache_free(g_uvm_va_block_cpu_node_state_cache, block->cpu.node_state[index]); + if (block->cpu.node_state[index]) + kmem_cache_free(g_uvm_va_block_cpu_node_state_cache, block->cpu.node_state[index]); + } } uvm_kvfree(block->cpu.node_state); @@ -1258,12 +1309,12 @@ NV_STATUS uvm_va_block_create(uvm_va_range_t *va_range, static void cpu_chunk_remove_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, uvm_gpu_t *gpu) { - NvU64 gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + NvU64 gpu_mapping_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent); if (gpu_mapping_addr == 0) return; uvm_pmm_sysmem_mappings_remove_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr); - uvm_cpu_chunk_unmap_gpu_phys(chunk, gpu->parent); + uvm_cpu_chunk_unmap_parent_gpu_phys(chunk, gpu->parent); } static NV_STATUS cpu_chunk_add_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, @@ -1277,7 +1328,7 @@ static NV_STATUS cpu_chunk_add_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, // When the Confidential Computing feature is enabled the transfers don't // use the DMA mapping of CPU chunks (since it's protected memory), but // the DMA address of the unprotected dma buffer. - if (uvm_conf_computing_mode_enabled(gpu)) + if (g_uvm_global.conf_computing_enabled) return NV_OK; status = uvm_cpu_chunk_map_gpu(chunk, gpu); @@ -1290,7 +1341,7 @@ static NV_STATUS cpu_chunk_add_sysmem_gpu_mapping(uvm_cpu_chunk_t *chunk, // pmm_sysmem_mappings_remove_gpu_mapping() in case of a // failure. status = uvm_pmm_sysmem_mappings_add_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), + uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent), uvm_va_block_cpu_page_address(block, page_index), chunk_size, block, @@ -1325,10 +1376,10 @@ static NV_STATUS block_gpu_map_phys_all_cpu_pages(uvm_va_block_t *block, uvm_gpu for_each_possible_uvm_node(nid) { for_each_cpu_chunk_in_block(chunk, page_index, block, nid) { - UVM_ASSERT_MSG(uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent) == 0, + UVM_ASSERT_MSG(uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent) == 0, "GPU%u DMA address 0x%llx\n", uvm_id_value(gpu->id), - uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent)); + uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent)); status = cpu_chunk_add_sysmem_gpu_mapping(chunk, block, page_index, gpu); if (status != NV_OK) @@ -1645,11 +1696,11 @@ static bool block_cpu_page_is_dirty(uvm_va_block_t *block, uvm_page_index_t page return uvm_cpu_chunk_is_dirty(chunk, page_index - chunk_region.first); } -static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, - uvm_chunk_size_t alloc_size, - uvm_cpu_chunk_alloc_flags_t flags, - int nid, - uvm_cpu_chunk_t **chunk) +static NV_STATUS block_alloc_cpu_chunk_inject_error(uvm_va_block_t *block, + uvm_chunk_size_t alloc_size, + uvm_cpu_chunk_alloc_flags_t flags, + int nid, + uvm_cpu_chunk_t **chunk) { uvm_va_block_test_t *block_test = uvm_va_block_get_test(block); @@ -1672,6 +1723,96 @@ static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, return uvm_cpu_chunk_alloc(alloc_size, flags, nid, chunk); } +// Allocate a CPU chunk with the given properties. This may involve retrying if +// allocations fail. Allocating larger chunk sizes takes priority over +// allocating on the specified node in the following manner: + +// 1. Attempt to allocate the largest chunk on nid. +// 2. If that fails attempt allocation of the largest chunk on any nid. +// 3. If that fails attempt progressively smaller allocations on any nid. +// +// Returns NV_OK on success. Returns NV_WARN_MORE_PROCESSING_REQUIRED if +// UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT was ignored to successfully allocate. +static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, + uvm_chunk_sizes_mask_t cpu_allocation_sizes, + uvm_cpu_chunk_alloc_flags_t flags, + int nid, + uvm_cpu_chunk_t **chunk) +{ + NV_STATUS status = NV_ERR_NO_MEMORY; + uvm_chunk_size_t alloc_size; + bool numa_fallback = false; + + for_each_chunk_size_rev(alloc_size, cpu_allocation_sizes) { + status = block_alloc_cpu_chunk_inject_error(block, alloc_size, flags, nid, chunk); + if (status == NV_OK) + break; + + if (flags & UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT) { + flags &= ~UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT; + numa_fallback = true; + status = block_alloc_cpu_chunk_inject_error(block, alloc_size, flags, NUMA_NO_NODE, chunk); + if (status == NV_OK) + break; + } + } + + UVM_ASSERT(status == NV_OK || status == NV_ERR_NO_MEMORY); + + if (uvm_va_block_is_hmm(block) && status == NV_OK) + (*chunk)->type = UVM_CPU_CHUNK_TYPE_HMM; + + if (numa_fallback && status == NV_OK) + status = NV_WARN_MORE_PROCESSING_REQUIRED; + + return status; +} + +// Find the largest allocation size we can use for the given page_index in the +// given block. Returns the mask of possible sizes and region covered by the +// largest. Callers may also elect to use a smaller size. +static uvm_chunk_sizes_mask_t block_calculate_largest_alloc_size(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + uvm_page_mask_t *allocated_mask, + uvm_chunk_sizes_mask_t cpu_allocation_sizes, + uvm_va_block_region_t *allocated_region) +{ + uvm_chunk_size_t alloc_size; + uvm_chunk_sizes_mask_t allocation_sizes = cpu_allocation_sizes; + + for_each_chunk_size_rev(alloc_size, cpu_allocation_sizes) { + NvU64 alloc_virt_addr; + + // Page must be aligned to the allocation size. + alloc_virt_addr = UVM_ALIGN_DOWN(uvm_va_block_cpu_page_address(va_block, page_index), alloc_size); + + // Allocation region must fit within the VA block. + if (!uvm_va_block_contains_address(va_block, alloc_virt_addr) || + !uvm_va_block_contains_address(va_block, alloc_virt_addr + alloc_size - 1)) { + allocation_sizes &= ~alloc_size; + continue; + } + + *allocated_region = uvm_va_block_region_from_start_end(va_block, + alloc_virt_addr, + alloc_virt_addr + alloc_size - 1); + + // Allocation region can't overlap previously allocated regions. + if (!uvm_page_mask_region_empty(allocated_mask, *allocated_region)) { + allocation_sizes &= ~alloc_size; + continue; + } + + return allocation_sizes; + } + + // No possible size was found. + allocated_region->first = 0; + allocated_region->outer = 0; + + return UVM_CHUNK_SIZE_INVALID; +} + // Handle insertion of overlapping CPU chunks. // In cases where the kernel allocates CPU chunks on NUMA nodes that already // have existing chunks, it's possible that the newly allocated chunk overlaps @@ -1684,7 +1825,7 @@ static NV_STATUS block_alloc_cpu_chunk(uvm_va_block_t *block, // the sub-chunks will be freed in order to maintain proper refcounts on the // parent chunk. static NV_STATUS block_populate_overlapping_cpu_chunks(uvm_va_block_t *block, - uvm_va_block_context_t *block_context, + uvm_page_mask_t *node_pages_mask, uvm_cpu_chunk_t *chunk, uvm_page_index_t page_index) { @@ -1696,7 +1837,6 @@ static NV_STATUS block_populate_overlapping_cpu_chunks(uvm_va_block_t *block, uvm_cpu_chunk_t **split_chunks; uvm_cpu_chunk_t **small_chunks = NULL; uvm_cpu_chunk_t *chunk_ptr; - uvm_page_mask_t *node_pages_mask = &block_context->make_resident.node_pages_mask; uvm_chunk_size_t split_size; size_t i; NV_STATUS status; @@ -1821,6 +1961,60 @@ static NV_STATUS block_populate_overlapping_cpu_chunks(uvm_va_block_t *block, return status; } +// Add the already allocated chunk to the block. Note that this +// handles chunk management on failure, so the caller must not free +// the chunk on failure. +static NV_STATUS block_add_cpu_chunk(uvm_va_block_t *block, + uvm_page_mask_t *node_pages_mask, + uvm_cpu_chunk_t *chunk, + uvm_va_block_region_t region) +{ + NV_STATUS status = NV_OK; + int alloced_nid; + uvm_va_block_cpu_node_state_t *node_state; + uvm_page_index_t page_index = region.first; + + alloced_nid = uvm_cpu_chunk_get_numa_node(chunk); + node_state = block_node_state_get(block, alloced_nid); + if (!uvm_page_mask_region_empty(&node_state->allocated, region)) { + // We may have ended up falling back to allocating the chunk on a + // non-preferred node which may already had a chunk allocated on it in + // which case we can discard the new chunk. + if (uvm_page_mask_region_full(&node_state->allocated, region)) { + uvm_cpu_chunk_free(chunk); + } + else { + // There is no need to free the chunk on failure since + // block_populate_overlapping_cpu_chunks() would already have + // done it. + status = block_populate_overlapping_cpu_chunks(block, node_pages_mask, chunk, page_index); + } + + return status; + } + else { + status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); + if (status != NV_OK) + goto out; + + status = uvm_va_block_map_cpu_chunk_on_gpus(block, chunk, page_index); + if (status != NV_OK) { + uvm_cpu_chunk_remove_from_block(block, uvm_cpu_chunk_get_numa_node(chunk), page_index); + goto out; + } + } + +out: + if (status != NV_OK) { + // We free the chunk even though it was allocated by the caller because + // block_populate_overlapping_cpu_chunks() can fail after freeing the + // orignal chunk so we need to do the same here. + uvm_cpu_chunk_free(chunk); + } + + return status; +} + // Allocates the input page in the block, if it doesn't already exist // // Also maps the page for physical access by all GPUs used by the block, which @@ -1835,11 +2029,12 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, uvm_cpu_chunk_t *chunk; uvm_va_block_test_t *block_test = uvm_va_block_get_test(block); uvm_chunk_sizes_mask_t cpu_allocation_sizes = uvm_cpu_chunk_get_allocation_sizes(); - uvm_chunk_size_t alloc_size; uvm_page_mask_t *resident_mask = &block_context->scratch_page_mask; uvm_page_mask_t *allocated_mask; uvm_cpu_chunk_alloc_flags_t alloc_flags = UVM_CPU_CHUNK_ALLOC_FLAGS_NONE; uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); + // TODO: Bug 4351121: uvm_lite_gpus should be pre-allocated, not on the + // stack. uvm_processor_mask_t uvm_lite_gpus; uvm_page_index_t page_index; uvm_gpu_id_t id; @@ -1852,11 +2047,15 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, if (preferred_nid != NUMA_NO_NODE) { uvm_va_block_cpu_node_state_t *node_state = block_node_state_get(block, preferred_nid); allocated_mask = &node_state->allocated; + alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT; } else { allocated_mask = &block->cpu.allocated; } + if (va_space->test.allow_allocation_from_movable) + alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ALLOW_MOVABLE; + // Check whether all requested pages have already been allocated. uvm_page_mask_init_from_region(&block_context->scratch_page_mask, populate_region, populate_page_mask); if (!uvm_page_mask_andnot(&block_context->scratch_page_mask, @@ -1882,17 +2081,17 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, if (!uvm_processor_mask_empty(&uvm_lite_gpus) || uvm_va_block_is_hmm(block)) cpu_allocation_sizes = PAGE_SIZE; - if (block_context->mm) + if (block_context->mm && !uvm_va_block_is_hmm(block)) alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ACCOUNT; UVM_ASSERT(cpu_allocation_sizes >= PAGE_SIZE); UVM_ASSERT(cpu_allocation_sizes & PAGE_SIZE); for_each_va_block_page_in_region_mask(page_index, populate_page_mask, populate_region) { - uvm_cpu_chunk_alloc_flags_t chunk_alloc_flags; + uvm_cpu_chunk_alloc_flags_t chunk_alloc_flags = alloc_flags; uvm_va_block_region_t region = populate_region; - uvm_va_block_cpu_node_state_t *node_state; - int alloced_nid; + uvm_page_mask_t *node_pages_mask = &block_context->make_resident.node_pages_mask; + uvm_chunk_sizes_mask_t allocation_sizes; if (uvm_page_mask_test(allocated_mask, page_index)) { page_index = uvm_va_block_next_unset_page_in_mask(populate_region, allocated_mask, page_index) - 1; @@ -1901,87 +2100,58 @@ static NV_STATUS block_populate_pages_cpu(uvm_va_block_t *block, UVM_ASSERT(!uvm_va_block_cpu_is_page_resident_on(block, preferred_nid, page_index)); - chunk_alloc_flags = alloc_flags; - - // Attempt to allocate CPU pages with the largest physically contiguous - // size from the set of CPU chunk sizes that we can. - // This is accomplished by: - // 1. Aligning the CPU page address down to the allocation size. - // 2. Ensuring that the entire allocation region fits withing the VA - // block. - // 3. Ensuring that the region covered by the allocation is empty. - for_each_chunk_size_rev(alloc_size, cpu_allocation_sizes) { - NvU64 alloc_virt_addr; - - chunk = NULL; - alloc_virt_addr = UVM_ALIGN_DOWN(uvm_va_block_cpu_page_address(block, page_index), alloc_size); - - if (!uvm_va_block_contains_address(block, alloc_virt_addr) || - !uvm_va_block_contains_address(block, alloc_virt_addr + alloc_size - 1)) - continue; - - region = uvm_va_block_region_from_start_end(block, alloc_virt_addr, alloc_virt_addr + alloc_size - 1); - - if (!uvm_page_mask_region_empty(allocated_mask, region)) - continue; + allocation_sizes = block_calculate_largest_alloc_size(block, + page_index, + allocated_mask, + cpu_allocation_sizes, + ®ion); + if (allocation_sizes == UVM_CHUNK_SIZE_INVALID) + return NV_ERR_NO_MEMORY; - // If not all pages in the allocation region are resident somewhere, - // zero out the allocated page. - // This could be wasteful if only a few pages in high-order - // allocation need to be zero'ed out but the alternative is to map - // single sub-pages one-by-one. - if (!uvm_page_mask_region_full(resident_mask, region)) - chunk_alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO; + // If not all pages in the allocation region are resident somewhere, + // zero out the allocated page. + // This could be wasteful if only a few pages in high-order + // allocation need to be zero'ed out but the alternative is to map + // single sub-pages one-by-one. + if (!uvm_page_mask_region_full(resident_mask, region)) + chunk_alloc_flags |= UVM_CPU_CHUNK_ALLOC_FLAGS_ZERO; - status = block_alloc_cpu_chunk(block, alloc_size, chunk_alloc_flags, preferred_nid, &chunk); - if (status == NV_OK) { - page_index = region.first; - break; - } - - UVM_ASSERT(status == NV_ERR_NO_MEMORY); + status = block_alloc_cpu_chunk(block, allocation_sizes, chunk_alloc_flags, preferred_nid, &chunk); + if (status == NV_WARN_MORE_PROCESSING_REQUIRED) { + alloc_flags &= ~UVM_CPU_CHUNK_ALLOC_FLAGS_STRICT; + preferred_nid = NUMA_NO_NODE; + block_context->make_resident.dest_nid = NUMA_NO_NODE; } - - if (status != NV_OK) - break; - - alloced_nid = uvm_cpu_chunk_get_numa_node(chunk); - node_state = block_node_state_get(block, alloced_nid); - if (!uvm_page_mask_region_empty(&node_state->allocated, region)) { - UVM_ASSERT(preferred_nid != NUMA_NO_NODE); - - if (uvm_page_mask_region_full(&node_state->allocated, region)) { - uvm_cpu_chunk_free(chunk); - goto skip; - } - - status = block_populate_overlapping_cpu_chunks(block, block_context, chunk, page_index); - if (status != NV_OK) - return status; + else if (status != NV_OK) { + return status; } - else { - status = uvm_cpu_chunk_insert_in_block(block, chunk, page_index); - if (status != NV_OK) { - uvm_cpu_chunk_free(chunk); - return status; - } - status = uvm_va_block_map_cpu_chunk_on_gpus(block, chunk, page_index); - if (status != NV_OK) - break; - } + // A smaller chunk than the maximum size may have been allocated, update the region accordingly. + region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); + status = block_add_cpu_chunk(block, node_pages_mask, chunk, region); + if (status != NV_OK) + return status; -skip: // Skip iterating over all pages covered by the allocated chunk. page_index = region.outer - 1; - } - if (status != NV_OK && chunk) { - uvm_cpu_chunk_remove_from_block(block, uvm_cpu_chunk_get_numa_node(chunk), page_index); - uvm_cpu_chunk_free(chunk); +#if UVM_IS_CONFIG_HMM() + if (uvm_va_block_is_hmm(block) && block_context) + block_context->hmm.dst_pfns[page_index] = migrate_pfn(page_to_pfn(chunk->page)); +#endif } - return status; + return NV_OK; +} + +// Note this clears the block_context caller_page_mask. +NV_STATUS uvm_va_block_populate_page_cpu(uvm_va_block_t *va_block, uvm_page_index_t page_index, uvm_va_block_context_t *block_context) +{ + uvm_page_mask_t *page_mask = &block_context->caller_page_mask; + + uvm_page_mask_zero(page_mask); + uvm_page_mask_set(page_mask, page_index); + return block_populate_pages_cpu(va_block, page_mask, uvm_va_block_region_from_block(va_block), block_context); } // Try allocating a chunk. If eviction was required, @@ -2281,6 +2451,28 @@ static NvU32 block_phys_page_size(uvm_va_block_t *block, block_phys_page_t page) return (NvU32)chunk_size; } +NvU32 uvm_va_block_get_physical_size(uvm_va_block_t *block, + uvm_processor_id_t processor, + uvm_page_index_t page_index) +{ + int nid = NUMA_NO_NODE; + block_phys_page_t page; + + UVM_ASSERT(block); + + uvm_assert_mutex_locked(&block->lock); + + if (UVM_ID_IS_CPU(processor)) { + nid = block_get_page_node_residency(block, page_index); + if (nid == NUMA_NO_NODE) + return 0; + } + + page = block_phys_page(processor, nid, page_index); + + return block_phys_page_size(block, page); +} + static uvm_pte_bits_cpu_t get_cpu_pte_bit_index(uvm_prot_t prot) { uvm_pte_bits_cpu_t pte_bit_index = UVM_PTE_BITS_CPU_MAX; @@ -2379,7 +2571,6 @@ void uvm_va_block_unmapped_pages_get(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_page_mask_t *out_mask) { - uvm_processor_mask_t non_uvm_lite_gpus; uvm_processor_id_t id; uvm_assert_mutex_locked(&va_block->lock); @@ -2390,9 +2581,8 @@ void uvm_va_block_unmapped_pages_get(uvm_va_block_t *va_block, } uvm_page_mask_region_fill(out_mask, region); - uvm_processor_mask_andnot(&non_uvm_lite_gpus, &va_block->mapped, block_get_uvm_lite_gpus(va_block)); - for_each_id_in_mask(id, &non_uvm_lite_gpus) { + for_each_id_in_mask(id, &va_block->mapped) { uvm_page_mask_andnot(out_mask, out_mask, uvm_va_block_map_mask_get(va_block, id)); } } @@ -2986,7 +3176,9 @@ static NV_STATUS block_populate_pages(uvm_va_block_t *block, const uvm_page_mask_t *page_mask) { NV_STATUS status; - const uvm_page_mask_t *resident_mask = block_resident_mask_get_alloc(block, dest_id, NUMA_NO_NODE); + const uvm_page_mask_t *resident_mask = block_resident_mask_get_alloc(block, + dest_id, + block_context->make_resident.dest_nid); uvm_page_mask_t *populate_page_mask = &block_context->make_resident.page_mask; uvm_page_mask_t *pages_staged = &block_context->make_resident.pages_staged; uvm_page_mask_t *cpu_populate_mask; @@ -3096,7 +3288,7 @@ static uvm_gpu_phys_address_t block_phys_page_address(uvm_va_block_t *block, if (UVM_ID_IS_CPU(block_page.processor)) { uvm_cpu_chunk_t *chunk = uvm_cpu_chunk_get_chunk_for_page(block, block_page.nid, block_page.page_index); - NvU64 dma_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + NvU64 dma_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent); uvm_va_block_region_t chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), block_page.page_index); @@ -3210,6 +3402,9 @@ typedef struct block_copy_addr_t src; block_copy_addr_t dst; uvm_conf_computing_dma_buffer_t *dma_buffer; + // True if at least one CE transfer (such as a memcopy) has already been + // pushed to the GPU during the VA block copy thus far. + bool copy_pushed; } block_copy_state_t; // Begin a push appropriate for copying data from src_id processor to dst_id processor. @@ -3226,12 +3421,26 @@ static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, uvm_processor_id_t dst_id = copy_state->dst.id; uvm_processor_id_t src_id = copy_state->src.id; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); - UVM_ASSERT_MSG(!uvm_id_equal(src_id, dst_id), - "Unexpected copy to self, processor %s\n", - block_processor_name(va_block, src_id)); + if (!(uvm_block_cpu_to_cpu_copy_with_ce || va_space->test.force_cpu_to_cpu_copy_with_ce) || + UVM_ID_IS_GPU(src_id) || + UVM_ID_IS_GPU(dst_id)) { + UVM_ASSERT_MSG(!uvm_id_equal(src_id, dst_id), + "Unexpected copy to self, processor %s\n", + block_processor_name(va_block, src_id)); + } + + if (UVM_ID_IS_CPU(src_id) && UVM_ID_IS_CPU(dst_id)) { + uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); + + gpu = uvm_va_space_find_first_gpu_attached_to_cpu_node(va_space, copy_state->src.nid); + if (!gpu) + gpu = uvm_va_space_find_first_gpu(va_space); - if (UVM_ID_IS_CPU(src_id)) { + channel_type = UVM_CHANNEL_TYPE_CPU_TO_GPU; + } + else if (UVM_ID_IS_CPU(src_id)) { gpu = block_get_gpu(va_block, dst_id); channel_type = UVM_CHANNEL_TYPE_CPU_TO_GPU; } @@ -3271,8 +3480,8 @@ static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, va_block->end); } - if (uvm_conf_computing_mode_enabled(gpu)) { - // When the Confidential Feature is enabled, additional dependencies + if (g_uvm_global.conf_computing_enabled) { + // When Confidential Computing is enabled, additional dependencies // apply to the input tracker as well as the dma_buffer tracker. // * In the CPU to GPU case, because UVM performs CPU side // crypto-operations first before the GPU copy, we both need to @@ -3318,39 +3527,46 @@ static NV_STATUS block_copy_begin_push(uvm_va_block_t *va_block, } // A page is clean iff... -// the destination is the preferred location and +// the destination is equal to the preferred location // the source is the CPU and +// the destination is not the CPU // the destination does not support faults/eviction and // the CPU page is not dirty static bool block_page_is_clean(uvm_va_block_t *block, uvm_processor_id_t dst_id, + int dst_nid, uvm_processor_id_t src_id, - uvm_page_index_t page_index, - int nid) + int src_nid, + uvm_page_index_t page_index) { return !uvm_va_block_is_hmm(block) && - uvm_id_equal(dst_id, uvm_va_range_get_policy(block->va_range)->preferred_location) && + uvm_va_policy_preferred_location_equal(uvm_va_range_get_policy(block->va_range), dst_id, dst_nid) && UVM_ID_IS_CPU(src_id) && + !UVM_ID_IS_CPU(dst_id) && !block_get_gpu(block, dst_id)->parent->isr.replayable_faults.handling && - !block_cpu_page_is_dirty(block, page_index, nid); + !block_cpu_page_is_dirty(block, page_index, src_nid); } // When the destination is the CPU... -// if the source is the preferred location, mark as clean +// if the source is the preferred location and NUMA node id, mark as clean // otherwise, mark as dirty static void block_update_page_dirty_state(uvm_va_block_t *block, uvm_processor_id_t dst_id, + int dst_nid, uvm_processor_id_t src_id, - int nid, + int src_nid, uvm_page_index_t page_index) { + uvm_va_policy_t *policy; + if (UVM_ID_IS_GPU(dst_id)) return; - if (uvm_id_equal(src_id, uvm_va_range_get_policy(block->va_range)->preferred_location)) - block_mark_cpu_page_clean(block, page_index, nid); + policy = uvm_va_range_get_policy(block->va_range); + if (uvm_va_policy_preferred_location_equal(policy, src_id, src_nid)) + block_mark_cpu_page_clean(block, page_index, dst_nid); else - block_mark_cpu_page_dirty(block, page_index, nid); + block_mark_cpu_page_dirty(block, page_index, dst_nid); } static void block_mark_memory_used(uvm_va_block_t *block, uvm_processor_id_t id) @@ -3367,7 +3583,7 @@ static void block_mark_memory_used(uvm_va_block_t *block, uvm_processor_id_t id) // HMM always allocates PAGE_SIZE GPU chunks so skip HMM va_blocks. if (!uvm_va_block_is_hmm(block) && uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && - uvm_gpu_supports_eviction(gpu)) { + uvm_parent_gpu_supports_eviction(gpu->parent)) { // The chunk has to be there if this GPU is resident UVM_ASSERT(uvm_processor_mask_test(&block->resident, id)); uvm_pmm_gpu_mark_root_chunk_used(&gpu->pmm, uvm_va_block_gpu_state_get(block, gpu->id)->chunks[0]); @@ -3402,7 +3618,7 @@ static void block_clear_resident_processor(uvm_va_block_t *block, uvm_processor_ // root chunk as unused in PMM. if (!uvm_va_block_is_hmm(block) && uvm_va_block_size(block) == UVM_CHUNK_SIZE_MAX && - uvm_gpu_supports_eviction(gpu)) { + uvm_parent_gpu_supports_eviction(gpu->parent)) { // The chunk may not be there any more when residency is cleared. uvm_va_block_gpu_state_t *gpu_state = uvm_va_block_gpu_state_get(block, gpu->id); if (gpu_state && gpu_state->chunks[0]) @@ -3499,18 +3715,18 @@ static void conf_computing_block_copy_push_cpu_to_gpu(uvm_va_block_t *block, UVM_ASSERT(UVM_ID_IS_CPU(copy_state->src.id)); UVM_ASSERT(UVM_ID_IS_GPU(copy_state->dst.id)); - - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); // See comment in block_copy_begin_push. UVM_ASSERT(uvm_tracker_is_completed(&block->tracker)); chunk = uvm_cpu_chunk_get_chunk_for_page(block, copy_state->src.nid, page_index); UVM_ASSERT(chunk); + // The caller guarantees that all pages in region are contiguous, // meaning they're guaranteed to be part of the same compound page. chunk_region = uvm_va_block_chunk_region(block, uvm_cpu_chunk_get_size(chunk), page_index); - UVM_ASSERT(uvm_va_block_region_contains_region(region, chunk_region)); + UVM_ASSERT(uvm_va_block_region_contains_region(chunk_region, region)); src_page = uvm_cpu_chunk_get_cpu_page(block, chunk, page_index); staging_buffer.address += page_index * PAGE_SIZE; @@ -3535,11 +3751,8 @@ static void conf_computing_block_copy_push_cpu_to_gpu(uvm_va_block_t *block, cpu_auth_tag_buffer); kunmap(src_page); - // First LCE operation should be non-pipelined to guarantee ordering as - // we do not know when was the last non-pipelined copy. - // Last one applies the membar originally planned for the push if any - // TODO: 3857691: Inherit policy instead of forcing first invocation to - // be non pipelined. + // All but the first decryption can be pipelined. The first decryption + // uses the caller's pipelining settings. if (page_index > region.first) uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); @@ -3577,8 +3790,7 @@ static void conf_computing_block_copy_push_gpu_to_cpu(uvm_va_block_t *block, UVM_ASSERT(UVM_ID_IS_GPU(copy_state->src.id)); UVM_ASSERT(UVM_ID_IS_CPU(copy_state->dst.id)); - - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); staging_buffer.address += page_index * PAGE_SIZE; auth_tag_buffer.address += page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE; @@ -3594,11 +3806,8 @@ static void conf_computing_block_copy_push_gpu_to_cpu(uvm_va_block_t *block, for_each_va_block_page_in_region(page_index, region) { uvm_conf_computing_log_gpu_encryption(push->channel, &dma_buffer->decrypt_iv[page_index]); - // First LCE operation should be non-pipelined to guarantee ordering as - // we do not know when was the last non-pipelined copy. - // Last one applies the membar originally planned for the push if any - // TODO: 3857691: Inherit policy instead of forcing first invocation to - // be non pipelined. + // All but the first encryption can be pipelined. The first encryption + // uses the caller's pipelining settings. if (page_index > region.first) uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); @@ -3628,7 +3837,7 @@ static NV_STATUS conf_computing_copy_pages_finish(uvm_va_block_t *block, void *auth_tag_buffer_base = uvm_mem_get_cpu_addr_kernel(dma_buffer->auth_tag); void *staging_buffer_base = uvm_mem_get_cpu_addr_kernel(dma_buffer->alloc); - UVM_ASSERT(uvm_conf_computing_mode_enabled(push->gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); if (UVM_ID_IS_GPU(copy_state->dst.id)) return NV_OK; @@ -3642,7 +3851,11 @@ static NV_STATUS conf_computing_copy_pages_finish(uvm_va_block_t *block, // kmap() only guarantees PAGE_SIZE contiguity, all encryption and // decryption must happen on a PAGE_SIZE basis. for_each_va_block_page_in_mask(page_index, encrypted_page_mask, block) { - struct page *dst_page = uvm_va_block_get_cpu_page(block, page_index); + // All CPU chunks for the copy have already been allocated in + // block_populate_pages() and copy_state has been filled in based on + // those allocations. + uvm_cpu_chunk_t *cpu_chunk = uvm_cpu_chunk_get_chunk_for_page(block, copy_state->dst.nid, page_index); + struct page *dst_page = uvm_cpu_chunk_get_cpu_page(block, cpu_chunk, page_index); void *staging_buffer = (char *)staging_buffer_base + (page_index * PAGE_SIZE); void *auth_tag_buffer = (char *)auth_tag_buffer_base + (page_index * UVM_CONF_COMPUTING_AUTH_TAG_SIZE); void *cpu_page_address = kmap(dst_page); @@ -3673,24 +3886,33 @@ static void block_copy_push(uvm_va_block_t *block, uvm_va_block_region_t region, uvm_push_t *push) { - uvm_gpu_address_t gpu_dst_address; - uvm_gpu_address_t gpu_src_address; + uvm_gpu_address_t gpu_dst_address, gpu_src_address; uvm_gpu_t *gpu = uvm_push_get_gpu(push); + // Only the first transfer is not pipelined. Since the callees observe the + // caller's pipeline settings, pipelining must be disabled in that first + // transfer. + if (copy_state->copy_pushed) + uvm_push_set_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + else + UVM_ASSERT(!uvm_push_test_flag(push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED)); + uvm_push_set_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE); - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { if (UVM_ID_IS_CPU(copy_state->src.id)) conf_computing_block_copy_push_cpu_to_gpu(block, copy_state, region, push); else conf_computing_block_copy_push_gpu_to_cpu(block, copy_state, region, push); + } + else { + gpu_dst_address = block_copy_get_address(block, ©_state->dst, region.first, gpu); + gpu_src_address = block_copy_get_address(block, ©_state->src, region.first, gpu); - return; + gpu->parent->ce_hal->memcopy(push, gpu_dst_address, gpu_src_address, uvm_va_block_region_size(region)); } - gpu_dst_address = block_copy_get_address(block, ©_state->dst, region.first, gpu); - gpu_src_address = block_copy_get_address(block, ©_state->src, region.first, gpu); - gpu->parent->ce_hal->memcopy(push, gpu_dst_address, gpu_src_address, uvm_va_block_region_size(region)); + copy_state->copy_pushed = true; } static NV_STATUS block_copy_end_push(uvm_va_block_t *block, @@ -3707,14 +3929,14 @@ static NV_STATUS block_copy_end_push(uvm_va_block_t *block, // at that point. uvm_push_end(push); - if ((push_status == NV_OK) && uvm_conf_computing_mode_enabled(push->gpu)) + if ((push_status == NV_OK) && g_uvm_global.conf_computing_enabled) push_status = conf_computing_copy_pages_finish(block, copy_state, push); tracker_status = uvm_tracker_add_push_safe(copy_tracker, push); if (push_status == NV_OK) push_status = tracker_status; - if (uvm_conf_computing_mode_enabled(push->gpu)) { + if (g_uvm_global.conf_computing_enabled) { uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); uvm_tracker_overwrite_with_push(&local_tracker, push); @@ -3728,6 +3950,67 @@ static NV_STATUS block_copy_end_push(uvm_va_block_t *block, return push_status; } +// Copies use CEs if: +// - uvm_block_cpu_to_cpu_copy_with_ce or +// uvm_test_force_block_cpu_to_cpu_copy_with_ce are set AND there are +// registered GPUs in the VA space. +// - the source and destination are not the CPU. +static bool block_copy_should_use_push(uvm_va_block_t *block, block_copy_state_t *copy_state) +{ + uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); + + return ((uvm_block_cpu_to_cpu_copy_with_ce || va_space->test.force_cpu_to_cpu_copy_with_ce) && + uvm_processor_mask_get_gpu_count(&va_space->registered_gpus)) || + !(UVM_ID_IS_CPU(copy_state->src.id) && uvm_id_equal(copy_state->src.id, copy_state->dst.id)); +} + +static NV_STATUS block_copy_pages(uvm_va_block_t *va_block, + block_copy_state_t *copy_state, + uvm_va_block_region_t region, + uvm_push_t *push) +{ + if (!block_copy_should_use_push(va_block, copy_state)) { + uvm_cpu_chunk_t *src_chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, copy_state->src.nid, region.first); + uvm_cpu_chunk_t *dst_chunk = uvm_cpu_chunk_get_chunk_for_page(va_block, copy_state->dst.nid, region.first); + uvm_va_block_region_t src_chunk_region = uvm_cpu_chunk_block_region(va_block, src_chunk, region.first); + uvm_va_block_region_t dst_chunk_region = uvm_cpu_chunk_block_region(va_block, dst_chunk, region.first); + struct page *src_chunk_page = uvm_cpu_chunk_get_cpu_page(va_block, src_chunk, src_chunk_region.first); + struct page *dst_chunk_page = uvm_cpu_chunk_get_cpu_page(va_block, dst_chunk, dst_chunk_region.first); + uvm_page_index_t page_index; + NV_STATUS status; + + UVM_ASSERT(dst_chunk); + UVM_ASSERT(uvm_cpu_chunk_get_size(src_chunk) >= uvm_va_block_region_size(region)); + UVM_ASSERT(uvm_cpu_chunk_get_size(src_chunk) <= uvm_cpu_chunk_get_size(dst_chunk)); + + // CPU-to-CPU copies using memcpy() don't have any inherent ordering with + // copies using GPU CEs. So, we have to make sure that all previously + // submitted work is complete. + status = uvm_tracker_wait(&va_block->tracker); + if (status != NV_OK) + return status; + + for_each_va_block_page_in_region(page_index, region) { + struct page *src_page = src_chunk_page + (page_index - src_chunk_region.first); + struct page *dst_page = dst_chunk_page + (page_index - dst_chunk_region.first); + void *src_addr = kmap(src_page); + void *dst_addr = kmap(dst_page); + + memcpy(dst_addr, src_addr, PAGE_SIZE); + kunmap(src_addr); + kunmap(dst_addr); + + if (block_cpu_page_is_dirty(va_block, page_index, copy_state->src.nid)) + block_mark_cpu_page_dirty(va_block, page_index, copy_state->dst.nid); + } + } + else { + block_copy_push(va_block, copy_state, region, push); + } + + return NV_OK; +} + // Copies pages resident on the src_id processor to the dst_id processor // // The function adds the pages that were successfully copied to the output @@ -3766,11 +4049,11 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, block_copy_state_t copy_state = {0}; uvm_va_range_t *va_range = block->va_range; uvm_va_space_t *va_space = uvm_va_block_get_va_space(block); + uvm_va_block_region_t contig_region = {0}; + NvU64 cpu_migration_begin_timestamp = 0; *copied_pages = 0; - UVM_ASSERT(UVM_ID_IS_GPU(src_id) || UVM_ID_IS_GPU(dst_id)); - if (UVM_ID_IS_CPU(src_id)) UVM_ASSERT(src_nid != NUMA_NO_NODE); @@ -3818,7 +4101,7 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, // the use of range_group's migrated_ranges list is a UVM-Lite // optimization - eviction is not supported on UVM-Lite GPUs. if (cause != UVM_MAKE_RESIDENT_CAUSE_EVICTION && !uvm_va_block_is_hmm(block) && - uvm_id_equal(src_id, uvm_va_range_get_policy(va_range)->preferred_location)) { + uvm_va_policy_preferred_location_equal(uvm_va_range_get_policy(va_range), src_id, src_nid)) { // rgr_has_changed is used to minimize the number of times the // migrated_ranges_lock is taken. It is set to false when the range // group range pointed by rgr is added to the migrated_ranges list, @@ -3849,33 +4132,51 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, // No need to copy pages that haven't changed. Just clear residency // information - if (block_page_is_clean(block, dst_id, src_id, page_index, copy_state.src.nid)) + if (block_page_is_clean(block, dst_id, copy_state.dst.nid, src_id, copy_state.src.nid, page_index)) continue; - if (!copying_gpu) { - status = block_copy_begin_push(block, ©_state, &block->tracker, &push); - - if (status != NV_OK) - break; - copying_gpu = uvm_push_get_gpu(&push); - - // Record all processors involved in the copy - uvm_processor_mask_set(&block_context->make_resident.all_involved_processors, copying_gpu->id); + if (last_index == region.outer) { + // Record all processors involved in the copy. uvm_processor_mask_set(&block_context->make_resident.all_involved_processors, dst_id); uvm_processor_mask_set(&block_context->make_resident.all_involved_processors, src_id); + } + + if (block_copy_should_use_push(block, ©_state)) { + if (!copying_gpu) { + status = block_copy_begin_push(block, ©_state, &block->tracker, &push); + + if (status != NV_OK) + break; - // This function is called just once per VA block and needs to - // receive the "main" cause for the migration (it mainly checks if - // we are in the eviction path). Therefore, we pass cause instead - // of contig_cause - uvm_tools_record_block_migration_begin(block, &push, dst_id, src_id, page_start, cause); + copying_gpu = uvm_push_get_gpu(&push); + + // Ensure that there is GPU state that can be used for CPU-to-CPU copies + if (UVM_ID_IS_CPU(dst_id) && uvm_id_equal(src_id, dst_id)) { + uvm_va_block_gpu_state_t *gpu_state = block_gpu_state_get_alloc(block, copying_gpu); + if (!gpu_state) { + status = NV_ERR_NO_MEMORY; + break; + } + } + + // Record the GPU involved in the copy + uvm_processor_mask_set(&block_context->make_resident.all_involved_processors, copying_gpu->id); + + // This function is called just once per VA block and needs to + // receive the "main" cause for the migration (it mainly checks if + // we are in the eviction path). Therefore, we pass cause instead + // of contig_cause + uvm_tools_record_block_migration_begin(block, &push, dst_id, src_id, page_start, cause); + } } else { - uvm_push_set_flag(&push, UVM_PUSH_FLAG_CE_NEXT_PIPELINED); + // For CPU-to-CPU copies using memcpy(), record the start of the + // migration here. This will be reported in the migration event. + cpu_migration_begin_timestamp = NV_GETTIME(); } if (!uvm_va_block_is_hmm(block)) - block_update_page_dirty_state(block, dst_id, src_id, copy_state.dst.nid, page_index); + block_update_page_dirty_state(block, dst_id, copy_state.dst.nid, src_id, copy_state.src.nid, page_index); if (last_index == region.outer) { bool can_cache_src_phys_addr = copy_state.src.is_block_contig; @@ -3883,82 +4184,121 @@ static NV_STATUS block_copy_resident_pages_between(uvm_va_block_t *block, contig_start_index = page_index; contig_cause = page_cause; - // When CC is enabled, transfers between GPU and CPU don't rely on - // any GPU mapping of CPU chunks, physical or virtual. - if (UVM_ID_IS_CPU(src_id) && uvm_conf_computing_mode_enabled(copying_gpu)) - can_cache_src_phys_addr = false; - if (UVM_ID_IS_CPU(dst_id) && uvm_conf_computing_mode_enabled(copying_gpu)) - can_cache_dst_phys_addr = false; - // Computing the physical address is a non-trivial operation and - // seems to be a performance limiter on systems with 2 or more - // NVLINK links. Therefore, for physically-contiguous block - // storage, we cache the start address and compute the page address - // using the page index. - if (can_cache_src_phys_addr) { - copy_state.src.gpu_address = block_phys_page_copy_address(block, - block_phys_page(src_id, - copy_state.src.nid, - 0), - copying_gpu); - } - if (can_cache_dst_phys_addr) { - copy_state.dst.gpu_address = block_phys_page_copy_address(block, - block_phys_page(dst_id, - copy_state.dst.nid, - 0), - copying_gpu); + if (block_copy_should_use_push(block, ©_state)) { + // When CC is enabled, transfers between GPU and CPU don't rely on + // any GPU mapping of CPU chunks, physical or virtual. + if (UVM_ID_IS_CPU(src_id) && g_uvm_global.conf_computing_enabled) + can_cache_src_phys_addr = false; + + if (UVM_ID_IS_CPU(dst_id) && g_uvm_global.conf_computing_enabled) + can_cache_dst_phys_addr = false; + // Computing the physical address is a non-trivial operation and + // seems to be a performance limiter on systems with 2 or more + // NVLINK links. Therefore, for physically-contiguous block + // storage, we cache the start address and compute the page address + // using the page index. + if (can_cache_src_phys_addr) { + copy_state.src.gpu_address = block_phys_page_copy_address(block, + block_phys_page(src_id, + copy_state.src.nid, + 0), + copying_gpu); + } + if (can_cache_dst_phys_addr) { + copy_state.dst.gpu_address = block_phys_page_copy_address(block, + block_phys_page(dst_id, + copy_state.dst.nid, + 0), + copying_gpu); + } } } else if ((page_index != last_index + 1) || contig_cause != page_cause) { - uvm_va_block_region_t contig_region = uvm_va_block_region(contig_start_index, last_index + 1); + contig_region = uvm_va_block_region(contig_start_index, last_index + 1); UVM_ASSERT(uvm_va_block_region_contains_region(region, contig_region)); // If both src and dst are physically-contiguous, consolidate copies // of contiguous pages into a single method. - if (copy_state.src.is_block_contig && copy_state.dst.is_block_contig) - block_copy_push(block, ©_state, contig_region, &push); + if (copy_state.src.is_block_contig && copy_state.dst.is_block_contig) { + status = block_copy_pages(block, ©_state, contig_region, &push); + if (status != NV_OK) + break; + } - uvm_perf_event_notify_migration(&va_space->perf_events, - &push, - block, - dst_id, - src_id, - uvm_va_block_region_start(block, contig_region), - uvm_va_block_region_size(contig_region), - transfer_mode, - contig_cause, - &block_context->make_resident); + if (block_copy_should_use_push(block, ©_state)) { + uvm_perf_event_notify_migration(&va_space->perf_events, + &push, + block, + dst_id, + src_id, + uvm_va_block_region_start(block, contig_region), + uvm_va_block_region_size(contig_region), + transfer_mode, + contig_cause, + &block_context->make_resident); + } + else { + uvm_perf_event_notify_migration_cpu(&va_space->perf_events, + block, + copy_state.dst.nid, + copy_state.src.nid, + uvm_va_block_region_start(block, contig_region), + uvm_va_block_region_size(contig_region), + cpu_migration_begin_timestamp, + transfer_mode, + contig_cause, + &block_context->make_resident); + } contig_start_index = page_index; contig_cause = page_cause; } - if (!copy_state.src.is_block_contig || !copy_state.dst.is_block_contig) - block_copy_push(block, ©_state, uvm_va_block_region_for_page(page_index), &push); + if (!copy_state.src.is_block_contig || !copy_state.dst.is_block_contig) { + status = block_copy_pages(block, ©_state, uvm_va_block_region_for_page(page_index), &push); + if (status != NV_OK) + return status; + } last_index = page_index; } // Copy the remaining pages - if (copying_gpu) { - uvm_va_block_region_t contig_region = uvm_va_block_region(contig_start_index, last_index + 1); - UVM_ASSERT(uvm_va_block_region_contains_region(region, contig_region)); - - if (copy_state.src.is_block_contig && copy_state.dst.is_block_contig) - block_copy_push(block, ©_state, contig_region, &push); + contig_region = uvm_va_block_region(contig_start_index, last_index + 1); + if (uvm_va_block_region_size(contig_region) && uvm_va_block_region_contains_region(region, contig_region)) { + if (copy_state.src.is_block_contig && copy_state.dst.is_block_contig) { + status = block_copy_pages(block, ©_state, contig_region, &push); + if (status != NV_OK) + return status; + } - uvm_perf_event_notify_migration(&va_space->perf_events, - &push, - block, - dst_id, - src_id, - uvm_va_block_region_start(block, contig_region), - uvm_va_block_region_size(contig_region), - transfer_mode, - contig_cause, - &block_context->make_resident); + if (block_copy_should_use_push(block, ©_state)) { + uvm_perf_event_notify_migration(&va_space->perf_events, + &push, + block, + dst_id, + src_id, + uvm_va_block_region_start(block, contig_region), + uvm_va_block_region_size(contig_region), + transfer_mode, + contig_cause, + &block_context->make_resident); + } + else { + uvm_perf_event_notify_migration_cpu(&va_space->perf_events, + block, + copy_state.dst.nid, + copy_state.src.nid, + uvm_va_block_region_start(block, contig_region), + uvm_va_block_region_size(contig_region), + cpu_migration_begin_timestamp, + transfer_mode, + contig_cause, + &block_context->make_resident); + } - status = block_copy_end_push(block, ©_state, copy_tracker, status, &push); + if (block_copy_should_use_push(block, ©_state) && copying_gpu) + status = block_copy_end_push(block, ©_state, copy_tracker, status, &push); } // Update VA block status bits @@ -4003,7 +4343,7 @@ static NV_STATUS block_copy_resident_pages_from(uvm_va_block_t *block, if (UVM_ID_IS_CPU(dst_id)) { for_each_node_mask(dst_nid, page_tracking->nodes) { - if (!uvm_page_mask_and(node_pages_mask, copy_mask, page_tracking->node_masks[node_to_index(dst_nid)])) + if (!uvm_page_mask_and(node_pages_mask, copy_mask, block_tracking_node_mask_get(block_context, dst_nid))) continue; status = block_copy_resident_pages_between(block, @@ -4079,8 +4419,6 @@ static NV_STATUS block_copy_resident_pages_mask(uvm_va_block_t *block, for_each_closest_id(src_id, &search_mask, dst_id, va_space) { NV_STATUS status; - UVM_ASSERT(!uvm_id_equal(src_id, dst_id)); - if (UVM_ID_IS_CPU(src_id)) { int nid; @@ -4152,15 +4490,16 @@ static void break_read_duplication_in_region(uvm_va_block_t *block, for_each_id_in_mask(id, &block->resident) { uvm_page_mask_t *other_resident_mask; - if (uvm_id_equal(id, dst_id)) + // Skip the destination processor, unless it's the CPU and a specific + // NUMA node is the target destination. This is because CPU-to-CPU + // migrations will switch the residency from one NUMA node to another + // but the resident processor will remain the CPU. + if (uvm_id_equal(id, dst_id) && + (!UVM_ID_IS_CPU(dst_id) || block_context->make_resident.dest_nid == NUMA_NO_NODE)) continue; if (UVM_ID_IS_CPU(id)) { - int nid; - - for_each_possible_uvm_node(nid) - uvm_va_block_cpu_clear_resident_mask(block, nid, break_pages_in_region); - + uvm_va_block_cpu_clear_resident_all_chunks(block, block_context, break_pages_in_region); other_resident_mask = uvm_va_block_resident_mask_get(block, UVM_ID_CPU, NUMA_NO_NODE); } else { @@ -4224,13 +4563,10 @@ static void block_select_cpu_node_pages(uvm_va_block_t *block, { uvm_va_block_cpu_node_state_t *node_state; uvm_make_resident_page_tracking_t *tracking = &block_context->make_resident.cpu_pages_used; - uvm_page_mask_t **node_masks = tracking->node_masks; uvm_page_mask_t *scratch_page_mask = &block_context->scratch_page_mask; - size_t index; + uvm_page_mask_t *node_mask; int nid; - nodes_clear(tracking->nodes); - if (uvm_page_mask_empty(page_mask)) return; @@ -4239,10 +4575,10 @@ static void block_select_cpu_node_pages(uvm_va_block_t *block, for_each_closest_uvm_node(nid, uvm_va_block_context_get_node(block_context), block_context->scratch_node_mask) { node_state = block_node_state_get(block, nid); - index = node_to_index(nid); - if (uvm_page_mask_and(node_masks[index], scratch_page_mask, &node_state->allocated)) { + node_mask = block_tracking_node_mask_get(block_context, nid); + if (uvm_page_mask_and(node_mask, scratch_page_mask, &node_state->allocated)) { node_set(nid, tracking->nodes); - if (!uvm_page_mask_andnot(scratch_page_mask, scratch_page_mask, node_masks[index])) + if (!uvm_page_mask_andnot(scratch_page_mask, scratch_page_mask, node_mask)) return; } } @@ -4264,7 +4600,9 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, NV_STATUS status = NV_OK; NV_STATUS tracker_status; uvm_tracker_t local_tracker = UVM_TRACKER_INIT(); - uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, dst_id, NUMA_NO_NODE); + uvm_page_mask_t *resident_mask = uvm_va_block_resident_mask_get(block, + dst_id, + block_context->make_resident.dest_nid); NvU32 missing_pages_count; NvU32 pages_copied; NvU32 pages_copied_to_cpu = 0; @@ -4273,6 +4611,7 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, uvm_page_mask_t *migrated_pages = &block_context->make_resident.pages_migrated; uvm_page_mask_t *pages_staged = &block_context->make_resident.pages_staged; uvm_page_mask_t *cpu_page_mask; + uvm_page_mask_t *numa_resident_pages; int nid; uvm_page_mask_zero(migrated_pages); @@ -4343,8 +4682,15 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, // destination is the CPU (src_processor_mask empty) and for a staged copy // (src_processor_mask containing processors with copy access to dst_id). uvm_processor_mask_andnot(&src_processor_mask, &block->resident, &src_processor_mask); - uvm_processor_mask_clear(&src_processor_mask, dst_id); - uvm_processor_mask_clear(&src_processor_mask, UVM_ID_CPU); + + // If the destination is the CPU but not all pages are resident on the + // destination NUMA node, the CPU is still a source. + numa_resident_pages = uvm_va_block_resident_mask_get(block, UVM_ID_CPU, block_context->make_resident.dest_nid); + if (!UVM_ID_IS_CPU(dst_id) || uvm_page_mask_subset(copy_page_mask, numa_resident_pages)) { + uvm_processor_mask_clear(&src_processor_mask, dst_id); + uvm_processor_mask_clear(&src_processor_mask, UVM_ID_CPU); + } + if (!uvm_page_mask_empty(cpu_page_mask)) { status = block_copy_resident_pages_mask(block, @@ -4383,7 +4729,7 @@ static NV_STATUS block_copy_resident_pages(uvm_va_block_t *block, for_each_node_mask(nid, block_context->make_resident.cpu_pages_used.nodes) { NvU32 pages_copied_from_node; uvm_page_mask_t *node_pages_mask = &block_context->make_resident.node_pages_mask; - uvm_page_mask_t *node_alloc_mask = block_context->make_resident.cpu_pages_used.node_masks[node_to_index(nid)]; + uvm_page_mask_t *node_alloc_mask = block_tracking_node_mask_get(block_context, nid); if (uvm_page_mask_and(node_pages_mask, pages_staged, node_alloc_mask)) { status = block_copy_resident_pages_between(block, @@ -4451,7 +4797,7 @@ NV_STATUS uvm_va_block_make_resident_copy(uvm_va_block_t *va_block, uvm_assert_mutex_locked(&va_block->lock); UVM_ASSERT(uvm_va_block_is_hmm(va_block) || va_block->va_range->type == UVM_VA_RANGE_TYPE_MANAGED); - resident_mask = block_resident_mask_get_alloc(va_block, dest_id, NUMA_NO_NODE); + resident_mask = block_resident_mask_get_alloc(va_block, dest_id, va_block_context->make_resident.dest_nid); if (!resident_mask) return NV_ERR_NO_MEMORY; @@ -5417,7 +5763,7 @@ static bool block_check_mappings(uvm_va_block_t *block) uvm_processor_id_t id; // Verify the master masks, since block_check_mappings_page relies on them - for_each_processor_id(id) { + for_each_id(id) { const uvm_page_mask_t *resident_mask, *map_mask; if (UVM_ID_IS_GPU(id) && !uvm_va_block_gpu_state_get(block, id)) { @@ -7071,7 +7417,7 @@ static void block_gpu_compute_new_pte_state(uvm_va_block_t *block, for_each_va_block_page_in_region_mask(page_index, pages_changing, big_region_all) { uvm_cpu_chunk_t *chunk = NULL; - int nid; + int nid = NUMA_NO_NODE; if (UVM_ID_IS_CPU(resident_id)) { nid = block_get_page_node_residency(block, page_index); @@ -8018,7 +8364,7 @@ static void map_get_allowed_destinations(uvm_va_block_t *block, else if ((uvm_va_policy_is_read_duplicate(policy, va_space) || (uvm_id_equal(policy->preferred_location, id) && !is_uvm_fault_force_sysmem_set() && - !uvm_hmm_must_use_sysmem(block, va_block_context))) && + !uvm_hmm_must_use_sysmem(block, va_block_context->hmm.vma))) && uvm_va_space_processor_has_memory(va_space, id)) { // When operating under read-duplication we should only map the local // processor to cause fault-and-duplicate of remote pages. @@ -9477,7 +9823,7 @@ static NV_STATUS block_split_cpu_chunk_one(uvm_va_block_t *block, uvm_page_index gpu = block_get_gpu(block, id); // If the parent chunk has not been mapped, there is nothing to split. - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + gpu_mapping_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent); if (gpu_mapping_addr == 0) continue; @@ -9499,7 +9845,7 @@ static NV_STATUS block_split_cpu_chunk_one(uvm_va_block_t *block, uvm_page_index merge: for_each_gpu_id_in_mask(id, &gpu_split_mask) { gpu = block_get_gpu(block, id); - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + gpu_mapping_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent); uvm_pmm_sysmem_mappings_merge_gpu_mappings(&gpu->pmm_reverse_sysmem_mappings, gpu_mapping_addr, chunk_size); @@ -9683,7 +10029,7 @@ static void block_merge_cpu_chunks_one(uvm_va_block_t *block, uvm_page_index_t p continue; gpu = block_get_gpu(block, id); - gpu_mapping_addr = uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent); + gpu_mapping_addr = uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, gpu->parent); if (gpu_mapping_addr == 0) continue; @@ -10135,7 +10481,8 @@ static void block_split_gpu(uvm_va_block_t *existing, uvm_va_block_t *new, uvm_g for_each_possible_uvm_node(nid) { for_each_cpu_chunk_in_block(cpu_chunk, page_index, new, nid) { uvm_pmm_sysmem_mappings_reparent_gpu_mapping(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_phys_addr(cpu_chunk, gpu->parent), + uvm_cpu_chunk_get_parent_gpu_phys_addr(cpu_chunk, + gpu->parent), new); } } @@ -10316,7 +10663,7 @@ NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, // Note that we usually shouldn't nest block locks, but it's ok here because // we just created new_block so no other thread could possibly take it out // of order with existing's lock. - uvm_mutex_lock_no_tracking(&new_block->lock); + uvm_mutex_lock_nested(&new_block->lock); // The split has to be transactional, meaning that if we fail, the existing // block must not be modified. Handle that by pre-allocating everything we @@ -10399,7 +10746,7 @@ NV_STATUS uvm_va_block_split_locked(uvm_va_block_t *existing_va_block, block_free_cpu_chunk_storage(new_block, nid); } - uvm_mutex_unlock_no_tracking(&new_block->lock); + uvm_mutex_unlock_nested(&new_block->lock); return status; } @@ -10935,15 +11282,16 @@ static bool map_remote_on_atomic_fault(uvm_va_space_t *va_space, // TODO: Bug 1766424: this function works on a single page at a time. This // could be changed in the future to optimize multiple faults or access // counter notifications on contiguous pages. -static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, - uvm_va_block_context_t *va_block_context, - uvm_page_index_t page_index, - uvm_processor_id_t processor_id, - NvU32 access_type_mask, - const uvm_va_policy_t *policy, - const uvm_perf_thrashing_hint_t *thrashing_hint, - uvm_service_operation_t operation, - bool *read_duplicate) +static uvm_processor_id_t block_select_processor_residency(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_page_index_t page_index, + uvm_processor_id_t processor_id, + NvU32 access_type_mask, + const uvm_va_policy_t *policy, + const uvm_perf_thrashing_hint_t *thrashing_hint, + uvm_service_operation_t operation, + const bool hmm_migratable, + bool *read_duplicate) { uvm_processor_id_t closest_resident_processor; uvm_va_space_t *va_space = uvm_va_block_get_va_space(va_block); @@ -10952,7 +11300,11 @@ static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, // TODO: Bug 3660968: Remove uvm_hmm_force_sysmem_set() check as soon as // HMM migration is implemented VMAs other than anonymous memory. - if (is_uvm_fault_force_sysmem_set() || uvm_hmm_must_use_sysmem(va_block, va_block_context)) { + // TODO: Bug 4050579: Remove hmm_migratable check when swap cached pages + // can be migrated. + if (is_uvm_fault_force_sysmem_set() || + !hmm_migratable || + uvm_hmm_must_use_sysmem(va_block, va_block_context->hmm.vma)) { *read_duplicate = false; return UVM_ID_CPU; } @@ -11046,12 +11398,72 @@ static uvm_processor_id_t block_select_residency(uvm_va_block_t *va_block, uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(preferred_location)], processor_id)) return preferred_location; + // Check if we should map the closest resident processor remotely on remote CPU fault + // + // When faulting on CPU, there's a linux process on behalf of it, which is associated + // with a unique VM pointed by current->mm. A block of memory residing on GPU is also + // associated with VM, pointed by va_block_context->mm. If they match, it's a regular + // (local) fault, and we may want to migrate a page from GPU to CPU. + // If it's a 'remote' fault, i.e. linux process differs from one associated with block + // VM, we might preserve residence. + // + // Establishing a remote fault without access counters means the memory could stay in + // the wrong spot for a long time, which is why we prefer to avoid creating remote + // mappings. However when NIC accesses a memory residing on GPU, it's worth to keep it + // in place for NIC accesses. + // + // The logic that's used to detect remote faulting also keeps memory in place for + // ptrace accesses. We would prefer to control those policies separately, but the + // NIC case takes priority. + // If the accessing processor is CPU, we're either handling a fault + // from other than owning process, or we're handling an MOMC + // notification. Only prevent migration for the former. + if (UVM_ID_IS_CPU(processor_id) && + operation != UVM_SERVICE_OPERATION_ACCESS_COUNTERS && + uvm_processor_mask_test(&va_space->accessible_from[uvm_id_value(closest_resident_processor)], processor_id) && + va_block_context->mm != current->mm) { + UVM_ASSERT(va_block_context->mm != NULL); + return closest_resident_processor; + } + // If the page is resident on a processor other than the preferred location, // or the faulting processor can't access the preferred location, we select // the faulting processor as the new residency. return processor_id; } +static int block_select_node_residency(uvm_va_block_t *va_block, + uvm_va_block_context_t *va_block_context, + uvm_page_index_t page_index, + uvm_processor_id_t new_residency, + const uvm_va_policy_t *policy, + const uvm_perf_thrashing_hint_t *thrashing_hint) +{ + // For CPU faults, the fault handler runs on the CPU that faulted. + // For GPU faults, the bottom half is pinned to CPUs closest to their GPU. + // Therefore, in both cases, we can use numa_mem_id() to get the NUMA node + // ID of the faulting processor. + int current_nid = numa_mem_id(); + bool may_read_duplicate = can_read_duplicate(va_block, page_index, policy, thrashing_hint); + + // If the new resident processor is not the CPU, return the preferred nid + // since it could be used for CPU allocations of staging pages. + if (!UVM_ID_IS_CPU(new_residency)) + return policy->preferred_nid; + + // If the preferred location is the CPU, the new resident nid is the + // preferred nid. + if (UVM_ID_IS_CPU(policy->preferred_location)) + return policy->preferred_nid; + + // If read duplication is enabled and the page is also resident on the CPU, + // keep its current NUMA node residency. + if (may_read_duplicate && uvm_va_block_cpu_is_page_resident_on(va_block, NUMA_NO_NODE, page_index)) + return block_get_page_node_residency(va_block, page_index); + + return current_nid; +} + uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_page_index_t page_index, @@ -11060,23 +11472,27 @@ uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint, uvm_service_operation_t operation, + const bool hmm_migratable, bool *read_duplicate) { uvm_processor_id_t id; + int nid; UVM_ASSERT(uvm_hmm_check_context_vma_is_valid(va_block, va_block_context->hmm.vma, uvm_va_block_region_for_page(page_index))); - id = block_select_residency(va_block, - va_block_context, - page_index, - processor_id, - access_type_mask, - policy, - thrashing_hint, - operation, - read_duplicate); + // First, select the processor for the new residency. + id = block_select_processor_residency(va_block, + va_block_context, + page_index, + processor_id, + access_type_mask, + policy, + thrashing_hint, + operation, + hmm_migratable, + read_duplicate); // If the intended residency doesn't have memory, fall back to the CPU. if (!block_processor_has_memory(va_block, id)) { @@ -11084,10 +11500,11 @@ uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, id = UVM_ID_CPU; } - // Set the destination NUMA node unconditionally since it could be used - // for CPU allocations (if staging pages are needed) even if the new - // residency is not the CPU. - va_block_context->make_resident.dest_nid = policy->preferred_nid; + // Now, that we know the new residency processor, select the NUMA node ID + // based on the new processor. + nid = block_select_node_residency(va_block, va_block_context, page_index, id, policy, thrashing_hint); + + va_block_context->make_resident.dest_nid = nid; return id; } @@ -11586,7 +12003,11 @@ NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, for_each_id_in_mask(new_residency, &service_context->resident_processors) { if (uvm_va_block_is_hmm(va_block)) { - status = uvm_hmm_va_block_service_locked(processor_id, new_residency, va_block, block_retry, service_context); + status = uvm_hmm_va_block_service_locked(processor_id, + new_residency, + va_block, + block_retry, + service_context); if (status != NV_OK) break; @@ -11609,7 +12030,7 @@ NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id, uvm_page_index_t page_index, - uvm_fault_type_t access_type, + uvm_fault_access_type_t access_type, bool allow_migration) { uvm_va_range_t *va_range = va_block->va_range; @@ -11722,6 +12143,7 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, uvm_processor_id_t new_residency; bool read_duplicate; const uvm_va_policy_t *policy; + const bool hmm_migratable = true; uvm_assert_rwsem_locked(&va_space->lock); @@ -11784,6 +12206,7 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, policy, &thrashing_hint, UVM_SERVICE_OPERATION_REPLAYABLE_FAULTS, + hmm_migratable, &read_duplicate); // Initialize the minimum necessary state in the fault service context @@ -11807,6 +12230,7 @@ static NV_STATUS block_cpu_fault_locked(uvm_va_block_t *va_block, service_context->region = uvm_va_block_region_for_page(page_index); status = uvm_va_block_service_locked(UVM_ID_CPU, va_block, va_block_retry, service_context); + UVM_ASSERT(status != NV_WARN_MISMATCHED_TARGET); ++service_context->num_retries; @@ -11959,7 +12383,7 @@ static NV_STATUS encrypted_memcopy_gpu_to_cpu(uvm_gpu_t *gpu, void *src_cipher, *auth_tag; va_list args; - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); UVM_ASSERT(size <= UVM_CONF_COMPUTING_DMA_BUFFER_SIZE); status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &dma_buffer, NULL); @@ -12020,7 +12444,7 @@ static NV_STATUS encrypted_memcopy_cpu_to_gpu(uvm_gpu_t *gpu, void *dst_cipher, *auth_tag; va_list args; - UVM_ASSERT(uvm_conf_computing_mode_enabled(gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); UVM_ASSERT(size <= UVM_CONF_COMPUTING_DMA_BUFFER_SIZE); status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &dma_buffer, NULL); @@ -12060,7 +12484,7 @@ static NV_STATUS va_block_write_cpu_to_gpu(uvm_va_block_t *va_block, uvm_push_t push; uvm_gpu_address_t src_gpu_address; - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { return encrypted_memcopy_cpu_to_gpu(gpu, dst_gpu_address, uvm_mem_get_cpu_addr_kernel(src_mem), @@ -12164,7 +12588,7 @@ static NV_STATUS va_block_read_gpu_to_cpu(uvm_va_block_t *va_block, uvm_push_t push; uvm_gpu_address_t dst_gpu_address; - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { return encrypted_memcopy_gpu_to_cpu(gpu, uvm_mem_get_cpu_addr_kernel(dst_mem), src_gpu_address, @@ -13004,11 +13428,12 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, gpu = uvm_va_space_get_gpu(va_space, id); - if (!gpu->parent->access_counters_supported) + if (!gpu->parent->access_counters_can_use_physical_addresses) continue; num_pages = uvm_pmm_sysmem_mappings_dma_to_virt(&gpu->pmm_reverse_sysmem_mappings, - uvm_cpu_chunk_get_gpu_phys_addr(chunk, gpu->parent), + uvm_cpu_chunk_get_parent_gpu_phys_addr(chunk, + gpu->parent), uvm_cpu_chunk_get_size(chunk), &sysmem_page, 1); @@ -13052,7 +13477,7 @@ NV_STATUS uvm_test_va_residency_info(UVM_TEST_VA_RESIDENCY_INFO_PARAMS *params, params->mapped_on_count = count; count = 0; - for_each_processor_id(id) { + for_each_id(id) { if (!block_processor_page_is_populated(block, id, page_index)) continue; diff --git a/kernel-open/nvidia-uvm/uvm_va_block.h b/kernel-open/nvidia-uvm/uvm_va_block.h index fdd4a0d2f7..9597f11d2d 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block.h +++ b/kernel-open/nvidia-uvm/uvm_va_block.h @@ -36,7 +36,6 @@ #include "uvm_tracker.h" #include "uvm_pmm_gpu.h" #include "uvm_perf_thrashing.h" -#include "uvm_perf_utils.h" #include "uvm_va_block_types.h" #include "uvm_range_tree.h" #include "uvm_mmu.h" @@ -1035,7 +1034,7 @@ NV_STATUS uvm_va_block_check_logical_permissions(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_processor_id_t processor_id, uvm_page_index_t page_index, - uvm_fault_type_t access_type, + uvm_fault_access_type_t access_type, bool allow_migration); // API for access privilege revocation @@ -1282,6 +1281,10 @@ NV_STATUS uvm_va_block_cpu_fault(uvm_va_block_t *va_block, // and the performance heuristics logic decided to throttle execution. // Any other error code different than NV_OK indicates OOM or a global fatal // error. +// NV_WARN_MISMATCHED_TARGET is a special case of GPU fault handling when a +// GPU is chosen as the destination and the source is a HMM CPU page that can't +// be migrated. In that case, uvm_va_block_select_residency() should be called +// with 'hmm_migratable' set to true so that system memory will be selected. NV_STATUS uvm_va_block_service_locked(uvm_processor_id_t processor_id, uvm_va_block_t *va_block, uvm_va_block_retry_t *block_retry, @@ -2150,6 +2153,14 @@ void uvm_va_block_unmap_cpu_chunk_on_gpus(uvm_va_block_t *va_block, // Locking: The va_block lock must be held. void uvm_va_block_remove_cpu_chunks(uvm_va_block_t *va_block, uvm_va_block_region_t region); +// Get the size of the physical allocation backing the page at page_index on the +// specified processor in the block. Returns 0 if the address is not resident on +// the specified processor. +// Locking: The va_block lock must be held. +NvU32 uvm_va_block_get_physical_size(uvm_va_block_t *block, + uvm_processor_id_t processor, + uvm_page_index_t page_index); + // Get CPU page size or 0 if it is not mapped NvU32 uvm_va_block_page_size_cpu(uvm_va_block_t *va_block, uvm_page_index_t page_index); @@ -2208,12 +2219,14 @@ size_t uvm_va_block_big_page_index(uvm_va_block_t *va_block, uvm_page_index_t pa // Returns the new residency for a page that faulted or triggered access counter // notifications. The read_duplicate output parameter indicates if the page -// meets the requirements to be read-duplicated va_block_context must not be +// meets the requirements to be read-duplicated. va_block_context must not be // NULL, and if the va_block is a HMM block, va_block_context->hmm.vma must be // valid which also means the va_block_context->mm is not NULL, retained, and // locked for at least read. See the comments for // uvm_va_block_check_policy_is_valid() and uvm_hmm_check_context_vma_is_valid() -// in uvm_hmm.h. Locking: the va_block lock must be held. +// in uvm_hmm.h. hmm_migratable should be true if the residency should be forced +// to be system memory. +// Locking: the va_block lock must be held. uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, uvm_va_block_context_t *va_block_context, uvm_page_index_t page_index, @@ -2222,6 +2235,7 @@ uvm_processor_id_t uvm_va_block_select_residency(uvm_va_block_t *va_block, const uvm_va_policy_t *policy, const uvm_perf_thrashing_hint_t *thrashing_hint, uvm_service_operation_t operation, + const bool hmm_migratable, bool *read_duplicate); // Return the maximum mapping protection for processor_id that will not require @@ -2230,6 +2244,13 @@ uvm_prot_t uvm_va_block_page_compute_highest_permission(uvm_va_block_t *va_block uvm_processor_id_t processor_id, uvm_page_index_t page_index); +// Allocates a page for the given page_index in the va_block and maps +// it to the GPU. +// Locking: the va_block lock must be held. +NV_STATUS uvm_va_block_populate_page_cpu(uvm_va_block_t *va_block, + uvm_page_index_t page_index, + uvm_va_block_context_t *block_context); + // A helper macro for handling allocation-retry // // The macro takes a VA block, uvm_va_block_retry_t struct and a function call diff --git a/kernel-open/nvidia-uvm/uvm_va_block_types.h b/kernel-open/nvidia-uvm/uvm_va_block_types.h index 8d68527884..bd1c7e8004 100644 --- a/kernel-open/nvidia-uvm/uvm_va_block_types.h +++ b/kernel-open/nvidia-uvm/uvm_va_block_types.h @@ -272,13 +272,6 @@ typedef struct struct page *pages[PAGES_PER_UVM_VA_BLOCK]; }; - // This flag indicates that at least one page in range being migrated - // or process for a GPU fault (i.e, faulted or prefetched), then - // the whole range will be migrated or remote mapped to system memory. - // TODO: Bug 4050579: Remove this when swap cached pages can be - // migrated. - bool swap_cached; - // Cached VMA pointer. This is only valid while holding the mmap_lock. struct vm_area_struct *vma; diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.c b/kernel-open/nvidia-uvm/uvm_va_policy.c index f125eefe12..5e21f78fc9 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.c +++ b/kernel-open/nvidia-uvm/uvm_va_policy.c @@ -101,6 +101,16 @@ const uvm_va_policy_t *uvm_va_policy_get_region(uvm_va_block_t *va_block, uvm_va } } +bool uvm_va_policy_preferred_location_equal(const uvm_va_policy_t *policy, uvm_processor_id_t proc, int cpu_numa_id) +{ + bool equal = uvm_id_equal(policy->preferred_location, proc); + + if (equal && UVM_ID_IS_CPU(policy->preferred_location)) + equal = uvm_numa_id_eq(policy->preferred_nid, cpu_numa_id); + + return equal; +} + #if UVM_IS_CONFIG_HMM() static struct kmem_cache *g_uvm_va_policy_node_cache __read_mostly; @@ -401,12 +411,14 @@ void uvm_va_policy_clear(uvm_va_block_t *va_block, NvU64 start, NvU64 end) static void uvm_va_policy_node_set(uvm_va_policy_node_t *node, uvm_va_policy_type_t which, uvm_processor_id_t processor_id, + int cpu_numa_nid, uvm_read_duplication_policy_t new_policy) { switch (which) { case UVM_VA_POLICY_PREFERRED_LOCATION: UVM_ASSERT(!UVM_ID_IS_INVALID(processor_id)); node->policy.preferred_location = processor_id; + node->policy.preferred_nid = cpu_numa_nid; break; case UVM_VA_POLICY_ACCESSED_BY: @@ -436,6 +448,7 @@ static void uvm_va_policy_node_clear(uvm_va_block_t *va_block, case UVM_VA_POLICY_PREFERRED_LOCATION: UVM_ASSERT(UVM_ID_IS_INVALID(processor_id)); node->policy.preferred_location = processor_id; + node->policy.preferred_nid = NUMA_NO_NODE; break; case UVM_VA_POLICY_ACCESSED_BY: @@ -464,6 +477,7 @@ static uvm_va_policy_node_t *create_node_and_set(uvm_va_block_t *va_block, NvU64 end, uvm_va_policy_type_t which, uvm_processor_id_t processor_id, + int cpu_numa_nid, uvm_read_duplication_policy_t new_policy) { uvm_va_policy_node_t *node; @@ -473,7 +487,7 @@ static uvm_va_policy_node_t *create_node_and_set(uvm_va_block_t *va_block, if (!node) return node; - uvm_va_policy_node_set(node, which, processor_id, new_policy); + uvm_va_policy_node_set(node, which, processor_id, cpu_numa_nid, new_policy); return node; } @@ -484,6 +498,7 @@ static bool va_policy_node_split_needed(uvm_va_policy_node_t *node, uvm_va_policy_type_t which, bool is_default, uvm_processor_id_t processor_id, + int cpu_numa_nid, uvm_read_duplication_policy_t new_policy) { // If the node doesn't extend beyond the range being set, it doesn't need @@ -494,7 +509,7 @@ static bool va_policy_node_split_needed(uvm_va_policy_node_t *node, // If the new policy value doesn't match the old value, a split is needed. switch (which) { case UVM_VA_POLICY_PREFERRED_LOCATION: - return !uvm_id_equal(node->policy.preferred_location, processor_id); + return !uvm_va_policy_preferred_location_equal(&node->policy, processor_id, cpu_numa_nid); case UVM_VA_POLICY_ACCESSED_BY: if (is_default) @@ -517,6 +532,7 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, uvm_va_policy_type_t which, bool is_default, uvm_processor_id_t processor_id, + int cpu_numa_nid, uvm_read_duplication_policy_t new_policy) { uvm_va_policy_node_t *node, *next, *new; @@ -548,6 +564,7 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, end, which, processor_id, + cpu_numa_nid, new_policy); if (!node) return NV_ERR_NO_MEMORY; @@ -560,7 +577,14 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, node_end = node->node.end; // Nodes should have been split before setting policy so verify that. - UVM_ASSERT(!va_policy_node_split_needed(node, start, end, which, is_default, processor_id, new_policy)); + UVM_ASSERT(!va_policy_node_split_needed(node, + start, + end, + which, + is_default, + processor_id, + cpu_numa_nid, + new_policy)); next = uvm_va_policy_node_iter_next(va_block, node, end); @@ -569,7 +593,7 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, // Note that node may have been deleted. } else { - uvm_va_policy_node_set(node, which, processor_id, new_policy); + uvm_va_policy_node_set(node, which, processor_id, cpu_numa_nid, new_policy); // TODO: Bug 1707562: Add support for merging policy ranges. } @@ -581,6 +605,7 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, node_start - 1, which, processor_id, + cpu_numa_nid, new_policy); if (!new) return NV_ERR_NO_MEMORY; @@ -592,6 +617,7 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, end, which, processor_id, + cpu_numa_nid, new_policy); if (!new) return NV_ERR_NO_MEMORY; @@ -605,6 +631,7 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, const uvm_va_policy_t *uvm_va_policy_set_preferred_location(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_processor_id_t processor_id, + int cpu_node_id, const uvm_va_policy_t *old_policy) { NvU64 start = uvm_va_block_region_start(va_block, region); @@ -633,6 +660,7 @@ const uvm_va_policy_t *uvm_va_policy_set_preferred_location(uvm_va_block_t *va_b } node->policy.preferred_location = processor_id; + node->policy.preferred_nid = cpu_node_id; return &node->policy; } diff --git a/kernel-open/nvidia-uvm/uvm_va_policy.h b/kernel-open/nvidia-uvm/uvm_va_policy.h index 7bb6ebd023..3337efb279 100644 --- a/kernel-open/nvidia-uvm/uvm_va_policy.h +++ b/kernel-open/nvidia-uvm/uvm_va_policy.h @@ -122,6 +122,12 @@ static const uvm_va_policy_node_t *uvm_va_policy_node_from_policy(const uvm_va_p return container_of(policy, uvm_va_policy_node_t, policy); } +// Compare the preferred location and preferred nid from the policy +// with the input processor and CPU node ID. +// For GPUs, only the processors are compared. For the CPU, the +// NUMA node IDs are also compared. +bool uvm_va_policy_preferred_location_equal(const uvm_va_policy_t *policy, uvm_processor_id_t proc, int cpu_node_id); + #if UVM_IS_CONFIG_HMM() // Module load/exit @@ -171,6 +177,7 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, uvm_va_policy_type_t which, bool is_default, uvm_processor_id_t processor_id, + int cpu_node_id, uvm_read_duplication_policy_t new_policy); // This is an optimized version of uvm_va_policy_set_range() where the caller @@ -182,6 +189,7 @@ NV_STATUS uvm_va_policy_set_range(uvm_va_block_t *va_block, const uvm_va_policy_t *uvm_va_policy_set_preferred_location(uvm_va_block_t *va_block, uvm_va_block_region_t region, uvm_processor_id_t processor_id, + int cpu_node_id, const uvm_va_policy_t *old_policy); // Iterators for specific VA policy ranges. diff --git a/kernel-open/nvidia-uvm/uvm_va_range.c b/kernel-open/nvidia-uvm/uvm_va_range.c index adceea8a2b..403e9256fc 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.c +++ b/kernel-open/nvidia-uvm/uvm_va_range.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2015-2022 NVIDIA Corporation + Copyright (c) 2015-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -25,13 +25,13 @@ #include "uvm_linux.h" #include "uvm_types.h" #include "uvm_api.h" +#include "uvm_global.h" #include "uvm_hal.h" #include "uvm_va_range.h" #include "uvm_va_block.h" #include "uvm_kvmalloc.h" #include "uvm_map_external.h" #include "uvm_perf_thrashing.h" -#include "uvm_conf_computing.h" #include "nv_uvm_interface.h" static struct kmem_cache *g_uvm_va_range_cache __read_mostly; @@ -374,7 +374,7 @@ NV_STATUS uvm_va_range_create_semaphore_pool(uvm_va_space_t *va_space, if (status != NV_OK) goto error; - if (i == 0 && g_uvm_global.sev_enabled) + if (i == 0 && g_uvm_global.conf_computing_enabled) mem_alloc_params.dma_owner = gpu; if (attrs.is_cacheable) { @@ -720,7 +720,7 @@ static void va_range_remove_gpu_va_space_semaphore_pool(uvm_va_range_t *va_range { UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_SEMAPHORE_POOL); - if (uvm_conf_computing_mode_enabled(gpu) && (va_range->semaphore_pool.mem->dma_owner == gpu)) + if (g_uvm_global.conf_computing_enabled && (va_range->semaphore_pool.mem->dma_owner == gpu)) uvm_va_range_destroy(va_range, NULL); else uvm_mem_unmap_gpu_user(va_range->semaphore_pool.mem, gpu); @@ -938,7 +938,7 @@ static void va_range_unregister_gpu_managed(uvm_va_range_t *va_range, uvm_gpu_t // Note: ignoring the return code of uvm_va_range_set_preferred_location since this // will only return on error when setting a preferred location, not on a reset if (uvm_id_equal(uvm_va_range_get_policy(va_range)->preferred_location, gpu->id)) - (void)uvm_va_range_set_preferred_location(va_range, UVM_ID_INVALID, mm, NULL); + (void)uvm_va_range_set_preferred_location(va_range, UVM_ID_INVALID, NUMA_NO_NODE, mm, NULL); uvm_va_range_unset_accessed_by(va_range, gpu->id, NULL); @@ -1165,6 +1165,7 @@ NV_STATUS uvm_va_range_split(uvm_va_range_t *existing_va_range, // concurrently on the eviction path will see the new range's data. uvm_va_range_get_policy(new)->read_duplication = uvm_va_range_get_policy(existing_va_range)->read_duplication; uvm_va_range_get_policy(new)->preferred_location = uvm_va_range_get_policy(existing_va_range)->preferred_location; + uvm_va_range_get_policy(new)->preferred_nid = uvm_va_range_get_policy(existing_va_range)->preferred_nid; uvm_processor_mask_copy(&uvm_va_range_get_policy(new)->accessed_by, &uvm_va_range_get_policy(existing_va_range)->accessed_by); uvm_processor_mask_copy(&new->uvm_lite_gpus, &existing_va_range->uvm_lite_gpus); @@ -1429,6 +1430,7 @@ static void range_update_uvm_lite_gpus_mask(uvm_va_range_t *va_range) NV_STATUS uvm_va_range_set_preferred_location(uvm_va_range_t *va_range, uvm_processor_id_t preferred_location, + int preferred_cpu_nid, struct mm_struct *mm, uvm_tracker_t *out_tracker) { @@ -1441,11 +1443,13 @@ NV_STATUS uvm_va_range_set_preferred_location(uvm_va_range_t *va_range, uvm_va_space_t *va_space = va_range->va_space; uvm_va_block_t *va_block; uvm_va_block_context_t *va_block_context; + uvm_va_policy_t *va_range_policy; uvm_assert_rwsem_locked_write(&va_space->lock); UVM_ASSERT(va_range->type == UVM_VA_RANGE_TYPE_MANAGED); - if (uvm_id_equal(uvm_va_range_get_policy(va_range)->preferred_location, preferred_location)) + va_range_policy = uvm_va_range_get_policy(va_range); + if (uvm_va_policy_preferred_location_equal(va_range_policy, preferred_location, preferred_cpu_nid)) return NV_OK; // Mark all range group ranges within this VA range as migrated since the preferred location has changed. @@ -1459,10 +1463,7 @@ NV_STATUS uvm_va_range_set_preferred_location(uvm_va_range_t *va_range, // Calculate the new UVM-Lite GPUs mask, but don't update va_range state so // that we can keep block_page_check_mappings() happy while updating the // mappings. - calc_uvm_lite_gpus_mask(va_space, - preferred_location, - &uvm_va_range_get_policy(va_range)->accessed_by, - &new_uvm_lite_gpus); + calc_uvm_lite_gpus_mask(va_space, preferred_location, &va_range_policy->accessed_by, &new_uvm_lite_gpus); // If the range contains non-migratable range groups, check that new UVM-Lite GPUs // can all map the new preferred location. @@ -1473,10 +1474,7 @@ NV_STATUS uvm_va_range_set_preferred_location(uvm_va_range_t *va_range, } if (UVM_ID_IS_INVALID(preferred_location)) { - uvm_range_group_for_each_migratability_in_safe(&iter, - va_space, - va_range->node.start, - va_range->node.end) { + uvm_range_group_for_each_migratability_in_safe(&iter, va_space, va_range->node.start, va_range->node.end) { if (!iter.migratable) { // Clear the range group assocation for any unmigratable ranges if there is no preferred location status = uvm_range_group_assign_range(va_space, NULL, iter.start, iter.end); @@ -1509,15 +1507,14 @@ NV_STATUS uvm_va_range_set_preferred_location(uvm_va_range_t *va_range, // The old preferred location should establish new remote mappings if it has // accessed-by set. - if (UVM_ID_IS_VALID(uvm_va_range_get_policy(va_range)->preferred_location)) - uvm_processor_mask_set(&set_accessed_by_processors, uvm_va_range_get_policy(va_range)->preferred_location); + if (UVM_ID_IS_VALID(va_range_policy->preferred_location)) + uvm_processor_mask_set(&set_accessed_by_processors, va_range_policy->preferred_location); - uvm_processor_mask_and(&set_accessed_by_processors, - &set_accessed_by_processors, - &uvm_va_range_get_policy(va_range)->accessed_by); + uvm_processor_mask_and(&set_accessed_by_processors, &set_accessed_by_processors, &va_range_policy->accessed_by); // Now update the va_range state - uvm_va_range_get_policy(va_range)->preferred_location = preferred_location; + va_range_policy->preferred_location = preferred_location; + va_range_policy->preferred_nid = preferred_cpu_nid; uvm_processor_mask_copy(&va_range->uvm_lite_gpus, &new_uvm_lite_gpus); va_block_context = uvm_va_space_block_context(va_space, mm); @@ -1805,7 +1802,7 @@ NV_STATUS uvm_api_alloc_semaphore_pool(UVM_ALLOC_SEMAPHORE_POOL_PARAMS *params, if (params->gpuAttributesCount > UVM_MAX_GPUS) return NV_ERR_INVALID_ARGUMENT; - if (g_uvm_global.sev_enabled && params->gpuAttributesCount == 0) + if (g_uvm_global.conf_computing_enabled && params->gpuAttributesCount == 0) return NV_ERR_INVALID_ARGUMENT; // The mm needs to be locked in order to remove stale HMM va_blocks. @@ -1850,6 +1847,7 @@ NV_STATUS uvm_test_va_range_info(UVM_TEST_VA_RANGE_INFO_PARAMS *params, struct f uvm_va_space_t *va_space; uvm_va_range_t *va_range; uvm_processor_id_t processor_id; + uvm_va_policy_t *policy; struct vm_area_struct *vma; NV_STATUS status = NV_OK; struct mm_struct *mm; @@ -1865,6 +1863,7 @@ NV_STATUS uvm_test_va_range_info(UVM_TEST_VA_RANGE_INFO_PARAMS *params, struct f goto out; } + policy = uvm_va_range_get_policy(va_range); params->va_range_start = va_range->node.start; params->va_range_end = va_range->node.end; @@ -1873,17 +1872,19 @@ NV_STATUS uvm_test_va_range_info(UVM_TEST_VA_RANGE_INFO_PARAMS *params, struct f BUILD_BUG_ON((int)UVM_READ_DUPLICATION_ENABLED != (int)UVM_TEST_READ_DUPLICATION_ENABLED); BUILD_BUG_ON((int)UVM_READ_DUPLICATION_DISABLED != (int)UVM_TEST_READ_DUPLICATION_DISABLED); BUILD_BUG_ON((int)UVM_READ_DUPLICATION_MAX != (int)UVM_TEST_READ_DUPLICATION_MAX); - params->read_duplication = uvm_va_range_get_policy(va_range)->read_duplication; + params->read_duplication = policy->read_duplication; - if (UVM_ID_IS_INVALID(uvm_va_range_get_policy(va_range)->preferred_location)) + if (UVM_ID_IS_INVALID(policy->preferred_location)) { memset(¶ms->preferred_location, 0, sizeof(params->preferred_location)); - else - uvm_va_space_processor_uuid(va_space, - ¶ms->preferred_location, - uvm_va_range_get_policy(va_range)->preferred_location); + params->preferred_cpu_nid = NUMA_NO_NODE; + } + else { + uvm_va_space_processor_uuid(va_space, ¶ms->preferred_location, policy->preferred_location); + params->preferred_cpu_nid = policy->preferred_nid; + } params->accessed_by_count = 0; - for_each_id_in_mask(processor_id, &uvm_va_range_get_policy(va_range)->accessed_by) + for_each_id_in_mask(processor_id, &policy->accessed_by) uvm_va_space_processor_uuid(va_space, ¶ms->accessed_by[params->accessed_by_count++], processor_id); // -Wall implies -Wenum-compare, so cast through int to avoid warnings diff --git a/kernel-open/nvidia-uvm/uvm_va_range.h b/kernel-open/nvidia-uvm/uvm_va_range.h index e837924deb..8e9a8ef1a6 100644 --- a/kernel-open/nvidia-uvm/uvm_va_range.h +++ b/kernel-open/nvidia-uvm/uvm_va_range.h @@ -811,6 +811,7 @@ uvm_va_block_t *uvm_va_range_block_next(uvm_va_range_t *va_range, uvm_va_block_t // mode. NV_STATUS uvm_va_range_set_preferred_location(uvm_va_range_t *va_range, uvm_processor_id_t preferred_location, + int preferred_cpu_nid, struct mm_struct *mm, uvm_tracker_t *out_tracker); diff --git a/kernel-open/nvidia-uvm/uvm_va_space.c b/kernel-open/nvidia-uvm/uvm_va_space.c index 4334eaff07..9d43c1fce2 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.c +++ b/kernel-open/nvidia-uvm/uvm_va_space.c @@ -283,7 +283,7 @@ static void unregister_gpu(uvm_va_space_t *va_space, uvm_gpu_t *gpu, struct mm_struct *mm, struct list_head *deferred_free_list, - uvm_global_processor_mask_t *peers_to_release) + uvm_processor_mask_t *peers_to_release) { uvm_gpu_t *peer_gpu; uvm_va_range_t *va_range; @@ -292,7 +292,7 @@ static void unregister_gpu(uvm_va_space_t *va_space, uvm_assert_rwsem_locked_write(&va_space->lock); if (peers_to_release) - uvm_global_processor_mask_zero(peers_to_release); + uvm_processor_mask_zero(peers_to_release); // If a GPU VA Space was explicitly registered, but not explicitly // unregistered, unregister it and add all of its objects to the free list. @@ -320,7 +320,7 @@ static void unregister_gpu(uvm_va_space_t *va_space, // brought up and torn down automatically within add_gpu and // remove_gpu. if (peers_to_release && g_uvm_global.peers[peer_table_index].link_type == UVM_GPU_LINK_PCIE) - uvm_global_processor_mask_set(peers_to_release, peer_gpu->global_id); + uvm_processor_mask_set(peers_to_release, peer_gpu->id); } } @@ -419,8 +419,7 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) uvm_va_range_t *va_range, *va_range_next; uvm_gpu_t *gpu; uvm_gpu_id_t gpu_id; - uvm_global_gpu_id_t global_gpu_id; - uvm_global_processor_mask_t retained_gpus; + uvm_processor_mask_t retained_gpus; LIST_HEAD(deferred_free_list); // Remove the VA space from the global list before we start tearing things @@ -448,7 +447,7 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) // registered GPUs in the VA space, so those faults will be canceled. uvm_va_space_down_write(va_space); - uvm_va_space_global_gpus(va_space, &retained_gpus); + uvm_processor_mask_copy(&retained_gpus, &va_space->registered_gpus); bitmap_copy(va_space->enabled_peers_teardown, va_space->enabled_peers, UVM_MAX_UNIQUE_GPU_PAIRS); @@ -500,7 +499,7 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) nv_kthread_q_flush(&g_uvm_global.global_q); - for_each_global_gpu_in_mask(gpu, &retained_gpus) { + for_each_gpu_in_mask(gpu, &retained_gpus) { if (!gpu->parent->isr.replayable_faults.handling) { UVM_ASSERT(!gpu->parent->isr.non_replayable_faults.handling); continue; @@ -545,16 +544,16 @@ void uvm_va_space_destroy(uvm_va_space_t *va_space) uvm_mutex_lock(&g_uvm_global.global_lock); // Release the GPUs and their peer counts. Do not use - // for_each_global_gpu_in_mask for the outer loop as it reads the GPU + // for_each_gpu_in_mask for the outer loop as it reads the GPU // state, which might get destroyed. - for_each_global_gpu_id_in_mask(global_gpu_id, &retained_gpus) { + for_each_gpu_id_in_mask(gpu_id, &retained_gpus) { uvm_gpu_t *peer_gpu; - gpu = uvm_gpu_get(global_gpu_id); + gpu = uvm_gpu_get(gpu_id); - uvm_global_processor_mask_clear(&retained_gpus, global_gpu_id); + uvm_processor_mask_clear(&retained_gpus, gpu_id); - for_each_global_gpu_in_mask(peer_gpu, &retained_gpus) { + for_each_gpu_in_mask(peer_gpu, &retained_gpus) { NvU32 peer_table_index = uvm_gpu_peer_table_index(gpu->id, peer_gpu->id); if (test_bit(peer_table_index, va_space->enabled_peers_teardown)) { uvm_gpu_peer_t *peer_caps = &g_uvm_global.peers[peer_table_index]; @@ -605,7 +604,7 @@ uvm_gpu_t *uvm_va_space_get_gpu_by_uuid(uvm_va_space_t *va_space, const NvProces uvm_gpu_t *gpu; for_each_va_space_gpu(gpu, va_space) { - if (uvm_processor_uuid_eq(uvm_gpu_uuid(gpu), gpu_uuid)) + if (uvm_uuid_eq(uvm_gpu_uuid(gpu), gpu_uuid)) return gpu; } @@ -641,24 +640,25 @@ uvm_gpu_t *uvm_va_space_retain_gpu_by_uuid(uvm_va_space_t *va_space, const NvPro bool uvm_va_space_can_read_duplicate(uvm_va_space_t *va_space, uvm_gpu_t *changing_gpu) { - uvm_processor_mask_t changing_gpu_mask; - uvm_processor_mask_t non_faultable_gpus; - uvm_processor_mask_t registered_gpu_va_spaces; + NvU32 count = va_space->num_non_faultable_gpu_va_spaces; - uvm_processor_mask_zero(&changing_gpu_mask); - - if (changing_gpu) - uvm_processor_mask_set(&changing_gpu_mask, changing_gpu->id); - - // flip the bit of the changing GPU to represent the state change in progress - uvm_processor_mask_xor(®istered_gpu_va_spaces, &changing_gpu_mask, &va_space->registered_gpu_va_spaces); + if (changing_gpu && !uvm_processor_mask_test(&va_space->faultable_processors, changing_gpu->id)) { + if (uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, changing_gpu->id)) { + // A non-faultable GPU is getting removed. + UVM_ASSERT(count > 0); + --count; + } + else { + // A non-faultable GPU is getting added. + ++count; + } + } - // Can't enable read-duplication if any non-fault-capable GPUs have GPU VA spaces registered - return !uvm_processor_mask_andnot(&non_faultable_gpus, ®istered_gpu_va_spaces, &va_space->faultable_processors); + return count == 0; } -// Note that the "VA space" in the function name refers to a UVM per-process VA space. -// (This is different from a per-GPU VA space.) +// Note that the "VA space" in the function name refers to a UVM per-process +// VA space. (This is different from a per-GPU VA space.) NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, const NvProcessorUuid *gpu_uuid, const uvm_rm_user_object_t *user_rm_device, @@ -711,7 +711,7 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, goto done; } - if (uvm_conf_computing_mode_enabled(gpu)) { + if (g_uvm_global.conf_computing_enabled) { NvU32 gpu_index = uvm_id_gpu_index(gpu->id); status = uvm_conf_computing_dma_buffer_alloc(&gpu->conf_computing.dma_buffer_pool, &va_space->gpu_unregister_dma_buffer[gpu_index], @@ -789,9 +789,7 @@ NV_STATUS uvm_va_space_register_gpu(uvm_va_space_t *va_space, if (status != NV_OK) goto cleanup; - status = uvm_perf_heuristics_register_gpu(va_space, gpu); - if (status != NV_OK) - goto cleanup; + uvm_perf_heuristics_register_gpu(va_space, gpu); uvm_for_each_va_range(va_range, va_space) { status = uvm_va_range_register_gpu(va_range, gpu); @@ -839,8 +837,8 @@ NV_STATUS uvm_va_space_unregister_gpu(uvm_va_space_t *va_space, const NvProcesso uvm_gpu_t *gpu; uvm_gpu_va_space_t *gpu_va_space; struct mm_struct *mm; - uvm_global_gpu_id_t peer_gpu_id; - uvm_global_processor_mask_t peers_to_release; + uvm_gpu_id_t peer_gpu_id; + uvm_processor_mask_t peers_to_release; LIST_HEAD(deferred_free_list); // Stopping channels requires holding the VA space lock in read mode, so do @@ -920,9 +918,9 @@ NV_STATUS uvm_va_space_unregister_gpu(uvm_va_space_t *va_space, const NvProcesso // Release the VA space's GPU and peer counts uvm_mutex_lock(&g_uvm_global.global_lock); - // Do not use for_each_global_gpu_in_mask as it reads the peer GPU state, + // Do not use for_each_gpu_in_mask as it reads the peer GPU state, // which might get destroyed when we release the peer entry. - for_each_global_gpu_id_in_mask(peer_gpu_id, &peers_to_release) { + for_each_gpu_id_in_mask(peer_gpu_id, &peers_to_release) { uvm_gpu_t *peer_gpu = uvm_gpu_get(peer_gpu_id); UVM_ASSERT(uvm_gpu_peer_caps(gpu, peer_gpu)->link_type == UVM_GPU_LINK_PCIE); uvm_gpu_release_pcie_peer_access(gpu, peer_gpu); @@ -1080,7 +1078,7 @@ static NV_STATUS retain_pcie_peers_from_uuids(uvm_va_space_t *va_space, *gpu0 = uvm_va_space_get_gpu_by_uuid(va_space, gpu_uuid_1); *gpu1 = uvm_va_space_get_gpu_by_uuid(va_space, gpu_uuid_2); - if (*gpu0 && *gpu1 && !uvm_id_equal((*gpu0)->id, (*gpu1)->id)) + if (*gpu0 && *gpu1 && !uvm_parent_id_equal((*gpu0)->parent->id, (*gpu1)->parent->id)) status = uvm_gpu_retain_pcie_peer_access(*gpu0, *gpu1); else status = NV_ERR_INVALID_DEVICE; @@ -1336,7 +1334,7 @@ static NV_STATUS create_gpu_va_space(uvm_gpu_t *gpu, gpu_va_space, UVM_PAGE_TREE_TYPE_USER, gpu_address_space_info.bigPageSize, - uvm_gpu_page_tree_init_location(gpu), + uvm_get_page_tree_location(gpu->parent), &gpu_va_space->page_tables); if (status != NV_OK) { UVM_ERR_PRINT("Initializing the page tree failed: %s, GPU %s\n", nvstatusToString(status), uvm_gpu_name(gpu)); @@ -1363,6 +1361,9 @@ static void add_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space) UVM_ASSERT(va_space); uvm_assert_rwsem_locked_write(&va_space->lock); + if (!uvm_processor_mask_test(&va_space->faultable_processors, gpu->id)) + va_space->num_non_faultable_gpu_va_spaces++; + uvm_processor_mask_set(&va_space->registered_gpu_va_spaces, gpu->id); va_space->gpu_va_spaces[uvm_id_gpu_index(gpu->id)] = gpu_va_space; gpu_va_space->state = UVM_GPU_VA_SPACE_STATE_ACTIVE; @@ -1511,6 +1512,49 @@ NV_STATUS uvm_va_space_register_gpu_va_space(uvm_va_space_t *va_space, return status; } +static NvU32 find_gpu_va_space_index(uvm_va_space_t *va_space, + uvm_parent_gpu_t *parent_gpu) +{ + uvm_gpu_id_t gpu_id; + NvU32 index = UVM_ID_MAX_PROCESSORS; + + // TODO: Bug 4351121: this conversion from parent ID to gpu ID depends on + // the fact that only one partition is registered per va_space per physical + // GPU. This code will need to change when multiple MIG instances are + // supported. + for_each_sub_processor_id_in_parent_gpu(gpu_id, parent_gpu->id) { + if (uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, gpu_id)) { + UVM_ASSERT(index == UVM_ID_MAX_PROCESSORS); + index = uvm_id_gpu_index(gpu_id); + } + } + + return index; +} + +uvm_gpu_va_space_t *uvm_gpu_va_space_get_by_parent_gpu(uvm_va_space_t *va_space, + uvm_parent_gpu_t *parent_gpu) +{ + uvm_gpu_va_space_t *gpu_va_space; + NvU32 gpu_index; + + uvm_assert_rwsem_locked(&va_space->lock); + + if (!parent_gpu) + return NULL; + + gpu_index = find_gpu_va_space_index(va_space, parent_gpu); + if (gpu_index == UVM_ID_MAX_PROCESSORS) + return NULL; + + gpu_va_space = va_space->gpu_va_spaces[gpu_index]; + UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); + UVM_ASSERT(gpu_va_space->va_space == va_space); + UVM_ASSERT(gpu_va_space->gpu->parent == parent_gpu); + + return gpu_va_space; +} + // The caller must have stopped all channels under this gpu_va_space before // calling this function. static void remove_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space, @@ -1520,6 +1564,7 @@ static void remove_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space, uvm_va_space_t *va_space; uvm_va_range_t *va_range; uvm_va_range_t *va_range_next; + uvm_gpu_t *gpu; if (!gpu_va_space || uvm_gpu_va_space_state(gpu_va_space) != UVM_GPU_VA_SPACE_STATE_ACTIVE) return; @@ -1550,8 +1595,15 @@ static void remove_gpu_va_space(uvm_gpu_va_space_t *gpu_va_space, // space to be destroyed. atomic_inc(&va_space->gpu_va_space_deferred_free.num_pending); - uvm_processor_mask_clear(&va_space->registered_gpu_va_spaces, gpu_va_space->gpu->id); - va_space->gpu_va_spaces[uvm_id_gpu_index(gpu_va_space->gpu->id)] = NULL; + gpu = gpu_va_space->gpu; + + if (!uvm_processor_mask_test(&va_space->faultable_processors, gpu->id)) { + UVM_ASSERT(va_space->num_non_faultable_gpu_va_spaces); + va_space->num_non_faultable_gpu_va_spaces--; + } + + uvm_processor_mask_clear(&va_space->registered_gpu_va_spaces, gpu->id); + va_space->gpu_va_spaces[uvm_id_gpu_index(gpu->id)] = NULL; gpu_va_space->state = UVM_GPU_VA_SPACE_STATE_DEAD; } @@ -2069,6 +2121,25 @@ NV_STATUS uvm_test_destroy_gpu_va_space_delay(UVM_TEST_DESTROY_GPU_VA_SPACE_DELA return NV_OK; } +NV_STATUS uvm_test_force_cpu_to_cpu_copy_with_ce(UVM_TEST_FORCE_CPU_TO_CPU_COPY_WITH_CE_PARAMS *params, + struct file *filp) + +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + va_space->test.force_cpu_to_cpu_copy_with_ce = params->force_copy_with_ce; + return NV_OK; +} + +NV_STATUS uvm_test_va_space_allow_movable_allocations(UVM_TEST_VA_SPACE_ALLOW_MOVABLE_ALLOCATIONS_PARAMS *params, + struct file *filp) +{ + uvm_va_space_t *va_space = uvm_va_space_get(filp); + + va_space->test.allow_allocation_from_movable = params->allow_movable; + return NV_OK; +} + // List of fault service contexts for CPU faults static LIST_HEAD(g_cpu_service_block_context_list); @@ -2166,7 +2237,7 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, bool major_fault = false; bool is_remote_mm = false; uvm_service_block_context_t *service_context; - uvm_global_processor_mask_t gpus_to_check_for_ecc; + uvm_processor_mask_t *gpus_to_check_for_ecc; if (status != NV_OK) goto convert_error; @@ -2299,20 +2370,17 @@ static vm_fault_t uvm_va_space_cpu_fault(uvm_va_space_t *va_space, } tools_enabled = va_space->tools.enabled; + gpus_to_check_for_ecc = &service_context->cpu_fault.gpus_to_check_for_ecc; - if (status == NV_OK && !is_remote_mm) { - uvm_va_space_global_gpus_in_mask(va_space, - &gpus_to_check_for_ecc, - &service_context->cpu_fault.gpus_to_check_for_ecc); - uvm_global_mask_retain(&gpus_to_check_for_ecc); - } + if (status == NV_OK && !is_remote_mm) + uvm_global_gpu_retain(gpus_to_check_for_ecc); uvm_va_space_up_read(va_space); uvm_record_unlock_mmap_lock_read(vma->vm_mm); if (status == NV_OK && !is_remote_mm) { - status = uvm_global_mask_check_ecc_error(&gpus_to_check_for_ecc); - uvm_global_mask_release(&gpus_to_check_for_ecc); + status = uvm_global_gpu_check_ecc_error(gpus_to_check_for_ecc); + uvm_global_gpu_release(gpus_to_check_for_ecc); } if (tools_enabled) diff --git a/kernel-open/nvidia-uvm/uvm_va_space.h b/kernel-open/nvidia-uvm/uvm_va_space.h index 8099dcd1dc..11a070f026 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space.h +++ b/kernel-open/nvidia-uvm/uvm_va_space.h @@ -159,9 +159,14 @@ struct uvm_va_space_struct // processor mask. uvm_gpu_t *registered_gpus_table[UVM_ID_MAX_GPUS]; - // Mask of processors registered with the va space that support replayable faults + // Mask of processors registered with the va space that support replayable + // faults. uvm_processor_mask_t faultable_processors; + // This is a count of non fault capable processors with a GPU VA space + // registered. + NvU32 num_non_faultable_gpu_va_spaces; + // Semaphore protecting the state of the va space uvm_rw_semaphore_t lock; @@ -342,6 +347,7 @@ struct uvm_va_space_struct struct { bool page_prefetch_enabled; + bool skip_migrate_vma; atomic_t migrate_vma_allocation_fail_nth; @@ -353,6 +359,10 @@ struct uvm_va_space_struct atomic64_t destroy_gpu_va_space_delay_us; atomic64_t split_invalidate_delay_us; + + bool force_cpu_to_cpu_copy_with_ce; + + bool allow_allocation_from_movable; } test; // Queue item for deferred f_ops->release() handling @@ -368,7 +378,7 @@ static uvm_gpu_t *uvm_va_space_get_gpu(uvm_va_space_t *va_space, uvm_gpu_id_t gp gpu = va_space->registered_gpus_table[uvm_id_gpu_index(gpu_id)]; UVM_ASSERT(gpu); - UVM_ASSERT(uvm_gpu_get(gpu->global_id) == gpu); + UVM_ASSERT(uvm_gpu_get(gpu->id) == gpu); return gpu; } @@ -593,22 +603,10 @@ static uvm_gpu_va_space_state_t uvm_gpu_va_space_state(uvm_gpu_va_space_t *gpu_v return gpu_va_space->state; } -static uvm_gpu_va_space_t *uvm_gpu_va_space_get_by_parent_gpu(uvm_va_space_t *va_space, uvm_parent_gpu_t *parent_gpu) -{ - uvm_gpu_va_space_t *gpu_va_space; - - uvm_assert_rwsem_locked(&va_space->lock); - - if (!parent_gpu || !uvm_processor_mask_test(&va_space->registered_gpu_va_spaces, parent_gpu->id)) - return NULL; - - gpu_va_space = va_space->gpu_va_spaces[uvm_id_gpu_index(parent_gpu->id)]; - UVM_ASSERT(uvm_gpu_va_space_state(gpu_va_space) == UVM_GPU_VA_SPACE_STATE_ACTIVE); - UVM_ASSERT(gpu_va_space->va_space == va_space); - UVM_ASSERT(gpu_va_space->gpu->parent == parent_gpu); - - return gpu_va_space; -} +// Return the GPU VA space for the given physical GPU. +// Locking: the va_space lock must be held. +uvm_gpu_va_space_t *uvm_gpu_va_space_get_by_parent_gpu(uvm_va_space_t *va_space, + uvm_parent_gpu_t *parent_gpu); static uvm_gpu_va_space_t *uvm_gpu_va_space_get(uvm_va_space_t *va_space, uvm_gpu_t *gpu) { @@ -712,23 +710,6 @@ static uvm_gpu_t *uvm_processor_mask_find_next_va_space_gpu(const uvm_processor_ #define for_each_va_space_gpu(gpu, va_space) \ for_each_va_space_gpu_in_mask(gpu, va_space, &(va_space)->registered_gpus) -static void uvm_va_space_global_gpus_in_mask(uvm_va_space_t *va_space, - uvm_global_processor_mask_t *global_mask, - const uvm_processor_mask_t *mask) -{ - uvm_gpu_t *gpu; - - uvm_global_processor_mask_zero(global_mask); - - for_each_va_space_gpu_in_mask(gpu, va_space, mask) - uvm_global_processor_mask_set(global_mask, gpu->global_id); -} - -static void uvm_va_space_global_gpus(uvm_va_space_t *va_space, uvm_global_processor_mask_t *global_mask) -{ - uvm_va_space_global_gpus_in_mask(va_space, global_mask, &va_space->registered_gpus); -} - // Return the processor in the candidates mask that is "closest" to src, or // UVM_ID_MAX_PROCESSORS if candidates is empty. The order is: // - src itself @@ -827,6 +808,10 @@ NV_STATUS uvm_test_get_pageable_mem_access_type(UVM_TEST_GET_PAGEABLE_MEM_ACCESS NV_STATUS uvm_test_enable_nvlink_peer_access(UVM_TEST_ENABLE_NVLINK_PEER_ACCESS_PARAMS *params, struct file *filp); NV_STATUS uvm_test_disable_nvlink_peer_access(UVM_TEST_DISABLE_NVLINK_PEER_ACCESS_PARAMS *params, struct file *filp); NV_STATUS uvm_test_destroy_gpu_va_space_delay(UVM_TEST_DESTROY_GPU_VA_SPACE_DELAY_PARAMS *params, struct file *filp); +NV_STATUS uvm_test_force_cpu_to_cpu_copy_with_ce(UVM_TEST_FORCE_CPU_TO_CPU_COPY_WITH_CE_PARAMS *params, + struct file *filp); +NV_STATUS uvm_test_va_space_allow_movable_allocations(UVM_TEST_VA_SPACE_ALLOW_MOVABLE_ALLOCATIONS_PARAMS *params, + struct file *filp); // Handle a CPU fault in the given VA space for a managed allocation, // performing any operations necessary to establish a coherent CPU mapping diff --git a/kernel-open/nvidia-uvm/uvm_va_space_mm.c b/kernel-open/nvidia-uvm/uvm_va_space_mm.c index 9e814577a4..3150c6c8eb 100644 --- a/kernel-open/nvidia-uvm/uvm_va_space_mm.c +++ b/kernel-open/nvidia-uvm/uvm_va_space_mm.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2018-2022 NVIDIA Corporation + Copyright (c) 2018-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -415,7 +415,10 @@ static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space) uvm_va_space_mm_t *va_space_mm = &va_space->va_space_mm; uvm_gpu_va_space_t *gpu_va_space; uvm_gpu_t *gpu; - uvm_global_processor_mask_t gpus_to_flush; + // TODO: Bug 4351121: retained_gpus should be pre-allocated, not on the + // stack. + uvm_processor_mask_t retained_gpus; + uvm_parent_processor_mask_t flushed_parent_gpus; LIST_HEAD(deferred_free_list); uvm_va_space_down_write(va_space); @@ -441,17 +444,20 @@ static void uvm_va_space_mm_shutdown(uvm_va_space_t *va_space) // puts them on the deferred free list, so only one thread will do this. uvm_va_space_down_write(va_space); uvm_va_space_detach_all_user_channels(va_space, &deferred_free_list); - uvm_va_space_global_gpus_in_mask(va_space, &gpus_to_flush, &va_space->faultable_processors); - uvm_global_mask_retain(&gpus_to_flush); + uvm_processor_mask_and(&retained_gpus, &va_space->registered_gpus, &va_space->faultable_processors); + uvm_global_gpu_retain(&retained_gpus); uvm_va_space_up_write(va_space); - // Flush the fault buffer on all GPUs. This will avoid spurious - // cancels of stale pending translated faults after we set - // UVM_VA_SPACE_MM_STATE_RELEASED later. - for_each_global_gpu_in_mask(gpu, &gpus_to_flush) - uvm_gpu_fault_buffer_flush(gpu); + // Flush the fault buffer on all registered faultable GPUs. + // This will avoid spurious cancels of stale pending translated + // faults after we set UVM_VA_SPACE_MM_STATE_RELEASED later. + uvm_parent_processor_mask_zero(&flushed_parent_gpus); + for_each_gpu_in_mask(gpu, &retained_gpus) { + if (!uvm_parent_processor_mask_test_and_set(&flushed_parent_gpus, gpu->parent->id)) + uvm_gpu_fault_buffer_flush(gpu); + } - uvm_global_mask_release(&gpus_to_flush); + uvm_global_gpu_release(&retained_gpus); // Call nvUvmInterfaceUnsetPageDirectory. This has no effect on non-MPS. // Under MPS this guarantees that no new GPU accesses will be made using @@ -513,7 +519,7 @@ static NV_STATUS mm_read64(struct mm_struct *mm, NvU64 addr, NvU64 *val) UVM_ASSERT(IS_ALIGNED(addr, sizeof(*val))); uvm_down_read_mmap_lock(mm); - ret = NV_PIN_USER_PAGES_REMOTE(mm, (unsigned long)addr, 1, 0, &page, NULL, NULL); + ret = NV_PIN_USER_PAGES_REMOTE(mm, (unsigned long)addr, 1, 0, &page, NULL); uvm_up_read_mmap_lock(mm); if (ret < 0) diff --git a/kernel-open/nvidia-uvm/uvm_volta.c b/kernel-open/nvidia-uvm/uvm_volta.c index 058449086e..628bd90f06 100644 --- a/kernel-open/nvidia-uvm/uvm_volta.c +++ b/kernel-open/nvidia-uvm/uvm_volta.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2016-2021 NVIDIA Corporation + Copyright (c) 2016-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -81,6 +81,8 @@ void uvm_hal_volta_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->access_counters_supported = true; + parent_gpu->access_counters_can_use_physical_addresses = true; + parent_gpu->fault_cancel_va_supported = true; parent_gpu->scoped_atomics_supported = true; @@ -98,4 +100,6 @@ void uvm_hal_volta_arch_init_properties(uvm_parent_gpu_t *parent_gpu) parent_gpu->smc.supported = false; parent_gpu->plc_supported = false; + + parent_gpu->no_ats_range_required = false; } diff --git a/kernel-open/nvidia-uvm/uvm_volta_access_counter_buffer.c b/kernel-open/nvidia-uvm/uvm_volta_access_counter_buffer.c index 049a136817..3f518a0b7e 100644 --- a/kernel-open/nvidia-uvm/uvm_volta_access_counter_buffer.c +++ b/kernel-open/nvidia-uvm/uvm_volta_access_counter_buffer.c @@ -116,6 +116,8 @@ static uvm_gpu_address_t get_address(uvm_parent_gpu_t *parent_gpu, NvU32 *access } else { uvm_aperture_t aperture = get_access_counter_aperture(access_counter_entry); + + UVM_ASSERT(parent_gpu->access_counters_can_use_physical_addresses); UVM_ASSERT_MSG(addr_type_value == NVC365_NOTIFY_BUF_ENTRY_ADDR_TYPE_GPA, "Invalid address type%u\n", addr_type_value); diff --git a/kernel-open/nvidia-uvm/uvm_volta_ce.c b/kernel-open/nvidia-uvm/uvm_volta_ce.c index d8b7e09545..5b4e70b178 100644 --- a/kernel-open/nvidia-uvm/uvm_volta_ce.c +++ b/kernel-open/nvidia-uvm/uvm_volta_ce.c @@ -113,7 +113,7 @@ void uvm_hal_volta_ce_memcopy(uvm_push_t *push, uvm_gpu_address_t dst, uvm_gpu_a NvU32 launch_dma_src_dst_type; NvU32 launch_dma_plc_mode; NvU32 flush_value = HWCONST(C3B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE); - NvU32 copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(push, dst, src); + NvU32 copy_type_value = gpu->parent->ce_hal->memcopy_copy_type(dst, src); UVM_ASSERT_MSG(gpu->parent->ce_hal->memcopy_is_valid(push, dst, src), "Memcopy validation failed in channel %s, GPU %s.\n", diff --git a/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c b/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c index d128f83592..a6786e3a70 100644 --- a/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c +++ b/kernel-open/nvidia-uvm/uvm_volta_fault_buffer.c @@ -76,7 +76,7 @@ void uvm_hal_volta_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 in // the HW replayable fault buffer, because UVM does not write to the actual // GET register; GSP-RM is responsible for clearing the bits in the real // GET register. - if (!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) + if (g_uvm_global.conf_computing_enabled) return; // Clear the GETPTR_CORRUPTED and OVERFLOW bits. @@ -253,7 +253,7 @@ static UvmFaultMetadataPacket *get_fault_buffer_entry_metadata(uvm_parent_gpu_t UvmFaultMetadataPacket *fault_entry_metadata; UVM_ASSERT(index < parent_gpu->fault_buffer_info.replayable.max_faults); - UVM_ASSERT(!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)); + UVM_ASSERT(g_uvm_global.conf_computing_enabled); fault_entry_metadata = parent_gpu->fault_buffer_info.rm_info.replayable.bufferMetadata; UVM_ASSERT(fault_entry_metadata != NULL); @@ -354,7 +354,7 @@ NV_STATUS uvm_hal_volta_fault_buffer_parse_replayable_entry(uvm_parent_gpu_t *pa // When Confidential Computing is enabled, faults are encrypted by RM, so // they need to be decrypted before they can be parsed - if (!uvm_parent_gpu_replayable_fault_buffer_is_uvm_owned(parent_gpu)) { + if (g_uvm_global.conf_computing_enabled) { NV_STATUS status; UvmFaultMetadataPacket *fault_entry_metadata = get_fault_buffer_entry_metadata(parent_gpu, index); diff --git a/kernel-open/nvidia-uvm/uvm_volta_mmu.c b/kernel-open/nvidia-uvm/uvm_volta_mmu.c index e064360021..76da47ab4b 100644 --- a/kernel-open/nvidia-uvm/uvm_volta_mmu.c +++ b/kernel-open/nvidia-uvm/uvm_volta_mmu.c @@ -1,5 +1,5 @@ /******************************************************************************* - Copyright (c) 2017-2021 NVIDIA Corporation + Copyright (c) 2017-2023 NVIDIA Corporation Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to @@ -145,13 +145,20 @@ static NvU64 small_half_pde_volta(uvm_mmu_page_table_alloc_t *phys_alloc) return pde_bits; } -static void make_pde_volta(void *entry, uvm_mmu_page_table_alloc_t **phys_allocs, NvU32 depth) +static void make_pde_volta(void *entry, + uvm_mmu_page_table_alloc_t **phys_allocs, + uvm_page_directory_t *dir, + NvU32 child_index) { - NvU32 entry_count = entries_per_index_volta(depth); + NvU32 entry_count; NvU64 *entry_bits = (NvU64 *)entry; + UVM_ASSERT(dir); + + entry_count = entries_per_index_volta(dir->depth); + if (entry_count == 1) { - *entry_bits = single_pde_volta(*phys_allocs, depth); + *entry_bits = single_pde_volta(*phys_allocs, dir->depth); } else if (entry_count == 2) { entry_bits[MMU_BIG] = big_half_pde_volta(phys_allocs[MMU_BIG]); diff --git a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_cert.h b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_cert.h index 0f0b5bca08..8bc485fa39 100644 --- a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_cert.h +++ b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_cert.h @@ -7,6 +7,8 @@ #ifndef CRYPTLIB_CERT_H #define CRYPTLIB_CERT_H +#if LIBSPDM_CERT_PARSE_SUPPORT + /** * Retrieve the tag and length of the tag. * @@ -199,7 +201,7 @@ extern bool libspdm_x509_get_key_usage(const uint8_t *cert, size_t cert_size, si * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. * @param[out] usage Key usage bytes. - * @param[in, out] usage_size Key usage buffer sizs in bytes. + * @param[in, out] usage_size Key usage buffer size in bytes. * * @retval true * @retval false @@ -214,7 +216,7 @@ extern bool libspdm_x509_get_extended_key_usage(const uint8_t *cert, * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. * @param[out] basic_constraints Basic constraints bytes. - * @param[in, out] basic_constraints_size Basic constraints buffer sizs in bytes. + * @param[in, out] basic_constraints_size Basic constraints buffer size in bytes. * * @retval true * @retval false @@ -250,16 +252,16 @@ extern bool libspdm_x509_verify_cert(const uint8_t *cert, size_t cert_size, * * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates * where the first certificate is signed by the Root - * Certificate or is the Root Cerificate itself. and - * subsequent cerificate is signed by the preceding - * cerificate. + * Certificate or is the Root Certificate itself. and + * subsequent certificate is signed by the preceding + * certificate. * @param[in] cert_chain_length Total length of the certificate chain, in bytes. * * @param[in] root_cert Trusted Root Certificate buffer. * * @param[in] root_cert_length Trusted Root Certificate buffer length. * - * @retval true All cerificates were issued by the first certificate in X509Certchain. + * @retval true All certificates were issued by the first certificate in X509Certchain. * @retval false Invalid certificate or the certificate was not issued by the given * trusted CA. **/ @@ -272,12 +274,12 @@ extern bool libspdm_x509_verify_cert_chain(const uint8_t *root_cert, size_t root * * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates * where the first certificate is signed by the Root - * Certificate or is the Root Cerificate itself. and - * subsequent cerificate is signed by the preceding - * cerificate. + * Certificate or is the Root Certificate itself. and + * subsequent certificate is signed by the preceding + * certificate. * @param[in] cert_chain_length Total length of the certificate chain, in bytes. * - * @param[in] cert_index Index of certificate. If index is -1 indecate the + * @param[in] cert_index Index of certificate. If index is -1 indicates the * last certificate in cert_chain. * * @param[out] cert The certificate at the index of cert_chain. @@ -301,7 +303,7 @@ extern bool libspdm_x509_get_cert_from_cert_chain(const uint8_t *cert_chain, * * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. - * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * @param[out] rsa_context Pointer to newly generated RSA context which contain the retrieved * RSA public key component. Use libspdm_rsa_free() function to free the * resource. * @@ -319,7 +321,7 @@ extern bool libspdm_rsa_get_public_key_from_x509(const uint8_t *cert, size_t cer * * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. - * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * @param[out] ec_context Pointer to newly generated EC DSA context which contain the retrieved * EC public key component. Use libspdm_ec_free() function to free the * resource. * @@ -340,7 +342,7 @@ extern bool libspdm_ec_get_public_key_from_x509(const uint8_t *cert, size_t cert * * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. - * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * @param[out] ecd_context Pointer to newly generated Ed DSA context which contain the retrieved * Ed public key component. Use libspdm_ecd_free() function to free the * resource. * @@ -361,7 +363,7 @@ extern bool libspdm_ecd_get_public_key_from_x509(const uint8_t *cert, size_t cer * * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. - * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * @param[out] sm2_context Pointer to newly generated sm2 context which contain the retrieved * sm2 public key component. Use sm2_free() function to free the * resource. * @@ -376,41 +378,6 @@ extern bool libspdm_sm2_get_public_key_from_x509(const uint8_t *cert, size_t cer void **sm2_context); #endif /* LIBSPDM_SM2_DSA_SUPPORT */ -#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP -/** - * Generate a CSR. - * - * @param[in] hash_nid hash algo for sign - * @param[in] asym_nid asym algo for sign - * - * @param[in] requester_info requester info to gen CSR - * @param[in] requester_info_length The len of requester info - * - * @param[in] context Pointer to asymmetric context - * @param[in] subject_name Subject name: should be break with ',' in the middle - * example: "C=AA,CN=BB" - * - * Subject names should contain a comma-separated list of OID types and values: - * The valid OID type name is in: - * {"CN", "commonName", "C", "countryName", "O", "organizationName","L", - * "OU", "organizationalUnitName", "ST", "stateOrProvinceName", "emailAddress", - * "serialNumber", "postalAddress", "postalCode", "dnQualifier", "title", - * "SN","givenName","GN", "initials", "pseudonym", "generationQualifier", "domainComponent", "DC"}. - * Note: The object of C and countryName should be CSR Supported Country Codes - * - * @param[in] csr_len For input, csr_len is the size of store CSR buffer. - * For output, csr_len is CSR len for DER format - * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. - * For output, csr_pointer is address for stored CSR. - * The csr_pointer address will be changed. - * - * @retval true Success. - * @retval false Failed to gen CSR. - **/ -extern bool libspdm_gen_x509_csr(size_t hash_nid, size_t asym_nid, - uint8_t *requester_info, size_t requester_info_length, - void *context, char *subject_name, - size_t *csr_len, uint8_t **csr_pointer); -#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ +#endif /* LIBSPDM_CERT_PARSE_SUPPORT */ #endif /* CRYPTLIB_CERT_H */ diff --git a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ec.h b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ec.h index 1b42da7037..75389a06bc 100644 --- a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ec.h +++ b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ec.h @@ -28,6 +28,44 @@ extern void *libspdm_ec_new_by_nid(size_t nid); * @param[in] ec_context Pointer to the EC context to be released. **/ extern void libspdm_ec_free(void *ec_context); + +#if LIBSPDM_FIPS_MODE +/** + * Sets the private key component into the established EC context. + * + * For P-256, the private_key_size is 32 byte. + * For P-384, the private_key_size is 48 byte. + * For P-521, the private_key_size is 66 byte. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] private_key Pointer to the private key buffer. + * @param[in] private_key_size The size of private key buffer in bytes. + * + * @retval true EC private key component was set successfully. + * @retval false Invalid EC private key component. + * + **/ +extern bool libspdm_ec_set_priv_key(void *ec_context, const uint8_t *private_key, + size_t private_key_size); + +/** + * Sets the public key component into the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] public Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true EC public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size); +#endif /* LIBSPDM_FIPS_MODE */ + #endif /* (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) */ #if LIBSPDM_ECDHE_SUPPORT @@ -99,6 +137,29 @@ extern bool libspdm_ec_compute_key(void *ec_context, const uint8_t *peer_public, #endif /* LIBSPDM_ECDHE_SUPPORT */ #if LIBSPDM_ECDSA_SUPPORT +/** + * Generates Elliptic Curve context from DER-encoded public key data. + * + * The public key is ASN.1 DER-encoded as RFC7250 describes, + * namely, the SubjectPublicKeyInfo structure of a X.509 certificate. + * + * @param[in] der_data Pointer to the DER-encoded public key data. + * @param[in] der_size Size of the DER-encoded public key data in bytes. + * @param[out] ec_context Pointer to newly generated EC context which contains the + * EC public key component. + * Use libspdm_ec_free() function to free the resource. + * + * If der_data is NULL, then return false. + * If ec_context is NULL, then return false. + * + * @retval true EC context was generated successfully. + * @retval false Invalid DER public key data. + * + **/ +extern bool libspdm_ec_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **ec_context); + /** * Carries out the EC-DSA signature. * @@ -132,6 +193,29 @@ extern bool libspdm_ecdsa_sign(void *ec_context, size_t hash_nid, const uint8_t *message_hash, size_t hash_size, uint8_t *signature, size_t *sig_size); +#if LIBSPDM_FIPS_MODE +/** + * Carries out the EC-DSA signature with caller input random function. This API can be used for FIPS test. + * + * @param[in] ec_context Pointer to EC context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive EC-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * @param[in] random_func random number function + * + * @retval true signature successfully generated in EC-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_ecdsa_sign_ex(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size, + int (*random_func)(void *, unsigned char *, size_t)); +#endif/*LIBSPDM_FIPS_MODE*/ + /** * Verifies the EC-DSA signature. * diff --git a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ecd.h b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ecd.h index 10cbbfb2ce..74e3bca319 100644 --- a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ecd.h +++ b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_ecd.h @@ -22,6 +22,29 @@ **/ extern void *libspdm_ecd_new_by_nid(size_t nid); +/** + * Generates Edwards-Curve context from DER-encoded public key data. + * + * The public key is ASN.1 DER-encoded as RFC7250 describes, + * namely, the SubjectPublicKeyInfo structure of a X.509 certificate. + * + * @param[in] der_data Pointer to the DER-encoded public key data. + * @param[in] der_size Size of the DER-encoded public key data in bytes. + * @param[out] ec_context Pointer to newly generated Ed context which contains the + * Ed public key component. + * Use libspdm_ecd_free() function to free the resource. + * + * If der_data is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true Ed context was generated successfully. + * @retval false Invalid DER public key data. + * + **/ +extern bool libspdm_ecd_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **ecd_context); + /** * Release the specified Ed context. * @@ -29,6 +52,56 @@ extern void *libspdm_ecd_new_by_nid(size_t nid); **/ extern void libspdm_ecd_free(void *ecd_context); +/** + * Sets the public key component into the established Ed context. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[in] public_key Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true Ed public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ecd_set_pub_key(void *ecd_context, const uint8_t *public_key, + size_t public_key_size); + +/** + * Sets the private key component into the established Ed context. + * + * For ed25519, the private_size is 32. + * For ed448, the private_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[in] private Pointer to the buffer to receive generated private X,Y. + * @param[in] private_size The size of private buffer in bytes. + * + * @retval true Ed private key component was set successfully. + * @retval false Invalid EC private key component. + * + **/ +bool libspdm_ecd_set_pri_key(void *ecd_context, const uint8_t *private_key, + size_t private_key_size); + +/** + * Gets the public key component from the established Ed context. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true Ed key component was retrieved successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ecd_get_pub_key(void *ecd_context, uint8_t *public_key, + size_t *public_key_size); + /** * Carries out the Ed-DSA signature. * diff --git a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h index 6135575b3b..b7e68a3649 100644 --- a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h +++ b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h @@ -35,6 +35,28 @@ typedef enum { **/ extern void *libspdm_rsa_new(void); +/** + * Generates RSA context from DER-encoded public key data. + * + * The public key is ASN.1 DER-encoded as RFC7250 describes, + * namely, the SubjectPublicKeyInfo structure of a X.509 certificate. + * + * @param[in] der_data Pointer to the DER-encoded public key data. + * @param[in] der_size Size of the DER-encoded public key data in bytes. + * @param[out] rsa_context Pointer to newly generated RSA context which contains the + * RSA public key component. + * Use libspdm_rsa_free() function to free the resource. + * + * If der_data is NULL, then return false. + * If rsa_context is NULL, then return false. + * + * @retval true RSA context was generated successfully. + * @retval false Invalid DER public key data. + **/ +extern bool libspdm_rsa_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **rsa_context); + /** * Release the specified RSA context. * @@ -67,80 +89,6 @@ extern void libspdm_rsa_free(void *rsa_context); extern bool libspdm_rsa_set_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, const uint8_t *big_number, size_t bn_size); -/** - * Gets the tag-designated RSA key component from the established RSA context. - * - * This function retrieves the tag-designated RSA key component from the - * established RSA context as a non-negative integer (octet string format - * represented in RSA PKCS#1). - * If specified key component has not been set or has been cleared, then returned - * bn_size is set to 0. - * If the big_number buffer is too small to hold the contents of the key, false - * is returned and bn_size is set to the required buffer size to obtain the key. - * - * If rsa_context is NULL, then return false. - * If bn_size is NULL, then return false. - * If bn_size is large enough but big_number is NULL, then return false. - * If this interface is not supported, then return false. - * - * @param[in, out] rsa_context Pointer to RSA context being set. - * @param[in] key_tag Tag of RSA key component being set. - * @param[out] big_number Pointer to octet integer buffer. - * @param[in, out] bn_size On input, the size of big number buffer in bytes. - * On output, the size of data returned in big number buffer in bytes. - * - * @retval true RSA key component was retrieved successfully. - * @retval false Invalid RSA key component tag. - * @retval false bn_size is too small. - * @retval false This interface is not supported. - **/ -extern bool libspdm_rsa_get_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, - uint8_t *big_number, size_t *bn_size); - -/** - * Generates RSA key components. - * - * This function generates RSA key components. It takes RSA public exponent E and - * length in bits of RSA modulus N as input, and generates all key components. - * If public_exponent is NULL, the default RSA public exponent (0x10001) will be used. - * - * If rsa_context is NULL, then return false. - * If this interface is not supported, then return false. - * - * @param[in, out] rsa_context Pointer to RSA context being set. - * @param[in] modulus_length Length of RSA modulus N in bits. - * @param[in] public_exponent Pointer to RSA public exponent. - * @param[in] public_exponent_size Size of RSA public exponent buffer in bytes. - * - * @retval true RSA key component was generated successfully. - * @retval false Invalid RSA key component tag. - * @retval false This interface is not supported. - **/ -extern bool libspdm_rsa_generate_key(void *rsa_context, size_t modulus_length, - const uint8_t *public_exponent, - size_t public_exponent_size); - -/** - * Validates key components of RSA context. - * NOTE: This function performs integrity checks on all the RSA key material, so - * the RSA key structure must contain all the private key data. - * - * This function validates key components of RSA context in following aspects: - * - Whether p is a prime - * - Whether q is a prime - * - Whether n = p * q - * - Whether d*e = 1 mod lcm(p-1,q-1) - * - * If rsa_context is NULL, then return false. - * If this interface is not supported, then return false. - * - * @param[in] rsa_context Pointer to RSA context to check. - * - * @retval true RSA key components are valid. - * @retval false RSA key components are not valid. - * @retval false This interface is not supported. - **/ -extern bool libspdm_rsa_check_key(void *rsa_context); #endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ #if LIBSPDM_RSA_SSA_SUPPORT @@ -260,5 +208,67 @@ extern bool libspdm_rsa_pss_sign(void *rsa_context, size_t hash_nid, extern bool libspdm_rsa_pss_verify(void *rsa_context, size_t hash_nid, const uint8_t *message_hash, size_t hash_size, const uint8_t *signature, size_t sig_size); + +#if LIBSPDM_FIPS_MODE +/** + * Carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme for FIPS test. + * + * This function carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme defined in + * RSA PKCS#1 v2.2 for FIPS test. + * + * The salt length is zero. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * @param[in] rsa_context Pointer to RSA context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive RSA-SSA PSS signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in RSA-SSA PSS. + * @retval false signature generation failed. + * @retval false sig_size is too small. + * + **/ +extern bool libspdm_rsa_pss_sign_fips(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the RSA-SSA signature with EMSA-PSS encoding scheme defined in + * RSA PKCS#1 v2.2 for FIPS test. + * + * The salt length is zero. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, SHA3_512. + * + * @param[in] rsa_context Pointer to RSA context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size size of the message hash in bytes. + * @param[in] signature Pointer to RSA-SSA PSS signature to be verified. + * @param[in] sig_size size of signature in bytes. + * + * @retval true Valid signature encoded in RSA-SSA PSS. + * @retval false Invalid signature or invalid RSA context. + * + **/ +extern bool libspdm_rsa_pss_verify_fips(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif /*LIBSPDM_FIPS_MODE*/ + #endif /* LIBSPDM_RSA_PSS_SUPPORT */ #endif /* CRYPTLIB_RSA_H */ diff --git a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_sm2.h b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_sm2.h index 2b382b9394..b733331892 100644 --- a/kernel-open/nvidia/hal/library/cryptlib/cryptlib_sm2.h +++ b/kernel-open/nvidia/hal/library/cryptlib/cryptlib_sm2.h @@ -22,6 +22,29 @@ **/ extern void *libspdm_sm2_dsa_new_by_nid(size_t nid); +/** + * Generates Shang-Mi2 context from DER-encoded public key data. + * + * The public key is ASN.1 DER-encoded as RFC7250 describes, + * namely, the SubjectPublicKeyInfo structure of a X.509 certificate. + * + * @param[in] der_data Pointer to the DER-encoded public key data. + * @param[in] der_size Size of the DER-encoded public key data in bytes. + * @param[out] sm2_context Pointer to newly generated SM2 context which contains the + * SM2 public key component. + * Use libspdm_sm2_free() function to free the resource. + * + * If der_data is NULL, then return false. + * If sm2_context is NULL, then return false. + * + * @retval true SM2 context was generated successfully. + * @retval false Invalid DER public key data. + * + **/ +extern bool libspdm_sm2_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **sm2_context); + /** * Release the specified sm2 context. * diff --git a/kernel-open/nvidia/internal/libspdm_lib_config.h b/kernel-open/nvidia/internal/libspdm_lib_config.h index 47d98bc737..a64be5eafd 100644 --- a/kernel-open/nvidia/internal/libspdm_lib_config.h +++ b/kernel-open/nvidia/internal/libspdm_lib_config.h @@ -13,39 +13,6 @@ #include LIBSPDM_CONFIG #endif -#if defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) && \ - !defined(LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP) -#ifdef _MSC_VER -#pragma message("LIBSPDM_ENABLE_SET_CERTIFICATE_CAP is deprecated. Use " \ - "LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP instead. This warning will be removed in a " \ - "future release.") -#else -#warning LIBSPDM_ENABLE_SET_CERTIFICATE_CAP is deprecated. Use \ - LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP instead. This warning will be removed in a \ - future release. -#endif /* _MSC_VER */ -#endif /* defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) */ - -#if defined(LIBSPDM_ENABLE_CHUNK_CAP) && !defined(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) -#ifdef _MSC_VER -#pragma message("LIBSPDM_ENABLE_CHUNK_CAP is deprecated. Use LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP " \ - "instead. This warning will be removed in a future release.") -#else -#warning LIBSPDM_ENABLE_CHUNK_CAP is deprecated. Use LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP \ - instead. This warning will be removed in a future release. -#endif /* _MSC_VER */ -#endif /* defined(LIBSPDM_ENABLE_CHUNK_CAP) */ - -#if defined(MDEPKG_NDEBUG) && !defined(LIBSPDM_DEBUG_ENABLE) -#ifdef _MSC_VER -#pragma message("MDEPKG_NDEBUG is deprecated. Use LIBSPDM_DEBUG_ENABLE " \ - "instead. This warning will be removed in a future release.") -#else -#warning MDEPKG_NDEBUG is deprecated. Use LIBSPDM_DEBUG_ENABLE \ - instead. This warning will be removed in a future release. -#endif /* _MSC_VER */ -#endif /* defined(MDEPKG_NDEBUG) */ - #if defined(LIBSPDM_DEBUG_ENABLE) #undef LIBSPDM_DEBUG_ASSERT_ENABLE #undef LIBSPDM_DEBUG_PRINT_ENABLE @@ -64,6 +31,67 @@ #define LIBSPDM_DEBUG_BLOCK_ENABLE 0 #endif /* defined(LIBSPDM_DEBUG_ENABLE) */ +/*when in FIPS mode, only support approved algo in FIPS */ +#if LIBSPDM_FIPS_MODE +#undef LIBSPDM_SM2_DSA_P256_SUPPORT +#define LIBSPDM_SM2_DSA_P256_SUPPORT 0 + +#undef LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT +#define LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT 0 + +#undef LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT +#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 0 + +#undef LIBSPDM_AEAD_SM4_128_GCM_SUPPORT +#define LIBSPDM_AEAD_SM4_128_GCM_SUPPORT 0 + +#undef LIBSPDM_SM3_256_SUPPORT +#define LIBSPDM_SM3_256_SUPPORT 0 +#endif /*LIBSPDM_FIPS_MODE*/ + +/* define crypto algorithm without parameter */ +#define LIBSPDM_RSA_SSA_SUPPORT ((LIBSPDM_RSA_SSA_2048_SUPPORT) || \ + (LIBSPDM_RSA_SSA_3072_SUPPORT) || \ + (LIBSPDM_RSA_SSA_4096_SUPPORT)) + +#define LIBSPDM_RSA_PSS_SUPPORT ((LIBSPDM_RSA_PSS_2048_SUPPORT) || \ + (LIBSPDM_RSA_PSS_3072_SUPPORT) || \ + (LIBSPDM_RSA_PSS_4096_SUPPORT)) + +#define LIBSPDM_ECDSA_SUPPORT ((LIBSPDM_ECDSA_P256_SUPPORT) || \ + (LIBSPDM_ECDSA_P384_SUPPORT) || \ + (LIBSPDM_ECDSA_P521_SUPPORT)) + +#define LIBSPDM_SM2_DSA_SUPPORT (LIBSPDM_SM2_DSA_P256_SUPPORT) + +#define LIBSPDM_EDDSA_SUPPORT ((LIBSPDM_EDDSA_ED25519_SUPPORT) || \ + (LIBSPDM_EDDSA_ED448_SUPPORT)) + +#define LIBSPDM_FFDHE_SUPPORT ((LIBSPDM_FFDHE_2048_SUPPORT) || \ + (LIBSPDM_FFDHE_3072_SUPPORT) || \ + (LIBSPDM_FFDHE_4096_SUPPORT)) + +#define LIBSPDM_ECDHE_SUPPORT ((LIBSPDM_ECDHE_P256_SUPPORT) || \ + (LIBSPDM_ECDHE_P384_SUPPORT) || \ + (LIBSPDM_ECDHE_P521_SUPPORT)) + +#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT (LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT) + +#define LIBSPDM_AEAD_GCM_SUPPORT ((LIBSPDM_AEAD_AES_128_GCM_SUPPORT) || \ + (LIBSPDM_AEAD_AES_256_GCM_SUPPORT)) + +#define LIBSPDM_AEAD_SM4_SUPPORT (LIBSPDM_AEAD_SM4_128_GCM_SUPPORT) + +#define LIBSPDM_SHA2_SUPPORT ((LIBSPDM_SHA256_SUPPORT) || \ + (LIBSPDM_SHA384_SUPPORT) || \ + (LIBSPDM_SHA512_SUPPORT)) + +#define LIBSPDM_SHA3_SUPPORT ((LIBSPDM_SHA3_256_SUPPORT) || \ + (LIBSPDM_SHA3_384_SUPPORT) || \ + (LIBSPDM_SHA3_512_SUPPORT)) + +#define LIBSPDM_SM3_SUPPORT (LIBSPDM_SM3_256_SUPPORT) + #if LIBSPDM_CHECK_MACRO #include "internal/libspdm_macro_check.h" #endif /* LIBSPDM_CHECK_MACRO */ diff --git a/kernel-open/nvidia/library/spdm_lib_config.h b/kernel-open/nvidia/library/spdm_lib_config.h index cfff674c5b..6203b51f13 100644 --- a/kernel-open/nvidia/library/spdm_lib_config.h +++ b/kernel-open/nvidia/library/spdm_lib_config.h @@ -7,6 +7,11 @@ #ifndef SPDM_LIB_CONFIG_H #define SPDM_LIB_CONFIG_H +/* Enables FIPS 140-3 mode. */ +#ifndef LIBSPDM_FIPS_MODE +#define LIBSPDM_FIPS_MODE 0 +#endif + /* Enables assertions and debug printing. When `LIBSPDM_DEBUG_ENABLE` is defined it overrides or * sets the values of `LIBSPDM_DEBUG_PRINT_ENABLE`, `LIBSPDM_DEBUG_ASSERT_ENABLE`, and * `LIBSPDM_BLOCK_ENABLE` to the value of `LIBSPDM_DEBUG_ENABLE`. @@ -21,7 +26,7 @@ /* The SPDM specification allows a Responder to return up to 256 version entries in the `VERSION` * response to the Requester, including duplicate entries. For a Requester this value specifies the * maximum number of entries that libspdm will tolerate in a `VERSION` response before returning an - * error. A similiar macro, `SPDM_MAX_VERSION_COUNT`, exists for the Responder. However this macro + * error. A similar macro, `SPDM_MAX_VERSION_COUNT`, exists for the Responder. However this macro * is not meant to be configured by the Integrator. */ #ifndef LIBSPDM_MAX_VERSION_COUNT @@ -71,38 +76,6 @@ #define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN 1024 #endif -#ifndef LIBSPDM_MAX_MESSAGE_BUFFER_SIZE -#define LIBSPDM_MAX_MESSAGE_BUFFER_SIZE 0x1200 -#endif -#ifndef LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE -#define LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE 0x100 /* to hold message_a before negotiate*/ -#endif -#ifndef LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE -#define LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE 0x300 /* to hold message_k before finished_key is ready*/ -#endif - -/* If the Responder replies with a Busy `ERROR` response to a request then the Requester is free to - * retry sending the request. This value specifies the maximum number of times libspdm will retry - * sending the request before returning an error. If its value is 0 then libspdm will not send any - * retry requests. - */ -#ifndef LIBSPDM_MAX_REQUEST_RETRY_TIMES -#define LIBSPDM_MAX_REQUEST_RETRY_TIMES 3 -#endif -#ifndef LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM -#define LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM 4 -#endif -#ifndef LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM -#define LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM 4 -#endif -#ifndef LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM -#define LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM 4 -#endif - -#ifndef LIBSPDM_MAX_CSR_SIZE -#define LIBSPDM_MAX_CSR_SIZE 0x1000 -#endif - /* To ensure integrity in communication between the Requester and the Responder libspdm calculates * cryptographic digests and signatures over multiple requests and responses. This value specifies * whether libspdm will use a running calculation over the transcript, where requests and responses @@ -113,23 +86,44 @@ #define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 #endif - /* Cryptography Configuration * In each category, at least one should be selected. * NOTE: Not all combination can be supported. E.g. Don't mix NIST algo with SMx.*/ -#ifndef LIBSPDM_RSA_SSA_SUPPORT -#define LIBSPDM_RSA_SSA_SUPPORT 1 +#ifndef LIBSPDM_RSA_SSA_2048_SUPPORT +#define LIBSPDM_RSA_SSA_2048_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_SSA_3072_SUPPORT +#define LIBSPDM_RSA_SSA_3072_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_SSA_4096_SUPPORT +#define LIBSPDM_RSA_SSA_4096_SUPPORT 1 +#endif + +#ifndef LIBSPDM_RSA_PSS_2048_SUPPORT +#define LIBSPDM_RSA_PSS_2048_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_PSS_3072_SUPPORT +#define LIBSPDM_RSA_PSS_3072_SUPPORT 1 #endif -#ifndef LIBSPDM_RSA_PSS_SUPPORT -#define LIBSPDM_RSA_PSS_SUPPORT 1 +#ifndef LIBSPDM_RSA_PSS_4096_SUPPORT +#define LIBSPDM_RSA_PSS_4096_SUPPORT 1 +#endif + +#ifndef LIBSPDM_ECDSA_P256_SUPPORT +#define LIBSPDM_ECDSA_P256_SUPPORT 1 #endif -#ifndef LIBSPDM_ECDSA_SUPPORT -#define LIBSPDM_ECDSA_SUPPORT 1 +#ifndef LIBSPDM_ECDSA_P384_SUPPORT +#define LIBSPDM_ECDSA_P384_SUPPORT 1 #endif -#ifndef LIBSPDM_SM2_DSA_SUPPORT -#define LIBSPDM_SM2_DSA_SUPPORT 1 +#ifndef LIBSPDM_ECDSA_P521_SUPPORT +#define LIBSPDM_ECDSA_P521_SUPPORT 1 #endif + +#ifndef LIBSPDM_SM2_DSA_P256_SUPPORT +#define LIBSPDM_SM2_DSA_P256_SUPPORT 1 +#endif + #ifndef LIBSPDM_EDDSA_ED25519_SUPPORT #define LIBSPDM_EDDSA_ED25519_SUPPORT 1 #endif @@ -137,24 +131,43 @@ #define LIBSPDM_EDDSA_ED448_SUPPORT 1 #endif -#ifndef LIBSPDM_FFDHE_SUPPORT -#define LIBSPDM_FFDHE_SUPPORT 1 +#ifndef LIBSPDM_FFDHE_2048_SUPPORT +#define LIBSPDM_FFDHE_2048_SUPPORT 1 #endif -#ifndef LIBSPDM_ECDHE_SUPPORT -#define LIBSPDM_ECDHE_SUPPORT 1 +#ifndef LIBSPDM_FFDHE_3072_SUPPORT +#define LIBSPDM_FFDHE_3072_SUPPORT 1 #endif -#ifndef LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT -#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT 1 +#ifndef LIBSPDM_FFDHE_4096_SUPPORT +#define LIBSPDM_FFDHE_4096_SUPPORT 1 #endif -#ifndef LIBSPDM_AEAD_GCM_SUPPORT -#define LIBSPDM_AEAD_GCM_SUPPORT 1 +#ifndef LIBSPDM_ECDHE_P256_SUPPORT +#define LIBSPDM_ECDHE_P256_SUPPORT 1 +#endif +#ifndef LIBSPDM_ECDHE_P384_SUPPORT +#define LIBSPDM_ECDHE_P384_SUPPORT 1 #endif +#ifndef LIBSPDM_ECDHE_P521_SUPPORT +#define LIBSPDM_ECDHE_P521_SUPPORT 1 +#endif + +#ifndef LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT +#define LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT 1 +#endif + +#ifndef LIBSPDM_AEAD_AES_128_GCM_SUPPORT +#define LIBSPDM_AEAD_AES_128_GCM_SUPPORT 1 +#endif +#ifndef LIBSPDM_AEAD_AES_256_GCM_SUPPORT +#define LIBSPDM_AEAD_AES_256_GCM_SUPPORT 1 +#endif + #ifndef LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT #define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 1 #endif -#ifndef LIBSPDM_AEAD_SM4_SUPPORT -#define LIBSPDM_AEAD_SM4_SUPPORT 1 + +#ifndef LIBSPDM_AEAD_SM4_128_GCM_SUPPORT +#define LIBSPDM_AEAD_SM4_128_GCM_SUPPORT 1 #endif #ifndef LIBSPDM_SHA256_SUPPORT @@ -166,6 +179,7 @@ #ifndef LIBSPDM_SHA512_SUPPORT #define LIBSPDM_SHA512_SUPPORT 1 #endif + #ifndef LIBSPDM_SHA3_256_SUPPORT #define LIBSPDM_SHA3_256_SUPPORT 1 #endif @@ -175,10 +189,16 @@ #ifndef LIBSPDM_SHA3_512_SUPPORT #define LIBSPDM_SHA3_512_SUPPORT 1 #endif + #ifndef LIBSPDM_SM3_256_SUPPORT #define LIBSPDM_SM3_256_SUPPORT 1 #endif +/* This can be set to 0 for the device which does not need X509 parser.*/ +#ifndef LIBSPDM_CERT_PARSE_SUPPORT +#define LIBSPDM_CERT_PARSE_SUPPORT 1 +#endif + /* Code space optimization for Optional request/response messages.*/ /* Consumers of libspdm may wish to not fully implement all of the optional @@ -192,17 +212,17 @@ /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP - Enable/Disable single CERT capability. * LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP - Enable/Disable single CHAL capability. - * LIBSPDM_ENABLE_CAPABILTIY_MEAS_CAP - Enable/Disables multiple MEAS capabilities: + * LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP - Enable/Disables multiple MEAS capabilities: * (MEAS_CAP_NO_SIG, MEAS_CAP_SIG, MEAS_FRESH_CAP)*/ /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP - Enable/Disable single Key Exchange capability. - * LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP - Enable/Disable PSK_EX and PSK_FINISH.*/ + * LIBSPDM_ENABLE_CAPABILITY_PSK_CAP - Enable/Disable PSK_EX and PSK_FINISH.*/ /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP - Enable/Disable mutual authentication. * LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP - Enable/Disable encapsulated message.*/ -/* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP - Enable/Disable get csr capability. - * LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP - Enable/Disable set certificate capability. */ +/* LIBSPDM_ENABLE_CAPABILITY_CSR_CAP - Enable/Disable get csr capability. + * LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP - Enable/Disable set certificate capability. */ #ifndef LIBSPDM_ENABLE_CAPABILITY_CERT_CAP #define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 @@ -220,8 +240,8 @@ #define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 #endif -#ifndef LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP -#define LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP 1 +#ifndef LIBSPDM_ENABLE_CAPABILITY_PSK_CAP +#define LIBSPDM_ENABLE_CAPABILITY_PSK_CAP 1 #endif #ifndef LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP @@ -236,18 +256,51 @@ #define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 1 #endif -#ifndef LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP -#define LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP 1 +#ifndef LIBSPDM_ENABLE_CAPABILITY_CSR_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CSR_CAP 1 #endif -#ifndef LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP -#define LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP 1 +#ifndef LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP +#define LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP 1 #endif #ifndef LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP #define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 1 #endif +/* If 1 then endpoint supports sending GET_CERTIFICATE and GET_DIGESTS requests. + * If enabled and endpoint is a Responder then LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP + * must also be enabled. + */ +#ifndef LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT +#define LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT 1 +#endif + +/* If 1 then endpoint supports sending CHALLENGE request. + * If enabled and endpoint is a Responder then LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP + * must also be enabled. + */ +#ifndef LIBSPDM_SEND_CHALLENGE_SUPPORT +#define LIBSPDM_SEND_CHALLENGE_SUPPORT 1 +#endif + +/* When LIBSPDM_RESPOND_IF_READY_SUPPORT is 0 then + * - For a Requester, if the Responder sends a ResponseNotReady ERROR response then the error + * is immediately returned to the Integrator. The Requester cannot send a RESPOND_IF_READY + * request. + * - For a Responder, it cannot send a RESPOND_IF_READY ERROR response and does not support + * RESPOND_IF_READY. + * When LIBSPDM_RESPOND_IF_READY_SUPPORT is 1 then + * - For a Requester, if the Responder sends a ResponseNotReady ERROR response then libspdm + * waits an amount of time, as specified by the RDTExponent parameter, before sending + * RESPOND_IF_READY. + * - For a Responder, if its response state is NOT_READY then it will send a ResponseNotReady + * ERROR response to the Requester, and will accept a subsequent RESPOND_IF_READY request. + */ +#ifndef LIBSPDM_RESPOND_IF_READY_SUPPORT +#define LIBSPDM_RESPOND_IF_READY_SUPPORT 1 +#endif + /* * MinDataTransferSize = 42 * @@ -290,7 +343,7 @@ * | CHALLENGE 1.2 | 40 | 1 | * | CHALLENGE_AUTH 1.2 | 38 + H * 2 + S [+ O] = [166, 678] | [6, 23] | * +--------------------------+------------------------------------------+---------+ - * | GET_MEASUREMENTS 1.2 | 5 + Nounce (0 or 32) | 1 | + * | GET_MEASUREMENTS 1.2 | 5 + Nonce (0 or 32) | 1 | * | MEASUREMENTS 1.2 | 42 + MeasRecLen (+ S) [+ O] = [106, 554] | [4, 19] | * +--------------------------+------------------------------------------+---------+ * | KEY_EXCHANGE 1.2 | 42 + D [+ O] = [106, 554] | [4, 19] | @@ -313,93 +366,6 @@ * +==========================+==========================================+=========+ */ -/* Maximum size of a large SPDM message. - * If chunk is unsupported, it must be same as LIBSPDM_DATA_TRANSFER_SIZE. - * If chunk is supported, it must be larger than LIBSPDM_DATA_TRANSFER_SIZE. - * It matches MaxSPDMmsgSize in SPDM specification. */ -#ifndef LIBSPDM_MAX_SPDM_MSG_SIZE -#define LIBSPDM_MAX_SPDM_MSG_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE -#endif - -/* Maximum size of a single SPDM message. - * It matches DataTransferSize in SPDM specification. */ -#ifndef LIBSPDM_DATA_TRANSFER_SIZE -#define LIBSPDM_DATA_TRANSFER_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE -#endif - -/* Required sender/receive buffer in device io. - * NOTE: This is transport specific. Below configuration is just an example. - * +-------+--------+---------------------------+------+--+------+---+--------+-----+ - * | TYPE |TransHdr| EncryptionHeader |AppHdr| |Random|MAC|AlignPad|FINAL| - * | | |SessionId|SeqNum|Len|AppLen| | | | | | | - * +-------+--------+---------------------------+------+ +------+---+--------+-----+ - * | MCTP | 1 | 4 | 2 | 2 | 2 | 1 | | 32 | 12| 0 | 56 | - * |PCI_DOE| 8 | 4 | 0 | 2 | 2 | 0 | | 0 | 12| 3 | 31 | - * +-------+--------+---------------------------+------+--+------+---+--------+-----+ - */ -#ifndef LIBSPDM_TRANSPORT_ADDITIONAL_SIZE -#define LIBSPDM_TRANSPORT_ADDITIONAL_SIZE 64 -#endif -#ifndef LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE -#define LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE (LIBSPDM_DATA_TRANSFER_SIZE + \ - LIBSPDM_TRANSPORT_ADDITIONAL_SIZE) -#endif - - -/* Required scratch buffer size for libspdm internal usage. - * It may be used to hold the encrypted/decrypted message and/or last sent/received message. - * It may be used to hold the large request/response and intermediate send/receive buffer - * in case of chunking. - * - * If chunking is not supported, it may be just LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE. - * If chunking is supported, it should be at least below. - * - * +---------------+--------------+--------------------------+------------------------------+ - * |SECURE_MESSAGE |LARGE_MESSAGE | SENDER_RECEIVER | LARGE_SENDER_RECEIVER | - * +---------------+--------------+--------------------------+------------------------------+ - * |<-Secure msg ->|<-Large msg ->|<-Snd/Rcv buf for chunk ->|<-Snd/Rcv buf for large msg ->| - * - * The value is NOT configurable. - * The value MAY be changed in different libspdm version. - * It is exposed here, just in case the libspdm consumer wants to configure the setting at build time. - */ -#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP - -/* first section */ -#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_OFFSET 0 - -#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) - -/* second section */ -#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY) - -#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) - -/* third section */ -#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET \ - (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY) - -#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) - -/* fourth section */ -#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET \ - (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY) - -#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) - -#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY \ - ) - -#else -#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE) -#endif - /* Enable message logging. * See https://github.com/DMTF/libspdm/blob/main/doc/user_guide.md#message-logging * for more information */ @@ -412,4 +378,9 @@ #define LIBSPDM_CHECK_MACRO 0 #endif +/* Enable checks to the SPDM context during runtime. */ +#ifndef LIBSPDM_CHECK_SPDM_CONTEXT +#define LIBSPDM_CHECK_SPDM_CONTEXT 1 +#endif + #endif /* SPDM_LIB_CONFIG_H */ diff --git a/kernel-open/nvidia/libspdm_shash.c b/kernel-open/nvidia/libspdm_shash.c index 10e9bff1a4..5a96501006 100644 --- a/kernel-open/nvidia/libspdm_shash.c +++ b/kernel-open/nvidia/libspdm_shash.c @@ -23,10 +23,16 @@ #include "internal_crypt_lib.h" +#ifdef USE_LKCA +#ifndef NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT +#include +#endif +#endif + void *lkca_hash_new(const char* alg_name) { #ifndef USE_LKCA - return false; + return NULL; #else //XXX: can we reuse crypto_shash part and just allocate desc struct crypto_shash *alg; @@ -87,9 +93,24 @@ bool lkca_hmac_duplicate(struct shash_desc *dst, struct shash_desc const *src) struct crypto_shash *src_tfm = src->tfm; struct crypto_shash *dst_tfm = dst->tfm; + int ss = crypto_shash_statesize(dst_tfm); + +#ifdef NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT char *src_ipad = crypto_tfm_ctx_aligned(&src_tfm->base); char *dst_ipad = crypto_tfm_ctx_aligned(&dst_tfm->base); - int ss = crypto_shash_statesize(dst_tfm); +#else + int ctx_size = crypto_shash_alg(dst_tfm)->base.cra_ctxsize; + char *src_ipad = crypto_shash_ctx(src_tfm); + char *dst_ipad = crypto_shash_ctx(dst_tfm); + /* + * Actual struct definition is hidden, so I assume data we need is at + * the end. In 6.0 the struct has a pointer to crpyto_shash followed by: + * 'u8 ipad[statesize];', then 'u8 opad[statesize];' + */ + src_ipad += ctx_size - 2 * ss; + dst_ipad += ctx_size - 2 * ss; +#endif + memcpy(dst_ipad, src_ipad, crypto_shash_blocksize(src->tfm)); memcpy(dst_ipad + ss, src_ipad + ss, crypto_shash_blocksize(src->tfm)); crypto_shash_clear_flags(dst->tfm, CRYPTO_TFM_NEED_KEY); diff --git a/kernel-open/nvidia/nv-caps.c b/kernel-open/nvidia/nv-caps.c index 50e04b0519..6d20610077 100644 --- a/kernel-open/nvidia/nv-caps.c +++ b/kernel-open/nvidia/nv-caps.c @@ -64,6 +64,7 @@ static nv_cap_table_entry_t g_nv_cap_mig_table[] = static nv_cap_table_entry_t g_nv_cap_sys_table[] = { + {"/driver/nvidia/capabilities/fabric-imex-mgmt"} }; #define NV_CAP_MIG_CI_ENTRIES(_gi) \ diff --git a/kernel-open/nvidia/nv-dma.c b/kernel-open/nvidia/nv-dma.c index f6d1a5a94d..1c2c609b3a 100644 --- a/kernel-open/nvidia/nv-dma.c +++ b/kernel-open/nvidia/nv-dma.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -447,7 +447,7 @@ NV_STATUS NV_API_CALL nv_dma_map_sgt( return NV_ERR_NOT_SUPPORTED; } - if (page_count > os_get_num_phys_pages()) + if (page_count > NV_NUM_PHYSPAGES) { NV_DMA_DEV_PRINTF(NV_DBG_ERRORS, dma_dev, "DMA mapping request too large!\n"); @@ -509,7 +509,7 @@ NV_STATUS NV_API_CALL nv_dma_unmap_sgt( return NV_OK; } -NV_STATUS NV_API_CALL nv_dma_map_pages( +static NV_STATUS NV_API_CALL nv_dma_map_pages( nv_dma_device_t *dma_dev, NvU64 page_count, NvU64 *va_array, @@ -530,7 +530,7 @@ NV_STATUS NV_API_CALL nv_dma_map_pages( return NV_ERR_NOT_SUPPORTED; } - if (page_count > os_get_num_phys_pages()) + if (page_count > NV_NUM_PHYSPAGES) { NV_DMA_DEV_PRINTF(NV_DBG_ERRORS, dma_dev, "DMA mapping request too large!\n"); @@ -582,7 +582,7 @@ NV_STATUS NV_API_CALL nv_dma_map_pages( return status; } -NV_STATUS NV_API_CALL nv_dma_unmap_pages( +static NV_STATUS NV_API_CALL nv_dma_unmap_pages( nv_dma_device_t *dma_dev, NvU64 page_count, NvU64 *va_array, @@ -602,7 +602,7 @@ NV_STATUS NV_API_CALL nv_dma_unmap_pages( dma_map = *priv; - if (page_count > os_get_num_phys_pages()) + if (page_count > NV_NUM_PHYSPAGES) { NV_DMA_DEV_PRINTF(NV_DBG_ERRORS, dma_dev, "DMA unmapping request too large!\n"); @@ -1100,7 +1100,6 @@ NV_STATUS NV_API_CALL nv_dma_import_dma_buf nv_dma_device_t *dma_dev, struct dma_buf *dma_buf, NvU32 *size, - void **user_pages, struct sg_table **sgt, nv_dma_buf_t **import_priv ) @@ -1113,7 +1112,6 @@ NV_STATUS NV_API_CALL nv_dma_import_from_fd nv_dma_device_t *dma_dev, NvS32 fd, NvU32 *size, - void **user_pages, struct sg_table **sgt, nv_dma_buf_t **import_priv ) @@ -1123,7 +1121,6 @@ NV_STATUS NV_API_CALL nv_dma_import_from_fd void NV_API_CALL nv_dma_release_dma_buf ( - void *user_pages, nv_dma_buf_t *import_priv ) { diff --git a/kernel-open/nvidia/nv-ibmnpu.c b/kernel-open/nvidia/nv-ibmnpu.c index 1926acf247..a541c0718f 100644 --- a/kernel-open/nvidia/nv-ibmnpu.c +++ b/kernel-open/nvidia/nv-ibmnpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -376,7 +376,7 @@ void NV_API_CALL nv_ibmnpu_cache_flush_range(nv_state_t *nv, NvU64 cpu_virtual, cbsize = nvl->npu->numa_info.l1d_cache_block_size; - CACHE_FLUSH(); + asm volatile("sync; isync" ::: "memory"); /* Force eviction of any cache lines from the NUMA-onlined region. */ for (offset = 0; offset < size; offset += cbsize) @@ -387,7 +387,7 @@ void NV_API_CALL nv_ibmnpu_cache_flush_range(nv_state_t *nv, NvU64 cpu_virtual, cond_resched(); } - CACHE_FLUSH(); + asm volatile("sync; isync" ::: "memory"); } #else diff --git a/kernel-open/nvidia/nv-mmap.c b/kernel-open/nvidia/nv-mmap.c index e7dcb16a4b..7c85cab192 100644 --- a/kernel-open/nvidia/nv-mmap.c +++ b/kernel-open/nvidia/nv-mmap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -705,9 +705,9 @@ int nvidia_mmap( struct vm_area_struct *vma ) { - nv_linux_state_t *nvl = NV_GET_NVL_FROM_FILEP(file); - nv_state_t *nv = NV_STATE_PTR(nvl); nv_linux_file_private_t *nvlfp = NV_GET_LINUX_FILE_PRIVATE(file); + nv_linux_state_t *nvl; + nv_state_t *nv; nvidia_stack_t *sp = NULL; int status; @@ -720,6 +720,19 @@ int nvidia_mmap( return -EINVAL; } + if (!nv_is_control_device(NV_FILE_INODE(file))) + { + status = nv_wait_open_complete_interruptible(nvlfp); + if (status != 0) + return status; + } + + nvl = nvlfp->nvptr; + if (nvl == NULL) + return -EIO; + + nv = NV_STATE_PTR(nvl); + status = nv_kmem_cache_alloc_stack(&sp); if (status != 0) { diff --git a/kernel-open/nvidia/nv-p2p.c b/kernel-open/nvidia/nv-p2p.c index c17f02f9ca..a1fc9c686e 100644 --- a/kernel-open/nvidia/nv-p2p.c +++ b/kernel-open/nvidia/nv-p2p.c @@ -171,7 +171,6 @@ static void nv_p2p_free_dma_mapping( nv_dma_device_t peer_dma_dev = {{ 0 }}; NvU32 page_size; NV_STATUS status; - NvU32 i; peer_dma_dev.dev = &dma_mapping->pci_dev->dev; peer_dma_dev.addressable_range.limit = dma_mapping->pci_dev->dma_mask; @@ -180,16 +179,64 @@ static void nv_p2p_free_dma_mapping( if (dma_mapping->private != NULL) { - WARN_ON(page_size != PAGE_SIZE); + /* + * If OS page size is smaller than P2P page size, + * page inflation logic applies for DMA unmapping too. + * Bigger P2P page needs to be split in smaller OS pages. + */ + if (page_size > PAGE_SIZE) + { + NvU64 *os_dma_addresses = NULL; + NvU32 os_pages_per_p2p_page = page_size; + NvU32 os_page_count; + NvU32 index, i, j; - status = nv_dma_unmap_alloc(&peer_dma_dev, - dma_mapping->entries, - dma_mapping->dma_addresses, - &dma_mapping->private); - WARN_ON(status != NV_OK); + do_div(os_pages_per_p2p_page, PAGE_SIZE); + + os_page_count = os_pages_per_p2p_page * dma_mapping->entries; + + status = os_alloc_mem((void **)&os_dma_addresses, + (os_page_count * sizeof(NvU64))); + if(WARN_ON(status != NV_OK)) + { + goto failed; + } + + index = 0; + for (i = 0; i < dma_mapping->entries; i++) + { + os_dma_addresses[index] = dma_mapping->dma_addresses[i]; + index++; + + for (j = 1; j < os_pages_per_p2p_page; j++) + { + os_dma_addresses[index] = os_dma_addresses[index - 1] + PAGE_SIZE; + index++; + } + } + + status = nv_dma_unmap_alloc(&peer_dma_dev, + os_page_count, + os_dma_addresses, + &dma_mapping->private); + WARN_ON(status != NV_OK); + + os_free_mem(os_dma_addresses); + } + else + { + WARN_ON(page_size != PAGE_SIZE); + + status = nv_dma_unmap_alloc(&peer_dma_dev, + dma_mapping->entries, + dma_mapping->dma_addresses, + &dma_mapping->private); + WARN_ON(status != NV_OK); + } } else { + NvU32 i; for (i = 0; i < dma_mapping->entries; i++) { nv_dma_unmap_peer(&peer_dma_dev, page_size / PAGE_SIZE, @@ -197,6 +244,7 @@ static void nv_p2p_free_dma_mapping( } } +failed: os_free_mem(dma_mapping->dma_addresses); os_free_mem(dma_mapping); @@ -316,14 +364,14 @@ int nvidia_p2p_init_mapping( return -ENOTSUPP; } -EXPORT_SYMBOL(nvidia_p2p_init_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_init_mapping); int nvidia_p2p_destroy_mapping(uint64_t p2p_token) { return -ENOTSUPP; } -EXPORT_SYMBOL(nvidia_p2p_destroy_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_destroy_mapping); static void nv_p2p_mem_info_free_callback(void *data) { @@ -587,7 +635,7 @@ int nvidia_p2p_get_pages( p2p_token, va_space, virtual_address, length, page_table, free_callback, data); } -EXPORT_SYMBOL(nvidia_p2p_get_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_get_pages); int nvidia_p2p_get_pages_persistent( uint64_t virtual_address, @@ -605,7 +653,7 @@ int nvidia_p2p_get_pages_persistent( virtual_address, length, page_table, NULL, NULL); } -EXPORT_SYMBOL(nvidia_p2p_get_pages_persistent); +NV_EXPORT_SYMBOL(nvidia_p2p_get_pages_persistent); /* * This function is a no-op, but is left in place (for now), in order to allow @@ -618,7 +666,7 @@ int nvidia_p2p_free_page_table(struct nvidia_p2p_page_table *page_table) return 0; } -EXPORT_SYMBOL(nvidia_p2p_free_page_table); +NV_EXPORT_SYMBOL(nvidia_p2p_free_page_table); int nvidia_p2p_put_pages( uint64_t p2p_token, @@ -649,7 +697,7 @@ int nvidia_p2p_put_pages( return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_put_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_put_pages); int nvidia_p2p_put_pages_persistent( uint64_t virtual_address, @@ -689,7 +737,7 @@ int nvidia_p2p_put_pages_persistent( return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_put_pages_persistent); +NV_EXPORT_SYMBOL(nvidia_p2p_put_pages_persistent); int nvidia_p2p_dma_map_pages( struct pci_dev *peer, @@ -804,7 +852,7 @@ int nvidia_p2p_dma_map_pages( return nvidia_p2p_map_status(status); } -EXPORT_SYMBOL(nvidia_p2p_dma_map_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_dma_map_pages); int nvidia_p2p_dma_unmap_pages( struct pci_dev *peer, @@ -844,7 +892,7 @@ int nvidia_p2p_dma_unmap_pages( return 0; } -EXPORT_SYMBOL(nvidia_p2p_dma_unmap_pages); +NV_EXPORT_SYMBOL(nvidia_p2p_dma_unmap_pages); /* * This function is a no-op, but is left in place (for now), in order to allow @@ -859,7 +907,7 @@ int nvidia_p2p_free_dma_mapping( return 0; } -EXPORT_SYMBOL(nvidia_p2p_free_dma_mapping); +NV_EXPORT_SYMBOL(nvidia_p2p_free_dma_mapping); int nvidia_p2p_register_rsync_driver( nvidia_p2p_rsync_driver_t *driver, @@ -888,7 +936,7 @@ int nvidia_p2p_register_rsync_driver( driver->wait_for_rsync, data); } -EXPORT_SYMBOL(nvidia_p2p_register_rsync_driver); +NV_EXPORT_SYMBOL(nvidia_p2p_register_rsync_driver); void nvidia_p2p_unregister_rsync_driver( nvidia_p2p_rsync_driver_t *driver, @@ -920,7 +968,7 @@ void nvidia_p2p_unregister_rsync_driver( driver->wait_for_rsync, data); } -EXPORT_SYMBOL(nvidia_p2p_unregister_rsync_driver); +NV_EXPORT_SYMBOL(nvidia_p2p_unregister_rsync_driver); int nvidia_p2p_get_rsync_registers( nvidia_p2p_rsync_reg_info_t **reg_info @@ -1013,7 +1061,7 @@ int nvidia_p2p_get_rsync_registers( return 0; } -EXPORT_SYMBOL(nvidia_p2p_get_rsync_registers); +NV_EXPORT_SYMBOL(nvidia_p2p_get_rsync_registers); void nvidia_p2p_put_rsync_registers( nvidia_p2p_rsync_reg_info_t *reg_info @@ -1045,4 +1093,4 @@ void nvidia_p2p_put_rsync_registers( os_free_mem(reg_info); } -EXPORT_SYMBOL(nvidia_p2p_put_rsync_registers); +NV_EXPORT_SYMBOL(nvidia_p2p_put_rsync_registers); diff --git a/kernel-open/nvidia/nv-pci-table.c b/kernel-open/nvidia/nv-pci-table.c index e3494735a5..ac730d5710 100644 --- a/kernel-open/nvidia/nv-pci-table.c +++ b/kernel-open/nvidia/nv-pci-table.c @@ -25,6 +25,15 @@ #include #include "nv-pci-table.h" +#include "cpuopsys.h" + +#if defined(NV_BSD) +/* Define PCI classes that FreeBSD's linuxkpi is missing */ +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 +#endif /* Devices supported by RM */ struct pci_device_id nv_pci_table[] = { @@ -48,7 +57,7 @@ struct pci_device_id nv_pci_table[] = { }; /* Devices supported by all drivers in nvidia.ko */ -struct pci_device_id nv_module_device_table[] = { +struct pci_device_id nv_module_device_table[4] = { { .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_ANY_ID, @@ -76,4 +85,6 @@ struct pci_device_id nv_module_device_table[] = { { } }; +#if defined(NV_LINUX) MODULE_DEVICE_TABLE(pci, nv_module_device_table); +#endif diff --git a/kernel-open/nvidia/nv-pci-table.h b/kernel-open/nvidia/nv-pci-table.h index b28483bb61..25daaf420f 100644 --- a/kernel-open/nvidia/nv-pci-table.h +++ b/kernel-open/nvidia/nv-pci-table.h @@ -27,5 +27,6 @@ #include extern struct pci_device_id nv_pci_table[]; +extern struct pci_device_id nv_module_device_table[4]; #endif /* _NV_PCI_TABLE_H_ */ diff --git a/kernel-open/nvidia/nv-pci.c b/kernel-open/nvidia/nv-pci.c index f7bec54731..40cf248c38 100644 --- a/kernel-open/nvidia/nv-pci.c +++ b/kernel-open/nvidia/nv-pci.c @@ -280,6 +280,78 @@ static int nv_resize_pcie_bars(struct pci_dev *pci_dev) { #endif /* NV_PCI_REBAR_GET_POSSIBLE_SIZES_PRESENT */ } +#if defined(NV_DEVICE_PROPERTY_READ_U64_PRESENT) && \ + defined(CONFIG_ACPI_NUMA) && \ + NV_IS_EXPORT_SYMBOL_PRESENT_pxm_to_node +/* + * Parse the SRAT table to look for numa node associated with the GPU. + * + * find_gpu_numa_nodes_in_srat() is strongly associated with + * nv_init_coherent_link_info(). Hence matching the conditions wrapping. + */ +static NvU32 find_gpu_numa_nodes_in_srat(nv_linux_state_t *nvl) +{ + NvU32 gi_dbdf, dev_dbdf, pxm_count = 0; + struct acpi_table_header *table_header; + struct acpi_subtable_header *subtable_header; + unsigned long table_end, subtable_header_length; + struct acpi_srat_generic_affinity *gi; + NvU32 numa_node = NUMA_NO_NODE; + + if (acpi_get_table(ACPI_SIG_SRAT, 0, &table_header)) { + nv_printf(NV_DBG_INFO, "NVRM: Failed to parse the SRAT table.\n"); + return 0; + } + + table_end = (unsigned long)table_header + table_header->length; + subtable_header = (struct acpi_subtable_header *) + ((unsigned long)table_header + sizeof(struct acpi_table_srat)); + subtable_header_length = subtable_header->length; + + dev_dbdf = NV_PCI_DOMAIN_NUMBER(nvl->pci_dev) << 16 | + NV_PCI_BUS_NUMBER(nvl->pci_dev) << 8 | + NV_PCI_DEVFN(nvl->pci_dev); + + /* + * On baremetal and passthrough, there could be upto 8 generic initiators. + * This is not a hack as a device can have any number of initiators hardware + * supports. + */ + while (subtable_header_length && + (((unsigned long)subtable_header) + subtable_header_length < table_end)) { + + if (subtable_header->type == ACPI_SRAT_TYPE_GENERIC_AFFINITY) { + gi = (struct acpi_srat_generic_affinity *) subtable_header; + gi_dbdf = *((NvU16 *)(&gi->device_handle[0])) << 16 | + *((NvU16 *)(&gi->device_handle[2])); + + if (gi_dbdf == dev_dbdf) { + numa_node = pxm_to_node(gi->proximity_domain); + if (numa_node < MAX_NUMNODES) { + pxm_count++; + set_bit(numa_node, nvl->coherent_link_info.free_node_bitmap); + } + else { + /* We shouldn't be here. This is a mis-configuration. */ + nv_printf(NV_DBG_INFO, "NVRM: Invalid node-id found.\n"); + pxm_count = 0; + goto exit; + } + } + } + + subtable_header = (struct acpi_subtable_header *) + ((unsigned long) subtable_header + subtable_header_length); + subtable_header_length = subtable_header->length; + } + +exit: + acpi_put_table(table_header); + return pxm_count; +} + +#endif + static void nv_init_coherent_link_info ( @@ -294,16 +366,28 @@ nv_init_coherent_link_info NvU64 pxm_start = 0; NvU64 pxm_count = 0; NvU32 pxm; + NvU32 gi_found = 0, node; if (!NVCPU_IS_AARCH64) return; - if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-start", &pxm_start) != 0) - goto failed; - if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-count", &pxm_count) != 0) + if (!dev_is_pci(nvl->dev)) + return; + + gi_found = find_gpu_numa_nodes_in_srat(nvl); + if (!gi_found && + (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-start", &pxm_start) != 0 || + device_property_read_u64(nvl->dev, "nvidia,gpu-mem-pxm-count", &pxm_count) != 0)) goto failed; - if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-base-pa", &pa) != 0) + + if (device_property_read_u64(nvl->dev, "nvidia,gpu-mem-base-pa", &pa) == 0) { + nvl->coherent_link_info.gpu_mem_pa = pa; + } + else + { + unsigned int gpu_bar1_offset, gpu_bar2_offset; + /* * This implies that the DSD key for PXM start and count is present * while the one for Physical Address (PA) is absent. @@ -316,28 +400,80 @@ nv_init_coherent_link_info /* * For the virtualization usecase on SHH, the coherent GPU memory - * PA is exposed as BAR1 to the VM and the nvidia,gpu-mem-base-pa - * is not present. Set the GPU memory PA to the BAR1 start address. + * PA is exposed as BAR2 to the VM and the "nvidia,gpu-mem-base-pa" + * is not present. Set the GPU memory PA to the BAR2 start address. + * + * In the case of passthrough, reserved memory portion of the coherent + * GPU memory is exposed as BAR1 */ - pa = nv->fb->cpu_address; + + /* + * Hopper+ uses 64-bit BARs, so GPU BAR2 should be at BAR4/5 and + * GPU BAR1 is at BAR2/3 + */ + gpu_bar1_offset = 2; + gpu_bar2_offset = 4; + + /* + * cannot use nv->bars[] here as it is not populated correctly if BAR1 is + * not present but BAR2 is, even though PCIe spec allows it. Not fixing + * nv->bars[] since this is not a valid scenario with the actual HW and + * possible only with this host emulated BAR scenario. + */ + if (!((NV_PCI_RESOURCE_VALID(nvl->pci_dev, gpu_bar2_offset)) && + (NV_PCI_RESOURCE_FLAGS(nvl->pci_dev, gpu_bar2_offset) & PCI_BASE_ADDRESS_SPACE) + == PCI_BASE_ADDRESS_SPACE_MEMORY)) + { + // BAR2 contains the cacheable part of the coherent FB region and must have. + goto failed; + } + nvl->coherent_link_info.gpu_mem_pa = + NV_PCI_RESOURCE_START(nvl->pci_dev, gpu_bar2_offset); + + if ((NV_PCI_RESOURCE_VALID(nvl->pci_dev, gpu_bar1_offset)) && + (NV_PCI_RESOURCE_FLAGS(nvl->pci_dev, gpu_bar1_offset) & PCI_BASE_ADDRESS_SPACE) + == PCI_BASE_ADDRESS_SPACE_MEMORY) + { + // Present only in passthrough case + nvl->coherent_link_info.rsvd_mem_pa = NV_PCI_RESOURCE_START(nvl->pci_dev, gpu_bar1_offset); + } + + // + // Unset nv->bars[] as the BARs in the virtualization case are used + // only to convey the coherent GPU memory information and doesn't + // contain the traditional GPU BAR1/BAR2. This is to ensure the + // coherent FB addresses don't inadvertently pass the IS_FB_OFFSET + // or IS_IMEM_OFFSET checks. + // + memset(&nv->bars[1], 0, sizeof(nv->bars[1])); + memset(&nv->bars[2], 0, sizeof(nv->bars[2])); } - NV_DEV_PRINTF(NV_DBG_INFO, nv, "DSD properties: \n"); - NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PA: 0x%lx \n", pa); - NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PXM start: %u \n", pxm_start); - NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PXM count: %u \n", pxm_count); - nvl->coherent_link_info.gpu_mem_pa = pa; + NV_DEV_PRINTF(NV_DBG_INFO, nv, "DSD properties: \n"); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU memory PA: 0x%lx \n", + nvl->coherent_link_info.gpu_mem_pa); + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tGPU reserved memory PA: 0x%lx \n", + nvl->coherent_link_info.rsvd_mem_pa); - for (pxm = pxm_start; pxm < (pxm_start + pxm_count); pxm++) + if (!gi_found) { - NvU32 node = pxm_to_node(pxm); - if (node != NUMA_NO_NODE) + for (pxm = pxm_start; pxm < (pxm_start + pxm_count); pxm++) { - set_bit(node, nvl->coherent_link_info.free_node_bitmap); + node = pxm_to_node(pxm); + if (node != NUMA_NO_NODE) + { + set_bit(node, nvl->coherent_link_info.free_node_bitmap); + } } } + for (node = 0; (node = find_next_bit(nvl->coherent_link_info.free_node_bitmap, + MAX_NUMNODES, node)) != MAX_NUMNODES; node++) + { + NV_DEV_PRINTF(NV_DBG_INFO, nv, "\tNVRM: GPU memory NUMA node: %u\n", node); + } + if (NVreg_EnableUserNUMAManagement && !os_is_vgx_hyper()) { NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_OFFLINE); @@ -696,6 +832,14 @@ nv_pci_probe goto err_zero_dev; } + nv->cpu_numa_node_id = dev_to_node(nvl->dev); + + if (nv_linux_init_open_q(nvl) != 0) + { + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, "nv_linux_init_open_q() failed!\n"); + goto err_zero_dev; + } + nv_printf(NV_DBG_INFO, "NVRM: PCI:%04x:%02x:%02x.%x (%04x:%04x): BAR0 @ 0x%llx (%lluMB)\n", nv->pci_info.domain, nv->pci_info.bus, nv->pci_info.slot, @@ -720,7 +864,7 @@ nv_pci_probe if (nv_linux_add_device_locked(nvl) != 0) { UNLOCK_NV_LINUX_DEVICES(); - goto err_zero_dev; + goto err_add_device; } UNLOCK_NV_LINUX_DEVICES(); @@ -772,6 +916,8 @@ nv_pci_probe LOCK_NV_LINUX_DEVICES(); nv_linux_remove_device_locked(nvl); UNLOCK_NV_LINUX_DEVICES(); +err_add_device: + nv_linux_stop_open_q(nvl); err_zero_dev: rm_free_private_state(sp, nv); err_not_supported: @@ -820,14 +966,22 @@ nv_pci_remove(struct pci_dev *pci_dev) return; } - LOCK_NV_LINUX_DEVICES(); nvl = pci_get_drvdata(pci_dev); if (!nvl || (nvl->pci_dev != pci_dev)) { - goto done; + nv_kmem_cache_free_stack(sp); + return; } nv = NV_STATE_PTR(nvl); + + /* + * Flush and stop open_q before proceeding with removal to ensure nvl + * outlives all enqueued work items. + */ + nv_linux_stop_open_q(nvl); + + LOCK_NV_LINUX_DEVICES(); down(&nvl->ldata_lock); /* @@ -1067,6 +1221,21 @@ NvU8 nv_find_pci_capability(struct pci_dev *pci_dev, NvU8 capability) return 0; } +static void check_for_bound_driver(struct pci_dev *pci_dev) +{ + if (pci_dev->dev.driver) + { + const char *driver_name = pci_dev->dev.driver->name; + + nv_printf(NV_DBG_WARNINGS, "NVRM: GPU %04x:%02x:%02x.%x is already " + "bound to %s.\n", + NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), + NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn), + driver_name ? driver_name : "another driver" + ); + } +} + /* make sure the pci_driver called probe for all of our devices. * we've seen cases where rivafb claims the device first and our driver * doesn't get called. @@ -1094,6 +1263,7 @@ nv_pci_count_devices(void) pci_dev->subsystem_device, NV_TRUE /* print_legacy_warning */)) { + check_for_bound_driver(pci_dev); count++; } pci_dev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pci_dev); @@ -1111,6 +1281,7 @@ nv_pci_count_devices(void) pci_dev->subsystem_device, NV_TRUE /* print_legacy_warning */)) { + check_for_bound_driver(pci_dev); count++; } pci_dev = pci_get_class(PCI_CLASS_DISPLAY_3D << 8, pci_dev); diff --git a/kernel-open/nvidia/nv-reg.h b/kernel-open/nvidia/nv-reg.h index d552477293..9d6978fe26 100644 --- a/kernel-open/nvidia/nv-reg.h +++ b/kernel-open/nvidia/nv-reg.h @@ -822,6 +822,23 @@ #define __NV_RM_NVLINK_BW RmNvlinkBandwidth #define NV_RM_NVLINK_BW NV_REG_STRING(__NV_RM_NVLINK_BW) +/* + * Option: NVreg_EnableNonblockingOpen + * + * Description: + * + * When this option is enabled, the NVIDIA driver will try to perform any + * required device initialization in the background when /dev/nvidiaN devices + * are opened with the flag O_NONBLOCK. + * + * Possible Values: + * 0 = O_NONBLOCK flag when opening devices is ignored + * 1 = O_NONBLOCK flag when opening devices results in background device + * initialization (default) + */ +#define __NV_ENABLE_NONBLOCKING_OPEN EnableNonblockingOpen +#define NV_ENABLE_NONBLOCKING_OPEN NV_REG_STRING(__NV_ENABLE_NONBLOCKING_OPEN) + #if defined(NV_DEFINE_REGISTRY_KEY_TABLE) /* @@ -860,6 +877,7 @@ NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_PCIE_RELAXED_ORDERING_MODE, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_REGISTER_PCI_DRIVER, 1); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_RESIZABLE_BAR, 0); NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_DBG_BREAKPOINT, 0); +NV_DEFINE_REG_ENTRY_GLOBAL(__NV_ENABLE_NONBLOCKING_OPEN, 1); NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_REGISTRY_DWORDS_PER_DEVICE, NULL); diff --git a/kernel-open/nvidia/nv-vm.c b/kernel-open/nvidia/nv-vm.c index 1c7c15ce7f..0f5dc505d6 100644 --- a/kernel-open/nvidia/nv-vm.c +++ b/kernel-open/nvidia/nv-vm.c @@ -516,7 +516,6 @@ NV_STATUS nv_alloc_system_pages( // Order should be zero except for EGM allocations. unsigned int alloc_page_size = PAGE_SIZE << at->order; - unsigned int alloc_page_shift = BIT_IDX_32(alloc_page_size); unsigned int alloc_num_pages = NV_CEIL(at->num_pages * PAGE_SIZE, alloc_page_size); unsigned int sub_page_idx; @@ -644,8 +643,6 @@ void nv_free_system_pages( // Order should be zero except for EGM allocations. unsigned int alloc_page_size = PAGE_SIZE << at->order; - unsigned int alloc_page_shift = BIT_IDX_32(alloc_page_size); - unsigned int alloc_num_pages = NV_CEIL(at->num_pages * PAGE_SIZE, alloc_page_size); unsigned int os_pages_in_page = alloc_page_size / PAGE_SIZE; nv_printf(NV_DBG_MEMINFO, diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index 6aa36099d4..cf5248ee9f 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -37,7 +37,6 @@ #include "nv-msi.h" #include "nv-pci-table.h" #include "nv-chardev-numbers.h" -#include "nv-register-module.h" // TODO remove once NVKMS migrates #if defined(NV_UVM_ENABLE) #include "nv_uvm_interface.h" @@ -156,10 +155,6 @@ static struct cdev nv_linux_devices_cdev; // cdev covering the control device static struct cdev nv_linux_control_device_cdev; -// lock for nvidia_register_module "extmod" emulation -// TODO remove once NVKMS migrates -static struct semaphore nv_extmod_lock; - extern NvU32 nv_dma_remap_peer_mmio; nv_kthread_q_t nv_kthread_q; @@ -182,8 +177,6 @@ static int nv_tce_bypass_mode = NV_TCE_BYPASS_MODE_DEFAULT; struct semaphore nv_linux_devices_lock; -static NvTristate nv_chipset_is_io_coherent = NV_TRISTATE_INDETERMINATE; - // True if all the successfully probed devices support ATS // Assigned at device probe (module init) time NvBool nv_ats_supported = NVCPU_IS_PPC64LE @@ -667,8 +660,6 @@ nv_module_init(nv_stack_t **sp) { int rc; - NV_INIT_MUTEX(&nv_extmod_lock); // TODO remove once NVKMS migrates - rc = nv_module_resources_init(sp); if (rc < 0) { @@ -861,9 +852,8 @@ static int __init nvidia_init_module(void) "NVRM: The NVIDIA probe routine was not called for %d device(s).\n", count - num_probed_nv_devices); nv_printf(NV_DBG_ERRORS, - "NVRM: This can occur when a driver such as: \n" - "NVRM: nouveau, rivafb, nvidiafb or rivatv " - "\nNVRM: was loaded and obtained ownership of the NVIDIA device(s).\n"); + "NVRM: This can occur when another driver was loaded and \n" + "NVRM: obtained ownership of the NVIDIA device(s).\n"); nv_printf(NV_DBG_ERRORS, "NVRM: Try unloading the conflicting kernel module (and/or\n" "NVRM: reconfigure your kernel without the conflicting\n" @@ -1019,12 +1009,32 @@ static void nv_free_file_private(nv_linux_file_private_t *nvlfp) NV_KFREE(nvlfp, sizeof(nv_linux_file_private_t)); } - -static int nv_is_control_device( - struct inode *inode -) +/* + * Find the nv device with the given minor device number in the minor number + * table. Caller should hold nv_linux_devices_lock using + * LOCK_NV_LINUX_DEVICES. This function does not automatically take + * nvl->ldata_lock, so the caller must do that if required. + */ +static nv_linux_state_t *find_minor_locked(NvU32 minor) { - return (minor((inode)->i_rdev) == NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE); + nv_linux_state_t *nvl; + + if (minor > NV_MINOR_DEVICE_NUMBER_REGULAR_MAX) + return NULL; + + nvl = nv_linux_minor_num_table[minor]; + if (nvl == NULL) + { + // there isn't actually a GPU present for nv_linux_minor_num_table[minor] + } + else if (nvl->minor_num != minor) + { + // nv_linux_minor_num_table out of sync -- this shouldn't happen + WARN_ON(1); + nvl = NULL; + } + + return nvl; } /* @@ -1040,17 +1050,11 @@ static nv_linux_state_t *find_minor(NvU32 minor) LOCK_NV_LINUX_DEVICES(); - nvl = nv_linux_minor_num_table[minor]; - if (nvl->minor_num == minor) + nvl = find_minor_locked(minor); + if (nvl != NULL) { down(&nvl->ldata_lock); } - else - { - // nv_linux_minor_num_table out of sync -- this shouldn't happen - WARN_ON(1); - nvl = NULL; - } UNLOCK_NV_LINUX_DEVICES(); return nvl; @@ -1320,12 +1324,11 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp) rm_read_registry_dword(sp, nv, NV_REG_ENABLE_MSI, &msi_config); if (msi_config == 1) { - if (pci_find_capability(nvl->pci_dev, PCI_CAP_ID_MSIX)) + if (nvl->pci_dev->msix_cap && rm_is_msix_allowed(sp, nv)) { nv_init_msix(nv); } - if (pci_find_capability(nvl->pci_dev, PCI_CAP_ID_MSI) && - !(nv->flags & NV_FLAG_USES_MSIX)) + if (nvl->pci_dev->msi_cap && !(nv->flags & NV_FLAG_USES_MSIX)) { nv_init_msi(nv); } @@ -1528,6 +1531,17 @@ static int nv_open_device(nv_state_t *nv, nvidia_stack_t *sp) int rc; NV_STATUS status; + if ((nv->flags & NV_FLAG_EXCLUDE) != 0) + { + char *uuid = rm_get_gpu_uuid(sp, nv); + NV_DEV_PRINTF(NV_DBG_ERRORS, nv, + "open() not permitted for excluded %s\n", + (uuid != NULL) ? uuid : "GPU"); + if (uuid != NULL) + os_free_mem(uuid); + return -EPERM; + } + if (os_is_vgx_hyper()) { /* fail open if GPU is being unbound */ @@ -1575,6 +1589,8 @@ static int nv_open_device(nv_state_t *nv, nvidia_stack_t *sp) return -EBUSY; } + nv_assert_not_in_gpu_exclusion_list(sp, nv); + NV_ATOMIC_INC(nvl->usage_count); return 0; } @@ -1601,6 +1617,108 @@ static void nv_init_mapping_revocation(nv_linux_state_t *nvl, up(&nvl->mmap_lock); } +/* + * Like nv_open_device but stores rc and adapter status in the given nvlfp. + * Assumes nvl->ldata_lock is held. + */ +static int nv_open_device_for_nvlfp( + nv_state_t *nv, + nvidia_stack_t *sp, + nv_linux_file_private_t *nvlfp +) +{ + nvlfp->open_rc = nv_open_device(nv, sp); + + if (nvlfp->open_rc == 0) + { + nvlfp->adapter_status = NV_OK; + } + else + { + nvlfp->adapter_status = rm_get_adapter_status_external(sp, nv); + } + + return nvlfp->open_rc; +} + +static void nvidia_open_deferred(void *nvlfp_raw) +{ + nv_linux_file_private_t *nvlfp = (nv_linux_file_private_t *) nvlfp_raw; + nv_linux_state_t *nvl = nvlfp->deferred_open_nvl; + int rc; + + /* + * Deferred opens and device removal are synchronized via + * nvl->is_accepting_opens and nvl->open_q flushes so that nvl is + * guaranteed to outlive any pending open operation. + * + * So, it is safe to take nvl->ldata_lock here without holding + * any refcount or larger lock. + * + * Deferred opens and system suspend are synchronized by an explicit + * nvl->open_q flush before suspending. + * + * So, it is safe to proceed without nv_system_pm_lock here (in fact, it + * must not be taken to ensure nvl->open_q can make forward progress). + */ + down(&nvl->ldata_lock); + rc = nv_open_device_for_nvlfp(NV_STATE_PTR(nvl), nvlfp->sp, nvlfp); + up(&nvl->ldata_lock); + + /* Set nvptr only upon success (where nvl->usage_count is incremented) */ + if (rc == 0) + nvlfp->nvptr = nvl; + + complete_all(&nvlfp->open_complete); +} + +/* + * Tries to prepare (by taking nvl->ldata_lock) for an open in the foreground + * for the given file and device. + * + * This succeeds if: + * - O_NONBLOCK is not passed (or non-blocking opens are disabled), or + * - O_NONBLOCK is passed, but we are able to determine (without blocking) + * that the device is already initialized + * + * Returns 0 with nvl->ldata_lock taken if open can occur in the foreground. + * Otherwise, returns non-zero (without nvl->ldata_lock taken). + */ +static int nv_try_lock_foreground_open( + struct file *file, + nv_linux_state_t *nvl +) +{ + nv_state_t *nv = NV_STATE_PTR(nvl); + + if (NVreg_EnableNonblockingOpen && (file->f_flags & O_NONBLOCK)) + { + if (down_trylock(&nvl->ldata_lock) == 0) + { + if (nv->flags & NV_FLAG_OPEN) + { + /* device already initialized */ + return 0; + } + else + { + /* device not initialized yet */ + up(&nvl->ldata_lock); + return -EWOULDBLOCK; + } + } + else + { + /* unable to check nv->flags safely without blocking */ + return -EWOULDBLOCK; + } + } + + /* O_NONBLOCK not passed or non-blocking opens are disabled */ + down(&nvl->ldata_lock); + return 0; +} + /* ** nvidia_open ** @@ -1651,37 +1769,81 @@ nvidia_open( if (rc < 0) goto failed; - /* Takes nvl->ldata_lock */ - nvl = find_minor(NV_DEVICE_MINOR_NUMBER(inode)); - if (!nvl) + /* nvptr will get set to actual nvl upon successful open */ + nvlfp->nvptr = NULL; + + init_completion(&nvlfp->open_complete); + + LOCK_NV_LINUX_DEVICES(); + + nvl = find_minor_locked(NV_DEVICE_MINOR_NUMBER(inode)); + if (nvl == NULL) { rc = -ENODEV; + UNLOCK_NV_LINUX_DEVICES(); up_read(&nv_system_pm_lock); goto failed; } - nvlfp->nvptr = nvl; nv = NV_STATE_PTR(nvl); - if ((nv->flags & NV_FLAG_EXCLUDE) != 0) + if (nv_try_lock_foreground_open(file, nvl) == 0) { - char *uuid = rm_get_gpu_uuid(sp, nv); - NV_DEV_PRINTF(NV_DBG_ERRORS, nv, - "open() not permitted for excluded %s\n", - (uuid != NULL) ? uuid : "GPU"); - if (uuid != NULL) - os_free_mem(uuid); - rc = -EPERM; - goto failed1; + /* Proceed in foreground */ + /* nvl->ldata_lock is already taken at this point */ + + UNLOCK_NV_LINUX_DEVICES(); + + rc = nv_open_device_for_nvlfp(nv, nvlfp->sp, nvlfp); + + up(&nvl->ldata_lock); + + /* Set nvptr only upon success (where nvl->usage_count is incremented) */ + if (rc == 0) + nvlfp->nvptr = nvl; + + complete_all(&nvlfp->open_complete); } + else + { + /* Defer to background kthread */ + int item_scheduled = 0; - rc = nv_open_device(nv, sp); - /* Fall-through on error */ + /* + * Take nvl->open_q_lock in order to check nvl->is_accepting_opens and + * schedule work items on nvl->open_q. + * + * Continue holding nv_linux_devices_lock (LOCK_NV_LINUX_DEVICES) + * until the work item gets onto nvl->open_q in order to ensure the + * lifetime of nvl. + */ + down(&nvl->open_q_lock); - nv_assert_not_in_gpu_exclusion_list(sp, nv); + if (!nvl->is_accepting_opens) + { + /* Background kthread is not accepting opens, bail! */ + rc = -EBUSY; + goto nonblock_end; + } -failed1: - up(&nvl->ldata_lock); + nvlfp->deferred_open_nvl = nvl; + nv_kthread_q_item_init(&nvlfp->open_q_item, + nvidia_open_deferred, + nvlfp); + + item_scheduled = nv_kthread_q_schedule_q_item( + &nvl->open_q, &nvlfp->open_q_item); + + if (!item_scheduled) + { + WARN_ON(!item_scheduled); + rc = -EBUSY; + } + +nonblock_end: + up(&nvl->open_q_lock); + UNLOCK_NV_LINUX_DEVICES(); + } up_read(&nv_system_pm_lock); failed: @@ -1876,11 +2038,27 @@ nvidia_close_callback( nv_linux_file_private_t *nvlfp ) { - nv_linux_state_t *nvl = nvlfp->nvptr; - nv_state_t *nv = NV_STATE_PTR(nvl); - nvidia_stack_t *sp = nvlfp->sp; + nv_linux_state_t *nvl; + nv_state_t *nv; + nvidia_stack_t *sp; NvBool bRemove = NV_FALSE; + nvl = nvlfp->nvptr; + if (nvl == NULL) + { + /* + * If nvlfp has no associated nvl device (meaning the open operation + * failed), then there is no state outside of nvlfp to cleanup. + */ + + nv_free_file_private(nvlfp); + nv_kmem_cache_free_stack(nvlfp->sp); + return; + } + + nv = NV_STATE_PTR(nvl); + sp = nvlfp->sp; + rm_cleanup_file_private(sp, nv, &nvlfp->nvfp); down(&nvl->mmap_lock); @@ -1934,6 +2112,8 @@ static void nvidia_close_deferred(void *data) { nv_linux_file_private_t *nvlfp = data; + nv_wait_open_complete(nvlfp); + down_read(&nv_system_pm_lock); nvidia_close_callback(nvlfp); @@ -1949,10 +2129,10 @@ nvidia_close( { int rc; nv_linux_file_private_t *nvlfp = NV_GET_LINUX_FILE_PRIVATE(file); - nv_linux_state_t *nvl = nvlfp->nvptr; - nv_state_t *nv = NV_STATE_PTR(nvl); - NV_DEV_PRINTF(NV_DBG_INFO, nv, "nvidia_close on GPU with minor number %d\n", NV_DEVICE_MINOR_NUMBER(inode)); + nv_printf(NV_DBG_INFO, + "NVRM: nvidia_close on GPU with minor number %d\n", + NV_DEVICE_MINOR_NUMBER(inode)); if (nv_is_control_device(inode)) { @@ -1961,7 +2141,12 @@ nvidia_close( NV_SET_FILE_PRIVATE(file, NULL); - rc = nv_down_read_interruptible(&nv_system_pm_lock); + rc = nv_wait_open_complete_interruptible(nvlfp); + if (rc == 0) + { + rc = nv_down_read_interruptible(&nv_system_pm_lock); + } + if (rc == 0) { nvidia_close_callback(nvlfp); @@ -1989,10 +2174,26 @@ nvidia_poll( unsigned int mask = 0; nv_linux_file_private_t *nvlfp = NV_GET_LINUX_FILE_PRIVATE(file); unsigned long eflags; - nv_linux_state_t *nvl = NV_GET_NVL_FROM_FILEP(file); - nv_state_t *nv = NV_STATE_PTR(nvl); + nv_linux_state_t *nvl; + nv_state_t *nv; NV_STATUS status; + if (!nv_is_control_device(NV_FILE_INODE(file))) + { + if (!nv_is_open_complete(nvlfp)) + { + return POLLERR; + } + } + + nvl = nvlfp->nvptr; + if (nvl == NULL) + { + return POLLERR; + } + + nv = NV_STATE_PTR(nvl); + status = nv_check_gpu_state(nv); if (status == NV_ERR_GPU_IS_LOST) { @@ -2097,9 +2298,9 @@ nvidia_ioctl( { NV_STATUS rmStatus; int status = 0; - nv_linux_state_t *nvl = NV_GET_NVL_FROM_FILEP(file); - nv_state_t *nv = NV_STATE_PTR(nvl); nv_linux_file_private_t *nvlfp = NV_GET_LINUX_FILE_PRIVATE(file); + nv_linux_state_t *nvl; + nv_state_t *nv; nvidia_stack_t *sp = NULL; nv_ioctl_xfer_t ioc_xfer; void *arg_ptr = (void *) i_arg; @@ -2110,23 +2311,11 @@ nvidia_ioctl( nv_printf(NV_DBG_INFO, "NVRM: ioctl(0x%x, 0x%x, 0x%x)\n", _IOC_NR(cmd), (unsigned int) i_arg, _IOC_SIZE(cmd)); - status = nv_down_read_interruptible(&nv_system_pm_lock); - if (status < 0) - return status; - - status = nv_kmem_cache_alloc_stack(&sp); - if (status != 0) + if (!nv_is_control_device(inode)) { - nv_printf(NV_DBG_ERRORS, "NVRM: Unable to allocate altstack for ioctl\n"); - goto done; - } - - rmStatus = nv_check_gpu_state(nv); - if (rmStatus == NV_ERR_GPU_IS_LOST) - { - nv_printf(NV_DBG_INFO, "NVRM: GPU is lost, skipping nvidia_ioctl\n"); - status = -EINVAL; - goto done; + status = nv_wait_open_complete_interruptible(nvlfp); + if (status != 0) + goto done_early; } arg_size = _IOC_SIZE(cmd); @@ -2139,7 +2328,7 @@ nvidia_ioctl( nv_printf(NV_DBG_ERRORS, "NVRM: invalid ioctl XFER structure size!\n"); status = -EINVAL; - goto done; + goto done_early; } if (NV_COPY_FROM_USER(&ioc_xfer, arg_ptr, sizeof(ioc_xfer))) @@ -2147,7 +2336,7 @@ nvidia_ioctl( nv_printf(NV_DBG_ERRORS, "NVRM: failed to copy in ioctl XFER data!\n"); status = -EFAULT; - goto done; + goto done_early; } arg_cmd = ioc_xfer.cmd; @@ -2158,7 +2347,7 @@ nvidia_ioctl( { nv_printf(NV_DBG_ERRORS, "NVRM: invalid ioctl XFER size!\n"); status = -EINVAL; - goto done; + goto done_early; } } @@ -2167,13 +2356,55 @@ nvidia_ioctl( { nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate ioctl memory\n"); status = -ENOMEM; - goto done; + goto done_early; } if (NV_COPY_FROM_USER(arg_copy, arg_ptr, arg_size)) { nv_printf(NV_DBG_ERRORS, "NVRM: failed to copy in ioctl data!\n"); status = -EFAULT; + goto done_early; + } + + /* + * Handle NV_ESC_WAIT_OPEN_COMPLETE early as it is allowed to work + * with or without nvl. + */ + if (arg_cmd == NV_ESC_WAIT_OPEN_COMPLETE) + { + nv_ioctl_wait_open_complete_t *params = arg_copy; + params->rc = nvlfp->open_rc; + params->adapterStatus = nvlfp->adapter_status; + goto done_early; + } + + nvl = nvlfp->nvptr; + if (nvl == NULL) + { + status = -EIO; + goto done_early; + } + + nv = NV_STATE_PTR(nvl); + + status = nv_down_read_interruptible(&nv_system_pm_lock); + if (status < 0) + { + goto done_early; + } + + status = nv_kmem_cache_alloc_stack(&sp); + if (status != 0) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Unable to allocate altstack for ioctl\n"); + goto done_pm_unlock; + } + + rmStatus = nv_check_gpu_state(nv); + if (rmStatus == NV_ERR_GPU_IS_LOST) + { + nv_printf(NV_DBG_INFO, "NVRM: GPU is lost, skipping nvidia_ioctl\n"); + status = -EINVAL; goto done; } @@ -2425,8 +2656,10 @@ nvidia_ioctl( done: nv_kmem_cache_free_stack(sp); +done_pm_unlock: up_read(&nv_system_pm_lock); +done_early: if (arg_copy != NULL) { if (status != -EFAULT) @@ -3285,6 +3518,16 @@ NV_STATUS NV_API_CALL nv_get_phys_pages( return NV_OK; } +void nv_get_disp_smmu_stream_ids +( + nv_state_t *nv, + NvU32 *dispIsoStreamId, + NvU32 *dispNisoStreamId) +{ + *dispIsoStreamId = nv->iommus.dispIsoStreamId; + *dispNisoStreamId = nv->iommus.dispNisoStreamId; +} + void* NV_API_CALL nv_alloc_kernel_mapping( nv_state_t *nv, void *pAllocPrivate, @@ -3486,6 +3729,11 @@ NV_STATUS NV_API_CALL nv_alloc_pages( } else { + if (page_size == 0) + { + status = NV_ERR_INVALID_ARGUMENT; + goto failed; + } at->order = get_order(page_size); status = nv_alloc_system_pages(nv, at); } @@ -3578,6 +3826,7 @@ NvBool nv_lock_init_locks NV_INIT_MUTEX(&nvl->ldata_lock); NV_INIT_MUTEX(&nvl->mmap_lock); + NV_INIT_MUTEX(&nvl->open_q_lock); NV_ATOMIC_SET(nvl->usage_count, 0); @@ -3898,8 +4147,11 @@ nvos_count_devices(void) return count; } +#if NVCPU_IS_AARCH64 NvBool nvos_is_chipset_io_coherent(void) { + static NvTristate nv_chipset_is_io_coherent = NV_TRISTATE_INDETERMINATE; + if (nv_chipset_is_io_coherent == NV_TRISTATE_INDETERMINATE) { nvidia_stack_t *sp = NULL; @@ -3918,6 +4170,7 @@ NvBool nvos_is_chipset_io_coherent(void) return nv_chipset_is_io_coherent; } +#endif // NVCPU_IS_AARCH64 #if defined(CONFIG_PM) static NV_STATUS @@ -3948,6 +4201,17 @@ nv_power_management( /* fall through */ case NV_PM_ACTION_HIBERNATE: { + /* + * Flush nvl->open_q before suspend/hibernate to ensure deferred + * opens do not get attempted during the PM transition. + * + * Note: user space is either frozen by the kernel or locked out + * by nv_system_pm_lock, so no further deferred opens can be + * enqueued before resume (meaning we do not need to unset + * nvl->is_accepting_opens). + */ + nv_kthread_q_flush(&nvl->open_q); + status = rm_power_management(sp, nv, pm_action); nv_kthread_q_stop(&nvl->bottom_half_q); @@ -4656,7 +4920,7 @@ NvU64 NV_API_CALL nv_get_dma_start_address( } else if ((dma_addr & saved_dma_mask) != 0) { - NvU64 memory_size = os_get_num_phys_pages() * PAGE_SIZE; + NvU64 memory_size = NV_NUM_PHYSPAGES * PAGE_SIZE; if ((dma_addr & ~saved_dma_mask) != ((dma_addr + memory_size) & ~saved_dma_mask)) { @@ -4964,6 +5228,7 @@ NV_STATUS NV_API_CALL nv_get_device_memory_config( nv_state_t *nv, NvU64 *compr_addr_sys_phys, NvU64 *addr_guest_phys, + NvU64 *rsvd_phys, NvU32 *addr_width, NvS32 *node_id ) @@ -5024,6 +5289,10 @@ NV_STATUS NV_API_CALL nv_get_device_memory_config( { *addr_guest_phys = nvl->coherent_link_info.gpu_mem_pa; } + if (rsvd_phys) + { + *rsvd_phys = nvl->coherent_link_info.rsvd_mem_pa; + } if (addr_width) { // TH500 PA width - NV_PFB_PRI_MMU_ATS_ADDR_RANGE_GRANULARITY @@ -5240,6 +5509,35 @@ void nv_linux_remove_device_locked(nv_linux_state_t *nvl) nv_linux_minor_num_table[nvl->minor_num] = NULL; } +int nv_linux_init_open_q(nv_linux_state_t *nvl) +{ + int rc; + rc = nv_kthread_q_init(&nvl->open_q, "nv_open_q"); + if (rc != 0) + return rc; + + down(&nvl->open_q_lock); + nvl->is_accepting_opens = NV_TRUE; + up(&nvl->open_q_lock); + return 0; +} + +void nv_linux_stop_open_q(nv_linux_state_t *nvl) +{ + NvBool should_stop = NV_FALSE; + + down(&nvl->open_q_lock); + if (nvl->is_accepting_opens) + { + should_stop = NV_TRUE; + nvl->is_accepting_opens = NV_FALSE; + } + up(&nvl->open_q_lock); + + if (should_stop) + nv_kthread_q_stop(&nvl->open_q); +} + void NV_API_CALL nv_control_soc_irqs(nv_state_t *nv, NvBool bEnable) { int count; @@ -5452,15 +5750,10 @@ void NV_API_CALL nv_audio_dynamic_power( static int nv_match_dev_state(const void *data, struct file *filp, unsigned fd) { nv_linux_state_t *nvl = NULL; - dev_t rdev = 0; if (filp == NULL || - filp->private_data == NULL || - NV_FILE_INODE(filp) == NULL) - return 0; - - rdev = (NV_FILE_INODE(filp))->i_rdev; - if (MAJOR(rdev) != NV_MAJOR_DEVICE_NUMBER) + filp->f_op != &nvidia_fops || + filp->private_data == NULL) return 0; nvl = NV_GET_NVL_FROM_FILEP(filp); @@ -5758,89 +6051,5 @@ NV_STATUS NV_API_CALL nv_get_egm_info( } -/* - * nvidia_register_module "extmod" emulation - * - * TODO remove once NVKMS migrates - * - * Emulate nv-frontend's behavior of enabling the use of minor number 254 - * given module->instance == 1 via the file operations provided in the - * nvidia_module_t structure. - * - * This path is only used by NVKMS and will be removed once NVKMS migrates - * to export its own file_operations structure directly. - */ -static struct file_operations nv_extmod_fops; -static struct cdev nv_extmod_cdev; -static nvidia_module_t *nv_extmod; - -static long nv_extmod_unlocked_ioctl( - struct file *file, - unsigned int cmd, - unsigned long i_arg -) -{ - return nv_extmod->ioctl(NV_FILE_INODE(file), file, cmd, i_arg); -} - -int nvidia_register_module(nvidia_module_t *module) -{ - int rc; - - down(&nv_extmod_lock); - if ((nv_extmod != NULL) || (module == NULL) || (module->instance != 1)) - { - nv_printf(NV_DBG_ERRORS, - "NVRM: NVIDIA module (emulated) registration failed.\n"); - up(&nv_extmod_lock); - return -EINVAL; - } - - memset(&nv_extmod_fops, 0, sizeof(nv_extmod_fops)); - nv_extmod_fops.owner = module->owner; - nv_extmod_fops.poll = module->poll; - nv_extmod_fops.unlocked_ioctl = nv_extmod_unlocked_ioctl; -#if NVCPU_IS_X86_64 || NVCPU_IS_AARCH64 - nv_extmod_fops.compat_ioctl = nv_extmod_unlocked_ioctl; -#endif - nv_extmod_fops.mmap = module->mmap; - nv_extmod_fops.open = module->open; - nv_extmod_fops.release = module->close; - - rc = nv_register_chrdev(NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE, 1, - &nv_extmod_cdev, "nvidia-modeset", &nv_extmod_fops); - if (rc < 0) - { - up(&nv_extmod_lock); - return rc; - } - - nv_extmod = module; - up(&nv_extmod_lock); - return rc; -} -EXPORT_SYMBOL(nvidia_register_module); - -int nvidia_unregister_module(nvidia_module_t *module) -{ - down(&nv_extmod_lock); - if (nv_extmod == NULL) - { - nv_printf(NV_DBG_ERRORS, - "NVRM: NVIDIA module (emulated) non-existent de-registration.\n"); - up(&nv_extmod_lock); - return -EINVAL; - } - - nv_unregister_chrdev(NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE, 1, - &nv_extmod_cdev); - - nv_extmod = NULL; - up(&nv_extmod_lock); - return 0; -} -EXPORT_SYMBOL(nvidia_unregister_module); - - module_init(nvidia_init_module); module_exit(nvidia_exit_module); diff --git a/kernel-open/nvidia/nv_gpu_ops.h b/kernel-open/nvidia/nv_gpu_ops.h index 21a4c04423..149acf2158 100644 --- a/kernel-open/nvidia/nv_gpu_ops.h +++ b/kernel-open/nvidia/nv_gpu_ops.h @@ -60,6 +60,7 @@ NV_STATUS nvGpuOpsDeviceDestroy(struct gpuDevice *device); NV_STATUS nvGpuOpsAddressSpaceCreate(struct gpuDevice *device, NvU64 vaBase, NvU64 vaSize, + NvBool enableAts, gpuAddressSpaceHandle *vaSpace, UvmGpuAddressSpaceInfo *vaSpaceInfo); @@ -93,11 +94,6 @@ NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NvU64 pageSize, NvU32 flags); -NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, - NvU64 *pPages, - NvLength pageCount, - NvU64 pageSize); - NV_STATUS nvGpuOpsTsgAllocate(gpuAddressSpaceHandle vaSpace, const gpuTsgAllocParams *params, gpuTsgHandle *tsgHandle); @@ -285,11 +281,14 @@ NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel, NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device); +NV_STATUS nvGpuOpsTogglePrefetchFaults(gpuFaultInfo *pFaultInfo, NvBool bEnable); + // Interface used for CCSL NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx, gpuChannelHandle channel); NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx); +NV_STATUS nvGpuOpsCcslContextUpdate(struct ccslContext_t *ctx); NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, NvU8 direction); NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx, @@ -322,5 +321,7 @@ NV_STATUS nvGpuOpsIncrementIv(struct ccslContext_t *ctx, NvU8 direction, NvU64 increment, NvU8 *iv); +NV_STATUS nvGpuOpsLogDeviceEncryption(struct ccslContext_t *ctx, + NvU32 bufferSize); #endif /* _NV_GPU_OPS_H_*/ diff --git a/kernel-open/nvidia/nv_uvm_interface.c b/kernel-open/nvidia/nv_uvm_interface.c index c5638adc6f..bb1a23cb41 100644 --- a/kernel-open/nvidia/nv_uvm_interface.c +++ b/kernel-open/nvidia/nv_uvm_interface.c @@ -209,7 +209,7 @@ NV_STATUS nvUvmInterfaceSessionCreate(uvmGpuSessionHandle *session, memset(platformInfo, 0, sizeof(*platformInfo)); platformInfo->atsSupported = nv_ats_supported; - platformInfo->sevEnabled = os_cc_enabled; + platformInfo->confComputingEnabled = os_cc_enabled; status = rm_gpu_ops_create_session(sp, (gpuSessionHandle *)session); @@ -295,6 +295,7 @@ EXPORT_SYMBOL(nvUvmInterfaceDupAddressSpace); NV_STATUS nvUvmInterfaceAddressSpaceCreate(uvmGpuDeviceHandle device, unsigned long long vaBase, unsigned long long vaSize, + NvBool enableAts, uvmGpuAddressSpaceHandle *vaSpace, UvmGpuAddressSpaceInfo *vaSpaceInfo) { @@ -310,6 +311,7 @@ NV_STATUS nvUvmInterfaceAddressSpaceCreate(uvmGpuDeviceHandle device, (gpuDeviceHandle)device, vaBase, vaSize, + enableAts, (gpuAddressSpaceHandle *)vaSpace, vaSpaceInfo); @@ -493,26 +495,6 @@ NV_STATUS nvUvmInterfacePmaPinPages(void *pPma, } EXPORT_SYMBOL(nvUvmInterfacePmaPinPages); -NV_STATUS nvUvmInterfacePmaUnpinPages(void *pPma, - NvU64 *pPages, - NvLength pageCount, - NvU64 pageSize) -{ - nvidia_stack_t *sp = NULL; - NV_STATUS status; - - if (nv_kmem_cache_alloc_stack(&sp) != 0) - { - return NV_ERR_NO_MEMORY; - } - - status = rm_gpu_ops_pma_unpin_pages(sp, pPma, pPages, pageCount, pageSize); - - nv_kmem_cache_free_stack(sp); - return status; -} -EXPORT_SYMBOL(nvUvmInterfacePmaUnpinPages); - void nvUvmInterfaceMemoryFree(uvmGpuAddressSpaceHandle vaSpace, UvmGpuPointer gpuPointer) { @@ -1015,6 +997,18 @@ NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(uvmGpuDeviceHandle device) } EXPORT_SYMBOL(nvUvmInterfaceFlushReplayableFaultBuffer); +NV_STATUS nvUvmInterfaceTogglePrefetchFaults(UvmGpuFaultInfo *pFaultInfo, NvBool bEnable) +{ + nvidia_stack_t *sp = nvUvmGetSafeStack(); + NV_STATUS status; + + status = rm_gpu_ops_toggle_prefetch_faults(sp, pFaultInfo, bEnable); + + nvUvmFreeSafeStack(sp); + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceTogglePrefetchFaults); + NV_STATUS nvUvmInterfaceDestroyAccessCntrInfo(uvmGpuDeviceHandle device, UvmGpuAccessCntrInfo *pAccessCntrInfo) { @@ -1516,6 +1510,17 @@ void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext) } EXPORT_SYMBOL(nvUvmInterfaceDeinitCslContext); +NV_STATUS nvUvmInterfaceCslUpdateContext(UvmCslContext *uvmCslContext) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_context_update(sp, uvmCslContext->ctx); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslUpdateContext); + NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext, UvmCslOperation operation) { @@ -1614,6 +1619,18 @@ NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext, } EXPORT_SYMBOL(nvUvmInterfaceCslIncrementIv); +NV_STATUS nvUvmInterfaceCslLogExternalEncryption(UvmCslContext *uvmCslContext, + NvU32 bufferSize) +{ + NV_STATUS status; + nvidia_stack_t *sp = uvmCslContext->nvidia_stack; + + status = rm_gpu_ops_ccsl_log_device_encryption(sp, uvmCslContext->ctx, bufferSize); + + return status; +} +EXPORT_SYMBOL(nvUvmInterfaceCslLogExternalEncryption); + #else // NV_UVM_ENABLE NV_STATUS nv_uvm_suspend(void) diff --git a/kernel-open/nvidia/nvidia.Kbuild b/kernel-open/nvidia/nvidia.Kbuild index e868c6c32c..7908ce7168 100644 --- a/kernel-open/nvidia/nvidia.Kbuild +++ b/kernel-open/nvidia/nvidia.Kbuild @@ -195,6 +195,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_task_ioprio NV_CONFTEST_FUNCTION_COMPILE_TESTS += mdev_set_iommu_device NV_CONFTEST_FUNCTION_COMPILE_TESTS += offline_and_remove_memory +NV_CONFTEST_FUNCTION_COMPILE_TESTS += crypto_tfm_ctx_aligned NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_of_node_to_nid NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sme_active @@ -215,6 +216,7 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_get_dram_num_channe NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_dram_types NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pxm_to_node NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_screen_info +NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_screen_info NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_i2c_bus_status NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_fuse_control_read NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_get_platform diff --git a/kernel-open/nvidia/os-interface.c b/kernel-open/nvidia/os-interface.c index 524e8c4877..1344ddb4dd 100644 --- a/kernel-open/nvidia/os-interface.c +++ b/kernel-open/nvidia/os-interface.c @@ -30,14 +30,18 @@ #include #include +#include #include +#if defined(CONFIG_LOCKDEP) +#include +#endif // CONFIG_LOCKDEP extern char *NVreg_TemporaryFilePath; -#define MAX_ERROR_STRING 512 +#define MAX_ERROR_STRING 528 static char nv_error_string[MAX_ERROR_STRING]; -nv_spinlock_t nv_error_string_lock; +static NV_DEFINE_SPINLOCK(nv_error_string_lock); extern nv_linux_state_t nv_ctl_device; @@ -238,7 +242,20 @@ NV_STATUS NV_API_CALL os_release_semaphore return NV_OK; } -typedef struct rw_semaphore os_rwlock_t; +typedef struct +{ + struct rw_semaphore sem; + +#if defined(CONFIG_LOCKDEP) + /** + * A key of lock class. It would be registered to Lockdep validator so all + * instances' usages and dependencies will contribute to constructing correct + * locking rules and this lock will be tracked by the Lockdep validator. + * + */ + struct lock_class_key key; +#endif // CONFIG_LOCKDEP +} os_rwlock_t; void* NV_API_CALL os_alloc_rwlock(void) { @@ -247,11 +264,17 @@ void* NV_API_CALL os_alloc_rwlock(void) NV_STATUS rmStatus = os_alloc_mem((void *)&os_rwlock, sizeof(os_rwlock_t)); if (rmStatus != NV_OK) { - nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate rw_semaphore!\n"); + nv_printf(NV_DBG_ERRORS, "NVRM: failed to allocate a struct os_rwlock_t!\n"); return NULL; } - init_rwsem(os_rwlock); + init_rwsem(&os_rwlock->sem); + +#if defined(CONFIG_LOCKDEP) + // Register the dynamically allocated key to Lockdep. + lockdep_register_key(&os_rwlock->key); + lockdep_set_class(&os_rwlock->sem, &os_rwlock->key); +#endif // CONFIG_LOCKDEP return os_rwlock; } @@ -259,6 +282,12 @@ void* NV_API_CALL os_alloc_rwlock(void) void NV_API_CALL os_free_rwlock(void *pRwLock) { os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; + +#if defined(CONFIG_LOCKDEP) + // Unregister the dynamically allocated key. + lockdep_unregister_key(&os_rwlock->key); +#endif // CONFIG_LOCKDEP + os_free_mem(os_rwlock); } @@ -270,7 +299,7 @@ NV_STATUS NV_API_CALL os_acquire_rwlock_read(void *pRwLock) { return NV_ERR_INVALID_REQUEST; } - down_read(os_rwlock); + down_read(&os_rwlock->sem); return NV_OK; } @@ -282,7 +311,7 @@ NV_STATUS NV_API_CALL os_acquire_rwlock_write(void *pRwLock) { return NV_ERR_INVALID_REQUEST; } - down_write(os_rwlock); + down_write(&os_rwlock->sem); return NV_OK; } @@ -290,7 +319,7 @@ NV_STATUS NV_API_CALL os_cond_acquire_rwlock_read(void *pRwLock) { os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; - if (down_read_trylock(os_rwlock)) + if (down_read_trylock(&os_rwlock->sem)) { return NV_ERR_TIMEOUT_RETRY; } @@ -302,7 +331,7 @@ NV_STATUS NV_API_CALL os_cond_acquire_rwlock_write(void *pRwLock) { os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; - if (down_write_trylock(os_rwlock)) + if (down_write_trylock(&os_rwlock->sem)) { return NV_ERR_TIMEOUT_RETRY; } @@ -313,13 +342,13 @@ NV_STATUS NV_API_CALL os_cond_acquire_rwlock_write(void *pRwLock) void NV_API_CALL os_release_rwlock_read(void *pRwLock) { os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; - up_read(os_rwlock); + up_read(&os_rwlock->sem); } void NV_API_CALL os_release_rwlock_write(void *pRwLock) { os_rwlock_t *os_rwlock = (os_rwlock_t *)pRwLock; - up_write(os_rwlock); + up_write(&os_rwlock->sem); } NvBool NV_API_CALL os_semaphore_may_sleep(void) @@ -343,11 +372,6 @@ NvBool NV_API_CALL os_allow_priority_override(void) return capable(CAP_SYS_NICE); } -NvU64 NV_API_CALL os_get_num_phys_pages(void) -{ - return (NvU64)NV_NUM_PHYSPAGES; -} - char* NV_API_CALL os_string_copy( char *dst, const char *src @@ -782,8 +806,6 @@ inline void NV_API_CALL out_string(const char *str) printk("%s", str); } -#define NV_PRINT_LOCAL_BUFF_LEN_MAX 530 - /* * nv_printf() prints to the kernel log for the driver. * Returns the number of characters written. @@ -792,38 +814,11 @@ int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...) { va_list arglist; int chars_written = 0; - NvBool bForced = (NV_DBG_FORCE_LEVEL(debuglevel) == debuglevel); - debuglevel = debuglevel & 0xff; - - // This function is protected by the "_nv_dbg_lock" lock, so it is still - // thread-safe to store the print buffer in a static variable, thus - // avoiding a problem with kernel stack size. - static char buff[NV_PRINT_LOCAL_BUFF_LEN_MAX]; - /* - * Print a message if: - * 1. Caller indicates that filtering should be skipped, or - * 2. debuglevel is at least cur_debuglevel for DBG_MODULE_OS (bits 4:5). Support for print - * modules has been removed with DBG_PRINTF, so this check should be cleaned up. - */ - if (bForced || - (debuglevel >= ((cur_debuglevel >> 4) & 0x3))) + if (debuglevel >= ((cur_debuglevel >> 4) & 0x3)) { - size_t loglevel_length = 0, format_length = strlen(printf_format); - size_t length = 0; - const char *loglevel = ""; - - switch (debuglevel) - { - case NV_DBG_INFO: loglevel = KERN_DEBUG; break; - case NV_DBG_SETUP: loglevel = KERN_NOTICE; break; - case NV_DBG_WARNINGS: loglevel = KERN_WARNING; break; - case NV_DBG_ERRORS: loglevel = KERN_ERR; break; - case NV_DBG_HW_ERRORS: loglevel = KERN_CRIT; break; - case NV_DBG_FATAL: loglevel = KERN_CRIT; break; - } - - loglevel_length = strlen(loglevel); + size_t length; + unsigned long flags; // When printk is called to extend the output of the previous line // (i.e. when the previous line did not end in \n), the printk call @@ -843,19 +838,22 @@ int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...) // string always contains only one \n (at the end) and NV_PRINTF_EX // is deleted. But that is unlikely to ever happen. - length = loglevel_length + format_length + sizeof(KERN_CONT); + length = strlen(printf_format); if (length < 1) return 0; + NV_SPIN_LOCK_IRQSAVE(&nv_error_string_lock, flags); + // KERN_CONT changed in the 3.6 kernel, so we can't assume its // composition or size. - memcpy(buff, KERN_CONT, sizeof(KERN_CONT) - 1); - memcpy(buff + sizeof(KERN_CONT) - 1, loglevel, loglevel_length); - memcpy(buff + sizeof(KERN_CONT) - 1 + loglevel_length, printf_format, length + 1); + memcpy(nv_error_string, KERN_CONT, sizeof(KERN_CONT) - 1); + memcpy(nv_error_string + sizeof(KERN_CONT) - 1, printf_format, length + 1); va_start(arglist, printf_format); - chars_written = vprintk(buff, arglist); + chars_written = vprintk(nv_error_string, arglist); va_end(arglist); + + NV_SPIN_UNLOCK_IRQRESTORE(&nv_error_string_lock, flags); } return chars_written; @@ -1007,26 +1005,29 @@ void NV_API_CALL os_unmap_kernel_space( nv_iounmap(addr, size_bytes); } -// flush the cpu's cache, uni-processor version -NV_STATUS NV_API_CALL os_flush_cpu_cache(void) +#if NVCPU_IS_AARCH64 + +static inline void nv_flush_cache_cpu(void *info) { - CACHE_FLUSH(); - return NV_OK; + if (!nvos_is_chipset_io_coherent()) + { +#if defined(NV_FLUSH_CACHE_ALL_PRESENT) + flush_cache_all(); +#else + WARN_ONCE(0, "kernel does not provide flush_cache_all()\n"); +#endif + } } // flush the cache of all cpus NV_STATUS NV_API_CALL os_flush_cpu_cache_all(void) { -#if defined(NVCPU_AARCH64) - CACHE_FLUSH_ALL(); + on_each_cpu(nv_flush_cache_cpu, NULL, 1); return NV_OK; -#endif - return NV_ERR_NOT_SUPPORTED; } NV_STATUS NV_API_CALL os_flush_user_cache(void) { -#if defined(NVCPU_AARCH64) if (!NV_MAY_SLEEP()) { return NV_ERR_NOT_SUPPORTED; @@ -1037,16 +1038,27 @@ NV_STATUS NV_API_CALL os_flush_user_cache(void) // although it is possible. For now, just flush the entire cache to be // safe. // - CACHE_FLUSH_ALL(); + on_each_cpu(nv_flush_cache_cpu, NULL, 1); return NV_OK; -#else +} + +#else // NVCPU_IS_AARCH64 + +NV_STATUS NV_API_CALL os_flush_cpu_cache_all(void) +{ return NV_ERR_NOT_SUPPORTED; -#endif } +NV_STATUS NV_API_CALL os_flush_user_cache(void) +{ + return NV_ERR_NOT_SUPPORTED; +} + +#endif + void NV_API_CALL os_flush_cpu_write_combine_buffer(void) { - WRITE_COMBINE_FLUSH(); + wmb(); } // override initial debug level from registry @@ -1055,8 +1067,6 @@ void NV_API_CALL os_dbg_init(void) NvU32 new_debuglevel; nvidia_stack_t *sp = NULL; - NV_SPIN_LOCK_INIT(&nv_error_string_lock); - if (nv_kmem_cache_alloc_stack(&sp) != 0) { return; @@ -1082,7 +1092,7 @@ void NV_API_CALL os_dbg_set_level(NvU32 new_debuglevel) NvU64 NV_API_CALL os_get_max_user_va(void) { - return TASK_SIZE; + return TASK_SIZE; } NV_STATUS NV_API_CALL os_schedule(void) @@ -1271,9 +1281,12 @@ void NV_API_CALL os_get_screen_info( * SYSFB_SIMPLEFB registers a dummy framebuffer which does not contain the * information required by os_get_screen_info(), therefore you need to * fall back onto the screen_info structure. + * + * After commit b8466fe82b79 ("efi: move screen_info into efi init code") + * in v6.7, 'screen_info' is exported as GPL licensed symbol for ARM64. */ -#if NV_IS_EXPORT_SYMBOL_PRESENT_screen_info +#if NV_CHECK_EXPORT_SYMBOL(screen_info) /* * If there is not a framebuffer console, return 0 size. * @@ -1714,7 +1727,7 @@ NV_STATUS NV_API_CALL os_alloc_pages_node * instead). * * 6. (Optional) __GFP_RECLAIM: Used to allow/forbid reclaim. - * This is part of GFP_USER and consequently + * This is part of GFP_USER and consequently * GFP_HIGHUSER_MOVABLE. * * Some of these flags are relatively more recent, with the last of them @@ -2330,6 +2343,37 @@ NV_STATUS NV_API_CALL os_numa_add_gpu_memory goto failed; } + /* + * On systems with cpuset cgroup controller enabled, memory alloc on + * this just hotplugged GPU memory node can fail if the + * cpuset_hotplug_work is not scheduled yet. cpuset_hotplug_work is + * where the current->mems_allowed is updated in the path + * cpuset_hotplug_workfn->update_tasks_nodemask. When cpuset is + * enabled and current->mems_allowed is not updated, memory allocation + * with __GFP_THISNODE and this node id fails. cpuset_wait_for_hotplug + * kernel function can be used to wait for the work to finish but that + * is not exported. Adding a time loop to wait for + * current->mems_allowed to be updated as a WAR while an upstream + * kernel fix is being explored. Bug 4385903 + */ + if (!node_isset(node, cpuset_current_mems_allowed)) + { + unsigned long delay; + + delay = jiffies + (HZ / 10); // 100ms + while(time_before(jiffies, delay) && + !node_isset(node, cpuset_current_mems_allowed)) + { + os_schedule(); + } + + if (!node_isset(node, cpuset_current_mems_allowed)) + { + nv_printf(NV_DBG_ERRORS, "NVRM: Hotplugged GPU memory NUMA node: %d " + "not set in current->mems_allowed!\n", node); + } + } + *nodeId = node; clear_bit(node, nvl->coherent_link_info.free_node_bitmap); NV_ATOMIC_SET(nvl->numa_info.status, NV_IOCTL_NUMA_STATUS_ONLINE); diff --git a/kernel-open/nvidia/os-mlock.c b/kernel-open/nvidia/os-mlock.c index e378245e0e..ebb498bd54 100644 --- a/kernel-open/nvidia/os-mlock.c +++ b/kernel-open/nvidia/os-mlock.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -243,7 +243,7 @@ NV_STATUS NV_API_CALL os_lock_user_pages( nv_mmap_read_lock(mm); ret = NV_PIN_USER_PAGES((unsigned long)address, - page_count, gup_flags, user_pages, NULL); + page_count, gup_flags, user_pages); nv_mmap_read_unlock(mm); pinned = ret; diff --git a/nouveau/extract-firmware-nouveau.py b/nouveau/extract-firmware-nouveau.py index 837edc8de2..a28ef056ae 100755 --- a/nouveau/extract-firmware-nouveau.py +++ b/nouveau/extract-firmware-nouveau.py @@ -286,30 +286,186 @@ def scrubber(gpu, sigsize): # And finally, the actual scrubber image f.write(firmware) +# Extract the GSP-RM firmware from the .run file and copy the binaries +# to the target directory. +def gsp_firmware(filename): + global outputpath + global version + + import subprocess + import tempfile + import shutil + import time + + with tempfile.TemporaryDirectory() as temp: + os.chdir(temp) + + try: + print(f"Extracting {os.path.basename(filename)} to {temp}") + # The -x parameter tells the installer to only extract the + # contents and then exit. + subprocess.run(['/bin/sh', filename, '-x'], shell=False, + check=True, timeout=60, + stdout = subprocess.PIPE, stderr = subprocess.STDOUT) + except subprocess.CalledProcessError as error: + print(error.output.decode()) + sys.exit(error.returncode) + except subprocess.TimeoutExpired as error: + print(error.output.decode()) + sys.exit(error.returncode) + + try: + # The .run file extracts its contents to a directory with the same + # name as the file itself, minus the .run. The GSP-RM firmware + # images are in the 'firmware' subdirectory. + directory = os.path.splitext(os.path.basename(filename))[0] + os.chdir(f"{directory}/firmware") + except: + print("Firmware failed to extract") + sys.exit(1) + + if not os.path.exists('gsp_tu10x.bin') or not os.path.exists('gsp_ga10x.bin'): + print("Firmware files are missing") + sys.exit(1) + + shutil.copyfile('gsp_tu10x.bin', f"{outputpath}/nvidia/tu102/gsp/gsp-{version}.bin") + print(f"Copied gsp_tu10x.bin to tu102/gsp/gsp-{version}.bin") + shutil.copyfile('gsp_ga10x.bin', f"{outputpath}/nvidia/ga102/gsp/gsp-{version}.bin") + print(f"Copied gsp_ga10x.bin to ga102/gsp/gsp-{version}.bin") + +# Create a symlink, deleting the existing file/link if necessary +def symlink(src, dst, target_is_directory = False): + import errno + + try: + os.symlink(src, dst, target_is_directory = target_is_directory) + except OSError as e: + if e.errno == errno.EEXIST: + os.remove(dst) + os.symlink(src, dst, target_is_directory = target_is_directory) + else: + raise e + +# Create symlinks in the target directory for the other GPUs. This mirrors +# what the WHENCE file in linux-firmware does. +def symlinks(): + global outputpath + global version + + print(f"Creating symlinks in {outputpath}/nvidia") + os.chdir(f"{outputpath}/nvidia") + + for d in ['tu104', 'tu106', 'tu117']: + os.makedirs(d, exist_ok = True) + symlink('../tu102/gsp', f"{d}/gsp", target_is_directory = True) + + for d in ['ad103', 'ad104', 'ad106', 'ad107']: + os.makedirs(d, exist_ok = True) + symlink('../ad102/gsp', f"{d}/gsp", target_is_directory = True) + + for d in ['ga103', 'ga104', 'ga106', 'ga107']: + os.makedirs(d, exist_ok = True) + symlink('../ga102/gsp', f"{d}/gsp", target_is_directory = True) + + symlink(f"../../tu102/gsp/bootloader-{version}.bin", f"tu116/gsp/bootloader-{version}.bin") + + symlink(f"../../tu102/gsp/gsp-{version}.bin", f"tu116/gsp/gsp-{version}.bin") + symlink(f"../../tu102/gsp/gsp-{version}.bin", f"ga100/gsp/gsp-{version}.bin") + symlink(f"../../ga102/gsp/gsp-{version}.bin", f"ad102/gsp/gsp-{version}.bin") + +# Create a text file that can be inserted as-is to the WHENCE file of the +# linux-firmware git repository. +def whence(): + global outputpath + global version + + whence = f""" +File: nvidia/tu102/gsp/bootloader-{version}.bin +File: nvidia/tu102/gsp/booter_load-{version}.bin +File: nvidia/tu102/gsp/booter_unload-{version}.bin +Link: nvidia/tu104/gsp -> ../tu102/gsp +Link: nvidia/tu106/gsp -> ../tu102/gsp + +File: nvidia/tu116/gsp/booter_load-{version}.bin +File: nvidia/tu116/gsp/booter_unload-{version}.bin +Link: nvidia/tu116/gsp/bootloader-{version}.bin -> ../../tu102/gsp/bootloader-{version}.bin +Link: nvidia/tu117/gsp -> ../tu116/gsp + +File: nvidia/ga100/gsp/bootloader-{version}.bin +File: nvidia/ga100/gsp/booter_load-{version}.bin +File: nvidia/ga100/gsp/booter_unload-{version}.bin + +File: nvidia/ad102/gsp/bootloader-{version}.bin +File: nvidia/ad102/gsp/booter_load-{version}.bin +File: nvidia/ad102/gsp/booter_unload-{version}.bin +Link: nvidia/ad103/gsp -> ../ad102/gsp +Link: nvidia/ad104/gsp -> ../ad102/gsp +Link: nvidia/ad106/gsp -> ../ad102/gsp +Link: nvidia/ad107/gsp -> ../ad102/gsp + +File: nvidia/ga102/gsp/bootloader-{version}.bin +File: nvidia/ga102/gsp/booter_load-{version}.bin +File: nvidia/ga102/gsp/booter_unload-{version}.bin +Link: nvidia/ga103/gsp -> ../ga102/gsp +Link: nvidia/ga104/gsp -> ../ga102/gsp +Link: nvidia/ga106/gsp -> ../ga102/gsp +Link: nvidia/ga107/gsp -> ../ga102/gsp + +File: nvidia/tu102/gsp/gsp-{version}.bin +Origin: gsp_tu10x.bin from NVIDIA-Linux-x86_64-{version}.run +Link: nvidia/tu116/gsp/gsp-{version}.bin -> ../../tu102/gsp/gsp-{version}.bin +Link: nvidia/ga100/gsp/gsp-{version}.bin -> ../../tu102/gsp/gsp-{version}.bin + +File: nvidia/ga102/gsp/gsp-{version}.bin +Origin: gsp_ga10x.bin from NVIDIA-Linux-x86_64-{version}.run +Link: nvidia/ad102/gsp/gsp-{version}.bin -> ../../ga102/gsp/gsp-{version}.bin +""" + + with open(f"{outputpath}/WHENCE.txt", 'w') as f: + f.writelines(whence) + + print(f"Created {outputpath}/WHENCE.txt") + def main(): global outputpath global version parser = argparse.ArgumentParser( description = 'Extract firmware binaries from the OpenRM git repository' - ' in a format expected by the Nouveau device driver.') + ' in a format expected by the Nouveau device driver.', + epilog = 'Running as root and specifying -o /lib/firmware will install' + ' the firmware files directly where Nouveau expects them.' + ' The --revision option is useful for testing new firmware' + ' versions without changing Nouveau source code.' + ' The --driver option lets you specify the path to the .run file,' + ' and this script also will extract and copy the GSP-RM firmware images.') parser.add_argument('-i', '--input', default = os.getcwd(), help = 'Path to source directory (where version.mk exists)') parser.add_argument('-o', '--output', default = os.path.abspath(os.getcwd() + '/_out'), help = 'Path to target directory (where files will be written)') + parser.add_argument('-r', '--revision', + help = 'Files will be named with this version number') + parser.add_argument('-d', '--driver', + help = 'Path to Nvidia driver .run package, for also extracting the GSP-RM firmware') + parser.add_argument('-s', '--symlink', action='store_true', + help = 'Also create symlinks for all supported GPUs') + parser.add_argument('-w', '--whence', action='store_true', + help = 'Also generate a WHENCE file') args = parser.parse_args() os.chdir(args.input) - with open("version.mk") as f: - version = re.search(r'^NVIDIA_VERSION = ([^\s]+)', f.read(), re.MULTILINE).group(1) - print(f"Generating files for version {version}") + if args.driver: + if not os.path.exists(args.driver): + print(f"File {args.driver} does not exist.") + sys.exit(1) + + version = args.revision + if not version: + with open("version.mk") as f: + version = re.search(r'^NVIDIA_VERSION = ([^\s]+)', f.read(), re.MULTILINE).group(1) - # Normal version strings are of the format xxx.yy.zz, which are all - # numbers. If it's a normal version string, convert it to a single number, - # as Nouveau currently expects. Otherwise, leave it alone. - if set(version) <= set('0123456789.'): - version = version.replace(".", "") + print(f"Generating files for version {version}") outputpath = args.output; print(f"Writing files to {outputpath}") @@ -337,6 +493,15 @@ def main(): bootloader("ad102", "_prod_") # scrubber("ad102", 384) # Not currently used by Nouveau + if args.driver: + gsp_firmware(os.path.abspath(args.driver)) + + if args.symlink: + symlinks() + + if args.whence: + whence() + if __name__ == "__main__": main() diff --git a/src/common/displayport/inc/dp_configcaps.h b/src/common/displayport/inc/dp_configcaps.h index 17ddf03f0b..cdf0a7ab53 100644 --- a/src/common/displayport/inc/dp_configcaps.h +++ b/src/common/displayport/inc/dp_configcaps.h @@ -229,15 +229,15 @@ namespace DisplayPort // Physical layer feature set // virtual NvU64 getMaxLinkRate() = 0; // Maximum byte-block in Hz - virtual unsigned getMaxLaneCount() = 0; // DPCD offset 2 + virtual unsigned getMaxLaneCount() = 0; // DPCD offset 0x0002h virtual unsigned getMaxLaneCountSupportedAtLinkRate(LinkRate linkRate) = 0; virtual bool getEnhancedFraming() = 0; virtual bool getSupportsNoHandshakeTraining() = 0; virtual bool getMsaTimingparIgnored() = 0; - virtual bool getDownstreamPort(NvU8 *portType) = 0; // DPCD offset 5 - virtual bool getSupportsMultistream() = 0; // DPCD offset 21h - virtual bool getNoLinkTraining() = 0; // DPCD offset 330h - virtual unsigned getPhyRepeaterCount() = 0; // DPCD offset F0002h + virtual bool getDownstreamPort(NvU8 *portType) = 0; // DPCD offset 0x0005h + virtual bool getSupportsMultistream() = 0; // DPCD offset 0x0021h + virtual bool getNoLinkTraining() = 0; // DPCD offset 0x0330h + virtual unsigned getPhyRepeaterCount() = 0; // DPCD offset 0xF0002h }; class OUI @@ -306,7 +306,7 @@ namespace DisplayPort virtual bool getSDPExtnForColorimetry() = 0; virtual bool getRootAsyncSDPSupported() = 0; - bool isAtLeastVersion(unsigned major, unsigned minor) + bool isAtLeastVersion(unsigned major, unsigned minor) { if (getRevisionMajor() > major) return true; @@ -317,7 +317,7 @@ namespace DisplayPort return getRevisionMinor() >= minor; } - bool isVersion(unsigned major, unsigned minor) + bool isVersion(unsigned major, unsigned minor) { if ((getRevisionMajor() == major) && (getRevisionMinor() == minor)) @@ -326,7 +326,7 @@ namespace DisplayPort return false; } - bool lttprIsAtLeastVersion(unsigned major, unsigned minor) + bool lttprIsAtLeastVersion(unsigned major, unsigned minor) { if (lttprGetRevisionMajor() > major) return true; @@ -337,7 +337,7 @@ namespace DisplayPort return lttprGetRevisionMinor() >= minor; } - bool lttprIsVersion(unsigned major, unsigned minor) + bool lttprIsVersion(unsigned major, unsigned minor) { if ((lttprGetRevisionMajor() == major) && (lttprGetRevisionMinor() == minor)) diff --git a/src/common/displayport/inc/dp_connector.h b/src/common/displayport/inc/dp_connector.h index d26eee763c..b9388d215b 100644 --- a/src/common/displayport/inc/dp_connector.h +++ b/src/common/displayport/inc/dp_connector.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,7 +48,10 @@ namespace DisplayPort { class EvoInterface; - + +#define SET_DP_IMP_ERROR(pErrorCode, errorCode) \ + if (pErrorCode && *pErrorCode == DP_IMP_ERROR_NONE) *pErrorCode = errorCode; + typedef enum { DP_IMP_ERROR_NONE, @@ -497,8 +500,8 @@ namespace DisplayPort virtual bool compoundQueryAttach(Group * target, const DpModesetParams &modesetParams, // Modeset info - DscParams *pDscParams, // DSC parameters - DP_IMP_ERROR *errorStatus = NULL) = 0; // Error Status code + DscParams *pDscParams, // DSC parameters + DP_IMP_ERROR *errorStatus = NULL) = 0; // Error Status code virtual bool endCompoundQuery() = 0; @@ -729,7 +732,7 @@ namespace DisplayPort virtual bool readPsrErrorStatus(vesaPsrErrorStatus *psrErr) = 0; virtual bool writePsrEvtIndicator(vesaPsrEventIndicator psrErr) = 0; virtual bool readPsrEvtIndicator(vesaPsrEventIndicator *psrErr) = 0; - virtual bool updatePsrLinkState(bool bTrainLink) = 0; + virtual bool updatePsrLinkState(bool bTurnOnLink) = 0; virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0; diff --git a/src/common/displayport/inc/dp_connectorimpl.h b/src/common/displayport/inc/dp_connectorimpl.h index 263ff4d967..f62ff826cd 100644 --- a/src/common/displayport/inc/dp_connectorimpl.h +++ b/src/common/displayport/inc/dp_connectorimpl.h @@ -194,7 +194,9 @@ namespace DisplayPort unsigned compoundQueryLocalLinkPBN; bool compoundQueryForceEnableFEC; - unsigned freeSlots, maximumSlots; + unsigned freeSlots; + unsigned maximumSlots; + int firstFreeSlot; // Multistream messaging MessageManager * messageManager; @@ -346,12 +348,22 @@ namespace DisplayPort // bool bPowerDownPhyBeforeD3; + // + // Reset the MSTM_CTRL registers on branch device irrespective of + // IRQ VECTOR register having stale message. Certain branch devices + // need to reset the topology before issuing new discovery commands + // as there can be case where previous is still in process and a + // possibility that clearPendingMessage() might not be able to catch + // the stale messages from previous discovery. + // + bool bForceClearPendingMsg; + + Group *perHeadAttachedGroup[NV_MAX_HEADS]; NvU32 inTransitionHeadMask; void sharedInit(); ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink); - void setPolicyModesetOrderMitigation(bool enabled); void setPolicyForceLTAtNAB(bool enabled); void setPolicyAssessLinkSafely(bool enabled); @@ -599,6 +611,8 @@ namespace DisplayPort bool beforeAddStreamMST(GroupImpl * group, bool force = false, bool forFlushMode = false); + virtual bool checkIsModePossibleMST(GroupImpl * group); + bool deleteAllVirtualChannels(); void clearTimeslices(); bool allocateTimeslice(GroupImpl * targetGroup); @@ -664,7 +678,7 @@ namespace DisplayPort virtual bool writePsrEvtIndicator(vesaPsrEventIndicator psrErr); virtual bool readPsrEvtIndicator(vesaPsrEventIndicator *psrErr); virtual bool readPsrState(vesaPsrState *psrState); - virtual bool updatePsrLinkState(bool bTrainLink); + virtual bool updatePsrLinkState(bool bTurnOnLink); virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo); diff --git a/src/common/displayport/inc/dp_deviceimpl.h b/src/common/displayport/inc/dp_deviceimpl.h index c9964b9337..b3041062f5 100644 --- a/src/common/displayport/inc/dp_deviceimpl.h +++ b/src/common/displayport/inc/dp_deviceimpl.h @@ -449,6 +449,8 @@ namespace DisplayPort NvBool getDSCSupport(); bool getFECSupport(); NvBool isDSCPassThroughSupported(); + NvBool isDynamicPPSSupported(); + NvBool isDynamicDscToggleSupported(); NvBool isDSCSupported(); NvBool isDSCDecompressionSupported(); NvBool isDSCPossible(); diff --git a/src/common/displayport/inc/dp_evoadapter.h b/src/common/displayport/inc/dp_evoadapter.h index 478a2758c4..b91b47091d 100644 --- a/src/common/displayport/inc/dp_evoadapter.h +++ b/src/common/displayport/inc/dp_evoadapter.h @@ -39,6 +39,8 @@ #include "dp_regkeydatabase.h" #include +#include +#include #define HDCP_DUMMY_CN (0x1) #define HDCP_DUMMY_CKSV (0xFFFFF) @@ -131,10 +133,7 @@ namespace DisplayPort class EvoMainLink : public MainLink { - EvoInterface * provider; - Timer * timer; - NvU32 displayId; - NvU32 subdeviceIndex; + private: NvU32 _maxLinkRateSupportedGpu; NvU32 _maxLinkRateSupportedDfp; unsigned allHeadMask; @@ -160,6 +159,7 @@ namespace DisplayPort bool _enableMSAOverrideOverMST; bool _isLTPhyRepeaterSupported; + bool _isMSTPCONCapsReadDisabled; // // LTTPR count reported by RM, it might not be the same with DPLib probe // For example, some Intel LTTPR might not be ready to response 0xF0000 probe @@ -178,11 +178,19 @@ namespace DisplayPort unsigned maxNumHztSlices; unsigned lineBufferBitDepth; }_DSC; - - private: void initializeRegkeyDatabase(); void applyRegkeyOverrides(); + protected: + EvoInterface * provider; + Timer * timer; + + NvU32 displayId; + NvU32 subdeviceIndex; + + NV0073_CTRL_DFP_GET_INFO_PARAMS dfpParams; + NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS dpParams; + public: EvoMainLink(EvoInterface * provider, Timer * timer); @@ -379,8 +387,8 @@ namespace DisplayPort bool isActive(); bool isEDP(); bool skipPowerdownEdpPanelWhenHeadDetach(); + bool isMSTPCONCapsReadDisabled(); bool supportMSAOverMST(); - bool queryAndUpdateDfpParams(); bool controlRateGoverning(NvU32 head, bool enable, bool updateNow); bool getDpTestPattern(NV0073_CTRL_DP_TESTPATTERN *testPattern); @@ -393,14 +401,15 @@ namespace DisplayPort NvU32 monitorDenylistInfo(NvU32 ManufacturerID, NvU32 ProductID, DpMonitorDenylistData *pDenylistData); NvU32 allocDisplayId(); bool freeDisplayId(NvU32 displayId); - void queryGPUCapability(); + virtual bool queryAndUpdateDfpParams(); + virtual bool queryGPUCapability(); bool getEdpPowerData(bool *panelPowerOn, bool *dpcdPowerStateD0); virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status); void configureTriggerSelect(NvU32 head, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID streamIdentifier = DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY); void configureTriggerAll(NvU32 head, bool enable); - bool configureLinkRateTable(const NvU16 *pLinkRateTable, LinkRates *pLinkRates); + virtual bool configureLinkRateTable(const NvU16 *pLinkRateTable, LinkRates *pLinkRates); bool configureFec(const bool bEnableFec); }; diff --git a/src/common/displayport/inc/dp_linkconfig.h b/src/common/displayport/inc/dp_linkconfig.h index 221294b6cc..4d741d4d5f 100644 --- a/src/common/displayport/inc/dp_linkconfig.h +++ b/src/common/displayport/inc/dp_linkconfig.h @@ -242,7 +242,6 @@ namespace DisplayPort bool disablePostLTRequest; bool bEnableFEC; bool bDisableLTTPR; - // // The counter to record how many times link training happens. // Client can reset the counter by calling setLTCounter(0) @@ -252,7 +251,8 @@ namespace DisplayPort LinkConfiguration() : lanes(0), peakRatePossible(0), peakRate(0), minRate(0), enhancedFraming(false), multistream(false), disablePostLTRequest(false), - bEnableFEC(false), bDisableLTTPR(false), linkTrainCounter(0) {}; + bEnableFEC(false), bDisableLTTPR(false), + linkTrainCounter(0) {}; LinkConfiguration(LinkPolicy * p, unsigned lanes, LinkRate peakRate, bool enhancedFraming, bool MST, bool disablePostLTRequest = false, @@ -316,42 +316,113 @@ namespace DisplayPort bDisableLTTPR(false), linkTrainCounter(0) { + // // Reverse engineer a link configuration from Total TotalLinkPBN // Note that HBR2 twice HBR. The table below treats HBR2x1 and HBRx2, etc. - // - // BW Effective Lanes Total TotalLinkPBN - // 165 1 195.5555556 - // 165 2 391.1111111 - // 165 4 782.2222222 - // 270 1 320 - // 270 2 640 - // 270 4 1280 - // 270 8 2560 + // PBN Calculation + // Definition of PBN is "54/64 MBps". + // Note this is the "data" actually transmitted in the main link. + // So we need to take channel coding into consideration. + // Formula: PBN = Lane Count * Link Rate (Gbps) * 1000 * (1/8) * ChannelCoding Efficiency * (64 / 54) + // Example: + // 1. 4 * HBR2: 4 * 5.4 * 1000 * (1/8) * (8/10) * (64/54) = 2560 + // 2. 2 * UHBR10: 2 * 10 * 1000 * (1/8) * (128/132) * (64/54) = 2873 + // + // Full list: + // + // BW (Gbps) Lanes TotalLinkPBN + // 1.62 1 192 + // 1.62 2 384 + // 1.62 4 768 + // 2.70 1 320 + // 2.70 2 640 + // 2.70 4 1280 + // 5.40 1 640 + // 5.40 2 1280 + // 5.40 4 2560 + // 8.10 1 960 + // 8.10 2 1920 + // 8.10 4 3840 + // 10.00 1 1436 + // 10.00 2 2873 + // 10.00 4 5746 + // 13.50 1 1939 + // 13.50 2 3878 + // 13.50 4 7757 + // 20.00 1 2873 + // 20.00 2 5746 + // 20.00 4 11492 // if (TotalLinkPBN <= 90) - peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes=0; // FAIL - if (TotalLinkPBN <= 195) - peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes=1; + { + peakRatePossible = peakRate = RBR; + minRate = linkOverhead(RBR); + lanes = 0; // FAIL + } + if (TotalLinkPBN <= 192) + { + peakRatePossible = peakRate = RBR; + minRate = linkOverhead(RBR); + lanes = 1; + } else if (TotalLinkPBN <= 320) - peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 1; - else if (TotalLinkPBN <= 391) - peakRatePossible = peakRate = RBR, minRate=linkOverhead(RBR), lanes = 2; + { + peakRatePossible = peakRate = HBR; + minRate = linkOverhead(HBR); + lanes = 1; + } + else if (TotalLinkPBN <= 384) + { + peakRatePossible = peakRate = RBR; + minRate = linkOverhead(RBR); + lanes = 2; + } else if (TotalLinkPBN <= 640) - peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 2; // could be HBR2x1, but TotalLinkPBN works out same - else if (TotalLinkPBN <= 782) - peakRatePossible = peakRate = RBR, minRate=linkOverhead(RBR), lanes = 4; + { + // could be HBR2 x 1, but TotalLinkPBN works out same + peakRatePossible = peakRate = HBR; + minRate = linkOverhead(HBR); + lanes = 2; + } + else if (TotalLinkPBN <= 768) + { + peakRatePossible = peakRate = RBR; + minRate = linkOverhead(RBR); + lanes = 4; + } else if (TotalLinkPBN <= 960) - peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 1; + { + peakRatePossible = peakRate = HBR3; + minRate = linkOverhead(HBR3); + lanes = 1; + } else if (TotalLinkPBN <= 1280) - peakRatePossible = peakRate = HBR, minRate=linkOverhead(HBR), lanes = 4; // could be HBR2x2 + { + // could be HBR2 x 2 + peakRatePossible = peakRate = HBR; + minRate = linkOverhead(HBR); + lanes = 4; + } else if (TotalLinkPBN <= 1920) - peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 2; // could be HBR2x + { + peakRatePossible = peakRate = HBR3; + minRate = linkOverhead(HBR3); + lanes = 2; + } else if (TotalLinkPBN <= 2560) - peakRatePossible = peakRate = HBR2, minRate=linkOverhead(HBR2), lanes = 4; + { + peakRatePossible = peakRate = HBR2; + minRate = linkOverhead(HBR2); + lanes = 4; + } else if (TotalLinkPBN <= 3840) - peakRatePossible = peakRate = HBR3, minRate=linkOverhead(HBR3), lanes = 4; + { + peakRatePossible = peakRate = HBR3; + minRate = linkOverhead(HBR3); + lanes = 4; + } else { peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes = 0; // FAIL DP_ASSERT(0 && "Unknown configuration"); @@ -412,7 +483,6 @@ namespace DisplayPort } minRate = linkOverhead(peakRate); - return lanes != laneCount_0; } diff --git a/src/common/displayport/inc/dp_mainlink.h b/src/common/displayport/inc/dp_mainlink.h index b3d44a9061..0db0809834 100644 --- a/src/common/displayport/inc/dp_mainlink.h +++ b/src/common/displayport/inc/dp_mainlink.h @@ -144,6 +144,9 @@ namespace DisplayPort // Check if we should skip power down eDP when head detached. virtual bool skipPowerdownEdpPanelWhenHeadDetach() = 0; + // Check if we should skip reading PCON Caps in MST case. + virtual bool isMSTPCONCapsReadDisabled() = 0; + // Get GPU DSC capabilities virtual void getDscCaps(bool *pbDscSupported = NULL, unsigned *pEncoderColorFormatMask = NULL, @@ -242,7 +245,7 @@ namespace DisplayPort virtual NvU32 getRootDisplayId() = 0; virtual NvU32 allocDisplayId() = 0; virtual bool freeDisplayId(NvU32 displayId) = 0; - virtual void queryGPUCapability() = 0; + virtual bool queryGPUCapability() {return false;} virtual bool queryAndUpdateDfpParams() = 0; virtual bool getEdpPowerData(bool *panelPowerOn, bool *bDPCDPowerStateD0) = 0; virtual bool vrrRunEnablementStage(unsigned stage, NvU32 *status) = 0; diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h index 3d36761b20..e79f783a02 100644 --- a/src/common/displayport/inc/dp_regkeydatabase.h +++ b/src/common/displayport/inc/dp_regkeydatabase.h @@ -63,7 +63,7 @@ #define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY" // -// Regkey to re-assess max link if the first assessed link config +// Regkey to re-assess max link if the first assessed link config // is lower than the panel max // #define NV_DP_REGKEY_REASSESS_MAX_LINK "DP_REASSESS_MAX_LINK" @@ -74,6 +74,11 @@ // #define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315" +// +// Bug 4388987 : This regkey will disable reading PCON caps for MST. +// +#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR" + // // Data Base used to store all the regkey values. // The actual data base is declared statically in dp_evoadapter.cpp. @@ -107,6 +112,7 @@ struct DP_REGKEY_DATABASE bool bDscMstCapBug3143315; bool bPowerDownPhyBeforeD3; bool bReassessMaxLink; + bool bMSTPCONCapsReadDisabled; }; #endif //INCLUDED_DP_REGKEYDATABASE_H diff --git a/src/common/displayport/inc/dp_timer.h b/src/common/displayport/inc/dp_timer.h index bf8c3f6177..bc27da9295 100644 --- a/src/common/displayport/inc/dp_timer.h +++ b/src/common/displayport/inc/dp_timer.h @@ -65,7 +65,6 @@ namespace DisplayPort private: RawTimer * raw; - NvU64 nextTimestamp; List pending; struct PendingCallback : ListElement { diff --git a/src/common/displayport/inc/dp_watermark.h b/src/common/displayport/inc/dp_watermark.h index 4e1d3865e2..7cf8a30e7b 100644 --- a/src/common/displayport/inc/dp_watermark.h +++ b/src/common/displayport/inc/dp_watermark.h @@ -38,13 +38,13 @@ namespace DisplayPort { class LinkConfiguration; - struct ModesetInfo + struct ModesetInfo { unsigned twoChannelAudioHz; // if you need 192khz stereo specify 192000 here unsigned eightChannelAudioHz; // Same setting for multi channel audio. // DisplayPort encodes 3-8 channel streams as 8 channel NvU64 pixelClockHz; // Requested pixel clock for the mode - unsigned rasterWidth; + unsigned rasterWidth; unsigned rasterHeight; unsigned surfaceWidth; // RasterBlankStartX - newRasterBlankEndX unsigned surfaceHeight; // Active region height @@ -56,35 +56,35 @@ namespace DisplayPort DSC_MODE mode; // DSC Mode bool bEnablePassThroughForPCON; - ModesetInfo(): twoChannelAudioHz(0), - eightChannelAudioHz(0), - pixelClockHz(0), - rasterWidth(0), - rasterHeight(0), - surfaceWidth(0), + ModesetInfo(): twoChannelAudioHz(0), + eightChannelAudioHz(0), + pixelClockHz(0), + rasterWidth(0), + rasterHeight(0), + surfaceWidth(0), surfaceHeight(0), depth(0), - rasterBlankStartX(0), + rasterBlankStartX(0), rasterBlankEndX(0), bitsPerComponent(0), bEnableDsc(false), mode(DSC_SINGLE), bEnablePassThroughForPCON(false) {} - - ModesetInfo(unsigned newTwoChannelAudioHz, unsigned newEightChannelAudioHz, NvU64 newPixelClockHz, - unsigned newRasterWidth, unsigned newRasterHeight, + + ModesetInfo(unsigned newTwoChannelAudioHz, unsigned newEightChannelAudioHz, NvU64 newPixelClockHz, + unsigned newRasterWidth, unsigned newRasterHeight, unsigned newSurfaceWidth, unsigned newSurfaceHeight, unsigned newDepth, unsigned newRasterBlankStartX=0, unsigned newRasterBlankEndX=0, bool newBEnableDsc = false, DSC_MODE newMode = DSC_SINGLE, bool newBEnablePassThroughForPCON = false): - twoChannelAudioHz(newTwoChannelAudioHz), - eightChannelAudioHz(newEightChannelAudioHz), - pixelClockHz(newPixelClockHz), - rasterWidth(newRasterWidth), + twoChannelAudioHz(newTwoChannelAudioHz), + eightChannelAudioHz(newEightChannelAudioHz), + pixelClockHz(newPixelClockHz), + rasterWidth(newRasterWidth), rasterHeight(newRasterHeight), surfaceWidth(newSurfaceWidth), surfaceHeight(newSurfaceHeight), depth(newDepth), - rasterBlankStartX(newRasterBlankStartX), + rasterBlankStartX(newRasterBlankStartX), rasterBlankEndX(newRasterBlankEndX), bitsPerComponent(0), bEnableDsc(newBEnableDsc), @@ -98,6 +98,7 @@ namespace DisplayPort unsigned tuSize; unsigned hBlankSym; unsigned vBlankSym; + NvU32 effectiveBpp; }; bool isModePossibleSST @@ -130,6 +131,13 @@ namespace DisplayPort Watermark * dpInfo ); + bool dp2xIsModePossibleMSTWithFEC + ( + const LinkConfiguration & linkConfig, + const ModesetInfo & modesetInfo, + Watermark * dpInfo + ); + // Return Payload Bandwidth Number(PBN)for requested mode unsigned pbnForMode(const ModesetInfo & modesetInfo); } diff --git a/src/common/displayport/src/dp_configcaps.cpp b/src/common/displayport/src/dp_configcaps.cpp index a302a89d87..125b9c20ce 100644 --- a/src/common/displayport/src/dp_configcaps.cpp +++ b/src/common/displayport/src/dp_configcaps.cpp @@ -115,6 +115,8 @@ struct DPCDHALImpl : DPCDHAL // DPCD Offset 0119h [0] - If we grant the extendedSleepWakeTimeoutRequest bool bExtendedSleepWakeTimeoutGranted; + bool bFECSupported; + // DPCD Offset F0002h - Number of Physical Repeaters present (after mapping) between Source and Sink unsigned phyRepeaterCount; // DPCD offset 700 - EDP_DPCD_REV @@ -126,6 +128,10 @@ struct DPCDHALImpl : DPCDHAL LinkRate maxLinkRate; // DPCD offset F0001h unsigned maxLaneCount; // DPCD offset F0004h unsigned phyRepeaterExtendedWakeTimeoutMs; // DPCD offset F0005h + // The array to keep track of FEC capability of each LTTPR + bool bFECSupportedRepeater[NV_DPCD14_PHY_REPEATER_CNT_MAX]; + // If all the LTTPRs supports FEC + bool bFECSupported; } repeaterCaps; PCONCaps pconCaps; @@ -280,6 +286,11 @@ struct DPCDHALImpl : DPCDHAL NvU8 byte = 0; AuxRetry::status status; unsigned retries = 16; + + NvU8 lttprIdx = 0; + + caps.phyRepeaterCount = 0; + // Burst read from 0x00 to 0x0F. // @@ -530,6 +541,24 @@ struct DPCDHALImpl : DPCDHAL _PHY_REPEATER_EXTENDED_WAKE_TIMEOUT, _REQ, buffer[0x5]) * 10; + for (lttprIdx = 0; lttprIdx < caps.phyRepeaterCount; lttprIdx++) + { + caps.repeaterCaps.bFECSupported = true; + if (AuxRetry::ack == + bus.read(NV_DPCD14_PHY_REPEATER_FEC_CAP_0(lttprIdx), &byte, 1)) + { + caps.repeaterCaps.bFECSupportedRepeater[lttprIdx] = + FLD_TEST_DRF(_DPCD14, + _PHY_REPEATER_FEC_CAP_0, + _FEC_CAPABLE, + _YES, + byte); + + // bFECSupported is only true if all LTTPR supports FEC. + caps.repeaterCaps.bFECSupported &= + caps.repeaterCaps.bFECSupportedRepeater[lttprIdx]; + } + } } else { diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index 646765f6c7..042275c1eb 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -48,9 +48,6 @@ #include "ctrl/ctrl0073/ctrl0073dp.h" #include "dp_tracing.h" -#define SET_DP_IMP_ERROR(pErrorCode, errorCode) \ - if (pErrorCode && *pErrorCode == DP_IMP_ERROR_NONE) *pErrorCode = errorCode; - using namespace DisplayPort; ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink) @@ -141,12 +138,12 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co // Set if LTTPR training is supported per regKey hal->setLttprSupported(main->isLttprSupported()); - const DP_REGKEY_DATABASE& dpRegkeyDatabase = main->getRegkeyDatabase(); this->applyRegkeyOverrides(dpRegkeyDatabase); hal->applyRegkeyOverrides(dpRegkeyDatabase); highestAssessedLC = getMaxLinkConfig(); + } void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase) @@ -687,8 +684,11 @@ void ConnectorImpl::processNewDevice(const DiscoveryManager::Device & device, // else if (newDev->parent && (newDev->parent)->isVirtualPeerDevice()) { - newDev->parent->getPCONCaps(&(newDev->pconCaps)); - newDev->connectorType = newDev->parent->getConnectorType(); + if (!main->isMSTPCONCapsReadDisabled()) + { + newDev->parent->getPCONCaps(&(newDev->pconCaps)); + newDev->connectorType = newDev->parent->getConnectorType(); + } } } @@ -890,6 +890,9 @@ void ConnectorImpl::hardwareWasReset() g->setHeadAttached(false); } + + while (!dscEnabledDevices.isEmpty()) + (void) dscEnabledDevices.pop(); } Group * ConnectorImpl::resume(bool firmwareLinkHandsOff, @@ -999,19 +1002,19 @@ LinkConfiguration ConnectorImpl::getMaxLinkConfig() } LinkRate linkRate = maxLinkRate ? - DP_MIN(maxLinkRate, main->maxLinkRateSupported()) : - main->maxLinkRateSupported(); + DP_MIN(maxLinkRate, main->maxLinkRateSupported()) : + main->maxLinkRateSupported(); unsigned laneCount = hal->getMaxLaneCount() ? - DP_MIN(hal->getMaxLaneCountSupportedAtLinkRate(linkRate), hal->getMaxLaneCount()) : - 4; + DP_MIN(hal->getMaxLaneCountSupportedAtLinkRate(linkRate), hal->getMaxLaneCount()) : + 4U; return LinkConfiguration (&this->linkPolicy, - laneCount, linkRate, - this->hal->getEnhancedFraming(), - linkUseMultistream(), - false, /* disablePostLTRequest */ - this->bFECEnable); + laneCount, linkRate, + this->hal->getEnhancedFraming(), + linkUseMultistream(), + false, /* disablePostLTRequest */ + this->bFECEnable); } LinkConfiguration ConnectorImpl::getActiveLinkConfig() @@ -1311,36 +1314,20 @@ bool ConnectorImpl::compoundQueryAttachMSTIsDscPossible { if (dev && dev->isDSCPossible()) { - if (dev->devDoingDscDecompression != dev) + if ((dev->devDoingDscDecompression != dev) || + ((dev->devDoingDscDecompression == dev) && + (dev->isLogical() && dev->parent))) { // - // If DSC decoding is going to happen at sink's parent then - // we have to make sure the path from source to sink's parent - // is fec is capable. + // If DSC decoding is going to happen at sink's parent or + // decoding will be done by sink but sink is a logical port, + // where intermediate link between Branch DFP and Rx Panel can be + // anything other than DP (i.e. DSI, LVDS or something else), + // then we have to only make sure the path from source to sink's + // parent is fec is capable. // Refer DP 1.4 Spec 5.4.5 // - if(dev->address.size() == 2) - { - // - // if there is only one branch between source and sink then branch - // should be directly connected to source (sst-case) and dpcd cap - // should already be available. - // - bFecCapable = dev->parent->isFECSupported(); - } - else - { - // - // If there are multiple branches in the path, we have to check - // fecCapability field in epr reply to sink's parent's parent. - // Epr reply for each branch should already be updated with inferLeafLink. - // fecCapability field being true here means up to sink's parent, - // which is "downstream end of path" for sink's parent's parent, - // is fec capable. - // Refer DP 1.4 Spec 2.11.9.4.1 - // - bFecCapable = dev->parent->parent->isFECSupported(); - } + bFecCapable = dev->parent->isFECSupported(); } else { @@ -1480,27 +1467,59 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target, warData.connectorType = DSC_DP; DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr; - pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); - + pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) + dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, &warData, availableBandwidthBitsPerSecond, - (NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16), - pScratchBuffer); + pScratchBuffer, + (NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16)); - // Try max dsc compression bpp = 8 once to check if that can support that mode. - if (result != NVT_STATUS_SUCCESS && !bDscBppForced) + // + // From NVD 5.0 later, Dplib needs to pass sliceCountMask to clients + // with all slice counts that can support the mode since clients + // might need to use a slice count other than the minimum slice count + // that supports the mode. Currently we keep the same policy of + // trying 10 bpp first and if that does not pass, try 8pp. But later + // with dynamic PPS update, this will be moved a better algorithm, + // that optimizes bpp for requested mode on each display. + // + if (dscInfo.gpuCaps.maxNumHztSlices > 4U) + { + result = DSC_GeneratePPSWithSliceCountMask(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16), + &(pDscParams->sliceCountMask)); + // Try max dsc compression bpp = 8 once to check if that can support that mode. + if (result != NVT_STATUS_SUCCESS && !bDscBppForced) + { + pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16; + bitsPerPixelX16 = pDscParams->bitsPerPixelX16; + result = DSC_GeneratePPSWithSliceCountMask(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16), + &(pDscParams->sliceCountMask)); + } + } + else { - pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16; - - bitsPerPixelX16 = pDscParams->bitsPerPixelX16; - result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, &warData, availableBandwidthBitsPerSecond, - (NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16), - pScratchBuffer); + pScratchBuffer, (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16)); + // Try max dsc compression bpp = 8 once to check if that can support that mode. + if (result != NVT_STATUS_SUCCESS && !bDscBppForced) + { + pDscParams->bitsPerPixelX16 = MAX_DSC_COMPRESSION_BPPX16; + bitsPerPixelX16 = pDscParams->bitsPerPixelX16; + result = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, + &warData, availableBandwidthBitsPerSecond, + pScratchBuffer, (NvU32*)(PPS), + (NvU32*)(&bitsPerPixelX16)); + } } - - if (pScratchBuffer) + if (pScratchBuffer != nullptr) { dpFree(pScratchBuffer); pScratchBuffer = nullptr; @@ -1557,9 +1576,9 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target, // if (dev->pconCaps.maxHdmiLinkBandwidthGbps != 0) { - NvU64 requiredBW = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); - NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * 1000000000); - if (requiredBW > availableBw) + NvU64 requiredBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + NvU64 availableBw = (NvU64)(dev->pconCaps.maxHdmiLinkBandwidthGbps * (NvU64)1000000000U); + if (requiredBw > availableBw) { compoundQueryResult = false; SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_FRL_BANDWIDTH) @@ -1574,10 +1593,10 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target, else if (dev->pconCaps.maxTmdsClkRate != 0) { NvU64 maxTmdsClkRateU64 = (NvU64)(dev->pconCaps.maxTmdsClkRate); - NvU64 requireBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); + NvU64 requiredBw = (NvU64)(modesetParams.modesetInfo.pixelClockHz * modesetParams.modesetInfo.depth); if (modesetParams.colorFormat == dpColorFormat_YCbCr420) { - if (maxTmdsClkRateU64 < ((requireBw/24)/2)) + if (maxTmdsClkRateU64 < ((requiredBw/24)/2)) { compoundQueryResult = false; SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH) @@ -1586,7 +1605,7 @@ bool ConnectorImpl::compoundQueryAttachMSTDsc(Group * target, } else { - if (maxTmdsClkRateU64 < (requireBw/24)) + if (maxTmdsClkRateU64 < (requiredBw/24)) { compoundQueryResult = false; SET_DP_IMP_ERROR(pErrorCode, DP_IMP_ERROR_DSC_PCON_HDMI2_BANDWIDTH) @@ -1829,14 +1848,14 @@ bool ConnectorImpl::compoundQueryAttachSST(Group * target, warData.connectorType = DSC_DP; DSC_GENERATE_PPS_OPAQUE_WORKAREA *pScratchBuffer = nullptr; - pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); - + pScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*) + dpMalloc(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); NVT_STATUS ppsStatus = DSC_GeneratePPS(&dscInfo, &modesetInfoDSC, &warData, availableBandwidthBitsPerSecond, + pScratchBuffer, (NvU32*)(PPS), - (NvU32*)(&bitsPerPixelX16), - pScratchBuffer); - if (pScratchBuffer) + (NvU32*)(&bitsPerPixelX16)); + if (pScratchBuffer != nullptr) { dpFree(pScratchBuffer); pScratchBuffer = nullptr; @@ -2836,24 +2855,17 @@ bool ConnectorImpl::setDeviceDscState(Device * dev, bool bEnableDsc) if (bEnableDsc) { - if (dscEnabledDevices.contains(dev)) - { - DP_LOG(("DP> DSC already enabled on device")); - return true; - } if(!(((DeviceImpl *)dev)->setDscEnable(true /*bEnableDsc*/))) { DP_ASSERT(!"DP-CONN> Failed to configure DSC on Sink!"); return false; } - dscEnabledDevices.insertFront(dev); + + if (!dscEnabledDevices.contains(dev)) + dscEnabledDevices.insertFront(dev); } else { - if (!dscEnabledDevices.contains(dev)) - { - return true; - } bool bCurrDscEnable = false; // Get Current DSC Enable State if (!((DeviceImpl *)dev)->getDscEnable(&bCurrDscEnable)) @@ -2875,13 +2887,16 @@ bool ConnectorImpl::setDeviceDscState(Device * dev, bool bEnableDsc) break; } } + if(bDisableDsc && !((DeviceImpl *)dev)->setDscEnable(false /*bEnableDsc*/)) { DP_ASSERT(!"DP-CONN> Failed to configure DSC on Sink!"); return false; } } - dscEnabledDevices.remove(dev); + + if (dscEnabledDevices.contains(dev)) + dscEnabledDevices.remove(dev); } return true; } @@ -3139,8 +3154,8 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr if (linkUseMultistream()) { // Which pipeline to take the affect out of trigger ACT - if ((DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST != targetImpl->singleHeadMultiStreamMode) || - (DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY == targetImpl->singleHeadMultiStreamID)) + if ((targetImpl->singleHeadMultiStreamMode != DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST) || + (targetImpl->singleHeadMultiStreamID == DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY)) { main->configureTriggerSelect(targetImpl->headIndex, targetImpl->singleHeadMultiStreamID); } @@ -3244,8 +3259,8 @@ void ConnectorImpl::notifyAttachEnd(bool modesetCancelled) // Add rest of the streams (other than primary) in notifyAE, since this can't be done // unless a SOR is attached to a Head (part of modeset), and trigger ACT immediate // - if ((DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST == currentModesetDeviceGroup->singleHeadMultiStreamMode) && - (currentModesetDeviceGroup->singleHeadMultiStreamID > DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY)) + if ((currentModesetDeviceGroup->singleHeadMultiStreamMode == DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST) && + (currentModesetDeviceGroup->singleHeadMultiStreamID > DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY)) { DP_ASSERT(linkUseMultistream() && "it should be multistream link to configure single head MST"); hal->payloadTableClearACT(); @@ -3307,13 +3322,13 @@ void ConnectorImpl::notifyDetachBegin(Group * target) // Set the trigger select so as to which frontend corresponding to the stream // to take the affect // - if(linkUseMultistream()) + if (linkUseMultistream()) { main->configureTriggerSelect(group->headIndex, group->singleHeadMultiStreamID); // Clear payload of other than primary streams and trigger ACT immediate - if ((DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST == group->singleHeadMultiStreamMode) && - (DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY != group->singleHeadMultiStreamID)) + if ((group->singleHeadMultiStreamMode == DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST) && + (group->singleHeadMultiStreamID != DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY)) { main->triggerACT(); if (!hal->payloadWaitForACTReceived()) @@ -4162,7 +4177,7 @@ bool ConnectorImpl::handleCPIRQ() if (pGroupAttached && (pGroupAttached->singleHeadMultiStreamMode == DP_SINGLE_HEAD_MULTI_STREAM_MODE_SST) && - (pGroupAttached->singleHeadMultiStreamID == DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_SECONDARY)) + (pGroupAttached->singleHeadMultiStreamID == DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_SECONDARY)) { DP_ASSERT(this->pCoupledConnector); sstPrim = this->pCoupledConnector; @@ -5063,20 +5078,17 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, LinkTrainingType trainType) { LinkTrainingType preferredTrainingType = trainType; - bool result; + bool result = true; - // // Validate link config against caps - // - if (!force) + if (!force && !validateLinkConfiguration(lConfig)) { - if (!validateLinkConfiguration(lConfig)) - return false; + return false; } if (!lConfig.multistream) { - for (Device * i = enumDevices(0); i; i=enumDevices(i)) + for (Device * i = enumDevices(0); i; i=enumDevices(i)) { DeviceImpl * dev = (DeviceImpl *)i; if (dev->powerOnMonitorBeforeLt() && lConfig.lanes != 0) @@ -5100,7 +5112,6 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, else if (hal->getSupportsNoHandshakeTraining()) preferredTrainingType = FAST_LINK_TRAINING; } - } // @@ -5145,7 +5156,15 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, if (!result) activeLinkConfig.lanes = 0; else + { + if (activeLinkConfig.multistream) + { + // Total slot is 64, reserve slot 0 for header + maximumSlots = 63; + firstFreeSlot = 1; + } bNoLtDoneAfterHeadDetach = false; + } if (!force && result) this->hal->setDirtyLinkStatus(true); @@ -5184,6 +5203,13 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force, // fallback happens, returns fail to make sure clients notice it. result = false; } + + if (result) + { + // update PSR link cache on successful LT + this->psrLinkConfig = activeLinkConfig; + } + return result; } @@ -5414,11 +5440,8 @@ void ConnectorImpl::freeTimeslice(GroupImpl * targetGroup) targetGroup->timeslot.hardwareDirty = true; } -bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup) +bool ConnectorImpl::checkIsModePossibleMST(GroupImpl *targetGroup) { - unsigned base_pbn, slot_count, slots_pbn; - - DP_ASSERT(isLinkActive()); if (this->isFECSupported()) { if (!isModePossibleMSTWithFEC(activeLinkConfig, @@ -5426,7 +5449,7 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup) &targetGroup->timeslot.watermarks)) { DP_ASSERT(0 && "DisplayDriver bug! This mode is not possible at any " - "link configuration. It would have been reject at mode filtering time!"); + "link configuration. It should have been rejected at mode filtering time!"); return false; } } @@ -5437,10 +5460,22 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup) &targetGroup->timeslot.watermarks)) { DP_ASSERT(0 && "DisplayDriver bug! This mode is not possible at any " - "link configuration. It would have been reject at mode filtering time!"); + "link configuration. It should have been rejected at mode filtering time!"); return false; } } + return true; +} + +bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup) +{ + unsigned base_pbn, slot_count, slots_pbn; + int firstSlot = firstFreeSlot; + + DP_ASSERT(isLinkActive()); + + if (!checkIsModePossibleMST(targetGroup)) + return false; activeLinkConfig.pbnRequired(targetGroup->lastModesetInfo, base_pbn, slot_count, slots_pbn); @@ -5448,16 +5483,14 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup) if (slot_count > freeSlots) return false; - int firstFreeSlot = 1; - for (ListElement * i = activeGroups.begin(); i != activeGroups.end(); i = i->next) { GroupImpl * group = (GroupImpl *)i; if (group->timeslot.count != 0 && - (group->timeslot.begin + group->timeslot.count) >= firstFreeSlot) + (group->timeslot.begin + group->timeslot.count) >= firstSlot) { - firstFreeSlot = group->timeslot.begin + group->timeslot.count; + firstSlot = group->timeslot.begin + group->timeslot.count; } } @@ -5467,7 +5500,7 @@ bool ConnectorImpl::allocateTimeslice(GroupImpl * targetGroup) DP_ASSERT(!targetGroup->timeslot.count && "Reallocation of stream that is already present"); targetGroup->timeslot.count = slot_count; - targetGroup->timeslot.begin = firstFreeSlot; + targetGroup->timeslot.begin = firstSlot; targetGroup->timeslot.PBN = base_pbn; targetGroup->timeslot.hardwareDirty = true; freeSlots -= slot_count; @@ -5494,17 +5527,17 @@ void ConnectorImpl::flushTimeslotsToHardware() } main->configureMultiStream(group->headIndex, - group->timeslot.watermarks.hBlankSym, - group->timeslot.watermarks.vBlankSym, - group->timeslot.begin, - group->timeslot.begin+group->timeslot.count-1, - group->timeslot.PBN, - activeLinkConfig.PBNForSlots(group->timeslot.count), - group->colorFormat, - group->singleHeadMultiStreamID, - group->singleHeadMultiStreamMode, - bAudioOverRightPanel, - bEnable2Head1Or); + group->timeslot.watermarks.hBlankSym, + group->timeslot.watermarks.vBlankSym, + group->timeslot.begin, + group->timeslot.begin+group->timeslot.count - 1, + group->timeslot.PBN, + activeLinkConfig.PBNForSlots(group->timeslot.count), + group->colorFormat, + group->singleHeadMultiStreamID, + group->singleHeadMultiStreamMode, + bAudioOverRightPanel, + bEnable2Head1Or); } } } @@ -5577,8 +5610,8 @@ void ConnectorImpl::beforeDeleteStream(GroupImpl * group, bool forFlushMode) // RG at loadv // if (forFlushMode || - ((DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST == group->singleHeadMultiStreamMode) && - (DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY != group->singleHeadMultiStreamID))) + ((group->singleHeadMultiStreamMode == DP_SINGLE_HEAD_MULTI_STREAM_MODE_MST) && + (group->singleHeadMultiStreamID != DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY))) { main->controlRateGoverning(group->headIndex, true/*enable*/, forFlushMode /*Immediate/loadv*/); } @@ -6140,7 +6173,17 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) // // Shutdown the old message manager if there was one + // If there is a previous stale messageManager or discoveryManager + // present then there is a chance on certain docks where MSTM bits + // needs to be cleared as previous transactions might still be in + // flight. Just checking IRQ VECTOR field might not be enough to + // check for stale messages. + // Please see bug 3928070/4066192 // + if (discoveryManager || messageManager) + { + bForceClearPendingMsg = true; + } delete discoveryManager; isDiscoveryDetectComplete = false; bIsDiscoveryDetectActive = true; @@ -6180,7 +6223,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) discoveryManager = new DiscoveryManager(messageManager, this, timer, hal); // Check and clear if any pending message here - if (hal->clearPendingMsg()) + if (hal->clearPendingMsg() || bForceClearPendingMsg) { DP_LOG(("DP> Stale MSG found: set branch to D3 and back to D0...")); if (hal->isAtLeastVersion(1, 4)) @@ -6423,7 +6466,9 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) } completed: previousPlugged = statusConnected; - fireEvents(); + { + fireEvents(); + } if (!statusConnected) { @@ -6939,7 +6984,7 @@ void ConnectorImpl::createFakeMuxDevice(const NvU8 *buffer, NvU32 bufferSize) return; // Return immediately if DSC is not supported - if(FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DSC_SUPPORT, _YES, buffer[0]) != 1) + if(FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DECOMPRESSION, _YES, buffer[0]) != 1) return; DeviceImpl * existingDev = findDeviceInList(Address()); @@ -7241,31 +7286,45 @@ bool ConnectorImpl::readPsrEvtIndicator(vesaPsrEventIndicator *psrEvt) return hal->readPsrEvtIndicator(psrEvt); } -bool ConnectorImpl::updatePsrLinkState(bool bTrainLink) +bool ConnectorImpl::updatePsrLinkState(bool bTurnOnLink) { bool bRet = true; - if (bTrainLink) + bool bEnteredFlushMode = false; + + if (bTurnOnLink) { - // Bug 3438892 If the panel is turned off the reciever on its side, - // force panel link on by writting 600 = 1 - this->hal->setDirtyLinkStatus(true); - if (this->isLinkLost()) + hal->setPowerState(PowerStateD0); + + if (isLinkLost()) { - hal->setPowerState(PowerStateD0); - return false; - } + if (!this->psrLinkConfig.isValid()) + { + DP_ASSERT(0 && "Invalid PSR link config"); + return false; + } + + // NOTE: always verify changes to below line with 2H1OR case + if (!(bEnteredFlushMode = this->enableFlush())) + { + DP_ASSERT(0 && "Flush fails"); + } + + bRet = this->train(this->psrLinkConfig, false); - // Check if Link config is valid - if (!this->psrLinkConfig.isValid()) + if (bEnteredFlushMode) + { + this->disableFlush(true); + } + } + else { - return false; + // return early if link is already up + return true; } - // Restore Link config/do Link Train - bRet = setPreferredLinkConfig(this->psrLinkConfig, false, true, NORMAL_LINK_TRAINING); } else { - // Save the link config + // Save the current link config this->psrLinkConfig = getActiveLinkConfig(); } return bRet; @@ -7417,5 +7476,6 @@ void ConnectorImpl::configInit() bNoFallbackInPostLQA = 0; LT2FecLatencyMs = 0; bDscCapBasedOnParent = false; + bForceClearPendingMsg = false; } diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp index 07399ae5ac..fc9659f37f 100644 --- a/src/common/displayport/src/dp_deviceimpl.cpp +++ b/src/common/displayport/src/dp_deviceimpl.cpp @@ -1564,11 +1564,11 @@ NvBool DeviceImpl::getDSCSupport() if(AuxBus::success == this->getDpcdData(NV_DPCD14_DSC_SUPPORT, &byte, sizeof(byte), &size, &nakReason)) { - if (FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DSC_SUPPORT, _YES, byte)) + if (FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DECOMPRESSION, _YES, byte)) { dscCaps.bDSCDecompressionSupported = true; } - if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, byte)) + if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH, _YES, byte)) { dscCaps.bDSCPassThroughSupported = true; } @@ -1712,6 +1712,16 @@ NvBool DeviceImpl::isDSCPassThroughSupported() return dscCaps.bDSCPassThroughSupported; } +NvBool DeviceImpl::isDynamicPPSSupported() +{ + return dscCaps.bDynamicPPSSupported; +} + +NvBool DeviceImpl::isDynamicDscToggleSupported() +{ + return dscCaps.bDynamicDscToggleSupported; +} + NvBool DeviceImpl::isDSCPossible() { return this->bDSCPossible; @@ -1731,11 +1741,21 @@ bool DeviceImpl::parseDscCaps(const NvU8 *buffer, NvU32 bufferSize) return false; } - if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, buffer[0x0])) + if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH, _YES, buffer[0x0])) { dscCaps.bDSCPassThroughSupported = true; } + if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED, _YES, buffer[0x0])) + { + dscCaps.bDynamicPPSSupported = true; + } + + if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED, _YES, buffer[0x0])) + { + dscCaps.bDynamicDscToggleSupported = true; + } + dscCaps.versionMajor = DRF_VAL(_DPCD14, _DSC_ALGORITHM_REVISION, _MAJOR, buffer[0x1]); dscCaps.versionMinor = DRF_VAL(_DPCD14, _DSC_ALGORITHM_REVISION, _MINOR, buffer[0x1]); @@ -1987,7 +2007,7 @@ bool DeviceImpl::getDscEnable(bool *pEnable) return false; } - *pEnable = FLD_TEST_DRF(_DPCD14, _DSC_ENABLE, _SINK, _YES, byte); + *pEnable = FLD_TEST_DRF(_DPCD14, _DSC_ENABLE, _DECOMPRESSION, _YES, byte); return true; } @@ -2145,7 +2165,7 @@ bool DeviceImpl::setDscEnable(bool enable) if (!bCurrDscEnable) { - dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _SINK, _YES, dscEnableByte); + dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _DECOMPRESSION, _YES, dscEnableByte); DP_LOG(("DP-DEV> Enabling DSC decompression on device - %s", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); } @@ -2166,7 +2186,7 @@ bool DeviceImpl::setDscEnable(bool enable) if (bCurrDscEnable) { - dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _SINK, _NO, dscEnableByte); + dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _DECOMPRESSION, _NO, dscEnableByte); DP_LOG(("DP-DEV> Disabling DSC decompression on device - %s", this->devDoingDscDecompression->getTopologyAddress().toString(buffer))); } @@ -2237,7 +2257,7 @@ bool DeviceImpl::setDscEnableDPToHDMIPCON(bool bDscEnable, bool bEnablePassThrou } else { - dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _SINK, _YES, dscEnableByte); + dscEnableByte = FLD_SET_DRF(_DPCD14, _DSC_ENABLE, _DECOMPRESSION, _YES, dscEnableByte); DP_LOG(("DP-DEV> Enabling DSC decompression on DP to HDMI PCON device - %s", this->getTopologyAddress().toString(buffer))); } diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp index 9dee4985c8..d5f306b864 100644 --- a/src/common/displayport/src/dp_evoadapter.cpp +++ b/src/common/displayport/src/dp_evoadapter.cpp @@ -35,8 +35,6 @@ #include "dp_vrr.h" #include -#include -#include #include #include #include @@ -95,7 +93,8 @@ const struct {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL}, - {NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL} + {NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL}, + {NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL} }; EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) : @@ -113,10 +112,12 @@ EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) : this->initializeRegkeyDatabase(); this->applyRegkeyOverrides(); - _isDynamicMuxCapable = false; - _isLTPhyRepeaterSupported = true; - _rmPhyRepeaterCount = 0; - dpMemZero(&_DSC, sizeof(_DSC)); + _isDynamicMuxCapable = false; + _isLTPhyRepeaterSupported = true; + _rmPhyRepeaterCount = 0; + dpMemZero(&_DSC, sizeof(_DSC)); + dpMemZero(&dfpParams, sizeof(dfpParams)); + dpMemZero(&dpParams, sizeof(dpParams)); // // Tell RM to hands off on the DisplayPort hardware @@ -257,63 +258,60 @@ NvU32 EvoMainLink::headToStream(NvU32 head, DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE return streamIndex; } -void EvoMainLink::queryGPUCapability() +bool EvoMainLink::queryGPUCapability() { - NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS params; - - dpMemZero(¶ms, sizeof(params)); - params.subDeviceInstance = subdeviceIndex; - params.sorIndex = provider->getSorIndex(); - NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_GET_CAPS, ¶ms, sizeof(params)); + dpMemZero(&dpParams, sizeof(dpParams)); + dpParams.subDeviceInstance = subdeviceIndex; + dpParams.sorIndex = provider->getSorIndex(); + NvU32 code = provider->rmControl0073(NV0073_CTRL_CMD_DP_GET_CAPS, &dpParams, sizeof(dpParams)); if (code != NVOS_STATUS_SUCCESS) { DP_ASSERT(0 && "Unable to process GPU caps"); + return false; } - else - { - // - // Check if MST feature needs to be disabled by regkey. This is requirement by few OEMs, they don't want to support - // MST feature on particular sku, whenever requested through INF. - // - _hasMultistream = (params.bIsMultistreamSupported == NV_TRUE) && !_isMstDisabledByRegkey; + // + // Check if MST feature needs to be disabled by regkey. This is requirement by few OEMs, they don't want to support + // MST feature on particular sku, whenever requested through INF. + // + _hasMultistream = (dpParams.bIsMultistreamSupported == NV_TRUE) && !_isMstDisabledByRegkey; - _gpuSupportedDpVersions = params.dpVersionsSupported; + _gpuSupportedDpVersions = dpParams.dpVersionsSupported; - _isStreamCloningEnabled = (params.bIsSCEnabled == NV_TRUE) ? true : false; - _hasIncreasedWatermarkLimits = (params.bHasIncreasedWatermarkLimits == NV_TRUE) ? true : false; + _isStreamCloningEnabled = (dpParams.bIsSCEnabled == NV_TRUE) ? true : false; + _hasIncreasedWatermarkLimits = (dpParams.bHasIncreasedWatermarkLimits == NV_TRUE) ? true : false; - _isFECSupported = (params.bFECSupported == NV_TRUE) ? true : false; + _isFECSupported = (dpParams.bFECSupported == NV_TRUE) ? true : false; - _useDfpMaxLinkRateCaps = (params.bOverrideLinkBw == NV_TRUE) ? true : false; + _useDfpMaxLinkRateCaps = (dpParams.bOverrideLinkBw == NV_TRUE) ? true : false; - _isLTPhyRepeaterSupported = (params.bIsTrainPhyRepeater == NV_TRUE) ? true : false; + _isLTPhyRepeaterSupported = (dpParams.bIsTrainPhyRepeater == NV_TRUE) ? true : false; - if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _1_62, params.maxLinkRate)) - _maxLinkRateSupportedGpu = RBR; //in Hz - else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _2_70, params.maxLinkRate)) - _maxLinkRateSupportedGpu = HBR; //in Hz - else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _5_40, params.maxLinkRate)) - _maxLinkRateSupportedGpu = HBR2; //in Hz - else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _8_10, params.maxLinkRate)) - _maxLinkRateSupportedGpu = HBR3; //in Hz - else - { - DP_ASSERT(0 && "Unable to get max link rate"); - // Assume that we can at least support RBR. - _maxLinkRateSupportedGpu = RBR; - } + if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _1_62, dpParams.maxLinkRate)) + _maxLinkRateSupportedGpu = RBR; //in Hz + else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _2_70, dpParams.maxLinkRate)) + _maxLinkRateSupportedGpu = HBR; //in Hz + else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _5_40, dpParams.maxLinkRate)) + _maxLinkRateSupportedGpu = HBR2; //in Hz + else if (FLD_TEST_DRF(0073, _CTRL_CMD_DP_GET_CAPS, _MAX_LINK_RATE, _8_10, dpParams.maxLinkRate)) + _maxLinkRateSupportedGpu = HBR3; //in Hz + else + { + DP_ASSERT(0 && "Unable to get max link rate"); + // Assume that we can at least support RBR. + _maxLinkRateSupportedGpu = RBR; + } - if (!_isDscDisabledByRegkey) - { - _DSC.isDscSupported = params.DSC.bDscSupported ? true : false; - _DSC.encoderColorFormatMask = params.DSC.encoderColorFormatMask; - _DSC.lineBufferSizeKB = params.DSC.lineBufferSizeKB; - _DSC.rateBufferSizeKB = params.DSC.rateBufferSizeKB; - _DSC.bitsPerPixelPrecision = params.DSC.bitsPerPixelPrecision; - _DSC.maxNumHztSlices = params.DSC.maxNumHztSlices; - _DSC.lineBufferBitDepth = params.DSC.lineBufferBitDepth; - } + if (!_isDscDisabledByRegkey) + { + _DSC.isDscSupported = dpParams.DSC.bDscSupported ? true : false; + _DSC.encoderColorFormatMask = dpParams.DSC.encoderColorFormatMask; + _DSC.lineBufferSizeKB = dpParams.DSC.lineBufferSizeKB; + _DSC.rateBufferSizeKB = dpParams.DSC.rateBufferSizeKB; + _DSC.bitsPerPixelPrecision = dpParams.DSC.bitsPerPixelPrecision; + _DSC.maxNumHztSlices = dpParams.DSC.maxNumHztSlices; + _DSC.lineBufferBitDepth = dpParams.DSC.lineBufferBitDepth; } + return true; } void EvoMainLink::triggerACT() @@ -643,18 +641,18 @@ bool EvoMainLink::physicalLayerSetTestPattern(PatternInfo * patternInfo) { ctrlPattern.testPattern = NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM; - params.cstm.lower = patternInfo->ctsmLower; - params.cstm.middle = patternInfo->ctsmMiddle; - params.cstm.upper = patternInfo->ctsmUpper; + params.cstm.field_31_0 = patternInfo->ctsmLower; + params.cstm.field_63_32 = patternInfo->ctsmMiddle; + params.cstm.field_95_64 = patternInfo->ctsmUpper; break; } #ifdef NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE case LINK_QUAL_HBR2_COMPLIANCE_EYE: { ctrlPattern.testPattern = NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE; - params.cstm.lower = 0; - params.cstm.middle = 0; - params.cstm.upper = 0; + params.cstm.field_31_0 = 0; + params.cstm.field_63_32 = 0; + params.cstm.field_95_64 = 0; break; } #endif @@ -893,6 +891,7 @@ void EvoMainLink::applyRegkeyOverrides() _skipPowerdownEDPPanelWhenHeadDetach = dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped; _applyLinkBwOverrideWarRegVal = dpRegkeyDatabase.bLinkBwOverrideWarApplied; _enableMSAOverrideOverMST = dpRegkeyDatabase.bMsaOverMstEnabled; + _isMSTPCONCapsReadDisabled = dpRegkeyDatabase.bMSTPCONCapsReadDisabled; } NvU32 EvoMainLink::getRegkeyValue(const char *key) @@ -1373,7 +1372,6 @@ bool EvoMainLink::getMaxLinkConfigFromUefi(NvU8 &linkRate, NvU8 &laneCount) bool EvoMainLink::queryAndUpdateDfpParams() { - NV0073_CTRL_DFP_GET_INFO_PARAMS dfpParams; NvU32 dfpFlags; dpMemZero(&dfpParams, sizeof(dfpParams)); dfpParams.subDeviceInstance = subdeviceIndex; @@ -1516,6 +1514,10 @@ bool EvoMainLink::skipPowerdownEdpPanelWhenHeadDetach() return _skipPowerdownEDPPanelWhenHeadDetach; } +bool EvoMainLink::isMSTPCONCapsReadDisabled() +{ + return _isMSTPCONCapsReadDisabled; +} bool EvoMainLink::isActive() { diff --git a/src/common/displayport/src/dp_wardatabase.cpp b/src/common/displayport/src/dp_wardatabase.cpp index f4e6c483ef..024d9621c7 100644 --- a/src/common/displayport/src/dp_wardatabase.cpp +++ b/src/common/displayport/src/dp_wardatabase.cpp @@ -561,7 +561,7 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen // NCP case 0x7038: - if ((ProductID == 0x005F)) + if (ProductID == 0x005F) { this->WARFlags.bIgnoreDscCap = true; DP_LOG(("DP-WAR> NCP panels incorrectly exposing DSC capability. Ignoring it.")); diff --git a/src/common/inc/displayport/displayport.h b/src/common/inc/displayport/displayport.h index b258d1c367..daa7003a6a 100644 --- a/src/common/inc/displayport/displayport.h +++ b/src/common/inc/displayport/displayport.h @@ -23,6 +23,7 @@ #ifndef _DISPLAYPORT_H_ #define _DISPLAYPORT_H_ +#include "nvcfg_sdk.h" #include "nvmisc.h" #include "dpcd.h" @@ -161,7 +162,7 @@ typedef enum trainingPattern_1 = 0x1, trainingPattern_2 = 0x2, trainingPattern_3 = 0x3, - trainingPattern_4 = 0xB + trainingPattern_4 = 0xB, } DP_TRAININGPATTERN; typedef enum @@ -245,6 +246,8 @@ typedef struct DscCaps { NvBool bDSCSupported; NvBool bDSCDecompressionSupported; + NvBool bDynamicPPSSupported; + NvBool bDynamicDscToggleSupported; NvBool bDSCPassThroughSupported; unsigned versionMajor, versionMinor; unsigned rcBufferBlockSize; diff --git a/src/common/inc/displayport/dpcd.h b/src/common/inc/displayport/dpcd.h index cdedffc77d..d8896d75bf 100644 --- a/src/common/inc/displayport/dpcd.h +++ b/src/common/inc/displayport/dpcd.h @@ -697,6 +697,14 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE6 5:4 /* R-XUF */ #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE7 7:6 /* R-XUF */ +#define NV_DPCD_EDP_LINK_CONFIG_STATUS (0x0000020c) /* RWXUR */ +#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET 0:0 /* R-XUF */ +#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET_LINK_BW (0x00000000) /* R-XUV */ +#define NV_DPCD_EDP_LINK_CONFIG_STATUS_SET_LINK_RATE (0x00000001) /* R-XUV */ +#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID 1:1 /* R-XUF */ +#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID_NO (0x00000000) /* R-XUV */ +#define NV_DPCD_EDP_LINK_CONFIG_STATUS_VALID_YES (0x00000001) /* R-XUV */ + // 0020Fh: RESERVED. Read all 0s #define NV_DPCD_SYMBOL_ERROR_COUNT_LANEX_BYTE0(i) (0x00000210+(i)*2) /* R--1A */ diff --git a/src/common/inc/displayport/dpcd14.h b/src/common/inc/displayport/dpcd14.h index ea649b46d1..7b911d8d55 100644 --- a/src/common/inc/displayport/dpcd14.h +++ b/src/common/inc/displayport/dpcd14.h @@ -43,9 +43,9 @@ #define NV_DPCD14_TRAINING_AUX_RD_INTERVAL_EXTENDED_RX_CAP_YES (0x00000001) /* R-XUV */ #define NV_DPCD14_DSC_SUPPORT (0x00000060) /* R-XUR */ -#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT 0:0 /* R-XUF */ -#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT_NO (0x00000000) /* R-XUV */ -#define NV_DPCD14_DSC_SUPPORT_DSC_SUPPORT_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION 0:0 /* R-XUF */ +#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_DSC_SUPPORT_DECOMPRESSION_YES (0x00000001) /* R-XUV */ #define NV_DPCD14_DSC_ALGORITHM_REVISION (0x00000061) /* R-XUR */ #define NV_DPCD14_DSC_ALGORITHM_REVISION_MAJOR 3:0 /* R-XUF */ @@ -190,9 +190,9 @@ #define NV_DPCD14_DSC_BITS_PER_PIXEL_INCREMENT_SUPPORTED_1 (0x00000004) /* R-XUV */ #define NV_DPCD14_DSC_ENABLE (0x00000160) /* R-XUR */ -#define NV_DPCD14_DSC_ENABLE_SINK 0:0 /* R-XUF */ -#define NV_DPCD14_DSC_ENABLE_SINK_NO (0x00000000) /* R-XUV */ -#define NV_DPCD14_DSC_ENABLE_SINK_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION 0:0 /* R-XUF */ +#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_DSC_ENABLE_DECOMPRESSION_YES (0x00000001) /* R-XUV */ #define NV_DPCD14_FEC_CAPABILITY (0x00000090) /* R-XUR */ #define NV_DPCD14_FEC_CAPABILITY_FEC_CAPABLE 0:0 /* R-XUF */ @@ -213,7 +213,9 @@ #define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE 5:5 /* R-XUF */ #define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */ #define NV_DPCD14_FEC_CAPABILITY_PARITY_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */ -// Bit 6 : RESERVED. Read 0 +#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT 6:6 /* R-XUF */ +#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_FEC_CAPABILITY_FEC_RUNNING_INDICATOR_SUPPORT_YES (0x00000001) /* R-XUV */ #define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED 7:7 /* R-XUF */ #define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED_NO (0x00000000) /* R-XUV */ #define NV_DPCD14_FEC_CAPABILITY_FEC_ERROR_REPORTING_POLICY_SUPPORTED_YES (0x00000001) /* R-XUV */ @@ -629,36 +631,6 @@ #define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_REQ 6:0 /* R-XUF */ #define NV_DPCD14_PHY_REPEATER_EXTENDED_WAKE_TIMEOUT_GRANT 7:7 /* RWXUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE (0x000F0008) /* R-XUR */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR(i) (i):(i) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0 0:0 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_0_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1 1:1 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_1_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2 2:2 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_2_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3 3:3 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_3_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4 4:4 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_4_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5 5:5 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_5_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6 6:6 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_6_YES (0x00000001) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7 7:7 /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7_NO (0x00000000) /* R-XUF */ -#define NV_DPCD14_PHY_REPEATER_EQ_DONE_LTTPR_7_YES (0x00000001) /* R-XUF */ - - #define NV_DPCD14_PHY_REPEATER_START(i) (0x000F0010+(i)*0x50) /* RW-1A */ #define NV_DPCD14_PHY_REPEATER_START__SIZE 8 /* R---S */ // Following defines are offsets @@ -689,6 +661,56 @@ #define NV_DPCD14_ADJUST_REQUEST_LANE0_1_PHY_REPEATER (0x00000023) /* R-XUR */ #define NV_DPCD14_ADJUST_REQUEST_LANE2_3_PHY_REPEATER (0x00000024) /* R-XUR */ +#define NV_DPCD14_PHY_REPEATER_FEC__SIZE NV_DPCD14_PHY_REPEATER_CNT_MAX /* R---S */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS(i) (0x000F0290+(i)*8) /* R--1A */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED 0:0 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_EN_DETECTED_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED 1:1 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_DECODE_DIS_DETECTED_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR 2:2 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_STATUS_FEC_RUNNING_INDICATOR_YES (0x00000001) /* R-XUV */ + +#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT(i) (0x000F0291+(i)*8) /* R--2A */ +#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_LOW_BYTE(i) (NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT(i)) +#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_HIGH_BYTE(i) ((0x000F0292+(i)*8)) /* R-XUR */ +#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID 7:7 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_ERR_COUNT_VALID_YES (0x00000001) /* R-XUV */ + +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0(i) (0x000F0294+(i)*8) /* R--1A */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE 0:0 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_CAPABLE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE 1:1 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE 2:2 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0CORRECTED_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_CORRECTED_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE 3:3 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_BIT_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE 4:4 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_BLOCK_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE 5:5 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_PARITY_ERROR_COUNT_CAPABLE_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT 6:6 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_RUNNING_INDICATOR_SUPPORT_YES (0x00000001) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED 7:7 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED_NO (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_0_FEC_ERROR_REPORTING_POLICY_SUPPORTED_YES (0x00000001) /* R-XUV */ + +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1(i) (0x000F0295+(i)*8) /* R--1A */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE 0:0 /* R-XUF */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE_CAPABLE_N (0x00000000) /* R-XUV */ +#define NV_DPCD14_PHY_REPEATER_FEC_CAP_1_AGGREGATE_ERR_COUNT_CAPABLE_CAPABLE_YES (0x00000001) /* R-XUV */ + // BRANCH SPECIFIC DSC CAPS #define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0) #define NV_DPCD14_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0 diff --git a/src/common/inc/displayport/dpcd20.h b/src/common/inc/displayport/dpcd20.h index 4387e5308d..7742f31623 100644 --- a/src/common/inc/displayport/dpcd20.h +++ b/src/common/inc/displayport/dpcd20.h @@ -25,14 +25,24 @@ #include "nvcfg_sdk.h" // DSC Pass Through related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0. -#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT 1:1 /* R-XUF */ -#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_NO (0x00000000) /* R-XUV */ -#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_SUPPORT_YES (0x00000001) /* R-XUV */ +#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH 1:1 /* R-XUF */ +#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_NO (0x00000000) /* R-XUV */ +#define NV_DPCD20_DSC_SUPPORT_PASS_THROUGH_YES (0x00000001) /* R-XUV */ // DSC Pass Through related DPCD. New bits in DPCD 0x0160h defined in DPCD2.0. #define NV_DPCD20_DSC_ENABLE_PASS_THROUGH 1:1 /* R-XUF */ #define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_NO (0x00000000) /* R-XUV */ #define NV_DPCD20_DSC_ENABLE_PASS_THROUGH_YES (0x00000001) /* R-XUV */ +// DSC Dynamic PPS related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0. +#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED 2:2 +#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED_NO (0x00000000) +#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_COMPRESSED_TO_COMPRESSED_YES (0x00000001) + +// DSC Dynamic PPS related DPCD. New bits in DPCD 0x0060h defined in DPCD2.0. +#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED 3:3 +#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED_NO (0x00000000) +#define NV_DPCD20_DSC_SUPPORT_DYNAMIC_PPS_UNCOMPRESSED_TO_FROM_COMPRESSED_YES (0x00000001) + // PANEL REPLAY RELATED DPCD #define NV_DPCD20_PANEL_REPLAY_CAPABILITY (0x000000B0) #define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0 diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index 74bbd54a45..4719dd5388 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,26 +36,26 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r545_96 + #define NV_BUILD_BRANCH r551_06 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r545_96 + #define NV_PUBLIC_BRANCH r551_06 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r545/r545_96-124" -#define NV_BUILD_CHANGELIST_NUM (33538619) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r551_06-132" +#define NV_BUILD_CHANGELIST_NUM (33773930) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r545/r545_96-124" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33538619) +#define NV_BUILD_NAME "rel/gpu_drv/r550/r551_06-132" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33773930) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r545_96-8" -#define NV_BUILD_CHANGELIST_NUM (33517029) +#define NV_BUILD_BRANCH_VERSION "r551_06-14" +#define NV_BUILD_CHANGELIST_NUM (33773930) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "546.17" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33517029) -#define NV_BUILD_BRANCH_BASE_VERSION R545 +#define NV_BUILD_NAME "551.23" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33773930) +#define NV_BUILD_BRANCH_BASE_VERSION R550 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvPNPVendorIds.h b/src/common/inc/nvPNPVendorIds.h index 423559f9dc..1a2ca53d21 100644 --- a/src/common/inc/nvPNPVendorIds.h +++ b/src/common/inc/nvPNPVendorIds.h @@ -157,6 +157,7 @@ static const PNPVendorId PNPVendorIds[] = { "CRS", _VENDOR_NAME_ENTRY("Cisco") }, { "CSE", _VENDOR_NAME_ENTRY("Compu Shack") }, { "CSI", _VENDOR_NAME_ENTRY("Cabletron") }, + { "CSO", _VENDOR_NAME_ENTRY("California institute of Technology")}, { "CSS", _VENDOR_NAME_ENTRY("CSS Laboratories") }, { "CSW", _VENDOR_NAME_ENTRY("China Star Optoelectronics Technology Co., Ltd") }, { "CTN", _VENDOR_NAME_ENTRY("Computone") }, @@ -294,6 +295,7 @@ static const PNPVendorId PNPVendorIds[] = { "ITK", _VENDOR_NAME_ENTRY("NTI Group") }, { "IVK", _VENDOR_NAME_ENTRY("Iiyama") }, { "IVM", _VENDOR_NAME_ENTRY("Idek Iiyama") }, + { "IVO", _VENDOR_NAME_ENTRY("InfoVision OptoElectronics Co., Ltd")}, { "IVR", _VENDOR_NAME_ENTRY("Inlife-Handnet Co., Ltd.") }, { "IWR", _VENDOR_NAME_ENTRY("Icuiti Corporation") }, diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index ffff0d900d..8cf1a85705 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "545.29.06" +#define NV_VERSION_STRING "550.40.07" #else diff --git a/src/common/inc/nvVer.h b/src/common/inc/nvVer.h index 4e55a3c779..c8113d6183 100644 --- a/src/common/inc/nvVer.h +++ b/src/common/inc/nvVer.h @@ -3,7 +3,7 @@ #define NV_COMPANY_NAME_STRING_SHORT "NVIDIA" #define NV_COMPANY_NAME_STRING_FULL "NVIDIA Corporation" #define NV_COMPANY_NAME_STRING NV_COMPANY_NAME_STRING_FULL -#define NV_COPYRIGHT_YEAR "2023" +#define NV_COPYRIGHT_YEAR "2024" #define NV_COPYRIGHT "(C) " NV_COPYRIGHT_YEAR " NVIDIA Corporation. All rights reserved." // Please do not use the non-ascii copyright symbol for (C). #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ diff --git a/src/common/inc/nveGPUConfig.h b/src/common/inc/nveGPUConfig.h deleted file mode 100644 index 25b6f42776..0000000000 --- a/src/common/inc/nveGPUConfig.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef _NVEGPUCONFIG_H_ -#define _NVEGPUCONFIG_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -#define EGPU_INLINE NV_FORCEINLINE -#else //!__cplusplus -#if defined(NV_UNIX) || defined(NVCPU_RISCV64) || defined(NV_MODS) -#define EGPU_INLINE static NV_INLINE -#else //NV_UNIX -#define EGPU_INLINE NV_INLINE -#endif //NV_UNIX -#endif //!__cplusplus - -// Surprise removal capable TB3 and TB2 BUS Device ID -#define BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01 0x1578 -#define BUS_DEVICE_ID_TB3_02 0x1576 -#define BUS_DEVICE_ID_TB3_03 0x15C0 -#define BUS_DEVICE_ID_TB3_04 0x15D3 -#define BUS_DEVICE_ID_TB3_05 0x15DA -#define BUS_DEVICE_ID_TB3_06 0x15EA -#define BUS_DEVICE_ID_TB3_07 0x15E7 -#define BUS_DEVICE_ID_TB3_08 0x15EF -#define BUS_DEVICE_ID_TB3_09 0x1133 -#define BUS_DEVICE_ID_TB3_10 0x1136 - -// IceLake-U TB3 device ids. Below TB3 would be integrated to CPU. -#define BUS_DEVICE_ID_ICELAKE_TB3_01 0x8A1D -#define BUS_DEVICE_ID_ICELAKE_TB3_02 0x8A1F -#define BUS_DEVICE_ID_ICELAKE_TB3_03 0x8A21 -#define BUS_DEVICE_ID_ICELAKE_TB3_04 0x8A23 -#define BUS_DEVICE_ID_ICELAKE_TB3_05 0x8A0D -#define BUS_DEVICE_ID_ICELAKE_TB3_06 0x8A17 - -// TigerLake Thunderbolt device ids. -#define BUS_DEVICE_ID_TIGERLAKE_TB3_01 0x9A1B -#define BUS_DEVICE_ID_TIGERLAKE_TB3_02 0x9A1D -#define BUS_DEVICE_ID_TIGERLAKE_TB3_03 0x9A1F -#define BUS_DEVICE_ID_TIGERLAKE_TB3_04 0x9A21 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_05 0x9A23 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_06 0x9A25 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_07 0x9A27 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_08 0x9A29 -#define BUS_DEVICE_ID_TIGERLAKE_TB3_09 0x9A2B -#define BUS_DEVICE_ID_TIGERLAKE_TB3_10 0x9A2D - -// Meteor Lake ThunderBolt Device IDs -#define BUS_DEVICE_ID_METEOR_TB3_01 0x7EB2 -#define BUS_DEVICE_ID_METEOR_TB3_02 0x7EC2 -#define BUS_DEVICE_ID_METEOR_TB3_03 0x7EC3 -#define BUS_DEVICE_ID_METEOR_TB3_04 0x7EB4 -#define BUS_DEVICE_ID_METEOR_TB3_05 0x7EC4 -#define BUS_DEVICE_ID_METEOR_TB3_06 0x7EB5 -#define BUS_DEVICE_ID_METEOR_TB3_07 0x7EC5 -#define BUS_DEVICE_ID_METEOR_TB3_08 0x7EC6 -#define BUS_DEVICE_ID_METEOR_TB3_09 0x7EC7 - -// Raptor Lake ThunderBolt Device IDs -#define BUS_DEVICE_ID_RAPTOR_TB3_01 0xA73E -#define BUS_DEVICE_ID_RAPTOR_TB3_02 0xA76D -#define BUS_DEVICE_ID_RAPTOR_TB3_03 0x466E -#define BUS_DEVICE_ID_RAPTOR_TB3_04 0x463F -#define BUS_DEVICE_ID_RAPTOR_TB3_05 0x462F -#define BUS_DEVICE_ID_RAPTOR_TB3_06 0x461F - -//#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_01 0X156C // obsolete -#define BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02 0X156D -#define BUS_DEVICE_ID_TB2_03 0x157E -#define BUS_DEVICE_ID_TB2_04 0x156B -#define BUS_DEVICE_ID_TB2_05 0x1567 -#define BUS_DEVICE_ID_TB2_06 0x1569 -//#define BUS_DEVICE_ID_TB2_07 0x1548 // obsolete -#define BUS_DEVICE_ID_TB2_08 0x151B -#define BUS_DEVICE_ID_TB2_09 0x1549 -#define BUS_DEVICE_ID_TB2_10 0x1513 - -//***************************************************************************** -// Function: isTB3DeviceID -// -// Routine Description: -// -// Function to match the specified Device ID with the known TB3 BUS's -// device IDs. -// -// Arguments: -// -// deviceID[IN]: Device ID to match with the TB3 Bus -// -// Return Value: -// -// true: When the passed Dev ID match with TB3's BUS Device ID -// false: When the passed Dev ID is not matching with known TB3's -// BUS Device ID -//***************************************************************************** -EGPU_INLINE NvBool isTB3DeviceID(NvU16 deviceID) -{ - NvU32 index; - NvU16 tb3DeviceIDList[]={ BUS_DEVICE_ID_TB3_ALPINE_RIDGE_01, - BUS_DEVICE_ID_TB3_02, - BUS_DEVICE_ID_TB3_03, - BUS_DEVICE_ID_TB3_04, - BUS_DEVICE_ID_TB3_05, - BUS_DEVICE_ID_TB3_06, - BUS_DEVICE_ID_TB3_07, - BUS_DEVICE_ID_TB3_08, - BUS_DEVICE_ID_TB3_09, - BUS_DEVICE_ID_TB3_10, - BUS_DEVICE_ID_ICELAKE_TB3_01, - BUS_DEVICE_ID_ICELAKE_TB3_02, - BUS_DEVICE_ID_ICELAKE_TB3_03, - BUS_DEVICE_ID_ICELAKE_TB3_04, - BUS_DEVICE_ID_ICELAKE_TB3_05, - BUS_DEVICE_ID_ICELAKE_TB3_06, - BUS_DEVICE_ID_TIGERLAKE_TB3_01, - BUS_DEVICE_ID_TIGERLAKE_TB3_02, - BUS_DEVICE_ID_TIGERLAKE_TB3_03, - BUS_DEVICE_ID_TIGERLAKE_TB3_04, - BUS_DEVICE_ID_TIGERLAKE_TB3_05, - BUS_DEVICE_ID_TIGERLAKE_TB3_06, - BUS_DEVICE_ID_TIGERLAKE_TB3_07, - BUS_DEVICE_ID_TIGERLAKE_TB3_08, - BUS_DEVICE_ID_TIGERLAKE_TB3_09, - BUS_DEVICE_ID_TIGERLAKE_TB3_10, - BUS_DEVICE_ID_METEOR_TB3_01, - BUS_DEVICE_ID_METEOR_TB3_02, - BUS_DEVICE_ID_METEOR_TB3_03, - BUS_DEVICE_ID_METEOR_TB3_04, - BUS_DEVICE_ID_METEOR_TB3_05, - BUS_DEVICE_ID_METEOR_TB3_06, - BUS_DEVICE_ID_METEOR_TB3_07, - BUS_DEVICE_ID_METEOR_TB3_08, - BUS_DEVICE_ID_METEOR_TB3_09, - BUS_DEVICE_ID_RAPTOR_TB3_01, - BUS_DEVICE_ID_RAPTOR_TB3_02, - BUS_DEVICE_ID_RAPTOR_TB3_03, - BUS_DEVICE_ID_RAPTOR_TB3_04, - BUS_DEVICE_ID_RAPTOR_TB3_05, - BUS_DEVICE_ID_RAPTOR_TB3_06 - }; - for (index = 0; index < (sizeof(tb3DeviceIDList)/sizeof(NvU16)); index++) - { - if (deviceID == tb3DeviceIDList[index]) - { - return NV_TRUE; - } - } - return NV_FALSE; -} // isTB3DeviceID - -//***************************************************************************** -// Function: isTB2DeviceID -// -// Routine Description: -// -// Function to match the specified Device ID with the known TB2 BUS's -// device IDs. -// -// Arguments: -// -// deviceID[IN]: Device ID to match with the TB2 Bus -// -// Return Value: -// -// true: When the passed Dev ID match with TB2's BUS Device ID -// false: When the passed Dev ID is not matching with known TB2's -// BUS Device ID -//***************************************************************************** -EGPU_INLINE NvBool isTB2DeviceID(NvU16 deviceID) -{ - NvU32 index; - NvU16 tb2DeviceIDList[]={ BUS_DEVICE_ID_TB2_FALCON_RIDGE_DSL5520_02, - BUS_DEVICE_ID_TB2_03, BUS_DEVICE_ID_TB2_04, - BUS_DEVICE_ID_TB2_05, BUS_DEVICE_ID_TB2_06, - BUS_DEVICE_ID_TB2_08, BUS_DEVICE_ID_TB2_09, - BUS_DEVICE_ID_TB2_10 - }; - for (index = 0; index < (sizeof(tb2DeviceIDList)/sizeof(NvU16)); index++) - { - if (deviceID == tb2DeviceIDList[index]) - { - return NV_TRUE; - } - } - return NV_FALSE; -} // isTB2DeviceID - -#ifdef __cplusplus -} -#endif -#endif //_NVEGPUCONFIG_H_ diff --git a/src/common/inc/nvhybridacpi.h b/src/common/inc/nvhybridacpi.h index 8a43a8a553..2656c3ddc3 100644 --- a/src/common/inc/nvhybridacpi.h +++ b/src/common/inc/nvhybridacpi.h @@ -68,6 +68,39 @@ extern "C" #define NVHG_ERROR_UNSUPPORTED 0x80000002 // FunctionCode or SubFunctionCode not supported by this system #define NVHG_ERROR_PARM_INVALID 0x80000003 // Parameter is invalid (i.e. start page beyond end of buffer) +// **************************************************** +// For MXDS Display Output Mux Control Method +// **************************************************** +#define MXDS_METHOD_GET_MUX_STATE 0x00000000 +#define MXDS_METHOD_SET_DISP_MUX_TO_THISGPU 0x00000001 +#define MXDS_METHOD_SET_BACKLIGHT_MUX_TO_THISGPU 0x00000002 +#define MXDS_METHOD_SET_DISP_AND_BACKLIGHT_MUX_TO_THISGPU 0x00000003 + +// return buffer definitions +#define MXDS_METHOD_MUX_STATE_NOT_MUXED 0x00000000 +#define MXDS_METHOD_MUX_STATE_IS_MUXED 0x00000001 + +// +// ACPI _MXDS (Switch DispMux state) specific defines +// These defines are as per the ACPI spec from Bug 2297713 +// +#define MXDS_METHOD_MUX_OP 3:0 +#define MXDS_METHOD_MUX_OP_GET 0x00000000 +#define MXDS_METHOD_MUX_OP_SET 0x00000001 +#define MXDS_METHOD_MUX_SET_MODE 4:4 +#define MXDS_METHOD_MUX_SET_MODE_IGPU 0x00000000 +#define MXDS_METHOD_MUX_SET_MODE_DGPU 0x00000001 + +// +// ACPI _LRST (LCD VDD force reset) specific defines +// These defines are as per the ACPI spec from NVIDIA +// DDS Partner Guidelines For Notebook (OEM Doc) +// +#define LRST_METHOD_FORCE_RESET_OP 2:0 +#define LRST_METHOD_FORCE_RESET_OP_GET 0x00000000 +#define LRST_METHOD_FORCE_RESET_OP_SET_LOW 0x00000001 +#define LRST_METHOD_FORCE_RESET_OP_SET_HIGH 0x00000002 + #if defined(__cplusplus) } // extern "C" #endif // defined(__cplusplus) diff --git a/src/common/inc/nvlog_defs.h b/src/common/inc/nvlog_defs.h index f7bcb0ba82..2bdbe92ff7 100644 --- a/src/common/inc/nvlog_defs.h +++ b/src/common/inc/nvlog_defs.h @@ -103,14 +103,8 @@ struct _NVLOG_BUFFER #define NVLOG_MAX_BUFFERS_v11 16 #define NVLOG_MAX_BUFFERS_v12 256 -#if NVOS_IS_UNIX #define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v12 #define NVLOG_LOGGER_VERSION 12 // v1.2 -#else -#define NVLOG_MAX_BUFFERS NVLOG_MAX_BUFFERS_v11 -#define NVLOG_LOGGER_VERSION 11 // v1.1 -#endif // NVOS_IS_UNIX - // Due to this file's peculiar location, NvPort may or may not be includable typedef struct PORT_SPINLOCK PORT_SPINLOCK; diff --git a/src/common/inc/swref/published/ada/ad102/dev_bus.h b/src/common/inc/swref/published/ada/ad102/dev_bus.h index 7eea0fd2c4..5781dda400 100644 --- a/src/common/inc/swref/published/ada/ad102/dev_bus.h +++ b/src/common/inc/swref/published/ada/ad102/dev_bus.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,18 @@ #define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */ #define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */ #define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */ +#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */ +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */ #endif // ad102_dev_nv_bus_h diff --git a/src/common/inc/swref/published/ada/ad102/dev_fault.h b/src/common/inc/swref/published/ada/ad102/dev_fault.h new file mode 100644 index 0000000000..d2259556d6 --- /dev/null +++ b/src/common/inc/swref/published/ada/ad102/dev_fault.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ad102_dev_fault_h__ +#define __ad102_dev_fault_h__ + +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */ +#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC0 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC1 26 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC2 27 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC3 28 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC4 29 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG0 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG1 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG2 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG3 24 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_OFA0 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */ + +#define NV_PFAULT_CLIENT_HUB_NVJPG1 0x00000072 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG2 0x00000073 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG3 0x00000074 /* */ + +#endif // __ad102_dev_fault_h__ diff --git a/src/common/inc/swref/published/ampere/ga100/dev_boot.h b/src/common/inc/swref/published/ampere/ga100/dev_boot.h index 5e1dfb690e..3be914d110 100644 --- a/src/common/inc/swref/published/ampere/ga100/dev_boot.h +++ b/src/common/inc/swref/published/ampere/ga100/dev_boot.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -33,6 +33,12 @@ #define NV_PMC_ENABLE_NVDEC 15:15 /* */ #define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ #define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */ +#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ #define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */ #define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */ #define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */ diff --git a/src/common/inc/swref/published/ampere/ga100/dev_bus.h b/src/common/inc/swref/published/ampere/ga100/dev_bus.h index a1ee1c5dbb..e17cd974f6 100644 --- a/src/common/inc/swref/published/ampere/ga100/dev_bus.h +++ b/src/common/inc/swref/published/ampere/ga100/dev_bus.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,5 +28,17 @@ #define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */ #define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */ #define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */ +#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */ +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */ #endif // ga100_dev_nv_bus_h diff --git a/src/common/inc/swref/published/ampere/ga100/dev_fault.h b/src/common/inc/swref/published/ampere/ga100/dev_fault.h new file mode 100644 index 0000000000..ca493c005f --- /dev/null +++ b/src/common/inc/swref/published/ampere/ga100/dev_fault.h @@ -0,0 +1,206 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ga100_dev_fault_h__ +#define __ga100_dev_fault_h__ + +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */ +#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC0 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC1 26 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC2 27 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC3 28 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC4 29 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG0 30 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE9 24 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_OFA0 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */ + +#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */ + +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */ +#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */ + +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */ +#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */ +#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */ +#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */ +#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */ +#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */ +#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */ +#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */ +#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */ +#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */ +#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */ +#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */ +#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */ +#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */ +#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */ +#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */ +#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */ +#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */ + +#endif // __ga100_dev_fault_h__ diff --git a/src/common/inc/swref/published/ampere/ga100/hwproject.h b/src/common/inc/swref/published/ampere/ga100/hwproject.h new file mode 100644 index 0000000000..21c6b4538c --- /dev/null +++ b/src/common/inc/swref/published/ampere/ga100/hwproject.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __ga100_hwproject_h__ +#define __ga100_hwproject_h__ + +#define NV_SCAL_LITTER_NUM_FBPAS 24 + +#endif // __ga100_hwproject_h__ diff --git a/src/common/inc/swref/published/ampere/ga102/dev_vm.h b/src/common/inc/swref/published/ampere/ga102/dev_vm.h index cf07e6f504..e5a1498404 100644 --- a/src/common/inc/swref/published/ampere/ga102/dev_vm.h +++ b/src/common/inc/swref/published/ampere/ga102/dev_vm.h @@ -61,4 +61,5 @@ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */ #define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */ #endif // __ga102_dev_vm_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_bus.h b/src/common/inc/swref/published/hopper/gh100/dev_bus.h new file mode 100644 index 0000000000..fc328ea05c --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_bus.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef gh100_dev_nv_bus_h +#define gh100_dev_nv_bus_h + +#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */ +#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */ +#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */ +#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */ + +#endif // gh100_dev_nv_bus_h diff --git a/src/common/inc/swref/published/hopper/gh100/dev_bus_addendum.h b/src/common/inc/swref/published/hopper/gh100/dev_bus_addendum.h new file mode 100644 index 0000000000..4aabb9f324 --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_bus_addendum.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef gh100_dev_nv_bus_addendum_h +#define gh100_dev_nv_bus_addendum_h + +/*! + * @defgroup FRTS_INSECURE_SCRATCH_REGISTERS + * + * Used to communicate the location/size of insecure FRTS + * + * @{ + */ +#define NV_PBUS_SW_FRTS_INSECURE_ADDR_LO32 NV_PBUS_SW_SCRATCH(0x3D) + +#define NV_PBUS_SW_FRTS_INSECURE_ADDR_HI32 NV_PBUS_SW_SCRATCH(0x3E) + +#define NV_PBUS_SW_FRTS_INSECURE_CONFIG NV_PBUS_SW_SCRATCH(0x3F) +#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K 15U:0U +#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_INVALID 0x0000 +#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_SHIFT 12U +#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE 16U:16U +#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_FB 0U +#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_SYSMEM 1U +/*!@}*/ + +#endif // gh100_dev_nv_bus_addendum_h diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fault.h b/src/common/inc/swref/published/hopper/gh100/dev_fault.h index a85faa6e86..22089ffc9a 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_fault.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_fault.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,183 @@ #ifndef __gh100_dev_fault_h__ #define __gh100_dev_fault_h__ -#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */ +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */ +#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 256 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 320 /* */ +#define NV_PFAULT_MMU_ENG_ID_FSP 7 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF0 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 5 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 56 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 43 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 44 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 45 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 46 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 47 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 48 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 49 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 50 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 51 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE9 52 /* */ + +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */ +#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */ + +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_CE3 0x0000000C /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */ +#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */ +#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */ +#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */ +#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */ +#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */ +#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */ +#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */ +#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */ +#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */ +#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */ +#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */ +#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */ +#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */ +#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */ +#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */ +#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */ +#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC5 0x0000006F /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC6 0x00000070 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC7 0x00000071 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG1 0x00000072 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG2 0x00000073 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG3 0x00000074 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG4 0x00000075 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG5 0x00000076 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG6 0x00000077 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG7 0x00000078 /* */ +#define NV_PFAULT_CLIENT_HUB_FSP 0x00000079 /* */ #endif // __gh100_dev_fault_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_fb.h b/src/common/inc/swref/published/hopper/gh100/dev_fb.h index b94b765694..24df1cd805 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_fb.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_fb.h @@ -30,24 +30,4 @@ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */ #define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ -#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ - -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ -#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ - -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ -#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #endif // __gh100_dev_fb_h_ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_gsp.h b/src/common/inc/swref/published/hopper/gh100/dev_gsp.h index c598d2b1a3..61eb8014cd 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_gsp.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_gsp.h @@ -31,4 +31,22 @@ #define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */ #define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */ #define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */ +#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMC__SIZE_1 8 /* */ +#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */ +#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */ +#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMD__SIZE_1 8 /* */ +#define NV_PGSP_EMEMD_DATA 31:0 /* RWXVF */ + #endif // __gh100_dev_gsp_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_perf.h b/src/common/inc/swref/published/hopper/gh100/dev_perf.h new file mode 100644 index 0000000000..4e61b3f70b --- /dev/null +++ b/src/common/inc/swref/published/hopper/gh100/dev_perf.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gh100_dev_perf_h__ +#define __gh100_dev_perf_h__ + +#define NV_PERF_PMMSYSROUTER_NUM_USER_STREAMING_CHANNELS 9 /* */ + +#endif // __gh100_dev_perf_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_vm.h b/src/common/inc/swref/published/hopper/gh100/dev_vm.h index 64c6379b0a..8673969d46 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_vm.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_vm.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -65,4 +65,46 @@ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */ #define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR 0x00000F60 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MAP 31:10 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING 0:0 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING 1:1 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE 9:9 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET 11:10 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_PTR 31:12 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_PTR_0 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR 0x00000F64 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR_PTR 31:0 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR_PTR_0 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_PTR_SHIFT 12 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR 0x00000F70 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MAP 31:10 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING 0:0 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING 1:1 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE 9:9 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET 11:10 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR 31:12 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR_0 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR 0x00000F74 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR_PTR (52-33):0 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR_PTR_0 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_PTR_SHIFT 12 /* */ #endif // __gh100_dev_vm_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h index e7ab802c14..e72268ce4b 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h +++ b/src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h @@ -24,6 +24,8 @@ #ifndef __gh100_dev_xtl_ep_pcfg_gpu_h__ #define __gh100_dev_xtl_ep_pcfg_gpu_h__ #define NV_EP_PCFG_GPU_ID 0x00000000 /* R--4R */ +#define NV_EP_PCFG_GPU_ID_VENDOR 15:0 /* R-EVF */ +#define NV_EP_PCFG_GPU_ID_VENDOR_NVIDIA 0x000010DE /* R-E-V */ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS 0x00000004 /* RW-4R */ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE 0:0 /* RWIVF */ #define NV_EP_PCFG_GPU_CTRL_CMD_AND_STATUS_CMD_IO_SPACE_ENABLE 0x00000001 /* RW--V */ @@ -114,4 +116,5 @@ #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_WDG 14:14 /* R-CVF */ #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_BOOTFSM 15:15 /* R-CVF */ #define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */ +#define NV_EP_PCFG_GPU_L1_PM_SS_CONTROL_1_REGISTER 0x00000298 /* RW-4R */ #endif // __gh100_dev_xtl_ep_pcfg_gpu_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/hwproject.h b/src/common/inc/swref/published/hopper/gh100/hwproject.h index 11bd952c16..7725d0e95b 100644 --- a/src/common/inc/swref/published/hopper/gh100/hwproject.h +++ b/src/common/inc/swref/published/hopper/gh100/hwproject.h @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ #define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52 -#define NV_LTC_PRI_STRIDE 8192 -#define NV_LTS_PRI_STRIDE 512 -#define NV_FBPA_PRI_STRIDE 16384 -#define NV_SCAL_LITTER_NUM_FBPAS 24 #define NV_XPL_BASE_ADDRESS 540672 #define NV_XTL_BASE_ADDRESS 593920 +#define NV_FBPA_PRI_STRIDE 16384 diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_boot.h b/src/common/inc/swref/published/maxwell/gm107/dev_boot.h index c5a275b9b8..3d0a2d762a 100644 --- a/src/common/inc/swref/published/maxwell/gm107/dev_boot.h +++ b/src/common/inc/swref/published/maxwell/gm107/dev_boot.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,4 +40,7 @@ #define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */ #define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */ #define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ #endif // __gm107_dev_boot_h__ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_bus.h b/src/common/inc/swref/published/maxwell/gm107/dev_bus.h index b9a94bd990..e785d83c7a 100644 --- a/src/common/inc/swref/published/maxwell/gm107/dev_bus.h +++ b/src/common/inc/swref/published/maxwell/gm107/dev_bus.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,6 +48,18 @@ #define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_PBUS_BAR0_WINDOW_BASE_SHIFT 16 /* */ +#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */ +#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* RWXUF */ +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */ #define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */ #define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* RWXUF */ #define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */ @@ -64,4 +76,23 @@ #define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ #define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ #define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */ +#define NV_PBUS_BIND_STATUS 0x00001710 /* R--4R */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_IFB_PENDING 4:4 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_IFB_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_IFB_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING 5:5 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_IFB_OUTSTANDING_TRUE 0x00000001 /* R---V */ #endif // __gm107_dev_bus_h__ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_fifo.h b/src/common/inc/swref/published/maxwell/gm107/dev_fifo.h new file mode 100644 index 0000000000..2bb453af27 --- /dev/null +++ b/src/common/inc/swref/published/maxwell/gm107/dev_fifo.h @@ -0,0 +1,33 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gm107_dev_fifo_h__ +#define __gm107_dev_fifo_h__ +#define NV_PFIFO_FB_IFACE 0x000026f0 /* RW-4R */ +#define NV_PFIFO_FB_IFACE_CONTROL 0:0 /* RWIUF */ +#define NV_PFIFO_FB_IFACE_CONTROL_DISABLE 0x00000000 /* RW--V */ +#define NV_PFIFO_FB_IFACE_CONTROL_ENABLE 0x00000001 /* RWI-V */ +#define NV_PFIFO_FB_IFACE_STATUS 4:4 /* R-IUF */ +#define NV_PFIFO_FB_IFACE_STATUS_DISABLED 0x00000000 /* R---V */ +#define NV_PFIFO_FB_IFACE_STATUS_ENABLED 0x00000001 /* R-I-V */ +#endif // __gm107_dev_fifo_h__ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h b/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h index b5610c4240..4e53e8720b 100644 --- a/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h +++ b/src/common/inc/swref/published/maxwell/gm107/dev_nv_xve.h @@ -160,5 +160,7 @@ #define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */ -#define NV_XVE_CYA_2 0x00000704 /* RW-4R */ +#define NV_XVE_CYA_2 0x00000704 /* RW-4R */ +#define NV_XVE_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */ +#define NV_XVE_L1_PM_SUBSTATES_CTRL1 0x00000260 /* RW-4R */ #endif // __gm107_dev_nv_xve_h__ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_pri_ringstation_sys.h b/src/common/inc/swref/published/maxwell/gm107/dev_pri_ringstation_sys.h new file mode 100644 index 0000000000..c67b3b007d --- /dev/null +++ b/src/common/inc/swref/published/maxwell/gm107/dev_pri_ringstation_sys.h @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gm107_dev_pri_ringstation_sys_h__ +#define __gm107_dev_pri_ringstation_sys_h__ + +#define NV_PPRIV_SYS_PRI_ERROR_CODE 31:8 /* --XVF */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_FECS_ERR 0xBAD00F /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_PRI_TIMEOUT 0xBAD001 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_FB_ACK_TIMEOUT 0xBAD0B0 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_TIMEOUT 0xBADF10 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_DECODE 0xBADF11 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_RESET 0xBADF12 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_FLOORSWEEP 0xBADF13 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_STUCK_ACK 0xBADF14 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_0_EXPECTED_ACK 0xBADF15 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_FENCE_ERROR 0xBADF16 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_SUBID_ERROR 0xBADF17 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_ORPHAN 0xBADF20 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_DEAD_RING 0xBADF30 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_TRAP 0xBADF40 /* ----V */ +#define NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_CLIENT_ERR 0xBADF50 /* ----V */ + +#endif // __gm107_dev_pri_ringstation_sys_h__ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_ram.h b/src/common/inc/swref/published/maxwell/gm107/dev_ram.h index 53f25790ec..c2dd71839b 100644 --- a/src/common/inc/swref/published/maxwell/gm107/dev_ram.h +++ b/src/common/inc/swref/published/maxwell/gm107/dev_ram.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -55,4 +55,15 @@ #define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x00000080 /* RWI-V */ #define NV_RAMRL_ENTRY_SIZE 8 /* */ #define NV_RAMRL_ENTRY_TSG_LENGTH_MAX 0x00000020 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (128*32+1):(128*32+0) /* RWXUF */ +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_VOL (128*32+2):(128*32+2) /* RWXUF */ +#define NV_RAMIN_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_LO (128*32+31):(128*32+12) /* RWXUF */ +#define NV_RAMIN_PAGE_DIR_BASE_HI (129*32+7):(129*32+0) /* RWXUF */ +#define NV_RAMIN_ADR_LIMIT_LO (130*32+31):(130*32+12) /* RWXUF */ +#define NV_RAMIN_ADR_LIMIT_HI (131*32+7):(131*32+0) /* RWXUF */ #endif // __gm107_dev_ram_h__ diff --git a/src/common/inc/swref/published/maxwell/gm200/dev_boot.h b/src/common/inc/swref/published/maxwell/gm200/dev_boot.h new file mode 100644 index 0000000000..2614d92d23 --- /dev/null +++ b/src/common/inc/swref/published/maxwell/gm200/dev_boot.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gm200_dev_boot_h__ +#define __gm200_dev_boot_h__ +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ +#define NV_PMC_ENABLE_PMEDIA 4:4 /* */ +#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PWR 13:13 /* */ +#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PGRAPH 12:12 /* */ +#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_SEC 14:14 /* */ +#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE0 6:6 /* */ +#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE1 7:7 /* */ +#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE2 21:21 /* */ +#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC 15:15 /* */ +#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_NVENC0 18:18 /* */ +#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC1 19:19 /* */ +#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */ +#endif // __gm200_dev_boot_h__ diff --git a/src/common/inc/swref/published/maxwell/gm200/dev_fifo.h b/src/common/inc/swref/published/maxwell/gm200/dev_fifo.h new file mode 100644 index 0000000000..057068c047 --- /dev/null +++ b/src/common/inc/swref/published/maxwell/gm200/dev_fifo.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gm200_dev_fifo_h__ +#define __gm200_dev_fifo_h__ +#define NV_PFIFO_CFG0 0x00002004 /* R--4R */ +#define NV_PFIFO_CFG0_NUM_PBDMA 7:0 /* R-IUF */ +#endif // __gm200_dev_fifo_h__ diff --git a/src/common/inc/swref/published/nv_arch.h b/src/common/inc/swref/published/nv_arch.h index b09551c75b..1147b52b6b 100644 --- a/src/common/inc/swref/published/nv_arch.h +++ b/src/common/inc/swref/published/nv_arch.h @@ -47,7 +47,6 @@ #define GPU_ARCHITECTURE_TURING GPU_ARCHITECTURE(_CLASSIC, 0x0160) #define GPU_ARCHITECTURE_AMPERE GPU_ARCHITECTURE(_CLASSIC, 0x0170) #define GPU_ARCHITECTURE_HOPPER GPU_ARCHITECTURE(_CLASSIC, 0x0180) - #define GPU_ARCHITECTURE_ADA GPU_ARCHITECTURE(_CLASSIC, 0x0190) #define GPU_ARCHITECTURE_T12X GPU_ARCHITECTURE(_TEGRA, 0x0040) @@ -93,18 +92,11 @@ #define GPU_IMPLEMENTATION_GA106 0x06 #define GPU_IMPLEMENTATION_GA107 0x07 #define GPU_IMPLEMENTATION_GA102F 0x0F - #define GPU_IMPLEMENTATION_GH100 0x00 - - #define GPU_IMPLEMENTATION_AD102 0x02 - #define GPU_IMPLEMENTATION_AD103 0x03 - #define GPU_IMPLEMENTATION_AD104 0x04 - #define GPU_IMPLEMENTATION_AD106 0x06 - #define GPU_IMPLEMENTATION_AD107 0x07 #define GPU_IMPLEMENTATION_T124 0x00 diff --git a/src/common/inc/swref/published/nv_ref.h b/src/common/inc/swref/published/nv_ref.h index 5db05b3b8e..4f85cf1586 100644 --- a/src/common/inc/swref/published/nv_ref.h +++ b/src/common/inc/swref/published/nv_ref.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h b/src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h index a9e9ee1e03..980fcbb714 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_fsp_pri.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -30,4 +30,21 @@ #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */ #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ + +#define NV_PFSP_QUEUE_HEAD(i) (0x008F2c00+(i)*8) /* RW-4A */ +#define NV_PFSP_QUEUE_TAIL(i) (0x008F2c04+(i)*8) /* RW-4A */ + +#define NV_PFSP_MSGQ_HEAD(i) (0x008F2c80+(i)*8) /* RW-4A */ +#define NV_PFSP_MSGQ_TAIL(i) (0x008F2c84+(i)*8) /* RW-4A */ + +#define NV_PFSP_EMEMC(i) (0x008F2ac0+(i)*8) /* RW-4A */ +#define NV_PFSP_EMEMC_OFFS 7:2 /* RWIVF */ +#define NV_PFSP_EMEMC_BLK 15:8 /* RWIVF */ +#define NV_PFSP_EMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PFSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PFSP_EMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PFSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ + +#define NV_PFSP_EMEMD(i) (0x008F2ac4+(i)*8) /* RW-4A */ + #endif // __ls10_dev_fsp_pri_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h index 175a7de3c0..bbd4280c74 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -300,6 +300,51 @@ #define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_R4_RETRY_CLEAR 0x00000001 /* -W--V */ #define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY 8:8 /* -WXVF */ #define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0 0x00002e00 /* RW-4R */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0__PRIV_LEVEL_MASK 0x00002ff4 /* */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0 31:0 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1 0x00002e04 /* RW-4R */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1__PRIV_LEVEL_MASK 0x00002ff4 /* */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1 31:0 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2 0x00002e08 /* RW-4R */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2__PRIV_LEVEL_MASK 0x00002ff4 /* */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0 31:0 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3 0x00002e0c /* RW-4R */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3__PRIV_LEVEL_MASK 0x00002ff4 /* */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1 31:0 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4 0x00002e10 /* RW-4R */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4__PRIV_LEVEL_MASK 0x00002ff4 /* */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_COM_OUT 0:0 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_COM_OUT_INIT 0x00000001 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_SKIP_OUT 1:1 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_MASK_SKIP_OUT_INIT 0x00000001 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_SEND_DATA_OUT 2:2 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_SEND_DATA_OUT_INIT 0x00000001 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT 11:3 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT_INIT 0x00000100 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_CONFIG 0x00002e14 /* RW-4R */ +#define NV_NVLDL_TXIOBIST_CONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */ +#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST 0:0 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN 1:1 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD 2:2 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT 3:3 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT_NRZ 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT_PAM4 0x00000001 /* RW--V */ +#define NV_NVLDL_TXIOBIST_CONFIGREG 0x00002e18 /* RW-4R */ +#define NV_NVLDL_TXIOBIST_CONFIGREG__PRIV_LEVEL_MASK 0x00002ff0 /* */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN 2:2 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN 3:3 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN_INIT 0x00000000 /* RWE-V */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN 17:17 /* RWEUF */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN_INIT 0x00000000 /* RWE-V */ #define NV_NVLDL_RX_SLSM_STATUS_RX 0x00003014 /* R--4R */ #define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE 3:0 /* R-EVF */ #define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE_STABLE 0x00000000 /* R-E-V */ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h index 7a7d50d07f..392f0b7c64 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvldl_ip_addendum.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,18 @@ #ifndef __ls10_dev_nvldl_ip_addendum_h__ #define __ls10_dev_nvldl_ip_addendum_h__ +#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SKIP_SYMBOL_0_SYMBOL 0x7845bdcd /* RWIUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_3_SKIP_SYMBOL_1_SYMBOL 0x124507ff /* RWIUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_0_COM_SYMBOL_0_SYMBOL 0xad3d6c5b /* RWIUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_COM_SYMBOL_1_SYMBOL 0xbe35879e /* RWIUF */ +#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_4_RESET_WORD_CNT_OUT_COUNT 0x000000bd /* RWI-V */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST_ENABLE 0x00000001 /* RWI-V */ +#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD_ENABLE 0x00000001 /* RWI-V */ + #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN 2:0 #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT 0x00000003 #define NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP 3:3 diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h index a4ac4bf5de..088a0de01b 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -635,4 +635,11 @@ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT 28:28 /* RWIVF */ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */ #define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1 0x00000688 /* RW-4R */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT 1:1 /* RWIVF */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */ +#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_AN1_PWRM_L1_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */ +#define NV_NVLIPT_LNK_SCRATCH_WARM 0x000007c0 /* RW-4R */ +#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA 31:0 /* RWEVF */ +#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */ #endif // __ls10_dev_nvlipt_lnk_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h b/src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h index ba00c7f32d..9f40a4cba1 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_pmgr.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -82,4 +82,18 @@ #define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER 10:10 /* */ #define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_NO 0x00000000 /* */ #define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_YES 0x00000001 /* */ +#define NV_GPIO_OUTPUT_CNTL(i) (0x00021200 +((i) * 0x4)) /* RW-4A */ +#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT 12:12 /* RWIVF */ +#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_INIT 0x00000000 /* R-I-V */ +#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_0 0x00000000 /* RW--V */ +#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_1 0x00000001 /* RW--V */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1 0x00021644 /* RWI4R */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000001 /* RWI-V */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_DISABLED 0x00000000 /* RW--V */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_ENABLED 0x00000001 /* RW--V */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000001 /* RWI-V */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_DISABLED 0x00000000 /* RW--V */ +#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_ENABLED 0x00000001 /* RW--V */ #endif // __ls10_dev_pmgr_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h b/src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h index af31411c3f..6f99a55e4c 100644 --- a/src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h +++ b/src/common/inc/swref/published/nvswitch/ls10/dev_timer_ip.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,14 +24,18 @@ #ifndef __ls10_dev_timer_ip_h__ #define __ls10_dev_timer_ip_h__ /* This file is autogenerated. Do not edit */ -#define NV_PTIMER 0x00000FFF:0x00000000 /* RW--D */ +#define NV_PTIMER 0x00000FFF:0x00000000 /* RW--D */ #define NV_PTIMER_PRI_TMR_CG1 0x00000600 /* RW-4R */ #define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */ #define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ -#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */ +#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */ #define NV_PTIMER_PRI_TMR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTIMER_PRI_TMR_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */ #define NV_PTIMER_PRI_TMR_CG1_SLCG__PROD 0x00000000 /* RW--V */ +#define NV_PTIMER_TIME_0 0x00000400 /* R--4R */ +#define NV_PTIMER_TIME_0_NSEC 31:5 /* R-XUF */ +#define NV_PTIMER_TIME_1 0x00000410 /* R--4R */ +#define NV_PTIMER_TIME_1_NSEC 28:0 /* R-XUF */ #endif // __ls10_dev_timer_ip_h__ diff --git a/src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h b/src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h new file mode 100644 index 0000000000..93d2c403a9 --- /dev/null +++ b/src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the Software), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ls10_ptop_discovery_ip_h__ +#define __ls10_ptop_discovery_ip_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */ +#endif // __ls10_ptop_discovery_ip_h__ diff --git a/src/common/inc/swref/published/pascal/gp100/dev_boot.h b/src/common/inc/swref/published/pascal/gp100/dev_boot.h index 4f032d55e5..b0bb982234 100644 --- a/src/common/inc/swref/published/pascal/gp100/dev_boot.h +++ b/src/common/inc/swref/published/pascal/gp100/dev_boot.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,4 +44,53 @@ #define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */ #define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */ #define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */ +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ +#define NV_PMC_ENABLE_PMEDIA 4:4 /* */ +#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PWR 13:13 /* */ +#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PGRAPH 12:12 /* */ +#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_SEC 14:14 /* */ +#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE0 6:6 /* */ +#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE1 7:7 /* */ +#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE2 21:21 /* */ +#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE3 22:22 /* */ +#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE4 23:23 /* */ +#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE5 24:24 /* */ +#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC 15:15 /* */ +#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_NVENC0 18:18 /* */ +#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC1 19:19 /* */ +#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC2 4:4 /* */ +#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */ #endif // __gp100_dev_boot_h__ diff --git a/src/common/inc/swref/published/pascal/gp100/dev_fb.h b/src/common/inc/swref/published/pascal/gp100/dev_fb.h new file mode 100644 index 0000000000..17c1a581c4 --- /dev/null +++ b/src/common/inc/swref/published/pascal/gp100/dev_fb.h @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef __gp100_dev_fb_h__ +#define __gp100_dev_fb_h__ + +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL 0x00000004 /* */ +#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ACK 8:7 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */ +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--T */ + +#endif // __gv100_dev_fb_h__ diff --git a/src/common/inc/swref/published/pascal/gp102/dev_boot.h b/src/common/inc/swref/published/pascal/gp102/dev_boot.h new file mode 100644 index 0000000000..ff7aa8c877 --- /dev/null +++ b/src/common/inc/swref/published/pascal/gp102/dev_boot.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gp102_dev_boot_h__ +#define __gp102_dev_boot_h__ +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ +#define NV_PMC_ENABLE_PMEDIA 4:4 /* */ +#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PWR 13:13 /* */ +#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PGRAPH 12:12 /* */ +#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_SEC 14:14 /* */ +#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE0 6:6 /* */ +#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE1 7:7 /* */ +#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE2 21:21 /* */ +#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE3 22:22 /* */ +#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE4 23:23 /* */ +#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE5 24:24 /* */ +#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC 15:15 /* */ +#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_NVENC0 18:18 /* */ +#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC1 19:19 /* */ +#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC2 4:4 /* */ +#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */ +#endif // __gp102_dev_boot_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_boot.h b/src/common/inc/swref/published/turing/tu102/dev_boot.h index 24ef324144..3a41432b39 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_boot.h +++ b/src/common/inc/swref/published/turing/tu102/dev_boot.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -49,7 +49,74 @@ #define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */ #define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */ #define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */ +#define NV_PMC_ENABLE_PMEDIA 4:4 /* */ +#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PWR 13:13 /* */ +#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE0 6:6 /* */ +#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE1 7:7 /* */ +#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE2 21:21 /* */ +#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE3 22:22 /* */ +#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE4 23:23 /* */ +#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE5 24:24 /* */ +#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE6 9:9 /* */ +#define NV_PMC_ENABLE_CE6_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE6_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE7 10:10 /* */ +#define NV_PMC_ENABLE_CE7_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE7_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE8 11:11 /* */ +#define NV_PMC_ENABLE_CE8_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE8_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PGRAPH 12:12 /* */ +#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_SEC 14:14 /* */ +#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */ #define NV_PMC_ENABLE_NVDEC 15:15 /* */ #define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ #define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC0 15:15 /* */ +#define NV_PMC_ENABLE_NVDEC0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVDEC0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC1 16:16 /* */ +#define NV_PMC_ENABLE_NVDEC1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVDEC1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC2 20:20 /* */ +#define NV_PMC_ENABLE_NVENC0 18:18 /* */ +#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC1 19:19 /* */ +#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC2 20:20 /* */ +#define NV_PMC_ENABLE_NVDEC2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVDEC2_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */ +#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_NVJPG0 31:31 /* */ +#define NV_PMC_ENABLE_NVJPG0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVJPG0_ENABLED 0x00000001 /* */ #endif // __tu102_dev_boot_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_bus.h b/src/common/inc/swref/published/turing/tu102/dev_bus.h index a3371152f6..852c606aa6 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_bus.h +++ b/src/common/inc/swref/published/turing/tu102/dev_bus.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,4 +35,47 @@ #define NV_PBUS_IFR_FMT_FIXED2 0x00000008 /* */ #define NV_PBUS_IFR_FMT_FIXED2_TOTAL_DATA_SIZE 19:0 /* */ +#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */ +#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */ +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */ +#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */ +#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* */ +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */ +#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */ +#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */ +#define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */ +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */ +#define NV_PBUS_BAR2_BLOCK_RESERVED 30:30 /* */ +#define NV_PBUS_BAR2_BLOCK_RESERVED_DEFAULT 0x00000001 /* */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */ + #endif // __tu102_dev_bus_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_fault.h b/src/common/inc/swref/published/turing/tu102/dev_fault.h new file mode 100644 index 0000000000..b965ade42c --- /dev/null +++ b/src/common/inc/swref/published/turing/tu102/dev_fault.h @@ -0,0 +1,149 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ad102_dev_fault_h__ +#define __ad102_dev_fault_h__ + +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC0 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC1 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC2 26 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG0 24 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */ + +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */ + +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */ +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */ +#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */ +#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ + +#endif // _ad102_dev_fault_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_fb.h b/src/common/inc/swref/published/turing/tu102/dev_fb.h index 4c9fb4632d..b4f1ae5c62 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_fb.h +++ b/src/common/inc/swref/published/turing/tu102/dev_fb.h @@ -38,4 +38,37 @@ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */ + +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ +#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ + #endif // __tu102_dev_fb_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_fbpa.h b/src/common/inc/swref/published/turing/tu102/dev_fbpa.h new file mode 100644 index 0000000000..c1465c9539 --- /dev/null +++ b/src/common/inc/swref/published/turing/tu102/dev_fbpa.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __tu102_dev_fbpa_h_ +#define __tu102_dev_fbpa_h_ + +#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 2 /* */ +#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x00900488+(i)*4) /* RW-4A */ +#endif // __tu102_dev_fbpa_h_ diff --git a/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h b/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h index 51f6c47255..4f89a4ebc5 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h +++ b/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h @@ -24,6 +24,7 @@ #ifndef __tu102_dev_gc6_island_h__ #define __tu102_dev_gc6_island_h__ +#define NV_PGC6 0x118fff:0x118000 /* RW--D */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ diff --git a/src/common/inc/swref/published/turing/tu102/dev_gsp.h b/src/common/inc/swref/published/turing/tu102/dev_gsp.h index 7a00e288d0..0e6e4a3608 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_gsp.h +++ b/src/common/inc/swref/published/turing/tu102/dev_gsp.h @@ -38,5 +38,22 @@ #define NV_PGSP_QUEUE_HEAD(i) (0x110c00+(i)*8) /* RW-4A */ #define NV_PGSP_QUEUE_HEAD__SIZE_1 8 /* */ #define NV_PGSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */ +#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMC__SIZE_1 4 /* */ +#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */ +#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */ +#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */ +#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */ +#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */ +#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */ +#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */ +#define NV_PGSP_EMEMD__SIZE_1 4 /* */ +#define NV_PGSP_EMEMD_DATA 31:0 /* RW-VF */ #endif // __tu102_dev_gsp_h__ diff --git a/src/common/inc/swref/published/hopper/gh100/dev_ltc.h b/src/common/inc/swref/published/turing/tu102/dev_ltc.h similarity index 95% rename from src/common/inc/swref/published/hopper/gh100/dev_ltc.h rename to src/common/inc/swref/published/turing/tu102/dev_ltc.h index f1eec19372..0206ed7e7a 100644 --- a/src/common/inc/swref/published/hopper/gh100/dev_ltc.h +++ b/src/common/inc/swref/published/turing/tu102/dev_ltc.h @@ -21,8 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef __gh100_dev_ltc_h_ -#define __gh100_dev_ltc_h_ +#ifndef __tu102_dev_ltc_h_ +#define __tu102_dev_ltc_h_ #define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */ #define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */ @@ -30,4 +30,4 @@ #define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */ #define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */ -#endif // __gh100_dev_ltc_h_ +#endif // __tu102_dev_ltc_h_ diff --git a/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h b/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h index a5c43d5eba..f4d62d4924 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h +++ b/src/common/inc/swref/published/turing/tu102/dev_nv_xve.h @@ -24,6 +24,10 @@ #ifndef __tu102_dev_nv_xve_h__ #define __tu102_dev_nv_xve_h__ #define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */ +#define NV_XVE_ID 0x00000000 /* R--4R */ +#define NV_XVE_ID_VENDOR 15:0 /* C--VF */ +#define NV_XVE_ID_VENDOR_NVIDIA 0x000010DE /* C---V */ +#define NV_XVE_SW_RESET 0x00000718 /* RW-4R */ #define NV_XVE_DEVICE_CAPABILITY 0x0000007C /* R--4R */ #define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */ #define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */ @@ -35,6 +39,10 @@ #define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */ #define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */ +#define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */ #define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */ #define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */ #define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */ diff --git a/src/common/inc/swref/published/turing/tu102/dev_vm.h b/src/common/inc/swref/published/turing/tu102/dev_vm.h index d444ce272b..33fc29cebb 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_vm.h +++ b/src/common/inc/swref/published/turing/tu102/dev_vm.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,6 +23,8 @@ #ifndef __tu102_dev_vm_h__ #define __tu102_dev_vm_h__ +#define NV_VIRTUAL_FUNCTION_PRIV 0x0002FFFF:0x00000000 /* RW--D */ +#define NV_VIRTUAL_FUNCTION 0x0003FFFF:0x00030000 /* RW--D */ #define NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET 0x00BBFFFF:0x00B80000 /* RW--D */ #define NV_VIRTUAL_FUNCTION_PRIV_L2_SYSMEM_INVALIDATE 0x00000F00 /* RW-4R */ #define NV_VIRTUAL_FUNCTION_PRIV_L2_PEERMEM_INVALIDATE 0x00000F04 /* RW-4R */ @@ -97,7 +99,23 @@ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE(i) (0x00003010+(i)*32) /* RW-4A */ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO 0x00003080 /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI 0x00003084 /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO 0x00003088 /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI 0x0000308C /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO 0x00003090 /* R--4R */ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS 0x00003094 /* RW-4R */ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB 0x000030A0 /* RW-4R */ #define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWEVF */ @@ -210,5 +228,51 @@ #define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */ #define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */ #define NV_VIRTUAL_FUNCTION_ERR_CONT 0x30094 /* R--4R */ -#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK 0x00000F40 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK__VFALIAS NV_VBUS_VF_BAR1_BLOCK(f) /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MAP 29:0 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK 0x00000F48 /* RW-4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK__VFALIAS NV_VBUS_VF_BAR2_BLOCK(f) /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MAP 29:0 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS 0x00000F50 /* R--4R */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS__VFALIAS NV_VBUS_VF_BIND_STATUS(f) /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i) (0x0001000C+(i)*16) /* RW-4A */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */ +#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */ #endif // __tu102_dev_vm_h__ diff --git a/src/common/inc/swref/published/turing/tu102/hwproject.h b/src/common/inc/swref/published/turing/tu102/hwproject.h index 26bb4a548a..586adf3daa 100644 --- a/src/common/inc/swref/published/turing/tu102/hwproject.h +++ b/src/common/inc/swref/published/turing/tu102/hwproject.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,5 +25,10 @@ #define __tu102_hwproject_h__ #define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 47 +#define NV_HOST_NUM_PBDMA 12 +#define NV_SCAL_LITTER_NUM_FBPAS 16 +#define NV_FBPA_PRI_STRIDE 16384 +#define NV_LTC_PRI_STRIDE 8192 +#define NV_LTS_PRI_STRIDE 512 #endif // __tu102_hwproject_h__ diff --git a/src/common/inc/swref/published/volta/gv100/dev_boot.h b/src/common/inc/swref/published/volta/gv100/dev_boot.h index 425fe1d86a..f87659344d 100644 --- a/src/common/inc/swref/published/volta/gv100/dev_boot.h +++ b/src/common/inc/swref/published/volta/gv100/dev_boot.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,4 +44,62 @@ #define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */ #define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */ #define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */ +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ +#define NV_PMC_ENABLE_PMEDIA 4:4 /* */ +#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PWR 13:13 /* */ +#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PGRAPH 12:12 /* */ +#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_SEC 14:14 /* */ +#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE0 6:6 /* */ +#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE1 7:7 /* */ +#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE2 21:21 /* */ +#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE3 22:22 /* */ +#define NV_PMC_ENABLE_CE3_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE3_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE4 23:23 /* */ +#define NV_PMC_ENABLE_CE4_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE4_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE5 24:24 /* */ +#define NV_PMC_ENABLE_CE5_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE5_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE6 9:9 /* */ +#define NV_PMC_ENABLE_CE6_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE6_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE7 10:10 /* */ +#define NV_PMC_ENABLE_CE7_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE7_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE8 11:11 /* */ +#define NV_PMC_ENABLE_CE8_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE8_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC 15:15 /* */ +#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_NVENC0 18:18 /* */ +#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC1 19:19 /* */ +#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC2 4:4 /* */ +#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */ #endif // __gv100_dev_boot_h__ diff --git a/src/common/inc/swref/published/volta/gv100/dev_fault.h b/src/common/inc/swref/published/volta/gv100/dev_fault.h index 923d21c59b..bcbd6e1e06 100644 --- a/src/common/inc/swref/published/volta/gv100/dev_fault.h +++ b/src/common/inc/swref/published/volta/gv100/dev_fault.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,4 +24,42 @@ #ifndef __gv100_dev_fault_h__ #define __gv100_dev_fault_h__ #define NV_PFAULT_MMU_ENG_ID_GRAPHICS 64 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */ +#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */ +#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */ +#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */ +#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */ +#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */ +#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */ +#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */ +#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */ +#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */ +#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */ +#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */ +#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */ #endif // __gv100_dev_fault_h__ diff --git a/src/common/inc/swref/published/volta/gv100/dev_fb.h b/src/common/inc/swref/published/volta/gv100/dev_fb.h index 781fef5e29..ca9045fb24 100644 --- a/src/common/inc/swref/published/volta/gv100/dev_fb.h +++ b/src/common/inc/swref/published/volta/gv100/dev_fb.h @@ -73,6 +73,8 @@ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK 31:31 /* -WIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK_INIT 0x0 /* -WI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK_CLR 0x1 /* -W--V */ +#define NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER 0 +#define NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER 1 #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET(i) (0x00100E2C+(i)*20) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */ @@ -95,6 +97,44 @@ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW 31:31 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR 31:12 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR 31:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID 8:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE 11:10 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR 31:12 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR 31:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE 4:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT 7:7 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT 14:8 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE 19:16 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_READ 0x00000000 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_WRITE 0x00000001 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_ATOMIC 0x00000002 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PREFETCH 0x00000003 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_READ 0x00000000 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_READ 0x00000008 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE 20:20 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID 28:24 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE 29:29 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN 30:30 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INFO_VALID 31:31 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INFO_VALID_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS 0x00100E60 /* RW-4R */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */ @@ -159,4 +199,15 @@ #define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_SET 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */ #endif // __gv100_dev_fb_h__ diff --git a/src/common/inc/swref/published/volta/gv11b/dev_boot.h b/src/common/inc/swref/published/volta/gv11b/dev_boot.h new file mode 100644 index 0000000000..74fe8b2188 --- /dev/null +++ b/src/common/inc/swref/published/volta/gv11b/dev_boot.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gv11b_dev_boot_h__ +#define __gv11b_dev_boot_h__ +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ +#define NV_PMC_ENABLE_PMEDIA 4:4 /* */ +#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PWR 13:13 /* */ +#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PGRAPH 12:12 /* */ +#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_SEC 14:14 /* */ +#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE0 6:6 /* */ +#define NV_PMC_ENABLE_CE0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE1 7:7 /* */ +#define NV_PMC_ENABLE_CE1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_CE2 21:21 /* */ +#define NV_PMC_ENABLE_CE2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_CE2_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVDEC 15:15 /* */ +#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_NVENC0 18:18 /* */ +#define NV_PMC_ENABLE_NVENC0_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC0_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC1 19:19 /* */ +#define NV_PMC_ENABLE_NVENC1_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC1_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVENC2 4:4 /* */ +#define NV_PMC_ENABLE_NVENC2_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_NVENC2_ENABLED 0x00000001 /* */ +#endif // __gv11b_dev_boot_h__ diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.c b/src/common/modeset/hdmipacket/nvhdmipkt.c index 4960430c4d..07dd704eb7 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt.c @@ -243,7 +243,7 @@ NvHdmiPkt_PacketWrite(NvHdmiPkt_Handle libHandle, ((infoframeType == hdmi_pktType_GamutMetadata) && (packetLen < sizeof(NVT_GAMUT_METADATA))) || ((infoframeType == hdmi_pktType_ExtendedMetadata) && (packetLen < sizeof(NVT_EXTENDED_METADATA_PACKET_INFOFRAME)))|| ((infoframeType == hdmi_pktType_VendorSpecInfoFrame) && (packetLen < 8)) || - ((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < sizeof(NVT_VIDEO_INFOFRAME))) || + ((infoframeType == hdmi_pktType_AviInfoFrame) && (packetLen < 13)) || ((infoframeType == hdmi_pktType_SrcProdDescInfoFrame) && (packetLen < sizeof(NVT_SPD_INFOFRAME))) || ((infoframeType == hdmi_pktType_DynamicRangeMasteringInfoFrame) && (packetLen < sizeof(NVT_HDR_INFOFRAME)))) // Unused: hdmi_pktType_AudioClkRegeneration diff --git a/src/common/modeset/hdmipacket/nvhdmipkt.h b/src/common/modeset/hdmipacket/nvhdmipkt.h index deb9908572..f55b4ac2ad 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt.h +++ b/src/common/modeset/hdmipacket/nvhdmipkt.h @@ -127,6 +127,12 @@ typedef enum _NVHDMIPKT_TC DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _SINGLE, _DIS) | DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _CHKSUM_HW, _EN)), + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_EVERY_FRAME_SW_CHECKSUM = + (DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _ENABLE, _EN) | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _OTHER, _DIS) | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _SINGLE, _DIS) | + DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _CHKSUM_HW, _DIS)), + NVHDMIPKT_TRANSMIT_CONTROL_ENABLE_SINGLE_FRAME = (DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _ENABLE, _EN) | DRF_DEF(_HDMI_PKT, _TRANSMIT_CTRL, _OTHER, _DIS) | diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c index 46537360b0..e6b85ed541 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_9171.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_9171.c @@ -36,7 +36,6 @@ #include "ctrl/ctrl0073/ctrl0073specific.h" #define NVHDMIPKT_9171_INVALID_PKT_TYPE ((NV9171_SF_HDMI_INFO_IDX_VSI) + 1) -#define NVHDMIPKT_CTAIF_MAX_PKT_BYTES 31 // 3 bytes header + 28 bytes data (CTA infoframe max payload size) #define NVHDMIPKT_9171_MAX_PKT_BYTES_AVI 17 // 3 bytes header + 14 bytes data NVHDMIPKT_RESULT @@ -157,8 +156,7 @@ hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis, if (packetLen > NVHDMIPKT_9171_MAX_PKT_BYTES_AVI) { - NvHdmiPkt_Print(pThis, "ERROR - input AVI packet length incorrect. Write will be capped to max allowable bytes"); - NvHdmiPkt_Assert(0); + NvHdmiPkt_Print(pThis, "WARNING - input AVI packet length incorrect. Write will be capped to max allowable bytes"); } data = REG_RD32(pBaseReg, NV9171_SF_HDMI_AVI_INFOFRAME_HEADER(head)); diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_C671.c b/src/common/modeset/hdmipacket/nvhdmipkt_C671.c index 62ef36004c..4298bd0f70 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_C671.c +++ b/src/common/modeset/hdmipacket/nvhdmipkt_C671.c @@ -777,11 +777,15 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis, calcBppMinMax(pSrcCaps, pSinkCaps, pVidTransInfo, &bppMinX16, &bppMaxX16); bCanUseDSC = evaluateIsDSCPossible(pThis, pSrcCaps, pSinkCaps, pVidTransInfo, &frlParams); + const NvU32 numHeadsDrivingSink = pVidTransInfo->bDualHeadMode ? 2 : 1; // Input validation + // Note, maxNumHztSlices src cap is per head. account for total number of heads driving the sink if ((pClientCtrl->forceFRLRate && (pClientCtrl->frlRate > pSinkCaps->linkMaxFRLRate)) || (pClientCtrl->enableDSC && !bCanUseDSC) || - (pClientCtrl->forceSliceCount && (pClientCtrl->sliceCount > (NvU32)(NV_MIN(pSrcCaps->dscCaps.maxNumHztSlices, pSinkCaps->pHdmiForumInfo->dsc_MaxSlices)))) || + (pClientCtrl->forceSliceCount && (pClientCtrl->sliceCount > + (NvU32)(NV_MIN(pSrcCaps->dscCaps.maxNumHztSlices * numHeadsDrivingSink, + pSinkCaps->pHdmiForumInfo->dsc_MaxSlices)))) || (pClientCtrl->forceSliceWidth && (pClientCtrl->sliceWidth > NV_MIN(pSrcCaps->dscCaps.maxWidthPerSlice, MAX_RECONSTRUCTED_HACTIVE_PIXELS))) || (pClientCtrl->forceBppx16 && ((pClientCtrl->bitsPerPixelX16 < bppMinX16) || (pClientCtrl->bitsPerPixelX16 > bppMaxX16))) || (pClientCtrl->forceBppx16 && !pSinkCaps->pHdmiForumInfo->dsc_All_bpp)) @@ -1171,20 +1175,18 @@ hdmiQueryFRLConfigC671(NVHDMIPKT_CLASS *pThis, DSC_GENERATE_PPS_OPAQUE_WORKAREA *pDscScratchBuffer = NULL; pDscScratchBuffer = (DSC_GENERATE_PPS_OPAQUE_WORKAREA*)pThis->callback.malloc(pThis->cbHandle, sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA)); - if ((DSC_GeneratePPS(&dscInfo, &dscModesetInfo, &warData, availableLinkBw, + pDscScratchBuffer, pFRLConfig->dscInfo.pps, - &bitsPerPixelX16, - pDscScratchBuffer)) != NVT_STATUS_SUCCESS) + &bitsPerPixelX16)) != NVT_STATUS_SUCCESS) { NvHdmiPkt_Print(pThis, "ERROR - DSC PPS calculation failed."); NvHdmiPkt_Assert(0); result = NVHDMIPKT_FAIL; } - if (pDscScratchBuffer != NULL) { pThis->callback.free(pThis->cbHandle, pDscScratchBuffer); diff --git a/src/common/modeset/hdmipacket/nvhdmipkt_internal.h b/src/common/modeset/hdmipacket/nvhdmipkt_internal.h index 68942a8d45..e631f3af01 100644 --- a/src/common/modeset/hdmipacket/nvhdmipkt_internal.h +++ b/src/common/modeset/hdmipacket/nvhdmipkt_internal.h @@ -34,6 +34,9 @@ #define toHdmiPktHandle(p) ((NvHdmiPkt_Handle)(p)) #define fromHdmiPktHandle(h) ((NVHDMIPKT_CLASS*)(h)) +// CTA infoframe max payload size +#define NVHDMIPKT_CTAIF_MAX_PKT_BYTES 31 // 3 bytes header + 28 bytes data + extern void initializeHdmiPktInterface0073(NVHDMIPKT_CLASS*); extern void initializeHdmiPktInterface9171(NVHDMIPKT_CLASS*); extern void initializeHdmiPktInterface9271(NVHDMIPKT_CLASS*); diff --git a/src/common/modeset/timing/nvt_dsc_pps.c b/src/common/modeset/timing/nvt_dsc_pps.c index 3cd00ef629..a8793a816f 100644 --- a/src/common/modeset/timing/nvt_dsc_pps.c +++ b/src/common/modeset/timing/nvt_dsc_pps.c @@ -38,19 +38,10 @@ /* ------------------------ Macros ----------------------------------------- */ -// -// DSC_Print macro was for debugging purposes in early development of -// DSC PPS library. The print statements no longer get logged -// inside any client logger. But the lines of print in this file are useful -// for browsing code, hence this DSC_Print is left as a stub -// definition intentionally to help reader understand the PPS code. -// -#define DSC_Print(...) do { } while(0) - -#define MIN_CHECK(s,a,b) { if((a)<(b)) { DSC_Print("%s (=%u) needs to be larger than %u",s,a,b); return (NVT_STATUS_ERR);} } -#define RANGE_CHECK(s,a,b,c) { if((((NvS32)(a))<(NvS32)(b))||(((NvS32)(a))>(NvS32)(c))) { DSC_Print("%s (=%u) needs to be between %u and %u",s,a,b,c); return (NVT_STATUS_ERR);} } -#define ENUM2_CHECK(s,a,b,c) { if(((a)!=(b))&&((a)!=(c))) { DSC_Print("%s (=%u) needs to be %u or %u",s,a,b,c); return (NVT_STATUS_ERR);} } -#define ENUM3_CHECK(s,a,b,c,d) { if(((a)!=(b))&&((a)!=(c))&&((a)!=(d))) { DSC_Print("%s (=%u) needs to be %u, %u or %u",s,a,b,c,d); return (NVT_STATUS_ERR);} } +#define MIN_CHECK(s,a,b) { if((a)<(b)) { return (NVT_STATUS_ERR);} } +#define RANGE_CHECK(s,a,b,c) { if((((NvS32)(a))<(NvS32)(b))||(((NvS32)(a))>(NvS32)(c))) { return (NVT_STATUS_ERR);} } +#define ENUM2_CHECK(s,a,b,c) { if(((a)!=(b))&&((a)!=(c))) { return (NVT_STATUS_ERR);} } +#define ENUM3_CHECK(s,a,b,c,d) { if(((a)!=(b))&&((a)!=(c))&&((a)!=(d))) { return (NVT_STATUS_ERR);} } #define MAX(a,b) (((a)>=(b) || (b == 0xffffffff))?(a):(b)) #define MIN(a,b) ((a)>=(b)?(b):(a)) #define CLAMP(a,b,c) ((a)<=(b)?(b):((a)>(c)?(c):(a))) @@ -182,7 +173,7 @@ typedef struct _DSC_GENERATE_PPS_WORKAREA } DSC_GENERATE_PPS_WORKAREA; // Compile time check to ensure Opaque workarea buffer size always covers required work area. -ct_assert(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA) >= sizeof(DSC_GENERATE_PPS_WORKAREA)); +ct_assert(sizeof(DSC_GENERATE_PPS_OPAQUE_WORKAREA) == sizeof(DSC_GENERATE_PPS_WORKAREA)); /* ------------------------ Global Variables ------------------------------- */ @@ -406,13 +397,11 @@ static const NvU32 rcBufThresh[] = { 896, 1792, 2688, 3584, 4480, 5376, 6272, 67 /* ------------------------ Static Variables ------------------------------- */ /* ------------------------ Private Functions Prototype--------------------- */ - static NvU32 DSC_GetHigherSliceCount ( NvU32 common_slice_count_mask, NvU32 desired_slice_num, - NvU32 dual_mode, NvU32 *new_slice_num ); static NvU32 DSC_AlignDownForBppPrecision(NvU32 bitsPerPixelX16, NvU32 bitsPerPixelPrecision); @@ -423,6 +412,21 @@ DSC_GetPeakThroughputMps(NvU32 peak_throughput); static NvU32 DSC_SliceCountMaskforSliceNum (NvU32 slice_num); +static NvU32 +DSC_GetSliceCountMask(NvU32 maxSliceNum, NvBool bInclusive); + +static NVT_STATUS +DSC_GetMinSliceCountForMode +( + NvU32 picWidth, + NvU32 pixelClkMhz, + NvU32 maxSliceWidth, + NvU32 peakThroughPutMps, + NvU32 maxSliceCount, + NvU32 commonSliceCountMask, + NvU32 *pMinSliceCount +); + /* ------------------------ Private Functions ------------------------------ */ /* @@ -1037,6 +1041,11 @@ DSC_PpsConstruct NvU32 i; NvU32 pps[96]; + if (data == NULL) + { + return; + } + pps[0] = (in->dsc_version_major << 4) | (in->dsc_version_minor & 0xF); pps[1] = in->pps_identifier; pps[2] = 0; @@ -1219,6 +1228,59 @@ DSC_GetPeakThroughputMps(NvU32 peak_throughput) return peak_throughput_mps; } +/* + * @brief Get minimum slice count needed to support the mode. + * + * @param[in] picWidth active width of the mode. + * @param[in] pixelClkMhz pixel clock in Mhz of the mode. + * @param[in] maxSliceWidth Max slice with considering gpu and sink + * @param[in] peakThroughPutMps Max throughput supported by the sink dsc decoder. + * @param[in] maxSliceCount Max slice count considering gpu and sink + * @param[in] bInclusive maximum slice count should be included in mask or not + @param[in] commonSliceCountMask Slice count mask to be considered + @param[out] minSliceCount Minimum slice count to be used for the mode. + * + * @returns minimum slice count to be used for the mode. + */ +static NVT_STATUS +DSC_GetMinSliceCountForMode +( + NvU32 picWidth, + NvU32 pixelClkMhz, + NvU32 maxSliceWidth, + NvU32 peakThroughPutMps, + NvU32 maxSliceCount, + NvU32 commonSliceCountMask, + NvU32 *pMinSliceCount +) +{ + NvU32 minSliceCountLocal = 0U; + NvU32 minSliceCountPicWidth = (picWidth + maxSliceWidth - 1) / maxSliceWidth; + NvU32 minsliceCountThroughput = (pixelClkMhz + peakThroughPutMps - 1) / peakThroughPutMps; + minSliceCountLocal = MAX(minSliceCountPicWidth, minsliceCountThroughput); + if (maxSliceCount < minSliceCountLocal) + { + return NVT_STATUS_MIN_SLICE_COUNT_ERROR; + } + if ((DSC_SliceCountMaskforSliceNum(minSliceCountLocal) & commonSliceCountMask) == 0x0) + { + // + // It is possible that the mininum slice count calculated from pic width and + // pixel clock criteria is not a valid slice count supported by both GPU and + // sink. In those cases, we need to find next valid slice count for the + // combo. + // + NvU32 newMinSliceCount = 0U; + if (DSC_GetHigherSliceCount(commonSliceCountMask, minSliceCountLocal, &newMinSliceCount) != NVT_STATUS_SUCCESS) + { + return NVT_STATUS_MIN_SLICE_COUNT_ERROR; + } + minSliceCountLocal = newMinSliceCount; + } + *pMinSliceCount = minSliceCountLocal; + return NVT_STATUS_SUCCESS; +} + /* * @brief Get slice count mask upto max slice count. * @@ -1235,24 +1297,24 @@ DSC_GetSliceCountMask ) { // Below are the valid slice counts according to DP2.0 spec. - NvU32 validSliceNum[] = {1,2,4,6,8,10,12,16,20,24}; - NvU32 sliceCountMask = 0; + NvU32 validSliceNum[] = {1U,2U,4U,6U,8U,10U,12U,16U,20U,24U}; + NvU32 sliceCountMask = 0U; NvU32 sliceArrayCount; NvU32 i; sliceArrayCount = sizeof(validSliceNum)/sizeof(NvU32); - if (maxSliceNum == 0) - return 0; + if (maxSliceNum == 0U) + return 0U; - for(i = 0; ((i < sliceArrayCount) && (validSliceNum[i] < maxSliceNum)); i++) + for(i = 0U; ((i < sliceArrayCount) && (validSliceNum[i] < maxSliceNum)); i++) { - sliceCountMask |= NVBIT(validSliceNum[i] - 1); + sliceCountMask |= DSC_SliceCountMaskforSliceNum(validSliceNum[i]); } if (bInclusive && (i < sliceArrayCount)) { - sliceCountMask |= NVBIT(validSliceNum[i] - 1); + sliceCountMask |= DSC_SliceCountMaskforSliceNum(validSliceNum[i]); } return sliceCountMask; @@ -1261,10 +1323,16 @@ DSC_GetSliceCountMask /* * @brief Get the next higher valid slice count. * - * @param[in] common_slice_count_mask Includes slice counts supported by both. - * @param[in] desired_slice_num desired slice count - * @param[in] dual_mode if dual mode or not - * @param[in] new_slice_num new slice count if one was found. + * Note each bit position in the mask represents corresponding slice count as + * per validSliceNum. The function compares the bit position of the each set + * bits in the mask against the passed current slice count. If it finds a slice + * count that is more than the current slice count, that is returned as next + * higher slice count. + * + * @param[in] commonSliceCountMask Includes slice counts supported by both + * GPU and sink + * @param[in] currentSliceCount Current slice count + * @param[in] newSliceCount Higher slice count if one was found. * * @returns NVT_STATUS_SUCCESS if successful; * NVT_STATUS_ERR if unsuccessful; @@ -1272,36 +1340,42 @@ DSC_GetSliceCountMask static NvU32 DSC_GetHigherSliceCount ( - NvU32 common_slice_count_mask, - NvU32 desired_slice_num, - NvU32 dual_mode, - NvU32 *new_slice_num + NvU32 commonSliceCountMask, + NvU32 currentSliceCount, + NvU32 *newSliceCount ) { + NvU32 i = 0U; + NvU32 sliceMask = commonSliceCountMask; // - // slice num = 6 won't exist in common_slice_count_mask, but - // still keeping it to align mask bits and valid_slice_num index. + // Below are the valid slice counts according to DP2.0 spec. + // Refer DPCD 64h & 6Dh. Note validSliceNum[2] is kept 0 to + // indicate DPCD 64[2] which is kept reserved according to spec. // - NvU32 valid_slice_num[6] = {1,2,0,4,6,8}; - NvU32 i = 0; - NvU32 slice_mask = common_slice_count_mask; - NvU32 max_slice_num_index = dual_mode ? 5 : 3; + NvU32 validSliceNum[] = {1U,2U,0U,4U,6U,8U,10U,12U,16U,20U,24U}; + NvU32 sliceArrayCount; - while (slice_mask && i <= max_slice_num_index) + sliceArrayCount = sizeof(validSliceNum)/sizeof(NvU32); + + // + // We need to decode the slice count mask and find out if there is a slice + // count in the mask that is higher than the passed in currentSliceCount. + // + while (sliceMask != 0U && i < sliceArrayCount) { - if (slice_mask & 0x1) + if (sliceMask & 0x1) { - if (valid_slice_num[i] > desired_slice_num) + if (validSliceNum[i] > currentSliceCount) { - *new_slice_num = valid_slice_num[i]; + *newSliceCount = validSliceNum[i]; return NVT_STATUS_SUCCESS; } } - slice_mask = slice_mask >> 1; + sliceMask = sliceMask >> 1; i++; } - return NVT_STATUS_ERR; + return NVT_STATUS_PPS_SLICE_COUNT_ERROR; } /* @@ -1345,74 +1419,64 @@ DSC_PpsCalcSliceParams NvU32 peak_throughput_mps; NvU32 common_slice_count_mask; NvU32 gpu_slice_count_mask; + NVT_STATUS status; gpu_slice_count_mask = DSC_GetSliceCountMask(max_slice_num, NV_TRUE /*bInclusive*/); if (dual_mode) { - // remove slice count 1 as it is not valid for 2Head1OR case. - gpu_slice_count_mask &= ~(0x1); + // + // Dual mode will be set until Ada which supports upto 8 slices with 2 heads + // So minimum slice count to be used in this mode is 2 (1 slice on each head) + // Also slice count 6 is not supported until Ada. So we need to remove both + // slice counts from the mask. + // + gpu_slice_count_mask &= ~(DSC_SliceCountMaskforSliceNum(1) | + DSC_SliceCountMaskforSliceNum(6)); } common_slice_count_mask = gpu_slice_count_mask & slice_count_mask; if (!common_slice_count_mask) { - DSC_Print("DSC cannot be supported since no common supported slice count\n"); + // DSC cannot be supported since no common supported slice count return NVT_STATUS_DSC_SLICE_ERROR; } peak_throughput_mps = DSC_GetPeakThroughputMps(peak_throughput); if (!peak_throughput_mps) { - DSC_Print("Peak throughput cannot be zero.\n"); + // Peak throughput cannot be zero return NVT_STATUS_INVALID_PEAK_THROUGHPUT; } if (out->slice_num == 0 && out->slice_width == 0) { - NvU32 new_slice_num = 0; - NvU32 min_slice_num_1 = (out->pic_width + max_slice_width - 1) / max_slice_width; - NvU32 min_slice_num_2 = (pixel_clkMHz + peak_throughput_mps - 1) / peak_throughput_mps; - min_slice_num = MAX(min_slice_num_1, min_slice_num_2); - - if (max_slice_num < min_slice_num) + status = DSC_GetMinSliceCountForMode(out->pic_width, pixel_clkMHz, + max_slice_width, peak_throughput_mps, + max_slice_num, + common_slice_count_mask, + &min_slice_num); + if (status != NVT_STATUS_SUCCESS) { - DSC_Print("Requested mode cannot be supported with DSC\n"); - return NVT_STATUS_MIN_SLICE_COUNT_ERROR; - } - - if (!(DSC_SliceCountMaskforSliceNum(min_slice_num) & common_slice_count_mask)) - { - if (DSC_GetHigherSliceCount(common_slice_count_mask, min_slice_num, dual_mode, &new_slice_num) == NVT_STATUS_ERR) - { - DSC_Print("DSC cannot be enabled for this mode\n"); - return NVT_STATUS_MIN_SLICE_COUNT_ERROR; - } - else - { - out->slice_num = new_slice_num; - } - } - else - { - out->slice_num = min_slice_num; + return status; } + out->slice_num = min_slice_num; out->slice_width = (out->pic_width + out->slice_num - 1) / out->slice_num; } else if (out->slice_num == 0) { if (out->slice_width > max_slice_width) { - DSC_Print("Error! Max Supported Slice Width = %u\n", max_slice_width); + // Error! Calculated slice width exceeds max Supported Slice Width return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } out->slice_num = (out->pic_width + out->slice_width - 1) / out->slice_width; if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask)) { - DSC_Print("Slice count corresponding to requested slice_width is not supported\n"); + // Slice count corresponding to requested slice_width is not supported return NVT_STATUS_PPS_SLICE_COUNT_ERROR; } } @@ -1420,7 +1484,7 @@ DSC_PpsCalcSliceParams { if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask)) { - DSC_Print("Slice count requested is not supported\n"); + // Slice count requested is not supported return NVT_STATUS_PPS_SLICE_COUNT_ERROR; } @@ -1433,7 +1497,7 @@ DSC_PpsCalcSliceParams if (out->slice_width > max_slice_width) { - DSC_Print("Slice width corresponding to the requested slice count is not supported\n"); + // Slice width corresponding to the requested slice count is not supported return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } } @@ -1441,37 +1505,37 @@ DSC_PpsCalcSliceParams { if (!(DSC_SliceCountMaskforSliceNum(out->slice_num) & common_slice_count_mask)) { - DSC_Print("Requested slice count is not supported\n"); + // Requested slice count is not supported return NVT_STATUS_PPS_SLICE_COUNT_ERROR; } if (out->slice_width > max_slice_width) { - DSC_Print("Requested slice width cannot be supported\n"); + // Requested slice width cannot be supported return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } if (out->slice_width != (out->pic_width + out->slice_num - 1) / out->slice_num) { - DSC_Print("slice_width must equal CEIL(pic_width/slice_num) \n"); + // slice_width must equal CEIL(pic_width/slice_num) return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } } if((pixel_clkMHz / out->slice_num) > peak_throughput_mps) { - DSC_Print("Sink DSC decoder does not support minimum throughout required for this DSC config \n"); + // Sink DSC decoder does not support minimum throughout required for this DSC config return NVT_STATUS_ERR; } if (max_slice_width < SINK_MAX_SLICE_WIDTH_DEFAULT) { - DSC_Print("Sink has to support a max slice width of at least 2560 as per DP1.4 spec. Ignoring for now."); + // Sink has to support a max slice width of at least 2560 as per DP1.4 spec. Ignoring for now. } if (out->slice_width < 32) { - DSC_Print("slice_width must >= 32\n"); + // slice_width must >= 32 return NVT_STATUS_PPS_SLICE_WIDTH_ERROR; } @@ -1485,7 +1549,8 @@ DSC_PpsCalcSliceParams // if ((out->chunk_size + 3) / 4 * out->slice_num > out->pic_width) { - DSC_Print("Error! bpp too high, RG will overflow, normally, this error is also caused by padding (pic_widthpic_height % out->slice_height != 0) { - DSC_Print("Error! pic_height %% slice_height must be 0"); + // Error! pic_height % slice_height must be 0 return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR; } if(DSC_PpsCheckSliceHeight(out) != NVT_STATUS_SUCCESS) { - DSC_Print("Error! slice_height not valid"); + // Error! slice_height not valid return NVT_STATUS_PPS_SLICE_HEIGHT_ERROR; } return NVT_STATUS_SUCCESS; @@ -1614,6 +1679,7 @@ DSC_PpsCalc * then pack pps parameters into 32bit data array. * * @param[in] in DSC input parameter + * @param[in] pPpsOut A preallocated work-area buffer for calculations * @param[out] out DSC output parameter * NvU32[32] to return the pps data. * The data can be send to SetDscPpsData* methods directly. @@ -1626,7 +1692,7 @@ DSC_PpsDataGen ( const DSC_INPUT_PARAMS *in, DSC_OUTPUT_PARAMS *pPpsOut, - NvU32 out[DSC_MAX_PPS_SIZE_DWORD] + NvU32 out[DSC_MAX_PPS_SIZE_DWORD] ) { NVT_STATUS ret; @@ -1635,7 +1701,6 @@ DSC_PpsDataGen ret = DSC_PpsCalc(in, pPpsOut); if (ret != NVT_STATUS_SUCCESS) { - DSC_Print("ERROR - Invalid parameter."); goto done; } @@ -1643,6 +1708,7 @@ DSC_PpsDataGen /* fall through */ done: + return ret; } @@ -1668,177 +1734,177 @@ _validateInput ) { // Validate DSC Info - if (pDscInfo->sinkCaps.decoderColorFormatMask == 0) + if (pDscInfo->sinkCaps.decoderColorFormatMask == 0U) { - DSC_Print("ERROR - At least one of the color format decoding needs to be supported by Sink."); + // ERROR - At least one of the color format decoding needs to be supported by Sink. return NVT_STATUS_INVALID_PARAMETER; } if (!ONEBITSET(pDscInfo->sinkCaps.bitsPerPixelPrecision)) { - DSC_Print("ERROR - Only one of Bits Per Pixel Precision should be set"); + // ERROR - Only one of Bits Per Pixel Precision should be set return NVT_STATUS_INVALID_PARAMETER; } - if ((pDscInfo->sinkCaps.bitsPerPixelPrecision != 1) && - (pDscInfo->sinkCaps.bitsPerPixelPrecision != 2) && - (pDscInfo->sinkCaps.bitsPerPixelPrecision != 4) && - (pDscInfo->sinkCaps.bitsPerPixelPrecision != 8) && - (pDscInfo->sinkCaps.bitsPerPixelPrecision != 16)) + if ((pDscInfo->sinkCaps.bitsPerPixelPrecision != 1U) && + (pDscInfo->sinkCaps.bitsPerPixelPrecision != 2U) && + (pDscInfo->sinkCaps.bitsPerPixelPrecision != 4U) && + (pDscInfo->sinkCaps.bitsPerPixelPrecision != 8U) && + (pDscInfo->sinkCaps.bitsPerPixelPrecision != 16U)) { - DSC_Print("ERROR - Bits Per Pixel Precision should be 1/16, 1/8, 1/4, 1/2 or 1 bpp."); + // ERROR - Bits Per Pixel Precision should be 1/16, 1/8, 1/4, 1/2 or 1 bpp. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->sinkCaps.maxSliceWidth == 0) + if (pDscInfo->sinkCaps.maxSliceWidth == 0U) { - DSC_Print("ERROR - Invalid max slice width supported by sink."); + // ERROR - Invalid max slice width supported by sink. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->sinkCaps.maxNumHztSlices == 0) + if (pDscInfo->sinkCaps.maxNumHztSlices == 0U) { - DSC_Print("ERROR - Invalid max number of horizontal slices supported by sink."); + // ERROR - Invalid max number of horizontal slices supported by sink. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->sinkCaps.lineBufferBitDepth == 0) + if (pDscInfo->sinkCaps.lineBufferBitDepth == 0U) { - DSC_Print("ERROR - Invalid line buffer bit depth supported by sink."); + // ERROR - Invalid line buffer bit depth supported by sink. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->sinkCaps.algorithmRevision.versionMinor == 0) + if (pDscInfo->sinkCaps.algorithmRevision.versionMinor == 0U) { - DSC_Print("ERROR - Invalid DSC algorithm revision supported by sink."); + // ERROR - Invalid DSC algorithm revision supported by sink. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->gpuCaps.encoderColorFormatMask == 0) + if (pDscInfo->gpuCaps.encoderColorFormatMask == 0U) { - DSC_Print("ERROR - At least one of the color format encoding needs to be supported by GPU."); + // ERROR - At least one of the color format encoding needs to be supported by GPU. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->gpuCaps.lineBufferSize == 0) + if (pDscInfo->gpuCaps.lineBufferSize == 0U) { - DSC_Print("ERROR - Invalid Line buffer size supported by GPU."); + // ERROR - Invalid Line buffer size supported by GPU. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->gpuCaps.maxNumHztSlices == 0) + if (pDscInfo->gpuCaps.maxNumHztSlices == 0U) { - DSC_Print("ERROR - Invalid max number of horizontal slices supported by GPU."); + // ERROR - Invalid max number of horizontal slices supported by GPU. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->gpuCaps.lineBufferBitDepth == 0) + if (pDscInfo->gpuCaps.lineBufferBitDepth == 0U) { - DSC_Print("ERROR - Invalid line buffer bit depth supported by GPU."); + // ERROR - Invalid line buffer bit depth supported by GPU. return NVT_STATUS_INVALID_PARAMETER; } if (pDscInfo->forcedDscParams.sliceCount > pDscInfo->sinkCaps.maxNumHztSlices) { - DSC_Print("ERROR - Client can't specify forced slice count greater than what sink supports."); + // ERROR - Client can't specify forced slice count greater than what sink supports. return NVT_STATUS_DSC_SLICE_ERROR; } if ((pDscInfo->forcedDscParams.sliceCount / (pModesetInfo->bDualMode ? 2 : 1)) > pDscInfo->gpuCaps.maxNumHztSlices) { - DSC_Print("ERROR - Client can't specify forced slice count greater than what GPU supports."); + // ERROR - Client can't specify forced slice count greater than what GPU supports. return NVT_STATUS_DSC_SLICE_ERROR; } if (pDscInfo->forcedDscParams.sliceWidth > pDscInfo->sinkCaps.maxSliceWidth) { - DSC_Print("ERROR - Client can't specify forced slice width greater than what sink supports."); + // ERROR - Client can't specify forced slice width greater than what sink supports. return NVT_STATUS_DSC_SLICE_ERROR; } - if ((pDscInfo->forcedDscParams.sliceCount > 0) && - (pDscInfo->forcedDscParams.sliceWidth != 0)) + if ((pDscInfo->forcedDscParams.sliceCount > 0U) && + (pDscInfo->forcedDscParams.sliceWidth != 0U)) { - DSC_Print("ERROR - Client can't specify both forced slice count and slice width."); + // ERROR - Client can't specify both forced slice count and slice width. return NVT_STATUS_DSC_SLICE_ERROR; } - if ((pDscInfo->forcedDscParams.sliceCount != 0) && - (pDscInfo->forcedDscParams.sliceCount != 1) && - (pDscInfo->forcedDscParams.sliceCount != 2) && - (pDscInfo->forcedDscParams.sliceCount != 4) && - (pDscInfo->forcedDscParams.sliceCount != 8)) + if ((pDscInfo->forcedDscParams.sliceCount != 0U) && + (pDscInfo->forcedDscParams.sliceCount != 1U) && + (pDscInfo->forcedDscParams.sliceCount != 2U) && + (pDscInfo->forcedDscParams.sliceCount != 4U) && + (pDscInfo->forcedDscParams.sliceCount != 8U)) { - DSC_Print("ERROR - Forced Slice Count has to be 1/2/4/8."); + // ERROR - Forced Slice Count has to be 1/2/4/8. return NVT_STATUS_DSC_SLICE_ERROR; } if (pDscInfo->forcedDscParams.sliceWidth > pModesetInfo->activeWidth) { - DSC_Print("ERROR - Forced Slice Width can't be more than Active Width."); + // ERROR - Forced Slice Width can't be more than Active Width. return NVT_STATUS_DSC_SLICE_ERROR; } if (pDscInfo->forcedDscParams.sliceHeight > pModesetInfo->activeHeight) { - DSC_Print("ERROR - Forced Slice Height can't be more than Active Height."); + // ERROR - Forced Slice Height can't be more than Active Height. return NVT_STATUS_DSC_SLICE_ERROR; } if (pDscInfo->forcedDscParams.dscRevision.versionMinor > pDscInfo->sinkCaps.algorithmRevision.versionMinor) { - DSC_Print("ERROR - Forced DSC Algorithm Revision is greater than Sink Supported value."); + // ERROR - Forced DSC Algorithm Revision is greater than Sink Supported value. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->forcedDscParams.dscRevision.versionMinor > 2) + if (pDscInfo->forcedDscParams.dscRevision.versionMinor > 2U) { - DSC_Print("ERROR - Forced DSC Algorithm Revision is greater than 1.2"); + // ERROR - Forced DSC Algorithm Revision is greater than 1.2 return NVT_STATUS_INVALID_PARAMETER; } - if (pModesetInfo->pixelClockHz == 0) + if (pModesetInfo->pixelClockHz == 0U) { - DSC_Print("ERROR - Invalid pixel Clock for mode."); + // ERROR - Invalid pixel Clock for mode. return NVT_STATUS_INVALID_PARAMETER; } - if ((pDscInfo->branchCaps.overallThroughputMode0 != 0) && + if ((pDscInfo->branchCaps.overallThroughputMode0 != 0U) && (pModesetInfo->pixelClockHz > pDscInfo->branchCaps.overallThroughputMode0 * MHZ_TO_HZ)) { - DSC_Print("ERROR - Pixel clock cannot be greater than Branch DSC Overall Throughput Mode 0"); + // ERROR - Pixel clock cannot be greater than Branch DSC Overall Throughput Mode 0 return NVT_STATUS_OVERALL_THROUGHPUT_ERROR; } - if (pModesetInfo->activeWidth == 0) + if (pModesetInfo->activeWidth == 0U) { - DSC_Print("ERROR - Invalid active width for mode."); + // ERROR - Invalid active width for mode. return NVT_STATUS_INVALID_PARAMETER; } - if (pDscInfo->branchCaps.maxLineBufferWidth != 0 && + if (pDscInfo->branchCaps.maxLineBufferWidth != 0U && pModesetInfo->activeWidth > pDscInfo->branchCaps.maxLineBufferWidth) { - DSC_Print("ERROR - Active width cannot be greater than DSC Decompressor max line buffer width"); + // ERROR - Active width cannot be greater than DSC Decompressor max line buffer width return NVT_STATUS_MAX_LINE_BUFFER_ERROR; } - if (pModesetInfo->activeHeight == 0) + if (pModesetInfo->activeHeight == 0U) { - DSC_Print("ERROR - Invalid active height for mode."); + // ERROR - Invalid active height for mode. return NVT_STATUS_INVALID_PARAMETER; } - if (pModesetInfo->bitsPerComponent == 0) + if (pModesetInfo->bitsPerComponent == 0U) { - DSC_Print("ERROR - Invalid bits per component for mode."); + // ERROR - Invalid bits per component for mode. return NVT_STATUS_INVALID_PARAMETER; } - if (availableBandwidthBitsPerSecond == 0) + if (availableBandwidthBitsPerSecond == 0U) { - DSC_Print("ERROR - Invalid available bandwidth in Bits Per Second."); + // ERROR - Invalid available bandwidth in Bits Per Second. return NVT_STATUS_INVALID_PARAMETER; } @@ -1853,7 +1919,7 @@ _validateInput (!((pDscInfo->gpuCaps.encoderColorFormatMask & DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422) && (pDscInfo->sinkCaps.decoderColorFormatMask & DSC_DECODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422)))) { - DSC_Print("ERROR - Can't enable YCbCr422 with current GPU and Sink DSC config."); + // ERROR - Can't enable YCbCr422 with current GPU and Sink DSC config. return NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; } } @@ -1866,22 +1932,22 @@ _validateInput if (!((pDscInfo->gpuCaps.encoderColorFormatMask & DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420) && (pDscInfo->sinkCaps.decoderColorFormatMask & DSC_DECODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420))) { - DSC_Print("ERROR - Can't enable YCbCr420 with current GPU and Sink DSC config."); + // ERROR - Can't enable YCbCr420 with current GPU and Sink DSC config. return NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; } } - if ((pDscInfo->sinkCaps.algorithmRevision.versionMajor == 1) && - (pDscInfo->sinkCaps.algorithmRevision.versionMinor == 1) && + if ((pDscInfo->sinkCaps.algorithmRevision.versionMajor == 1U) && + (pDscInfo->sinkCaps.algorithmRevision.versionMinor == 1U) && (pModesetInfo->colorFormat == NVT_COLOR_FORMAT_YCbCr420)) { - DSC_Print("WARNING: DSC v1.2 or higher is recommended for using YUV444"); - DSC_Print("Current version is 1.1"); + // WARNING: DSC v1.2 or higher is recommended for using YUV444 + // Current version is 1.1 } if (pDscInfo->sinkCaps.maxBitsPerPixelX16 > 1024U) { - DSC_Print("ERROR - Max bits per pixel can't be greater than 1024"); + // ERROR - Max bits per pixel can't be greater than 1024 return NVT_STATUS_INVALID_PARAMETER; } @@ -1892,33 +1958,33 @@ _validateInput case 12: if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_12_BITS)) { - DSC_Print("ERROR - Sink DSC Decoder does not support 12 bpc"); + // ERROR - Sink DSC Decoder does not support 12 bpc return NVT_STATUS_INVALID_BPC; } break; case 10: if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_10_BITS)) { - DSC_Print("ERROR - Sink DSC Decoder does not support 10 bpc"); + // ERROR - Sink DSC Decoder does not support 10 bpc return NVT_STATUS_INVALID_BPC; } break; case 8: if (!(pDscInfo->sinkCaps.decoderColorDepthMask & DSC_DECODER_COLOR_DEPTH_CAPS_8_BITS)) { - DSC_Print("ERROR - Sink DSC Decoder does not support 8 bpc"); + // ERROR - Sink DSC Decoder does not support 8 bpc return NVT_STATUS_INVALID_BPC; } break; default: - DSC_Print("ERROR - Invalid bits per component specified"); + // ERROR - Invalid bits per component specified return NVT_STATUS_INVALID_PARAMETER; } } else { - DSC_Print("WARNING - Decoder Color Depth Mask was not provided. Assuming that decoder supports all depths."); + // WARNING - Decoder Color Depth Mask was not provided. Assuming that decoder supports all depths. } // Validate WAR data @@ -1926,7 +1992,7 @@ _validateInput { if ((pWARData->connectorType != DSC_DP) && (pWARData->connectorType != DSC_HDMI)) { - DSC_Print("WARNING - Incorrect connector info sent with WAR data"); + // WARNING - Incorrect connector info sent with WAR data return NVT_STATUS_INVALID_PARAMETER; } @@ -1934,25 +2000,25 @@ _validateInput { if (!IS_VALID_LANECOUNT(pWARData->dpData.laneCount)) { - DSC_Print("ERROR - Incorrect DP Lane count info sent with WAR data"); + // ERROR - Incorrect DP Lane count info sent with WAR data return NVT_STATUS_INVALID_PARAMETER; } if (!IS_VALID_LINKBW(pWARData->dpData.linkRateHz / DP_LINK_BW_FREQ_MULTI_MBPS)) { - DSC_Print("ERROR - Incorrect DP Link rate info sent with WAR data"); + // ERROR - Incorrect DP Link rate info sent with WAR data return NVT_STATUS_INVALID_PARAMETER; } if (pWARData->dpData.hBlank > MAX_HBLANK_PIXELS) { - DSC_Print("ERROR - Incorrect DP HBlank info sent with WAR data"); + // ERROR - Incorrect DP HBlank info sent with WAR data return NVT_STATUS_INVALID_HBLANK; } if ((pWARData->dpData.dpMode != DSC_DP_SST) && (pWARData->dpData.dpMode != DSC_DP_MST)) { - DSC_Print("ERROR - Incorrect DP Stream mode sent with WAR data"); + // ERROR - Incorrect DP Stream mode sent with WAR data return NVT_STATUS_INVALID_PARAMETER; } } @@ -1963,6 +2029,158 @@ _validateInput /* ------------------------ Public Functions ------------------------------- */ +/* + * @brief Calculate PPS parameters and slice count mask based on passed down + * Sink, GPU capability and modeset info + * + * + * @param[in] pDscInfo Includes Sink and GPU DSC capabilities + * @param[in] pModesetInfo Modeset related information + * @param[in] pWARData Data required for providing WAR for issues + * @param[in] availableBandwidthBitsPerSecond Available bandwidth for video + * transmission(After FEC/Downspread overhead consideration) + * @param[out] pps Calculated PPS parameter. + * The data can be sent to SetDscPpsData* methods directly. + * @param[out] pBitsPerPixelX16 Bits per pixel multiplied by 16 + * @param[out] pSliceCountMask Mask of all slice counts supported by the mode. + * + * @returns NVT_STATUS_SUCCESS if successful; + * NVT_STATUS_DSC_SLICE_ERROR if no common slice count could be found; + * NVT_STATUS_INVALID_PEAK_THROUGHPUT if peak through put is invalid; + * NVT_STATUS_PPS_SLICE_COUNT_ERROR if there is no slice count possible for the mode. + * In case this returns failure consider that PPS is not possible. + */ +NVT_STATUS +DSC_GeneratePPSWithSliceCountMask +( + const DSC_INFO *pDscInfo, + const MODESET_INFO *pModesetInfo, + const WAR_DATA *pWARData, + NvU64 availableBandwidthBitsPerSecond, + NvU32 pps[DSC_MAX_PPS_SIZE_DWORD], + NvU32 *pBitsPerPixelX16, + NvU32 *pSliceCountMask +) +{ + NvU32 commonSliceCountMask; + NvU32 gpuSliceCountMask; + NvU32 rejectSliceCountMask; + NvU32 possibleSliceCountMask; + NvU32 validSliceCountMask = 0x0; + NvU32 peakThroughPutIndex = 0U; + NvU32 peakThroughPutMps = 0U; + NvU32 maxSliceCount; + NvU32 maxSliceWidth; + NvU32 minSliceCount; + NvU32 sliceArrayCount; + NvU32 i; + DSC_INFO localDscInfo; + NvU32* ppsOut = NULL; + NVT_STATUS status; + DSC_GENERATE_PPS_OPAQUE_WORKAREA scratchBuffer; + + // Below are the valid slice counts according to DP2.0 spec. + NvU32 validSliceNum[] = {1U,2U,4U,6U,8U,10U,12U,16U,20U,24U}; + + // if any slice parameters are forced, just return PPS. + if (pDscInfo->forcedDscParams.sliceWidth != 0U || + pDscInfo->forcedDscParams.sliceCount != 0U) + { + return DSC_GeneratePPS(pDscInfo, pModesetInfo, pWARData, + availableBandwidthBitsPerSecond, + &scratchBuffer, pps, pBitsPerPixelX16); + } + + sliceArrayCount = sizeof(validSliceNum)/sizeof(NvU32); + + maxSliceCount = MIN(pDscInfo->sinkCaps.maxNumHztSlices, pDscInfo->gpuCaps.maxNumHztSlices); + + // lineBufferSize is reported in 1024 units by HW, so need to multiply by 1024 to get pixels. + maxSliceWidth = MIN(pDscInfo->sinkCaps.maxSliceWidth, pDscInfo->gpuCaps.lineBufferSize * 1024); + + gpuSliceCountMask = DSC_GetSliceCountMask(maxSliceCount, NV_TRUE /*bInclusive*/); + + commonSliceCountMask = gpuSliceCountMask & pDscInfo->sinkCaps.sliceCountSupportedMask; + + if (commonSliceCountMask == 0x0) + { + return NVT_STATUS_DSC_SLICE_ERROR; + } + + if (pModesetInfo->colorFormat == NVT_COLOR_FORMAT_YCbCr422 || + pModesetInfo->colorFormat == NVT_COLOR_FORMAT_YCbCr420) + { + peakThroughPutIndex = pDscInfo->sinkCaps.peakThroughputMode1; + } + else + { + peakThroughPutIndex = pDscInfo->sinkCaps.peakThroughputMode0; + } + + peakThroughPutMps = DSC_GetPeakThroughputMps(peakThroughPutIndex); + if (peakThroughPutMps == 0U) + { + return NVT_STATUS_INVALID_PEAK_THROUGHPUT; + } + + status = DSC_GetMinSliceCountForMode(pModesetInfo->activeWidth, + (NvU32)(pModesetInfo->pixelClockHz / 1000000L), + maxSliceWidth, + peakThroughPutMps, + maxSliceCount, + commonSliceCountMask, + &minSliceCount); + if (status != NVT_STATUS_SUCCESS) + return status; + + // Find mask of slice counts which are less than min slice count + rejectSliceCountMask = DSC_GetSliceCountMask(minSliceCount, NV_FALSE /*bInclusive*/); + + // Now find mask of slice counts that can be supported by the mode + possibleSliceCountMask = commonSliceCountMask & (~rejectSliceCountMask); + + // + // If we have mask of all possible slice counts, loop to generate PPS with + // each of those slice counts forced. + // + if (possibleSliceCountMask) + { + localDscInfo = *pDscInfo; + + for(i = 0U ; i < sliceArrayCount; i++) + { + if (possibleSliceCountMask & NVBIT(validSliceNum[i] - 1)) + { + ppsOut = NULL; + localDscInfo.forcedDscParams.sliceCount = validSliceNum[i]; + if (localDscInfo.forcedDscParams.sliceCount == minSliceCount) + { + // + // We need to return PPS with minimum slice count if client + // has not forced any slice count even though we generate + // pps with all other possible slice counts to validate them. + // + ppsOut = pps; + } + if (DSC_GeneratePPS(&localDscInfo, pModesetInfo, pWARData, + availableBandwidthBitsPerSecond, &scratchBuffer, + ppsOut, pBitsPerPixelX16) == NVT_STATUS_SUCCESS) + { + validSliceCountMask |= NVBIT(validSliceNum[i] - 1); + } + } + } + } + else + { + return NVT_STATUS_PPS_SLICE_COUNT_ERROR; + } + + *pSliceCountMask = validSliceCountMask; + + return NVT_STATUS_SUCCESS; +} + /* * @brief Calculate PPS parameters based on passed down Sink, * GPU capability and modeset info @@ -1972,6 +2190,8 @@ _validateInput * @param[in] pWARData Data required for providing WAR for issues * @param[in] availableBandwidthBitsPerSecond Available bandwidth for video * transmission(After FEC/Downspread overhead consideration) + * @param[in] pOpaqueWorkarea Scratch buffer of sufficient size pre-allocated + by client for DSC PPS calculations internal use * @param[out] pps Calculated PPS parameter. * The data can be send to SetDscPpsData* methods directly. * @param[out] pBitsPerPixelX16 Bits per pixel multiplied by 16 @@ -1987,9 +2207,9 @@ DSC_GeneratePPS const MODESET_INFO *pModesetInfo, const WAR_DATA *pWARData, NvU64 availableBandwidthBitsPerSecond, + DSC_GENERATE_PPS_OPAQUE_WORKAREA *pOpaqueWorkarea, NvU32 pps[DSC_MAX_PPS_SIZE_DWORD], - NvU32 *pBitsPerPixelX16, - DSC_GENERATE_PPS_OPAQUE_WORKAREA *pOpaqueWorkarea + NvU32 *pBitsPerPixelX16 ) { DSC_INPUT_PARAMS *in = NULL; @@ -1997,9 +2217,8 @@ DSC_GeneratePPS DSC_GENERATE_PPS_WORKAREA *pWorkarea = NULL; NVT_STATUS ret = NVT_STATUS_ERR; - if ((!pDscInfo) || (!pModesetInfo) || (!pBitsPerPixelX16) || (!pOpaqueWorkarea)) + if ((!pDscInfo) || (!pModesetInfo) || (!pOpaqueWorkarea) || (!pBitsPerPixelX16)) { - DSC_Print("ERROR - Invalid parameter."); ret = NVT_STATUS_INVALID_PARAMETER; goto done; } @@ -2011,8 +2230,6 @@ DSC_GeneratePPS ret = _validateInput(pDscInfo, pModesetInfo, pWARData, availableBandwidthBitsPerSecond); if (ret != NVT_STATUS_SUCCESS) { - DSC_Print("ERROR - Invalid parameter."); - ret = NVT_STATUS_INVALID_PARAMETER; goto done; } @@ -2045,7 +2262,7 @@ DSC_GeneratePPS } else { - DSC_Print("ERROR - YCbCr422 is not possible with current config."); + // ERROR - YCbCr422 is not possible with current config. ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; goto done; } @@ -2060,14 +2277,14 @@ DSC_GeneratePPS } else { - DSC_Print("ERROR - YCbCr420 is not possible with current config."); + // ERROR - YCbCr420 is not possible with current config. ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; goto done; } break; default: - DSC_Print("ERROR - Invalid color Format specified."); + // ERROR - Invalid color Format specified. ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; goto done; } @@ -2167,14 +2384,16 @@ DSC_GeneratePPS { *pBitsPerPixelX16 = DSC_AlignDownForBppPrecision(*pBitsPerPixelX16, pDscInfo->sinkCaps.bitsPerPixelPrecision); + // // The calculation of in->bits_per_pixel here in PPSlib, which is the maximum bpp that is allowed by available bandwidth, // which is applicable to DP alone and not to HDMI FRL. // Before calling PPS lib to generate PPS data, HDMI library has done calculation according to HDMI2.1 spec // to determine if FRL rate is sufficient for the requested bpp. So restricting the condition to DP alone. + // if ((pWARData && (pWARData->connectorType == DSC_DP)) && (*pBitsPerPixelX16 > in->bits_per_pixel)) { - DSC_Print("ERROR - Invalid bits per pixel value specified."); + // ERROR - Invalid bits per pixel value specified. ret = NVT_STATUS_INVALID_BPP; goto done; } @@ -2183,17 +2402,21 @@ DSC_GeneratePPS in->bits_per_pixel = *pBitsPerPixelX16; } - // For DSC Dual Mode, because of architectural limitation we can't use bits_per_pixel more than 16. - if (pModesetInfo->bDualMode && (in->bits_per_pixel > 256 /*bits_per_pixel = 16*/)) + // + // For DSC Dual Mode or Multi-tile configs (NVD 5.0 and later), + // because of architectural limitation we can't use bits_per_pixel + // more than 16. + // + if ((pModesetInfo->bDualMode || (pDscInfo->gpuCaps.maxNumHztSlices > 4U)) && + (in->bits_per_pixel > 256 /*bits_per_pixel = 16*/)) { - DSC_Print("ERROR - DSC Dual Mode, because of architectural limitation we can't use bits_per_pixel more than 16."); ret = NVT_STATUS_INVALID_BPP; goto done; } if ((pDscInfo->sinkCaps.maxBitsPerPixelX16 != 0) && (*pBitsPerPixelX16 > pDscInfo->sinkCaps.maxBitsPerPixelX16)) { - DSC_Print("ERROR - bits per pixel value specified by user is greater than what DSC decompressor can support."); + // ERROR - bits per pixel value specified by user is greater than what DSC decompressor can support. ret = NVT_STATUS_INVALID_BPP; goto done; } @@ -2201,33 +2424,35 @@ DSC_GeneratePPS else { // - // For DSC Dual Mode, because of architectural limitation we can't use bits_per_pixel more than 16. - // Forcing it to 16. + // For DSC Dual Mode or for multi-tile configs (NVD 5.0 and later), + // because of architectural limitation we can't use bits_per_pixel more + // than 16. So forcing it to 16. // - if (pModesetInfo->bDualMode && (in->bits_per_pixel > 256 /*bits_per_pixel = 16*/)) + if ((pModesetInfo->bDualMode || (pDscInfo->gpuCaps.maxNumHztSlices > 4U)) && + (in->bits_per_pixel > 256 /*bits_per_pixel = 16*/)) { - DSC_Print("ERROR - DSC Dual Mode, because of architectural limitation we can't use bits_per_pixel more than 16."); - DSC_Print("ERROR - Forcing it to 16."); + // ERROR - DSC Dual Mode, because of architectural limitation we can't use bits_per_pixel more than 16. + // ERROR - Forcing it to 16. in->bits_per_pixel = 256; } // If calculated bits_per_pixel is 126 or 127, we need to use 128 value. Bug 2686078 if ((in->bits_per_pixel == 126) || (in->bits_per_pixel == 127)) { - DSC_Print("WARNING: bits_per_pixel is forced to 128 because calculated value was 126 or 127"); + // WARNING: bits_per_pixel is forced to 128 because calculated value was 126 or 127 in->bits_per_pixel = 128; } if ((pDscInfo->sinkCaps.maxBitsPerPixelX16 != 0) && (in->bits_per_pixel > pDscInfo->sinkCaps.maxBitsPerPixelX16)) { - DSC_Print("WARNING - Optimal bits per pixel value calculated is greater than what DSC decompressor can support. Forcing it to max that decompressor can support"); + // WARNING - Optimal bits per pixel value calculated is greater than what DSC decompressor can support. Forcing it to max that decompressor can support in->bits_per_pixel = pDscInfo->sinkCaps.maxBitsPerPixelX16; } } if (pModesetInfo->bDualMode && (pDscInfo->gpuCaps.maxNumHztSlices > 4U)) { - DSC_Print("ERROR - Dual Mode should not be set when GPU can support more than 4 slices per head."); + // ERROR - Dual Mode should not be set when GPU can support more than 4 slices per head. ret = NVT_STATUS_INVALID_PARAMETER; goto done; } @@ -2254,7 +2479,7 @@ DSC_GeneratePPS { if (in->dsc_version_minor == 1) { - DSC_Print("Error! DSC1.1 can't support native422!\n"); + // Error! DSC1.1 can't support native422! ret = NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED; goto done; } @@ -2262,8 +2487,7 @@ DSC_GeneratePPS if((((NvS32)(in->bits_per_pixel)) < (NvS32)(2*6*BPP_UNIT)) || (((NvS32)(in->bits_per_pixel)) > (NvS32)(2*32*BPP_UNIT-1))) { - DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u", - in->bits_per_pixel, 2*6*BPP_UNIT, 2*32*BPP_UNIT-1); + // ERROR - bits_per_pixelx16 outside valid range ret = NVT_STATUS_INVALID_BPP; goto done; } @@ -2273,8 +2497,7 @@ DSC_GeneratePPS if ((((NvS32)(in->bits_per_pixel)) < (NvS32)(8*BPP_UNIT)) || (((NvS32)(in->bits_per_pixel)) > (NvS32)(32*BPP_UNIT))) { - DSC_Print("bits_per_pixelx16 (=%u) needs to be between %u and %u", - in->bits_per_pixel, 8*BPP_UNIT, 32*BPP_UNIT); + // ERROR - bits_per_pixelx16 outside valid range ret = NVT_STATUS_INVALID_BPP; goto done; } diff --git a/src/common/modeset/timing/nvt_dsc_pps.h b/src/common/modeset/timing/nvt_dsc_pps.h index 426ac43e1d..070dcb9982 100644 --- a/src/common/modeset/timing/nvt_dsc_pps.h +++ b/src/common/modeset/timing/nvt_dsc_pps.h @@ -42,7 +42,6 @@ #define DSC_MAX_PPS_SIZE_DWORD 32 /* ------------------------ Datatypes -------------------------------------- */ - typedef struct { NvU32 versionMajor; @@ -257,14 +256,8 @@ typedef struct }dpData; } WAR_DATA; -// -// DSC PPS calculations need large scratch buffer to work with, which can be too -// big for some platforms. These buffers need to be allocated on heap rather -// than local stack variable. Clients are expected to pre-allocate -// this buffer and pass it in to DSC PPS interface -// typedef struct { - NvU8 data[512U]; // an upper bound of total size of DSC_IN/OUTPUT_PARAMS + NvU8 data[492U]; // total size of DSC_IN/OUTPUT_PARAMS } DSC_GENERATE_PPS_OPAQUE_WORKAREA; /* @@ -281,6 +274,7 @@ typedef struct { #ifdef __cplusplus extern "C" { #endif + /* * @brief Calculate PPS parameters based on passed down Sink, * GPU capability and modeset info @@ -290,6 +284,8 @@ extern "C" { * @param[in] pWARData Data required for providing WAR for issues * @param[in] availableBandwidthBitsPerSecond Available bandwidth for video * transmission(After FEC/Downspread overhead consideration) + * @param[in] pOpaqueWorkarea Scratch buffer of sufficient size pre-allocated + by client for DSC PPS calculations use * @param[out] pps Calculated PPS parameter. * The data can be send to SetDscPpsData* methods directly. * @param[out] pBitsPerPixelX16 Bits per pixel multiplied by 16 @@ -301,9 +297,40 @@ NVT_STATUS DSC_GeneratePPS(const DSC_INFO *pDscInfo, const MODESET_INFO *pModesetInfo, const WAR_DATA *pWARData, NvU64 availableBandwidthBitsPerSecond, + DSC_GENERATE_PPS_OPAQUE_WORKAREA *pOpaqueWorkarea, NvU32 pps[DSC_MAX_PPS_SIZE_DWORD], - NvU32 *pBitsPerPixelX16, - DSC_GENERATE_PPS_OPAQUE_WORKAREA *pOpaqueWorkarea); + NvU32 *pBitsPerPixelX16); + +/* + * @brief Calculate PPS parameters and slice count mask based on passed down + * Sink, GPU capability and modeset info + * + * + * @param[in] pDscInfo Includes Sink and GPU DSC capabilities + * @param[in] pModesetInfo Modeset related information + * @param[in] pWARData Data required for providing WAR for issues + * @param[in] availableBandwidthBitsPerSecond Available bandwidth for video + * transmission(After FEC/Downspread overhead consideration) + * @param[out] pps Calculated PPS parameter. + * The data can be send to SetDscPpsData* methods directly. + * @param[out] pBitsPerPixelX16 Bits per pixel multiplied by 16 + * @param[out] pSliceCountMask Mask of all slice counts supported by the mode. + * + * @returns NVT_STATUS_SUCCESS if successful; + * NVT_STATUS_ERR if unsuccessful; + * In case this returns failure consider that PPS is not possible. + */ +NVT_STATUS +DSC_GeneratePPSWithSliceCountMask +( + const DSC_INFO *pDscInfo, + const MODESET_INFO *pModesetInfo, + const WAR_DATA *pWARData, + NvU64 availableBandwidthBitsPerSecond, + NvU32 pps[DSC_MAX_PPS_SIZE_DWORD], + NvU32 *pBitsPerPixelX16, + NvU32 *sliceCountMask +); #ifdef __cplusplus } diff --git a/src/common/modeset/timing/nvt_edid.c b/src/common/modeset/timing/nvt_edid.c index 7501117e34..2b55ec0ea6 100644 --- a/src/common/modeset/timing/nvt_edid.c +++ b/src/common/modeset/timing/nvt_edid.c @@ -1076,6 +1076,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID if (p861Info->revision >= NVT_CTA861_REV_H) { + if (p861Info->total_vfdb != 0) parseCta861VideoFormatDataBlock(p861Info, pInfo); if (p861Info->total_did_type7db != 0) parseCta861DIDType7VideoTimingDataBlock(p861Info, pInfo); if (p861Info->total_did_type8db != 0) parseCta861DIDType8VideoTimingDataBlock(p861Info, pInfo); if (p861Info->total_did_type10db != 0) parseCta861DIDType10VideoTimingDataBlock(p861Info, pInfo); @@ -1105,9 +1106,14 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID pInfo->ext_displayid20.interface_features.yuv420_min_pclk = 0; } - if (!pInfo->ext861.basic_caps) + if (pInfo->ext861.revision == 0 && pInfo->ext_displayid20.valid_data_blocks.interface_feature_present) { - pInfo->ext861.basic_caps = pInfo->ext_displayid20.basic_caps; + pInfo->ext861.revision = NVT_CEA861_REV_B; + } + + if (pInfo->ext_displayid20.valid_data_blocks.interface_feature_present) + { + pInfo->ext861.basic_caps |= pInfo->ext_displayid20.basic_caps; } } } @@ -1161,7 +1167,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID } // check for cvt timings - in display range limits or cvt 3-byte LDD, only for EDID1.4 and above - if (pInfo->version > 0x0103) + if (pInfo->version > NVT_EDID_VER_1_3) { parseEdidCvtTiming(pInfo); } @@ -1436,7 +1442,7 @@ NVT_STATUS NvTiming_Get18ByteLongDescriptorIndex(NVT_EDID_INFO *pEdidInfo, NvU8 // get the edid timing CODE_SEGMENT(PAGE_DD_CODE) -NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k) +NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k, NvU32 pclk) { NvU8 kth = 0; NvU32 i, j; @@ -1449,7 +1455,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f if (pEdidInfo == NULL || pEdidInfo->total_timings == 0 || pT == 0) return NVT_STATUS_ERR; - if (width == 0 || height == 0 || rr == 0) // rrx1k is optional, can be 0. + if (width == 0 || height == 0 || rr == 0 ) // rrx1k and pclk are optional, can be 0. return NVT_STATUS_ERR; pEdidTiming = pEdidInfo->timing; @@ -1473,7 +1479,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f if (pEdidInfo->ext861.total_svr > 1) { - kth = getHighestPrioritySVRIdx(pEdidInfo->ext861.svr_vfpdb[0]); + kth = getHighestPrioritySVRIdx(&pEdidInfo->ext861); } for (i = 0; i < pEdidInfo->total_timings; i++) @@ -1492,7 +1498,7 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f ((rrx1k == 0) || (rrx1k == pEdidTiming[i].etc.rrx1k)) && !!(flag & NVT_PVT_INTERLACED_MASK) == !!pEdidTiming[i].interlaced) { - if (map0 >= pEdidInfo->total_timings) + if (map0 >= pEdidInfo->total_timings || pEdidTiming[i].pclk == pclk) { // make sure we take the priority as "detailed>standard>established". (The array timing[] always have the detailed timings in the front and then the standard and established.) map0 = i; @@ -1906,6 +1912,12 @@ NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 f return NVT_STATUS_SUCCESS; } +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k) +{ + return NvTiming_GetEdidTimingExWithPclk(width, height, rr, flag, pEdidInfo, pT, rrx1k, 0); +} + // get the edid timing CODE_SEGMENT(PAGE_DD_CODE) NVT_STATUS NvTiming_GetEdidTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT) @@ -2814,28 +2826,35 @@ NvBool assignNextAvailableTiming(NVT_EDID_INFO *pInfo, } /** - * @brief Return the first high priority nth index based on the different SVR + * @brief Return the nth highest priority index based on the different SVR * @param svr Short Video Reference */ CODE_SEGMENT(PAGE_DD_CODE) -NvU8 getHighestPrioritySVRIdx(NvU8 svr) +NvU8 getHighestPrioritySVRIdx(const NVT_EDID_CEA861_INFO *pExt861) { - // In general sink shall define the first one timing sequence + // In general, sink shall define the first one timing sequence NvU8 kth = 1; + NvU8 i = 0; - // Reserved - if (svr == 0 || svr == 128 || (svr >= 176 && svr <= 192) || svr == 255) - return 0; - - if (svr >= 129 && svr <= 144) return svr - 128; // Interpret as the Kth 18-byte DTD in both base0 and CTA block (for N = 1 to 16) - else if (svr >= 145 && svr <= 160) return svr - 144; // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor. (for N = 1 to 16) - else if (svr >= 161 && svr <= 175) return svr - 160; // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N (for N = 1 to 15) - else if (svr == 254) return kth; // Interpret as the timing format indicated by the first code of the first T8VTDB (for N = 1) - else // assign corresponding CTA format's timing from pre-defined CE timing table, EIA861B + for (i = 0; i < pExt861->total_svr; i++) { - // ( SVR >= 1 and SVR <= 127) and (SVR >= 193 and SVR <= 253) needs to handle it by client - return svr; + NvU8 svr = pExt861->svr_vfpdb[i]; + + // Reserved + if (svr == 0 || svr == 128 || (svr >= 176 && svr <= 192) || svr == 255) + continue; + + if (svr >= 129 && svr <= 144) return svr - 128; // Interpret as the Kth 18-byte DTD in both base0 and CTA block (for N = 1 to 16) + else if (svr >= 145 && svr <= 160) return svr - 144; // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor. (for N = 1 to 16) + else if (svr >= 161 && svr <= 175) return svr - 160; // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N (for N = 1 to 15) + else if (svr == 254) return kth; // Interpret as the timing format indicated by the first code of the first T8VTDB (for N = 1) + else // assign corresponding CTA format's timing from pre-defined CE timing table, EIA861B + { + // ( SVR >= 1 and SVR <= 127) and (SVR >= 193 and SVR <= 253) needs to handle it by client + return svr; + } } + return 0; } diff --git a/src/common/modeset/timing/nvt_edidext_861.c b/src/common/modeset/timing/nvt_edidext_861.c index d369c0f670..36a453153e 100644 --- a/src/common/modeset/timing/nvt_edidext_861.c +++ b/src/common/modeset/timing/nvt_edidext_861.c @@ -40,7 +40,6 @@ PUSH_SEGMENTS {hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\ 0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_STATUS_EDID_861STn(format),"CEA-861B:#"#format""}} - #define NVT_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rrx1k,ip,aspect,rep,format,name) \ {hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\ 0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_TYPE_NV_PREDEFINEDn(format),name}} @@ -49,6 +48,8 @@ PUSH_SEGMENTS {hv,0,hfp,hsw,ht,(hsp)=='-',vv,0,vfp,vsw,vt,(vsp)=='-',(ip)=='i' ? NVT_INTERLACED:NVT_PROGRESSIVE,\ 0,{0,((rrx1k)+500)/1000,rrx1k,((1?aspect)<<16)|(0?aspect),rep,{0},{0},{0},{0},NVT_STATUS_HDMI_EXTn(format),name}} +#define RID_MODE(hv, hsp, vv, vsp, ip, aspect, rid) \ + {hv, (hsp)=='-', vv, (vsp)=='-',(ip)=='i'? NVT_INTERLACED:NVT_PROGRESSIVE,((1?aspect)<<16)|(0?aspect), rid} DATA_SEGMENT(PAGE_DATA) CONS_SEGMENT(PAGE_CONS) @@ -280,7 +281,7 @@ static const NVT_TIMING EIA861B[]= EIA_TIMING( 4096, 800, 88, 5280,'+',2160, 8,10,2250,'+',100000,'p',256:135,0x1,218),// 4096 x 2160p @100 (Format 218) EIA_TIMING( 4096, 88, 88, 4400,'+',2160, 8,10,2250,'+',119880,'p',256:135,0x1,219),// 4096 x 2160p @119.88/120 (Format 219) // 220-255 Reserved for the Future - // the end + // the end EIA_TIMING(0,0,0,0,'-',0,0,0,0,'-',0,'p',4:3,0,0) }; static NvU32 MAX_CEA861B_FORMAT = sizeof(EIA861B)/sizeof(EIA861B[0]) - 1; @@ -338,6 +339,81 @@ static const NvU32 EIA861B_DUAL_ASPECT_VICS[][2] = }; static NvU32 MAX_EIA861B_DUAL_ASPECT_VICS = sizeof(EIA861B_DUAL_ASPECT_VICS) / sizeof(EIA861B_DUAL_ASPECT_VICS[0]); +static const NVT_RID_CODES RID[] = +{ + RID_MODE( 0, '+', 0, '+', 'p', 16:9 , 0), // No Resolution Identification Available + RID_MODE( 1280, '+', 720, '+', 'p', 16:9 , 1), // HD, 720p + RID_MODE( 1280, '+', 720, '+', 'p', 64:27, 2), // HD, 720p, 21:9 anamorphic + RID_MODE( 1680, '+', 720, '+', 'p', 64:27, 3), // 21:9 "1.5k" + RID_MODE( 1920, '+', 1080, '+', 'p', 16:9 , 4), // Full HD, 1080p + RID_MODE( 1929, '+', 1080, '+', 'p', 64:27, 5), // Full HD, 1080p, 21:9 anamorphic + RID_MODE( 2560, '+', 1080, '+', 'p', 64:27, 6), // 21:9 "2.5k" + RID_MODE( 3840, '+', 1080, '+', 'p', 32:9 , 7), // 32:9 "4K" + RID_MODE( 2560, '+', 1440, '+', 'p', 16:9 , 8), // QHD, 1440p + RID_MODE( 3440, '+', 1440, '+', 'p', 64:27, 9), // WQHD + RID_MODE( 5120, '+', 1440, '+', 'p', 32:9 ,10), // 32:9 5k + RID_MODE( 3840, '+', 2160, '+', 'p', 16:9 ,11), // HD "4K", 2160p + RID_MODE( 3840, '+', 2160, '+', 'p', 64:27,12), // UHD "4K", 2160p, 21:9 anamorphic + RID_MODE( 5120, '+', 2160, '+', 'p', 64:27,13), // 21:9 "5K" + RID_MODE( 7680, '+', 2160, '+', 'p', 32:9 ,14), // 32:9 "8K" + RID_MODE( 5120, '+', 2880, '+', 'p', 16:9 ,15), // 2880p + RID_MODE( 5120, '+', 2880, '+', 'p', 64:27,16), // 2880p, 21:9 anamorphic + RID_MODE( 6880, '+', 2880, '+', 'p', 64:27,17), // 21:9 "6K" + RID_MODE(10240, '+', 2880, '+', 'p', 32:9 ,18), // 32:9 "10K" + RID_MODE( 7680, '+', 4320, '+', 'p', 16:9 ,19), // UHD "8K", 4320p + RID_MODE( 7680, '+', 4320, '+', 'p', 64:27,20), // UHD "8K", 4320p, 21:9 anamorphic + RID_MODE(10240, '+', 4320, '+', 'p', 64:27,21), // 21:9 "10K" + RID_MODE(15360, '+', 4320, '+', 'p', 32:9 ,22), // 32:9 "15K" + RID_MODE(11520, '+', 6480, '+', 'p', 16:9 ,23), // UHD "12K", 6480p + RID_MODE(11520, '+', 6480, '+', 'p', 64:27,24), // UHD "12K", 6480p, 21:9 anamorphic + RID_MODE(15360, '+', 6480, '+', 'p', 64:27,25), // 21:9 "15K" + RID_MODE(15360, '+', 8640, '+', 'p', 16:9 ,26), // UHD "16K", 8640p + RID_MODE(15360, '+', 8640, '+', 'p', 64:27,27), // UHD "16K", 8640p, 21:9 anamorphic + RID_MODE(20480, '+', 8640, '+', 'p', 64:27,28) // 21:9 "20K" + // 29...63 Reserved for future +}; +static NvU32 MAX_RID_CODES_COUNT = sizeof(RID) / sizeof(RID[0]) - 1; + +// RID to VIC Mapping +static const NvU8 RID_VIC_MAP[][8] = +{ + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 60, 61, 62, 108, 19, 4, 41, 47 }, // RID 01 + { 65, 66, 67, 109, 68, 69, 70, 71 }, // RID 02 + { 79, 80, 81, 110, 82, 83, 84, 85 }, // RID 03 + { 32, 33, 34, 111, 31, 16, 64, 63 }, // RID 04 + { 72, 73, 74, 112, 75, 76, 77, 78 }, // RID 05 + { 86, 87, 88, 113, 89, 90, 91, 92 }, // RID 06 + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 93, 94, 95, 114, 96, 97, 117, 118 }, // RID 11 + { 103, 104, 105, 116, 106, 107, 119, 120 }, // RID 12 + { 121, 122, 123, 124, 125, 126, 127, 193 }, // RID 13 + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 194, 195, 196, 197, 198, 199, 200, 201 }, // RID 19 + { 202, 203, 204, 205, 206, 207, 208, 209 }, // RID 20 + { 210, 211, 212, 213, 214, 215, 216, 217 }, // RID 21 + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0 } +}; + +// All the frame rate supported in VF +static const NvU16 VF_FRAME_RATE[] = +{ + 0, 24, 25, 30, 48, 50, 60, 100, 120, 144, 200, 240, 300, 360, 400, 480 +}; +static NvU8 MAX_VF_FRAME_RATE_COUNT = sizeof(VF_FRAME_RATE) / sizeof (VF_FRAME_RATE[0])-1; + static const NVT_TIMING PSF_TIMING[]= { NVT_TIMING( 1920,600, 88,2750,'+', 540, 2,5,562,'+',47952,'i',16:9, 0x1, 1, "ITU-R BT.709-5:1080i/24Psf"),//1920x1080i @47.952Hz | 24/PsF | ITU-R BT.709-5 @@ -371,7 +447,7 @@ static const HDMI3DDETAILS HDMI_MANDATORY_3D_FORMATS[] = {20, NVT_HDMI_3D_SUPPORTED_SIDEBYSIDEHALF_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH} // 1920 x 1080i @ 50 Hz }; static NvU32 MAX_HDMI_MANDATORY_3D_FORMAT = sizeof(HDMI_MANDATORY_3D_FORMATS) / sizeof(HDMI_MANDATORY_3D_FORMATS[0]); -static const NVT_VIDEO_INFOFRAME DEFAULT_VIDEO_INFOFRAME = {/*header*/2,2,13, /*byte1*/0, /*byte2*/0x8, /*byte3*/0, /*byte4*/0, /*byte5*/0, /*byte6~13*/0,0,0,0,0,0,0,0}; +static const NVT_VIDEO_INFOFRAME DEFAULT_VIDEO_INFOFRAME = {/*header*/2,2,13, /*byte1*/0, /*byte2*/0x8, /*byte3*/0, /*byte4*/0, /*byte5*/0, /*byte6~13*/0,0,0,0,0,0,0,0, /*byte14~15*/0,0}; static const NVT_AUDIO_INFOFRAME DEFAULT_AUDIO_INFOFRAME = {/*header*/4,1,10, /*byte1*/0, /*byte2*/0, /*byte3*/0, /*byte*/0, /*byte5*/0, /*byte6~10*/0,0,0,0,0}; CODE_SEGMENT(PAGE_DD_CODE) @@ -388,6 +464,7 @@ getExistedCTATimingSeqNumber( case NVT_TYPE_CTA861_DID_T7: case NVT_TYPE_CTA861_DID_T8: case NVT_TYPE_CTA861_DID_T10: + case NVT_TYPE_EDID_861ST: break; default: return count; @@ -395,13 +472,79 @@ getExistedCTATimingSeqNumber( for (i = 0; i< pInfo->total_timings; i++) { - if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == timingType) + if (timingType == NVT_TYPE_EDID_861ST) + { + if (NVT_TIMING_IS_OVT(pInfo->timing[i].etc.flag)) + ++count; + } + else if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == timingType) + { ++count; + } } return count; } +CODE_SEGMENT(PAGE_DD_CODE) +static NvBool isVFDRefreshRate(NvU8 vfdSize, NvU8 *vfd, NvU8 rateIdx) +{ + NvU8 rid, factor, i; + NvU16 rr; + NvBool bFR24, bFR48, bBFR50, bBFR60, bFR144, bFRFactor; + + // frame rate factor {0.5x, 1x, 2x, 4x, 6x, 8x} x 2 + const NvU8 frame_rate_factors[6] = { 1, 2, 4, 8, 12, 16 }; + + rr = VF_FRAME_RATE[rateIdx]; + factor = 0; + + rid = ((const VFD_ONE_BYTE*)vfd)->rid; + if (rid == 0) return NV_FALSE; + + bBFR50 = ((const VFD_ONE_BYTE*)vfd)->bfr50; + // frame rate factor + // If Byte 2 is not present in the VFD, flags 0.5X, 1X and BFR60 shall be considered set + bBFR60 = vfdSize > 1 ? ((const VFD_TWO_BYTE*)vfd)->bfr60 : 1; + bFRFactor = vfdSize > 1 ? ((const VFD_TWO_BYTE*)vfd)->frRate : 3; + + // individual frame rate + bFR24 = ((const VFD_ONE_BYTE*)vfd)->fr24; + if (rr == 24) return bFR24; + + // individual frame rate + bFR48 = vfdSize > 2 ? ((const VFD_THREE_BYTE*)vfd)->fr48 : 0; + if (rr == 48) return bFR48; + + // individual frame rate + bFR144 = vfdSize > 1 ? ((const VFD_TWO_BYTE*)vfd)->fr144 : 0; + if (rr == 144) return bFR144; + + if (rr % (50/2) == 0) + { + if (!bBFR50) return NV_FALSE; + factor = rr / 25; + } + else if (rr % (60/2) == 0) + { + if (!bBFR60) return NV_FALSE; + factor = rr / 30; + } + + for (i = 0; i < COUNT(frame_rate_factors); i++) + { + if (frame_rate_factors[i] == factor) + { + if (bFRFactor & (1 << i)) + return NV_TRUE; + else + break; + } + } + + return NV_FALSE; +} + // parse the 861 detailed timing info CODE_SEGMENT(PAGE_DD_CODE) void parse861ExtDetailedTiming(NvU8 *pEdidExt, @@ -485,7 +628,7 @@ void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, for (i = 0; i < total_svd; i++) { - vic = NVT_GET_CTA_8BIT_VIC(pVic[i]); + vic = NVT_GET_CTA_8BIT_VIC(pVic[i]); if (vic == 0 || vic > MAX_CEA861B_FORMAT) continue; @@ -563,6 +706,120 @@ void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, } } +CODE_SEGMENT(PAGE_DD_CODE) +void parseCta861VideoFormatDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo) +{ + NvU8 i = 0; + NvU8 rateIdx = 0; + NvU8 vfdb_idx = 0; + NvU8 startSeqNum = 0; + NvU8 eachOfDescSize = 0; + NvU32 width = 0; + NvU32 height = 0; + + const VFD_ONE_BYTE *pVFDOneByte = 0 ; + + NVT_TIMING newTiming; + NVT_EDID_INFO *pInfo = (NVT_EDID_INFO *)pRawInfo; + + for (vfdb_idx = 0; vfdb_idx < pExt861->total_vfdb; vfdb_idx++) + { + eachOfDescSize = pExt861->vfdb[vfdb_idx].info.vfd_len + 1; + + if (eachOfDescSize == 0) + { + nvt_assert(0 && "Video Format Descriptor length is 0!\n"); + return; + } + + for (i = 0; i < pExt861->vfdb[vfdb_idx].total_vfd; i++) + { + // data block value sanity check: + if (eachOfDescSize > 2 && (((const VFD_THREE_BYTE*)&pExt861->vfdb[vfdb_idx].video_format_desc[i*eachOfDescSize])->f31_37 != 0)) + nvt_assert(0 && "F31-F37 bits does not be 0 in Byte3!.\n"); + + if (eachOfDescSize > 3 && ((const VFD_FOUR_BYTE*)&pExt861->vfdb[vfdb_idx].video_format_desc[i*eachOfDescSize])->f40_47 !=0) + nvt_assert(0 && "It is not support yet in Byte4!"); + + pVFDOneByte = (const VFD_ONE_BYTE *)&pExt861->vfdb[vfdb_idx].video_format_desc[i*eachOfDescSize]; + + /* + * If any of the following is true, then the RID shall be set to 0: + * 1. If a Video Format not listed in "Table 12 - Resolution Identification (RID) is sent + * 2. if a Video Format with Frame Rates not listed in "Table 13 - AVI InfoFrame Video Format Frame Rate" is sent + * 3. if a Video Format listed in "Table 14 - RID To VIC Mapping" is sent. + */ + // For 1. + if ((pVFDOneByte->rid & NVT_CTA861_VF_RID_MASK) == 0 || pVFDOneByte->rid > MAX_RID_CODES_COUNT) + { + nvt_assert(0 && "shall have a non-zero RID value or RID code value larger than 28"); + continue; + } + + width = RID[pVFDOneByte->rid].HVisible; + height = RID[pVFDOneByte->rid].VVisible; + + // If the Source is sending a Video Format that can be indicated by RID and FR, + // and is not listed in Table 14 (RID to VIC), then it shall set the RID and FR fields to the proper codes + for (rateIdx = 1; rateIdx <= MAX_VF_FRAME_RATE_COUNT; rateIdx++) + { + // For 2. + if (!isVFDRefreshRate(eachOfDescSize, &pExt861->vfdb[vfdb_idx].video_format_desc[i*eachOfDescSize], rateIdx)) + { + continue; + } + + // For 3. + if (VF_FRAME_RATE[rateIdx] < 144 && RID_VIC_MAP[pVFDOneByte->rid][rateIdx-1]) + { + nvt_assert(0 && "RID not allowed since it maps to VIC!"); + continue; + } + + startSeqNum = getExistedCTATimingSeqNumber(pInfo, NVT_TYPE_EDID_861ST); + + NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming)); + + if (NvTiming_CalcOVT(width, height, VF_FRAME_RATE[rateIdx], &newTiming) == NVT_STATUS_SUCCESS) + { + if (pExt861->vfdb[vfdb_idx].info.y420 && newTiming.pclk > NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN) + { + UPDATE_BPC_FOR_COLORFORMAT(newTiming.etc.yuv420, 0, 1, + pInfo->hdmiForumInfo.dc_30bit_420, + pInfo->hdmiForumInfo.dc_36bit_420, 0, + pInfo->hdmiForumInfo.dc_48bit_420); + } + + newTiming.etc.flag |= NVT_FLAG_CTA_OVT_TIMING; + if (pExt861->vfdb[vfdb_idx].info.ntsc) + { + newTiming.etc.flag |= NVT_FLAG_CTA_OVT_FRR_TIMING; + } + + newTiming.etc.status = NVT_STATUS_EDID_861STn(++startSeqNum); + NVT_SNPRINTF((char *)newTiming.etc.name, sizeof(newTiming.etc.name), "CTA861-OVT%d:#%3d:%dx%dx%3d.%03dHz/%s", + (int)pVFDOneByte->rid, + (int)NVT_GET_TIMING_STATUS_SEQ(newTiming.etc.status), + (int)newTiming.HVisible, + (int)newTiming.VVisible, + (int)newTiming.etc.rrx1k/1000, + (int)newTiming.etc.rrx1k%1000, + (newTiming.interlaced ? "I":"P")); + newTiming.etc.name[sizeof(newTiming.etc.name) - 1] = '\0'; + if (!assignNextAvailableTiming(pInfo, &newTiming)) + { + continue; + } + } + else + { + continue; + } + } + } + } +} + // parse the 861B short Yuv420 timing descriptor CODE_SEGMENT(PAGE_DD_CODE) void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, @@ -603,7 +860,6 @@ void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, return; } - for (i = 0; i < total_y420vdb; i++) { vic = NVT_GET_CTA_8BIT_VIC(pYuv420Vic[i]); @@ -735,6 +991,7 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, NvU8 extDTDCount = 0; NvU8 DIDT7Count = 0; NvU8 DIDT10Count = 0; + NvU8 OVTCount = 0; if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) { @@ -765,10 +1022,11 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, else if (NVT_IS_EXT_DTD(pInfo->timing[j].etc.status)) extDTDCount++; else if (NVT_IS_CTA861_DID_T7(pInfo->timing[j].etc.status)) DIDT7Count++; else if (NVT_IS_CTA861_DID_T10(pInfo->timing[j].etc.status)) DIDT10Count++; + else if (NVT_TIMING_IS_OVT(pInfo->timing[j].etc.flag)) OVTCount++; } } - // this only handle single SVR right now + // this only handles single SVR for (i = 0; i < totalSvr; i++) { NvU8 svr = 0; @@ -804,17 +1062,12 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, break; } } - - if (pExt861->valid.NVRDB == 1) - pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; - else - pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; } } else if (svr >= 145 && svr <= 160) { // Interpret as the Nth 20-byte DTD or 6- or 7-byte CVT-based descriptor - // where N = SVR – 144 (for N = 1 to 16) + // where N = SVR - 144 (for N = 1 to 16) kth = svr - 144; if (flag == FROM_CTA861_EXTENSION) @@ -833,18 +1086,24 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, break; } } - - if (pExt861->valid.NVRDB == 1) - pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; - else - pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; - } + } } else if (svr >= 161 && svr <= 175) { // Interpret as the video format indicated by the first VFD of the first VFDB with Frame Rates of Rate Index N // where N = SVR - 160 (for N = 1 to 15) - break; + kth = svr - 160; + if (flag == FROM_CTA861_EXTENSION) + { + for (j = 0; j < pInfo->total_timings; j++) + { + if (kth <= OVTCount) + { + if (NVT_IS_CTA861_OVT_Tn(pInfo->timing[j].etc.flag, pInfo->timing[j].etc.status, kth)) + break; + } + } + } } else if (svr == 254) { @@ -855,15 +1114,11 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, { if (NVT_IS_CTA861_DID_T8_1(pInfo->timing[j].etc.status)) { - if (pExt861->valid.NVRDB == 1) - pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; - else - pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; + kth = 1; break; } } } - break; } else // assign corresponding CEA format's timing from pre-defined CE timing table, EIA861B { @@ -877,13 +1132,7 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, { isMatch = NvTiming_IsTimingExactEqual(&pInfo->timing[j], &preferTiming); if (isMatch && (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_861ST)) - { - if (pExt861->valid.NVRDB == 1) - pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; - else - pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; break; - } } } else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) @@ -892,16 +1141,25 @@ void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, { isMatch = NvTiming_IsTimingExactEqual(&pDisplayID20->timing[j], &preferTiming); if (isMatch && (NVT_GET_TIMING_STATUS_TYPE(pDisplayID20->timing[j].etc.status) == NVT_TYPE_EDID_861ST)) - { - if (pExt861->valid.NVRDB == 1) - pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; - else - pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; break; - } } } } + + if (flag == FROM_CTA861_EXTENSION || flag == FROM_DISPLAYID_13_DATA_BLOCK) + { + if (pExt861->valid.NVRDB == 1) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING; + else if (vic != 0 || kth != 0) + pInfo->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING; + } + else if (flag == FROM_DISPLAYID_20_DATA_BLOCK) + { + if (pExt861->valid.NVRDB == 1) + pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_NATIVE_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; + else if (vic !=0 || kth != 0) + pDisplayID20->timing[j].etc.flag |= NVT_FLAG_CTA_PREFERRED_TIMING | NVT_FLAG_DISPLAYID_2_0_TIMING; + } } } @@ -1423,6 +1681,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, NvU32 vsvdb_index = 0; NvU32 yuv420vdb_index = 0; NvU32 yuv420cmdb_index = 0; + NvU8 vfd_index = 0; NvU8 didT7_index = 0; NvU8 didT8_index = 0; NvU8 didT10_index = 0; @@ -1456,6 +1715,9 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, case NVT_CEA861_TAG_VESA_DTC: case NVT_CEA861_TAG_RSVD: break; + case NVT_CTA861_TAG_VIDEO_FORMAT: + if (payload < 2) return NVT_STATUS_ERR; // no VFD + break; case NVT_CEA861_TAG_VENDOR: if (payload < 3) return NVT_STATUS_ERR; break; @@ -1504,7 +1766,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, } break; default: - break; + break; } return NVT_STATUS_SUCCESS; } @@ -1592,6 +1854,22 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p, vendor_index++; } } + else if (tag == NVT_CTA861_TAG_VIDEO_FORMAT) + { + p861info->vfdb[vfd_index].info.vfd_len = p[i] & 0x03; + p861info->vfdb[vfd_index].info.ntsc = (p[i] & 0x40) >> 6; + p861info->vfdb[vfd_index].info.y420 = (p[i] & 0x80) >> 7; + p861info->vfdb[vfd_index].total_vfd = (NvU8)(payload - 1) / (p861info->vfdb[vfd_index].info.vfd_len + 1); + + i++; payload--; + + for (j = 0; j < payload; j++, i++) + { + p861info->vfdb[vfd_index].video_format_desc[j] = p[i]; + } + + p861info->total_vfdb = ++vfd_index; + } else if (tag == NVT_CEA861_TAG_EXTENDED_FLAG) { if (payload >= 1) @@ -2025,6 +2303,7 @@ NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_V { // Prior RFE 543088 if (pCtrl->video_format_id == 0 && + !(NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag) || NVT_TIMING_IS_OVT(pTiming->etc.flag)) && NVT_GET_TIMING_STATUS_TYPE(pTiming->etc.status) == NVT_TYPE_EDID_861ST) { pCtrl->video_format_id = (NvU8)NVT_GET_TIMING_STATUS_SEQ(pTiming->etc.status); @@ -2040,6 +2319,129 @@ NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_V } } + // setup RID code + if (pCtrl->rid == NVT_INFOFRAME_CTRL_DONTCARE) + { + if (NVT_TYPE_EDID_861ST == NVT_GET_TIMING_STATUS_TYPE(pTiming->etc.status) && + NVT_TIMING_IS_OVT(pTiming->etc.flag)) + { + NvU8 ridIdx = 0; + + // get the correct rid from the name string = CTA861-OVT'%d':xxx + // %d value shall included two digital or one digital character + if (pTiming->etc.name[11] == ':') + { + ridIdx = pTiming->etc.name[10] - '0'; + } + else + { + ridIdx = 10 * (pTiming->etc.name[10] - '0') + (pTiming->etc.name[11] - '0'); + } + + if (ridIdx > NVT_CTA861_RID_1280x720p_16x9 && + ridIdx < NVT_CTA861_RID_20480x8640p_64x27) + { + pCtrl->rid = ridIdx; + } + else + { + pCtrl->rid = NVT_INFOFRAME_CTRL_DONTCARE; + } + } + } + + // setup Video Format Frame Rate + if (pCtrl->rid != NVT_INFOFRAME_CTRL_DONTCARE) + { + switch (pTiming->etc.rr) + { + case 24: + pCtrl->frame_rate = NVT_CTA861_FR_2400; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_2398; + } + break; + case 25: + pCtrl->frame_rate = NVT_CTA861_FR_2500; + break; + case 30: + pCtrl->frame_rate = NVT_CTA861_FR_3000; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_2997; + } + break; + case 48: + pCtrl->frame_rate = NVT_CTA861_FR_48000; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_4795; + } + break; + case 50: + pCtrl->frame_rate = NVT_CTA861_FR_5000; + break; + case 60: + pCtrl->frame_rate = NVT_CTA861_FR_6000; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_5994; + } + break; + case 100: + pCtrl->frame_rate = NVT_CTA861_FR_10000; + break; + case 120: + pCtrl->frame_rate = NVT_CTA861_FR_12000; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_11988; + } + break; + case 144: + pCtrl->frame_rate = NVT_CTA861_FR_14400; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_14386; + } + break; + case 200: + pCtrl->frame_rate = NVT_CTA861_FR_20000; + break; + case 240: + pCtrl->frame_rate = NVT_CTA861_FR_24000; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_23976; + } + break; + case 300: + pCtrl->frame_rate = NVT_CTA861_FR_30000; + break; + case 360: + pCtrl->frame_rate = NVT_CTA861_FR_36000; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_35964; + } + break; + case 400: + pCtrl->frame_rate = NVT_CTA861_FR_40000; + break; + case 480: + pCtrl->frame_rate = NVT_CTA861_FR_48000; + if (NVT_FRR_TIMING_IS_OVT(pTiming->etc.flag)) + { + pCtrl->frame_rate = NVT_CTA861_FR_47952; + } + break; + default: + pCtrl->frame_rate = NVT_INFOFRAME_CTRL_DONTCARE; + break; + } + } + // for HDMI_EXT timing, AVI VIC should be 0. if (NVT_GET_TIMING_STATUS_TYPE(pTiming->etc.status) == NVT_TYPE_HDMI_EXT) { @@ -2125,47 +2527,42 @@ NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_ // init the header pInfoFrame->type = NVT_INFOFRAME_TYPE_VIDEO; - // TODO : This is just to check the version, we still need to change lots of structure - // "NVT_VIDEO_INFOFRAME" / "VIDEO_INFOFRAME" / "DEFAULT_VIDEO_INFOFRAME" / "NVM_DISP_STATE" etc.. - // to accept the new ACE0-3 bits supported in the future. Right now no any sink to support this. - // - // Based on the latest CTA-861-H.pdf file, we need to do following logic to get the correct CTA861 version - // When Y=7, the IDO defines the C, EC and ACE fields, it shall use AVI InfoFrame Version 4. - // When Y < 7, the following algorithm shall be used for AVI InfoFrame version selection: - // if (C=3 and EC=7) - // Sources shall use AVI InfoFrame Version 4. - // Else if (VIC>=128) - // Sources shall use AVI InfoFrame Version 3. - // Else - // Sources shall use AVI InfoFrame Version 2. - // End if - // + // see 6.4 Format of Version 2, 3, and 4 AVI InfoFrames in CTA861-I if (pCtrl) { - if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED) - { - pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; - } - else if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) < NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED) + if (nvt_get_bits(pInfoFrame->byte1, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK, NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT) <= NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420) // this shall be as 0 always. { + if ((pCtrl->rid != NVT_CTA861_RID_NONE) || (pCtrl->frame_rate != NVT_CTA861_FR_NO_DATA)) + { + pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; // just put the logic to get the correct version 4, but it shall not be used at currently stage. + pInfoFrame->length = sizeof(NVT_VIDEO_INFOFRAME) - sizeof(NVT_INFOFRAME_HEADER); // Length == 15 + } + else if ((nvt_get_bits(pInfoFrame->byte2, NVT_VIDEO_INFOFRAME_BYTE2_C1C0_MASK, NVT_VIDEO_INFOFRAME_BYTE2_C1C0_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE2_C1C0_EXT_COLORIMETRY) && //EC2-0 is based on the 7.5.5 at CTA861-G which DCI-P3 bit defined or notat byte4 (nvt_get_bits(pInfoFrame->byte3, NVT_VIDEO_INFOFRAME_BYTE3_EC_MASK, NVT_VIDEO_INFOFRAME_BYTE3_EC_SHIFT) == NVT_VIDEO_INFOFRAME_BYTE3_EC_AdditionalColorExt)) { - pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; // just put the logic to get the correct version 4, but it shall not be used at currently stage. + pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; // just put the logic to get the correct version 4, but it shall not be used at currently stage. + pInfoFrame->length = 14; } else { - pInfoFrame->version = (((pCtrl->video_format_id & NVT_VIDEO_INFOFRAME_BYTE4_VIC7) == NVT_VIDEO_INFOFRAME_BYTE4_VIC7) ? NVT_VIDEO_INFOFRAME_VERSION_3 : + pInfoFrame->version = (((pCtrl->video_format_id & NVT_VIDEO_INFOFRAME_BYTE4_VIC7) != 0) ? NVT_VIDEO_INFOFRAME_VERSION_3 : ((pEdidInfo->ext861.revision >= NVT_CEA861_REV_B) ? NVT_VIDEO_INFOFRAME_VERSION_2 : NVT_VIDEO_INFOFRAME_VERSION_1)); + pInfoFrame->length = 13; } } + else // Y=7, the IDO defineds the C, EC, ACE fileds. In the case the Source shall set the AVI InforFrame Version filed to no less than 3 + { + pInfoFrame->version = NVT_VIDEO_INFOFRAME_VERSION_4; + pInfoFrame->length = 14; + } } else { pInfoFrame->version = (pEdidInfo->ext861.revision >= NVT_CEA861_REV_B) ? NVT_VIDEO_INFOFRAME_VERSION_2 : NVT_VIDEO_INFOFRAME_VERSION_1; + pInfoFrame->length = 13; } - pInfoFrame->length = sizeof(NVT_VIDEO_INFOFRAME) - sizeof(NVT_INFOFRAME_HEADER); if (pInfoFrame->version < NVT_VIDEO_INFOFRAME_VERSION_3) { @@ -2287,6 +2684,34 @@ NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_ pInfoFrame->right_bar_low = (NvU8)(pCtrl->right_bar % 0x100); pInfoFrame->right_bar_high = (NvU8)(pCtrl->right_bar / 0x100); } + + // byte 14-15 + if (pInfoFrame->version >= NVT_VIDEO_INFOFRAME_VERSION_4) + { + if (pCtrl->addition_colorimetry_ext != NVT_INFOFRAME_CTRL_DONTCARE) + { + nvt_nvu8_set_bits(pInfoFrame->byte14, pCtrl->addition_colorimetry_ext, NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_MASK, NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_SHIFT); + } + + if (pCtrl->frame_rate != NVT_INFOFRAME_CTRL_DONTCARE) + { + // Frame rate + nvt_nvu8_set_bits(pInfoFrame->byte14, pCtrl->frame_rate, NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_MASK, NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_SHIFT); + pInfoFrame->byte15 &= NVT_VIDEO_INFOFRAME_BYTE15_FR4_MASK^0xFFU; + pInfoFrame->byte15 |= ((pCtrl->frame_rate & NVT_VIDEO_INFOFRAME_BYTE14_FR4_ONE_BIT_MASK) << NVT_VIDEO_INFOFRAME_BYTE15_FR4_SHIFT) & NVT_VIDEO_INFOFRAME_BYTE15_FR4_MASK; + } + + if (pCtrl->rid != NVT_INFOFRAME_CTRL_DONTCARE) + { + // RID + nvt_nvu8_set_bits(pInfoFrame->byte15, pCtrl->rid, NVT_VIDEO_INFOFRAME_BYTE15_RID_MASK, NVT_VIDEO_INFOFRAME_BYTE15_RID_SHIFT); + } + } + else // version 2 or 3 + { + pInfoFrame->byte14 = 0; + pInfoFrame->byte15 = 0; + } } return NVT_STATUS_SUCCESS; @@ -2602,7 +3027,7 @@ NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe( } else if (pCtrl->EnableQMS) { - nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], 1, + nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], pCtrl->MConst, NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK, NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT); nvt_nvu8_set_bits(pInfoFrame->Data.metadataBytes[0], @@ -2711,6 +3136,16 @@ void NvTiming_ConstructAdaptiveSyncSDP( NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_MASK, NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_SHIFT); } + + if (pCtrl->srCoastingVTotal) + { + nvt_nvu8_set_bits(pSdp->payload.db7, pCtrl->srCoastingVTotal & 0xff, + NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_SHIFT); + nvt_nvu8_set_bits(pSdp->payload.db8, (pCtrl->srCoastingVTotal & 0xff00) >> 8, + NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_MASK, + NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_SHIFT); + } } // Enumerate Psf Timing @@ -3406,7 +3841,6 @@ void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo) default: break; - } } diff --git a/src/common/modeset/timing/nvt_ovt.c b/src/common/modeset/timing/nvt_ovt.c index df81d44a8e..f1bc73a033 100644 --- a/src/common/modeset/timing/nvt_ovt.c +++ b/src/common/modeset/timing/nvt_ovt.c @@ -28,3 +28,266 @@ //***************************************************************************** +#include "nvBinSegment.h" +#include "nvmisc.h" + +#include "nvtiming_pvt.h" + +PUSH_SEGMENTS + +CONS_SEGMENT(PAGE_CONS) + +const NvU32 NVT_OVT_PIXEL_CLOCK_GRANULARITY = 1000; // Resulting Pixel Clock will be a multiple of this +const NvU32 NVT_OVT_MIN_H_TOTAL_GRANULARITY = 8; // Resulting Htotal value will be a multiple of this +const NvU32 NVT_OVT_MIN_V_BLANK_MICROSEC = 460; // Minimum duration of Vblank (us) +const NvU32 NVT_OVT_MIN_V_SYNC_LEADING_EDGE = 400; // Minimum duration of Vsync + Vback (us) +const NvU32 NVT_OVT_MIN_CLOCK_RATE_420 = 590000000; // interface-specific minimum pixel rate for transport of 4:2:0 sample +const NvU32 NVT_OVT_PIXEL_FACTOR_420 = 2; // Worst case of two pixels per link character for pixel rates of MinClockRate420 or more +const NvU32 NVT_OVT_MIN_H_BLANK_444 = 80; // Minimum Hblank width for pixel rates below MinClockRate420 +const NvU32 NVT_OVT_MIN_H_BLANK_420 = 128; // Minimum Hblank width for pixel rates of MinClockRate420 or more +const NvU32 NVT_OVT_MAX_CHUNK_RATE = 650000000; // Maximum rate of chunks of pixels with a power-of-two size +const NvU32 NVT_OVT_AUDIO_PACKET_RATE = 195000; // 192k sample packets + 3k auxiliary data packets +const NvU32 NVT_OVT_AUDIO_PACKET_SIZE = 32; // each packet carries 8 audio sample +const NvU32 NVT_OVT_LINE_OVERHEAD = 32; // interface-specific overhead: 32 pixels/line + +const NvU32 NVT_OVT_H_SYNC_PIXELS = 32; +const NvU32 NVT_OVT_H_BACK_WIDTH = 32; +const NvU32 NVT_OVT_V_SYNC_WIDTH = 8; + +CODE_SEGMENT(PAGE_DD_CODE) +static NvU32 nvFloorPow2_U32(NvU32 x) +{ + return x & ~(x - 1); +} + +CODE_SEGMENT(PAGE_DD_CODE) +static NvU32 computeGCD(NvU32 a, NvU32 b) +{ + NvU32 temp; + while (b != 0) + { + temp = a % b; + if (temp == 0) return b; + a = b; + b = temp; + } + return a; +} + +CODE_SEGMENT(PAGE_DD_CODE) +static NvU32 calculate_aspect_ratio(NVT_TIMING *pT) +{ + NvU32 gcd = computeGCD(pT->HVisible, pT->VVisible); + + if (gcd == 0) + { + pT->etc.aspect = (NvU32)0; + return 0; + } + + return (pT->HVisible / gcd) << 16 | (pT->VVisible / gcd); +} + +/** + * OVT Algorithm Calculations Formula + * + * @brief Sinks can indicate supported video formats with VFD in a VFDB that are not represented by a CTA VIC. + * The timing parameters of those Video Formats are determined by the Optimized Video Timing(OVT) algorithm + * + * @param width : resolution width from RID + * @param height : resolution height from RID + * @param refreshRate : refresh rate x fraction rate + * @param pT : output all the parameters in NVT_TIMING + * + * @return NVT_STATUS_SUCCESS + * + */ +CODE_SEGMENT(PAGE_DD_CODE) +NVT_STATUS NvTiming_CalcOVT(NvU32 width, NvU32 height, NvU32 refreshRate, NVT_TIMING *pT) +{ + NvU32 hTotal = 0; + NvU32 vTotal = 0; + NvU32 maxVRate = refreshRate; + NvU32 vTotalGranularity = 1; + NvU32 resolutionGranularity = 0; + NvU32 minVBlank, minVTotal, minLineRate, minHBlank, minHTotal, vBlank, vSyncPosition; + NvU32 hTotalGranularityChunk, hTotalGranularity, maxAudioPacketsPerLine; + + NvU64 minPixelClockRate = 0LL; + NvU64 pixelClockRate = 0LL; + NvU64 maxActiveTime = 0LL; + NvU64 minLineTime = 0LL; + NvU64 minResolution = 0LL; + NvU32 V = 0; + NvU32 H = 0; + NvU64 R = 0; + + // parameter sanity check + if (width % 8 != 0) + return NVT_STATUS_ERR; + + // ** Preparation ** + // 1. Determine maximum Vrate of frame rate group (see Table 13) and V-Total granularity: + switch (refreshRate) + { + case 24: case 25: case 30: + maxVRate = 30; + vTotalGranularity = 20; + break; + case 48: case 50: case 60: + maxVRate = 60; + vTotalGranularity = 20; + break; + case 100: case 120: + maxVRate = 120; + vTotalGranularity = 5; + break; + case 144: + maxVRate = 144; + vTotalGranularity = 1; + break; + case 200: case 240: + maxVRate = 240; + vTotalGranularity = 5; + break; + case 300: case 360: + maxVRate = 360; + vTotalGranularity = 5; + break; + case 400: case 480: + maxVRate = 480; + vTotalGranularity = 5; + break; + default: + vTotalGranularity = 1; + maxVRate = refreshRate; + nvt_assert (0 && "invalid input refresh rate!"); + } + + // 2. Minimum Vtotal is found from highest frame rate of Vrate group, Vactive and the minimum Vblank time of 460 μSec: + // 2.1 the minimum number of determine the maximum active time. For the sake of precision, it is multiplied by 1,000,000. + maxActiveTime = ((NvU64)1000000000000 / (NvU64)maxVRate) - (NvU64)NVT_OVT_MIN_V_BLANK_MICROSEC * 1000000; + // 2.2 get the minimum line time + minLineTime = maxActiveTime / (NvU64)height; + // 2.3 get the minimum number of VBlank lines. The multiplicand 1000000 is for accuracy, because we multiply it at 2.1 + minVBlank = (NvU32)(NV_UNSIGNED_DIV_CEIL((NvU64)NVT_OVT_MIN_V_BLANK_MICROSEC * (NvU64)1000000, (NvU64)minLineTime)); + // 2.4 get the minimum total number of lines + minVTotal = height + minVBlank; + if (minVTotal % vTotalGranularity !=0) + minVTotal += (vTotalGranularity - (minVTotal % vTotalGranularity)); + + // 3. Find the audio packet rate and use it to determine the required audio packets per line: + // 3.1 determine a minimum line rate + minLineRate = maxVRate * minVTotal; // Hz + // 3.2 The maximum number of audio packets + maxAudioPacketsPerLine = NV_UNSIGNED_DIV_CEIL(NVT_OVT_AUDIO_PACKET_RATE, minLineRate); + + // 4. Find initial minimum horizontal total size, based on audio requirements (1 pixel = 1 character): + minHBlank = NVT_OVT_LINE_OVERHEAD + NVT_OVT_AUDIO_PACKET_SIZE * maxAudioPacketsPerLine; + // 4.1 determine a minimum Horizontal Total pixel (MinHtotal) + minHTotal = width + NV_MAX(NVT_OVT_MIN_H_BLANK_444, minHBlank); + + // 5. Find hTotal and vTotal so that the pixelClockRate is divisible by the pixelClockGranularity, and + // hTotal is divisible by an appropriate processing chunk size: + minPixelClockRate = (NvU64)maxVRate * (NvU64)minHTotal * (NvU64)minVTotal; // Hz + // 5.1 determinate new granularity and minHtotal based on the new granularity + hTotalGranularityChunk = nvNextPow2_U32((NvU32)NV_UNSIGNED_DIV_CEIL(minPixelClockRate, (NvU64)NVT_OVT_MAX_CHUNK_RATE)); + // 5.2 If this value is greater than the 8, it becomes the new horizontal granularity + hTotalGranularity = NV_MAX((NvU64)NVT_OVT_MIN_H_TOTAL_GRANULARITY, hTotalGranularityChunk); + if (minHTotal % hTotalGranularity != 0) + { + minHTotal += (hTotalGranularity - (minHTotal % hTotalGranularity)); + } + // 5.3 optimized by iterating on resolution totals without multiplying by the max refresh rate. + resolutionGranularity = NVT_OVT_PIXEL_CLOCK_GRANULARITY / computeGCD(NVT_OVT_PIXEL_CLOCK_GRANULARITY, maxVRate); + + // ** OVT Timing Search ** + // 5.4 it will repeat until the found pixel clock is greater than the divisible pixel clock of the search at hte previous vTotal value, + // the hTotal and vTotal values of that preceding search are chosen for the video timing + for(;;) + { + minResolution = 0; + V = minVTotal; + + for(;;) + { + H = minHTotal; + R = (NvU64)H * (NvU64)V; + + if (minResolution && R > minResolution) + break; + + while (R % resolutionGranularity || maxVRate * R / nvFloorPow2_U32(H) > NVT_OVT_MAX_CHUNK_RATE) + { + H += hTotalGranularity; + R = (NvU64)H * (NvU64)V; + } + + if (minResolution == 0 || R < minResolution) + { + hTotal = H; + vTotal = V; + minResolution = R; + } + V += vTotalGranularity; + } + + pixelClockRate = maxVRate * minResolution; + + // 6. Check if timing requires adjustments for 4:2:0: + // 6.a Re-calculate minHTotal, in pixels, adjusted for 4:2:0 requirements. (2 pixels = 1 character): + minHTotal = width + NV_MAX(NVT_OVT_MIN_H_BLANK_420, NVT_OVT_PIXEL_FACTOR_420 * minHBlank); + // 6.b If the resulting PixelClockRate allows for 4:2:0, assure that the new Hblank requirement is met, or repeat calculation with new MinHtotal: + if (pixelClockRate >= NVT_OVT_MIN_CLOCK_RATE_420 && hTotal < minHTotal) + { + continue; + } + break; + } + + // ** post-processing ** + // 7. Adjust Vtotal, in lines, to achieve (integer) target Vrate: + vTotal = vTotal * maxVRate / refreshRate; + + // 8. Find Vsync leading edge: + vBlank = vTotal - height; + vSyncPosition = (NvU32)NV_UNSIGNED_DIV_CEIL(((NvU64)NVT_OVT_MIN_V_SYNC_LEADING_EDGE * (NvU64)pixelClockRate), ((NvU64)1000000 * (NvU64)hTotal)); + + // 10. fill in the essential timing info for output + pT->HVisible = (NvU16)width; + pT->HTotal = (NvU16)hTotal; + pT->HFrontPorch = (NvU16)(hTotal - width - NVT_OVT_H_SYNC_PIXELS - NVT_OVT_H_BACK_WIDTH); + pT->HSyncWidth = (NvU16)NVT_OVT_H_SYNC_PIXELS; + pT->VVisible = (NvU16)height; + pT->VTotal = (NvU16)vTotal; + pT->VSyncWidth = (NvU16)NVT_OVT_V_SYNC_WIDTH; + pT->VFrontPorch = (NvU16)(vBlank - vSyncPosition); + pT->pclk = (NvU32)(pixelClockRate /*Hz*/ / 1000 + 5) / 10; //convert to 10Khz + pT->HSyncPol = NVT_H_SYNC_POSITIVE; + pT->VSyncPol = NVT_V_SYNC_POSITIVE; + pT->HBorder = pT->VBorder = 0; // not supported + pT->interlaced = 0; // not supported + // fill in the extra timing info + pT->etc.flag = 0; + pT->etc.rr = (NvU16)refreshRate; + pT->etc.rrx1k = (NvU32)axb_div_c_64((NvU64)pT->pclk, (NvU64)10000 * (NvU64)1000, (NvU64)pT->HTotal*(NvU64)pT->VTotal); + pT->etc.aspect = calculate_aspect_ratio(pT); + pT->etc.rep = 0x1; + NVT_SNPRINTF((char *)pT->etc.name, 40, "CTA861-OVT:%dx%dx%dHz", width, height, refreshRate); + pT->etc.name[39] = '\0'; + + return NVT_STATUS_SUCCESS; +} + +CODE_SEGMENT(PAGE_DD_CODE) +NvBool NvTiming_IsTimingOVT(const NVT_TIMING *pTiming) +{ + // Check from the Timing Type + if (pTiming->etc.flag & NVT_FLAG_CTA_OVT_TIMING) + { + return NV_TRUE; + } + return NV_FALSE; +} + +POP_SEGMENTS diff --git a/src/common/modeset/timing/nvtiming.h b/src/common/modeset/timing/nvtiming.h index d818493381..dcc7eb731f 100644 --- a/src/common/modeset/timing/nvtiming.h +++ b/src/common/modeset/timing/nvtiming.h @@ -114,6 +114,13 @@ typedef union tagNVT_COLORDEPTH (_colorFormat).bpc.bpc8 ? NVT_EDID_VIDEOSIGNAL_BPC_8 : \ (_colorFormat).bpc.bpc6 ? NVT_EDID_VIDEOSIGNAL_BPC_6 : NVT_EDID_VIDEOSIGNAL_BPC_NOT_DEFINED +#define NVT_COLORDEPTH_LOWEREST_BPC(_colorFormat) \ + (_colorFormat).bpc.bpc6 ? NVT_EDID_VIDEOSIGNAL_BPC_6 : \ + (_colorFormat).bpc.bpc8 ? NVT_EDID_VIDEOSIGNAL_BPC_8 : \ + (_colorFormat).bpc.bpc10 ? NVT_EDID_VIDEOSIGNAL_BPC_10 : \ + (_colorFormat).bpc.bpc12 ? NVT_EDID_VIDEOSIGNAL_BPC_12 : \ + (_colorFormat).bpc.bpc16 ? NVT_EDID_VIDEOSIGNAL_BPC_16 : NVT_EDID_VIDEOSIGNAL_BPC_NOT_DEFINED + typedef struct tagNVT_TIMINGEXT { NvU32 flag; // reserve for NV h/w based enhancement like double-scan. @@ -430,6 +437,7 @@ typedef enum NVT_TV_FORMAT #define NVT_STATUS_CTA861_DID_T7N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T7, n) #define NVT_STATUS_CTA861_DID_T8N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T8, n) #define NVT_STATUS_CTA861_DID_T10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T10, n) +#define NVT_STATUS_CTA861_OVT_Tn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_OVT, n) //******************************** // CEA/EIA 861 related EDID info @@ -469,7 +477,7 @@ typedef enum NVT_TV_FORMAT #define NVT_CEA861_TAG_VENDOR 3 // Vendor Specific Data Block #define NVT_CEA861_TAG_SPEAKER_ALLOC 4 // Speaker Allocation Data Block #define NVT_CEA861_TAG_VESA_DTC 5 // VESA DTC data block -#define NVT_CEA861_TAG_RSVD1 6 // reserved block +#define NVT_CTA861_TAG_VIDEO_FORMAT 6 // Video Format Data Block in CTA861.6 #define NVT_CEA861_TAG_EXTENDED_FLAG 7 // use Extended Tag // // the extended tag codes when NVT_CEA861_TAG_EXTENDED_FLAG @@ -563,7 +571,7 @@ typedef enum NVT_TV_FORMAT // information but where the vertical frequency is adjusted by a factor of // 1000/1001 (i.e., 24/1.001, 30/1.001, 60/1.001, 120/1.001 or 240/1.001). // Excluding ceaIndex 1 640x480 which is a PC Mode. -#define NVT_CEA861_TIMING_FRR(_VID_, _RR_) ((_VID_) > 1 && ((_RR_) % 6) == 0) +#define NVT_CTA861_TIMING_FRR(_VID_, _RR_) ((_VID_) > 1 && ((_RR_) % 6) == 0) #define NVT_CEA861_640X480P_59940HZ_4X3 1 // Video Identification Code: format 1 #define NVT_CEA861_720X480P_59940HZ_4X3 2 // Video Identification Code: format 2 #define NVT_CEA861_720X480P_59940HZ_16X9 3 // Video Identification Code: format 3 @@ -734,6 +742,66 @@ typedef enum NVT_TV_FORMAT // NVT_CEA861_1280X720P_100000HZ_16X9, // NVT_CEA861_1280X720P_119880HZ_16X9 +// According to CEA-861-I Spec. +// Table 11 - Resoution Identification (RID) +#define NVT_CTA861_OVT_TIMING_FRR(_FLAG_, _RR_) (((_FLAG_) & (NVT_FLAG_CTA_OVT_TIMING)) != 0 && ((_RR_) % 6) == 0 && (_RR_) != 300) +#define NVT_CTA861_RID_NONE NVT_INFOFRAME_CTRL_DONTCARE +#define NVT_CTA861_RID_1280x720p_16x9 1 +#define NVT_CTA861_RID_1280x720p_64x27 2 +#define NVT_CTA861_RID_1680x720p_64x27 3 +#define NVT_CTA861_RID_1920x1080p_16x9 4 +#define NVT_CTA861_RID_1920x1080p_64x27 5 +#define NVT_CTA861_RID_2560x1080p_64x27 6 +#define NVT_CTA861_RID_3840x1080p_32x9 7 +#define NVT_CTA861_RID_2560x1440p_16x9 8 +#define NVT_CTA861_RID_3440x1440p_64x27 9 +#define NVT_CTA861_RID_5120x1440p_32x9 10 +#define NVT_CTA861_RID_3840x2160p_16x9 11 +#define NVT_CTA861_RID_3840x2160p_64x27 12 +#define NVT_CTA861_RID_5120x2160p_64x27 13 +#define NVT_CTA861_RID_7680x2160p_32x9 14 +#define NVT_CTA861_RID_5120x2880p_16x9 15 +#define NVT_CTA861_RID_5120x2880p_64x27 16 +#define NVT_CTA861_RID_6880x2880p_64x27 17 +#define NVT_CTA861_RID_10240x2880p_32x9 18 +#define NVT_CTA861_RID_7680x4320p_16x9 19 +#define NVT_CTA861_RID_7680x4320p_64x27 20 +#define NVT_CTA861_RID_10240x4320p_64x27 21 +#define NVT_CTA861_RID_15360x4320p_32x9 22 +#define NVT_CTA861_RID_11520x6480p_16x9 23 +#define NVT_CTA861_RID_11520x6480p_64x27 24 +#define NVT_CTA861_RID_15360x6480p_64x27 25 +#define NVT_CTA861_RID_15360x8640p_16x9 26 +#define NVT_CTA861_RID_15360x8640p_64x27 27 +#define NVT_CTA861_RID_20480x8640p_64x27 28 + +// Table 12 - AVI InfoFrame Video Format Frame Rate +#define NVT_CTA861_FR_NO_DATA NVT_INFOFRAME_CTRL_DONTCARE +#define NVT_CTA861_FR_2398 1 +#define NVT_CTA861_FR_2400 2 +#define NVT_CTA861_FR_2500 3 +#define NVT_CTA861_FR_2997 4 +#define NVT_CTA861_FR_3000 5 +#define NVT_CTA861_FR_4795 6 +#define NVT_CTA861_FR_4800 7 +#define NVT_CTA861_FR_5000 8 +#define NVT_CTA861_FR_5994 9 +#define NVT_CTA861_FR_6000 10 +#define NVT_CTA861_FR_10000 11 +#define NVT_CTA861_FR_11988 12 +#define NVT_CTA861_FR_12000 13 +#define NVT_CTA861_FR_14386 14 +#define NVT_CTA861_FR_14400 15 +#define NVT_CTA861_FR_20000 16 +#define NVT_CTA861_FR_23976 17 +#define NVT_CTA861_FR_24000 18 +#define NVT_CTA861_FR_30000 19 +#define NVT_CTA861_FR_35964 20 +#define NVT_CTA861_FR_36000 21 +#define NVT_CTA861_FR_40000 22 +#define NVT_CTA861_FR_47952 23 +#define NVT_CTA861_FR_48000 24 + //************************* // short audio descriptor //************************* @@ -845,7 +913,68 @@ typedef struct VSVDB_DATA NvU8 vendor_data[NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH]; } VSVDB_DATA; +//******************************* +// Video Format Data Block (VFDB) +//******************************* + +#define NVT_CTA861_VF_MAX_BLOCKS 4 +#define NVT_CTA861_VF_MAX_DESCRIPTORS 30 + +#define NVT_CTA861_VF_RID_MASK 0x3F + +typedef struct tagNVT_RID_CODES +{ + NvU16 HVisible; // horizontal visible + NvU8 HSyncPol; // horizontal sync polarity: 1-negative, 0-positive + NvU16 VVisible; // vertical visible + NvU8 VSyncPol; // vertical sync polarity: 1-negative, 0-positive + NvU16 interlaced; // 1-interlaced, 0-progressive + NvU32 aspect; // the display aspect ratio Hi(aspect):horizontal-aspect, Low(aspect):vertical-aspect + NvU8 rid; // Resolution Identification (RID) +} NVT_RID_CODES; + #pragma pack(1) +typedef struct tagVFD_ONE_BYTE +{ + NvU8 rid : 6; + NvU8 fr24 : 1; + NvU8 bfr50 : 1; +} VFD_ONE_BYTE; + +typedef struct tagVFD_TWO_BYTE +{ + VFD_ONE_BYTE in_onebyte; + NvU8 frRate : 6; + NvU8 fr144 : 1; + NvU8 bfr60 : 1; +} VFD_TWO_BYTE; + +typedef struct tagVFD_THREE_BYTE +{ + VFD_TWO_BYTE in_twobyte; + NvU8 fr48 : 1; + NvU8 f31_37 : 7; +} VFD_THREE_BYTE; + +typedef struct tagVFD_FOUR_BYTE +{ + VFD_THREE_BYTE in_threebyte; + NvU8 f40_47; +} VFD_FOUR_BYTE; + +typedef struct tagVFDB_DATA +{ + struct { + NvU8 vfd_len : 2; + NvU8 f22_25 : 4; + NvU8 ntsc : 1; + NvU8 y420 : 1; + } info; + + NvU8 total_vfd; + NvU8 video_format_desc[NVT_CTA861_VF_MAX_DESCRIPTORS]; +} VFDB_DATA; + typedef struct tagNVT_DV_STATIC_METADATA_TYPE0 { // first byte @@ -1290,6 +1419,10 @@ typedef struct tagEDID_CEA861_INFO // vendor specific video data NvU8 total_vsvdb; VSVDB_DATA vsvdb[NVT_CEA861_VSVDB_MAX_BLOCKS]; + + // video format data + NvU8 total_vfdb; + VFDB_DATA vfdb[NVT_CTA861_VF_MAX_BLOCKS]; // indicates which of the extended data blocks below contain valid data excluding extended blocks with total count NVT_VALID_EXTENDED_BLOCKS valid; @@ -2858,6 +2991,7 @@ typedef enum NVT_PROTOCOL_UNKNOWN = 0, NVT_PROTOCOL_DP = 1, NVT_PROTOCOL_HDMI = 2, + NVT_PROTOCOL_DVI = 3, } NVT_PROTOCOL; // the display interface/connector claimed by the EDID @@ -2870,14 +3004,14 @@ typedef enum // the EDID extension TAG -#define NVT_EDID_EXTENSION_CTA 0x02 // CTA 861 series extensions -#define NVT_EDID_EXTENSION_VTB 0x10 // video timing block extension -#define NVT_EDID_EXTENSION_DI 0x40 // display information extension -#define NVT_EDID_EXTENSION_LS 0x50 // localized string extension -#define NVT_EDID_EXTENSION_DPVL 0x60 // digital packet video link extension -#define NVT_EDID_EXTENSION_DISPLAYID 0x70 // display id -#define NVT_EDID_EXTENSION_BM 0xF0 // extension block map -#define NVT_EDID_EXTENSION_OEM 0xFF // extension defined by the display manufacturer +#define NVT_EDID_EXTENSION_CTA 0x02 // CTA 861 series extensions +#define NVT_EDID_EXTENSION_VTB 0x10 // video timing block extension +#define NVT_EDID_EXTENSION_DI 0x40 // display information extension +#define NVT_EDID_EXTENSION_LS 0x50 // localized string extension +#define NVT_EDID_EXTENSION_DPVL 0x60 // digital packet video link extension +#define NVT_EDID_EXTENSION_DISPLAYID 0x70 // display id +#define NVT_EDID_EXTENSION_BM 0xF0 // extension block map +#define NVT_EDID_EXTENSION_OEM 0xFF // extension defined by the display manufacturer //************************************ // Audio and Video Infoframe Control @@ -2906,6 +3040,9 @@ typedef struct tagNVT_VIDEO_INFOFRAME_CTRL NvU16 bottom_bar; NvU16 left_bar; NvU16 right_bar; + NvU8 addition_colorimetry_ext; + NvU8 frame_rate; + NvU8 rid; }NVT_VIDEO_INFOFRAME_CTRL; // @@ -2922,7 +3059,7 @@ typedef struct tagNVT_AUDIO_INFOFRAME_CTRL typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_CTRL { - NvU32 Enable; + NvU8 Enable; NvU8 HDMIRevision; NvU8 HDMIFormat; NvU8 HDMI_VIC; @@ -2950,12 +3087,14 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL NvU32 EnableQMS; NvU32 NextTFR; NvU32 Sync; + NvU32 MConst; } NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL; typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL { NvU32 minVTotal; NvU32 targetRefreshRate; + NvU32 srCoastingVTotal; NvBool bFixedVTotal; NvBool bRefreshRateDivider; }NVT_ADAPTIVE_SYNC_SDP_CTRL; @@ -3032,6 +3171,10 @@ typedef struct tagNVT_VIDEO_INFOFRAME NvU8 left_bar_high; NvU8 right_bar_low; NvU8 right_bar_high; + + // byte 14~15 + NvU8 byte14; + NvU8 byte15; }NVT_VIDEO_INFOFRAME; // #define NVT_VIDEO_INFOFRAME_VERSION_1 1 @@ -3186,8 +3329,17 @@ typedef struct tagNVT_VIDEO_INFOFRAME #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_MASK 0xFF #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_SHIFT 0 // -#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_MASK 0x0F -#define NVT_VIDEO_INFOFRAME_BYTE14_RESERVED_SHIFT 0 +#define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_MASK 0x0F +#define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_SHIFT 0 +#define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_NODATA 0 +#define NVT_VIDEO_INFOFRAME_BYTE14_FR4_ONE_BIT_MASK 0x10 +#define NVT_VIDEO_INFOFRAME_BYTE15_FR4_MASK 0x40 +#define NVT_VIDEO_INFOFRAME_BYTE15_FR4_NODATA 0 +#define NVT_VIDEO_INFOFRAME_BYTE15_FR4_SHIFT 2 +// +#define NVT_VIDEO_INFOFRAME_BYTE15_RID_MASK 0x3F +#define NVT_VIDEO_INFOFRAME_BYTE15_RID_SHIFT 0 +#define NVT_VIDEO_INFOFRAME_BYTE15_RID_NODATA 0 // #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_MASK 0xF0 #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_SHIFT 4 @@ -3252,7 +3404,21 @@ typedef struct NvU16 topBar; NvU16 bottomBar; NvU16 leftBar; - NvU16 rightBar; + NvU16 rightBar; + + // byte 14~15 + struct + { + NvU8 fr_low : 4; + NvU8 ace : 4; + } byte14; + + struct + { + NvU8 rid : 6; + NvU8 fr_hi : 1; + NvU8 rsvd_bits_byte15 : 1; + }byte15; } NVT_VIDEO_INFOFRAME_OVERRIDE; #pragma pack() @@ -3302,6 +3468,11 @@ typedef struct #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_PR_MASK 0xF // pixel repetitions #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_CN1CN0_MASK 0x3 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_YQ1YQ0_MASK 0x3 // YCC quantization +// +#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE14_FR0FR3_MASK 0xF // Frame rate 0-3 bits in Byte14 +#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE14_ACE0ACE3_MASK 0xF // Additional Colorimetry Extension +#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE15_RID0RID5_MASK 0x3F // Resolution Identification +#define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE15_FR4_MASK 0x1 // Frame rate 4th bit in Byte 15 // audio infoframe structure typedef struct tagNVT_AUDIO_INFOFRAME @@ -3778,9 +3949,9 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME #define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0 #define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0 #define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1 -#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK 0x01 +#define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK 0x02 #define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT 1 -#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK 0x01 +#define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK 0x04 #define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_SHIFT 2 #define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_DISABLE 0 #define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_ENABLE 1 @@ -3793,7 +3964,7 @@ typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME #define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0 #define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1 -#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK 0x1f +#define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK 0xf8 #define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_SHIFT 3 #define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03 @@ -4622,7 +4793,7 @@ typedef struct tagNVT_DPCD #define NVT_DPCD_LANE_COUNT_8 8 // note: the values of NVT_COLOR_FORMAT_* are fixed in order to match the equivalent NV classes -typedef enum +typedef enum _NVT_COLOR_FORMAT { NVT_COLOR_FORMAT_RGB = 0, NVT_COLOR_FORMAT_YCbCr422 = 1, @@ -5617,6 +5788,8 @@ typedef enum #define NVT_FLAG_DISPLAYID_2_0_TIMING 0x00800000 // this one for the CTA861 embedded in DID20 #define NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated #define NVT_FLAG_CTA_NATIVE_TIMING 0x02000000 // NVRDB defined +#define NVT_FLAG_CTA_OVT_TIMING 0x04000000 // CTA861 CTA OVT Timing +#define NVT_FLAG_CTA_OVT_FRR_TIMING 0x08000000 // CTA861 CTA OVT Timing supported ntsc #define NVT_FLAG_INTERLACED_MASK (NVT_FLAG_INTERLACED_TIMING | NVT_FLAG_INTERLACED_TIMING2) @@ -5655,6 +5828,10 @@ NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is10 NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width, NvU32 height, NvU32 rr, NvU32 deltaHBlank, NvU32 vBlankMicroSec, NvBool isEarlyVSync, NVT_TIMING *pT); NvBool NvTiming_IsTimingCVTRB(const NVT_TIMING *pTiming); +// OVT timing calculation +NVT_STATUS NvTiming_CalcOVT(NvU32 width, NvU32 height, NvU32 rr, NVT_TIMING *pT); +NvBool NvTiming_IsTimingOVT(const NVT_TIMING *pTiming); + // CEA/EIA/Psf timing NVT_STATUS NvTiming_CalcCEA861bTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NvU32 pixelRepeatCount, NVT_TIMING *pT); NVT_STATUS NvTiming_EnumCEA861bTiming(NvU32 ceaFormat, NVT_TIMING *pT); @@ -5668,6 +5845,7 @@ NVT_STATUS NvTiming_EnumHdmiVsdbExtendedTiming(NvU32 hdmi_vic, NVT_TIMING *pT); NVT_STATUS NvTiming_GetTvTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NvU32 tvFormat, NVT_TIMING *pT); // Get EDID timing +NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k, NvU32 pclk); NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k); NVT_STATUS NvTiming_GetEdidTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT); @@ -5679,7 +5857,6 @@ NVT_STATUS NvTiming_GetHDMIStereoMandatoryFormatDetail(const NvU8 vic, NvU16 *pS // EDID based AspectRatio Timing NVT_STATUS NvTiming_GetEDIDBasedASPRTiming(NvU16 width, NvU16 height, NvU16 rr, NVT_EDID_INFO *pEI, NVT_TIMING *ft); - // EDID or DISPLAYID2 version NvU32 NvTiming_GetVESADisplayDescriptorVersion(NvU8 *rawData, NvU32 *pVer); @@ -5738,11 +5915,15 @@ NVT_STATUS NvTiming_GetDTD1Timing (NVT_EDID_INFO * pEdidInfo, NVT_TIMING * pT); #define NVT_IS_CTA861_DID_T8_1(d) ((NVT_IS_CTA861_DID_T8((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1)) #define NVT_IS_CTA861_DID_T10n(d, n) ((NVT_IS_CTA861_DID_T10((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n)) +#define NVT_IS_CTA861_OVT_Tn(flag, status, n) ((0 != (NVT_FLAG_CTA_OVT_TIMING & (flag))) && (NVT_GET_TIMING_STATUS_SEQ((status)) == n)) + #define NVT_DID20_TIMING_IS_CTA861(flag, status) ((NVT_IS_CTA861((status))) && (0 != (NVT_FLAG_DISPLAYID_2_0_TIMING & (flag)))) #define NVT_PREFERRED_TIMING_IS_DTD1(flag, status) ((NVT_IS_DTD1((status))) && (0 != (NVT_FLAG_DTD1_PREFERRED_TIMING & (flag)))) #define NVT_PREFERRED_TIMING_IS_DISPLAYID(flag) (0 != (NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING & flag)) #define NVT_PREFERRED_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_PREFERRED_TIMING & flag)) #define NVT_NATIVE_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_NATIVE_TIMING & flag)) +#define NVT_TIMING_IS_OVT(flag) (0 != (NVT_FLAG_CTA_OVT_TIMING & flag)) +#define NVT_FRR_TIMING_IS_OVT(flag) (0 != (NVT_FLAG_CTA_OVT_FRR_TIMING & flag)) #ifdef __cplusplus } diff --git a/src/common/modeset/timing/nvtiming_pvt.h b/src/common/modeset/timing/nvtiming_pvt.h index ce044da407..c353e501aa 100644 --- a/src/common/modeset/timing/nvtiming_pvt.h +++ b/src/common/modeset/timing/nvtiming_pvt.h @@ -72,6 +72,7 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *pEdid, NvU32 size, NVT_EDID_CEA861_INF void parse861ExtDetailedTiming(NvU8 *pEdidExt, NvU8 basicCaps, NVT_EDID_INFO *pInfo); void parse861bShortTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parse861bShortYuv420Timing(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); +void parseCta861VideoFormatDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo); void parseCta861NativeOrPreferredTiming(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); void parseCta861VsvdbBlocks(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag); @@ -94,7 +95,7 @@ NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT); NvU32 isHdmi3DStereoType(NvU8 StereoStructureType); NvU32 getCEA861TimingAspectRatio(NvU32 vic); -NvU8 getHighestPrioritySVRIdx(NvU8 svr); +NvU8 getHighestPrioritySVRIdx(const NVT_EDID_CEA861_INFO *pExt861); void SetActiveSpaceForHDMI3DStereo(const NVT_TIMING *pTiming, NVT_EXT_TIMING *pExtTiming); void AddModeToSupportMap(HDMI3DSUPPORTMAP * pMap, NvU8 vic, NvU8 structure, NvU8 Detail); void getMonitorDescriptorString(NvU8 *pEdid, NvU8 tag, char *str, int onceOnly); diff --git a/src/common/nvlink/inband/interface/nvlink_inband_msg.h b/src/common/nvlink/inband/interface/nvlink_inband_msg.h index 26e71a4a3f..4d0e618512 100644 --- a/src/common/nvlink/inband/interface/nvlink_inband_msg.h +++ b/src/common/nvlink/inband/interface/nvlink_inband_msg.h @@ -37,7 +37,7 @@ * - Avoid conditional fields in the structs. * - Avoid nested and complex structs. Keep them simple and flat for ease of encoding and decoding. * - Avoid embedded pointers. Flexible arrays at the end of the struct are allowed. - * - Always use the packed struct to typecast inband messages. More details: + * - Always use the packed struct to typecast inband messages. More details: * - Always have reserved flags or fields to CYA given the stable ABI conditions. */ @@ -50,17 +50,22 @@ #include "nvstatus.h" #include "nvstatuscodes.h" -#define NVLINK_INBAND_MAX_MSG_SIZE 4096 +#define NVLINK_INBAND_MAX_MSG_SIZE 5120 #define NVLINK_INBAND_MSG_MAGIC_ID_FM 0xadbc /* Nvlink Inband messages types */ -#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REQ 0 -#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP 1 -#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ 2 -#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP 3 -#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ 4 -#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ_V2 5 -#define NVLINK_INBAND_MSG_TYPE_MAX 6 +#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REQ 0 +#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP 1 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ 2 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP 3 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_RELEASE_REQ 4 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ_V2 5 +#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_UPDATE_REQ 6 +#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REPLAY_REQ 7 +#define NVLINK_INBAND_MSG_TYPE_GPU_PROBE_REPLAY_RSP NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REPLAY_REQ 8 +#define NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REPLAY_RSP NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP +#define NVLINK_INBAND_MSG_TYPE_MAX 9 /* Nvlink Inband message packet header */ typedef struct @@ -74,6 +79,7 @@ typedef struct } nvlink_inband_msg_header_t; #define NVLINK_INBAND_GPU_PROBE_CAPS_SRIOV_ENABLED NVBIT(0) +#define NVLINK_INBAND_GPU_PROBE_CAPS_PROBE_UPDATE NVBIT(1) /* Add more caps as need in the future */ @@ -109,6 +115,11 @@ typedef struct #define NVLINK_INBAND_FM_CAPS_BW_MODE_3QUARTER NVBIT64(4) #define NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2 NVBIT64(5) +#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0 +#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0 +#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1 +#define NVLINK_INBAND_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2 + typedef struct { NvU64 gpuHandle; /* Unique handle assigned by initialization entity for this GPU */ @@ -122,7 +133,8 @@ typedef struct NvU64 flaAddressRange; /* GPU FLA address range */ NvU32 linkMaskToBeReduced; /* bit mask of unused NVLink ports for P2P */ NvU32 cliqueId; /* Fabric Clique Id */ - NvU8 reserved[24]; /* For future use. Must be initialized to zero */ + NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */ + NvU8 reserved[20]; /* For future use. Must be initialized to zero */ } nvlink_inband_gpu_probe_rsp_t; typedef struct @@ -131,6 +143,20 @@ typedef struct nvlink_inband_gpu_probe_rsp_t probeRsp; } nvlink_inband_gpu_probe_rsp_msg_t; +typedef struct +{ + NvU64 gpuHandle; /* Unique handle assigned by initialization entity for this GPU */ + NvU32 cliqueId; /* Fabric Clique Id*/ + NvU32 fabricHealthMask; /* Mask containing bits indicating various fabric health parameters */ + NvU8 reserved[32]; /* For future use. Must be initialized to zero */ +} nvlink_inband_gpu_probe_update_req_t; + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_gpu_probe_update_req_t probeUpdate; +} nvlink_inband_gpu_probe_update_req_msg_t; + typedef struct { NvU64 mcAllocSize; /* Multicast allocation size requested */ @@ -203,6 +229,58 @@ typedef struct nvlink_inband_mc_team_release_req_t mcTeamReleaseReq; } nvlink_inband_mc_team_release_req_msg_t; +typedef struct +{ + /* Fields to be replayed */ + NvU64 gpuHandle; /* Unique handle that was provided by FM pre-migration. */ + + /* Other fields from the request */ + NvU64 pciInfo; /* Encoded as Domain(63:32):Bus(15:8):Device(0:7). (debug only) */ + NvU8 moduleId; /* GPIO based physical/module ID of the GPU. (debug only) */ + NvUuid gpuUuid; /* UUID of the GPU. (debug only) */ + NvU64 discoveredLinkMask; /* GPU's discovered NVLink mask info. (debug only) */ + NvU64 enabledLinkMask; /* GPU's currently enabled NvLink mask info. (debug only) */ + + NvU32 gpuCapMask; /* GPU capabilities, one of NVLINK_INBAND_GPU_PROBE_CAPS */ + NvU8 bwMode; /* NVLink bandwidth mode, one of NVLINK_INBAND_BW_MODE */ + NvU8 reserved[31]; /* For future use. Must be initialized to zero */ +} nvlink_inband_gpu_probe_replay_req_t; + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_gpu_probe_replay_req_t probeReplayReq; +} nvlink_inband_gpu_probe_replay_req_msg_t; + +typedef nvlink_inband_gpu_probe_rsp_t nvlink_inband_gpu_probe_replay_rsp_t; +typedef nvlink_inband_gpu_probe_rsp_msg_t nvlink_inband_gpu_probe_replay_rsp_msg_t; + +typedef struct +{ + /* Fields to be replayed */ + NvU64 mcTeamHandle; /* Unique handle assigned for this Multicast team */ + NvU64 mcAddressBase; /* FLA starting address assigned for the Multicast slot */ + NvU64 mcAddressSize; /* Size of FLA assigned to the Multicast slot */ + + /* Other fields from the request */ + NvU64 mcAllocSize; /* Multicast allocation size requested */ + NvU32 flags; /* For future use. Must be initialized to zero */ + NvU8 reserved[8]; /* For future use. Must be initialized to zero */ + NvU16 numGpuHandles; /* Number of GPUs in this team */ + NvU16 numKeys; /* Number of keys (a.k.a request ID) used by FM to send response */ + NvU64 gpuHandlesAndKeys[]; /* Array of probed handles and keys, should be last */ +} nvlink_inband_mc_team_setup_replay_req_t; + + +typedef struct +{ + nvlink_inband_msg_header_t msgHdr; + nvlink_inband_mc_team_setup_replay_req_t mcTeamSetupReplayReq; +} nvlink_inband_mc_team_setup_replay_req_msg_t; + +typedef nvlink_inband_mc_team_setup_rsp_t nvlink_inband_mc_team_setup_replay_rsp_t; +typedef nvlink_inband_mc_team_setup_rsp_msg_t nvlink_inband_mc_team_setup_replay_rsp_msg_t; + #pragma pack(pop) /********************* Don't add any message structs after this line ******************************/ diff --git a/src/common/nvlink/interface/nvlink.h b/src/common/nvlink/interface/nvlink.h index 404836136c..8ddae4494b 100644 --- a/src/common/nvlink/interface/nvlink.h +++ b/src/common/nvlink/interface/nvlink.h @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2014-2023 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ // // nvlink.h @@ -233,6 +234,8 @@ struct nvlink_link // Has INITNEGOTIATE received CONFIG_GOOD (NVL3.0+) NvBool bInitnegotiateConfigGood; + NvBool bCciManaged; + // Power state transition status enum { @@ -279,6 +282,7 @@ struct nvlink_link_handlers NV_API_CALL NvlStatus (*read_discovery_token) (struct nvlink_link *link, NvU64 *token); NV_API_CALL void (*training_complete) (struct nvlink_link *link); NV_API_CALL void (*get_uphy_load) (struct nvlink_link *link, NvBool* bUnlocked); + NV_API_CALL NvlStatus (*get_cci_link_mode) (struct nvlink_link *link, NvU64 *mode); NV_API_CALL NvlStatus (*ali_training) (struct nvlink_link *link); }; @@ -352,6 +356,7 @@ typedef struct nvlink_inband_data nvlink_inband_data; #define NVLINK_LINKSTATE_INITPHASE5 0x1B // INITPHASE5 #define NVLINK_LINKSTATE_ALI 0x1C // ALI #define NVLINK_LINKSTATE_ACTIVE_PENDING 0x1D // Intermediate state for a link going to active +#define NVLINK_LINKSTATE_TRAINING_CCI 0x1E // Intermediate state for a link that is still training #define NVLINK_LINKSTATE_INVALID 0xFF // Invalid state // NVLINK TX SUBLINK states diff --git a/src/common/nvlink/interface/nvlink_lib_ctrl.h b/src/common/nvlink/interface/nvlink_lib_ctrl.h index d77fbb04ca..245b7b227e 100644 --- a/src/common/nvlink/interface/nvlink_lib_ctrl.h +++ b/src/common/nvlink/interface/nvlink_lib_ctrl.h @@ -1,28 +1,30 @@ -/******************************************************************************* - Copyright (c) 2016-2023 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _NVLINK_LIB_CTRL_H_ #define _NVLINK_LIB_CTRL_H_ + #include "nvtypes.h" #include "nvlink_errors.h" @@ -67,6 +69,8 @@ #define NVLINK_VERSION_STRING_LENGTH 64 +#define NVLINK_CCI_TRAINING_TIMEOUT_SEC 30 + /* * NVLink version consists of, * major - no compatibility. @@ -155,6 +159,7 @@ typedef enum nvlink_link_mode_disable_pm, nvlink_link_mode_traffic_setup, nvlink_link_mode_contain, + nvlink_link_mode_training_cci } nvlink_link_mode; /* sublink tx modes */ diff --git a/src/common/nvlink/interface/nvlink_lock.h b/src/common/nvlink/interface/nvlink_lock.h index 0b1a2bd92e..df707ddaa3 100644 --- a/src/common/nvlink/interface/nvlink_lock.h +++ b/src/common/nvlink/interface/nvlink_lock.h @@ -1,21 +1,25 @@ -/******************************************************************************* - Copyright (c) 2020 NVidia Corporation - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _NVLINK_LOCK_H_ diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c b/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c index 53290ec59f..8fd41d877f 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_conn_mgmt.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2022 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c b/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c index 00c8d2fb5f..27d5cb3cb3 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_discovery.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c b/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c index b203a10855..0721cf935a 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_initialize.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2021 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c index 029bb638aa..a09ace3bbc 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_ioctl.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2017-2023 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvVer.h" @@ -297,6 +298,7 @@ nvlink_core_get_endpoint_state NvU64 state = NVLINK_LINKSTATE_INVALID; NvU64 dlState = NVLINK_LINKSTATE_INVALID; NvU64 tlState = NVLINK_LINKSTATE_INVALID; + NvU64 cciState = NVLINK_LINKSTATE_INVALID; if ((link == NULL) || (linkState == NULL)) { return; @@ -317,6 +319,13 @@ nvlink_core_get_endpoint_state linkState->linkMode = _nvlink_core_map_link_state(dlState, tlState); + // CCI link training in progress + link->link_handlers->get_cci_link_mode(link, &cciState); + if (cciState == NVLINK_LINKSTATE_TRAINING_CCI) + { + linkState->linkMode = nvlink_link_mode_training_cci; + } + status = link->link_handlers->get_tx_mode(link, &state, &txSubLinkSubstate); diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c index eba23115c3..47230aec8f 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_link_mgmt.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c b/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c index e854108b34..16f4050cb2 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_logger.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c index c4ff10bec8..519e994434 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2022 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" @@ -434,6 +435,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off if (conns[i] == NULL) continue; + if (conns[i]->end0->bCciManaged || + conns[i]->end1->bCciManaged) + { + continue; + } + // Disable Power Management before moving link out of Active conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_DISABLE_PM, @@ -463,6 +470,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off if (conns[i] == NULL) continue; + if (conns[i]->end0->bCciManaged || + conns[i]->end1->bCciManaged) + { + continue; + } + // Wait for the end0 to go to SWCFG status = nvlink_core_poll_link_state(conns[i]->end0, NVLINK_LINKSTATE_SAFE, @@ -521,6 +534,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_off if (conns[i] == NULL) continue; + if (conns[i]->end0->bCciManaged || + conns[i]->end1->bCciManaged) + { + continue; + } + // Wait for sublinks to go to SAFE if(conns[i]->end0->inSWCFG == NV_TRUE) { @@ -674,6 +693,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg if (conns[i] == NULL) continue; + if (conns[i]->end0->bCciManaged || + conns[i]->end1->bCciManaged) + { + continue; + } + // Disable Power Management before moving link out of Active conns[i]->end0->link_handlers->set_dl_link_mode(conns[i]->end0, NVLINK_LINKSTATE_DISABLE_PM, @@ -705,6 +730,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg if (conns[i] == NULL) continue; + if (conns[i]->end0->bCciManaged || + conns[i]->end1->bCciManaged) + { + continue; + } + // Wait for the end0 to go to SWCFG status = nvlink_core_poll_link_state(conns[i]->end0, NVLINK_LINKSTATE_SAFE, @@ -751,6 +782,12 @@ nvlink_core_powerdown_intranode_conns_from_active_to_swcfg if (conns[i] == NULL) continue; + if (conns[i]->end0->bCciManaged || + conns[i]->end1->bCciManaged) + { + continue; + } + status = nvlink_core_poll_sublink_state(conns[i]->end0, NVLINK_SUBLINK_STATE_TX_SAFE, NVLINK_SUBLINK_SUBSTATE_TX_STABLE, @@ -842,6 +879,12 @@ nvlink_core_reset_intranode_conns if (conns[i] == NULL) continue; + if (conns[i]->end0->bCciManaged || + conns[i]->end1->bCciManaged) + { + continue; + } + // // Reset both ends of this connection. // This path should enable/init those link endpoints as well. diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_training.c b/src/common/nvlink/kernel/nvlink/core/nvlink_training.c index 57e39617d0..db6addbeb4 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_training.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_training.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" @@ -50,6 +51,11 @@ nvlink_core_train_check_link_ready_ALI if (links[i] == NULL) continue; + if (links[i]->bCciManaged) + { + continue; + } + if (!nvlink_core_check_link_state(links[i], NVLINK_LINKSTATE_ALI)) { // If link is not in active, update status to be error and continue @@ -966,6 +972,11 @@ nvlink_core_train_intranode_conns_from_off_to_active_ALI if (pLinks[i] == NULL) continue; + if (pLinks[i]->bCciManaged) + { + continue; + } + status = pLinks[i]->link_handlers->ali_training(pLinks[i]); if (status != NVL_SUCCESS) { diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c index 14f176eedf..6b2aedf579 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_ioctl_entry.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2017-2023 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvVer.h" diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c index 4542e45e09..afbcb17173 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_discovery_entry.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c index f34f33a1d7..d9452cd389 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_initialize_entry.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c index 633c0a3123..a8887b9fe0 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_link_mgmt_entry.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c index db2b3efd46..29345c7961 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_registration_entry.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c index 5604870cf6..b6e838f127 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c index 7f2e328148..eaca8e60cf 100644 --- a/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c +++ b/src/common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/nvlink_ctx.h b/src/common/nvlink/kernel/nvlink/nvlink_ctx.h index 0c3ab607fc..39554daac3 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_ctx.h +++ b/src/common/nvlink/kernel/nvlink/nvlink_ctx.h @@ -1,25 +1,25 @@ -/******************************************************************************* - Copyright (c) 2014-2017 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ - +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _NVLINK_CTX_H_ #define _NVLINK_CTX_H_ diff --git a/src/common/nvlink/kernel/nvlink/nvlink_helper.h b/src/common/nvlink/kernel/nvlink/nvlink_helper.h index 77fb470911..a8a7f12737 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_helper.h +++ b/src/common/nvlink/kernel/nvlink/nvlink_helper.h @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2017-2020 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #ifndef _NVLINK_HELPER_H_ #define _NVLINK_HELPER_H_ diff --git a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c index 9925329316..eb150f1a12 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c +++ b/src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c @@ -1,24 +1,25 @@ -/******************************************************************************* - Copyright (c) 2019-2023 NVidia Corporation - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvlink_export.h" diff --git a/src/common/nvlink/kernel/nvlink/nvlink_lock.c b/src/common/nvlink/kernel/nvlink/nvlink_lock.c index ab902ba229..92a623fb4e 100644 --- a/src/common/nvlink/kernel/nvlink/nvlink_lock.c +++ b/src/common/nvlink/kernel/nvlink/nvlink_lock.c @@ -1,21 +1,25 @@ -/******************************************************************************* - Copyright (c) 2020 NVidia Corporation - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to - deal in the Software without restriction, including without limitation the - rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - sell copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - The above copyright notice and this permission notice shall be - included in all copies or substantial portions of the Software. - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - DEALINGS IN THE SOFTWARE. -*******************************************************************************/ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include "nvlink.h" #include "nvtypes.h" diff --git a/src/common/nvswitch/common/inc/rmsoecmdif.h b/src/common/nvswitch/common/inc/rmsoecmdif.h index 8ba53a73af..e7ada59d2c 100644 --- a/src/common/nvswitch/common/inc/rmsoecmdif.h +++ b/src/common/nvswitch/common/inc/rmsoecmdif.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -35,6 +35,8 @@ * message structures, RM_SOE_COMMAND and RM_SOE_MESSAGE (respectively). */ + + #include "flcnifcmn.h" #include "soe/soebif.h" @@ -47,6 +49,8 @@ #include "soe/soeifsmbpbi.h" #include "soe/soeifcore.h" #include "soe/soeifchnmgmt.h" +#include "soe/soeifcci.h" +#include "soe/soeifheartbeat.h" /*! * Defines the structure that must be populated to send any arbitrary command @@ -67,6 +71,7 @@ typedef struct RM_SOE_BIF_CMD bif; RM_SOE_CORE_CMD core; RM_SOE_CHNMGMT_CMD chnmgmt; + RM_SOE_CCI_CMD cci; } cmd; } RM_FLCN_CMD_SOE, *PRM_FLCN_CMD_SOE; @@ -90,6 +95,8 @@ typedef struct RM_FLCN_MSG_SOE_INIT init; RM_SOE_CHNMGMT_MSG chnmgmt; RM_SOE_CORE_MSG core; + RM_SOE_CCI_MSG cci; + RM_SOE_HEARTBEAT_MSG heartbeat; } msg; } RM_FLCN_MSG_SOE, *PRM_FLCN_MSG_SOE; @@ -116,8 +123,11 @@ typedef struct #define RM_SOE_TASK_ID_IFR 0x0A #define RM_SOE_TASK_ID_CHNMGMT 0x0B #define RM_SOE_TASK_ID_RMMSG 0x0C +#define RM_SOE_TASK_ID_CCI 0x0D +#define RM_SOE_TASK_ID_FSPMGMT 0x0E +#define RM_SOE_TASK_ID_HEARTBEAT 0x0F // Add new task ID here... -#define RM_SOE_TASK_ID__END 0x0D +#define RM_SOE_TASK_ID__END 0x10 /*! * Unit-identifiers: @@ -139,8 +149,10 @@ typedef struct #define RM_SOE_UNIT_CORE (0x0B) #define RM_SOE_UNIT_IFR (0x0C) #define RM_SOE_UNIT_CHNMGMT (0x0D) +#define RM_SOE_UNIT_CCI (0x0E) +#define RM_SOE_UNIT_HEARTBEAT (0x0F) // Add new unit ID here... -#define RM_SOE_UNIT_END (0x0E) +#define RM_SOE_UNIT_END (0x10) #endif // _RMSOECMDIF_H_ diff --git a/src/common/nvswitch/common/inc/soe/cci/cci_cmis.h b/src/common/nvswitch/common/inc/soe/cci/cci_cmis.h new file mode 100644 index 0000000000..eb644a8c3b --- /dev/null +++ b/src/common/nvswitch/common/inc/soe/cci/cci_cmis.h @@ -0,0 +1,142 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CCI_CMIS_H_ +#define _CCI_CMIS_H_ + +// Based on CMIS 4.0/5.0 specification + +// Page 0h +#define CMIS_REV_BYTE 1 +#define CMIS_REV_BYTE_WHOLE 7:4 +#define CMIS_REV_BYTE_DECIMAL 3:0 +#define CMIS_CHARACTERISTICS_BYTE 2 +#define CMIS_CHARACTERISTICS_BYTE_FLAT_MEM 7:7 +#define CMIS_MODULE_FLAGS_CUSTOM_BYTE 13 +#define CMIS_OSFP_TEMPERATURE_BYTE 14 +#define CMIS_CDB_BLOCK_STATUS_BYTE(block) ((block) + 37) +#define CMIS_CDB_BLOCK_STATUS_BYTE_BUSY 7:7 +#define CMIS_CDB_BLOCK_STATUS_BYTE_BUSY_FALSE 0 +#define CMIS_CDB_BLOCK_STATUS_BYTE_BUSY_TRUE 1 +#define CMIS_ACTIVE_FW_MAJOR_REVISION 39 +#define CMIS_ACTIVE_FW_MINOR_REVISION 40 +#define CMIS_BANK_PAGE 126 +#define CMIS_MIT_BYTE 212 +#define CMIS_CHECKSUM_BYTE 222 +#define CMIS_CHECKSUM_LENGTH 94 + +// Media Interface Technology Table +#define CMIS_MIT_BYTE_COPPER 0xA +#define CMIS_MIT_BYTE_COPPER_UNEQUALIZED 0xA +#define CMIS_MIT_BYTE_COPPER_PASSIVE_EQUALIZED 0xB +#define CMIS_MIT_BYTE_COPPER_NEAR_FAR_END_LIMITING_ACTIVE_EQUALIZED 0xC +#define CMIS_MIT_BYTE_COPPER_FAR_END_LIMITING_ACTIVE_EQUALIZED 0xD +#define CMIS_MIT_BYTE_COPPER_NEAR_END_LIMITING_ACTIVE_EQUALIZED 0xE +#define CMIS_MIT_BYTE_COPPER_LINEAR_ACTIVE_EQUALIZED 0xF +#define CMIS_MIT_BYTE_RESERVED 0x10 + +// Page 01h +#define CMIS_SI_CONTROLS 161 +#define CMIS_SI_CONTROLS_CDR_IMPLEMENTED 0:0 +#define CMIS_DATA_PATH_MAX_DURATION_BYTE 144 +#define CMIS_DATA_PATH_MAX_DURATION_BYTE_DEINIT 7:4 +#define CMIS_DATA_PATH_MAX_DURATION_BYTE_INIT 3:0 +#define CMIS_MODULE_POWER_MAX_DURATION_BYTE 167 +#define CMIS_MODULE_POWER_MAX_DURATION_BYTE_DOWN 7:4 +#define CMIS_MODULE_POWER_MAX_DURATION_BYTE_UP 3:0 +#define CMIS_DATA_PATH_TX_MAX_DURATION_BYTE 168 +#define CMIS_DATA_PATH_TX_MAX_DURATION_BYTE_OFF 7:4 +#define CMIS_DATA_PATH_TX_MAX_DURATION_BYTE_ON 3:0 + +// Page 02h +#define CMIS_OSFP_OVERT_LIMIT_BYTE 128 +#define CMIS_OSFP_WARN_LIMIT_BYTE 132 + + +// +// CMIS 4.0: Table 8-29 State Duration Encoding +// Stores time in ms +// Times > 60s will be considered errors +// +static const NvU64 dur_en_map[] = {1, 5, 10, 50, + 100, 500, 1000, 5*1000, + 10*1000, 60*1000, 0, 0, + 0, 0, 0, 0}; +#define CMIS_MAX_DURATION_EN_TO_MS_MAP(en) (dur_en_map[en]) + +// Page 10h +#define CMIS_DATA_PATH_CONTROL_BYTE 128 +#define CMIS_STAGE_CONTROL_SET_0 143 +#define CMIS_STAGE_CONTROL_SET_0_SIZE 35 +#define CMIS_STAGE_CONTROL_SET_0_APP_SEL 145 + +// Page 11h +#define CMIS_DATA_PATH_STATE 128 +// Used to determine which byte(128-131) encodes given lane's datapath state +#define CMIS_DATA_PATH_STATE_LANE_BYTE_MAP(lane) (lane/2) +#define CMIS_DATA_PATH_STATE_SIZE 4 +#define CMIS_DATA_PATH_STATE_BYTE_LANE_0 3:0 +#define CMIS_DATA_PATH_STATE_BYTE_LANE_1 7:4 +#define CMIS_DATA_PATH_CONFIG_ERROR_CODES 202 +#define CMIS_ACTIVE_CONTROL_SET 206 +#define CMIS_ACTIVE_CONTROL_SET_SIZE 29 + +// Datapath states +#define CMIS_DATA_PATH_STATE_LANE_DEACTIVATED 0x1 +#define CMIS_DATA_PATH_CONFIG_ALL_LANES_ACCEPTED 0x11111111 + +// CDB command payload size +#define CMIS_CDB_LPL_MAX_SIZE 120 + +// +// CMIS 4.0: Table 9-16 CDB Command 0100h: Get firmware Info +// Index of information in LPL +// +#define CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS 0 +#define CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS_IMAGE_A_RUNNING 0:0 +#define CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS_IMAGE_A_COMMITTED 1:1 +#define CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS_IMAGE_A_EMPTY 2:2 +#define CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS_IMAGE_B_RUNNING 4:4 +#define CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS_IMAGE_B_COMMITTED 5:5 +#define CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS_IMAGE_B_EMPTY 6:6 +#define CMIS_CDB_GET_FW_INFO_LPL_INFO_BLOCK 1 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_A_MAJOR_BYTE 2 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_A_MINOR_BYTE 3 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_A_BUILD 4 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_A_BUILD_SIZE 2 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_A_EXTRA_STRING 6 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_A_EXTRA_STRING_SIZE 32 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_B_MAJOR_BYTE 38 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_B_MINOR_BYTE 39 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_B_BUILD 40 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_B_BUILD_SIZE 2 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_B_EXTRA_STRING 42 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_B_EXTRA_STRING_SIZE 32 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_FACTORY_BOOT_MAJOR_BYTE 74 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_FACTORY_BOOT_MINOR_BYTE 75 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_FACTORY_BOOT_BUILD 76 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_FACTORY_BOOT_BUILD_SIZE 2 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_FACTORY_BOOT_EXTRA_STRING 78 +#define CMIS_CDB_GET_FW_INFO_LPL_IMAGE_FACTORY_BOOT_EXTRA_STRING_SIZE 32 + +#endif //_CCI_CMIS_H_ diff --git a/src/common/nvswitch/common/inc/soe/cci/cci_onboard_phases.h b/src/common/nvswitch/common/inc/soe/cci/cci_onboard_phases.h new file mode 100644 index 0000000000..6651571c4b --- /dev/null +++ b/src/common/nvswitch/common/inc/soe/cci/cci_onboard_phases.h @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CCI_ONBOARD_PHASES_H_ +#define _CCI_ONBOARD_PHASES_H_ + +// Defines common onboarding phases +typedef enum cci_module_onboard_phase +{ + CCI_ONBOARD_PHASE_CHECK_CONDITION = 0x0, + CCI_ONBOARD_PHASE_IDENTIFY = 0x1, + CCI_ONBOARD_PHASE_INIT_COPPER = 0x2, + CCI_ONBOARD_PHASE_INIT_DIRECT = 0x3, + CCI_ONBOARD_PHASE_INIT_OPTICAL = 0x4, + CCI_ONBOARD_PHASE_LAUNCH_ALI = 0x5, + CCI_ONBOARD_PHASE_SLEEP = 0x6, + CCI_ONBOARD_PHASE_MONITOR = 0x7, + CCI_ONBOARD_PHASE_NON_CONTINUOUS_ALI = 0x8 +} CCI_MODULE_ONBOARD_PHASE; + +// Defines onboarding phases that are specific to optical modules +typedef enum cci_module_onboard_subphase_optical +{ + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_START = 0x0, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_CMIS_SELECT_APPLICATION = 0x1, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_CONFIGURE_LINKS = 0x2, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_DISABLE_ALI = 0x3, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_SETUP = 0x4, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_SEND_CDB = 0x5, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_POLL = 0x6, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_GO_TRANSPARENT = 0x7, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_RESET_LINKS = 0x8, + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_ENABLE_ALI = 0x9, +} CCI_MODULE_ONBOARD_SUBPHASE_OPTICAL; + +#endif //_CCI_ONBOARD_PHASES_H_ diff --git a/src/common/nvswitch/common/inc/soe/cci/cpld_machx03.h b/src/common/nvswitch/common/inc/soe/cci/cpld_machx03.h new file mode 100644 index 0000000000..49891adfed --- /dev/null +++ b/src/common/nvswitch/common/inc/soe/cci/cpld_machx03.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CPLD_MACHX03_H_ +#define _CPLD_MACHX03_H_ + +// Register definitions +#define CPLD_MACHXO3_VERSION_MAJOR 0x0 +#define CPLD_MACHXO3_VERSION_MINOR 0x1 +#define CPLD_MACHXO3_PART_NUMBER_MSB 0x2 +#define CPLD_MACHXO3_PART_NUMBER_LSB 0x3 +#define CPLD_MACHXO3_PORTS_RESET_REG1 0x4 +#define CPLD_MACHXO3_PORTS_RESET_REG2 0x5 +#define CPLD_MACHXO3_PORTS_INT_REG1 0x6 +#define CPLD_MACHXO3_PORTS_INT_REG2 0x7 +#define CPLD_MACHXO3_PORTS_PRSNT_REG1 0x8 +#define CPLD_MACHXO3_PORTS_PRSNT_REG2 0x9 +#define CPLD_MACHXO3_PORTS_LPMODE_REG1 0xA +#define CPLD_MACHXO3_PORTS_LPMODE_REG2 0xB +#define CPLD_MACHXO3_LD_SW_EN_REG1 0xC +#define CPLD_MACHXO3_LD_SW_EN_REG2 0xD +#define CPLD_MACHXO3_LD_SW_PG_REG1 0xE +#define CPLD_MACHXO3_LD_SW_PG_REG2 0xF +#define CPLD_MACHXO3_LIN_EQ_EN_REG1 0x10 +#define CPLD_MACHXO3_LIN_EQ_EN_REG2 0x11 +#define CPLD_MACHXO3_LED_STATE_REG(cageNum) (0x12 + cageNum) +#define CPLD_MACHXO3_LED_STATE_REG_LED_A 3:0 +#define CPLD_MACHXO3_LED_STATE_REG_LED_B 7:4 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_OFF 0x0 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_AMBER 0x1 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_GREEN 0x2 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_3HZ_AMBER 0x3 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_3HZ_GREEN 0x4 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_6HZ_AMBER 0x5 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_6HZ_GREEN 0x6 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_3HZ_AMBER_GREEN 0x7 +#define CPLD_MACHXO3_LED_STATE_REG_LED_STATE_6HZ_AMBER_GREEN 0x8 +#define CPLD_MACHXO3_PORTS_UNPLUG_REG1 0x23 +#define CPLD_MACHXO3_PORTS_UNPLUG_REG2 0x24 +#define CPLD_MACHXO3_CPLD_CTL_REG1 0x25 +#define CPLD_MACHXO3_CPLD_CTL_REG1_I2CC_MUX_RESET 2:2 +#define CPLD_MACHXO3_CPLD_CTL_REG1_I2CB_MUX_RESET 1:1 +#define CPLD_MACHXO3_CPLD_CTL_REG1_WATCHDOG_ENABLE 0:0 +#define CPLD_MACHXO3_CPLD_STATUS_REG 0x26 +#define CPLD_MACHXO3_LD_SW_FAULT_REG1 0x29 +#define CPLD_MACHXO3_LD_SW_FAULT_REG2 0x2A +#define CPLD_MACHXO3_PORTS_PRSNT_STATE_CHANGE_REG1 0x2B +#define CPLD_MACHXO3_PORTS_PRSNT_STATE_CHANGE_REG2 0x2C +#define CPLD_MACHXO3_CPLD_ID 0x2D +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL 0x31 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED 3:0 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_OFF 0x0 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_AMBER 0x1 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_GREEN 0x2 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_3HZ_AMBER 0x3 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_3HZ_GREEN 0x4 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_6HZ_AMBER 0x5 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_6HZ_GREEN 0x6 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_3HZ_AMBER_GREEN 0x7 +#define CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_6HZ_AMBER_GREEN 0x8 + + +#endif //_CPLD_MACHX03_H_ diff --git a/src/common/nvswitch/common/inc/soe/soeifcci.h b/src/common/nvswitch/common/inc/soe/soeifcci.h new file mode 100644 index 0000000000..4dc6837f12 --- /dev/null +++ b/src/common/nvswitch/common/inc/soe/soeifcci.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SOEIFCCI_H_ +#define _SOEIFCCI_H_ + +#include "nvfixedtypes.h" + +/*! + * @file soeifcci.h + * @brief SOE CCI Command Queue + * + * The CCI unit ID will be used for sending and recieving + * Command Messages between driver and CCI unt of SOE + */ + +/*! + * @brief CCI Message IDs + */ +enum +{ + RM_SOE_CCI_MSG_ID_ALI_OPTIMIZE_LINK_INFO, +}; + +/*! + * @brief Message for ALI link info + */ +typedef struct +{ + NvU8 msgType; + + // Global link id of the link to be optimized + NvU8 linkId; +} RM_SOE_CCI_MSG_ALI_OPTIMIZE_LINK_INFO; + +/*! + * @brief A simple union of all CCI messages. + * Use msgType to determine the actual type of the message. + */ +typedef union +{ + NvU8 msgType; + + // The following struct is expected to include msgType as its first member + RM_SOE_CCI_MSG_ALI_OPTIMIZE_LINK_INFO linkInfo; +} RM_SOE_CCI_MSG; + +/*! + * @brief CCI Command types + */ +enum +{ + RM_SOE_CCI_CMD_ID_SEND_MSG_TO_DRIVER, +}; + +/*! + * @brief Send aysncronous message about CCI events. + */ +typedef struct +{ + NvU8 cmdType; + union + { + NvU8 msgType; + RM_SOE_CCI_MSG_ALI_OPTIMIZE_LINK_INFO linkInfo; + } data; +} RM_SOE_CCI_CMD_SEND_MSG_TO_DRIVER; + +/*! + * @brief A simple union of all CCI commands. + * Use cmdType to determine the actual type of the command. + */ +typedef union +{ + NvU8 cmdType; + + // The following struct is expected to include cmdType as its first member + RM_SOE_CCI_CMD_SEND_MSG_TO_DRIVER msg; +} RM_SOE_CCI_CMD; + +#endif // _SOEIFCCI_H_ diff --git a/src/common/nvswitch/common/inc/soe/soeifcore.h b/src/common/nvswitch/common/inc/soe/soeifcore.h index 976dc2163e..1e1056cd48 100644 --- a/src/common/nvswitch/common/inc/soe/soeifcore.h +++ b/src/common/nvswitch/common/inc/soe/soeifcore.h @@ -24,6 +24,8 @@ #ifndef _SOECORE_H_ #define _SOECORE_H_ + + #define SOE_CORE_BIOS_SIZE_LS10 0x100000 // 1 MB /*! @@ -42,62 +44,87 @@ enum /*! * Read the BIOS Size */ - RM_SOE_CORE_CMD_READ_BIOS_SIZE, + RM_SOE_CORE_CMD_READ_BIOS_SIZE = 0x0, /*! * Read the BIOS */ - RM_SOE_CORE_CMD_READ_BIOS, + RM_SOE_CORE_CMD_READ_BIOS = 0x1, /*! * Run DMA self-test */ - RM_SOE_CORE_CMD_DMA_SELFTEST, + RM_SOE_CORE_CMD_DMA_SELFTEST = 0x2, /*! * Perform I2C transaction */ - RM_SOE_CORE_CMD_I2C_ACCESS, + RM_SOE_CORE_CMD_I2C_ACCESS = 0x3, /*! * Issue NPORT Reset */ - RM_SOE_CORE_CMD_ISSUE_NPORT_RESET, + RM_SOE_CORE_CMD_ISSUE_NPORT_RESET = 0x4, /*! * Restore NPORT state */ - RM_SOE_CORE_CMD_RESTORE_NPORT_STATE, + RM_SOE_CORE_CMD_RESTORE_NPORT_STATE = 0x5, /*! * Set NPORT TPROD state */ - RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE, + RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE = 0x6, /*! * Read VRs */ - RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES, + RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES = 0x7, /*! * Init PLM2 protected registers */ - RM_SOE_CORE_CMD_INIT_L2_STATE, + RM_SOE_CORE_CMD_INIT_L2_STATE = 0x8, /*! * Read Power */ - RM_SOE_CORE_CMD_GET_POWER_VALUES, + RM_SOE_CORE_CMD_GET_POWER_VALUES = 0x9, /*! * Set NPORT interrupts */ - RM_SOE_CORE_CMD_SET_NPORT_INTRS, + RM_SOE_CORE_CMD_SET_NPORT_INTRS = 0xA, + + /*! + * Set Module LP mode + */ + RM_SOE_CORE_CMD_SET_MODULE_LP_MODE = 0xB, + + /*! + * Read from Ports CPLD + */ + RM_SOE_CORE_CMD_READ_PORTS_CPLD = 0xC, + + /*! + * Write to Ports CPLD + */ + RM_SOE_CORE_CMD_WRITE_PORTS_CPLD = 0xD, + + /*! + * Perform a module onboard phase on behalf of the driver + */ + RM_SOE_CORE_CMD_PERFORM_MODULE_ONBOARD_PHASE = 0xE, /*! * Disable NPORT fatal interrupt */ - RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR, + RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR = 0xF, + + /* + * Issue Ingress stop + */ + RM_SOE_CORE_CMD_ISSUE_INGRESS_STOP = 0x10, }; // Timeout for SOE reset callback function @@ -181,6 +208,41 @@ typedef struct NvBool bEnable; } RM_SOE_CORE_CMD_NPORT_INTRS; +typedef struct +{ + NvU8 cmdType; + NvU8 moduleId; + NvBool bAssert; +} RM_SOE_CORE_CMD_SET_LP_MODE; + +typedef struct +{ + NvU8 cmdType; + NvU8 reg; +} RM_SOE_CORE_CMD_READ_CPLD; + +typedef struct +{ + NvU8 cmdType; + NvU8 reg; + NvU8 dataIn; +} RM_SOE_CORE_CMD_WRITE_CPLD; + +typedef struct +{ + NvU8 cmdType; + NvU8 moduleId; + NvU8 onboardPhase; + NvU8 onboardSubPhase; + struct { + NvBool rxDetEnable; + NvU8 reserved0; + NvU8 reserved1; + NvU8 reserved2; + } attributes; + RM_FLCN_U64 linkMask; +} RM_SOE_CORE_CMD_PERFORM_ONBOARD_PHASE; + typedef struct { NvU8 cmdType; @@ -217,6 +279,10 @@ typedef union RM_SOE_CORE_CMD_L2_STATE l2State; RM_SOE_CORE_CMD_GET_POWER getPower; RM_SOE_CORE_CMD_NPORT_INTRS nportIntrs; + RM_SOE_CORE_CMD_SET_LP_MODE setLpMode; + RM_SOE_CORE_CMD_READ_CPLD readCpld; + RM_SOE_CORE_CMD_WRITE_CPLD writeCpld; + RM_SOE_CORE_CMD_PERFORM_ONBOARD_PHASE performOnboardPhase; RM_SOE_CORE_CMD_NPORT_FATAL_INTR nportDisableIntr; } RM_SOE_CORE_CMD; @@ -238,10 +304,39 @@ typedef struct NvU32 hvdd_w; } RM_SOE_CORE_MSG_GET_POWER; +typedef struct +{ + NvU8 msgType; + NvU8 flcnStatus; +} RM_SOE_CORE_MSG_SET_LP_MODE; + +typedef struct +{ + NvU8 msgType; + NvU8 flcnStatus; + NvU8 dataOut; +} RM_SOE_CORE_MSG_READ_CPLD; + +typedef struct +{ + NvU8 msgType; + NvU8 flcnStatus; +} RM_SOE_CORE_MSG_WRITE_CPLD; + +typedef struct +{ + NvU8 msgType; + NvU8 flcnStatus; +} RM_SOE_CORE_MSG_PERFORM_ONBOARD_PHASE; + typedef union { NvU8 msgType; RM_SOE_CORE_MSG_GET_VOLTAGE getVoltage; RM_SOE_CORE_MSG_GET_POWER getPower; + RM_SOE_CORE_MSG_SET_LP_MODE setLpMode; + RM_SOE_CORE_MSG_READ_CPLD readCpld; + RM_SOE_CORE_MSG_WRITE_CPLD writeCpld; + RM_SOE_CORE_MSG_PERFORM_ONBOARD_PHASE performOnboardPhase; } RM_SOE_CORE_MSG; #endif // _SOECORE_H_ diff --git a/src/common/nvswitch/common/inc/soe/soeifheartbeat.h b/src/common/nvswitch/common/inc/soe/soeifheartbeat.h new file mode 100644 index 0000000000..109dc186a6 --- /dev/null +++ b/src/common/nvswitch/common/inc/soe/soeifheartbeat.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _SOEIFHEARTBEAT_H_ +#define _SOEIFHEARTBEAT_H_ + +#include "nvfixedtypes.h" + +/*! + * @file soeifheartbeat.h + * @brief SOE Heartbeat Command Queue + */ + +/* ------------------------ Defines ---------------------------------*/ + +typedef struct +{ + NvU8 msgType; +} RM_SOE_HEARTBEAT_MSG_OSFP_THERM; + +typedef union +{ + NvU8 msgType; + RM_SOE_HEARTBEAT_MSG_OSFP_THERM msg; +} RM_SOE_HEARTBEAT_MSG; + +// OSFP Thermal Message IDs +enum +{ + RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_WARN_ACTIVATED, + RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_WARN_DEACTIVATED, + RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_OVERT_ACTIVATED, + RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_OVERT_DEACTIVATED, + RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_HEARTBEAT_SHUTDOWN, +}; + +#endif // _SOEIFHEARTBEAT_H_ + diff --git a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h index fd9a6aa1b0..b8a409a81b 100644 --- a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h +++ b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h @@ -830,6 +830,7 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN = 10006, NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007, NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008, + NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE = 10009, NVSWITCH_ERR_HW_HOST_LAST, @@ -1262,24 +1263,44 @@ typedef enum nvswitch_err_type NVSWITCH_ERR_HW_SOE_WATCHDOG = 26008, NVSWITCH_ERR_HW_SOE_LAST, /* Note: Must be last */ + /* CCI errors */ + NVSWITCH_ERR_HW_CCI = 27000, + NVSWITCH_ERR_HW_CCI_RESET = 27001, + NVSWITCH_ERR_HW_CCI_INIT = 27002, + NVSWITCH_ERR_HW_CCI_TIMEOUT = 27003, + NVSWITCH_ERR_HW_CCI_SHUTDOWN = 27004, + NVSWITCH_ERR_HW_CCI_MODULE = 27005, + NVSWITCH_ERR_HW_CCI_MODULE_BOOT = 27006, + NVSWITCH_ERR_HW_CCI_MODULE_RECOVERY = 27007, + NVSWITCH_ERR_HW_CCI_LAST, /* Note: Must be last */ + + /* OSFP Therm Errors */ + NVSWITCH_ERR_HW_OSFP_THERM = 28000, + NVSWITCH_ERR_HW_OSFP_THERM_WARN_ACTIVATED = 28001, + NVSWITCH_ERR_HW_OSFP_THERM_WARN_DEACTIVATED = 28002, + NVSWITCH_ERR_HW_OSFP_THERM_OVERT_ACTIVATED = 28003, + NVSWITCH_ERR_HW_OSFP_THERM_OVERT_DEACTIVATED = 28004, + NVSWITCH_ERR_HW_OSFP_THERM_HEARTBEAT_SHUTDOWN = 28005, + NVSWITCH_ERR_HW_OSFP_THERM_LAST, /* Note: Must be last */ + /* NPORT: Multicast Tstate errors */ - NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE = 28000, - NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR = 28001, - NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_DBE_ERR = 28002, - NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 28003, - NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_DBE_ERR = 28004, - NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 28005, - NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_MCTO_ERR = 28006, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE = 29000, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_LIMIT_ERR = 29001, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_TAGPOOL_ECC_DBE_ERR = 29002, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 29003, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_ECC_DBE_ERR = 29004, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 29005, + NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_CRUMBSTORE_MCTO_ERR = 29006, NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_LAST, /* Note: Must be last */ /* NPORT: Reduction Tstate errors */ - NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE = 29000, - NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR = 29001, - NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_DBE_ERR = 29002, - NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 29003, - NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_DBE_ERR = 29004, - NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 29005, - NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_RTO_ERR = 29006, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE = 30000, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_LIMIT_ERR = 30001, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_TAGPOOL_ECC_DBE_ERR = 30002, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_LIMIT_ERR = 30003, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_ECC_DBE_ERR = 30004, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_BUF_OVERWRITE_ERR = 30005, + NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_CRUMBSTORE_RTO_ERR = 30006, NVSWITCH_ERR_HW_NPORT_REDUCTIONTSTATE_LAST, /* Note: Must be last */ /* Please update nvswitch_translate_hw_errors with a newly added error class. */ @@ -2755,6 +2776,242 @@ typedef struct nvswitch_get_nvlink_ecc_errors NVSWITCH_LINK_ECC_ERROR errorLink[NVSWITCH_NVLINK_MAX_LINKS]; } NVSWITCH_GET_NVLINK_ECC_ERRORS_PARAMS; +/* + * CTRL_NVSWITCH_CCI_CMIS_PRESENCE + * + * Control to get module presence bitmasks + * + * Parameters: + * cagesMask [OUT] + * Bitmask representing the CMIS module cages present + * (associated with) the selected ASIC device + * modulesMask [OUT] + * Bitmask representing the CMIS modules currently present + * (plugged in) on the selected ASIC device + */ + +typedef struct nvswitch_cci_cmis_presence_params +{ + NvU32 cagesMask; + NvU32 modulesMask; + NvU32 reserved0; + NvU32 reserved1; + NvU32 reserved2; + NvU32 reserved3; +} NVSWITCH_CCI_CMIS_PRESENCE_PARAMS; + +#define NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE(i) (7 + (i<<3)):(i<<3) +#define NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE_LINK_ID 5:0 +#define NVSWITCH_CCI_CMIS_NVLINK_MAPPING_GET_OSFP_LANE_MASK(laneMask, linkId, eVal) \ + do { \ + NvU8 _byte, _lane; \ + \ + laneMask = 0; \ + for (_lane = 0; _lane < 8; _lane++) \ + { \ + _byte = REF_VAL64(NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE(_lane), eVal); \ + if (REF_VAL64(NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE_LINK_ID, _byte) == linkId) \ + { \ + laneMask |= NVBIT(_lane); \ + } \ + } \ + } while (0); + +/* + * CTRL_NVSWITCH_CCI_CMIS_NVLINK_MAPPING + * + * Control to get cage to NVLink link mappings + * + * Provided macros should be used to extract fields from + * encoded value. + * + * Parameters: + * cageIndex [IN] + * Target cage index (>=0 and <= 31) on the + * selected ASIC device. + * linkMask [OUT] + * Mask of Nvlinks mapped to the given cage + * encodedValue [OUT] + * Value that encodes the following: + * -Link Ids to OSFP lane number + */ + +typedef struct nvswitch_cci_cmis_nvlink_mapping_params +{ + NvU8 cageIndex; + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NV_DECLARE_ALIGNED(NvU64 encodedValue, 8); + NvU32 reserved0; + NvU32 reserved1; + NvU32 reserved2; + NvU32 reserved3; +} NVSWITCH_CCI_CMIS_NVLINK_MAPPING_PARAMS; + +#define NVSWITCH_CCI_CMIS_MEMORY_ACCESS_BUF_SIZE (128) + +/* + * CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ + * + * Control for direct memory accesses to cages + * + * Parameters: + * cageIndex [IN] + * Target cage index (>=0 and <= 31) on the + * selected ASIC device + * bank [IN] + * Target bank in module (if address >= 0x80) + * page [IN] + * Target page in module (if address >= 0x80) + * address [IN] + * Target byte address (offset) in module + * count [IN] + * Number of bytes to read (>=0 and <= 0x7F) + * bSequenceLock [IN] + * Allows clients to own the module for + * CMIS read/write sequences. This must + * be set to TRUE for all accesses within + * the sequence. Setting it to FALSE will + * release the lock. The lock will expire + * and be released if the module is left idle + * for greater than 10 seconds. + * data[] [OUT] + * 128 byte data buffer + */ + +typedef struct nvswitch_cci_cmis_memory_access_read_params +{ + NvU8 cageIndex; + NvU8 bank; + NvU8 page; + NvU8 address; + NvU8 count; + NvU8 data[NVSWITCH_CCI_CMIS_MEMORY_ACCESS_BUF_SIZE]; + NvBool bSequenceLock; + NvU8 reserved0[3]; + NvU32 reserved1; + NvU32 reserved2; + NvU32 reserved3; +} NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ_PARAMS; + +/* + * CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE + * + * Control for direct memory accesses to cages + * + * Parameters: + * cageIndex [IN] + * Target cage index (>=0 and <= 31) on the + * selected ASIC device + * bank [IN] + * Target bank in module (if address >= 0x80) + * page [IN] + * Target page in module (if address >= 0x80) + * address [IN] + * Target byte address (offset) in module + * count [IN] + * Number of bytes to write (>=0 and <= 0x7F) + * bSequenceLock [IN] + * Allows clients to own the module for + * CMIS read/write sequences. This must + * be set to TRUE for all accesses within + * the sequence. Setting it to FALSE will + * release the lock. The lock will expire + * and be released if the module is left idle + * for greater than 10 seconds. + * data[] [IN] + * 128 byte data buffer + */ + +typedef struct nvswitch_cci_cmis_memory_access_write_params +{ + NvU8 cageIndex; + NvU8 bank; + NvU8 page; + NvU8 address; + NvU8 count; + NvU8 data[NVSWITCH_CCI_CMIS_MEMORY_ACCESS_BUF_SIZE]; + NvBool bSequenceLock; + NvU8 reserved0[3]; + NvU32 reserved1; + NvU32 reserved2; + NvU32 reserved3; +} NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE_PARAMS; + +#define NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING_LEN 31 + +/* + * CTRL_NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING + * + * Control to get bezel information for a cage. + * + * Parameters: + * cageIndex [IN] + * Target cage index (>=0 and <= 31) on the + * selected ASIC device. + * bezelMarking [OUT] + * + */ + +typedef struct nvswitch_cci_cmis_cage_bezel_marking_params +{ + NvU8 cageIndex; + char bezelMarking[NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING_LEN + 1]; + NvU32 reserved0; + NvU32 reserved1; + NvU32 reserved2; + NvU32 reserved3; +} NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING_PARAMS; + +#define NVSWITCH_CCI_XVCR_LANES 0x8 + +/* + * + * Structure to store cci grading values + * + * + * This API is not supported on SV10. + * + * Parameters: + * tx_init + * TX-Input Initial Tuning grading. + * rx_init + * RX-Input Initial Tuning grading. + * tx_maint + * TX-Input Maintenance grading. + * rx_maint + * RX-Input Maintenance grading. + */ +typedef struct nvswitch_cci_grading_values +{ + NvU8 tx_init[NVSWITCH_CCI_XVCR_LANES]; + NvU8 rx_init[NVSWITCH_CCI_XVCR_LANES]; + NvU8 tx_maint[NVSWITCH_CCI_XVCR_LANES]; + NvU8 rx_maint[NVSWITCH_CCI_XVCR_LANES]; +} NVSWITCH_CCI_GRADING_VALUES; + +/* + * CTRL_NVSWITCH_CCI_GET_GRADING_VALUES + * + * Control to get cci xvcr grading values + * + * + * This API is not supported on SV10. + * + * Parameters: + * link [IN] + * Link number + * laneMask [OUT] + * Lane mask of valid indexes in the grading data + * grading [OUT] + * xvcr grading values + */ +typedef struct nvswitch_cci_get_grading_values_params +{ + NvU32 linkId; + NvU8 laneMask; + NVSWITCH_CCI_GRADING_VALUES grading; +} NVSWITCH_CCI_GET_GRADING_VALUES_PARAMS; + #define NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_DAYS 5 #define NVSWITCH_NVLINK_MAX_CORRECTABLE_ERROR_MONTHS 3 @@ -3466,7 +3723,7 @@ typedef struct NVSWITCH_NVLINK_ERR_INFO linkErrInfo[NVSWITCH_NVLINK_MAX_LINKS]; } NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS; -#define NVSWITCH_INBAND_DATA_SIZE 4096 +#define NVSWITCH_INBAND_DATA_SIZE 5120 /* * CTRL_NVSWITCH_INBAND_SEND_DATA @@ -3640,6 +3897,10 @@ typedef enum { NVSWITCH_I2C_DEVICE_UNKNOWN = 0, + // OSFP Devices + NVSWITCH_I2C_DEVICE_CMIS4_MODULE = 0xB0, + NVSWITCH_I2C_DEVICE_CMIS4_MUX_PCA9847 = 0xB1, + NVSWITCH_I2C_DEVICE_SKIP = 0xFF } NVSWITCH_I2C_DEVICE_TYPE; @@ -3801,6 +4062,11 @@ typedef enum NVSWITCH_I2C_ACQUIRER_UNKNOWN, NVSWITCH_I2C_ACQUIRER_IOCTL, // e.g. MODS NVSWITCH_I2C_ACQUIRER_EXTERNAL, // e.g. Linux Direct + NVSWITCH_I2C_ACQUIRER_CCI_INITIALIZE, // CCI Init/Startup + NVSWITCH_I2C_ACQUIRER_CCI_TRAIN, // Cable training + NVSWITCH_I2C_ACQUIRER_CCI_UX, // User interface e.g. LEDs + NVSWITCH_I2C_ACQUIRER_CCI_SERVICE, // e.g. ISR + NVSWITCH_I2C_ACQUIRER_CCI_SMBPBI, // OOB path } NVSWITCH_I2C_ACQUIRER; @@ -3881,6 +4147,162 @@ typedef struct nvswitch_minion_ali_debug_registers NvU32 dlstatLinkIntr; } NVSWITCH_MINION_ALI_DEBUG_REGISTERS; +/* + * CTRL_NVSWITCH_CCI_GET_PORTS_CPLD_INFO + * + * Retrieve information about the Ports CPLD + * + * Parameters: + * + * versionMajor[OUT] + * Major number of CPLD version + * versionMinor[OUT] + * Minor number of CPLD version + */ +typedef struct nvswitch_cci_get_ports_cpld_info_params +{ + NvU8 versionMajor; + NvU8 versionMinor; +} NVSWITCH_CCI_GET_PORTS_CPLD_INFO_PARAMS; + +#define NVSWITCH_CCI_FW_FLAGS_PRESENT 0:0 +#define NVSWITCH_CCI_FW_FLAGS_PRESENT_NO 0 +#define NVSWITCH_CCI_FW_FLAGS_PRESENT_YES 1 +#define NVSWITCH_CCI_FW_FLAGS_ACTIVE 1:1 +#define NVSWITCH_CCI_FW_FLAGS_ACTIVE_NO 0 +#define NVSWITCH_CCI_FW_FLAGS_ACTIVE_YES 1 +#define NVSWITCH_CCI_FW_FLAGS_COMMITED 2:2 +#define NVSWITCH_CCI_FW_FLAGS_COMMITED_NO 0 +#define NVSWITCH_CCI_FW_FLAGS_COMMITED_YES 1 +#define NVSWITCH_CCI_FW_FLAGS_EMPTY 3:3 +#define NVSWITCH_CCI_FW_FLAGS_EMPTY_NO 0 +#define NVSWITCH_CCI_FW_FLAGS_EMPTY_YES 1 + +#define NVSWITCH_CCI_FW_IMAGE_A 0x0 +#define NVSWITCH_CCI_FW_IMAGE_B 0x1 +#define NVSWITCH_CCI_FW_IMAGE_FACTORY 0x2 +#define NVSWITCH_CCI_FW_IMAGE_COUNT 0x3 + +/* + * Structure to store FW revision parameters + * + * Parameters: + * status + * FW status flags + * image + * Firmware Image A/B/Factory. + * major + * FW major revision. + * minor + * FW minor revision. + * build + * FW build number. + */ +typedef struct nvswitch_cci_get_fw_revisions +{ + NvU8 flags; + NvU8 major; + NvU8 minor; + NvU16 build; +} NVSWITCH_CCI_GET_FW_REVISIONS; + +/* + * CTRL_NVSWITCH_CCI_GET_FW_REVISIONS + * + * Control to get cci firmware revisions of the transreciever. + * + * This API is not supported on SV10. + * + * Parameters: + * link [IN] + * Link number + * revisions [OUT] + * Stores the CCI FW revision params + */ +typedef struct nvswitch_cci_get_fw_revision_params +{ + NvU32 linkId; + NVSWITCH_CCI_GET_FW_REVISIONS revisions[NVSWITCH_CCI_FW_IMAGE_COUNT]; +} NVSWITCH_CCI_GET_FW_REVISION_PARAMS; + +/* + * CTRL_NVSWITCH_CCI_SET_LOCATE_LED + * + * Control to turn on/off the LOCATE LED on a module cage. + * This command will override the current LED state. + * + * Parameters: + * cageIndex [IN] + * Target cage index (>=0 and <= 31) on the + * selected ASIC device. + * portNum [IN] + * Target port (0 or 1) on the seleted + * cage. + * bSetLocateOn [IN] + * Turn on/off LED. NV_TRUE == ON, NV_FALSE == OFF + */ +typedef struct nvswitch_cci_set_locate_led_params +{ + NvU8 cageIndex; + NvU8 portNum; + NvBool bSetLocateOn; +} NVSWITCH_CCI_SET_LOCATE_LED_PARAMS; + +/* + * CTRL_NVSWITCH_GET_SOE_HEARTBEAT + * + * Retrieve SOE Heartbeat status + * + * Parameters: + * + * timestampNs[OUT] + * PTIMER timestamp of the SOE Heartbeat GPIO reading + * gpioVal[OUT] + * Current SOE Heartbeat GPIO value + */ +typedef struct nvswitch_get_soe_heartbeat_params +{ + NvU64 timestampNs; + NvU32 gpioVal; +} NVSWITCH_GET_SOE_HEARTBEAT_PARAMS; + +/* + * CTRL_NVSWITCH_SET_CONTINUOUS_ALI + * + * Enable/disable continuous ALI for all CCI managed links. + * This also enables/disables hot plug. + * + * Continuous ALI is enabled by default. + * + * Parameters: + * bEnable [IN] + */ + +typedef struct +{ + NvBool bEnable; +} NVSWITCH_SET_CONTINUOUS_ALI_PARAMS; + +/* + * CTRL_NVSWITCH_REQUEST_ALI + * + * Request link training for links specified in the mask. + * NVswitch must be in non-continuous ALI mode. Reset + * and drain will always be performed along with ALI. ALI + * requests for links that are currently being trained will be + * dropped. This is an asynchronous request. + * + * Parameters: + * linkMaskTrain [IN] + */ + +typedef struct +{ + // TODO: not used, remove later + NvU64 linkMaskForcedResetAndDrain; + NvU64 linkMaskTrain; +} NVSWITCH_REQUEST_ALI_PARAMS; + /* * CTRL_NVSWITCH_REGISTER_READ/WRITE * @@ -3956,6 +4378,87 @@ typedef struct NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES errorThreshold[NVSWITCH_NVLINK_MAX_LINKS]; } NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS; +/* + * CTRL_NVSWITCH_GET_NVLINK_L1_CAPABILITY + * + * Control to query NvLink L1 Threshold capability. + * + * Parameters: + * linkMask [IN] + * A valid link mask for which we need to get the L1 Threshold + * + * l1Capable [OUT] + * An array of links that are capable of supporting L1 Thresholds + */ +typedef struct +{ + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NvBool l1Capable[NVSWITCH_NVLINK_MAX_LINKS]; +} NVSWITCH_GET_NVLINK_L1_CAPABILITY_PARAMS; + +/* + * CTRL_NVSWITCH_GET_NVLINK_L1_THRESHOLD + * + * Control to query NvLink L1 Thresholds. + * + * Parameters: + * linkMask [IN] + * A valid link mask for which we need to get the L1 Threshold + * + * l1Threshold [OUT] + * L1 Threshold values in units of 100us + */ +typedef struct +{ + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NvU32 l1Threshold[NVSWITCH_NVLINK_MAX_LINKS]; +} NVSWITCH_GET_NVLINK_L1_THRESHOLD_PARAMS; + +#define NVSWITCH_SET_NVLINK_L1_THRESHOLD_MIN 0x1 +#define NVSWITCH_SET_NVLINK_L1_THRESHOLD_MAX 0x1fff +#define NVSWITCH_SET_NVLINK_L1_THRESHOLD_DEFAULT 0xffffffff + +/* + * CTRL_NVSWITCH_SET_NVLINK_L1_THRESHOLD + * + * Control to set NvLink L1 Thresholds. + * + * Parameters: + * linkMask [IN] + * A valid link mask for which we need to get the L1 Threshold + * + * l1Threshold [IN] + * L1 Threshold values in units of 100us + */ +typedef struct +{ + NV_DECLARE_ALIGNED(NvU64 linkMask, 8); + NvU32 l1Threshold[NVSWITCH_NVLINK_MAX_LINKS]; +} NVSWITCH_SET_NVLINK_L1_THRESHOLD_PARAMS; + +/* + * CTRL_NVSWITCH_FSPRPC_GET_CAPS + * + * Control to query FSP capabilities + * + * Parameters: + * commandNvdmType [OUT] + * NVDM type of the command RPC + * responseNvdmType [OUT] + * NVDM type of the RPC response + * errorCode [OUT] + * Error code of the RPC + * pRspPayload [OUT] + * Payload of the response + */ +typedef struct +{ + NvU32 commandNvdmType; + NvU32 responseNvdmType; + NvU32 errorCode; + NvU8* pRspPayload; +} NVSWITCH_FSPRPC_GET_CAPS_PARAMS; + #define REGISTER_RW_ENGINE_RAW 0x00 #define REGISTER_RW_ENGINE_CLKS 0x10 @@ -4061,12 +4564,12 @@ typedef struct #define CTRL_NVSWITCH_SET_RESIDENCY_BINS 0x34 #define CTRL_NVSWITCH_GET_RESIDENCY_BINS 0x35 #define CTRL_NVSWITCH_GET_RB_STALL_BUSY 0x36 -#define CTRL_NVSWITCH_RESERVED_0 0x37 -#define CTRL_NVSWITCH_RESERVED_1 0x38 -#define CTRL_NVSWITCH_RESERVED_2 0x39 -#define CTRL_NVSWITCH_RESERVED_3 0x3A -#define CTRL_NVSWITCH_RESERVED_4 0x3B -#define CTRL_NVSWITCH_RESERVED_5 0x3C +#define CTRL_NVSWITCH_CCI_CMIS_PRESENCE 0x37 +#define CTRL_NVSWITCH_CCI_CMIS_NVLINK_MAPPING 0x38 +#define CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ 0x39 +#define CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE 0x3A +#define CTRL_NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING 0x3B +#define CTRL_NVSWITCH_CCI_GET_GRADING_VALUES 0x3C #define CTRL_NVSWITCH_GET_MULTICAST_ID_ERROR_VECTOR 0x3D #define CTRL_NVSWITCH_CLEAR_MULTICAST_ID_ERROR_VECTOR 0x3E #define CTRL_NVSWITCH_INBAND_SEND_DATA 0x43 @@ -4076,9 +4579,9 @@ typedef struct #define CTRL_NVSWITCH_GET_SW_INFO 0x47 #define CTRL_NVSWITCH_RESERVED_6 0x48 #define CTRL_NVSWITCH_RESERVED_7 0x49 -#define CTRL_NVSWITCH_RESERVED_8 0x4A -#define CTRL_NVSWITCH_RESERVED_9 0x4B -#define CTRL_NVSWITCH_RESERVED_10 0x4C +#define CTRL_NVSWITCH_CCI_GET_PORTS_CPLD_INFO 0x4A +#define CTRL_NVSWITCH_CCI_GET_FW_REVISIONS 0x4B +#define CTRL_NVSWITCH_CCI_SET_LOCATE_LED 0x4C #define CTRL_NVSWITCH_REGISTER_READ 0x4D #define CTRL_NVSWITCH_REGISTER_WRITE 0x4E #define CTRL_NVSWITCH_GET_INFOROM_VERSION 0x4F @@ -4087,7 +4590,7 @@ typedef struct #define CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 0x52 #define CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 0x53 #define CTRL_NVSWITCH_GET_VOLTAGE 0x54 -#define CTRL_NVSWITCH_RESERVED_11 0x55 +#define CTRL_NVSWITCH_GET_SOE_HEARTBEAT 0x55 #define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x56 #define CTRL_NVSWITCH_GET_POWER 0x57 #define CTRL_NVSWITCH_GET_PORT_EVENTS 0x58 @@ -4095,6 +4598,12 @@ typedef struct #define CTRL_NVSWITCH_GET_TIME_INFO 0x60 #define CTRL_NVSWITCH_GET_TEMP_DATA 0x61 #define CTRL_NVSWITCH_GET_TEMP_SAMPLES 0x62 +#define CTRL_NVSWITCH_SET_CONTINUOUS_ALI 0x63 +#define CTRL_NVSWITCH_REQUEST_ALI 0x64 +#define CTRL_NVSWITCH_GET_NVLINK_L1_CAPABILITY 0x65 +#define CTRL_NVSWITCH_GET_NVLINK_L1_THRESHOLD 0x66 +#define CTRL_NVSWITCH_SET_NVLINK_L1_THRESHOLD 0x67 +#define CTRL_NVSWITCH_FSPRPC_GET_CAPS 0x68 #ifdef __cplusplus } diff --git a/src/common/nvswitch/kernel/cci/cables/cci_common.c b/src/common/nvswitch/kernel/cci/cables/cci_common.c new file mode 100644 index 0000000000..12c8282ca4 --- /dev/null +++ b/src/common/nvswitch/kernel/cci/cables/cci_common.c @@ -0,0 +1,1535 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "cci/cci_nvswitch.h" +#include "cci/cci_priv_nvswitch.h" +#include "cci/cci_cables_nvswitch.h" + +#include "nvlink_export.h" + +#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" +#include "ls10/ls10.h" + +#include "soe/soe_nvswitch.h" +#include "flcn/flcnable_nvswitch.h" +#include "flcn/flcn_nvswitch.h" +#include "rmflcncmdif_nvswitch.h" +#include "soe/soeifcmn.h" + +static void +_cci_get_active_fault_link_masks +( + nvswitch_device *device, + NvU64 linkMask, + NvU64 *pLinkMaskActive, + NvU64 *pLinkMaskActivePending, + NvU64 *pLinkMaskFault +) +{ + nvlink_link *link; + NvU64 linkStateDl; + NvU64 linkStateTl; + NvU8 linkNum; + NvU64 linkMaskActive; + NvU64 linkMaskActivePending; + NvU64 linkMaskFault; + + linkMaskActive = 0; + linkMaskActivePending = 0; + linkMaskFault = 0; + + FOR_EACH_INDEX_IN_MASK(64, linkNum, linkMask) + { + link = nvswitch_get_link(device, linkNum); + + if ((link == NULL) || + (device->hal.nvswitch_corelib_get_dl_link_mode(link, &linkStateDl) != NVL_SUCCESS) || + (device->hal.nvswitch_corelib_get_tl_link_mode(link, &linkStateTl) != NVL_SUCCESS)) + { + continue; + } + + switch (linkStateDl) + { + case NVLINK_LINKSTATE_HS: + { + linkMaskActive |= NVBIT64(linkNum); + break; + } + case NVLINK_LINKSTATE_FAULT: + { + linkMaskFault |= NVBIT64(linkNum); + break; + } + default: + { + break; + } + } + + switch (linkStateTl) + { + case NVLINK_LINKSTATE_ACTIVE_PENDING: + { + linkMaskActivePending |= NVBIT64(linkNum); + break; + } + default: + { + break; + } + } + } + FOR_EACH_INDEX_IN_MASK_END; + + if (pLinkMaskActive != NULL) + { + *pLinkMaskActive = linkMaskActive; + } + + if (pLinkMaskActivePending != NULL) + { + *pLinkMaskActivePending = linkMaskActivePending; + } + + if (pLinkMaskFault != NULL) + { + *pLinkMaskFault = linkMaskFault; + } +} + +static NvU8 +_cci_cmis_checksum +( + NvU8 *data, + NvU32 size +) +{ + NvU32 i; + NvU8 checksum = 0; + + for (i = 0; i < size; ++i) + { + checksum += data[i]; + } + return checksum; +} + +static NvlStatus +_cci_module_detect +( + nvswitch_device *device, + NvU8 moduleId +) +{ + PCCI pCci = device->pCci; + NvlStatus retval; + NvU8 charateristicsByte; + + retval = cciCmisRead(device, moduleId, 0, 0, + CMIS_CHARACTERISTICS_BYTE, 1, &charateristicsByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // + // Must be set before further CMIS accesses + // This is done to avoid attempts at setting the page and bank for + // modules with flat memory + // + if (REF_VAL(CMIS_CHARACTERISTICS_BYTE_FLAT_MEM, charateristicsByte) == 0x1) + { + pCci->isFlatMemory[moduleId] = NV_TRUE; + } + else + { + pCci->isFlatMemory[moduleId] = NV_FALSE; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_module_cable_detect +( + nvswitch_device *device, + NvU8 moduleId +) +{ + PCCI pCci = device->pCci; + NvlStatus retval; + NvU8 mitByte; + NvU8 siControls[2]; + + pCci->cableType[moduleId] = CABLE_TYPE_INVALID; + + retval = cciCmisRead(device, moduleId, 0, 0, + CMIS_MIT_BYTE, 1, &mitByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + NVSWITCH_PRINT(device, INFO, + "%s: Module %d CMIS MIT byte 0x%x\n", __FUNCTION__, moduleId, mitByte); + + if (mitByte >= CMIS_MIT_BYTE_RESERVED) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (mitByte >= CMIS_MIT_BYTE_COPPER) + { + switch (mitByte) + { + case CMIS_MIT_BYTE_COPPER_UNEQUALIZED: + { + // OPT loopback modules incorrectly report non-flat memory + pCci->isFlatMemory[moduleId] = NV_TRUE; + pCci->rxDetEnable[moduleId] = NV_TRUE; + break; + } + case CMIS_MIT_BYTE_COPPER_PASSIVE_EQUALIZED: + case CMIS_MIT_BYTE_COPPER_NEAR_FAR_END_LIMITING_ACTIVE_EQUALIZED: + case CMIS_MIT_BYTE_COPPER_FAR_END_LIMITING_ACTIVE_EQUALIZED: + case CMIS_MIT_BYTE_COPPER_NEAR_END_LIMITING_ACTIVE_EQUALIZED: + case CMIS_MIT_BYTE_COPPER_LINEAR_ACTIVE_EQUALIZED: + { + pCci->rxDetEnable[moduleId] = NV_FALSE; + break; + } + default: + { + NVSWITCH_ASSERT(0); + break; + } + } + + pCci->cableType[moduleId] = CABLE_TYPE_COPPER; + } + else + { + NVSWITCH_ASSERT(!pCci->isFlatMemory[moduleId]); + + retval = cciCmisRead(device, moduleId, 0, 1, + CMIS_SI_CONTROLS, 2, siControls); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // rx and tx CDR must both be either implemented or not implemented + if (mitByte >= 8 || + (REF_VAL(CMIS_SI_CONTROLS_CDR_IMPLEMENTED, siControls[0]) != + REF_VAL(CMIS_SI_CONTROLS_CDR_IMPLEMENTED, siControls[1]))) + { + pCci->cableType[moduleId] = CABLE_TYPE_INVALID; + } + + if ((REF_VAL(CMIS_SI_CONTROLS_CDR_IMPLEMENTED, siControls[0]) == 0x1) && + (REF_VAL(CMIS_SI_CONTROLS_CDR_IMPLEMENTED, siControls[1]) == 0x1)) + { + pCci->cableType[moduleId] = CABLE_TYPE_OPTICAL; + } + else + { + pCci->cableType[moduleId] = CABLE_TYPE_DIRECT; + } + + pCci->rxDetEnable[moduleId] = NV_FALSE; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_module_validate +( + nvswitch_device *device, + NvU8 moduleId +) +{ + PCCI pCci = device->pCci; + NvlStatus retval; + NvU8 revByte; + NvU8 checksumByte; + NvU8 checksumBuf[CMIS_CHECKSUM_LENGTH]; + NvU8 checksum; + + // Passive copper so do nothing + if (pCci->cableType[moduleId] == CABLE_TYPE_COPPER && + pCci->rxDetEnable[moduleId]) + { + return NVL_SUCCESS; + } + + retval = cciCmisRead(device, moduleId, 0, 0, + CMIS_REV_BYTE, 1, &revByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + if (!(REF_VAL(CMIS_REV_BYTE_WHOLE, revByte) == 0x4 || + REF_VAL(CMIS_REV_BYTE_WHOLE, revByte) == 0x5)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CMIS version %d.%d not supported\n", __FUNCTION__, + REF_VAL(CMIS_REV_BYTE_WHOLE, revByte), + REF_VAL(CMIS_REV_BYTE_DECIMAL, revByte)); + return -NVL_ERR_NOT_SUPPORTED; + } + + retval = cciCmisRead(device, moduleId, 0, 0, + 128, CMIS_CHECKSUM_LENGTH, checksumBuf); + if (retval != NVL_SUCCESS) + { + return retval; + } + + checksum = _cci_cmis_checksum(checksumBuf, CMIS_CHECKSUM_LENGTH); + + retval = cciCmisRead(device, moduleId, 0, 0, + CMIS_CHECKSUM_BYTE, 1, &checksumByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + if (checksum != checksumByte) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CMIS checksum error\n", __FUNCTION__); + return -NVL_ERR_GENERIC; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_module_identify +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + + // Already identified module + if (device->pCci->moduleState[moduleId].bModuleIdentified) + { + return NVL_SUCCESS; + } + + if (!cciModuleHWGood(device, moduleId)) + { + // Mark as faulty + device->pCci->isFaulty[moduleId] = NV_TRUE; + + NVSWITCH_PRINT(device, ERROR, + "%s: Module HW check failed. Module %d\n", __FUNCTION__, moduleId); + return -NVL_ERR_GENERIC; + } + + NVSWITCH_ASSERT(device->pCci->isFaulty[moduleId] == NV_FALSE); + + // Detect basic module characteristics + retval = _cci_module_detect(device, moduleId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module detection failed. Module %d\n", __FUNCTION__, moduleId); + return retval; + } + + // Determine cable type + retval = _cci_module_cable_detect(device, moduleId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module cable detection failed. Module %d\n", __FUNCTION__, moduleId); + return retval; + } + + // Validate module + retval = _cci_module_validate(device, moduleId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module validate failed. Module %d\n", __FUNCTION__, moduleId); + return retval; + } + + device->pCci->moduleState[moduleId].bModuleIdentified = NV_TRUE; + + return NVL_SUCCESS; +} + +static void +_cci_reset_module_state_hw +( + nvswitch_device *device, + NvU8 moduleId +) +{ + // HW reset via CPLD + cciResetModule(device, moduleId); + + NVSWITCH_PRINT(device, INFO, + "%s: Module %d HW reset\n", __FUNCTION__, moduleId); +} + +static void +_cci_reset_module_state_sw +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + // Clear SW state + nvswitch_os_memset(pOnboardState, 0, sizeof(CCI_MODULE_STATE)); + + if (device->pCci->bModeContinuousALI[moduleId]) + { + pOnboardState->currOnboardState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + } + else + { + pOnboardState->currOnboardState.onboardPhase = CCI_ONBOARD_PHASE_NON_CONTINUOUS_ALI; + } + device->pCci->isFaulty[moduleId] = NV_FALSE; + + NVSWITCH_PRINT(device, INFO, + "%s: Module %d SW reset\n", __FUNCTION__, moduleId); +} + +/** + * @brief Return the mask of enabled CCI managed links mapped to the given module + * + * @param[in] device nvswitch_device pointer + * @param[in] moduleId + * @param[out] pLinkMask + */ +static void +_cci_get_enabled_link_mask +( + nvswitch_device *device, + NvU8 moduleId, + NvU64 *pLinkMask +) +{ + NvlStatus status; + NvU64 linkMask; + + linkMask = 0; + + status = cciGetCageMapping(device, moduleId, &linkMask, NULL); + if (status != NVL_SUCCESS) + { + linkMask = 0; + } + + // Skip disabled links + linkMask &= device->pCci->linkMask; + + if (pLinkMask != NULL) + { + *pLinkMask = linkMask; + } +} + +/** + * @brief Setup link training mask and module HW for onboarding + * + * @param[in] device nvswitch_device pointer + * @param[in] moduleId + * + */ +static void +_cci_setup_onboard +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + NvU64 linkMask; + NvU64 linkMaskActive; + NvU64 linkMaskActivePending; + NvU64 linkMaskFault; + NvU64 linkMaskReset; + NvU64 linkMaskResetForced; + + pOnboardState = &device->pCci->moduleState[moduleId]; + linkMask = 0; + linkMaskActive = 0; + + _cci_get_enabled_link_mask(device, moduleId, &linkMask); + + _cci_get_active_fault_link_masks(device, linkMask, &linkMaskActive, &linkMaskActivePending, &linkMaskFault); + + NVSWITCH_PRINT(device, INFO, + "%s: Module %d link masks: ACTIVE 0x%llx ACTIVE_PENDING 0x%llx FAULT 0x%llx\n", + __FUNCTION__, moduleId, linkMaskActive, linkMaskActivePending, linkMaskFault); + + if (device->pCci->bModeContinuousALI[moduleId]) + { + // Only train non-active links + pOnboardState->linkTrainMask = linkMask & ~linkMaskActive; + } + else + { + // Clear ALI requests for links that are active pending + device->pCci->linkMaskAliRequested &= ~linkMaskActivePending; + pOnboardState->linkTrainMask = linkMask & device->pCci->linkMaskAliRequested; + } + + // Skip attempts to retrain links that are still being trained in MINION + pOnboardState->linkTrainMask &= ~linkMaskActivePending; + + if (linkMaskActive || linkMaskActivePending) + { + // Module is considered onboarded if any link is active + pOnboardState->bModuleOnboarded = NV_TRUE; + } + + // Nothing to do + if (pOnboardState->linkTrainMask == 0) + { + return; + } + + pOnboardState->bPartialLinkTrainComplete = NV_FALSE; + pOnboardState->bLinkTrainComplete = NV_FALSE; + + // Reset links that are going to be trained + linkMaskReset = pOnboardState->linkTrainMask & linkMaskFault; + linkMaskResetForced = pOnboardState->linkTrainMask & ~linkMaskFault; + + // Faulted links + if (linkMaskReset) + { + device->hal.nvswitch_cci_reset_and_drain_links(device, linkMaskReset, NV_FALSE); + } + + // Link re-training might occur on links that have not faulted + if (linkMaskResetForced) + { + device->hal.nvswitch_cci_reset_and_drain_links(device, linkMaskResetForced, NV_TRUE); + } + + // + // Reset module if all enabled links mapped to a module are going to be trained + // or if module has not been successfully onboarded + // + if (pOnboardState->linkTrainMask == linkMask || !pOnboardState->bModuleOnboarded) + { + _cci_reset_module_state_hw(device, moduleId); + pOnboardState->bModuleOnboarded = NV_FALSE; + } +} + +static void +_cci_module_check_onboard_condition_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + CCI_MODULE_ONBOARD_STATE nextState; + NvBool bDoOnboard; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + pOnboardState = &device->pCci->moduleState[moduleId]; + + // Do nothing if module HW is faulty + if (device->pCci->isFaulty[moduleId]) + { + bDoOnboard = NV_FALSE; + } + else + { + _cci_setup_onboard(device, moduleId); + + // Check if onboarding should actually be performed after setup + bDoOnboard = cciModulePresent(device, moduleId) && + pOnboardState->linkTrainMask && + (pOnboardState->onboardAttempts < CCI_ONBOARD_MAX_ATTEMPTS); + } + + if (bDoOnboard) + { + pOnboardState->onboardAttempts++; + nextState.onboardPhase = CCI_ONBOARD_PHASE_IDENTIFY; + + NVSWITCH_PRINT(device, INFO, + "%s: Module %d on-board attempt %d\n", + __FUNCTION__, moduleId, pOnboardState->onboardAttempts); + } + else + { + nextState.onboardPhase = CCI_ONBOARD_PHASE_MONITOR; + } + + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} + +static void +_cci_module_identify_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + PCCI pCci = device->pCci; + CCI_MODULE_ONBOARD_STATE nextState; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + retval = _cci_module_identify(device, moduleId); + if (retval == NVL_SUCCESS) + { + switch (pCci->cableType[moduleId]) + { + case CABLE_TYPE_COPPER: + { + nextState.onboardPhase = CCI_ONBOARD_PHASE_INIT_COPPER; + break; + } + case CABLE_TYPE_DIRECT: + { + nextState.onboardPhase = CCI_ONBOARD_PHASE_INIT_DIRECT; + break; + } + case CABLE_TYPE_OPTICAL: + { + nextState.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + break; + } + default: + { + // Not expected + NVSWITCH_ASSERT(0); + nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + break; + } + } + } + else + { + nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + } + + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} + +static void +_cci_launch_ALI_async +( + nvswitch_device *device, + NvU32 moduleId +) +{ + NvlStatus retval = NVL_SUCCESS; + CCI_MODULE_STATE *pOnboardState; + CCI_MODULE_ONBOARD_STATE nextState; + nvlink_link *link; + NvU64 linkTrainMask; + NvU32 linkId; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + pOnboardState = &device->pCci->moduleState[moduleId]; + + linkTrainMask = pOnboardState->linkTrainMask; + + FOR_EACH_INDEX_IN_MASK(64, linkId, linkTrainMask) + { + NVSWITCH_ASSERT(linkId < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, linkId); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID(device, linkId, NVLIPT_LNK) || + (linkId >= NVSWITCH_NVLINK_MAX_LINKS)) + { + continue; + } + + if (!nvswitch_is_link_in_reset(device, link)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Link: %d not in reset\n", + __FUNCTION__, linkId); + continue; + } + + NVSWITCH_PRINT(device, INFO, + "%s: ALI launching on link: %d\n", + __FUNCTION__, linkId); + + retval = nvswitch_request_tl_link_state_ls10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE, + NV_FALSE); + + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link state request to active for ALI failed for link: %d\n", + __FUNCTION__, linkId); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + nextState.onboardPhase = CCI_ONBOARD_PHASE_MONITOR; + + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} + +static void +_cci_module_onboard_sleep_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + CCI_MODULE_ONBOARD_STATE nextState; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + pOnboardState = &device->pCci->moduleState[moduleId]; + + // Move to saved state if enough time has elapsed + if (nvswitch_os_get_platform_time() >= pOnboardState->sleepState.wakeUpTimestamp) + { + nextState = pOnboardState->sleepState.returnState; + } + else + { + nextState = pOnboardState->currOnboardState; + } + + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} + +static void +_cci_module_onboard_monitor_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvU64 linkMask; + NvU64 linkMaskActive; + NvU64 linkMaskFault; + CCI_MODULE_STATE *pOnboardState; + CCI_MODULE_ONBOARD_STATE nextState; + NvBool bRetryOnboard; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + pOnboardState = &device->pCci->moduleState[moduleId]; + nextState.onboardPhase = CCI_ONBOARD_PHASE_MONITOR; + linkMask = 0; + linkMaskActive = 0; + linkMaskFault = 0; + bRetryOnboard = NV_FALSE; + + _cci_get_enabled_link_mask(device, moduleId, &linkMask); + + // 1. Get active/fault link masks and update onboarding state + _cci_get_active_fault_link_masks(device, linkMask, &linkMaskActive, NULL, &linkMaskFault); + + if (linkMaskActive) + { + // Module is considered onboarded if any link is active + pOnboardState->bModuleOnboarded = NV_TRUE; + + if (!device->pCci->bModeContinuousALI[moduleId]) + { + // Only clear active links that ALI was requested for + device->pCci->linkMaskAliRequested &= ~(pOnboardState->linkTrainMask & linkMaskActive); + } + + // Clear trained links from train mask + pOnboardState->linkTrainMask &= ~linkMaskActive; + } + + // + // In non-continuous ALI mode, only handle faulted links + // that are being trained + // + if (!device->pCci->bModeContinuousALI[moduleId]) + { + linkMaskFault &= pOnboardState->linkTrainMask; + } + + // 2. Handle module/link errors and trigger re-onboard if necessary + if (linkMaskFault || pOnboardState->onboardError.bOnboardFailure) + { + // + // ACTIVE -> FAULT transition detected + // This could be a hot plug event(remote end) + // Reset SW state to re-attempt training for non-ACTIVE module links + // + // Hot plug path only entered if continuous ALI requested + // + if ((pOnboardState->linkMaskActiveSaved & linkMaskFault) && + device->bModeContinuousALI) + { + // In case faults occur in the middle of onboarding, keep track of onboarding attempts + if (pOnboardState->onboardAttempts > 0) + { + NVSWITCH_PRINT(device, INFO, + "%s: ACTIVE -> FAULT detected on module %d links 0x%llx. On-board attempts: %d\n", + __FUNCTION__, moduleId, pOnboardState->linkMaskActiveSaved & linkMaskFault, + pOnboardState->onboardAttempts); + } + + // + // HW reset will be performed during onboard setup if the + // event is actually a hot plug + // + _cci_reset_module_state_sw(device, moduleId); + bRetryOnboard = NV_TRUE; + } + + if (pOnboardState->onboardAttempts == CCI_ONBOARD_MAX_ATTEMPTS) + { + // Check will only be performed once per module until a hot plug event + if (!pOnboardState->onboardError.bErrorsChecked) + { + cciSetLPMode(device, moduleId, NV_FALSE); + cciModuleOnboardCheckErrors(device, moduleId); + pOnboardState->onboardError.bErrorsChecked = NV_TRUE; + } + + // + // Remaining non-active links failed to train so + // remove from ALI requested mask + // + if (!device->pCci->bModeContinuousALI[moduleId]) + { + device->pCci->linkMaskAliRequested &= ~pOnboardState->linkTrainMask; + } + + // Clear links from train mask after all attempts exhausted + pOnboardState->linkTrainMask = 0; + } + else + { + // Attempt to re-onboard links/module + bRetryOnboard = NV_TRUE; + nvswitch_os_memset(&pOnboardState->onboardError, 0, sizeof(CCI_MODULE_ONBOARD_ERROR)); + nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + } + } + + // 3. Re-attempt onboard if training for some links were deferred + if ((pOnboardState->linkTrainMask == 0) && + pOnboardState->bLinkTrainDeferred) + { + NVSWITCH_PRINT(device, INFO, + "%s: Module %d link training deferred\n", + __FUNCTION__, moduleId); + + pOnboardState->bLinkTrainDeferred = NV_FALSE; + bRetryOnboard = NV_TRUE; + nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + } + + // + // 4. Mark the link training portion of onboarding as complete if the + // link train mask is empty and if there are no retry requests. + // + if ((pOnboardState->linkTrainMask == 0) && !bRetryOnboard) + { + if (!pOnboardState->bLinkTrainComplete && linkMaskActive) + { + NVSWITCH_PRINT(device, INFO, + "%s: Module %d links 0x%llx ACTIVE. On-board attempts: %d\n", + __FUNCTION__, moduleId, linkMaskActive, pOnboardState->onboardAttempts); + } + + pOnboardState->bLinkTrainComplete = NV_TRUE; + + if (device->pCci->bModeContinuousALI[moduleId]) + { + pOnboardState->linkMaskActiveSaved = linkMaskActive; + } + + // + // Move to non-continuous ALI mode or stay in it. + // The only way to transition back to continuous ALI would be + // from the non-continuous ALI phase + // + if (!device->bModeContinuousALI || + !device->pCci->bModeContinuousALI[moduleId]) + { + device->pCci->bModeContinuousALI[moduleId] = NV_FALSE; + nextState.onboardPhase = CCI_ONBOARD_PHASE_NON_CONTINUOUS_ALI; + } + } + + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} + +static void +_cci_module_non_continuous_ALI_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus status; + CCI_MODULE_ONBOARD_STATE nextState; + NvU64 linkMask; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nextState.onboardPhase = CCI_ONBOARD_PHASE_NON_CONTINUOUS_ALI; + linkMask = 0; + + // Go back to continuous ALI mode + if (device->bModeContinuousALI) + { + device->pCci->bModeContinuousALI[moduleId] = NV_TRUE; + nextState.onboardPhase = CCI_ONBOARD_PHASE_MONITOR; + _cci_reset_module_state_sw(device, moduleId); + goto _cci_module_non_continuous_ALI_async_exit; + } + + status = _cci_module_identify(device, moduleId); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to identify module %d\n", + __FUNCTION__, moduleId); + } + + // Attempt to train requested links + _cci_get_enabled_link_mask(device, moduleId, &linkMask); + if (device->pCci->linkMaskAliRequested & linkMask) + { + _cci_reset_module_state_sw(device, moduleId); + nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + } + +_cci_module_non_continuous_ALI_async_exit: + + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} + +static void +_cci_module_onboard_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + CCI_MODULE_ONBOARD_STATE nextState; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + pOnboardState = &device->pCci->moduleState[moduleId]; + + switch (pOnboardState->currOnboardState.onboardPhase) + { + case CCI_ONBOARD_PHASE_CHECK_CONDITION: + { + _cci_module_check_onboard_condition_async(device, moduleId); + break; + } + case CCI_ONBOARD_PHASE_IDENTIFY: + { + _cci_module_identify_async(device, moduleId); + break; + } + case CCI_ONBOARD_PHASE_INIT_COPPER: + { + cciCablesInitializeCopperAsync(device, moduleId); + break; + } + case CCI_ONBOARD_PHASE_INIT_DIRECT: + { + cciCablesInitializeDirectAsync(device, moduleId); + break; + } + case CCI_ONBOARD_PHASE_INIT_OPTICAL: + { + cciCablesInitializeOpticalAsync(device, moduleId); + break; + } + case CCI_ONBOARD_PHASE_LAUNCH_ALI: + { + _cci_launch_ALI_async(device, moduleId); + break; + } + case CCI_ONBOARD_PHASE_SLEEP: + { + _cci_module_onboard_sleep_async(device, moduleId); + break; + } + case CCI_ONBOARD_PHASE_MONITOR: + { + _cci_module_onboard_monitor_async(device, moduleId); + break; + } + case CCI_ONBOARD_PHASE_NON_CONTINUOUS_ALI: + { + _cci_module_non_continuous_ALI_async(device, moduleId); + break; + } + default: + { + // Not expected + NVSWITCH_ASSERT(0); + nextState.onboardPhase = CCI_ONBOARD_PHASE_MONITOR; + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); + break; + } + } +} + +void +cciModulesOnboardInit +( + nvswitch_device *device +) +{ + NvlStatus status; + CCI_MODULE_STATE *pOnboardState; + NvU32 cageMask; + NvU32 moduleMaskPresent; + NvU8 moduleId; + NvU64 linkMask; + NvU64 linkMaskActive; + + status = cciGetXcvrMask(device, &cageMask, &moduleMaskPresent); + if (status != NVL_SUCCESS) + { + return; + } + + FOR_EACH_INDEX_IN_MASK(32, moduleId, cageMask) + { + device->pCci->bModeContinuousALI[moduleId] = device->bModeContinuousALI; + } + FOR_EACH_INDEX_IN_MASK_END; + + // Check if on-boarding needed on init + FOR_EACH_INDEX_IN_MASK(32, moduleId, moduleMaskPresent) + { + pOnboardState = &device->pCci->moduleState[moduleId]; + linkMask = 0; + linkMaskActive = 0; + + _cci_reset_module_state_sw(device, moduleId); + _cci_get_enabled_link_mask(device, moduleId, &linkMask); + _cci_get_active_fault_link_masks(device, linkMask, &linkMaskActive, NULL, NULL); + + // Check if links on module are already active + if (linkMaskActive) + { + NVSWITCH_PRINT(device, INFO, + "%s: Module %d links 0x%llx ACTIVE.\n", + __FUNCTION__, moduleId, linkMaskActive); + + // Module is considered onboarded if any link is active + pOnboardState->bModuleOnboarded = NV_TRUE; + pOnboardState->linkMaskActiveSaved = linkMaskActive; + + if (linkMaskActive == linkMask) + { + pOnboardState->bLinkTrainComplete = NV_TRUE; + } + + status = _cci_module_identify(device, moduleId); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module identification failed. Module %d\n", __FUNCTION__, moduleId); + } + } + } + FOR_EACH_INDEX_IN_MASK_END; +} + +static NvBool +_cciCmisAccessSafe +( + nvswitch_device *device, + NvU8 moduleId +) +{ + return !cciCheckLPMode(device, moduleId); +} + +void +cciModulesOnboardCallback +( + nvswitch_device *device +) +{ + NvlStatus retval; + NvU32 cagesMask; + NvU32 moduleMaskPresentChange; + NvU32 moduleId; + + cciDetectXcvrsPresent(device); + + retval = cciGetXcvrMask(device, &cagesMask, NULL); + if (retval != NVL_SUCCESS) + { + return; + } + + cciGetModulePresenceChange(device, &moduleMaskPresentChange); + + FOR_EACH_INDEX_IN_MASK(32, moduleId, moduleMaskPresentChange) + { + // + // Hot plug/unplug detected(local end), so reset SW state for future on-board + // HW reset will be performed during onboard setup + // + _cci_reset_module_state_sw(device, moduleId); + cciCmisAccessReleaseLock(device, moduleId); + } + FOR_EACH_INDEX_IN_MASK_END; + + FOR_EACH_INDEX_IN_MASK(32, moduleId, cagesMask) + { + // Try to acquire CMIS access lock for module + if (!cciCmisAccessTryLock(device, moduleId)) + { + continue; + } + + _cci_module_onboard_async(device, moduleId); + + // Release CMIS access lock if safe to do so + if (_cciCmisAccessSafe(device, moduleId)) + { + cciCmisAccessReleaseLock(device, moduleId); + } + } + FOR_EACH_INDEX_IN_MASK_END; +} + +NvBool +cciLinkTrainIdle +( + nvswitch_device *device, + NvU8 linkId +) +{ + NvlStatus retval; + CCI_MODULE_STATE *pOnboardState; + NvU32 moduleId; + NvBool bLinkTrainIdle; + + bLinkTrainIdle = NV_FALSE; + + retval = cciGetModuleId(device, linkId, &moduleId); + if (retval != NVL_SUCCESS) + { + return NV_TRUE; + } + + if (cciModulePresent(device, moduleId)) + { + pOnboardState = &device->pCci->moduleState[moduleId]; + bLinkTrainIdle = !(pOnboardState->linkTrainMask & NVBIT64(linkId)); + + return bLinkTrainIdle; + } + else + { + return NV_TRUE; + } +} + +NvBool +cciModuleOnboardFailed +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + if (pOnboardState->onboardAttempts < CCI_ONBOARD_MAX_ATTEMPTS) + { + return NV_FALSE; + } + else + { + return pOnboardState->onboardError.bOnboardFailure; + } +} + +void +cciModuleOnboardShutdown +( + nvswitch_device *device +) +{ + CCI_MODULE_STATE *pOnboardState; + NvU32 cagesMask; + NvU8 moduleId; + NvU8 ledState; + NvlStatus retval; + + retval = cciGetXcvrMask(device, &cagesMask, NULL); + if (retval != NVL_SUCCESS) + { + return; + } + + ledState = 0; + ledState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_A, + CCI_LED_STATE_OFF, ledState); + ledState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_B, + CCI_LED_STATE_OFF, ledState); + + // CCI temporarily disables ALI during onboarding so re-enable during driver unload + FOR_EACH_INDEX_IN_MASK(32, moduleId, cagesMask) + { + // Force Enable ALI onboard phase + pOnboardState = &device->pCci->moduleState[moduleId]; + pOnboardState->currOnboardState.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + pOnboardState->currOnboardState.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_ENABLE_ALI; + + // Have SOE re-enable ALI for links assoicated with module + retval = cciModulesOnboardSOE(device, moduleId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_SHUTDOWN, + "Failed to re-enable ALI for module %d links.\n", + moduleId); + } + + // + // Turn off LEDs since driver is being unloaded and + // will no longer be monitoring links/modules + // + cciSetNextXcvrLedState(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + moduleId, ledState); + cciSetXcvrLedState(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + moduleId, NV_FALSE); + + // Prevent Onboard state machine from performing other phases + pOnboardState->currOnboardState.onboardPhase = CCI_ONBOARD_PHASE_MONITOR; + } + FOR_EACH_INDEX_IN_MASK_END; +} + +static void +_cciSetupCmdModulesOnboardSOE +( + nvswitch_device *device, + NvU8 moduleId, + RM_SOE_CORE_CMD_PERFORM_ONBOARD_PHASE *pCmd +) +{ + PCCI pCci = device->pCci; + CCI_MODULE_STATE *pOnboardState; + NvU64 linkMask; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + pCmd->cmdType = RM_SOE_CORE_CMD_PERFORM_MODULE_ONBOARD_PHASE; + pCmd->moduleId = moduleId; + pCmd->onboardPhase = pOnboardState->currOnboardState.onboardPhase; + + switch (pCmd->onboardPhase) + { + case CCI_ONBOARD_PHASE_INIT_OPTICAL: + { + pCmd->onboardSubPhase = pOnboardState->currOnboardState.onboardSubPhase.optical; + break; + } + default: + { + break; + } + } + + pCmd->attributes.rxDetEnable = pCci->rxDetEnable[moduleId]; + + linkMask = pOnboardState->linkTrainMask; + + RM_FLCN_U64_PACK(&pCmd->linkMask, &linkMask); +} + +NvlStatus +cciModulesOnboardSOE +( + nvswitch_device *device, + NvU8 moduleId +) +{ + FLCN *pFlcn; + NvU32 cmdSeqDesc; + NV_STATUS status; + NvU8 flcnStatus; + RM_FLCN_CMD_SOE cmd; + RM_FLCN_MSG_SOE msg; + RM_SOE_CORE_CMD_PERFORM_ONBOARD_PHASE *pPerformOnboardPhaseCmd; + NVSWITCH_TIMEOUT timeout; + + if (!nvswitch_is_soe_supported(device)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(&cmd, 0, sizeof(RM_FLCN_CMD_SOE)); + nvswitch_os_memset(&msg, 0, sizeof(RM_FLCN_MSG_SOE)); + + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, PERFORM_ONBOARD_PHASE); + + msg.hdr.unitId = RM_SOE_UNIT_CORE; + msg.hdr.size = RM_SOE_MSG_SIZE(CORE, PERFORM_ONBOARD_PHASE); + + pPerformOnboardPhaseCmd = &cmd.cmd.core.performOnboardPhase; + _cciSetupCmdModulesOnboardSOE(device, moduleId, pPerformOnboardPhaseCmd); + + cmdSeqDesc = 0; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS * 5, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + (PRM_FLCN_MSG)&msg, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed onboard SOE phase for module 0x%x\n", + __FUNCTION__, moduleId); + return -NVL_ERR_INVALID_STATE; + } + + flcnStatus = msg.msg.core.performOnboardPhase.flcnStatus; + + if (flcnStatus != FLCN_OK) + { + if (flcnStatus == FLCN_ERR_INVALID_ARGUMENT) + { + return -NVL_BAD_ARGS; + } + else + { + return -NVL_ERR_GENERIC; + } + } + + return NVL_SUCCESS; +} + +NvlStatus +cciModuleEject +( + nvswitch_device *device, + NvU8 moduleId +) +{ + return -NVL_ERR_NOT_IMPLEMENTED; +} + +NvlStatus +cciRequestALI +( + nvswitch_device *device, + NvU64 linkMaskTrain +) +{ + NvlStatus status; + CCI_MODULE_STATE *pOnboardState; + NvU32 linkId; + NvU32 moduleId; + + if (device->bModeContinuousALI) + { + return -NVL_ERR_INVALID_STATE; + } + + FOR_EACH_INDEX_IN_MASK(64, linkId, linkMaskTrain) + { + status = cciGetModuleId(device, linkId, &moduleId); + if (status != NVL_SUCCESS) + { + continue; + } + + pOnboardState = &device->pCci->moduleState[moduleId]; + + // Reset state to prevent deadlock in synchronization stages of link training + if (!device->pCci->bModeContinuousALI[moduleId] && + !pOnboardState->bPartialLinkTrainComplete) + { + _cci_reset_module_state_sw(device, moduleId); + } + + device->pCci->linkMaskAliRequested |= NVBIT64(linkId); + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + + +// Helper functions + +NvlStatus +cciSetLedsInitialize +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvU8 ledState; + + ledState = 0; + ledState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_A, + CCI_LED_STATE_INITIALIZE, ledState); + ledState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_B, + CCI_LED_STATE_INITIALIZE, ledState); + cciSetNextXcvrLedState(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + moduleId, ledState); + cciSetXcvrLedState(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + moduleId, NV_FALSE); + + return NVL_SUCCESS; +} + +/** + * @brief Moves a module into the provided next state. + * This should be called as the last operation of a particular phase. + * The purpose of this function is to provide a trace + * point for phase transitions to aid with clarity and logging. + * + * @param[in] device nvswitch_device pointer + * @param[in] moduleId Modules to perfrom phase transition on + * @param[in] nextState The next state a module will be put into + * + */ +void +cciModuleOnboardPerformPhaseTransitionAsync +( + nvswitch_device *device, + NvU8 moduleId, + CCI_MODULE_ONBOARD_STATE nextState +) +{ + CCI_MODULE_STATE *pOnboardState; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + pOnboardState->prevOnboardState = pOnboardState->currOnboardState; + pOnboardState->currOnboardState = nextState; +} + +/** + * @brief Inserts a non-blocking delay between the current module state and the + * provided return state. + * Will setup the sleep state to move the input module into the provided + * return state after the given sleep period. + * This should be called as the last operation of a particular phase. + * + * @param[in] device nvswitch_device pointer + * @param[in] moduleId Modules to perfrom phase transition on + * @param[in] sleepMs Time delay in ms. Note that the sleep resolution will + * a multiple of the polling period of the onboard state machine + * @param[in] returnState The state a module will be put into after the delay + * + */ +void +cciModuleOnboardSleepAsync +( + nvswitch_device *device, + NvU8 moduleId, + NvU32 sleepMs, + CCI_MODULE_ONBOARD_STATE returnState +) +{ + CCI_MODULE_STATE *pOnboardState; + CCI_MODULE_ONBOARD_STATE nextState; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + pOnboardState = &device->pCci->moduleState[moduleId]; + + // Save information to return from the sleep phase + pOnboardState->sleepState.wakeUpTimestamp = nvswitch_os_get_platform_time() + + (sleepMs * NVSWITCH_INTERVAL_1MSEC_IN_NS); + pOnboardState->sleepState.returnState = returnState; + + // Move to sleep phase + nextState.onboardPhase = CCI_ONBOARD_PHASE_SLEEP; + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} + +void +cciModuleOnboardPerformPhaseAsync +( + nvswitch_device *device, + NvU8 moduleId, + NvlStatus (*func)(nvswitch_device *, NvU8), + CCI_MODULE_ONBOARD_STATE nextStateSuccess, + CCI_MODULE_ONBOARD_STATE nextStateFail +) +{ + NvlStatus retval; + CCI_MODULE_STATE *pOnboardState; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + retval = func(device, moduleId); + if (retval == NVL_SUCCESS) + { + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextStateSuccess); + } + else + { + pOnboardState->onboardError.bOnboardFailure = NV_TRUE; + pOnboardState->onboardError.failedOnboardState = pOnboardState->currOnboardState; + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextStateFail); + } +} diff --git a/src/common/nvswitch/kernel/cci/cables/cci_copper.c b/src/common/nvswitch/kernel/cci/cables/cci_copper.c new file mode 100644 index 0000000000..01f0b8d562 --- /dev/null +++ b/src/common/nvswitch/kernel/cci/cables/cci_copper.c @@ -0,0 +1,166 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" + +#include "cci/cci_nvswitch.h" +#include "cci/cci_priv_nvswitch.h" +#include "cci/cci_cables_nvswitch.h" + +#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" +#include "ls10/ls10.h" + +static NvlStatus +_cci_cable_initialize_links +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + NvlStatus retval; + NvlStatus loopStatus; + NvU64 linkState; + NvU64 linkMask; + NvU32 linkId; + nvlink_link *link; + + loopStatus = NVL_SUCCESS; + pOnboardState = &device->pCci->moduleState[moduleId]; + + // De-assert lpmode + retval = cciSetLPMode(device, moduleId, NV_FALSE); + if (retval != NVL_SUCCESS) + { + return retval; + } + + linkMask = pOnboardState->linkTrainMask; + + FOR_EACH_INDEX_IN_MASK(64, linkId, linkMask) + { + NVSWITCH_ASSERT(linkId < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, linkId); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID(device, link->linkNumber, NVLIPT_LNK) || + (linkId >= NVSWITCH_NVLINK_MAX_LINKS)) + { + continue; + } + + retval = link->link_handlers->get_dl_link_mode(link, &linkState); + + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get link state for link: %d\n", + __FUNCTION__, linkId); + continue; + } + + // This only makes sense to do in the driver + if (linkState == NVLINK_LINKSTATE_HS || + linkState == NVLINK_LINKSTATE_SAFE || + linkState == NVLINK_LINKSTATE_RECOVERY || + linkState == NVLINK_LINKSTATE_SLEEP) + { + continue; + } + + // Shutdown and Reset link + if (linkState != NVLINK_LINKSTATE_RESET) + { + retval = nvswitch_request_tl_link_state_ls10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN, + NV_TRUE); + + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link shutdown request failed for link: %d\n", + __FUNCTION__, linkId); + } + + retval = nvswitch_request_tl_link_state_ls10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, + NV_TRUE); + + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link reset request failed for link: %d\n", + __FUNCTION__, linkId); + loopStatus = retval; + } + } + } + FOR_EACH_INDEX_IN_MASK_END; + + if (loopStatus != NVL_SUCCESS) + { + return loopStatus; + } + + // Have SOE perform system register setup + retval = cciModulesOnboardSOE(device, moduleId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: System register setup failed for module: %d\n", + __FUNCTION__, moduleId); + return retval; + } + + return NVL_SUCCESS; +} + +/* + * @brief Initialize copper cable + * + * @param[in] device nvswitch_device pointer + * @param[in] moduleId Module will be initialized. + * + */ +void +cciCablesInitializeCopperAsync +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextStateSuccess; + CCI_MODULE_ONBOARD_STATE nextStateFail; + + nvswitch_os_memset(&nextStateSuccess, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nvswitch_os_memset(&nextStateFail, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + nextStateSuccess.onboardPhase = CCI_ONBOARD_PHASE_LAUNCH_ALI; + nextStateFail.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseAsync(device, moduleId, + _cci_cable_initialize_links, + nextStateSuccess, + nextStateFail); + cciSetLedsInitialize(device, moduleId); +} diff --git a/src/common/nvswitch/kernel/cci/cables/cci_direct.c b/src/common/nvswitch/kernel/cci/cables/cci_direct.c new file mode 100644 index 0000000000..6bc5f63627 --- /dev/null +++ b/src/common/nvswitch/kernel/cci/cables/cci_direct.c @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "cci/cci_nvswitch.h" +#include "cci/cci_priv_nvswitch.h" +#include "cci/cci_cables_nvswitch.h" + +void +cciCablesInitializeDirectAsync +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextState; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + NVSWITCH_PRINT(device, INFO, + "%s: Not implemented.\n", + __FUNCTION__); + nextState.onboardPhase = CCI_ONBOARD_PHASE_MONITOR; + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} diff --git a/src/common/nvswitch/kernel/cci/cables/cci_error.c b/src/common/nvswitch/kernel/cci/cables/cci_error.c new file mode 100644 index 0000000000..139d612fb3 --- /dev/null +++ b/src/common/nvswitch/kernel/cci/cables/cci_error.c @@ -0,0 +1,284 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "cci/cci_nvswitch.h" +#include "cci/cci_priv_nvswitch.h" +#include "cci/cci_cables_nvswitch.h" + +#include "nvlink_export.h" + +// +// Custom byte definition obtained from the following doc: +// "LINKX BOOT FAIL AND RECOVERY INDICATIONS" +// +#define MODULE_FLAGS_CUSTOM_BYTE_BOOT_FAILURE 0:0 +#define MODULE_FLAGS_CUSTOM_BYTE_RECOVERY 1:1 + +static const char* +_cci_onboard_phase_to_text +( + CCI_MODULE_ONBOARD_PHASE phase, + CCI_MODULE_ONBOARD_SUBPHASE_OPTICAL subphase +) +{ + switch (phase) + { + case CCI_ONBOARD_PHASE_CHECK_CONDITION: + { + return "CCI Onboard Phase Check Condition"; + } + case CCI_ONBOARD_PHASE_IDENTIFY: + { + return "CCI Onboard Phase Identify"; + } + case CCI_ONBOARD_PHASE_INIT_COPPER: + { + return "CCI Onboard Phase Init Copper"; + } + case CCI_ONBOARD_PHASE_INIT_DIRECT: + { + return "CCI Onboard Phase Init Direct"; + } + case CCI_ONBOARD_PHASE_INIT_OPTICAL: + { + switch (subphase) + { + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_START: + { + return "CCI Onboard Subphase Init Optical Start"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_CMIS_SELECT_APPLICATION: + { + return "CCI Onboard Subphase Init Optical CMIS Select Application"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_CONFIGURE_LINKS: + { + return "CCI Onboard Subphase Init Optical Configure Links"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_DISABLE_ALI: + { + return "CCI Onboard Subphase Init Optical Disable ALI"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_SETUP: + { + return "CCI Onboard Subphase Init Optical Pretrain Setup"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_SEND_CDB: + { + return "CCI Onboard Subphase Init Optical Pretrain Send CDB"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_POLL: + { + return "CCI Onboard Subphase Init Optical Pretrain Poll"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_GO_TRANSPARENT: + { + return "CCI Onboard Subphase Init Optical Go Transparent"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_RESET_LINKS: + { + return "CCI Onboard Subphase Init Optical Reset Links"; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_ENABLE_ALI: + { + return "CCI Onboard Subphase Init Optical Enable ALI"; + } + default: + { + return "Unknown"; + } + } + } + case CCI_ONBOARD_PHASE_LAUNCH_ALI: + { + return "CCI Onboard Phase Launch ALI"; + } + case CCI_ONBOARD_PHASE_SLEEP: + { + return "CCI Onboard Phase Sleep"; + } + case CCI_ONBOARD_PHASE_MONITOR: + { + return "CCI Onboard Phase Monitor"; + } + default: + { + return "Unknown"; + } + } +} + +static void +_cci_check_module_boot_failure +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + NvU8 fwInfo[CMIS_CDB_LPL_MAX_SIZE]; + NvU8 fwStatusFlags; + NvU8 moduleFlagsCustomByte; + + retval = cciCmisRead(device, moduleId, 0, 0, + CMIS_MODULE_FLAGS_CUSTOM_BYTE, + 1, &moduleFlagsCustomByte); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get module custom flags\n", + __FUNCTION__); + return; + } + + if (REF_NUM(MODULE_FLAGS_CUSTOM_BYTE_BOOT_FAILURE, moduleFlagsCustomByte) || + REF_NUM(MODULE_FLAGS_CUSTOM_BYTE_RECOVERY, moduleFlagsCustomByte)) + { + retval = cciGetXcvrFWInfo(device, moduleId, fwInfo); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_MODULE_BOOT, + "Module %d boot failure\n", moduleId); + } + else + { + fwStatusFlags = fwInfo[CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS]; + + if (REF_VAL(CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS_IMAGE_A_RUNNING, + fwStatusFlags)) + { + // NULL terminate string + fwInfo[CMIS_CDB_GET_FW_INFO_LPL_IMAGE_A_EXTRA_STRING + + CMIS_CDB_GET_FW_INFO_LPL_IMAGE_FACTORY_BOOT_EXTRA_STRING_SIZE - 1] = 0; + + if (REF_NUM(MODULE_FLAGS_CUSTOM_BYTE_BOOT_FAILURE, moduleFlagsCustomByte)) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_MODULE_BOOT, + "Module %d Image A boot failure\n", + moduleId); + } + else + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_MODULE_RECOVERY, + "Module %d Image A recovery failure\n", + moduleId); + } + + NVSWITCH_PRINT(device, ERROR, "%s: Module %d Image A boot/recovery failure. ExtraString: %s\n", + __FUNCTION__, moduleId, + &fwInfo[CMIS_CDB_GET_FW_INFO_LPL_IMAGE_A_EXTRA_STRING]); + } + + if (REF_VAL(CMIS_CDB_GET_FW_INFO_LPL_FW_STATUS_FLAGS_IMAGE_B_RUNNING, + fwStatusFlags)) + { + // NULL terminate string + fwInfo[CMIS_CDB_GET_FW_INFO_LPL_IMAGE_B_EXTRA_STRING + + CMIS_CDB_GET_FW_INFO_LPL_IMAGE_FACTORY_BOOT_EXTRA_STRING_SIZE - 1] = 0; + + if (REF_NUM(MODULE_FLAGS_CUSTOM_BYTE_BOOT_FAILURE, moduleFlagsCustomByte)) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_MODULE_BOOT, + "Module %d Image B boot failure\n", + moduleId); + } + else + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_MODULE_RECOVERY, + "Module %d Image B recovery failure\n", + moduleId); + } + + NVSWITCH_PRINT(device, ERROR, "%s: Module %d Image B boot/recovery failure. ExtraString: %s\n", + __FUNCTION__, moduleId, + &fwInfo[CMIS_CDB_GET_FW_INFO_LPL_IMAGE_B_EXTRA_STRING]); + } + } + } +} + +void +cciModuleOnboardCheckErrors +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + if (pOnboardState->onboardError.bOnboardFailure) + { + if (device->regkeys.cci_error_log_enable) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_MODULE, "Module %d failed %s\n", + moduleId, + _cci_onboard_phase_to_text( + pOnboardState->onboardError.failedOnboardState.onboardPhase, + pOnboardState->onboardError.failedOnboardState.onboardSubPhase.optical)); + } + } + + _cci_check_module_boot_failure(device, moduleId); +} + +NvBool +cciReportLinkErrors +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + NvlStatus retval; + NvU64 mode; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (!cciIsLinkManaged(device, linkNumber)) + { + return NV_TRUE; + } + + retval = cciGetLinkMode(device, linkNumber, &mode); + if (retval != NVL_SUCCESS) + { + return NV_TRUE; + } + + if (mode == NVLINK_LINKSTATE_TRAINING_CCI) + { + return NV_FALSE; + } + else + { + return NV_TRUE; + } +} diff --git a/src/common/nvswitch/kernel/cci/cables/cci_optical.c b/src/common/nvswitch/kernel/cci/cables/cci_optical.c new file mode 100644 index 0000000000..75a273c647 --- /dev/null +++ b/src/common/nvswitch/kernel/cci/cables/cci_optical.c @@ -0,0 +1,930 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "cci/cci_nvswitch.h" +#include "cci/cci_priv_nvswitch.h" +#include "cci/cci_cables_nvswitch.h" + +#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" +#include "nvswitch/ls10/dev_nvldl_ip.h" +#include "ls10/ls10.h" + +static NvlStatus +_cci_cmis_deactivate_lanes +( + nvswitch_device *device, + NvU8 moduleId, + NvU8 deactivateLaneMask +) +{ + NvlStatus retval; + NVSWITCH_TIMEOUT timeout; + NvU64 timeoutMs; + NvU8 dataPathState[4]; + NvU8 byte; + NvU8 laneMaskTemp; + NvU8 laneNum; + NvU8 laneState; + + laneMaskTemp = 0; + + // Deactivate lanes + byte = deactivateLaneMask; + retval = cciCmisWrite(device, moduleId, 0, 0x10, + CMIS_DATA_PATH_CONTROL_BYTE, 1, &byte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Read max timeout value + retval = cciCmisRead(device, moduleId, 0, 0x1, + CMIS_DATA_PATH_MAX_DURATION_BYTE, 1, &byte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + timeoutMs = CMIS_MAX_DURATION_EN_TO_MS_MAP( + REF_VAL(CMIS_DATA_PATH_MAX_DURATION_BYTE_DEINIT, byte)); + NVSWITCH_ASSERT(timeoutMs != 0); + + nvswitch_timeout_create(timeoutMs * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + do + { + // Check if lanes are deactivated + retval = cciCmisRead(device, moduleId, 0, 0x11, + CMIS_DATA_PATH_STATE, CMIS_DATA_PATH_STATE_SIZE, + dataPathState); + if (retval != NVL_SUCCESS) + { + return retval; + } + + laneMaskTemp = 0; + FOR_EACH_INDEX_IN_MASK(8, laneNum, deactivateLaneMask) + { + byte = dataPathState[CMIS_DATA_PATH_STATE_LANE_BYTE_MAP(laneNum)]; + + laneState = (laneNum % 2) ? REF_VAL(CMIS_DATA_PATH_STATE_BYTE_LANE_1, byte) : + REF_VAL(CMIS_DATA_PATH_STATE_BYTE_LANE_0, byte); + + if (laneState == CMIS_DATA_PATH_STATE_LANE_DEACTIVATED) + { + laneMaskTemp |= NVBIT(laneNum); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // Operation successful when all lanes are in expected state + if (laneMaskTemp == deactivateLaneMask) + { + break; + } + + if (nvswitch_timeout_check(&timeout)) + { + return -NVL_ERR_GENERIC; + } + + nvswitch_os_sleep(10); + } while (NV_TRUE); + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_cmis_check_config_errors +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + NVSWITCH_TIMEOUT timeout; + NvU64 timeoutMs; + NvU32 i; + NvU8 errorCodes[4]; + NvU8 byte; + NvBool bLanesAccepted; + + bLanesAccepted = NV_FALSE; + + // Read max timeout value + retval = cciCmisRead(device, moduleId, 0, 0x1, + CMIS_DATA_PATH_MAX_DURATION_BYTE, 1, &byte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + timeoutMs = CMIS_MAX_DURATION_EN_TO_MS_MAP( + REF_VAL(CMIS_DATA_PATH_MAX_DURATION_BYTE_DEINIT, byte)); + NVSWITCH_ASSERT(timeoutMs != 0); + + nvswitch_timeout_create(timeoutMs * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + do + { + // Check for errors in config(applied in deactivated state) + retval = cciCmisRead(device, moduleId, 0, 0x11, + CMIS_DATA_PATH_CONFIG_ERROR_CODES, 4, errorCodes); + if (retval != NVL_SUCCESS) + { + return retval; + } + + if ((*(NvU32*)errorCodes) == CMIS_DATA_PATH_CONFIG_ALL_LANES_ACCEPTED) + { + bLanesAccepted = NV_TRUE; + break; + } + + if (nvswitch_timeout_check(&timeout)) + { + break; + } + + nvswitch_os_sleep(10); + } while (NV_TRUE); + + if (!bLanesAccepted) + { + for (i = 0; i < 4; i++) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Lane %d, error code: 0x%x. Lane %d, error code: 0x%x", + __FUNCTION__, 2*i, (errorCodes[i] & 0xF), 2*i + 1, (errorCodes[i] >> 4)); + } + return -NVL_ERR_GENERIC; + } + + return NVL_SUCCESS; +} + +/* + * Operation is performed on all lanes in the given module + */ +static NvlStatus +_cci_cmis_select_application +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + NvlStatus retval; + NvU32 i; + NvU8 nvl4AppSel[] = {0x20, 0x20, 0x24, 0x24, 0x28, 0x28, 0x2c, 0x2c}; + NvU8 nvl4AppSelTemp[8]; + NvU8 byte; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + // Nothing to do if module already setup + if (pOnboardState->bModuleOnboarded) + { + return NVL_SUCCESS; + } + + // 1. Deactivate all lanes + retval = _cci_cmis_deactivate_lanes(device, moduleId, 0xFF); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module %d: Lanes deactivate failed.\n", + __FUNCTION__, moduleId); + return retval; + } + + // 2. Select application + retval = cciCmisWrite(device, moduleId, 0, 0x10, + CMIS_STAGE_CONTROL_SET_0_APP_SEL, 8, nvl4AppSel); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module %d: Select application failed.\n", + __FUNCTION__, moduleId); + return retval; + } + + // 3. Apply application + byte = 0xFF; + retval = cciCmisWrite(device, moduleId, 0, 0x10, + CMIS_STAGE_CONTROL_SET_0, 1, &byte); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module %d: Apply application failed.\n", + __FUNCTION__, moduleId); + return retval; + } + + // 4. Check for errors + retval = _cci_cmis_check_config_errors(device, moduleId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module %d: Datapath config failed.\n", + __FUNCTION__, moduleId); + return retval; + } + + // 5. Verify that the application selection went through + retval = cciCmisRead(device, moduleId, 0, 0x11, + CMIS_ACTIVE_CONTROL_SET, 8, nvl4AppSelTemp); + if (retval != NVL_SUCCESS) + { + return retval; + } + + for (i = 0; i < 8; i++) + { + if (nvl4AppSelTemp[i] != nvl4AppSel[i]) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module %d: Application selection failed.\n", + __FUNCTION__, moduleId); + return -NVL_ERR_GENERIC; + } + } + + // 6. De-assert lpmode + retval = cciSetLPMode(device, moduleId, NV_FALSE); + if (retval != NVL_SUCCESS) + { + return retval; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_disable_ALI +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + + // Have SOE perform this phase + retval = cciModulesOnboardSOE(device, moduleId); + if (retval != NVL_SUCCESS) + { + return retval; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_enable_ALI +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + + // Have SOE perform this phase + retval = cciModulesOnboardSOE(device, moduleId); + if (retval != NVL_SUCCESS) + { + return retval; + } + + return NVL_SUCCESS; +} + + +static NvlStatus +_cci_configure_links +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + + // Have SOE perform this phase + retval = cciModulesOnboardSOE(device, moduleId); + if (retval != NVL_SUCCESS) + { + return retval; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_pretrain_setup +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + NvlStatus retval; + NvU64 linkTrainMask; + NvU32 linkId; + NvU8 laneMask; + NvU8 byte; + + retval = cciSetLedsInitialize(device, moduleId); + if (retval != NVL_SUCCESS) + { + return retval; + } + + pOnboardState = &device->pCci->moduleState[moduleId]; + + linkTrainMask = pOnboardState->linkTrainMask; + + // Train links to enable IOBIST + FOR_EACH_INDEX_IN_MASK(64, linkId, linkTrainMask) + { + retval = cciGetLaneMask(device, linkId, &laneMask); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = _cci_cmis_deactivate_lanes(device, moduleId, laneMask); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = nvswitch_cci_initialization_sequence_ls10(device, linkId); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = nvswitch_cci_enable_iobist_ls10(device, linkId, NV_TRUE); + if (retval != NVL_SUCCESS) + { + return retval; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // Activate lanes + byte = 0; + retval = cciCmisWrite(device, moduleId, 0, 0x10, + CMIS_DATA_PATH_CONTROL_BYTE, 1, &byte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_pretrain_send_cdb +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + NvlStatus retval; + NvU64 linkTrainMask; + NvBool freeze_maintenance; + NvBool restart_training; + NvBool nvlink_mode; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + linkTrainMask = pOnboardState->linkTrainMask; + freeze_maintenance = NV_TRUE; + restart_training = NV_TRUE; + nvlink_mode = NV_TRUE; + + retval = cciConfigureNvlinkModeModule(device, NVSWITCH_I2C_ACQUIRER_CCI_TRAIN, + moduleId, linkTrainMask, + freeze_maintenance, restart_training, nvlink_mode); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Pre-train CMD to module failed.\n", + __FUNCTION__); + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_go_transparant +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + NvlStatus retval; + NvU64 linkTrainMask; + NvBool freeze_maintenance; + NvBool restart_training; + NvBool nvlink_mode; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + linkTrainMask = pOnboardState->linkTrainMask; + freeze_maintenance = NV_TRUE; + restart_training = NV_FALSE; + nvlink_mode = NV_TRUE; + + retval = cciConfigureNvlinkModeModule(device, NVSWITCH_I2C_ACQUIRER_CCI_TRAIN, + moduleId, linkTrainMask, + freeze_maintenance, restart_training, nvlink_mode); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to go transparent on links on module: %d\n", + __FUNCTION__, moduleId); + return retval; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_reset_links +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + NvlStatus retval; + nvlink_link *link; + NvU64 linkTrainMask; + NvU32 linkId; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + linkTrainMask = pOnboardState->linkTrainMask; + + FOR_EACH_INDEX_IN_MASK(64, linkId, linkTrainMask) + { + link = nvswitch_get_link(device, linkId); + + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID(device, link->linkNumber, NVLIPT_LNK) || + (linkId >= NVSWITCH_NVLINK_MAX_LINKS)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get link: %d\n", + __FUNCTION__, linkId); + return -NVL_ERR_GENERIC; + } + + if (nvswitch_is_link_in_reset(device, link)) + { + continue; + } + + retval = nvswitch_cci_deinitialization_sequence_ls10(device, linkId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: nvswitch_cci_deinitialization_sequence_ls10 failed for link: %d\n", + __FUNCTION__, linkId); + return -NVL_ERR_GENERIC; + } + + // Disable IOBIST + retval = nvswitch_cci_enable_iobist_ls10(device, linkId, NV_FALSE); + if (retval != NVL_SUCCESS) + { + return -NVL_ERR_GENERIC; + } + + // Shutdown link + retval = nvswitch_request_tl_link_state_ls10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN, + NV_TRUE); + + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link shutdown request failed for link: %d\n", + __FUNCTION__, linkId); + return -NVL_ERR_GENERIC; + } + + // Reset link + retval = nvswitch_request_tl_link_state_ls10(link, + NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, + NV_TRUE); + + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: TL link reset request failed for link: %d\n", + __FUNCTION__, linkId); + return -NVL_ERR_GENERIC; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + +static void +_cci_init_optical_start_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextStateSuccess; + CCI_MODULE_ONBOARD_STATE nextStateFail; + + nvswitch_os_memset(&nextStateSuccess, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nvswitch_os_memset(&nextStateFail, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + nextStateSuccess.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + nextStateSuccess.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_CMIS_SELECT_APPLICATION; + nextStateFail.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseAsync(device, moduleId, + _cci_reset_links, + nextStateSuccess, + nextStateFail); +} + +static void +_cci_cmis_select_application_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextStateSuccess; + CCI_MODULE_ONBOARD_STATE nextStateFail; + + nvswitch_os_memset(&nextStateSuccess, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nvswitch_os_memset(&nextStateFail, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + nextStateSuccess.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + nextStateSuccess.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_CONFIGURE_LINKS; + nextStateFail.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseAsync(device, moduleId, + _cci_cmis_select_application, + nextStateSuccess, + nextStateFail); +} + +static void +_cci_configure_links_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextStateSuccess; + CCI_MODULE_ONBOARD_STATE nextStateFail; + + nvswitch_os_memset(&nextStateSuccess, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nvswitch_os_memset(&nextStateFail, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + nextStateSuccess.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + nextStateSuccess.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_DISABLE_ALI; + nextStateFail.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseAsync(device, moduleId, + _cci_configure_links, + nextStateSuccess, + nextStateFail); +} + +static void +_cci_disable_ALI_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextStateSuccess; + CCI_MODULE_ONBOARD_STATE nextStateFail; + + nvswitch_os_memset(&nextStateSuccess, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nvswitch_os_memset(&nextStateFail, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + nextStateSuccess.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + nextStateSuccess.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_SETUP; + nextStateFail.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseAsync(device, moduleId, + _cci_disable_ALI, + nextStateSuccess, + nextStateFail); +} + +static void +_cci_pretrain_setup_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextStateSuccess; + CCI_MODULE_ONBOARD_STATE nextStateFail; + + nvswitch_os_memset(&nextStateSuccess, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nvswitch_os_memset(&nextStateFail, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + nextStateSuccess.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + nextStateSuccess.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_SEND_CDB; + nextStateFail.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseAsync(device, moduleId, + _cci_pretrain_setup, + nextStateSuccess, + nextStateFail); +} + +static void +_cci_pretrain_send_cdb_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextStateSuccess; + CCI_MODULE_ONBOARD_STATE nextStateFail; + + nvswitch_os_memset(&nextStateSuccess, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nvswitch_os_memset(&nextStateFail, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + nextStateSuccess.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + nextStateSuccess.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_POLL; + nextStateFail.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseAsync(device, moduleId, + _cci_pretrain_send_cdb, + nextStateSuccess, + nextStateFail); +} + +static void +_cci_pretrain_poll_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + CCI_MODULE_ONBOARD_STATE nextState; + NvU64 linkTrainMaskDone; + NvU32 linkId; + NvBool bTx; + NvBool bPreTrainDone; + + pOnboardState = &device->pCci->moduleState[moduleId]; + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + linkTrainMaskDone = 0; + FOR_EACH_INDEX_IN_MASK(64, linkId, pOnboardState->linkTrainMask) + { + bTx = NV_TRUE; + bPreTrainDone = cciCheckForPreTraining(device, + NVSWITCH_I2C_ACQUIRER_CCI_TRAIN, linkId, bTx); + if (!bPreTrainDone) + { + continue; + } + + bTx = NV_FALSE; + bPreTrainDone = cciCheckForPreTraining(device, + NVSWITCH_I2C_ACQUIRER_CCI_TRAIN, linkId, bTx); + if (!bPreTrainDone) + { + continue; + } + + linkTrainMaskDone |= NVBIT64(linkId); + } + FOR_EACH_INDEX_IN_MASK_END; + + // + // Allow link training to proceed + // to prevent possible deadlock + // + if (linkTrainMaskDone) + { + pOnboardState->bPartialLinkTrainComplete = NV_TRUE; + pOnboardState->preTrainCounter++; + + // Train remaining links on next attempts + if (pOnboardState->preTrainCounter == CCI_ONBOARD_PHASE_POLL_MAX) + { + if (pOnboardState->linkTrainMask != linkTrainMaskDone) + { + pOnboardState->bLinkTrainDeferred = NV_TRUE; + } + pOnboardState->linkTrainMask = linkTrainMaskDone; + pOnboardState->preTrainCounter = 0; + } + } + + nextState.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + if (linkTrainMaskDone == pOnboardState->linkTrainMask) + { + nextState.onboardSubPhase.optical = + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_GO_TRANSPARENT; + } + else + { + // Stay in poll phase until pre-training complete + nextState.onboardSubPhase.optical = + CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_POLL; + } + + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); +} + +static void +_cci_go_transparant_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + CCI_MODULE_ONBOARD_STATE nextState; + CCI_MODULE_STATE *pOnboardState; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + retval = _cci_go_transparant(device, moduleId); + if (retval == NVL_SUCCESS) + { + // Move to next phase after sleep + nextState.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + nextState.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_RESET_LINKS; + cciModuleOnboardSleepAsync(device, moduleId, 10000, nextState); + } + else + { + pOnboardState->onboardError.bOnboardFailure = NV_TRUE; + pOnboardState->onboardError.failedOnboardState = pOnboardState->currOnboardState; + nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); + } +} + +static void +_cci_reset_links_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + CCI_MODULE_ONBOARD_STATE nextState; + CCI_MODULE_STATE *pOnboardState; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + retval = _cci_reset_links(device, moduleId); + if (retval == NVL_SUCCESS) + { + // Move to next phase after sleep + nextState.onboardPhase = CCI_ONBOARD_PHASE_INIT_OPTICAL; + nextState.onboardSubPhase.optical = CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_ENABLE_ALI; + cciModuleOnboardSleepAsync(device, moduleId, 10000, nextState); + } + else + { + pOnboardState->onboardError.bOnboardFailure = NV_TRUE; + pOnboardState->onboardError.failedOnboardState = pOnboardState->currOnboardState; + nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseTransitionAsync(device, moduleId, nextState); + } +} + +static void +_cci_enable_ALI_async +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_ONBOARD_STATE nextStateSuccess; + CCI_MODULE_ONBOARD_STATE nextStateFail; + + nvswitch_os_memset(&nextStateSuccess, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + nvswitch_os_memset(&nextStateFail, 0, sizeof(CCI_MODULE_ONBOARD_STATE)); + + nextStateSuccess.onboardPhase = CCI_ONBOARD_PHASE_LAUNCH_ALI; + nextStateFail.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION; + cciModuleOnboardPerformPhaseAsync(device, moduleId, + _cci_enable_ALI, + nextStateSuccess, + nextStateFail); +} + +/* + * @brief Initialize optical cables asynchronously + * + * @param[in] device nvswitch_device pointer + * @param[in] moduleId Module will be initialized. + * + */ +void +cciCablesInitializeOpticalAsync +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_MODULE_STATE *pOnboardState; + + pOnboardState = &device->pCci->moduleState[moduleId]; + + NVSWITCH_ASSERT(pOnboardState->currOnboardState.onboardPhase == CCI_ONBOARD_PHASE_INIT_OPTICAL); + + switch (pOnboardState->currOnboardState.onboardSubPhase.optical) + { + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_START: + { + _cci_init_optical_start_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_CMIS_SELECT_APPLICATION: + { + _cci_cmis_select_application_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_CONFIGURE_LINKS: + { + _cci_configure_links_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_DISABLE_ALI: + { + _cci_disable_ALI_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_SETUP: + { + _cci_pretrain_setup_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_SEND_CDB: + { + _cci_pretrain_send_cdb_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_PRETRAIN_POLL: + { + _cci_pretrain_poll_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_GO_TRANSPARENT: + { + _cci_go_transparant_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_RESET_LINKS: + { + _cci_reset_links_async(device, moduleId); + break; + } + case CCI_ONBOARD_SUBPHASE_INIT_OPTICAL_ENABLE_ALI: + { + _cci_enable_ALI_async(device, moduleId); + break; + } + default: + { + break; + } + } +} diff --git a/src/common/nvswitch/kernel/cci/cci_cdb_async_nvswitch.c b/src/common/nvswitch/kernel/cci/cci_cdb_async_nvswitch.c new file mode 100644 index 0000000000..88fbbbff98 --- /dev/null +++ b/src/common/nvswitch/kernel/cci/cci_cdb_async_nvswitch.c @@ -0,0 +1,475 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "cci/cci_nvswitch.h" +#include "cci/cci_priv_nvswitch.h" + +/*! + * @brief Checks for CDB command completion. + * + * Page 00h byte 37 contains status bits. BIT 7 is the busy bit. + * (see CMIS rev4.0, Table 9-3, CDB Command 0000h: QUERY-Status) + */ +static NvlStatus +_cci_check_for_cdb_complete +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp +) +{ + NvU8 status; + + cciRead(device, client, osfp, CMIS_CDB_BLOCK_STATUS_BYTE(0), 1, &status); + + // Return when the STS_BUSY bit goes to 0 + if (FLD_TEST_REF(CMIS_CDB_BLOCK_STATUS_BYTE_BUSY, _FALSE, status)) + { + return NVL_SUCCESS; + } + + return NVL_ERR_STATE_IN_USE; +} + +/*! + * @brief Check if module can recieve CDB command + */ +static NvlStatus +_cci_check_cdb_ready +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_CDB_STATE *pCdbState; + NvlStatus retval; + + pCdbState = &device->pCci->cdbState[moduleId]; + + if (pCdbState->cdbPhase != CCI_CDB_PHASE_CHECK_READY) + { + return -NVL_ERR_GENERIC; + } + + if (!cciModulePresent(device, moduleId)) + { + NVSWITCH_PRINT(device, INFO, + "%s: osfp %d is missing\n", + __FUNCTION__, moduleId); + return -NVL_NOT_FOUND; + } + + retval = _cci_check_for_cdb_complete(device, pCdbState->client, moduleId); + if (retval != NVL_SUCCESS) + { + return retval; + } + + pCdbState->cdbPhase = CCI_CDB_PHASE_SEND_COMMAND; + + return NVL_SUCCESS; +} + +/*! + * @brief Send CDB command + */ +static NvlStatus +_cci_send_cdb_command +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + CCI_CDB_STATE *pCdbState; + NvU8 payload[CMIS_CDB_LPL_MAX_SIZE]; + NvU32 payLength; + NvU32 command; + NvBool padding; + NvU8 laneMask; + + pCdbState = &device->pCci->cdbState[moduleId]; + + if (pCdbState->cdbPhase != CCI_CDB_PHASE_SEND_COMMAND) + { + return -NVL_ERR_GENERIC; + } + + if (!cciModulePresent(device, moduleId)) + { + NVSWITCH_PRINT(device, INFO, + "%s: osfp %d is missing\n", + __FUNCTION__, moduleId); + return -NVL_NOT_FOUND; + } + + // Roll up lanes that will be operated on + laneMask = pCdbState->laneMasksPending[0] | + pCdbState->laneMasksPending[1] | + pCdbState->laneMasksPending[2] | + pCdbState->laneMasksPending[3]; + + // Clear lanes whose commands will be triggered + pCdbState->laneMasksPending[0] &= ~laneMask; + pCdbState->laneMasksPending[1] &= ~laneMask; + pCdbState->laneMasksPending[2] &= ~laneMask; + pCdbState->laneMasksPending[3] &= ~laneMask; + + payload[0] = 0; + payload[1] = (pCdbState->freeze_maintenance << 4) + + (pCdbState->restart_training << 1) + + pCdbState->nvlink_mode; + payload[2] = 0; + + // Tx + payload[3] = laneMask; + payload[4] = 0; + + // Rx + payload[5] = laneMask; + + payLength = 6; + command = NVSWITCH_CCI_CDB_CMD_ID; + padding = NV_FALSE; + + retval = cciSendCDBCommand(device, pCdbState->client, moduleId, command, payLength, payload, padding); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, + "%s: Failed to send CDB Command: 0x%x\n", + __FUNCTION__, command); + return -NVL_ERR_GENERIC; + } + + pCdbState->cdbPhase = CCI_CDB_PHASE_GET_RESPONSE; + + return NVL_SUCCESS; +} + +/*! + * @brief Get get CDB response. + */ +static NvlStatus +_cci_get_cdb_response +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + CCI_CDB_STATE *pCdbState; + NvU8 cdbStatus = 0; + NvU8 response[CMIS_CDB_LPL_MAX_SIZE]; + NvU32 resLength; + + pCdbState = &device->pCci->cdbState[moduleId]; + + if (pCdbState->cdbPhase != CCI_CDB_PHASE_GET_RESPONSE) + { + return -NVL_ERR_GENERIC; + } + + if (!cciModulePresent(device, moduleId)) + { + NVSWITCH_PRINT(device, INFO, + "%s: osfp %d is missing\n", + __FUNCTION__, moduleId); + return -NVL_NOT_FOUND; + } + + retval = _cci_check_for_cdb_complete(device, pCdbState->client, moduleId); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = cciGetCDBStatus(device, pCdbState->client, moduleId, &cdbStatus); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB command failed! result = 0x%x\n", + __FUNCTION__, cdbStatus); + return -NVL_ERR_GENERIC; + } + + retval = cciGetCDBResponse(device, pCdbState->client, moduleId, response, &resLength); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get CDB command response\n", + __FUNCTION__); + return -NVL_ERR_GENERIC; + } + + pCdbState->cdbPhase = CCI_CDB_PHASE_CHECK_DONE; + + return NVL_SUCCESS; +} + +/*! + * @brief + */ +static NvlStatus +_cci_check_cdb_done +( + nvswitch_device *device, + NvU8 moduleId +) +{ + CCI_CDB_STATE *pCdbState; + + pCdbState = &device->pCci->cdbState[moduleId]; + + if (pCdbState->cdbPhase != CCI_CDB_PHASE_CHECK_DONE) + { + return -NVL_ERR_GENERIC; + } + + // Finish pending links + if (pCdbState->laneMasksPending[0] || + pCdbState->laneMasksPending[1] || + pCdbState->laneMasksPending[2] || + pCdbState->laneMasksPending[3]) + { + pCdbState->cdbPhase = CCI_CDB_PHASE_CHECK_READY; + } + else + { + pCdbState->cdbPhase = CCI_CDB_PHASE_IDLE; + } + + return NVL_SUCCESS; +} + +/* + * @brief Performs CDB stages on a module without blocking + * + */ +static void +_cci_cdb_perform_phases +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NVSWITCH_TIMEOUT timeout; + NvlStatus retval = NVL_SUCCESS; + NvBool bContinue = NV_TRUE; + CCI_CDB_STATE *pCdbState; + + pCdbState = &device->pCci->cdbState[moduleId]; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + + do + { + switch (pCdbState->cdbPhase) + { + case CCI_CDB_PHASE_CHECK_READY: + { + retval = _cci_check_cdb_ready(device, moduleId); + break; + } + case CCI_CDB_PHASE_SEND_COMMAND: + { + retval = _cci_send_cdb_command(device, moduleId); + break; + } + case CCI_CDB_PHASE_GET_RESPONSE: + { + retval = _cci_get_cdb_response(device, moduleId); + break; + } + case CCI_CDB_PHASE_CHECK_DONE: + { + retval = _cci_check_cdb_done(device, moduleId); + break; + } + default: + { + retval = NVL_SUCCESS; + bContinue = NV_FALSE; + NVSWITCH_ASSERT(pCdbState->cdbPhase == CCI_CDB_PHASE_IDLE); + break; + } + } + + // Module is busy + if (retval == NVL_ERR_STATE_IN_USE) + { + // Nothing more to do for now + bContinue = NV_FALSE; + } + + if (retval < 0) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB error module %d, phase %d!\n", + __FUNCTION__, moduleId, pCdbState->cdbPhase); + bContinue = NV_FALSE; + pCdbState->cdbPhase = CCI_CDB_PHASE_CHECK_DONE; + } + + // Just in case + if (nvswitch_timeout_check(&timeout)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Timeout!\n", + __FUNCTION__); + break; + } + } while(bContinue); +} + +void +cciProcessCDBCallback +( + nvswitch_device *device +) +{ + NVSWITCH_TIMEOUT timeout; + NvU32 moduleMaskPriority; + NvU32 moduleMask; + NvU8 moduleId; + + moduleMaskPriority = 0; + + nvswitch_timeout_create(20 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + // Attempt to complete CDB commands for present modules + if (cciGetXcvrMask(device, &moduleMask, NULL) == NVL_SUCCESS) + { + FOR_EACH_INDEX_IN_MASK(32, moduleId, moduleMask) + { + // + // Prioritize sending CDB commands. + // This also prioritizes getting responses for CDBs in the event that + // fewer than all lanes of a module were operated on. + // + if (device->pCci->cdbState[moduleId].laneMasksPending[0] || + device->pCci->cdbState[moduleId].laneMasksPending[1] || + device->pCci->cdbState[moduleId].laneMasksPending[2] || + device->pCci->cdbState[moduleId].laneMasksPending[3]) + { + moduleMaskPriority |= NVBIT32(moduleId); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + FOR_EACH_INDEX_IN_MASK(32, moduleId, moduleMaskPriority) + { + _cci_cdb_perform_phases(device, moduleId); + } + FOR_EACH_INDEX_IN_MASK_END; + + FOR_EACH_INDEX_IN_MASK(32, moduleId, moduleMask) + { + _cci_cdb_perform_phases(device, moduleId); + + // Short circuit getting non time sensistive responses + if (nvswitch_timeout_check(&timeout)) + { + break; + } + } + FOR_EACH_INDEX_IN_MASK_END; + } +} + +NvlStatus +cciConfigureNvlinkModeAsync +( + nvswitch_device *device, + NvU32 client, + NvU8 linkId, + NvBool freeze_maintenance, + NvBool restart_training, + NvBool nvlink_mode +) +{ + NvlStatus retval; + CCI_CDB_STATE *pCdbState; + NvU32 moduleId; + NvU8 laneMask; + NvU8 laneMasksIndex; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + retval = cciGetModuleId(device, linkId, &moduleId); + if (retval != NVL_SUCCESS) + { + return retval; + } + + if (!cciModulePresent(device, moduleId)) + { + return -NVL_NOT_FOUND; + } + + if (cciGetLaneMask(device, linkId, &laneMask) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get osfp lanemask associated with link %d\n", + __FUNCTION__, linkId); + return -NVL_ERR_NOT_SUPPORTED; + } + + pCdbState = &device->pCci->cdbState[moduleId]; + + // Add to first available slot + for (laneMasksIndex = 0; laneMasksIndex < NVSWITCH_CCI_NUM_LINKS_PER_OSFP_LS10; laneMasksIndex++) + { + if (pCdbState->laneMasksPending[laneMasksIndex] == 0) + { + pCdbState->laneMasksPending[laneMasksIndex] = laneMask; + break; + } + } + + if (pCdbState->cdbPhase != CCI_CDB_PHASE_IDLE) + { + // Don't support queuing multiple CDB command types + NVSWITCH_ASSERT(pCdbState->client == client); + NVSWITCH_ASSERT(pCdbState->freeze_maintenance == freeze_maintenance); + NVSWITCH_ASSERT(pCdbState->restart_training == restart_training); + NVSWITCH_ASSERT(pCdbState->nvlink_mode == nvlink_mode); + + return NVL_SUCCESS; + } + + // Setup cdbstate for callback + pCdbState->client = client; + pCdbState->freeze_maintenance = freeze_maintenance; + pCdbState->restart_training = restart_training; + pCdbState->nvlink_mode = nvlink_mode; + pCdbState->cdbPhase = CCI_CDB_PHASE_CHECK_READY; + + return NVL_SUCCESS; +} diff --git a/src/common/nvswitch/kernel/cci/cci_nvswitch.c b/src/common/nvswitch/kernel/cci/cci_nvswitch.c new file mode 100644 index 0000000000..b8fbe018c4 --- /dev/null +++ b/src/common/nvswitch/kernel/cci/cci_nvswitch.c @@ -0,0 +1,3059 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "cci/cci_priv_nvswitch.h" + +/* -------------------- Object construction/initialization ------------------- */ + +NvBool +nvswitch_is_cci_supported +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_is_cci_supported(device); +} + +NvlStatus +nvswitch_cci_discovery +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_cci_discovery(device); +} + +void +nvswitch_cci_setup_gpio_pins +( + nvswitch_device *device +) +{ + device->hal.nvswitch_cci_setup_gpio_pins(device); +} + +NvlStatus +nvswitch_cci_ports_cpld_read +( + nvswitch_device *device, + NvU8 reg, + NvU8 *pData +) +{ + return device->hal.nvswitch_cci_ports_cpld_read(device, reg, pData); +} + +NvlStatus +nvswitch_cci_ports_cpld_write +( + nvswitch_device *device, + NvU8 reg, + NvU8 data +) +{ + return device->hal.nvswitch_cci_ports_cpld_write(device, reg, data); +} + +NvlStatus +nvswitch_cci_reset +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_cci_reset(device); +} + +NvlStatus +nvswitch_cci_reset_links +( + nvswitch_device *device, + NvU64 linkMask +) +{ + return device->hal.nvswitch_cci_reset_links(device, linkMask); +} + +void +nvswitch_cci_get_xcvrs_present +( + nvswitch_device *device, + NvU32 *pMaskPresent +) +{ + device->hal.nvswitch_cci_get_xcvrs_present(device, pMaskPresent); +} + +void +nvswitch_cci_get_xcvrs_present_change +( + nvswitch_device *device, + NvU32 *pMaskPresentChange +) +{ + device->hal.nvswitch_cci_get_xcvrs_present_change(device, pMaskPresentChange); +} + +void +nvswitch_cci_update_link_state_led +( + nvswitch_device *device +) +{ + device->hal.nvswitch_cci_update_link_state_led(device); +} + +NvlStatus +nvswitch_cci_set_xcvr_led_state +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvBool bSetLocate +) +{ + return device->hal.nvswitch_cci_set_xcvr_led_state(device, client, osfp, bSetLocate); +} + +NvlStatus +nvswitch_cci_get_xcvr_led_state +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 *pLedState +) +{ + return device->hal.nvswitch_cci_get_xcvr_led_state(device, client, osfp, pLedState); +} + +NvlStatus +nvswitch_cci_setup_onboard +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_cci_setup_onboard(device); +} + +NvlStatus +nvswitch_cci_setup_module_path +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp +) +{ + return device->hal.nvswitch_cci_setup_module_path(device, client, osfp); +} + +NvlStatus +nvswitch_cci_module_access_cmd +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU32 addr, + NvU32 length, + NvU8 *pValArray, + NvBool bRead, + NvBool bBlk +) +{ + return device->hal.nvswitch_cci_module_access_cmd(device, client, osfp, addr, length, + pValArray, bRead, bBlk); +} + +NvlStatus +nvswitch_cci_apply_control_set_values +( + nvswitch_device *device, + NvU32 client, + NvU32 moduleMask +) +{ + return device->hal.nvswitch_cci_apply_control_set_values(device, client, moduleMask); +} + +NvlStatus +nvswitch_cci_cmis_cage_bezel_marking +( + nvswitch_device *device, + NvU8 cageIndex, + char *pBezelMarking +) +{ + return device->hal.nvswitch_cci_cmis_cage_bezel_marking(device, cageIndex, pBezelMarking); +} + +NvlStatus +nvswitch_cci_get_grading_values +( + nvswitch_device *device, + NvU32 client, + NvU32 linkId, + NvU8 *laneMask, + NVSWITCH_CCI_GRADING_VALUES *pGrading +) +{ + return device->hal.nvswitch_cci_get_grading_values(device, client, linkId, laneMask, pGrading); +} + +NvlStatus +nvswitch_cci_get_xcvr_mask +( + nvswitch_device *device, + NvU32 *pMaskAll, + NvU32 *pMaskPresent +) +{ + return device->hal.nvswitch_cci_get_xcvr_mask(device, pMaskAll, pMaskPresent); +} + +void +nvswitch_cci_set_xcvr_present +( + nvswitch_device *device, + NvU32 maskPresent +) +{ + device->hal.nvswitch_cci_set_xcvr_present(device, maskPresent); +} + +void +nvswitch_cci_destroy +( + nvswitch_device *device +) +{ + device->hal.nvswitch_cci_destroy(device); +} + +NvBool +cciSupported +( + nvswitch_device *device +) +{ + PCCI pCci = device->pCci; + NvlStatus retval; + + if (pCci == NULL) + { + return NV_FALSE; + } + + if (pCci->bDiscovered) + { + return pCci->bSupported; + } + + // Discover if CCI supported board + retval = nvswitch_cci_discovery(device); + if (retval == NVL_SUCCESS) + { + pCci->bSupported = NV_TRUE; + } + else + { + pCci->bSupported = NV_FALSE; + } + + pCci->bDiscovered = NV_TRUE; + + return pCci->bSupported; +} + +CCI * +cciAllocNew(void) +{ + CCI *pCci = nvswitch_os_malloc(sizeof(*pCci)); + if (pCci != NULL) + { + nvswitch_os_memset(pCci, 0, sizeof(*pCci)); + } + + return pCci; +} + +static void +_nvswitch_cci_poll_callback +( + nvswitch_device *device +) +{ + PCCI pCci = device->pCci; + NvU32 i; + + // call all functions at specified frequencies + for (i = 0; i < NVSWITCH_CCI_CALLBACK_NUM_MAX; i++) + { + if ((pCci->callbackList[i].functionPtr != NULL) && + ((pCci->callbackCounter % pCci->callbackList[i].interval) == 0)) + { + pCci->callbackList[i].functionPtr(device); + } + } + pCci->callbackCounter++; +} + +NvlStatus +cciInit +( + nvswitch_device *device, + CCI *pCci, + NvU32 pci_device_id +) +{ + nvswitch_task_create(device, _nvswitch_cci_poll_callback, + NVSWITCH_INTERVAL_1SEC_IN_NS / NVSWITCH_CCI_POLLING_RATE_HZ, + 0); + return NVL_SUCCESS; +} + +// reverse of cciInit() +void +cciDestroy +( + nvswitch_device *device, + CCI *pCci +) +{ + nvswitch_cci_destroy(device); +} + +static NvBool +_nvswitch_cci_module_present +( + nvswitch_device *device, + NvU32 osfp +) +{ + return !!(device->pCci->osfpMaskPresent & NVBIT(osfp)); +} + +static NvlStatus +_nvswitch_cci_get_module_id +( + nvswitch_device *device, + NvU32 linkId, + NvU32 *osfp +) +{ + PCCI pCci = device->pCci; + NvU32 i; + + for (i = 0; i < pCci->osfp_map_size; i++) + { + if (pCci->osfp_map[i].linkId == linkId) + { + *osfp = pCci->osfp_map[i].moduleId; + + if (!(device->pCci->cagesMask & NVBIT(*osfp))) + { + NVSWITCH_PRINT(device, ERROR, + "%s: osfp %d associated with link %d is not supported\n", + __FUNCTION__, linkId, *osfp); + return -NVL_NOT_FOUND; + } + + return NVL_SUCCESS; + } + } + + return -NVL_NOT_FOUND; +} + +NvlStatus +cciWrite +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU32 addr, + NvU32 length, + NvU8 *pVal +) +{ + NvlStatus status = NVL_SUCCESS; + NvBool bRead = NV_FALSE; + NvBool bBlk = NV_FALSE; + + if (!pVal) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Bad Args!\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if (!device->pCci->bInitialized) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI is not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (!cciModulePresent(device, osfp)) + { + return -NVL_NOT_FOUND; + } + + status = nvswitch_cci_setup_module_path(device, client, osfp); + if (status != NVL_SUCCESS) + { + return status; + } + + status = nvswitch_cci_module_access_cmd(device, client, osfp, addr, + length, pVal, bRead, bBlk); + if (status != NVL_SUCCESS) + { + return status; + } + + return NVL_SUCCESS; +} + +NvlStatus +cciRead +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU32 addr, + NvU32 length, + NvU8 *pVal +) +{ + NvlStatus status = NVL_SUCCESS; + NvBool bRead = NV_TRUE; + NvBool bBlk = NV_FALSE; + + if (!pVal) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Bad Args!\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if (!device->pCci->bInitialized) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI is not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (!cciModulePresent(device, osfp)) + { + return -NVL_NOT_FOUND; + } + + status = nvswitch_cci_setup_module_path(device, client, osfp); + if (status != NVL_SUCCESS) + { + return status; + } + + status = nvswitch_cci_module_access_cmd(device, client, osfp, addr, + length, pVal, bRead, bBlk); + if (status != NVL_SUCCESS) + { + return status; + } + + return NVL_SUCCESS; +} + +/* + * @brief Set bank an page in the CMIS memory table. + * + * CMIS4 states, "For a bank change, the host shall write the Bank Select + * and Page Select registers in the same TWI transaction". + * + * Write to Page 0h, byte 126 sets the bank and page. + */ +NvlStatus +cciSetBankAndPage +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 bank, + NvU8 page +) +{ + NvU8 temp[2]; + + // Modules with flat memory will fail setting of page and bank + if (device->pCci->isFlatMemory[osfp]) + { + if ((page > 0x0) || (bank > 0x0)) + { + return -NVL_BAD_ARGS; + } + return NVL_SUCCESS; + } + + temp[0] = bank; + temp[1] = page; + + return cciWrite(device, client, osfp, 126, 2, temp); +} + +/* + * @brief Gets the current bank and page in the CMIS memory table. + * + * Read from Page 0h, byte 126 to get the bank and page. + */ +NvlStatus +cciGetBankAndPage +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 *pBank, + NvU8 *pPage +) +{ + NvlStatus status; + NvU8 temp[2] = {0}; + + status = cciRead(device, client, osfp, 126, 2, temp); + + if (pBank != NULL) + { + *pBank = temp[0]; + } + + if (pPage != NULL) + { + *pPage = temp[1]; + } + + return status; +} + +#define NVSWITCH_CCI_MAX_CDB_LENGTH 128 + +/* + * @brief Send commands for Command Data Block(CDB) communication. + * + * CDB reads and writes are performed on memory map pages 9Fh-AFh. + * + * Page 9Fh is used to specify the CDB command and use + * local payload (LPL) of 120 bytes. + * + * Pages A0h-AFh contain up to 2048 bytes of extended payload (EPL). + * + * Payload may be a zero-length array if no payload to send. + * + * (ref CMIS rev4.0, sections 7.2, 8.13, 8.2.7, 8.4.11). + */ +NvlStatus +cciSendCDBCommand +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU32 command, + NvU32 length, + NvU8 *payload, + NvBool padding +) +{ + NvU8 cmd_msb = (command >> 8) & 0xff; + NvU8 cmd_lsb = command & 0xff; + NvU32 chkcode; + NvU32 i; + NvU8 temp[8]; + + if (length > NVSWITCH_CCI_MAX_CDB_LENGTH) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Command length %d exceeded max length %d. " + "CDB yet to support extended payloads\n", + __FUNCTION__, length, NVSWITCH_CCI_MAX_CDB_LENGTH); + return -NVL_ERR_GENERIC; + } + + // + // Compute checksum over payload, including header bytes(command, length,...) + // + // CdbChkCode is the ones complement of the summation of page 9Fh, + // bytes 128 to (135+LPL_Length) with bytes 133,134 and 135 equal to 0. + // (ref CMIS 4.0, sec 8.13) + // + chkcode = cmd_msb + cmd_lsb + length; + + // now add payload bytes + if (length > 0) + { + for (i = 0; i < length; i++) + { + chkcode += payload[i]; + } + } + chkcode = (~(chkcode & 0xff)) & 0xff; + + // # nw: page 198 of cmis4 spec. + // # nw: + + // Set page to 0x9F to setup CDB command + cciSetBankAndPage(device, client, osfp, 0, 0x9f); + + // + // Send CDB message + // + // Fill page 9Fh bytes 128-135 in the order - + // [cmd_msb, cmd_lsb, epl_length msb, epl_length lsb, lpl_length, + // chkcode, resp_length = 0, resp_chkcode = 0] + // + // LPL starts from Bytes 136 upto 120 bytes. + // The command is triggered when byte 129 is written. So fill bytes 128, 129 at the end. + // + + // #1. Write bytes 130-135. The "header portion", minus the first two bytes + // which is the command code. + temp[0] = 0; // epl_length msb + temp[1] = 0; // epl_length lsb + temp[2] = length; // lpl_length + temp[3] = chkcode; // cdb chkcode + temp[4] = 0; // response length + temp[5] = 0; // response chkcode + cciWrite(device, client, osfp, 130, 6, temp); + + // #2. If payload's not empty, write the payload (bytes 136 to 255). + // If payload is empty, infer the command is payload-less and skip. + if ((length > 0) && padding) + { + for (i = length; i < CMIS_CDB_LPL_MAX_SIZE; i++) + { + payload[i] = 0; + } + cciWrite(device, client, osfp, 136, CMIS_CDB_LPL_MAX_SIZE, payload); + } + else if ((length > 0) && !padding) + { + cciWrite(device, client, osfp, 136, length, payload); + } + + // # 3. Write the command code (bytes 128,129), which additionally + // kicks off processing of the command by the module. + temp[0] = cmd_msb; + temp[1] = cmd_lsb; + cciWrite(device, client, osfp, 128, 2, temp); + + return NVL_SUCCESS; +} + +/*! + * @brief Waits for CDB command completion and returns status. + * + * Page 00h byte 37 contains status bits. + * (see CMIS rev4.0, Table 9-3, CDB Command 0000h: QUERY-Status) + */ +NvlStatus +cciGetCDBStatus +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 *pStatus +) +{ + NvBool status_busy; + NvBool status_fail; + NvU8 cdb_result; + NvU8 status; + NVSWITCH_TIMEOUT timeout; + + status = 0; + + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + + do + { + cciRead(device, client, osfp, CMIS_CDB_BLOCK_STATUS_BYTE(0), 1, &status); + *pStatus = status; + + // Quit when the STS_BUSY bit goes to 0 + if (FLD_TEST_REF(CMIS_CDB_BLOCK_STATUS_BYTE_BUSY, _FALSE, status)) + { + break; + } + + if (nvswitch_timeout_check(&timeout)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Timeout waiting for CDB command to complete! " + "STATUS = 0x%x\n", + __FUNCTION__, status); + break; + } + + nvswitch_os_sleep(10); + } while (NV_TRUE); + + status_busy = (status >> 7) & 0x1; + status_fail = (status >> 6) & 0x1; + cdb_result = status & 0x3f; + + if (status_busy) // status is busy + { + if (cdb_result == 0x01) + { + NVSWITCH_PRINT(device, INFO, + "%s: CDB status = BUSY. Last Command Result: " + "'Command is captured but not processed'\n", + __FUNCTION__); + } + else if (cdb_result == 0x02) + { + NVSWITCH_PRINT(device, INFO, + "%s: CDB status = BUSY. Last Command Result: " + "'Command checking is in progress'\n", + __FUNCTION__); + } + else if (cdb_result == 0x03) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = BUSY. Last Command Result: " + "'Command execution is in progress'\n", + __FUNCTION__); + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = BUSY. Last Command Result: " + "Unknown (0x%x)\n", + __FUNCTION__, cdb_result); + } + + return -NVL_ERR_GENERIC; + } + + if (status_fail) // status failed + { + if (cdb_result == 0x01) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = FAIL. Last Command Result: " + "'CMD Code unknown'\n", + __FUNCTION__); + } + else if (cdb_result == 0x02) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = FAIL. Last Command Result: " + "'Parameter range error or not supported'\n", + __FUNCTION__); + } + else if (cdb_result == 0x03) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = FAIL. Last Command Result: " + "'Previous CMD was not ABORTED by CMD Abort'\n", + __FUNCTION__); + } + else if (cdb_result == 0x04) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = FAIL. Last Command Result: " + "'Command checking time out'\n", + __FUNCTION__); + } + else if (cdb_result == 0x05) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = FAIL. Last Command Result: " + "'CdbCheckCode Error'\n", + __FUNCTION__); + } + else if (cdb_result == 0x06) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = FAIL. Last Command Result: " + "'Password Error'\n", + __FUNCTION__); + } + else + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB status = FAIL. Last Command Result: " + "Unknown (0x%x)\n", + __FUNCTION__, cdb_result); + } + + return -NVL_ERR_GENERIC; + } + + return NVL_SUCCESS; +} + +/*! + * @brief Waits for CDB command completion. + * + * Page 00h byte 37 contains status bits. BIT 7 is the busy bit. + * (see CMIS rev4.0, Table 9-3, CDB Command 0000h: QUERY-Status) + */ +NvlStatus +cciWaitForCDBComplete +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp +) +{ + NVSWITCH_TIMEOUT timeout; + NvU8 status; + + status = 0; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + + do + { + cciRead(device, client, osfp, CMIS_CDB_BLOCK_STATUS_BYTE(0), 1, &status); + + // Return when the STS_BUSY bit goes to 0 + if (FLD_TEST_REF(CMIS_CDB_BLOCK_STATUS_BYTE_BUSY, _FALSE, status)) + { + return NVL_SUCCESS; + } + + if (nvswitch_timeout_check(&timeout)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Timeout waiting for CDB command to complete! STATUS = 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_GENERIC; + } + + nvswitch_os_sleep(10); + } while (NV_TRUE); +} + +/*! + * @brief Get the CDB response data. + * + * This function must be sent after CDB status is success. + * + * Page 9Fh, bytes 134-255 contains response data + * Byte 134 : Response LPL Length of the data returned by CDB command code. + * Byte 135 : Response LPL ChkCode + * Bytes 136-255 : Local payload of the module response. + */ +NvlStatus +cciGetCDBResponse +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 *response, + NvU32 *resLength +) +{ + NvU8 header[8] = {0}; + NvU32 rlpllen; // Response local payload length + NvU8 rlplchkcode; // Response local payload check code + NvU8 chksum = 0; + NvU32 i; + NvBool bSkipChecksum = NV_FALSE; + + cciSetBankAndPage(device, client, osfp, 0, 0x9f); + + // get header + cciRead(device, client, osfp, 128, 8, header); + + // get reported response length + rlpllen = header[6]; + rlplchkcode = header[7]; + + // TODO : Remove this once FW support improves + if (rlpllen == 0) + { + // bug with earlier Stallion FW, presume hit it an read maximum-sized lpl. + // Assume the maximum length of 120 and skip checksum because it will also + // be zero + rlpllen = CMIS_CDB_LPL_MAX_SIZE; + bSkipChecksum = NV_TRUE; + } + + if (rlpllen > CMIS_CDB_LPL_MAX_SIZE) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Error: Invalid CDB response length: %d\n", + __FUNCTION__, rlpllen); + return -NVL_ERR_GENERIC; + } + + if (rlpllen != 0) + { + // get response + cciRead(device, client, osfp, 136, rlpllen, response); + + if (!bSkipChecksum) + { + // compute checksum of response + for (i = 0; i < rlpllen; i++) + { + chksum += response[i]; + } + + // and compare against rlplchkcode (byte 7 of page 9Fh) + if ((~chksum & 0xff) != rlplchkcode) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Error: RLPLChkCode incorrect for returned data\n", + __FUNCTION__); + return -NVL_ERR_GENERIC; + } + } + } + + if (resLength != NULL) + { + *resLength = rlpllen; + } + + return NVL_SUCCESS; +} + +/*! + * @brief Get the CDB command and get response. + */ +NvlStatus +cciSendCDBCommandAndGetResponse +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU32 command, + NvU32 payLength, + NvU8 *payload, + NvU32 *resLength, + NvU8 *response, + NvBool padding +) +{ + NvlStatus retval; + NvU8 status = 0; + + if (!cciModulePresent(device, osfp)) + { + NVSWITCH_PRINT(device, INFO, + "%s: osfp %d is missing\n", + __FUNCTION__, osfp); + return -NVL_NOT_FOUND; + } + + // Wait for CDB status to be free + retval = cciWaitForCDBComplete(device, client, osfp); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, + "%s: CDB is busy!!\n", + __FUNCTION__); + return -NVL_ERR_GENERIC; + } + + retval = cciSendCDBCommand(device, client, osfp, command, payLength, payload, padding); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, + "%s: Failed to send CDB Command: 0x%x\n", + __FUNCTION__, command); + return -NVL_ERR_GENERIC; + } + + retval = cciGetCDBStatus(device, client, osfp, &status); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CDB command failed! result = 0x%x\n", + __FUNCTION__, status); + return -NVL_ERR_GENERIC; + } + + retval = cciGetCDBResponse(device, client, osfp, response, resLength); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get CDB command response\n", + __FUNCTION__); + return -NVL_ERR_GENERIC; + } + + return NVL_SUCCESS; +} + +NvlStatus +cciRegisterCallback +( + nvswitch_device *device, + NvU32 callbackId, + void (*functionPtr)(nvswitch_device*), + NvU32 rateHz +) +{ + PCCI pCci = device->pCci; + + if ((callbackId >= NVSWITCH_CCI_CALLBACK_NUM_MAX) || + (functionPtr == NULL)) + { + return -NVL_BAD_ARGS; + } + + if ((rateHz == 0) || ((NVSWITCH_CCI_POLLING_RATE_HZ % rateHz) != 0)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Input rate must divide main polling rate: %d\n", + __FUNCTION__, NVSWITCH_CCI_POLLING_RATE_HZ); + return -NVL_BAD_ARGS; + } + + if (pCci->callbackList[callbackId].functionPtr != NULL) + { + NVSWITCH_PRINT(device, SETUP, + "%s: CCI callback previously set.\n", + __FUNCTION__); + } + + pCci->callbackList[callbackId].interval = NVSWITCH_CCI_POLLING_RATE_HZ/rateHz; + pCci->callbackList[callbackId].functionPtr = functionPtr; + + return NVL_SUCCESS; +} + +// CCI CONTROL CALLS +NvlStatus +nvswitch_ctrl_get_cci_fw_revisions +( + nvswitch_device *device, + NVSWITCH_CCI_GET_FW_REVISION_PARAMS *pParams +) +{ + return cciGetFWRevisions(device, 0, pParams->linkId, + pParams->revisions); +} + +NvlStatus +nvswitch_ctrl_get_grading_values +( + nvswitch_device *device, + NVSWITCH_CCI_GET_GRADING_VALUES_PARAMS *pParams +) +{ + return cciGetGradingValues(device, 0, pParams->linkId, + &pParams->laneMask, &pParams->grading); +} + +NvlStatus +nvswitch_ctrl_get_ports_cpld_info +( + nvswitch_device *device, + NVSWITCH_CCI_GET_PORTS_CPLD_INFO_PARAMS *pParams +) +{ + NvlStatus retval = NVL_SUCCESS; + NvU8 val; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + retval = nvswitch_cci_ports_cpld_read(device, CPLD_MACHXO3_VERSION_MAJOR, &val); + if (retval != NVL_SUCCESS) + { + return -NVL_IO_ERROR; + } + pParams->versionMajor = val; + + retval = nvswitch_cci_ports_cpld_read(device, CPLD_MACHXO3_VERSION_MINOR, &val); + if (retval != NVL_SUCCESS) + { + return -NVL_IO_ERROR; + } + pParams->versionMinor = val; + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_set_locate_led +( + nvswitch_device *device, + NVSWITCH_CCI_SET_LOCATE_LED_PARAMS *pParams +) +{ + NvlStatus retval = NVL_SUCCESS; + NvU32 cagesMask; + NvU8 ledState; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + retval = cciGetXcvrMask(device, &cagesMask, NULL); + if (retval != NVL_SUCCESS) + { + return retval; + } + + if (!(cagesMask & NVBIT(pParams->cageIndex))) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module cage does not exist\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if (pParams->portNum > 1) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Invalid port number\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + ledState = device->pCci->xcvrCurrentLedState[pParams->cageIndex]; + + if (pParams->portNum == 0) + { + ledState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_A, + pParams->bSetLocateOn ? CCI_LED_STATE_LOCATE : + CCI_LED_STATE_OFF, + ledState); + } + else + { + ledState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_B, + pParams->bSetLocateOn ? CCI_LED_STATE_LOCATE : + CCI_LED_STATE_OFF, + ledState); + } + + cciSetNextXcvrLedState(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + pParams->cageIndex, ledState); + cciSetXcvrLedState(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + pParams->cageIndex, NV_FALSE); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_cci_request_ali +( + nvswitch_device *device, + NVSWITCH_REQUEST_ALI_PARAMS *pParams +) +{ + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + return cciRequestALI(device, pParams->linkMaskTrain); +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +/* + * @Brief : Reset CCI on this device. + * + * This is temporary and eventually moved to bios. + * Tracking this in bug 200668898. + * + */ +static NvlStatus +_nvswitch_reset_cci +( + nvswitch_device *device +) +{ + return nvswitch_cci_reset(device); +} + +/* + * @Brief : Execute CCI pre-reset sequence for secure reset. + */ +static NvlStatus +_nvswitch_cci_prepare_for_reset +( + nvswitch_device *device +) +{ + nvswitch_cci_setup_gpio_pins(device); + + return NVL_SUCCESS; +} + +/* + * Check for CMIS boards by pinging on OSFP devices + */ +static NvlStatus +_nvswitch_identify_cci_devices +( + nvswitch_device *device +) +{ + PCCI pCci = device->pCci; + NvU32 maskPresent; + + maskPresent = 0; + + nvswitch_cci_get_xcvrs_present(device, &maskPresent); + pCci->osfpMaskPresent = maskPresent; + pCci->osfpMaskAll = pCci->cagesMask; + + NVSWITCH_PRINT(device, SETUP, + "%s: Identified modules mask: 0x%x\n", + __FUNCTION__, pCci->osfpMaskPresent); + + pCci->bInitialized = NV_TRUE; + + return NVL_SUCCESS; +} + +NvBool +cciIsLinkManaged +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + return NV_FALSE; + } + + return !!(device->pCci->linkMask & NVBIT64(linkNumber)); +} + +NvlStatus +cciGetLinkMode +( + nvswitch_device *device, + NvU32 linkNumber, + NvU64 *mode +) +{ + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (mode == NULL) + { + return -NVL_BAD_ARGS; + } + + if (!cciIsLinkManaged(device, linkNumber)) + { + return -NVL_BAD_ARGS; + } + + if (cciLinkTrainIdle(device, linkNumber)) + { + *mode = NVLINK_LINKSTATE_OFF; + } + else + { + *mode = NVLINK_LINKSTATE_TRAINING_CCI; + } + + return NVL_SUCCESS; +} + +/* + * @Brief : Bootstrap CCI on the specified device + * + * @param[in] device Bootstrap CCI on this device + */ +NvlStatus +cciLoad +( + nvswitch_device *device +) +{ + NvlStatus status; + + if (IS_FMODEL(device) || IS_RTLSIM(device)) + { + NVSWITCH_PRINT(device, SETUP, + "%s: Skipping CCI init on preSilicon.\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (device->pCci == NULL) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_INIT, + "Failed to init CCI(0)\n"); + return -NVL_BAD_ARGS; + } + + // Prepare CCI for reset. + status = _nvswitch_cci_prepare_for_reset(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_RESET, + "Failed to reset CCI(0)\n"); + return status; + } + + // Reset CCI + status = _nvswitch_reset_cci(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_RESET, + "Failed to reset CCI(1)\n"); + return status; + } + + // Identify CCI devices + status = _nvswitch_identify_cci_devices(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_INIT, + "Failed to init CCI(1)\n"); + return status; + } + + // Complete CCI setup + status = nvswitch_cci_setup_onboard(device); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_INIT, + "Failed to init CCI(2)\n"); + return status; + } + + NVSWITCH_PRINT(device, SETUP, + "%s: CCI load successful.\n", + __FUNCTION__); + + return status; +} + +/* + * @brief Get FW revisions of the osfp device by link Id + * + * Module FW revision is obtained from CDB command 0x100. + * (ref CMIS rev4.0, Table 9-16 CDB Command 0100h: Get firmware Info) + */ +NvlStatus +cciGetFWRevisions +( + nvswitch_device *device, + NvU32 client, + NvU32 linkId, + NVSWITCH_CCI_GET_FW_REVISIONS *pRevisions +) +{ + NvU32 osfp; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (cciGetModuleId(device, linkId, &osfp) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get moduleid associated with link %d\n", + __FUNCTION__, linkId); + return -NVL_ERR_NOT_SUPPORTED; + } + + return cciGetXcvrFWRevisions(device, client, osfp, pRevisions); +} + +static NvlStatus +_cciGetXcvrFWRevisionsFlatMem +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NVSWITCH_CCI_GET_FW_REVISIONS *pRevisions +) +{ + NvlStatus retVal; + NvU8 versionByte; + + retVal = cciCmisRead(device, osfp, 0, 0, + CMIS_ACTIVE_FW_MAJOR_REVISION, 1, &versionByte); + if (retVal != NVL_SUCCESS) + { + return retVal; + } + + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].major = versionByte; + + retVal = cciCmisRead(device, osfp, 0, 0, + CMIS_ACTIVE_FW_MINOR_REVISION, 1, &versionByte); + if (retVal != NVL_SUCCESS) + { + return retVal; + } + + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].minor = versionByte; + + if (pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].major || + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].minor) + { + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _ACTIVE, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags); + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _PRESENT, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags); + } + + // Entries for images A and B will be left as 0 + + return NVL_SUCCESS; +} + +/* + * @brief Get FW revisions of the osfp device by OSFP xceiver index + * + * Module FW revision is obtained from CDB command 0x100. + * (ref CMIS rev4.0, Table 9-16 CDB Command 0100h: Get firmware Info) + */ +NvlStatus +cciGetXcvrFWRevisions +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NVSWITCH_CCI_GET_FW_REVISIONS *pRevisions +) +{ + NvU8 response[CMIS_CDB_LPL_MAX_SIZE]; + NvU32 resLength; + NvlStatus retVal; + NvU8 status; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (osfp >= (sizeof(device->pCci->osfpMaskAll) * 8)) + { + return -NVL_BAD_ARGS; + } + + if (!(device->pCci->osfpMaskPresent & NVBIT(osfp))) + { + NVSWITCH_PRINT(device, ERROR, + "%s: osfp %d is missing\n", + __FUNCTION__, osfp); + return -NVL_ERR_NOT_SUPPORTED; + } + + nvswitch_os_memset(pRevisions, 0, sizeof(NVSWITCH_CCI_GET_FW_REVISIONS)); + + if (device->pCci->isFlatMemory[osfp]) + { + retVal = _cciGetXcvrFWRevisionsFlatMem(device, client, osfp, pRevisions); + if (retVal != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get FW revisions\n", + __FUNCTION__); + return -NVL_ERR_GENERIC; + } + + return NVL_SUCCESS; + } + + retVal = cciSendCDBCommandAndGetResponse(device, client, osfp, + 0x100, 0, NULL, &resLength, response, NV_FALSE); + if (retVal != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get FW revisions\n", + __FUNCTION__); + return -NVL_ERR_GENERIC; + } + + // Byte 0(or 136) contains FW status + status = response[0]; + + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags = 0; + if (status == 0) + { + NVSWITCH_PRINT(device, INFO, + "%s: Factory Boot Image is Running\n", + __FUNCTION__); + + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _ACTIVE, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags); + } + + if (response[1] & NVBIT(2)) + { + // + // For Factory Image, + // Byte 74(or 210) contains major revision + // Byte 75(or 211) contains minor revision + // Byte 76, 77(or 212, 213) contains build number + // + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _PRESENT, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].flags); + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].major = response[74]; + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].minor = response[75]; + pRevisions[NVSWITCH_CCI_FW_IMAGE_FACTORY].build = (response[76] << 4 | response[77]); + } + + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags = 0; + if (status & NVBIT(0)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Image A is Running\n", + __FUNCTION__); + + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _ACTIVE, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags); + } + if (status & NVBIT(1)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Image A is committed, module boots from Image A\n", + __FUNCTION__); + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _COMMITED, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags); + } + if (status & NVBIT(2)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Image A is erased/empty\n", + __FUNCTION__); + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _EMPTY, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags); + } + + if (response[1] & NVBIT(0)) + { + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _PRESENT, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].flags); + // + // For Image A, + // Byte 2(or 138) contains major revision + // Byte 3(or 139) contains minor revision + // Byte 4, 5(or 140, 141) contains build number + // + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].major = response[2]; + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].minor = response[3]; + pRevisions[NVSWITCH_CCI_FW_IMAGE_A].build = (response[4] << 4 | response[5]); + } + + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags = 0; + if (status & NVBIT(4)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Image B is Running\n", + __FUNCTION__); + + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _ACTIVE, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags); + } + if (status & NVBIT(5)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Image B is committed, module boots from Image B\n", + __FUNCTION__); + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _COMMITED, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags); + } + if (status & NVBIT(6)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Image B is erased/empty\n", + __FUNCTION__); + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _EMPTY, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags); + } + + if (response[1] & NVBIT(1)) + { + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags = + FLD_SET_DRF(SWITCH, _CCI_FW_FLAGS, _PRESENT, _YES, + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].flags); + // + // For Image B, + // Byte 38(or 174) contains major revision + // Byte 39(or 175) contains minor revision + // Byte 40, 41(or 176, 177) contains build number + // + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].major = response[38]; + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].minor = response[39]; + pRevisions[NVSWITCH_CCI_FW_IMAGE_B].build = (response[40] << 8 | response[41]); + } + + return NVL_SUCCESS; +} + +/* + * @brief Get xceiver LED state by OSFP xceiver index. + * + */ +NvlStatus +cciGetXcvrLedState +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 *pLedState +) +{ + NvlStatus status; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + status = nvswitch_cci_get_xcvr_led_state(device, client, osfp, pLedState); + if (status != NVL_SUCCESS) + { + return status; + } + + return status; +} + +/* + * @brief Set the next LED state for the given OSFP. + * The HW will reflect this state on the next iteration of link + * state update callback. + */ +NvlStatus +cciSetNextXcvrLedState +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 nextLedState +) +{ + NvlStatus status; + NvU32 cagesMask; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + status = cciGetXcvrMask(device, &cagesMask, NULL); + if (status != NVL_SUCCESS) + { + return status; + } + + if ((cagesMask & NVBIT32(osfp)) == 0) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module cage not found\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + device->pCci->xcvrNextLedState[osfp] = nextLedState; + + return status; +} + +/* + * @brief Set HW xceiver LED state (Locate On/Off) by OSFP xceiver index. + * If Locate is off then set LED state based on link state. + * + */ +NvlStatus +cciSetXcvrLedState +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvBool bSetLocate +) +{ + NvlStatus status; + NvU32 cagesMask; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + status = cciGetXcvrMask(device, &cagesMask, NULL); + if (status != NVL_SUCCESS) + { + return status; + } + + if ((cagesMask & NVBIT32(osfp)) == 0) + { + return -NVL_BAD_ARGS; + } + + status = nvswitch_cci_set_xcvr_led_state(device, client, osfp, bSetLocate); + if (status != NVL_SUCCESS) + { + return status; + } + + return status; +} + +/* + * @brief Determine which OSFP transceivers are connected + * + */ +void +cciDetectXcvrsPresent +( + nvswitch_device *device +) +{ + NvU32 maskPresent; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return; + } + + maskPresent = 0; + + nvswitch_cci_get_xcvrs_present(device, &maskPresent); + nvswitch_cci_set_xcvr_present(device, maskPresent); +} + +/* + * @brief Get the bitset mask of connected OSFP transceivers + * + */ +NvlStatus +cciGetXcvrMask +( + nvswitch_device *device, + NvU32 *pMaskAll, + NvU32 *pMaskPresent +) +{ + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + return nvswitch_cci_get_xcvr_mask(device, pMaskAll, pMaskPresent); +} + +NvlStatus +cciConfigureNvlinkModeModule +( + nvswitch_device *device, + NvU32 client, + NvU8 moduleId, + NvU64 linkMask, + NvBool freeze_maintenance, + NvBool restart_training, + NvBool nvlink_mode +) +{ + NvlStatus status; + NvU8 payload[CMIS_CDB_LPL_MAX_SIZE]; + NvU8 response[CMIS_CDB_LPL_MAX_SIZE]; + NvU32 resLength; + NvU8 linkId; + NvU8 laneMask; + NvU8 laneMaskTemp; + + laneMask = 0; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + FOR_EACH_INDEX_IN_MASK(64, linkId, linkMask) + { + status = cciGetLaneMask(device, linkId, &laneMaskTemp); + if (status != NVL_SUCCESS) + { + return status; + } + laneMask |= laneMaskTemp; + } + FOR_EACH_INDEX_IN_MASK_END; + + payload[0] = 0; + payload[1] = (freeze_maintenance << 4) + (restart_training << 1) + nvlink_mode; + payload[2] = 0; + + // Tx + payload[3] = laneMask; + payload[4] = 0; + + // Rx + payload[5] = laneMask; + + status = cciSendCDBCommandAndGetResponse(device, client, moduleId, NVSWITCH_CCI_CDB_CMD_ID, 6, + payload, &resLength, response, NV_FALSE); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to configure nvlink mode\n", + __FUNCTION__); + return status; + } + + return NVL_SUCCESS; +} + +/* + * @brief Configures individual RX and TX osfp lanes to NVLink mode + * + * Freeze Maintenance(FM) : When pre-training starts this should be set, and later + * cleared once link becomes active. + * + * Restart Training(RT) : must be set only when linkup flow is reset and pre-training + * should be performed. + * + * Nvlink Mode(NV) : Must be set to 0x1 for NVLink Mode. + * + * CDB address 0xCD19. Write sequence - + * [0, (0,0,0,0,FM,0,0,RT,NV), TX CH Mask 15..8(00h), TX CH Mask 7..0(FFh), RX CH Mask 15..8 (00h), RX CH Mask 7..0(FFh)] + * + * (ref cdb_prospector.pdf) + */ +NvlStatus +cciConfigureNvlinkMode +( + nvswitch_device *device, + NvU32 client, + NvU32 linkId, + NvBool bTx, + NvBool freeze_maintenance, + NvBool restart_training, + NvBool nvlink_mode +) +{ + NvU8 payload[CMIS_CDB_LPL_MAX_SIZE]; + NvU8 response[CMIS_CDB_LPL_MAX_SIZE]; + NvU32 resLength; + NvlStatus status; + NvU32 osfp; + NvU8 laneMask; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (cciGetModuleId(device, linkId, &osfp) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get moduleId associated with link %d\n", + __FUNCTION__, linkId); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (!cciModulePresent(device, osfp)) + { + return -NVL_NOT_FOUND; + } + + if (cciGetLaneMask(device, linkId, &laneMask) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get osfp lanemask associated with link %d\n", + __FUNCTION__, linkId); + return -NVL_ERR_NOT_SUPPORTED; + } + + payload[0] = 0; + payload[1] = (freeze_maintenance<<4)+(restart_training<<1)+nvlink_mode; + payload[2] = 0; + payload[3] = bTx ? laneMask : 0; + payload[4] = 0; + payload[5] = bTx ? 0 : laneMask; + + status = cciSendCDBCommandAndGetResponse(device, client, osfp, + NVSWITCH_CCI_CDB_CMD_ID, 6, payload, &resLength, response, NV_FALSE); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to configure nvlink mode\n", + __FUNCTION__); + return status; + } + + return NVL_SUCCESS; +} + +/* + * @brief Check for optical pre training completion + * + * CDB address CD20h - Retrieves individual RX and TX channels training status. + * Read sequence - + * [TX CH Mask 15..8(00h), TX CH Mask 7..0(FFh), RX CH Mask 15..8 (00h), RX CH Mask 7..0(FFh)] + * + * (ref cdb_prospector.pdf) + */ +NvBool +cciCheckForPreTraining +( + nvswitch_device *device, + NvU32 client, + NvU32 linkId, + NvBool bTx +) +{ + NvlStatus status; + NvU8 response[CMIS_CDB_LPL_MAX_SIZE]; + NvU32 resLength; + NvU32 osfp; + NvU8 train_mask; + NvU8 lane_mask; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return NV_FALSE; + } + + if (cciGetModuleId(device, linkId, &osfp) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get moduleId associated with link %d\n", + __FUNCTION__, linkId); + return NV_FALSE; + } + + if (!cciModulePresent(device, osfp)) + { + return NV_FALSE; + } + + if (cciGetLaneMask(device, linkId, &lane_mask) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get osfp lanemask associated with link %d\n", + __FUNCTION__, linkId); + return NV_FALSE; + } + + status = cciSendCDBCommandAndGetResponse(device, client, osfp, + 0xcd20, 0, NULL, &resLength, response, NV_FALSE); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get nvlink status\n", + __FUNCTION__); + return NV_FALSE; + } + + train_mask = bTx ? response[1] : response[3]; + if ((lane_mask & train_mask) == lane_mask) + { + NVSWITCH_PRINT(device, INFO, + "%s: pre-training completed on link %d!\n", + __FUNCTION__, linkId); + return NV_TRUE; + } + + return NV_FALSE; +} + +NvlStatus +cciApplyControlSetValues +( + nvswitch_device *device, + NvU32 client, + NvU32 moduleMask +) +{ + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + return nvswitch_cci_apply_control_set_values(device, client, moduleMask); +} + +NvlStatus +cciGetGradingValues +( + nvswitch_device *device, + NvU32 client, + NvU32 linkId, + NvU8 *laneMask, + NVSWITCH_CCI_GRADING_VALUES *pGrading +) +{ + return nvswitch_cci_get_grading_values(device, client, linkId, laneMask, pGrading); +} + +/* + * @brief Gets the mapping between cageIndex and link Ids + * Returns a bitmask containing all links mapped to the given + * cage. Also returns a value that encodes other information + * including the mapping between OSFP link lane and Nvlink link + */ +NvlStatus +cciGetCageMapping +( + nvswitch_device *device, + NvU8 cageIndex, + NvU64 *pLinkMask, + NvU64 *pEncodedValue +) +{ + NVSWITCH_CCI_MODULE_LINK_LANE_MAP *p_nvswitch_cci_osfp_map; + NvU64 linkMask; + NvU64 encodedValue; + NvU8 *pEncodedByte; + NvU32 nvswitch_cci_osfp_map_size; + NvU32 i; + NvU8 linkId; + NvU8 osfpLane; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not initialized\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + linkMask = 0; + encodedValue = 0; + pEncodedByte = (NvU8 *)&encodedValue; + p_nvswitch_cci_osfp_map = device->pCci->osfp_map; + nvswitch_cci_osfp_map_size = device->pCci->osfp_map_size; + + for (i = 0; i < nvswitch_cci_osfp_map_size; i++) + { + if (p_nvswitch_cci_osfp_map[i].moduleId == cageIndex) + { + linkId = p_nvswitch_cci_osfp_map[i].linkId; + NVSWITCH_ASSERT(linkId <= 63); + + linkMask |= NVBIT64(linkId); + FOR_EACH_INDEX_IN_MASK(8, osfpLane, p_nvswitch_cci_osfp_map[i].laneMask) + { + pEncodedByte[osfpLane] = + REF_NUM(NVSWITCH_CCI_CMIS_NVLINK_MAPPING_ENCODED_VALUE_LINK_ID, linkId); + } + FOR_EACH_INDEX_IN_MASK_END; + } + } + + if (pLinkMask != NULL) + { + *pLinkMask = linkMask; + } + + if (pEncodedValue != NULL) + { + *pEncodedValue = encodedValue; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cciCmisAccessSetup +( + nvswitch_device *device, + NvU8 cageIndex, + NvU8 bank, + NvU8 page, + NvU8 address, + NvU8 count, + NvU8 *pSavedBank, + NvU8 *pSavedPage +) +{ + NvlStatus status; + NvU32 cagesMask; + + status = cciGetXcvrMask(device, &cagesMask, NULL); + if (status != NVL_SUCCESS) + { + return status; + } + + if (!(cagesMask & NVBIT(cageIndex))) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Provided cage index does not exist.\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if (count == 0 || + count > NVSWITCH_CCI_CMIS_MEMORY_ACCESS_BUF_SIZE) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Invalid byte count.\n", + __FUNCTION__); + return -NVL_BAD_ARGS; + } + + if (device->pCci->isFlatMemory[cageIndex]) + { + if (page != 0 || bank !=0) + { + return -NVL_ERR_NOT_SUPPORTED; + } + else + { + return NVL_SUCCESS; + } + } + + if (address >= 0x80) + { + // Save previous bank and page + status = cciGetBankAndPage(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + cageIndex, pSavedBank, pSavedPage); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to save bank and page.\n", + __FUNCTION__); + return status; + } + + // Don't change bank and page unnecessarily + if (*pSavedBank != bank || *pSavedPage != page) + { + status = cciSetBankAndPage(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + cageIndex, bank, page); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to set bank and page.\n", + __FUNCTION__); + return status; + } + } + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cciCmisAccessRestore +( + nvswitch_device *device, + NvU8 cageIndex, + NvU8 bank, + NvU8 page, + NvU8 address, + NvU8 savedBank, + NvU8 savedPage +) +{ + NvlStatus status; + + if (device->pCci->isFlatMemory[cageIndex]) + { + if (page != 0 || bank !=0) + { + return -NVL_ERR_NOT_SUPPORTED; + } + else + { + return NVL_SUCCESS; + } + } + + // Restore previous bank and page + if (address >= 0x80) + { + if (savedBank != bank || savedPage != page) + { + status = cciSetBankAndPage(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + cageIndex, savedBank, savedPage); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to restore bank and page.\n", + __FUNCTION__); + return status; + } + } + } + + return NVL_SUCCESS; +} + +static NvBool +_cciCmisAccessAllowed +( + nvswitch_device *device, + NvU8 cageIndex +) +{ + PCCI pCci = device->pCci; + NvU32 pid; + NvlStatus status; + + status = nvswitch_os_get_pid(&pid); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, + "%s: CCI CMIS lock not supported\n", + __FUNCTION__); + return NV_TRUE; + } + + // Reject clients with different PIDs that attempt access + if (pCci->cmisAccessLock[cageIndex].bLocked && + (pid != pCci->cmisAccessLock[cageIndex].pid)) + { + return NV_FALSE; + } + + return NV_TRUE; +} + +/*! + * @brief Try to obtain lock for CMIS accesses + */ +NvBool +cciCmisAccessTryLock +( + nvswitch_device *device, + NvU8 cageIndex +) +{ + PCCI pCci = device->pCci; + NvU64 timestampCurr; + NvU64 timestampSaved; + NvU32 pid; + NvlStatus status; + + status = nvswitch_os_get_pid(&pid); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, + "%s: CCI CMIS lock not supported\n", + __FUNCTION__); + return NV_TRUE; + } + + timestampCurr = nvswitch_os_get_platform_time(); + timestampSaved = pCci->cmisAccessLock[cageIndex].timestamp; + + // Release lock if modules accesses have been idle + if ((timestampCurr - timestampSaved) >= NVSWITCH_CCI_CMIS_LOCK_TIMEOUT) + { + cciCmisAccessReleaseLock(device, cageIndex); + } + + if (!_cciCmisAccessAllowed(device, cageIndex)) + { + return NV_FALSE; + } + + // Lock CMIS access to module. External clients may attempt to lock multiple times + pCci->cmisAccessLock[cageIndex].bLocked = NV_TRUE; + pCci->cmisAccessLock[cageIndex].timestamp = timestampCurr; + pCci->cmisAccessLock[cageIndex].pid = pid; + + return NV_TRUE; +} + +/*! + * @brief Release lock for CMIS accesses + */ +void +cciCmisAccessReleaseLock +( + nvswitch_device *device, + NvU8 cageIndex +) +{ + PCCI pCci = device->pCci; + NvU32 pid; + NvlStatus status; + + status = nvswitch_os_get_pid(&pid); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, + "%s: CCI CMIS lock not supported\n", + __FUNCTION__); + return; + } + + pCci->cmisAccessLock[cageIndex].bLocked = NV_FALSE; +} + +/*! + * @brief Read from specified module cage. + * Sets the bank and page if necessary. + */ +NvlStatus +cciCmisRead +( + nvswitch_device *device, + NvU8 cageIndex, + NvU8 bank, + NvU8 page, + NvU8 address, + NvU8 count, + NvU8 *pData +) +{ + NvU8 savedBank; + NvU8 savedPage; + NvlStatus status; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + // Prevent internal driver CMIS reads from occuring while access is locked + if (!_cciCmisAccessAllowed(device, cageIndex)) + { + return -NVL_ERR_STATE_IN_USE; + } + + // Perform checks and save bank/page if needed + status = _cciCmisAccessSetup(device, cageIndex, bank, page, + address, count, &savedBank, &savedPage); + if (status != NVL_SUCCESS) + { + return status; + } + + status = cciRead(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + cageIndex, address, count, pData); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to read from module cage %d\n", + __FUNCTION__, cageIndex); + return status; + } + + status = _cciCmisAccessRestore(device, cageIndex, bank, page, + address, savedBank, savedPage); + if (status != NVL_SUCCESS) + { + return status; + } + + return NVL_SUCCESS; +} + +/*! + * @brief Write to specified module cage. + * Sets the bank and page if necessary. + */ +NvlStatus +cciCmisWrite +( + nvswitch_device *device, + NvU8 cageIndex, + NvU8 bank, + NvU8 page, + NvU8 address, + NvU8 count, + NvU8 *pData +) +{ + NvU8 savedBank; + NvU8 savedPage; + NvlStatus status; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + // Prevent internal driver CMIS reads from occuring while access is locked + if (!_cciCmisAccessAllowed(device, cageIndex)) + { + return -NVL_ERR_STATE_IN_USE; + } + + // Perform checks and save bank/page if needed + status = _cciCmisAccessSetup(device, cageIndex, bank, page, + address, count, &savedBank, &savedPage); + if (status != NVL_SUCCESS) + { + return status; + } + + status = cciWrite(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + cageIndex, address, count, pData); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to write to module cage %d\n", + __FUNCTION__, cageIndex); + return status; + } + + status = _cciCmisAccessRestore(device, cageIndex, bank, page, + address, savedBank, savedPage); + if (status != NVL_SUCCESS) + { + return status; + } + + return NVL_SUCCESS; +} + +NvlStatus +cciCmisCageBezelMarking +( + nvswitch_device *device, + NvU8 cageIndex, + char *pBezelMarking +) +{ + return nvswitch_cci_cmis_cage_bezel_marking(device, cageIndex, pBezelMarking); +} + +// Helper functions for CCI subcomponents +NvlStatus +cciGetModuleId +( + nvswitch_device *device, + NvU32 linkId, + NvU32 *osfp +) +{ + return _nvswitch_cci_get_module_id(device, linkId, osfp); +} + +NvBool +cciModulePresent +( + nvswitch_device *device, + NvU32 osfp +) +{ + return _nvswitch_cci_module_present(device, osfp); +} + +void +cciGetModulePresenceChange +( + nvswitch_device *device, + NvU32 *pModuleMask +) +{ + nvswitch_cci_get_xcvrs_present_change(device, pModuleMask); +} + +NvlStatus +cciResetModule +( + nvswitch_device *device, + NvU32 moduleId +) +{ + NvlStatus retval; + NvU8 regByte; + + // Assert OSFP reset + regByte = NVBIT32(moduleId); + retval = nvswitch_cci_ports_cpld_write(device, CPLD_MACHXO3_PORTS_RESET_REG1, regByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + regByte = (NVBIT32(moduleId) >> 8); + retval = nvswitch_cci_ports_cpld_write(device, CPLD_MACHXO3_PORTS_RESET_REG2, regByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + nvswitch_os_sleep(1); + + // De-assert OSFP reset + retval = nvswitch_cci_ports_cpld_write(device, CPLD_MACHXO3_PORTS_RESET_REG1, 0); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = nvswitch_cci_ports_cpld_write(device, CPLD_MACHXO3_PORTS_RESET_REG2, 0); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Assert lpmode + retval = cciSetLPMode(device, moduleId, NV_TRUE); + if (retval != NVL_SUCCESS) + { + return retval; + } + + return NVL_SUCCESS; +} + +/* + * @brief Get FW info + * Module FW info is obtained from CDB command 0x100. + * (ref CMIS rev4.0, Table 9-16 CDB Command 0100h: Get firmware Info) + * + * @pre pInfo points to a buffer of size CMIS_CDB_LPL_MAX_SIZE bytes + */ +NvlStatus +cciGetXcvrFWInfo +( + nvswitch_device *device, + NvU32 moduleId, + NvU8 *pInfo +) +{ + NvlStatus retVal; + + if ((device->pCci == NULL) || (!device->pCci->bInitialized)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (pInfo == NULL) + { + return -NVL_BAD_ARGS; + } + + if (!cciModulePresent(device, moduleId)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Module %d is missing\n", + __FUNCTION__, moduleId); + return -NVL_NOT_FOUND; + } + + retVal = cciSendCDBCommandAndGetResponse(device, 0, moduleId, + 0x100, 0, NULL, NULL, pInfo, NV_FALSE); + if (retVal != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get FW revisions\n", + __FUNCTION__); + return -NVL_ERR_GENERIC; + } + + return NVL_SUCCESS; +} + +NvlStatus +cciSetLPMode +( + nvswitch_device *device, + NvU8 moduleId, + NvBool bAssert +) +{ + NvlStatus retval; + NvU8 valReg1; + NvU8 valReg2; + + retval = nvswitch_cci_ports_cpld_read(device, CPLD_MACHXO3_PORTS_LPMODE_REG1, &valReg1); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = nvswitch_cci_ports_cpld_read(device, CPLD_MACHXO3_PORTS_LPMODE_REG2, &valReg2); + if (retval != NVL_SUCCESS) + { + return retval; + } + + if (bAssert) + { + valReg1 = valReg1 | NVBIT32(moduleId); + valReg2 = valReg2 | (NVBIT32(moduleId) >> 8); + } + else + { + valReg1 = valReg1 & ~NVBIT32(moduleId); + valReg2 = valReg2 & ~(NVBIT32(moduleId) >> 8); + } + + retval = nvswitch_cci_ports_cpld_write(device, CPLD_MACHXO3_PORTS_LPMODE_REG1, valReg1); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = nvswitch_cci_ports_cpld_write(device, CPLD_MACHXO3_PORTS_LPMODE_REG2, valReg2); + if (retval != NVL_SUCCESS) + { + return retval; + } + + return NVL_SUCCESS; +} + +NvBool +cciCheckLPMode +( + nvswitch_device *device, + NvU8 moduleId +) +{ + NvlStatus retval; + NvU8 valReg1; + NvU8 valReg2; + + retval = nvswitch_cci_ports_cpld_read(device, CPLD_MACHXO3_PORTS_LPMODE_REG1, &valReg1); + if (retval != NVL_SUCCESS) + { + return NV_FALSE; + } + + retval = nvswitch_cci_ports_cpld_read(device, CPLD_MACHXO3_PORTS_LPMODE_REG2, &valReg2); + if (retval != NVL_SUCCESS) + { + return NV_FALSE; + } + + if ((valReg1 & NVBIT32(moduleId)) || + (valReg2 & (NVBIT32(moduleId) >> 8))) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +void +cciPingModules +( + nvswitch_device *device, + NvU32 *pMaskPresent +) +{ + NVSWITCH_CTRL_I2C_INDEXED_PARAMS i2c_params = { 0 }; + NvU32 idx_i2cdevice; + PCCI pCci; + NvU32 presentMask; + NvU32 client; + NvlStatus retval; + + pCci = device->pCci; + presentMask = 0; + client = NVSWITCH_I2C_ACQUIRER_CCI_INITIALIZE; + + for (idx_i2cdevice = 0; idx_i2cdevice < pCci->osfp_num; idx_i2cdevice++) + { + retval = nvswitch_cci_setup_module_path(device, client, idx_i2cdevice); + if (retval != NVL_SUCCESS) + { + continue; + } + + i2c_params.port = pCci->osfp_i2c_info[idx_i2cdevice].i2cPortLogical; + i2c_params.address = (NvU16) pCci->osfp_i2c_info[idx_i2cdevice].i2cAddress; + i2c_params.bIsRead = NV_FALSE; + i2c_params.flags = + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _START, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _RESTART, _NONE) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _STOP, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _ADDRESS_MODE, _7BIT) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _INDEX_LENGTH, _ZERO) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _FLAVOR, _HW) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _SPEED_MODE, _400KHZ) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _BLOCK_PROTOCOL, _DISABLED) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _TRANSACTION_MODE, _PING); + i2c_params.messageLength = 0; + i2c_params.acquirer = client; + + if (nvswitch_ctrl_i2c_indexed(device, &i2c_params) == NVL_SUCCESS) + { + // Only print if newly present OSFP + if (!cciModulePresent(device, idx_i2cdevice)) + { + NVSWITCH_PRINT(device, INFO, + "%s: Identified osfp = %d, port = %d, addr = 0x%x\n", + __FUNCTION__, idx_i2cdevice, i2c_params.port, i2c_params.address); + } + + presentMask |= NVBIT(idx_i2cdevice); + } + } + + if (pMaskPresent != NULL) + { + *pMaskPresent = presentMask; + } +} + +void +cciGetAllLinks +( + nvswitch_device *device, + NvU64 *pLinkMaskAll +) +{ + PCCI pCci = device->pCci; + NvU64 linkMaskAll; + NvU32 i; + + linkMaskAll = 0; + for (i = 0; i < pCci->osfp_map_size; i++) + { + linkMaskAll |= NVBIT64(pCci->osfp_map[i].linkId); + } + + if (pLinkMaskAll != NULL) + { + *pLinkMaskAll = linkMaskAll; + } +} + +NvlStatus +cciGetModuleMask +( + nvswitch_device *device, + NvU64 linkMask, + NvU32 *pModuleMask +) +{ + NvU32 cciModuleMask; + NvU32 moduleId; + NvU8 linkId; + NvlStatus retval; + + cciModuleMask = 0; + + FOR_EACH_INDEX_IN_MASK(64, linkId, linkMask) + { + retval = cciGetModuleId(device, linkId, &moduleId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to get moduleId associated with link %d\n", + __FUNCTION__, linkId); + return retval; + } + + cciModuleMask |= NVBIT32(moduleId); + } + FOR_EACH_INDEX_IN_MASK_END; + + *pModuleMask = cciModuleMask; + + return NVL_SUCCESS; +} + +NvBool +cciCheckXcvrForLinkTraffic +( + nvswitch_device *device, + NvU32 osfp, + NvU64 linkMask +) +{ + NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *pCounterParams = NULL; + NvU64 *pCounterValues; + NvU64 tpCounterPreviousSum; + NvU64 tpCounterCurrentSum; + NvBool bTraffic = NV_FALSE; + NvU8 linkNum; + + pCounterParams = nvswitch_os_malloc(sizeof(*pCounterParams)); + if (pCounterParams == NULL) + goto out; + + pCounterParams->counterMask = NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_TX | + NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_RX; + pCounterParams->linkMask = linkMask; + if (nvswitch_ctrl_get_throughput_counters(device, + pCounterParams) != NVL_SUCCESS) + { + goto out; + } + + // Sum TX/RX traffic for each link + FOR_EACH_INDEX_IN_MASK(64, linkNum, linkMask) + { + pCounterValues = pCounterParams->counters[linkNum].values; + + tpCounterPreviousSum = device->pCci->tpCounterPreviousSum[linkNum]; + + // Sum taken to save space as it is unlikely to overflow before system is reset + tpCounterCurrentSum = pCounterValues[NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_TX] + + pCounterValues[NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_RX]; + + device->pCci->tpCounterPreviousSum[linkNum] = tpCounterCurrentSum; + + // Skip traffic check in first call on system start up + if (device->pCci->callbackCounter == 0) + { + continue; + } + + if (tpCounterCurrentSum > tpCounterPreviousSum) + { + bTraffic = NV_TRUE; + } + } + FOR_EACH_INDEX_IN_MASK_END; + +out: + nvswitch_os_free(pCounterParams); + return bTraffic; +} + +NvlStatus +cciGetLaneMask +( + nvswitch_device *device, + NvU32 linkId, + NvU8 *laneMask +) +{ + NVSWITCH_CCI_MODULE_LINK_LANE_MAP * module_map = device->pCci->osfp_map; + NvU32 module_map_size = device->pCci->osfp_map_size; + NvU32 i; + + for (i = 0; i < module_map_size; i++) + { + if (module_map[i].linkId == linkId) + { + *laneMask = module_map[i].laneMask; + + return NVL_SUCCESS; + } + } + + return -NVL_NOT_FOUND; +} + +void +cciSetModulePower +( + nvswitch_device *device, + NvU32 moduleId, + NvBool bPowerOn +) +{ + NvlStatus status; + NvU8 regVal; + + if (moduleId < 8) + { + status = nvswitch_cci_ports_cpld_read(device, + CPLD_MACHXO3_LD_SW_EN_REG1, + ®Val); + if (status == NVL_SUCCESS) + { + regVal = bPowerOn ? regVal | NVBIT(moduleId) : + regVal & ~NVBIT(moduleId); + nvswitch_cci_ports_cpld_write(device, + CPLD_MACHXO3_LD_SW_EN_REG1, + regVal); + } + } + else + { + status = nvswitch_cci_ports_cpld_read(device, + CPLD_MACHXO3_LD_SW_EN_REG2, + ®Val); + if (status == NVL_SUCCESS) + { + regVal = bPowerOn ? regVal | NVBIT(moduleId - 8) : + regVal & ~NVBIT(moduleId - 8); + nvswitch_cci_ports_cpld_write(device, + CPLD_MACHXO3_LD_SW_EN_REG2, + regVal); + } + } +} + +static void +_cciClearModuleFault +( + nvswitch_device *device, + NvU32 moduleId +) +{ + if (moduleId < 8) + { + nvswitch_cci_ports_cpld_write(device, + CPLD_MACHXO3_LD_SW_FAULT_REG1, + ~NVBIT(moduleId)); + } + else + { + nvswitch_cci_ports_cpld_write(device, + CPLD_MACHXO3_LD_SW_FAULT_REG2, + ~NVBIT(moduleId - 8)); + } +} + +static NvBool +_cciCheckModuleFault +( + nvswitch_device *device, + NvU32 moduleId +) +{ + NvlStatus status; + NvU8 regVal; + + if (moduleId < 8) + { + status = nvswitch_cci_ports_cpld_read(device, CPLD_MACHXO3_LD_SW_FAULT_REG1, ®Val); + if (status != NVL_SUCCESS) + { + return NV_TRUE; + } + + if (regVal & NVBIT(moduleId)) + { + return NV_TRUE; + } + } + else + { + status = nvswitch_cci_ports_cpld_read(device, CPLD_MACHXO3_LD_SW_FAULT_REG2, ®Val); + if (status != NVL_SUCCESS) + { + return NV_TRUE; + } + + if (regVal & NVBIT(moduleId - 8)) + { + return NV_TRUE; + } + } + + return NV_FALSE; +} + +NvBool +cciModuleHWGood +( + nvswitch_device *device, + NvU32 moduleId +) +{ + if (_cciCheckModuleFault(device, moduleId)) + { + // Attempt to recover module by power cycling + cciSetModulePower(device, moduleId, NV_FALSE); + nvswitch_os_sleep(1); + cciSetModulePower(device, moduleId, NV_TRUE); + + // Clear fault flag and check again + _cciClearModuleFault(device, moduleId); + nvswitch_os_sleep(1); + + if (_cciCheckModuleFault(device, moduleId)) + { + return NV_FALSE; + } + } + + return NV_TRUE; +} + diff --git a/src/common/nvswitch/kernel/error_nvswitch.c b/src/common/nvswitch/kernel/error_nvswitch.c index 2b97a56a9e..3f160ef984 100644 --- a/src/common/nvswitch/kernel/error_nvswitch.c +++ b/src/common/nvswitch/kernel/error_nvswitch.c @@ -405,6 +405,16 @@ nvswitch_translate_hw_error { return NVSWITCH_ERR_HW_SOE; } + else if ((type >= NVSWITCH_ERR_HW_CCI) && + (type < NVSWITCH_ERR_HW_CCI_LAST)) + { + return NVSWITCH_ERR_HW_CCI; + } + else if ((type >= NVSWITCH_ERR_HW_OSFP_THERM) && + (type < NVSWITCH_ERR_HW_OSFP_THERM_LAST)) + { + return NVSWITCH_ERR_HW_OSFP_THERM; + } else if ((type >= NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE) && (type < NVSWITCH_ERR_HW_NPORT_MULTICASTTSTATE_LAST)) { diff --git a/src/common/nvswitch/kernel/fsprpc_nvswitch.c b/src/common/nvswitch/kernel/fsprpc_nvswitch.c new file mode 100644 index 0000000000..2b411f7a03 --- /dev/null +++ b/src/common/nvswitch/kernel/fsprpc_nvswitch.c @@ -0,0 +1,460 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "haldef_nvswitch.h" +#include "fsprpc_nvswitch.h" + +#include "fsp/nvdm_payload_cmd_response.h" +#include "fsp/fsp_nvdm_format.h" + +/*! + * @brief Check if FSP RM command queue is empty + * + * @param[in] device nvswitch device pointer + * + * @return NV_TRUE if queue is empty, NV_FALSE otherwise + */ +static NvBool +_nvswitch_fsp_is_queue_empty +( + nvswitch_device *device +) +{ + NvU32 cmdqHead, cmdqTail; + + nvswitch_fsp_get_cmdq_head_tail(device, &cmdqHead, &cmdqTail); + + // FSP will set QUEUE_HEAD = TAIL after each packet is received + return (cmdqHead == cmdqTail); +} + +/*! + * @brief Check if FSP RM message queue is empty + * + * @param[in] device nvswitch_device pointer + * + * @return NV_TRUE if queue is empty, NV_FALSE otherwise + */ +static NvBool +_nvswitch_fsp_is_msgq_empty +( + nvswitch_device *device +) +{ + NvU32 msgqHead, msgqTail; + + nvswitch_fsp_get_msgq_head_tail(device, &msgqHead, &msgqTail); + return (msgqHead == msgqTail); +} + +/*! + * @brief Wait for FSP RM command queue to be empty + * + * @param[in] device nvswitch_device pointer + * + * @return NVL_SUCCESS, or NV_ERR_TIMEOUT + */ +static NvlStatus +_nvswitch_fsp_poll_for_queue_empty +( + nvswitch_device *device +) +{ + NvBool bKeepPolling; + NvBool bMsgqEmpty; + NvBool bCmdqEmpty; + NVSWITCH_TIMEOUT timeout; + + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + do + { + bKeepPolling = nvswitch_timeout_check(&timeout) ? NV_FALSE : NV_TRUE; + + bMsgqEmpty = _nvswitch_fsp_is_msgq_empty(device); + bCmdqEmpty = _nvswitch_fsp_is_queue_empty(device); + + // + // For now we assume that any response from FSP before sending a command + // indicates an error and we should abort. + // + if (!bCmdqEmpty && !bMsgqEmpty) + { + nvswitch_fsp_read_message(device, NULL, 0); + NVSWITCH_PRINT(device, ERROR, "Received error message from FSP while waiting for CMDQ to be empty.\n"); + return -NVL_ERR_GENERIC; + } + + if (bCmdqEmpty) + { + break; + } + + if (!bKeepPolling) + { + NVSWITCH_PRINT(device, ERROR, "Timed out waiting for FSP command queue to be empty.\n"); + return -NVL_ERR_GENERIC; + } + + nvswitch_os_sleep(1); + } + while(bKeepPolling); + + return NVL_SUCCESS; +} + +/*! + * @brief Poll for response from FSP via RM message queue + * + * @param[in] device nvswitch_device pointer + * + * @return NVL_SUCCESS, or NV_ERR_TIMEOUT + */ +static NvlStatus +_nvswitch_fsp_poll_for_response +( + nvswitch_device *device +) +{ + NvBool bKeepPolling; + NVSWITCH_TIMEOUT timeout; + + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + + do + { + bKeepPolling = nvswitch_timeout_check(&timeout) ? NV_FALSE : NV_TRUE; + + // + // Poll for message queue to wait for FSP's reply + // + if (!_nvswitch_fsp_is_msgq_empty(device)) + { + break; + } + + if (!bKeepPolling) + { + NVSWITCH_PRINT(device, ERROR, "FSP command timed out.\n"); + return -NVL_ERR_GENERIC; + } + + nvswitch_os_sleep(1); + } + while(bKeepPolling); + + return NVL_SUCCESS; +} + +/*! + * @brief Read and process message from FSP via RM message queue. + * + * Supports both single and multi-packet message. For multi-packet messages, this + * loops until all packets are received, polling at each iteration for the next + * packet to come in. If a buffer is provided, the message payload will be + * returned there. + * + * @note: For multi-packet messages, a buffer in which the message payload will + * be reconstructed must be provided. + * + * @param[in] device nvswitch_device pointer + * @param[in/out] pPayloadBuffer Buffer in which to return message payload + * @param[in] payloadBufferSize Payload buffer size + * + * @return NVL_SUCCESS, NV_ERR_INVALID_DATA, NV_ERR_INSUFFICIENT_RESOURCES, or errors + * from functions called within + */ +NvlStatus +nvswitch_fsp_read_message +( + nvswitch_device *device, + NvU8 *pPayloadBuffer, + NvU32 payloadBufferSize +) +{ + NvU8 *pPacketBuffer; + NvlStatus status; + NvU32 totalPayloadSize = 0; + NvU8 *pMessagePayload; + NvU8 packetState = MCTP_PACKET_STATE_START; + + if (_nvswitch_fsp_is_msgq_empty(device)) + { + NVSWITCH_PRINT(device, WARN, "Tried to read FSP response but MSG queue is empty\n"); + return NVL_SUCCESS; + } + + pPacketBuffer = nvswitch_os_malloc(nvswitch_fsp_get_channel_size(device)); + if (pPacketBuffer == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "Failed to allocate memory for GLT!!\n"); + return -NVL_NO_MEM; + } + + while ((packetState != MCTP_PACKET_STATE_END) && (packetState != MCTP_PACKET_STATE_SINGLE_PACKET)) + { + NvU32 msgqHead, msgqTail; + NvU32 packetSize; + NvU32 curPayloadSize; + NvU8 curHeaderSize; + NvU8 tag; + + // Wait for next packet + status = _nvswitch_fsp_poll_for_response(device); + if (status != NVL_SUCCESS) + { + goto done; + } + + nvswitch_fsp_get_msgq_head_tail(device, &msgqHead, &msgqTail); + + // Tail points to last DWORD in packet, not DWORD immediately following it + packetSize = (msgqTail - msgqHead) + sizeof(NvU32); + + if ((packetSize < sizeof(NvU32)) || + (packetSize > nvswitch_fsp_get_channel_size(device))) + { + NVSWITCH_PRINT(device, ERROR, "FSP response packet is invalid size: size=0x%x bytes\n", packetSize); + status = -NVL_ERR_INVALID_STATE; + goto done; + } + + nvswitch_fsp_read_from_emem(device, pPacketBuffer, packetSize); + + status = nvswitch_fsp_get_packet_info(device, pPacketBuffer, packetSize, &packetState, &tag); + if (status != NVL_SUCCESS) + { + goto done; + } + + if ((packetState == MCTP_PACKET_STATE_START) || (packetState == MCTP_PACKET_STATE_SINGLE_PACKET)) + { + // Packet contains payload header + curHeaderSize = sizeof(MCTP_HEADER); + } + else + { + curHeaderSize = sizeof(NvU32); + } + + curPayloadSize = packetSize - curHeaderSize; + + if ((pPayloadBuffer == NULL) && (packetState != MCTP_PACKET_STATE_SINGLE_PACKET)) + { + NVSWITCH_PRINT(device, ERROR, "No buffer provided when receiving multi-packet message. Buffer needed to reconstruct message\n"); + status = -NVL_ERR_GENERIC; + goto done; + } + + if (pPayloadBuffer != NULL) + { + if (payloadBufferSize < (totalPayloadSize + curPayloadSize)) + { + NVSWITCH_PRINT(device, ERROR, "Buffer provided for message payload too small. Payload size: 0x%x Buffer size: 0x%x\n", + totalPayloadSize + curPayloadSize, payloadBufferSize); + status = -NVL_ERR_GENERIC; + goto done; + } + nvswitch_os_memcpy(pPayloadBuffer + totalPayloadSize, + pPacketBuffer + curHeaderSize, curPayloadSize); + } + totalPayloadSize += curPayloadSize; + + // Set TAIL = HEAD to indicate CPU received message + nvswitch_fsp_update_msgq_head_tail(device, msgqHead, msgqHead); + } + + pMessagePayload = (pPayloadBuffer == NULL) ? (pPacketBuffer + sizeof(MCTP_HEADER)) : pPayloadBuffer; + + status = nvswitch_fsp_process_nvdm_msg(device, pMessagePayload, totalPayloadSize); + +done: + nvswitch_os_free(pPacketBuffer); + return status; +} + +/*! + * @brief Send one MCTP packet to FSP via EMEM + * + * @param[in] device nvswitch_device pointer + * @param[in] pPacket MCTP packet + * @param[in] packetSize MCTP packet size in bytes + * + * @return NVL_SUCCESS, or NV_ERR_INSUFFICIENT_RESOURCES + */ +NvlStatus +nvswitch_fsp_send_packet +( + nvswitch_device *device, + NvU8 *pPacket, + NvU32 packetSize +) +{ + NvU32 paddedSize; + NvU8 *pBuffer = NULL; + NV_STATUS status = NVL_SUCCESS; + + // Check that queue is ready to receive data + status = _nvswitch_fsp_poll_for_queue_empty(device); + if (status != NVL_SUCCESS) + { + return -NVL_ERR_GENERIC; + } + + // Pad to align size to 4-bytes boundary since EMEMC increments by DWORDS + paddedSize = NV_ALIGN_UP(packetSize, sizeof(NvU32)); + pBuffer = nvswitch_os_malloc(paddedSize); + if (pBuffer == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "Failed to allocate memory!!\n"); + return -NVL_NO_MEM; + } + nvswitch_os_memset(pBuffer, 0, paddedSize); + nvswitch_os_memcpy(pBuffer, pPacket, paddedSize); + + nvswitch_fsp_write_to_emem(device, pBuffer, paddedSize); + + // Update HEAD and TAIL with new EMEM offset; RM always starts at offset 0. + nvswitch_fsp_update_cmdq_head_tail(device, 0, paddedSize - sizeof(NvU32)); + + nvswitch_os_free(pBuffer); + return status; +} + +/*! + * @brief Send a MCTP message to FSP via EMEM, and read response + * + * + * Response payload buffer is optional if response fits in a single packet. + * + * @param[in] device nvswitch_device pointer + * @param[in] pPayload Pointer to message payload + * @param[in] size Message payload size + * @param[in] nvdmType NVDM type of message being sent + * @param[in] pResponsePayload Buffer in which to return response payload + * @param[in] responseBufferSize Response payload buffer size + * + * @return NVL_SUCCESS, or NV_ERR_* + */ +NvlStatus +nvswitch_fsp_send_and_read_message +( + nvswitch_device *device, + NvU8 *pPayload, + NvU32 size, + NvU32 nvdmType, + NvU8 *pResponsePayload, + NvU32 responseBufferSize +) +{ + NvU32 dataSent, dataRemaining; + NvU32 packetPayloadCapacity; + NvU32 curPayloadSize; + NvU32 headerSize; + NvU32 fspEmemChannelSize; + NvBool bSinglePacket; + NV_STATUS status; + NvU8 *pBuffer = NULL; + NvU8 seq = 0; + NvU8 seid = 0; + + // Allocate buffer of same size as channel + fspEmemChannelSize = nvswitch_fsp_get_channel_size(device); + pBuffer = nvswitch_os_malloc(fspEmemChannelSize); + if (pBuffer == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to allocate memory!!\n", + __FUNCTION__); + return -NVL_NO_MEM; + + } + + nvswitch_os_memset(pBuffer, 0, fspEmemChannelSize); + + // + // Check if message will fit in single packet + // We lose 2 DWORDS to MCTP and NVDM headers + // + headerSize = 2 * sizeof(NvU32); + packetPayloadCapacity = fspEmemChannelSize - headerSize; + bSinglePacket = (size <= packetPayloadCapacity); + + // First packet + seid = nvswitch_fsp_nvdm_to_seid(device, nvdmType); + ((NvU32 *)pBuffer)[0] = nvswitch_fsp_create_mctp_header(device, 1, (NvU8)bSinglePacket, seid, seq); // SOM=1,EOM=?,SEID,SEQ=0 + ((NvU32 *)pBuffer)[1] = nvswitch_fsp_create_nvdm_header(device, nvdmType); + + curPayloadSize = NV_MIN(size, packetPayloadCapacity); + nvswitch_os_memcpy(pBuffer + headerSize, pPayload, curPayloadSize); + + status = nvswitch_fsp_send_packet(device, pBuffer, curPayloadSize + headerSize); + if (status != NVL_SUCCESS) + { + goto failed; + } + + if (!bSinglePacket) + { + // Multi packet case + dataSent = curPayloadSize; + dataRemaining = size - dataSent; + headerSize = sizeof(NvU32); // No longer need NVDM header + packetPayloadCapacity = fspEmemChannelSize - headerSize; + + while (dataRemaining > 0) + { + NvBool bLastPacket = (dataRemaining <= packetPayloadCapacity); + curPayloadSize = (bLastPacket) ? dataRemaining : packetPayloadCapacity; + + nvswitch_os_memset(pBuffer, 0, fspEmemChannelSize); + ((NvU32 *)pBuffer)[0] = nvswitch_fsp_create_mctp_header(device, 0, (NvU8)bLastPacket, seid, (++seq) % 4); + + nvswitch_os_memcpy(pBuffer + headerSize, pPayload + dataSent, curPayloadSize); + + status = nvswitch_fsp_send_packet(device, pBuffer, curPayloadSize + headerSize); + if (status != NVL_SUCCESS) + { + goto failed; + } + + dataSent += curPayloadSize; + dataRemaining -= curPayloadSize; + } + } + + status = _nvswitch_fsp_poll_for_response(device); + if (status != NVL_SUCCESS) + { + goto failed; + } + status = nvswitch_fsp_read_message(device, pResponsePayload, responseBufferSize); + +failed: + nvswitch_os_free(pBuffer); + + return status; +} diff --git a/src/common/nvswitch/kernel/inc/boards_nvswitch.h b/src/common/nvswitch/kernel/inc/boards_nvswitch.h new file mode 100644 index 0000000000..984ffa4556 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/boards_nvswitch.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _BOARDS_NVSWITCH_H_ +#define _BOARDS_NVSWITCH_H_ + +#include "common_nvswitch.h" + +// +// NVSwitch board IDs +// +#define NVSWITCH_BOARD_UNKNOWN 0x0 + +#define NVSWITCH_BOARD_LS10_4840_0000_PC0 0x0396 +#define NVSWITCH_BOARD_LS10_4840_0072_STA 0x0398 +#define NVSWITCH_BOARD_LS10_5612_0002_890 0x03B7 +#define NVSWITCH_BOARD_LS10_5612_0012_895 0x03B8 +#define NVSWITCH_BOARD_LS10_5612_0002_ES 0x03D6 +#define NVSWITCH_BOARD_LS10_4697_0000_895 0x03B9 +#define NVSWITCH_BOARD_LS10_4262_0000_895 0x04FE + +#define NVSWITCH_BOARD_UNKNOWN_NAME "UNKNOWN" + +#define NVSWITCH_BOARD_LS10_4840_0000_PC0_NAME "LS10_4840_0000_PC0" +#define NVSWITCH_BOARD_LS10_4840_0072_STA_NAME "LS10_4840_0072_STA" +#define NVSWITCH_BOARD_LS10_5612_0002_890_NAME "LS10_5612_0002_890" +#define NVSWITCH_BOARD_LS10_5612_0012_895_NAME "LS10_5612_0012_895" +#define NVSWITCH_BOARD_LS10_5612_0002_ES_NAME "LS10_5612_0002_ES" +#define NVSWITCH_BOARD_LS10_4697_0000_895_NAME "LS10_4697_0000_895" +#define NVSWITCH_BOARD_LS10_4262_0000_895_NAME "LS10_4262_0000_895" + +#endif // _BOARDS_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/cci/cci_cables_nvswitch.h b/src/common/nvswitch/kernel/inc/cci/cci_cables_nvswitch.h new file mode 100644 index 0000000000..8d9b2bf831 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/cci/cci_cables_nvswitch.h @@ -0,0 +1,122 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CCI_CABLES_NVSWITCH_H_ +#define _CCI_CABLES_NVSWITCH_H_ + +#include "cci_nvswitch.h" +#include "nvlink_errors.h" +#include "nvtypes.h" +#include "nvfixedtypes.h" +#include "nvstatus.h" +#include "ctrl_dev_nvswitch.h" +#include "export_nvswitch.h" +#include "soe/cci/cci_onboard_phases.h" + +#define CABLE_TYPE_INVALID 0x0 +#define CABLE_TYPE_COPPER 0x1 +#define CABLE_TYPE_DIRECT 0x2 +#define CABLE_TYPE_OPTICAL 0x3 + +#define CCI_ONBOARD_MAX_ATTEMPTS (device->regkeys.cci_max_onboard_attempts) +#define CCI_ONBOARD_PHASE_POLL_MAX (5) + +// Union of different onboarding subphases +typedef union CCI_MODULE_ONBOARD_SUBPHASE +{ + CCI_MODULE_ONBOARD_SUBPHASE_OPTICAL optical; +} CCI_MODULE_ONBOARD_SUBPHASE; + +// Defines the phase of onboarding that a module is in +typedef struct cci_module_onboard_state +{ + CCI_MODULE_ONBOARD_PHASE onboardPhase; + CCI_MODULE_ONBOARD_SUBPHASE onboardSubPhase; +} CCI_MODULE_ONBOARD_STATE; + +// Used to manage the SLEEP phase of a module +typedef struct cci_module_onboard_sleep_state +{ + NvU64 wakeUpTimestamp; + CCI_MODULE_ONBOARD_STATE returnState; +} CCI_MODULE_ONBOARD_SLEEP_STATE; + +// Stores discovered errors in regards to module onboarding +typedef struct cci_module_onboard_error +{ + NvBool bErrorsChecked; + NvBool bOnboardFailure; + CCI_MODULE_ONBOARD_STATE failedOnboardState; +} CCI_MODULE_ONBOARD_ERROR; + +// Defines the current state of a module +typedef struct cci_module_state +{ + NvU8 onboardAttempts; + NvBool bModuleIdentified; + NvBool bModuleOnboarded; + NvBool bLinkTrainDeferred; + NvBool bPartialLinkTrainComplete; + NvBool bLinkTrainComplete; + NvU8 preTrainCounter; + NvU64 linkTrainMask; + NvU64 linkMaskActiveSaved; + CCI_MODULE_ONBOARD_STATE currOnboardState; + CCI_MODULE_ONBOARD_STATE prevOnboardState; + CCI_MODULE_ONBOARD_SLEEP_STATE sleepState; + CCI_MODULE_ONBOARD_ERROR onboardError; +} CCI_MODULE_STATE; + + +void cciModulesOnboardInit(nvswitch_device *device); +void cciModulesOnboardCallback(nvswitch_device *device); + +void cciCablesInitializeCopperAsync(nvswitch_device *device, NvU8 moduleId); +void cciCablesInitializeDirectAsync(nvswitch_device *device, NvU8 moduleId); +void cciCablesInitializeOpticalAsync(nvswitch_device *device, NvU8 moduleId); + +NvBool cciLinkTrainIdle(nvswitch_device *device, NvU8 linkId); +NvBool cciModuleOnboardFailed(nvswitch_device *device, NvU8 moduleId); + +NvlStatus cciRequestALI(nvswitch_device *device, NvU64 linkMaskTrain); + +void cciModuleOnboardShutdown(nvswitch_device *device); + +// For phases that have work that needs to be performed in SOE +NvlStatus cciModulesOnboardSOE(nvswitch_device *device, NvU8 moduleId); + +// Error management +void cciModuleOnboardCheckErrors(nvswitch_device *device, NvU8 moduleId); + +// Helper functions +NvlStatus cciSetLedsInitialize(nvswitch_device *device, NvU8 moduleId); + +void cciModuleOnboardPerformPhaseTransitionAsync(nvswitch_device *device, NvU8 moduleId, + CCI_MODULE_ONBOARD_STATE nextState); +void cciModuleOnboardSleepAsync(nvswitch_device *device, NvU8 moduleId, NvU32 ms, + CCI_MODULE_ONBOARD_STATE returnState); +void cciModuleOnboardPerformPhaseAsync(nvswitch_device *device, NvU8 moduleId, + NvlStatus (*func)(nvswitch_device *, NvU8 moduleId), + CCI_MODULE_ONBOARD_STATE nextStateSuccess, + CCI_MODULE_ONBOARD_STATE nextStateFail); +#endif //_CCI_CABLES_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/cci/cci_cdb_async_nvswitch.h b/src/common/nvswitch/kernel/inc/cci/cci_cdb_async_nvswitch.h new file mode 100644 index 0000000000..00a5a949da --- /dev/null +++ b/src/common/nvswitch/kernel/inc/cci/cci_cdb_async_nvswitch.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CCI_CDB_ASYNC_NVSWITCH_H_ +#define _CCI_CDB_ASYNC_NVSWITCH_H_ + +#include "ls10/cci_ls10.h" + +#include "nvlink_errors.h" +#include "nvtypes.h" + +typedef enum cci_cdb_phase +{ + CCI_CDB_PHASE_IDLE = 0x0, + CCI_CDB_PHASE_CHECK_READY, + CCI_CDB_PHASE_SEND_COMMAND, + CCI_CDB_PHASE_GET_RESPONSE, + CCI_CDB_PHASE_CHECK_DONE +} CCI_CDB_PHASE; + +typedef struct cci_cdb_state +{ + CCI_CDB_PHASE cdbPhase; + NvU8 client; + NvU8 laneMasksPending[NVSWITCH_CCI_NUM_LINKS_PER_OSFP_LS10]; + NvBool freeze_maintenance; + NvBool restart_training; + NvBool nvlink_mode; +} CCI_CDB_STATE; + +// Should be called at some regular polling rate +void cciProcessCDBCallback(nvswitch_device *device); + +NvlStatus cciConfigureNvlinkModeAsync(nvswitch_device *device, NvU32 client, NvU8 linkId, NvBool freeze_maintenance, NvBool restart_training, NvBool nvlink_mode); +#endif //_CCI_CDB_ASYNC_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/cci/cci_nvswitch.h b/src/common/nvswitch/kernel/inc/cci/cci_nvswitch.h new file mode 100644 index 0000000000..4d6620aaec --- /dev/null +++ b/src/common/nvswitch/kernel/inc/cci/cci_nvswitch.h @@ -0,0 +1,118 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CCI_NVSWITCH_H_ +#define _CCI_NVSWITCH_H_ + +#include "common_nvswitch.h" + +#include "nvlink_errors.h" +#include "nvtypes.h" +#include "nvfixedtypes.h" +#include "nvstatus.h" +#include "ctrl_dev_nvswitch.h" +#include "export_nvswitch.h" + +typedef struct CCI CCI, *PCCI; +struct nvswitch_device; + +// Polling Callback ids +#define NVSWITCH_CCI_CALLBACK_SMBPBI 0 +#define NVSWITCH_CCI_CALLBACK_LINK_STATE_UPDATE 1 +#define NVSWITCH_CCI_CALLBACK_CDB 2 +#define NVSWITCH_CCI_CALLBACK_NUM_MAX 3 + +// +// Determines the range of frequencies that functions can +// run at. +// This rate must be divisible by client provided frequencies. +// +#define NVSWITCH_CCI_POLLING_RATE_HZ 50 + +// CCI LED states on LS10 Systems +#define CCI_LED_STATE_LOCATE 0U +#define CCI_LED_STATE_FAULT 1U +#define CCI_LED_STATE_OFF 2U +#define CCI_LED_STATE_INITIALIZE 3U +#define CCI_LED_STATE_UP_WARM 4U +#define CCI_LED_STATE_UP_ACTIVE 5U +#define CCI_NUM_LED_STATES 6U + +// +// Mapping between XCVR module, nvlink-id, xvcr lane-mask +// +typedef struct nvswitch_cci_module_link_lane_map +{ + NvU8 moduleId; + NvU8 linkId; + NvU8 laneMask; +} NVSWITCH_CCI_MODULE_LINK_LANE_MAP; + +CCI* cciAllocNew(void); +NvBool cciSupported(nvswitch_device *device); +NvlStatus cciInit(nvswitch_device *device, PCCI pCci, NvU32 pci_device_id); +NvlStatus cciLoad(nvswitch_device *device); +void cciDestroy(nvswitch_device *device, PCCI pCci); +NvlStatus cciRead(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU32 addr, NvU32 length, NvU8 *pVal); +NvlStatus cciWrite(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU32 addr, NvU32 length, NvU8 *pVal); +NvlStatus cciSetBankAndPage(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 bank, NvU8 page); +NvlStatus cciSendCDBCommandAndGetResponse(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU32 command, NvU32 payLength, NvU8 *payload, NvU32 *resLength, NvU8 *response, NvBool padding); +NvlStatus cciSendCDBCommand(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU32 command, NvU32 length, NvU8 *pValArray, NvBool padding); +NvlStatus cciGetBankAndPage(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 *pBank, NvU8 *pPage); +NvlStatus cciGetCDBResponse(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 *response, NvU32 *resLength); +NvlStatus cciGetCDBStatus(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 *pStatus); +NvlStatus cciWaitForCDBComplete(nvswitch_device *device, NvU32 client, NvU32 osfp); +NvlStatus cciRegisterCallback(nvswitch_device *device, NvU32 callbackId, void (*functionPtr)(nvswitch_device *device), NvU32 rateHz); + +NvlStatus cciModuleEject (nvswitch_device *device, NvU8 moduleId); +NvBool cciIsLinkManaged (nvswitch_device *device, NvU32 linkNumber); +NvlStatus cciGetLinkMode (nvswitch_device *device, NvU32 linkNumber, NvU64 *mode); +NvBool cciReportLinkErrors (nvswitch_device *device, NvU32 linkNumber); +NvlStatus cciGetFWRevisions (nvswitch_device *device, NvU32 client, NvU32 linkId, NVSWITCH_CCI_GET_FW_REVISIONS *pRevisions); +NvlStatus cciGetXcvrFWRevisions (nvswitch_device *device, NvU32 client, NvU32 osfp, NVSWITCH_CCI_GET_FW_REVISIONS *pRevisions); +void cciDetectXcvrsPresent (nvswitch_device *device); +NvlStatus cciGetXcvrMask (nvswitch_device *device, NvU32 *pMaskAll, NvU32 *pMaskPresent); +NvlStatus cciGetXcvrLedState (nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 *pLedState); +NvlStatus cciSetXcvrLedState (nvswitch_device *device, NvU32 client, NvU32 osfp, NvBool bSetLocate); +NvlStatus cciSetNextXcvrLedState (nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 nextLedState); +NvlStatus cciConfigureNvlinkMode (nvswitch_device *device, NvU32 client, NvU32 linkId, NvBool bTx, NvBool freeze_maintenance, NvBool restart_training, NvBool nvlink_mode); +NvlStatus cciConfigureNvlinkModeModule (nvswitch_device *device, NvU32 client, NvU8 moduleId, NvU64 linkMask, NvBool freeze_maintenance, NvBool restart_training, NvBool nvlink_mode); +NvBool cciCheckForPreTraining (nvswitch_device *device, NvU32 client, NvU32 linkId, NvBool bTx); +NvlStatus cciApplyControlSetValues (nvswitch_device *device, NvU32 client, NvU32 moduleMask); +NvlStatus cciGetGradingValues (nvswitch_device *device, NvU32 client, NvU32 linkId, NvU8 *laneMask, NVSWITCH_CCI_GRADING_VALUES *pGrading); + +NvlStatus cciGetCageMapping (nvswitch_device *device, NvU8 cageIndex, NvU64 *pLinkMask, NvU64 *pEncodedValue); +NvBool cciCmisAccessTryLock (nvswitch_device *device, NvU8 cageIndex); +void cciCmisAccessReleaseLock (nvswitch_device *device, NvU8 cageIndex); +NvlStatus cciCmisRead (nvswitch_device *device, NvU8 cageIndex, NvU8 bank, NvU8 page, NvU8 address, NvU8 count, NvU8 *pData); +NvlStatus cciCmisWrite (nvswitch_device *device, NvU8 cageIndex, NvU8 bank, NvU8 page, NvU8 address, NvU8 count, NvU8 *pData); +NvlStatus cciCmisCageBezelMarking (nvswitch_device *device, NvU8 cageIndex, char *pBezelMarking); + +// CCI Control calls +NvlStatus nvswitch_ctrl_get_cci_fw_revisions (nvswitch_device *device, NVSWITCH_CCI_GET_FW_REVISION_PARAMS *pParams); +NvlStatus nvswitch_ctrl_get_grading_values (nvswitch_device *device, NVSWITCH_CCI_GET_GRADING_VALUES_PARAMS *pParams); +NvlStatus nvswitch_ctrl_get_ports_cpld_info (nvswitch_device *device, NVSWITCH_CCI_GET_PORTS_CPLD_INFO_PARAMS *pParams); +NvlStatus nvswitch_ctrl_set_locate_led (nvswitch_device *device, NVSWITCH_CCI_SET_LOCATE_LED_PARAMS *pParams); +NvlStatus nvswitch_ctrl_cci_request_ali (nvswitch_device *device, NVSWITCH_REQUEST_ALI_PARAMS *pParams); + +#endif //_CCI_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/cci/cci_priv_nvswitch.h b/src/common/nvswitch/kernel/inc/cci/cci_priv_nvswitch.h new file mode 100644 index 0000000000..1fd31501e9 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/cci/cci_priv_nvswitch.h @@ -0,0 +1,132 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CCI_PRIV_NVSWITCH_H_ +#define _CCI_PRIV_NVSWITCH_H_ + +#include "common_nvswitch.h" + +#include "nvtypes.h" +#include "cci/cci_nvswitch.h" +#include "cci/cci_cdb_async_nvswitch.h" +#include "cci/cci_cables_nvswitch.h" +#include "soe/cci/cpld_machx03.h" +#include "soe/cci/cci_cmis.h" + +// +// CCI is the top-level management state for all cable controllers on a device. +// The management tasks related to cable controllers is encapsulated by a PCS +// or Platform Cable System, for which CCI is largely a container. +// + +#define NVSWITCH_CCI_LINK_NUM_MAX 64 +#define NVSWITCH_CCI_OSFP_NUM_MAX 32 + +// Vendor specified number(Used across all LR10/LS10 systems) +#define NVSWITCH_CCI_CDB_CMD_ID 0xcd19 + +// LS10 Saved LED state +#define CCI_LED_STATE_LED_A CPLD_MACHXO3_LED_STATE_REG_LED_A +#define CCI_LED_STATE_LED_B CPLD_MACHXO3_LED_STATE_REG_LED_B + +// Timeout for CMIS access locks +#define NVSWITCH_CCI_CMIS_LOCK_TIMEOUT (10 * NVSWITCH_INTERVAL_1SEC_IN_NS) + +// Cable Controller Interface +struct CCI +{ + // Links that are supported by CCI. The value here is defined in the BIOS + // and is a static property of the system. See repeater bit in NVLink. + NvU64 linkMask; + + // ================================================================ + // === State below this line has been moved and can be deleted. === + // ================================================================ + + // Other member variables specific to CCI go here + NvBool bDiscovered; + NvBool bSupported; + NvBool bInitialized; + NvU32 osfpMaskAll; // All the possible module positions + NvU32 osfpMaskPresent; // Currently present modules + NvU32 cagesMask; // All the possible module cage positions + NvU32 modulesMask; // Currently present modules(currently mirrors osfpMaskPresent) + NvU32 numLinks; + NVSWITCH_CCI_MODULE_LINK_LANE_MAP *osfp_map; + struct NVSWITCH_I2C_DEVICE_DESCRIPTOR *osfp_i2c_info; + NvU32 osfp_map_size; + NvU32 osfp_num; + + struct { + void (*functionPtr)(struct nvswitch_device*); + NvU32 interval; + } callbackList[NVSWITCH_CCI_CALLBACK_NUM_MAX]; + NvU32 callbackCounter; + NvU8 xcvrCurrentLedState[NVSWITCH_CCI_OSFP_NUM_MAX]; + NvU8 xcvrNextLedState[NVSWITCH_CCI_OSFP_NUM_MAX]; + NvU64 tpCounterPreviousSum[NVSWITCH_CCI_LINK_NUM_MAX]; + + // LS10 cable initialization + NvU8 cableType[NVSWITCH_CCI_OSFP_NUM_MAX]; + NvBool rxDetEnable[NVSWITCH_CCI_OSFP_NUM_MAX]; + + // LS10 Async module onboarding + CCI_MODULE_STATE moduleState[NVSWITCH_CCI_OSFP_NUM_MAX]; + + // LS10 Async CDB management + CCI_CDB_STATE cdbState[NVSWITCH_CCI_OSFP_NUM_MAX]; + + // LS10 Module info + NvBool isFlatMemory[NVSWITCH_CCI_OSFP_NUM_MAX]; + struct { + NvBool bLocked; + NvU32 pid; + NvU64 timestamp; + } cmisAccessLock[NVSWITCH_CCI_OSFP_NUM_MAX]; + + // LS10 link training mode + NvBool bModeContinuousALI[NVSWITCH_CCI_OSFP_NUM_MAX]; + NvU64 linkMaskAliRequested; + + // LS10 Module HW state + NvBool isFaulty[NVSWITCH_CCI_OSFP_NUM_MAX]; + +}; + +// Helper functions for CCI subcomponents +NvlStatus cciGetModuleId(nvswitch_device *device, NvU32 linkId, NvU32 *pModuleId); +NvBool cciModulePresent(nvswitch_device *device, NvU32 moduleId); +void cciGetModulePresenceChange(nvswitch_device *device, NvU32 *pModuleMask); +NvlStatus cciResetModule(nvswitch_device *device, NvU32 moduleId); +NvlStatus cciGetXcvrFWInfo(nvswitch_device *device, NvU32 moduleId, NvU8 *pInfo); +NvlStatus cciSetLPMode(nvswitch_device *device, NvU8 moduleId, NvBool bAssert); +NvBool cciCheckLPMode(nvswitch_device *device, NvU8 moduleId); +void cciPingModules(nvswitch_device *device, NvU32 *pMaskPresent); +void cciGetAllLinks(nvswitch_device *device, NvU64 *pLinkMaskAll); +NvlStatus cciGetModuleMask(nvswitch_device *device, NvU64 linkMask, NvU32 *pModuleMask); +NvBool cciCheckXcvrForLinkTraffic(nvswitch_device *device, NvU32 osfp, NvU64 linkMask); +NvlStatus cciGetLaneMask(nvswitch_device *device, NvU32 linkId, NvU8 *laneMask); +NvBool cciModuleHWGood(nvswitch_device *device, NvU32 moduleId); +void cciSetModulePower(nvswitch_device *device, NvU32 moduleId, NvBool bPowerOn); + +#endif //_CCI_PRIV_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/common_nvswitch.h b/src/common/nvswitch/kernel/inc/common_nvswitch.h index d654bda7b1..6a7e57dbcf 100644 --- a/src/common/nvswitch/kernel/inc/common_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/common_nvswitch.h @@ -39,6 +39,9 @@ #include "spi_nvswitch.h" #include "smbpbi_nvswitch.h" #include "nvCpuUuid.h" +#include "fsprpc_nvswitch.h" + +#include "soe/cci/cpld_machx03.h" #define NVSWITCH_GET_BIT(v, p) (((v) >> (p)) & 1) #define NVSWITCH_SET_BIT(v, p) ((v) | NVBIT(p)) @@ -121,6 +124,9 @@ static NV_INLINE void nvswitch_clear_flags(NvU32 *val, NvU32 flags) nvswitch_os_malloc_trace(_size, NULL, 0) #endif +// LS10 Saved LED state +#define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED + // // This macro should be used to check assertion statements and print Error messages. // @@ -248,6 +254,11 @@ typedef struct NvU32 soe_disable; NvU32 soe_enable; NvU32 soe_boot_core; + NvU32 cci_control; + NvU32 cci_link_train_disable_mask; + NvU32 cci_link_train_disable_mask2; + NvU32 cci_max_onboard_attempts; + NvU32 cci_error_log_enable; NvU32 latency_counter; NvU32 nvlink_speed_control; NvU32 inforom_bbx_periodic_flush; @@ -404,6 +415,12 @@ struct nvswitch_device // SOE FLCNABLE *pSoe; + // CCI + struct CCI *pCci; + + NvU8 current_led_state; + NvU8 next_led_state; + NvU64 tp_counter_previous_sum[NVSWITCH_NVLINK_MAX_LINKS]; // DMA NvU32 dma_addr_width; @@ -418,6 +435,7 @@ struct nvswitch_device struct smbpbi *pSmbpbi; // NVSWITCH_LINK_TYPE + NvBool bModeContinuousALI; NVSWITCH_LINK_TYPE link[NVSWITCH_MAX_LINK_COUNT]; // PLL @@ -566,6 +584,14 @@ do \ } \ } while(0) +// Access link LED states on LS10 Systems +#define ACCESS_LINK_LED_STATE_FAULT 0U +#define ACCESS_LINK_LED_STATE_OFF 1U +#define ACCESS_LINK_LED_STATE_INITIALIZE 2U +#define ACCESS_LINK_LED_STATE_UP_WARM 3U +#define ACCESS_LINK_LED_STATE_UP_ACTIVE 4U +#define ACCESS_LINK_NUM_LED_STATES 5U + #define NVSWITCH_GET_CAP(tbl,cap,field) (((NvU8)tbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) & (0?cap##field)) #define NVSWITCH_SET_CAP(tbl,cap,field) ((tbl[((1?cap##field)>=cap##_TBL_SIZE) ? 0/0 : (1?cap##field)]) |= (0?cap##field)) diff --git a/src/common/nvswitch/kernel/inc/fsprpc_nvswitch.h b/src/common/nvswitch/kernel/inc/fsprpc_nvswitch.h new file mode 100644 index 0000000000..d97a034e98 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/fsprpc_nvswitch.h @@ -0,0 +1,92 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSPRPC_NVSWITCH_H_ +#define _FSPRPC_NVSWITCH_H_ + +#define FSP_OK (0x00U) +#define FSP_ERR_IFS_ERR_INVALID_STATE (0x9EU) +#define FSP_ERR_IFR_FILE_NOT_FOUND (0x9FU) +#define FSP_ERR_IFS_ERR_NOT_SUPPORTED (0xA0U) +#define FSP_ERR_IFS_ERR_INVALID_DATA (0xA1U) + +#pragma pack(1) +typedef struct mctp_header +{ + NvU32 constBlob; + NvU8 msgType; + NvU16 vendorId; +} MCTP_HEADER; + +// Needed to remove unnecessary padding +#pragma pack(1) +typedef struct nvdm_payload_cot +{ + NvU16 version; + NvU16 size; + NvU64 gspFmcSysmemOffset; + NvU64 frtsSysmemOffset; + NvU32 frtsSysmemSize; + + // Note this is an offset from the end of FB + NvU64 frtsVidmemOffset; + NvU32 frtsVidmemSize; + + // Authentication related fields + NvU32 hash384[12]; + NvU32 publicKey[96]; + NvU32 signature[96]; + + NvU64 gspBootArgsSysmemOffset; +} NVDM_PAYLOAD_COT; +#pragma pack() + +typedef struct nvdm_packet +{ + NvU8 nvdmType; + + // We can make this a union when adding more NVDM payloads + NVDM_PAYLOAD_COT cotPayload; +} NVDM_PACKET; + +// The structure cannot have embedded pointers to send as byte stream +typedef struct mctp_packet +{ + MCTP_HEADER header; + NVDM_PACKET nvdmPacket; +} MCTP_PACKET, *PMCTP_PACKET; + +// Type of packet, can either be SOM, EOM, neither, or both (1-packet messages) +typedef enum mctp_packet_state +{ + MCTP_PACKET_STATE_START, + MCTP_PACKET_STATE_INTERMEDIATE, + MCTP_PACKET_STATE_END, + MCTP_PACKET_STATE_SINGLE_PACKET +} MCTP_PACKET_STATE, *PMCTP_PACKET_STATE; + +NvlStatus nvswitch_fsp_read_message(nvswitch_device *device, NvU8 *pPayloadBuffer, NvU32 payloadBufferSize); +NvlStatus nvswitch_fsp_send_packet(nvswitch_device *device, NvU8 *pPacket, NvU32 packetSize); +NvlStatus nvswitch_fsp_send_and_read_message(nvswitch_device *device, NvU8 *pPayload, NvU32 size, NvU32 nvdmType, NvU8 *pResponsePayload, NvU32 responseBufferSize); + +#endif //_FSPRPC_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h index 756e7f238f..5ea6dcbe26 100644 --- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h @@ -47,6 +47,36 @@ // _op(return type, function name, (parameter list), _arch) // +#define NVSWITCH_HAL_FUNCTION_LIST_FEATURE_0(_op, _arch) \ + _op(NvBool, nvswitch_is_cci_supported, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_cci_setup_gpio_pins, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_cci_get_cci_link_mode, (nvswitch_device *device, NvU32 linkNumber, NvU64 *mode), _arch) \ + _op(NvlStatus, nvswitch_cci_discovery, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_cci_get_xcvrs_present, (nvswitch_device *device, NvU32 *pMaskPresent), _arch) \ + _op(void, nvswitch_cci_get_xcvrs_present_change, (nvswitch_device *device, NvU32 *pMaskPresentChange), _arch) \ + _op(NvlStatus, nvswitch_cci_reset, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_cci_reset_links, (nvswitch_device *device, NvU64 linkMask), _arch) \ + _op(NvlStatus, nvswitch_cci_ports_cpld_read, (nvswitch_device *device, NvU8 reg, NvU8 *pData), _arch) \ + _op(NvlStatus, nvswitch_cci_ports_cpld_write, (nvswitch_device *device, NvU8 reg, NvU8 Data), _arch) \ + _op(void, nvswitch_cci_update_link_state_led, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_cci_set_xcvr_led_state, (nvswitch_device *device, NvU32 client, NvU32 osfp, NvBool bSetLocate), _arch) \ + _op(NvlStatus, nvswitch_cci_get_xcvr_led_state, (nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 *pLedState), _arch) \ + _op(NvlStatus, nvswitch_cci_setup_onboard, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_cci_setup_module_path, (nvswitch_device *device, NvU32 client, NvU32 osfp), _arch) \ + _op(NvlStatus, nvswitch_cci_module_access_cmd, (nvswitch_device *device, NvU32 client, NvU32 osfp, NvU32 addr, NvU32 length, \ + NvU8 *pValArray, NvBool bRead, NvBool bBlk), _arch) \ + _op(NvlStatus, nvswitch_cci_apply_control_set_values, (nvswitch_device *device, NvU32 client, NvU32 moduleMask), _arch) \ + _op(NvlStatus, nvswitch_cci_reset_and_drain_links, (nvswitch_device *device, NvU64 link_mask, NvBool bForced), _arch) \ + _op(NvlStatus, nvswitch_cci_cmis_cage_bezel_marking, (nvswitch_device *device, NvU8 cageIndex, char *pBezelMarking), _arch) \ + _op(NvlStatus, nvswitch_cci_get_grading_values, (nvswitch_device *device, NvU32 client, NvU32 linkId, NvU8 *laneMask, NVSWITCH_CCI_GRADING_VALUES *pGrading), _arch) \ + _op(NvlStatus, nvswitch_cci_get_xcvr_mask, (nvswitch_device *device, NvU32 *pMaskAll, NvU32 *pMaskPresent), _arch) \ + _op(void, nvswitch_cci_set_xcvr_present, (nvswitch_device *device, NvU32 maskPresent), _arch) \ + _op(void, nvswitch_cci_destroy, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_soe_heartbeat, (nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p), _arch) \ + _op(void, nvswitch_update_link_state_led, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_led_shutdown, (nvswitch_device *device), _arch) \ + + #define NVSWITCH_HAL_FUNCTION_LIST(_op, _arch) \ _op(NvlStatus, nvswitch_initialize_device_state, (nvswitch_device *device), _arch) \ _op(void, nvswitch_destroy_device_state, (nvswitch_device *device), _arch) \ @@ -68,7 +98,7 @@ _op(NvlStatus, nvswitch_lib_service_interrupts, (nvswitch_device *device), _arch) \ _op(NvU64, nvswitch_hw_counter_read_counter, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_link_in_use, (nvswitch_device *device, NvU32 link_id), _arch) \ - _op(NvlStatus, nvswitch_reset_and_drain_links, (nvswitch_device *device, NvU64 link_mask), _arch) \ + _op(NvlStatus, nvswitch_reset_and_drain_links, (nvswitch_device *device, NvU64 link_mask, NvBool bForced), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_info, (nvswitch_device *device, NVSWITCH_GET_INFO *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_nvlink_status, (nvswitch_device *device, NVSWITCH_GET_NVLINK_STATUS_PARAMS *ret), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_counters, (nvswitch_device *device, NVSWITCH_NVLINK_GET_COUNTERS_PARAMS *ret), _arch) \ @@ -214,6 +244,7 @@ _op(void, nvswitch_reset_persistent_link_hw_state, (nvswitch_device *device, NvU32 linkNumber), _arch)\ _op(void, nvswitch_store_topology_information, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(void, nvswitch_init_lpwr_regs, (nvlink_link *link), _arch) \ + _op(void, nvswitch_program_l1_scratch_reg, (nvswitch_device *device, NvU32 linkNumber), _arch) \ _op(NvlStatus, nvswitch_set_training_mode, (nvswitch_device *device), _arch) \ _op(NvU32, nvswitch_get_sublink_width, (nvswitch_device *device, NvU32 linkNumber), _arch) \ _op(NvBool, nvswitch_i2c_is_device_access_allowed, (nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead), _arch) \ @@ -233,8 +264,31 @@ _op(NvlStatus, nvswitch_ctrl_therm_read_voltage, (nvswitch_device *device, NVSWITCH_CTRL_GET_VOLTAGE_PARAMS *info), _arch) \ _op(void, nvswitch_soe_init_l2_state, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_ctrl_therm_read_power, (nvswitch_device *device, NVSWITCH_GET_POWER_PARAMS *info), _arch) \ + _op(NvlStatus, nvswitch_get_board_id, (nvswitch_device *device, NvU16 *boardId), _arch) \ _op(NvBool, nvswitch_does_link_need_termination_enabled, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvlStatus, nvswitch_link_termination_setup, (nvswitch_device *device, nvlink_link *link), _arch) \ + _op(NvlStatus, nvswitch_check_io_sanity, (nvswitch_device *device), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_link_l1_capability, (nvswitch_device *device, NvU32 linkNum, NvBool *isL1Capable), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_link_l1_threshold, (nvswitch_device *device, NvU32 linkNum, NvU32 *lpThreshold), _arch) \ + _op(NvlStatus, nvswitch_ctrl_set_link_l1_threshold, (nvlink_link *link, NvU32 lpEntryThreshold), _arch) \ + _op(void, nvswitch_fsp_update_cmdq_head_tail, (nvswitch_device *device, NvU32 queueHead, NvU32 queueTail), _arch) \ + _op(void, nvswitch_fsp_get_cmdq_head_tail, (nvswitch_device *device, NvU32 *pQueueHead, NvU32 *pQueueTail), _arch) \ + _op(void, nvswitch_fsp_update_msgq_head_tail, (nvswitch_device *device, NvU32 msgqHead, NvU32 msgqTail), _arch) \ + _op(void, nvswitch_fsp_get_msgq_head_tail, (nvswitch_device *device, NvU32 *pMsgqHead, NvU32 *pMsgqTail), _arch) \ + _op(NvU32, nvswitch_fsp_get_channel_size, (nvswitch_device *device), _arch) \ + _op(NvU8, nvswitch_fsp_nvdm_to_seid, (nvswitch_device *device, NvU8 nvdmType), _arch) \ + _op(NvU32, nvswitch_fsp_create_mctp_header, (nvswitch_device *device, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq), _arch) \ + _op(NvU32, nvswitch_fsp_create_nvdm_header, (nvswitch_device *device, NvU32 nvdmType), _arch) \ + _op(NvlStatus, nvswitch_fsp_validate_mctp_payload_header, (nvswitch_device *device, NvU8 *pBuffer, NvU32 size), _arch) \ + _op(NvlStatus, nvswitch_fsp_process_nvdm_msg, (nvswitch_device *device, NvU8 *pBuffer, NvU32 size), _arch) \ + _op(NvlStatus, nvswitch_fsp_process_cmd_response, (nvswitch_device *device, NvU8 *pBuffer, NvU32 size), _arch) \ + _op(NvlStatus, nvswitch_fsp_config_ememc, (nvswitch_device *device, NvU32 offset, NvBool bAincw, NvBool bAincr), _arch) \ + _op(NvlStatus, nvswitch_fsp_write_to_emem, (nvswitch_device *device, NvU8 *pBuffer, NvU32 size), _arch) \ + _op(NvlStatus, nvswitch_fsp_read_from_emem, (nvswitch_device *device, NvU8 *pBuffer, NvU32 size), _arch) \ + _op(NvlStatus, nvswitch_fsp_error_code_to_nvlstatus_map, (nvswitch_device *device, NvU32 errorCode), _arch) \ + _op(NvlStatus, nvswitch_fsp_get_packet_info, (nvswitch_device *device, NvU8 *pBuffer, NvU32 size, NvU8 *pPacketState, NvU8 *pTag), _arch) \ + _op(NvlStatus, nvswitch_fsprpc_get_caps, (nvswitch_device *device, NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params), _arch) \ + NVSWITCH_HAL_FUNCTION_LIST_FEATURE_0(_op, _arch) \ #define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \ _op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \ diff --git a/src/common/nvswitch/kernel/inc/lr10/cci_lr10.h b/src/common/nvswitch/kernel/inc/lr10/cci_lr10.h new file mode 100644 index 0000000000..1a9c449e71 --- /dev/null +++ b/src/common/nvswitch/kernel/inc/lr10/cci_lr10.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CCI_LR10_H_ +#define _CCI_LR10_H_ + +// HALs +NvBool nvswitch_is_cci_supported_lr10(nvswitch_device *device); +void nvswitch_cci_setup_gpio_pins_lr10(nvswitch_device *device); +NvlStatus nvswitch_cci_get_cci_link_mode_lr10(nvswitch_device *device, NvU32 linkNumber, NvU64 *mode); +NvlStatus nvswitch_cci_discovery_lr10(nvswitch_device *device); +void nvswitch_cci_get_xcvrs_present_lr10(nvswitch_device *device, NvU32 *pMaskPresent); +void nvswitch_cci_get_xcvrs_present_change_lr10(nvswitch_device *device, NvU32 *pMaskPresentChange); +NvlStatus nvswitch_cci_reset_lr10(nvswitch_device *device); +NvlStatus nvswitch_cci_reset_links_lr10(nvswitch_device *device, NvU64 linkMask); +NvlStatus nvswitch_cci_ports_cpld_read_lr10(nvswitch_device *device, NvU8 reg, NvU8 *pData); +NvlStatus nvswitch_cci_ports_cpld_write_lr10(nvswitch_device *device, NvU8 reg, NvU8 data); +void nvswitch_cci_update_link_state_led_lr10(nvswitch_device *device); +NvlStatus nvswitch_cci_set_xcvr_led_state_lr10(nvswitch_device *device, NvU32 client, NvU32 osfp, NvBool bSetLocate); +NvlStatus nvswitch_cci_get_xcvr_led_state_lr10(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 *pLedState); +NvlStatus nvswitch_cci_setup_onboard_lr10(nvswitch_device *device); +NvlStatus nvswitch_cci_setup_module_path_lr10(nvswitch_device *device, NvU32 client, NvU32 osfp); +NvlStatus nvswitch_cci_module_access_cmd_lr10(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU32 addr, NvU32 length, + NvU8 *pValArray, NvBool bRead, NvBool bBlk); +NvlStatus nvswitch_cci_apply_control_set_values_lr10(nvswitch_device *device, NvU32 client, NvU32 moduleMask); +NvlStatus nvswitch_cci_cmis_cage_bezel_marking_lr10(nvswitch_device *device, NvU8 cageIndex, char *pBezelMarking); +NvlStatus nvswitch_cci_get_grading_values_lr10(nvswitch_device *device, NvU32 client, NvU32 linkId, NvU8 *laneMask, NVSWITCH_CCI_GRADING_VALUES *pGrading); +NvlStatus nvswitch_cci_get_xcvr_mask_lr10(nvswitch_device *device, NvU32 *pMaskAll, NvU32 *pMaskPresent); +void nvswitch_cci_set_xcvr_present_lr10(nvswitch_device *device, NvU32 maskPresent); +void nvswitch_cci_destroy_lr10(nvswitch_device *device); + +#endif //_CCI_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/lr10/lr10.h b/src/common/nvswitch/kernel/inc/lr10/lr10.h index 5b7d9b486b..7017fa1081 100644 --- a/src/common/nvswitch/kernel/inc/lr10/lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/lr10.h @@ -652,6 +652,7 @@ void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32 void nvswitch_reset_persistent_link_hw_state_lr10(nvswitch_device *device, NvU32 linkNumber); void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link); void nvswitch_init_lpwr_regs_lr10(nvlink_link *link); +void nvswitch_program_l1_scratch_reg_lr10(nvswitch_device *device, NvU32 linkNumber); NvlStatus nvswitch_set_training_mode_lr10(nvswitch_device *device); NvBool nvswitch_i2c_is_device_access_allowed_lr10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead); NvU32 nvswitch_get_sublink_width_lr10(nvswitch_device *device,NvU32 linkNumber); @@ -673,6 +674,14 @@ void nvswitch_setup_link_system_registers_lr10(nvswitch_device *device, nvl void nvswitch_load_link_disable_settings_lr10(nvswitch_device *device, nvlink_link *link); NvBool nvswitch_is_smbpbi_supported_lr10(nvswitch_device *device); NvlStatus nvswitch_ctrl_get_board_part_number_lr10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p); +NvlStatus nvswitch_ctrl_get_link_l1_capability_lr10(nvswitch_device *device, NvU32 linkId, NvBool *isL1Capable); +NvlStatus nvswitch_ctrl_get_link_l1_threshold_lr10(nvswitch_device *device, NvU32 linkNum, NvU32 *lpThreshold); +NvlStatus nvswitch_ctrl_set_link_l1_threshold_lr10(nvlink_link *link, NvU32 lpEntryThreshold); +NvlStatus nvswitch_get_board_id_lr10(nvswitch_device *device, NvU16 *boardId); + +NvlStatus nvswitch_ctrl_get_soe_heartbeat_lr10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p); +void nvswitch_update_link_state_led_lr10(nvswitch_device *device); +void nvswitch_led_shutdown_lr10(nvswitch_device *device); NvlStatus nvswitch_ctrl_set_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p); NvlStatus nvswitch_ctrl_get_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p); @@ -682,5 +691,21 @@ NvlStatus nvswitch_reset_and_train_link_lr10(nvswitch_device *device, nvlink_lin NvlStatus nvswitch_ctrl_get_bios_info_lr10(nvswitch_device *device, NVSWITCH_GET_BIOS_INFO_PARAMS *p); NvBool nvswitch_does_link_need_termination_enabled_lr10(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_link_termination_setup_lr10(nvswitch_device *device, nvlink_link* link); +void nvswitch_fsp_update_cmdq_head_tail_lr10(nvswitch_device *device, NvU32 queueHead, NvU32 queueTail); +void nvswitch_fsp_get_cmdq_head_tail_lr10(nvswitch_device *device, NvU32 *pQueueHead, NvU32 *pQueueTail); +void nvswitch_fsp_update_msgq_head_tail_lr10(nvswitch_device *device, NvU32 msgqHead, NvU32 msgqTail); +void nvswitch_fsp_get_msgq_head_tail_lr10(nvswitch_device *device, NvU32 *pMsgqHead, NvU32 *pMsgqTail); +NvU32 nvswitch_fsp_get_channel_size_lr10(nvswitch_device *device); +NvU8 nvswitch_fsp_nvdm_to_seid_lr10(nvswitch_device *device, NvU8 nvdmType); +NvU32 nvswitch_fsp_create_mctp_header_lr10(nvswitch_device *device, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq); +NvU32 nvswitch_fsp_create_nvdm_header_lr10(nvswitch_device *device, NvU32 nvdmType); +NvlStatus nvswitch_fsp_get_packet_info_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size, NvU8 *pPacketState, NvU8 *pTag); +NvlStatus nvswitch_fsp_validate_mctp_payload_header_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_process_nvdm_msg_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_process_cmd_response_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_config_ememc_lr10(nvswitch_device *device, NvU32 offset, NvBool bAincw, NvBool bAincr); +NvlStatus nvswitch_fsp_write_to_emem_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_read_from_emem_lr10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_lr10(nvswitch_device *device, NvU32 errorCode); #endif //_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/cci_ls10.h b/src/common/nvswitch/kernel/inc/ls10/cci_ls10.h new file mode 100644 index 0000000000..d953bd689f --- /dev/null +++ b/src/common/nvswitch/kernel/inc/ls10/cci_ls10.h @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _CCI_LS10_H_ +#define _CCI_LS10_H_ + +#define NVSWITCH_CCI_VBIOS_REV_LOCK_VERSION_LS10 (0x9610360000) +#define NVSWITCH_CCI_VBIOS_REV_LOCK_VERSION_STRING_LS10 ("96.10.36.00.00") + +#define NVSWITCH_CCI_NUM_LINKS_PER_OSFP_LS10 4 + +// HALs +NvBool nvswitch_is_cci_supported_ls10(nvswitch_device *device); +void nvswitch_cci_setup_gpio_pins_ls10(nvswitch_device *device); +NvlStatus nvswitch_cci_get_cci_link_mode_ls10(nvswitch_device *device, NvU32 linkNumber, NvU64 *mode); +NvlStatus nvswitch_cci_discovery_ls10(nvswitch_device *device); +void nvswitch_cci_get_xcvrs_present_ls10(nvswitch_device *device, NvU32 *pMaskPresent); +void nvswitch_cci_get_xcvrs_present_change_ls10(nvswitch_device *device, NvU32 *pMaskPresentChange); +NvlStatus nvswitch_cci_reset_ls10(nvswitch_device *device); +NvlStatus nvswitch_cci_reset_links_ls10(nvswitch_device *device, NvU64 linkMask); +NvlStatus nvswitch_cci_ports_cpld_read_ls10(nvswitch_device *device, NvU8 reg, NvU8 *pData); +NvlStatus nvswitch_cci_ports_cpld_write_ls10(nvswitch_device *device, NvU8 reg, NvU8 data); +void nvswitch_cci_update_link_state_led_ls10(nvswitch_device *device); +NvlStatus nvswitch_cci_set_xcvr_led_state_ls10(nvswitch_device *device, NvU32 client, NvU32 osfp, NvBool bSetLocate); +NvlStatus nvswitch_cci_get_xcvr_led_state_ls10(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU8 *pLedState); +NvlStatus nvswitch_cci_setup_onboard_ls10(nvswitch_device *device); +NvlStatus nvswitch_cci_setup_module_path_ls10(nvswitch_device *device, NvU32 client, NvU32 osfp); +NvlStatus nvswitch_cci_module_access_cmd_ls10(nvswitch_device *device, NvU32 client, NvU32 osfp, NvU32 addr, NvU32 length, + NvU8 *pValArray, NvBool bRead, NvBool bBlk); +NvlStatus nvswitch_cci_apply_control_set_values_ls10(nvswitch_device *device, NvU32 client, NvU32 moduleMask); +NvlStatus nvswitch_cci_cmis_cage_bezel_marking_ls10(nvswitch_device *device, NvU8 cageIndex, char *pBezelMarking); +NvlStatus nvswitch_cci_get_grading_values_ls10(nvswitch_device *device, NvU32 client, NvU32 linkId, NvU8 *laneMask, NVSWITCH_CCI_GRADING_VALUES *pGrading); +NvlStatus nvswitch_cci_get_xcvr_mask_ls10(nvswitch_device *device, NvU32 *pMaskAll, NvU32 *pMaskPresent); +void nvswitch_cci_set_xcvr_present_ls10(nvswitch_device *device, NvU32 maskPresent); +void nvswitch_cci_destroy_ls10(nvswitch_device *device); + +#endif //_CCI_LS10_H_ + \ No newline at end of file diff --git a/src/common/nvswitch/kernel/inc/ls10/ls10.h b/src/common/nvswitch/kernel/inc/ls10/ls10.h index 0abd4bcd50..ca83679fc1 100644 --- a/src/common/nvswitch/kernel/inc/ls10/ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/ls10.h @@ -188,6 +188,18 @@ #define SOE_VBIOS_VERSION_MASK 0xFF0000 #define SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR 0x370000 +#define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x440000 + +// LS10 Saved LED state +#define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED + +// Access link LED states on LS10 Systems +#define ACCESS_LINK_LED_STATE_FAULT 0U +#define ACCESS_LINK_LED_STATE_OFF 1U +#define ACCESS_LINK_LED_STATE_INITIALIZE 2U +#define ACCESS_LINK_LED_STATE_UP_WARM 3U +#define ACCESS_LINK_LED_STATE_UP_ACTIVE 4U +#define ACCESS_LINK_NUM_LED_STATES 5U // // Helpful IO wrappers @@ -503,7 +515,8 @@ typedef struct NV_NPORT_PORTSTAT_LS10(_block, _reg, _idx, ), _data); \ } -#define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS (12 * NVSWITCH_INTERVAL_1SEC_IN_NS) +#define NVSWITCH_DEFERRED_LINK_STATE_CHECK_INTERVAL_NS ((device->bModeContinuousALI ? 12 : 30) *\ + NVSWITCH_INTERVAL_1SEC_IN_NS) #define NVSWITCH_DEFERRED_FAULT_UP_CHECK_INTERVAL_NS (12 * NVSWITCH_INTERVAL_1MSEC_IN_NS) // Struct used for passing around error masks in error handling functions @@ -788,7 +801,6 @@ typedef const struct #define nvswitch_is_link_valid_ls10 nvswitch_is_link_valid_lr10 #define nvswitch_is_link_in_use_ls10 nvswitch_is_link_in_use_lr10 -#define nvswitch_initialize_device_state_ls10 nvswitch_initialize_device_state_lr10 #define nvswitch_deassert_link_reset_ls10 nvswitch_deassert_link_reset_lr10 #define nvswitch_determine_platform_ls10 nvswitch_determine_platform_lr10 #define nvswitch_get_swap_clk_default_ls10 nvswitch_get_swap_clk_default_lr10 @@ -938,6 +950,7 @@ void nvswitch_corelib_clear_link_state_lr10(nvlink_link *link); NvlStatus nvswitch_corelib_set_dl_link_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); NvlStatus nvswitch_corelib_set_tx_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags); void nvswitch_init_lpwr_regs_ls10(nvlink_link *link); +void nvswitch_program_l1_scratch_reg_ls10(nvswitch_device *device, NvU32 linkNumber); NvlStatus nvswitch_minion_service_falcon_interrupts_ls10(nvswitch_device *device, NvU32 instance); @@ -987,15 +1000,16 @@ void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link); void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link); void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 link); - void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); void nvswitch_set_dlpl_interrupts_ls10(nvlink_link *link); -NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask); - void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); NvlStatus nvswitch_ctrl_get_board_part_number_ls10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p); void nvswitch_create_deferred_link_state_check_task_ls10(nvswitch_device *device, NvU32 nvlipt_instance, NvU32 link); NvlStatus nvswitch_request_tl_link_state_ls10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync); +NvlStatus nvswitch_ctrl_get_link_l1_capability_ls10(nvswitch_device *device, NvU32 linkId, NvBool *isL1Capable); +NvlStatus nvswitch_ctrl_get_link_l1_threshold_ls10(nvswitch_device *device, NvU32 linkNum, NvU32 *lpThreshold); +NvlStatus nvswitch_ctrl_set_link_l1_threshold_ls10(nvlink_link *link, NvU32 lpEntryThreshold); +NvlStatus nvswitch_get_board_id_ls10(nvswitch_device *device, NvU16 *boardId); // // SU generated functions @@ -1020,6 +1034,30 @@ NvBool nvswitch_are_link_clocks_on_ls10(nvswitch_device *device, nvlink_link NvBool nvswitch_does_link_need_termination_enabled_ls10(nvswitch_device *device, nvlink_link *link); NvlStatus nvswitch_link_termination_setup_ls10(nvswitch_device *device, nvlink_link* link); void nvswitch_get_error_rate_threshold_ls10(nvlink_link *link); +void nvswitch_fsp_update_cmdq_head_tail_ls10(nvswitch_device *device, NvU32 queueHead, NvU32 queueTail); +void nvswitch_fsp_get_cmdq_head_tail_ls10(nvswitch_device *device, NvU32 *pQueueHead, NvU32 *pQueueTail); +void nvswitch_fsp_update_msgq_head_tail_ls10(nvswitch_device *device, NvU32 msgqHead, NvU32 msgqTail); +void nvswitch_fsp_get_msgq_head_tail_ls10(nvswitch_device *device, NvU32 *pMsgqHead, NvU32 *pMsgqTail); +NvU32 nvswitch_fsp_get_channel_size_ls10(nvswitch_device *device); +NvU8 nvswitch_fsp_nvdm_to_seid_ls10(nvswitch_device *device, NvU8 nvdmType); +NvU32 nvswitch_fsp_create_mctp_header_ls10(nvswitch_device *device, NvU8 som, NvU8 eom, NvU8 seid, NvU8 seq); +NvU32 nvswitch_fsp_create_nvdm_header_ls10(nvswitch_device *device, NvU32 nvdmType); +NvlStatus nvswitch_fsp_get_packet_info_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size, NvU8 *pPacketState, NvU8 *pTag); +NvlStatus nvswitch_fsp_validate_mctp_payload_header_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_process_nvdm_msg_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_process_cmd_response_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_config_ememc_ls10(nvswitch_device *device, NvU32 offset, NvBool bAincw, NvBool bAincr); +NvlStatus nvswitch_fsp_write_to_emem_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_read_from_emem_ls10(nvswitch_device *device, NvU8 *pBuffer, NvU32 size); +NvlStatus nvswitch_fsp_error_code_to_nvlstatus_map_ls10(nvswitch_device *device, NvU32 errorCode); +NvlStatus nvswitch_fsprpc_get_caps_ls10(nvswitch_device *device, NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params); + +NvlStatus nvswitch_ctrl_get_soe_heartbeat_ls10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p); +NvlStatus nvswitch_cci_enable_iobist_ls10(nvswitch_device *device, NvU32 linkNumber, NvBool bEnable); +NvlStatus nvswitch_cci_initialization_sequence_ls10(nvswitch_device *device, NvU32 linkNumber); +NvlStatus nvswitch_cci_deinitialization_sequence_ls10(nvswitch_device *device, NvU32 linkNumber); +void nvswitch_update_link_state_led_ls10(nvswitch_device *device); +void nvswitch_led_shutdown_ls10(nvswitch_device *device); #endif //_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h b/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h index d7046b2b53..650b210c36 100644 --- a/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/multicast_ls10.h @@ -42,10 +42,11 @@ // // Debug and trace print toggles // To enable tracing, define NVSWITCH_MC_TRACE +// To enable extensive debug messages uncomment the below define NVSWITCH_MC_DEBUG // -#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) -#define NVSWITCH_MC_DEBUG 1 -#endif +// #if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) +// #define NVSWITCH_MC_DEBUG 1 +// #endif typedef struct { NvU32 column; diff --git a/src/common/nvswitch/kernel/inc/regkey_nvswitch.h b/src/common/nvswitch/kernel/inc/regkey_nvswitch.h index 7d7dc483f0..c94e6b5ed6 100644 --- a/src/common/nvswitch/kernel/inc/regkey_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/regkey_nvswitch.h @@ -298,6 +298,52 @@ #define NV_SWITCH_REGKEY_SOE_DMA_SELFTEST_DISABLE 0x00 #define NV_SWITCH_REGKEY_SOE_DMA_SELFTEST_ENABLE 0x01 +/* + * CCI Control + * + * This regkey controls enablement of CCI on LS10 systems. + * + * Public: Available in release drivers + */ +#define NV_SWITCH_REGKEY_CCI_CONTROL "CCIControl" +#define NV_SWITCH_REGKEY_CCI_CONTROL_DEFAULT 0x1 +#define NV_SWITCH_REGKEY_CCI_CONTROL_ENABLE 0:0 +#define NV_SWITCH_REGKEY_CCI_CONTROL_ENABLE_FALSE 0x00 +#define NV_SWITCH_REGKEY_CCI_CONTROL_ENABLE_TRUE 0x01 + +/* + * CCI Link Train Disable Mask + * + * These regkeys will disable link training for CCI managed links. + * + * Mask contains links 0-31 + * Mask2 contains links 32-63 + * + * Private: Will only be applied on debug/develop drivers and MODS + */ +#define NV_SWITCH_REGKEY_CCI_DISABLE_LINK_TRAIN_MASK "CCILinkTrainDisableMask" +#define NV_SWITCH_REGKEY_CCI_DISABLE_LINK_TRAIN_MASK2 "CCILinkTrainDisableMask2" +#define NV_SWITCH_REGKEY_CCI_DISABLE_LINK_TRAIN_MASK_DEFAULT 0x0 +#define NV_SWITCH_REGKEY_CCI_DISABLE_LINK_TRAIN_MASK2_DEFAULT 0x0 + +/* + * CCI Max Onboard Attempts + * + * Public: Available in release drivers + */ +#define NV_SWITCH_REGKEY_CCI_MAX_ONBOARD_ATTEMPTS "CCIMaxOnboardAttempts" +#define NV_SWITCH_REGKEY_CCI_MAX_ONBOARD_ATTEMPTS_DEFAULT 0x5 + +/* + * CCI Error Log Enable + * + * This regkey will enable emission of CCI module onboarding SXids errors. + * + * Public: Available in release drivers + */ +#define NV_SWITCH_REGKEY_CCI_ERROR_LOG_ENABLE "CCIErrorLogEnable" +#define NV_SWITCH_REGKEY_CCI_ERROR_LOG_ENABLE_DEFAULT 0x1 + /* * Disables logging of latency counters * diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index c306f08bde..beb5679f56 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -35,7 +35,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x9c890a00, 0x9abf000f, 0x1100a0b3, 0x0d00b0b3, 0xa001aa98, 0xf8a43dba, 0x0a02f800, 0xbd00f8ff, 0xfc30f494, 0x40fe02f9, 0x04009001, - 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002e8989, 0xa43d9d20, 0x00006b3e, + 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002e8d89, 0xa43d9d20, 0x00006b3e, 0xfc09040a, 0x0bf4f9a6, 0xfbff0a05, 0x337e0405, 0xa0330000, 0xa0330a04, 0x02f80600, 0xb37e00f8, 0xafb20003, 0x0801a4b3, 0x00f8a43d, 0xfc09040a, 0x0bf4f9a6, 0x0a02f807, 0xbd00f8ff, 0xbdc4bdb4, 0x007e7ed4, 0xf900f800, 0xb2a2b222, 0xb2c0b2b1, 0xb21bb22a, 0x7eff0d0c, 0x3300007e, 0xfbf400a4, @@ -157,11 +157,11 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0142fe01, 0x90271190, 0x1ab22622, 0x5e7e2bb2, 0x020a0038, 0x787eab32, 0x0abf0038, 0x00043998, 0x3f95f901, 0x7e2b3f1a, 0xbf003878, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, 0x3dbcb200, 0x8aabb2d4, 0x7e0010e0, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010e0, 0xf8000e6b, - 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2e808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, + 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2e848900, 0x0b9abf00, 0x00de7eff, 0xff19c400, 0x0301008f, 0xbc099e94, 0xefcfe0ef, 0x8099b800, 0x94b60001, 0x009dcf09, 0xf0020918, 0x09352095, 0xf40fa602, 0xf63e411b, 0xf918000f, 0x2094f002, 0x3f340bf4, 0x009433f9, 0xf8cbbc0b, 0x000fef3e, - 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002e68, - 0xc91bf4fd, 0x002e8089, 0x9b7e9abf, 0x11fb0000, 0x0c8b02f9, 0x127e0011, 0xa0320000, 0x0f00a033, + 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002e6c, + 0xc91bf4fd, 0x002e8489, 0x9b7e9abf, 0x11fb0000, 0x0c8b02f9, 0x127e0011, 0xa0320000, 0x0f00a033, 0x0000ea7e, 0x7eff0bc4, 0x8900184a, 0xbf00110c, 0x11108990, 0x899fbf00, 0x180010fc, 0x9e35180e, 0xf40fa60e, 0x0918101b, 0x00943319, 0x3ea4bd0a, 0x1800107a, 0xb4331d0b, 0xa4bd0a00, 0x00106f3e, 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00111089, 0x01fb90a0, 0x89ffa4f0, @@ -230,11 +230,11 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x31f400f8, 0x0028f400, 0x02f800f8, 0x477e00f8, 0x00f80019, 0x001434d9, 0x0d9b1800, 0x7e0c9a18, 0xf8001a12, 0x1a127e00, 0x7e00f800, 0xf80019cd, 0x14008900, 0x0099cf02, 0xf40194f0, 0xf17e160b, 0x008f003c, 0xf9ce0213, 0x0195f000, 0xf800f9f7, 0xf802f800, 0xf830f400, 0x0005ecdf, 0xbf02f900, - 0x0149feff, 0xa0089990, 0xd9f43d9f, 0x00002e89, 0x004f9f20, 0x00ffcf06, 0xcf07004e, 0x004900ee, + 0x0149feff, 0xa0089990, 0xd9f43d9f, 0x00002e8d, 0x004f9f20, 0x00ffcf06, 0xcf07004e, 0x004900ee, 0x0099cf02, 0x95049ffd, 0xeeb910ef, 0x049efd00, 0xff00ffb9, 0x09c4049f, 0x070bf401, 0x003b797e, 0x100009e4, 0x0f2f0bf4, 0x0149fe01, 0x0289008e, 0x20079990, 0x00e9ce9f, 0x9ffdfe0f, 0x00e9f704, 0x001408d9, 0xfe9abf00, 0x010c014b, 0x7e07bb90, 0xe400006e, 0x73800009, 0x7e080090, 0x49001871, - 0x90f70100, 0x0149fe00, 0xbf089990, 0x05ecd99e, 0x9fbf0000, 0x002e89d9, 0xa69a3f00, 0x070bf4ef, + 0x90f70100, 0x0149fe00, 0xbf089990, 0x05ecd99e, 0x9fbf0000, 0x002e8dd9, 0xa69a3f00, 0x070bf4ef, 0x003a317e, 0x0a0805fb, 0xf900f801, 0x03a99802, 0x94f0a0b2, 0x0d0bf401, 0x277eaabf, 0x673e001a, 0xa9bf0019, 0x98009acf, 0x0998030f, 0x020e9801, 0xff02f4f0, 0x9ea694a9, 0x320b9cf0, 0x00f0b39a, 0x0096300c, 0x320b9cf0, 0xf401fb9a, 0x12f9ec30, 0x900149fe, 0xecd10899, 0xa0000005, 0x019bb59a, @@ -304,11 +304,11 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x9b7ea032, 0xdd7e000a, 0x1fbf000d, 0x0a3229bf, 0x0bf4f9a6, 0x3a317e07, 0x1855fb00, 0x3d7e040a, 0xa033003a, 0x508a2400, 0x277e1200, 0xa4f0001a, 0x150bf401, 0x1200588a, 0x001a277e, 0x1a00a0b3, 0xf407a9c4, 0x02f8070b, 0x020a00f8, 0x003a3d7e, 0x0600a433, 0x00f802f8, 0x00140cd9, 0xdb9abf00, - 0x40000000, 0x08b4aab8, 0x83ed7e00, 0xd900f800, 0x0000140c, 0x00db9abf, 0xb8400000, 0x0008c4aa, - 0x0083ed7e, 0x0cd900f8, 0xbf000014, 0x0000db9a, 0xaab88000, 0x7e0008c4, 0xf80083ed, 0x140cd900, + 0x40000000, 0x08b4aab8, 0x83f57e00, 0xd900f800, 0x0000140c, 0x00db9abf, 0xb8400000, 0x0008c4aa, + 0x0083f57e, 0x0cd900f8, 0xbf000014, 0x0000db9a, 0xaab88000, 0x7e0008c4, 0xf80083f5, 0x140cd900, 0x99bf0000, 0x01c0008f, 0xcf609a90, 0x99c700f9, 0x0090b34c, 0x0190b337, 0x3e02f8f6, 0xcf00222b, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8b00223f, 0xcf01c200, 0x18d900bb, 0xfd040400, - 0xed7e05b9, 0x00f80083, 0x01c10089, 0xdf009af6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, + 0xf57e05b9, 0x00f80083, 0x01c10089, 0xdf009af6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x223f3e9f, 0xd902f900, 0x0000140c, 0xa0b299bf, 0x08c89ab8, 0x1a277e00, 0xbb010900, 0xa9fd0490, 0x0bacf004, 0x02f901fb, 0x00140cd9, 0x8f9ebf00, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b301bb, 0x02f8f501, 0x0022b33e, 0xc700f9cf, 0x99b34c99, 0xb3019700, 0xf8f50190, 0x22c83e02, 0x00f9cf00, @@ -318,7 +318,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb80099b3, 0x0190b300, 0x3e02f8f5, 0xcf00233a, 0x99c700f9, 0x0099b34c, 0x90b30081, 0x02f8f501, 0x00234f3e, 0xc700f9cf, 0x90b34c99, 0x90b35700, 0x02f8f601, 0x0023643e, 0x0065f57e, 0x000000d9, 0x9409ff40, 0x7e070bf4, 0xd90067e7, 0x02000000, 0x000000df, 0xb409ff04, 0xf4940fff, 0xbffd060b, - 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000140c, 0xaab89abf, 0x7e0008c4, 0xfb0083ed, + 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000140c, 0xaab89abf, 0x7e0008c4, 0xfb0083f5, 0xc2008901, 0x0099cf01, 0x95049dff, 0x94b31f09, 0x783eae01, 0xefb80023, 0x890008a4, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0023643e, 0x01c20089, 0x8f009dcf, 0x3e01c000, 0xb800234f, 0x000890ef, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, @@ -443,36 +443,36 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xecdff430, 0xf9000005, 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, - 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06d, 0x00a0b31a, 0x7eb43d1a, 0xb300b105, - 0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05ecd99f, 0x99bf0000, + 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b075, 0x00a0b31a, 0x7eb43d1a, 0xb300b10d, + 0xbf1200a0, 0x7eff001a, 0x3e00b647, 0x00003371, 0x0149feff, 0xbf149990, 0x05ecd99f, 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05ecdfd8, 0x62f90000, 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000654, 0x0038327e, - 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50741, - 0x352bb201, 0x42b51540, 0xbd92a006, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, + 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50841, + 0x352bb201, 0x42b51940, 0xbd92a007, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, 0x980d0090, 0x95f00149, 0x0149b508, 0x000654d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, - 0x95f101f9, 0xf9b54000, 0x299cda01, 0x037e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, - 0xb20091b0, 0xbdb4bd0d, 0x2e70da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, - 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ef7e2b, 0x1fa43300, - 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x00950a7e, 0x061fa033, 0xb4bd09f8, 0x0a7e020a, - 0x9cda0095, 0x7e000029, 0xfe009ab2, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, - 0xd9320204, 0x00000654, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, - 0x159f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, - 0x033e9824, 0x002a3cd9, 0x2a44df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, - 0x1c391801, 0x21009033, 0x00299cdf, 0x08399800, 0x982dfe98, 0x9efd2efd, 0x2df9b505, 0xfd093998, - 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, + 0x95f101f9, 0xf9b54000, 0x299cda01, 0x0b7e0000, 0x3098009c, 0x01027e02, 0x8aabd900, 0xacb20000, + 0xb20091b0, 0xbdb4bd0d, 0x2e74da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, + 0x1e000000, 0xfe549035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94f77e2b, 0x1fa43300, + 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x0095127e, 0x061fa033, 0xb4bd09f8, 0x127e020a, + 0x9cda0095, 0x7e000029, 0xfe009aba, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, + 0xd9320204, 0x00000654, 0xa0b39abf, 0xb8d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, + 0x199f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, + 0x033e9824, 0x002a40d9, 0x2a48df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, + 0x1c391801, 0x21009033, 0x00299cdf, 0x08399800, 0x982efe98, 0x9efd2ffd, 0x2ef9b505, 0xfd093998, + 0xf9b5059d, 0x01087e2f, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0530de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, - 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b97e, 0x0036063e, 0x1bb20ab2, - 0x3e7e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, + 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098c17e, 0x0036063e, 0x1bb20ab2, + 0x467e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, 0x0000d9be, 0xe9ff4000, 0x6b0bf494, 0x681fa433, 0x900149fe, 0x9dbf4099, 0xbf049992, 0x1ee4339c, 0x0003df42, 0xff89ff00, 0xefff3fff, 0x94d9fff4, 0xff0294b6, 0xc0b3e5f9, 0xe9c50b00, 0x36703e03, 0x95fd0900, 0xe9fd16df, 0x00f0b304, 0x01e9c50d, 0x943eb9a0, 0xfe090036, 0x3e94e9ff, 0xdf003670, 0xff000000, 0xffffffd9, 0xf4efff00, 0xfd94d9ff, 0xbfa005f9, 0xfe0149fe, 0x9990014f, 0x44ff9040, 0xffbf9ebf, 0xbf049992, 0x0499929d, 0x99929fa0, 0x929ea004, 0x9da00499, 0x000a747e, 0x00299cd9, - 0x48991800, 0x0a009433, 0xd23e02f8, 0x90330036, 0x4efe1e01, 0x38ee9001, 0xffdfe9bf, 0xfde0ffff, - 0x00df049f, 0xfd010000, 0xe9a0059f, 0x9cd9f43d, 0x0d000029, 0x489f3501, 0xfe014bfe, 0xbb90014c, + 0x4c991800, 0x0a009433, 0xd23e02f8, 0x90330036, 0x4efe1e01, 0x38ee9001, 0xffdfe9bf, 0xfde0ffff, + 0x00df049f, 0xfd010000, 0xe9a0059f, 0x9cd9f43d, 0x0d000029, 0x4c9f3501, 0xfe014bfe, 0xbb90014c, 0x30cc9034, 0x90014afe, 0xb07e38aa, 0x9b7e0075, 0x143d000a, 0x00371a3e, 0x49fee401, 0x4c999001, 0xecd99fbf, 0xbf000005, 0xa61a3299, 0x070bf4f9, 0x003a317e, 0xfb0c30f4, 0xa9922865, 0x929ba004, 0xecb548ae, 0x00008906, 0xb2e9a030, 0x9294bdaf, 0xfab24cff, 0x00f8f9a0, 0x8f7e02f9, 0xa4b3005c, @@ -619,9 +619,9 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x1c339000, 0x05242290, 0xbf040402, 0x0d080c6a, 0x7e3bb2ff, 0x330000c1, 0x98f400a4, 0x193f0131, 0xeb079433, 0x3d041918, 0x2944da04, 0x94330000, 0x907e0a00, 0xa0320043, 0xb2013b18, 0x0f817e1a, 0x00043300, 0x022035ca, 0x11182520, 0x352ab203, 0xb4bd0124, 0x7e032135, 0x3e000f71, 0xf40048eb, - 0xecdff430, 0xf9000005, 0xbdffbf22, 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x7cd21499, - 0xa000002e, 0x7e01b29f, 0x3e0074f8, 0x9800497e, 0x993f0119, 0x0a099433, 0x967e0ab2, 0x70da0033, - 0x7e00002e, 0xb2001475, 0xb22abfad, 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002e70, 0x0014b57e, + 0xecdff430, 0xf9000005, 0xbdffbf22, 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x80d21499, + 0xa000002e, 0x7e01b29f, 0x3e0074f8, 0x9800497e, 0x993f0119, 0x0a099433, 0x967e0ab2, 0x74da0033, + 0x7e00002e, 0xb2001475, 0xb22abfad, 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002e74, 0x0014b57e, 0x00497e3e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -641,28 +641,28 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xa13018a1, 0x24a13020, 0x300101b0, 0x11300811, 0x1c01300c, 0x804e080d, 0x05d8da00, 0x0a7e0000, 0x20da005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x019000ad, 0xf1493f4c, 0xdb0000c3, 0x00000120, 0x3028a130, 0xa13000a1, 0x14a13010, 0x3018a130, 0xa13020a1, 0x0101b024, 0x30081130, 0x01300c11, - 0x4e070d1c, 0xdcda0100, 0x7e000005, 0xda005d0a, 0x00002e7c, 0x080c1bb2, 0x0059377e, 0x4300ad33, + 0x4e070d1c, 0xdcda0100, 0x7e000005, 0xda005d0a, 0x00002e80, 0x080c1bb2, 0x0059377e, 0x4300ad33, 0x48c24c01, 0x0000c3f1, 0x0000fcdb, 0x28a13000, 0x3000a130, 0xa13010a1, 0x18a13014, 0x3020a130, 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005e0, 0x005d0a7e, 0x001404da, 0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x0005e4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb, + 0x0005e4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7d3, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05e8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, 0x7e004d7d, 0x7e004df2, 0x7e005208, 0x7e005216, 0x7e0053af, 0x7e0053d2, 0x7e0053e7, 0x7e0053fc, 0x7e005438, 0x7e00544d, 0x7e00591d, 0x7e00706d, 0x7e005462, 0x7e004ea6, 0x330059ae, 0xf80600a0, - 0x2c30f402, 0x30d911fb, 0xbf000014, 0x2e88da99, 0x99980000, 0xf895f905, 0xf8400a00, 0x0070df00, + 0x2c30f402, 0x30d911fb, 0xbf000014, 0x2e8cda99, 0x99980000, 0xf895f905, 0xf8400a00, 0x0070df00, 0x00492000, 0x009ff607, 0xcf03004e, 0xff4f00e9, 0x049ffdcf, 0x800095f1, 0x8f00e9f6, 0x4900b071, 0x9ff60400, 0x15008f00, 0x00f9ce02, 0xf70195f0, 0x00f800f9, 0xf820004a, 0x01004f00, 0xf000f9ce, 0xf9f71095, 0x07004f00, 0xf000f9ce, 0xf9f71095, 0x04004f00, 0xf000f9ce, 0xf9f71095, 0xd900f800, - 0x00001430, 0x8ada99bf, 0x9800002e, 0x95f90899, 0x367e00f8, 0xa433004e, 0xaddf1100, 0x49deadde, + 0x00001430, 0x8eda99bf, 0x9800002e, 0x95f90899, 0x367e00f8, 0xa433004e, 0xaddf1100, 0x49deadde, 0x9ff61000, 0x7e02f800, 0x7e004e54, 0x7e004e15, 0xf8004e69, 0x90008900, 0x0099cf00, 0xf40194f0, 0x0089150b, 0x9fcf00a5, 0xf0ef0e00, 0xfefd07f5, 0x009ff604, 0x008900f8, 0x9fcf0090, 0x01f9c400, 0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00, 0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204, 0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014, - 0x95f90e99, 0x1e0a00f8, 0x00b9a27e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, + 0x95f90e99, 0x1e0a00f8, 0x00b9aa7e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8, 0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00, 0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000, @@ -690,24 +690,24 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x877e0c0a, 0xb4bd001a, 0xd4bdc4bd, 0x137e0f0a, 0xb4bd001f, 0x010ca1b2, 0x100ad4bd, 0x001f137e, 0x1a90a0b2, 0x1a277e0c, 0x10abc500, 0x7e0c0a90, 0xfb001a87, 0x1430d911, 0x99bf0000, 0x002928da, 0x11999800, 0x00f895f9, 0xc4bdb4bd, 0xa4bdd43d, 0x003aa97e, 0x30da00f8, 0x3d000029, 0x5e7f7eb4, - 0x2930d900, 0x99bf0000, 0x060094b3, 0x00f802f8, 0x001430d9, 0x3d9fbf00, 0x2e8bda94, 0xa9200000, + 0x2930d900, 0x99bf0000, 0x060094b3, 0x00f802f8, 0x001430d9, 0x3d9fbf00, 0x2e8fda94, 0xa9200000, 0xf910f998, 0xf8a43d95, 0x140cd900, 0x9abf0000, 0xb803034b, 0x0002dcaa, 0x001a877e, 0x066f448a, 0x001a277e, 0x000610d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000614, 0x9fa0a43d, 0x30d900f8, - 0xbf000014, 0xda943d9f, 0x00002e8c, 0xf9bfa920, 0xa43d95f9, 0x02f900f8, 0xd4bdc4bd, 0x110ab4bd, + 0xbf000014, 0xda943d9f, 0x00002e90, 0xf9bfa920, 0xa43d95f9, 0x02f900f8, 0xd4bdc4bd, 0x110ab4bd, 0x001f137e, 0x0484a0b8, 0x7e0ab200, 0xc5001a27, 0x0ab201ab, 0x001a877e, 0x08b8c08a, 0x001a277e, 0xa9fffb09, 0xb8c08ab4, 0x1a877e08, 0xb9408a00, 0x1a277e08, 0xffe00900, 0x408ab4a9, 0xb5f008b9, 0x1a877e02, 0xbd01fb00, 0xbdc4bdb4, 0x7ea4bdd4, 0xd9001f13, 0x00001430, 0x0cd99fbf, 0xa0000014, - 0x2e8eda9a, 0xf9980000, 0xf895f90c, 0xd002f900, 0x0000140c, 0xff0b0abf, 0x08b8aab8, 0x1a877e00, + 0x2e92da9a, 0xf9980000, 0xf895f90c, 0xd002f900, 0x0000140c, 0xff0b0abf, 0x08b8aab8, 0x1a877e00, 0x0b0abf00, 0xbcaab8ff, 0x877e0008, 0x0abf001a, 0xaab8ff0b, 0x7e0008c0, 0xbf001a87, 0xb8ff0b0a, 0x0008c4aa, 0x001a877e, 0x008b0abf, 0xaab87000, 0x7e0008d4, 0xbf001a87, 0x0000db0a, 0xaab80100, 0x7e0008a8, 0xbf001a87, 0xffffdb0a, 0xaab80e03, 0x7e0008e0, 0xbf001a87, 0x0000db0a, 0xaab8ce00, - 0x7e0008b4, 0xfb001a87, 0x1430d901, 0x99bf0000, 0x002e8fda, 0x07999800, 0x00f895f9, 0x001430d9, - 0xda99bf00, 0x00002e90, 0xf9099998, 0x0f00f895, 0x2938d9ff, 0x9fa00000, 0x9fb50f0f, 0xd900f801, - 0x00001430, 0x91da99bf, 0x9800002e, 0x95f90a99, 0x00f800f8, 0x001430d9, 0xda99bf00, 0x00002e92, - 0xf9049998, 0xf800f895, 0x1430d900, 0x99bf0000, 0x002e93da, 0x03999800, 0x00f895f9, 0x30d900f8, + 0x7e0008b4, 0xfb001a87, 0x1430d901, 0x99bf0000, 0x002e93da, 0x07999800, 0x00f895f9, 0x001430d9, + 0xda99bf00, 0x00002e94, 0xf9099998, 0x0f00f895, 0x2938d9ff, 0x9fa00000, 0x9fb50f0f, 0xd900f801, + 0x00001430, 0x95da99bf, 0x9800002e, 0x95f90a99, 0x00f800f8, 0x001430d9, 0xda99bf00, 0x00002e96, + 0xf9049998, 0xf800f895, 0x1430d900, 0x99bf0000, 0x002e97da, 0x03999800, 0x00f895f9, 0x30d900f8, 0xbf000014, 0x2978da99, 0x99980000, 0xdf95f90f, 0x00002970, 0x002944d9, 0x069fb500, 0x002968df, 0x059fb500, 0x9f35f4bd, 0xb59fa009, 0x9f35019f, 0xb5320f08, 0x00f8039f, 0x30d900f8, 0xbf000014, - 0x2e94da99, 0x99980000, 0xf895f906, 0xd900f800, 0x00001430, 0x98da99bf, 0x98000029, 0x95f90199, + 0x2e98da99, 0x99980000, 0xf895f906, 0xd900f800, 0x00001430, 0x98da99bf, 0x98000029, 0x95f90199, 0x30f500f8, 0xecdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001a27, 0x7e080aa0, 0xd9001a27, 0x40000000, 0xf50409fd, 0x95044d1b, 0x99b31fa9, 0x3d044601, 0x01dc4ba4, 0xa87e040c, 0xa4b20037, 0x4500a9b3, 0x76a0b503, 0xb571a0b5, 0xa0b572a0, 0x74a0b573, 0xd975a0b5, @@ -744,9 +744,9 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb8001a87, 0x00061c00, 0x277e0ab2, 0xabc5001a, 0x7e0ab204, 0x90001a87, 0x33950144, 0x01229d01, 0xf59523ff, 0x3eff641b, 0xfe0058dc, 0x90da0140, 0x90000029, 0xd4bd6000, 0x98de0bb2, 0x7e000000, 0x33004674, 0xff2a00ad, 0xfe0142fe, 0x03b20145, 0x2290143d, 0x24559098, 0x0056a03e, 0xb80149fe, - 0x00010899, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x83fb003a, 0xb4bd00e8, 0xda00c04c, - 0x0000299c, 0x000b947e, 0x001430d9, 0xda99bf00, 0x00002a58, 0xf90d9998, 0xf8a43d95, 0x05dcd900, - 0x9abf0000, 0x002e70db, 0x7e010c00, 0xf8005e25, 0x5c877e00, 0x3d00f800, 0x5e937ed4, 0xf400f800, + 0x00010899, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x83fb003a, 0xb4bd00e8, 0xda00c44c, + 0x0000299c, 0x000b947e, 0x001430d9, 0xda99bf00, 0x00002a5c, 0xf90d9998, 0xf8a43d95, 0x05dcd900, + 0x9abf0000, 0x002e74db, 0x7e010c00, 0xf8005e25, 0x5c877e00, 0x3d00f800, 0x5e937ed4, 0xf400f800, 0x12f9e430, 0xb0b2a1b2, 0x6100b0b3, 0xb004b998, 0x0cf40896, 0x0ba43d57, 0x384c7e44, 0x0aafb200, 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, @@ -773,7 +773,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xa000373a, 0x00aab90a, 0x98030ab5, 0x0a900519, 0x0109b510, 0x35181918, 0x19984109, 0x0209b502, 0x09b519bf, 0x1819180e, 0x98400935, 0x09b50319, 0x0be77e0f, 0x240a9000, 0x000be77e, 0x180700b5, 0x0909181f, 0xf00c00b5, 0x9fbbfff4, 0x0909b502, 0xa48911fb, 0x93fe0016, 0x05ad8a00, 0x7eb43d00, - 0x0a005dd4, 0x8900f801, 0xa00010d8, 0x8900f89a, 0xbf0010d8, 0x8a00f89a, 0x3d002e80, 0x5e7f7eb4, + 0x0a005dd4, 0x8900f801, 0xa00010d8, 0x8900f89a, 0xbf0010d8, 0x8a00f89a, 0x3d002e84, 0x5e7f7eb4, 0x00a03300, 0xf809f808, 0x10e08a00, 0x7eb43d00, 0x33005e89, 0xf80600a0, 0xf000f809, 0x94bd00b3, 0xa5a5a5df, 0x5cd13ea5, 0x90afa000, 0xaa900199, 0xf49ba604, 0x00f8f608, 0x00335089, 0x0010fc8f, 0xf9b59ab2, 0x35508b01, 0x02b9bb00, 0x7502b5b6, 0xbb7e04fb, 0x00f8005c, 0x0059c27e, 0x0c00a433, @@ -785,7 +785,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xb2340090, 0x593f7e0a, 0x33a13200, 0x332400a4, 0xbf100060, 0x3d6b320a, 0x7ed43dc4, 0xfe0011cc, 0x99900149, 0xa099bf34, 0x5dcf3e59, 0x32020100, 0x1c65fb1a, 0xb0b212f9, 0xb2d430f4, 0x4d797ea1, 0x72943d00, 0x0101b0ae, 0x91301cb2, 0x00913028, 0x30089130, 0x91300c91, 0x14913010, 0x30189130, - 0x91301c91, 0x24913020, 0x002e848a, 0x0001ac8b, 0x0a7ed43d, 0xa033005d, 0x02f80600, 0xfb2c30f4, + 0x91301c91, 0x24913020, 0x002e888a, 0x0001ac8b, 0x0a7ed43d, 0xa033005d, 0x02f80600, 0xfb2c30f4, 0xf8a43d11, 0xb202f900, 0x20c630b0, 0xf8050df4, 0xffcac402, 0xb604a994, 0xa9bc02a4, 0x2094bda0, 0x0109b50c, 0x0038547e, 0xfb020ab5, 0xb222f901, 0xb2a2b2c1, 0x0bba32d0, 0x384c7e54, 0x0aacb200, 0x00c0b305, 0xb21ab21c, 0x7e2db20b, 0xb3005fcc, 0x3d0a01a4, 0x5e7d3ea4, 0x0a02f800, 0x0c21fbff, @@ -804,22 +804,22 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xfb0ab200, 0x89008f41, 0x00f9ce02, 0xf70195f0, 0x00f800f9, 0x0089010f, 0x9ff60280, 0xb800f800, 0x000180aa, 0xf609a4b6, 0x00f800ab, 0x03210089, 0xb8009af6, 0x02010099, 0xf8009af6, 0xf030f400, 0x0005ecdf, 0xbf82f900, 0x0149feff, 0x32309990, 0x7e9fa0a1, 0xc4006014, 0x43feff1a, 0x1ae87e01, - 0x0142fe00, 0xb2ff16c4, 0x0f94d4a5, 0x33900000, 0x2c229024, 0x001400d8, 0x2e68d700, 0x9c3e0000, + 0x0142fe00, 0xb2ff16c4, 0x0f94d4a5, 0x33900000, 0x2c229024, 0x001400d8, 0x2e6cd700, 0x9c3e0000, 0x093f0061, 0x1e009433, 0xb2987ebc, 0xe949bc6a, 0x001ae87e, 0xa5b21b32, 0x817e0ab2, 0x9c3e000f, 0x09180061, 0x20010f01, 0x35fc0f3f, 0x30b50131, 0xff94f001, 0xfd039990, 0x09bc049f, 0xe949bc90, 0xf0330f3f, 0xf6307307, 0x150cf407, 0x9104f933, 0x05f03300, 0x02fd3355, 0xfe3e00c7, 0xf0330060, 0xf630600a, 0x0c0cf40a, 0xb409fd33, 0x612c3e00, 0x0bf03300, 0x0cfd3356, 0x523e00a7, 0x0ab20061, 0x817e1b32, 0x093f000f, 0xb4bd2ab2, 0x943d2920, 0x18022935, 0x04090300, 0x35012935, 0x717e0320, - 0x9c3e000f, 0x8abf0061, 0x0061903e, 0x002e7cdf, 0x61573e00, 0x1404d900, 0x4c3e0000, 0x20df0061, + 0x9c3e000f, 0x8abf0061, 0x0061903e, 0x002e80df, 0x61573e00, 0x1404d900, 0x4c3e0000, 0x20df0061, 0x3e000014, 0xd9006157, 0x00001428, 0x903e9abf, 0x1cdf0061, 0xbf000014, 0x61903efa, 0x3d2f2000, 0x350ab294, 0x00180229, 0x351b3203, 0x2035012f, 0x0f817e03, 0xb2b4bd00, 0x0f717e2a, 0x0a747e00, 0x19e87e00, 0x0028f400, 0x000a9b7e, 0x00619c3e, 0x0c00a0b3, 0x080c3bb2, 0x0000a77e, 0xbcff1ec4, 0x05a6084e, 0xfede1bf5, 0x0060057e, 0x900149fe, 0x9fbf3099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41085fb, 0xecdfb830, 0xf9000005, 0xfeffbf62, 0x99900149, 0xa03c0c60, 0x0140fe9f, - 0x0090b4bd, 0x7e0ab224, 0xd9000b94, 0x01000000, 0x002e68d1, 0xa09bb200, 0x0f94d919, 0xa4bd0000, + 0x0090b4bd, 0x7e0ab224, 0xd9000b94, 0x01000000, 0x002e6cd1, 0xa09bb200, 0x0f94d919, 0xa4bd0000, 0xf57e9ba0, 0x1bbf001a, 0x343da4bd, 0x7e008046, 0xbf00601f, 0x75020911, 0x09350406, 0x0101b501, 0x350a0335, 0xb4bd0b03, 0xda00804c, 0x01000000, 0x000b947e, 0xbd00804c, 0x0080dab4, 0x947e0100, - 0x057e000b, 0x80df0060, 0xd4010000, 0x00002e6c, 0x4fa0fab2, 0x00602c7e, 0xe0d24fbf, 0x75000010, + 0x057e000b, 0x80df0060, 0xd4010000, 0x00002e70, 0x4fa0fab2, 0x00602c7e, 0xe0d24fbf, 0x75000010, 0x03350806, 0x80f99012, 0xd90229b5, 0x00001b04, 0xb5030fb5, 0x1dd90329, 0xfe00001b, 0x29b50145, 0x1f559005, 0x53350109, 0x35592003, 0xfcd91309, 0xb5000010, 0x0975012f, 0x1b0ddf01, 0x04090000, 0x35042fb5, 0x32df0259, 0x0900000e, 0x062fb540, 0x20015935, 0x0a747e03, 0x7e2abf00, 0xb200009b, @@ -933,7 +933,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x006e607e, 0x0070463e, 0x0a1859bf, 0x030b1801, 0x18020c18, 0x0e98040d, 0x0091b002, 0xb0015998, 0x087e0191, 0xad33006d, 0x35ff6000, 0x2720022a, 0x32031e18, 0x351ab24b, 0x2e350126, 0x0f817e03, 0xbd2ab200, 0x0f717eb4, 0x6fa63e00, 0x05e4d900, 0x9abf0000, 0x001410db, 0x7e010c00, 0x7e005e25, - 0xf800709e, 0x1430d900, 0x9fbf0000, 0x8dda943d, 0x2000002e, 0x02f998a9, 0xa43d95f9, 0xa17e00f8, + 0xf800709e, 0x1430d900, 0x9fbf0000, 0x91da943d, 0x2000002e, 0x02f998a9, 0xa43d95f9, 0xa17e00f8, 0xaa7e003c, 0x00f8003b, 0xf9f830f4, 0xf4a1b222, 0xb2b2fc30, 0x900140fe, 0x0ca01000, 0x7e010db5, 0x09003da3, 0x00a033ff, 0x0109981e, 0x002944da, 0xb21cb200, 0x0091b02d, 0xab980ebf, 0x42ea7e07, 0x32a93200, 0x0430f49a, 0xdf0825fb, 0x000005ec, 0x30f4ffbf, 0x0149fef0, 0xa00c9990, 0x2944d99f, @@ -966,46 +966,46 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x277e0fa0, 0x2eb2001a, 0xbd011ab5, 0x00a1dbd4, 0x2e010000, 0x35f80d3c, 0xdd9002e1, 0x00a1dc01, 0xf9c40000, 0x64ffc70f, 0x3c98b93c, 0xe935f8bf, 0x90ef2001, 0xd4b303ee, 0xa9c4de04, 0x98c93c0f, 0xc70d2935, 0xc93c64a9, 0x0c293598, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, - 0x003a317e, 0xf91025fb, 0x29ccdb02, 0xcedc0000, 0xdd000029, 0x000029d0, 0x0029cada, 0x69c67e00, - 0x299cd000, 0x09980000, 0x29bcda01, 0x95f10000, 0x09b51e00, 0x73e27e01, 0x01099800, 0x0029d2da, + 0x003a317e, 0xf91025fb, 0x29d0db02, 0xd2dc0000, 0xdd000029, 0x000029d4, 0x0029ceda, 0x69c67e00, + 0x299cd000, 0x09980000, 0x29c0da01, 0x95f10000, 0x09b51e00, 0x73e27e01, 0x01099800, 0x0029d6da, 0x0095f100, 0x0109b501, 0x0073707e, 0xf1010998, 0xb5200095, 0x01fb0109, 0x00299cdd, 0x98dcbf00, 0xdf9801db, 0x0001d902, 0xc9fd3400, 0x0000d905, 0xde984c40, 0x05b9fd04, 0xf9fde309, 0xf0fe0904, - 0xf9fd04f5, 0x5000d904, 0xf9fd00c7, 0xf0050905, 0xd935c0e5, 0xa0ff0914, 0x04deb5dc, 0xb501dbb5, - 0xd9b502df, 0x74a77e15, 0xd900f800, 0x0000140c, 0xabc499bf, 0xc49ab801, 0x877e0007, 0x00f8001a, + 0xf9fd04f5, 0x5000d904, 0xf9fd00c7, 0xf0060905, 0xd935c0e5, 0xa0ff0918, 0x04deb5dc, 0xb501dbb5, + 0xd9b502df, 0x74a77e16, 0xd900f800, 0x0000140c, 0xabc499bf, 0xc49ab801, 0x877e0007, 0x00f8001a, 0xa0b212f9, 0x7d7eb1b2, 0x09bf006a, 0x1c0290b3, 0xf40296b0, 0x94b30b0c, 0x883e1001, 0x90b30075, 0x90b30a03, 0x94bd0604, 0x19bf09a0, 0x200390b3, 0xf40396b0, 0x90b30f0c, 0x94b31601, 0xac3e1002, 0x90b30075, 0x90b30a04, 0x94bd0605, 0x11fb19a0, 0xa1b222f9, 0xc2b2b0b2, 0x3200d433, 0x0e00a0b3, 0x0660e08a, 0x001a277e, 0x00b31aa0, 0xe48a0e00, 0x277e0660, 0x0aa0001a, 0x480020b3, 0x0660e88a, 0x001a277e, 0x203e2aa0, 0x020a0076, 0x3601d433, 0x0e00b0b3, 0xe48abbbf, 0x877e0660, 0x20b3001a, - 0x2bbf0e00, 0x0660e88a, 0x001a877e, 0x140010b3, 0x5c7e1ab2, 0x1bbf008c, 0x0660e08a, 0x001a877e, + 0x2bbf0e00, 0x0660e88a, 0x001a877e, 0x140010b3, 0x647e1ab2, 0x1bbf008c, 0x0660e08a, 0x001a877e, 0x21fba43d, 0x0005ecdf, 0xf4ffbf00, 0x49fef430, 0x08999001, 0x008f9fa0, 0xf9cf01c0, 0x4c99c700, 0x4c0099b3, 0x0190b301, 0x3e02f8f5, 0xcf00763a, 0x99c700f9, 0x0099b34c, 0x90b30125, 0x02f8f501, 0x00764f3e, 0xffffffd9, 0xc4f9ff7f, 0x01c0008f, 0xc700f9cf, 0x99b34c99, 0xb300db00, 0xf8f50190, 0x76703e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x76853e02, 0xc0008f00, 0x00f9cf01, 0xb34c99c7, 0x008d0099, 0xf50190b3, 0x9d3e02f8, 0xf9cf0076, 0x4c9dc700, 0x5e00d0b3, 0xf601d0b3, - 0xb23e02f8, 0xf9100076, 0x48e93501, 0xe100fd33, 0x0658d900, 0x4ffe0000, 0x01f9b501, 0x002e7cd9, + 0xb23e02f8, 0xf9100076, 0x4ce93501, 0xe100fd33, 0x0658d900, 0x4ffe0000, 0x01f9b501, 0x002e80d9, 0xa09abf00, 0x204809fd, 0xde0909f9, 0x00000658, 0x0409e920, 0x3502ecb5, 0x4bfe01fd, 0x03ed3501, 0x3502ed35, 0x080c01e9, 0x00006e7e, 0x0077ad3e, 0xad3e09f8, 0x00890077, 0x99cf01c2, 0x299cde00, - 0xef180000, 0x26ff0948, 0x9d1bf4f9, 0x0077ad3e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, + 0xef180000, 0x26ff094c, 0x9d1bf4f9, 0x0077ad3e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x76b23e9f, 0x60e08f00, 0xc1008906, 0x009ff601, 0x010099b8, 0x009cf600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0x853e9fb2, 0x00890076, 0x9fcf01c2, 0x1ff99500, 0x8c0194b3, 0x0076643e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x764f3e9f, 0x0149fe00, 0xbf089990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0c30f400, 0x30f400f8, 0x05ecdff4, 0x22f90000, 0x49feffbf, 0x14999001, 0x9fa0c1b2, 0x00299cd9, 0x019f9800, 0x00d9d2b2, 0x0e400000, 0x04f9fd08, 0x33750bf4, 0x0e1000a0, 0x01a43303, - 0x3ea0326c, 0x3d007809, 0x33040e04, 0x7e5e00b4, 0x33008a7a, 0x4b2400a0, 0x04330080, 0x884b0700, - 0x014afe00, 0xaa90080c, 0x8b2e7e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000654, 0x080e99bf, + 0x3ea0326c, 0x3d007809, 0x33040e04, 0x7e5e00b4, 0x33008a82, 0x4b2400a0, 0x04330080, 0x884b0700, + 0x014afe00, 0xaa90080c, 0x8b367e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000654, 0x080e99bf, 0x290090b3, 0x90014ffe, 0x00330cff, 0x9e981000, 0x98fea020, 0x623e2199, 0x9e980078, 0x98fea022, 0xf9b52399, 0x78833e01, 0x0149fe00, 0xbf149990, 0x05ecd99f, 0x99bf0000, 0xf9a6ea32, 0x3e200bf4, 0xfe007898, 0x99900149, 0x0e9fbf0c, 0x981fa01f, 0x29a00199, 0x0078693e, 0x003a317e, 0x090c25fb, - 0x0aa9a024, 0xd900f81f, 0x0000299c, 0xf9e830f4, 0x2d9f9882, 0x98289298, 0x90982b91, 0x0df1b029, - 0x980bc1b0, 0xd1b02a9f, 0x09e1b00a, 0xbf2e9998, 0x64f2ffcc, 0xb07410ff, 0xc1b00e91, 0x0da0330c, + 0x0aa9a024, 0xd900f81f, 0x0000299c, 0xf9e830f4, 0x2e9f9882, 0x98299298, 0x90982c91, 0x0df1b02a, + 0x980bc1b0, 0xd1b02b9f, 0x09e1b00a, 0xbf2f9998, 0x64f2ffcc, 0xb07410ff, 0xc1b00e91, 0x0da0330c, 0x0ea4330c, 0x78f93e10, 0xb264b200, 0x78ff3e75, 0xbd44bd00, 0x78ff3e54, 0x0d40b400, 0x090e50b4, 0xf5b926ff, 0x9500851b, 0x4c9d015d, 0x5555d901, 0x33d05555, 0xff333333, 0xd9ffe4c9, 0xe24ebcf4, 0xfff35fbc, 0xf994c4e0, 0x02e5b61e, 0xffe59eff, 0x0fd2d4f0, 0x950f0f0f, 0xe0ff02f1, 0xb410ffa4, 0xbca0acbc, 0xb994b1bd, 0x04ae951c, 0xff04bf95, 0xeabce59e, 0xf1fbbce0, 0xdc04e2fd, 0x01010101, 0xb2b4f2ff, 0x7eeab2cd, 0xb60038c2, 0xb0b318b5, 0x09090b24, 0x3300bdb3, 0x00b6b001, 0xf00b3cf0, - 0x84bd0136, 0x00799e3e, 0x0cffbac4, 0x7e240b40, 0x09008458, 0x00a93304, 0x58b20112, 0x7d9543b2, + 0x84bd0136, 0x00799e3e, 0x0cffbac4, 0x7e240b40, 0x09008460, 0x00a93304, 0x58b20112, 0x7d9543b2, 0x016c9d01, 0x333333d1, 0x5555d233, 0xc2ff5555, 0xf4d2ffe4, 0xbce26ebc, 0xe1fff37f, 0x1ef994c4, 0xff02e5b6, 0xf1ffe59e, 0x0f0fd4d4, 0xf0950f0f, 0xa4e1ff02, 0xbcb401ff, 0xbdbca0ac, 0x1cb994b1, 0x9504ae95, 0x9eff04bf, 0xe0eabce5, 0xfdf1fbbc, 0x01dc04e4, 0xff010101, 0xcdb2b4f4, 0xc27eeab2, @@ -1019,25 +1019,25 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x20943d06, 0x142ab809, 0x277e0030, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, 0x20943d06, 0xf421fb19, 0xecdff030, 0xf9000005, 0xf4ffbf32, 0x49fefc30, 0x20999001, 0x41fe9fa0, 0x9094bd01, 0x4efe1c11, 0x9019a001, 0xe9a018ee, 0xd3b2c2b2, 0xb926ff09, 0xfe201bf4, 0x240b0140, 0xb2140090, - 0x87d77e0c, 0xffa4f000, 0x3c1fa4b3, 0x10a000bf, 0x007b6e3e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, - 0x7e240d05, 0xf0008850, 0xa4b3ffa4, 0x49fe1a1f, 0x1c999001, 0x1f0a99bf, 0x49fe29a0, 0x18999001, + 0x87df7e0c, 0xffa4f000, 0x3c1fa4b3, 0x10a000bf, 0x007b6e3e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, + 0x7e240d05, 0xf0008858, 0xa4b3ffa4, 0x49fe1a1f, 0x1c999001, 0x1f0a99bf, 0x49fe29a0, 0x18999001, 0x39a099bf, 0x900149fe, 0x9fbf2099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, 0x30f41035, 0x05ecdff0, 0x32f90000, 0x30f4ffbf, 0x0149fefc, 0xa0209990, 0x0141fe9f, 0x119094bd, 0x014efe18, 0xee9019a0, 0xb2e9a014, 0x09d3b2c2, 0xf4b926ff, 0x40fe1d1b, 0x90240b01, 0x0cb21c00, - 0x0087d77e, 0x391fa433, 0x10a000bf, 0x007c073e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, 0x7e240d08, - 0x33008850, 0xfe1a1fa4, 0x99900149, 0x0a99bf18, 0xfe29a01f, 0x99900149, 0xa099bf14, 0x0149fe39, + 0x0087df7e, 0x391fa433, 0x10a000bf, 0x007c073e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, 0x7e240d08, + 0x33008858, 0xfe1a1fa4, 0x99900149, 0x0a99bf18, 0xfe29a01f, 0x99900149, 0xa099bf14, 0x0149fe39, 0xbf209990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0430f400, 0xf41035fb, 0xecdff430, 0xf9000005, 0xf4ffbf22, 0x49fefc30, 0x18999001, 0x4efe9fa0, 0x9094bd01, 0x40fe14ee, 0x90e9a001, - 0x09a01000, 0xd2b2c1b2, 0xb926ff09, 0xb20f1bf4, 0x7e240bec, 0x3e0087d7, 0xb0007c8c, 0xa4f00001, - 0xffb4f0ff, 0x240d010c, 0x0088507e, 0x201fa433, 0x900149fe, 0x99bf1499, 0x90014ffe, 0xffbf10ff, + 0x09a01000, 0xd2b2c1b2, 0xb926ff09, 0xb20f1bf4, 0x7e240bec, 0x3e0087df, 0xb0007c8c, 0xa4f00001, + 0xffb4f0ff, 0x240d010c, 0x0088587e, 0x201fa433, 0x900149fe, 0x99bf1499, 0x90014ffe, 0xffbf10ff, 0x038199e7, 0xffe719a0, 0x2fa00381, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, 0x30f40c25, 0x05ecdff4, 0x22f90000, 0x30f4ffbf, 0x0149fefc, 0xa0189990, 0x014efe9f, 0xee9094bd, 0x0140fe14, 0x0090e9a0, 0xb209a010, 0x09d2b2c1, 0xf4b926ff, 0xecb20f1b, - 0xd77e240b, 0x1b3e0087, 0x01b0007d, 0xffa4f000, 0x0cffb4f0, 0x7e240d20, 0x33008850, 0xfe181fa4, + 0xdf7e240b, 0x1b3e0087, 0x01b0007d, 0xffa4f000, 0x0cffb4f0, 0x7e240d20, 0x33008858, 0xfe181fa4, 0x99900149, 0xa099bf14, 0x0149fe19, 0xbf109990, 0xfe29a099, 0x99900149, 0xd99fbf18, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xf4003a31, 0x25fb0430, 0xf430f40c, 0x0005ecdf, 0xbf52f900, 0x0149feff, 0x32209990, 0xb29fa0b0, 0xb00405c4, 0x0cf523a6, 0x34bd00bb, 0xfe0142fe, 0x22900141, 0x1c119018, - 0x13a023a0, 0x2cb21bb2, 0x0084407e, 0xad33a532, 0xbf009b1f, 0x7e2bbf1a, 0x330084fc, 0xa00a00a4, + 0x13a023a0, 0x2cb21bb2, 0x0084487e, 0xad33a532, 0xbf009b1f, 0x7e2bbf1a, 0x33008504, 0xa00a00a4, 0x7e293e43, 0xbf2fbf00, 0x0ff4b619, 0xbc1494b6, 0x00df90f9, 0xbc010100, 0x0033909f, 0x06302e04, 0x0b0cf404, 0x65030433, 0x007dd83e, 0x2d050033, 0x59060433, 0x007e093e, 0x22889ab8, 0x1a277e00, 0x10a5b600, 0x007df33e, 0x7e8c9a90, 0xf1001a27, 0xa003ffa4, 0x7e293e4a, 0x889ab800, 0x277e0032, @@ -1050,479 +1050,479 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40c45fb, 0xecdfb830, 0xf9000005, 0xfeffbf82, 0x99900149, 0xa0010568, 0x11c1b09f, 0xb049b130, 0xe1b010d1, 0x33c4bf0f, 0x30180aa0, 0x08f40aa6, 0x3302050f, 0x050c0ba0, 0x0ca03303, 0xbd543d06, 0x014ffe94, 0xff9064bd, 0xb504bd60, 0xf9a001f9, - 0xff9274bd, 0xb2f92008, 0xb20ab2f1, 0x860e7e1b, 0x1fad3300, 0x193f0480, 0x1c009033, 0xb4bd010a, - 0xcd7e0cb2, 0x7bff0039, 0xa56aff95, 0xaeb29fb2, 0xf7b2e6b2, 0xb3010090, 0x3ed22404, 0x340083c9, - 0x040a4990, 0xf5239630, 0x34044a0c, 0x010a49c0, 0xc4f0b4bd, 0x39cd7eff, 0xb2a0b200, 0x0849c5b1, - 0x000008df, 0xf49fffff, 0x7e13f1b0, 0x33008a7a, 0xfe4d00a4, 0x24bd0146, 0x34bd1f0a, 0x6690443d, - 0x7fcd3e60, 0x0109c400, 0x321c0bf4, 0xb25b324a, 0x89ca7e6c, 0x1fa43300, 0x986ebf0f, 0x2ebc016f, - 0x313fbc20, 0x95014410, 0x009d0111, 0x9501ff01, 0x33d51bf4, 0x03c71fa9, 0x0083b13e, 0x0949b034, - 0xf4b926ff, 0x9cdf780b, 0xc4000029, 0xe994ff5e, 0x909fbc03, 0x98189f98, 0xf1fd1799, 0x0490fd04, - 0x1bf490a6, 0xf4f1a608, 0x02ff540b, 0xf413ff94, 0x1bf490a6, 0xf4f1a608, 0x9cd9440b, 0x94000029, - 0xf9bc03ef, 0x1ff998f0, 0x90000cb9, 0x1bb97cfe, 0x049cfd00, 0x981ff9b5, 0xfd9001e9, 0xfd090a5c, - 0xe9b5049b, 0x17f99801, 0xb5049cfd, 0xd99817f9, 0x049bfd01, 0x3e01d9b5, 0xf00083b1, 0x9cdbff54, - 0xb2000029, 0x0394b659, 0x98909bbc, 0x9998209f, 0x1451b01f, 0xfd04f1fd, 0x90a60490, 0xa6081bf4, - 0x100bf4f1, 0x44bd010e, 0xbd4ae130, 0x80db3e54, 0xb244bd00, 0xbd0cb21d, 0x3eb43d54, 0xc40080d0, - 0x0bf401c9, 0x14f0b425, 0x0006b4de, 0xffb9c400, 0xbc0394b6, 0x94b6909f, 0x909ebc03, 0x9f989ebf, - 0x404ebc01, 0x10515fbc, 0xdd9501bb, 0x01cc9d01, 0xf495cdff, 0xf43dcc1b, 0xb44af130, 0x9cdb1490, - 0xb6000029, 0x9bbc0394, 0x189f9890, 0xfd179998, 0x90fd04f1, 0xf490a604, 0xf1a6091b, 0x01200bf5, - 0xe43d94bd, 0xb01791b0, 0xe1301691, 0x81dc3e4b, 0x0169c400, 0x00b90bf5, 0x344b9034, 0x94df4bc0, - 0x0a000006, 0xff94f001, 0x9894b4bd, 0xffc4f006, 0x7e808fbc, 0xd20039cd, 0x000029f8, 0xb000b9b9, - 0xa1b00db1, 0x00abb90e, 0xb00b91b0, 0x8db20cb1, 0xa034343d, 0x09d1b04b, 0x4cfe3b32, 0x58cc9001, - 0x0089ca7e, 0x2c9829bf, 0x09d0b401, 0x351fa033, 0xdea0e4bd, 0xb401deb5, 0x2f980cb0, 0x092e9808, - 0xa0049bfd, 0x0bb0b429, 0xb594cbff, 0x90b40129, 0x04ebfd0c, 0xfd092eb5, 0x2fb504f9, 0x81bd3e08, - 0x16e0b400, 0xb517f0b4, 0x8ea0018f, 0xfd0ef0b4, 0x29a0059f, 0xff0db0b4, 0x29b595cb, 0x01331001, - 0x9008dd90, 0x88900822, 0x04343308, 0x4be03489, 0x9d017795, 0xee100166, 0x4be13001, 0xf59567ff, - 0x34ff321b, 0xff0949f0, 0x0bf4f926, 0x1490b429, 0x00299cdb, 0x0394b600, 0x98909bbc, 0x9998189f, - 0x04f1fd17, 0xa60490fd, 0xd71bf590, 0xf5f1a601, 0xb401d11b, 0xe5f013e0, 0x13e1b004, 0x900149fe, - 0x96bf6099, 0xb4019798, 0x9cdf1490, 0x3d000029, 0xb624bde4, 0x34bd0394, 0x30909fbc, 0x9b9057e1, - 0x5c98907c, 0x3e0ab1b0, 0xc40082cf, 0x0bf40109, 0x14f0b472, 0xde579034, 0x00000694, 0x0006b4db, - 0xf0010a00, 0x94b6ff94, 0x909fbc03, 0xb6039f94, 0xfbbc0394, 0x909ebcf0, 0x979896bf, 0x01f7b501, - 0xc034f6a0, 0xbcb4bd57, 0x37bc2026, 0xffc4f031, 0x0039cd7e, 0xbf018f98, 0x00b9b98e, 0xb904f9fd, - 0x8fb500a9, 0x04e9fd01, 0xf0b48ea0, 0x98f9bf0a, 0x9afd01ff, 0x05fbfd05, 0xa00ab0b4, 0x01bfb5b9, - 0x9557e034, 0x009d0111, 0x01ee1001, 0xff57e130, 0x1bf59501, 0x49feff79, 0x60999001, 0xa00197b5, - 0x4af03496, 0xb600fd33, 0xc224bc00, 0xb3d335bc, 0x891300d4, 0xa60ffffe, 0x090cf4c9, 0x5e3ef43d, - 0xdf940083, 0x0ada9516, 0xff0ac995, 0xafb2b5f9, 0xecb2beb2, 0xd4b3fdb2, 0x010f0f00, 0x0ffffe89, - 0x0df4c9a6, 0x0abf953c, 0x9516a994, 0x9fff0aab, 0xb2bfb2a5, 0xb2ecb2ae, 0x00d4b3fd, 0x89020f0f, - 0xa60ffffe, 0x190df4c9, 0x950aaf95, 0xb9940abd, 0x059ffd16, 0x9eb2dfb2, 0xfdb2ecb2, 0xb0b4030f, - 0x03f4f013, 0xb9fffc09, 0xe5f9ff94, 0x0d00d4b3, 0x0fffff89, 0x0df4c9a6, 0x08e9c50a, 0x0083a03e, - 0xb694c9ff, 0x0fdf0494, 0xffff0000, 0xf9fdf4ef, 0xfff70905, 0xa03e94f9, 0x90b40083, 0x0895f013, - 0x0a10e0b4, 0xb4e2a01f, 0xf3a00ff0, 0xa011b0b4, 0x0149feb9, 0xbf689990, 0x05ecd99f, 0x99bf0000, - 0x0bf4f9a6, 0x83e63e28, 0x49e03400, 0x73b262b2, 0xe926ff09, 0xfb8b1bf5, 0x71b260b2, 0x007f7d3e, - 0xb13e090a, 0x317e0083, 0x85fb003a, 0xc0008f48, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, - 0x83f13e02, 0x00f9cf00, 0xb34c99c7, 0xb3330090, 0xf8f60190, 0x84053e02, 0xc1008900, 0x009af601, - 0x010099b8, 0x009bf600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0x053e9fb2, 0x00f80084, - 0xaf95a9b2, 0xb0060a02, 0x0cf408f6, 0xf0bfa00c, 0x1f0a0394, 0x00f8c9a0, 0xbc01bb92, 0xbcffb0bc, - 0xffb4f0bc, 0xacf0aba6, 0xf900f808, 0xb2c0b202, 0x02a0b3dc, 0x02a6b039, 0xb30b0cf4, 0x3e1001a4, - 0xb3008491, 0xb32d07a0, 0x0a3b08a0, 0x84fa3e06, 0xb31f0a00, 0xbf670104, 0x1fb9c4df, 0x09bc1f0a, - 0x05f9fd94, 0xfa3edfa0, 0xd0a00084, 0x0084f83e, 0xbf07b9c4, 0x0294b6dd, 0x901f9ec4, 0xd63e0399, - 0xddbf0084, 0xbc05bfcd, 0x9fbc90ff, 0x9099bc90, 0x901f9ec4, 0x99b90599, 0x1f94f000, 0x0f909ebc, - 0x05f9bbff, 0xbb94f0ff, 0x9ebb04fe, 0x00ffb904, 0xfd04fdfd, 0xcfa005f9, 0x01fb1f0a, 0xb1b212f9, - 0xeb7ea0b2, 0xa033003c, 0xa43d0a00, 0x00853e3e, 0xdf0f1994, 0x01017000, 0xbc1404b6, 0x09bc000f, - 0x000ab800, 0x277e0006, 0xa1b2001a, 0x03800ab8, 0x1a277e00, 0x05a1fd00, 0xf001a6f0, 0x11fb01a4, - 0xdff430f4, 0x000005ec, 0xffbf32f9, 0x900149fe, 0xb2b21899, 0x06039fa0, 0xf523a6b0, 0xfe00960c, - 0x40fe0141, 0x14119001, 0xb2100090, 0x7e0cb21b, 0x32008440, 0x1fa433a3, 0xbf1abf7c, 0x84fc7e0b, - 0x00a03300, 0xbf19bf5a, 0x1494b60a, 0xbc0fa4b6, 0x00d9a0a9, 0xbc010100, 0x277ea0a9, 0xa4f0001a, - 0x04a0b3ff, 0x04a6b04c, 0xb0130cf4, 0x0cf402a6, 0x01a6b039, 0x3e2d18f4, 0xb30085db, 0xb02c08a0, - 0x0cf408a6, 0x05a4b30b, 0x85db3e10, 0x0aa0b300, 0x0ba0b31a, 0x3e060310, 0xbd0085f1, 0x85ef3e94, - 0x3e010900, 0x090085ef, 0x85ef3e02, 0xa0030900, 0x0149fe29, 0xbf189990, 0x05ecd99f, 0x99bf0000, - 0xf9a63a32, 0x7e070bf4, 0xfb003a31, 0x30f40c35, 0x05ecd9f8, 0x12f90000, 0x4ffe99bf, 0x0cff9001, - 0xf9a0b1b2, 0x40feff09, 0x08009001, 0x0bb209a0, 0x0085407e, 0x0e1fa433, 0x96b009bf, 0x0b9cf002, - 0x49fe1920, 0x0c999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0xe830f408, - 0x0005ecdf, 0xbf42f900, 0x0149feff, 0xb2289990, 0xb29fa0b0, 0x02a033c3, 0x02a63045, 0x330c0cf4, - 0x00a601ad, 0x0086963e, 0xb407a933, 0x08ad3300, 0x4a3e0098, 0xbab20087, 0x900140fe, 0x0bb22700, - 0x00860e7e, 0xad33a232, 0x3f01141f, 0x00963009, 0xf00b9cf0, 0xb83e0196, 0x04020087, 0xf523b630, - 0xc400fb0c, 0x44feffba, 0x0141fe01, 0x90204490, 0x4bb21c11, 0x407e1cb2, 0xa2320084, 0xde1fad33, - 0xff0ac400, 0x900140fe, 0x0bb22700, 0x00860e7e, 0xad33a232, 0x3f00c81f, 0x00943309, 0x3e94bd0a, - 0xbf0087b8, 0xb61abf49, 0xa4b61494, 0xa0a9bc0f, 0x01760cd9, 0xa0a9bc01, 0x001a277e, 0x3008a5b6, - 0x0df407a6, 0x3e060209, 0xc40087ba, 0x48d9ffaf, 0xbc000000, 0x3fa0f89f, 0x0087ba3e, 0xcbb2bab2, - 0x0085407e, 0xba3ea232, 0x04020087, 0xf423b630, 0xbac46b0c, 0x0141feff, 0x900144fe, 0x44901811, - 0xb21bb214, 0x84407e4c, 0x33a23200, 0xc44f1fa4, 0x40feff0a, 0x20009001, 0x0e7e0bb2, 0xa2320086, - 0x3a1fa433, 0x9433093f, 0x3f090a00, 0x0087b83e, 0x4b3f1a3f, 0xfe0141fe, 0x11900140, 0x1c009027, - 0x0db21cb2, 0x007aac7e, 0x1f3f093f, 0xf00794f0, 0x94b607f4, 0x059ffd03, 0x49fe39a0, 0x28999001, - 0xecd99fbf, 0xbf000005, 0xa62a3299, 0x070bf4f9, 0x003a317e, 0xf41845fb, 0xecdff830, 0xf9000005, - 0xfeffbf62, 0xff010149, 0xfe209990, 0xa5320142, 0xc4b2b3b2, 0x04bd9fa0, 0xb21c2290, 0x882a3e16, - 0xb25a3200, 0x7e2cb20b, 0x3300865d, 0xbf2a1fa4, 0xf416a629, 0x91b2091b, 0x0088273e, 0x0bf419a6, - 0x3e090a09, 0x90008835, 0x03a60100, 0xbfd508f4, 0xa01f0a22, 0x0149fe42, 0xbf209990, 0x05ecd99f, - 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0865fb00, 0xdff830f4, 0x000005ec, 0xffbf82f9, 0x900149fe, - 0xc2b22899, 0xd5b2b0b2, 0x9fa0cbb2, 0xa4b2e7b2, 0x7ea000bc, 0xb20016fc, 0xbca3b25b, 0x0ab2c022, - 0x7e6032bc, 0x01008458, 0x0c80b404, 0x7500a033, 0x43fe30b2, 0x24339001, 0x0088bb3e, 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0x0149feff, 0xb2289990, 0xb29fa0b0, 0x02a033c3, + 0x02a63045, 0x330c0cf4, 0x00a601ad, 0x00869e3e, 0xb407a933, 0x08ad3300, 0x523e0098, 0xbab20087, + 0x900140fe, 0x0bb22700, 0x0086167e, 0xad33a232, 0x3f01141f, 0x00963009, 0xf00b9cf0, 0xc03e0196, + 0x04020087, 0xf523b630, 0xc400fb0c, 0x44feffba, 0x0141fe01, 0x90204490, 0x4bb21c11, 0x487e1cb2, + 0xa2320084, 0xde1fad33, 0xff0ac400, 0x900140fe, 0x0bb22700, 0x0086167e, 0xad33a232, 0x3f00c81f, + 0x00943309, 0x3e94bd0a, 0xbf0087c0, 0xb61abf49, 0xa4b61494, 0xa0a9bc0f, 0x01760cd9, 0xa0a9bc01, + 0x001a277e, 0x3008a5b6, 0x0df407a6, 0x3e060209, 0xc40087c2, 0x48d9ffaf, 0xbc000000, 0x3fa0f89f, + 0x0087c23e, 0xcbb2bab2, 0x0085487e, 0xc23ea232, 0x04020087, 0xf423b630, 0xbac46b0c, 0x0141feff, + 0x900144fe, 0x44901811, 0xb21bb214, 0x84487e4c, 0x33a23200, 0xc44f1fa4, 0x40feff0a, 0x20009001, + 0x167e0bb2, 0xa2320086, 0x3a1fa433, 0x9433093f, 0x3f090a00, 0x0087c03e, 0x4b3f1a3f, 0xfe0141fe, + 0x11900140, 0x1c009027, 0x0db21cb2, 0x007aac7e, 0x1f3f093f, 0xf00794f0, 0x94b607f4, 0x059ffd03, + 0x49fe39a0, 0x28999001, 0xecd99fbf, 0xbf000005, 0xa62a3299, 0x070bf4f9, 0x003a317e, 0xf41845fb, + 0xecdff830, 0xf9000005, 0xfeffbf62, 0xff010149, 0xfe209990, 0xa5320142, 0xc4b2b3b2, 0x04bd9fa0, + 0xb21c2290, 0x88323e16, 0xb25a3200, 0x7e2cb20b, 0x33008665, 0xbf2a1fa4, 0xf416a629, 0x91b2091b, + 0x00882f3e, 0x0bf419a6, 0x3e090a09, 0x9000883d, 0x03a60100, 0xbfd508f4, 0xa01f0a22, 0x0149fe42, + 0xbf209990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0865fb00, 0xdff830f4, 0x000005ec, + 0xffbf82f9, 0x900149fe, 0xc2b22899, 0xd5b2b0b2, 0x9fa0cbb2, 0xa4b2e7b2, 0x7ea000bc, 0xb20016fc, + 0xbca3b25b, 0x0ab2c022, 0x7e6032bc, 0x01008460, 0x0c80b404, 0x7500a033, 0x43fe30b2, 0x24339001, + 0x0088c33e, 0x0bb24a32, 0x657e3cb2, 0xa1320086, 0x591fa433, 0x0bb23cbf, 0x00904ab2, 0x7e7db201, + 0xa6008473, 0x4218f405, 0x08f406a6, 0x88f93eda, 0xb24a3200, 0x7e3cb20b, 0x32008665, 0x1fa433a1, + 0xb23cbf2c, 0x904ab20b, 0x8db20100, 0x0084737e, 0x08f405a6, 0x89093e10, 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0x00e9b302, 0xaf18027f, 0x0141fe2c, 0x119094bd, 0x0019a054, 0x00f93303, + 0xc43d026d, 0x487e1db2, 0xa0b200a6, 0x5e00adb3, 0xbc17bf02, 0x7998f068, 0xf59fa601, 0x98024d08, + 0x94b30479, 0x05000a01, 0x00aeea3e, 0x3e0069b3, 0x027f9802, 0xf9a6f009, 0x022a0bf5, 0xf27e3ab2, + 0xa2b200a5, 0x1e00a9b3, 0x0c3c9802, 0x40fe7bb2, 0x34009001, 0x307e0ab2, 0x0ab200a6, 0xcc0570b5, + 0xc97e708b, 0xa0b200a6, 0xe900adb3, 0x0d00b401, 0x01a6f001, 0x01ce0bf5, 0x01d00cf5, 0x804cb43d, + 0x7e2ab200, 0xbf00b798, 0x070b943a, 0xb200804c, 0xb7817e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, + 0x76042f18, 0xf4f00894, 0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, + 0x18902fbc, 0x9d330999, 0x90018200, 0xf4b301ff, 0x043ef207, 0x8e3c00af, 0xf59f26f2, 0xc4016d08, + 0x94f0fffd, 0x529dbcff, 0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100adaf, + 0xf5006fd6, 0xb401450c, 0xbe3c0b10, 0xf81e3c98, 0x0bf4f926, 0xff94f017, 0xfd009939, 0x9033049f, + 0x010a0600, 0x0ce9bf3c, 0x01ee9001, 0xa601dd90, 0xce08f4e5, 0xed00c933, 0xf0293f00, 0x0bf40894, + 0x00a93308, 0x94bd00d0, 0x91b03ab2, 0x1391b014, 0x301291b0, 0x4bfe5b91, 0x5bbb9001, 0x00a7017e, + 0xadb3a0b2, 0x3400ef00, 0x90335b90, 0x3ab21100, 0x00a9e17e, 0xadb3a0b2, 0xb400db00, 0x40b40d00, + 0x014ffe11, 0xb250ff90, 0x070d942e, 0x4101f1b0, 0x3ab20080, 0x4cb2010b, 0x7e0011b0, 0xb200a5ec, + 0xb22cb20b, 0x014dfe3a, 0x7e4cdd90, 0xb400a4c6, 0xa0b214e0, 0x3ab21cb2, 0x0db2b4bd, 0x00a5ee7e, + 0x91000db3, 0x13b0b400, 0x90014afe, 0x657e34aa, 0x3a9800a9, 0x0db0b40c, 0x90014cfe, 0x677e48cc, + 0xa0b200b6, 0x6d00a4b3, 0x011290b4, 0xf491a6f0, 0x4e98321b, 0x70efcd01, 0x0600f4b3, 0x2918700f, + 0xff94f006, 0xbb909ebc, 0x49b5029f, 0xaea13e01, 0xb20bb200, 0x7e2cb23a, 0xb200a447, 0x00a4b3a0, + 0x0265bb34, 0x90014afe, 0xb27e34aa, 0x60b300a6, 0x90b42000, 0x8085bc0b, 0xb09095bc, 0xed3e0b91, + 0x020000ac, 0x00aed13e, 0xd13e0300, 0x00b400ae, 0xb23ab20c, 0xa6147e2b, 0xb594bd00, 0xea3e0579, + 0x030000ae, 0x00aeea3e, 0x49fe0200, 0x5c999001, 0xecd99fbf, 0xbf000005, 0xa60ab299, 0x170bf4f9, + 0x00af103e, 0x33062918, 0xfe4f009d, 0x00aec83e, 0x003a317e, 0xfb0830f4, 0x30f43485, 0x05ecdfdc, + 0x82f90000, 0x30f4ffbf, 0x0149fef8, 0xa04c9990, 0x0bb1b09f, 0xd4b2c2b2, 0xa5b2e6b2, 0x1700b9b3, + 0x00e9b301, 0x94bd0112, 0x3d0141fe, 0x481190c4, 0x1db219a0, 0x00a6487e, 0xadb3a0b2, 0xbf00fb00, + 0xf042bc19, 0xa6019998, 0xea08f59f, 0x005ab200, 0xa5f27e03, 0xb3a3b200, 0x00de00a9, 0x5c981bbf, + 0x0140fe0c, 0xb2300090, 0xa6307e0a, 0xcc0ab200, 0xc97e702b, 0xa8b200a6, 0xad00adb3, 0x7021cd00, + 0x420147fe, 0x77900080, 0xb0403e44, 0x0c00b400, 0x79a094bd, 0x09a6f009, 0x00091bf4, 0xb0473e02, + 0xa6f00900, 0x090df409, 0x473e0300, 0xc0b400b0, 0x0704b60b, 0x0db2e4bd, 0xb4bd5ab2, 0xb00021b0, + 0xec7e0171, 0x5abf00a5, 0x2cb20bb2, 0x817e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xee7e0db2, + 0x04b300a5, 0x3ab24500, 0x197eb4bd, 0xa0b200a4, 0x3700a4b3, 0x01bb7000, 0xf404a602, 0x40b2050d, + 0xb2101b90, 0xb03bbc6a, 0xa17e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xb27e6060, 0x14bd00a6, + 0x6d004db3, 0xb280b2ff, 0x7e3bb25a, 0x3e00a614, 0x0000b055, 0x0149fe02, 0xbf4c9990, 0x05ecd99f, + 0x99bf0000, 0xf9a60ab2, 0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005ecd9, 0xbf32f900, + 0x014ffe99, 0xb214ff90, 0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0xa77e0ab2, + 0x09bf00b7, 0x4c0090b3, 0x4800a4b3, 0x09bf91a0, 0xbf0192b5, 0x1000490f, 0xbf04f9b5, 0xb520090f, + 0x09bf05f9, 0xbf0693b5, 0x3501090f, 0x09bf1cf9, 0xbf2c9a35, 0xb5f0090f, 0x0fbf0af9, 0xb540f990, + 0x0fbf0ef9, 0xb5c0f990, 0x0abf0ff9, 0x00b0f23e, 0x49fea4bd, 0x14999001, 0xecd99fbf, 0xbf000005, + 0xf4f9a699, 0x317e070b, 0x35fb003a, 0xd030f408, 0x0005ecdf, 0xbf82f900, 0x0149feff, 0xb2509990, + 0x059fa0a3, 0x00a9b302, 0xb63004fb, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5f27e, 0x3abfa0b2, + 0x804cb4bd, 0x7e0db200, 0xb200b781, 0x00adb3a5, 0x093f04b1, 0xa24a9d33, 0x01091804, 0x9a469d33, + 0x02091804, 0x92469d33, 0x03091804, 0x8a539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, + 0xf0ff94f0, 0x94b6fff4, 0x10f4b608, 0xb6059efd, 0xf9fd18d4, 0x05dffd05, 0x045e0bf5, 0xd6b00505, + 0x5d0cf503, 0x013db504, 0x0e01d4b3, 0xb5500049, 0xe03e0239, 0x0d1800b1, 0x09091808, 0x180a0f18, + 0xd4f00b0e, 0xff94f0ff, 0xb6fff4f0, 0xf4b60894, 0x059dfd10, 0xfd18e4b6, 0xeffd05f9, 0x023eb505, + 0x0bb23ab2, 0x00a6147e, 0x09023a98, 0xf4a9a6ff, 0x04bd091b, 0x00b5f63e, 0x9007a5b6, 0x3ab5303b, + 0xb6da7e03, 0xb3a5b200, 0x03f500ad, 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb7a77e03, + 0xb3a5b200, 0x03d900ad, 0xfe0147fe, 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3503e, + 0x8ea0e4bd, 0x0f0044b3, 0xbd0c3a98, 0x3efe0cb4, 0xb200b273, 0xb24bb23a, 0xa5817e7c, 0xb3a5b200, + 0x039d00ad, 0x94f0793f, 0x120bf401, 0xb20c3a98, 0x7eff0c4b, 0x3e00b67e, 0xb200b34d, 0xa3387e7a, + 0x00a0b300, 0x0c3a980f, 0xfd0c4bb2, 0x00b2733e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, + 0xb400b342, 0x3ab209b0, 0x8db2010c, 0x00a6487e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, + 0x980a91b0, 0x54b354f5, 0xb0b43900, 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, + 0xa17e1ab2, 0x30bc00b7, 0x4309b800, 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b30d, + 0xff900122, 0x1424b318, 0xb63a3ebe, 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, + 0xcc00f3f0, 0x96cb70ff, 0xcb4bb21f, 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2ee, 0x4bb20c3a, + 0x7e7e6cb2, 0xa5b200b6, 0xb400adb3, 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, + 0xbd7e8ab2, 0xa5b200b7, 0x9400adb3, 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, + 0x39bc0001, 0x0b91b090, 0x5300f9b3, 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b7987e, + 0x3e0f60b4, 0x9800b46b, 0x2bb20d3a, 0x7e0c41b0, 0x3300a2fe, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, + 0x7e38cc90, 0xb300b667, 0x020c00ad, 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, + 0x0c2bb20d, 0xa2f67e01, 0x014cfe00, 0x2bb23ab2, 0x7e30cc90, 0xb300a59c, 0x981306a4, 0x2bb20c3a, + 0x7e7efd0c, 0x683e00b6, 0xadb300b4, 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, + 0x091bf4ff, 0x683e0260, 0x3a9800b4, 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b667, 0x019800ad, + 0x343af034, 0xf9263690, 0x60100df4, 0xff1be402, 0x0c3a98ff, 0x00b45d3e, 0xb20c3a98, 0x7efd0c2b, + 0xb300b67e, 0x017000ad, 0x98012290, 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, + 0x00b49f3e, 0x9473e97f, 0x010d0a00, 0x00b4993e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, + 0xe308f4fa, 0x0b00c4b3, 0x3e547cb5, 0x3300b5db, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, + 0x5479b56d, 0xf4bde4bd, 0x00b4de3e, 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, + 0xf4f9a603, 0x553ee908, 0x94bd00b5, 0x79b5f101, 0xb224bd54, 0xb52f3e1b, 0xe4407f00, 0xf4ffff09, + 0xf10f260b, 0x1bf4bfa6, 0xff0be40b, 0xb5273eff, 0x0c3a9800, 0xffff0ce4, 0x00b67e7e, 0xb900adb3, + 0xff0be400, 0x9019b2ff, 0x44900122, 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, + 0x3c980c3a, 0xb67e7e0a, 0x00adb300, 0x31b5008c, 0xb5db3e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, + 0x04bd00f3, 0x3e527fb5, 0x7f00b593, 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, + 0xb300b67e, 0xb45200a4, 0xe9980be0, 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, + 0xffff0be4, 0x00b67e7e, 0x2d00a4b3, 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5817e, 0x1900a4b3, + 0x98469034, 0x94f0517f, 0xf0f9bcff, 0x3e517fb5, 0x0a00b5db, 0x3ea5b203, 0x9000b5e6, 0x77900188, + 0x148db318, 0x49fefd90, 0x3c999001, 0x517e9abf, 0xfc3e00b7, 0x030500b5, 0x00b5fe3e, 0x0bb204bd, + 0x147e3ab2, 0x50b300a6, 0x3a981a00, 0x7e04bd0c, 0x9800b6d0, 0x30b50d3a, 0xb7517e0c, 0x0d30b500, + 0x900149fe, 0x9fbf5099, 0x0005ecd9, 0xb299bf00, 0xf4f9a65a, 0x403e110b, 0x010500b6, 0x00b5fc3e, + 0x003a317e, 0xf93085fb, 0x7ea0b202, 0x9800a5f0, 0xd07e0c0a, 0x0a9800b6, 0xb7517e0d, 0x7e0ab200, + 0xbd00b751, 0xbf01fba4, 0x0aafb2a9, 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, + 0x020aafb2, 0x18f4b9a6, 0x01b9900b, 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, + 0xfbb500f8, 0xb5fca002, 0x00f801fc, 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, + 0xa998a9a0, 0xa6aabf01, 0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7517e, 0x30f400f8, 0x05ecdff8, + 0x32f90000, 0x49feffbf, 0x14999001, 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, + 0xb60141fe, 0x119002b4, 0x7e1ab210, 0xb300b7bd, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, + 0x9eb201e9, 0xa699fcbc, 0xf408f490, 0x3da0ddbf, 0x00b7363e, 0x49fe020a, 0x14999001, 0xecd99fbf, + 0xbf000005, 0xf4f9a699, 0x317e070b, 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, + 0xa6f00bac, 0x01aab901, 0x44da00f8, 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, + 0x2944da00, 0xd77e0000, 0xa6300042, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, + 0x0b7e7e00, 0xf900f800, 0x3da0b202, 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, + 0x7ea43da0, 0xb000382a, 0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xecdfe430, 0xf9000005, 0xfeffbf82, + 0x45fe0149, 0x3c999001, 0xa00147fe, 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, + 0xff0d2cbb, 0x0000c17e, 0xeb00a433, 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, + 0x3e043d00, 0x9800b979, 0x2cd9023f, 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, + 0xff090159, 0xf43379a0, 0xf77e1800, 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, + 0xbd0043f0, 0xb8b93e14, 0x0241bc00, 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, + 0xff2ce49a, 0xb26bb2ff, 0x1300de0d, 0x1a7e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, + 0x7c0eb204, 0x10bc2020, 0x1300da10, 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, + 0xa6000013, 0xa408f414, 0x00b9683e, 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, + 0x18389003, 0x090159b5, 0x3379a0ff, 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, + 0xff26e4f1, 0x3e24bdff, 0xbc00b959, 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, + 0x042d9001, 0x00da1eb2, 0x7e000013, 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, + 0x40417c00, 0x3500a433, 0x001424d9, 0x7e9abf00, 0xa000ac44, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, + 0xa6000013, 0xa608f426, 0x5c985bbf, 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, + 0x0d33000f, 0x30fe7100, 0x020f3a01, 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, + 0x717e38aa, 0xf33e000f, 0x02f900b7, 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, + 0xa6008961, 0x009fcf02, 0x1000f5f1, 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, + 0x00a43300, 0x2930d915, 0x9abf0000, 0x00009b7e, 0x1e3e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, + 0xb802a400, 0x000200aa, 0x920aa5b6, 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, + 0x000001fb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0xfb3a453a, 0x7158de23, 0xaef7305e, 0xd220040f, - 0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8db5cb00, 0x30cfe9a4, 0xc1a3eea2, 0x79a1340e, + 0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x294f2cc2, 0x883a9d68, 0x493e2990, 0xc8e27d59, + 0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8fc5fac6, 0xe1f366be, 0x1ec159bf, 0x352ff984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index 61230d1040..e55f4f5dfe 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -35,7 +35,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00fec0d0, 0x0004fe00, 0x0017167e, 0x08f802f8, 0xa4b300f8, 0x9c890a00, 0x9abf000f, 0x1100a0b3, 0x0d00b0b3, 0xa001aa98, 0xf8a43dba, 0x0a02f800, 0xbd00f8ff, 0xfc30f494, 0x40fe02f9, 0x04009001, - 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002e8989, 0xa43d9d20, 0x00006b3e, + 0x0db209a0, 0x0003237e, 0xa4b3afb2, 0x0dbf1601, 0x0a01d4b3, 0x002e8d89, 0xa43d9d20, 0x00006b3e, 0xfc09040a, 0x0bf4f9a6, 0xfbff0a05, 0x337e0405, 0xa0330000, 0xa0330a04, 0x02f80600, 0xb37e00f8, 0xafb20003, 0x0801a4b3, 0x00f8a43d, 0xfc09040a, 0x0bf4f9a6, 0x0a02f807, 0xbd00f8ff, 0xbdc4bdb4, 0x007e7ed4, 0xf900f800, 0xb2a2b222, 0xb2c0b2b1, 0xb21bb22a, 0x7eff0d0c, 0x3300007e, 0xfbf400a4, @@ -157,11 +157,11 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0142fe01, 0x90271190, 0x1ab22622, 0x5e7e2bb2, 0x020a0038, 0x787eab32, 0x0abf0038, 0x00043998, 0x3f95f901, 0x7e2b3f1a, 0xbf003878, 0x009b7e3a, 0xfb0a3200, 0x5d330c65, 0x3dff5c00, 0x0f4b3e04, 0x3dbcb200, 0x8aabb2d4, 0x7e0010e0, 0xf8000e6b, 0x0dbcb200, 0x8aabb201, 0x7e0010e0, 0xf8000e6b, - 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2e808900, 0x0b9abf00, 0x00de7eff, 0xff19c400, + 0xb212f900, 0xb3b132a0, 0xf80a00a4, 0x100e3e09, 0x2e848900, 0x0b9abf00, 0x00de7eff, 0xff19c400, 0x0301008f, 0xbc099e94, 0xefcfe0ef, 0x8099b800, 0x94b60001, 0x009dcf09, 0xf0020918, 0x09352095, 0xf40fa602, 0xf63e411b, 0xf918000f, 0x2094f002, 0x3f340bf4, 0x009433f9, 0xf8cbbc0b, 0x000fef3e, - 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002e68, - 0xc91bf4fd, 0x002e8089, 0x9b7e9abf, 0x11fb0000, 0x0c8b02f9, 0x127e0011, 0xa0320000, 0x0f00a033, + 0xf001f918, 0x9990ff94, 0x049afd03, 0xf6f0f9bc, 0xff3e00ef, 0x1bc4000f, 0x8cfc0aff, 0xa6002e6c, + 0xc91bf4fd, 0x002e8489, 0x9b7e9abf, 0x11fb0000, 0x0c8b02f9, 0x127e0011, 0xa0320000, 0x0f00a033, 0x0000ea7e, 0x7eff0bc4, 0x8900184a, 0xbf00110c, 0x11108990, 0x899fbf00, 0x180010fc, 0x9e35180e, 0xf40fa60e, 0x0918101b, 0x00943319, 0x3ea4bd0a, 0x1800107a, 0xb4331d0b, 0xa4bd0a00, 0x00106f3e, 0x3d200a90, 0x13607ec4, 0x00a6b000, 0x3d0e1ef4, 0x19093594, 0x00111089, 0x01fb90a0, 0x89ffa4f0, @@ -230,11 +230,11 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x31f400f8, 0x0028f400, 0x02f800f8, 0x477e00f8, 0x00f80019, 0x001434d9, 0x0d9b1800, 0x7e0c9a18, 0xf8001a12, 0x1a127e00, 0x7e00f800, 0xf80019cd, 0x14008900, 0x0099cf02, 0xf40194f0, 0xf17e160b, 0x008f003c, 0xf9ce0213, 0x0195f000, 0xf800f9f7, 0xf802f800, 0xf830f400, 0x0005ecdf, 0xbf02f900, - 0x0149feff, 0xa0089990, 0xd9f43d9f, 0x00002e89, 0x004f9f20, 0x00ffcf06, 0xcf07004e, 0x004900ee, + 0x0149feff, 0xa0089990, 0xd9f43d9f, 0x00002e8d, 0x004f9f20, 0x00ffcf06, 0xcf07004e, 0x004900ee, 0x0099cf02, 0x95049ffd, 0xeeb910ef, 0x049efd00, 0xff00ffb9, 0x09c4049f, 0x070bf401, 0x003b797e, 0x100009e4, 0x0f2f0bf4, 0x0149fe01, 0x0289008e, 0x20079990, 0x00e9ce9f, 0x9ffdfe0f, 0x00e9f704, 0x001408d9, 0xfe9abf00, 0x010c014b, 0x7e07bb90, 0xe400006e, 0x73800009, 0x7e080090, 0x49001871, - 0x90f70100, 0x0149fe00, 0xbf089990, 0x05ecd99e, 0x9fbf0000, 0x002e89d9, 0xa69a3f00, 0x070bf4ef, + 0x90f70100, 0x0149fe00, 0xbf089990, 0x05ecd99e, 0x9fbf0000, 0x002e8dd9, 0xa69a3f00, 0x070bf4ef, 0x003a317e, 0x0a0805fb, 0xf900f801, 0x03a99802, 0x94f0a0b2, 0x0d0bf401, 0x277eaabf, 0x673e001a, 0xa9bf0019, 0x98009acf, 0x0998030f, 0x020e9801, 0xff02f4f0, 0x9ea694a9, 0x320b9cf0, 0x00f0b39a, 0x0096300c, 0x320b9cf0, 0xf401fb9a, 0x12f9ec30, 0x900149fe, 0xecd10899, 0xa0000005, 0x019bb59a, @@ -304,11 +304,11 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x9b7ea032, 0xdd7e000a, 0x1fbf000d, 0x0a3229bf, 0x0bf4f9a6, 0x3a317e07, 0x1855fb00, 0x3d7e040a, 0xa033003a, 0x508a2400, 0x277e1200, 0xa4f0001a, 0x150bf401, 0x1200588a, 0x001a277e, 0x1a00a0b3, 0xf407a9c4, 0x02f8070b, 0x020a00f8, 0x003a3d7e, 0x0600a433, 0x00f802f8, 0x00140cd9, 0xdb9abf00, - 0x40000000, 0x08b4aab8, 0x83ed7e00, 0xd900f800, 0x0000140c, 0x00db9abf, 0xb8400000, 0x0008c4aa, - 0x0083ed7e, 0x0cd900f8, 0xbf000014, 0x0000db9a, 0xaab88000, 0x7e0008c4, 0xf80083ed, 0x140cd900, + 0x40000000, 0x08b4aab8, 0x83f57e00, 0xd900f800, 0x0000140c, 0x00db9abf, 0xb8400000, 0x0008c4aa, + 0x0083f57e, 0x0cd900f8, 0xbf000014, 0x0000db9a, 0xaab88000, 0x7e0008c4, 0xf80083f5, 0x140cd900, 0x99bf0000, 0x01c0008f, 0xcf609a90, 0x99c700f9, 0x0090b34c, 0x0190b337, 0x3e02f8f6, 0xcf00222b, 0x99c700f9, 0x0090b34c, 0x0190b30e, 0x3e02f8f6, 0x8b00223f, 0xcf01c200, 0x18d900bb, 0xfd040400, - 0xed7e05b9, 0x00f80083, 0x01c10089, 0xdf009af6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, + 0xf57e05b9, 0x00f80083, 0x01c10089, 0xdf009af6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x223f3e9f, 0xd902f900, 0x0000140c, 0xa0b299bf, 0x08c89ab8, 0x1a277e00, 0xbb010900, 0xa9fd0490, 0x0bacf004, 0x02f901fb, 0x00140cd9, 0x8f9ebf00, 0xcf01c000, 0x99c700f9, 0x0099b34c, 0x90b301bb, 0x02f8f501, 0x0022b33e, 0xc700f9cf, 0x99b34c99, 0xb3019700, 0xf8f50190, 0x22c83e02, 0x00f9cf00, @@ -318,7 +318,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb80099b3, 0x0190b300, 0x3e02f8f5, 0xcf00233a, 0x99c700f9, 0x0099b34c, 0x90b30081, 0x02f8f501, 0x00234f3e, 0xc700f9cf, 0x90b34c99, 0x90b35700, 0x02f8f601, 0x0023643e, 0x0065f57e, 0x000000d9, 0x9409ff40, 0x7e070bf4, 0xd90067e7, 0x02000000, 0x000000df, 0xb409ff04, 0xf4940fff, 0xbffd060b, - 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000140c, 0xaab89abf, 0x7e0008c4, 0xfb0083ed, + 0x0000df05, 0x0fff0800, 0x060bf494, 0xd905bffd, 0x0000140c, 0xaab89abf, 0x7e0008c4, 0xfb0083f5, 0xc2008901, 0x0099cf01, 0x95049dff, 0x94b31f09, 0x783eae01, 0xefb80023, 0x890008a4, 0xf601c100, 0xf1df009f, 0xb8800000, 0x02010099, 0xcf009ff7, 0x9fb2009f, 0x0023643e, 0x01c20089, 0x8f009dcf, 0x3e01c000, 0xb800234f, 0x000890ef, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, @@ -443,36 +443,36 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0032b13e, 0xb53e3505, 0x02050032, 0x0032b53e, 0x003a317e, 0xf42885fb, 0xecdff430, 0xf9000005, 0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56, 0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033, - 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06d, 0x00a0b31a, 0x7eb43d1a, 0xb300b105, - 0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05ecd99f, 0x99bf0000, + 0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b075, 0x00a0b31a, 0x7eb43d1a, 0xb300b10d, + 0xbf1200a0, 0x7eff001a, 0x3e00b647, 0x00003371, 0x0149feff, 0xbf149990, 0x05ecd99f, 0x99bf0000, 0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05ecdfd8, 0x62f90000, 0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03, 0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000654, 0x0038327e, - 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50741, - 0x352bb201, 0x42b51540, 0xbd92a006, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, + 0xa4b35aa0, 0x02f80c00, 0x1a3e0501, 0x49fe0037, 0x28999001, 0x00299cd4, 0xb51cb200, 0x91b50841, + 0x352bb201, 0x42b51940, 0xbd92a007, 0x10dc4ed4, 0x0020d07e, 0xad33a132, 0xbf015900, 0x33993f59, 0x980d0090, 0x95f00149, 0x0149b508, 0x000654d9, 0x1899bf00, 0x90336999, 0x9cdf1300, 0x98000029, - 0x95f101f9, 0xf9b54000, 0x299cda01, 0x037e0000, 0x3098009c, 0x01027e02, 0x8aa3d900, 0xacb20000, - 0xb20091b0, 0xbdb4bd0d, 0x2e70da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, - 0x1e000000, 0xfe509035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94ef7e2b, 0x1fa43300, - 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x00950a7e, 0x061fa033, 0xb4bd09f8, 0x0a7e020a, - 0x9cda0095, 0x7e000029, 0xfe009ab2, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, - 0xd9320204, 0x00000654, 0xa0b39abf, 0xb4d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, - 0x159f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, - 0x033e9824, 0x002a3cd9, 0x2a44df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, - 0x1c391801, 0x21009033, 0x00299cdf, 0x08399800, 0x982dfe98, 0x9efd2efd, 0x2df9b505, 0xfd093998, - 0xf9b5059d, 0x01087e2e, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, + 0x95f101f9, 0xf9b54000, 0x299cda01, 0x0b7e0000, 0x3098009c, 0x01027e02, 0x8aabd900, 0xacb20000, + 0xb20091b0, 0xbdb4bd0d, 0x2e74da04, 0x01b00000, 0x08013001, 0xc87e010e, 0x9cd90013, 0xdf000029, + 0x1e000000, 0xfe549035, 0x99900149, 0x0142fe34, 0x22909fa0, 0xb2010a38, 0x94f77e2b, 0x1fa43300, + 0xc42bbf1b, 0x1bf401b9, 0x01b5f014, 0x2ba0010a, 0x0095127e, 0x061fa033, 0xb4bd09f8, 0x127e020a, + 0x9cda0095, 0x7e000029, 0xfe009aba, 0xb4bd014a, 0x010dc4bd, 0x7e34aa90, 0x3e0075b0, 0x33003574, + 0xd9320204, 0x00000654, 0xa0b39abf, 0xb8d97f00, 0x98000029, 0x9bbf019c, 0x9cd9f43d, 0xbd000029, + 0x199f35d4, 0x7e10dc4e, 0x320020d0, 0x356f3ea1, 0x030d3300, 0x0e7e0207, 0x39180001, 0x00903308, + 0x033e9824, 0x002a40d9, 0x2a48df00, 0x9ea00000, 0xb5043e98, 0x3998019e, 0x98f9a005, 0xfeb5063e, + 0x1c391801, 0x21009033, 0x00299cdf, 0x08399800, 0x982efe98, 0x9efd2ffd, 0x2ef9b505, 0xfd093998, + 0xf9b5059d, 0x01087e2f, 0x3e143d00, 0x33003574, 0x01ab001d, 0xb2016b18, 0x0f817e3a, 0xfe020900, 0xff90014f, 0x3df92048, 0x02f93594, 0x09033318, 0xb2b4bd04, 0x03f335fa, 0x7e01f935, 0x3e000f71, 0xfe00371a, 0x41fe0140, 0x44009001, 0xfe401190, 0x0ab20142, 0xb23c2290, 0x3d2cb21b, 0x75b07ed4, 0x02399800, 0x010a0fbf, 0x1bf4f9a6, 0x0530de3c, 0xe93f0000, 0x0e009033, 0x1e0a943d, 0x063ee920, - 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098b97e, 0x0036063e, 0x1bb20ab2, - 0x3e7e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, + 0xffd90036, 0xff200000, 0x94b394f9, 0x0ab2121c, 0x2cb21bb2, 0x0098c17e, 0x0036063e, 0x1bb20ab2, + 0x467e2cb2, 0x4bfe008d, 0x44bb9001, 0xa9c4bebf, 0xffffdf1f, 0x94b6e0ff, 0x04effd18, 0xa0e59eff, 0x0000d9be, 0xe9ff4000, 0x6b0bf494, 0x681fa433, 0x900149fe, 0x9dbf4099, 0xbf049992, 0x1ee4339c, 0x0003df42, 0xff89ff00, 0xefff3fff, 0x94d9fff4, 0xff0294b6, 0xc0b3e5f9, 0xe9c50b00, 0x36703e03, 0x95fd0900, 0xe9fd16df, 0x00f0b304, 0x01e9c50d, 0x943eb9a0, 0xfe090036, 0x3e94e9ff, 0xdf003670, 0xff000000, 0xffffffd9, 0xf4efff00, 0xfd94d9ff, 0xbfa005f9, 0xfe0149fe, 0x9990014f, 0x44ff9040, 0xffbf9ebf, 0xbf049992, 0x0499929d, 0x99929fa0, 0x929ea004, 0x9da00499, 0x000a747e, 0x00299cd9, - 0x48991800, 0x0a009433, 0xd23e02f8, 0x90330036, 0x4efe1e01, 0x38ee9001, 0xffdfe9bf, 0xfde0ffff, - 0x00df049f, 0xfd010000, 0xe9a0059f, 0x9cd9f43d, 0x0d000029, 0x489f3501, 0xfe014bfe, 0xbb90014c, + 0x4c991800, 0x0a009433, 0xd23e02f8, 0x90330036, 0x4efe1e01, 0x38ee9001, 0xffdfe9bf, 0xfde0ffff, + 0x00df049f, 0xfd010000, 0xe9a0059f, 0x9cd9f43d, 0x0d000029, 0x4c9f3501, 0xfe014bfe, 0xbb90014c, 0x30cc9034, 0x90014afe, 0xb07e38aa, 0x9b7e0075, 0x143d000a, 0x00371a3e, 0x49fee401, 0x4c999001, 0xecd99fbf, 0xbf000005, 0xa61a3299, 0x070bf4f9, 0x003a317e, 0xfb0c30f4, 0xa9922865, 0x929ba004, 0xecb548ae, 0x00008906, 0xb2e9a030, 0x9294bdaf, 0xfab24cff, 0x00f8f9a0, 0x8f7e02f9, 0xa4b3005c, @@ -619,9 +619,9 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x1c339000, 0x05242290, 0xbf040402, 0x0d080c6a, 0x7e3bb2ff, 0x330000c1, 0x98f400a4, 0x193f0131, 0xeb079433, 0x3d041918, 0x2944da04, 0x94330000, 0x907e0a00, 0xa0320043, 0xb2013b18, 0x0f817e1a, 0x00043300, 0x022035ca, 0x11182520, 0x352ab203, 0xb4bd0124, 0x7e032135, 0x3e000f71, 0xf40048eb, - 0xecdff430, 0xf9000005, 0xbdffbf22, 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x7cd21499, - 0xa000002e, 0x7e01b29f, 0x3e0074f8, 0x9800497e, 0x993f0119, 0x0a099433, 0x967e0ab2, 0x70da0033, - 0x7e00002e, 0xb2001475, 0xb22abfad, 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002e70, 0x0014b57e, + 0xecdff430, 0xf9000005, 0xbdffbf22, 0x0140fe94, 0xb50c0090, 0x09a00109, 0x900149fe, 0x80d21499, + 0xa000002e, 0x7e01b29f, 0x3e0074f8, 0x9800497e, 0x993f0119, 0x0a099433, 0x967e0ab2, 0x74da0033, + 0x7e00002e, 0xb2001475, 0xb22abfad, 0x7e080c0b, 0x330000c1, 0xdadc00a0, 0x00002e74, 0x0014b57e, 0x00497e3e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -641,28 +641,28 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xa13018a1, 0x24a13020, 0x300101b0, 0x11300811, 0x1c01300c, 0x804e080d, 0x05d8da00, 0x0a7e0000, 0x20da005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x019000ad, 0xf1493f4c, 0xdb0000c3, 0x00000120, 0x3028a130, 0xa13000a1, 0x14a13010, 0x3018a130, 0xa13020a1, 0x0101b024, 0x30081130, 0x01300c11, - 0x4e070d1c, 0xdcda0100, 0x7e000005, 0xda005d0a, 0x00002e7c, 0x080c1bb2, 0x0059377e, 0x4300ad33, + 0x4e070d1c, 0xdcda0100, 0x7e000005, 0xda005d0a, 0x00002e80, 0x080c1bb2, 0x0059377e, 0x4300ad33, 0x48c24c01, 0x0000c3f1, 0x0000fcdb, 0x28a13000, 0x3000a130, 0xa13010a1, 0x18a13014, 0x3020a130, 0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005e0, 0x005d0a7e, 0x001404da, 0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028, 0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09, - 0x0005e4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb, + 0x0005e4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7d3, 0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130, 0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05e8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04, 0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249, 0x7e004d7d, 0x7e004df2, 0x7e005208, 0x7e005216, 0x7e0053af, 0x7e0053d2, 0x7e0053e7, 0x7e0053fc, 0x7e005438, 0x7e00544d, 0x7e00591d, 0x7e00706d, 0x7e005462, 0x7e004ea6, 0x330059ae, 0xf80600a0, - 0x2c30f402, 0x30d911fb, 0xbf000014, 0x2e88da99, 0x99980000, 0xf895f905, 0xf8400a00, 0x0070df00, + 0x2c30f402, 0x30d911fb, 0xbf000014, 0x2e8cda99, 0x99980000, 0xf895f905, 0xf8400a00, 0x0070df00, 0x00492000, 0x009ff607, 0xcf03004e, 0xff4f00e9, 0x049ffdcf, 0x800095f1, 0x8f00e9f6, 0x4900b071, 0x9ff60400, 0x15008f00, 0x00f9ce02, 0xf70195f0, 0x00f800f9, 0xf820004a, 0x01004f00, 0xf000f9ce, 0xf9f71095, 0x07004f00, 0xf000f9ce, 0xf9f71095, 0x04004f00, 0xf000f9ce, 0xf9f71095, 0xd900f800, - 0x00001430, 0x8ada99bf, 0x9800002e, 0x95f90899, 0x367e00f8, 0xa433004e, 0xaddf1100, 0x49deadde, + 0x00001430, 0x8eda99bf, 0x9800002e, 0x95f90899, 0x367e00f8, 0xa433004e, 0xaddf1100, 0x49deadde, 0x9ff61000, 0x7e02f800, 0x7e004e54, 0x7e004e15, 0xf8004e69, 0x90008900, 0x0099cf00, 0xf40194f0, 0x0089150b, 0x9fcf00a5, 0xf0ef0e00, 0xfefd07f5, 0x009ff604, 0x008900f8, 0x9fcf0090, 0x01f9c400, 0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00, 0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204, 0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014, - 0x95f90e99, 0x1e0a00f8, 0x00b9a27e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, + 0x95f90e99, 0x1e0a00f8, 0x00b9aa7e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f, 0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8, 0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00, 0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000, @@ -690,24 +690,24 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x877e0c0a, 0xb4bd001a, 0xd4bdc4bd, 0x137e0f0a, 0xb4bd001f, 0x010ca1b2, 0x100ad4bd, 0x001f137e, 0x1a90a0b2, 0x1a277e0c, 0x10abc500, 0x7e0c0a90, 0xfb001a87, 0x1430d911, 0x99bf0000, 0x002928da, 0x11999800, 0x00f895f9, 0xc4bdb4bd, 0xa4bdd43d, 0x003aa97e, 0x30da00f8, 0x3d000029, 0x5e7f7eb4, - 0x2930d900, 0x99bf0000, 0x060094b3, 0x00f802f8, 0x001430d9, 0x3d9fbf00, 0x2e8bda94, 0xa9200000, + 0x2930d900, 0x99bf0000, 0x060094b3, 0x00f802f8, 0x001430d9, 0x3d9fbf00, 0x2e8fda94, 0xa9200000, 0xf910f998, 0xf8a43d95, 0x140cd900, 0x9abf0000, 0xb803034b, 0x0002dcaa, 0x001a877e, 0x066f448a, 0x001a277e, 0x000610d9, 0xffa4f100, 0x42408f3f, 0xd99aa00f, 0x00000614, 0x9fa0a43d, 0x30d900f8, - 0xbf000014, 0xda943d9f, 0x00002e8c, 0xf9bfa920, 0xa43d95f9, 0x02f900f8, 0xd4bdc4bd, 0x110ab4bd, + 0xbf000014, 0xda943d9f, 0x00002e90, 0xf9bfa920, 0xa43d95f9, 0x02f900f8, 0xd4bdc4bd, 0x110ab4bd, 0x001f137e, 0x0484a0b8, 0x7e0ab200, 0xc5001a27, 0x0ab201ab, 0x001a877e, 0x08b8c08a, 0x001a277e, 0xa9fffb09, 0xb8c08ab4, 0x1a877e08, 0xb9408a00, 0x1a277e08, 0xffe00900, 0x408ab4a9, 0xb5f008b9, 0x1a877e02, 0xbd01fb00, 0xbdc4bdb4, 0x7ea4bdd4, 0xd9001f13, 0x00001430, 0x0cd99fbf, 0xa0000014, - 0x2e8eda9a, 0xf9980000, 0xf895f90c, 0xd002f900, 0x0000140c, 0xff0b0abf, 0x08b8aab8, 0x1a877e00, + 0x2e92da9a, 0xf9980000, 0xf895f90c, 0xd002f900, 0x0000140c, 0xff0b0abf, 0x08b8aab8, 0x1a877e00, 0x0b0abf00, 0xbcaab8ff, 0x877e0008, 0x0abf001a, 0xaab8ff0b, 0x7e0008c0, 0xbf001a87, 0xb8ff0b0a, 0x0008c4aa, 0x001a877e, 0x008b0abf, 0xaab87000, 0x7e0008d4, 0xbf001a87, 0x0000db0a, 0xaab80100, 0x7e0008a8, 0xbf001a87, 0xffffdb0a, 0xaab80e03, 0x7e0008e0, 0xbf001a87, 0x0000db0a, 0xaab8ce00, - 0x7e0008b4, 0xfb001a87, 0x1430d901, 0x99bf0000, 0x002e8fda, 0x07999800, 0x00f895f9, 0x001430d9, - 0xda99bf00, 0x00002e90, 0xf9099998, 0x0f00f895, 0x2938d9ff, 0x9fa00000, 0x9fb50f0f, 0xd900f801, - 0x00001430, 0x91da99bf, 0x9800002e, 0x95f90a99, 0x00f800f8, 0x001430d9, 0xda99bf00, 0x00002e92, - 0xf9049998, 0xf800f895, 0x1430d900, 0x99bf0000, 0x002e93da, 0x03999800, 0x00f895f9, 0x30d900f8, + 0x7e0008b4, 0xfb001a87, 0x1430d901, 0x99bf0000, 0x002e93da, 0x07999800, 0x00f895f9, 0x001430d9, + 0xda99bf00, 0x00002e94, 0xf9099998, 0x0f00f895, 0x2938d9ff, 0x9fa00000, 0x9fb50f0f, 0xd900f801, + 0x00001430, 0x95da99bf, 0x9800002e, 0x95f90a99, 0x00f800f8, 0x001430d9, 0xda99bf00, 0x00002e96, + 0xf9049998, 0xf800f895, 0x1430d900, 0x99bf0000, 0x002e97da, 0x03999800, 0x00f895f9, 0x30d900f8, 0xbf000014, 0x2978da99, 0x99980000, 0xdf95f90f, 0x00002970, 0x002944d9, 0x069fb500, 0x002968df, 0x059fb500, 0x9f35f4bd, 0xb59fa009, 0x9f35019f, 0xb5320f08, 0x00f8039f, 0x30d900f8, 0xbf000014, - 0x2e94da99, 0x99980000, 0xf895f906, 0xd900f800, 0x00001430, 0x98da99bf, 0x98000029, 0x95f90199, + 0x2e98da99, 0x99980000, 0xf895f906, 0xd900f800, 0x00001430, 0x98da99bf, 0x98000029, 0x95f90199, 0x30f500f8, 0xecdfff18, 0xf9000005, 0xfeffbf82, 0x99b80149, 0x0a000108, 0x7e9fa008, 0xb2001a27, 0x7e080aa0, 0xd9001a27, 0x40000000, 0xf50409fd, 0x95044d1b, 0x99b31fa9, 0x3d044601, 0x01dc4ba4, 0xa87e040c, 0xa4b20037, 0x4500a9b3, 0x76a0b503, 0xb571a0b5, 0xa0b572a0, 0x74a0b573, 0xd975a0b5, @@ -744,9 +744,9 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb8001a87, 0x00061c00, 0x277e0ab2, 0xabc5001a, 0x7e0ab204, 0x90001a87, 0x33950144, 0x01229d01, 0xf59523ff, 0x3eff641b, 0xfe0058dc, 0x90da0140, 0x90000029, 0xd4bd6000, 0x98de0bb2, 0x7e000000, 0x33004674, 0xff2a00ad, 0xfe0142fe, 0x03b20145, 0x2290143d, 0x24559098, 0x0056a03e, 0xb80149fe, - 0x00010899, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x83fb003a, 0xb4bd00e8, 0xda00c04c, - 0x0000299c, 0x000b947e, 0x001430d9, 0xda99bf00, 0x00002a58, 0xf90d9998, 0xf8a43d95, 0x05dcd900, - 0x9abf0000, 0x002e70db, 0x7e010c00, 0xf8005e25, 0x5c877e00, 0x3d00f800, 0x5e937ed4, 0xf400f800, + 0x00010899, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x83fb003a, 0xb4bd00e8, 0xda00c44c, + 0x0000299c, 0x000b947e, 0x001430d9, 0xda99bf00, 0x00002a5c, 0xf90d9998, 0xf8a43d95, 0x05dcd900, + 0x9abf0000, 0x002e74db, 0x7e010c00, 0xf8005e25, 0x5c877e00, 0x3d00f800, 0x5e937ed4, 0xf400f800, 0x12f9e430, 0xb0b2a1b2, 0x6100b0b3, 0xb004b998, 0x0cf40896, 0x0ba43d57, 0x384c7e44, 0x0aafb200, 0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503, 0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0, @@ -773,7 +773,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xa000373a, 0x00aab90a, 0x98030ab5, 0x0a900519, 0x0109b510, 0x35181918, 0x19984109, 0x0209b502, 0x09b519bf, 0x1819180e, 0x98400935, 0x09b50319, 0x0be77e0f, 0x240a9000, 0x000be77e, 0x180700b5, 0x0909181f, 0xf00c00b5, 0x9fbbfff4, 0x0909b502, 0xa48911fb, 0x93fe0016, 0x05ad8a00, 0x7eb43d00, - 0x0a005dd4, 0x8900f801, 0xa00010d8, 0x8900f89a, 0xbf0010d8, 0x8a00f89a, 0x3d002e80, 0x5e7f7eb4, + 0x0a005dd4, 0x8900f801, 0xa00010d8, 0x8900f89a, 0xbf0010d8, 0x8a00f89a, 0x3d002e84, 0x5e7f7eb4, 0x00a03300, 0xf809f808, 0x10e08a00, 0x7eb43d00, 0x33005e89, 0xf80600a0, 0xf000f809, 0x94bd00b3, 0xa5a5a5df, 0x5cd13ea5, 0x90afa000, 0xaa900199, 0xf49ba604, 0x00f8f608, 0x00335089, 0x0010fc8f, 0xf9b59ab2, 0x35508b01, 0x02b9bb00, 0x7502b5b6, 0xbb7e04fb, 0x00f8005c, 0x0059c27e, 0x0c00a433, @@ -785,7 +785,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xb2340090, 0x593f7e0a, 0x33a13200, 0x332400a4, 0xbf100060, 0x3d6b320a, 0x7ed43dc4, 0xfe0011cc, 0x99900149, 0xa099bf34, 0x5dcf3e59, 0x32020100, 0x1c65fb1a, 0xb0b212f9, 0xb2d430f4, 0x4d797ea1, 0x72943d00, 0x0101b0ae, 0x91301cb2, 0x00913028, 0x30089130, 0x91300c91, 0x14913010, 0x30189130, - 0x91301c91, 0x24913020, 0x002e848a, 0x0001ac8b, 0x0a7ed43d, 0xa033005d, 0x02f80600, 0xfb2c30f4, + 0x91301c91, 0x24913020, 0x002e888a, 0x0001ac8b, 0x0a7ed43d, 0xa033005d, 0x02f80600, 0xfb2c30f4, 0xf8a43d11, 0xb202f900, 0x20c630b0, 0xf8050df4, 0xffcac402, 0xb604a994, 0xa9bc02a4, 0x2094bda0, 0x0109b50c, 0x0038547e, 0xfb020ab5, 0xb222f901, 0xb2a2b2c1, 0x0bba32d0, 0x384c7e54, 0x0aacb200, 0x00c0b305, 0xb21ab21c, 0x7e2db20b, 0xb3005fcc, 0x3d0a01a4, 0x5e7d3ea4, 0x0a02f800, 0x0c21fbff, @@ -804,22 +804,22 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xfb0ab200, 0x89008f41, 0x00f9ce02, 0xf70195f0, 0x00f800f9, 0x0089010f, 0x9ff60280, 0xb800f800, 0x000180aa, 0xf609a4b6, 0x00f800ab, 0x03210089, 0xb8009af6, 0x02010099, 0xf8009af6, 0xf030f400, 0x0005ecdf, 0xbf82f900, 0x0149feff, 0x32309990, 0x7e9fa0a1, 0xc4006014, 0x43feff1a, 0x1ae87e01, - 0x0142fe00, 0xb2ff16c4, 0x0f94d4a5, 0x33900000, 0x2c229024, 0x001400d8, 0x2e68d700, 0x9c3e0000, + 0x0142fe00, 0xb2ff16c4, 0x0f94d4a5, 0x33900000, 0x2c229024, 0x001400d8, 0x2e6cd700, 0x9c3e0000, 0x093f0061, 0x1e009433, 0xb2987ebc, 0xe949bc6a, 0x001ae87e, 0xa5b21b32, 0x817e0ab2, 0x9c3e000f, 0x09180061, 0x20010f01, 0x35fc0f3f, 0x30b50131, 0xff94f001, 0xfd039990, 0x09bc049f, 0xe949bc90, 0xf0330f3f, 0xf6307307, 0x150cf407, 0x9104f933, 0x05f03300, 0x02fd3355, 0xfe3e00c7, 0xf0330060, 0xf630600a, 0x0c0cf40a, 0xb409fd33, 0x612c3e00, 0x0bf03300, 0x0cfd3356, 0x523e00a7, 0x0ab20061, 0x817e1b32, 0x093f000f, 0xb4bd2ab2, 0x943d2920, 0x18022935, 0x04090300, 0x35012935, 0x717e0320, - 0x9c3e000f, 0x8abf0061, 0x0061903e, 0x002e7cdf, 0x61573e00, 0x1404d900, 0x4c3e0000, 0x20df0061, + 0x9c3e000f, 0x8abf0061, 0x0061903e, 0x002e80df, 0x61573e00, 0x1404d900, 0x4c3e0000, 0x20df0061, 0x3e000014, 0xd9006157, 0x00001428, 0x903e9abf, 0x1cdf0061, 0xbf000014, 0x61903efa, 0x3d2f2000, 0x350ab294, 0x00180229, 0x351b3203, 0x2035012f, 0x0f817e03, 0xb2b4bd00, 0x0f717e2a, 0x0a747e00, 0x19e87e00, 0x0028f400, 0x000a9b7e, 0x00619c3e, 0x0c00a0b3, 0x080c3bb2, 0x0000a77e, 0xbcff1ec4, 0x05a6084e, 0xfede1bf5, 0x0060057e, 0x900149fe, 0x9fbf3099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf41085fb, 0xecdfb830, 0xf9000005, 0xfeffbf62, 0x99900149, 0xa03c0c60, 0x0140fe9f, - 0x0090b4bd, 0x7e0ab224, 0xd9000b94, 0x01000000, 0x002e68d1, 0xa09bb200, 0x0f94d919, 0xa4bd0000, + 0x0090b4bd, 0x7e0ab224, 0xd9000b94, 0x01000000, 0x002e6cd1, 0xa09bb200, 0x0f94d919, 0xa4bd0000, 0xf57e9ba0, 0x1bbf001a, 0x343da4bd, 0x7e008046, 0xbf00601f, 0x75020911, 0x09350406, 0x0101b501, 0x350a0335, 0xb4bd0b03, 0xda00804c, 0x01000000, 0x000b947e, 0xbd00804c, 0x0080dab4, 0x947e0100, - 0x057e000b, 0x80df0060, 0xd4010000, 0x00002e6c, 0x4fa0fab2, 0x00602c7e, 0xe0d24fbf, 0x75000010, + 0x057e000b, 0x80df0060, 0xd4010000, 0x00002e70, 0x4fa0fab2, 0x00602c7e, 0xe0d24fbf, 0x75000010, 0x03350806, 0x80f99012, 0xd90229b5, 0x00001b04, 0xb5030fb5, 0x1dd90329, 0xfe00001b, 0x29b50145, 0x1f559005, 0x53350109, 0x35592003, 0xfcd91309, 0xb5000010, 0x0975012f, 0x1b0ddf01, 0x04090000, 0x35042fb5, 0x32df0259, 0x0900000e, 0x062fb540, 0x20015935, 0x0a747e03, 0x7e2abf00, 0xb200009b, @@ -933,7 +933,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x006e607e, 0x0070463e, 0x0a1859bf, 0x030b1801, 0x18020c18, 0x0e98040d, 0x0091b002, 0xb0015998, 0x087e0191, 0xad33006d, 0x35ff6000, 0x2720022a, 0x32031e18, 0x351ab24b, 0x2e350126, 0x0f817e03, 0xbd2ab200, 0x0f717eb4, 0x6fa63e00, 0x05e4d900, 0x9abf0000, 0x001410db, 0x7e010c00, 0x7e005e25, - 0xf800709e, 0x1430d900, 0x9fbf0000, 0x8dda943d, 0x2000002e, 0x02f998a9, 0xa43d95f9, 0xa17e00f8, + 0xf800709e, 0x1430d900, 0x9fbf0000, 0x91da943d, 0x2000002e, 0x02f998a9, 0xa43d95f9, 0xa17e00f8, 0xaa7e003c, 0x00f8003b, 0xf9f830f4, 0xf4a1b222, 0xb2b2fc30, 0x900140fe, 0x0ca01000, 0x7e010db5, 0x09003da3, 0x00a033ff, 0x0109981e, 0x002944da, 0xb21cb200, 0x0091b02d, 0xab980ebf, 0x42ea7e07, 0x32a93200, 0x0430f49a, 0xdf0825fb, 0x000005ec, 0x30f4ffbf, 0x0149fef0, 0xa00c9990, 0x2944d99f, @@ -966,46 +966,46 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x277e0fa0, 0x2eb2001a, 0xbd011ab5, 0x00a1dbd4, 0x2e010000, 0x35f80d3c, 0xdd9002e1, 0x00a1dc01, 0xf9c40000, 0x64ffc70f, 0x3c98b93c, 0xe935f8bf, 0x90ef2001, 0xd4b303ee, 0xa9c4de04, 0x98c93c0f, 0xc70d2935, 0xc93c64a9, 0x0c293598, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, - 0x003a317e, 0xf91025fb, 0x29ccdb02, 0xcedc0000, 0xdd000029, 0x000029d0, 0x0029cada, 0x69c67e00, - 0x299cd000, 0x09980000, 0x29bcda01, 0x95f10000, 0x09b51e00, 0x73e27e01, 0x01099800, 0x0029d2da, + 0x003a317e, 0xf91025fb, 0x29d0db02, 0xd2dc0000, 0xdd000029, 0x000029d4, 0x0029ceda, 0x69c67e00, + 0x299cd000, 0x09980000, 0x29c0da01, 0x95f10000, 0x09b51e00, 0x73e27e01, 0x01099800, 0x0029d6da, 0x0095f100, 0x0109b501, 0x0073707e, 0xf1010998, 0xb5200095, 0x01fb0109, 0x00299cdd, 0x98dcbf00, 0xdf9801db, 0x0001d902, 0xc9fd3400, 0x0000d905, 0xde984c40, 0x05b9fd04, 0xf9fde309, 0xf0fe0904, - 0xf9fd04f5, 0x5000d904, 0xf9fd00c7, 0xf0050905, 0xd935c0e5, 0xa0ff0914, 0x04deb5dc, 0xb501dbb5, - 0xd9b502df, 0x74a77e15, 0xd900f800, 0x0000140c, 0xabc499bf, 0xc49ab801, 0x877e0007, 0x00f8001a, + 0xf9fd04f5, 0x5000d904, 0xf9fd00c7, 0xf0060905, 0xd935c0e5, 0xa0ff0918, 0x04deb5dc, 0xb501dbb5, + 0xd9b502df, 0x74a77e16, 0xd900f800, 0x0000140c, 0xabc499bf, 0xc49ab801, 0x877e0007, 0x00f8001a, 0xa0b212f9, 0x7d7eb1b2, 0x09bf006a, 0x1c0290b3, 0xf40296b0, 0x94b30b0c, 0x883e1001, 0x90b30075, 0x90b30a03, 0x94bd0604, 0x19bf09a0, 0x200390b3, 0xf40396b0, 0x90b30f0c, 0x94b31601, 0xac3e1002, 0x90b30075, 0x90b30a04, 0x94bd0605, 0x11fb19a0, 0xa1b222f9, 0xc2b2b0b2, 0x3200d433, 0x0e00a0b3, 0x0660e08a, 0x001a277e, 0x00b31aa0, 0xe48a0e00, 0x277e0660, 0x0aa0001a, 0x480020b3, 0x0660e88a, 0x001a277e, 0x203e2aa0, 0x020a0076, 0x3601d433, 0x0e00b0b3, 0xe48abbbf, 0x877e0660, 0x20b3001a, - 0x2bbf0e00, 0x0660e88a, 0x001a877e, 0x140010b3, 0x5c7e1ab2, 0x1bbf008c, 0x0660e08a, 0x001a877e, + 0x2bbf0e00, 0x0660e88a, 0x001a877e, 0x140010b3, 0x647e1ab2, 0x1bbf008c, 0x0660e08a, 0x001a877e, 0x21fba43d, 0x0005ecdf, 0xf4ffbf00, 0x49fef430, 0x08999001, 0x008f9fa0, 0xf9cf01c0, 0x4c99c700, 0x4c0099b3, 0x0190b301, 0x3e02f8f5, 0xcf00763a, 0x99c700f9, 0x0099b34c, 0x90b30125, 0x02f8f501, 0x00764f3e, 0xffffffd9, 0xc4f9ff7f, 0x01c0008f, 0xc700f9cf, 0x99b34c99, 0xb300db00, 0xf8f50190, 0x76703e02, 0x00f9cf00, 0xb34c99c7, 0xb30e0090, 0xf8f60190, 0x76853e02, 0xc0008f00, 0x00f9cf01, 0xb34c99c7, 0x008d0099, 0xf50190b3, 0x9d3e02f8, 0xf9cf0076, 0x4c9dc700, 0x5e00d0b3, 0xf601d0b3, - 0xb23e02f8, 0xf9100076, 0x48e93501, 0xe100fd33, 0x0658d900, 0x4ffe0000, 0x01f9b501, 0x002e7cd9, + 0xb23e02f8, 0xf9100076, 0x4ce93501, 0xe100fd33, 0x0658d900, 0x4ffe0000, 0x01f9b501, 0x002e80d9, 0xa09abf00, 0x204809fd, 0xde0909f9, 0x00000658, 0x0409e920, 0x3502ecb5, 0x4bfe01fd, 0x03ed3501, 0x3502ed35, 0x080c01e9, 0x00006e7e, 0x0077ad3e, 0xad3e09f8, 0x00890077, 0x99cf01c2, 0x299cde00, - 0xef180000, 0x26ff0948, 0x9d1bf4f9, 0x0077ad3e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, + 0xef180000, 0x26ff094c, 0x9d1bf4f9, 0x0077ad3e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x76b23e9f, 0x60e08f00, 0xc1008906, 0x009ff601, 0x010099b8, 0x009cf600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0x853e9fb2, 0x00890076, 0x9fcf01c2, 0x1ff99500, 0x8c0194b3, 0x0076643e, 0x0660e08f, 0x01c10089, 0xdf009ff6, 0x800000f1, 0x010099b8, 0x009ff702, 0xb2009fcf, 0x764f3e9f, 0x0149fe00, 0xbf089990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0c30f400, 0x30f400f8, 0x05ecdff4, 0x22f90000, 0x49feffbf, 0x14999001, 0x9fa0c1b2, 0x00299cd9, 0x019f9800, 0x00d9d2b2, 0x0e400000, 0x04f9fd08, 0x33750bf4, 0x0e1000a0, 0x01a43303, - 0x3ea0326c, 0x3d007809, 0x33040e04, 0x7e5e00b4, 0x33008a7a, 0x4b2400a0, 0x04330080, 0x884b0700, - 0x014afe00, 0xaa90080c, 0x8b2e7e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000654, 0x080e99bf, + 0x3ea0326c, 0x3d007809, 0x33040e04, 0x7e5e00b4, 0x33008a82, 0x4b2400a0, 0x04330080, 0x884b0700, + 0x014afe00, 0xaa90080c, 0x8b367e0c, 0x33060e00, 0x3e3a00a4, 0xd9007883, 0x00000654, 0x080e99bf, 0x290090b3, 0x90014ffe, 0x00330cff, 0x9e981000, 0x98fea020, 0x623e2199, 0x9e980078, 0x98fea022, 0xf9b52399, 0x78833e01, 0x0149fe00, 0xbf149990, 0x05ecd99f, 0x99bf0000, 0xf9a6ea32, 0x3e200bf4, 0xfe007898, 0x99900149, 0x0e9fbf0c, 0x981fa01f, 0x29a00199, 0x0078693e, 0x003a317e, 0x090c25fb, - 0x0aa9a024, 0xd900f81f, 0x0000299c, 0xf9e830f4, 0x2d9f9882, 0x98289298, 0x90982b91, 0x0df1b029, - 0x980bc1b0, 0xd1b02a9f, 0x09e1b00a, 0xbf2e9998, 0x64f2ffcc, 0xb07410ff, 0xc1b00e91, 0x0da0330c, + 0x0aa9a024, 0xd900f81f, 0x0000299c, 0xf9e830f4, 0x2e9f9882, 0x98299298, 0x90982c91, 0x0df1b02a, + 0x980bc1b0, 0xd1b02b9f, 0x09e1b00a, 0xbf2f9998, 0x64f2ffcc, 0xb07410ff, 0xc1b00e91, 0x0da0330c, 0x0ea4330c, 0x78f93e10, 0xb264b200, 0x78ff3e75, 0xbd44bd00, 0x78ff3e54, 0x0d40b400, 0x090e50b4, 0xf5b926ff, 0x9500851b, 0x4c9d015d, 0x5555d901, 0x33d05555, 0xff333333, 0xd9ffe4c9, 0xe24ebcf4, 0xfff35fbc, 0xf994c4e0, 0x02e5b61e, 0xffe59eff, 0x0fd2d4f0, 0x950f0f0f, 0xe0ff02f1, 0xb410ffa4, 0xbca0acbc, 0xb994b1bd, 0x04ae951c, 0xff04bf95, 0xeabce59e, 0xf1fbbce0, 0xdc04e2fd, 0x01010101, 0xb2b4f2ff, 0x7eeab2cd, 0xb60038c2, 0xb0b318b5, 0x09090b24, 0x3300bdb3, 0x00b6b001, 0xf00b3cf0, - 0x84bd0136, 0x00799e3e, 0x0cffbac4, 0x7e240b40, 0x09008458, 0x00a93304, 0x58b20112, 0x7d9543b2, + 0x84bd0136, 0x00799e3e, 0x0cffbac4, 0x7e240b40, 0x09008460, 0x00a93304, 0x58b20112, 0x7d9543b2, 0x016c9d01, 0x333333d1, 0x5555d233, 0xc2ff5555, 0xf4d2ffe4, 0xbce26ebc, 0xe1fff37f, 0x1ef994c4, 0xff02e5b6, 0xf1ffe59e, 0x0f0fd4d4, 0xf0950f0f, 0xa4e1ff02, 0xbcb401ff, 0xbdbca0ac, 0x1cb994b1, 0x9504ae95, 0x9eff04bf, 0xe0eabce5, 0xfdf1fbbc, 0x01dc04e4, 0xff010101, 0xcdb2b4f4, 0xc27eeab2, @@ -1019,25 +1019,25 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x20943d06, 0x142ab809, 0x277e0030, 0x0309001a, 0xb364aac7, 0x090c00a0, 0x04a0b301, 0x20943d06, 0xf421fb19, 0xecdff030, 0xf9000005, 0xf4ffbf32, 0x49fefc30, 0x20999001, 0x41fe9fa0, 0x9094bd01, 0x4efe1c11, 0x9019a001, 0xe9a018ee, 0xd3b2c2b2, 0xb926ff09, 0xfe201bf4, 0x240b0140, 0xb2140090, - 0x87d77e0c, 0xffa4f000, 0x3c1fa4b3, 0x10a000bf, 0x007b6e3e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, - 0x7e240d05, 0xf0008850, 0xa4b3ffa4, 0x49fe1a1f, 0x1c999001, 0x1f0a99bf, 0x49fe29a0, 0x18999001, + 0x87df7e0c, 0xffa4f000, 0x3c1fa4b3, 0x10a000bf, 0x007b6e3e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, + 0x7e240d05, 0xf0008858, 0xa4b3ffa4, 0x49fe1a1f, 0x1c999001, 0x1f0a99bf, 0x49fe29a0, 0x18999001, 0x39a099bf, 0x900149fe, 0x9fbf2099, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, 0x30f41035, 0x05ecdff0, 0x32f90000, 0x30f4ffbf, 0x0149fefc, 0xa0209990, 0x0141fe9f, 0x119094bd, 0x014efe18, 0xee9019a0, 0xb2e9a014, 0x09d3b2c2, 0xf4b926ff, 0x40fe1d1b, 0x90240b01, 0x0cb21c00, - 0x0087d77e, 0x391fa433, 0x10a000bf, 0x007c073e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, 0x7e240d08, - 0x33008850, 0xfe1a1fa4, 0x99900149, 0x0a99bf18, 0xfe29a01f, 0x99900149, 0xa099bf14, 0x0149fe39, + 0x0087df7e, 0x391fa433, 0x10a000bf, 0x007c073e, 0xf000e1b0, 0xb4f0ffa4, 0x0c1eb2ff, 0x7e240d08, + 0x33008858, 0xfe1a1fa4, 0x99900149, 0x0a99bf18, 0xfe29a01f, 0x99900149, 0xa099bf14, 0x0149fe39, 0xbf209990, 0x05ecd99f, 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0430f400, 0xf41035fb, 0xecdff430, 0xf9000005, 0xf4ffbf22, 0x49fefc30, 0x18999001, 0x4efe9fa0, 0x9094bd01, 0x40fe14ee, 0x90e9a001, - 0x09a01000, 0xd2b2c1b2, 0xb926ff09, 0xb20f1bf4, 0x7e240bec, 0x3e0087d7, 0xb0007c8c, 0xa4f00001, - 0xffb4f0ff, 0x240d010c, 0x0088507e, 0x201fa433, 0x900149fe, 0x99bf1499, 0x90014ffe, 0xffbf10ff, + 0x09a01000, 0xd2b2c1b2, 0xb926ff09, 0xb20f1bf4, 0x7e240bec, 0x3e0087df, 0xb0007c8c, 0xa4f00001, + 0xffb4f0ff, 0x240d010c, 0x0088587e, 0x201fa433, 0x900149fe, 0x99bf1499, 0x90014ffe, 0xffbf10ff, 0x038199e7, 0xffe719a0, 0x2fa00381, 0x900149fe, 0x9fbf1899, 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xfb0430f4, 0x30f40c25, 0x05ecdff4, 0x22f90000, 0x30f4ffbf, 0x0149fefc, 0xa0189990, 0x014efe9f, 0xee9094bd, 0x0140fe14, 0x0090e9a0, 0xb209a010, 0x09d2b2c1, 0xf4b926ff, 0xecb20f1b, - 0xd77e240b, 0x1b3e0087, 0x01b0007d, 0xffa4f000, 0x0cffb4f0, 0x7e240d20, 0x33008850, 0xfe181fa4, + 0xdf7e240b, 0x1b3e0087, 0x01b0007d, 0xffa4f000, 0x0cffb4f0, 0x7e240d20, 0x33008858, 0xfe181fa4, 0x99900149, 0xa099bf14, 0x0149fe19, 0xbf109990, 0xfe29a099, 0x99900149, 0xd99fbf18, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xf4003a31, 0x25fb0430, 0xf430f40c, 0x0005ecdf, 0xbf52f900, 0x0149feff, 0x32209990, 0xb29fa0b0, 0xb00405c4, 0x0cf523a6, 0x34bd00bb, 0xfe0142fe, 0x22900141, 0x1c119018, - 0x13a023a0, 0x2cb21bb2, 0x0084407e, 0xad33a532, 0xbf009b1f, 0x7e2bbf1a, 0x330084fc, 0xa00a00a4, + 0x13a023a0, 0x2cb21bb2, 0x0084487e, 0xad33a532, 0xbf009b1f, 0x7e2bbf1a, 0x33008504, 0xa00a00a4, 0x7e293e43, 0xbf2fbf00, 0x0ff4b619, 0xbc1494b6, 0x00df90f9, 0xbc010100, 0x0033909f, 0x06302e04, 0x0b0cf404, 0x65030433, 0x007dd83e, 0x2d050033, 0x59060433, 0x007e093e, 0x22889ab8, 0x1a277e00, 0x10a5b600, 0x007df33e, 0x7e8c9a90, 0xf1001a27, 0xa003ffa4, 0x7e293e4a, 0x889ab800, 0x277e0032, @@ -1050,479 +1050,479 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x0005ecd9, 0xa699bf00, 0x070bf4f9, 0x003a317e, 0xf40c45fb, 0xecdfb830, 0xf9000005, 0xfeffbf82, 0x99900149, 0xa0010568, 0x11c1b09f, 0xb049b130, 0xe1b010d1, 0x33c4bf0f, 0x30180aa0, 0x08f40aa6, 0x3302050f, 0x050c0ba0, 0x0ca03303, 0xbd543d06, 0x014ffe94, 0xff9064bd, 0xb504bd60, 0xf9a001f9, - 0xff9274bd, 0xb2f92008, 0xb20ab2f1, 0x860e7e1b, 0x1fad3300, 0x193f0480, 0x1c009033, 0xb4bd010a, - 0xcd7e0cb2, 0x7bff0039, 0xa56aff95, 0xaeb29fb2, 0xf7b2e6b2, 0xb3010090, 0x3ed22404, 0x340083c9, - 0x040a4990, 0xf5239630, 0x34044a0c, 0x010a49c0, 0xc4f0b4bd, 0x39cd7eff, 0xb2a0b200, 0x0849c5b1, - 0x000008df, 0xf49fffff, 0x7e13f1b0, 0x33008a7a, 0xfe4d00a4, 0x24bd0146, 0x34bd1f0a, 0x6690443d, - 0x7fcd3e60, 0x0109c400, 0x321c0bf4, 0xb25b324a, 0x89ca7e6c, 0x1fa43300, 0x986ebf0f, 0x2ebc016f, - 0x313fbc20, 0x95014410, 0x009d0111, 0x9501ff01, 0x33d51bf4, 0x03c71fa9, 0x0083b13e, 0x0949b034, - 0xf4b926ff, 0x9cdf780b, 0xc4000029, 0xe994ff5e, 0x909fbc03, 0x98189f98, 0xf1fd1799, 0x0490fd04, - 0x1bf490a6, 0xf4f1a608, 0x02ff540b, 0xf413ff94, 0x1bf490a6, 0xf4f1a608, 0x9cd9440b, 0x94000029, - 0xf9bc03ef, 0x1ff998f0, 0x90000cb9, 0x1bb97cfe, 0x049cfd00, 0x981ff9b5, 0xfd9001e9, 0xfd090a5c, - 0xe9b5049b, 0x17f99801, 0xb5049cfd, 0xd99817f9, 0x049bfd01, 0x3e01d9b5, 0xf00083b1, 0x9cdbff54, - 0xb2000029, 0x0394b659, 0x98909bbc, 0x9998209f, 0x1451b01f, 0xfd04f1fd, 0x90a60490, 0xa6081bf4, - 0x100bf4f1, 0x44bd010e, 0xbd4ae130, 0x80db3e54, 0xb244bd00, 0xbd0cb21d, 0x3eb43d54, 0xc40080d0, - 0x0bf401c9, 0x14f0b425, 0x0006b4de, 0xffb9c400, 0xbc0394b6, 0x94b6909f, 0x909ebc03, 0x9f989ebf, - 0x404ebc01, 0x10515fbc, 0xdd9501bb, 0x01cc9d01, 0xf495cdff, 0xf43dcc1b, 0xb44af130, 0x9cdb1490, - 0xb6000029, 0x9bbc0394, 0x189f9890, 0xfd179998, 0x90fd04f1, 0xf490a604, 0xf1a6091b, 0x01200bf5, - 0xe43d94bd, 0xb01791b0, 0xe1301691, 0x81dc3e4b, 0x0169c400, 0x00b90bf5, 0x344b9034, 0x94df4bc0, - 0x0a000006, 0xff94f001, 0x9894b4bd, 0xffc4f006, 0x7e808fbc, 0xd20039cd, 0x000029f8, 0xb000b9b9, - 0xa1b00db1, 0x00abb90e, 0xb00b91b0, 0x8db20cb1, 0xa034343d, 0x09d1b04b, 0x4cfe3b32, 0x58cc9001, - 0x0089ca7e, 0x2c9829bf, 0x09d0b401, 0x351fa033, 0xdea0e4bd, 0xb401deb5, 0x2f980cb0, 0x092e9808, - 0xa0049bfd, 0x0bb0b429, 0xb594cbff, 0x90b40129, 0x04ebfd0c, 0xfd092eb5, 0x2fb504f9, 0x81bd3e08, - 0x16e0b400, 0xb517f0b4, 0x8ea0018f, 0xfd0ef0b4, 0x29a0059f, 0xff0db0b4, 0x29b595cb, 0x01331001, - 0x9008dd90, 0x88900822, 0x04343308, 0x4be03489, 0x9d017795, 0xee100166, 0x4be13001, 0xf59567ff, - 0x34ff321b, 0xff0949f0, 0x0bf4f926, 0x1490b429, 0x00299cdb, 0x0394b600, 0x98909bbc, 0x9998189f, - 0x04f1fd17, 0xa60490fd, 0xd71bf590, 0xf5f1a601, 0xb401d11b, 0xe5f013e0, 0x13e1b004, 0x900149fe, - 0x96bf6099, 0xb4019798, 0x9cdf1490, 0x3d000029, 0xb624bde4, 0x34bd0394, 0x30909fbc, 0x9b9057e1, - 0x5c98907c, 0x3e0ab1b0, 0xc40082cf, 0x0bf40109, 0x14f0b472, 0xde579034, 0x00000694, 0x0006b4db, - 0xf0010a00, 0x94b6ff94, 0x909fbc03, 0xb6039f94, 0xfbbc0394, 0x909ebcf0, 0x979896bf, 0x01f7b501, - 0xc034f6a0, 0xbcb4bd57, 0x37bc2026, 0xffc4f031, 0x0039cd7e, 0xbf018f98, 0x00b9b98e, 0xb904f9fd, - 0x8fb500a9, 0x04e9fd01, 0xf0b48ea0, 0x98f9bf0a, 0x9afd01ff, 0x05fbfd05, 0xa00ab0b4, 0x01bfb5b9, - 0x9557e034, 0x009d0111, 0x01ee1001, 0xff57e130, 0x1bf59501, 0x49feff79, 0x60999001, 0xa00197b5, - 0x4af03496, 0xb600fd33, 0xc224bc00, 0xb3d335bc, 0x891300d4, 0xa60ffffe, 0x090cf4c9, 0x5e3ef43d, - 0xdf940083, 0x0ada9516, 0xff0ac995, 0xafb2b5f9, 0xecb2beb2, 0xd4b3fdb2, 0x010f0f00, 0x0ffffe89, - 0x0df4c9a6, 0x0abf953c, 0x9516a994, 0x9fff0aab, 0xb2bfb2a5, 0xb2ecb2ae, 0x00d4b3fd, 0x89020f0f, - 0xa60ffffe, 0x190df4c9, 0x950aaf95, 0xb9940abd, 0x059ffd16, 0x9eb2dfb2, 0xfdb2ecb2, 0xb0b4030f, - 0x03f4f013, 0xb9fffc09, 0xe5f9ff94, 0x0d00d4b3, 0x0fffff89, 0x0df4c9a6, 0x08e9c50a, 0x0083a03e, - 0xb694c9ff, 0x0fdf0494, 0xffff0000, 0xf9fdf4ef, 0xfff70905, 0xa03e94f9, 0x90b40083, 0x0895f013, - 0x0a10e0b4, 0xb4e2a01f, 0xf3a00ff0, 0xa011b0b4, 0x0149feb9, 0xbf689990, 0x05ecd99f, 0x99bf0000, - 0x0bf4f9a6, 0x83e63e28, 0x49e03400, 0x73b262b2, 0xe926ff09, 0xfb8b1bf5, 0x71b260b2, 0x007f7d3e, - 0xb13e090a, 0x317e0083, 0x85fb003a, 0xc0008f48, 0x00f9cf01, 0xb34c99c7, 0xb3220090, 0xf8f60190, - 0x83f13e02, 0x00f9cf00, 0xb34c99c7, 0xb3330090, 0xf8f60190, 0x84053e02, 0xc1008900, 0x009af601, - 0x010099b8, 0x009bf600, 0x0000f2df, 0x0099b880, 0x9ff60202, 0x009fcf00, 0x053e9fb2, 0x00f80084, - 0xaf95a9b2, 0xb0060a02, 0x0cf408f6, 0xf0bfa00c, 0x1f0a0394, 0x00f8c9a0, 0xbc01bb92, 0xbcffb0bc, - 0xffb4f0bc, 0xacf0aba6, 0xf900f808, 0xb2c0b202, 0x02a0b3dc, 0x02a6b039, 0xb30b0cf4, 0x3e1001a4, - 0xb3008491, 0xb32d07a0, 0x0a3b08a0, 0x84fa3e06, 0xb31f0a00, 0xbf670104, 0x1fb9c4df, 0x09bc1f0a, - 0x05f9fd94, 0xfa3edfa0, 0xd0a00084, 0x0084f83e, 0xbf07b9c4, 0x0294b6dd, 0x901f9ec4, 0xd63e0399, - 0xddbf0084, 0xbc05bfcd, 0x9fbc90ff, 0x9099bc90, 0x901f9ec4, 0x99b90599, 0x1f94f000, 0x0f909ebc, - 0x05f9bbff, 0xbb94f0ff, 0x9ebb04fe, 0x00ffb904, 0xfd04fdfd, 0xcfa005f9, 0x01fb1f0a, 0xb1b212f9, - 0xeb7ea0b2, 0xa033003c, 0xa43d0a00, 0x00853e3e, 0xdf0f1994, 0x01017000, 0xbc1404b6, 0x09bc000f, - 0x000ab800, 0x277e0006, 0xa1b2001a, 0x03800ab8, 0x1a277e00, 0x05a1fd00, 0xf001a6f0, 0x11fb01a4, - 0xdff430f4, 0x000005ec, 0xffbf32f9, 0x900149fe, 0xb2b21899, 0x06039fa0, 0xf523a6b0, 0xfe00960c, - 0x40fe0141, 0x14119001, 0xb2100090, 0x7e0cb21b, 0x32008440, 0x1fa433a3, 0xbf1abf7c, 0x84fc7e0b, - 0x00a03300, 0xbf19bf5a, 0x1494b60a, 0xbc0fa4b6, 0x00d9a0a9, 0xbc010100, 0x277ea0a9, 0xa4f0001a, - 0x04a0b3ff, 0x04a6b04c, 0xb0130cf4, 0x0cf402a6, 0x01a6b039, 0x3e2d18f4, 0xb30085db, 0xb02c08a0, - 0x0cf408a6, 0x05a4b30b, 0x85db3e10, 0x0aa0b300, 0x0ba0b31a, 0x3e060310, 0xbd0085f1, 0x85ef3e94, - 0x3e010900, 0x090085ef, 0x85ef3e02, 0xa0030900, 0x0149fe29, 0xbf189990, 0x05ecd99f, 0x99bf0000, - 0xf9a63a32, 0x7e070bf4, 0xfb003a31, 0x30f40c35, 0x05ecd9f8, 0x12f90000, 0x4ffe99bf, 0x0cff9001, - 0xf9a0b1b2, 0x40feff09, 0x08009001, 0x0bb209a0, 0x0085407e, 0x0e1fa433, 0x96b009bf, 0x0b9cf002, - 0x49fe1920, 0x0c999001, 0xecd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x15fb003a, 0xe830f408, - 0x0005ecdf, 0xbf42f900, 0x0149feff, 0xb2289990, 0xb29fa0b0, 0x02a033c3, 0x02a63045, 0x330c0cf4, - 0x00a601ad, 0x0086963e, 0xb407a933, 0x08ad3300, 0x4a3e0098, 0xbab20087, 0x900140fe, 0x0bb22700, - 0x00860e7e, 0xad33a232, 0x3f01141f, 0x00963009, 0xf00b9cf0, 0xb83e0196, 0x04020087, 0xf523b630, - 0xc400fb0c, 0x44feffba, 0x0141fe01, 0x90204490, 0x4bb21c11, 0x407e1cb2, 0xa2320084, 0xde1fad33, - 0xff0ac400, 0x900140fe, 0x0bb22700, 0x00860e7e, 0xad33a232, 0x3f00c81f, 0x00943309, 0x3e94bd0a, - 0xbf0087b8, 0xb61abf49, 0xa4b61494, 0xa0a9bc0f, 0x01760cd9, 0xa0a9bc01, 0x001a277e, 0x3008a5b6, - 0x0df407a6, 0x3e060209, 0xc40087ba, 0x48d9ffaf, 0xbc000000, 0x3fa0f89f, 0x0087ba3e, 0xcbb2bab2, - 0x0085407e, 0xba3ea232, 0x04020087, 0xf423b630, 0xbac46b0c, 0x0141feff, 0x900144fe, 0x44901811, - 0xb21bb214, 0x84407e4c, 0x33a23200, 0xc44f1fa4, 0x40feff0a, 0x20009001, 0x0e7e0bb2, 0xa2320086, - 0x3a1fa433, 0x9433093f, 0x3f090a00, 0x0087b83e, 0x4b3f1a3f, 0xfe0141fe, 0x11900140, 0x1c009027, - 0x0db21cb2, 0x007aac7e, 0x1f3f093f, 0xf00794f0, 0x94b607f4, 0x059ffd03, 0x49fe39a0, 0x28999001, - 0xecd99fbf, 0xbf000005, 0xa62a3299, 0x070bf4f9, 0x003a317e, 0xf41845fb, 0xecdff830, 0xf9000005, - 0xfeffbf62, 0xff010149, 0xfe209990, 0xa5320142, 0xc4b2b3b2, 0x04bd9fa0, 0xb21c2290, 0x882a3e16, - 0xb25a3200, 0x7e2cb20b, 0x3300865d, 0xbf2a1fa4, 0xf416a629, 0x91b2091b, 0x0088273e, 0x0bf419a6, - 0x3e090a09, 0x90008835, 0x03a60100, 0xbfd508f4, 0xa01f0a22, 0x0149fe42, 0xbf209990, 0x05ecd99f, - 0x99bf0000, 0x0bf4f9a6, 0x3a317e07, 0x0865fb00, 0xdff830f4, 0x000005ec, 0xffbf82f9, 0x900149fe, - 0xc2b22899, 0xd5b2b0b2, 0x9fa0cbb2, 0xa4b2e7b2, 0x7ea000bc, 0xb20016fc, 0xbca3b25b, 0x0ab2c022, - 0x7e6032bc, 0x01008458, 0x0c80b404, 0x7500a033, 0x43fe30b2, 0x24339001, 0x0088bb3e, 0x0bb24a32, - 0x5d7e3cb2, 0xa1320086, 0x591fa433, 0x0bb23cbf, 0x00904ab2, 0x7e7db201, 0xa600846b, 0x4218f405, - 0x08f406a6, 0x88f13eda, 0xb24a3200, 0x7e3cb20b, 0x3200865d, 0x1fa433a1, 0xb23cbf2c, 0x904ab20b, - 0x8db20100, 0x00846b7e, 0x08f405a6, 0x89013e10, 0x0143fe00, 0x902062bc, 0x02a62433, 0x01cd08f4, - 0x0149fe1f, 0xbf289990, 0x05ecd99f, 0x99bf0000, 0xf9a61a32, 0x7e070bf4, 0xfb003a31, 0x30f40885, - 0x05ecdff4, 0x62f90000, 0x94bdffbf, 0xfe0141fe, 0x11900140, 0x1c009020, 0x09a019a0, 0x900149fe, - 0xb2b22499, 0xd5b2c6b2, 0x1bb29fa0, 0x407e0cb2, 0xa3320084, 0x591fa433, 0x0bbf1abf, 0x0084fc7e, - 0x0a00a433, 0xad3e0903, 0x19bf0089, 0x94b600bf, 0x0f04b614, 0x7e0009bc, 0xd900010e, 0x01015000, - 0xbc0009bc, 0x60bc4002, 0x7e1ab210, 0xb2001a27, 0x7e4ab2a0, 0xb2001a27, 0x7e1ab2a2, 0xa6001a27, - 0xe81bf40a, 0x0001087e, 0xa00150b5, 0x0149fe52, 0xbf249990, 0x05ecd99f, 0x99bf0000, 0xf9a63a32, - 0x7e070bf4, 0xfb003a31, 0x30f40c65, 0x05ecdff4, 0x02f90000, 0x49feffbf, 0x0c999001, 0x9fa0c0b2, - 0x040aaf32, 0xf423f630, 0x94bd780c, 0x90014dfe, 0xd9b504dd, 0x33d9a001, 0x302501b0, 0x08f401b6, - 0x02b03311, 0x331f0a28, 0x3e3c03b4, 0xc4008a36, 0x4c4bfffa, 0x15504c15, 0x008a3f3e, 0x4bfffac4, - 0x504c1d4c, 0x8a3f3e1d, 0xfffac400, 0x4c15f44b, 0x3f3e15f8, 0xfac4008a, 0x1df44bff, 0x7e1df84c, - 0xfe00891e, 0x99900149, 0x989ebf04, 0xe5b60199, 0x069f9506, 0xb51a94b6, 0xe9fd010f, 0xfe0ea005, - 0x99900149, 0xd99fbf0c, 0x000005ec, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x9cd90c05, 0x18000029, - 0x00f8159a, 0xa033080f, 0x1f0f1901, 0xf401a630, 0xa9121008, 0x30060f30, 0x0cf40496, 0x32070f05, - 0xf400f8fa, 0x22f9f830, 0x0005ecd2, 0xfe29bf00, 0x11900141, 0x0140fe10, 0x0e7e19a0, 0x00900001, - 0x7e0ab20c, 0xdf00732c, 0x0000299c, 0xf9980ebf, 0x15feb515, 0x9cf09ea6, 0x58f9350b, 0x0001087e, - 0x29bf1fbf, 0x0bf4f9a6, 0x3a317e07, 0x0825fb00, 0x00299cd9, 0x15991800, 0xbeb2adb2, 0x9033cfb2, - 0xb4d91a00, 0x98000029, 0x9bbf019c, 0x367efab2, 0x847e0021, 0x00f8008a, 0x000654d9, 0xb29abf00, - 0xbcecb2cb, 0x7e7ea0ad, 0x1f0a000b, 0xbdb200f8, 0xa0b3ceb2, 0xb6b13800, 0x0cf423bf, 0x23c04930, - 0xa6029bbb, 0x250cf4c9, 0x00299cd9, 0x15991800, 0x9033010f, 0xb4d91a00, 0x98000029, 0x9bbf019c, - 0x0020d07e, 0x6c3eaf32, 0x020f008b, 0x00f8fa32, 0xdfd830f4, 0x000005ec, 0xffbf72f9, 0x900149fe, - 0x46fe4499, 0xb29fa001, 0xb2b1b2a0, 0x246690c4, 0x23c0a6b1, 0xb17d0cf4, 0xf423c0b6, 0xbabc760c, - 0xc096b190, 0x6c0cf423, 0x000e067e, 0xd50302c4, 0x000029b4, 0x07ff29c4, 0x3209bc20, 0x008c033e, - 0x5c985bbf, 0xb26ab201, 0x7e200e3d, 0x330020d0, 0x000a00a0, 0x8c093e06, 0xff29c400, 0xa60279bc, - 0x050df401, 0x2bc410b2, 0xff0cc4ff, 0x04f04ab2, 0xb06bbcff, 0xbb203390, 0x7e7e0210, 0x40bc000b, - 0xb3243d40, 0x00bd0014, 0x0ddd7e1f, 0x8c133e00, 0xfe060000, 0x99900149, 0xd99fbf44, 0x000005ec, - 0x0a3299bf, 0x0bf4f9a6, 0x3a317e07, 0x2875fb00, 0x00299cd9, 0x15991800, 0xbeb2adb2, 0x0a009033, - 0x008b707e, 0x54d900f8, 0xbf000006, 0xb2cab29b, 0xb0bdbcec, 0x000b7e7e, 0x00f81f0a, 0xdff430f4, - 0x000005ec, 0xffbf32f9, 0x900149fe, 0xa2b21899, 0xa9bf9fa0, 0xb39899c7, 0x00aa1d99, 0x00299cd9, - 0x02999800, 0xb34299c7, 0x009a0099, 0x0a0140fe, 0x14009001, 0xef7e0bb2, 0xa4330094, 0x4bfe551f, - 0x90020a01, 0xef7e10bb, 0xa4330094, 0x09bf451f, 0x04bd0103, 0xbc1493ff, 0x94f09530, 0x121bf401, - 0x0f0204b3, 0x009a457e, 0x0700a033, 0x900415f0, 0x04b30100, 0x49fee50a, 0x14999001, 0x19a699bf, - 0x0a150bf4, 0x7e1bb201, 0x3300950a, 0xf80a1fa0, 0x8d233e09, 0xfe2ebf00, 0x99900149, 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0x010a49c0, 0xc4f0b4bd, 0x39cd7eff, 0xb2a0b200, 0x0849c5b1, + 0x000008df, 0xf49fffff, 0x7e13f1b0, 0x33008a82, 0xfe4d00a4, 0x24bd0146, 0x34bd1f0a, 0x6690443d, + 0x7fcd3e60, 0x0109c400, 0x321c0bf4, 0xb25b324a, 0x89d27e6c, 0x1fa43300, 0x986ebf0f, 0x2ebc016f, + 0x313fbc20, 0x95014410, 0x009d0111, 0x9501ff01, 0x33d51bf4, 0x03cf1fa9, 0x0083b93e, 0x0949b034, + 0xf4b926ff, 0x5ec4780b, 0x29fcdcff, 0xe9940000, 0x909cbc03, 0xbf019f98, 0x04f1fd99, 0xa60490fd, + 0x081bf490, 0x0bf4f1a6, 0x9402ff55, 0xa6f413ff, 0x081bf490, 0x0bf4f1a6, 0x2a1cd945, 0xef940000, + 0xf0f9bc03, 0xbf01f998, 0x001bb9fd, 0x0029fcdc, 0x049bfd00, 0xb503e4b6, 0xecbc01f9, 0x000cb9e0, + 0xa004dcfd, 0x98efbffd, 0x090a01e9, 0xfd04fcfd, 0xefa0049b, 0x3e01e9b5, 0xf00083b9, 0x1cdeff54, + 0xb200002a, 0x0394b659, 0x98909ebc, 0x99bf019f, 0xfd1451b0, 0x90fd04f1, 0xf490a604, 0xf1a6081b, + 0x0f100bf4, 0x3044bd01, 0x54bd4af1, 0x0080d83e, 0x1db244bd, 0x54bd0cb2, 0xcf3eb43d, 0xc9c40080, + 0x250bf401, 0xdf14e0b4, 0x000006b4, 0xb6ffb9c4, 0x9ebc0394, 0x0394b690, 0xbf909fbc, 0x019f989e, + 0xbc404ebc, 0xbb10515f, 0x01dd9501, 0xff01cc9d, 0x1bf495cd, 0x4a9130cc, 0xdb1490b4, 0x000029fc, + 0xbc0394b6, 0x9f98909b, 0xfd99bf01, 0x90fd04f1, 0xf490a604, 0xf1a6091b, 0x011f0bf5, 0xc43d94bd, + 0xb01791b0, 0xc1301691, 0x81d83e4b, 0x0169c400, 0x00b90bf5, 0x344b9034, 0x94de4bc0, 0x0a000006, + 0xff94f001, 0x9894b4bd, 0xffc4f006, 0x7e808ebc, 0xd20039cd, 0x000029fc, 0xb900bfb9, 0xb1b000a9, + 0x0ea1b00d, 0xb00bf1b0, 0x8db20c91, 0xa034343d, 0x09d1b04b, 0x4cfe3b32, 0x58cc9001, 0x0089d27e, + 0x2c9829bf, 0x09d0b401, 0x351fa033, 0xdba0b4bd, 0xb401dbb5, 0x2f980cb0, 0x092e9808, 0xa0049bfd, + 0x0bb0b429, 0xb594cbff, 0xc0b40129, 0x04ebfd0c, 0xfd092eb5, 0x2fb504fc, 0x81b93e08, 0x16e0b400, + 0xb517f0b4, 0x8ea0018f, 0xfd0ef0b4, 0x29a0059f, 0xff0db0b4, 0x29b595cb, 0x01331001, 0x9008dd90, + 0x88900822, 0x04343308, 0x4bc03489, 0x9d017795, 0xcc100166, 0x4bc13001, 0xf59567ff, 0x34ff321b, + 0xff0949e0, 0x0bf4e926, 0x1490b428, 0x0029fcdf, 0x0394b600, 0x98909fbc, 0x99bf019f, 0xfd04f1fd, + 0x90a60490, 0x01e41bf5, 0x1bf5f1a6, 0x90b401de, 0x0495f013, 0xb41391b0, 0x80b414b0, 0x0149fe14, + 0x0029fcdc, 0x60999000, 0xbf03b4b6, 0x01979896, 0xb6b0bcbc, 0x1cde0384, 0x3d00002a, 0xb024bdf4, + 0x34bd0ab1, 0x30808ebc, 0xd73e57f1, 0x09c40082, 0x770bf401, 0x3414b0b4, 0xb4dc5790, 0xde000006, + 0x00000694, 0x94f0010a, 0x0394b6ff, 0x94909bbc, 0x94b6039f, 0xf0fcbc03, 0xbf909ebc, 0x01979896, + 0xa001f7b5, 0x57c034f6, 0x26bcb4bd, 0x3137bc20, 0x7effc4f0, 0xb40039cd, 0xb9b90af0, 0xbfbdb200, + 0x01ff98fe, 0xb404f9fd, 0x9fb50a90, 0x0ab0b401, 0xfd00a9b9, 0xbea004e9, 0x8f9889bf, 0x059afd01, + 0xa005fdfd, 0x018fb589, 0x9557c034, 0x009d0111, 0x01cc1001, 0xff57c130, 0x1bf59501, 0x49feff74, + 0x60999001, 0xa00197b5, 0x4ae03496, 0xb600ed33, 0xc224bc00, 0xb3d335bc, 0x891300d4, 0xa60ffffe, + 0x090cf4c9, 0x663ef43d, 0xdf940083, 0x0ada9516, 0xff0ac995, 0xafb2b5f9, 0xecb2beb2, 0xd4b3fdb2, + 0x010f0f00, 0x0ffffe89, 0x0df4c9a6, 0x0abf953c, 0x9516a994, 0x9fff0aab, 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0x3501090f, 0x09bf1cf9, 0xbf2c9a35, 0xb5f0090f, 0x0fbf0af9, 0xb540f990, + 0x0fbf0ef9, 0xb5c0f990, 0x0abf0ff9, 0x00b0f23e, 0x49fea4bd, 0x14999001, 0xecd99fbf, 0xbf000005, + 0xf4f9a699, 0x317e070b, 0x35fb003a, 0xd030f408, 0x0005ecdf, 0xbf82f900, 0x0149feff, 0xb2509990, + 0x059fa0a3, 0x00a9b302, 0xb63004fb, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5f27e, 0x3abfa0b2, + 0x804cb4bd, 0x7e0db200, 0xb200b781, 0x00adb3a5, 0x093f04b1, 0xa24a9d33, 0x01091804, 0x9a469d33, + 0x02091804, 0x92469d33, 0x03091804, 0x8a539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, + 0xf0ff94f0, 0x94b6fff4, 0x10f4b608, 0xb6059efd, 0xf9fd18d4, 0x05dffd05, 0x045e0bf5, 0xd6b00505, + 0x5d0cf503, 0x013db504, 0x0e01d4b3, 0xb5500049, 0xe03e0239, 0x0d1800b1, 0x09091808, 0x180a0f18, + 0xd4f00b0e, 0xff94f0ff, 0xb6fff4f0, 0xf4b60894, 0x059dfd10, 0xfd18e4b6, 0xeffd05f9, 0x023eb505, + 0x0bb23ab2, 0x00a6147e, 0x09023a98, 0xf4a9a6ff, 0x04bd091b, 0x00b5f63e, 0x9007a5b6, 0x3ab5303b, + 0xb6da7e03, 0xb3a5b200, 0x03f500ad, 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb7a77e03, + 0xb3a5b200, 0x03d900ad, 0xfe0147fe, 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3503e, + 0x8ea0e4bd, 0x0f0044b3, 0xbd0c3a98, 0x3efe0cb4, 0xb200b273, 0xb24bb23a, 0xa5817e7c, 0xb3a5b200, + 0x039d00ad, 0x94f0793f, 0x120bf401, 0xb20c3a98, 0x7eff0c4b, 0x3e00b67e, 0xb200b34d, 0xa3387e7a, + 0x00a0b300, 0x0c3a980f, 0xfd0c4bb2, 0x00b2733e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, + 0xb400b342, 0x3ab209b0, 0x8db2010c, 0x00a6487e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, + 0x980a91b0, 0x54b354f5, 0xb0b43900, 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, + 0xa17e1ab2, 0x30bc00b7, 0x4309b800, 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b30d, + 0xff900122, 0x1424b318, 0xb63a3ebe, 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, + 0xcc00f3f0, 0x96cb70ff, 0xcb4bb21f, 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2ee, 0x4bb20c3a, + 0x7e7e6cb2, 0xa5b200b6, 0xb400adb3, 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, + 0xbd7e8ab2, 0xa5b200b7, 0x9400adb3, 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, + 0x39bc0001, 0x0b91b090, 0x5300f9b3, 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b7987e, + 0x3e0f60b4, 0x9800b46b, 0x2bb20d3a, 0x7e0c41b0, 0x3300a2fe, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, + 0x7e38cc90, 0xb300b667, 0x020c00ad, 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, + 0x0c2bb20d, 0xa2f67e01, 0x014cfe00, 0x2bb23ab2, 0x7e30cc90, 0xb300a59c, 0x981306a4, 0x2bb20c3a, + 0x7e7efd0c, 0x683e00b6, 0xadb300b4, 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, + 0x091bf4ff, 0x683e0260, 0x3a9800b4, 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b667, 0x019800ad, + 0x343af034, 0xf9263690, 0x60100df4, 0xff1be402, 0x0c3a98ff, 0x00b45d3e, 0xb20c3a98, 0x7efd0c2b, + 0xb300b67e, 0x017000ad, 0x98012290, 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, + 0x00b49f3e, 0x9473e97f, 0x010d0a00, 0x00b4993e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, + 0xe308f4fa, 0x0b00c4b3, 0x3e547cb5, 0x3300b5db, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, + 0x5479b56d, 0xf4bde4bd, 0x00b4de3e, 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, + 0xf4f9a603, 0x553ee908, 0x94bd00b5, 0x79b5f101, 0xb224bd54, 0xb52f3e1b, 0xe4407f00, 0xf4ffff09, + 0xf10f260b, 0x1bf4bfa6, 0xff0be40b, 0xb5273eff, 0x0c3a9800, 0xffff0ce4, 0x00b67e7e, 0xb900adb3, + 0xff0be400, 0x9019b2ff, 0x44900122, 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, + 0x3c980c3a, 0xb67e7e0a, 0x00adb300, 0x31b5008c, 0xb5db3e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, + 0x04bd00f3, 0x3e527fb5, 0x7f00b593, 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, + 0xb300b67e, 0xb45200a4, 0xe9980be0, 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, + 0xffff0be4, 0x00b67e7e, 0x2d00a4b3, 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5817e, 0x1900a4b3, + 0x98469034, 0x94f0517f, 0xf0f9bcff, 0x3e517fb5, 0x0a00b5db, 0x3ea5b203, 0x9000b5e6, 0x77900188, + 0x148db318, 0x49fefd90, 0x3c999001, 0x517e9abf, 0xfc3e00b7, 0x030500b5, 0x00b5fe3e, 0x0bb204bd, + 0x147e3ab2, 0x50b300a6, 0x3a981a00, 0x7e04bd0c, 0x9800b6d0, 0x30b50d3a, 0xb7517e0c, 0x0d30b500, + 0x900149fe, 0x9fbf5099, 0x0005ecd9, 0xb299bf00, 0xf4f9a65a, 0x403e110b, 0x010500b6, 0x00b5fc3e, + 0x003a317e, 0xf93085fb, 0x7ea0b202, 0x9800a5f0, 0xd07e0c0a, 0x0a9800b6, 0xb7517e0d, 0x7e0ab200, + 0xbd00b751, 0xbf01fba4, 0x0aafb2a9, 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, + 0x020aafb2, 0x18f4b9a6, 0x01b9900b, 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, + 0xfbb500f8, 0xb5fca002, 0x00f801fc, 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, + 0xa998a9a0, 0xa6aabf01, 0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7517e, 0x30f400f8, 0x05ecdff8, + 0x32f90000, 0x49feffbf, 0x14999001, 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, + 0xb60141fe, 0x119002b4, 0x7e1ab210, 0xb300b7bd, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, + 0x9eb201e9, 0xa699fcbc, 0xf408f490, 0x3da0ddbf, 0x00b7363e, 0x49fe020a, 0x14999001, 0xecd99fbf, + 0xbf000005, 0xf4f9a699, 0x317e070b, 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, + 0xa6f00bac, 0x01aab901, 0x44da00f8, 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, + 0x2944da00, 0xd77e0000, 0xa6300042, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, + 0x0b7e7e00, 0xf900f800, 0x3da0b202, 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, + 0x7ea43da0, 0xb000382a, 0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xecdfe430, 0xf9000005, 0xfeffbf82, + 0x45fe0149, 0x3c999001, 0xa00147fe, 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, + 0xff0d2cbb, 0x0000c17e, 0xeb00a433, 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, + 0x3e043d00, 0x9800b979, 0x2cd9023f, 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, + 0xff090159, 0xf43379a0, 0xf77e1800, 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, + 0xbd0043f0, 0xb8b93e14, 0x0241bc00, 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, + 0xff2ce49a, 0xb26bb2ff, 0x1300de0d, 0x1a7e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, + 0x7c0eb204, 0x10bc2020, 0x1300da10, 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, + 0xa6000013, 0xa408f414, 0x00b9683e, 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, + 0x18389003, 0x090159b5, 0x3379a0ff, 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, + 0xff26e4f1, 0x3e24bdff, 0xbc00b959, 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, + 0x042d9001, 0x00da1eb2, 0x7e000013, 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, + 0x40417c00, 0x3500a433, 0x001424d9, 0x7e9abf00, 0xa000ac44, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, + 0xa6000013, 0xa608f426, 0x5c985bbf, 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, + 0x0d33000f, 0x30fe7100, 0x020f3a01, 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, + 0x717e38aa, 0xf33e000f, 0x02f900b7, 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, + 0xa6008961, 0x009fcf02, 0x1000f5f1, 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, + 0x00a43300, 0x2930d915, 0x9abf0000, 0x00009b7e, 0x1e3e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, + 0xb802a400, 0x000200aa, 0x920aa5b6, 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, + 0x000001fb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0xfb3a453a, 0x7158de23, 0xaef7305e, 0xd220040f, - 0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8db5cb00, 0x30cfe9a4, 0xc1a3eea2, 0x79a1340e, + 0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x294f2cc2, 0x883a9d68, 0x493e2990, 0xc8e27d59, + 0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8fc5fac6, 0xe1f366be, 0x1ec159bf, 0x352ff984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h b/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h index d482145135..4f33b77593 100644 --- a/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/soe/soe_priv_nvswitch.h @@ -55,6 +55,11 @@ struct SOE /*! The event descriptor for the Thermal event handler */ NvU32 thermEvtDesc; + /*! The event descriptor for the CCI event handler */ + NvU32 cciEvtDesc; + + /*! The event descriptor for the Heartbeat event handler */ + NvU32 heartbeatEvtDesc; }; #endif //_SOE_PRIV_NVSWITCH_H_ diff --git a/src/common/nvswitch/kernel/lr10/cci_lr10.c b/src/common/nvswitch/kernel/lr10/cci_lr10.c new file mode 100644 index 0000000000..e2c436e9c2 --- /dev/null +++ b/src/common/nvswitch/kernel/lr10/cci_lr10.c @@ -0,0 +1,258 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" + + +NvBool +nvswitch_is_cci_supported_lr10 +( + nvswitch_device *device +) +{ + return NV_FALSE; +} + +void +nvswitch_cci_setup_gpio_pins_lr10 +( + nvswitch_device *device +) +{ + // NOP +} + +NvlStatus +nvswitch_cci_get_cci_link_mode_lr10 +( + nvswitch_device *device, + NvU32 linkNumber, + NvU64 *mode +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_discovery_lr10 +( + nvswitch_device *device +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_cci_get_xcvrs_present_lr10 +( + nvswitch_device *device, + NvU32 *pMaskPresent +) +{ + // NOP +} + +void +nvswitch_cci_get_xcvrs_present_change_lr10 +( + nvswitch_device *device, + NvU32 *pMaskPresentChange +) +{ + // NOP +} + +NvlStatus +nvswitch_cci_reset_lr10 +( + nvswitch_device *device +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_reset_links_lr10 +( + nvswitch_device *device, + NvU64 linkMask +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_ports_cpld_read_lr10 +( + nvswitch_device *device, + NvU8 reg, + NvU8 *pData +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_ports_cpld_write_lr10 +( + nvswitch_device *device, + NvU8 reg, + NvU8 data +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_cci_update_link_state_led_lr10 +( + nvswitch_device *device +) +{ + // Not supported +} + +NvlStatus +nvswitch_cci_set_xcvr_led_state_lr10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvBool bSetLocate +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_get_xcvr_led_state_lr10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 *pLedState +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_setup_onboard_lr10 +( + nvswitch_device *device +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_setup_module_path_lr10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_module_access_cmd_lr10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU32 addr, + NvU32 length, + NvU8 *pValArray, + NvBool bRead, + NvBool bBlk +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_apply_control_set_values_lr10 +( + nvswitch_device *device, + NvU32 client, + NvU32 moduleMask +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_cmis_cage_bezel_marking_lr10 +( + nvswitch_device *device, + NvU8 cageIndex, + char *pBezelMarking +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_get_grading_values_lr10 +( + nvswitch_device *device, + NvU32 client, + NvU32 linkId, + NvU8 *laneMask, + NVSWITCH_CCI_GRADING_VALUES *pGrading +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_get_xcvr_mask_lr10 +( + nvswitch_device *device, + NvU32 *pMaskAll, + NvU32 *pMaskPresent +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_cci_set_xcvr_present_lr10 +( + nvswitch_device *device, + NvU32 maskPresent +) +{ + // NOP +} + +void +nvswitch_cci_destroy_lr10 +( + nvswitch_device *device +) +{ + // NOP +} diff --git a/src/common/nvswitch/kernel/lr10/link_lr10.c b/src/common/nvswitch/kernel/lr10/link_lr10.c index 552d88579f..f3ddd5211e 100644 --- a/src/common/nvswitch/kernel/lr10/link_lr10.c +++ b/src/common/nvswitch/kernel/lr10/link_lr10.c @@ -571,6 +571,11 @@ nvswitch_init_lpwr_regs_lr10 return; } + if (nvswitch_is_link_in_reset(device, link)) + { + return; + } + if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) { return; @@ -686,6 +691,15 @@ nvswitch_init_lpwr_regs_lr10 tempRegVal); } +void +nvswitch_program_l1_scratch_reg_lr10 +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + // Not Implemented for LR10 +} void nvswitch_init_buffer_ready_lr10 @@ -2635,3 +2649,36 @@ nvswitch_link_termination_setup_lr10 return NVL_SUCCESS; } + +NvlStatus +nvswitch_ctrl_get_link_l1_capability_lr10 +( + nvswitch_device *device, + NvU32 linkNum, + NvBool *isL1Capable +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_ctrl_get_link_l1_threshold_lr10 +( + nvswitch_device *device, + NvU32 linkNum, + NvU32 *lpThreshold +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_ctrl_set_link_l1_threshold_lr10 +( + nvlink_link *link, + NvU32 lpEntryThreshold +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index f7bffaf1ac..879a70f36c 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,6 +36,7 @@ #include "lr10/smbpbi_lr10.h" #include "flcn/flcnable_nvswitch.h" #include "soe/soe_nvswitch.h" +#include "lr10/cci_lr10.h" #include "nvswitch/lr10/dev_nvs_top.h" #include "nvswitch/lr10/dev_pri_ringmaster.h" @@ -3656,6 +3657,15 @@ nvswitch_initialize_device_state_lr10 goto nvswitch_initialize_device_state_exit; } + retval = nvswitch_check_io_sanity(device); + if (NVL_SUCCESS != retval) + { + NVSWITCH_PRINT(device, ERROR, + "%s: IO sanity test failed\n", + __FUNCTION__); + goto nvswitch_initialize_device_state_exit; + } + NVSWITCH_PRINT(device, SETUP, "%s: MMIO discovery\n", __FUNCTION__); @@ -5974,7 +5984,8 @@ NvlStatus nvswitch_reset_and_drain_links_lr10 ( nvswitch_device *device, - NvU64 link_mask + NvU64 link_mask, + NvBool bForced ) { NvlStatus status = -NVL_ERR_GENERIC; @@ -7856,6 +7867,250 @@ nvswitch_ctrl_get_nvlink_error_threshold_lr10 return -NVL_ERR_NOT_SUPPORTED; } +NvlStatus +nvswitch_get_board_id_lr10 +( + nvswitch_device *device, + NvU16 *pBoardId +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_ctrl_get_soe_heartbeat_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +static NvlStatus +nvswitch_cci_reset_and_drain_links_lr10 +( + nvswitch_device *device, + NvU64 link_mask, + NvBool bForced +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_update_link_state_led_lr10 +( + nvswitch_device *device +) +{ + return; +} + +void +nvswitch_led_shutdown_lr10 +( + nvswitch_device *device +) +{ + return; +} + +NvlStatus +nvswitch_check_io_sanity_lr10 +( + nvswitch_device *device +) +{ + return NVL_SUCCESS; +} + +void +nvswitch_fsp_update_cmdq_head_tail_lr10 +( + nvswitch_device *device, + NvU32 queueHead, + NvU32 queueTail +) +{ + return; // -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_fsp_get_cmdq_head_tail_lr10 +( + nvswitch_device *device, + NvU32 *pQueueHead, + NvU32 *pQueueTail +) +{ + return; // -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_fsp_update_msgq_head_tail_lr10 +( + nvswitch_device *device, + NvU32 msgqHead, + NvU32 msgqTail +) +{ + return; // -NVL_ERR_NOT_SUPPORTED; +} + +void +nvswitch_fsp_get_msgq_head_tail_lr10 +( + nvswitch_device *device, + NvU32 *pMsgqHead, + NvU32 *pMsgqTail +) +{ + return; // -NVL_ERR_NOT_SUPPORTED; +} + +NvU32 +nvswitch_fsp_get_channel_size_lr10 +( + nvswitch_device *device +) +{ + return 0; // -NVL_ERR_NOT_SUPPORTED; +} + +NvU8 +nvswitch_fsp_nvdm_to_seid_lr10 +( + nvswitch_device *device, + NvU8 nvdmType +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvU32 +nvswitch_fsp_create_mctp_header_lr10 +( + nvswitch_device *device, + NvU8 som, + NvU8 eom, + NvU8 seid, + NvU8 seq +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvU32 +nvswitch_fsp_create_nvdm_header_lr10 +( + nvswitch_device *device, + NvU32 nvdmType +) +{ + return 0; // -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsp_get_packet_info_lr10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size, + NvU8 *pPacketState, + NvU8 *pTag +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsp_validate_mctp_payload_header_lr10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsp_process_nvdm_msg_lr10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsp_process_cmd_response_lr10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsp_config_ememc_lr10 +( + nvswitch_device *device, + NvU32 offset, + NvBool bAincw, + NvBool bAincr +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsp_write_to_emem_lr10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsp_read_from_emem_lr10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsp_error_code_to_nvlstatus_map_lr10 +( + nvswitch_device *device, + NvU32 errorCode +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_fsprpc_get_caps_lr10 +( + nvswitch_device *device, + NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + // // This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL // macro in haldef_nvswitch.h diff --git a/src/common/nvswitch/kernel/ls10/cci_ls10.c b/src/common/nvswitch/kernel/ls10/cci_ls10.c new file mode 100644 index 0000000000..14f2070d56 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/cci_ls10.c @@ -0,0 +1,1728 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "error_nvswitch.h" +#include "export_nvswitch.h" +#include "soe/soe_nvswitch.h" +#include "ls10/soe_ls10.h" +#include "soe/soeifcci.h" +#include "cci/cci_nvswitch.h" +#include "cci/cci_priv_nvswitch.h" +#include "nvswitch/ls10/dev_pmgr.h" +#include "boards_nvswitch.h" +#include "regkey_nvswitch.h" + +#include "ls10/cci_ls10.h" + +#define CCI_LINK_TRAINING_POLLING_RATE_HZ 1 +#define CCI_CDB_PROCESSING_POLLING_RATE_HZ 50 + +#define OSFP_LANE_MASK_LS10(lane0, lane1) \ + (NVBIT(lane0) | NVBIT(lane1)) + +#define MUX_I2C_ADDR_PCA9847 (0x71 << 1) +#define MODULE_ID_TO_MUX_CHANNEL_PCA9847(id) (id | 0x8) + +// +// E4840 board +// +NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE nvswitch_i2c_device_list_e4840[] = +{ + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), +}; + +const NvU32 nvswitch_i2c_device_list_e4840_size = + NV_ARRAY_ELEMENTS(nvswitch_i2c_device_list_e4840); + +// +// Vulcan board +// +NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE nvswitch_i2c_device_list_vulcan[] = +{ + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), +}; + +const NvU32 nvswitch_i2c_device_list_vulcan_size = + NV_ARRAY_ELEMENTS(nvswitch_i2c_device_list_vulcan); + +// +// Kong board +// +NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE nvswitch_i2c_device_list_kong[] = +{ + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CC, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CC, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CC, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CC, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CC, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CC, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CC, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CC, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), +}; + +const NvU32 nvswitch_i2c_device_list_kong_size = + NV_ARRAY_ELEMENTS(nvswitch_i2c_device_list_kong); + +// +// Goldstone board +// +NVSWITCH_I2C_DEVICE_DESCRIPTOR_TYPE nvswitch_i2c_device_list_goldstone[] = +{ + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), + NVSWITCH_DESCRIBE_I2C_DEVICE(_I2CB, 0xA0, _CMIS4_MODULE, + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _READ_ACCESS_LEVEL, _PUBLIC) | + DRF_DEF(_NVSWITCH, _I2C_DEVICE, _WRITE_ACCESS_LEVEL, _PUBLIC)), +}; + +const NvU32 nvswitch_i2c_device_list_goldstone_size = + NV_ARRAY_ELEMENTS(nvswitch_i2c_device_list_goldstone); + +/* + * Mapping between osfp, linkId, and osfp-lane-mask for E4840. + * + */ +NVSWITCH_CCI_MODULE_LINK_LANE_MAP nvswitch_cci_osfp_map_e4840[] = +{ + { 0, 36, OSFP_LANE_MASK_LS10(0, 1) }, + { 0, 37, OSFP_LANE_MASK_LS10(2, 3) }, + { 0, 38, OSFP_LANE_MASK_LS10(4, 5) }, + { 0, 39, OSFP_LANE_MASK_LS10(6, 7) }, + { 1, 40, OSFP_LANE_MASK_LS10(0, 1) }, + { 1, 41, OSFP_LANE_MASK_LS10(2, 3) }, + { 1, 42, OSFP_LANE_MASK_LS10(4, 5) }, + { 1, 43, OSFP_LANE_MASK_LS10(6, 7) }, + { 2, 44, OSFP_LANE_MASK_LS10(0, 1) }, + { 2, 45, OSFP_LANE_MASK_LS10(2, 3) }, + { 2, 46, OSFP_LANE_MASK_LS10(4, 5) }, + { 2, 47, OSFP_LANE_MASK_LS10(6, 7) }, + { 3, 48, OSFP_LANE_MASK_LS10(0, 1) }, + { 3, 49, OSFP_LANE_MASK_LS10(2, 3) }, + { 3, 50, OSFP_LANE_MASK_LS10(4, 5) }, + { 3, 51, OSFP_LANE_MASK_LS10(6, 7) }, + { 4, 52, OSFP_LANE_MASK_LS10(0, 1) }, + { 4, 53, OSFP_LANE_MASK_LS10(2, 3) }, + { 4, 54, OSFP_LANE_MASK_LS10(4, 5) }, + { 4, 55, OSFP_LANE_MASK_LS10(6, 7) }, + { 5, 56, OSFP_LANE_MASK_LS10(0, 1) }, + { 5, 57, OSFP_LANE_MASK_LS10(2, 3) }, + { 5, 58, OSFP_LANE_MASK_LS10(4, 5) }, + { 5, 59, OSFP_LANE_MASK_LS10(6, 7) }, + { 6, 60, OSFP_LANE_MASK_LS10(0, 1) }, + { 6, 61, OSFP_LANE_MASK_LS10(2, 3) }, + { 6, 62, OSFP_LANE_MASK_LS10(4, 5) }, + { 6, 63, OSFP_LANE_MASK_LS10(6, 7) }, +}; + +const NvU32 nvswitch_cci_osfp_map_e4840_size = + NV_ARRAY_ELEMENTS(nvswitch_cci_osfp_map_e4840); + +/* + * Mapping between osfp, linkId, and osfp-lane-mask for Vulcan. + * + */ +NVSWITCH_CCI_MODULE_LINK_LANE_MAP nvswitch_cci_osfp_map_vulcan[] = +{ + { 0, 10, OSFP_LANE_MASK_LS10(0, 1) }, + { 0, 11, OSFP_LANE_MASK_LS10(2, 3) }, + { 0, 8, OSFP_LANE_MASK_LS10(4, 5) }, + { 0, 9, OSFP_LANE_MASK_LS10(6, 7) }, + { 1, 14, OSFP_LANE_MASK_LS10(0, 1) }, + { 1, 15, OSFP_LANE_MASK_LS10(2, 3) }, + { 1, 12, OSFP_LANE_MASK_LS10(4, 5) }, + { 1, 13, OSFP_LANE_MASK_LS10(6, 7) }, + { 2, 28, OSFP_LANE_MASK_LS10(0, 1) }, + { 2, 29, OSFP_LANE_MASK_LS10(2, 3) }, + { 2, 30, OSFP_LANE_MASK_LS10(4, 5) }, + { 2, 31, OSFP_LANE_MASK_LS10(6, 7) }, + { 3, 24, OSFP_LANE_MASK_LS10(0, 1) }, + { 3, 25, OSFP_LANE_MASK_LS10(2, 3) }, + { 3, 26, OSFP_LANE_MASK_LS10(4, 5) }, + { 3, 27, OSFP_LANE_MASK_LS10(6, 7) }, + { 4, 20, OSFP_LANE_MASK_LS10(0, 1) }, + { 4, 21, OSFP_LANE_MASK_LS10(2, 3) }, + { 4, 22, OSFP_LANE_MASK_LS10(4, 5) }, + { 4, 23, OSFP_LANE_MASK_LS10(6, 7) }, +}; + +const NvU32 nvswitch_cci_osfp_map_vulcan_size = + NV_ARRAY_ELEMENTS(nvswitch_cci_osfp_map_vulcan); + +/* + * Mapping between osfp, linkId, and osfp-lane-mask for Kong. + * + */ +NVSWITCH_CCI_MODULE_LINK_LANE_MAP nvswitch_cci_osfp_map_kong[] = +{ + { 0, 50, OSFP_LANE_MASK_LS10(0, 1) }, + { 0, 49, OSFP_LANE_MASK_LS10(2, 3) }, + { 0, 51, OSFP_LANE_MASK_LS10(4, 5) }, + { 0, 48, OSFP_LANE_MASK_LS10(6, 7) }, + { 1, 59, OSFP_LANE_MASK_LS10(0, 1) }, + { 1, 56, OSFP_LANE_MASK_LS10(2, 3) }, + { 1, 58, OSFP_LANE_MASK_LS10(4, 5) }, + { 1, 57, OSFP_LANE_MASK_LS10(6, 7) }, + { 2, 54, OSFP_LANE_MASK_LS10(0, 1) }, + { 2, 53, OSFP_LANE_MASK_LS10(2, 3) }, + { 2, 55, OSFP_LANE_MASK_LS10(4, 5) }, + { 2, 52, OSFP_LANE_MASK_LS10(6, 7) }, + { 3, 63, OSFP_LANE_MASK_LS10(0, 1) }, + { 3, 60, OSFP_LANE_MASK_LS10(2, 3) }, + { 3, 62, OSFP_LANE_MASK_LS10(4, 5) }, + { 3, 61, OSFP_LANE_MASK_LS10(6, 7) }, + { 4, 47, OSFP_LANE_MASK_LS10(0, 1) }, + { 4, 44, OSFP_LANE_MASK_LS10(2, 3) }, + { 4, 46, OSFP_LANE_MASK_LS10(4, 5) }, + { 4, 45, OSFP_LANE_MASK_LS10(6, 7) }, + { 5, 38, OSFP_LANE_MASK_LS10(0, 1) }, + { 5, 37, OSFP_LANE_MASK_LS10(2, 3) }, + { 5, 39, OSFP_LANE_MASK_LS10(4, 5) }, + { 5, 36, OSFP_LANE_MASK_LS10(6, 7) }, + { 6, 43, OSFP_LANE_MASK_LS10(0, 1) }, + { 6, 40, OSFP_LANE_MASK_LS10(2, 3) }, + { 6, 42, OSFP_LANE_MASK_LS10(4, 5) }, + { 6, 41, OSFP_LANE_MASK_LS10(6, 7) }, + { 7, 34, OSFP_LANE_MASK_LS10(0, 1) }, + { 7, 33, OSFP_LANE_MASK_LS10(2, 3) }, + { 7, 35, OSFP_LANE_MASK_LS10(4, 5) }, + { 7, 32, OSFP_LANE_MASK_LS10(6, 7) }, + { 8, 2, OSFP_LANE_MASK_LS10(0, 1) }, + { 8, 1, OSFP_LANE_MASK_LS10(2, 3) }, + { 8, 3, OSFP_LANE_MASK_LS10(4, 5) }, + { 8, 0, OSFP_LANE_MASK_LS10(6, 7) }, + { 9, 11, OSFP_LANE_MASK_LS10(0, 1) }, + { 9, 8, OSFP_LANE_MASK_LS10(2, 3) }, + { 9, 10, OSFP_LANE_MASK_LS10(4, 5) }, + { 9, 9, OSFP_LANE_MASK_LS10(6, 7) }, + { 10, 6, OSFP_LANE_MASK_LS10(0, 1) }, + { 10, 5, OSFP_LANE_MASK_LS10(2, 3) }, + { 10, 7, OSFP_LANE_MASK_LS10(4, 5) }, + { 10, 4, OSFP_LANE_MASK_LS10(6, 7) }, + { 11, 15, OSFP_LANE_MASK_LS10(0, 1) }, + { 11, 12, OSFP_LANE_MASK_LS10(2, 3) }, + { 11, 14, OSFP_LANE_MASK_LS10(4, 5) }, + { 11, 13, OSFP_LANE_MASK_LS10(6, 7) }, + { 12, 31, OSFP_LANE_MASK_LS10(0, 1) }, + { 12, 28, OSFP_LANE_MASK_LS10(2, 3) }, + { 12, 30, OSFP_LANE_MASK_LS10(4, 5) }, + { 12, 29, OSFP_LANE_MASK_LS10(6, 7) }, + { 13, 22, OSFP_LANE_MASK_LS10(0, 1) }, + { 13, 21, OSFP_LANE_MASK_LS10(2, 3) }, + { 13, 23, OSFP_LANE_MASK_LS10(4, 5) }, + { 13, 20, OSFP_LANE_MASK_LS10(6, 7) }, + { 14, 27, OSFP_LANE_MASK_LS10(0, 1) }, + { 14, 24, OSFP_LANE_MASK_LS10(2, 3) }, + { 14, 26, OSFP_LANE_MASK_LS10(4, 5) }, + { 14, 25, OSFP_LANE_MASK_LS10(6, 7) }, + { 15, 18, OSFP_LANE_MASK_LS10(0, 1) }, + { 15, 17, OSFP_LANE_MASK_LS10(2, 3) }, + { 15, 19, OSFP_LANE_MASK_LS10(4, 5) }, + { 15, 16, OSFP_LANE_MASK_LS10(6, 7) }, +}; + +const NvU32 nvswitch_cci_osfp_map_kong_size = + NV_ARRAY_ELEMENTS(nvswitch_cci_osfp_map_kong); + +/* + * Mapping between osfp, linkId, and osfp-lane-mask for Goldstone. + * + */ +NVSWITCH_CCI_MODULE_LINK_LANE_MAP nvswitch_cci_osfp_map_goldstone[] = +{ + { 0, 50, OSFP_LANE_MASK_LS10(0, 1) }, + { 0, 49, OSFP_LANE_MASK_LS10(2, 3) }, + { 0, 51, OSFP_LANE_MASK_LS10(4, 5) }, + { 0, 48, OSFP_LANE_MASK_LS10(6, 7) }, + { 1, 54, OSFP_LANE_MASK_LS10(0, 1) }, + { 1, 53, OSFP_LANE_MASK_LS10(2, 3) }, + { 1, 55, OSFP_LANE_MASK_LS10(4, 5) }, + { 1, 52, OSFP_LANE_MASK_LS10(6, 7) }, + { 2, 58, OSFP_LANE_MASK_LS10(0, 1) }, + { 2, 57, OSFP_LANE_MASK_LS10(2, 3) }, + { 2, 59, OSFP_LANE_MASK_LS10(4, 5) }, + { 2, 56, OSFP_LANE_MASK_LS10(6, 7) }, + { 3, 62, OSFP_LANE_MASK_LS10(0, 1) }, + { 3, 61, OSFP_LANE_MASK_LS10(2, 3) }, + { 3, 63, OSFP_LANE_MASK_LS10(4, 5) }, + { 3, 60, OSFP_LANE_MASK_LS10(6, 7) }, + { 4, 47, OSFP_LANE_MASK_LS10(0, 1) }, + { 4, 44, OSFP_LANE_MASK_LS10(2, 3) }, + { 4, 46, OSFP_LANE_MASK_LS10(4, 5) }, + { 4, 45, OSFP_LANE_MASK_LS10(6, 7) }, + { 5, 43, OSFP_LANE_MASK_LS10(0, 1) }, + { 5, 40, OSFP_LANE_MASK_LS10(2, 3) }, + { 5, 42, OSFP_LANE_MASK_LS10(4, 5) }, + { 5, 41, OSFP_LANE_MASK_LS10(6, 7) }, + { 6, 39, OSFP_LANE_MASK_LS10(0, 1) }, + { 6, 36, OSFP_LANE_MASK_LS10(2, 3) }, + { 6, 38, OSFP_LANE_MASK_LS10(4, 5) }, + { 6, 37, OSFP_LANE_MASK_LS10(6, 7) }, + { 7, 35, OSFP_LANE_MASK_LS10(0, 1) }, + { 7, 32, OSFP_LANE_MASK_LS10(2, 3) }, + { 7, 34, OSFP_LANE_MASK_LS10(4, 5) }, + { 7, 33, OSFP_LANE_MASK_LS10(6, 7) }, +}; + +const NvU32 nvswitch_cci_osfp_map_goldstone_size = + NV_ARRAY_ELEMENTS(nvswitch_cci_osfp_map_goldstone); + +NvBool +nvswitch_is_cci_supported_ls10 +( + nvswitch_device *device +) +{ + if (FLD_TEST_DRF(_SWITCH_REGKEY, _CCI_CONTROL, _ENABLE, _FALSE, + device->regkeys.cci_control)) + { + NVSWITCH_PRINT(device, INFO, "CCI is disabled via regkey.\n"); + return NV_FALSE; + } + + // + // Currently, device needs to be initialized before + // board ID can be obtained from bios + // + if (NVSWITCH_IS_DEVICE_INITIALIZED(device) && + !cciSupported(device)) + { + NVSWITCH_PRINT(device, INFO, + "%s: CCI is not supported on current board.\n", + __FUNCTION__); + return NV_FALSE; + } + + return NV_TRUE; +} + +void +nvswitch_cci_setup_gpio_pins_ls10 +( + nvswitch_device *device +) +{ + NvU32 intrCtrl; + + // Disable Ports CPLD interrupts since they are unused + intrCtrl = NVSWITCH_REG_RD32(device, _GPIO_RM_INTR_MSK, _GPIO_LIST_1); + intrCtrl = FLD_SET_DRF(_GPIO, _RM_INTR_MSK_GPIO_LIST_1, _GPIO15_RISING, _DISABLED, intrCtrl); + intrCtrl = FLD_SET_DRF(_GPIO, _RM_INTR_MSK_GPIO_LIST_1, _GPIO15_FALLING, _DISABLED, intrCtrl); + NVSWITCH_REG_WR32(device, _GPIO_RM_INTR_MSK, _GPIO_LIST_1, intrCtrl); +} + +static void +_nvswitch_cci_optimize_link_ls10 +( + nvswitch_device *device, + NvU32 linkId +) +{ + NvBool freeze_maintenance; + NvBool restart_training; + NvBool nvlink_mode; + + freeze_maintenance = NV_FALSE; + restart_training = NV_FALSE; + nvlink_mode = NV_TRUE; + + NVSWITCH_PRINT(device, INFO, "%s Recieved optimize link command for link %d\n", __FUNCTION__, linkId); + + // Optimize Tx & Rx (FM = RT = 0 for OptimizeLink command) + cciConfigureNvlinkModeAsync(device, NVSWITCH_I2C_ACQUIRER_CCI_TRAIN, linkId, + freeze_maintenance, restart_training, nvlink_mode); +} + +/*! + * @brief Callback function to recieve CCI messages from SOE. + */ +void +nvswitch_cci_soe_callback_ls10 +( + nvswitch_device *device, + RM_FLCN_MSG *pGenMsg, + void *pParams, + NvU32 seqDesc, + NV_STATUS status +) +{ + RM_FLCN_MSG_SOE *pMsg = (RM_FLCN_MSG_SOE*)pGenMsg; + RM_SOE_CCI_MSG_ALI_OPTIMIZE_LINK_INFO aliLinkInfo; + + switch (pMsg->msg.cci.msgType) + { + case RM_SOE_CCI_MSG_ID_ALI_OPTIMIZE_LINK_INFO: + { + aliLinkInfo = pMsg->msg.cci.linkInfo; + + _nvswitch_cci_optimize_link_ls10(device, aliLinkInfo.linkId); + break; + } + default: + { + NVSWITCH_PRINT(device, ERROR, "%s Unknown message ID 0x%x\n", __FUNCTION__, pMsg->msg.cci.msgType); + NVSWITCH_ASSERT(0); + } + } +} + +NvlStatus +nvswitch_cci_get_cci_link_mode_ls10 +( + nvswitch_device *device, + NvU32 linkNumber, + NvU64 *mode +) +{ + return cciGetLinkMode(device, linkNumber, mode); +} + +static void +_nvswitch_update_cages_mask_ls10 +( + nvswitch_device *device +) +{ + PCCI pCci = device->pCci; + NvU32 idx_i2cdevice; + NvU32 new_cages; + + new_cages = 0; + + // + // osfp modules will be enumerated based on the order they are listed in + // the CMIS modules device list + // Ex. nvswitch_i2c_device_list_vulcan + // + for(idx_i2cdevice = 0; idx_i2cdevice < pCci->osfp_num; idx_i2cdevice++) + { + new_cages |= NVBIT(idx_i2cdevice); + } + + device->pCci->cagesMask |= new_cages; +} + +// TODO: should be bios driven +static void +_nvswitch_cci_setup_vulcan_config_ls10 +( + nvswitch_device *device +) +{ + PCCI pCci = device->pCci; + NvU32 nvswitchNum; + + nvswitchNum = nvswitch_read_physical_id(device); + + pCci->osfp_i2c_info = nvswitch_i2c_device_list_vulcan; + pCci->osfp_map = nvswitch_cci_osfp_map_vulcan; + + if (nvswitchNum == 0 || nvswitchNum == 3) + { + pCci->osfp_num = (nvswitch_i2c_device_list_vulcan_size - 1); + pCci->osfp_map_size = (nvswitch_cci_osfp_map_vulcan_size - 4); + pCci->numLinks = 16; + } + else + { + pCci->osfp_num = nvswitch_i2c_device_list_vulcan_size; + pCci->osfp_map_size = nvswitch_cci_osfp_map_vulcan_size; + pCci->numLinks = 20; + } +} + +/* + * @brief Detect board + * + */ +static NvlStatus +_nvswitch_cci_detect_board_ls10 +( + nvswitch_device *device +) +{ + PCCI pCci = device->pCci; + NvlStatus retval = NVL_SUCCESS; + NvU16 boardId; + + retval = nvswitch_get_board_id(device, &boardId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s Failed to get board ID. rc:%d\n", + __FUNCTION__, retval); + return -NVL_ERR_NOT_SUPPORTED; + } + + switch (boardId) + { + case NVSWITCH_BOARD_LS10_4840_0000_PC0: + case NVSWITCH_BOARD_LS10_4840_0072_STA: + { + pCci->osfp_i2c_info = nvswitch_i2c_device_list_e4840; + pCci->osfp_num = nvswitch_i2c_device_list_e4840_size; + pCci->osfp_map = nvswitch_cci_osfp_map_e4840; + pCci->osfp_map_size = nvswitch_cci_osfp_map_e4840_size; + pCci->numLinks = 28; + _nvswitch_update_cages_mask_ls10(device); + break; + } + case NVSWITCH_BOARD_LS10_5612_0012_895: + { + _nvswitch_cci_setup_vulcan_config_ls10(device); + _nvswitch_update_cages_mask_ls10(device); + break; + } + case NVSWITCH_BOARD_LS10_4697_0000_895: + { + pCci->osfp_i2c_info = nvswitch_i2c_device_list_kong; + pCci->osfp_num = nvswitch_i2c_device_list_kong_size; + pCci->osfp_map = nvswitch_cci_osfp_map_kong; + pCci->osfp_map_size = nvswitch_cci_osfp_map_kong_size; + pCci->numLinks = 64; + _nvswitch_update_cages_mask_ls10(device); + break; + } + case NVSWITCH_BOARD_LS10_4262_0000_895: + { + pCci->osfp_i2c_info = nvswitch_i2c_device_list_goldstone; + pCci->osfp_num = nvswitch_i2c_device_list_goldstone_size; + pCci->osfp_map = nvswitch_cci_osfp_map_goldstone; + pCci->osfp_map_size = nvswitch_cci_osfp_map_goldstone_size; + pCci->numLinks = 32; + _nvswitch_update_cages_mask_ls10(device); + break; + } + default: + { + return -NVL_ERR_NOT_SUPPORTED; + } + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_cci_discovery_ls10 +( + nvswitch_device *device +) +{ + NvU64 biosVersion; + NvlStatus retval; + + retval = _nvswitch_cci_detect_board_ls10(device); + if (retval != NVL_SUCCESS) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + retval = nvswitch_lib_get_bios_version(device, &biosVersion); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s Get VBIOS version failed.\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (biosVersion < NVSWITCH_CCI_VBIOS_REV_LOCK_VERSION_LS10) + { + NVSWITCH_PRINT(device, ERROR, "%s CCI not supported on current VBIOS. Please update to version %s\n", + __FUNCTION__, NVSWITCH_CCI_VBIOS_REV_LOCK_VERSION_STRING_LS10); + return -NVL_ERR_NOT_SUPPORTED; + } + + return NVL_SUCCESS; +} + +static void +_nvswitch_detect_presence_cci_devices_ls10 +( + nvswitch_device *device, + NvU32 *pMaskPresent +) +{ + NvlStatus retval; + NvU8 val; + NvU32 maskPresent; + + maskPresent = 0; + + retval = nvswitch_cci_ports_cpld_read_ls10(device, CPLD_MACHXO3_PORTS_PRSNT_REG1, &val); + if (retval == NVL_SUCCESS) + { + maskPresent |= val; + } + + retval = nvswitch_cci_ports_cpld_read_ls10(device, CPLD_MACHXO3_PORTS_PRSNT_REG2, &val); + if (retval == NVL_SUCCESS) + { + maskPresent |= (val << 8); + } + + if (pMaskPresent != NULL) + { + *pMaskPresent = maskPresent; + } +} + +void +nvswitch_cci_get_xcvrs_present_ls10 +( + nvswitch_device *device, + NvU32 *pMaskPresent +) +{ + NvU32 maskPresent; + + maskPresent = 0; + + _nvswitch_detect_presence_cci_devices_ls10(device, &maskPresent); + + if (pMaskPresent != NULL) + { + *pMaskPresent = maskPresent; + } +} + +void +nvswitch_cci_set_xcvr_present_ls10 +( + nvswitch_device *device, + NvU32 maskPresent +) +{ + device->pCci->osfpMaskPresent = maskPresent; +} + +void +nvswitch_cci_destroy_ls10 +( + nvswitch_device *device +) +{ + PCCI pCci = device->pCci; + + if (pCci != NULL && pCci->bInitialized) + { + cciModuleOnboardShutdown(device); + } +} + +static void +_nvswitch_detect_presence_change_cci_devices_ls10 +( + nvswitch_device *device, + NvU32 *pMaskPresentChange +) +{ + NvlStatus retval; + NvU8 val; + NvU32 maskPresentChange; + + maskPresentChange = 0; + + retval = nvswitch_cci_ports_cpld_read(device, + CPLD_MACHXO3_PORTS_PRSNT_STATE_CHANGE_REG1, + &val); + if (retval == NVL_SUCCESS) + { + maskPresentChange |= val; + + if (val) + { + // Only clear presence change bits that were set + nvswitch_cci_ports_cpld_write(device, + CPLD_MACHXO3_PORTS_PRSNT_STATE_CHANGE_REG1, + ~val); + } + } + + retval = nvswitch_cci_ports_cpld_read(device, + CPLD_MACHXO3_PORTS_PRSNT_STATE_CHANGE_REG2, + &val); + if (retval == NVL_SUCCESS) + { + maskPresentChange |= (val << 8); + + if (val) + { + // Only clear presence change bits that were set + nvswitch_cci_ports_cpld_write(device, + CPLD_MACHXO3_PORTS_PRSNT_STATE_CHANGE_REG2, + ~val); + } + } + + if (pMaskPresentChange != NULL) + { + *pMaskPresentChange = maskPresentChange; + } +} + +// +// Detects if a hot plug event occured. This operation +// will clear the presence change status register +// +void +nvswitch_cci_get_xcvrs_present_change_ls10 +( + nvswitch_device *device, + NvU32 *pMaskPresentChange +) +{ + NvU32 maskPresentChange; + + maskPresentChange = 0; + + _nvswitch_detect_presence_change_cci_devices_ls10(device, &maskPresentChange); + + if (pMaskPresentChange != NULL) + { + *pMaskPresentChange = maskPresentChange; + } +} + +#define CPLD_MACHXO3_I2C_ADDR (0xC6) + +NvlStatus +nvswitch_cci_ports_cpld_read_ls10 +( + nvswitch_device *device, + NvU8 reg, + NvU8 *pData +) +{ + NVSWITCH_CTRL_I2C_INDEXED_PARAMS i2cIndexed = {0}; + NvlStatus status; + + i2cIndexed.port = NVSWITCH_I2C_PORT_I2CA; + i2cIndexed.bIsRead = NV_TRUE; + i2cIndexed.address = CPLD_MACHXO3_I2C_ADDR; + i2cIndexed.flags = + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _START, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _RESTART, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _STOP, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _ADDRESS_MODE, _7BIT) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _FLAVOR, _HW) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _SPEED_MODE, _100KHZ) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _BLOCK_PROTOCOL, _DISABLED) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _TRANSACTION_MODE, _NORMAL) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _INDEX_LENGTH, _ONE); + i2cIndexed.index[0] = reg; + i2cIndexed.messageLength = 1; + i2cIndexed.acquirer = NVSWITCH_I2C_ACQUIRER_CCI_INITIALIZE; + + status = nvswitch_ctrl_i2c_indexed(device, &i2cIndexed); + + if (status == NVL_SUCCESS) + { + *pData = i2cIndexed.message[0]; + } + + return status; +} + +NvlStatus +nvswitch_cci_ports_cpld_write_ls10 +( + nvswitch_device *device, + NvU8 reg, + NvU8 data +) +{ + NVSWITCH_CTRL_I2C_INDEXED_PARAMS i2cIndexed = {0}; + NvlStatus status; + + i2cIndexed.port = NVSWITCH_I2C_PORT_I2CA; + i2cIndexed.bIsRead = NV_FALSE; + i2cIndexed.address = CPLD_MACHXO3_I2C_ADDR; + i2cIndexed.flags = + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _START, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _RESTART, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _STOP, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _ADDRESS_MODE, _7BIT) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _FLAVOR, _HW) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _SPEED_MODE, _100KHZ) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _BLOCK_PROTOCOL, _DISABLED) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _TRANSACTION_MODE, _NORMAL) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _INDEX_LENGTH, _ONE); + i2cIndexed.index[0] = reg; + i2cIndexed.messageLength = 1; + i2cIndexed.acquirer = NVSWITCH_I2C_ACQUIRER_CCI_INITIALIZE; + + i2cIndexed.message[0] = data; + + status = nvswitch_ctrl_i2c_indexed(device, &i2cIndexed); + + return status; +} + +static NvlStatus +_nvswitch_cci_reset_mux_ls10 +( + nvswitch_device *device, + NvU8 i2cPort +) +{ + NvlStatus retval; + NvU8 regByte; + + retval = nvswitch_cci_ports_cpld_read_ls10(device, CPLD_MACHXO3_CPLD_CTL_REG1, ®Byte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Assert I2C Mux reset + if (i2cPort == NVSWITCH_I2C_PORT_I2CB) + { + regByte = FLD_SET_REF_NUM(CPLD_MACHXO3_CPLD_CTL_REG1_I2CB_MUX_RESET, 1, regByte); + } + else + { + regByte = FLD_SET_REF_NUM(CPLD_MACHXO3_CPLD_CTL_REG1_I2CC_MUX_RESET, 1, regByte); + } + + retval = nvswitch_cci_ports_cpld_write_ls10(device, CPLD_MACHXO3_CPLD_CTL_REG1, regByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + nvswitch_os_sleep(1); + + // De-assert I2C Mux reset + if (i2cPort == NVSWITCH_I2C_PORT_I2CB) + { + regByte = FLD_SET_REF_NUM(CPLD_MACHXO3_CPLD_CTL_REG1_I2CB_MUX_RESET, 0, regByte); + } + else + { + regByte = FLD_SET_REF_NUM(CPLD_MACHXO3_CPLD_CTL_REG1_I2CC_MUX_RESET, 0, regByte); + } + + retval = nvswitch_cci_ports_cpld_write_ls10(device, CPLD_MACHXO3_CPLD_CTL_REG1, regByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_cci_reset_ls10 +( + nvswitch_device *device +) +{ + NvlStatus retval; + NvU8 regByte; + + // De-assert OSFP reset + retval = nvswitch_cci_ports_cpld_write_ls10(device, CPLD_MACHXO3_PORTS_RESET_REG1, 0); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = nvswitch_cci_ports_cpld_write_ls10(device, CPLD_MACHXO3_PORTS_RESET_REG2, 0); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Clear latch + retval = nvswitch_cci_ports_cpld_write_ls10(device, CPLD_MACHXO3_CPLD_STATUS_REG, 0); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Setup control register + retval = nvswitch_cci_ports_cpld_read_ls10(device, CPLD_MACHXO3_CPLD_CTL_REG1, ®Byte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // Disable watchdog TODO: remove once watchdog implemented + regByte = FLD_SET_REF_NUM(CPLD_MACHXO3_CPLD_CTL_REG1_WATCHDOG_ENABLE, 0, regByte); + + retval = nvswitch_cci_ports_cpld_write_ls10(device, CPLD_MACHXO3_CPLD_CTL_REG1, regByte); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = _nvswitch_cci_reset_mux_ls10(device, NVSWITCH_I2C_PORT_I2CB); + if (retval != NVL_SUCCESS) + { + return retval; + } + + retval = _nvswitch_cci_reset_mux_ls10(device, NVSWITCH_I2C_PORT_I2CC); + if (retval != NVL_SUCCESS) + { + return retval; + } + + nvswitch_os_sleep(1000); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_cci_reset_ls10 +( + nvswitch_device *device +) +{ + PCCI pCci = device->pCci; + + if ((pCci == NULL) || (!pCci->bSupported)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + return _nvswitch_cci_reset_ls10(device); +} + +static NvU8 +_cciGetXcvrNextLedStateLink_ls10 +( + nvswitch_device *device, + NvU8 currentLedState, + NvU8 linkNum +) +{ + nvlink_link *link; + NvU64 linkState; + + link = nvswitch_get_link(device, linkNum); + + if ((link == NULL) || + (device->hal.nvswitch_corelib_get_dl_link_mode(link, &linkState) != NVL_SUCCESS)) + { + return CCI_LED_STATE_OFF; + } + + switch (linkState) + { + case NVLINK_LINKSTATE_HS: + case NVLINK_LINKSTATE_RECOVERY: + { + return CCI_LED_STATE_UP_WARM; + } + case NVLINK_LINKSTATE_FAULT: + { + return CCI_LED_STATE_FAULT; + } + default: + { + if (currentLedState == CCI_LED_STATE_INITIALIZE) + { + return CCI_LED_STATE_INITIALIZE; + } + return CCI_LED_STATE_OFF; + } + } +} + +static NvU8 +_cciResolveXcvrLedStates_ls10 +( + NvU8 ledState0, + NvU8 ledState1 +) +{ + // Used to resolve link state discrepancies between partner links + ct_assert(CCI_LED_STATE_LOCATE < CCI_LED_STATE_FAULT); + ct_assert(CCI_LED_STATE_FAULT < CCI_LED_STATE_OFF); + ct_assert(CCI_LED_STATE_OFF < CCI_LED_STATE_INITIALIZE); + ct_assert(CCI_LED_STATE_INITIALIZE < CCI_LED_STATE_UP_WARM); + + return (ledState0 < ledState1 ? ledState0 : ledState1); + +} + +static NvU8 +_cciGetXcvrNextLedStateLinks_ls10 +( + nvswitch_device *device, + NvU32 osfp, + NvU8 currentLedState, + NvU64 linkMask +) +{ + NvU8 linkNum; + NvU8 ledState; + NvU8 nextLedState; + + nextLedState = CCI_NUM_LED_STATES; + + NVSWITCH_ASSERT(linkMask != 0); + FOR_EACH_INDEX_IN_MASK(64, linkNum, linkMask) + { + ledState = _cciGetXcvrNextLedStateLink_ls10(device, currentLedState, linkNum); + nextLedState = _cciResolveXcvrLedStates_ls10(nextLedState, ledState); + } + FOR_EACH_INDEX_IN_MASK_END; + + if (nextLedState == CCI_LED_STATE_UP_WARM) + { + // Only tells us that one of the links has activity + if (cciCheckXcvrForLinkTraffic(device, osfp, linkMask)) + { + nextLedState = CCI_LED_STATE_UP_ACTIVE; + } + } + + return nextLedState; +} + +/* + * Determines LED states for both LED A and LED B based on link + * and module state + */ +static NvU8 +_cciGetXcvrNextLedsState_ls10 +( + nvswitch_device *device, + NvU32 osfp +) +{ + NvlStatus status; + NvU64 linkMask; + NvU64 linkMaskA; + NvU64 linkMaskB; + NvU8 linkNum; + NvU8 laneMask; + NvU8 ledsNextState; + NvU8 currentLedsState; + NvU8 currentLedAState; + NvU8 currentLedBState; + + ledsNextState = 0; + + if (device->pCci->isFaulty[osfp] || cciModuleOnboardFailed(device, osfp)) + { + ledsNextState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_A, + CCI_LED_STATE_FAULT, + ledsNextState); + ledsNextState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_B, + CCI_LED_STATE_FAULT, + ledsNextState); + return ledsNextState; + } + + status = cciGetCageMapping(device, osfp, &linkMask, NULL); + if (status != NVL_SUCCESS) + { + ledsNextState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_A, + CCI_LED_STATE_OFF, + ledsNextState); + ledsNextState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_B, + CCI_LED_STATE_OFF, + ledsNextState); + return ledsNextState; + } + + linkMaskA = 0; + linkMaskB = 0; + + // Filter link pairs between those corresponding to LED A and LED B + FOR_EACH_INDEX_IN_MASK(64, linkNum, linkMask) + { + if (cciGetLaneMask(device, linkNum, &laneMask) != NVL_SUCCESS) + { + continue; + } + + // Lanes 0-3 mapped to LED A, lanes 4-7 mapped to LED B + if (laneMask == OSFP_LANE_MASK_LS10(0, 1) || + laneMask == OSFP_LANE_MASK_LS10(2, 3)) + { + linkMaskA |= NVBIT64(linkNum); + } + else + { + linkMaskB |= NVBIT64(linkNum); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // Determine states for LED A and LED B separately + currentLedsState = device->pCci->xcvrCurrentLedState[osfp]; + currentLedAState = REF_VAL(CCI_LED_STATE_LED_A, + currentLedsState); + currentLedBState = REF_VAL(CCI_LED_STATE_LED_B, + currentLedsState); + + ledsNextState = 0; + ledsNextState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_A, + _cciGetXcvrNextLedStateLinks_ls10(device, osfp, + currentLedAState, + linkMaskA), + ledsNextState); + ledsNextState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_B, + _cciGetXcvrNextLedStateLinks_ls10(device, osfp, + currentLedBState, + linkMaskB), + ledsNextState); + + return ledsNextState; +} + +static void +_nvswitch_cci_update_link_state_led_ls10 +( + nvswitch_device *device +) +{ + NvU32 cagesMask; + NvU8 osfp; + NvU8 currentLedsState; + NvU8 currentLedAState; + NvU8 currentLedBState; + NvU8 nextLedsState; + + nextLedsState = 0; + + // LEDs are soldered to the carrier PCBA + if (cciGetXcvrMask(device, &cagesMask, NULL) == NVL_SUCCESS) + { + // Loop over all cages and update leds + FOR_EACH_INDEX_IN_MASK(32, osfp, cagesMask) + { + // + // xcvrCurrentLedState[] is only updated when LED HW state is set + // currentLedsState represents the state of 2 LEDs for LS10 systems + // + currentLedsState = device->pCci->xcvrCurrentLedState[osfp]; + + if (cciModulePresent(device, osfp)) + { + currentLedAState = REF_VAL(CCI_LED_STATE_LED_A, + currentLedsState); + currentLedBState = REF_VAL(CCI_LED_STATE_LED_B, + currentLedsState); + + nextLedsState = _cciGetXcvrNextLedsState_ls10(device, osfp); + + // Locate state overrides other states + if (currentLedAState == CCI_LED_STATE_LOCATE) + { + nextLedsState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_A, + CCI_LED_STATE_LOCATE, + nextLedsState); + } + + if (currentLedBState == CCI_LED_STATE_LOCATE) + { + nextLedsState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_B, + CCI_LED_STATE_LOCATE, + nextLedsState); + } + } + else + { + nextLedsState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_A, + CCI_LED_STATE_OFF, + nextLedsState); + nextLedsState = FLD_SET_REF_NUM(CCI_LED_STATE_LED_B, + CCI_LED_STATE_OFF, + nextLedsState); + } + + // This is the next state that the LED will be set to + cciSetNextXcvrLedState(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + osfp, nextLedsState); + + // Only update HW if required + if (currentLedsState != nextLedsState) + { + // bSetLocate input param is unused for E4840 implementation + cciSetXcvrLedState(device, NVSWITCH_I2C_ACQUIRER_CCI_UX, + osfp, NV_FALSE); + } + } + FOR_EACH_INDEX_IN_MASK_END; + } +} + +void +nvswitch_cci_update_link_state_led_ls10 +( + nvswitch_device *device +) +{ + _nvswitch_cci_update_link_state_led_ls10(device); +} + +/* + * Returns the CPLD register value assigned to a particular CCI LED state + * confluence page ID: 1011518154 + */ +static NvU8 +_cciGetXcvrLedStateRegVal_ls10 +( + NvU8 ledState +) +{ + switch (ledState) + { + case CCI_LED_STATE_OFF: + { + return CPLD_MACHXO3_LED_STATE_REG_LED_STATE_OFF; + } + case CCI_LED_STATE_UP_WARM: + { + return CPLD_MACHXO3_LED_STATE_REG_LED_STATE_GREEN; + } + case CCI_LED_STATE_INITIALIZE: + { + return CPLD_MACHXO3_LED_STATE_REG_LED_STATE_3HZ_AMBER; + } + case CCI_LED_STATE_UP_ACTIVE: + { + return CPLD_MACHXO3_LED_STATE_REG_LED_STATE_3HZ_GREEN; + } + case CCI_LED_STATE_FAULT: + { + return CPLD_MACHXO3_LED_STATE_REG_LED_STATE_6HZ_AMBER; + } + case CCI_LED_STATE_LOCATE: + { + return CPLD_MACHXO3_LED_STATE_REG_LED_STATE_6HZ_AMBER_GREEN; + } + default: + { + NVSWITCH_ASSERT(0); + return CPLD_MACHXO3_LED_STATE_REG_LED_STATE_OFF; + } + } +} + +/* + * + */ +static NvlStatus +_cciSetXcvrLedState_ls10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp +) +{ + NvlStatus retval; + NvU8 ledAState; + NvU8 ledBState; + NvU8 nextLedState; + NvU8 regVal; + + nextLedState = device->pCci->xcvrNextLedState[osfp]; + ledAState = REF_VAL(CCI_LED_STATE_LED_A, nextLedState); + ledBState = REF_VAL(CCI_LED_STATE_LED_B, nextLedState); + + regVal = 0; + regVal = FLD_SET_REF_NUM(CPLD_MACHXO3_LED_STATE_REG_LED_A, + _cciGetXcvrLedStateRegVal_ls10(ledAState), + regVal); + regVal = FLD_SET_REF_NUM(CPLD_MACHXO3_LED_STATE_REG_LED_B, + _cciGetXcvrLedStateRegVal_ls10(ledBState), + regVal); + + // Set states for both LED A and LED B + retval = nvswitch_cci_ports_cpld_write(device, CPLD_MACHXO3_LED_STATE_REG(osfp), regVal); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // save CCI HW state + device->pCci->xcvrCurrentLedState[osfp] = REF_NUM(CCI_LED_STATE_LED_A, ledAState) | + REF_NUM(CCI_LED_STATE_LED_B, ledBState); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_cci_set_xcvr_led_state_ls10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvBool bSetLocate +) +{ + return _cciSetXcvrLedState_ls10(device, client, osfp); +} + +static NvlStatus +_nvswitch_cci_setup_link_mask_ls10 +( + nvswitch_device *device +) +{ + NvU64 linkTrainDisableMask; + nvlink_link *link; + NvU8 linkId; + + cciGetAllLinks(device, &device->pCci->linkMask); + + linkTrainDisableMask = 0; + +#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS) + linkTrainDisableMask = (NvU64)device->regkeys.cci_link_train_disable_mask | + ((NvU64)device->regkeys.cci_link_train_disable_mask2 << 32); +#endif + device->pCci->linkMask = device->pCci->linkMask & ~linkTrainDisableMask; + + // Mark links as CCI managed for use by the NVLink library + FOR_EACH_INDEX_IN_MASK(64, linkId, device->pCci->linkMask) + { + link = nvswitch_get_link(device, linkId); + if (link == NULL) + { + return -NVL_ERR_GENERIC; + } + link->bCciManaged = NV_TRUE; + } + FOR_EACH_INDEX_IN_MASK_END; + + NVSWITCH_PRINT(device, INFO, + "%s: Initial CCI link mask 0x%llx\n", __FUNCTION__, + device->pCci->linkMask); + + return NVL_SUCCESS; +} + +static void +_nvswitch_cci_link_training_callback_ls10 +( + nvswitch_device *device +) +{ + nvswitch_cci_update_link_state_led(device); + cciModulesOnboardCallback(device); +} + +static void +_nvswitch_cci_cdb_processing_callback_ls10 +( + nvswitch_device *device +) +{ + // + // TODO: Should be performed in SWGEN0 interrupt handler + // Bug 3660933 + // + if (nvswitch_is_soe_supported(device)) + { + soeService_HAL(device, ((PSOE)device->pSoe)); + cciProcessCDBCallback(device); + } +} + +NvlStatus +nvswitch_cci_setup_onboard_ls10 +( + nvswitch_device *device +) +{ + NvlStatus status; + + // Update Link Mask + status = _nvswitch_cci_setup_link_mask_ls10(device); + if (status != NVL_SUCCESS) + { + return status; + } + + // Initializes module onboard state machine + cciModulesOnboardInit(device); + + status = cciRegisterCallback(device, NVSWITCH_CCI_CALLBACK_LINK_STATE_UPDATE, + _nvswitch_cci_link_training_callback_ls10, + CCI_LINK_TRAINING_POLLING_RATE_HZ); + if (status != NVL_SUCCESS) + { + return status; + } + + status = cciRegisterCallback(device, NVSWITCH_CCI_CALLBACK_CDB, + _nvswitch_cci_cdb_processing_callback_ls10, + CCI_CDB_PROCESSING_POLLING_RATE_HZ); + if (status != NVL_SUCCESS) + { + return status; + } + + return status; +} + +NvlStatus +nvswitch_cci_setup_module_path_ls10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp +) +{ + NVSWITCH_CTRL_I2C_INDEXED_PARAMS i2cIndexed = { 0 }; + NvU8 channel; + NvlStatus retval; + + NVSWITCH_ASSERT(osfp < device->pCci->osfp_num); + channel = MODULE_ID_TO_MUX_CHANNEL_PCA9847(osfp); + + if (device->pCci->isFaulty[osfp]) + { + return -NVL_ERR_GENERIC; + } + + i2cIndexed.bIsRead = NV_FALSE; + i2cIndexed.port = device->pCci->osfp_i2c_info[osfp].i2cPortLogical; + i2cIndexed.address = MUX_I2C_ADDR_PCA9847; + i2cIndexed.acquirer = client; + i2cIndexed.flags = + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _START, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _STOP, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _ADDRESS_MODE, _7BIT) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _INDEX_LENGTH, _ONE) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _FLAVOR, _HW) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _SPEED_MODE, _400KHZ) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _TRANSACTION_MODE, _NORMAL); + i2cIndexed.flags |= DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _BLOCK_PROTOCOL, _DISABLED); + i2cIndexed.flags |= DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _RESTART, _NONE); + i2cIndexed.index[0] = channel; + i2cIndexed.messageLength = 1; + i2cIndexed.message[0] = channel; + + retval = nvswitch_ctrl_i2c_indexed(device, &i2cIndexed); + if (retval != NVL_SUCCESS) + { + // Reset mux and try again + _nvswitch_cci_reset_mux_ls10(device, i2cIndexed.port); + + retval = nvswitch_ctrl_i2c_indexed(device, &i2cIndexed); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Setting mux port %d addr 0x%x to channel %d failed. retval %d\n", + __FUNCTION__, i2cIndexed.port, i2cIndexed.address, channel, retval); + return retval; + } + } + + return NVL_SUCCESS; +} + +static NvlStatus +_cci_process_cmd_ls10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU32 addr, + NvU32 length, + NvU8 *pValArray, + NvBool bRead, + NvBool bBlk +) +{ + NVSWITCH_CTRL_I2C_INDEXED_PARAMS i2cIndexed = { 0 }; + NvlStatus retval; + PCCI pCci = device->pCci; + + i2cIndexed.bIsRead = bRead; + i2cIndexed.port = pCci->osfp_i2c_info[osfp].i2cPortLogical; + i2cIndexed.address = (NvU16) pCci->osfp_i2c_info[osfp].i2cAddress; + i2cIndexed.messageLength = length; + i2cIndexed.acquirer = client; + i2cIndexed.flags = + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _START, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _STOP, _SEND) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _ADDRESS_MODE, _7BIT) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _INDEX_LENGTH, _ONE) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _FLAVOR, _HW) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _SPEED_MODE, _400KHZ) | + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _TRANSACTION_MODE, _NORMAL); + i2cIndexed.flags |= bBlk ? + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _BLOCK_PROTOCOL, _ENABLED) : + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _BLOCK_PROTOCOL, _DISABLED); + i2cIndexed.flags |= bRead ? + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _RESTART, _SEND) : + DRF_DEF(SWITCH_CTRL, _I2C_FLAGS, _RESTART, _NONE); + i2cIndexed.index[0] = addr; + + if (!bRead) + { + nvswitch_os_memcpy(i2cIndexed.message, pValArray, length); + } + + retval = nvswitch_ctrl_i2c_indexed(device, &i2cIndexed); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, MMIO, + "%s: I2C command to osfp[%d](addr : 0x%x, port : %d) failed\n", + __FUNCTION__, osfp, + pCci->osfp_i2c_info[osfp].i2cAddress, + pCci->osfp_i2c_info[osfp].i2cPortLogical); + return retval; + } + + if (bRead) + { + nvswitch_os_memcpy(pValArray, i2cIndexed.message, length); + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_cci_module_access_cmd_ls10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU32 addr, + NvU32 length, + NvU8 *pValArray, + NvBool bRead, + NvBool bBlk +) +{ + NvlStatus status; + NVSWITCH_TIMEOUT timeout; + + nvswitch_timeout_create(5 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + + do + { + status = _cci_process_cmd_ls10(device, client, osfp, addr, length, pValArray, bRead, bBlk); + if (status == NVL_SUCCESS) + { + return status; + } + + if (nvswitch_timeout_check(&timeout)) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Timeout waiting for CMIS access to complete! rc = %d\n", + __FUNCTION__, status); + + NVSWITCH_PRINT(device, ERROR, + "%s: Access to register 0x%x failed on osfp[%d](addr : 0x%x, port : %d)\n", + __FUNCTION__, addr, osfp, + device->pCci->osfp_i2c_info[osfp].i2cAddress, + device->pCci->osfp_i2c_info[osfp].i2cPortLogical); + + // Mark as faulty + device->pCci->isFaulty[osfp] = NV_TRUE; + + return -NVL_IO_ERROR; + } + + nvswitch_os_sleep(10); + } while (NV_TRUE); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_cci_get_xcvr_mask_ls10 +( + nvswitch_device *device, + NvU32 *pMaskAll, + NvU32 *pMaskPresent +) +{ + if (pMaskAll != NULL) + { + *pMaskAll = device->pCci->cagesMask; + } + + if (pMaskPresent != NULL) + { + device->pCci->modulesMask = device->pCci->osfpMaskPresent; + *pMaskPresent = device->pCci->modulesMask; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_cci_apply_control_set_values_ls10 +( + nvswitch_device *device, + NvU32 client, + NvU32 moduleMask +) +{ + return -NVL_ERR_NOT_IMPLEMENTED; +} + +NvlStatus +nvswitch_cci_get_xcvr_led_state_ls10 +( + nvswitch_device *device, + NvU32 client, + NvU32 osfp, + NvU8 *pLedState +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_reset_links_ls10 +( + nvswitch_device *device, + NvU64 linkMask +) +{ + // Links resets are managed by the onboard state machine for CCI managed links + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_cmis_cage_bezel_marking_ls10 +( + nvswitch_device *device, + NvU8 cageIndex, + char *pBezelMarking +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +NvlStatus +nvswitch_cci_get_grading_values_ls10 +( + nvswitch_device *device, + NvU32 client, + NvU32 linkId, + NvU8 *laneMask, + NVSWITCH_CCI_GRADING_VALUES *pGrading +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} diff --git a/src/common/nvswitch/kernel/ls10/flcn_ls10.c b/src/common/nvswitch/kernel/ls10/flcn_ls10.c index 5b18bacc30..5c359af892 100644 --- a/src/common/nvswitch/kernel/ls10/flcn_ls10.c +++ b/src/common/nvswitch/kernel/ls10/flcn_ls10.c @@ -279,6 +279,7 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10 { NvU32 ctl, ridx, widx, bufferSize; NvBool bWasFull; + NvU64 bios_version; // Only supported on riscv if (!UPROC_ENG_ARCH_FALCON_RISCV(pFlcn)) @@ -354,8 +355,13 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10 break; } - NVSWITCH_PRINT(device, ERROR, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc); + NVSWITCH_PRINT_SXID_NO_BBX(device, NVSWITCH_ERR_HW_SOE_HALT, "SOE HALT data[%d] = 0x%16llx\n", entry, pc); } + + // Print VBIOS version at the end + nvswitch_lib_get_bios_version(device, &bios_version); + NVSWITCH_PRINT_SXID_NO_BBX(device, NVSWITCH_ERR_HW_SOE_HALT, + "SOE HALT data[%d] = 0x%16llx\n", entry, bios_version); } // reset trace buffer diff --git a/src/common/nvswitch/kernel/ls10/fsprpc_ls10.c b/src/common/nvswitch/kernel/ls10/fsprpc_ls10.c new file mode 100644 index 0000000000..b226098787 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/fsprpc_ls10.c @@ -0,0 +1,612 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "nvlink_export.h" + + +#include "common_nvswitch.h" +#include "fsprpc_nvswitch.h" +#include "ls10/ls10.h" + +#include "fsp/fsp_emem_channels.h" +#include "fsp/nvdm_payload_cmd_response.h" +#include "fsp/fsp_nvdm_format.h" +#include "fsp/fsp_mctp_format.h" +#include "fsp/fsp_tnvl_rpc.h" + +#include "nvswitch/ls10/dev_fsp_pri.h" + +/*! + * @brief Update command queue head and tail pointers + * + * @param[in] device nvswitch device pointer + * @param[in] queueHead Offset to write to command queue head + * @param[in] queueTail Offset to write to command queue tail + */ +void +nvswitch_fsp_update_cmdq_head_tail_ls10 +( + nvswitch_device *device, + NvU32 queueHead, + NvU32 queueTail +) +{ + // The write to HEAD needs to happen after TAIL because it will interrupt FSP + NVSWITCH_REG_WR32(device, _PFSP, _QUEUE_TAIL(FSP_EMEM_CHANNEL_RM), queueTail); + NVSWITCH_REG_WR32(device, _PFSP, _QUEUE_HEAD(FSP_EMEM_CHANNEL_RM), queueHead); +} + +/*! + * @brief Read command queue head and tail pointers + * + * @param[in] device nvswitch device pointer + * @param[out] pQueueHead Pointer where we write command queue head + * @param[out] pQueueTail Pointer where we write command queue tail + */ +void +nvswitch_fsp_get_cmdq_head_tail_ls10 +( + nvswitch_device *device, + NvU32 *pQueueHead, + NvU32 *pQueueTail +) +{ + *pQueueHead = NVSWITCH_REG_RD32(device, _PFSP, _QUEUE_HEAD(FSP_EMEM_CHANNEL_RM)); + *pQueueTail = NVSWITCH_REG_RD32(device, _PFSP, _QUEUE_TAIL(FSP_EMEM_CHANNEL_RM)); +} + +/*! + * @brief Update message queue head and tail pointers + * + * @param[in] device nvswitch device pointer + * @param[in] msgqHead Offset to write to message queue head + * @param[in] msgqTail Offset to write to message queue tail + */ +void +nvswitch_fsp_update_msgq_head_tail_ls10 +( + nvswitch_device *device, + NvU32 msgqHead, + NvU32 msgqTail +) +{ + NVSWITCH_REG_WR32(device, _PFSP, _MSGQ_TAIL(FSP_EMEM_CHANNEL_RM), msgqTail); + NVSWITCH_REG_WR32(device, _PFSP, _MSGQ_HEAD(FSP_EMEM_CHANNEL_RM), msgqHead); +} + +/*! + * @brief Read message queue head and tail pointers + * + * @param[in] device nvswitch device pointer + * @param[out] pMsgqHead Pointer where we write message queue head + * @param[out] pMsgqTail Pointer where we write message queue tail + */ +void +nvswitch_fsp_get_msgq_head_tail_ls10 +( + nvswitch_device *device, + NvU32 *pMsgqHead, + NvU32 *pMsgqTail +) +{ + *pMsgqHead = NVSWITCH_REG_RD32(device, _PFSP, _MSGQ_HEAD(FSP_EMEM_CHANNEL_RM)); + *pMsgqTail = NVSWITCH_REG_RD32(device, _PFSP, _MSGQ_TAIL(FSP_EMEM_CHANNEL_RM)); +} + +/*! + * @brief Get size of RM's channel in FSP EMEM + * + * @param[in] device nvswitch device pointer + * + * @return RM channel size in bytes + */ +NvU32 +nvswitch_fsp_get_channel_size_ls10 +( + nvswitch_device *device +) +{ + // + // Channel size is hardcoded to 1K for now. Later we will use EMEMR to + // properly fetch the lower and higher bounds of the EMEM channel + // + return FSP_EMEM_CHANNEL_RM_SIZE; +} + +/*! + * @brief Retreive SEID based on NVDM type + * + * For now, SEIDs are only needed for use-cases that send multi-packet RM->FSP + * messages. The SEID is used in these cases to route packets to the correct + * task as FSP receives them. Single-packet use-cases are given SEID 0. + * + * @param[in] device nvswitch device pointer + * @param[in] nvdmType NVDM message type + * + * @return SEID corresponding to passed-in NVDM type + */ +NvU8 +nvswitch_fsp_nvdm_to_seid_ls10 +( + nvswitch_device *device, + NvU8 nvdmType +) +{ + NvU8 seid; + + switch (nvdmType) + { + case NVDM_TYPE_INFOROM: + seid = 1; + break; + case NVDM_TYPE_HULK: + default: + seid = 0; + break; + } + + return seid; +} + +/*! + * @brief Create MCTP header + * + * @param[in] device nvswitch_device pointer + * @param[in] som Start of Message flag + * @param[in] eom End of Message flag + * @param[in] tag Message tag + * @param[in] seq Packet sequence number + * + * @return Constructed MCTP header + */ +NvU32 +nvswitch_fsp_create_mctp_header_ls10 +( + nvswitch_device *device, + NvU8 som, + NvU8 eom, + NvU8 seid, + NvU8 seq +) +{ + return (REF_NUM(MCTP_HEADER_SOM, (som)) | + REF_NUM(MCTP_HEADER_EOM, (eom)) | + REF_NUM(MCTP_HEADER_SEID, (seid)) | + REF_NUM(MCTP_HEADER_SEQ, (seq))); +} + +/*! + * @brief Create NVDM payload header + * + * @param[in] device nvswitch_device pointer + * @param[in] nvdmType NVDM type to include in header + * + * @return Constructed NVDM payload header + */ +NvU32 +nvswitch_fsp_create_nvdm_header_ls10 +( + nvswitch_device *device, + NvU32 nvdmType +) +{ + return (REF_DEF(MCTP_MSG_HEADER_TYPE, _VENDOR_PCI) | + REF_DEF(MCTP_MSG_HEADER_VENDOR_ID, _NV) | + REF_NUM(MCTP_MSG_HEADER_NVDM_TYPE, (nvdmType))); +} + +/*! + * @brief Retrieve and validate info in packet's MCTP headers + * + * @param[in] device nvswitch device pointer + * @param[in] pBuffer Buffer containing packet + * @param[in] size Size of buffer in bytes + * @param[out] pPacketState Pointer where we write packet state + * @param[out] pTag Pointer where we write packet's MCTP tag + * + * @return NVL_SUCCESS or NV_ERR_INVALID_DATA + */ +NvlStatus +nvswitch_fsp_get_packet_info_ls10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size, + NvU8 *pPacketState, + NvU8 *pTag +) +{ + NvU32 mctpHeader; + NvU8 som, eom; + NvlStatus status = NVL_SUCCESS; + + mctpHeader = ((NvU32 *)pBuffer)[0]; + + som = REF_VAL(MCTP_HEADER_SOM, mctpHeader); + eom = REF_VAL(MCTP_HEADER_EOM, mctpHeader); + + if ((som == 1) && (eom == 0)) + { + *pPacketState = MCTP_PACKET_STATE_START; + } + else if ((som == 0) && (eom == 1)) + { + *pPacketState = MCTP_PACKET_STATE_END; + } + else if ((som == 1) && (eom == 1)) + { + *pPacketState = MCTP_PACKET_STATE_SINGLE_PACKET; + } + else + { + *pPacketState = MCTP_PACKET_STATE_INTERMEDIATE; + } + + if ((*pPacketState == MCTP_PACKET_STATE_START) || + (*pPacketState == MCTP_PACKET_STATE_SINGLE_PACKET)) + { + // Packet contains payload header, check it + status = nvswitch_fsp_validate_mctp_payload_header(device, pBuffer, size); + } + + *pTag = REF_VAL(MCTP_HEADER_TAG, mctpHeader); + + return status; +} + +/*! + * @brief Validate packet's MCTP payload header + * + * @param[in] device nvswitch device pointer + * @param[in] pBuffer Buffer containing packet + * @param[in] size Size of buffer in bytes + * + * @return NVL_SUCCESS or NV_ERR_INVALID_DATA + */ +NvlStatus +nvswitch_fsp_validate_mctp_payload_header_ls10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + NvU32 mctpPayloadHeader; + NvU16 mctpVendorId; + NvU8 mctpMessageType; + + mctpPayloadHeader = ((NvU32 *)pBuffer)[1]; + + mctpMessageType = REF_VAL(MCTP_MSG_HEADER_TYPE, mctpPayloadHeader); + if (mctpMessageType != MCTP_MSG_HEADER_TYPE_VENDOR_PCI) + { + NVSWITCH_PRINT(device, ERROR, "Invalid MCTP Message type 0x%0x, expecting 0x7e (Vendor Defined PCI)\n", + mctpMessageType); + return -NVL_ERR_INVALID_STATE ; + } + + mctpVendorId = REF_VAL(MCTP_MSG_HEADER_VENDOR_ID, mctpPayloadHeader); + if (mctpVendorId != MCTP_MSG_HEADER_VENDOR_ID_NV) + { + NVSWITCH_PRINT(device, ERROR, "Invalid PCI Vendor Id 0x%0x, expecting 0x10de (Nvidia)\n", + mctpVendorId); + return -NVL_ERR_INVALID_STATE ; + } + + if (size < (sizeof(MCTP_HEADER) + sizeof(NvU8))) + { + NVSWITCH_PRINT(device, ERROR, "Packet doesn't contain NVDM type in payload header\n"); + return -NVL_ERR_INVALID_STATE ; + } + + return NVL_SUCCESS; +} + +/*! + * @brief Process NVDM payload + * + * @param[in] device nvswitch device pointer + * @param[in] pBuffer Buffer containing packet data + * @param[in] Size Buffer size + * + * @return NVL_SUCCESS or NV_ERR_NOT_SUPPORTED + */ +NvlStatus +nvswitch_fsp_process_nvdm_msg_ls10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + NvU8 nvdmType; + NvlStatus status = NVL_SUCCESS; + + nvdmType = pBuffer[0]; + + switch (nvdmType) + { + case NVDM_TYPE_FSP_RESPONSE: + status = nvswitch_fsp_process_cmd_response(device, pBuffer, size); + break; + default: + NVSWITCH_PRINT(device, ERROR, "Unknown or unsupported NVDM type received: 0x%0x\n", + nvdmType); + status = -NVL_ERR_NOT_SUPPORTED; + break; + } + + return status; +} + +/*! + * @brief Process FSP command response + * + * @param[in] device nvswitch device pointer + * @param[in] pBuffer Buffer containing packet data + * @param[in] Size Buffer size + * + * @return NVL_SUCCESS or -NVL_ERR_INVALID_STATE + */ +NvlStatus +nvswitch_fsp_process_cmd_response_ls10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + NVDM_PAYLOAD_COMMAND_RESPONSE *pCmdResponse; + NvU32 headerSize = sizeof(NvU8); // NVDM type + NvlStatus status = NVL_SUCCESS; + + if (size < (headerSize + sizeof(NVDM_PAYLOAD_COMMAND_RESPONSE))) + { + NVSWITCH_PRINT(device, ERROR, "Expected FSP command response, but packet is not big enough for payload. Size: 0x%0x\n", size); + return -NVL_ERR_INVALID_STATE; + } + + pCmdResponse = (NVDM_PAYLOAD_COMMAND_RESPONSE *)&(pBuffer[1]); + + NVSWITCH_PRINT(device, INFO, "Received FSP command response. Task ID: 0x%0x Command type: 0x%0x Error code: 0x%0x\n", + pCmdResponse->taskId, pCmdResponse->commandNvdmType, pCmdResponse->errorCode); + + status = nvswitch_fsp_error_code_to_nvlstatus_map(device, pCmdResponse->errorCode); + if (status == NVL_SUCCESS) + { + NVSWITCH_PRINT(device, INFO, "Last command was processed by FSP successfully!\n"); + } + else if (status != -NVL_NOT_FOUND) + { + + NVSWITCH_PRINT(device, ERROR, "FSP response reported error. Task ID: 0x%0x Command type: 0x%0x Error code: 0x%0x\n", + pCmdResponse->taskId, pCmdResponse->commandNvdmType, pCmdResponse->errorCode); + } + + return status; +} + +/*! + * @brief Configure EMEMC for RM's queue in FSP EMEM + * + * @param[in] device nvswitch device pointer + * @param[in] offset Offset to write to EMEMC in DWORDS + * @param[in] bAincw Flag to set auto-increment on writes + * @param[in] bAincr Flag to set auto-increment on reads + * + * @return NVL_SUCCESS + */ +NvlStatus +nvswitch_fsp_config_ememc_ls10 +( + nvswitch_device *device, + NvU32 offset, + NvBool bAincw, + NvBool bAincr +) +{ + NvU32 offsetBlks, offsetDwords; + NvU32 reg32 = 0; + + // + // EMEMC offset is encoded in terms of blocks (64 DWORDS) and DWORD offset + // within a block, so calculate each. + // + offsetBlks = offset / 64; + offsetDwords = offset % 64; + + reg32 = FLD_SET_DRF_NUM(_PFSP, _EMEMC, _OFFS, offsetDwords, reg32); + reg32 = FLD_SET_DRF_NUM(_PFSP, _EMEMC, _BLK, offsetBlks, reg32); + + if (bAincw) + { + reg32 = FLD_SET_DRF(_PFSP, _EMEMC, _AINCW, _TRUE, reg32); + } + if (bAincr) + { + reg32 = FLD_SET_DRF(_PFSP, _EMEMC, _AINCR, _TRUE, reg32); + } + + NVSWITCH_REG_WR32(device, _PFSP, _EMEMC(FSP_EMEM_CHANNEL_RM), reg32); + + return NVL_SUCCESS; +} + +/*! + * @brief Write data in buffer to RM channel in FSP's EMEM + * + * @param[in] device nvswitch device pointer + * @param[in] pBuffer Buffer with data to write to EMEM + * @param[in] Size Size of buffer in bytes, assumed DWORD aligned + * + * @return NVL_SUCCESS + */ +NvlStatus +nvswitch_fsp_write_to_emem_ls10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + NvU32 i, reg32; + NvU32 ememOffsetEnd; + + // + // First configure EMEMC, RM always writes 0 to the offset, which is OK + // because RM's channel starts at 0 on GH100 and we always start from the + // beginning for each packet. It should be improved later to use EMEMR to + // properly fetch the lower and higher bounds of the EMEM channel + // + nvswitch_fsp_config_ememc(device, 0, NV_TRUE, NV_FALSE); + + NVSWITCH_PRINT(device, INFO, "About to send data to FSP, ememcOff=0, size=0x%x\n", size); + if (!NV_IS_ALIGNED(size, sizeof(NvU32))) + { + NVSWITCH_PRINT(device, WARN, "Size=0x%x is not DWORD-aligned, data will be truncated!\n", size); + } + + // Now write to EMEMD + for (i = 0; i < (size / 4); i++) + { + NVSWITCH_REG_WR32(device, _PFSP, _EMEMD(FSP_EMEM_CHANNEL_RM), ((NvU32*)(void*)pBuffer)[i]); + } + + // Sanity check offset. If this fails, the autoincrement did not work + reg32 = NVSWITCH_REG_RD32(device, _PFSP, _EMEMC(FSP_EMEM_CHANNEL_RM)); + ememOffsetEnd = DRF_VAL(_PFSP, _EMEMC, _OFFS, reg32); + + // Blocks are 64 DWORDS + ememOffsetEnd += DRF_VAL(_PFSP, _EMEMC, _BLK, reg32) * 64; + NVSWITCH_PRINT(device, INFO, "After sending data, ememcOff = 0x%x\n", ememOffsetEnd); + + NVSWITCH_ASSERT((ememOffsetEnd) == (size / sizeof(NvU32))); + return NVL_SUCCESS; +} + +/*! + * @brief Read data to buffer from RM channel in FSP's EMEM + * + * @param[in] device nvswitch_device pointer + * @param[in/out] pBuffer Buffer where we copy data from EMEM + * @param[in] size Size to read in bytes, assumed DWORD aligned + * + * @return NVL_SUCCESS + */ +NvlStatus +nvswitch_fsp_read_from_emem_ls10 +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + NvU32 i, reg32; + NvU32 ememOffsetEnd; + + // + // First configure EMEMC, RM always writes 0 to the offset, which is OK + // because RM's channel starts at 0 on GH100 and we always start from the + // beginning for each packet. It should be improved later to use EMEMR to + // properly fetch the lower and higher bounds of the EMEM channel + // + nvswitch_fsp_config_ememc(device, 0, NV_FALSE, NV_TRUE); + + NVSWITCH_PRINT(device, INFO, "About to read data from FSP, ememcOff=0, size=0x%x\n", size); + if (!NV_IS_ALIGNED(size, sizeof(NvU32))) + { + NVSWITCH_PRINT(device, WARN, "Size=0x%x is not DWORD-aligned, data will be truncated!\n", size); + } + + // Now read from EMEMD + for (i = 0; i < (size / 4); i++) + { + ((NvU32*)(void*)pBuffer)[i] = NVSWITCH_REG_RD32(device, _PFSP, _EMEMD(FSP_EMEM_CHANNEL_RM)); + } + + // Sanity check offset. If this fails, the autoincrement did not work + reg32 = NVSWITCH_REG_RD32(device, _PFSP, _EMEMC(FSP_EMEM_CHANNEL_RM)); + ememOffsetEnd = DRF_VAL(_PFSP, _EMEMC, _OFFS, reg32); + + // Blocks are 64 DWORDS + ememOffsetEnd += DRF_VAL(_PFSP, _EMEMC, _BLK, reg32) * 64; + NVSWITCH_PRINT(device, INFO, "After reading data, ememcOff = 0x%x\n", ememOffsetEnd); + + NVSWITCH_ASSERT((ememOffsetEnd) == (size / sizeof(NvU32))); + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_fsp_error_code_to_nvlstatus_map_ls10 +( + nvswitch_device *device, + NvU32 errorCode +) +{ + switch (errorCode) + { + case FSP_OK: + return NVL_SUCCESS; + + case FSP_ERR_IFR_FILE_NOT_FOUND: + return -NVL_NOT_FOUND; + + case FSP_ERR_IFS_ERR_INVALID_STATE: + case FSP_ERR_IFS_ERR_INVALID_DATA: + return -NVL_ERR_INVALID_STATE; + + default: + return -NVL_ERR_GENERIC; + } +} + +NvlStatus +nvswitch_fsprpc_get_caps_ls10 +( + nvswitch_device *device, + NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params +) +{ + TNVL_RPC_CAPS_PAYLOAD payload; + TNVL_RPC_CAPS_RSP_PAYLOAD responsePayload; + NvlStatus status; + + payload.subMessageId = TNVL_CAPS_SUBMESSAGE_ID; + nvswitch_os_memset(&responsePayload, 0, sizeof(TNVL_RPC_CAPS_RSP_PAYLOAD)); + + status = nvswitch_fsp_send_and_read_message(device, + (NvU8*) &payload, sizeof(TNVL_RPC_CAPS_PAYLOAD), NVDM_TYPE_CAPS_QUERY, + (NvU8*) &responsePayload, sizeof(TNVL_RPC_CAPS_RSP_PAYLOAD)); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "RPC failed for FSP caps query\n"); + return status; + } + + params->responseNvdmType = responsePayload.nvdmType; + params->commandNvdmType = responsePayload.cmdResponse.commandNvdmType; + params->errorCode = responsePayload.cmdResponse.errorCode; + params->pRspPayload = responsePayload.rspPayload; + + return NVL_SUCCESS; +} diff --git a/src/common/nvswitch/kernel/ls10/heartbeat_ls10.c b/src/common/nvswitch/kernel/ls10/heartbeat_ls10.c new file mode 100644 index 0000000000..5fce9536c6 --- /dev/null +++ b/src/common/nvswitch/kernel/ls10/heartbeat_ls10.c @@ -0,0 +1,86 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "common_nvswitch.h" +#include "error_nvswitch.h" +#include "export_nvswitch.h" +#include "ls10/soe_ls10.h" +#include "soe/soeifheartbeat.h" + +/*! + * @brief Callback function to recieve Heartbeat messages from SOE. + */ +void +nvswitch_heartbeat_soe_callback_ls10 +( + nvswitch_device *device, + RM_FLCN_MSG *pGenMsg, + void *pParams, + NvU32 seqDesc, + NV_STATUS status +) +{ + RM_FLCN_MSG_SOE *pMsg = (RM_FLCN_MSG_SOE *)pGenMsg; + + switch (pMsg->msg.heartbeat.msgType) + { + case RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_WARN_ACTIVATED: + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_OSFP_THERM_WARN_ACTIVATED, + "OSFP Thermal Warn Activated\n"); + break; + } + + case RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_WARN_DEACTIVATED: + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_OSFP_THERM_WARN_DEACTIVATED, + "OSFP Thermal Warn Deactivated\n"); + break; + } + + case RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_OVERT_ACTIVATED: + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_OSFP_THERM_OVERT_ACTIVATED, + "OSFP Thermal Overt Activated\n"); + break; + } + + case RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_OVERT_DEACTIVATED: + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_OSFP_THERM_OVERT_DEACTIVATED, + "OSFP Thermal Overt Deactivated\n"); + break; + } + case RM_SOE_HEARTBEAT_MSG_ID_OSFP_THERM_HEARTBEAT_SHUTDOWN: + { + NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_OSFP_THERM_HEARTBEAT_SHUTDOWN, + "OSFP Thermal SOE Heartbeat Shutdown\n"); + break; + } + default: + { + NVSWITCH_PRINT(device, ERROR, "%s Unknown message Id\n", __FUNCTION__); + NVSWITCH_ASSERT(0); + } + } +} diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c index a55a9fea58..86af149c03 100644 --- a/src/common/nvswitch/kernel/ls10/intr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -25,6 +25,7 @@ #include "intr_nvswitch.h" #include "regkey_nvswitch.h" #include "soe/soe_nvswitch.h" +#include "cci/cci_nvswitch.h" #include "ls10/ls10.h" #include "ls10/minion_ls10.h" @@ -1264,12 +1265,12 @@ _nvswitch_service_route_fatal_ls10 if (nvswitch_is_soe_supported(device)) { nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, - report.raw_enable ^ pending, RM_SOE_CORE_NPORT_ROUTE_INTERRUPT); + report.raw_enable & ~pending, RM_SOE_CORE_NPORT_ROUTE_INTERRUPT); } else { NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } } @@ -1478,7 +1479,7 @@ _nvswitch_service_route_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _ROUTE, _ERR_NON_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -1743,12 +1744,12 @@ _nvswitch_service_ingress_fatal_ls10 if (nvswitch_is_soe_supported(device)) { nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, - report.raw_enable ^ pending, RM_SOE_CORE_NPORT_INGRESS_INTERRUPT); + report.raw_enable & ~pending, RM_SOE_CORE_NPORT_INGRESS_INTERRUPT); } else { NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } } @@ -2046,7 +2047,7 @@ _nvswitch_service_ingress_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_NON_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -2189,7 +2190,7 @@ _nvswitch_service_ingress_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _INGRESS, _ERR_NON_FATAL_REPORT_EN_1, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -2329,7 +2330,7 @@ _nvswitch_service_tstate_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_NON_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -2519,12 +2520,12 @@ _nvswitch_service_tstate_fatal_ls10 if (nvswitch_is_soe_supported(device)) { nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, - report.raw_enable ^ pending, RM_SOE_CORE_NPORT_TSTATE_INTERRUPT); + report.raw_enable & ~pending, RM_SOE_CORE_NPORT_TSTATE_INTERRUPT); } else { NVSWITCH_ENG_WR32(device, NPORT, , link, _TSTATE, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } } @@ -2653,7 +2654,7 @@ _nvswitch_service_egress_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_NON_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -2898,7 +2899,7 @@ _nvswitch_service_egress_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_NON_FATAL_REPORT_EN_1, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -3175,12 +3176,12 @@ _nvswitch_service_egress_fatal_ls10 if (nvswitch_is_soe_supported(device)) { nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, - report.raw_enable ^ pending, RM_SOE_CORE_NPORT_EGRESS_0_INTERRUPT); + report.raw_enable & ~pending, RM_SOE_CORE_NPORT_EGRESS_0_INTERRUPT); } else { NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } } @@ -3306,12 +3307,12 @@ _nvswitch_service_egress_fatal_ls10 if (nvswitch_is_soe_supported(device)) { nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, - report.raw_enable ^ pending, RM_SOE_CORE_NPORT_EGRESS_1_INTERRUPT); + report.raw_enable & ~pending, RM_SOE_CORE_NPORT_EGRESS_1_INTERRUPT); } else { NVSWITCH_ENG_WR32(device, NPORT, , link, _EGRESS, _ERR_FATAL_REPORT_EN_1, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } } @@ -3410,7 +3411,7 @@ _nvswitch_service_sourcetrack_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_NON_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -3538,12 +3539,12 @@ _nvswitch_service_sourcetrack_fatal_ls10 if (nvswitch_is_soe_supported(device)) { nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, - report.raw_enable ^ pending, RM_SOE_CORE_NPORT_SOURCETRACK_INTERRUPT); + report.raw_enable & ~pending, RM_SOE_CORE_NPORT_SOURCETRACK_INTERRUPT); } else { NVSWITCH_ENG_WR32(device, NPORT, , link, _SOURCETRACK, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } } @@ -3690,7 +3691,7 @@ _nvswitch_service_multicast_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_NON_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -3830,12 +3831,12 @@ _nvswitch_service_multicast_fatal_ls10 if (nvswitch_is_soe_supported(device)) { nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, - report.raw_enable ^ pending, RM_SOE_CORE_NPORT_MULTICAST_INTERRUPT); + report.raw_enable & ~pending, RM_SOE_CORE_NPORT_MULTICAST_INTERRUPT); } else { NVSWITCH_ENG_WR32(device, NPORT, , link, _MULTICASTTSTATE, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } } @@ -3976,7 +3977,7 @@ _nvswitch_service_reduction_nonfatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_NON_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -4131,12 +4132,12 @@ _nvswitch_service_reduction_fatal_ls10 if (nvswitch_is_soe_supported(device)) { nvswitch_soe_disable_nport_fatal_interrupts_ls10(device, link, - report.raw_enable ^ pending, RM_SOE_CORE_NPORT_REDUCTION_INTERRUPT); + report.raw_enable & ~pending, RM_SOE_CORE_NPORT_REDUCTION_INTERRUPT); } else { NVSWITCH_ENG_WR32(device, NPORT, , link, _REDUCTIONTSTATE, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } } @@ -4534,7 +4535,7 @@ _nvswitch_service_nvltlc_tx_sys_fatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_STATUS_0, pending); @@ -4654,7 +4655,7 @@ _nvswitch_service_nvltlc_rx_sys_fatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_STATUS_0, pending); @@ -4755,7 +4756,7 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -4942,7 +4943,7 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -5045,7 +5046,7 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32_LS10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_1, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -5208,7 +5209,7 @@ _nvswitch_service_nvlipt_common_fatal_ls10 (device->link[link].fatal_error_occurred)) { NVSWITCH_ENG_WR32(device, NVLIPT, , instance, _NVLIPT_COMMON, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); break; } } @@ -5331,7 +5332,7 @@ _nvswitch_service_nxbar_tile_ls10 // Disable interrupts that have occurred after fatal error. // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. NVSWITCH_TILE_WR32(device, tile, _NXBAR_TILE, _ERR_FATAL_INTR_EN, - report.raw_enable ^ pending); + report.raw_enable & ~pending); NVSWITCH_TILE_WR32(device, link, _NXBAR_TILE, _ERR_STATUS, pending); @@ -5435,7 +5436,7 @@ _nvswitch_service_nxbar_tileout_ls10 // Disable interrupts that have occurred after fatal error. // This helps prevent an interrupt storm if HW keeps triggering unnecessary stream of interrupts. NVSWITCH_TILEOUT_WR32(device, tileout, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, - report.raw_enable ^ pending); + report.raw_enable & ~pending); NVSWITCH_TILEOUT_WR32(device, tileout, _NXBAR_TILEOUT, _ERR_STATUS, pending); @@ -5838,6 +5839,12 @@ _nvswitch_deferred_link_state_check_ls10 chip_device->deferredLinkErrors[link].state.bLinkStateCallBackEnabled = NV_FALSE; bRedeferLinkStateCheck = NV_FALSE; + // Ask CCI if link state check should be futher deferred + if (cciIsLinkManaged(device, link) && !cciReportLinkErrors(device, link)) + { + bRedeferLinkStateCheck = NV_TRUE; + } + // Link came up after last retrain if (lastLinkUpTime >= lastRetrainTime) { @@ -6310,7 +6317,7 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -6532,7 +6539,7 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_1, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (report.raw_first & report.mask) @@ -7103,7 +7110,7 @@ _nvswitch_service_nvlipt_lnk_fatal_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FATAL_REPORT_EN_0, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } // clear interrupts @@ -7768,16 +7775,29 @@ nvswitch_service_nvldl_fatal_link_ls10 NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_DOWN event\n", __FUNCTION__); } - dlDeferredIntrLinkMask |= bit; + dlDeferredIntrLinkMask |= bit; + + // + // Disable LTSSM FAULT DOWN, NPG, and NVLW interrupts to avoid interrupt storm. The interrupts + // will be re-enabled in reset and drain + // + report.raw_enable = FLD_SET_DRF(_NVLDL_TOP, _INTR_STALL_EN, _LTSSM_FAULT_DOWN, _DISABLE, report.raw_enable); + NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR_STALL_EN, report.raw_enable); + nvswitch_link_disable_interrupts_ls10(device, link); + if (device->bModeContinuousALI) + { // // Since reset and drain will reset the link, including clearing // pending interrupts, skip the clear write below. There are cases // where link clocks will not be on after reset and drain so there // maybe PRI errors on writing to the register // - { - bRequireResetAndDrain = NV_TRUE; + // CCI will perform reset and drain + if (!cciIsLinkManaged(device, link)) + { + bRequireResetAndDrain = NV_TRUE; + } } nvswitch_clear_flags(&unhandled, bit); } @@ -7792,25 +7812,41 @@ nvswitch_service_nvldl_fatal_link_ls10 NVSWITCH_PRINT(device, ERROR, "%s: Failed to notify PORT_DOWN event\n", __FUNCTION__); } - dlDeferredIntrLinkMask |= bit; + dlDeferredIntrLinkMask |= bit; + // + // Disable LTSSM FAULT UP, NPG, and NVLW link interrupts to avoid interrupt storm. The interrupts + // will be re-enabled in reset and drain + // + report.raw_enable = FLD_SET_DRF(_NVLDL_TOP, _INTR_STALL_EN, _LTSSM_FAULT_UP, _DISABLE, report.raw_enable); + NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR_STALL_EN, report.raw_enable); + nvswitch_link_disable_interrupts_ls10(device, link); + + if (device->bModeContinuousALI) + { // // Since reset and drain will reset the link, including clearing // pending interrupts, skip the clear write below. There are cases // where link clocks will not be on after reset and drain so there // maybe PRI errors on writing to the register // - { - bRequireResetAndDrain = NV_TRUE; + // CCI will perform reset and drain + if (!cciIsLinkManaged(device, link)) + { + bRequireResetAndDrain = NV_TRUE; + } } nvswitch_clear_flags(&unhandled, bit); } if (bRequireResetAndDrain) { - chip_device->deferredLinkErrors[link].data.fatalIntrMask.dl |= dlDeferredIntrLinkMask; - device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link)); - chip_device->deferredLinkErrors[link].state.lastRetrainTime = nvswitch_os_get_platform_time(); + device->hal.nvswitch_reset_and_drain_links(device, NVBIT64(link), NV_FALSE); + } + + chip_device->deferredLinkErrors[link].data.fatalIntrMask.dl |= dlDeferredIntrLinkMask; + if (dlDeferredIntrLinkMask) + { nvswitch_create_deferred_link_state_check_task_ls10(device, nvlipt_instance, link); } @@ -7820,7 +7856,7 @@ nvswitch_service_nvldl_fatal_link_ls10 if (device->link[link].fatal_error_occurred) { NVSWITCH_LINK_WR32(device, link, NVLDL, _NVLDL_TOP, _INTR_STALL_EN, - report.raw_enable ^ pending); + report.raw_enable & ~pending); } if (!bRequireResetAndDrain) diff --git a/src/common/nvswitch/kernel/ls10/link_ls10.c b/src/common/nvswitch/kernel/ls10/link_ls10.c index 900ab70673..9e7baf509e 100644 --- a/src/common/nvswitch/kernel/ls10/link_ls10.c +++ b/src/common/nvswitch/kernel/ls10/link_ls10.c @@ -28,6 +28,7 @@ #include "regkey_nvswitch.h" #include "ls10/ls10.h" #include "nvswitch/ls10/dev_nvldl_ip_addendum.h" +#include "cci/cci_nvswitch.h" #include "nvswitch/ls10/dev_nvldl_ip.h" #include "nvswitch/ls10/dev_nvlipt_lnk_ip.h" @@ -99,53 +100,51 @@ _nvswitch_configure_reserved_throughput_counters } void -nvswitch_init_lpwr_regs_ls10 +nvswitch_program_l1_scratch_reg_ls10 ( - nvlink_link *link + nvswitch_device *device, + NvU32 linkNumber ) { - nvswitch_device *device = link->dev->pDevInfo; - // NVSWITCH_BIOS_NVLINK_CONFIG *bios_config; - NvU32 linkNum = link->linkNumber; - NvU32 tempRegVal, lpEntryThreshold; - NvU8 softwareDesired; - NvBool bLpEnable; + NvU32 scrRegVal; + NvU32 tempRegVal; - if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + // Read L1 register and store initial/VBIOS L1 Threshold Value in Scratch register + tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD); + + scrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _SCRATCH_WARM); + + // Update the scratch register value only if it has not been written to before + if (scrRegVal == NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT) { - return; + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _SCRATCH_WARM, tempRegVal); } +} - if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) +#define BUG_3797211_LS10_VBIOS_VERSION 0x9610410000 + +void +nvswitch_init_lpwr_regs_ls10 +( + nvlink_link *link +) +{ + NvlStatus status; + nvswitch_device *device; + + if (link == NULL) { return; } - // bios_config = nvswitch_get_bios_nvlink_config(device); + device = link->dev->pDevInfo; - // IC Enter Threshold - if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) - { - // - // Do nothing since VBIOS sets the default L1 threshold. - // Refer Bug 3797211 for more info. - // - } - else + status = nvswitch_ctrl_set_link_l1_threshold_ls10(link, device->regkeys.lp_threshold); + if (status != NVL_SUCCESS) { - lpEntryThreshold = device->regkeys.lp_threshold; - tempRegVal = 0; - tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal); - NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal); + NVSWITCH_PRINT(device, ERROR, "%s: Failed to set L1 Threshold\n", + __FUNCTION__); } - - //LP Entry Enable - bLpEnable = NV_TRUE; - softwareDesired = (bLpEnable) ? 0x1 : 0x0; - - tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL); - tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_CTRL, _L1_SOFTWARE_DESIRED, softwareDesired, tempRegVal); - NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL, tempRegVal); } void @@ -573,6 +572,15 @@ nvswitch_corelib_get_tl_link_mode_ls10 link_state = DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, val); + if (cciIsLinkManaged(device, link->linkNumber)) + { + if (link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_RESET) + { + *mode = NVLINK_LINKSTATE_RESET; + return NVL_SUCCESS; + } + } + switch(link_state) { case NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE: @@ -1434,6 +1442,7 @@ nvswitch_load_link_disable_settings_ls10 if (FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, _DISABLE, regVal)) { + NVSWITCH_ASSERT(!cciIsLinkManaged(device, link->linkNumber)); // Set link to invalid and unregister from corelib device->link[link->linkNumber].valid = NV_FALSE; @@ -1544,6 +1553,12 @@ nvswitch_reset_and_train_link_ls10 nvswitch_execute_unilateral_link_shutdown_ls10(link); nvswitch_corelib_clear_link_state_ls10(link); + // If link is CCI managed then return early + if (cciIsLinkManaged(device, link->linkNumber)) + { + return NVL_SUCCESS; + } + // // When a link faults there could be a race between the driver requesting // reset and MINION processing Emergency Shutdown. Minion will notify if @@ -1738,6 +1753,176 @@ nvswitch_request_tl_link_state_ls10 return status; } +// Initialize optical links for pre-training +NvlStatus +nvswitch_cci_initialization_sequence_ls10 +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + NvlStatus status; + nvlink_link link; + nvlink_device dev; + + link.linkNumber = linkNumber; + link.dev = &dev; + link.dev->pDevInfo = device; + + // Perform INITPHASE1 + status = nvswitch_minion_send_command(device, linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s : NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE1 failed on link %d.\n", + __FUNCTION__, linkNumber); + return status; + } + + // SET RX detect + status = nvswitch_minion_send_command(device, linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_TURING_RXDET, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Set RXDET failed for link %d.\n", + __FUNCTION__, linkNumber); + return status; + } + + // Enable Common mode on Tx + status = _nvswitch_init_dl_pll(&link); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to enable common mode for link %d.\n", + __FUNCTION__, linkNumber); + return status; + } + + status = nvswitch_minion_send_command(device, linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE5A, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s : NV_MINION_NVLINK_DL_CMD_COMMAND_INITPHASE5A failed on link %d.\n", + __FUNCTION__, linkNumber); + return status; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_cci_deinitialization_sequence_ls10 +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + NvlStatus status; + nvlink_link link; + nvlink_device dev; + + link.linkNumber = linkNumber; + link.dev = &dev; + link.dev->pDevInfo = device; + + // Perform ABORTRXDET + status = nvswitch_minion_send_command(device, linkNumber, + NV_MINION_NVLINK_DL_CMD_COMMAND_ABORTRXDET, 0); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s : NV_MINION_NVLINK_DL_CMD_COMMAND_ABORTRXDET failed on link %d.\n", + __FUNCTION__, linkNumber); + return status; + } + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_cci_enable_iobist_ls10 +( + nvswitch_device *device, + NvU32 linkNumber, + NvBool bEnable +) +{ + NvU32 val; + + if (bEnable) + { + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIG, _CFGCLKGATEEN, _ENABLE, val); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIG, _PRBSALT, _PAM4, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_4); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_4, _MASK_SKIP_OUT, _INIT, val); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_4, _MASK_COM_OUT, _INIT, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_4, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_2); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_2, _SKIP_SYMBOL_0, _SYMBOL, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_2, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_3); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_3, _SKIP_SYMBOL_1, _SYMBOL, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_3, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_0); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_0, _COM_SYMBOL_0, _SYMBOL, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_0, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_1); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_1, _COM_SYMBOL_1, _SYMBOL, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_1, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_4); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_4, _SEND_DATA_OUT, _INIT, val); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_4, _RESET_WORD_CNT_OUT, _COUNT, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _SKIPCOMINSERTERGEN_4, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIGREG); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIGREG, _TX_BIST_EN_IN, _ENABLE, val); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIGREG, _DISABLE_WIRED_ENABLE_IN, _ENABLE, val); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIGREG, _IO_BIST_MODE_IN, _ENABLE, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIGREG, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIG, _DPG_PRBSSEEDLD, _ENABLE, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG, val); + + nvswitch_os_sleep(5); + + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIG, _DPG_PRBSSEEDLD, _INIT, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIG, _STARTTEST, _ENABLE, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG, val); + } + else + { + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIG, _STARTTEST, _INIT, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIG, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIGREG); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIGREG, _DISABLE_WIRED_ENABLE_IN, _INIT, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIGREG, val); + + val = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIGREG); + val = FLD_SET_DRF(_NVLDL_TXIOBIST, _CONFIGREG, _TX_BIST_EN_IN, _INIT, val); + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TXIOBIST, _CONFIGREG, val); + } + + return NVL_SUCCESS; +} + NvBool nvswitch_does_link_need_termination_enabled_ls10 ( @@ -1759,3 +1944,116 @@ nvswitch_link_termination_setup_ls10 // Not supported for LS10 return -NVL_ERR_NOT_SUPPORTED; } + +NvlStatus +nvswitch_ctrl_get_link_l1_capability_ls10 +( + nvswitch_device *device, + NvU32 linkNum, + NvBool *isL1Capable +) +{ + NvU32 regData; + NvBool bL1Capable; + + regData = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL); + bL1Capable = FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, _PWRM_L1_ENABLE, _ENABLE, regData); + + regData = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_CAP_LOCAL_LINK_AN1); + bL1Capable &= FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_CAP_LOCAL_LINK_AN1, _PWRM_L1_SUPPORT, _SUPPORTED, regData); + + *isL1Capable = bL1Capable; + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_get_link_l1_threshold_ls10 +( + nvswitch_device *device, + NvU32 linkNum, + NvU32 *lpThreshold +) +{ + NvU32 regData; + + regData = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD); + *lpThreshold = DRF_VAL(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, regData); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_set_link_l1_threshold_ls10 +( + nvlink_link *link, + NvU32 lpEntryThreshold +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNum = link->linkNumber; + NvU32 tempRegVal, lpThreshold; + NvU8 softwareDesired; + NvU64 biosVersion; + + if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (nvswitch_lib_get_bios_version(device, &biosVersion) != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, WARN, "%s Get VBIOS version failed.\n", + __FUNCTION__); + biosVersion = 0; + } + + if (device->regkeys.lp_threshold != NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT) + { + lpThreshold = device->regkeys.lp_threshold; + } + else if ((lpEntryThreshold == NVSWITCH_SET_NVLINK_L1_THRESHOLD_DEFAULT) || + (lpEntryThreshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT)) + { + if (biosVersion >= BUG_3797211_LS10_VBIOS_VERSION) + { + // + // Read the default L1 Threshold programmed by the + // VBIOS (version 96.10.41.00.00 and above). + // + lpThreshold = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, + _NVLIPT_LNK, _SCRATCH_WARM); + } + else + { + lpThreshold = 1; + } + } + else + { + lpThreshold = lpEntryThreshold; + } + + tempRegVal = 0; + tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, + _THRESHOLD, lpThreshold, tempRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, + _PWRM_L1_ENTER_THRESHOLD, tempRegVal); + + //LP Entry Enable + softwareDesired = NV_NVLIPT_LNK_PWRM_CTRL_L1_SOFTWARE_DESIRED_L1; + tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, + _NVLIPT_LNK, _PWRM_CTRL); + tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_CTRL, _L1_SOFTWARE_DESIRED, + softwareDesired, tempRegVal); + NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, + _PWRM_CTRL, tempRegVal); + + return NVL_SUCCESS; +} + diff --git a/src/common/nvswitch/kernel/ls10/ls10.c b/src/common/nvswitch/kernel/ls10/ls10.c index 741312ee90..826babb2fc 100644 --- a/src/common/nvswitch/kernel/ls10/ls10.c +++ b/src/common/nvswitch/kernel/ls10/ls10.c @@ -37,11 +37,14 @@ #include "ls10/pmgr_ls10.h" #include "ls10/therm_ls10.h" #include "ls10/smbpbi_ls10.h" +#include "ls10/cci_ls10.h" +#include "cci/cci_nvswitch.h" #include "ls10/multicast_ls10.h" #include "ls10/soe_ls10.h" #include "ls10/gfw_ls10.h" #include "nvswitch/ls10/dev_nvs_top.h" +#include "nvswitch/ls10/ptop_discovery_ip.h" #include "nvswitch/ls10/dev_pri_masterstation_ip.h" #include "nvswitch/ls10/dev_pri_hub_sys_ip.h" #include "nvswitch/ls10/dev_nvlw_ip.h" @@ -1405,10 +1408,12 @@ static NvlStatus _nvswitch_reset_and_drain_links_ls10 ( nvswitch_device *device, - NvU64 link_mask + NvU64 link_mask, + NvBool bForced ) { NvlStatus status = NVL_SUCCESS; + ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device); nvlink_link *link_info = NULL; NvU32 link; NvU32 data32; @@ -1465,6 +1470,11 @@ _nvswitch_reset_and_drain_links_ls10 continue; } + if (nvswitch_is_link_in_reset(device, link_info)) + { + continue; + } + // Unregister links to make them unusable while reset is in progress. nvlink_lib_unregister_link(link_info); @@ -1503,46 +1513,54 @@ _nvswitch_reset_and_drain_links_ls10 // Step 3.0 : // Prior to starting port reset, ensure the links is in emergency shutdown // - bIsLinkInEmergencyShutdown = NV_FALSE; - nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); - do + // Forcibly shutdown links if requested + // + if (bForced) { - bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + nvswitch_execute_unilateral_link_shutdown_ls10(link_info); + } + else + { + bIsLinkInEmergencyShutdown = NV_FALSE; + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1MSEC_IN_NS, &timeout); + do + { + bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; - status = nvswitch_minion_get_dl_status(device, link_info->linkNumber, - NV_NVLSTAT_UC01, 0, &stat_data); + status = nvswitch_minion_get_dl_status(device, link_info->linkNumber, + NV_NVLSTAT_UC01, 0, &stat_data); - if (status != NVL_SUCCESS) - { - continue; - } + if (status != NVL_SUCCESS) + { + continue; + } - link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data); + link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data); - bIsLinkInEmergencyShutdown = (link_state == LINKSTATUS_EMERGENCY_SHUTDOWN) ? - NV_TRUE:NV_FALSE; + bIsLinkInEmergencyShutdown = (link_state == LINKSTATUS_EMERGENCY_SHUTDOWN) ? + NV_TRUE:NV_FALSE; - if (bIsLinkInEmergencyShutdown == NV_TRUE) - { - break; + if (bIsLinkInEmergencyShutdown == NV_TRUE) + { + break; + } } - } - while(bKeepPolling); + while(bKeepPolling); - if (bIsLinkInEmergencyShutdown == NV_FALSE) - { - NVSWITCH_PRINT(device, ERROR, - "%s: link %d failed to enter emergency shutdown\n", - __FUNCTION__, link); - - // Re-register links. - status = nvlink_lib_register_link(device->nvlink_device, link_info); - if (status != NVL_SUCCESS) + if (bIsLinkInEmergencyShutdown == NV_FALSE) { - nvswitch_destroy_link(link_info); + NVSWITCH_PRINT(device, ERROR, + "%s: link %d failed to enter emergency shutdown\n", + __FUNCTION__, link); + + // Re-register links. + status = nvlink_lib_register_link(device->nvlink_device, link_info); + if (status != NVL_SUCCESS) + { + nvswitch_destroy_link(link_info); + } + continue; } - - continue; } nvswitch_corelib_clear_link_state_ls10(link_info); @@ -1585,30 +1603,25 @@ _nvswitch_reset_and_drain_links_ls10 NV_NVLSTAT_MN00, 0, &stat_data) == NVL_SUCCESS) { link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data); - } - else - { - continue; - } - - if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && - (link_intr_subcode == MINION_ALARM_BUSY)) - { - status = nvswitch_request_tl_link_state_ls10(link_info, - NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET, NV_TRUE); - - // - // We retry the shutdown sequence 3 times when we see a MINION_REQUEST_FAIL - // or MINION_ALARM_BUSY - // - retry_count--; - } - else - { - break; + if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) && + (link_intr_subcode == MINION_ALARM_BUSY)) + { + + // + // We retry the reset sequence when we see a MINION_REQUEST_FAIL + // or MINION_ALARM_BUSY + // + } + else + { + break; + } } + + retry_count--; } + } while(retry_count); if (status != NVL_SUCCESS) @@ -1651,6 +1664,9 @@ _nvswitch_reset_and_drain_links_ls10 continue; } + // Initialize select scratch registers to 0x0 + device->hal.nvswitch_init_scratch(device); + // // Step 9.0: Launch ALI training to re-initialize and train the links // nvswitch_launch_ALI_link_training(device, link_info); @@ -1658,6 +1674,8 @@ _nvswitch_reset_and_drain_links_ls10 // Request active, but don't block. FM will come back and check // active link status by blocking on this TLREQ's completion // + // CCI will re-train links + if (!cciIsLinkManaged(device, link)) { status = nvswitch_request_tl_link_state_ls10(link_info, NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE, @@ -1698,6 +1716,8 @@ _nvswitch_reset_and_drain_links_ls10 } FOR_EACH_INDEX_IN_MASK_END; + chip_device->deferredLinkErrors[link].state.lastRetrainTime = nvswitch_os_get_platform_time(); + return NVL_SUCCESS; } @@ -1708,12 +1728,25 @@ NvlStatus nvswitch_reset_and_drain_links_ls10 ( nvswitch_device *device, - NvU64 link_mask + NvU64 link_mask, + NvBool bForced ) { NvlStatus status = NVL_SUCCESS; - status = _nvswitch_reset_and_drain_links_ls10(device, link_mask); + NvU32 link; + + // CCI will call reset and drain separately + FOR_EACH_INDEX_IN_MASK(64, link, link_mask) + { + if (cciIsLinkManaged(device, link)) + { + link_mask = link_mask & ~NVBIT64(link); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + status = _nvswitch_reset_and_drain_links_ls10(device, link_mask, bForced); if (status != NVL_SUCCESS) { return status; @@ -5163,6 +5196,10 @@ nvswitch_launch_ALI_ls10 continue; } + if (cciIsLinkManaged(device, i)) + { + continue; + } nvswitch_launch_ALI_link_training(device, link, NV_FALSE); } FOR_EACH_INDEX_IN_MASK_END; @@ -5512,7 +5549,7 @@ nvswitch_ctrl_inband_send_data_ls10 NvlStatus status; nvswitch_inband_send_data inBandData; - // ct_assert(NVLINK_INBAND_MAX_MSG_SIZE >= NVSWITCH_INBAND_DATA_SIZE); + ct_assert(NVLINK_INBAND_MAX_MSG_SIZE == NVSWITCH_INBAND_DATA_SIZE); if (p->dataSize == 0 || p->dataSize > NVSWITCH_INBAND_DATA_SIZE) { @@ -5858,6 +5895,514 @@ nvswitch_ctrl_get_nvlink_error_threshold_ls10 return NVL_SUCCESS; } +NvlStatus +nvswitch_get_board_id_ls10 +( + nvswitch_device *device, + NvU16 *pBoardId +) +{ + NvlStatus ret; + NvU32 biosOemVersionBytes; + + if (pBoardId == NULL) + { + return -NVL_BAD_ARGS; + } + + // Check if bios valid + ret = nvswitch_lib_get_bios_version(device, NULL); + if (ret != NVL_SUCCESS) + { + return ret; + } + + biosOemVersionBytes = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW_SW, + _OEM_BIOS_VERSION); + *pBoardId = DRF_VAL(_NVLSAW_SW, _OEM_BIOS_VERSION, _BOARD_ID, biosOemVersionBytes); + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_check_io_sanity_ls10 +( + nvswitch_device *device +) +{ + NvBool keepPolling; + NVSWITCH_TIMEOUT timeout; + NvU32 val; + NvBool error = NV_FALSE; + NvU32 sxid; + const char *sxid_desc = NULL; + + // + // NOTE: MMIO discovery has not been performed so only constant BAR0 offset + // addressing can be performed. + // + + // BAR0 offset 0 should always contain valid data -- unless it doesn't + val = NVSWITCH_OFF_RD32(device, 0); + if (val == 0) + { + error = NV_TRUE; + sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE; + sxid_desc = "Firmware recovery mode"; + } + else if ((val == 0xFFFFFFFF) || ((val & 0xFFFF0000) == 0xBADF0000)) + { + error = NV_TRUE; + sxid = NVSWITCH_ERR_HW_HOST_IO_FAILURE; + sxid_desc = "IO failure"; + } + else if (!IS_FMODEL(device)) + { + // check if FSP successfully started + nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout); + do + { + keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE; + + val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); + if (FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val)) + { + break; + } + + nvswitch_os_sleep(1); + } + while (keepPolling); + if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val)) + { + error = NV_TRUE; + sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE; + sxid_desc = "Firmware initialization failure"; + } + } + + if (error) + { + NVSWITCH_RAW_ERROR_LOG_TYPE report = { 0, { 0 } }; + NVSWITCH_RAW_ERROR_LOG_TYPE report_saw = {0, { 0 }}; + NvU32 report_idx = 0; + NvU32 i; + + val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS); + report.data[report_idx++] = val; + NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n", + __FUNCTION__, val); + + for (i = 0; i <= 15; i++) + { + val = NVSWITCH_OFF_RD32(device, + NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 + NV_NVLSAW_SW_SCRATCH(i)); + report_saw.data[i] = val; + NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n", + __FUNCTION__, i, val); + } + + for (i = 0; i < NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1; i++) + { + val = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i)); + report.data[report_idx++] = val; + NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n", + __FUNCTION__, i, val); + } + + // Include useful scratch information for triage + NVSWITCH_PRINT_SXID_NO_BBX(device, sxid, + "Fatal, %s (0x%x/0x%x, 0x%x, 0x%x, 0x%x/0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", sxid_desc, + report.data[0], report.data[1], report.data[2], report.data[3], report.data[4], + report_saw.data[0], report_saw.data[1], report_saw.data[12], report_saw.data[14], report_saw.data[15]); + + return -NVL_INITIALIZATION_TOTAL_FAILURE; + } + + return NVL_SUCCESS; +} + +/* + * @brief: This function returns the current value of the SOE heartbeat gpio + * @params[in] device reference to current nvswitch device + * @params[in] p NVSWITCH_GET_SOE_HEARTBEAT_PARAMS + */ +NvlStatus +nvswitch_ctrl_get_soe_heartbeat_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p +) +{ + NvU32 gpioVal = 0; + NvU64 hi = 0; + NvU64 lo = 0; + NvU64 test = 0; + + if (!nvswitch_is_cci_supported(device)) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + // Read status of heartbeat gpio + gpioVal = NVSWITCH_REG_RD32(device, _GPIO, _OUTPUT_CNTL(3)); + + // Record timestamp of gpio read from PTIMER + do + { + hi = NVSWITCH_ENG_RD32(device, PTIMER, , 0, _PTIMER, _TIME_1); + lo = NVSWITCH_ENG_RD32(device, PTIMER, , 0, _PTIMER, _TIME_0); + test = NVSWITCH_ENG_RD32(device, PTIMER, , 0, _PTIMER, _TIME_1); + } + while (hi != test); + p->timestampNs = (hi << 32) | lo; + + if (FLD_TEST_DRF(_GPIO, _OUTPUT_CNTL, _IO_OUTPUT, _1, gpioVal)) + { + p->gpioVal = 1; + } + else if (FLD_TEST_DRF(_GPIO, _OUTPUT_CNTL, _IO_OUTPUT, _0, gpioVal)) + { + p->gpioVal = 0; + } + + return NVL_SUCCESS; +} + +static NvlStatus +nvswitch_cci_reset_and_drain_links_ls10 +( + nvswitch_device *device, + NvU64 link_mask, + NvBool bForced +) +{ + NvU32 link; + + FOR_EACH_INDEX_IN_MASK(64, link, link_mask) + { + if (!cciIsLinkManaged(device, link)) + { + link_mask = link_mask & ~NVBIT64(link); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return _nvswitch_reset_and_drain_links_ls10(device, link_mask, bForced); +} + +/* + * @brief Set the next LED state + * The HW will reflect this state on the next iteration of link + * state update. + */ +static void +_nvswitch_set_next_led_state_ls10 +( + nvswitch_device *device, + NvU8 nextLedState +) +{ + device->next_led_state = nextLedState; +} + +/* + * Returns the CPLD register value assigned to a particular LED state + * confluence page ID: 1011518154 + */ +static NvU8 +_nvswitch_get_led_state_regval_ls10 +( + nvswitch_device *device, + NvU8 ledState +) +{ + switch (ledState) + { + case ACCESS_LINK_LED_STATE_OFF: + { + return CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_OFF; + } + case ACCESS_LINK_LED_STATE_UP_WARM: + { + return CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_GREEN; + } + case ACCESS_LINK_LED_STATE_INITIALIZE: + { + return CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_3HZ_AMBER; + } + case ACCESS_LINK_LED_STATE_UP_ACTIVE: + { + return CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_3HZ_GREEN; + } + case ACCESS_LINK_LED_STATE_FAULT: + { + return CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_6HZ_AMBER; + } + default: + { + NVSWITCH_ASSERT(0); + return CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED_REG_STATE_OFF; + } + } +} + +/* + * @brief Set HW LED state using CPLD write + * + */ +static NvlStatus +_nvswitch_set_led_state_ls10 +( + nvswitch_device *device +) +{ + NvlStatus retval; + NvU8 ledState; + NvU8 nextLedState; + NvU8 regVal = 0; + + nextLedState = device->next_led_state; + ledState = REF_VAL(ACCESS_LINK_LED_STATE, nextLedState); + + regVal = FLD_SET_REF_NUM(CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED, + _nvswitch_get_led_state_regval_ls10(device, ledState), + regVal); + + // Set state for LED + retval = nvswitch_cci_ports_cpld_write(device, CPLD_MACHXO3_ACCESS_LINK_LED_CTL, regVal); + if (retval != NVL_SUCCESS) + { + return retval; + } + + // save HW state + device->current_led_state = REF_NUM(ACCESS_LINK_LED_STATE, ledState); + + return NVL_SUCCESS; +} + +static NvBool +_nvswitch_check_for_link_traffic +( + nvswitch_device *device, + NvU64 linkMask +) +{ + NVSWITCH_GET_THROUGHPUT_COUNTERS_PARAMS *pCounterParams = NULL; + NvU64 *pCounterValues; + NvU64 tpCounterPreviousSum; + NvU64 tpCounterCurrentSum; + NvBool bTraffic = NV_FALSE; + NvU8 linkNum; + + pCounterParams = nvswitch_os_malloc(sizeof(*pCounterParams)); + if (pCounterParams == NULL) + goto out; + + pCounterParams->counterMask = NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_TX | + NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_RX; + pCounterParams->linkMask = linkMask; + if (nvswitch_ctrl_get_throughput_counters(device, + pCounterParams) != NVL_SUCCESS) + { + goto out; + } + + // Sum TX/RX traffic for each link + FOR_EACH_INDEX_IN_MASK(64, linkNum, linkMask) + { + pCounterValues = pCounterParams->counters[linkNum].values; + + tpCounterPreviousSum = device->tp_counter_previous_sum[linkNum]; + + // Sum taken to save space as it is unlikely to overflow before system is reset + tpCounterCurrentSum = pCounterValues[NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_TX] + + pCounterValues[NVSWITCH_THROUGHPUT_COUNTERS_TYPE_DATA_RX]; + + device->tp_counter_previous_sum[linkNum] = tpCounterCurrentSum; + + if (tpCounterCurrentSum > tpCounterPreviousSum) + { + bTraffic = NV_TRUE; + } + } + FOR_EACH_INDEX_IN_MASK_END; + +out: + nvswitch_os_free(pCounterParams); + return bTraffic; +} + +static NvU8 +_nvswitch_resolve_led_state_ls10 +( + nvswitch_device *device, + NvU8 ledState0, + NvU8 ledState1 +) +{ + // Used to resolve link state discrepancies between partner links + ct_assert(ACCESS_LINK_LED_STATE_FAULT < ACCESS_LINK_LED_STATE_OFF); + ct_assert(ACCESS_LINK_LED_STATE_OFF < ACCESS_LINK_LED_STATE_INITIALIZE); + ct_assert(ACCESS_LINK_LED_STATE_INITIALIZE < ACCESS_LINK_LED_STATE_UP_WARM); + + return (ledState0 < ledState1 ? ledState0 : ledState1); +} + +static NvU8 +_nvswitch_get_next_led_state_link_ls10 +( + nvswitch_device *device, + NvU8 currentLedState, + NvU8 linkNum +) +{ + nvlink_link *link; + NvU64 linkState; + + link = nvswitch_get_link(device, linkNum); + + if ((link == NULL) || + (device->hal.nvswitch_corelib_get_dl_link_mode(link, &linkState) != NVL_SUCCESS)) + { + return ACCESS_LINK_LED_STATE_OFF; + } + + switch (linkState) + { + case NVLINK_LINKSTATE_OFF: + { + return ACCESS_LINK_LED_STATE_OFF; + } + case NVLINK_LINKSTATE_HS: + case NVLINK_LINKSTATE_RECOVERY: + case NVLINK_LINKSTATE_SLEEP: + { + return ACCESS_LINK_LED_STATE_UP_WARM; + } + case NVLINK_LINKSTATE_FAULT: + { + return ACCESS_LINK_LED_STATE_FAULT; + } + default: + { + if (currentLedState == ACCESS_LINK_LED_STATE_INITIALIZE) + { + return ACCESS_LINK_LED_STATE_INITIALIZE; + } + return ACCESS_LINK_LED_STATE_OFF; + } + } +} + +static NvU8 +_nvswitch_get_next_led_state_links_ls10 +( + nvswitch_device *device, + NvU8 currentLedState, + NvU64 linkMask +) +{ + NvU8 linkNum; + NvU8 ledState; + NvU8 nextLedState; + + nextLedState = ACCESS_LINK_NUM_LED_STATES; + + NVSWITCH_ASSERT(linkMask != 0); + FOR_EACH_INDEX_IN_MASK(64, linkNum, linkMask) + { + ledState = _nvswitch_get_next_led_state_link_ls10(device, currentLedState, linkNum); + nextLedState = _nvswitch_resolve_led_state_ls10(device, nextLedState, ledState); + } + FOR_EACH_INDEX_IN_MASK_END; + + if (nextLedState == ACCESS_LINK_LED_STATE_UP_WARM) + { + // Only tells us that one of the links has activity + if (_nvswitch_check_for_link_traffic(device, linkMask)) + { + nextLedState = ACCESS_LINK_LED_STATE_UP_ACTIVE; + } + } + + return nextLedState; +} + +static NvU8 +_nvswitch_get_next_led_state_ls10 +( + nvswitch_device *device +) +{ + NvU8 linkNum; + NvU8 ledNextState = 0; + NvU8 currentLedState; + NvU64 enabledLinkMask; + + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + + FOR_EACH_INDEX_IN_MASK(64, linkNum, enabledLinkMask) + { + if (cciIsLinkManaged(device, linkNum)) + { + enabledLinkMask = enabledLinkMask & ~NVBIT64(linkNum); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + currentLedState = device->current_led_state; + currentLedState = REF_VAL(ACCESS_LINK_LED_STATE, currentLedState); + + ledNextState = FLD_SET_REF_NUM(ACCESS_LINK_LED_STATE, + _nvswitch_get_next_led_state_links_ls10(device, + currentLedState, + enabledLinkMask), + ledNextState); + + return ledNextState; +} + +void +nvswitch_update_link_state_led_ls10 +( + nvswitch_device *device +) +{ + NvU8 currentLedState; + NvU8 nextLedState; + + currentLedState = device->current_led_state; + + currentLedState = REF_VAL(ACCESS_LINK_LED_STATE, currentLedState); + nextLedState = _nvswitch_get_next_led_state_ls10(device); + + // This is the next state that the LED will be set to + _nvswitch_set_next_led_state_ls10(device, nextLedState); + + // Only update HW if required + if (currentLedState != nextLedState) + { + _nvswitch_set_led_state_ls10(device); + } +} + +void +nvswitch_led_shutdown_ls10 +( + nvswitch_device *device +) +{ + NvU8 ledState = 0; + ledState = FLD_SET_REF_NUM(ACCESS_LINK_LED_STATE, + ACCESS_LINK_LED_STATE_OFF, ledState); + + // This is the next state that the LED will be set to + _nvswitch_set_next_led_state_ls10(device, ledState); + _nvswitch_set_led_state_ls10(device); +} + NvlStatus nvswitch_read_vbios_link_entries_ls10 ( @@ -6009,6 +6554,27 @@ nvswitch_ctrl_get_inforom_version_ls10 return NVL_SUCCESS; } +/* + * @Brief : Initializes an NvSwitch hardware state + * + * @Description : + * + * @param[in] device a reference to the device to initialize + * + * @returns NVL_SUCCESS if the action succeeded + * -NVL_BAD_ARGS if bad arguments provided + * -NVL_PCI_ERROR if bar info unable to be retrieved + */ +NvlStatus +nvswitch_initialize_device_state_ls10 +( + nvswitch_device *device +) +{ + device->bModeContinuousALI = NV_TRUE; + return nvswitch_initialize_device_state_lr10(device); +} + // // This function auto creates the ls10 HAL connectivity from the NVSWITCH_INIT_HAL // macro in haldef_nvswitch.h diff --git a/src/common/nvswitch/kernel/ls10/soe_ls10.c b/src/common/nvswitch/kernel/ls10/soe_ls10.c index 65c4c861fa..efde1de439 100644 --- a/src/common/nvswitch/kernel/ls10/soe_ls10.c +++ b/src/common/nvswitch/kernel/ls10/soe_ls10.c @@ -512,10 +512,9 @@ nvswitch_soe_disable_nport_fatal_interrupts_ls10 NVSWITCH_TIMEOUT timeout; RM_SOE_CORE_CMD_NPORT_FATAL_INTR *pNportIntrDisable; NVSWITCH_GET_BIOS_INFO_PARAMS p = { 0 }; - NvlStatus stat; - stat = device->hal.nvswitch_ctrl_get_bios_info(device, &p); - if ((stat != NVL_SUCCESS) || ((p.version & SOE_VBIOS_VERSION_MASK) < + status = device->hal.nvswitch_ctrl_get_bios_info(device, &p); + if ((status != NVL_SUCCESS) || ((p.version & SOE_VBIOS_VERSION_MASK) < SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR)) { NVSWITCH_PRINT(device, ERROR, @@ -696,6 +695,40 @@ nvswitch_soe_register_event_callbacks_ls10 return -NVL_ERR_INVALID_STATE; } + // Register CCI callback funcion + status = flcnQueueEventRegister( + device, pFlcn, + RM_SOE_UNIT_CCI, + NULL, + nvswitch_cci_soe_callback_ls10, + NULL, + &pSoe->cciEvtDesc); + + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to register CCI event handler.\n", + __FUNCTION__); + return -NVL_ERR_INVALID_STATE; + } + + // Register Heartbeat callback funcion + status = flcnQueueEventRegister( + device, pFlcn, + RM_SOE_UNIT_HEARTBEAT, + NULL, + nvswitch_heartbeat_soe_callback_ls10, + NULL, + &pSoe->heartbeatEvtDesc); + + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to register Heartbeat event handler.\n", + __FUNCTION__); + return -NVL_ERR_INVALID_STATE; + } + return NVL_SUCCESS; } @@ -718,6 +751,25 @@ nvswitch_soe_unregister_events_ls10 "%s: Failed to un-register thermal event handler.\n", __FUNCTION__); } + // un-register thermal callback funcion + status = flcnQueueEventUnregister(device, pFlcn, + pSoe->cciEvtDesc); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to un-register cci event handler.\n", + __FUNCTION__); + } + + // un-register heartbeat callback funcion + status = flcnQueueEventUnregister(device, pFlcn, + pSoe->heartbeatEvtDesc); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to un-register heartbeat event handler.\n", + __FUNCTION__); + } } /*! diff --git a/src/common/nvswitch/kernel/nvswitch.c b/src/common/nvswitch/kernel/nvswitch.c index e1cb318e8d..724c634da2 100644 --- a/src/common/nvswitch/kernel/nvswitch.c +++ b/src/common/nvswitch/kernel/nvswitch.c @@ -33,6 +33,7 @@ #include "soe/soeififr.h" #include "nvVer.h" #include "nvlink_inband_msg.h" +#include "cci/cci_nvswitch.h" static NvlStatus _nvswitch_ctrl_inband_flush_data(nvswitch_device *device, NVSWITCH_INBAND_FLUSH_DATA_PARAMS *p); @@ -312,6 +313,31 @@ _nvswitch_corelib_write_discovery_token return NVL_SUCCESS; } +static NV_API_CALL NvlStatus +_nvswitch_corelib_read_discovery_token +( + nvlink_link *link, + NvU64 *token +) +{ + if (link->version >= NVLINK_DEVICE_VERSION_40) + { + return NVL_SUCCESS; + } + return NVL_SUCCESS; +} + +static NV_API_CALL NvlStatus +_nvswitch_corelib_get_cci_link_mode +( + nvlink_link *link, + NvU64 *mode +) +{ + nvswitch_device *device = link->dev->pDevInfo; + return device->hal.nvswitch_cci_get_cci_link_mode(device, link->linkNumber, mode); +} + static NV_API_CALL NvlStatus _nvswitch_corelib_ali_training ( @@ -349,7 +375,9 @@ nvswitch_get_link_handlers nvswitch_link_handlers->training_complete = _nvswitch_corelib_training_complete; nvswitch_link_handlers->get_uphy_load = _nvswitch_corelib_get_uphy_load; nvswitch_link_handlers->write_discovery_token = _nvswitch_corelib_write_discovery_token; + nvswitch_link_handlers->read_discovery_token = _nvswitch_corelib_read_discovery_token; nvswitch_link_handlers->ali_training = _nvswitch_corelib_ali_training; + nvswitch_link_handlers->get_cci_link_mode = _nvswitch_corelib_get_cci_link_mode; } #define NVSWITCH_INIT_REGKEY(_private, _regkey, _string, _default_val) \ @@ -401,6 +429,21 @@ _nvswitch_init_device_regkeys NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET, NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET_DISABLE); + NVSWITCH_INIT_REGKEY(_PUBLIC, cci_control, + NV_SWITCH_REGKEY_CCI_CONTROL, + NV_SWITCH_REGKEY_CCI_CONTROL_DEFAULT); + NVSWITCH_INIT_REGKEY(_PRIVATE, cci_link_train_disable_mask, + NV_SWITCH_REGKEY_CCI_DISABLE_LINK_TRAIN_MASK, + NV_SWITCH_REGKEY_CCI_DISABLE_LINK_TRAIN_MASK_DEFAULT); + NVSWITCH_INIT_REGKEY(_PRIVATE, cci_link_train_disable_mask2, + NV_SWITCH_REGKEY_CCI_DISABLE_LINK_TRAIN_MASK2, + NV_SWITCH_REGKEY_CCI_DISABLE_LINK_TRAIN_MASK2_DEFAULT); + NVSWITCH_INIT_REGKEY(_PUBLIC, cci_max_onboard_attempts, + NV_SWITCH_REGKEY_CCI_MAX_ONBOARD_ATTEMPTS, + NV_SWITCH_REGKEY_CCI_MAX_ONBOARD_ATTEMPTS_DEFAULT); + NVSWITCH_INIT_REGKEY(_PUBLIC, cci_error_log_enable, + NV_SWITCH_REGKEY_CCI_ERROR_LOG_ENABLE, + NV_SWITCH_REGKEY_CCI_ERROR_LOG_ENABLE_DEFAULT); // // Debug use regkeys // Not available on release build kernel drivers @@ -453,7 +496,7 @@ _nvswitch_init_device_regkeys NV_SWITCH_REGKEY_SKIP_BUFFER_READY, 0); - NVSWITCH_INIT_REGKEY(_PRIVATE, enable_pm, + NVSWITCH_INIT_REGKEY(_PUBLIC, enable_pm, NV_SWITCH_REGKEY_ENABLE_PM, NV_SWITCH_REGKEY_ENABLE_PM_YES); @@ -762,6 +805,192 @@ nvswitch_soe_init_l2_state device->hal.nvswitch_soe_init_l2_state(device); } +void +nvswitch_fsp_update_cmdq_head_tail +( + nvswitch_device *device, + NvU32 queueHead, + NvU32 queueTail +) +{ + return device->hal.nvswitch_fsp_update_cmdq_head_tail(device, queueHead, queueTail); +} + +void +nvswitch_fsp_get_cmdq_head_tail +( + nvswitch_device *device, + NvU32 *pQueueHead, + NvU32 *pQueueTail +) +{ + return device->hal.nvswitch_fsp_get_cmdq_head_tail(device, pQueueHead, pQueueTail); +} + +void +nvswitch_fsp_update_msgq_head_tail +( + nvswitch_device *device, + NvU32 msgqHead, + NvU32 msgqTail +) +{ + return device->hal.nvswitch_fsp_update_msgq_head_tail(device, msgqHead, msgqTail); +} + +void +nvswitch_fsp_get_msgq_head_tail +( + nvswitch_device *device, + NvU32 *pMsgqHead, + NvU32 *pMsgqTail +) +{ + return device->hal.nvswitch_fsp_get_msgq_head_tail(device, pMsgqHead, pMsgqTail); +} + +NvU32 +nvswitch_fsp_get_channel_size +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_fsp_get_channel_size(device); +} + +NvU8 +nvswitch_fsp_nvdm_to_seid +( + nvswitch_device *device, + NvU8 nvdmType +) +{ + return device->hal.nvswitch_fsp_nvdm_to_seid(device, nvdmType); +} + +NvU32 +nvswitch_fsp_create_mctp_header +( + nvswitch_device *device, + NvU8 som, + NvU8 eom, + NvU8 seid, + NvU8 seq +) +{ + return device->hal.nvswitch_fsp_create_mctp_header(device, som, eom, seid, seq); +} + +NvU32 +nvswitch_fsp_create_nvdm_header +( + nvswitch_device *device, + NvU32 nvdmType +) +{ + return device->hal.nvswitch_fsp_create_nvdm_header(device, nvdmType); +} + +NvlStatus +nvswitch_fsp_get_packet_info +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size, + NvU8 *pPacketState, + NvU8 *pTag +) +{ + return device->hal.nvswitch_fsp_get_packet_info(device, pBuffer, size, pPacketState, pTag); +} + +NvlStatus +nvswitch_fsp_validate_mctp_payload_header +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return device->hal.nvswitch_fsp_validate_mctp_payload_header(device, pBuffer, size); +} + +NvlStatus +nvswitch_fsp_process_nvdm_msg +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return device->hal.nvswitch_fsp_process_nvdm_msg(device, pBuffer, size); +} + +NvlStatus +nvswitch_fsp_process_cmd_response +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return device->hal.nvswitch_fsp_process_cmd_response(device, pBuffer, size); +} + +NvlStatus +nvswitch_fsp_config_ememc +( + nvswitch_device *device, + NvU32 offset, + NvBool bAincw, + NvBool bAincr +) +{ + return device->hal.nvswitch_fsp_config_ememc(device, offset, bAincw, bAincr); +} + +NvlStatus +nvswitch_fsp_write_to_emem +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return device->hal.nvswitch_fsp_write_to_emem(device, pBuffer, size); +} + +NvlStatus +nvswitch_fsp_read_from_emem +( + nvswitch_device *device, + NvU8 *pBuffer, + NvU32 size +) +{ + return device->hal.nvswitch_fsp_read_from_emem(device, pBuffer, size); +} + +NvlStatus +nvswitch_fsp_error_code_to_nvlstatus_map +( + nvswitch_device *device, + NvU32 errorCode +) +{ + return device->hal.nvswitch_fsp_error_code_to_nvlstatus_map(device, errorCode); +} + +static NvlStatus +_nvswitch_ctrl_fsprpc_get_caps +( + nvswitch_device *device, + NVSWITCH_FSPRPC_GET_CAPS_PARAMS *params +) +{ + return device->hal.nvswitch_fsprpc_get_caps(device, params); +} + static NvlStatus _nvswitch_construct_soe ( @@ -824,6 +1053,75 @@ _nvswitch_destruct_soe device->pSoe = NULL; } +static NvlStatus +_nvswitch_construct_cci +( + nvswitch_device *device +) +{ + CCI *pCci = NULL; + NvlStatus retval; + + device->pCci = pCci = cciAllocNew(); + if (pCci == NULL) + { + NVSWITCH_PRINT(device, ERROR, "CCI allocation failed.\n"); + return -NVL_NO_MEM; + } + + retval = cciInit(device, pCci, device->nvlink_device->pciInfo.pciDeviceId); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "CCI init failed.\n"); + goto cci_init_failed; + } + + return NVL_SUCCESS; + +cci_init_failed: + nvswitch_os_free(pCci); + device->pCci = NULL; + + return retval; +} + +static void +_nvswitch_destruct_cci +( + nvswitch_device *device +) +{ + CCI *pCci = device->pCci; + + if (pCci == NULL) + { + return; + } + + cciDestroy(device, pCci); + + nvswitch_os_free(pCci); + device->pCci = NULL; +} + +static void +_nvswitch_update_link_state_led +( + nvswitch_device *device +) +{ + device->hal.nvswitch_update_link_state_led(device); +} + +static void +_nvswitch_led_shutdown +( + nvswitch_device *device +) +{ + device->hal.nvswitch_led_shutdown(device); +} + static NvlStatus _nvswitch_initialize_device_state ( @@ -1461,6 +1759,19 @@ nvswitch_lib_initialize_device { NVSWITCH_PRINT(device, INFO, "SOE is not supported, skipping construct\n"); } + if (nvswitch_is_cci_supported(device)) + { + retval = _nvswitch_construct_cci(device); + if (retval != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "Failed to construct CCI: %d\n", retval); + goto nvswitch_initialize_cci_fail; + } + } + else + { + NVSWITCH_PRINT(device, INFO, "CCI is not supported, skipping construct\n"); + } _nvswitch_set_dma_mask(device); @@ -1577,10 +1888,17 @@ nvswitch_lib_initialize_device nvswitch_reset_persistent_link_hw_state(device, link_num); + // + // During Nvswitch initialization, the default L1 thresholds are programmed by the + // BIOS from the BIOS tables. Save these L1 Threshold Values in scratch registers + // for use when resetting the thresholds to default. + // + nvswitch_program_l1_scratch_reg(device, link_num); + // // WAR : Initializing the L1 threshold registers at this point as a WAR for - // Bug 3963639 where is it was discussed that the L1 threshold register should have - // value the default value for all available links and not just for active links. + // Bug 3963639 where it was discussed that the L1 threshold register should have + // the default value for all available links and not just for active links. // nvswitch_init_lpwr_regs(link); } @@ -1667,6 +1985,8 @@ nvswitch_lib_initialize_device nvswitch_destroy_inforom(device); nvswitch_initialize_device_state_fail: + _nvswitch_destruct_cci(device); +nvswitch_initialize_cci_fail: _nvswitch_destruct_soe(device); nvswitch_tasks_destroy(device); @@ -1701,6 +2021,7 @@ nvswitch_lib_post_init_device NvU32 link_num; NvU64 mode; nvlink_link *link; + NvU64 enabledLinkMaskNonCci; if (!NVSWITCH_IS_DEVICE_INITIALIZED(device)) { @@ -1712,7 +2033,7 @@ nvswitch_lib_post_init_device { return retval; } - + if (nvswitch_is_bios_supported(device)) { retval = nvswitch_bios_get_image(device); @@ -1734,6 +2055,39 @@ nvswitch_lib_post_init_device __FUNCTION__); } + if (nvswitch_is_cci_supported(device)) + { + retval = cciLoad(device); + if (NVL_SUCCESS != retval) + { + NVSWITCH_PRINT(device, ERROR, "%s: Init CCI failed\n", + __FUNCTION__); + return retval; + } + + enabledLinkMaskNonCci = nvswitch_get_enabled_link_mask(device); + + FOR_EACH_INDEX_IN_MASK(64, link_num, enabledLinkMaskNonCci) + { + if (cciIsLinkManaged(device, link_num)) + { + enabledLinkMaskNonCci = enabledLinkMaskNonCci & ~NVBIT64(link_num); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + if (enabledLinkMaskNonCci != 0) + { + nvswitch_task_create(device, &_nvswitch_update_link_state_led, + NVSWITCH_INTERVAL_1SEC_IN_NS, 0); + } + } + else + { + NVSWITCH_PRINT(device, INFO, "%s: Skipping CCI init.\n", + __FUNCTION__); + } + retval = _nvswitch_setup_system_registers(device); if (retval != NVL_SUCCESS) { @@ -1761,6 +2115,11 @@ nvswitch_lib_post_init_device continue; } + // CCI links are trained and managed by SOE, skip any driver based training + if (cciIsLinkManaged(device, link_num)) + { + continue; + } status = nvlink_lib_get_link(device->nvlink_device, link_num, &link); if (status != NVL_SUCCESS) { @@ -2210,6 +2569,9 @@ nvswitch_lib_shutdown_device p.linkMask = nvswitch_get_enabled_link_mask(device); _nvswitch_ctrl_inband_flush_data(device, &p); + _nvswitch_destruct_cci(device); + _nvswitch_led_shutdown(device); + _nvswitch_unregister_links(device); nvswitch_destroy_error_log(device, &device->log_FATAL_ERRORS); @@ -3335,7 +3697,7 @@ _nvswitch_ctrl_reset_and_drain_links NVSWITCH_RESET_AND_DRAIN_LINKS_PARAMS *params ) { - return device->hal.nvswitch_reset_and_drain_links(device, params->linkMask); + return device->hal.nvswitch_reset_and_drain_links(device, params->linkMask, NV_FALSE); } static NvlStatus @@ -3665,49 +4027,254 @@ nvswitch_link_termination_setup } static NvlStatus -_nvswitch_ctrl_get_inforom_nvlink_max_correctable_error_rate +_nvswitch_ctrl_cci_cmis_presence ( nvswitch_device *device, - NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params + NVSWITCH_CCI_CMIS_PRESENCE_PARAMS *pParams ) { - return nvswitch_inforom_nvlink_get_max_correctable_error_rate(device, params); -} + nvswitch_os_memset(pParams, 0, sizeof(NVSWITCH_CCI_CMIS_PRESENCE_PARAMS)); + if (device->pCci != NULL) + { + (void)cciGetXcvrMask(device, &pParams->cagesMask, &pParams->modulesMask); + } -static NvlStatus -_nvswitch_ctrl_get_inforom_nvlink_errors -( - nvswitch_device *device, - NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params -) -{ - return nvswitch_inforom_nvlink_get_errors(device, params); + // IOCTL will always succeed + return NVL_SUCCESS; } static NvlStatus -_nvswitch_ctrl_get_inforom_ecc_errors +_nvswitch_ctrl_cci_nvlink_mappings ( nvswitch_device *device, - NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *params + NVSWITCH_CCI_CMIS_NVLINK_MAPPING_PARAMS *pParams ) { - return nvswitch_inforom_ecc_get_errors(device, params); + if (device->pCci == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + return cciGetCageMapping(device, pParams->cageIndex, &pParams->linkMask, &pParams->encodedValue); } static NvlStatus -_nvswitch_ctrl_get_inforom_bbx_sxid +_nvswitch_ctrl_cci_memory_access_read ( nvswitch_device *device, - NVSWITCH_GET_SXIDS_PARAMS *params + NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ_PARAMS *pParams ) { - return nvswitch_inforom_bbx_get_sxid(device, params); -} + NvlStatus retVal; -static NvlStatus -_nvswitch_ctrl_get_inforom_bbx_sys_info -( - nvswitch_device *device, + if (device->pCci == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (!cciCmisAccessTryLock(device, pParams->cageIndex)) + { + return -NVL_ERR_STATE_IN_USE; + } + + retVal = cciCmisRead(device, pParams->cageIndex, pParams->bank, + pParams->page, pParams->address, pParams->count, + pParams->data); + + if (!pParams->bSequenceLock) + { + cciCmisAccessReleaseLock(device, pParams->cageIndex); + } + + return retVal; +} + +static NvlStatus +_nvswitch_ctrl_cci_memory_access_write +( + nvswitch_device *device, + NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE_PARAMS *pParams +) +{ + NvlStatus retVal; + + if (device->pCci == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (!cciCmisAccessTryLock(device, pParams->cageIndex)) + { + return -NVL_ERR_STATE_IN_USE; + } + + retVal = cciCmisWrite(device, pParams->cageIndex, pParams->bank, + pParams->page, pParams->address, pParams->count, + pParams->data); + + if (!pParams->bSequenceLock) + { + cciCmisAccessReleaseLock(device, pParams->cageIndex); + } + + return retVal; +} + +static NvlStatus +_nvswitch_ctrl_cci_cage_bezel_marking +( + nvswitch_device *device, + NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING_PARAMS *pParams +) +{ + if (device->pCci == NULL) + { + NVSWITCH_PRINT(device, ERROR, + "%s: CCI not supported\n", + __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + return cciCmisCageBezelMarking(device, pParams->cageIndex, pParams->bezelMarking); +} + +static NvlStatus +_nvswitch_ctrl_get_soe_heartbeat +( + nvswitch_device *device, + NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *pParams +) +{ + return device->hal.nvswitch_ctrl_get_soe_heartbeat(device, pParams); +} + +static NvlStatus +_nvswitch_ctrl_set_continuous_ali +( + nvswitch_device *device, + NVSWITCH_SET_CONTINUOUS_ALI_PARAMS *pParams +) +{ + device->bModeContinuousALI = pParams->bEnable; + NVSWITCH_PRINT(device, INFO, + "%s: Continuous ALI 0x%x\n", + __FUNCTION__, device->bModeContinuousALI); + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_ctrl_request_ali +( + nvswitch_device *device, + NVSWITCH_REQUEST_ALI_PARAMS *pParams +) +{ + nvlink_link *link; + NvU64 linkStateTl; + NvU64 enabledLinkMask; + NvU8 linkId; + + if (device->bModeContinuousALI) + { + return -NVL_ERR_INVALID_STATE; + } + + // Only process enabled links + enabledLinkMask = nvswitch_get_enabled_link_mask(device); + pParams->linkMaskTrain &= enabledLinkMask; + + NVSWITCH_PRINT(device, INFO, + "%s: ALI requested for links 0x%llx\n", + __FUNCTION__, pParams->linkMaskTrain); + + // Handle access links + FOR_EACH_INDEX_IN_MASK(64, linkId, pParams->linkMaskTrain) + { + // Only directly launch ALI on non-CCI managed links + if (cciIsLinkManaged(device, linkId)) + { + continue; + } + + link = nvswitch_get_link(device, linkId); + if ((link == NULL) || + !NVSWITCH_IS_LINK_ENG_VALID(device, linkId, NVLIPT_LNK) || + (linkId >= NVSWITCH_NVLINK_MAX_LINKS) || + (device->hal.nvswitch_corelib_get_tl_link_mode(link, &linkStateTl) != NVL_SUCCESS)) + { + continue; + } + + if (linkStateTl == NVLINK_LINKSTATE_ACTIVE_PENDING) + { + continue; + } + + // Forcibly reset and re-train access links + device->hal.nvswitch_reset_and_drain_links(device, + NVBIT64(linkId), NV_TRUE); + } + FOR_EACH_INDEX_IN_MASK_END; + + // Ask CCI to handle trunk links + nvswitch_ctrl_cci_request_ali(device, pParams); + + return NVL_SUCCESS; +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_nvlink_max_correctable_error_rate +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params +) +{ + return nvswitch_inforom_nvlink_get_max_correctable_error_rate(device, params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_nvlink_errors +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params +) +{ + return nvswitch_inforom_nvlink_get_errors(device, params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_ecc_errors +( + nvswitch_device *device, + NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *params +) +{ + return nvswitch_inforom_ecc_get_errors(device, params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_sxid +( + nvswitch_device *device, + NVSWITCH_GET_SXIDS_PARAMS *params +) +{ + return nvswitch_inforom_bbx_get_sxid(device, params); +} + +static NvlStatus +_nvswitch_ctrl_get_inforom_bbx_sys_info +( + nvswitch_device *device, NVSWITCH_GET_SYS_INFO_PARAMS *params ) { @@ -4925,6 +5492,25 @@ nvswitch_init_lpwr_regs device->hal.nvswitch_init_lpwr_regs(link); } +void +nvswitch_program_l1_scratch_reg +( + nvswitch_device *device, + NvU32 linkNumber +) +{ + device->hal.nvswitch_program_l1_scratch_reg(device, linkNumber); +} + +NvlStatus +nvswitch_check_io_sanity +( + nvswitch_device *device +) +{ + return device->hal.nvswitch_check_io_sanity(device); +} + NvlStatus nvswitch_launch_ALI ( @@ -5096,6 +5682,212 @@ _nvswitch_ctrl_therm_read_power return device->hal.nvswitch_ctrl_therm_read_power(device, info); } +NvlStatus +nvswitch_get_board_id +( + nvswitch_device *device, + NvU16 *boardId +) +{ + return device->hal.nvswitch_get_board_id(device, boardId); +} + +NvlStatus +_nvswitch_ctrl_get_link_l1_capability +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_L1_CAPABILITY_PARAMS *p +) +{ + NvlStatus status; + nvlink_link *link; + NvU8 i; + + if (p->linkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: No links in linkMask\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + FOR_EACH_INDEX_IN_MASK(64, i, p->linkMask) + { + NvU32 linkNum; + + NVSWITCH_ASSERT(i < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, i); + if ((link == NULL) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + NVSWITCH_PRINT(device, ERROR, "%s: Invalid input link %d set in linkMask\n", + __FUNCTION__, i); + return -NVL_BAD_ARGS; + } + + linkNum = link->linkNumber; + + status = device->hal.nvswitch_ctrl_get_link_l1_capability(device, linkNum, &(p->l1Capable[linkNum])); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to get l1 capability for link %d\n", + __FUNCTION__, linkNum); + return status; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + +NvlStatus +_nvswitch_ctrl_get_link_l1_threshold +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_L1_THRESHOLD_PARAMS *p +) +{ + NvlStatus status; + nvlink_link *link; + NvBool isL1Capable; + NvU8 i; + + if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) + { + NVSWITCH_PRINT(device, INFO, "%s: L1 Threshold is disabled\n", __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (p->linkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: No links in linkMask\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + FOR_EACH_INDEX_IN_MASK(64, i, p->linkMask) + { + NvU32 linkNum; + + NVSWITCH_ASSERT(i < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, i); + if ((link == NULL) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + NVSWITCH_PRINT(device, ERROR, "%s: Invalid input link %d set in linkMask\n", + __FUNCTION__, i); + return -NVL_BAD_ARGS; + } + + linkNum = link->linkNumber; + + status = device->hal.nvswitch_ctrl_get_link_l1_capability(device, linkNum, &isL1Capable); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to get l1 capability for link %d\n", + __FUNCTION__, linkNum); + return status; + } + + if (!isL1Capable) + { + NVSWITCH_PRINT(device, ERROR, "%s: Input link %d does not support L1\n", + __FUNCTION__, i); + return -NVL_ERR_NOT_SUPPORTED; + } + + // Get HAL + status = device->hal.nvswitch_ctrl_get_link_l1_threshold(device, linkNum, &(p->l1Threshold[linkNum])); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to get L1 Threshold for link %d\n", + __FUNCTION__, linkNum); + return status; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + +NvlStatus +_nvswitch_ctrl_set_link_l1_threshold +( + nvswitch_device *device, + NVSWITCH_SET_NVLINK_L1_THRESHOLD_PARAMS *p +) +{ + NvlStatus status; + nvlink_link *link; + NvBool isL1Capable; + NvU8 i; + + if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO) + { + NVSWITCH_PRINT(device, INFO, "%s: L1 Threshold is disabled\n", __FUNCTION__); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (p->linkMask == 0) + { + NVSWITCH_PRINT(device, ERROR, "%s: No links in linkMask\n", __FUNCTION__); + return -NVL_BAD_ARGS; + } + + FOR_EACH_INDEX_IN_MASK(64, i, p->linkMask) + { + NvU32 linkNum; + NvU32 l1Threshold; + + NVSWITCH_ASSERT(i < NVSWITCH_LINK_COUNT(device)); + + link = nvswitch_get_link(device, i); + if ((link == NULL) || + (i >= NVSWITCH_NVLINK_MAX_LINKS)) + { + NVSWITCH_PRINT(device, ERROR, "%s: Invalid input link %d set in linkMask\n", + __FUNCTION__, i); + return -NVL_BAD_ARGS; + } + + linkNum = link->linkNumber; + l1Threshold = p->l1Threshold[linkNum]; + + status = device->hal.nvswitch_ctrl_get_link_l1_capability(device, linkNum, &isL1Capable); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to get l1 capability for link %d\n", + __FUNCTION__, linkNum); + return status; + } + + if (!isL1Capable) + { + NVSWITCH_PRINT(device, ERROR, "%s: Input link %d does not support L1\n", + __FUNCTION__, i); + return -NVL_ERR_NOT_SUPPORTED; + } + + if (((l1Threshold < NVSWITCH_SET_NVLINK_L1_THRESHOLD_MIN) || + (l1Threshold > NVSWITCH_SET_NVLINK_L1_THRESHOLD_MAX)) && + (l1Threshold != NVSWITCH_SET_NVLINK_L1_THRESHOLD_DEFAULT)) + { + return -NVL_BAD_ARGS; + } + + status = device->hal.nvswitch_ctrl_set_link_l1_threshold(link, + p->l1Threshold[linkNum]); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to set L1 Threshold for link %d\n", + __FUNCTION__, linkNum); + return status; + } + } + FOR_EACH_INDEX_IN_MASK_END + + return NVL_SUCCESS; +} + NvlStatus nvswitch_lib_ctrl ( @@ -5316,26 +6108,66 @@ nvswitch_lib_ctrl _nvswitch_ctrl_i2c_smbus_command, NVSWITCH_I2C_SMBUS_COMMAND_PARAMS, osPrivate, NVSWITCH_DEV_CMD_CHECK_ADMIN); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_0); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_1); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_2); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_3); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_4); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_5); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_8); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_9); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_10); - NVSWITCH_DEV_CMD_DISPATCH_RESERVED( - CTRL_NVSWITCH_RESERVED_11); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_CMIS_PRESENCE, + _nvswitch_ctrl_cci_cmis_presence, + NVSWITCH_CCI_CMIS_PRESENCE_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_CMIS_NVLINK_MAPPING, + _nvswitch_ctrl_cci_nvlink_mappings, + NVSWITCH_CCI_CMIS_NVLINK_MAPPING_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ, + _nvswitch_ctrl_cci_memory_access_read, + NVSWITCH_CCI_CMIS_MEMORY_ACCESS_READ_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE, + _nvswitch_ctrl_cci_memory_access_write, + NVSWITCH_CCI_CMIS_MEMORY_ACCESS_WRITE_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING, + _nvswitch_ctrl_cci_cage_bezel_marking, + NVSWITCH_CCI_CMIS_CAGE_BEZEL_MARKING_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_GET_GRADING_VALUES, + nvswitch_ctrl_get_grading_values, + NVSWITCH_CCI_GET_GRADING_VALUES_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_GET_PORTS_CPLD_INFO, + nvswitch_ctrl_get_ports_cpld_info, + NVSWITCH_CCI_GET_PORTS_CPLD_INFO_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_GET_FW_REVISIONS, + nvswitch_ctrl_get_cci_fw_revisions, + NVSWITCH_CCI_GET_FW_REVISION_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_CCI_SET_LOCATE_LED, + nvswitch_ctrl_set_locate_led, + NVSWITCH_CCI_SET_LOCATE_LED_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_GET_SOE_HEARTBEAT, + _nvswitch_ctrl_get_soe_heartbeat, + NVSWITCH_GET_SOE_HEARTBEAT_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_SET_CONTINUOUS_ALI, + _nvswitch_ctrl_set_continuous_ali, + NVSWITCH_SET_CONTINUOUS_ALI_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( + CTRL_NVSWITCH_REQUEST_ALI, + _nvswitch_ctrl_request_ali, + NVSWITCH_REQUEST_ALI_PARAMS, + osPrivate, flags); NVSWITCH_DEV_CMD_DISPATCH( CTRL_NVSWITCH_GET_TEMPERATURE_LIMIT, _nvswitch_ctrl_therm_get_temperature_limit, @@ -5463,6 +6295,19 @@ nvswitch_lib_ctrl _nvswitch_ctrl_get_inforom_bbx_temp_samples, NVSWITCH_GET_TEMP_SAMPLES_PARAMS, osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_NVLINK_L1_CAPABILITY, + _nvswitch_ctrl_get_link_l1_capability, + NVSWITCH_GET_NVLINK_L1_CAPABILITY_PARAMS); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_NVLINK_L1_THRESHOLD, + _nvswitch_ctrl_get_link_l1_threshold, + NVSWITCH_GET_NVLINK_L1_THRESHOLD_PARAMS); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(CTRL_NVSWITCH_SET_NVLINK_L1_THRESHOLD, + _nvswitch_ctrl_set_link_l1_threshold, + NVSWITCH_SET_NVLINK_L1_THRESHOLD_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_FSPRPC_GET_CAPS, + _nvswitch_ctrl_fsprpc_get_caps, + NVSWITCH_FSPRPC_GET_CAPS_PARAMS); default: nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd); diff --git a/src/common/nvswitch/kernel/smbpbi_nvswitch.c b/src/common/nvswitch/kernel/smbpbi_nvswitch.c index 8cefb389df..cca0e90de1 100644 --- a/src/common/nvswitch/kernel/smbpbi_nvswitch.c +++ b/src/common/nvswitch/kernel/smbpbi_nvswitch.c @@ -85,7 +85,6 @@ nvswitch_smbpbi_post_init { return -NVL_ERR_NOT_SUPPORTED; } - status = device->hal.nvswitch_smbpbi_post_init_hal(device); if (status == NVL_SUCCESS) diff --git a/src/common/sdk/nvidia/inc/cc_drv.h b/src/common/sdk/nvidia/inc/cc_drv.h index b8a3e5f243..4115658722 100644 --- a/src/common/sdk/nvidia/inc/cc_drv.h +++ b/src/common/sdk/nvidia/inc/cc_drv.h @@ -55,6 +55,17 @@ typedef enum ROTATE_IV_TYPE { ROTATE_IV_ALL_VALID = 3, // Rotate the IV for all valid bundles in the KMB } ROTATE_IV_TYPE; +// Status value written into NvNotification.Info16 +typedef enum KEY_ROTATION_STATUS { + KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress + KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation + KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress + KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels + KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels + KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel. + KEY_ROTATION_STATUS_MAX_COUNT = 6, +} KEY_ROTATION_STATUS; + typedef struct CC_AES_CRYPTOBUNDLE { NvU32 iv[CC_AES_256_GCM_IV_SIZE_DWORD]; NvU32 key[CC_AES_256_GCM_KEY_SIZE_DWORD]; @@ -79,3 +90,11 @@ typedef struct CC_KMB { } CC_KMB; typedef struct CC_KMB *PCC_KMB; +typedef struct CC_CRYPTOBUNDLE_STATS { + NV_DECLARE_ALIGNED(NvU64 numEncryptionsH2D, 8); + NV_DECLARE_ALIGNED(NvU64 numEncryptionsD2H, 8); + NV_DECLARE_ALIGNED(NvU64 bytesEncryptedH2D, 8); + NV_DECLARE_ALIGNED(NvU64 bytesDecryptedD2H, 8); +} CC_CRYPTOBUNDLE_STATS; +typedef struct CC_CRYPTOBUNDLE_STATS *PCC_CRYPTOBUNDLE_STATS; + diff --git a/src/common/sdk/nvidia/inc/class/cl00de.h b/src/common/sdk/nvidia/inc/class/cl00de.h index 20227baf1c..29a62bb2e3 100644 --- a/src/common/sdk/nvidia/inc/class/cl00de.h +++ b/src/common/sdk/nvidia/inc/class/cl00de.h @@ -36,6 +36,8 @@ extern "C" { #define RUSD_TIMESTAMP_WRITE_IN_PROGRESS (NV_U64_MAX) #define RUSD_TIMESTAMP_INVALID 0 +#define RUSD_SEQ_DATA_VALID(x) ((((NvU32)(x)) & 0x1U) == 0) + enum { RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0, RUSD_CLK_PUBLIC_DOMAIN_MEMORY, diff --git a/src/common/sdk/nvidia/inc/class/cl00e0.h b/src/common/sdk/nvidia/inc/class/cl00e0.h index f2dce87735..8fac1e3e51 100644 --- a/src/common/sdk/nvidia/inc/class/cl00e0.h +++ b/src/common/sdk/nvidia/inc/class/cl00e0.h @@ -30,10 +30,16 @@ // Source file: class/cl00e0.finn // -#include "nvcfg_sdk.h" #include "cl0080.h" - +/* + * Class definition for exporting memory handles to a different RM client on the + * same or another node (OS). + * + * No memory is allocated or mapped using this class. + * Parented by hClient. + * NvRmDupObject() is not supported. Use NV_MEM_EXPORT_FLAGS_DUP_BY_UUID instead. + */ #define NV_MEMORY_EXPORT (0xe0U) /* finn: Evaluated from "NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID" */ @@ -49,7 +55,47 @@ typedef struct NV_EXPORT_MEM_PACKET { #define NV_MEM_EXPORT_FLAGS_DEFAULT 0x00000000 #define NV_MEM_EXPORT_FLAGS_DUP_BY_UUID 0x00000001 - +/* + * imexChannel [IN] + * Used to associated export object with an IMEX channel. + * When duping, + * - If the caller is not the privileged IMEX daemon, validate the caller + * is subscribed to the channel. + * - Validate that the imexChannel matches with that of the export object being + * duped. + * + * packet [IN/OUT] + * Bag of bits which uniquely identifies this object universally. + * - When a new object is allocated, "packet" is returned as output. + * - If NV_MEM_EXPORT_FLAGS_DUP_BY_UUID is provided, "packet" is used as + * input to duplicate the existing object. + * + * numMaxHandles [IN/OUT] + * Max number of memory handles to be attached to the export object. + * - Input when a new object is allocated. + * - Output When duplicating. + * + * flags [IN/OUT] + * One of NV_MEM_EXPORT_FLAGS_* + * - Input when a new object is allocated or duplicated. + * - Output when duplicating. The flags at the time of allocation are + * returned. + * + * metadata [IN/OUT] + * Private data about the export object (opaque to kernel mode) + * - Input when a new object is allocated. + * - Output When duplicating. + * + * deviceInstanceMask [OUT] + * Attached device instance mask + * + * giIdMasks [OUT] + * Attached GPU instance ID mask (MIG is currently not supported) + * Must be indexed using deviceInstanceMask. + * + * numCurHandles [OUT] + * Number of memory handles currently attached to the export object. + */ #define NV00E0_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00e0U) diff --git a/src/common/sdk/nvidia/inc/class/cl00f1.h b/src/common/sdk/nvidia/inc/class/cl00f1.h new file mode 100644 index 0000000000..c2b35ae811 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl00f1.h @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f1.finn +// + +#define NV_IMEX_SESSION (0xf1U) /* finn: Evaluated from "NV00F1_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +#define NV00F1_ALLOC_FLAGS_DEFAULT 0 + +// +// Disables channel recovery on IMEX shutdown. This can lead to security +// issues. The flag is intended to be used for testing purpose only. +// +#define NV00F1_ALLOC_DISABLE_CHANNEL_RECOVERY NVBIT(0) + +#define NV00F1_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f1U) + +typedef struct NV00F1_ALLOCATION_PARAMETERS { + // + // capDescriptor is a file descriptor for UNIX RM clients, but a void + // pointer for windows RM clients. + // + // capDescriptor is transparent to RM clients i.e. RM's user-mode shim + // populates this field on behalf of clients. + // + NV_DECLARE_ALIGNED(NvU64 capDescriptor, 8); + + // See NV00F1_ALLOC_FLAGS_xxx + NvU32 flags; + + // OS event handle created with NvRmAllocOsEvent(). + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); + + // Node ID which represent this OS/RM instance + NvU16 nodeId; +} NV00F1_ALLOCATION_PARAMETERS; + diff --git a/src/common/sdk/nvidia/inc/class/cl00f9.h b/src/common/sdk/nvidia/inc/class/cl00f9.h new file mode 100644 index 0000000000..8f37e0a83f --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl00f9.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00f9.finn +// + +#include "cl00e0.h" + +/* + * Class definition for importing memory handles from a different RM client on + * the same or another node (OS). + */ + +#define NV_MEMORY_FABRIC_IMPORT_V2 (0xf9U) /* finn: Evaluated from "NV00F9_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * imexChannel [IN] + * IMEX channel to be used for import. (Currently ignored, driver picks the + * appropriate channel) + * + * packet [DEPRECATED, use expPacket instead] + * Fabric packet which uniquely identifies this object universally. + * + * expPacket [IN] + * Export object (see cl00e0.h) identifier from which memory will be imported. + * + * index [IN] + * Index into the FLA handle array associated with the export UUID. + * + * flags [IN] + * For future use. + * Set to zero for default behavior. + * + * pOsEvent [IN] + * Optional OS event handle created with NvRmAllocOsEvent(). + * + * id [IN] + * A 48-bit ID for this import call. The caller has freedom to uniqueness + * of the ID. RM would track the object uniquely using + * . + */ + +#define NV00F9_IMPORT_ID_MAX (NVBIT64(48) - 1) +#define NV00F9_IMPORT_ID_SHIFT 16 + +#define NV00F9_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00f9U) + +typedef struct NV00F9_ALLOCATION_PARAMETERS { + NvU32 imexChannel; + NV_EXPORT_MEM_PACKET expPacket; + NvU16 index; + NvU32 flags; + NV_DECLARE_ALIGNED(NvP64 pOsEvent, 8); + NV_DECLARE_ALIGNED(NvU64 id, 8); +} NV00F9_ALLOCATION_PARAMETERS; + diff --git a/src/common/sdk/nvidia/inc/class/cl00fb.h b/src/common/sdk/nvidia/inc/class/cl00fb.h new file mode 100644 index 0000000000..181d3e37d9 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cl00fb.h @@ -0,0 +1,71 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cl00fb.finn +// + +#include "cl00e0.h" + +/* + * Class definition for referencing the imported fabric memory, + * NV_MEMORY_FABRIC_IMPORT_V2, using the export object UUID. + * + * A privileged fabric manager only class, parented by client. + * + * No fabric events will be generated during creation or destruction of + * this class. + */ + +#define NV_MEMORY_FABRIC_IMPORTED_REF (0xfbU) /* finn: Evaluated from "NV00FB_ALLOCATION_PARAMETERS_MESSAGE_ID" */ + +/* + * exportUuid [IN] + * Universally unique identifier of the export object. This is extracted + * from a fabric packet. + * + * index [IN] + * Index of the export object to which the memory object is attached. + * + * flags [IN] + * Currently unused. Must be zero for now. + * + * id [IN] + * Import ID. An import request is uniquely identified using, + * . + */ + +#define NV00FB_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fbU) + +typedef struct NV00FB_ALLOCATION_PARAMETERS { + NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN]; + NvU16 index; + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 id, 8); +} NV00FB_ALLOCATION_PARAMETERS; + diff --git a/src/common/sdk/nvidia/inc/class/cl00fd.h b/src/common/sdk/nvidia/inc/class/cl00fd.h index 271bcb3ad3..0cc657cb11 100644 --- a/src/common/sdk/nvidia/inc/class/cl00fd.h +++ b/src/common/sdk/nvidia/inc/class/cl00fd.h @@ -36,8 +36,18 @@ #include "cl00e0.h" + + #define NV_MEMORY_MULTICAST_FABRIC (0xfdU) /* finn: Evaluated from "NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID" */ +/* + * expPacket [IN] + * Export object (see cl00e0.h) identifier from which memory will be imported. + * + * index [IN] + * Index of the export object to which the memory object is attached. + */ + /* * alignment [IN] @@ -62,6 +72,13 @@ #define NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M 0x20000000 +/* + * This flag must be passed if the object is created using export packet. Note + * when this flag is provided, the input params: alignment, allocSize, + * numGpus, pageSize won't be honored. + */ +#define NV_MEMORY_MULTICAST_FABRIC_ALLOC_FLAGS_USE_EXPORT_PACKET 0x00000001 + #define NV00FD_ALLOCATION_PARAMETERS_MESSAGE_ID (0x00fdU) @@ -69,6 +86,8 @@ typedef struct NV00FD_ALLOCATION_PARAMETERS { NV_EXPORT_MEM_PACKET expPacket; NvU16 index; + + NV_DECLARE_ALIGNED(NvU64 alignment, 8); NV_DECLARE_ALIGNED(NvU64 allocSize, 8); NvU32 pageSize; diff --git a/src/common/sdk/nvidia/inc/class/cl00fe.h b/src/common/sdk/nvidia/inc/class/cl00fe.h index 581881b982..b0235a6b08 100644 --- a/src/common/sdk/nvidia/inc/class/cl00fe.h +++ b/src/common/sdk/nvidia/inc/class/cl00fe.h @@ -41,6 +41,7 @@ #define NV_MEMORY_MAPPER_ALLOCATION_PARAMS_MESSAGE_ID (0x00FEU) typedef struct NV_MEMORY_MAPPER_ALLOCATION_PARAMS { - NvBool unused; + NvHandle hSemaphoreSurface; + NvU32 maxQueueSize; } NV_MEMORY_MAPPER_ALLOCATION_PARAMS; diff --git a/src/common/sdk/nvidia/inc/class/cl2080_notification.h b/src/common/sdk/nvidia/inc/class/cl2080_notification.h index 1097ec791b..2af8fae956 100644 --- a/src/common/sdk/nvidia/inc/class/cl2080_notification.h +++ b/src/common/sdk/nvidia/inc/class/cl2080_notification.h @@ -221,7 +221,11 @@ extern "C" { #define NV2080_NOTIFIERS_RESERVED180 (180) #define NV2080_NOTIFIERS_AUX_POWER_EVENT (181) #define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182) -#define NV2080_NOTIFIERS_MAXCOUNT (183) +#define NV2080_NOTIFIERS_RESERVED_183 (183) // Unused +#define NV2080_NOTIFIERS_GSP_PERF_TRACE (184) +#define NV2080_NOTIFIERS_INBAND_RESPONSE (185) +#define NV2080_NOTIFIERS_RESERVED_186 (186) // Unused +#define NV2080_NOTIFIERS_MAXCOUNT (187) // Indexed GR notifier reference #define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1))) @@ -330,7 +334,8 @@ extern "C" { #define NV2080_ENGINE_TYPE_RESERVED3c (0x0000003c) #define NV2080_ENGINE_TYPE_RESERVED3d (0x0000003d) #define NV2080_ENGINE_TYPE_RESERVED3e (0x0000003e) -#define NV2080_ENGINE_TYPE_LAST (0x0000003f) +#define NV2080_ENGINE_TYPE_RESERVED3f (0x0000003f) +#define NV2080_ENGINE_TYPE_LAST (0x00000040) #define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff) // @@ -507,7 +512,7 @@ typedef struct Nv2080HdmiFrlRequestNotificationRec { NvU32 displayId; } Nv2080HdmiFrlRequestNotification; -/* +/* * Platform Power Mode event information */ typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS { @@ -516,8 +521,8 @@ typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS { NvU8 eventReason; } NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS; -#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0 -#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0 +#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8 #define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16 /* diff --git a/src/common/sdk/nvidia/inc/class/cl90cdtypes.h b/src/common/sdk/nvidia/inc/class/cl90cdtypes.h index f2a40cf350..d4b33a1703 100644 --- a/src/common/sdk/nvidia/inc/class/cl90cdtypes.h +++ b/src/common/sdk/nvidia/inc/class/cl90cdtypes.h @@ -36,9 +36,11 @@ extern "C" { #define NV_EVENT_BUFFER_RECORD_TYPE_VIDEO_TRACE (1) #define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH_V2 (2) #define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SYSTEM (4) +#define NV_EVENT_BUFFER_RECORD_TYPE_RATS_GSP_TRACE (8) #define NV_EVENT_BUFFER_RECORD_TYPE_NVTELEMETRY_REPORT_EVENT_SUBDEVICE (132) #define NV_EVENT_BUFFER_RECORD_TYPE_FECS_CTX_SWITCH (134) + #ifdef __cplusplus }; /* extern "C" */ #endif diff --git a/src/common/sdk/nvidia/inc/class/cla080.h b/src/common/sdk/nvidia/inc/class/cla080.h new file mode 100644 index 0000000000..95bbf1dd0b --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cla080.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla080.finn +// + +#define KEPLER_DEVICE_VGPU 0x0000a080U + diff --git a/src/common/sdk/nvidia/inc/class/cla084.h b/src/common/sdk/nvidia/inc/class/cla084.h index 1840257405..e31346179b 100644 --- a/src/common/sdk/nvidia/inc/class/cla084.h +++ b/src/common/sdk/nvidia/inc/class/cla084.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -46,6 +46,8 @@ * swizzId [IN] -> Used only when MIG mode is enabled otherwise set * to NV2080_CTRL_GPU_PARTITION_ID_INVALID. * numChannels -> Used only when SRIOV is enabled. Must be a power of 2. + * placementId [IN] -> Used to provide placement ID of with heterogeneous timesliced vGPUs. + * Otherwise set to NVA081_PLACEMENT_ID_INVALID. * bDisableDefaultSmcExecPartRestore - If set to true, SMC default execution partition * save/restore will not be done in host-RM * vgpuDeviceInstanceId -> Specifies the vGPU device instance per VM to be used @@ -67,6 +69,7 @@ typedef struct NVA084_ALLOC_PARAMETERS { NvU32 vmPid; NvU32 numChannels; NvU32 numPluginChannels; + NvU16 placementId; VM_ID_TYPE vmIdType; NV_DECLARE_ALIGNED(VM_ID guestVmId, 8); NvBool bDisableDefaultSmcExecPartRestore; diff --git a/src/common/sdk/nvidia/inc/class/cla0bc.h b/src/common/sdk/nvidia/inc/class/cla0bc.h new file mode 100644 index 0000000000..bc2681923b --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cla0bc.h @@ -0,0 +1,209 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla0bc.finn +// + +#define NVENC_SW_SESSION (0xa0bcU) /* finn: Evaluated from "NVA0BC_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * NVENC_SESSION_INFO_REGION_MAX_COUNT_V1 + * Number of regions. + * Currently we have two regions. + * +---------+ <== Region 1 Start + * | Entry 1 | + * | Entry 2 | + * | ... | + * | Entry N | + * +---------+ <== Region 1 End, Region 2 Start. + * | Entry 1 | + * | Entry 2 | + * | ... | + * | Entry N | + * +---------+ <== Region 2 End + * Region 1 : Contains GPU timestamp of each frame when frame was submitted + * to encode by UMD. + * Region 2 : Two entries in this region for each frame. Start and end GPU + * timestamps of when GPU started and ended encoding a frame. + */ +#define NVENC_SESSION_INFO_REGION_MAX_COUNT_V1 2 + +/* + * NVENC_SESSION_INFO_ENTRY_V1 + * This structure represents a single timestamp entry for a frame. + * frameId + * Frame id of the frame being submitted for encoding by UMD. + * reserved + * This is a reserved field. Unused. + * timestamp + * GPU timestamp. + */ + +typedef struct NVENC_SESSION_INFO_ENTRY_V1 { + NvU32 frameId; + NvU32 reserved; + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); +} NVENC_SESSION_INFO_ENTRY_V1; + +/* + * NVENC_SESSION_INFO_REGION_1_ENTRY_V1 + * This structure represents an entry in Region 1. + * submissionTSEntry + * Frame id and GPU timestamp of the time when the frame was submitted to + * encode by UMD. + * + * NVENC_SESSION_INFO_REGION_1_ENTRY_SIZE_V1 + * Size of each entry in region 1. + * + * NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 + * No of entries in region 1. + * + * NVENC_SESSION_INFO_REGION_1_V1 + * This structure represents Region 1. + * + * NVENC_SESSION_INFO_REGION_1_SIZE_V1 + * Size of region 1. + * + * NVENC_SESSION_INFO_REGION_1_OFFSET_V1 + * First region, so offset is 0. + */ + +typedef struct NVENC_SESSION_INFO_REGION_1_ENTRY_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 submissionTSEntry, 8); +} NVENC_SESSION_INFO_REGION_1_ENTRY_V1; + +#define NVENC_SESSION_INFO_REGION_1_ENTRY_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_1_ENTRY_V1) + +#define NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 256 + +typedef struct NVENC_SESSION_INFO_REGION_1_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_1_ENTRY_V1 frameInfo[NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1], 8); +} NVENC_SESSION_INFO_REGION_1_V1; + +#define NVENC_SESSION_INFO_REGION_1_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_1_V1) + +#define NVENC_SESSION_INFO_REGION_1_OFFSET_V1 0 + +/* + * NVENC_SESSION_INFO_REGION_2_ENTRY_V1 + * This structure represents a complete entry in Region 2. + * startTSEntry + * Frame id and GPU timestamp of the time when frame encoding started. + * endTSEntry + * Frame id and GPU timestamp of the time when frame encoding ended. + * + * NVENC_SESSION_INFO_REGION_2_ENTRY_SIZE_V1 + * Size of each entry in region 2. + * + * NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1 + * No of entries in region 2. + * + * NVENC_SESSION_INFO_REGION_2_V1 + * This structure represents Region 2. + * + * NVENC_SESSION_INFO_REGION_2_SIZE_V1 + * Size of region 2. + * + * NVENC_SESSION_INFO_REGION_2_OFFSET_V1 + * Offset of region 2 from base. + */ + +typedef struct NVENC_SESSION_INFO_REGION_2_ENTRY_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 startTSEntry, 8); + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_ENTRY_V1 endTSEntry, 8); +} NVENC_SESSION_INFO_REGION_2_ENTRY_V1; + +#define NVENC_SESSION_INFO_REGION_2_ENTRY_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_2_ENTRY_V1) + +#define NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1 NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 + +typedef struct NVENC_SESSION_INFO_REGION_2_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_2_ENTRY_V1 frameInfo[NVENC_SESSION_INFO_REGION_2_MAX_ENTRIES_COUNT_V1], 8); +} NVENC_SESSION_INFO_REGION_2_V1; + +#define NVENC_SESSION_INFO_REGION_2_SIZE_V1 sizeof(NVENC_SESSION_INFO_REGION_2_V1) + +#define NVENC_SESSION_INFO_REGION_2_OFFSET_V1 (NVENC_SESSION_INFO_REGION_1_OFFSET_V1 + \ + NVENC_SESSION_INFO_REGION_1_SIZE_V1) + +/* + * NVENC_SESSION_INFO_V1 + * This structure represents the complete memory allocated to store the per + * frame submission-start-end timestamps data. + * + * NVENC_SESSION_INFO_SIZE_V1 + * Size of complete memory. + */ + +typedef struct NVENC_SESSION_INFO_V1 { + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_1_V1 region1, 8); + NV_DECLARE_ALIGNED(NVENC_SESSION_INFO_REGION_2_V1 region2, 8); +} NVENC_SESSION_INFO_V1; + +#define NVENC_SESSION_INFO_SIZE_V1 sizeof(NVENC_SESSION_INFO_V1) + +/* + * NVA0BC_ALLOC_PARAMETERS + * + * This structure represents NVENC SW session allocation parameters. + * + * codecType + * Codec type to be used to do the encoding. + * hResolution + * Width of frames to be encoded. + * vResolution + * Height of frames to be encoded. + * version + * Adding version to handle any future changes to struct. + * In future we can extend this struct to notify RM that UMD needs to send + * other data. Versioning will help in identifying the difference in structs. + * Values are defined by NVA0BC_ALLOC_PARAMS_VER_xxx. + * hMem + * Handle to the system memory allocated by UMD. + * RM needs to access the memory to get the raw timestamp data and process it. + */ + +#define NVA0BC_ALLOC_PARAMETERS_MESSAGE_ID (0xa0bcU) + +typedef struct NVA0BC_ALLOC_PARAMETERS { + NvU32 codecType; + NvU32 hResolution; + NvU32 vResolution; + + NvU32 version; + NvHandle hMem; +} NVA0BC_ALLOC_PARAMETERS; + +#define NVA0BC_ALLOC_PARAMS_VER_0 0x00000000 +#define NVA0BC_ALLOC_PARAMS_VER_1 0x00000001 + +#define NVA0BC_NVENC_SESSION_CODEC_TYPE_H264 0x000000 +#define NVA0BC_NVENC_SESSION_CODEC_TYPE_HEVC 0x000001 +#define NVA0BC_NVENC_SESSION_CODEC_TYPE_AV1 0x000002 +#define NVA0BC_NVENC_SESSION_CODEC_TYPE_UNKNOWN 0x0000FF diff --git a/src/common/sdk/nvidia/inc/class/cla0bd.h b/src/common/sdk/nvidia/inc/class/cla0bd.h new file mode 100644 index 0000000000..fb91d2dee4 --- /dev/null +++ b/src/common/sdk/nvidia/inc/class/cla0bd.h @@ -0,0 +1,81 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: class/cla0bd.finn +// + +#define NVFBC_SW_SESSION (0xa0bdU) /* finn: Evaluated from "NVA0BD_ALLOC_PARAMETERS_MESSAGE_ID" */ + +/* + * NVA0BD_ALLOC_PARAMETERS + * + * displayOrdinal + * This parameter specifies the display identifier. + * sessionType + * This parameter NVFBC session type. Possible values are specified + * by NVA0BD_NVFBC_SESSION_TYPE_* macros. + * sessionFlags + * This parameter returns various flags values of the NVFBC session. + * Valid flag values include: + * NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED + * When true this flag indicates there are user has enabled + * diff map feature for the session. + * NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED + * When true this flag indicates there are user has enabled + * diff map feature for the session. + * hMaxResolution + * This parameter returns the max horizontal resolution supported by + * the NvFBC session. + * vMaxResolution + * This parameter returns the max vertical resolution supported by + * the NvFBC session. + */ + +#define NVA0BD_ALLOC_PARAMETERS_MESSAGE_ID (0xa0bdU) + +typedef struct NVA0BD_ALLOC_PARAMETERS { + NvU32 displayOrdinal; + NvU32 sessionType; + NvU32 sessionFlags; + NvU32 hMaxResolution; + NvU32 vMaxResolution; +} NVA0BD_ALLOC_PARAMETERS; + +#define NVA0BD_NVFBC_SESSION_TYPE_UNKNOWN 0x000000 +#define NVA0BD_NVFBC_SESSION_TYPE_TOSYS 0x000001 +#define NVA0BD_NVFBC_SESSION_TYPE_CUDA 0x000002 +#define NVA0BD_NVFBC_SESSION_TYPE_VID 0x000003 +#define NVA0BD_NVFBC_SESSION_TYPE_HWENC 0x000004 + +#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED 0:0 +#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED_FALSE (0x00000000) +#define NVA0BD_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED_TRUE (0x00000001) +#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED 1:1 +#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED_FALSE (0x00000000) +#define NVA0BD_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED_TRUE (0x00000001) + diff --git a/src/common/sdk/nvidia/inc/class/clc86f.h b/src/common/sdk/nvidia/inc/class/clc86f.h index 48154a3d00..9d5e54c9e9 100644 --- a/src/common/sdk/nvidia/inc/class/clc86f.h +++ b/src/common/sdk/nvidia/inc/class/clc86f.h @@ -52,6 +52,7 @@ typedef volatile struct Nvc86fControl_struct { #define NVC86F_SEM_PAYLOAD_HI (0x00000068) #define NVC86F_SEM_EXECUTE (0x0000006c) #define NVC86F_SEM_EXECUTE_OPERATION 2:0 +#define NVC86F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 #define NVC86F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 #define NVC86F_SEM_EXECUTE_RELEASE_WFI 20:20 #define NVC86F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 diff --git a/src/common/sdk/nvidia/inc/class/clc86fsw.h b/src/common/sdk/nvidia/inc/class/clc86fsw.h index dce4dfd566..6020315d6a 100644 --- a/src/common/sdk/nvidia/inc/class/clc86fsw.h +++ b/src/common/sdk/nvidia/inc/class/clc86fsw.h @@ -35,7 +35,8 @@ #define NVC86F_NOTIFIERS_SW (6) #define NVC86F_NOTIFIERS_GR_DEBUG_INTR (7) #define NVC86F_NOTIFIERS_REPLAYABLE_FAULT (8) -#define NVC86F_NOTIFIERS_MAXCOUNT (9) +#define NVC86F_NOTIFIERS_KEY_ROTATION (9) +#define NVC86F_NOTIFIERS_MAXCOUNT (10) /* NvNotification[] fields and values */ #define NVC86F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000) diff --git a/src/common/sdk/nvidia/inc/class/clcba2.h b/src/common/sdk/nvidia/inc/class/clcba2.h index 86936384ee..adfeaed338 100644 --- a/src/common/sdk/nvidia/inc/class/clcba2.h +++ b/src/common/sdk/nvidia/inc/class/clcba2.h @@ -118,6 +118,7 @@ typedef volatile struct _clcba2_tag0 { // Class definitions #define NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES (2*1024*1024) +#define NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES (1024*1024*1024) // Errors #define NVCBA2_ERROR_NONE (0x00000000) @@ -149,6 +150,7 @@ typedef volatile struct _clcba2_tag0 { #define NVCBA2_ERROR_SCRUBBER_INVALD_ADDRESS (0x0000001a) #define NVCBA2_ERROR_SCRUBBER_INSUFFICIENT_PERMISSIONS (0x0000001b) #define NVCBA2_ERROR_SCRUBBER_MUTEX_ACQUIRE_FAILURE (0x0000001c) +#define NVCBA2_ERROR_SCRUB_SIZE_MAX_EXCEEDED (0x0000001d) #ifdef __cplusplus }; /* extern "C" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h index 6e8cc5b113..2e8f0df44c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000client.h @@ -179,6 +179,30 @@ typedef struct NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS { NvBool bDuplicates; /* [out] - Returns true if duplicates */ } NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS; +/* + * NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL: + * + * Subscribes to the first accessible or provided channel. + * Subscription is valid throughout the lifetime of a client. + * + * devDescriptor [OPAQUE IN] + * devDescriptor is an IMEX file descriptor for UNIX RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + * + * channel [IN/OUT] + * Channel number to which the client is subscribed + * If -1 is passed, RM picks the first accessible channel. + */ +#define NV0000_CTRL_CMD_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL (0xd08) /* finn: Evaluated from "(FINN_NV01_ROOT_CLIENT_INTERFACE_ID << 8) | NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS { + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); + NvU32 channel; +} NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS; + /* _ctrl0000client_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h index ec89bb54ae..351222d0a6 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h @@ -1027,5 +1027,73 @@ typedef struct NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS { NV0000_CTRL_GPU_ACTIVE_DEVICE devices[NV0000_CTRL_GPU_MAX_ACTIVE_DEVICES]; } NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS; +/* + * NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID + * + * This command attaches the GPU with the given gpuId, similar to + * NV0000_CTRL_CMD_GPU_ATTACH_IDS. However, this command instructs the RM + * to perform the attach in the background. + * + * After calling this command, clients are expected to call + * NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID before performing any operation that + * depends on the GPU being attached. + * + * If the gpuId fails to attach, either this command or the subsequent + * NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID command may fail. + * + * If clients from multiple processes use this command or the + * NV0000_CTRL_CMD_GPU_ATTACH_IDS command to attach a gpuId, the RM ensures + * that the gpuId won't be detached until all processes have issued a call to + * NV0000_CTRL_CMD_GPU_DETACH_IDS to detach the gpuId (or have terminated). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID (0x289U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS_MESSAGE_ID (0x89U) + +typedef struct NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS { + NvU32 gpuId; +} NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS; + +/* + * NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID + * + * This command waits for and returns the status of a background attach + * operation started by NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID. + * + * Clients are expected to call this command after calling + * NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID before performing any operation that + * depends on the GPU being attached. + * + * If the gpuId fails to attach, either this command or the previous + * NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID command may fail. + * + * Calling this command for a gpuId that is already attached (for example, + * after a successful NV0000_CTRL_CMD_GPU_ATTACH_IDS) is a no-op. + * + * Calling this command for a gpuId that is neither attached nor has a + * background attach operation will result in NV_ERR_INVALID_ARGUMENT. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OPERATING_SYSTEM + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_IRQ_EDGE_TRIGGERED + * NV_ERR_IRQ_NOT_FIRING + */ +#define NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID (0x290U) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID" */ + +#define NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS_MESSAGE_ID (0x90U) + +typedef struct NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS { + NvU32 gpuId; +} NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS; + /* _ctrl0000gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h index 1c9b6d0425..42c8e0908c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -202,8 +202,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS { * Vendor defined Model and Extended Model combined * stepping * Silicon stepping - * bSEVEnabled - * Secure Encrypted Virtualization enabled/disabled state + * bCCEnabled + * Confidentail compute enabled/disabled state * * Possible status values returned are: * NV_OK @@ -227,7 +227,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { NvU32 model; /* Vendor defined Model and Extended Model combined */ NvU8 stepping; /* Silicon stepping */ NvU32 coresOnDie; /* cpu cores per die */ - NvBool bSEVEnabled; /* SEV enabled on cpu */ + NvBool bCCEnabled; /* CC enabled on cpu */ } NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS; // Macros for CPU family information @@ -418,28 +418,6 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS { -/* - * NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE - * - * This command is used to set the system memory size in pages. - * - * memorySize - * This parameter specifies the system memory size in pages. All values - * are considered legal. - * - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_PARAM_STRUCT - */ -#define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */ - -#define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS { - NvU32 memorySize; -} NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS; - /* * NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES * @@ -467,7 +445,7 @@ typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS { * NV_ERR_NOT_SUPPORTED */ -#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */ +#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */ #define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U) @@ -1092,6 +1070,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { NvU32 p2pOptimalWriteCEs; NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8); + NV_DECLARE_ALIGNED(NvP64 busEgmPeerIds, 8); } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS; /* valid p2pCaps values */ @@ -1225,6 +1204,11 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS { * busPeerIds[X * gpuCount + Y] maps from index X to index Y in * the gpuIds[] table. For invalid or non-existent peer busPeerIds[] * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. + * [out] busEgmPeerIds + * EGM Peer ID matrix. It is a one-dimentional array. + * busEgmPeerIds[X * gpuCount + Y] maps from index X to index Y in + * the gpuIds[] table. For invalid or non-existent peer busEgmPeerIds[] + * has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER. * * Possible status values returned are: * NV_OK @@ -1246,6 +1230,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS { NvU32 p2pOptimalWriteCEs; NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE]; NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; + NvU32 busEgmPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED]; } NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS; /* @@ -2178,8 +2163,6 @@ typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS { #define CONTROLLER_FILTER_TYPE_MOVING_MAX 1U /* Valid NVPCF subfunction case */ -#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE 0U -#define NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE 1U #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE 2U #define NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE 3U diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h index 4b39094270..153cfb8ee5 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -68,4 +68,52 @@ typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS { NvU32 maxNumHztSlices; NvU32 lineBufferBitDepth; } NV0073_CTRL_CMD_DSC_CAP_PARAMS; + +/* + * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. This parameter must specify a value between zero and the + * total number of subdevices within the parent device. This parameter + * should be set to zero for default behavior + * cmd + * This parameter is an input to this command. + * Here are the current defined fields: + * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER + * Set to specify what operation to run. + * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP + * Request to power up pad. + * NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN + * Request to power down the pad. + * linkBw + * This parameter is used to pass in the link bandwidth required to run the + * power up sequence. Refer enum DM_FRL_LINK_RATE_GBPS for valid values. + * laneCount + * This parameter is used to pass the lanecount. + * sorIndex + * This parameter is used to pass the SOR index. + * padlinkIndex + * This parameter is used to pass the padlink index for primary link. + * Please refer enum DFPPADLINK for valid index values for Link A~F. + */ + +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD (0x730502U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID << 8) | NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS { + NvU32 subDeviceInstance; + NvU32 cmd; + NvU32 linkBw; + NvU32 laneCount; + NvU32 sorIndex; + NvU32 padlinkIndex; +} NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS; + +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER 0:0 +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP (0x00000000U) +#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN (0x00000001U) + /* _ctrl0073common_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h index 63f462763a..537c0c75eb 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h @@ -946,7 +946,6 @@ typedef struct NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS { #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_NO 0x00000000U #define NV0073_CTRL_DFP_DISP_MUX_FLAGS_SKIP_BACKLIGHT_ENABLE_YES 0x00000001U - #define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MIN 0U #define NV0073_CTRL_DISP_MUX_BACKLIGHT_BRIGHTNESS_MAX 100U @@ -1288,4 +1287,33 @@ typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS { +/* + * NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD + * + * This command is called when we want to inform RM of driver + * unload. + * + * subDeviceInstance (in) + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation + * should be directed. + * displayId (in) + * This parameter inputs the displayId of the active display. A value + * of zero indicates no display is active. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV0073_CTRL_CMD_DFP_EDP_DRIVER_UNLOAD (0x731174U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS_MESSAGE_ID (0x74U) + +typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; +} NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS; + /* _ctrl0073dfp_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h index 8f3f292173..fe9e6a9b98 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h @@ -771,41 +771,51 @@ typedef NV0073_CTRL_DP_LANE_DATA_PARAMS NV0073_CTRL_DP_SET_LANE_DATA_PARAMS; /* * NV0073_CTRL_DP_CSTM * - * This structure specifies the 80 bit DP CSTM Test Pattern data - * The fields of this structure are to be specified as follows: - * lower takes bits 31:0 - * middle takes bits 63:32 - * upper takes bits 79:64 - * + * This structure specifies - + * A) 80 bit DP CSTM Test Pattern data for DP1.x (HBR2 + 8b/10b channel coding) + * The fields of this structure are to be specified as follows: + * field_31_0 takes bits 31:0 + * field_63_32 takes bits 63:32 + * field_95_64 takes bits 79:64 + * B) 264 bit DP CSTM Test Pattern data for DP2.x (128b/132b channel coding) + * The fields of this structure are to be specified as follows: + * field_31_0 contains bits 31:0 + * field_63_32 contains bits 63:32 + * field_95_64 contains bits 95:64 + * field_127_95 contains bits 127:95 + * field_159_128 contains bits 159:128 + * field_191_160 contains bits 191:160 + * field_223_192 contains bits 223:192 + * field_255_224 contains bits 255:224 + * field_263_256 contains bits 263:256 */ typedef struct NV0073_CTRL_DP_CSTM { - NvU32 lower; - NvU32 middle; - NvU32 upper; + NvU32 field_31_0; + NvU32 field_63_32; + NvU32 field_95_64; + NvU32 field_127_95; + NvU32 field_159_128; + NvU32 field_191_160; + NvU32 field_223_192; + NvU32 field_255_224; + NvU32 field_263_256; } NV0073_CTRL_DP_CSTM; +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2 15:0 +#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM8 7:0 + + /* * NV0073_CTRL_DP_TESTPATTERN * - * This structure specifies the possible test patterns available in - * display port. The field testPattern can be one of the following - * values. - * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_NONE - * No test pattern on the main link - * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_D10_2 - * D10.2 pattern on the main link - * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_SERMP - * SERMP pattern on main link - * NV0073_CTRL_DP_SET_TESTPATTERN_DATA_PRBS_7 - * PRBS7 pattern on the main link - * + * This structure specifies the possible test patterns available in display port. */ typedef struct NV0073_CTRL_DP_TESTPATTERN { NvU32 testPattern; } NV0073_CTRL_DP_TESTPATTERN; -#define NV0073_CTRL_DP_TESTPATTERN_DATA 2:0 +#define NV0073_CTRL_DP_TESTPATTERN_DATA 4:0 #define NV0073_CTRL_DP_TESTPATTERN_DATA_NONE (0x00000000U) #define NV0073_CTRL_DP_TESTPATTERN_DATA_D10_2 (0x00000001U) #define NV0073_CTRL_DP_TESTPATTERN_DATA_SERMP (0x00000002U) @@ -813,6 +823,20 @@ typedef struct NV0073_CTRL_DP_TESTPATTERN { #define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM (0x00000004U) #define NV0073_CTRL_DP_TESTPATTERN_DATA_HBR2COMPLIANCE (0x00000005U) #define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT3 (0x00000006U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING1 (0x00000007U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING2 (0x00000008U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING3 (0x00000009U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_TRAINING4 (0x0000000AU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CP2520PAT1 (0x0000000BU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS1 (0x0000000CU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_128B132B_TPS2 (0x0000000DU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_9 (0x0000000EU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_11 (0x0000000FU) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_15 (0x00000010U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_23 (0x00000011U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_PRBS_31 (0x00000012U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_SQNUM (0x00000013U) +#define NV0073_CTRL_DP_TESTPATTERN_DATA_CSTM_264 (0x00000014U) /* * NV0073_CTRL_CMD_DP_SET_TESTPATTERN @@ -880,10 +904,6 @@ typedef struct NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS { #define NV0073_CTRL_CMD_DP_SET_TESTPATTERN (0x731347U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_MESSAGE_ID" */ -#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM0 31:0 -#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM1 63:32 -#define NV0073_CTRL_DP_SET_TESTPATTERN_PARAMS_CSTM2 15:0 - /* * NV0073_CTRL_CMD_GET_DP_TESTPATTERN * @@ -2816,244 +2836,5 @@ typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS { NvU16 prodId; } NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS; -/* - * NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL - * - * This command is used to trigger link training on DP2.x device with 128b132b channel encoding. - * - * subDeviceInstance - * This parameter specifies the subdevice instance within the - * NV04_DISPLAY_COMMON parent device to which the operation should be - * directed. This parameter must specify a value between zero and the - * total number of subdevices within the parent device. This parameter - * should be set to zero for default behavior. - * - * displayId - * This parameter specifies the ID of the display for which the dfp - * caps should be returned. The display ID must a dfp display. - * If more than one displayId bit is set or the displayId is not a dfp, - * this call will return NV_ERR_INVALID_ARGUMENT. - * - * cmd - * This parameter is an input to this command. - * Here are the current defined fields: - * 1.Ask RM to enter specific stage - * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING - * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ - * _CDS - * _SET_* only valid if _SETTING_TRUE - * - * 2.Ask RM to check the completion of specific stage - * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING - * NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE - * _CHNL_EQ_INTERLANE_ALIGN - * _CDS - * _POLL_* only valid if _POLLING_TRUE - * - * _SETTING_TRUE and _POLLING_TRUE are mutual exclusive. - * RM will return NV_ERR_INVALID_ARGUMENT if both bit are set. - * - * 3.Downspread configuration - * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD - * Specifies whether RM should be forced to enable or disable the DP - * Downspread setting. This can be used along with the Fake link - * training option so that we can configure the GPU to enable/disable - * spread when a real display is not connected. - * - * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (default behavior) - * RM will enable Downspread when the display supports it. - * NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES - * RM will enable/disable Downspread according to _SET_DOWNSPREAD field. - * - * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD - * Specifies if RM should enable or disable downspread. - * Only valid when _FORCED_DOWNSPREAD is set to _YES - * - * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE - * RM will enable Downspread even if the display does not support it. - * NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE - * RM will not enable Downspread even if the display does support it. - * - * 4.NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING - * This field specifies if fake link training is to be done. This will - * program enough of the hardware to avoid any hardware hangs and - * depending upon option chosen by the client, OR will be enabled for - * transmisssion. - * - * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO - * No Fake LT will be performed - * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION - * SOR will be not powered up during Fake LT - * NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON - * SOR will be powered up during Fake LT - * - * 5.NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG - * - * 6.NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING - * Specifies whether RM should skip HW training of the link. - * If this is the case then RM only updates its SW state without actually - * touching any HW registers. Clients should use this ONLY if it has determined - - * a. link is trained and not lost - * b. desired link config is same as current trained link config - * c. link is not in D3 (should be in D0) - * - * NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO - * RM doesn't skip HW LT as the current Link Config is not the same as the - * requested Link Config. - * NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES - * RM skips HW LT and only updates its SW state as client has determined that - * the current state of the link and the requested Link Config is the same. - * data - * This parameter is an input and output to this command. - * Here are the current defined fields: - * NV0073_CTRL_DP2X_DATA_LANE_COUNT - * Valid values: 0, 1, 2, 4 - * NV0073_CTRL_DP2X_DATA_LINK_BW - * Valid values: all standard link rates defined in DP2.x and ILRs defined in eDP spec. - * - * pollingInfo - * This parameter is an output to this command. - * Here are the current defined fields: - * - * NV0073_CTRL_DP2X_POLLING_INFO_CHNL_EQ_INTERVAL - * For Channel equalization, the polling interval is defined in DPCD 0x2216. - * RM report to DPLib when _SET_STAGE is set to _CHNL_EQ. - * (For CDS stage, the polling interval is fixed at 3ms.) - * - * NV0073_CTRL_DP2X_POLLING_INFO_RESULT - * _DONE: if the specified stage is done. - * _PENDING: if the specified stage is still pending. - * - * err - * This parameter specifies provides info regarding the outcome - * of this calling control call. If zero, no errors were found. - * Otherwise, this parameter will specify the error detected. - * The valid parameter is broken down as follows: - * NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE - * If set to _ERR, link training failed at channel equalization phase. - * NV0073_CTRL_DP2X_ERR_CDS_DONE - * If set to _ERR, link training failed at CDS phase. - * NV0073_CTRL_DP2X_ERR_TIMEOUT - * If set to _ERR, link training failed because of timeout. - * NV0073_CTRL_DP2X_ERR_LT_FAILED - * If set to _ERR, link training failed. - * NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER - * If set to _ERR, link configuration or displayID is invalid. - * NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT - * If set to _ERR, link training failed when setting lane count. - * NV0073_CTRL_DP2X_ERR_SET_LINK_BW - * If set to _ERR, link training failed when setting link rate. - * NV0073_CTRL_DP2X_ERR_ENABLE_FEC - * If set to _ERR, link training failed when enabling FEC. - * NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR - * If set to _ERR, link training failed when setting LTTPR. - * NV0073_CTRL_DP2X_ERR_PRE_LT - * If set to _ERR, link training failed before link training start. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - * NVOS_STATUS_ERROR - */ - -#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL (0x731383U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID" */ -#define NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS_MESSAGE_ID (0x83U) - -typedef struct NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS { - NvU32 subDeviceInstance; - NvU32 displayId; - NvU32 cmd; - NvU32 data; - NvU32 pollingInfo; - NvU32 err; -} NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS; - -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING 0:0 -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_FALSE (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SETTING_TRUE (0x00000001U) -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET 1:1 -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CHNL_EQ (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_SET_CDS (0x00000001U) -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING 8:8 -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_FALSE (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLLING_TRUE (0x00000001U) -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL 10:9 -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_DONE (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CHNL_EQ_INTERLANE_ALIGN (0x00000001U) -#define NV0073_CTRL_DP2X_CMD_LINK_TRAINING_POLL_CDS (0x00000002U) - -// Flags for link training. -#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD 16:16 -#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_NO (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_FORCED_DOWNSPREAD_YES (0x00000001U) -#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD 17:17 -#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_DISABLE (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_SET_DOWNSPREAD_ENABLE (0x00000001U) -#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING 18:18 -#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U) -#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING 20:19 -#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_NO (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U) -#define NV0073_CTRL_DP2X_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U) -#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG 21:21 -#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_FALSE (0x00000000U) -#define NV0073_CTRL_DP2X_CMD_FALLBACK_CONFIG_TRUE (0x00000001U) - -// Basic Data for Link training: Lane count and bandwidth. -#define NV0073_CTRL_DP2X_DATA_LANE_COUNT 3:0 -#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_0 (0x00000000U) -#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_1 (0x00000001U) -#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_2 (0x00000002U) -#define NV0073_CTRL_DP2X_DATA_LANE_COUNT_4 (0x00000004U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW 7:4 -#define NV0073_CTRL_DP2X_DATA_LINK_BW_1_62GBPS (0x00000001U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_16GBPS (0x00000002U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_43GBPS (0x00000003U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_2_70GBPS (0x00000004U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_3_24GBPS (0x00000005U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_4_32GBPS (0x00000006U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_5_40GBPS (0x00000007U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_6_75GBPS (0x00000008U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_8_10GBPS (0x00000009U) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR10_0 (0x0000000AU) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR13_5 (0x0000000BU) -#define NV0073_CTRL_DP2X_DATA_LINK_BW_UHBR20_0 (0x0000000CU) - -#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ 0:0 -#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_DONE (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_CHANNEL_EQ_FAILED (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_CDS 1:1 -#define NV0073_CTRL_DP2X_ERR_CDS_DONE (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_CDS_FAILED (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_TIMEOUT 2:2 -#define NV0073_CTRL_DP2X_ERR_TIMEOUT_NO (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_TIMEOUT_YES (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_LT_FAILED 3:3 -#define NV0073_CTRL_DP2X_ERR_LT_FAILED_NO (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_LT_FAILED_YES (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER 4:4 -#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_NOERR (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_INVALID_PARAMETER_ERR (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT 5:5 -#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_NOERR (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_SET_LANE_COUNT_ERR (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW 6:6 -#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_NOERR (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_SET_LINK_BW_ERR (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC 7:7 -#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_NOERR (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_ENABLE_FEC_ERR (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR 8:8 -#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_NOERR (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_CONFIG_LTTPR_ERR (0x00000001U) -#define NV0073_CTRL_DP2X_ERR_PRE_LT 9:9 -#define NV0073_CTRL_DP2X_ERR_PRE_LT_NOERR (0x00000000U) -#define NV0073_CTRL_DP2X_ERR_PRE_LT_ERR (0x00000001U) - -#define NV0073_CTRL_DP2X_POLLING_INFO_CHNL_EQ_INTERVAL 7:0 -#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT 31:31 -#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_PENDING (0x00000001U) -#define NV0073_CTRL_DP2X_POLLING_INFO_RESULT_DONE (0x00000000U) /* _ctrl0073dp_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h index bc419e1e6b..bd7c235079 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h @@ -30,6 +30,7 @@ #include "ctrl/ctrl0073/ctrl0073base.h" #include "ctrl/ctrl0073/ctrl0073system.h" +#include "ctrl/ctrl0073/ctrl0073dfp.h" #define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */ @@ -43,4 +44,22 @@ typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_ typedef NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS; +#define NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX (0x730460U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x3U) + +typedef NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX_PARAMS; + +#define NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS (0x730404U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x4U) + +typedef NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS; + +#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL (0x730405U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID (0x5U) + +typedef NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS; + /* ctrl0073internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h index 4bcf0bee89..8812d26734 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h @@ -126,8 +126,8 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_TYPE_PARAMS { * Perform the read and return an unadulterated EDID. * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE * A client uses this field to indicate whether to read EDID - * from SBIOS using ACPI sub function for display dynamic switching - * feature. This flag should only be set on internal display with + * from SBIOS using ACPI sub function for display dynamic switching + * feature. This flag should only be set on internal display with * dynamic switching feature enabled. * Possible values are: * NV0073_CTRL_SPECIFIC_GET_EDID_FLAGS_DISPMUX_READ_MODE_ACPI @@ -789,10 +789,10 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS { * It is temporal and will be deprecated soon. * packetSize * packet size of packets in pPacket to send, including header and payload. - * targetHead - * Specifies the target head number for which SDP needs to be updated. + * targetHead + * Specifies the target head number for which SDP needs to be updated. * bUsePsrHeadforSdp - * Indicates use targetHead field for setting SDP or infoframe packet instead + * Indicates use targetHead field for setting SDP or infoframe packet instead * of deriving the active head from displayID. * pPacket * pPacket points to the packets to send. @@ -1346,7 +1346,7 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_MONITOR_POWER_PARAMS { * For FRL 4-lane configuration and 10 Gbps bandwidth per lane. * NV0073_CTRL_HDMI_FRL_DATA_SET_FRL_RATE_4LANES_12G * For FRL 4-lane configuration and 12 Gbps bandwidth per lane. -* On return, the link bandwidth setting is returned which may be +* On return, the link bandwidth setting is returned which may be * different from the requested input setting. * bFakeLt * This flag as input to this command. @@ -1406,7 +1406,7 @@ typedef struct NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS_PARAMS { * NV0073_CTRL_CMD_SPECIFIC_GET_REGIONAL_CRCS * * This command is used to capture the active viewport region CRCs - * + * * [in]subDeviceInstance * This parameter specifies the subdevice instance within the * NV04_DISPLAY_COMMON parent device to which the operation should be @@ -1502,13 +1502,13 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_GPU_CAPS_PARAMS { /* * NV0073_CTRL_CMD_SPECIFIC_DISPLAY_CHANGE - * + * * Notifies the system that a display change is about to begin/end. * Also performs the necessary synchronizations for the same. - * + * * The command takes a NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS structure as an * argument with appropriate subDeviceInstance. - * + * * [in]subDeviceInstance * The sub-device instance * [in]newDevices @@ -1555,7 +1555,7 @@ typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS { * NV04_DISPLAY_COMMON parent device to which the operation should be * directed. * displayId - * This parameter specifies the displayId of HDMI sink. + * This parameter specifies the displayId of HDMI sink. * offset * This parameter specifies the SCDC offset which the read operation * should be used. @@ -1639,7 +1639,7 @@ typedef struct NV0073_CTRL_SPECIFIC_IS_DIRECTMODE_DISPLAY_PARAMS { * This parameter specifies the command for the HDMI FRL capacity computation. * [in] input * This parameter specifies the input data for the HDMI FRL capacity - * computation. + * computation. * [out] result * This indicates the computation result of HDMI FRL capacity computation. * [in/out] preCalc @@ -1727,7 +1727,7 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS { * This generic packets can be used for both HDMI and DP. * HW has added 6 new generic packets for each head because some usecases have * requirement to send infoframe in particular location (vsync, vblank, loadV). - * + * * Note: 1. Client first needs to reserve or acquire a free infoframe index * using NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET. * 2. Client needs to update the SDP index for head through control call @@ -1753,7 +1753,7 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS { * Set to _YES will cause new infoframe to be transmitted exactly once. * Set to _NO will cause new infoframe to be transmitted every frame. * NV0073_CTRL_SPECIFIC_SHARED_GENERIC_CTRL_LOC - * SDP can be sent in 3 different locations: + * SDP can be sent in 3 different locations: * VBLANK - new infoframe will be sent at Vblank. * VSYNC - new infoframe will be sent at Vsync. * LOADV - new infoframe will be triggered by LOADV, and sent at Vsync @@ -1765,9 +1765,9 @@ typedef struct NV0073_CTRL_SPECIFIC_GET_HDMI_FRL_CAPACITY_COMPUTATION_PARAMS { * _DISABLE: do not override shared generic infoframe subpacker DB1 bit3. * [in]packetSize * size of packets in Packet array to send, including header and payload. - * [in]infoframeIndex + * [in]infoframeIndex * Specifies the target head number for which SDP needs to be updated. - * [in]infoframeIndex + * [in]infoframeIndex * Specifies the index of infoframe. * [in]packet * pPacket points to the packets to send. @@ -1823,9 +1823,9 @@ typedef struct NV0073_CTRL_SPECIFIC_SET_SHARED_GENERIC_PACKET_PARAMS { /* * NV0073_CTRL_CMD_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET * - * This command is used to reserve the infoframe for head and RM would assign + * This command is used to reserve the infoframe for head and RM would assign * free infoframe index and return the index of infoframe. Later client needs - * to call control call NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET + * to call control call NV0073_CTRL_CMD_SPECIFIC_RELEASE_SHARED_GENERIC_PACKET * to release the index. * * [in]subDeviceInstance @@ -1871,7 +1871,7 @@ typedef struct NV0073_CTRL_SPECIFIC_ACQUIRE_SHARED_GENERIC_PACKET_PARAMS { * of subdevices within the parent device. This parameter should be set * to zero for default behavior. * [in]targetHeadIndex - * Specifies the target head number for which SDP needs to be updated. + * Specifies the target head number for which SDP needs to be updated. * [in]infoframeIndex * Infoframe index for the target head * Possible status values returned are: @@ -1994,4 +1994,96 @@ typedef struct NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS { NvBool bDefaultAdaptivesync; } NV0073_CTRL_SPECIFIC_DEFAULT_ADAPTIVESYNC_DISPLAY_PARAMS; +/* + * NV0073_CTRL_CMD_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM + * NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM + * These commands retrieve and set the brightness level and Local Tone Mapping (LTM) settings for + * the specified display. + * + * subDeviceInstance + * This parameter specifies the subdevice instance within the + * NV04_DISPLAY_COMMON parent device to which the operation should be + * directed. + * + * displayId + * Display for which brightness/LTM settings is to be retrieved or set. + * + * brightnessMilliNits + * the display brightness in the millinits units in the [0,10000000] range, inclusive. + * + * transitionTimeMs + * the transition time for display brightness to transition from current brightness level to the brightnessMilliNits + * + * bUncalibrated + * if true the parameter indicates brightnessMilliNits has to be interpreted as brightness % value, in 0.001% units + * + * bAdaptiveBrightness + * if true the brightnessMilliNits is set by the OS in the response to the ambient light sensor (ALS) input (if present on the system) + * + * bBoostRange + * if true the brightnessMilliNits value is set by the OS in the response to the ambient light sensor (ALS) input (if present on the system) + * Indicating very bright ambient light environment + * + * ambientIlluminance + * if bAdaptiveBrightness = true, ambientIlluminance represents an ambient illuminance value reported by the ALS sensor, in 0.001 Lux units + * + * ambientChromaticityX + * if bAdaptiveBrightness = true, ambientChromaticityX represents X chromaticity value reported by ALS sensor, in 0.001 units of [0,1] range + * + * ambientChromaticityY + * if bAdaptiveBrightness = true, ambientChromaticityY represents Y chromaticity value reported by ALS sensor, in 0.001 units of [0,1] range + * + * bLtmEnable + * if set to true, enable LTM functionality in GPU display HW. Set to true by default. + * + * bEnhanceContrast + * if bLtmEnable = true, and if set to true, enhance local contrast via LTM regardless of any other contrast enhancement driver policies. Set to false by default. + * + * contrastGain + * if bLtmEnable = true, this is used to how gain we need to apply on the contrast. + * + * detailGain + * if bLtmEnable = true, how much details needs to be boosted is indicated by this parameter. + * + * bContentAdaptiveBrightness + * if bLtmEnable = true, and if set to true, modify display backlight level and adjust pixel values dynamically on per-frame basis to perform content adaptive brightness control to reduce display power. Set to false by default. + * + * bDynamicHdrTonemapping + * if bLtmEnable = true, and if set to true, and output is HDR, enable dynamic per frame HDR tonemapping. Set to false by default. + * + * Possible status values returned include: + * NV_OK + * NV_ERR_NOT_SUPPORTED + */ + +typedef struct NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS { + NvU32 subDeviceInstance; + NvU32 displayId; + NvU32 brightnessMilliNits; + NvU32 transitionTimeMs; + NvBool bUncalibrated; + NvBool bAdaptiveBrightness; + NvBool bBoostRange; + NvU32 ambientIlluminance; + NvU32 ambientChromaticityX; + NvU32 ambientChromaticityY; + NvBool bEnhanceContrast; + NvU16 contrastGain; + NvU16 detailGain; + NvBool bContentAdaptiveBrightness; + NvBool bDynamicHdrTonemapping; +} NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS; + +#define NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID (0xAFU) + +typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM (0x7302afU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID (0xB0U) + +typedef NV0073_CTRL_SPECIFIC_DISPLAY_BRIGHTNESS_LTM_PARAMS NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS; + +#define NV0073_CTRL_CMD_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM (0x7302b0U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_DISPLAY_BRIGHTNESS_LTM_PARAMS_MESSAGE_ID" */ + /* _ctrl0073specific_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h index 91c9a50f78..bf598c0c5c 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h @@ -1468,8 +1468,8 @@ typedef struct NV0073_CTRL_SYSTEM_ARM_LIGHTWEIGHT_SUPERVISOR_PARAMS { * * bVrrDirty * When set to NV_TRUE, indicates that vrr configuration has been changed -* When set to NV_FALSE, this will indicate transitions from One shot mode to -* Continuous mode and vice versa +* When set to NV_FALSE, this will indicate transitions from One shot mode to +* Continuous mode and vice versa * * bVrrEnabled * When set to NV_TRUE, indicates that vrr has been enabled, i.e. vBp extended by 2 lines @@ -1541,7 +1541,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS { * because it exceeds the total bandwidth available to the system, or because * too much bandwidth is already allocated to other clients), the call will * fail and NV_ERR_INSUFFICIENT_RESOURCES will be returned. - * + * * If bandwidth has already been allocated via a prior call, and a new * allocation is requested, the new allocation will replace the old one. (If * the new allocation fails, the old allocation remains in effect.) @@ -1718,7 +1718,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS { * This parameter inputs the displayId of the active display. A value * of zero indicates no display is active. * bIsSidebandSrSupported - * If it is true, it means that sideband is supported and not PSR API. + * If it is true, it means that sideband is supported and not PSR API. * * Possible status values returned are: * NV_OK @@ -1755,7 +1755,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_SR_SUPPORT_PARAMS { * NV_ERR_GENERIC */ -/* +/* * This is the shared structure that will be used to communicate between * Physical RM and clients. As of now the access relies on single source of * truth operation, i.e. only Physical RM writes into the shared location @@ -1791,5 +1791,153 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS { NvHandle hMemory; } NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS; +/* + * NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL + * + * The VBlank Semaphore Control API ("VBlank Sem Control") allows clients to + * register for a semaphore release to be performed on the specified memory. + * + * One or more clients may register a memory allocation + offset by specifying + * _PARAMS::bEnabled = NV_TRUE and describing a video memory object with + * _PARAMS::hMemory and an offset within that memory object + * (_PARAMS::memoryOffset). Until the hMemory + memoryOffset combination is + * disabled by a subsequent call with bEnabled = NV_FALSE, during each vblank on + * the specified head, RM will interpret the specified memory location as an + * NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA data structure. + * + * _PARAMS::memoryOffset must be a multiple of 8, so that GPU semaphore releases + * and GSP can write to 8-byte fields within + * NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA with natural alignment. + * + * During vblank, the _CONTROL_DATA::control field will be read, and the + * following pseudocode will be performed: + * + * swapInterval = DRF_VAL(data->flags) + * useMinimumGpuTime = DRV_VAL(data->flags) + * + * if (data->requestCounter == prevRequestCounter) + * return + * + * if (currentVblankCount < (prevVBlankCount + swapInterval)) + * return + * + * if (useMinimumGpuTime && (data->minimumGpuTime < currentGpuTime)) + * return + * + * data->vblankCount = currentVblankCount + * data->releaseGpuTime = currentGpuTime + * data->semaphore = data->requestCounter + * + * prevRequestCounter = data->requestCounter + * previousVblankCount = currentVblankCount + * + * I.e., if the client-described conditions are met, the RM will write + * _CONTROL_DATA::semaphore to the client-requested 'requestCounter' along with + * several informational fields (vblankCount, releaseGpuTime). + * + * The intent is for clients to use semaphore releases to write: + * + * _CONTROL_DATA::minimumGpuTime (if desired) + * _CONTROL_DATA::swapInterval + * _CONTROL_DATA::requestCounter + * + * and then perform a semaphore acquire on _CONTROL_DATA::semaphore >= + * requestCounter (using the ACQ_GEQ semaphore operation). This will block any + * following methods in the client's channel (e.g., a blit) until the requested + * conditions are met. Note the ::requestCounter should be written last, + * because the change in value of ::requestCounter is what causes RM, during a + * vblank callback, to inspect the other fields. + * + * Additionally, clients should use the CPU (not semaphore releases in their + * channel) to write the field _CONTROL_DATA::requestCounterAccel at the same + * time that they enqueue the semaphore release to write to + * _CONTROL_DATA::requestCounter. ::requestCounterAccel will be used by resman + * to "accelerate" the vblank sem control by copying the value from + * ::requestCounterAccel to ::semaphore. This will be done when the vblank sem + * control is disabled, and when a client calls + * NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS. It is important for resman + * to have access to the value in ::requestCounterAccel, and not just + * ::requestCounter. The latter is only the last value released so far by the + * client's channel (further releases to ::requestCounter may still be inflight, + * perhaps blocked on pending semaphore acquires). The former should be the + * most recent value enqueued in the channel. This is also why it is important + * for clients to acquire with ACQ_GEQ (greater-than-or-equal-to), rather than + * just ACQUIRE. + * + * The same hMemory (with difference memoryOffsets) may be used by multiple + * VBlank Sem Controls. + */ + +/* Fields within NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA::flags */ +#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_SWAP_INTERVAL 15:0 +#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_USE_MINIMUM_GPU_TIME 16:16 + +typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA { + NvU32 requestCounterAccel; + NvU32 requestCounter; + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 minimumGpuTime, 8); + + NvU32 semaphore; + NV_DECLARE_ALIGNED(NvU64 vblankCount, 8); + NV_DECLARE_ALIGNED(NvU64 releaseGpuTime, 8); +} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA; + +#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL (0x73019fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS_MESSAGE_ID (0x9FU) + +typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS { + NvU32 subDeviceInstance; + NvBool bEnable; + NvU32 head; + NvHandle hMemory; + NV_DECLARE_ALIGNED(NvU64 memoryOffset, 8); +} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS; + +/* + * Accelerate all VBlank Sem Controls on the specified heads. + * + * For all enabled vblank sem controls on the specified heads, immediate set + * their pending ::semaphore fields to the value in their ::requestCounterAccel + * field. + */ +#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS (0x7301a2U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID (0xA2U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS { + NvU32 subDeviceInstance; + NvU32 headMask; +} NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS; + +/* + * Maps the memory allocated in Kernel RM into Physical RM using the + * memory descriptor information provided. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +typedef struct NV0073_CTRL_SHARED_MEMDESC_INFO { + NV_DECLARE_ALIGNED(NvU64 base, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 alignment, 8); + NvU32 addressSpace; + NvU32 cpuCacheAttrib; +} NV0073_CTRL_SHARED_MEMDESC_INFO; + +#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA (0x7301a3U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID" */ + +#define NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS_MESSAGE_ID (0xA3U) + +typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS { + NV_DECLARE_ALIGNED(NV0073_CTRL_SHARED_MEMDESC_INFO memDescInfo, 8); + NvU32 subDeviceInstance; + NvBool bMap; +} NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS; + /* _ctrl0073system_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h index 6243e21728..7d36ae0a57 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bif.h @@ -62,7 +62,8 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS { NvU32 flags; } NV0080_CTRL_BIF_RESET_PARAMS; -#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 3:0 + +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE 4:0 #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SW_RESET 0x1 #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_SBR 0x2 #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_FUNDAMENTAL 0x3 @@ -70,6 +71,7 @@ typedef struct NV0080_CTRL_BIF_RESET_PARAMS { #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BOOT_DEVICE 0x5 #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_PEX 0x6 #define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_OOBHUB_TRIGGER 0x7 +#define NV0080_CTRL_BIF_RESET_FLAGS_TYPE_BASE 0x8 /* * NV0080_CTRL_BIF_GET_DMA_BASE_SYSMEM_ADDR diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h index 48fb1e0502..45acad19e2 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h @@ -228,7 +228,36 @@ typedef struct NV0080_CTRL_FB_GET_CAPS_V2_PARAMS { NvU8 capsTbl[NV0080_CTRL_FB_CAPS_TBL_SIZE]; } NV0080_CTRL_FB_GET_CAPS_V2_PARAMS; +/** + * NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY + * + * When clients allocate video memory specifying _DEFAULT (0) for + * NVOS32_ATTR_PHYSICALITY, RM will usually allocate contiguous memory. + * Clients can change that behavior with this command so that _DEFAULT maps to + * another value. + * + * The expectation is that clients currently implicitly rely on the default, + * but can be incrementally updated to explicitly specify _CONTIGUOUS where + * necessary and change the default for their allocations to _NONCONTIGUOUS or + * _ALLOW_NONCONTIGUOUS. + * + * In the future RM may be updated to globally default to _NONCONTIGUOUS or + * _ALLOW_NONCONTIGUOUS, and at that point this can be removed. + */ +#define NV0080_CTRL_CMD_FB_SET_DEFAULT_VIDMEM_PHYSICALITY (0x801308) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_FB_INTERFACE_ID << 8) | NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS_MESSAGE_ID (0x8U) + +typedef struct NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS { + NvU32 value; +} NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS; +typedef enum NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY { + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT = 0, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS = 1, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS = 2, + NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS = 3, +} NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY; /* _ctrl0080fb_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h index 0a5e4e0c1d..bd68d2a427 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h @@ -190,7 +190,8 @@ typedef struct NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS { #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_GFXP_CTRL_BLK (0x00000016) #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_FECS_EVENT (0x00000017) #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PRIV_ACCESS_MAP (0x00000018) -#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x00000019) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP (0x00000019) +#define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT (0x0000001a) #define NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_MESSAGE_ID (0x7U) typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS { diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h index a115499697..0cacb00464 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gpu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -468,6 +468,9 @@ typedef struct NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS { * bNonPowerOf2ChannelCountSupported * Flag for whether non power of 2 VF channels are supported. * + * bVfResizableBAR1Supported + * Flag for whether Resizable VF BAR1 capability is supported. + * * Possible status values returned are: * NV_OK * NV_ERR_NOT_SUPPORTED @@ -494,11 +497,12 @@ typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS { NvBool bEmulateVFBar0TlbInvalidationRegister; NvBool bClientRmAllocatedCtxBuffer; NvBool bNonPowerOf2ChannelCountSupported; + NvBool bVfResizableBAR1Supported; } NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS; // Update this macro if new HW exceeds GPU Classlist MAX_SIZE -#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 160 +#define NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE 174 #define NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 (0x800292) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS_MESSAGE_ID" */ @@ -550,32 +554,32 @@ typedef struct NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS { /* * These are the per-VF BAR1 sizes that we support in MB. - * They are used with the NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE control call and - * should match the NV_XVE_BAR1_CONFIG_SIZE register defines. */ -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M 64 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M 128 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M 256 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M 512 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G 1024 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G 2048 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G 4096 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G 8192 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G 16384 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G 32768 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G 65536 -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G 131072 +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M (1 << 6) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128M (1 << 7) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256M (1 << 8) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_512M (1 << 9) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_1G (1 << 10) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_2G (1 << 11) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_4G (1 << 12) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_8G (1 << 13) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_16G (1 << 14) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_32G (1 << 15) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64G (1 << 16) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G (1 << 17) +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G (1 << 18) #define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MIN NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_64M -#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_128G +#define NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_MAX NV0080_CTRL_GPU_VGPU_VF_BAR1_SIZE_256G -#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID NV_U32_MAX +#define NV0080_CTRL_GPU_VGPU_NUM_VFS_INVALID 0x0 /* * NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE * * @brief Resize BAR1 per-VF on the given GPU - * vfBar1SizeMB[in] size of per-VF BAR1 size in MB - * numVfs[out] number of VFs that can be created given the new BAR1 size + * vfBar1SizeMB[in] Requested VF BAR1 size in MB + * numVfs[out] Number of VFs that can be created + * given the requested BAR1 size */ #define NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE (0x800296) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS_MESSAGE_ID" */ @@ -586,4 +590,60 @@ typedef struct NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS { NvU32 numVfs; } NV0080_CTRL_GPU_SET_VGPU_VF_BAR1_SIZE_PARAMS; +/* + * NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE + * + * This command set a value indicating vGPU heterogeneous mode. + * vGPU heterogeneous mode on a GPU can only be set when the command + * is running in a vGPU host device. + * + * bHeterogeneousMode + * This parameter set the vGPU heterogeneous mode of the device. + * Possible values are: + * NV_TRUE + * This value indicates that the device will be associated with vGPU heterogeneous mode. + * NV_FALSE + * This value indicates that the device will be removed from vGPU heterogeneous mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_IN_USE + * NV_ERR_NOT_SUPPORTED + */ + +#define NV0080_CTRL_CMD_GPU_SET_VGPU_HETEROGENEOUS_MODE (0x800297) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0x97U) + +typedef struct NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS { + NvBool bHeterogeneousMode; +} NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS; + +/** + * NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE + * + * This command returns a value indicating vGPU heterogeneous mode of + * the GPU. + * + * bHeterogeneousMode + * This parameter returns the vGPU heterogeneous mode of the device. + * Possible values are: + * NV_TRUE + * This value indicates that the device is associated with vGPU heterogeneous mode. + * NV_FALSE + * This value indicates that the device is not in vGPU heterogeneous mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV0080_CTRL_CMD_GPU_GET_VGPU_HETEROGENEOUS_MODE (0x800298) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_GPU_INTERFACE_ID << 8) | NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0x98U) + +typedef struct NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS { + NvBool bHeterogeneousMode; +} NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS; + /* _ctrl0080gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h index c15b4aaccc..22d0f48558 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h index 7155f17954..b1abacab6f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h @@ -30,7 +30,6 @@ // Source file: ctrl/ctrl0080/ctrl0080internal.finn // -#include "nvlimits.h" #include "ctrl0080gr.h" #include "ctrl0080fifo.h" #include "ctrl/ctrl0080/ctrl0080base.h" @@ -89,18 +88,6 @@ typedef struct NV0080_CTRL_CMD_INTERNAL_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS { -/*! - * @ref NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT - */ -#define NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT (0x802006) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID" */ - -#define NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS_MESSAGE_ID (0x6U) - -typedef struct NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS { - NvU8 powerDisconnectedGpuBus[NV_MAX_DEVICES]; - NvU8 powerDisconnectedGpuCount; -} NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS; - /* * NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h index fc5971c7a7..84a7983abc 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h @@ -68,6 +68,23 @@ typedef struct NV0080_CTRL_MSENC_GET_CAPS_PARAMS { /* size in bytes of MSENC caps table */ -#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4 +#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE 4 + +/* + * NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 + * + * This command is a version of NV0080_CTRL_CMD_MSENC_GET_CAPS with caps passed inline in capsTbl. + * + * For consistency with other video caps controls, it adds `instanceId` parameter. Currently it is + * ignored. + */ +#define NV0080_CTRL_CMD_MSENC_GET_CAPS_V2 (0x801b02) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_MSENC_INTERFACE_ID << 8) | NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID" */ + +#define NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS { + NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE]; + NvU32 instanceId; // ignored +} NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS; /* _ctrl0080msenc_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h index da58539df1..1768aa7a90 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -43,6 +43,21 @@ typedef struct NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS { } NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS; +/* + * This command sets the control information pertaining to Cuda limit. + * + * bCudaLimit + * When set to TRUE, clocks will be limited based on Cuda. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + */ +#define NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL (0x801909) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_PERF_INTERFACE_ID << 8) | NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS_MESSAGE_ID" */ + + /* _ctrl0080perf_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00e0.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00e0.h new file mode 100644 index 0000000000..1f34700d50 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00e0.h @@ -0,0 +1,158 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00e0.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "class/cl00e0.h" + +#define NV00E0_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00E0, NV00E0_CTRL_##cat, idx) + +/* NV00E0 command categories (6bits) */ +#define NV00E0_CTRL_RESERVED (0x00U) +#define NV00E0_CTRL_MEMORY_EXPORT (0x01U) + +/* + * NV00E0_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00E0_CTRL_CMD_NULL (0xe00000U) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + +/* + * NV00E0_CTRL_CMD_EXPORT_MEM + * + * Attaches memory handles to the export object. + * + * index [IN] + * Index into the export object at which to start attaching the provided + * memory handles. + * + * hParent [IN] + * Parent of memory handles to be attached (client or device or subdevice) + * If device or subdevice is used as parent, the related GPU is ref-counted + * by populating devDescriptor on behalf of the caller. + * + * handles [IN] + * Memory handles to be attached. + * + * numHandles [IN] + * Number of memory handles to be attached. + * + * devDescriptor [OPAQUE] + * devDescriptor is a file descriptor for unix RM clients, but a void + * pointer for windows RM clients. It is transparent to RM clients i.e. RM's + * user-mode shim populates this field on behalf of clients. + * + * Notes: + * - Imported fabric memory handles not supported. + * - No MIG support. + * - If 'numHandles' and 'index' overlap with a prior call, the newer call's + * RM handles will overwrite the attached handles from the previous call. + * This overlapping behavior can also be used to detach a handle by setting + * the appropriate object in 'handles' to 0. + */ +#define NV00E0_CTRL_CMD_EXPORT_MEM (0xe00101) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_EXPORT_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00E0_MAX_EXPORT_HANDLES 256 + +#define NV00E0_CTRL_EXPORT_MEM_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00E0_CTRL_EXPORT_MEM_PARAMS { + NvU16 index; + NvHandle hParent; + NvHandle handles[NV00E0_MAX_EXPORT_HANDLES]; + NvU16 numHandles; + NV_DECLARE_ALIGNED(NvU64 devDescriptor, 8); +} NV00E0_CTRL_EXPORT_MEM_PARAMS; + +/* + * NV00E0_CTRL_CMD_IMPORT_MEM + * + * Imports attached objects into the caller's RM client. + * + * index [IN] + * Index into the export object from which start importing. + * + * numHandles [IN] + * Number of memory handles to be imported. + * + * handles [IN] + * Handles to be used for importing. + * + * memInfos [OUT] + * Information of the imported objects + */ +#define NV00E0_CTRL_CMD_IMPORT_MEM (0xe00102) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_IMPORT_MEM_PARAMS_MESSAGE_ID" */ + +#define NV00E0_MAX_IMPORT_HANDLES 128 + +#define NV00E0_ADDR_SPACE_TYPE_SYSMEM 0x1 +#define NV00E0_ADDR_SPACE_TYPE_VIDMEM 0x2 +#define NV00E0_ADDR_SPACE_TYPE_FABRIC 0x3 +#define NV00E0_ADDR_SPACE_TYPE_FABRIC_MC 0x4 + +typedef struct NV_IMPORT_MEM_INFO { + NvHandle hParent; + NvU8 addrSpace; +} NV_IMPORT_MEM_INFO; + +#define NV00E0_CTRL_IMPORT_MEM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00E0_CTRL_IMPORT_MEM_PARAMS { + NvU16 index; + NvU16 numHandles; + NvHandle handles[NV00E0_MAX_IMPORT_HANDLES]; + NV_IMPORT_MEM_INFO memInfos[NV00E0_MAX_IMPORT_HANDLES]; +} NV00E0_CTRL_IMPORT_MEM_PARAMS; + +/* +* NV00E0_CTRL_CMD_GET_INFO +* +* Returns object information +* +* info [OUT] +* Same as NV00E0_ALLOCATION_PARAMETERS, see cl00e0.h for details. +*/ +#define NV00E0_CTRL_CMD_GET_INFO (0xe00103) /* finn: Evaluated from "(FINN_NV_MEMORY_EXPORT_INTERFACE_ID << 8) | NV00E0_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00E0_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00E0_CTRL_GET_INFO_PARAMS { + NV00E0_ALLOCATION_PARAMETERS info; +} NV00E0_CTRL_GET_INFO_PARAMS; + +/* _ctrl00e0_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00f1.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00f1.h new file mode 100644 index 0000000000..219d2a09da --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00f1.h @@ -0,0 +1,233 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00f1.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "class/cl00e0.h" + +/* + * NV00F1_CTRL_CMD_GET_FABRIC_EVENTS + * + * Queries the fabric object for events. + * + * eventArray [OUT] + * An array of import lifetime events. + * + * numEvents [OUT] + * The number of valid events in eventArray. + * + * bMoreEvents [OUT] + * Whether there are any remaining events to be queried. + * + * Possible status values returned are: + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV00F1_CTRL_CMD_GET_FABRIC_EVENTS (0xf10001U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS_MESSAGE_ID" */ + +/* Event types */ +#define NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_IMPORT 0U +#define NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_UNIMPORT 1U +#define NV00F1_CTRL_FABRIC_EVENT_TYPE_REMOTE_GPU_ATTACH 2U +#define NV00F1_CTRL_FABRIC_EVENT_TYPE_CLIQUE_ID_CHANGE 3U + +/* + * id + * Import ID. An import request can be uniquely identified using, + * . + * + * index + * Index of the export object to which the memory object is attached. + * + * exportNodeId + * ID of the exporter node where memory will be imported. + * + * exportUuid + * Universally unique identifier of the export object. This is extracted + * from a fabric packet. + * + + */ +typedef struct NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA { + NV_DECLARE_ALIGNED(NvU64 id, 8); + NvU16 index; + NvU16 exportNodeId; + NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN]; +} NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA; + +/* + * importEventId + * ID of the corresponding import event. + * + * exportNodeId + * ID of the exporter node where memory will be unimported. + */ +typedef struct NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA { + NV_DECLARE_ALIGNED(NvU64 importEventId, 8); + NvU16 exportNodeId; +} NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA; + +/* + * gpuFabricProbeHandle [IN] + * Fabric probe handle of the remote GPU + * + * key [IN] + * Key is used by the GFM in the MCFLA team response as an ID to allow the + * RM to correlate it with the MCFLA team request. + * + * cliqueId [IN] + * Clique ID of the remote GPU being attached. + * + * index + * Index of the export object to which the memory object is attached. + * + * exportNodeId + * ID of the exporter node where memory will be imported. + * + * exportUuid + * Universally unique identifier of the export object. This is extracted + * from a fabric packet. + */ +typedef struct NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA { + NV_DECLARE_ALIGNED(NvU64 gpuFabricProbeHandle, 8); + NV_DECLARE_ALIGNED(NvU64 key, 8); + NvU32 cliqueId; + NvU16 index; + NvU16 exportNodeId; + NvU8 exportUuid[NV_MEM_EXPORT_UUID_LEN]; +} NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA; + +/* + * gpuId + * GPU ID of the GPU whose cliqueID has changed. + * + * cliqueId + * Clique ID of the GPU. + */ +typedef struct NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA { + NvU32 gpuId; + NvU32 cliqueId; +} NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA; + +/* + * type + * Event type, one of NV00F1_CTRL_FABRIC_EVENT_TYPE_*. + * + * id + * A monotonically increasing event ID. + * + * imexChannel + * imex channel subscribed by the caller. + * + * data + * Event data + */ +typedef struct NV00F1_CTRL_FABRIC_EVENT { + NvU8 type; + NV_DECLARE_ALIGNED(NvU64 id, 8); + NvU32 imexChannel; + + union { + NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_MEM_IMPORT_EVENT_DATA import, 8); + NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_MEM_UNIMPORT_EVENT_DATA unimport, 8); + NV_DECLARE_ALIGNED(NV00F1_CTRL_ATTACH_REMOTE_GPU_EVENT_DATA attach, 8); + NV00F1_CTRL_CLIQUE_ID_CHANGE_GPU_EVENT_DATA cliqueIdChange; + } data; +} NV00F1_CTRL_FABRIC_EVENT; + +#define NV00F1_CTRL_GET_FABRIC_EVENTS_ARRAY_SIZE 128U + +#define NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS { + NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_EVENT eventArray[NV00F1_CTRL_GET_FABRIC_EVENTS_ARRAY_SIZE], 8); + NvU32 numEvents; + NvBool bMoreEvents; +} NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS; + +/* + * NV00F1_CTRL_CMD_FINISH_MEM_UNIMPORT + * + * Notifies the unimport sequence is finished. + * + * tokenArray [IN] + * An array of tokens that finished the unimport sequence. + * + * numTokens [IN] + * The number of valid tokens in the tokenArray. + * + * Possible status values returned are: + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV00F1_CTRL_CMD_FINISH_MEM_UNIMPORT (0xf10002U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS_MESSAGE_ID" */ + +/* + * unimportEventId + * ID of the unimport event. + */ +typedef struct NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN { + NV_DECLARE_ALIGNED(NvU64 unimportEventId, 8); +} NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN; + +#define NV00F1_CTRL_FINISH_MEM_UNIMPORT_ARRAY_SIZE 256U + +#define NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS { + NV_DECLARE_ALIGNED(NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN tokenArray[NV00F1_CTRL_FINISH_MEM_UNIMPORT_ARRAY_SIZE], 8); + NvU32 numTokens; +} NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS; + +/* + * NV00F1_CTRL_CMD_DISABLE_IMPORTERS + * + * Disables clients which imported memory from the given nodeId. Channel + * recovery (disablement) sequence is also invoked to halt fabric traffic + * from these clients. + * + * nodeId [IN] + * An array of tokens that finished the unimport sequence. + * + * Possible status values returned are: + * NV_ERR_NOT_SUPPORTED + * NV_OK + */ +#define NV00F1_CTRL_CMD_DISABLE_IMPORTERS (0xf10003U) /* finn: Evaluated from "(FINN_IMEX_SESSION_INTERFACE_ID << 8) | NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS_MESSAGE_ID" */ + +#define NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS_MESSAGE_ID (0x3U) + +typedef struct NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS { + NvU16 nodeId; +} NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS; + +/* _ctrl00f1.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h index 240593aeca..b9c221ff68 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h @@ -205,7 +205,8 @@ typedef struct NV00F8_CTRL_ATTACH_MEM_INFO { * * Restrictions: * a. Physical memory with 2MB pagesize is allowed - * b. Only vidmem physical memory handle can be attached + * b. vidmem and sysmem with fixed node ID can be attached. + * sysmem with fixed node ID is supported only if EGM is enabled. * c. Supported only for flexible fabric objects. */ #define NV00F8_CTRL_CMD_ATTACH_MEM (0xf80103) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00F8_CTRL_ATTACH_MEM_PARAMS_MESSAGE_ID" */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00f9.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00f9.h new file mode 100644 index 0000000000..a51caa5335 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00f9.h @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-22 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00f9.finn +// + +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl00f8.h" + +#define NV00F9_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x00f9, NV00F9_CTRL_##cat, idx) + +/* NV00F9 command categories (6bits) */ +#define NV00F9_CTRL_RESERVED (0x00U) +#define NV00F9_CTRL_IMPORT (0x01U) + +/* + * NV00F9_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00F9_CTRL_CMD_NULL (0xf90000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV00F9_CTRL_CMD_GET_INFO + * + * Queries memory allocation attributes. + * + * size [OUT] + * Size of the allocation. + * + * pageSize [OUT] + * Page size of the allocation + * + * memFlags [OUT] + * Flags associated with memory allocation. + * + * physAttrs [OUT] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + */ +#define NV00F9_CTRL_CMD_GET_INFO (0xf90101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID << 8) | NV00F9_CTRL_GET_INFO_PARAMS_MESSAGE_ID" */ + +#define NV00F9_CTRL_GET_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00F9_CTRL_GET_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 size, 8); + NV_DECLARE_ALIGNED(NvU64 pageSize, 8); + NvU32 memFlags; + NV_PHYSICAL_MEMORY_ATTRS physAttrs; +} NV00F9_CTRL_GET_INFO_PARAMS; + +/* _ctrl00f9_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fb.h new file mode 100644 index 0000000000..d995ffcc25 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fb.h @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-22 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrl00fb.finn +// + +#include "nvtypes.h" +#include "ctrl/ctrlxxxx.h" +#include "ctrl/ctrl00f8.h" + +#define NV00FB_CTRL_CMD(cat, idx) \ + NVXXXX_CTRL_CMD(0x00fb, NV00FB_CTRL_##cat, idx) + +/* NV00FB command categories (6bits) */ +#define NV00FB_CTRL_RESERVED (0x00U) +#define NV00FB_CTRL_IMPORT_REF (0x01U) + +/* + * NV00FB_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ +#define NV00FB_CTRL_CMD_NULL (0xfb0000U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID << 8) | 0x0" */ + + + + + +/* + * NV00FB_CTRL_CMD_VALIDATE + * + * Populate the imported memory, making it ready to map locally. + * + * attrs [IN] + * Attributes associated with memory allocation. + * + * physAttrs [IN] + * Physical attributes associated with memory allocation. + * For flexible mappings, it is not possible to retrieve this information, + * behavior is undefined (returns all zeros). + * + * offset [IN] + * Offset into memory allocation to query physical addresses for. + * + * totalPfns [IN] + * Number of PFNs in memory allocation. + * + * pfnArray [IN] + * Array of PFNs in memory allocation (2MB page size shifted). + * + * numPfns [IN] + * Number of valid entries in pfnArray. + * + * memFlags [IN] + * Flags associated with memory allocation. + * + * flags [IN] + * Flags to notify RM about errors during import. + * + * bDone [out] + * Whether the RM is expecting additional calls to _VALIDATE. + */ +#define NV00FB_CTRL_CMD_VALIDATE (0xfb0101U) /* finn: Evaluated from "(FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID << 8) | NV00FB_CTRL_VALIDATE_PARAMS_MESSAGE_ID" */ + +#define NV00FB_CTRL_VALIDATE_PFN_ARRAY_SIZE 512U + +#define NV00FB_CTRL_FLAGS_NONE 0U +#define NV00FB_CTRL_FLAGS_IMPORT_FAILED 1U + +#define NV00FB_CTRL_VALIDATE_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV00FB_CTRL_VALIDATE_PARAMS { + NV_DECLARE_ALIGNED(NV_FABRIC_MEMORY_ATTRS attrs, 8); + NV_PHYSICAL_MEMORY_ATTRS physAttrs; + NV_DECLARE_ALIGNED(NvU64 offset, 8); + NV_DECLARE_ALIGNED(NvU64 totalPfns, 8); + NvU32 pfnArray[NV00FB_CTRL_VALIDATE_PFN_ARRAY_SIZE]; + NvU32 numPfns; + NvU32 memFlags; + NvU32 flags; + NvBool bDone; +} NV00FB_CTRL_VALIDATE_PARAMS; + +/* _ctrl00fb_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h index 6a9f746c2d..79fbb1396e 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fd.h @@ -202,6 +202,53 @@ typedef struct NV00FD_CTRL_DETACH_MEM_PARAMS { NvU32 flags; } NV00FD_CTRL_DETACH_MEM_PARAMS; +/* + * NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU + * + * Attaches a remote GPU to the Multicast FLA object. This control call is + * restricted to the privileged clients like IMEX daemon. + * + * gpuFabricProbeHandle [IN] + * Fabric probe handle of the remote GPU + * + * key [IN] + * Key is used by the GFM in the MCFLA team response as an ID to allow the + * RM to correlate it with the MCFLA team request. + * + * cliqueId [IN] + * Clique ID of the remote GPU being attached. + * + * nodeId [IN] + * nodeID from which the remote GPU is being attached. + */ +#define NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU (0xfd0106) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS { + NV_DECLARE_ALIGNED(NvU64 gpuFabricProbeHandle, 8); + NV_DECLARE_ALIGNED(NvU64 key, 8); + NvU32 cliqueId; + NvU16 nodeId; +} NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS; + +/* + * NV00FD_CTRL_CMD_SET_FAILURE + * + * Marks the MCLFA object allocation with a failure. This control call is + * restricted to the privileged client like IMEX daemon. + * + * status [IN] + * Failure status, shouldn't be NV_OK. + */ +#define NV00FD_CTRL_CMD_SET_FAILURE (0xfd0107) /* finn: Evaluated from "(FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID << 8) | NV00FD_CTRL_SET_FAILURE_PARAMS_MESSAGE_ID" */ + +#define NV00FD_CTRL_SET_FAILURE_PARAMS_MESSAGE_ID (0x7U) + +typedef struct NV00FD_CTRL_SET_FAILURE_PARAMS { + NV_STATUS status; +} NV00FD_CTRL_SET_FAILURE_PARAMS; + /* _ctrl00fd_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h b/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h index 6c0b0ceba5..e80f7d8362 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl00fe.h @@ -30,35 +30,62 @@ // Source file: ctrl/ctrl00fe.finn // -#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION 0:0 -#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_PHYSICAL (0x00000000U) -#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_FLAG_PAGE_KIND_SOURCE_ALLOCATION_VIRTUAL (0x00000001U) +typedef enum NV00FE_CTRL_OPERATION_TYPE { + NV00FE_CTRL_OPERATION_TYPE_NOP = 0, // operation is ignored, used internally + NV00FE_CTRL_OPERATION_TYPE_MAP = 1, + NV00FE_CTRL_OPERATION_TYPE_UNMAP = 2, + NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_WAIT = 3, + NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_SIGNAL = 4, +} NV00FE_CTRL_OPERATION_TYPE; -typedef struct NV00FE_CTRL_PAGING_OPERATION { +typedef struct NV00FE_CTRL_OPERATION_MAP { NvHandle hVirtualMemory; NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8); NvHandle hPhysicalMemory; NV_DECLARE_ALIGNED(NvU64 physicalOffset, 8); NV_DECLARE_ALIGNED(NvU64 size, 8); - NvU32 flags; -} NV00FE_CTRL_PAGING_OPERATION; + NvU32 dmaFlags; // NVOS46_FLAGS +} NV00FE_CTRL_OPERATION_MAP; + +typedef struct NV00FE_CTRL_OPERATION_UNMAP { + NvHandle hVirtualMemory; + NV_DECLARE_ALIGNED(NvU64 virtualOffset, 8); + NV_DECLARE_ALIGNED(NvU64 size, 8); + NvU32 dmaFlags; // NVOS47_FLAGS +} NV00FE_CTRL_OPERATION_UNMAP; + +typedef struct NV00FE_CTRL_OPERATION_SEMAPHORE { + NvU32 index; + NV_DECLARE_ALIGNED(NvU64 value, 8); +} NV00FE_CTRL_OPERATION_SEMAPHORE; + +typedef struct NV00FE_CTRL_OPERATION { + NV00FE_CTRL_OPERATION_TYPE type; + + union { + NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_MAP map, 8); + NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_UNMAP unmap, 8); + NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION_SEMAPHORE semaphore, 8); + } data; +} NV00FE_CTRL_OPERATION; /* - * NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS + * NV00FE_CTRL_CMD_SUBMIT_OPERATIONS * - * Execute a list of paging operations + * Execute a list of mapping/semaphore operations * Page size is determined by the virtual allocation * Offsets/sizes must respect the page size * */ -#define NV00FE_CTRL_CMD_SUBMIT_PAGING_OPERATIONS (0xfe0002U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID" */ +#define NV00FE_CTRL_CMD_SUBMIT_OPERATIONS (0xfe0101U) /* finn: Evaluated from "(FINN_NV_MEMORY_MAPPER_INTERFACE_ID << 8) | NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS_MESSAGE_ID" */ -#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_MAX_COUNT (0x00010000U) +#define NV00FE_MAX_OPERATIONS_COUNT (0x00001000U) -#define NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS_MESSAGE_ID (0x2U) +#define NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS_MESSAGE_ID (0x1U) -typedef struct NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS { - NvU32 pagingOpsCount; - NV_DECLARE_ALIGNED(NvP64 pagingOps, 8); -} NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS; +typedef struct NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS { + NvU32 operationsCount; + NV_DECLARE_ALIGNED(NV00FE_CTRL_OPERATION pOperations[NV00FE_MAX_OPERATIONS_COUNT], 8); + NvU32 operationsProcessedCount; +} NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h index 25d3c2c8ed..47ffccf626 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -353,6 +353,8 @@ typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS { * This field returns the sku for the current chip. * chipSKUMod * This field returns the SKU modifier. + * skuConfigVersion + * Version number for the SKU configuration detailing pstate, thermal, VF curve and so on. * project * This field returns the Project (Board) number. * projectSKU @@ -369,15 +371,13 @@ typedef struct NV2080_CTRL_BIOS_GET_NBSI_OBJ_PARAMS { */ #define NV2080_CTRL_CMD_BIOS_GET_SKU_INFO (0x20800808) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BIOS_INTERFACE_ID << 8) | NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID" */ -/* maximum length of parameter strings */ - - #define NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_MESSAGE_ID (0x8U) typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS { NvU32 BoardID; - char chipSKU[4]; - char chipSKUMod[2]; + char chipSKU[9]; + char chipSKUMod[5]; + NvU32 skuConfigVersion; char project[5]; char projectSKU[5]; char CDP[6]; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h index d19a2f5c37..d8905557d1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ecc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -60,4 +60,80 @@ typedef struct NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS { NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotalCounts, 8); NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotalCounts, 8); } NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS; + +#define NV2080_CTRL_CMD_ECC_GET_ECI_COUNTERS (0x20803401U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS + * + * sramParityUncorrectedUnique [out] + * sramSecDedUncorrectedUnique [out] + * sramCorrectedTotal [out] + * dramUncorrectedTotal [out] + * dramCorrectedTotal [out] + * Aggregate error counts for SRAM and DRAM. + * + * lastClearedTimestamp [out] + * unix-epoch based timestamp. These fields indicate when the error counters + * were last cleared by the user. + * + * sramBucketL2 [out] + * sramBucketSM [out] + * sramBucketPcie [out] + * sramBucketFirmware [out] + * sramBucketOther [out] + * Aggregate unique uncorrctable error counts for SRAM buckets. + * + * sramErrorThresholdExceeded [out] + * Boolean flag which is set if SRAM error threshold was exceeded + */ + +#define NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 sramParityUncorrectedUnique, 8); + NV_DECLARE_ALIGNED(NvU64 sramSecDedUncorrectedUnique, 8); + NV_DECLARE_ALIGNED(NvU64 sramCorrectedTotal, 8); + NV_DECLARE_ALIGNED(NvU64 dramUncorrectedTotal, 8); + NV_DECLARE_ALIGNED(NvU64 dramCorrectedTotal, 8); + + NvU32 lastClearedTimestamp; + + NV_DECLARE_ALIGNED(NvU64 sramBucketL2, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketSM, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketPcie, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketFirmware, 8); + NV_DECLARE_ALIGNED(NvU64 sramBucketOther, 8); + + NvBool sramErrorThresholdExceeded; +} NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS; + +/* + * NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS + * + * Reports count of volatile errors + * + * sramCorUni [out]: + * Unique correctable SRAM error count + * sramUncParityUni [out]: + * Unique uncorrectable SRAM parity error count + * sramUncSecDedUni [out]: + * Unique uncorrectable SRAM SEC-DED error count + * dramCorTot [out]: + * Total correctable DRAM error count + * dramUncTot [out]: + * total uncorrectable DRAM error count + */ +#define NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS (0x20803402U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_ECC_INTERFACE_ID << 8) | NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS { + NV_DECLARE_ALIGNED(NvU64 sramCorUni, 8); + NV_DECLARE_ALIGNED(NvU64 sramUncParityUni, 8); + NV_DECLARE_ALIGNED(NvU64 sramUncSecDedUni, 8); + NV_DECLARE_ALIGNED(NvU64 dramCorTot, 8); + NV_DECLARE_ALIGNED(NvU64 dramUncTot, 8); +} NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS; + /* _ctrl2080ecc_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h index 6dfa610406..22c8981231 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h @@ -335,4 +335,39 @@ typedef struct NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS { NvBool bAllUsers; } NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS; + +/* + * NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_FOR_UID + * + * This command is used to create a RATS tracing bindpoint to eventbuffer. + * + * hEventBuffer[IN] + * The event buffer to bind to + * + * tracepointMask[IN] + * Bitmask for selecting tracepoints + * + * gspLoggingBufferSize[IN] + * User defined size of GSP owned event logging buffer + * + * gspLoggingBufferWatermark[IN] + * User defined watermark that triggers RPC to kernel of traces + * HINT: set higher for more frequent trace updates + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF (0x2080030a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS_MESSAGE_ID (0xAU) + +typedef struct NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS { + NvHandle hEventBuffer; + NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8); + NvU32 gspLoggingBufferSize; + NvU32 gspLoggingBufferWatermark; +} NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS; + /* _ctrl2080event_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h index c4558761a2..8dec1fd07f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h @@ -35,6 +35,7 @@ /* NV20_SUBDEVICE_XX fb control commands and parameters */ #include "nvlimits.h" +#include "nvcfg_sdk.h" /* * NV2080_CTRL_FB_INFO @@ -360,6 +361,8 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO; #define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/ #define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */ + + /* valid RAM LOCATION types */ #define NV2080_CTRL_FB_INFO_RAM_LOCATION_GPU_DEDICATED (0x00000000U) #define NV2080_CTRL_FB_INFO_RAM_LOCATION_SYS_SHARED (0x00000001U) @@ -519,8 +522,60 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS { } NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS; /* valid flags parameter values */ -#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) -#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_NONE (0x00000000U) +#define NV2080_CTRL_CMD_FB_GET_CAL_FLAG_RESET (0x00000001U) + +/* + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL + * + * If supported by hardware and the OS, this command implements a streamlined version of + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE which can be called at high IRQL and Bypass the + * RM Lock. + * + * Requires the following NVOS54_PARAMETERS to be set for raised IRQ / Lock Bypass operation: + * NVOS54_FLAGS_IRQL_RAISED + * NVOS54_FLAGS_LOCK_BYPASS + * + * flags + * Contains flags to control various aspects of the flush. Valid values + * are defined in NV2080_CTRL_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS*. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * + * See Also: + * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE + * This is the more generalized version which is not intended to be called at raised IRQ level + * NV0080_CTRL_CMD_DMA_FLUSH + * Performs flush operations in broadcast for the GPU cache and other hardware + * engines. Use this call if you want to flush all GPU caches in a + * broadcast device. + * NV0041_CTRL_CMD_SURFACE_FLUSH_GPU_CACHE + * Flushes memory associated with a single allocation if the hardware + * supports it. Use this call if you want to flush a single allocation and + * you have a memory object describing the physical memory. + */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL (0x2080130dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS { + NvU32 flags; +} NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_PARAMS; + +/* valid fields and values for flags */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK 0:0 +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_NO (0x00000000U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_WRITE_BACK_YES (0x00000001U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE 1:1 +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_NO (0x00000000U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_INVALIDATE_YES (0x00000001U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH 2:2 +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_NO (0x00000000U) +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL_FLAGS_FB_FLUSH_YES (0x00000001U) /* * NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE @@ -565,9 +620,9 @@ typedef struct NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS { * supports it. Use this call if you want to flush a single allocation and * you have a memory object describing the physical memory. */ -#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE (0x2080130eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U +#define NV2080_CTRL_FB_FLUSH_GPU_CACHE_MAX_ADDRESSES 500U #define NV2080_CTRL_FB_FLUSH_GPU_CACHE_PARAMS_MESSAGE_ID (0xEU) @@ -2294,6 +2349,34 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS { NV_DECLARE_ALIGNED(NvU64 fbpaSubpEnMask, 8); } NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS; +/*! + * Structure holding the in/out params for NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK. + */ +typedef struct NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS { + /*! + * [IN]: physical/local sys Id. + */ + NvU32 sysIdx; + /*! + * [OUT]: physical/local sysltc mask. + */ + NvU32 sysl2LtcEnMask; +} NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS; + +/*! + * Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PAC_MASK. + */ +typedef struct NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS { + /*! + * [IN]: physical/local FB partition index. + */ + NvU32 fbpIndex; + /*! + * [OUT]: physical/local PAC mask. + */ + NvU32 pacEnMask; +} NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS; + // Possible values for queryType #define NV2080_CTRL_FB_FS_INFO_INVALID_QUERY 0x0U #define NV2080_CTRL_FB_FS_INFO_FBP_MASK 0x1U @@ -2308,6 +2391,8 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS { #define NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK 0xAU #define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK 0xBU #define NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP 0xCU +#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK 0xDU +#define NV2080_CTRL_FB_FS_INFO_PAC_MASK 0xEU typedef struct NV2080_CTRL_FB_FS_INFO_QUERY { NvU16 queryType; @@ -2327,6 +2412,8 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY { NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS dmFbpaSubp, 8); NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS fbpaSubp; NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS fbpLogicalMap; + NV2080_CTRL_SYSL2_FS_INFO_SYSLTC_MASK_PARAMS sysl2Ltc; + NV2080_CTRL_FB_FS_INFO_PAC_MASK_PARAMS pac; } queryParams; } NV2080_CTRL_FB_FS_INFO_QUERY; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h index 88cccdf011..033d974964 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h @@ -30,6 +30,7 @@ // Source file: ctrl/ctrl2080/ctrl2080fifo.finn // +#include "nvcfg_sdk.h" #include "ctrl/ctrl2080/ctrl2080base.h" /* @@ -466,6 +467,94 @@ typedef struct NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS { #define NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_ATTRIBUTE_WRITECOMBINED 0X00000002 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_UNKNOWN 0 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER 1 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT 2 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE 3 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE 4 + +// Count of the supported vGPU scheduler policies +#define NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT 3 + +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DEFAULT 0 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_DISABLE 1 +#define NV2080_CTRL_CMD_VGPU_SCHEDULER_ARR_ENABLE 2 + +/* + * NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG + * + * This command returns the OBJSCHED_SW log enties. + * + * engineId + * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log + * entries are to be fetched. + * + * count + * This field returns the count of log entries fetched. + * + * entry + * The array of SW runlist log entries. + * + * timestampNs + * Timestamp in ns when this SW runlist was preeempted. + * + * timeRunTotalNs + * Total time in ns this SW runlist has run as compared to others. + * + * timeRunNs + * Time in ns this SW runlist ran before preemption. + * + * swrlId + * SW runlist Id. + * + * schedPolicy + * This field returns the runlist scheduling policy. It specifies the + * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. + * + * arrEnabled + * This field returns if Adaptive round robin scheduler + * is enabled/disabled. + * + * arrAvgFactor + * This field returns the average factor to be used in compensating the timeslice + * for Adaptive scheduler mode. + * + * targetTimesliceNs + * This field returns the target timeslice duration in ns for each SW runlist + * as configured by the user or the default value otherwise. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT +*/ + +#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SW_GET_LOG (0x2080110e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_OBJSCHED_SW_COUNT 32 +#define NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS 8 +#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES 200 + +#define NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS { + NvU32 engineId; + NvU32 count; + struct { + NV_DECLARE_ALIGNED(NvU64 timestampNs, 8); + NV_DECLARE_ALIGNED(NvS64 timeRunTotalNs, 8); + NvU32 timeRunNs; + NvU32 swrlId; + NvU32 targetTimeSlice; + NV_DECLARE_ALIGNED(NvU64 cumulativePreemptionTime, 8); + NV_DECLARE_ALIGNED(NvU64 counters[NV2080_CTRL_FIFO_OBJSCHED_SW_NCOUNTERS], 8); + } entry[NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_ENTRIES]; + NvU32 schedPolicy; + NvU32 arrEnabled; + NvU32 arrAvgFactor; + NvU32 targetTimesliceNs; +} NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS; + + /* * NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE @@ -783,6 +872,189 @@ typedef struct NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS { NvU32 bitMask[NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_MAX_CHANNELS / 32]; } NV2080_CTRL_FIFO_GET_ALLOCATED_CHANNELS_PARAMS; +/* + * NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION + * + * This command will disable and preempt channels described in the + * list provided and mark them ready for key rotation. + * hClient <-> hChannel pairs should use the same index in the arrays. + * + * numChannels + * The number of valid entries in hChannelList array. + * hClientList + * An array of NvHandle listing the client handles + * hChannelList + * An array of NvHandle listing the channel handles + * to be stopped. + * bEnableAfterKeyRotation + * This determines if channel is enabled by RM after it completes key rotation. + * Possible status values returned are: + * NV_OK + * NVOS_INVALID_STATE + */ +#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION (0x2080111a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES (64) + +#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS_MESSAGE_ID (0x1AU) + +typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS { + NvU32 numChannels; + NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; + NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES]; + NvBool bEnableAfterKeyRotation; +} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS; + + + +/* + * NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE + * + * This command returns the vGPU schedular state. + * + * engineId + * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log + * entries are to be fetched. + * + * schedPolicy + * This field returns the runlist scheduling policy. It specifies the + * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. + * + * arrEnabled + * This field returns if Adaptive round robin scheduler + * is enabled/disabled. + * + * targetTimesliceNs + * This field returns the target timeslice duration in ns for each SW runlist + * as configured by the user or the default value otherwise. + * + * arrAvgFactor + * This field returns the average factor to be used in compensating the timeslice + * for Adaptive scheduler mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_STATE (0x20801120) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS_MESSAGE_ID (0x20U) + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS { + NvU32 engineId; + NvU32 schedPolicy; + NvU32 arrEnabled; + NvU32 targetTimesliceNs; + NvU32 arrAvgFactor; +} NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE + * + * This command set the vGPU schedular state. + * + * engineId + * This field specifies the NV2080_ENGINE_TYPE_* engine. + * + * schedPolicy + * This field sets the runlist scheduling policy. It specifies the + * NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. + * + * enableArr + * This field sets the Adaptive round robin scheduler + * is enabled/disabled. + * + * timesliceTargetNs + * This field sets the time slice target time in ns. + * + * frequencyForARR + * This field sets the scheduling frequency for Adaptive round robin scheduler mode. + * + * avgFactorForARR + * This field sets the average factor to be used in compensating the timeslice + * for Adaptive scheduler mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_DEVICE + * NV_ERR_INVALID_STATE + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INSUFFICIENT_PERMISSIONS + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ + +#define NV2080_CTRL_CMD_FIFO_OBJSCHED_SET_STATE (0x20801121) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS_MESSAGE_ID (0x21U) + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS { + NvU32 engineId; + NvU32 schedPolicy; + NvU32 enableArr; + NvU32 timesliceTargetNs; + NvU32 frequencyForARR; + NvU32 avgFactorForARR; +} NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS; + +/* + * NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS + * + * This command returns the vGPU schedular capabilities. + * + * engineId [in] + * This field specifies the NV2080_ENGINE_TYPE_* engine whose SW runlist log + * entries are to be fetched. + * + * supportedSchedulers [out] + * This field returns the supported runlist scheduling policies on the device. + * It specifies the NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy. + * + * bIsArrModeSupported [out] + * This field returns if Adaptive scheduler mode is enabled/disabled. + * + * maxTimesliceNs [out] + * This field returns the maximum time slice value in ns. + * + * minTimesliceNs [out] + * This field returns the minimum time slice value in ns. + * + * maxFrequencyForARR [out] + * This field returns the maximum scheduling frequency for + * Adaptive round robin scheduler mode. + * + * minFrequencyForARR [out] + * This field returns the minimum scheduling frequency for + * Adaptive round robin scheduler mode. + * + * maxAvgFactorForARR [out] + * This field returns the maximum average factor in compensating + * the timeslice for Adaptive scheduler mode. + * + * minAvgFactorForARR [out] + * This field returns the minimum average factor in compensating + * the timeslice for Adaptive scheduler mode. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ +#define NV2080_CTRL_CMD_FIFO_OBJSCHED_GET_CAPS (0x20801122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS_MESSAGE_ID (0x22U) + +typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS { + NvU32 engineId; + NvU32 supportedSchedulers[NV2080_CTRL_CMD_SUPPORTED_VGPU_SCHEDULER_POLICY_COUNT]; + NvBool bIsArrModeSupported; + NvU32 maxTimesliceNs; + NvU32 minTimesliceNs; + NvU32 maxFrequencyForARR; + NvU32 minFrequencyForARR; + NvU32 maxAvgFactorForARR; + NvU32 minAvgFactorForARR; +} NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS; /* _ctrl2080fifo_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h index a75045d1b1..1485d6366f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h @@ -148,6 +148,7 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS { #define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_DEFAULT 0x0 #define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_FALCON 0x1 #define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV 0x2 +#define NV2080_CTRL_FLCN_GET_ENGINE_ARCH_RISCV_EB 0x3 /*!@}*/ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h index 79838bfb5e..e85c339244 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h @@ -748,7 +748,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS { #define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */ /* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ -#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x3FU +#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x40U #define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U) @@ -2518,6 +2518,8 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN { NV_DECLARE_ALIGNED(NvU64 hi, 8); } NV2080_CTRL_GPU_PARTITION_SPAN; +#define NV_GI_UUID_LEN 16U + /* * NV2080_CTRL_GPU_SET_PARTITION_INFO * @@ -2538,6 +2540,9 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN { * - PartitionID associated with a newly created partition. Input in case * of partition invalidation. * + * uuid[OUT] + * - Uuid of a newly created partition. + * * partitionFlag[IN] * - Flags to determine if GPU is requested to be partitioned in FULL, * HALF, QUARTER or ONE_EIGHTHED and whether the partition requires @@ -2566,6 +2571,7 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN { */ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO { NvU32 swizzId; + NvU8 uuid[NV_GI_UUID_LEN]; NvU32 partitionFlag; NvBool bValid; NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PARTITION_SPAN placement, 8); @@ -3824,7 +3830,7 @@ typedef struct NV2080_CTRL_GPU_SET_EGM_GPA_FABRIC_BASE_ADDR_PARAMS { */ #define NV2080_CTRL_CMD_GPU_GET_ENGINE_LOAD_TIMES (0x2080019bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC0U +#define NV2080_CTRL_GPU_MAX_ENGINE_OBJECTS 0xC8U #define NV2080_CTRL_GPU_GET_ENGINE_LOAD_TIMES_PARAMS_MESSAGE_ID (0x9BU) @@ -4038,7 +4044,14 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { #define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED NVBIT64(0) +#define NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED NVBIT64(1) + + +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1 +#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2 /*! * NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS @@ -4068,7 +4081,9 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS { * Possible values are * NV2080_CTRL_GPU_FABRIC_PROBE_CAP_* * fabricCliqueId[OUT] - * - Unique ID of a set of GPUs within a fabric partition that can perform P2P + * - Unique ID of a set of GPUs within a fabric partition that can perform P2P + * fabricHealthMask[OUT] + * - Mask where bits indicate different status about the health of the fabric */ #define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xA3U) @@ -4079,6 +4094,7 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS { NvU16 fabricPartitionId; NV_DECLARE_ALIGNED(NvU64 fabricCaps, 8); NvU32 fabricCliqueId; + NvU32 fabricHealthMask; } NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS; #define NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO (0x208001a3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID" */ @@ -4284,4 +4300,39 @@ typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS { #define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */ +typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO { + NvU32 engDesc; + NvU32 ctxAttr; + NvU32 ctxBufferSize; + NvU32 addrSpaceList; + NvU32 registerBase; +} NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO; +#define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS 0x40 + +#define NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO (0x208001b0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0xB0U) + +typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS { + NvU32 numConstructedFalcons; + NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS]; +} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS; + +/* + * NV2080_CTRL_GPU_GET_FIPS_STATUS + * + * @brief get FIPS status (enabled/disabled) from GSP-RM + * + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID (0xe4U) + +typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS { + NvBool bFipsEnabled; +} NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS; +#define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */ + + /* _ctrl2080gpu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h index dcb4336cbf..e789e19af7 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h @@ -622,6 +622,35 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS { } NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS; /* valid pmMode values same as above NV2080_CTRL_CTXSW_PM_MODE */ +/* + * NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND + * + * This command is used to set the Setup context switch mode and virtual address + * for the specified channel. A value of NV_ERR_NOT_SUPPORTED is + * returned if the target channel does not support setup context switch mode + * changes. + * + * hClient + * This parameter specifies the client handle of + * that owns the Setup context buffer. This field must match + * the hClient used in the control call for non-kernel clients. + * hChannel + * This parameter specifies the channel handle of + * the channel that is to have its Setup context switch mode changed. + * vMemPtr + * This parameter specifies the 64 bit virtual address + * for the allocated Setup context buffer. + */ +#define NV2080_CTRL_CMD_GR_CTXSW_SETUP_BIND (0x2080123aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0x3AU) + +typedef struct NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS { + NvHandle hClient; + NvHandle hChannel; + NV_DECLARE_ALIGNED(NvU64 vMemPtr, 8); +} NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS; + /* * NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP * @@ -1067,10 +1096,10 @@ typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS { NV_DECLARE_ALIGNED(NV2080_CTRL_GR_CTX_BUFFER_INFO ctxBufferInfo[NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT], 8); } NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS; -// Aperture flags -#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNWON ADDR_UNKNOWN -#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM ADDR_SYSMEM -#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM ADDR_FBMEM +// Aperture flags. The defines should match the defines in mem_desc.h +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_UNKNOWN 0 +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_SYSMEM 1 +#define NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_FBMEM 2 /* * NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h index 87dae28799..5f1188f910 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -76,6 +76,9 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS { NvBool bPrimaryVga; NvU32 i2cPort; NvU32 internalDispActiveMask; + NvU32 embeddedDisplayPortMask; + NvBool bExternalMuxSupported; + NvBool bInternalMuxSupported; } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS; @@ -112,8 +115,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { /*! L2 cache size */ NV_DECLARE_ALIGNED(NvU64 l2CacheSize, 8); - NvBool bReservedMemAtBottom; - /*! Indicate whether fpba is present or not */ NvBool bFbpaPresent; @@ -123,9 +124,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { /*! log32(comprPageSize) */ NvU32 comprPageShift; - /*! Maximum number of pages that can be dynamaically blacklisted */ - NvU16 maximumBlacklistPages; - /*! RAM type */ NvU32 ramType; @@ -134,12 +132,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS { /*! LTS per LTC count */ NvU32 ltsPerLtcCount; - - /*! Ampere PLC bug */ - NvBool bDisablePlcForCertainOffsetsBug3046774; - - /*! FB override Start KB */ - NV_DECLARE_ALIGNED(NvU64 fbOverrideStartKb, 8); } NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; /*! @@ -294,7 +286,7 @@ typedef struct NV2080_CTRL_INTERNAL_BSP_GET_CAPS_PARAMS { */ #define NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS (0x20800a25) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS_MESSAGE_ID" */ -#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 3 +#define NV2080_CTRL_CMD_INTERNAL_MAX_MSENCS 8 typedef struct NV2080_CTRL_INTERNAL_MSENC_CAPS { NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE]; @@ -558,7 +550,7 @@ typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL -#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19 +#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x1a typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO { NvU32 size; @@ -631,7 +623,6 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS { NvU8 chipSubRev; NvU32 emulationRev1; NvBool isCmpSku; - NvU32 bar1Size; NvU32 pciDeviceId; NvU32 pciSubDeviceId; NvU32 pciRevisionId; @@ -805,7 +796,7 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO { NvU32 runlistPriBase; NvU32 groupId; } NV2080_CTRL_INTERNAL_DEVICE_INFO; -#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 88 +#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256 #define NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE (0x20800a40) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */ @@ -831,24 +822,6 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS { NvU8 profilingRanges[NV2080_CTRL_INTERNAL_GPU_USER_REGISTER_ACCESS_MAP_MAX_PROFILING_RANGES]; } NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS; -typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO { - NvU32 engDesc; - NvU32 ctxAttr; - NvU32 ctxBufferSize; - NvU32 addrSpaceList; - NvU32 registerBase; -} NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO; -#define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40 - -#define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID (0x42U) - -typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS { - NvU32 numConstructedFalcons; - NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS]; -} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS; - /** * Get GR PDB properties synchronized between Kernel and Physical * @@ -858,6 +831,37 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS { +typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { + NV_DECLARE_ALIGNED(NvU64 lo, 8); + NV_DECLARE_ALIGNED(NvU64 hi, 8); +} NV2080_CTRL_INTERNAL_NV_RANGE; + +/*! + * NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS + * + * This structure specifies a target swizz-id and mem_range to update + * + * swizzId[IN] + * - Targeted swizz-id for which the memRange is being set + * + * memAddrRange[IN] + * - Memory Range for given GPU instance + */ +#define NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x43U) + +typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS { + NvU32 swizzId; + NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_NV_RANGE memAddrRange, 8); +} NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a44) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID (0x44U) + +typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS; + +#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */ + typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES { NvBool bPerSubCtxheaderSupported; } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES; @@ -1029,7 +1033,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS { * validGfxCTSIdMask [OUT] * # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile */ -#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 20 +#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60 @@ -1104,10 +1108,12 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS { +#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE 4 + #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U) typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS { - NV_DECLARE_ALIGNED(NvU64 engineMask, 8); + NV_DECLARE_ALIGNED(NvU64 engineMask[NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_MAX_ENGINES_MASK_SIZE], 8); } NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS; #define NV2080_CTRL_INTERNAL_FIFO_MAX_RUNLIST_BUFFERS 2 @@ -1142,6 +1148,23 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS { TEGRA_IMP_IMPORT_DATA tegraImpImportData; } NV2080_CTRL_INTERNAL_DISPLAY_SET_IMP_INIT_INFO_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO (0x20800a55) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS_MESSAGE_ID (0x55U) + +typedef struct NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS { + NvU16 pciDeviceId; + NvU16 pciSubDeviceId; + NvBool iseGPUBridge; + NvU8 approvedBusType; +} NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS; + +#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_NONE (0x00000000) +#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_CUSTOM (0x00000001) +#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB2 (0x00000002) +#define NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3 (0x00000003) + + /*! * NV2080_CTRL_CMD_INTERNAL_BUS_FLUSH_WITH_SYSMEMBAR * @@ -1357,6 +1380,9 @@ typedef struct NV2080_CTRL_INTERNAL_VMMU_GET_SPA_FOR_GPA_ENTRIES_PARAMS { * valid [IN] * This bit indicates whether pushbuffer parameters are valid or not * + * pbTargetAperture [IN] + * Indicates the PushBuffer Target Aperture type (IOVA, PCI, PCI_COHERENT or NVM) + * */ #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */ @@ -1370,6 +1396,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS { NvU32 hclass; NvU32 channelInstance; NvBool valid; + NvU32 pbTargetAperture; } NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS; /*! @@ -1556,11 +1583,6 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_ACTIVE_DISPLAY_DEVICES_PARAMS { #define NV2080_CTRL_INTERNAL_MAX_SWIZZ_ID 15 -typedef struct NV2080_CTRL_INTERNAL_NV_RANGE { - NV_DECLARE_ALIGNED(NvU64 lo, 8); - NV_DECLARE_ALIGNED(NvU64 hi, 8); -} NV2080_CTRL_INTERNAL_NV_RANGE; - #define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x60U) typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS { @@ -2127,6 +2149,7 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO { typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS { NvU32 swizzId; + NvU8 uuid[NV_GI_UUID_LEN]; NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8); } NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS; @@ -2610,54 +2633,55 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { } NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; /* - * NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE * * An internal call to invoke the sequence VGA register reads & writes to * perform save and restore of VGA * - * [in] saveOrRestore + * [in] bSave * To indicate whether save or restore needs to be performed. - * [in] useVbios + * [in] bUseVbios * Primary VGA indication from OS. * * Possible status values returned are: * NV_OK - * NV_ERR_GENERIC + * NV_ERR_INVALID_OPERATION * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE (0x20800a76) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ -typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS { +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x76U) - NvBool bSaveOrRestore; +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS { + NvBool bSave; NvBool bUseVbios; -} NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS; /*! - * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE + * NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE * - * To perform restore operation from saved fonts. + * To perform save or restore operation from/to saved fonts. * - * [in] saveOrRestore + * [in] bSave * To indicate whether save or restore needs to be performed. - * [in] useVbios + * [in] bUseVbios * Primary VGA indication from OS. + * [in] bVbiosCallSuccessful + * Indicates if vbios invocation was successful or not. * * Possible status values returned are: * NV_OK - * NV_ERR_GENERIC * NV_ERR_NOT_SUPPORTED */ -#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS_MESSAGE_ID (0x77U) +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE (0x20800a77) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID" */ -typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS { +#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS_MESSAGE_ID (0x77U) - NvBool bWriteCr; -} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS; +typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS { + NvBool bSave; + NvBool bUseVbios; + NvBool bVbiosCallSuccessful; +} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS; /*! * @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES @@ -3683,22 +3707,6 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS { NvBool bIsPcieTrusted; } NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS; -/*! - * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL - * - * This command is used to trigger the initialization / suspension of encrypted RPCs for Confidential Compute. - * bEncryptionControl : [IN] - * NV_TRUE indicates initialization. - * NV_FALSE indicates suspension. - */ -#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL (0x208001b2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID" */ - -#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS_MESSAGE_ID (0xB2U) - -typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS { - NvBool bEncryptionControl; -} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS; - /*! * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS * @@ -3749,6 +3757,25 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS { NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK ivMaskSet[NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT]; } NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS; +/*! + * NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE + * + * This control call can be used to set gpu state on GSP to accept client requests + * or to block client requests. + * This is a internal command sent from Kernel RM to Physical RM. + * + * bAcceptClientRequest:[IN] + * NV_TRUE : set gpu state to accept client work requests + * NV_FALSE: set gpu state to block client work requests + * + */ +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE (0x20800ae7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS_MESSAGE_ID (0xE7U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS { + NvBool bAcceptClientRequest; +} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS; /* @@ -3960,4 +3987,64 @@ typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS { } NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS; #define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */ +/*! + * NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS + * + * This structure provides the params for starting GPU Fabric Probe + * + * tracepointMask[IN] + * - tracepoint selection filter + * bufferSize[IN] + * - size of gsp side logging buffer + * bufferWatermark[IN] + * - entry threshold for GSP to issue RPC of logged entries to kernel RM + * bStart[IN] + * - if true, start tracing. if false, stop tracing. + */ +#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID (0xE3U) + +typedef struct NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS { + NV_DECLARE_ALIGNED(NvU64 tracepointMask, 8); + NvU32 bufferSize; + NvU32 bufferWatermark; + NvBool bStart; +} NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS; + +/* + * NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE + * + * This command is used to start GSP-RM trace tool. + * This command accepts NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS + * + */ +#define NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE (0x208001e3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS_MESSAGE_ID" */ + +/* + * NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES + * + * @brief get state (enabled/disabled) of SEC2 classes + * + * + * @return NV_OK on success + * @return NV_ERR_ otherwise + */ +#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID (0xAFU) + +typedef struct NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS { + NvBool bMaxwellSec2Enabled; + NvBool bNv95A1TsecEnabled; + NvBool bHopperSec2WorkLaunchAEnabled; +} NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS; +#define NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES (0x20800aaf) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_CMD_INTERNAL_GET_ENABLED_SEC2_CLASSES_PARAMS_MESSAGE_ID" */ + + +/*! + * @ref NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND + */ +#define NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_SETUP_BIND (0x20800ae4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS_MESSAGE_ID (0xE4U) + +typedef NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS NV2080_CTRL_INTERNAL_GR_CTXSW_SETUP_BIND_PARAMS; + /* ctrl2080internal_h */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h index f5b7202c56..cda8614751 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -209,44 +209,61 @@ typedef struct NV2080_NOCAT_JOURNAL_RECORD { // NOCAT activity counter indexes // collection activity -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 1 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 2 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 3 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 4 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX 5 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_IDX 0 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX 1 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 2 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 3 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX 4 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 5 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 6 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX 7 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX 8 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX 9 + +// Journal Lock activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX 10 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 11 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX 12 + +// lookup activity +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX 13 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX 14 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX 15 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX 16 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX 17 // reporting activity -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 6 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 7 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 8 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX 9 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 18 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 19 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 20 // update activity -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 10 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 11 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 12 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 21 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 22 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 23 // general errors -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 13 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 14 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 15 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 24 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 25 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 26 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 16 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 17 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CACHE_UPDATE_IDX 18 -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX 19 +// reserved entries for temporary use. +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES5_IDX 27 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX 28 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX 29 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 30 +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX 31 // this should be relative to the highest counter index -#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x14) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX + 1" */ +#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT (0x20) /* finn: Evaluated from "NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX + 1" */ #define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY 0:0 -#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1 -#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0 +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_YES 1 +#define NV2080_CTRL_NOCAT_GET_COUNTERS_ONLY_NO 0 #define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS 1:1 -#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1 -#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0 +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_YES 1 +#define NV2080_CTRL_NOCAT_GET_RESET_COUNTERS_NO 0 #define NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS_MESSAGE_ID (0x9U) @@ -266,7 +283,7 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS { * This command reports the TDR data collected by KMD to be added to the * nocat record * - * dataType: + * dataType * [IN] specifies the type of data provided. * targetRecordType * [IN] specifies record type the data is intended for. @@ -274,23 +291,22 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS { * [IN] specifies the data to be added. */ -#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA (0x2080240b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS_MESSAGE_ID" */ // data types & structures -#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0 -#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1 -#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD 2 -#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 3 -#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 4 - -#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0 -#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1 -#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2 -#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3 -#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4 -#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5 -#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6 -#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_EMPTY 0 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_TDR_REASON 1 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG 2 +#define NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_RCLOG 3 + +#define NV2080_CTRL_NOCAT_TDR_TYPE_NONE 0 +#define NV2080_CTRL_NOCAT_TDR_TYPE_LEGACY 1 +#define NV2080_CTRL_NOCAT_TDR_TYPE_FULLCHIP 2 +#define NV2080_CTRL_NOCAT_TDR_TYPE_BUSRESET 3 +#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4 +#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5 +#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6 +#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7 typedef struct NV2080CtrlNocatJournalDataTdrReason { NvU32 flags; @@ -300,23 +316,6 @@ typedef struct NV2080CtrlNocatJournalDataTdrReason { NvU32 reasonCode; } NV2080CtrlNocatJournalDataTdrReason; -#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0 -#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1 -#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0 -#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1 -#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1 -#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0 -typedef struct NV2080CtrlNocatJournalInsertRecord { - NvU32 flags; - NvU8 recType; - NvU32 bugcheck; - NvU8 source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; - NvU32 subsystem; - NV_DECLARE_ALIGNED(NvU64 errorCode, 8); - NvU8 faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; - NvU32 tdrReason; -} NV2080CtrlNocatJournalInsertRecord; - #define NV2080_CTRL_NOCAT_TAG_CLEAR 0:0 #define NV2080_CTRL_NOCAT_TAG_CLEAR_YES 1 #define NV2080_CTRL_NOCAT_TAG_CLEAR_NO 0 @@ -342,9 +341,44 @@ typedef struct NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS { NvU32 targetRecordType; union { NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalDataTdrReason tdrReason, 8); - NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord insertData, 8); NV2080CtrlNocatJournalSetTag tagData; NV2080CtrlNocatJournalRclog rclog; } nocatJournalData; } NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS; + /* + * NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD + * + * This command Inserts a NOCAT Journal record from an outside component. + * + * nocatJournalData + * [IN] specifies the data to be added. + */ + +#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD (0x2080240c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVD_INTERFACE_ID << 8) | NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR 0:0 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_YES 1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_NULL_STR_NO 0 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER 1:1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_YES 1 +#define NV2080_CTRL_NOCAT_INSERT_ALLOW_0_LEN_BUFFER_NO 0 + +typedef struct NV2080CtrlNocatJournalInsertRecord { + NvU32 flags; + NV_DECLARE_ALIGNED(NvU64 timestamp, 8); + NvU8 recType; + NvU32 bugcheck; + char source[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 subsystem; + NV_DECLARE_ALIGNED(NvU64 errorCode, 8); + char faultingEngine[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; + NvU32 tdrReason; + NvU32 diagBufferLen; + NvU8 diagBuffer[NV2080_NOCAT_JOURNAL_MAX_DIAG_BUFFER]; +} NV2080CtrlNocatJournalInsertRecord; +#define NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS { + NV_DECLARE_ALIGNED(NV2080CtrlNocatJournalInsertRecord nocatJournalRecord, 8); +} NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS; /* _ctr2080nvd_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h index 411a6194dd..2558100e01 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,7 @@ // #include "ctrl/ctrl2080/ctrl2080base.h" +#include "nvcfg_sdk.h" /* NV20_SUBDEVICE_XX bus control commands and parameters */ @@ -809,6 +810,8 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS { NV_DECLARE_ALIGNED(NvU64 linkMask, 8); } NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS; + + /* * NV2080_CTRL_CMD_NVLINK_INJECT_ERROR * This command causes all the same actions to occur as if the related @@ -820,7 +823,7 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS { * This parameter specifies that the error should be fatal. * */ -#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_NVLINK_INJECT_ERROR (0x20803006U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID" */ #define NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS_MESSAGE_ID (0x6U) @@ -1655,13 +1658,23 @@ typedef struct NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS { NvBool bEnable; } NV2080_CTRL_NVLINK_ENABLE_NVLINK_PEER_PARAMS; -#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U -#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U -#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U -#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U -#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U -#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U -#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 6U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_SLEEP 5U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_HS_TIME 6U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_EXIT_TIME 7U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_ENTRY_TIME 8U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_LP_EXIT_TIME 9U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_LOCAL_FULL_BW_ENTRY_TIME 10U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_EXIT_TIME 11U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_ENTRY_TIME 12U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_LP_EXIT_TIME 13U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_REMOTE_FULL_BW_ENTRY_TIME 14U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_OTHER_STATE_TIME 15U +#define NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 16U /* * NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS @@ -1694,6 +1707,8 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS { #define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */ + /* * NVLINK Link states * These should ALWAYS match the nvlink core library defines in nvlink.h @@ -2830,6 +2845,7 @@ typedef struct NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS { * cmd [IN] enum identifying the EOM related command for the driver to process * link [IN] linkId * params [IN] NvU32 word that is written into NV_PMINION_SCRATCH_SWRW_0 before calling CONFIGEOM dlcmd + * measurements [OUT] output of EOM * * Params Packing is specified in Minion IAS */ @@ -2841,27 +2857,37 @@ typedef enum NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND { NVLINK_EOM_CONTROL_FULL_EOM_SEQUENCE = 3, } NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND; +typedef struct NV2080_CTRL_NVLINK_EOM_MEASUREMENT { + NvU8 upper; + NvU8 middle; + NvU8 lower; + NvU8 composite; +} NV2080_CTRL_NVLINK_EOM_MEASUREMENT; + #define NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID (0x3cU) typedef struct NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS { NV2080_CTRL_CMD_NVLINK_EOM_CONTROL_PARAMS_COMMAND cmd; NvU32 linkId; NvU32 params; + NV2080_CTRL_NVLINK_EOM_MEASUREMENT measurements[NV2080_CTRL_NVLINK_MAX_LANES]; } NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS; -#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */ +#define NV2080_CTRL_CMD_NVLINK_EOM_CONTROL (0x2080303c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS_MESSAGE_ID" */ /*! - * Inband Recieved Data + * Inband Received Data */ -#define NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE 4096 +#define NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE 5120 #define NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID (0x3dU) typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS { - NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE]; + NvU8 data[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE]; NvU32 dataSize; } NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS; +#define NV2080_CTRL_CMD_READ_NVLINK_INBAND_RESPONSE (0x2080303d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_MESSAGE_ID" */ + /* * NV2080_CTRL_CMD_NVLINK_SET_L1_THRESHOLD * @@ -2909,7 +2935,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS { #define NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS_MESSAGE_ID (0x40U) typedef struct NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS { - NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_MSG_SIZE]; + NvU8 buffer[NV2080_CTRL_NVLINK_INBAND_MAX_DATA_SIZE]; NvU32 dataSize; } NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS; @@ -3074,5 +3100,18 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS { #define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */ + +/*! + * + * NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS + * + * Nvlink Fatal Error Recovery + * This command accepts no parameters. + * + */ + +#define NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY (0x20803048U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x48" */ + + /* _ctrl2080nvlink_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h index 4873686621..4b7cc28fad 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -444,6 +444,14 @@ typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE { * NV DECODER utilization sample. */ NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec; + /*! + * NV JPEG utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg; + /*! + * NV OFA utilization sample. + */ + NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa; } NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE; /*! @@ -582,5 +590,247 @@ typedef struct NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS { } NV2080_CTRL_PERF_AGGRESSIVE_PSTATE_NOTIFY_PARAMS; +typedef struct NV2080_CTRL_PERF_GET_CLK_INFO { + NvU32 flags; + NvU32 domain; + NvU32 currentFreq; + NvU32 defaultFreq; + NvU32 minFreq; + NvU32 maxFreq; +} NV2080_CTRL_PERF_GET_CLK_INFO; + + +#define NV2080_CTRL_PERF_CLK_MAX_DOMAINS 32U + +#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO (0x20802002) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS { + NvU32 level; + NvU32 flags; + NV_DECLARE_ALIGNED(NvP64 perfGetClkInfoList, 8); + NvU32 perfGetClkInfoListSize; +} NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS; + +#define NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO_V2 (0x2080200b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS_MESSAGE_ID (0xBU) + +typedef struct NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS { + NvU32 level; + NvU32 flags; + NV2080_CTRL_PERF_GET_CLK_INFO perfGetClkInfoList[NV2080_CTRL_PERF_CLK_MAX_DOMAINS]; + NvU32 perfGetClkInfoListSize; +} NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS; + +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE 0:0 +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_DEFAULT (0x00000000) +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_TYPE_OVERCLOCK (0x00000001) +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE 2:1 +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_NONE (0x00000000) +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_DESKTOP (0x00000001) +#define NV2080_CTRL_PERF_GET_LEVEL_INFO_FLAGS_MODE_MAXPERF (0x00000002) + +/* + * NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE + * + * This command can be used to obtain video decoder utilization of + * the associated subdevice. + * This command is not supported with SMC enabled. + * + * engineType + * This parameter will allow clients to set type of video + * engine in question. It can be NVENC or NVDEC. + * clkPercentBusy + * This parameter contains the percentage during the sample that + * the clock remains busy. + * samplingPeriodUs + * This field returns the sampling period in microseconds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ +#define NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE (0x20802087) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID" */ + +typedef enum NV2080_CTRL_CMD_PERF_VID_ENG { + /*! + * GPU Video encoder engine. + */ + NV2080_CTRL_CMD_PERF_VID_ENG_NVENC = 1, + + /*! + * GPU video decoder engine. + */ + NV2080_CTRL_CMD_PERF_VID_ENG_NVDEC = 2, + + /*! + * GPU JPEG engine. + */ + NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG = 3, + + /*! + * GPU OFA engine. + */ + NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA = 4, +} NV2080_CTRL_CMD_PERF_VID_ENG; + +#define NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_MESSAGE_ID (0x87U) + +typedef struct NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS { + NV2080_CTRL_CMD_PERF_VID_ENG engineType; + NvU32 clkPercentBusy; + NvU32 samplingPeriodUs; +} NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_GET_POWERSTATE + * + * This command can be used to find out whether the perf power state is AC/battery. + * + * powerStateInfo + * This parameter specifies the power source type. + * + * Possible status values returned are: + * NV_OK + */ +#define NV2080_CTRL_CMD_PERF_GET_POWERSTATE (0x2080205a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS_MESSAGE_ID (0x5AU) + +typedef struct NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS { + NV2080_CTRL_PERF_POWERSTATE_PARAMS powerStateInfo; +} NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS; + +/* + * NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT + * + * This command can be used by video driver to notify RM concerning + * performance related events. + * + * videoEvent + * This parameter specifies the video event to notify. + * Legal values for this parameter include: + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP + * These values indicate that a HD video stream (less than 4K) + * has started/stopped. + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP + * These are now obsolete in new products as we no longer + * need to differentiate between SD and HD. + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START + * NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP + * These value indicates that a 4K video stream (3840x2160 pixels + * or higher) has started/stopped. + * NV2080_CTRL_PERF_VIDEOEVENT_OFA_START + * NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP + * These value indicates that Optical Flow Accelerator usage has + * started/stopped. + * The following flags may be or'd into the event value: + * NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE + * The stream operates BSP/VP2 or MSVLD/MSPDEC communication in + * linear mode (default is ring mode). + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_INVALID_PARAM_STRUCT + */ +#define NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT (0x2080205d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS_MESSAGE_ID (0x5DU) + +typedef struct NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS { + NvU32 videoEvent; +} NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS; + +#define NV2080_CTRL_PERF_VIDEOEVENT_EVENT_MASK (0x0000ffff) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START (0x00000001) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP (0x00000002) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_START NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_START +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_STOP NV2080_CTRL_PERF_VIDEOEVENT_STREAM_HD_STOP +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_START (0x00000003) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_SD_STOP (0x00000004) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_START (0x00000005) +#define NV2080_CTRL_PERF_VIDEOEVENT_STREAM_4K_STOP (0x00000006) +#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_START (0x00000007) +#define NV2080_CTRL_PERF_VIDEOEVENT_OFA_STOP (0x00000008) +#define NV2080_CTRL_PERF_VIDEOEVENT_FLAG_LINEAR_MODE (0x00010000) + +/*! + * @defgroup NV2080_CTRL_PERF_PSTATES + * + * These are definitions of performance states (P-states) values. + * P0 has the maximum performance capability and consumes maximum + * power. P1 has a lower perf and power than P0, and so on. + * For NVIDIA GPUs, the following definitions are made: + * P0 - maximum 3D performance + * P1 - original P0 when active clocked + * P2-P3 - balanced 3D performance-power + * P8 - basic HD video playback + * P10 - SD video playback + * P12 - minimum idle power + * P15 - max possible P-state under current scheme (currently not used) + * Not all P-states are available on a given system. + * + * @note The @ref NV2080_CTRL_PERF_PSTATES_ID was introduced after the + * original constants were added, so not all places that intend to use + * these values are using the type. They should be updated to do so. + * @{ + */ +typedef NvU32 NV2080_CTRL_PERF_PSTATES_ID; +#define NV2080_CTRL_PERF_PSTATES_UNDEFINED (0x00000000U) +#define NV2080_CTRL_PERF_PSTATES_CLEAR_FORCED (0x00000000U) +#define NV2080_CTRL_PERF_PSTATES_MIN (0x00000001U) +#define NV2080_CTRL_PERF_PSTATES_P0 (0x00000001U) +#define NV2080_CTRL_PERF_PSTATES_P1 (0x00000002U) +#define NV2080_CTRL_PERF_PSTATES_P2 (0x00000004U) +#define NV2080_CTRL_PERF_PSTATES_P3 (0x00000008U) +#define NV2080_CTRL_PERF_PSTATES_P4 (0x00000010U) +#define NV2080_CTRL_PERF_PSTATES_P5 (0x00000020U) +#define NV2080_CTRL_PERF_PSTATES_P6 (0x00000040U) +#define NV2080_CTRL_PERF_PSTATES_P7 (0x00000080U) +#define NV2080_CTRL_PERF_PSTATES_P8 (0x00000100U) +#define NV2080_CTRL_PERF_PSTATES_P9 (0x00000200U) +#define NV2080_CTRL_PERF_PSTATES_P10 (0x00000400U) +#define NV2080_CTRL_PERF_PSTATES_P11 (0x00000800U) +#define NV2080_CTRL_PERF_PSTATES_P12 (0x00001000U) +#define NV2080_CTRL_PERF_PSTATES_P13 (0x00002000U) +#define NV2080_CTRL_PERF_PSTATES_P14 (0x00004000U) +#define NV2080_CTRL_PERF_PSTATES_P15 (0x00008000U) +#define NV2080_CTRL_PERF_PSTATES_MAX NV2080_CTRL_PERF_PSTATES_P15 +#define NV2080_CTRL_PERF_PSTATES_SKIP_ENTRY (0x10000U) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX << 1)" */ +#define NV2080_CTRL_PERF_PSTATES_ALL (0xffffU) /* finn: Evaluated from "(NV2080_CTRL_PERF_PSTATES_MAX | (NV2080_CTRL_PERF_PSTATES_MAX - 1))" */ +/*!@}*/ + +/* + * NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE + * + * This command returns the current performance state of the GPU. + * + * currPstate + * This parameter returns the current P-state, as defined in + * NV2080_CTRL_PERF_PSTATES values. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_PARAM_STRUCT + * NV_ERR_NOT_SUPPORTED + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE (0x20802068) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_MESSAGE_ID (0x68U) + +typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS { + NvU32 currPstate; +} NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS; + + /* _ctrl2080perf_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h index a8860cc88e..d4f9bb3f6d 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmu.h @@ -1,4 +1,3 @@ - /* * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT @@ -24,6 +23,8 @@ #pragma once +#include + // // This file was generated with FINN, an NVIDIA coding tool. // Source file: ctrl/ctrl2080/ctrl2080pmu.finn @@ -31,8 +32,6 @@ -#include "nvtypes.h" - /*! * @file * diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h index 35a309b04a..9fb34dd656 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h @@ -38,93 +38,45 @@ * @brief SPDM Command Types * */ -#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1) -#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2) -#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3) -#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4) +#define RM_GSP_SPDM_CMD_ID_CC_INIT (0x1) +#define RM_GSP_SPDM_CMD_ID_CC_DEINIT (0x2) +#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3) +#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4) +#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5) -#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF) +#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF) -#define RSVD7_SIZE 16 +#define RSVD7_SIZE 16 -#define RSVD8_SIZE 2 - -/*! - * Guest RM must send RM_GSP_SPDM_CMD_ID_CC_INIT to GSP-RM before SPDM session start - */ -typedef struct RM_GSP_SPDM_CC_INIT_CTX { - NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc - - - NvU64_ALIGN32 dmaAddr; // The address RM allocate in SYS memory or FB memory. - - NvU32 rmBufferSizeInByte; // The memort size allocated by RM(exclude NV_SPDM_DESC_HEADER) - -} RM_GSP_SPDM_CC_INIT_CTX; -typedef struct RM_GSP_SPDM_CC_INIT_CTX *PRM_GSP_SPDM_CC_INIT_CTX; +#define RSVD8_SIZE 2 /*! * Guest RM provides INIT context */ typedef struct RM_GSP_SPDM_CMD_CC_INIT { // Command must be first as this struct is the part of union - NvU8 cmdType; - - RM_GSP_SPDM_CC_INIT_CTX ccInitCtx; + NvU8 cmdType; } RM_GSP_SPDM_CMD_CC_INIT; typedef struct RM_GSP_SPDM_CMD_CC_INIT *PRM_GSP_SPDM_CMD_CC_INIT; -#define DEINIT_FLAGS_FORCE_CLEAR (0x1) - -/*! - * Guest RM must send RM_GSP_SPDM_CMD_ID_CC_DEINIT to GSP-RM to end a session - */ -typedef struct RM_GSP_SPDM_CC_DEINIT_CTX { - NvU32 guestId; // To indicate CC guest Id, VM0, VM1 ... etc - - NvU32 endpointId; // To indicate SPDM endpoint Id - - NvU32 flags; -} RM_GSP_SPDM_CC_DEINIT_CTX; -typedef struct RM_GSP_SPDM_CC_DEINIT_CTX *PRM_GSP_SPDM_CC_DEINIT_CTX; - /*! * Guest RM provides INIT context */ typedef struct RM_GSP_SPDM_CMD_CC_DEINIT { // Command must be first as this struct is the part of union - NvU8 cmdType; - - RM_GSP_SPDM_CC_DEINIT_CTX ccDeinitCtx; + NvU8 cmdType; } RM_GSP_SPDM_CMD_CC_DEINIT; typedef struct RM_GSP_SPDM_CMD_CC_DEINIT *PRM_GSP_SPDM_CMD_CC_DEINIT; -/*! - * RM provides SPDM message request context, include header + corresponding payload - */ - -typedef struct RM_GSP_SPDM_CC_CTRL_CTX { - - NvU32 version; - - NvU32 guestId; // To indicate CC client Id, VM0, VM1 ... etc - - NvU32 endpointId; // To indicate SPDM endpoint Id - -} RM_GSP_SPDM_CC_CTRL_CTX; -typedef struct RM_GSP_SPDM_CC_CTRL_CTX *PRM_GSP_SPDM_CC_CTRL_CTX; - /*! * RM provides the SPDM request info to GSP */ typedef struct RM_GSP_SPDM_CMD_CC_CTRL { // Command must be first as this struct is the part of union - NvU8 cmdType; - - RM_GSP_SPDM_CC_CTRL_CTX ccCtrlCtx; + NvU8 cmdType; } RM_GSP_SPDM_CMD_CC_CTRL; typedef struct RM_GSP_SPDM_CMD_CC_CTRL *PRM_GSP_SPDM_CMD_CC_CTRL; @@ -136,9 +88,9 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA { NvU32 rsvd1; - char rsvd2[4]; + char rsvd2[9]; - char rsvd3[2]; + char rsvd3[5]; char rsvd4[5]; @@ -152,6 +104,15 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA { } RM_GSP_SPDM_CMD_CC_INIT_RM_DATA; typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA; +typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL { + // Command must be first as this struct is the part of union + NvU8 cmdType; + + // Whether to enable or disable heartbeats + NvBool bEnable; +} RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL; +typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL; + /*! * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives @@ -164,11 +125,12 @@ typedef struct RM_GSP_SPDM_CMD_CC_INIT_RM_DATA *PRM_GSP_SPDM_CMD_CC_INIT_RM_DATA * A union of all SPDM Commands. */ typedef union RM_GSP_SPDM_CMD { - NvU8 cmdType; - RM_GSP_SPDM_CMD_CC_INIT ccInit; - RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit; - RM_GSP_SPDM_CMD_CC_CTRL ccCtrl; - RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd; + NvU8 cmdType; + RM_GSP_SPDM_CMD_CC_INIT ccInit; + RM_GSP_SPDM_CMD_CC_DEINIT ccDeinit; + RM_GSP_SPDM_CMD_CC_CTRL ccCtrl; + RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd; + RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl; } RM_GSP_SPDM_CMD; typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD; @@ -182,17 +144,18 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD; /*! * Returns the status for program CE keys to RM */ -#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1) -#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2) -#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3) -#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4) +#define RM_GSP_SPDM_MSG_ID_CC_INIT (0x1) +#define RM_GSP_SPDM_MSG_ID_CC_DEINIT (0x2) +#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3) +#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4) +#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5) /*! * Returns the Error Status for Invalid Command */ -#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF) +#define RM_GSP_SPDM_MSG_ID_INVALID_COMMAND (0xFF) /*! * NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives @@ -207,12 +170,6 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD; typedef struct RM_GSP_SPDM_MSG { NvU8 msgType; - NvU32 version; - - NvU32 guestId; - - NvU32 endpointId; - // status returned from GSP message infrastructure. NvU32 status; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h index 61a40b67c9..c190f601b4 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h @@ -61,7 +61,7 @@ #define NV2080_CTRL_MAX_VMMU_SEGMENTS 384 /* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */ -#define NV2080_GPU_MAX_ENGINES 0x3f +#define NV2080_GPU_MAX_ENGINES 0x40 #define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U) @@ -412,4 +412,28 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS { NvBool bSupportHeterogeneousTimeSlicedVgpuTypes; } NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS; +/* + * NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT + * + * Reroutes NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES to GSP RM to enable + * kernel clients to utilize NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES. + * + * gfid [IN] + * This parameter specifies the gfid of vGPU assigned to VM. + * flags [IN] + * Specifies what component of HostVgpuDevice to free. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES (0x2080400c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS { + NvU32 gfid; + NvU32 flags; +} NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS; + /* _ctrl2080vgpumgrinternal_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h index 8271ff70da..bb0b8a7eed 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -126,4 +126,6 @@ typedef struct NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS { NvU32 numHshubmmus; } NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS; + + /* _ctrl208fmmu_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h index 4ff3a45103..d0129947ac 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl506f.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -93,4 +93,21 @@ typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS { NvU32 exceptType; NvU32 engineID; -} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS;/* _ctrl506f.h_ */ +} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS; + +/* + * NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL + * + * This command is an internal command sent from Kernel RM to Physical RM + * to perform the channel reset operations in hardware on an isolated channel + * + * Please see description of NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL for more information. + * + */ +#define NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL (0x506f0106) /* finn: Evaluated from "(FINN_NV50_CHANNEL_GPFIFO_GPFIFO_INTERFACE_ID << 8) | NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS_MESSAGE_ID (0x6U) + +typedef NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS; + +/* _ctrl506f.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h index 2831174e3d..ab31072e17 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070verif.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2001-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2001-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h b/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h index a2db393618..57bcdc4b80 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl906f.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -119,6 +119,9 @@ typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS { * resetReason * Specifies reason to reset a channel. * + * bIsRcPending + * Specifies if an RC is pending on the channel + * * Possible status values returned are: * NV_OK */ @@ -138,9 +141,10 @@ typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS { #define NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_MESSAGE_ID (0x2U) typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS { - NvU32 engineID; - NvU32 subdeviceInstance; - NvU32 resetReason; + NvU32 engineID; + NvU32 subdeviceInstance; + NvU32 resetReason; + NvBool bIsRcPending; } NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS; /* diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h index b259fcd7ab..b3e4a4a308 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,7 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ - #pragma once #include @@ -31,6 +30,29 @@ // Source file: ctrl/ctrla080.finn // +#include "ctrl/ctrlxxxx.h" +/* KEPLER_DEVICE_VGPU control commands and parameters */ + +#define NVA080_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA080, NVA080_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA080_CTRL_RESERVED (0x00) +#define NVA080_CTRL_VGPU_DISPLAY (0x01) +#define NVA080_CTRL_VGPU_MEMORY (0x02) +#define NVA080_CTRL_VGPU_OTHERS (0x03) + +/* + * NVA080_CTRL_CMD_NULL + * + * This command does nothing. + * This command does not take any parameters. + * + * Possible status values returned are: + * NV_OK + */ + +#define NVA080_CTRL_CMD_NULL (0xa0800000) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_RESERVED_INTERFACE_ID << 8) | 0x0" */ + @@ -181,142 +203,7 @@ typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS { NvU32 blankingEnabled; } NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS; -/* - * NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS - * - * This command returns CPU virtual address of the mouse pointer mapping for VGPU. - * The address returned by this command is the pointer address for the head 0. - * VGPU_POINTER_OFFSET_HEAD(i) should be added to this address to get the address of head i. - * VGPU mouse pointer is a 32 bit value, X location of the mouse pointer is stored in - * 15:0 and Y location is stored in 31:16 bits. X location value of the mouse pointer is - * negative if bit 15 is set. Similarly, Y location value is negative if bit 31 is set. - * - * Parameters: - * pPointerAddress - * CPU virtual address of the mouse pointer mapping for VGPU - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - * NVOS_STATUS_NOT_SUPPORTED - */ - -#define NVA080_CTRL_CMD_VGPU_DISPLAY_GET_POINTER_ADDRESS (0xa0800105) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID" */ - -#define NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS_MESSAGE_ID (0x5U) - -typedef struct NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS { - NV_DECLARE_ALIGNED(NvP64 pPointerAddress, 8); -} NVA080_CTRL_VGPU_DISPLAY_GET_POINTER_ADDRESS_PARAMS; - -#define VGPU_POINTER_OFFSET_HEAD0_VALUE 0x00000000 -#define VGPU_POINTER_OFFSET_HEAD0_FLAG 0x00000004 -#define VGPU_POINTER_OFFSET_HEAD1_VALUE 0x00000008 -#define VGPU_POINTER_OFFSET_HEAD1_FLAG 0x0000000c -#define VGPU_POINTER_OFFSET_HEAD2_VALUE 0x00000010 -#define VGPU_POINTER_OFFSET_HEAD2_FLAG 0x00000014 -#define VGPU_POINTER_OFFSET_HEAD3_VALUE 0x00000018 -#define VGPU_POINTER_OFFSET_HEAD3_FLAG 0x0000001c -#define VGPU_POINTER_OFFSET_HEAD_VALUE(i) (i * 8) -#define VGPU_POINTER_OFFSET_HEAD_FLAG(i) (4 + i * 8) -#define VGPU_POINTER_OFFSET_HEAD_SIZE 4 - -/* - * NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE - * - * This command returns mappable video size to be used by each VM. - * - * Parameters: - * mappableVideoSize - * This parameter returns mappable video size in bytes. - * - * Possible status values returned are: - * NV_OK - * NV_ERR_INVALID_ARGUMENT - * NVOS_STATUS_NOT_SUPPORTED - */ - - -#define NV_VGPU_POINTER_X_LOCATION 15:0 -#define NV_VGPU_POINTER_Y_LOCATION 31:16 -#define NVA080_CTRL_CMD_GET_MAPPABLE_VIDEO_SIZE (0xa0800201) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID" */ - -#define NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS_MESSAGE_ID (0x1U) - -typedef struct NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS { - NV_DECLARE_ALIGNED(NvU64 mappableVideoSize, 8); -} NVA080_CTRL_GET_MAPPABLE_VIDEO_SIZE_PARAMS; - -/* - * NVA080_CTRL_CMD_MAP_SEMA_MEM - * - * This command returns GPU VA for the channel with 'hCtxDma' handle - * where per VM semaphore memory is mapped which is used for tracking - * non-stall interrupt of each VM. - * - * Parameters: - * hClient [in] - * This parameter specifies the handle to the NV01_ROOT object of - * the client. This object should be the parent of the object - * specified by hDevice. - * hDevice [in] - * This parameter specifies the handle of the NV01_DEVICE object - * representing the desired GPU. - * hMemory [in] - * This parameter specifies the handle for semaphore memory - * hCtxDma [in] - * This parameter specifies the handle of the NV01_CONTEXT_DMA - * object through which bufferId is written in semaphore memory for - * non-stall interrupt tracking. - * semaAddress [out] - * This parameter returns the GPU virtual address of the semaphore - * memory. - * - * Possible status values returned are: - * NV_OK - * NVOS_STATUS_INVALID_DATA - * NV_ERR_INVALID_CLIENT - * NV_ERR_INVALID_OBJECT_HANDLE - * - */ - -#define NVA080_CTRL_CMD_MAP_SEMA_MEM (0xa0800202) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID" */ -typedef struct NVA080_CTRL_SEMA_MEM_PARAMS { - NvHandle hClient; - NvHandle hDevice; - NvHandle hMemory; - NvHandle hCtxDma; - NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); -} NVA080_CTRL_SEMA_MEM_PARAMS; - -#define NVA080_CTRL_MAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x2U) - -typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_MAP_SEMA_MEM_PARAMS; - -/* - * NVA080_CTRL_CMD_UNMAP_SEMA_MEM - * - * This command unmaps per VM semaphore memory from GPU VA space, mapped by - * NVA080_CTRL_CMD_MAP_SEMA_MEM command. - * - * Parameters: - * Same as NVA080_CTRL_MAP_SEMA_MEM_PARAMS, except semaAddress is input - * parameter here. - * - * Possible status values returned are: - * NV_OK - * NVOS_STATUS_INVALID_DATA - * NV_ERR_INVALID_CLIENT - * NV_ERR_INVALID_OBJECT_HANDLE - * - */ - -#define NVA080_CTRL_CMD_UNMAP_SEMA_MEM (0xa0800203) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID" */ - -#define NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS_MESSAGE_ID (0x3U) - -typedef NVA080_CTRL_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_SEMA_MEM_PARAMS; /*! * NVA080_CTRL_CMD_SET_FB_USAGE @@ -338,140 +225,6 @@ typedef struct NVA080_CTRL_SET_FB_USAGE_PARAMS { NV_DECLARE_ALIGNED(NvU64 fbUsed, 8); } NVA080_CTRL_SET_FB_USAGE_PARAMS; -/*! -* NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM -* -* This command allocates the per engine vGPU semaphore memory and map it to -* GPU/CPU VA. -* -* Calculate engine's semaphore GPU VA = -* semaAddress + semaStride * NV2080_ENGINE_TYPE_ of that engine -* -* Parameters: -* hClient [in] -* This parameter specifies the handle to the NV01_ROOT object of -* the client. This object should be the parent of the object -* specified by hDevice. -* hDevice [in] -* This parameter specifies the handle of the NV01_DEVICE object -* representing the desired GPU. -* hMemory [in] -* This parameter specifies the handle for semaphore memory -* hCtxDma [in] -* This parameter specifies the handle of the NV01_CONTEXT_DMA -* object through which bufferId is written in semaphore memory for -* non-stall interrupt tracking. -* semaAddress [out] -* This parameter returns the GPU VA of the per engine semaphore memory. -* semaStride [out] -* This parameter specifies the stride of each engine's semaphore offset within this memory. -* -* Possible status values returned are: -* NV_OK -*/ - -#define NVA080_CTRL_CMD_MAP_PER_ENGINE_SEMA_MEM (0xa0800205) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ - -typedef struct NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS { - NvU32 hClient; - NvU32 hDevice; - NvHandle hMemory; - NvU32 hCtxDma; - NV_DECLARE_ALIGNED(NvU64 semaAddress, 8); - NvU32 semaStride; -} NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS; - -#define NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x5U) - -typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS; - -/*! -* NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM -* -* This command unmaps and frees the per engine vGPU semaphore memory. -* -* Parameters: -* Same as NVA080_CTRL_MAP_PER_ENGINE_SEMA_MEM_PARAMS, except semaAddress is input -* parameter here. -* -* Possible status values returned are: -* NV_OK -*/ - -#define NVA080_CTRL_CMD_UNMAP_PER_ENGINE_SEMA_MEM (0xa0800206) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID" */ - -#define NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS_MESSAGE_ID (0x6U) - -typedef NVA080_CTRL_PER_ENGINE_SEMA_MEM_PARAMS NVA080_CTRL_UNMAP_PER_ENGINE_SEMA_MEM_PARAMS; - -/* - * NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP - * - * This command provides the guest RM with PFN information, so that it can - * update the shared memory with the plugin, which keeps track of guest sysmem. - * - * Parameters: - * destPhysAddr - * Start address of the segment to be tracked - * - * pageCount - * Number of pages in the segment - * - * pageSize - * Size of pages in the segment - * - * isValid: - * TRUE : Set bits corresponding to PFNs in bitmap and increase segment refcount - * FALSE: Decrease segment refcount and then unset bits if refcount is 0 - * - * pfnList - * List of PFNs in the segment - * - * flags - * FLAGS_DST_PHYS_ADDR_BAR1_OFFSET - * Flag set to TRUE if pteMem is CPU VA pointing to BAR1 and - * dstPhysAddr contains BAR1 offset. - * - * Possible status values returned are: - * NVOS_STATUS_SUCCESS - */ - -#define NVA080_CTRL_CMD_UPDATE_SYSMEM_BITMAP (0xa0800207) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID << 8) | NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID" */ - -#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET 0:0 -#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_FALSE (0x00000000) -#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_FLAGS_DST_PHYS_ADDR_BAR1_OFFSET_TRUE (0x00000001) - -#define NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS_MESSAGE_ID (0x7U) - -typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { - NV_DECLARE_ALIGNED(NvU64 destPhysAddr, 8); - NvU32 pageCount; - NvU32 pageSize; - NvBool isValid; - NV_DECLARE_ALIGNED(NvP64 pfnList, 8); - NvU32 flags; -} NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS; - -/* - * Blit semaphore offset location - */ -#define VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET 0x200 -#define VGPU_BLIT_RESTORE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_RESTORE_SEMA_MEM_OFFSET) - -#define VGPU_BLIT_SEMA_MEM_OFFSET 0x400 -#define VGPU_BLIT_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_BLIT_SEMA_MEM_OFFSET) - -#define VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET 0x800 -#define VGPU_FBMEMCE_PUSH_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PUSH_SEMA_MEM_OFFSET) - -#define VGPU_FBMEMCE_SEMA_MEM_OFFSET 0x810 -#define VGPU_FBMEMCE_SEMA_MEM_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_SEMA_MEM_OFFSET) - -#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET 0x820 -#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_LOWER_OFFSET) - -#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET 0x824 /* * NVA080_CTRL_CMD_VGPU_GET_CONFIG @@ -571,7 +324,7 @@ typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { * NV_ERR_INVALID_PARAM_STRUCT * NV_ERR_INVALID_ARGUMENT */ -#define VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_ADDR(addr) (((NvU64)addr) + VGPU_FBMEMCE_PIPELINED_SEMA_MEM_UPPER_OFFSET) + #define NVA080_CTRL_CMD_VGPU_GET_CONFIG (0xa0800301) /* finn: Evaluated from "(FINN_KEPLER_DEVICE_VGPU_VGPU_OTHERS_INTERFACE_ID << 8) | NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID" */ #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_SW_VSYNC_ENABLED 0:0 diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla081.h b/src/common/sdk/nvidia/inc/ctrl/ctrla081.h index f625a59c0b..12cc0e21f1 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla081.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla081.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -51,6 +51,7 @@ #define NVA081_PCI_CONFIG_SPACE_SIZE 0x100 #define NVA081_PGPU_METADATA_STRING_SIZE 256 #define NVA081_EXTRA_PARAMETERS_SIZE 1024 +#define NVA081_PLACEMENT_ID_INVALID 0xFFFFU /* * NVA081_CTRL_CMD_VGPU_CONFIG_SET_INFO @@ -118,6 +119,9 @@ typedef struct NVA081_CTRL_VGPU_INFO { NvU32 exclusiveSize; // used only by NVML NvU32 gpuInstanceProfileId; + NvU32 placementSize; + NvU32 placementCount; + NvU32 placementIds[NVA081_MAX_VGPU_PER_PGPU]; } NVA081_CTRL_VGPU_INFO; /* @@ -231,6 +235,9 @@ typedef struct NVA081_GUEST_VM_INFO { * This parameter specifies whether driver is loaded on this particular vGPU. * swizzId [OUT] * This param specifies the GPU Instance ID or Swizz ID + * placementId [OUT] + * This param specifies the placement ID of heterogeneous timesliced vGPU instance. + * Otherwise it is NVA081_PLACEMENT_ID_INVALID. * */ typedef struct NVA081_HOST_VGPU_DEVICE { @@ -244,6 +251,7 @@ typedef struct NVA081_HOST_VGPU_DEVICE { NvU32 eccState; NvBool bDriverLoaded; NvU32 swizzId; + NvU32 placementId; } NVA081_HOST_VGPU_DEVICE; /* ECC state values */ @@ -463,11 +471,11 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS { } NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS; /* - * NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER + * NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO * * This command register the GPU to Linux kernel's mdev module for vGPU on KVM. */ -#define NVA081_CTRL_CMD_VGPU_CONFIG_MDEV_REGISTER (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_PGPU_INFO (0xa0810109) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | 0x9" */ /* * NVA081_CTRL_CMD_VGPU_CONFIG_SET_VGPU_INSTANCE_ENCODER_CAPACITY @@ -747,4 +755,130 @@ typedef struct NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS { NvU32 swizzId; } NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS; +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO + * + * This command is used to get a placement Id from RM for timesliced + * heterogeneous vGPUs. + * + * isHeterogeneousEnabled [OUT] + * This param specific whether timesliced heterogeneous vGPU is enabled + * for different FB sized profiles. + * + * vgpuTypeId [IN] + * This param specifies the Type ID for VGPU profile + * + * placementId [IN / OUT] + * This param specifies the input placement ID provided by hypervisor + * or output placement ID reserved by RM for vGPU type ID. + * + * TODO : This same RmCtrl will be also be used to provide GSP heap offset + * to CPU plugin when vGPU-GSP is enabled. + * (As guest fb and gsp heap is allocated before A084 object) + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO (0xa081011b) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS_MESSAGE_ID (0x1bU) + +typedef struct NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS { + NvBool isHeterogeneousEnabled; + NvU16 placementId; + NvU32 vgpuTypeId; + NV_DECLARE_ALIGNED(NvU64 guestFbLength, 8); + NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8); + NV_DECLARE_ALIGNED(NvU64 gspHeapOffset, 8); +} NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS; + +/* + * NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS + * + * This command fetches count and list of creatable vGPU placements + * + * Parameters: + * + * vgpuTypeId [IN] + * The client provided vGPU type ID + * + * placementSize [OUT] + * The number of placement slots occupied by the vGPU type + * + * count [OUT] + * This parameter returns the number of placements supported for the vGPU + * + * placementIds [OUT] + * Array of creatable placement IDs + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_NOT_SUPPORTED + */ + +#define NVA081_CTRL_CMD_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS (0xa081011c) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS_MESSAGE_ID (0x1cU) + +typedef struct NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS { + NvU32 vgpuTypeId; + NvU32 placementSize; + NvU32 count; + NvU32 placementIds[NVA081_MAX_VGPU_PER_PGPU]; +} NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS; + +/* + * NVA081_CTRL_CMD_PGPU_GET_VGPU_STREAMING_CAPABILITY + * + * This command is used to get streaming capability for the physical GPU. + * + * streamingCapability [OUT] + * This param specifies whether vGPU profiles on the GPU supports migration data streaming + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_REQUEST + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_PGPU_GET_VGPU_STREAMING_CAPABILITY (0xa081011d) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS_MESSAGE_ID (0x1dU) + +typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS { + NvBool streamingCapability; +} NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS; + +/* vGPU capabilities */ +#define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0 + +/* + * NVA081_CTRL_CMD_VGPU_SET_CAPABILITY + * + * This command is used to set vGPU capability for the physical GPU. + * + * capability [IN] + * This param specifies the requested capabiity of the device that is to be set + * One of NVA081_CTRL_VGPU_CAPABILITY* values + * + * state [IN] + * This param specifies the state of the capability + * + * Possible status values returned are: + * NV_OK + * NV_ERR_OBJECT_NOT_FOUND + * NV_ERR_INVALID_ARGUMENT + */ +#define NVA081_CTRL_CMD_VGPU_SET_CAPABILITY (0xa081011e) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID" */ + +#define NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID (0x1eU) + +typedef struct NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS { + NvU32 capability; + NvBool state; +} NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS; + /* _ctrlA081vgpuconfig_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla084.h b/src/common/sdk/nvidia/inc/ctrl/ctrla084.h index d00d8e0259..b86e38e651 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla084.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla084.h @@ -284,4 +284,28 @@ typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS */ #define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_RESTORE_DEFAULT_EXEC_PARTITION (0xa084010b) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | 0xB" */ +/* + * NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES + * + * This command is a KernelHostVgpuDeviceApi counterpart of + * NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES, that allows + * to clean up a VF state. + * + * Parameters: + * + * flags [IN] + * Specifies what states need to be freed, same as in NVA082_CTRL_CMD_HOST_VGPU_DEVICE_FREE_STATES + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_STATE + */ +#define NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_FREE_STATES (0xa084010c) /* finn: Evaluated from "(FINN_NVA084_KERNEL_HOST_VGPU_DEVICE_KERNEL_HOST_VGPU_DEVICE_INTERFACE_ID << 8) | NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS_MESSAGE_ID" */ + +#define NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS_MESSAGE_ID (0xCU) + +typedef struct NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS { + NvU32 flags; +} NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS; + /* _ctrla084_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla0bc.h b/src/common/sdk/nvidia/inc/ctrl/ctrla0bc.h new file mode 100644 index 0000000000..68e48106bb --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla0bc.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla0bc.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVENC_SW_SESSION control commands and parameters */ +#define NVA0BC_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA0BC, NVA0BC_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA0BC_CTRL_RESERVED (0x00) +#define NVA0BC_CTRL_NVENC_SW_SESSION (0x01) + +#define NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES 60 + +/* + * NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO + * + * This command is used to let RM know about runtime information about + * running NVENC session on given GPU. + * * + * hResolution + * This parameter specifies the current horizontal resolution of NVENC session. + * vResolution + * This parameter specifies the current vertical resolution of NVENC session. + * averageEncodeLatency + * This field specifies the average encode latency over last 1 second. + * averageEncodeFps + * This field specifies the average encode FPS over last 1 second. + * timestampBufferSize + * This field specifies the number of entries in the caller's timestampBuffer. + * It should not be greater than NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES. + * When this field is zero, RM will assume that client has calculated averageEncodeFps + * and averageEncodeLatency, thus ignore timestampBuffer. + * timestampBuffer + * This field specifies a pointer in the caller's address space + * to the buffer holding encode timestamps in microseconds. + * This buffer must be at least as big as timestampBufferSize multiplied + * by the size of the NVA0BC_CTRL_NVENC_TIMESTAMP structure. + * e.g. if there are 10 fps, buffer will contain only 10 entries and rest of + * entries should be 0x00. However if there are more than 60 fps, buffer will + * contain last/latest 60 entries of frame encoding start-end timestamps. Caller + * should make sure timestamps won't wrap around. RM assume that for each + * frame timestamp value endTime would be greater than startTime. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO (0xa0bc0101) /* finn: Evaluated from "(FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID << 8) | NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NVA0BC_CTRL_NVENC_TIMESTAMP { + NV_DECLARE_ALIGNED(NvU64 startTime, 8); + NV_DECLARE_ALIGNED(NvU64 endTime, 8); +} NVA0BC_CTRL_NVENC_TIMESTAMP; + +#define NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS { + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeLatency; + NvU32 averageEncodeFps; + NvU32 timestampBufferSize; + NV_DECLARE_ALIGNED(NvP64 timestampBuffer, 8); +} NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS; + +/* +* NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO_V2 +* +* This command updates the NVENC software sessions information for the associate GPU. +* This command is similar to NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO but doesn't have +* embedded pointers. +* +* Check NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO for detailed information. +*/ + +#define NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO_V2 (0xa0bc0102) /* finn: Evaluated from "(FINN_NVENC_SW_SESSION_NVENC_SW_SESSION_INTERFACE_ID << 8) | NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS_MESSAGE_ID" */ + +#define NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS { + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeLatency; + NvU32 averageEncodeFps; + NvU32 timestampBufferSize; + NV_DECLARE_ALIGNED(NVA0BC_CTRL_NVENC_TIMESTAMP timestampBuffer[NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES], 8); +} NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS; + +/* _ctrla0bc_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla0bd.h b/src/common/sdk/nvidia/inc/ctrl/ctrla0bd.h new file mode 100644 index 0000000000..2d046ac500 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla0bd.h @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrla0bd.finn +// + +#include "ctrl/ctrlxxxx.h" +/* NVFBC_SW_SESSION control commands and parameters */ +#define NVA0BD_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0xA0BD, NVA0BD_CTRL_##cat, idx) + +/* Command categories (6bits) */ +#define NVA0BD_CTRL_RESERVED (0x00) +#define NVA0BD_CTRL_NVFBC_SW_SESSION (0x01) + +#define NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES 60 + +/* + * NVA0BD_CTRL_CMD_NVFBC_SW_SESSION_UPDATE_INFO + * + * This command is used to let RM know about runtime information about + * NVFBC session on given GPU. + * * + * hResolution + * This parameter specifies the current horizontal resolution of NVFBC session. + * vResolution + * This parameter specifies the current vertical resolution of NVFBC session. + * captureCallFlags + * This field specifies the flags associated with the capture call and the session. + * One of the flags specifies whether the user made the capture with wait or not. + * totalGrabCalls + * This field specifies the total number of grab calls made by the user. + * averageLatency + * This field specifies the average capture latency over last 1 second. + * averageFPS + * This field specifies the average frames captured. + * timestampEntryCount + * This field specifies the number of entries in the timestampEntry array. + * It should not be greater than NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES. + * When this field is zero, RM will assume that client has calculated averageFBCFps + * and averageFBCLatency, thus ignore timestampEntry array. + * timestampEntry + * This field specifies a array holding capture timestamps in microseconds. + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_ARGUMENT + */ + +#define NVA0BD_CTRL_CMD_NVFBC_SW_SESSION_UPDATE_INFO (0xa0bd0101) /* finn: Evaluated from "(FINN_NVFBC_SW_SESSION_NVFBC_SW_SESSION_INTERFACE_ID << 8) | NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID" */ + +typedef struct NVA0BD_CTRL_NVFBC_TIMESTAMP { + NV_DECLARE_ALIGNED(NvU64 startTime, 8); + NV_DECLARE_ALIGNED(NvU64 endTime, 8); +} NVA0BD_CTRL_NVFBC_TIMESTAMP; + +#define NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS { + NvU32 hResolution; + NvU32 vResolution; + NvU32 captureCallFlags; + NvU32 totalGrabCalls; + NvU32 averageLatency; + NvU32 averageFPS; + NvU32 timestampEntryCount; + NV_DECLARE_ALIGNED(NVA0BD_CTRL_NVFBC_TIMESTAMP timestampEntry[NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES], 8); +} NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS; + +#define NVA0BD_NVFBC_WITH_WAIT 1:0 +#define NVA0BD_NVFBC_WITH_WAIT_FALSE (0x00000000) +#define NVA0BD_NVFBC_WITH_WAIT_INFINITE (0x00000001) +#define NVA0BD_NVFBC_WITH_WAIT_TIMEOUT (0x00000010) + +/* _ctrla0bd_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h index 533748f6fb..3e8e16b22a 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccinternal.h @@ -48,7 +48,71 @@ typedef struct NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS { NV_DECLARE_ALIGNED(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS params, 8); } NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM_FINN_PARAMS; +/*! + * NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL + * + * This command is used to quiesce ongoing HWPM streamout and wait for PMA engine to + * become idle. After this point, no new PMA records would be generated and + * membytes streaming would be triggered if GR context is resident or HWPM ctxsw is disabled. + */ +#define NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL (0xb0cc0201) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_MESSAGE_ID (0x1U) + +typedef struct NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS { + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; + + /*! + * [out] Will return if membytes streaming was triggered, to decide if + * we need to poll membytes value on guest to complete streamout. + */ + NvBool bMembytesPollingRequired; +} NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS; + +/*! + * NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM + * + * Currently only used in vGPU full SRIOV mode. + * This command is used to promote VAs and required info about the HWPM IB + * and PMA buffers from guest to host in full SRIOV mode. + */ +#define NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM (0xb0cc0202) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_INTERNAL_INTERFACE_ID << 8) | NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID" */ + +#define NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_MESSAGE_ID (0x2U) + +typedef struct NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS { + /*! + * [in] The PMA Channel Index associated with a given PMA stream. + */ + NvU32 pmaChannelIdx; + /*! + * [in] PMA records buffer VA. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferVA, 8); + + /*! + * [in] size of the PMA records buffer. This must be <= NVB0CC_PMA_BUFFER_SIZE_MAX. + */ + NV_DECLARE_ALIGNED(NvU64 pmaBufferSize, 8); + /*! + * [in] Membytes buffer VA. + */ + NV_DECLARE_ALIGNED(NvU64 membytesVA, 8); + + /*! + * [in] HWPM PMA Instance Block PA + */ + NV_DECLARE_ALIGNED(NvU64 hwpmIBPA, 8); + + /*! + * [in] HWPM PMA Instance Block aperture + */ + NvU8 hwpmIBAperture; +} NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS; /*! * NVB0CC_CTRL_CMD_INTERNAL_PERMISSIONS_INIT diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h index fad97c53fa..7f1420dc59 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h @@ -591,4 +591,6 @@ typedef struct NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS { NvBool enabled; } NVB0CC_CTRL_GET_DYNAMIC_MMA_BOOST_STATUS_PARAMS; + + /* _ctrlb0ccprofiler_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370or.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370or.h new file mode 100644 index 0000000000..3e5e644cc5 --- /dev/null +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370or.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#include + +// +// This file was generated with FINN, an NVIDIA coding tool. +// Source file: ctrl/ctrlc370/ctrlc370or.finn +// + + + +#include "ctrl/ctrlc370/ctrlc370base.h" +/* C370 is partially derived from 5070 */ +#include "ctrl/ctrl5070/ctrl5070or.h" + + +/* _ctrlc370or_h_ */ + diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h index 58b0291b98..e18f96cf40 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc372/ctrlc372chnc.h @@ -147,16 +147,36 @@ * (On older post-Volta products, clients may set other * NVC372_CTRL_IMP_LUT_USAGE_xxx values, but they map to * NVC372_CTRL_IMP_LUT_USAGE_HW_MAX in RM-SW.) - * * head.cursorSize32p * This parameter specifies the width of the cursor, in units of 32 pixels. * So, for example, "8" would mean 8 * 32 = 256, for a 256x256 cursor. Zero * means the cursor is disabled. * + * head.tileMask + * This parameter specifies the number of tiles which will be assigned to + * the head. Normally, this parameter is set to zero, allowing IMP to + * calculate the number of tiles, but the number of tiles may be specified + * explicitly for test or debug. If the mode is not possible with the + * specified number of tiles, IMP will report the result as such; the + * number of tiles will not be adjusted. + * + * If tiles are forced for only a subset of active heads, IMP will + * calculate the tiles for the remaining heads (if possible). + * + * If head.bEnableDsc is enabled, head.possibleDscSliceCountMask may + * optionally be used to force the number of DSC slices. + * * head.bEnableDsc * bEnableDsc indicates whether or not DSC is enabled * + * head.dscTargetBppX16 + * dscTargetBppX16 is the DSC encoder's target bits per pixel, multiplied + * by 16. + * + * This field is required only on systems that support tiling, and only if + * head.bEnableDsc is true. + * * head.possibleDscSliceCountMask * This is a bit mask indicating how many DSC slices are allowed in a * scanline. If a bit n is set in the bit mask, it means that one possible @@ -584,8 +604,12 @@ typedef struct NVC372_CTRL_IMP_HEAD { NvU8 lut; NvU8 cursorSize32p; + NvU8 tileMask; + NvBool bEnableDsc; + NvU16 dscTargetBppX16; + NvU32 possibleDscSliceCountMask; NvU32 maxDscSliceWidth; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h index 1a226c28ee..0bb5554e50 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -162,12 +162,27 @@ typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { NvU32 workSubmitToken; } NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS; +/* + * NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR + * + * This struct defines the addresses to log encryption statistics + * amountEncryptedAddr + * Amount of bytes encrypted + * numberEncryptedAddr + * Number of times data was encrypted. + */ +typedef struct NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR { + NV_DECLARE_ALIGNED(NvP64 amountEncryptedAddr, 8); + NV_DECLARE_ALIGNED(NvP64 numberEncryptedAddr, 8); +} NVC56F_CTRL_CMD_GET_KMB_STAT_ADDR; + /* * NVC56F_CTRL_CMD_GET_KMB * * This command returns the Key Material Bundle (KMB) for the current channel. - * - * kmb [OUT] The KMB for the channel. + * + * kmb [OUT] The KMB for the channel. + * hMemory [IN] Memory handle to the encryption statistics buffer for the channel. * * Possible status values returned are: * NV_OK @@ -180,7 +195,8 @@ typedef struct NVC56F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS { #define NVC56F_CTRL_CMD_GET_KMB_PARAMS_MESSAGE_ID (0xBU) typedef struct NVC56F_CTRL_CMD_GET_KMB_PARAMS { - CC_KMB kmb; + CC_KMB kmb; + NvHandle hMemory; } NVC56F_CTRL_CMD_GET_KMB_PARAMS; /* @@ -206,6 +222,60 @@ typedef struct NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS { CC_KMB updatedKmb; } NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS; +/* + * NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY + * + * This command sets the CC security policy. + * It can only be set before GpuReadyState is set. + * Is ignored after GpuReadyState is set. + * + * attackerAdvantage [IN] + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_STATE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +/* + * The minimum and maximum values for attackerAdvantage. + * The probability of an attacker successfully guessing the contents of an encrypted packet go up ("attacker advantage"). + */ +#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MIN (50) +#define SET_SECURITY_POLICY_ATTACKER_ADVANTAGE_MAX (75) + +#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY (0xc56f010d) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xDU) + +typedef struct NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS { + NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8); +} NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS; + +/* + * NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY + * + * This command get the CC security policy. + * + * attackerAdvantage [OUT] + * + * Possible status values returned are: + * NV_OK + * NV_ERR_INVALID_OBJECT_HANDLE + * NV_ERR_INVALID_ARGUMENT + * NV_ERR_NOT_SUPPORTED + */ + +#define NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY (0xc56f010e) /* finn: Evaluated from "(FINN_AMPERE_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS_MESSAGE_ID" */ + +#define NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS_MESSAGE_ID (0xEU) + +typedef struct NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS { + NV_DECLARE_ALIGNED(NvU64 attackerAdvantage, 8); +} NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS; + /* _ctrlc56f.h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h index 16c69a74aa..a06c3e1dd8 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlc637.h @@ -391,4 +391,17 @@ typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS { NvU32 totalSpansCount; } NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS; +/* + * NVC637_CTRL_CMD_GET_UUID + */ +#define NVC637_CTRL_CMD_GET_UUID (0xc63701aaU) /* finn: Evaluated from "(FINN_AMPERE_SMC_PARTITION_REF_EXEC_PARTITIONS_INTERFACE_ID << 8) | NVC637_CTRL_GET_UUID_PARAMS_MESSAGE_ID" */ + +#define NVC637_CTRL_GET_UUID_PARAMS_MESSAGE_ID (0xAAU) + +typedef struct NVC637_CTRL_GET_UUID_PARAMS { + NvU8 uuid[NVC637_UUID_LEN]; + + char uuidStr[NVC637_UUID_STR_LEN]; +} NVC637_CTRL_GET_UUID_PARAMS; + // _ctrlc637_h_ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h b/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h index ee997955f4..f2b872cb44 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h @@ -89,6 +89,8 @@ * Dev tools mode is used for debugging/profiling * Dev tools mode is set at system level and implies that all GPUs in * the system have this mode enabled/disabled + * multiGpuMode: [OUT] + * Specifies the mode in which a multi gpu system is operating * * cpuCapability, gpusCapability & environment are determined by the * driver and cannot be modified later on @@ -101,26 +103,29 @@ * NV_ERR_INVALID_CLIENT * NV_ERR_OBJECT_NOT_FOUND */ -#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */ +#define NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES (0xcb330101) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0x1" */ -#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0 -#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1 -#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_AMD_SEV 1 +#define NV_CONF_COMPUTE_SYSTEM_CPU_CAPABILITY_INTEL_TDX 2 -#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0 -#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1 -#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_APM 1 +#define NV_CONF_COMPUTE_SYSTEM_GPUS_CAPABILITY_HCC 2 -#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0 -#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1 -#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE 0 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM 1 +#define NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD 2 -#define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0 -#define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1 -#define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED 0 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_APM_ENABLED 1 +#define NV_CONF_COMPUTE_SYSTEM_FEATURE_HCC_ENABLED 2 -#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0 -#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1 +#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED 0 +#define NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED 1 + +#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE 0 +#define NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE 1 typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS { NvU8 cpuCapability; @@ -128,6 +133,7 @@ typedef struct NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS { NvU8 environment; NvU8 ccFeature; NvU8 devToolsMode; + NvU8 multiGpuMode; } NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS; /* diff --git a/src/common/sdk/nvidia/inc/g_finn_rm_api.h b/src/common/sdk/nvidia/inc/g_finn_rm_api.h index b1b14c667a..f699582ea1 100644 --- a/src/common/sdk/nvidia/inc/g_finn_rm_api.h +++ b/src/common/sdk/nvidia/inc/g_finn_rm_api.h @@ -219,8 +219,6 @@ typedef FINN_RM_API FINN_NV01_TIMER_TMR; typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_RESERVED; #define FINN_FABRIC_MANAGER_SESSION_FM_INTERFACE_ID (0xf01U) typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_FM; -#define FINN_FABRIC_MANAGER_SESSION_IMEX_INTERFACE_ID (0xf02U) -typedef FINN_RM_API FINN_FABRIC_MANAGER_SESSION_IMEX; #define FINN_NV0020_GPU_MANAGEMENT_RESERVED_INTERFACE_ID (0x2000U) typedef FINN_RM_API FINN_NV0020_GPU_MANAGEMENT_RESERVED; #define FINN_NV0020_GPU_MANAGEMENT_GPU_MGMT_INTERFACE_ID (0x2001U) @@ -302,18 +300,6 @@ typedef FINN_RM_API FINN_NV_MEMORY_EXPORT_RESERVED; typedef FINN_RM_API FINN_NV_MEMORY_EXPORT; #define FINN_IMEX_SESSION_INTERFACE_ID (0xf100U) typedef FINN_RM_API FINN_IMEX_SESSION; -#define FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf400U) -typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_RESERVED; -#define FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT_INTERFACE_ID (0xf401U) -typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_EXPORT_EXPORT; -#define FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED_INTERFACE_ID (0xf500U) -typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_RESERVED; -#define FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT_INTERFACE_ID (0xf501U) -typedef FINN_RM_API FINN_NV01_MEMORY_FABRIC_IMPORT_IMPORT; -#define FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED_INTERFACE_ID (0xf700U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT_RESERVED; -#define FINN_NV_MEMORY_FABRIC_EXPORT_INTERFACE_ID (0xf701U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORT; #define FINN_NV_MEMORY_FABRIC_RESERVED_INTERFACE_ID (0xf800U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_RESERVED; #define FINN_NV_MEMORY_FABRIC_FABRIC_INTERFACE_ID (0xf801U) @@ -322,10 +308,6 @@ typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_FABRIC; typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_RESERVED; #define FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT_INTERFACE_ID (0xf901U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORT_V2_IMPORT; -#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED_INTERFACE_ID (0xfa00U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_RESERVED; -#define FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF_INTERFACE_ID (0xfa01U) -typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_EXPORTED_REF_EXPORT_REF; #define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED_INTERFACE_ID (0xfb00U) typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_RESERVED; #define FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF_INTERFACE_ID (0xfb01U) @@ -334,7 +316,7 @@ typedef FINN_RM_API FINN_NV_MEMORY_FABRIC_IMPORTED_REF_IMPORT_REF; typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_RESERVED; #define FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC_INTERFACE_ID (0xfd01U) typedef FINN_RM_API FINN_NV_MEMORY_MULTICAST_FABRIC_FABRIC; -#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0x00FE00U) +#define FINN_NV_MEMORY_MAPPER_INTERFACE_ID (0xfe01U) typedef FINN_RM_API FINN_NV_MEMORY_MAPPER; #define FINN_NV20_SUBDEVICE_0_RESERVED_INTERFACE_ID (0x208000U) @@ -587,7 +569,8 @@ typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_EVENT; typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO; #define FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL_INTERFACE_ID (0xa06f03U) typedef FINN_RM_API FINN_KEPLER_CHANNEL_GPFIFO_A_INTERNAL; - +#define FINN_KEPLER_DEVICE_VGPU_RESERVED_INTERFACE_ID (0xa08000U) +typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_RESERVED; #define FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY_INTERFACE_ID (0xa08001U) typedef FINN_RM_API FINN_KEPLER_DEVICE_VGPU_VGPU_DISPLAY; #define FINN_KEPLER_DEVICE_VGPU_VGPU_MEMORY_INTERFACE_ID (0xa08002U) @@ -690,6 +673,8 @@ typedef FINN_RM_API FINN_NVC370_DISPLAY_RESERVED; typedef FINN_RM_API FINN_NVC370_DISPLAY_CHNCTL; #define FINN_NVC370_DISPLAY_EVENT_INTERFACE_ID (0xc37009U) typedef FINN_RM_API FINN_NVC370_DISPLAY_EVENT; +#define FINN_NVC370_DISPLAY_OR_INTERFACE_ID (0xc37004U) +typedef FINN_RM_API FINN_NVC370_DISPLAY_OR; #define FINN_NVC370_DISPLAY_RG_INTERFACE_ID (0xc37002U) typedef FINN_RM_API FINN_NVC370_DISPLAY_RG; #define FINN_NVC370_DISPLAY_VERIF_INTERFACE_ID (0xc37006U) @@ -747,6 +732,10 @@ typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE; typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_RESERVED; #define FINN_NV_COUNTER_COLLECTION_UNIT_CCU_INTERFACE_ID (0xcbca01U) typedef FINN_RM_API FINN_NV_COUNTER_COLLECTION_UNIT_CCU; +#define FINN_NV_SCHEDULER_RESERVED_INTERFACE_ID (0xcbcb00U) +typedef FINN_RM_API FINN_NV_SCHEDULER_RESERVED; +#define FINN_NV_SCHEDULER_SCHEDULER_INTERFACE_ID (0xcbcb01U) +typedef FINN_RM_API FINN_NV_SCHEDULER_SCHEDULER; #define FINN_NVE2_SYNCPOINT_BASE_RESERVED_INTERFACE_ID (0xe2ad00U) typedef FINN_RM_API FINN_NVE2_SYNCPOINT_BASE_RESERVED; #define FINN_NVE2_SYNCPOINT_BASE_SYNCPOINT_BASE_INTERFACE_ID (0xe2ad01U) diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index 9ef5493037..3e10ddbea8 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -61,6 +61,7 @@ #define ROBUST_CHANNEL_PREEMPTIVE_REMOVAL (45) #define ROBUST_CHANNEL_NVENC0_ERROR (47) #define ROBUST_CHANNEL_GPU_ECC_DBE (48) +#define FB_MEMORY_ERROR (58) #define PMU_ERROR (59) #define ROBUST_CHANNEL_SEC2_ERROR (60) #define PMU_BREAKPOINT (61) @@ -108,6 +109,7 @@ #define ROBUST_CHANNEL_NVJPG5_ERROR (103) #define ROBUST_CHANNEL_NVJPG6_ERROR (104) #define ROBUST_CHANNEL_NVJPG7_ERROR (105) +#define DESTINATION_FLA_TRANSLATION_ERROR (108) #define SEC_FAULT_ERROR (110) #define GSP_RPC_TIMEOUT (119) #define GSP_ERROR (120) @@ -120,7 +122,9 @@ #define NVLINK_FLA_PRIV_ERR (137) #define ROBUST_CHANNEL_DLA_ERROR (138) #define UNRECOVERABLE_ECC_ERROR_ESCAPE (140) -#define ROBUST_CHANNEL_LAST_ERROR (UNRECOVERABLE_ECC_ERROR_ESCAPE) +#define ROBUST_CHANNEL_FAST_PATH_ERROR (141) +#define GPU_INIT_ERROR (143) +#define ROBUST_CHANNEL_LAST_ERROR (GPU_INIT_ERROR) // Indexed CE reference diff --git a/src/common/sdk/nvidia/inc/nvmisc.h b/src/common/sdk/nvidia/inc/nvmisc.h index fa33a9ffd9..6c47b6d3e1 100644 --- a/src/common/sdk/nvidia/inc/nvmisc.h +++ b/src/common/sdk/nvidia/inc/nvmisc.h @@ -919,6 +919,9 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address) // #define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); } +// Get the number of elements the specified fixed-size array +#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) + #ifdef __cplusplus } #endif //__cplusplus diff --git a/src/common/sdk/nvidia/inc/nvos.h b/src/common/sdk/nvidia/inc/nvos.h index 15d1465960..d9f23bdf99 100644 --- a/src/common/sdk/nvidia/inc/nvos.h +++ b/src/common/sdk/nvidia/inc/nvos.h @@ -722,6 +722,7 @@ typedef struct NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated } AllocSize; // NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT @@ -748,6 +749,7 @@ typedef struct NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive. NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated } AllocTiledPitchHeight; // NVOS32_FUNCTION_FREE @@ -823,6 +825,7 @@ typedef struct NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET) + NvS32 numaNode; // [IN] - NUMA node from which memory should be allocated } AllocSizeRange; // additions for Longhorn @@ -1300,6 +1303,11 @@ typedef struct #define NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE 0x00000000 #define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001 +// Deprecated. To be deleted once client code has removed references. +#define NVOS32_ATTR2_USE_EGM 24:24 +#define NVOS32_ATTR2_USE_EGM_FALSE 0x00000000 +#define NVOS32_ATTR2_USE_EGM_TRUE 0x00000001 + // // Allow client allocations to go to protected/unprotected video/system memory. // When Ampere Protected Model aka APM or Confidential Compute is enabled and @@ -1834,6 +1842,18 @@ typedef struct #define NVOS33_FLAGS_CACHING_TYPE_DEFAULT 6 #define NVOS33_FLAGS_CACHING_TYPE_UNCACHED_WEAK 7 +// +// For use when Hopper Confidential Compute is operating in devtools mode +// BAR1 access to CPR vidmem is blocked to CPU-RM by default when HCC is +// enabled in both devtools and prod modes. However, certain mappings are +// allowed to go through successfully only in devtools mode. For example, +// CPU mappings made on behalf of devtools, event buffer mappings are allowed +// to happen in devtools mode +// +#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC 26:26 +#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_NO (0x00000000) +#define NVOS33_FLAGS_ALLOW_MAPPING_ON_HCC_YES (0x00000001) + /* parameters */ typedef struct { @@ -2159,6 +2179,7 @@ typedef struct NvHandle hMemory; // [IN] memory handle for mapping NvV32 flags; // [IN] flags NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dma offset from NV04_MAP_MEMORY_DMA + NvU64 size NV_ALIGN_BYTES(8); // [IN] size to unmap, 0 to unmap entire mapping NvV32 status; // [OUT] status } NVOS47_PARAMETERS; @@ -2423,7 +2444,8 @@ typedef struct { #define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR 0x00000000 #define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN 0x00000001 -#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 2 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_KEY_ROTATION_STATUS 0x00000002 +#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 3 #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE 14:0 #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS 15:15 #define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1 @@ -2727,6 +2749,7 @@ typedef struct #define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL BIT(10) #define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11) #define NV_VASPACE_ALLOCATION_FLAGS_REQUIRE_FIXED_OFFSET BIT(12) +#define NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED BIT(13) #define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //= requested wait value") +NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event") // Warnings: NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch") diff --git a/src/common/sdk/nvidia/inc/nvtypes.h b/src/common/sdk/nvidia/inc/nvtypes.h index 5d3e853e3f..f20a927de3 100644 --- a/src/common/sdk/nvidia/inc/nvtypes.h +++ b/src/common/sdk/nvidia/inc/nvtypes.h @@ -141,7 +141,12 @@ typedef signed short NvS16; /* -32768 to 32767 */ #endif // Macro to build an NvU32 from four bytes, listed from msb to lsb -#define NvU32_BUILD(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) +#define NvU32_BUILD(a, b, c, d) \ + ((NvU32)( \ + (((NvU32)(a) & 0xff) << 24) | \ + (((NvU32)(b) & 0xff) << 16) | \ + (((NvU32)(c) & 0xff) << 8) | \ + (((NvU32)(d) & 0xff)))) #if NVTYPES_USE_STDINT typedef uint32_t NvV32; /* "void": enumerated or multiple fields */ diff --git a/src/common/shared/inc/g_vgpu_chip_flags.h b/src/common/shared/inc/g_vgpu_chip_flags.h new file mode 100644 index 0000000000..258e6297a8 --- /dev/null +++ b/src/common/shared/inc/g_vgpu_chip_flags.h @@ -0,0 +1,1138 @@ +/************************************************************************************ + * ################### THIS FILE IS AUTOGENERATED. DO NOT EDIT. ################### * + ***********************************************************************************/ + +#if !defined(_G_VGPU_CHIP_FLAGS_H_) +#define _G_VGPU_CHIP_FLAGS_H_ + +typedef struct _VGPU_USM_TYPES { + unsigned short ulDevID; + unsigned short ulSubID; + unsigned short ulSubSystemVendorID; +#if defined(NV_VGPU_CHIP_FLAGS_INCLUDE_NAME) + const char *sDevName; +#endif +} VGPU_USM_TYPES; + +#if defined(NV_VGPU_CHIP_FLAGS_INCLUDE_NAME) +#define ENTRY(a,b,c,d) { a, b, c, d } +#else +#define ENTRY(a,b,c,d) { a, b, c } +#endif + +static const VGPU_USM_TYPES sVgpuUsmTypesAC[] = { +ENTRY(0x2684, 0x17D1, 0x10de, "NVIDIA AC AD102 12Q"), +ENTRY(0x2684, 0x17D2, 0x10de, "NVIDIA AC AD102 20Q"), +ENTRY(0x2785, 0x17D1, 0x10de, "NVIDIA AC AD104 12Q"), +ENTRY(0x2785, 0x17D2, 0x10de, "NVIDIA AC AD104 20Q"), +ENTRY(0x2785, 0x17D3, 0x10de, "NVIDIA AC AD104-A 4Q"), +ENTRY(0x2785, 0x17D4, 0x10de, "NVIDIA AC AD104-A 8Q"), +}; + +static const VGPU_USM_TYPES sVgpuUsmTypes[] = { +ENTRY(0x13BD, 0x11CC, 0x10de, "GRID M10-0B"), +ENTRY(0x13BD, 0x11CD, 0x10de, "GRID M10-1B"), +ENTRY(0x13BD, 0x11CE, 0x10de, "GRID M10-0Q"), +ENTRY(0x13BD, 0x11CF, 0x10de, "GRID M10-1Q"), +ENTRY(0x13BD, 0x11D0, 0x10de, "GRID M10-2Q"), +ENTRY(0x13BD, 0x11D1, 0x10de, "GRID M10-4Q"), +ENTRY(0x13BD, 0x11D2, 0x10de, "GRID M10-8Q"), +ENTRY(0x13BD, 0x11D3, 0x10de, "GRID M10-1A"), +ENTRY(0x13BD, 0x11D4, 0x10de, "GRID M10-2A"), +ENTRY(0x13BD, 0x11D5, 0x10de, "GRID M10-4A"), +ENTRY(0x13BD, 0x11D6, 0x10de, "GRID M10-8A"), +ENTRY(0x13BD, 0x1286, 0x10de, "GRID M10-2B"), +ENTRY(0x13BD, 0x12EE, 0x10de, "GRID M10-2B4"), +ENTRY(0x13BD, 0x1339, 0x10de, "GRID M10-1B4"), +ENTRY(0x13F2, 0x114C, 0x10de, "GRID M60-0Q"), +ENTRY(0x13F2, 0x114D, 0x10de, "GRID M60-1Q"), +ENTRY(0x13F2, 0x114E, 0x10de, "GRID M60-2Q"), +ENTRY(0x13F2, 0x114F, 0x10de, "GRID M60-4Q"), +ENTRY(0x13F2, 0x1150, 0x10de, "GRID M60-8Q"), +ENTRY(0x13F2, 0x1176, 0x10de, "GRID M60-0B"), +ENTRY(0x13F2, 0x1177, 0x10de, "GRID M60-1B"), +ENTRY(0x13F2, 0x117D, 0x10de, "GRID M60-2B"), +ENTRY(0x13F2, 0x11AE, 0x10de, "GRID M60-1A"), +ENTRY(0x13F2, 0x11AF, 0x10de, "GRID M60-2A"), +ENTRY(0x13F2, 0x11B0, 0x10de, "GRID M60-4A"), +ENTRY(0x13F2, 0x11B1, 0x10de, "GRID M60-8A"), +ENTRY(0x13F2, 0x12EC, 0x10de, "GRID M60-2B4"), +ENTRY(0x13F2, 0x1337, 0x10de, "GRID M60-1B4"), +ENTRY(0x13F3, 0x117C, 0x10de, "GRID M6-2B"), +ENTRY(0x13F3, 0x117E, 0x10de, "GRID M6-0B"), +ENTRY(0x13F3, 0x117F, 0x10de, "GRID M6-1B"), +ENTRY(0x13F3, 0x1180, 0x10de, "GRID M6-0Q"), +ENTRY(0x13F3, 0x1181, 0x10de, "GRID M6-1Q"), +ENTRY(0x13F3, 0x1182, 0x10de, "GRID M6-2Q"), +ENTRY(0x13F3, 0x1183, 0x10de, "GRID M6-4Q"), +ENTRY(0x13F3, 0x1184, 0x10de, "GRID M6-8Q"), +ENTRY(0x13F3, 0x11AA, 0x10de, "GRID M6-1A"), +ENTRY(0x13F3, 0x11AB, 0x10de, "GRID M6-2A"), +ENTRY(0x13F3, 0x11AC, 0x10de, "GRID M6-4A"), +ENTRY(0x13F3, 0x11AD, 0x10de, "GRID M6-8A"), +ENTRY(0x13F3, 0x12ED, 0x10de, "GRID M6-2B4"), +ENTRY(0x13F3, 0x1338, 0x10de, "GRID M6-1B4"), +ENTRY(0x15F7, 0x1265, 0x10de, "GRID P100C-1B"), +ENTRY(0x15F7, 0x1266, 0x10de, "GRID P100C-1Q"), +ENTRY(0x15F7, 0x1267, 0x10de, "GRID P100C-2Q"), +ENTRY(0x15F7, 0x1268, 0x10de, "GRID P100C-4Q"), +ENTRY(0x15F7, 0x1269, 0x10de, "GRID P100C-6Q"), +ENTRY(0x15F7, 0x126A, 0x10de, "GRID P100C-12Q"), +ENTRY(0x15F7, 0x126B, 0x10de, "GRID P100C-1A"), +ENTRY(0x15F7, 0x126C, 0x10de, "GRID P100C-2A"), +ENTRY(0x15F7, 0x126D, 0x10de, "GRID P100C-4A"), +ENTRY(0x15F7, 0x126E, 0x10de, "GRID P100C-6A"), +ENTRY(0x15F7, 0x126F, 0x10de, "GRID P100C-12A"), +ENTRY(0x15F7, 0x128D, 0x10de, "GRID P100C-2B"), +ENTRY(0x15F7, 0x12F4, 0x10de, "GRID P100C-2B4"), +ENTRY(0x15F7, 0x133F, 0x10de, "GRID P100C-1B4"), +ENTRY(0x15F7, 0x137D, 0x10de, "GRID P100C-12C"), +ENTRY(0x15F7, 0x138C, 0x10de, "GRID P100C-4C"), +ENTRY(0x15F7, 0x138D, 0x10de, "GRID P100C-6C"), +ENTRY(0x15F8, 0x1221, 0x10de, "GRID P100-1B"), +ENTRY(0x15F8, 0x1222, 0x10de, "GRID P100-1Q"), +ENTRY(0x15F8, 0x1223, 0x10de, "GRID P100-2Q"), +ENTRY(0x15F8, 0x1224, 0x10de, "GRID P100-4Q"), +ENTRY(0x15F8, 0x1225, 0x10de, "GRID P100-8Q"), +ENTRY(0x15F8, 0x1226, 0x10de, "GRID P100-16Q"), +ENTRY(0x15F8, 0x1227, 0x10de, "GRID P100-1A"), +ENTRY(0x15F8, 0x1228, 0x10de, "GRID P100-2A"), +ENTRY(0x15F8, 0x1229, 0x10de, "GRID P100-4A"), +ENTRY(0x15F8, 0x122A, 0x10de, "GRID P100-8A"), +ENTRY(0x15F8, 0x122B, 0x10de, "GRID P100-16A"), +ENTRY(0x15F8, 0x128C, 0x10de, "GRID P100-2B"), +ENTRY(0x15F8, 0x12F2, 0x10de, "GRID P100-2B4"), +ENTRY(0x15F8, 0x133D, 0x10de, "GRID P100-1B4"), +ENTRY(0x15F8, 0x137C, 0x10de, "GRID P100-16C"), +ENTRY(0x15F8, 0x138A, 0x10de, "GRID P100-4C"), +ENTRY(0x15F8, 0x138B, 0x10de, "GRID P100-8C"), +ENTRY(0x15F9, 0x122C, 0x10de, "GRID P100X-1B"), +ENTRY(0x15F9, 0x122D, 0x10de, "GRID P100X-1Q"), +ENTRY(0x15F9, 0x122E, 0x10de, "GRID P100X-2Q"), +ENTRY(0x15F9, 0x122F, 0x10de, "GRID P100X-4Q"), +ENTRY(0x15F9, 0x1230, 0x10de, "GRID P100X-8Q"), +ENTRY(0x15F9, 0x1231, 0x10de, "GRID P100X-16Q"), +ENTRY(0x15F9, 0x1232, 0x10de, "GRID P100X-1A"), +ENTRY(0x15F9, 0x1233, 0x10de, "GRID P100X-2A"), +ENTRY(0x15F9, 0x1234, 0x10de, "GRID P100X-4A"), +ENTRY(0x15F9, 0x1235, 0x10de, "GRID P100X-8A"), +ENTRY(0x15F9, 0x1236, 0x10de, "GRID P100X-16A"), +ENTRY(0x15F9, 0x128B, 0x10de, "GRID P100X-2B"), +ENTRY(0x15F9, 0x12F3, 0x10de, "GRID P100X-2B4"), +ENTRY(0x15F9, 0x133E, 0x10de, "GRID P100X-1B4"), +ENTRY(0x15F9, 0x137B, 0x10de, "GRID P100X-16C"), +ENTRY(0x15F9, 0x1388, 0x10de, "GRID P100X-4C"), +ENTRY(0x15F9, 0x1389, 0x10de, "GRID P100X-8C"), +ENTRY(0x1B38, 0x11E7, 0x10de, "GRID P40-1B"), +ENTRY(0x1B38, 0x11E8, 0x10de, "GRID P40-1Q"), +ENTRY(0x1B38, 0x11E9, 0x10de, "GRID P40-2Q"), +ENTRY(0x1B38, 0x11EA, 0x10de, "GRID P40-3Q"), +ENTRY(0x1B38, 0x11EB, 0x10de, "GRID P40-4Q"), +ENTRY(0x1B38, 0x11EC, 0x10de, "GRID P40-6Q"), +ENTRY(0x1B38, 0x11ED, 0x10de, "GRID P40-8Q"), +ENTRY(0x1B38, 0x11EE, 0x10de, "GRID P40-12Q"), +ENTRY(0x1B38, 0x11EF, 0x10de, "GRID P40-24Q"), +ENTRY(0x1B38, 0x11F0, 0x10de, "GRID P40-1A"), +ENTRY(0x1B38, 0x11F1, 0x10de, "GRID P40-2A"), +ENTRY(0x1B38, 0x11F2, 0x10de, "GRID P40-3A"), +ENTRY(0x1B38, 0x11F3, 0x10de, "GRID P40-4A"), +ENTRY(0x1B38, 0x11F4, 0x10de, "GRID P40-6A"), +ENTRY(0x1B38, 0x11F5, 0x10de, "GRID P40-8A"), +ENTRY(0x1B38, 0x11F6, 0x10de, "GRID P40-12A"), +ENTRY(0x1B38, 0x11F7, 0x10de, "GRID P40-24A"), +ENTRY(0x1B38, 0x1287, 0x10de, "GRID P40-2B"), +ENTRY(0x1B38, 0x12B1, 0x10de, "GeForce GTX P40-24"), +ENTRY(0x1B38, 0x12B2, 0x10de, "GeForce GTX P40-12"), +ENTRY(0x1B38, 0x12B3, 0x10de, "GeForce GTX P40-6"), +ENTRY(0x1B38, 0x12EF, 0x10de, "GRID P40-2B4"), +ENTRY(0x1B38, 0x133A, 0x10de, "GRID P40-1B4"), +ENTRY(0x1B38, 0x137E, 0x10de, "GRID P40-24C"), +ENTRY(0x1B38, 0x1381, 0x10de, "GRID P40-4C"), +ENTRY(0x1B38, 0x1382, 0x10de, "GRID P40-6C"), +ENTRY(0x1B38, 0x1383, 0x10de, "GRID P40-8C"), +ENTRY(0x1B38, 0x1384, 0x10de, "GRID P40-12C"), +ENTRY(0x1B38, 0x13B0, 0x10de, "GRID GTX P40-6"), +ENTRY(0x1B38, 0x13B1, 0x10de, "GRID GTX P40-12"), +ENTRY(0x1B38, 0x13B2, 0x10de, "GRID GTX P40-24"), +ENTRY(0x1B38, 0x13D0, 0x10de, "GRID GTX P40-8"), +ENTRY(0x1BB3, 0x1203, 0x10de, "GRID P4-1B"), +ENTRY(0x1BB3, 0x1204, 0x10de, "GRID P4-1Q"), +ENTRY(0x1BB3, 0x1205, 0x10de, "GRID P4-2Q"), +ENTRY(0x1BB3, 0x1206, 0x10de, "GRID P4-4Q"), +ENTRY(0x1BB3, 0x1207, 0x10de, "GRID P4-8Q"), +ENTRY(0x1BB3, 0x1208, 0x10de, "GRID P4-1A"), +ENTRY(0x1BB3, 0x1209, 0x10de, "GRID P4-2A"), +ENTRY(0x1BB3, 0x120A, 0x10de, "GRID P4-4A"), +ENTRY(0x1BB3, 0x120B, 0x10de, "GRID P4-8A"), +ENTRY(0x1BB3, 0x1288, 0x10de, "GRID P4-2B"), +ENTRY(0x1BB3, 0x12F1, 0x10de, "GRID P4-2B4"), +ENTRY(0x1BB3, 0x133C, 0x10de, "GRID P4-1B4"), +ENTRY(0x1BB3, 0x136D, 0x10de, "GRID GTX P4-2"), +ENTRY(0x1BB3, 0x136E, 0x10de, "GRID GTX P4-4"), +ENTRY(0x1BB3, 0x136F, 0x10de, "GRID GTX P4-8"), +ENTRY(0x1BB3, 0x1380, 0x10de, "GRID P4-8C"), +ENTRY(0x1BB3, 0x1385, 0x10de, "GRID P4-4C"), +ENTRY(0x1BB4, 0x11F8, 0x10de, "GRID P6-1B"), +ENTRY(0x1BB4, 0x11F9, 0x10de, "GRID P6-1Q"), +ENTRY(0x1BB4, 0x11FA, 0x10de, "GRID P6-2Q"), +ENTRY(0x1BB4, 0x11FB, 0x10de, "GRID P6-4Q"), +ENTRY(0x1BB4, 0x11FC, 0x10de, "GRID P6-8Q"), +ENTRY(0x1BB4, 0x11FD, 0x10de, "GRID P6-16Q"), +ENTRY(0x1BB4, 0x11FE, 0x10de, "GRID P6-1A"), +ENTRY(0x1BB4, 0x11FF, 0x10de, "GRID P6-2A"), +ENTRY(0x1BB4, 0x1200, 0x10de, "GRID P6-4A"), +ENTRY(0x1BB4, 0x1201, 0x10de, "GRID P6-8A"), +ENTRY(0x1BB4, 0x1202, 0x10de, "GRID P6-16A"), +ENTRY(0x1BB4, 0x1289, 0x10de, "GRID P6-2B"), +ENTRY(0x1BB4, 0x12F0, 0x10de, "GRID P6-2B4"), +ENTRY(0x1BB4, 0x133B, 0x10de, "GRID P6-1B4"), +ENTRY(0x1BB4, 0x137F, 0x10de, "GRID P6-16C"), +ENTRY(0x1BB4, 0x1386, 0x10de, "GRID P6-4C"), +ENTRY(0x1BB4, 0x1387, 0x10de, "GRID P6-8C"), +ENTRY(0x1DB1, 0x1259, 0x10de, "GRID V100X-1B"), +ENTRY(0x1DB1, 0x125A, 0x10de, "GRID V100X-1Q"), +ENTRY(0x1DB1, 0x125B, 0x10de, "GRID V100X-2Q"), +ENTRY(0x1DB1, 0x125C, 0x10de, "GRID V100X-4Q"), +ENTRY(0x1DB1, 0x125D, 0x10de, "GRID V100X-8Q"), +ENTRY(0x1DB1, 0x125E, 0x10de, "GRID V100X-16Q"), +ENTRY(0x1DB1, 0x125F, 0x10de, "GRID V100X-1A"), +ENTRY(0x1DB1, 0x1260, 0x10de, "GRID V100X-2A"), +ENTRY(0x1DB1, 0x1261, 0x10de, "GRID V100X-4A"), +ENTRY(0x1DB1, 0x1262, 0x10de, "GRID V100X-8A"), +ENTRY(0x1DB1, 0x1263, 0x10de, "GRID V100X-16A"), +ENTRY(0x1DB1, 0x128E, 0x10de, "GRID V100X-2B"), +ENTRY(0x1DB1, 0x12F6, 0x10de, "GRID V100X-2B4"), +ENTRY(0x1DB1, 0x1341, 0x10de, "GRID V100X-1B4"), +ENTRY(0x1DB1, 0x1378, 0x10de, "GRID V100X-16C"), +ENTRY(0x1DB1, 0x138E, 0x10de, "GRID V100X-4C"), +ENTRY(0x1DB1, 0x138F, 0x10de, "GRID V100X-8C"), +ENTRY(0x1DB3, 0x1290, 0x10de, "GRID V100L-1B"), +ENTRY(0x1DB3, 0x1291, 0x10de, "GRID V100L-2B"), +ENTRY(0x1DB3, 0x1292, 0x10de, "GRID V100L-1Q"), +ENTRY(0x1DB3, 0x1293, 0x10de, "GRID V100L-2Q"), +ENTRY(0x1DB3, 0x1294, 0x10de, "GRID V100L-4Q"), +ENTRY(0x1DB3, 0x1295, 0x10de, "GRID V100L-8Q"), +ENTRY(0x1DB3, 0x1296, 0x10de, "GRID V100L-16Q"), +ENTRY(0x1DB3, 0x1297, 0x10de, "GRID V100L-1A"), +ENTRY(0x1DB3, 0x1298, 0x10de, "GRID V100L-2A"), +ENTRY(0x1DB3, 0x1299, 0x10de, "GRID V100L-4A"), +ENTRY(0x1DB3, 0x129A, 0x10de, "GRID V100L-8A"), +ENTRY(0x1DB3, 0x129B, 0x10de, "GRID V100L-16A"), +ENTRY(0x1DB3, 0x12F9, 0x10de, "GRID V100L-2B4"), +ENTRY(0x1DB3, 0x1344, 0x10de, "GRID V100L-1B4"), +ENTRY(0x1DB3, 0x137A, 0x10de, "GRID V100L-16C"), +ENTRY(0x1DB3, 0x1398, 0x10de, "GRID V100L-4C"), +ENTRY(0x1DB3, 0x1399, 0x10de, "GRID V100L-8C"), +ENTRY(0x1DB4, 0x124E, 0x10de, "GRID V100-1B"), +ENTRY(0x1DB4, 0x124F, 0x10de, "GRID V100-1Q"), +ENTRY(0x1DB4, 0x1250, 0x10de, "GRID V100-2Q"), +ENTRY(0x1DB4, 0x1251, 0x10de, "GRID V100-4Q"), +ENTRY(0x1DB4, 0x1252, 0x10de, "GRID V100-8Q"), +ENTRY(0x1DB4, 0x1253, 0x10de, "GRID V100-16Q"), +ENTRY(0x1DB4, 0x1254, 0x10de, "GRID V100-1A"), +ENTRY(0x1DB4, 0x1255, 0x10de, "GRID V100-2A"), +ENTRY(0x1DB4, 0x1256, 0x10de, "GRID V100-4A"), +ENTRY(0x1DB4, 0x1257, 0x10de, "GRID V100-8A"), +ENTRY(0x1DB4, 0x1258, 0x10de, "GRID V100-16A"), +ENTRY(0x1DB4, 0x128F, 0x10de, "GRID V100-2B"), +ENTRY(0x1DB4, 0x12F5, 0x10de, "GRID V100-2B4"), +ENTRY(0x1DB4, 0x1340, 0x10de, "GRID V100-1B4"), +ENTRY(0x1DB4, 0x1379, 0x10de, "GRID V100-16C"), +ENTRY(0x1DB4, 0x1393, 0x10de, "GRID V100-4C"), +ENTRY(0x1DB4, 0x1394, 0x10de, "GRID V100-8C"), +ENTRY(0x1DB5, 0x12CB, 0x10de, "GRID V100DX-1B"), +ENTRY(0x1DB5, 0x12CC, 0x10de, "GRID V100DX-2B"), +ENTRY(0x1DB5, 0x12CD, 0x10de, "GRID V100DX-1Q"), +ENTRY(0x1DB5, 0x12CE, 0x10de, "GRID V100DX-2Q"), +ENTRY(0x1DB5, 0x12CF, 0x10de, "GRID V100DX-4Q"), +ENTRY(0x1DB5, 0x12D0, 0x10de, "GRID V100DX-8Q"), +ENTRY(0x1DB5, 0x12D1, 0x10de, "GRID V100DX-16Q"), +ENTRY(0x1DB5, 0x12D2, 0x10de, "GRID V100DX-32Q"), +ENTRY(0x1DB5, 0x12D3, 0x10de, "GRID V100DX-1A"), +ENTRY(0x1DB5, 0x12D4, 0x10de, "GRID V100DX-2A"), +ENTRY(0x1DB5, 0x12D5, 0x10de, "GRID V100DX-4A"), +ENTRY(0x1DB5, 0x12D6, 0x10de, "GRID V100DX-8A"), +ENTRY(0x1DB5, 0x12D7, 0x10de, "GRID V100DX-16A"), +ENTRY(0x1DB5, 0x12D8, 0x10de, "GRID V100DX-32A"), +ENTRY(0x1DB5, 0x12F8, 0x10de, "GRID V100DX-2B4"), +ENTRY(0x1DB5, 0x1343, 0x10de, "GRID V100DX-1B4"), +ENTRY(0x1DB5, 0x1376, 0x10de, "GRID V100DX-32C"), +ENTRY(0x1DB5, 0x1390, 0x10de, "GRID V100DX-4C"), +ENTRY(0x1DB5, 0x1391, 0x10de, "GRID V100DX-8C"), +ENTRY(0x1DB5, 0x1392, 0x10de, "GRID V100DX-16C"), +ENTRY(0x1DB6, 0x12BD, 0x10de, "GRID V100D-1B"), +ENTRY(0x1DB6, 0x12BE, 0x10de, "GRID V100D-2B"), +ENTRY(0x1DB6, 0x12BF, 0x10de, "GRID V100D-1Q"), +ENTRY(0x1DB6, 0x12C0, 0x10de, "GRID V100D-2Q"), +ENTRY(0x1DB6, 0x12C1, 0x10de, "GRID V100D-4Q"), +ENTRY(0x1DB6, 0x12C2, 0x10de, "GRID V100D-8Q"), +ENTRY(0x1DB6, 0x12C3, 0x10de, "GRID V100D-16Q"), +ENTRY(0x1DB6, 0x12C4, 0x10de, "GRID V100D-32Q"), +ENTRY(0x1DB6, 0x12C5, 0x10de, "GRID V100D-1A"), +ENTRY(0x1DB6, 0x12C6, 0x10de, "GRID V100D-2A"), +ENTRY(0x1DB6, 0x12C7, 0x10de, "GRID V100D-4A"), +ENTRY(0x1DB6, 0x12C8, 0x10de, "GRID V100D-8A"), +ENTRY(0x1DB6, 0x12C9, 0x10de, "GRID V100D-16A"), +ENTRY(0x1DB6, 0x12CA, 0x10de, "GRID V100D-32A"), +ENTRY(0x1DB6, 0x12F7, 0x10de, "GRID V100D-2B4"), +ENTRY(0x1DB6, 0x1342, 0x10de, "GRID V100D-1B4"), +ENTRY(0x1DB6, 0x1377, 0x10de, "GRID V100D-32C"), +ENTRY(0x1DB6, 0x1395, 0x10de, "GRID V100D-4C"), +ENTRY(0x1DB6, 0x1396, 0x10de, "GRID V100D-8C"), +ENTRY(0x1DB6, 0x1397, 0x10de, "GRID V100D-16C"), +ENTRY(0x1DB6, 0x13CD, 0x10de, "GRID GTX V100D-8"), +ENTRY(0x1DB6, 0x13CE, 0x10de, "GRID GTX V100D-16"), +ENTRY(0x1DB6, 0x13CF, 0x10de, "GRID GTX V100D-32"), +ENTRY(0x1DF6, 0x13E1, 0x10de, "GRID V100S-1B"), +ENTRY(0x1DF6, 0x13E3, 0x10de, "GRID V100S-2B"), +ENTRY(0x1DF6, 0x13E5, 0x10de, "GRID V100S-1Q"), +ENTRY(0x1DF6, 0x13E6, 0x10de, "GRID V100S-2Q"), +ENTRY(0x1DF6, 0x13E7, 0x10de, "GRID V100S-4Q"), +ENTRY(0x1DF6, 0x13E8, 0x10de, "GRID V100S-8Q"), +ENTRY(0x1DF6, 0x13E9, 0x10de, "GRID V100S-16Q"), +ENTRY(0x1DF6, 0x13EA, 0x10de, "GRID V100S-32Q"), +ENTRY(0x1DF6, 0x13EB, 0x10de, "GRID V100S-1A"), +ENTRY(0x1DF6, 0x13EC, 0x10de, "GRID V100S-2A"), +ENTRY(0x1DF6, 0x13ED, 0x10de, "GRID V100S-4A"), +ENTRY(0x1DF6, 0x13EE, 0x10de, "GRID V100S-8A"), +ENTRY(0x1DF6, 0x13EF, 0x10de, "GRID V100S-16A"), +ENTRY(0x1DF6, 0x13F0, 0x10de, "GRID V100S-32A"), +ENTRY(0x1DF6, 0x13F1, 0x10de, "GRID V100S-4C"), +ENTRY(0x1DF6, 0x13F2, 0x10de, "GRID V100S-8C"), +ENTRY(0x1DF6, 0x13F3, 0x10de, "GRID V100S-16C"), +ENTRY(0x1DF6, 0x13F4, 0x10de, "GRID V100S-32C"), +ENTRY(0x1E30, 0x1325, 0x10de, "GRID RTX6000-1Q"), +ENTRY(0x1E30, 0x1326, 0x10de, "GRID RTX6000-2Q"), +ENTRY(0x1E30, 0x1327, 0x10de, "GRID RTX6000-3Q"), +ENTRY(0x1E30, 0x1328, 0x10de, "GRID RTX6000-4Q"), +ENTRY(0x1E30, 0x1329, 0x10de, "GRID RTX6000-6Q"), +ENTRY(0x1E30, 0x132A, 0x10de, "GRID RTX6000-8Q"), +ENTRY(0x1E30, 0x132B, 0x10de, "GRID RTX6000-12Q"), +ENTRY(0x1E30, 0x132C, 0x10de, "GRID RTX6000-24Q"), +ENTRY(0x1E30, 0x132D, 0x10de, "GRID RTX8000-1Q"), +ENTRY(0x1E30, 0x132E, 0x10de, "GRID RTX8000-2Q"), +ENTRY(0x1E30, 0x132F, 0x10de, "GRID RTX8000-3Q"), +ENTRY(0x1E30, 0x1330, 0x10de, "GRID RTX8000-4Q"), +ENTRY(0x1E30, 0x1331, 0x10de, "GRID RTX8000-6Q"), +ENTRY(0x1E30, 0x1332, 0x10de, "GRID RTX8000-8Q"), +ENTRY(0x1E30, 0x1333, 0x10de, "GRID RTX8000-12Q"), +ENTRY(0x1E30, 0x1334, 0x10de, "GRID RTX8000-16Q"), +ENTRY(0x1E30, 0x1335, 0x10de, "GRID RTX8000-24Q"), +ENTRY(0x1E30, 0x1336, 0x10de, "GRID RTX8000-48Q"), +ENTRY(0x1E30, 0x13B9, 0x10de, "GRID RTX6000-6"), +ENTRY(0x1E30, 0x13BA, 0x10de, "GRID RTX6000-12"), +ENTRY(0x1E30, 0x13BB, 0x10de, "GRID RTX6000-24"), +ENTRY(0x1E30, 0x13BC, 0x10de, "GRID RTX8000-12"), +ENTRY(0x1E30, 0x13BD, 0x10de, "GRID RTX8000-24"), +ENTRY(0x1E30, 0x13BE, 0x10de, "GRID RTX8000-48"), +ENTRY(0x1E30, 0x13BF, 0x10de, "GRID RTX6000-4C"), +ENTRY(0x1E30, 0x13C0, 0x10de, "GRID RTX6000-6C"), +ENTRY(0x1E30, 0x13C1, 0x10de, "GRID RTX6000-8C"), +ENTRY(0x1E30, 0x13C2, 0x10de, "GRID RTX6000-12C"), +ENTRY(0x1E30, 0x13C3, 0x10de, "GRID RTX6000-24C"), +ENTRY(0x1E30, 0x13C4, 0x10de, "GRID RTX8000-4C"), +ENTRY(0x1E30, 0x13C5, 0x10de, "GRID RTX8000-6C"), +ENTRY(0x1E30, 0x13C6, 0x10de, "GRID RTX8000-8C"), +ENTRY(0x1E30, 0x13C7, 0x10de, "GRID RTX8000-12C"), +ENTRY(0x1E30, 0x13C8, 0x10de, "GRID RTX8000-16C"), +ENTRY(0x1E30, 0x13C9, 0x10de, "GRID RTX8000-24C"), +ENTRY(0x1E30, 0x13CA, 0x10de, "GRID RTX8000-48C"), +ENTRY(0x1E30, 0x13CB, 0x10de, "GRID RTX6000-8"), +ENTRY(0x1E30, 0x13CC, 0x10de, "GRID RTX8000-16"), +ENTRY(0x1E30, 0x1437, 0x10de, "GRID RTX6000-1B"), +ENTRY(0x1E30, 0x1438, 0x10de, "GRID RTX6000-2B"), +ENTRY(0x1E30, 0x1439, 0x10de, "GRID RTX6000-1A"), +ENTRY(0x1E30, 0x143A, 0x10de, "GRID RTX6000-2A"), +ENTRY(0x1E30, 0x143B, 0x10de, "GRID RTX6000-3A"), +ENTRY(0x1E30, 0x143C, 0x10de, "GRID RTX6000-4A"), +ENTRY(0x1E30, 0x143D, 0x10de, "GRID RTX6000-6A"), +ENTRY(0x1E30, 0x143E, 0x10de, "GRID RTX6000-8A"), +ENTRY(0x1E30, 0x143F, 0x10de, "GRID RTX6000-12A"), +ENTRY(0x1E30, 0x1440, 0x10de, "GRID RTX6000-24A"), +ENTRY(0x1E30, 0x1441, 0x10de, "GRID RTX8000-1B"), +ENTRY(0x1E30, 0x1442, 0x10de, "GRID RTX8000-2B"), +ENTRY(0x1E30, 0x1443, 0x10de, "GRID RTX8000-1A"), +ENTRY(0x1E30, 0x1444, 0x10de, "GRID RTX8000-2A"), +ENTRY(0x1E30, 0x1445, 0x10de, "GRID RTX8000-3A"), +ENTRY(0x1E30, 0x1446, 0x10de, "GRID RTX8000-4A"), +ENTRY(0x1E30, 0x1447, 0x10de, "GRID RTX8000-6A"), +ENTRY(0x1E30, 0x1448, 0x10de, "GRID RTX8000-8A"), +ENTRY(0x1E30, 0x1449, 0x10de, "GRID RTX8000-12A"), +ENTRY(0x1E30, 0x144A, 0x10de, "GRID RTX8000-16A"), +ENTRY(0x1E30, 0x144B, 0x10de, "GRID RTX8000-24A"), +ENTRY(0x1E30, 0x144C, 0x10de, "GRID RTX8000-48A"), +ENTRY(0x1E37, 0x1347, 0x10de, "GeForce RTX T10x-8"), +ENTRY(0x1E37, 0x1348, 0x10de, "GeForce RTX T10x-4"), +ENTRY(0x1E37, 0x1349, 0x10de, "GeForce RTX T10x-2"), +ENTRY(0x1E37, 0x136A, 0x10de, "GRID RTX T10-4"), +ENTRY(0x1E37, 0x136B, 0x10de, "GRID RTX T10-8"), +ENTRY(0x1E37, 0x136C, 0x10de, "GRID RTX T10-16"), +ENTRY(0x1E37, 0x13A4, 0x10de, "GeForce RTX T10-4"), +ENTRY(0x1E37, 0x13A5, 0x10de, "GeForce RTX T10-8"), +ENTRY(0x1E37, 0x13A6, 0x10de, "GeForce RTX T10-16"), +ENTRY(0x1E37, 0x13A7, 0x10de, "GRID RTX T10x-2"), +ENTRY(0x1E37, 0x13A8, 0x10de, "GRID RTX T10x-4"), +ENTRY(0x1E37, 0x13A9, 0x10de, "GRID RTX T10x-8"), +ENTRY(0x1E37, 0x180D, 0x10de, "NVIDIA GeForce GTX 1060"), +ENTRY(0x1E37, 0x1820, 0x10de, "NVIDIA GeForce RTX 2080"), +ENTRY(0x1E78, 0x13F7, 0x10de, "GRID RTX6000P-1B"), +ENTRY(0x1E78, 0x13F8, 0x10de, "GRID RTX6000P-2B"), +ENTRY(0x1E78, 0x13F9, 0x10de, "GRID RTX6000P-1Q"), +ENTRY(0x1E78, 0x13FA, 0x10de, "GRID RTX6000P-2Q"), +ENTRY(0x1E78, 0x13FB, 0x10de, "GRID RTX6000P-3Q"), +ENTRY(0x1E78, 0x13FC, 0x10de, "GRID RTX6000P-4Q"), +ENTRY(0x1E78, 0x13FD, 0x10de, "GRID RTX6000P-6Q"), +ENTRY(0x1E78, 0x13FE, 0x10de, "GRID RTX6000P-8Q"), +ENTRY(0x1E78, 0x13FF, 0x10de, "GRID RTX6000P-12Q"), +ENTRY(0x1E78, 0x1400, 0x10de, "GRID RTX6000P-24Q"), +ENTRY(0x1E78, 0x1401, 0x10de, "GRID RTX6000P-1A"), +ENTRY(0x1E78, 0x1402, 0x10de, "GRID RTX6000P-2A"), +ENTRY(0x1E78, 0x1403, 0x10de, "GRID RTX6000P-3A"), +ENTRY(0x1E78, 0x1404, 0x10de, "GRID RTX6000P-4A"), +ENTRY(0x1E78, 0x1405, 0x10de, "GRID RTX6000P-6A"), +ENTRY(0x1E78, 0x1406, 0x10de, "GRID RTX6000P-8A"), +ENTRY(0x1E78, 0x1407, 0x10de, "GRID RTX6000P-12A"), +ENTRY(0x1E78, 0x1408, 0x10de, "GRID RTX6000P-24A"), +ENTRY(0x1E78, 0x1409, 0x10de, "GRID RTX6000P-6"), +ENTRY(0x1E78, 0x140A, 0x10de, "GRID RTX6000P-8"), +ENTRY(0x1E78, 0x140B, 0x10de, "GRID RTX6000P-12"), +ENTRY(0x1E78, 0x140C, 0x10de, "GRID RTX6000P-24"), +ENTRY(0x1E78, 0x140D, 0x10de, "GRID RTX6000P-4C"), +ENTRY(0x1E78, 0x140E, 0x10de, "GRID RTX6000P-6C"), +ENTRY(0x1E78, 0x140F, 0x10de, "GRID RTX6000P-8C"), +ENTRY(0x1E78, 0x1410, 0x10de, "GRID RTX6000P-12C"), +ENTRY(0x1E78, 0x1411, 0x10de, "GRID RTX6000P-24C"), +ENTRY(0x1E78, 0x1412, 0x10de, "GRID RTX8000P-1B"), +ENTRY(0x1E78, 0x1413, 0x10de, "GRID RTX8000P-2B"), +ENTRY(0x1E78, 0x1414, 0x10de, "GRID RTX8000P-1Q"), +ENTRY(0x1E78, 0x1415, 0x10de, "GRID RTX8000P-2Q"), +ENTRY(0x1E78, 0x1416, 0x10de, "GRID RTX8000P-3Q"), +ENTRY(0x1E78, 0x1417, 0x10de, "GRID RTX8000P-4Q"), +ENTRY(0x1E78, 0x1418, 0x10de, "GRID RTX8000P-6Q"), +ENTRY(0x1E78, 0x1419, 0x10de, "GRID RTX8000P-8Q"), +ENTRY(0x1E78, 0x141A, 0x10de, "GRID RTX8000P-12Q"), +ENTRY(0x1E78, 0x141B, 0x10de, "GRID RTX8000P-16Q"), +ENTRY(0x1E78, 0x141C, 0x10de, "GRID RTX8000P-24Q"), +ENTRY(0x1E78, 0x141D, 0x10de, "GRID RTX8000P-48Q"), +ENTRY(0x1E78, 0x141E, 0x10de, "GRID RTX8000P-1A"), +ENTRY(0x1E78, 0x141F, 0x10de, "GRID RTX8000P-2A"), +ENTRY(0x1E78, 0x1420, 0x10de, "GRID RTX8000P-3A"), +ENTRY(0x1E78, 0x1421, 0x10de, "GRID RTX8000P-4A"), +ENTRY(0x1E78, 0x1422, 0x10de, "GRID RTX8000P-6A"), +ENTRY(0x1E78, 0x1423, 0x10de, "GRID RTX8000P-8A"), +ENTRY(0x1E78, 0x1424, 0x10de, "GRID RTX8000P-12A"), +ENTRY(0x1E78, 0x1425, 0x10de, "GRID RTX8000P-24A"), +ENTRY(0x1E78, 0x1426, 0x10de, "GRID RTX8000P-48A"), +ENTRY(0x1E78, 0x1427, 0x10de, "GRID RTX8000P-12"), +ENTRY(0x1E78, 0x1428, 0x10de, "GRID RTX8000P-16"), +ENTRY(0x1E78, 0x1429, 0x10de, "GRID RTX8000P-24"), +ENTRY(0x1E78, 0x142A, 0x10de, "GRID RTX8000P-48"), +ENTRY(0x1E78, 0x142B, 0x10de, "GRID RTX8000P-4C"), +ENTRY(0x1E78, 0x142C, 0x10de, "GRID RTX8000P-6C"), +ENTRY(0x1E78, 0x142D, 0x10de, "GRID RTX8000P-8C"), +ENTRY(0x1E78, 0x142E, 0x10de, "GRID RTX8000P-12C"), +ENTRY(0x1E78, 0x142F, 0x10de, "GRID RTX8000P-16C"), +ENTRY(0x1E78, 0x1430, 0x10de, "GRID RTX8000P-24C"), +ENTRY(0x1E78, 0x1431, 0x10de, "GRID RTX8000P-48C"), +ENTRY(0x1E78, 0x1436, 0x10de, "GRID RTX8000P-16A"), +ENTRY(0x1EB8, 0x1309, 0x10de, "GRID T4-1B"), +ENTRY(0x1EB8, 0x130A, 0x10de, "GRID T4-2B"), +ENTRY(0x1EB8, 0x130B, 0x10de, "GRID T4-2B4"), +ENTRY(0x1EB8, 0x130C, 0x10de, "GRID T4-1Q"), +ENTRY(0x1EB8, 0x130D, 0x10de, "GRID T4-2Q"), +ENTRY(0x1EB8, 0x130E, 0x10de, "GRID T4-4Q"), +ENTRY(0x1EB8, 0x130F, 0x10de, "GRID T4-8Q"), +ENTRY(0x1EB8, 0x1310, 0x10de, "GRID T4-16Q"), +ENTRY(0x1EB8, 0x1311, 0x10de, "GRID T4-1A"), +ENTRY(0x1EB8, 0x1312, 0x10de, "GRID T4-2A"), +ENTRY(0x1EB8, 0x1313, 0x10de, "GRID T4-4A"), +ENTRY(0x1EB8, 0x1314, 0x10de, "GRID T4-8A"), +ENTRY(0x1EB8, 0x1315, 0x10de, "GRID T4-16A"), +ENTRY(0x1EB8, 0x1345, 0x10de, "GRID T4-1B4"), +ENTRY(0x1EB8, 0x1367, 0x10de, "GRID RTX T4-4"), +ENTRY(0x1EB8, 0x1368, 0x10de, "GRID RTX T4-8"), +ENTRY(0x1EB8, 0x1369, 0x10de, "GRID RTX T4-16"), +ENTRY(0x1EB8, 0x1375, 0x10de, "GRID T4-16C"), +ENTRY(0x1EB8, 0x139A, 0x10de, "GRID T4-4C"), +ENTRY(0x1EB8, 0x139B, 0x10de, "GRID T4-8C"), +ENTRY(0x20B0, 0x146F, 0x10de, "GRID A100X-1-5C"), +ENTRY(0x20B0, 0x1470, 0x10de, "GRID A100X-2-10C"), +ENTRY(0x20B0, 0x1471, 0x10de, "GRID A100X-3-20C"), +ENTRY(0x20B0, 0x1472, 0x10de, "GRID A100X-4-20C"), +ENTRY(0x20B0, 0x1473, 0x10de, "GRID A100X-7-40C"), +ENTRY(0x20B0, 0x1474, 0x10de, "GRID A100X-4C"), +ENTRY(0x20B0, 0x1475, 0x10de, "GRID A100X-5C"), +ENTRY(0x20B0, 0x1476, 0x10de, "GRID A100X-8C"), +ENTRY(0x20B0, 0x1477, 0x10de, "GRID A100X-10C"), +ENTRY(0x20B0, 0x1478, 0x10de, "GRID A100X-20C"), +ENTRY(0x20B0, 0x1479, 0x10de, "GRID A100X-40C"), +ENTRY(0x20B0, 0x160C, 0x10de, "GRID A100X-1-5CME"), +ENTRY(0x20B0, 0x1840, 0x10de, "GRID A100X-1-10C"), +ENTRY(0x20B2, 0x1523, 0x10de, "GRID A100DX-1-10C"), +ENTRY(0x20B2, 0x1524, 0x10de, "GRID A100DX-2-20C"), +ENTRY(0x20B2, 0x1525, 0x10de, "GRID A100DX-3-40C"), +ENTRY(0x20B2, 0x1526, 0x10de, "GRID A100DX-4-40C"), +ENTRY(0x20B2, 0x1527, 0x10de, "GRID A100DX-7-80C"), +ENTRY(0x20B2, 0x1528, 0x10de, "GRID A100DX-4C"), +ENTRY(0x20B2, 0x1529, 0x10de, "GRID A100DX-8C"), +ENTRY(0x20B2, 0x152A, 0x10de, "GRID A100DX-10C"), +ENTRY(0x20B2, 0x152B, 0x10de, "GRID A100DX-16C"), +ENTRY(0x20B2, 0x152C, 0x10de, "GRID A100DX-20C"), +ENTRY(0x20B2, 0x152D, 0x10de, "GRID A100DX-40C"), +ENTRY(0x20B2, 0x152E, 0x10de, "GRID A100DX-80C"), +ENTRY(0x20B2, 0x160D, 0x10de, "GRID A100DX-1-10CME"), +ENTRY(0x20B2, 0x1841, 0x10de, "GRID A100DX-1-20C"), +ENTRY(0x20B5, 0x1591, 0x10de, "GRID A100D-1-10C"), +ENTRY(0x20B5, 0x1592, 0x10de, "GRID A100D-2-20C"), +ENTRY(0x20B5, 0x1593, 0x10de, "GRID A100D-3-40C"), +ENTRY(0x20B5, 0x1594, 0x10de, "GRID A100D-4-40C"), +ENTRY(0x20B5, 0x1595, 0x10de, "GRID A100D-7-80C"), +ENTRY(0x20B5, 0x1596, 0x10de, "GRID A100D-4C"), +ENTRY(0x20B5, 0x1597, 0x10de, "GRID A100D-8C"), +ENTRY(0x20B5, 0x1598, 0x10de, "GRID A100D-10C"), +ENTRY(0x20B5, 0x1599, 0x10de, "GRID A100D-16C"), +ENTRY(0x20B5, 0x159A, 0x10de, "GRID A100D-20C"), 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"GRID A100-4C"), +ENTRY(0x20F1, 0x1499, 0x10de, "GRID A100-5C"), +ENTRY(0x20F1, 0x149A, 0x10de, "GRID A100-8C"), +ENTRY(0x20F1, 0x149B, 0x10de, "GRID A100-10C"), +ENTRY(0x20F1, 0x149C, 0x10de, "GRID A100-20C"), +ENTRY(0x20F1, 0x149D, 0x10de, "GRID A100-40C"), +ENTRY(0x20F1, 0x160E, 0x10de, "GRID A100-1-5CME"), +ENTRY(0x20F1, 0x183D, 0x10de, "GRID A100-1-10C"), +ENTRY(0x20F3, 0x17B2, 0x10de, "GRID A800DX-1-10CME"), +ENTRY(0x20F3, 0x17B3, 0x10de, "GRID A800DX-1-10C"), +ENTRY(0x20F3, 0x17B4, 0x10de, "GRID A800DX-2-20C"), +ENTRY(0x20F3, 0x17B5, 0x10de, "GRID A800DX-3-40C"), +ENTRY(0x20F3, 0x17B6, 0x10de, "GRID A800DX-4-40C"), +ENTRY(0x20F3, 0x17B7, 0x10de, "GRID A800DX-7-80C"), +ENTRY(0x20F3, 0x17B8, 0x10de, "GRID A800DX-4C"), +ENTRY(0x20F3, 0x17B9, 0x10de, "GRID A800DX-8C"), +ENTRY(0x20F3, 0x17BA, 0x10de, "GRID A800DX-10C"), +ENTRY(0x20F3, 0x17BB, 0x10de, "GRID A800DX-16C"), +ENTRY(0x20F3, 0x17BC, 0x10de, "GRID A800DX-20C"), +ENTRY(0x20F3, 0x17BD, 0x10de, "GRID A800DX-40C"), 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0x10de, "GRID A800-3-20C"), +ENTRY(0x20F6, 0x17D0, 0x10de, "GRID A800-4-20C"), +ENTRY(0x20F6, 0x17D1, 0x10de, "GRID A800-7-40C"), +ENTRY(0x20F6, 0x17D2, 0x10de, "GRID A800-4C"), +ENTRY(0x20F6, 0x17D3, 0x10de, "GRID A800-5C"), +ENTRY(0x20F6, 0x17D4, 0x10de, "GRID A800-8C"), +ENTRY(0x20F6, 0x17D5, 0x10de, "GRID A800-10C"), +ENTRY(0x20F6, 0x17D6, 0x10de, "GRID A800-20C"), +ENTRY(0x20F6, 0x17D7, 0x10de, "GRID A800-40C"), +ENTRY(0x20F6, 0x1843, 0x10de, "GRID A800-1-10C"), +ENTRY(0x2230, 0x14FA, 0x10de, "NVIDIA RTXA6000-1B"), +ENTRY(0x2230, 0x14FB, 0x10de, "NVIDIA RTXA6000-2B"), +ENTRY(0x2230, 0x14FC, 0x10de, "NVIDIA RTXA6000-1Q"), +ENTRY(0x2230, 0x14FD, 0x10de, "NVIDIA RTXA6000-2Q"), +ENTRY(0x2230, 0x14FE, 0x10de, "NVIDIA RTXA6000-3Q"), +ENTRY(0x2230, 0x14FF, 0x10de, "NVIDIA RTXA6000-4Q"), +ENTRY(0x2230, 0x1500, 0x10de, "NVIDIA RTXA6000-6Q"), +ENTRY(0x2230, 0x1501, 0x10de, "NVIDIA RTXA6000-8Q"), +ENTRY(0x2230, 0x1502, 0x10de, "NVIDIA RTXA6000-12Q"), +ENTRY(0x2230, 0x1503, 0x10de, "NVIDIA RTXA6000-16Q"), +ENTRY(0x2230, 0x1504, 0x10de, "NVIDIA RTXA6000-24Q"), +ENTRY(0x2230, 0x1505, 0x10de, "NVIDIA RTXA6000-48Q"), +ENTRY(0x2230, 0x1506, 0x10de, "NVIDIA RTXA6000-1A"), +ENTRY(0x2230, 0x1507, 0x10de, "NVIDIA RTXA6000-2A"), +ENTRY(0x2230, 0x1508, 0x10de, "NVIDIA RTXA6000-3A"), +ENTRY(0x2230, 0x1509, 0x10de, "NVIDIA RTXA6000-4A"), +ENTRY(0x2230, 0x150A, 0x10de, "NVIDIA RTXA6000-6A"), +ENTRY(0x2230, 0x150B, 0x10de, "NVIDIA RTXA6000-8A"), +ENTRY(0x2230, 0x150C, 0x10de, "NVIDIA RTXA6000-12A"), +ENTRY(0x2230, 0x150D, 0x10de, "NVIDIA RTXA6000-16A"), +ENTRY(0x2230, 0x150E, 0x10de, "NVIDIA RTXA6000-24A"), +ENTRY(0x2230, 0x150F, 0x10de, "NVIDIA RTXA6000-48A"), +ENTRY(0x2230, 0x1510, 0x10de, "NVIDIA RTXA6000-12"), +ENTRY(0x2230, 0x1511, 0x10de, "NVIDIA RTXA6000-16"), +ENTRY(0x2230, 0x1512, 0x10de, "NVIDIA RTXA6000-24"), +ENTRY(0x2230, 0x1513, 0x10de, "NVIDIA RTXA6000-48"), +ENTRY(0x2230, 0x1514, 0x10de, "NVIDIA RTXA6000-4C"), +ENTRY(0x2230, 0x1515, 0x10de, "NVIDIA RTXA6000-6C"), +ENTRY(0x2230, 0x1516, 0x10de, "NVIDIA RTXA6000-8C"), +ENTRY(0x2230, 0x1517, 0x10de, "NVIDIA RTXA6000-12C"), +ENTRY(0x2230, 0x1518, 0x10de, "NVIDIA RTXA6000-16C"), +ENTRY(0x2230, 0x1519, 0x10de, "NVIDIA RTXA6000-24C"), +ENTRY(0x2230, 0x151A, 0x10de, "NVIDIA RTXA6000-48C"), +ENTRY(0x2231, 0x1562, 0x10de, "NVIDIA RTXA5000-1B"), +ENTRY(0x2231, 0x1563, 0x10de, "NVIDIA RTXA5000-2B"), +ENTRY(0x2231, 0x1564, 0x10de, "NVIDIA RTXA5000-1Q"), +ENTRY(0x2231, 0x1565, 0x10de, "NVIDIA RTXA5000-2Q"), +ENTRY(0x2231, 0x1566, 0x10de, "NVIDIA RTXA5000-3Q"), +ENTRY(0x2231, 0x1567, 0x10de, "NVIDIA RTXA5000-4Q"), +ENTRY(0x2231, 0x1568, 0x10de, "NVIDIA RTXA5000-6Q"), +ENTRY(0x2231, 0x1569, 0x10de, "NVIDIA RTXA5000-8Q"), +ENTRY(0x2231, 0x156A, 0x10de, "NVIDIA RTXA5000-12Q"), +ENTRY(0x2231, 0x156B, 0x10de, "NVIDIA RTXA5000-24Q"), +ENTRY(0x2231, 0x156C, 0x10de, "NVIDIA RTXA5000-1A"), +ENTRY(0x2231, 0x156D, 0x10de, "NVIDIA RTXA5000-2A"), +ENTRY(0x2231, 0x156E, 0x10de, "NVIDIA RTXA5000-3A"), +ENTRY(0x2231, 0x156F, 0x10de, "NVIDIA RTXA5000-4A"), +ENTRY(0x2231, 0x1570, 0x10de, "NVIDIA RTXA5000-6A"), +ENTRY(0x2231, 0x1571, 0x10de, "NVIDIA RTXA5000-8A"), +ENTRY(0x2231, 0x1572, 0x10de, "NVIDIA RTXA5000-12A"), +ENTRY(0x2231, 0x1573, 0x10de, "NVIDIA RTXA5000-24A"), +ENTRY(0x2231, 0x1574, 0x10de, "NVIDIA RTXA5000-6"), +ENTRY(0x2231, 0x1575, 0x10de, "NVIDIA RTXA5000-8"), +ENTRY(0x2231, 0x1576, 0x10de, "NVIDIA RTXA5000-12"), +ENTRY(0x2231, 0x1577, 0x10de, "NVIDIA RTXA5000-24"), +ENTRY(0x2231, 0x1578, 0x10de, "NVIDIA RTXA5000-4C"), +ENTRY(0x2231, 0x1579, 0x10de, "NVIDIA RTXA5000-6C"), +ENTRY(0x2231, 0x157A, 0x10de, "NVIDIA RTXA5000-8C"), +ENTRY(0x2231, 0x157B, 0x10de, "NVIDIA RTXA5000-12C"), +ENTRY(0x2231, 0x157C, 0x10de, "NVIDIA RTXA5000-24C"), +ENTRY(0x2233, 0x165C, 0x10de, "NVIDIA RTXA5500-1B"), +ENTRY(0x2233, 0x165D, 0x10de, "NVIDIA RTXA5500-2B"), +ENTRY(0x2233, 0x165E, 0x10de, "NVIDIA RTXA5500-1Q"), +ENTRY(0x2233, 0x165F, 0x10de, "NVIDIA RTXA5500-2Q"), +ENTRY(0x2233, 0x1660, 0x10de, "NVIDIA RTXA5500-3Q"), +ENTRY(0x2233, 0x1661, 0x10de, "NVIDIA RTXA5500-4Q"), +ENTRY(0x2233, 0x1662, 0x10de, "NVIDIA RTXA5500-6Q"), +ENTRY(0x2233, 0x1663, 0x10de, "NVIDIA RTXA5500-8Q"), +ENTRY(0x2233, 0x1664, 0x10de, "NVIDIA RTXA5500-12Q"), +ENTRY(0x2233, 0x1665, 0x10de, "NVIDIA RTXA5500-24Q"), +ENTRY(0x2233, 0x1666, 0x10de, "NVIDIA RTXA5500-1A"), +ENTRY(0x2233, 0x1667, 0x10de, "NVIDIA RTXA5500-2A"), +ENTRY(0x2233, 0x1668, 0x10de, "NVIDIA RTXA5500-3A"), +ENTRY(0x2233, 0x1669, 0x10de, "NVIDIA RTXA5500-4A"), +ENTRY(0x2233, 0x166A, 0x10de, "NVIDIA RTXA5500-6A"), +ENTRY(0x2233, 0x166B, 0x10de, "NVIDIA RTXA5500-8A"), +ENTRY(0x2233, 0x166C, 0x10de, "NVIDIA RTXA5500-12A"), +ENTRY(0x2233, 0x166D, 0x10de, "NVIDIA RTXA5500-24A"), +ENTRY(0x2233, 0x166E, 0x10de, "NVIDIA RTXA5500-6"), +ENTRY(0x2233, 0x166F, 0x10de, "NVIDIA RTXA5500-8"), +ENTRY(0x2233, 0x1670, 0x10de, "NVIDIA RTXA5500-12"), +ENTRY(0x2233, 0x1671, 0x10de, "NVIDIA RTXA5500-24"), +ENTRY(0x2233, 0x1672, 0x10de, "NVIDIA RTXA5500-4C"), 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0x10de, "NVIDIA A16-2Q"), +ENTRY(0x25B6, 0x1601, 0x10de, "NVIDIA A16-4Q"), +ENTRY(0x25B6, 0x1602, 0x10de, "NVIDIA A16-8Q"), +ENTRY(0x25B6, 0x1603, 0x10de, "NVIDIA A16-16Q"), +ENTRY(0x25B6, 0x1604, 0x10de, "NVIDIA A16-1A"), +ENTRY(0x25B6, 0x1605, 0x10de, "NVIDIA A16-2A"), +ENTRY(0x25B6, 0x1606, 0x10de, "NVIDIA A16-4A"), +ENTRY(0x25B6, 0x1607, 0x10de, "NVIDIA A16-8A"), +ENTRY(0x25B6, 0x1608, 0x10de, "NVIDIA A16-16A"), +ENTRY(0x25B6, 0x1609, 0x10de, "NVIDIA A16-4C"), +ENTRY(0x25B6, 0x160A, 0x10de, "NVIDIA A16-8C"), +ENTRY(0x25B6, 0x160B, 0x10de, "NVIDIA A16-16C"), +ENTRY(0x25B6, 0x1646, 0x10de, "NVIDIA A2-1B"), +ENTRY(0x25B6, 0x1647, 0x10de, "NVIDIA A2-2B"), +ENTRY(0x25B6, 0x1648, 0x10de, "NVIDIA A2-1Q"), +ENTRY(0x25B6, 0x1649, 0x10de, "NVIDIA A2-2Q"), +ENTRY(0x25B6, 0x164A, 0x10de, "NVIDIA A2-4Q"), +ENTRY(0x25B6, 0x164B, 0x10de, "NVIDIA A2-8Q"), +ENTRY(0x25B6, 0x164C, 0x10de, "NVIDIA A2-16Q"), +ENTRY(0x25B6, 0x164D, 0x10de, "NVIDIA A2-1A"), +ENTRY(0x25B6, 0x164E, 0x10de, "NVIDIA A2-2A"), +ENTRY(0x25B6, 0x164F, 0x10de, "NVIDIA A2-4A"), +ENTRY(0x25B6, 0x1650, 0x10de, "NVIDIA A2-8A"), +ENTRY(0x25B6, 0x1651, 0x10de, "NVIDIA A2-16A"), +ENTRY(0x25B6, 0x1652, 0x10de, "NVIDIA A2-4"), +ENTRY(0x25B6, 0x1653, 0x10de, "NVIDIA A2-8"), +ENTRY(0x25B6, 0x1654, 0x10de, "NVIDIA A2-16"), +ENTRY(0x25B6, 0x1655, 0x10de, "NVIDIA A2-4C"), +ENTRY(0x25B6, 0x1656, 0x10de, "NVIDIA A2-8C"), +ENTRY(0x25B6, 0x1657, 0x10de, "NVIDIA A2-16C"), +ENTRY(0x26B1, 0x1708, 0x10de, "NVIDIA RTX6000-Ada-1B"), +ENTRY(0x26B1, 0x1709, 0x10de, "NVIDIA RTX6000-Ada-2B"), +ENTRY(0x26B1, 0x170A, 0x10de, "NVIDIA RTX6000-Ada-1Q"), +ENTRY(0x26B1, 0x170B, 0x10de, "NVIDIA RTX6000-Ada-2Q"), +ENTRY(0x26B1, 0x170C, 0x10de, "NVIDIA RTX6000-Ada-3Q"), +ENTRY(0x26B1, 0x170D, 0x10de, "NVIDIA RTX6000-Ada-4Q"), +ENTRY(0x26B1, 0x170E, 0x10de, "NVIDIA RTX6000-Ada-6Q"), +ENTRY(0x26B1, 0x170F, 0x10de, "NVIDIA RTX6000-Ada-8Q"), +ENTRY(0x26B1, 0x1710, 0x10de, "NVIDIA RTX6000-Ada-12Q"), +ENTRY(0x26B1, 0x1711, 0x10de, "NVIDIA RTX6000-Ada-16Q"), +ENTRY(0x26B1, 0x1712, 0x10de, "NVIDIA RTX6000-Ada-24Q"), +ENTRY(0x26B1, 0x1713, 0x10de, "NVIDIA RTX6000-Ada-48Q"), +ENTRY(0x26B1, 0x1714, 0x10de, "NVIDIA RTX6000-Ada-1A"), +ENTRY(0x26B1, 0x1715, 0x10de, "NVIDIA RTX6000-Ada-2A"), +ENTRY(0x26B1, 0x1716, 0x10de, "NVIDIA RTX6000-Ada-3A"), +ENTRY(0x26B1, 0x1717, 0x10de, "NVIDIA RTX6000-Ada-4A"), +ENTRY(0x26B1, 0x1718, 0x10de, "NVIDIA RTX6000-Ada-6A"), +ENTRY(0x26B1, 0x1719, 0x10de, "NVIDIA RTX6000-Ada-8A"), +ENTRY(0x26B1, 0x171A, 0x10de, "NVIDIA RTX6000-Ada-12A"), +ENTRY(0x26B1, 0x171B, 0x10de, "NVIDIA RTX6000-Ada-16A"), +ENTRY(0x26B1, 0x171C, 0x10de, "NVIDIA RTX6000-Ada-24A"), +ENTRY(0x26B1, 0x171D, 0x10de, "NVIDIA RTX6000-Ada-48A"), +ENTRY(0x26B1, 0x171E, 0x10de, "NVIDIA RTX6000-Ada-1"), +ENTRY(0x26B1, 0x171F, 0x10de, "NVIDIA RTX6000-Ada-2"), +ENTRY(0x26B1, 0x1720, 0x10de, "NVIDIA RTX6000-Ada-3"), +ENTRY(0x26B1, 0x1721, 0x10de, "NVIDIA RTX6000-Ada-4"), +ENTRY(0x26B1, 0x1722, 0x10de, "NVIDIA RTX6000-Ada-6"), +ENTRY(0x26B1, 0x1723, 0x10de, "NVIDIA RTX6000-Ada-8"), +ENTRY(0x26B1, 0x1724, 0x10de, "NVIDIA RTX6000-Ada-12"), +ENTRY(0x26B1, 0x1725, 0x10de, "NVIDIA RTX6000-Ada-16"), +ENTRY(0x26B1, 0x1726, 0x10de, "NVIDIA RTX6000-Ada-24"), +ENTRY(0x26B1, 0x1727, 0x10de, "NVIDIA RTX6000-Ada-48"), +ENTRY(0x26B1, 0x1728, 0x10de, "NVIDIA RTX6000-Ada-4C"), +ENTRY(0x26B1, 0x1729, 0x10de, "NVIDIA RTX6000-Ada-6C"), +ENTRY(0x26B1, 0x172A, 0x10de, "NVIDIA RTX6000-Ada-8C"), +ENTRY(0x26B1, 0x172B, 0x10de, "NVIDIA RTX6000-Ada-12C"), +ENTRY(0x26B1, 0x172C, 0x10de, "NVIDIA RTX6000-Ada-16C"), +ENTRY(0x26B1, 0x172D, 0x10de, "NVIDIA RTX6000-Ada-24C"), +ENTRY(0x26B1, 0x172E, 0x10de, "NVIDIA RTX6000-Ada-48C"), +ENTRY(0x26B2, 0x1821, 0x10de, "NVIDIA RTX5000-Ada-1B"), +ENTRY(0x26B2, 0x1822, 0x10de, "NVIDIA RTX5000-Ada-2B"), +ENTRY(0x26B2, 0x1823, 0x10de, "NVIDIA RTX5000-Ada-1Q"), +ENTRY(0x26B2, 0x1824, 0x10de, "NVIDIA RTX5000-Ada-2Q"), +ENTRY(0x26B2, 0x1825, 0x10de, "NVIDIA RTX5000-Ada-4Q"), +ENTRY(0x26B2, 0x1826, 0x10de, "NVIDIA RTX5000-Ada-8Q"), +ENTRY(0x26B2, 0x1827, 0x10de, "NVIDIA RTX5000-Ada-16Q"), +ENTRY(0x26B2, 0x1828, 0x10de, "NVIDIA RTX5000-Ada-32Q"), +ENTRY(0x26B2, 0x1829, 0x10de, "NVIDIA RTX5000-Ada-1A"), +ENTRY(0x26B2, 0x182A, 0x10de, "NVIDIA RTX5000-Ada-2A"), +ENTRY(0x26B2, 0x182B, 0x10de, "NVIDIA RTX5000-Ada-4A"), +ENTRY(0x26B2, 0x182C, 0x10de, "NVIDIA RTX5000-Ada-8A"), +ENTRY(0x26B2, 0x182D, 0x10de, "NVIDIA RTX5000-Ada-16A"), +ENTRY(0x26B2, 0x182E, 0x10de, "NVIDIA RTX5000-Ada-32A"), +ENTRY(0x26B2, 0x182F, 0x10de, "NVIDIA RTX5000-Ada-1"), +ENTRY(0x26B2, 0x1830, 0x10de, "NVIDIA RTX5000-Ada-2"), +ENTRY(0x26B2, 0x1831, 0x10de, "NVIDIA RTX5000-Ada-4"), +ENTRY(0x26B2, 0x1832, 0x10de, "NVIDIA RTX5000-Ada-8"), +ENTRY(0x26B2, 0x1833, 0x10de, "NVIDIA RTX5000-Ada-16"), +ENTRY(0x26B2, 0x1834, 0x10de, "NVIDIA RTX5000-Ada-32"), +ENTRY(0x26B2, 0x1835, 0x10de, "NVIDIA RTX5000-Ada-4C"), +ENTRY(0x26B2, 0x1836, 0x10de, "NVIDIA RTX5000-Ada-8C"), +ENTRY(0x26B2, 0x1837, 0x10de, "NVIDIA RTX5000-Ada-16C"), +ENTRY(0x26B2, 0x1838, 0x10de, "NVIDIA RTX5000-Ada-32C"), +ENTRY(0x26B5, 0x176D, 0x10de, "NVIDIA L40-1B"), +ENTRY(0x26B5, 0x176E, 0x10de, "NVIDIA L40-2B"), +ENTRY(0x26B5, 0x176F, 0x10de, "NVIDIA L40-1Q"), +ENTRY(0x26B5, 0x1770, 0x10de, "NVIDIA L40-2Q"), +ENTRY(0x26B5, 0x1771, 0x10de, "NVIDIA L40-3Q"), +ENTRY(0x26B5, 0x1772, 0x10de, "NVIDIA L40-4Q"), +ENTRY(0x26B5, 0x1773, 0x10de, "NVIDIA L40-6Q"), +ENTRY(0x26B5, 0x1774, 0x10de, "NVIDIA L40-8Q"), +ENTRY(0x26B5, 0x1775, 0x10de, "NVIDIA L40-12Q"), +ENTRY(0x26B5, 0x1776, 0x10de, "NVIDIA L40-16Q"), +ENTRY(0x26B5, 0x1777, 0x10de, "NVIDIA L40-24Q"), +ENTRY(0x26B5, 0x1778, 0x10de, "NVIDIA L40-48Q"), +ENTRY(0x26B5, 0x1779, 0x10de, "NVIDIA L40-1A"), +ENTRY(0x26B5, 0x177A, 0x10de, "NVIDIA L40-2A"), +ENTRY(0x26B5, 0x177B, 0x10de, "NVIDIA L40-3A"), +ENTRY(0x26B5, 0x177C, 0x10de, "NVIDIA L40-4A"), +ENTRY(0x26B5, 0x177D, 0x10de, "NVIDIA L40-6A"), +ENTRY(0x26B5, 0x177E, 0x10de, "NVIDIA L40-8A"), +ENTRY(0x26B5, 0x177F, 0x10de, "NVIDIA L40-12A"), +ENTRY(0x26B5, 0x1780, 0x10de, "NVIDIA L40-16A"), +ENTRY(0x26B5, 0x1781, 0x10de, "NVIDIA L40-24A"), +ENTRY(0x26B5, 0x1782, 0x10de, "NVIDIA L40-48A"), +ENTRY(0x26B5, 0x1783, 0x10de, "NVIDIA L40-1"), +ENTRY(0x26B5, 0x1784, 0x10de, "NVIDIA L40-2"), +ENTRY(0x26B5, 0x1785, 0x10de, "NVIDIA L40-3"), +ENTRY(0x26B5, 0x1786, 0x10de, "NVIDIA L40-4"), +ENTRY(0x26B5, 0x1787, 0x10de, "NVIDIA L40-6"), +ENTRY(0x26B5, 0x1788, 0x10de, "NVIDIA L40-8"), +ENTRY(0x26B5, 0x1789, 0x10de, "NVIDIA L40-12"), +ENTRY(0x26B5, 0x178A, 0x10de, "NVIDIA L40-16"), +ENTRY(0x26B5, 0x178B, 0x10de, "NVIDIA L40-24"), +ENTRY(0x26B5, 0x178C, 0x10de, "NVIDIA L40-48"), +ENTRY(0x26B5, 0x178D, 0x10de, "NVIDIA L40-4C"), +ENTRY(0x26B5, 0x178E, 0x10de, "NVIDIA L40-6C"), +ENTRY(0x26B5, 0x178F, 0x10de, "NVIDIA L40-8C"), +ENTRY(0x26B5, 0x1790, 0x10de, "NVIDIA L40-12C"), +ENTRY(0x26B5, 0x1791, 0x10de, "NVIDIA L40-16C"), +ENTRY(0x26B5, 0x1792, 0x10de, "NVIDIA L40-24C"), +ENTRY(0x26B5, 0x1793, 0x10de, "NVIDIA L40-48C"), +ENTRY(0x26B5, 0x1818, 0x10de, "NVIDIA GeForce RTX 3060"), +ENTRY(0x26B5, 0x181A, 0x10de, "NVIDIA GeForce RTX 3050"), +ENTRY(0x26B8, 0x174E, 0x10de, "NVIDIA L40G-1B"), +ENTRY(0x26B8, 0x174F, 0x10de, "NVIDIA L40G-2B"), +ENTRY(0x26B8, 0x1750, 0x10de, "NVIDIA L40G-1Q"), +ENTRY(0x26B8, 0x1751, 0x10de, "NVIDIA L40G-2Q"), +ENTRY(0x26B8, 0x1752, 0x10de, "NVIDIA L40G-3Q"), +ENTRY(0x26B8, 0x1753, 0x10de, "NVIDIA L40G-4Q"), +ENTRY(0x26B8, 0x1754, 0x10de, "NVIDIA L40G-6Q"), +ENTRY(0x26B8, 0x1755, 0x10de, "NVIDIA L40G-8Q"), +ENTRY(0x26B8, 0x1756, 0x10de, "NVIDIA L40G-12Q"), +ENTRY(0x26B8, 0x1757, 0x10de, "NVIDIA L40G-24Q"), +ENTRY(0x26B8, 0x1758, 0x10de, "NVIDIA L40G-1A"), +ENTRY(0x26B8, 0x1759, 0x10de, "NVIDIA L40G-2A"), +ENTRY(0x26B8, 0x175A, 0x10de, "NVIDIA L40G-3A"), +ENTRY(0x26B8, 0x175B, 0x10de, "NVIDIA L40G-4A"), +ENTRY(0x26B8, 0x175C, 0x10de, "NVIDIA L40G-6A"), +ENTRY(0x26B8, 0x175D, 0x10de, "NVIDIA L40G-8A"), +ENTRY(0x26B8, 0x175E, 0x10de, "NVIDIA L40G-12A"), +ENTRY(0x26B8, 0x175F, 0x10de, "NVIDIA L40G-24A"), +ENTRY(0x26B8, 0x1760, 0x10de, "NVIDIA L40G-1"), +ENTRY(0x26B8, 0x1761, 0x10de, "NVIDIA L40G-2"), +ENTRY(0x26B8, 0x1762, 0x10de, "NVIDIA L40G-3"), +ENTRY(0x26B8, 0x1763, 0x10de, "NVIDIA L40G-4"), +ENTRY(0x26B8, 0x1764, 0x10de, "NVIDIA L40G-6"), +ENTRY(0x26B8, 0x1765, 0x10de, "NVIDIA L40G-8"), +ENTRY(0x26B8, 0x1766, 0x10de, "NVIDIA L40G-12"), +ENTRY(0x26B8, 0x1767, 0x10de, "NVIDIA L40G-24"), +ENTRY(0x26B8, 0x1768, 0x10de, "NVIDIA L40G-4C"), +ENTRY(0x26B8, 0x1769, 0x10de, "NVIDIA L40G-6C"), +ENTRY(0x26B8, 0x176A, 0x10de, "NVIDIA L40G-8C"), +ENTRY(0x26B8, 0x176B, 0x10de, "NVIDIA L40G-12C"), +ENTRY(0x26B8, 0x176C, 0x10de, "NVIDIA L40G-24C"), +ENTRY(0x26B8, 0x181C, 0x10de, "NVIDIA GeForce RTX 3060"), +ENTRY(0x26B8, 0x181E, 0x10de, "NVIDIA GeForce RTX 3050"), +ENTRY(0x26B9, 0x1889, 0x10de, "NVIDIA L40S-1B"), +ENTRY(0x26B9, 0x188A, 0x10de, "NVIDIA L40S-2B"), +ENTRY(0x26B9, 0x188B, 0x10de, "NVIDIA L40S-1Q"), +ENTRY(0x26B9, 0x188C, 0x10de, "NVIDIA L40S-2Q"), +ENTRY(0x26B9, 0x188D, 0x10de, "NVIDIA L40S-3Q"), +ENTRY(0x26B9, 0x188E, 0x10de, "NVIDIA L40S-4Q"), +ENTRY(0x26B9, 0x188F, 0x10de, "NVIDIA L40S-6Q"), +ENTRY(0x26B9, 0x1890, 0x10de, "NVIDIA L40S-8Q"), +ENTRY(0x26B9, 0x1891, 0x10de, "NVIDIA L40S-12Q"), +ENTRY(0x26B9, 0x1892, 0x10de, "NVIDIA L40S-16Q"), +ENTRY(0x26B9, 0x1893, 0x10de, "NVIDIA L40S-24Q"), +ENTRY(0x26B9, 0x1894, 0x10de, "NVIDIA L40S-48Q"), +ENTRY(0x26B9, 0x1895, 0x10de, "NVIDIA L40S-1A"), +ENTRY(0x26B9, 0x1896, 0x10de, "NVIDIA L40S-2A"), +ENTRY(0x26B9, 0x1897, 0x10de, "NVIDIA L40S-3A"), +ENTRY(0x26B9, 0x1898, 0x10de, "NVIDIA L40S-4A"), +ENTRY(0x26B9, 0x1899, 0x10de, "NVIDIA L40S-6A"), +ENTRY(0x26B9, 0x189A, 0x10de, "NVIDIA L40S-8A"), +ENTRY(0x26B9, 0x189B, 0x10de, "NVIDIA L40S-12A"), +ENTRY(0x26B9, 0x189C, 0x10de, "NVIDIA L40S-16A"), +ENTRY(0x26B9, 0x189D, 0x10de, "NVIDIA L40S-24A"), +ENTRY(0x26B9, 0x189E, 0x10de, "NVIDIA L40S-48A"), +ENTRY(0x26B9, 0x189F, 0x10de, "NVIDIA GeForce RTX 3050"), +ENTRY(0x26B9, 0x18A0, 0x10de, "NVIDIA GeForce RTX 3060"), +ENTRY(0x26B9, 0x18A1, 0x10de, "NVIDIA L40S-1"), +ENTRY(0x26B9, 0x18A2, 0x10de, "NVIDIA L40S-2"), +ENTRY(0x26B9, 0x18A3, 0x10de, "NVIDIA L40S-3"), +ENTRY(0x26B9, 0x18A4, 0x10de, "NVIDIA L40S-4"), +ENTRY(0x26B9, 0x18A5, 0x10de, "NVIDIA L40S-6"), +ENTRY(0x26B9, 0x18A6, 0x10de, "NVIDIA L40S-8"), +ENTRY(0x26B9, 0x18A7, 0x10de, "NVIDIA L40S-12"), +ENTRY(0x26B9, 0x18A8, 0x10de, "NVIDIA L40S-16"), +ENTRY(0x26B9, 0x18A9, 0x10de, "NVIDIA L40S-24"), +ENTRY(0x26B9, 0x18AA, 0x10de, "NVIDIA L40S-48"), +ENTRY(0x26B9, 0x18AB, 0x10de, "NVIDIA L40S-4C"), +ENTRY(0x26B9, 0x18AC, 0x10de, "NVIDIA L40S-6C"), +ENTRY(0x26B9, 0x18AD, 0x10de, "NVIDIA L40S-8C"), +ENTRY(0x26B9, 0x18AE, 0x10de, "NVIDIA L40S-12C"), +ENTRY(0x26B9, 0x18AF, 0x10de, "NVIDIA L40S-16C"), +ENTRY(0x26B9, 0x18B0, 0x10de, "NVIDIA L40S-24C"), +ENTRY(0x26B9, 0x18B1, 0x10de, "NVIDIA L40S-48C"), +ENTRY(0x27B8, 0x172F, 0x10de, "NVIDIA L4-1B"), +ENTRY(0x27B8, 0x1730, 0x10de, "NVIDIA L4-2B"), +ENTRY(0x27B8, 0x1731, 0x10de, "NVIDIA L4-1Q"), +ENTRY(0x27B8, 0x1732, 0x10de, "NVIDIA L4-2Q"), +ENTRY(0x27B8, 0x1733, 0x10de, "NVIDIA L4-3Q"), +ENTRY(0x27B8, 0x1734, 0x10de, "NVIDIA L4-4Q"), +ENTRY(0x27B8, 0x1735, 0x10de, "NVIDIA L4-6Q"), +ENTRY(0x27B8, 0x1736, 0x10de, "NVIDIA L4-8Q"), +ENTRY(0x27B8, 0x1737, 0x10de, "NVIDIA L4-12Q"), +ENTRY(0x27B8, 0x1738, 0x10de, "NVIDIA L4-24Q"), +ENTRY(0x27B8, 0x1739, 0x10de, "NVIDIA L4-1A"), +ENTRY(0x27B8, 0x173A, 0x10de, "NVIDIA L4-2A"), +ENTRY(0x27B8, 0x173B, 0x10de, "NVIDIA L4-3A"), +ENTRY(0x27B8, 0x173C, 0x10de, "NVIDIA L4-4A"), +ENTRY(0x27B8, 0x173D, 0x10de, "NVIDIA L4-6A"), +ENTRY(0x27B8, 0x173E, 0x10de, "NVIDIA L4-8A"), +ENTRY(0x27B8, 0x173F, 0x10de, "NVIDIA L4-12A"), +ENTRY(0x27B8, 0x1740, 0x10de, "NVIDIA L4-24A"), +ENTRY(0x27B8, 0x1741, 0x10de, "NVIDIA L4-1"), +ENTRY(0x27B8, 0x1742, 0x10de, "NVIDIA L4-2"), +ENTRY(0x27B8, 0x1743, 0x10de, "NVIDIA L4-3"), +ENTRY(0x27B8, 0x1744, 0x10de, "NVIDIA L4-4"), +ENTRY(0x27B8, 0x1745, 0x10de, "NVIDIA L4-6"), +ENTRY(0x27B8, 0x1746, 0x10de, "NVIDIA L4-8"), +ENTRY(0x27B8, 0x1747, 0x10de, "NVIDIA L4-12"), +ENTRY(0x27B8, 0x1748, 0x10de, "NVIDIA L4-24"), +ENTRY(0x27B8, 0x1749, 0x10de, "NVIDIA L4-4C"), +ENTRY(0x27B8, 0x174A, 0x10de, "NVIDIA L4-6C"), +ENTRY(0x27B8, 0x174B, 0x10de, "NVIDIA L4-8C"), +ENTRY(0x27B8, 0x174C, 0x10de, "NVIDIA L4-12C"), +ENTRY(0x27B8, 0x174D, 0x10de, "NVIDIA L4-24C"), + +}; +#endif /* _G_VGPU_CHIP_FLAGS_H_ */ diff --git a/src/common/shared/inc/g_vgpu_resman_specific.h b/src/common/shared/inc/g_vgpu_resman_specific.h index 22273b7c6c..8be1f5bf1f 100644 --- a/src/common/shared/inc/g_vgpu_resman_specific.h +++ b/src/common/shared/inc/g_vgpu_resman_specific.h @@ -3,7 +3,7 @@ ***********************************************************************************/ -#ifdef __VGPU_ALIAS_PGPU_LIST__ +#if defined (__VGPU_ALIAS_PGPU_LIST__) static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id) { struct vgpu_alias_details { @@ -14,8 +14,13 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id) } vgpu_aliases[] = { { 0x20B5, 0x1642, 0x20B5, 0x1533 }, { 0x20B8, 0x1581, 0x20B5, 0x1533 }, + { 0x20B7, 0x1804, 0x20B7, 0x1532 }, { 0x20B9, 0x157F, 0x20B7, 0x1532 }, + { 0x20FD, 0x17F8, 0x20F5, 0x0 }, + { 0x2324, 0x17A8, 0x2324, 0x17A6 }, { 0x2330, 0x16C0, 0x2330, 0x16C1 }, + { 0x2336, 0x16C2, 0x2330, 0x16C1 }, + { 0x2342, 0x1809, 0x2342, 0x1805 }, }; for (NvU32 i = 0; i < (sizeof(vgpu_aliases) / sizeof(struct vgpu_alias_details)); ++i) { @@ -31,3 +36,157 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id) #endif //__VGPU_ALIAS_PGPU_LIST__ +#if defined(GENERATE_vgpuSmcTypeIdMappings) +static const struct { + NvU32 devId; + NvU32 partitionFlag; + NvU32 vgpuTypeId; +} vgpuSmcTypeIdMappings [] = { + {0x20B010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 463}, // GRID A100X-1-5C + {0x20B010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 464}, // GRID A100X-2-10C + {0x20B010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 465}, // GRID A100X-3-20C + {0x20B010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 466}, // GRID A100X-4-20C + {0x20B010DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 467}, // GRID A100X-7-40C + {0x20B010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 704}, // GRID A100X-1-5CME + {0x20B010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1056}, // GRID A100X-1-10C + {0x20B210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 622}, // GRID A100DX-1-10C + {0x20B210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 623}, // GRID A100DX-2-20C + {0x20B210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 624}, // GRID A100DX-3-40C + {0x20B210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 625}, // GRID A100DX-4-40C + {0x20B210DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 626}, // GRID A100DX-7-80C + {0x20B210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 705}, // GRID A100DX-1-10CME + {0x20B210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1057}, // GRID A100DX-1-20C + {0x20B510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 699}, // GRID A100D-1-10C + {0x20B810DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 699}, // GRID A100D-1-10C + {0x20B510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 700}, // GRID A100D-2-20C + {0x20B810DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 700}, // GRID A100D-2-20C + {0x20B510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 701}, // GRID A100D-3-40C + {0x20B810DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 701}, // GRID A100D-3-40C + {0x20B510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 702}, // GRID A100D-4-40C + {0x20B810DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 702}, // GRID A100D-4-40C + {0x20B510DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 703}, // GRID A100D-7-80C + {0x20B810DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 703}, // GRID A100D-7-80C + {0x20B510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 707}, // GRID A100D-1-10CME + {0x20B810DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 707}, // GRID A100D-1-10CME + {0x20B510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1054}, // GRID A100D-1-20C + {0x20B810DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1054}, // GRID A100D-1-20C + {0x20B710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 689}, // NVIDIA A30-1-6C + {0x20B910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 689}, // NVIDIA A30-1-6C + {0x20B710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 690}, // NVIDIA A30-2-12C + {0x20B910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 690}, // NVIDIA A30-2-12C + {0x20B710DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 691}, // NVIDIA A30-4-24C + {0x20B910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 691}, // NVIDIA A30-4-24C + {0x20B710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE) , 708}, // NVIDIA A30-1-6CME + {0x20B910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE) , 708}, // NVIDIA A30-1-6CME + {0x20B710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE) , 1052}, // NVIDIA A30-2-12CME + {0x20B910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE) , 1052}, // NVIDIA A30-2-12CME + {0x20F110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 474}, // GRID A100-1-5C + {0x20F110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 475}, // GRID A100-2-10C + {0x20F110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 476}, // GRID A100-3-20C + {0x20F110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 477}, // GRID A100-4-20C + {0x20F110DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 478}, // GRID A100-7-40C + {0x20F110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 706}, // GRID A100-1-5CME + {0x20F110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1053}, // GRID A100-1-10C + {0x20F310DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 994}, // GRID A800DX-1-10CME + {0x20F310DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 995}, // GRID A800DX-1-10C + {0x20F310DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 996}, // GRID A800DX-2-20C + {0x20F310DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 997}, // GRID A800DX-3-40C + {0x20F310DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 998}, // GRID A800DX-4-40C + {0x20F310DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 999}, // GRID A800DX-7-80C + {0x20F310DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1058}, // GRID A800DX-1-20C + {0x20F510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1007}, // GRID A800D-1-10CME + {0x20FD10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1007}, // GRID A800D-1-10CME + {0x20F510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1008}, // GRID A800D-1-10C + {0x20FD10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1008}, // GRID A800D-1-10C + {0x20F510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1009}, // GRID A800D-2-20C + {0x20FD10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1009}, // GRID A800D-2-20C + {0x20F510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1010}, // GRID A800D-3-40C + {0x20FD10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1010}, // GRID A800D-3-40C + {0x20F510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1011}, // GRID A800D-4-40C + {0x20FD10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1011}, // GRID A800D-4-40C + {0x20F510DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1012}, // GRID A800D-7-80C + {0x20FD10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1012}, // GRID A800D-7-80C + {0x20F510DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1055}, // GRID A800D-1-20C + {0x20FD10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1055}, // GRID A800D-1-20C + {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1089}, // GRID A800-1-5CME + {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1090}, // GRID A800-1-5C + {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1092}, // GRID A800-2-10C + {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1093}, // GRID A800-3-20C + {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1094}, // GRID A800-4-20C + {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1095}, // GRID A800-7-40C + {0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1091}, // GRID A800-1-10C + {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME + {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1062}, // NVIDIA H100L-1-12C + {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1063}, // NVIDIA H100L-1-24C + {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1064}, // NVIDIA H100L-2-24C + {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1065}, // NVIDIA H100L-3-47C + {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1066}, // NVIDIA H100L-4-47C + {0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1067}, // NVIDIA H100L-7-94C + {0x232210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 979}, // NVIDIA H800-1-10CME + {0x232210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 980}, // NVIDIA H800-1-10C + {0x232210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 981}, // NVIDIA H800-2-20C + {0x232210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 982}, // NVIDIA H800-3-40C + {0x232210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 983}, // NVIDIA H800-4-40C + {0x232210DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 984}, // NVIDIA H800-7-80C + {0x232210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1060}, // NVIDIA H800-1-20C + {0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1276}, // NVIDIA H800XM-1-10CME + {0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1277}, // NVIDIA H800XM-1-10C + {0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1278}, // NVIDIA H800XM-1-20C + {0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1279}, // NVIDIA H800XM-2-20C + {0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1280}, // NVIDIA H800XM-3-40C + {0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1281}, // NVIDIA H800XM-4-40C + {0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1282}, // NVIDIA H800XM-7-80C + {0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1130}, // NVIDIA H100XM-1-10CME + {0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1130}, // NVIDIA H100XM-1-10CME + {0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1131}, // NVIDIA H100XM-1-10C + {0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1131}, // NVIDIA H100XM-1-10C + {0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1132}, // NVIDIA H100XM-1-20C + {0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1132}, // NVIDIA H100XM-1-20C + {0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1133}, // NVIDIA H100XM-2-20C + {0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1133}, // NVIDIA H100XM-2-20C + {0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1134}, // NVIDIA H100XM-3-40C + {0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1134}, // NVIDIA H100XM-3-40C + {0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1135}, // NVIDIA H100XM-4-40C + {0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1135}, // NVIDIA H100XM-4-40C + {0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1136}, // NVIDIA H100XM-7-80C + {0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1136}, // NVIDIA H100XM-7-80C + {0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 821}, // NVIDIA H100-1-10C + {0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 822}, // NVIDIA H100-2-20C + {0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 823}, // NVIDIA H100-3-40C + {0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 824}, // NVIDIA H100-4-40C + {0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 825}, // NVIDIA H100-7-80C + {0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 993}, // NVIDIA H100-1-10CME + {0x233110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1059}, // NVIDIA H100-1-20C + {0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1305}, // NVIDIA H100XS-1-8CME + {0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1306}, // NVIDIA H100XS-1-8C + {0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1307}, // NVIDIA H100XS-1-16C + {0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1308}, // NVIDIA H100XS-2-16C + {0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1309}, // NVIDIA H100XS-3-32C + {0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1310}, // NVIDIA H100XS-4-32C + {0x233710DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1311}, // NVIDIA H100XS-7-64C + {0x233910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1291}, // NVIDIA H100XL-1-12CME + {0x233910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1292}, // NVIDIA H100XL-1-12C + {0x233910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1293}, // NVIDIA H100XL-1-24C + {0x233910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1294}, // NVIDIA H100XL-2-24C + {0x233910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1295}, // NVIDIA H100XL-3-47C + {0x233910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1296}, // NVIDIA H100XL-4-47C + {0x233910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1297}, // NVIDIA H100XL-7-94C + {0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1075}, // NVIDIA H800L-1-12CME + {0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1076}, // NVIDIA H800L-1-12C + {0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1077}, // NVIDIA H800L-1-24C + {0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1078}, // NVIDIA H800L-2-24C + {0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1079}, // NVIDIA H800L-3-47C + {0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1080}, // NVIDIA H800L-4-47C + {0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1081}, // NVIDIA H800L-7-94C + {0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1196}, // NVIDIA H100GL-1-12CME + {0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1197}, // NVIDIA H100GL-1-12C + {0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1198}, // NVIDIA H100GL-1-24C + {0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1199}, // NVIDIA H100GL-2-24C + {0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1200}, // NVIDIA H100GL-3-48C + {0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1201}, // NVIDIA H100GL-4-48C + {0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1202}, // NVIDIA H100GL-7-96C + +}; +#endif // GENERATE_vgpuSmcTypeIdMappings + + diff --git a/src/common/shared/inc/nvdevid.h b/src/common/shared/inc/nvdevid.h index 5dc62cbda3..768953597c 100644 --- a/src/common/shared/inc/nvdevid.h +++ b/src/common/shared/inc/nvdevid.h @@ -147,6 +147,8 @@ #define PCI_VENDOR_ID_ARM 0x13B5 #define PCI_VENDOR_ID_HYGON 0x1D94 #define PCI_VENDOR_ID_ALIBABA 0x1DED +#define PCI_VENDOR_ID_SIFIVE 0xF15E +#define PCI_VENDOR_ID_PLDA 0x1556 #define NV_PCI_DEVID_DEVICE 31:16 /* RW--F */ #define NV_PCI_SUBID_DEVICE 31:16 /* RW--F */ @@ -626,6 +628,9 @@ enum { , CS_INTEL_1B81 , CS_INTEL_18DC , CS_INTEL_7A04 +, CS_SIFIVE_FU740_C000 +, CS_PLDA_XPRESSRICH_AXI_REF +, CS_AMPERE_AMPEREONE , CS_MAX_PCIE }; diff --git a/src/common/shared/nvstatus/nvstatus.c b/src/common/shared/nvstatus/nvstatus.c index 92c5d7af8f..c01f4ea004 100644 --- a/src/common/shared/nvstatus/nvstatus.c +++ b/src/common/shared/nvstatus/nvstatus.c @@ -25,7 +25,8 @@ #if !defined(NV_PRINTF_STRING_SECTION) #if defined(NVRM) && NVOS_IS_LIBOS -#define NV_PRINTF_STRING_SECTION __attribute__ ((section (".logging"))) +#include "libos_log.h" +#define NV_PRINTF_STRING_SECTION LIBOS_SECTION_LOGGING #else // defined(NVRM) && NVOS_IS_LIBOS #define NV_PRINTF_STRING_SECTION #endif // defined(NVRM) && NVOS_IS_LIBOS @@ -33,7 +34,7 @@ /* * Include nvstatuscodes.h twice. Once for creating constant strings in the - * the NV_PRINTF_STRING_SECTION section of the ececutable, and once to build + * the NV_PRINTF_STRING_SECTION section of the executable, and once to build * the g_StatusCodeList table. */ #undef NV_STATUS_CODE diff --git a/src/common/unix/common/utils/unix_rm_handle.c b/src/common/unix/common/utils/unix_rm_handle.c index ed6ebbfb51..b24d0e05e3 100644 --- a/src/common/unix/common/utils/unix_rm_handle.c +++ b/src/common/unix/common/utils/unix_rm_handle.c @@ -195,8 +195,8 @@ NvU32 nvGenerateUnixRmHandleInternal(NVUnixRmHandleAllocatorPtr pAllocator) /* Find free handle */ handleId = 1; - while (USED(pAllocator->bitmap, handleId) && - (handleId <= pAllocator->maxHandles)) { + while ((handleId <= pAllocator->maxHandles) && + USED(pAllocator->bitmap, handleId)) { handleId++; } diff --git a/src/common/unix/nvidia-push/interface/nvidia-push-methods.h b/src/common/unix/nvidia-push/interface/nvidia-push-methods.h index bdbc558e79..6e06a7b5c2 100644 --- a/src/common/unix/nvidia-push/interface/nvidia-push-methods.h +++ b/src/common/unix/nvidia-push/interface/nvidia-push-methods.h @@ -72,6 +72,18 @@ static inline void nvPushSetMethodDataU64(NvPushChannelPtr p, const NvU64 data) __nvPushSetMethodDataSegmentU64(&p->main, data); } +/* Little-endian: least significant bits first. */ +static inline void __nvPushSetMethodDataSegmentU64LE(NvPushChannelSegmentPtr s, const NvU64 data) +{ + __nvPushSetMethodDataSegment(s, NvU64_LO32(data)); + __nvPushSetMethodDataSegment(s, NvU64_HI32(data)); +} + +static inline void nvPushSetMethodDataU64LE(NvPushChannelPtr p, const NvU64 data) +{ + __nvPushSetMethodDataSegmentU64LE(&p->main, data); +} + void __nvPushMoveDWORDS(NvU32* dst, const NvU32* src, int dwords); static inline void diff --git a/src/common/unix/nvidia-push/src/nvidia-push.c b/src/common/unix/nvidia-push/src/nvidia-push.c index c73e69f8d1..992a3bd1df 100644 --- a/src/common/unix/nvidia-push/src/nvidia-push.c +++ b/src/common/unix/nvidia-push/src/nvidia-push.c @@ -332,13 +332,7 @@ static void InsertProgressTracker(NvPushChannelPtr p, NvU32 putOffset, DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_WFI, _DIS)); __nvPushStart(p, progressTracker, 0, NVC36F_SEM_ADDR_LO, 5, _INC_METHOD); - /* - * NVC36F_SEM_ADDR_{LO,HI} is backwards from most 64-bit - * addresses spread over two methods, so we cannot use - * __nvPushSetMethodDataSegmentU64(). - */ - __nvPushSetMethodDataSegment(segment, NvU64_LO32(p->progressSemaphore.gpuVA)); - __nvPushSetMethodDataSegment(segment, NvU64_HI32(p->progressSemaphore.gpuVA)); + __nvPushSetMethodDataSegmentU64LE(segment, p->progressSemaphore.gpuVA); __nvPushSetMethodDataSegment(segment, payload); __nvPushSetMethodDataSegment(segment, 0); __nvPushSetMethodDataSegment(segment, semaphoreOperation); @@ -638,11 +632,16 @@ NvBool __nvPushTestPushBuffer(NvPushChannelPtr p) /* * Immediately after allocating the pushbuffer, push a channel NOP and * babysit the channel until it's consumed as a quick sanity check. + + * Note we use a full long timeout (10 seconds) when performing this + * sanity test. In normal operation, idling will happen very quickly. + * However, when the GPU is under heavy load in stress tests, it can + * take much longer to idle the channel. */ WriteGetOffset(p, 0); ret = IdleChannel(p, FALSE /* progressTrackerWFI */, - NV_PUSH_NOTIFIER_SHORT_TIMEOUT); + NV_PUSH_NOTIFIER_LONG_TIMEOUT); if (!ret) { nvPushImportLogError(p->pDevice, "Failed to initialize DMA."); @@ -1047,10 +1046,8 @@ static void VoltaReleaseTimelineSemaphore( NvU64 val) { nvPushMethod(p, 0, NVC36F_SEM_ADDR_LO, 5); - nvPushSetMethodData(p, NvU64_LO32(gpuAddress)); - nvPushSetMethodData(p, NvU64_HI32(gpuAddress)); // NVC36F_SEM_ADDR_HI - nvPushSetMethodData(p, NvU64_LO32(val)); // NVC36F_SEM_PAYLOAD_LO - nvPushSetMethodData(p, NvU64_HI32(val)); // NVC36F_SEM_PAYLOAD_HI + nvPushSetMethodDataU64LE(p, gpuAddress); // NVC36F_SEM_ADDR_LO/HI + nvPushSetMethodDataU64LE(p, val); // NVC36F_SEM_PAYLOAD_LO/HI nvPushSetMethodData(p, // NVC36F_SEM_EXECUTE DRF_DEF(C36F, _SEM_EXECUTE, _OPERATION, _RELEASE) | DRF_DEF(C36F, _SEM_EXECUTE, _RELEASE_WFI, _EN) | @@ -1067,10 +1064,8 @@ static void VoltaAcquireTimelineSemaphore( NvU64 val) { nvPushMethod(p, 0, NVC36F_SEM_ADDR_LO, 5); - nvPushSetMethodData(p, NvU64_LO32(gpuAddress)); - nvPushSetMethodData(p, NvU64_HI32(gpuAddress)); // NVC36F_SEM_ADDR_HI - nvPushSetMethodData(p, NvU64_LO32(val)); // NVC36F_SEM_PAYLOAD_LO - nvPushSetMethodData(p, NvU64_HI32(val)); // NVC36F_SEM_PAYLOAD_HI + nvPushSetMethodDataU64LE(p, gpuAddress); // NVC36F_SEM_ADDR_LO/HI + nvPushSetMethodDataU64LE(p, val); // NVC36F_SEM_PAYLOAD_LO/HI nvPushSetMethodData(p, // NVC36F_SEM_EXECUTE DRF_DEF(C36F, _SEM_EXECUTE, _OPERATION, _ACQ_STRICT_GEQ) | DRF_DEF(C36F, _SEM_EXECUTE, _ACQUIRE_SWITCH_TSG, _EN) | diff --git a/src/common/uproc/os/common/include/liblogdecode.h b/src/common/uproc/os/common/include/liblogdecode.h index c0c6862e78..845f43e6a8 100644 --- a/src/common/uproc/os/common/include/liblogdecode.h +++ b/src/common/uproc/os/common/include/liblogdecode.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -36,14 +36,16 @@ extern "C" { # define LIBOS_LOG_MAX_LOGS 5 // Max logs per GPU -#else // NVRM -# include +#elif defined(LIBOS_LOG_OFFLINE_DECODER) +# include "nvlog_decoder.h" # define LIBOS_LOG_DECODE_ENABLE 1 # define LIBOS_LOG_TO_NVLOG 0 # define LIBOS_LOG_MAX_LOGS 160 // Max logs for all GPUs for offline decoder +#else +# error "Need to define either NVRM or LIBOS_LOG_OFFLINE_DECODER." #endif // NVRM #define LIBOS_LOG_ENABLE (LIBOS_LOG_TO_NVLOG || LIBOS_LOG_DECODE_ENABLE) @@ -97,6 +99,8 @@ typedef struct NvU8 data[0]; } LIBOS_LOG_NVLOG_BUFFER; +#define LIBOS_LOG_NVLOG_BUFFER_SIZE(dataSize) (NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) + (dataSize)) + struct LIBOS_LOG_DECODE_LOG { volatile NvU64 *physicLogBuffer; @@ -147,20 +151,15 @@ typedef struct NvBool bDecodeStrShdr; #endif // LIBOS_LOG_DECODE_ENABLE -#if defined(NVSYM_STANDALONE) && !defined(PROTODMP_BUILD) - FILE *fout; // nvlog_decoder outputs to FILE descriptors -#elif defined(NVWATCH) - char *dest; // nvwatch dumps data into a string +#if defined(LIBOS_LOG_OFFLINE_DECODER) + LogPrinter *pLogPrinter; #endif } LIBOS_LOG_DECODE; -#if defined(NVSYM_STANDALONE) && !defined(PROTODMP_BUILD) -void libosLogCreate(LIBOS_LOG_DECODE *logDecode, FILE *fout); -void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName, FILE *fout); -#elif defined(NVWATCH) -void libosLogCreate(LIBOS_LOG_DECODE *logDecode, char *dest); -void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName, char *dest); +#if defined(LIBOS_LOG_OFFLINE_DECODER) +void libosLogCreate(LIBOS_LOG_DECODE *logDecode, LogPrinter *pLogPrinter); +void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName, LogPrinter *pLogPrinter); #else void libosLogCreate(LIBOS_LOG_DECODE *logDecode); void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName); @@ -181,7 +180,7 @@ void libosLogInitEx( NvBool bDecodeStrFmt, NvU64 elfSize); #endif // LIBOS_LOG_DECODE_ENABLE -void libosLogSymbolicateAddress(LIBOS_LOG_DECODE *logDecode, char *decodedLine, NvLength decodedLineSize, NvUPtr addr); +NvBool libosLogSymbolicateAddress(LIBOS_LOG_DECODE *logDecode, char *decodedLine, NvLength decodedLineSize, NvUPtr addr); void libosLogDestroy(LIBOS_LOG_DECODE *logDecode); diff --git a/src/common/uproc/os/common/include/libos_log.h b/src/common/uproc/os/common/include/libos_log.h index 6cb781b43f..bae9f577bb 100644 --- a/src/common/uproc/os/common/include/libos_log.h +++ b/src/common/uproc/os/common/include/libos_log.h @@ -46,6 +46,7 @@ typedef struct NV_DECLARE_ALIGNED(NvU32 lineNumber, 8); NvU8 argumentCount; //! Count of arguments not including format string. NvU8 printLevel; + NvU8 specialType; } libosLogMetadata; /** @@ -291,24 +292,31 @@ void LibosLogTokens(const libosLogMetadata * metadata, const LibosPrintfArgument /*! * Cast remaining log arguments to integers for storage */ -#define LIBOS_LOG_INTERNAL(dispatcher, level, ...) \ +#define LIBOS_LOG_INTERNAL_SPECIAL(dispatcher, level, special, ...) \ do \ { \ static const LIBOS_SECTION_LOGGING_CONST char libos_pvt_format[] = {LIBOS_MACRO_FIRST(__VA_ARGS__)}; \ static const LIBOS_SECTION_LOGGING_CONST char libos_pvt_file[] = {__FILE__}; \ - if (0) \ - LIBOS_CHECK_PRINTF_FMT(__VA_ARGS__); \ LIBOS_LOGGING_AUX_METADATA_DUMP; \ static const LIBOS_SECTION_LOGGING_METADATA libosLogMetadata libos_pvt_meta = { \ .filename = &libos_pvt_file[0], \ .format = &libos_pvt_format[0], \ .lineNumber = __LINE__, \ .argumentCount = LIBOS_MACRO_GET_COUNT(__VA_ARGS__) - 1, \ - .printLevel = level}; \ + .printLevel = level, \ + .specialType = special}; \ const NvU64 tokens[] = {APPLY_REMAINDER(__VA_ARGS__)(NvU64) & libos_pvt_meta}; \ dispatcher(sizeof(tokens) / sizeof(*tokens), &tokens[0]); \ } while (0) +#define LIBOS_LOG_INTERNAL(dispatcher, level, ...) \ + do \ + { \ + if (0) \ + LIBOS_CHECK_PRINTF_FMT(__VA_ARGS__); \ + LIBOS_LOG_INTERNAL_SPECIAL(dispatcher, level, 0 /* specialType */, __VA_ARGS__); \ + } while (0) + /*! * Cast remaining log arguments to integers for storage * This macro is used when logging for other task's address diff --git a/src/common/uproc/os/common/include/libos_printf_arg.h b/src/common/uproc/os/common/include/libos_printf_arg.h index 49aeb10c62..2349715532 100644 --- a/src/common/uproc/os/common/include/libos_printf_arg.h +++ b/src/common/uproc/os/common/include/libos_printf_arg.h @@ -24,7 +24,7 @@ #define LIBOS_PRINTF_ARG_H_ #include "nvtypes.h" -#if !defined(NVRM) && !defined(PMU_RTOS) && !defined(NVSYM_STANDALONE) +#if !defined(NVRM) && !defined(PMU_RTOS) && !defined(LIBOS_LOG_OFFLINE_DECODER) #include "libos-config.h" #endif diff --git a/src/common/uproc/os/common/include/libos_v3_crashcat.h b/src/common/uproc/os/common/include/libos_v3_crashcat.h new file mode 100644 index 0000000000..1aafd2ed13 --- /dev/null +++ b/src/common/uproc/os/common/include/libos_v3_crashcat.h @@ -0,0 +1,174 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef LIBOS_V3_CRASH_CAT_H +#define LIBOS_V3_CRASH_CAT_H + +#include "nv-crashcat.h" +#include "nv-crashcat-decoder.h" + +// libosv3 implements the CrashCat V1 protocol with the following implementation-defined bits + +typedef enum +{ + LibosPanicReasonUnspecified = 0x00, + LibosPanicReasonUnhandledState = 0x01, + LibosPanicReasonInvalidConfiguration = 0x02, + LibosPanicReasonFatalHardwareError = 0x03, + LibosPanicReasonInsufficientResources = 0x04, + LibosPanicReasonTimeout = 0x05, + LibosPanicReasonEnvCallFailed = 0x06, + LibosPanicReasonAsanMemoryError = 0x08, + LibosPanicReasonProgrammingError = 0x0a, + LibosPanicReasonAssertionFailed = 0x0b, + LibosPanicReasonTrapKernelPanic = 0x0c, + LibosPanicReasonTrapInstruction = 0x0d, + LibosPanicReasonCount +} LibosPanicReason; + +typedef enum{ + LibosKernelModuleInit = 0x00, + LibosKernelModuleIpi = 0x01, + LibosKernelModuleLoader = 0x02, + LibosKernelModulePartition = 0x03, + LibosKernelModuleSbi = 0x04, + LibosKernelModulePagetable = 0x05, + LibosKernelModuleAddressSpace = 0x06, + LibosKernelModuleIdentity = 0x07, + LibosKernelModuleObjectPool = 0x08, + LibosKernelModulePageState = 0x09, + LibosKernelModuleMemoryPool = 0x10, + LibosKernelModuleBuddyState = 0x11, + LibosKernelModuleServer = 0x12, + LibosKernelModuleDmaDriver = 0x13, + LibosKernelModuleExtIntrDriver = 0x14, + LibosKernelModuleSoftMmuCore = 0x15, + LibosKernelModulePagestream = 0x16, + LibosKernelModuleTask = 0x17, + LibosKernelModuleGdmaDriver = 0x18, + LibosKernelModuleCacheDriver = 0x19, + LibosKernelModuleMinTree = 0x20, + LibosKernelModuleList = 0x21, + LibosKernelModuleSpinlock = 0x22, + LibosKernelModuleScheduler = 0x23, + LibosKernelModulePort = 0x24, + LibosKernelModuleGlobalPort = 0x25, + LibosKernelModuleProxyPort = 0x26, + LibosKernelModuleTimer = 0x27, +} LibosKernelModule; + +// NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE (bits 63:0) - "LIBOS3.1" +#define NV_CRASHCAT_REPORT_IMPLEMENTER_SIGNATURE_LIBOS3 (0x4C49424F53332E31ull) + +// NV_CRASHCAT_REPORT_V1_REPORTER_ID_IMPL_DEF (bits 63:18) +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID 31:24 +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_RESERVED 63:32 +#define NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID_UNSPECIFIED (0xFF) + +static NV_INLINE +void crashcatReportV1SetReporterLibos3TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id) +{ + pReport->reporterId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS3_TASK_ID, + task_id, pReport->reporterId); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterLibos3TaskId(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_REPORTER_ID, _LIBOS3_TASK_ID, pReport->reporterId); +} + +// NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION (bits 31:0) +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_CL 23:0 +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_MINOR 27:24 +#define NV_CRASHCAT_REPORT_V1_REPORTER_DATA_VERSION_LIBOS3_MAJOR 31:28 + +static NV_INLINE +void crashcatReportV1SetReporterVersionLibos3(NvCrashCatReport_V1 *pReport, NvU32 cl) +{ + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_MAJOR, 3, pReport->reporterData); + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_MINOR, 1, pReport->reporterData); + pReport->reporterData = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_REPORTER_DATA, + _VERSION_LIBOS3_CL, cl, pReport->reporterData); +} + +static NV_INLINE +NvU32 crashcatReportV1ReporterVersionLibos3Cl(NvCrashCatReport_V1 *pReport) +{ + return DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_CL, + crashcatReportV1ReporterVersion(pReport)); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterVersionLibos3Minor(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_MINOR, + crashcatReportV1ReporterVersion(pReport)); +} + +static NV_INLINE +NvU8 crashcatReportV1ReporterVersionLibos3Major(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL(_CRASHCAT, _REPORT_V1_REPORTER_DATA_VERSION, _LIBOS3_MAJOR, + crashcatReportV1ReporterVersion(pReport)); +} + +// NV_CRASHCAT_REPORT_V1_SOURCE_ID_IMPL_DEF (63:18) +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID 31:24 +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_RESERVED 63:32 +#define NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID_UNSPECIFIED (0xFF) + +static NV_INLINE +void crashcatReportV1SetSourceLibos3TaskId(NvCrashCatReport_V1 *pReport, NvU8 task_id) +{ + pReport->sourceId = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS3_TASK_ID, task_id, + pReport->sourceId); +} + +static NV_INLINE +NvU8 crashcatReportV1SourceLibos3TaskId(NvCrashCatReport_V1 *pReport) +{ + return (NvU8)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_ID, _LIBOS3_TASK_ID, pReport->sourceId); +} + +// NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_IMPL_DEF (63:32) +#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS3_REASON 39:32 +#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_LIBOS3_RESERVED 63:40 + +static NV_INLINE +void crashcatReportV1SetSourceCauseLibos3Reason(NvCrashCatReport_V1 *pReport, + LibosPanicReason reason) +{ + pReport->sourceCause = FLD_SET_DRF_NUM64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS3_REASON, + reason, pReport->sourceCause); +} + +static NV_INLINE +LibosPanicReason crashcatReportV1SourceCauseLibos3Reason(NvCrashCatReport_V1 *pReport) +{ + return (LibosPanicReason)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _LIBOS3_REASON, + pReport->sourceCause); +} + +#endif // LIBOS_V3_CRASH_CAT_H diff --git a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c index 104cc9654c..5114675d60 100644 --- a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c @@ -55,20 +55,18 @@ # define portMemAllocNonPaged(l) malloc(l) # define portMemFree(p) free(p) -# if defined(PROTODMP_BUILD) -int logPrintf(const char *, ...); // Forward declaration. TODO: allow libos code to #include protodmp headers? -# define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) logPrintf(fmt, ##__VA_ARGS__) -# elif defined(NVSYM_STANDALONE) -# define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) fprintf(logDecode->fout, fmt, ##__VA_ARGS__) -# elif defined(NVWATCH) +# if defined(NVWATCH) # pragma warning(push) -# pragma warning(disable : 4200) # pragma warning(disable : 4244) # pragma warning(disable : 4267) -# define snprintf _snprintf -# define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) do { logDecode->dest += sprintf(logDecode->dest, fmt, ##__VA_ARGS__); } while (NV_FALSE) # endif +# if defined(LIBOS_LOG_OFFLINE_DECODER) +# define LIBOS_LOG_DECODE_PRINTF(level, fmt, ...) NVLD_PRINTF(logDecode->pLogPrinter, fmt, ##__VA_ARGS__) +# endif + +# define RMCFG_FEATURE_x 0 + #endif // NVRM #ifndef LIBOS_LOG_DECODE_PRINTF @@ -78,6 +76,7 @@ int logPrintf(const char *, ...); // Forward declaration. TODO: allow libos code #include #include "nvtypes.h" +#include "nvstatus.h" #include "liblogdecode.h" #include "utils/nvprintf_level.h" @@ -320,6 +319,14 @@ static void flush_line_buffer(LIBOS_LOG_DECODE *logDecode) // Sanitize log level for live decoding from RM. if (logLevel > NV_LEVEL_MAX) logLevel = NV_LEVEL_MAX; + + // + // FIXME (bug 3924763): by default, nv_printf prints messages at level >= NV_DBG_WARNINGS=3. + // We want to show all prints >= LEVEL_NOTICE=2, so bump LEVEL_NOTICE=2 to LEVEL_WARNING=3 for now. + // This will be fixed by remapping log levels correctly. + // + if (logLevel == LEVEL_NOTICE) + logLevel = LEVEL_WARNING; #endif LIBOS_LOG_DECODE_PRINTF(logLevel, "%s", logDecode->lineBuffer); @@ -354,7 +361,7 @@ static void emit_string(const char *s, int l, LIBOS_LOG_DECODE *logDecode) } } -static void s_getSymbolDataStr(LibosDebugResolver *resolver, char *decodedLine, NvLength decodedLineSize, NvUPtr addr) +static NvBool s_getSymbolDataStr(LibosDebugResolver *resolver, char *decodedLine, NvLength decodedLineSize, NvUPtr addr) { const char *directory; const char *filename; @@ -363,15 +370,19 @@ static void s_getSymbolDataStr(LibosDebugResolver *resolver, char *decodedLine, NvU64 outputLine; NvU64 outputColumn; NvU64 matchedAddress; + NvBool bResolved = NV_FALSE; + if (!LibosDebugResolveSymbolToName(resolver, addr, &name, &offset)) { - name = 0; + name = NULL; } + decodedLine[decodedLineSize - 1U] = '\0'; - if (LibosDwarfResolveLine( - resolver, addr, &directory, &filename, &outputLine, &outputColumn, - &matchedAddress)) + bResolved = LibosDwarfResolveLine(resolver, addr, &directory, &filename, &outputLine, + &outputColumn, &matchedAddress); + + if (bResolved) { if (name) { @@ -388,11 +399,15 @@ static void s_getSymbolDataStr(LibosDebugResolver *resolver, char *decodedLine, { snprintf(decodedLine, decodedLineSize - 1, "%s+%lld", name, offset); } + + bResolved |= (name != NULL); + + return bResolved; } -void libosLogSymbolicateAddress(LIBOS_LOG_DECODE *logDecode, char *decodedLine, NvLength decodedLineSize, NvUPtr addr) +NvBool libosLogSymbolicateAddress(LIBOS_LOG_DECODE *logDecode, char *decodedLine, NvLength decodedLineSize, NvUPtr addr) { - s_getSymbolDataStr(&logDecode->log[0].resolver, decodedLine, decodedLineSize, addr); + return s_getSymbolDataStr(&logDecode->log[0].resolver, decodedLine, decodedLineSize, addr); } /** @@ -501,6 +516,7 @@ static int libos_printf_a( char wc[2]; char *line_buffer_end = logDecode->lineBuffer + LIBOS_LOG_LINE_BUFFER_SIZE - 1; NvBool bResolvePtrVal = NV_FALSE; + NvBool bFixedString = NV_FALSE; for (;;) { @@ -515,24 +531,52 @@ static int libos_printf_a( cnt += l; } -# if defined(NVRM) if (logDecode->curLineBufPtr == logDecode->lineBuffer) { - // Prefix every line with NVRM GPUn Ucode-task: filename(lineNumber): - snprintf( - logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, - "NVRM GPU%u %s-%s: %s(%u): ", pRec->log->gpuInstance, + size_t remain = LIBOS_LOG_LINE_BUFFER_SIZE - 1; + int len; + +# if defined(NVRM) + // Prefix every line with NVRM: GPUn Ucode-task: filename(lineNumber): + len = snprintf( + logDecode->curLineBufPtr, remain, + NV_PRINTF_ADD_PREFIX("GPU%u %s-%s: %s(%u): "), pRec->log->gpuInstance, logDecode->sourceName, pRec->log->taskPrefix, filename, pRec->meta->lineNumber); - logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); - } + if (len < 0) + { + return -1; + } + if ((size_t)len >= remain) + { + // Truncated. + remain = 0; + logDecode->curLineBufPtr = line_buffer_end; + } + else + { + remain -= len; + logDecode->curLineBufPtr += len; + } # else - if (logDecode->curLineBufPtr == logDecode->lineBuffer) - { - // Prefix every line with GPUn Ucode-task: filename(lineNumber): - snprintf( - logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, + // Prefix every line with T:nnnn GPUn Ucode-task: filename(lineNumber): + len = snprintf( + logDecode->curLineBufPtr, remain, "T:%llu ", pRec->timeStamp); - logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); + if (len < 0) + { + return -1; + } + if ((size_t)len >= remain) + { + // Truncated. + remain = 0; + logDecode->curLineBufPtr = line_buffer_end; + } + else + { + remain -= len; + logDecode->curLineBufPtr += len; + } #if defined(NVSYM_STANDALONE) { @@ -548,7 +592,7 @@ static int libos_printf_a( #endif if (err == 0) { - snprintf(logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, + len = snprintf(logDecode->curLineBufPtr, remain, "%04d-%02d-%02d %d:%02d:%02d ", tmStruct.tm_year + 1900, // years since 1900 tmStruct.tm_mon + 1, // months since January - [0,11] @@ -556,28 +600,128 @@ static int libos_printf_a( tmStruct.tm_hour, // hours since midnight - [0,23] tmStruct.tm_min, // minutes after the hour - [0,59] tmStruct.tm_sec); // seconds after the minute - [0,59] - logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); + if (len < 0) + { + return -1; + } + if ((size_t)len >= remain) + { + // Truncated. + remain = 0; + logDecode->curLineBufPtr = line_buffer_end; + } + else + { + remain -= len; + logDecode->curLineBufPtr += len; + } } } #endif - snprintf( - logDecode->curLineBufPtr, LIBOS_LOG_LINE_BUFFER_SIZE - 1, + len = snprintf( + logDecode->curLineBufPtr, remain, "GPU%u%s%s-%s: %s(%u): ", pRec->log->gpuInstance, printfLevelToString(pRec->meta->printLevel), logDecode->sourceName, pRec->log->taskPrefix, filename, pRec->meta->lineNumber); - logDecode->curLineBufPtr += portStringLength(logDecode->curLineBufPtr); - } + if (len < 0) + { + return -1; + } + if ((size_t)len >= remain) + { + // Truncated. + remain = 0; + logDecode->curLineBufPtr = line_buffer_end; + } + else + { + remain -= len; + logDecode->curLineBufPtr += len; + } # endif + len = 0; + switch (pRec->meta->specialType) + { + case RM_GSP_LOG_SPECIAL_NONE: + break; + case RM_GSP_LOG_SPECIAL_ASSERT_FAILED: + // Add "Assertion failed: " prefix, and interpret the "format" + // as a fixed string. + len = snprintf( + logDecode->curLineBufPtr, remain, + "Assertion failed: "); + bFixedString = NV_TRUE; + break; + case RM_GSP_LOG_SPECIAL_ASSERT_OK_FAILED: + { + // Add "Assertion failed: (0xNN) returned from " + // prefix, and interpret the "format" as a fixed string. + NV_STATUS status; + if (arg_index >= arg_count) + { + return 0; + } + status = args[arg_index++]; + len = snprintf( + logDecode->curLineBufPtr, remain, + "Assertion failed: %s (0x%08X) returned from ", + nvstatusToString(status), status); + bFixedString = NV_TRUE; + break; + } + case RM_GSP_LOG_SPECIAL_CHECK_FAILED: + // Add "Check failed: " prefix, and interpret the "format" + // as a fixed string. + len = snprintf( + logDecode->curLineBufPtr, remain, + "Check failed: "); + bFixedString = NV_TRUE; + break; + case RM_GSP_LOG_SPECIAL_CHECK_OK_FAILED: + { + // Add "Check failed: (0xNN) returned from " + // prefix, and interpret the "format" as a fixed string. + NV_STATUS status; + if (arg_index >= arg_count) + { + return 0; + } + status = args[arg_index++]; + len = snprintf( + logDecode->curLineBufPtr, remain, + "Check failed: %s (0x%08X) returned from ", + nvstatusToString(status), status); + bFixedString = NV_TRUE; + break; + } + } + if (len < 0) + { + return -1; + } + if ((size_t)len >= remain) + { + // Truncated. + remain = 0; + logDecode->curLineBufPtr = line_buffer_end; + } + else + { + remain -= len; + logDecode->curLineBufPtr += len; + } + } + /* Handle literal text and %% format specifiers */ for (; *s; s++) { if (logDecode->curLineBufPtr >= line_buffer_end) flush_line_buffer(logDecode); - if (*s == '%') + if (!bFixedString && (*s == '%')) { if (s[1] == '%') s++; @@ -1237,6 +1381,7 @@ static NvBool libosCopyLogToNvlog_nowrap(LIBOS_LOG_DECODE_LOG *pLog) portMemCopy(pDst, len, pSrc, len); pNvLogBuffer->pos = putOffset + pLog->preservedNoWrapPos; // TODO: usage of NVLOG_BUFFER::pos is sus here, reconsider? *(NvU64 *)(pNoWrapBuf->data) = putCopy + pLog->preservedNoWrapPos / sizeof(NvU64); + return NV_TRUE; } @@ -1250,7 +1395,7 @@ static NvBool libosCopyLogToNvlog_wrap(LIBOS_LOG_DECODE_LOG *pLog) NvU64 putOffset = putCopy * sizeof(NvU64) + sizeof(NvU64); portMemCopy(pWrapBuf->data, pLog->logBufferSize, (void *)pLog->physicLogBuffer, pLog->logBufferSize); - pNvLogBuffer->pos = putOffset; // TODO: usage of NVLOG_BUFFER::pos is sus here, reconsider? + pNvLogBuffer->pos = NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) + putOffset; return NV_TRUE; } @@ -1350,27 +1495,16 @@ static void libosLogCreateExGeneric(LIBOS_LOG_DECODE *logDecode, const char *pSo portStringCopy(logDecode->sourceName, sizeof(logDecode->sourceName), pSourceName, sizeof(logDecode->sourceName)); } -#if defined(NVSYM_STANDALONE) && !defined(PROTODMP_BUILD) -void libosLogCreate(LIBOS_LOG_DECODE *logDecode, FILE *fout) +#if defined(LIBOS_LOG_OFFLINE_DECODER) +void libosLogCreate(LIBOS_LOG_DECODE *logDecode, LogPrinter *pLogPrinter) { libosLogCreateGeneric(logDecode); - logDecode->fout = fout; + logDecode->pLogPrinter = pLogPrinter; } -void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName, FILE *fout) +void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName, LogPrinter *pLogPrinter) { libosLogCreateExGeneric(logDecode, pSourceName); - logDecode->fout = fout; -} -#elif defined(NVWATCH) -void libosLogCreate(LIBOS_LOG_DECODE *logDecode, char *dest) -{ - libosLogCreateGeneric(logDecode); - logDecode->dest = dest; -} -void libosLogCreateEx(LIBOS_LOG_DECODE *logDecode, const char *pSourceName, char *dest) -{ - libosLogCreateExGeneric(logDecode, pSourceName); - logDecode->dest = dest; + logDecode->pLogPrinter = pLogPrinter; } #else void libosLogCreate(LIBOS_LOG_DECODE *logDecode) @@ -1443,7 +1577,7 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz if (!bFoundPreserved) { status = nvlogAllocBuffer( - bufferSize + NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data), libosNoWrapBufferFlags, + LIBOS_LOG_NVLOG_BUFFER_SIZE(bufferSize), libosNoWrapBufferFlags, tag, &pLog->hNvLogNoWrap); @@ -1461,6 +1595,7 @@ void libosLogAddLogEx(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSiz NvLogLogger.pBuffers[pLog->hNvLogNoWrap]->pos = sizeof(NvU64); // offset to account for put pointer pLog->bNvLogNoWrap = NV_TRUE; + } else { diff --git a/src/nvidia-modeset/Makefile b/src/nvidia-modeset/Makefile index 6246bb59d1..66edbf4e84 100644 --- a/src/nvidia-modeset/Makefile +++ b/src/nvidia-modeset/Makefile @@ -98,6 +98,13 @@ ifeq ($(TARGET_ARCH),aarch64) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics) endif +ifeq ($(TARGET_ARCH),riscv64) + CFLAGS += -march=rv64imac_zicsr_zifencei + CFLAGS += -mabi=lp64 + CFLAGS += -mcmodel=medany + CFLAGS += -mno-relax +endif + CFLAGS += -fno-pic CFLAGS += -fno-common CFLAGS += -fomit-frame-pointer diff --git a/src/nvidia-modeset/include/nvkms-evo.h b/src/nvidia-modeset/include/nvkms-evo.h index e3f8a405ab..486b6ed944 100644 --- a/src/nvidia-modeset/include/nvkms-evo.h +++ b/src/nvidia-modeset/include/nvkms-evo.h @@ -188,6 +188,8 @@ NvBool nvDowngradeColorSpaceAndBpc( NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, const NvBool b2Heads1Or, NVDscInfoEvoRec *pDscInfo, const struct NvKmsModeValidationParams *pParams); @@ -402,6 +404,10 @@ NvBool nvEvoUse2Heads1OR(const NVDpyEvoRec *pDpyEvo, NvU32 nvGetRefreshRate10kHz(const NVHwModeTimingsEvo *pTimings); +NvBool nvIsLockGroupFlipLocked(const NVLockGroup *pLockGroup); + +NvBool nvEvoIsConsoleActive(const NVDevEvoRec *pDevEvo); + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-hdmi.h b/src/nvidia-modeset/include/nvkms-hdmi.h index 674d0cbafe..2cd8303fcf 100644 --- a/src/nvidia-modeset/include/nvkms-hdmi.h +++ b/src/nvidia-modeset/include/nvkms-hdmi.h @@ -38,7 +38,7 @@ void nvUpdateHdmiInfoFrames(const NVDispEvoRec *pDispEvo, void nvDpyUpdateHdmiPreModesetEvo(NVDpyEvoPtr pDpyEvo); void nvDpyUpdateHdmiVRRCaps(NVDpyEvoPtr pDpyEvo); -void nvUpdateHdmiCaps(NVDpyEvoPtr pDpyEvo); +void nvSendHdmiCapsToRm(NVDpyEvoPtr pDpyEvo); void nvLogEdidCea861InfoEvo(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString); diff --git a/src/nvidia-modeset/include/nvkms-rm.h b/src/nvidia-modeset/include/nvkms-rm.h index 0178fc5d28..ef09bcbad0 100644 --- a/src/nvidia-modeset/include/nvkms-rm.h +++ b/src/nvidia-modeset/include/nvkms-rm.h @@ -28,10 +28,14 @@ extern "C" { #endif +#include #include "nvkms-types.h" #include /* NV0092_REGISTER_RG_LINE_CALLBACK_FN */ #include /* OSVBLANKCALLBACKPROC */ +#define NVKMS_RM_HANDLE_SPACE_DEVICE(_i) ((_i) + 1) +#define NVKMS_RM_HANDLE_SPACE_FRAMELOCK(_i) (NV_MAX_DEVICES + (_i) + 1) + NvBool nvWriteDPCDReg(NVConnectorEvoPtr pConnectorEvo, NvU32 dpcdAddr, NvU8 dpcdData); diff --git a/src/nvidia-modeset/include/nvkms-surface.h b/src/nvidia-modeset/include/nvkms-surface.h index a6160dc9d2..6de358f67d 100644 --- a/src/nvidia-modeset/include/nvkms-surface.h +++ b/src/nvidia-modeset/include/nvkms-surface.h @@ -72,6 +72,22 @@ void nvEvoUnregisterDeferredRequestFifo( NVDevEvoPtr pDevEvo, NVDeferredRequestFifoRec *pDeferredRequestFifo); +NVVblankSemControl *nvEvoEnableVblankSemControl( + NVDevEvoRec *pDevEvo, + NVDispEvoRec *pDispEvo, + NvU32 hwHead, + NVSurfaceEvoRec *pSurfaceEvo, + NvU64 surfaceOffset); + +NvBool nvEvoDisableVblankSemControl( + NVDevEvoRec *pDevEvo, + NVVblankSemControl *pVblankSemControl); + +NvBool nvEvoAccelVblankSemControls( + NVDevEvoPtr pDevEvo, + NvU32 dispIndex, + NvU32 hwHeadMask); + static inline NvBool nvEvoIsSurfaceOwner(const NVSurfaceEvoRec *pSurfaceEvo, const struct NvKmsPerOpenDev *pOpenDev, NvKmsSurfaceHandle surfaceHandle) diff --git a/src/nvidia-modeset/include/nvkms-types.h b/src/nvidia-modeset/include/nvkms-types.h index 6291b2813e..1b190176cb 100644 --- a/src/nvidia-modeset/include/nvkms-types.h +++ b/src/nvidia-modeset/include/nvkms-types.h @@ -151,6 +151,7 @@ typedef struct _NVDeferredRequestFifoRec *NVDeferredRequestFifoPtr; typedef struct _NVSwapGroupRec *NVSwapGroupPtr; typedef struct _NVEvoModesetUpdateState NVEvoModesetUpdateState; typedef struct _NVLockGroup NVLockGroup; +typedef struct _NVVblankSemControl *NVVblankSemControlPtr; /* * _NVHs*EvoRec are defined in nvkms-headsurface-priv.h; they are intentionally @@ -882,7 +883,6 @@ typedef struct { NvBool supportsHDMI20 :1; NvBool inputLutAppliesToBase :1; NvU8 validNIsoFormatMask; - NvU8 genericPageKind; NvU32 maxPitchValue; int maxWidthInBytes; int maxWidthInPixels; @@ -1128,6 +1128,12 @@ typedef struct _NVEvoDevRec { */ NvBool isHeadSurfaceSupported : 1; + /* + * vblank Sem Control requires support in resman; that support is not + * currently available on Tegra. + */ + NvBool supportsVblankSemControl : 1; + nvkms_timer_handle_t *postFlipIMPTimer; nvkms_timer_handle_t *consoleRestoreTimer; @@ -1266,29 +1272,6 @@ typedef struct _NVEvoDevRec { } apiHead[NVKMS_MAX_HEADS_PER_DISP]; } NVDevEvoRec; -static inline NvBool nvEvoIsConsoleActive(const NVDevEvoRec *pDevEvo) -{ - /* - * If (pDevEvo->modesetOwner == NULL) that means either the vbios - * console or the NVKMS console might be active. - */ - if (pDevEvo->modesetOwner == NULL) { - return TRUE; - } - - /* - * If (pDevEvo->modesetOwner != NULL) but - * pDevEvo->modesetOwnerChanged is TRUE, that means the modeset - * ownership is grabbed by the external client but it hasn't - * performed any modeset and the console is still active. - */ - if ((pDevEvo->modesetOwner != NULL) && pDevEvo->modesetOwnerChanged) { - return TRUE; - } - - return FALSE; -} - /* * The NVHwModeTimingsEvo structure stores all the values necessary to * perform a modeset with EVO @@ -2535,6 +2518,8 @@ typedef struct _NVFrameLockEvo { enum NvKmsFrameLockAttributeMulDivModeValue mulDivMode; NvBool testMode; + NVUnixRmHandleAllocatorRec handleAllocator; + } NVFrameLockEvoRec; /*! @@ -3185,6 +3170,13 @@ static inline void nvAssignHwHeadsMaskApiHeadState( nvPopCount32(hwHeadsMask); } +typedef struct _NVVblankSemControl { + NvU32 dispIndex; + NvU32 hwHead; + NvU64 surfaceOffset; + NVSurfaceEvoRec *pSurfaceEvo; +} NVVblankSemControl; + #ifdef __cplusplus }; #endif diff --git a/src/nvidia-modeset/include/nvkms-utils.h b/src/nvidia-modeset/include/nvkms-utils.h index b75f88f0ce..f0d3a3fd23 100644 --- a/src/nvidia-modeset/include/nvkms-utils.h +++ b/src/nvidia-modeset/include/nvkms-utils.h @@ -55,6 +55,11 @@ static inline NvBool A_plus_B_greater_than_C_U16(NvU16 a, NvU16 b, NvU16 c) return (NV_U16_MAX - a < b) || ((a + b) > c); } +static inline NvBool A_plus_B_greater_than_C_U64(NvU64 a, NvU64 b, NvU64 c) +{ + return (NV_U64_MAX - a < b) || ((a + b) > c); +} + static inline NvS32 clamp_S32(NvS32 val, NvS32 lo, NvS32 hi) { if (val < lo) { diff --git a/src/nvidia-modeset/interface/nvkms-api-types.h b/src/nvidia-modeset/interface/nvkms-api-types.h index f56195c193..686599c615 100644 --- a/src/nvidia-modeset/interface/nvkms-api-types.h +++ b/src/nvidia-modeset/interface/nvkms-api-types.h @@ -58,6 +58,7 @@ typedef NvU32 NvKmsFrameLockHandle; typedef NvU32 NvKmsDeferredRequestFifoHandle; typedef NvU32 NvKmsSwapGroupHandle; typedef NvU32 NvKmsVblankSyncObjectHandle; +typedef NvU32 NvKmsVblankSemControlHandle; struct NvKmsSize { NvU16 width; diff --git a/src/nvidia-modeset/interface/nvkms-api.h b/src/nvidia-modeset/interface/nvkms-api.h index 99da27e79b..8a776db3ce 100644 --- a/src/nvidia-modeset/interface/nvkms-api.h +++ b/src/nvidia-modeset/interface/nvkms-api.h @@ -268,6 +268,9 @@ enum NvKmsIoctlCommand { NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT, NVKMS_IOCTL_NOTIFY_VBLANK, NVKMS_IOCTL_SET_FLIPLOCK_GROUP, + NVKMS_IOCTL_ENABLE_VBLANK_SEM_CONTROL, + NVKMS_IOCTL_DISABLE_VBLANK_SEM_CONTROL, + NVKMS_IOCTL_ACCEL_VBLANK_SEM_CONTROLS, }; @@ -1121,12 +1124,6 @@ struct NvKmsAllocDeviceReply { NvU32 maxHeightInPixels; NvU32 maxCursorSize; - /*! - * The page kind used by the GPU's MMU for uncompressed block-linear color - * formats. - */ - NvU8 genericPageKind; - /*! * Describes the supported Color Key selects and blending modes for match * and nomatch cursor pixels. @@ -1180,6 +1177,18 @@ struct NvKmsAllocDeviceReply { * generator sync objects that signal at vblank. */ NvBool supportsVblankSyncObjects; + + /*! + * 'supportsVblankSemControl' indicates whether the VBlank Semaphore Control + * interface: + * + * NVKMS_IOCTL_ENABLE_VBLANK_SEM_CONTROL, + * NVKMS_IOCTL_DISABLE_VBLANK_SEM_CONTROL, + * NVKMS_IOCTL_ACCEL_VBLANK_SEM_CONTROLS, + * + * is supported. + */ + NvBool supportsVblankSemControl; }; struct NvKmsAllocDeviceParams { @@ -2739,7 +2748,6 @@ enum NvKmsDispAttribute { NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_TEST_SIGNAL, NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_RESET, NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_SET_SWAP_BARRIER, - NV_KMS_DISP_ATTRIBUTE_ALLOW_FLIPLOCK, NV_KMS_DISP_ATTRIBUTE_QUERY_DP_AUX_LOG, }; @@ -4079,4 +4087,79 @@ struct NvKmsSetFlipLockGroupParams { struct NvKmsSetFlipLockGroupReply reply; /*! out */ }; +/* + * NVKMS_IOCTL_ENABLE_VBLANK_SEM_CONTROL + * NVKMS_IOCTL_DISABLE_VBLANK_SEM_CONTROL + * NVKMS_IOCTL_ACCEL_VBLANK_SEM_CONTROLS + * + * Enable or disable vblank semaphore control for the given head using the + * specified surface and surface offset. The memory at that location is + * interpreted as an NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA. See the + * RMAPI documentation for NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA for + * details of the semantics of that interface. + * + * It is the responsibility of the nvkms client(s) to coordinate at modeset + * time: the mapping of nvkms apiHeads to underlying hwHeads may change during a + * modeset, such that a registered vblank sem control will no longer receive + * vblank callbacks if the head is shutdown. Before a modeset shuts down a + * head, nvkms clients should ensure that all in-flight semaphore acquires are + * satisfied, and then after the modeset the vblank sem controls should be + * re-enabled. + * + * NVKMS_IOCTL_ACCEL_VBLANK_SEM_CONTROLS can be used, specifying a particular + * set of heads, to set all vblank sem controls on those heads to have their + * semaphore set to the value in their respective + * NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA::requestCounterAccel fields. + * + * These ioctls are only available when + * NvKmsAllocDeviceReply::supportsVblankSemControl is true. + */ + +struct NvKmsEnableVblankSemControlRequest { + NvKmsDeviceHandle deviceHandle; + NvKmsDispHandle dispHandle; + NvU32 head; + NvKmsSurfaceHandle surfaceHandle; + NvU64 surfaceOffset NV_ALIGN_BYTES(8); +}; + +struct NvKmsEnableVblankSemControlReply { + NvKmsVblankSemControlHandle vblankSemControlHandle; +}; + +struct NvKmsEnableVblankSemControlParams { + struct NvKmsEnableVblankSemControlRequest request; + struct NvKmsEnableVblankSemControlReply reply; +}; + +struct NvKmsDisableVblankSemControlRequest { + NvKmsDeviceHandle deviceHandle; + NvKmsDispHandle dispHandle; + NvKmsVblankSemControlHandle vblankSemControlHandle; +}; + +struct NvKmsDisableVblankSemControlReply { + NvU32 padding; +}; + +struct NvKmsDisableVblankSemControlParams { + struct NvKmsDisableVblankSemControlRequest request; + struct NvKmsDisableVblankSemControlReply reply; +}; + +struct NvKmsAccelVblankSemControlsRequest { + NvKmsDeviceHandle deviceHandle; + NvKmsDispHandle dispHandle; + NvU32 headMask; +}; + +struct NvKmsAccelVblankSemControlsReply { + NvU32 padding; +}; + +struct NvKmsAccelVblankSemControlsParams { + struct NvKmsAccelVblankSemControlsRequest request; + struct NvKmsAccelVblankSemControlsReply reply; +}; + #endif /* NVKMS_API_H */ diff --git a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h index c487b4b786..f31f68101c 100644 --- a/src/nvidia-modeset/kapi/interface/nvkms-kapi.h +++ b/src/nvidia-modeset/kapi/interface/nvkms-kapi.h @@ -490,6 +490,8 @@ typedef enum NvKmsKapiRegisterWaiterResultRec { NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED, } NvKmsKapiRegisterWaiterResult; +typedef void NvKmsKapiSuspendResumeCallbackFunc(NvBool suspend); + struct NvKmsKapiFunctionsTable { /*! @@ -1399,6 +1401,15 @@ struct NvKmsKapiFunctionsTable { NvU64 index, NvU64 new_value ); + + /*! + * Set the callback function for suspending and resuming the display system. + */ + void + (*setSuspendResumeCallback) + ( + NvKmsKapiSuspendResumeCallbackFunc *function + ); }; /** @} */ diff --git a/src/nvidia-modeset/kapi/src/nvkms-kapi.c b/src/nvidia-modeset/kapi/src/nvkms-kapi.c index cc2d7fe851..d7d5a761e8 100644 --- a/src/nvidia-modeset/kapi/src/nvkms-kapi.c +++ b/src/nvidia-modeset/kapi/src/nvkms-kapi.c @@ -383,9 +383,6 @@ static NvBool KmsAllocateDevice(struct NvKmsKapiDevice *device) device->caps.maxHeightInPixels = paramsAlloc->reply.maxHeightInPixels; device->caps.maxCursorSizeInPixels = paramsAlloc->reply.maxCursorSize; device->caps.requiresVrrSemaphores = paramsAlloc->reply.requiresVrrSemaphores; - /* The generic page kind was determined during RM device allocation, - * but it should match what NVKMS reports */ - nvAssert(device->caps.genericPageKind == paramsAlloc->reply.genericPageKind); /* XXX Add LUT support */ @@ -3436,6 +3433,30 @@ static NvBool GetCRC32 return NV_TRUE; } +static NvKmsKapiSuspendResumeCallbackFunc *pSuspendResumeFunc; + +void nvKmsKapiSuspendResume +( + NvBool suspend +) +{ + if (pSuspendResumeFunc) { + pSuspendResumeFunc(suspend); + } +} + +static void nvKmsKapiSetSuspendResumeCallback +( + NvKmsKapiSuspendResumeCallbackFunc *function +) +{ + if (pSuspendResumeFunc && function) { + nvKmsKapiLogDebug("Kapi suspend/resume callback function already registered"); + } + + pSuspendResumeFunc = function; +} + NvBool nvKmsKapiGetFunctionsTableInternal ( struct NvKmsKapiFunctionsTable *funcsTable @@ -3514,6 +3535,7 @@ NvBool nvKmsKapiGetFunctionsTableInternal nvKmsKapiUnregisterSemaphoreSurfaceCallback; funcsTable->setSemaphoreSurfaceValue = nvKmsKapiSetSemaphoreSurfaceValue; + funcsTable->setSuspendResumeCallback = nvKmsKapiSetSuspendResumeCallback; return NV_TRUE; } diff --git a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h index 9f1a2f5428..af8d501417 100644 --- a/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h +++ b/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h @@ -100,6 +100,8 @@ NvBool nvkms_output_rounding_fix(void); NvBool nvkms_disable_hdmi_frl(void); NvBool nvkms_disable_vrr_memclk_switch(void); NvBool nvkms_hdmi_deepcolor(void); +NvBool nvkms_vblank_sem_control(void); +NvBool nvkms_opportunistic_display_sync(void); void nvkms_call_rm (void *ops); void* nvkms_alloc (size_t size, diff --git a/src/nvidia-modeset/os-interface/include/nvkms.h b/src/nvidia-modeset/os-interface/include/nvkms.h index b64fbb098e..25e4923b63 100644 --- a/src/nvidia-modeset/os-interface/include/nvkms.h +++ b/src/nvidia-modeset/os-interface/include/nvkms.h @@ -103,6 +103,8 @@ NvBool nvKmsKapiGetFunctionsTableInternal struct NvKmsKapiFunctionsTable *funcsTable ); +void nvKmsKapiSuspendResume(NvBool suspend); + NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness); NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness); diff --git a/src/nvidia-modeset/src/nvkms-difr.c b/src/nvidia-modeset/src/nvkms-difr.c index 0993e13dc2..070f010fc9 100644 --- a/src/nvidia-modeset/src/nvkms-difr.c +++ b/src/nvidia-modeset/src/nvkms-difr.c @@ -95,6 +95,7 @@ #include "nvkms-rm.h" #include "nvkms-rmapi.h" #include "nvkms-utils.h" +#include "nvkms-evo.h" #include "nvidia-push-init.h" #include "nvidia-push-methods.h" @@ -275,11 +276,23 @@ NvU32 nvDIFRPrefetchSurfaces(NVDIFRStateEvoPtr pDifr, size_t l2CacheSize) NvU32 status; /* - * If DIFR is disabled it's because we know we were or will be flipping, or - * if console is active then the scanout surfaces will get updated by the - * OS console driver without any knowledge of NVKMS. + * If the console is active then the scanout surfaces will get updated by + * the OS console driver without any knowledge of NVKMS, DIFR should not be + * enabled in that case. */ - if (pDifr->hwDisabled || nvEvoIsConsoleActive(pDevEvo)) { + if (nvEvoIsConsoleActive(pDevEvo)) { + /* + * NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE: Despite + * what the name suggests this will actually tell RM (and further PMU) + * to disable DIFR until the next modeset. + */ + return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_INSUFFICIENT_L2_SIZE; + } + + /* + * If DIFR is disabled it's because we know we were or will be flipping. + */ + if (pDifr->hwDisabled) { return NV2080_CTRL_LPWR_DIFR_PREFETCH_FAIL_OS_FLIPS_ENABLED; } @@ -845,8 +858,17 @@ static void IdleTimerProc(void *dataPtr, NvU32 dataU32) pDifr->idleTimer = NULL; if (now - pDifr->lastFlipTime >= idlePeriod) { - /* Enough time has passed with no new flips, enable DIFR. */ - SetDisabledState(pDifr, FALSE); + /* + * Enough time has passed with no new flips, enable DIFR if the console + * is not active. If the console is active then the scanout surfaces + * will get updated by the OS console driver without any knowledge of + * NVKMS, DIFR can not be enabled in that case; the idle timer will get + * scheduled by nvDIFRNotifyFlip() on next modeset/flip, till then DIFR + * will remain disabled. + */ + if (!nvEvoIsConsoleActive(pDifr->pDevEvo)) { + SetDisabledState(pDifr, FALSE); + } } else { /* New flips have happened since the original, reset idle timer. */ EnsureIdleTimer(pDifr); diff --git a/src/nvidia-modeset/src/nvkms-dpy.c b/src/nvidia-modeset/src/nvkms-dpy.c index aa3fe3b868..d6bd98b486 100644 --- a/src/nvidia-modeset/src/nvkms-dpy.c +++ b/src/nvidia-modeset/src/nvkms-dpy.c @@ -71,7 +71,7 @@ static NvBool ValidateEdid (const NVDpyEvoRec *pDpyEvo, const NvBool ignoreEdidChecksum); static void LogEdid (NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString); -static void ClearEdid (NVDpyEvoPtr pDpyEvo); +static void ClearEdid (NVDpyEvoPtr pDpyEvo, const NvBool bSendHdmiCapsToRm); static void ClearCustomEdid (const NVDpyEvoRec *pDpyEvo); static void WriteEdidToResman (const NVDpyEvoRec *pDpyEvo, const NVEdidRec *pEdid); @@ -90,14 +90,14 @@ static void AssignDpyEvoName (NVDpyEvoPtr pDpyEvo); static NvBool IsConnectorTMDS (NVConnectorEvoPtr); -static void DpyDisconnectEvo(NVDpyEvoPtr pDpyEvo) +static void DpyDisconnectEvo(NVDpyEvoPtr pDpyEvo, const NvBool bSendHdmiCapsToRm) { NVDispEvoPtr pDispEvo = pDpyEvo->pDispEvo; pDispEvo->connectedDisplays = nvDpyIdListMinusDpyId(pDispEvo->connectedDisplays, pDpyEvo->id); - ClearEdid(pDpyEvo); + ClearEdid(pDpyEvo, bSendHdmiCapsToRm); } static NvBool DpyConnectEvo( @@ -353,6 +353,7 @@ static void ApplyNewEdid( NVDpyEvoPtr pDpyEvo, const NVEdidRec *pEdid, const NVParsedEdidEvoRec *pParsedEdid, + const NvBool bSendHdmiCapsToRm, NVEvoInfoStringPtr pInfoString) { if (pDpyEvo->edid.buffer != NULL) { @@ -394,7 +395,9 @@ static void ApplyNewEdid( DpyAssignColorSpaceCaps(pDpyEvo, pInfoString); } - nvUpdateHdmiCaps(pDpyEvo); + if (bSendHdmiCapsToRm) { + nvSendHdmiCapsToRm(pDpyEvo); + } nvDpyProbeMaxPixelClock(pDpyEvo); @@ -656,7 +659,8 @@ static void ReadAndApplyEdidEvo( * worrying that this request has different parameters (like CustomEdid * or mode validation overrides). */ - ApplyNewEdid(pDpyEvo, &edid, pParsedEdid, &infoString); + ApplyNewEdid(pDpyEvo, &edid, pParsedEdid, TRUE /* bSendHdmiCapsToRm */, + &infoString); } else { nvFree(edid.buffer); } @@ -1917,14 +1921,15 @@ static void LogEdid(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString) * structure. */ -static void ClearEdid(NVDpyEvoPtr pDpyEvo) +static void ClearEdid(NVDpyEvoPtr pDpyEvo, const NvBool bSendHdmiCapsToRm) { NVEdidRec edid = { }; NVEvoInfoStringRec infoString; nvInitInfoString(&infoString, NULL, 0); if (EdidHasChanged(pDpyEvo, &edid, NULL)) { - ApplyNewEdid(pDpyEvo, &edid, NULL, &infoString); + ApplyNewEdid(pDpyEvo, &edid, NULL, + bSendHdmiCapsToRm, &infoString); } } @@ -2358,7 +2363,7 @@ void nvFreeDpyEvo(NVDispEvoPtr pDispEvo, NVDpyEvoPtr pDpyEvo) { nvCancelSDRTransitionTimer(pDpyEvo); - DpyDisconnectEvo(pDpyEvo); + DpyDisconnectEvo(pDpyEvo, FALSE /* bSendHdmiCapsToRm */); // Let the DP library host implementation handle deleting a pDpy as if the // library had notified it of a lost device. @@ -2952,7 +2957,7 @@ NvBool nvDpyGetDynamicData( return FALSE; } } else { - DpyDisconnectEvo(pDpyEvo); + DpyDisconnectEvo(pDpyEvo, TRUE /* bSendHdmiCapsToRm */); } if (nvConnectorUsesDPLib(pConnectorEvo)) { diff --git a/src/nvidia-modeset/src/nvkms-evo.c b/src/nvidia-modeset/src/nvkms-evo.c index 75f48b948f..caeaee9576 100644 --- a/src/nvidia-modeset/src/nvkms-evo.c +++ b/src/nvidia-modeset/src/nvkms-evo.c @@ -1837,8 +1837,11 @@ static NvBool ProhibitLockIfNecessary(NVDispEvoRec *pDispEvo) /* + * Prohibit locking if necessary for the active configuration. + * * Set up rasterlock between heads on a single GPU, if certain conditions are met: * - Locking is not prohibited due to the active configuration + * - Opportunistic display sync is not disabled via kernel module parameter * - All active heads have identical mode timings * * Set pDispEvo->pRasterLockPossible to indicate whether rasterlock is possible @@ -1866,7 +1869,12 @@ static void FinishModesetOneDisp( pDispEvo->rasterLockPossible = FALSE; if (ProhibitLockIfNecessary(pDispEvo)) { - /* If locking is prohibited, do not attempt to lock heads. */ + /* If all locking is prohibited, do not attempt rasterlock. */ + return; + } + + if (!nvkms_opportunistic_display_sync()) { + /* If opportunistic display sync is disabled, do not attempt rasterlock. */ return; } @@ -6663,35 +6671,41 @@ static NvBool GetDfpProtocol(const NVDpyEvoRec *pDpyEvo, if (nvDpyIsHdmiEvo(pDpyEvo) && /* If we don't require boot clocks... */ ((overrides & NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS) == 0) && - /* If FRL is supported, use it for 10 BPC if needed. */ - ((nvHdmiDpySupportsFrl(pDpyEvo) && - nvDpyIsHdmiDepth30Evo(pDpyEvo) && + /* If FRL is supported... */ + nvHdmiDpySupportsFrl(pDpyEvo) && + /* Use FRL for 10 BPC if needed. */ + ((nvDpyIsHdmiDepth30Evo(pDpyEvo) && nvHdmiTimingsNeedFrl(pDpyEvo, pTimings, HDMI_BPC10)) || - /* Fall back to 8 BPC, use FRL if needed. */ + /* Use FRL for 8 BPC if needed. */ nvHdmiTimingsNeedFrl(pDpyEvo, pTimings, HDMI_BPC8))) { - /* If FRL is needed for 8 BPC, but not supported, fail. */ - if (!nvHdmiDpySupportsFrl(pDpyEvo)) { - return FALSE; - } - nvAssert(nvDpyIsHdmiEvo(pDpyEvo)); nvAssert(rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A || rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B); timingsProtocol = NVKMS_PROTOCOL_SOR_HDMI_FRL; } else { + /* If HDMI FRL is needed for 8 BPC, but not supported, fail. */ + if (nvDpyIsHdmiEvo(pDpyEvo) && + nvHdmiTimingsNeedFrl(pDpyEvo, pTimings, HDMI_BPC8) && + ((overrides & NVKMS_MODE_VALIDATION_NO_MAX_PCLK_CHECK) == 0)) { + nvAssert(!nvHdmiDpySupportsFrl(pDpyEvo)); + return FALSE; + } + switch (rmProtocol) { default: nvAssert(!"unrecognized SOR RM protocol"); return FALSE; case NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A: - if (nvDpyRequiresDualLinkEvo(pDpyEvo, pTimings)) { + if (nvDpyRequiresDualLinkEvo(pDpyEvo, pTimings) && + ((overrides & NVKMS_MODE_VALIDATION_NO_MAX_PCLK_CHECK) == 0)) { return FALSE; } timingsProtocol = NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A; break; case NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B: - if (nvDpyRequiresDualLinkEvo(pDpyEvo, pTimings)) { + if (nvDpyRequiresDualLinkEvo(pDpyEvo, pTimings) && + ((overrides & NVKMS_MODE_VALIDATION_NO_MAX_PCLK_CHECK) == 0)) { return FALSE; } timingsProtocol = NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B; @@ -6874,13 +6888,15 @@ NvBool nvDowngradeColorSpaceAndBpc( NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, NVHwModeTimingsEvoPtr pTimings, + enum NvKmsDpyAttributeCurrentColorSpaceValue *pColorSpace, + enum NvKmsDpyAttributeColorBpcValue *pColorBpc, const NvBool b2Heads1Or, NVDscInfoEvoRec *pDscInfo, const struct NvKmsModeValidationParams *pParams) { NVConnectorEvoPtr pConnectorEvo = pDpyEvo->pConnectorEvo; - enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; - enum NvKmsDpyAttributeColorBpcValue colorBpc; + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace = *pColorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc = *pColorBpc; enum NvKmsDpyAttributeColorRangeValue colorRange; const NVColorFormatInfoRec supportedColorFormats = nvGetColorFormatInfo(pDpyEvo); @@ -6895,14 +6911,6 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, return TRUE; } - if (pTimings->yuv420Mode != NV_YUV420_MODE_NONE) { - colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; - colorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; - } else if (!nvGetDefaultColorSpace(&supportedColorFormats, &colorSpace, - &colorBpc)) { - return FALSE; - } - if (colorSpace != NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) { colorRange = NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED; } else { @@ -6928,6 +6936,8 @@ NvBool nvDPValidateModeEvo(NVDpyEvoPtr pDpyEvo, return FALSE; } + *pColorSpace = colorSpace; + *pColorBpc = colorBpc; return TRUE; } @@ -9405,6 +9415,7 @@ void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo, pHC->serverLock = NV_EVO_RASTER_LOCK; pHC->serverLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); pHC->setLockOffsetX = TRUE; + pHC->crashLockUnstallMode = FALSE; } else { pHC->clientLock = NV_EVO_RASTER_LOCK; pHC->clientLockPin = NV_EVO_LOCK_PIN_INTERNAL(primaryHead); @@ -9415,11 +9426,10 @@ void nvEvoEnableMergeModePreModeset(NVDispEvoRec *pDispEvo, } else { pHC->clientLockoutWindow = 2; } + pHC->crashLockUnstallMode = + (pTimings->vrr.type != NVKMS_DPY_VRR_TYPE_NONE); } - if (pTimings->vrr.type != NVKMS_DPY_VRR_TYPE_NONE) { - pHC->crashLockUnstallMode = TRUE; - } pHC->stereoLocked = FALSE; EvoUpdateHeadParams(pDispEvo, head, pUpdateState); @@ -9584,3 +9594,42 @@ NvBool nvEvoUse2Heads1OR(const NVDpyEvoRec *pDpyEvo, * maximum pixel clock support by a head. */ return (pTimings->pixelClock > pHeadCaps->maxPClkKHz); } + +NvBool nvIsLockGroupFlipLocked(const NVLockGroup *pLockGroup) +{ + return pLockGroup->flipLockEnabled; +} + +NvBool nvEvoIsConsoleActive(const NVDevEvoRec *pDevEvo) +{ + /* + * The actual console state can be known only after allocation of core + * channel, if core channel is not allocated yet then assume that console + * is active. + */ + if (pDevEvo->core == NULL) { + return TRUE; + } + + /* + * If (pDevEvo->modesetOwner == NULL) that means either the vbios + * console or the NVKMS console might be active. + * + * If (pDevEvo->modesetOwner != NULL) but + * pDevEvo->modesetOwnerChanged is TRUE, that means the modeset + * ownership is grabbed by the external client but it hasn't + * performed any modeset and the console is still active. + */ + if ((pDevEvo->modesetOwner == NULL) || pDevEvo->modesetOwnerChanged) { + NvU32 sd; + const NVDispEvoRec *pDispEvo; + FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) { + if (nvGetActiveHeadMask(pDispEvo) != 0x0) { + return TRUE; + } + } + } + + return FALSE; +} + diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c index 73b3383c35..29cb321cdc 100644 --- a/src/nvidia-modeset/src/nvkms-evo3.c +++ b/src/nvidia-modeset/src/nvkms-evo3.c @@ -3585,15 +3585,12 @@ EvoProgramSemaphore6(NVDevEvoPtr pDevEvo, const NVFlipNIsoSurfaceEvoHwState *pNIso; /*! Program Acq-only semaphore */ + pSurfaceDesc = NULL; offset = acqMode = relMode = value = 0; - if (pHwState->syncObject.usingSyncpt) { - if (pHwState->syncObject.u.syncpts.isPreSyncptSpecified) { - NvU32 id = pHwState->syncObject.u.syncpts.preSyncpt; - pSurfaceDesc = &pDevEvo->preSyncptTable[id].surfaceDesc; - } else { - pSurfaceDesc = NULL; - } - offset = 0; + if (pHwState->syncObject.usingSyncpt && + pHwState->syncObject.u.syncpts.isPreSyncptSpecified) { + NvU32 id = pHwState->syncObject.u.syncpts.preSyncpt; + pSurfaceDesc = &pDevEvo->preSyncptTable[id].surfaceDesc; acqMode = DRF_DEF(C67E, _SET_ACQ_SEMAPHORE_CONTROL, _ACQ_MODE, _CGEQ); value = pHwState->syncObject.u.syncpts.preValue; } else { @@ -3617,16 +3614,14 @@ EvoProgramSemaphore6(NVDevEvoPtr pDevEvo, /*! Program Rel-only semaphore */ pSurfaceDesc = NULL; offset = acqMode = relMode = value = 0; - if (pHwState->syncObject.usingSyncpt) { + if (pHwState->syncObject.usingSyncpt && + pHwState->syncObject.u.syncpts.isPostSyncptSpecified) { pSurfaceDesc = &pHwState->syncObject.u.syncpts.surfaceDesc; - offset = 0; acqMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _SKIP_ACQ, _TRUE); relMode = DRF_DEF(C67E, _SET_SEMAPHORE_CONTROL, _REL_MODE, _WRITE); value = pHwState->syncObject.u.syncpts.postValue; /*! increase local max val as well */ - if (pHwState->syncObject.u.syncpts.isPostSyncptSpecified) { - pChannel->postSyncpt.syncptMaxVal++; - } + pChannel->postSyncpt.syncptMaxVal++; } else { if (pHwState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo != NULL) { pNIso = &pHwState->syncObject.u.semaphores.releaseSurface; @@ -6771,12 +6766,19 @@ static void EvoSetStallLockC3(NVDispEvoPtr pDispEvo, const int head, NVEvoChannelPtr pChannel = pDevEvo->core; NVEvoSubDevPtr pEvoSubDev = &pDevEvo->gpus[pDispEvo->displayOwner]; NVEvoHeadControlPtr pHC = &pEvoSubDev->headControl[head]; + NvU32 data = 0x0; nvUpdateUpdateState(pDevEvo, updateState, pChannel); + if (pHC->crashLockUnstallMode) { + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _CRASH_LOCK); + } else { + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _LINE_LOCK); + } + if (enable) { - NvU32 data = DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _TRUE) | - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _MODE, _ONE_SHOT); + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _TRUE) | + DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _MODE, _ONE_SHOT); if (!pHC->useStallLockPin) { data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, _LOCK_PIN_NONE); @@ -6789,20 +6791,12 @@ static void EvoSetStallLockC3(NVDispEvoPtr pDispEvo, const int head, data |= DRF_NUM(C37D, _HEAD_SET_STALL_LOCK, _LOCK_PIN, NVC37D_HEAD_SET_STALL_LOCK_LOCK_PIN_LOCK_PIN(pin)); } - - if (pHC->crashLockUnstallMode) { - data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _CRASH_LOCK); - } else { - data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _UNSTALL_MODE, _LINE_LOCK); - } - - nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1); - nvDmaSetEvoMethodData(pChannel, data); } else { - nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1); - nvDmaSetEvoMethodData(pChannel, - DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _FALSE)); + data |= DRF_DEF(C37D, _HEAD_SET_STALL_LOCK, _ENABLE, _FALSE); } + + nvDmaSetStartEvoMethod(pChannel, NVC37D_HEAD_SET_STALL_LOCK(head), 1); + nvDmaSetEvoMethodData(pChannel, data); } static NvBool GetChannelState(NVDevEvoPtr pDevEvo, diff --git a/src/nvidia-modeset/src/nvkms-framelock.c b/src/nvidia-modeset/src/nvkms-framelock.c index 6fa3db20b3..5ed8fbefc5 100644 --- a/src/nvidia-modeset/src/nvkms-framelock.c +++ b/src/nvidia-modeset/src/nvkms-framelock.c @@ -368,8 +368,7 @@ static NvBool GpuIdInDevEvo(NVDevEvoPtr pDevEvo, NvU32 gpuId) /*! * Free the pFrameLock object. */ -static void FreeFrameLockEvo(NVDevEvoPtr pDevEvo, - NVFrameLockEvoPtr pFrameLockEvo) +static void FreeFrameLockEvo(NVFrameLockEvoPtr pFrameLockEvo) { if (pFrameLockEvo == NULL) { return; @@ -380,13 +379,15 @@ static void FreeFrameLockEvo(NVDevEvoPtr pDevEvo, nvEvoGlobal.clientHandle, pFrameLockEvo->device); - nvFreeUnixRmHandle(&pDevEvo->handleAllocator, + nvFreeUnixRmHandle(&pFrameLockEvo->handleAllocator, pFrameLockEvo->device); pFrameLockEvo->device = 0; } nvAssert(pFrameLockEvo->nGpuIds == 0); + nvTearDownUnixRmHandleAllocator(&pFrameLockEvo->handleAllocator); + nvListDel(&pFrameLockEvo->frameLockListEntry); nvFree(pFrameLockEvo); @@ -395,8 +396,8 @@ static void FreeFrameLockEvo(NVDevEvoPtr pDevEvo, /*! * Allocate and initialize a new pFrameLock object. */ -static NVFrameLockEvoPtr AllocFrameLockEvo(NVDevEvoPtr pDevEvo, - int instance, NvU32 gsyncId) +static NVFrameLockEvoPtr AllocFrameLockEvo(int instance, NvU32 gsyncId, + NvBool *pBadFirmware) { NV30F1_ALLOC_PARAMETERS gsyncAllocParams = { 0 }; NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS gsyncGetCapsParams = { 0 }; @@ -404,6 +405,8 @@ static NVFrameLockEvoPtr AllocFrameLockEvo(NVDevEvoPtr pDevEvo, nvAssert(FindFrameLock(gsyncId) == NULL); + *pBadFirmware = FALSE; + pFrameLockEvo = nvCalloc(1, sizeof(NVFrameLockEvoRec)); if (pFrameLockEvo == NULL) { @@ -412,7 +415,16 @@ static NVFrameLockEvoPtr AllocFrameLockEvo(NVDevEvoPtr pDevEvo, nvListInit(&pFrameLockEvo->frameLockListEntry); - pFrameLockEvo->device = nvGenerateUnixRmHandle(&pDevEvo->handleAllocator); + if (!nvInitUnixRmHandleAllocator( + &pFrameLockEvo->handleAllocator, + nvEvoGlobal.clientHandle, + NVKMS_RM_HANDLE_SPACE_FRAMELOCK(instance))) { + nvEvoLog(EVO_LOG_ERROR, "Failed to initialize framelock handles"); + goto fail; + } + + pFrameLockEvo->device = + nvGenerateUnixRmHandle(&pFrameLockEvo->handleAllocator); gsyncAllocParams.gsyncInstance = instance; @@ -456,13 +468,8 @@ static NVFrameLockEvoPtr AllocFrameLockEvo(NVDevEvoPtr pDevEvo, /* Check if the Quadro Sync card has a firmware * version compatible with the GPUs connected to it. */ - pDevEvo->badFramelockFirmware = gsyncGetCapsParams.isFirmwareRevMismatch; if (gsyncGetCapsParams.isFirmwareRevMismatch) { - nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "The firmware on this Quadro Sync " - "card is not compatible with the GPUs connected to it." - " Please visit " - " " - "for instructions on installing the correct firmware."); + *pBadFirmware = TRUE; goto fail; } @@ -514,7 +521,7 @@ static NVFrameLockEvoPtr AllocFrameLockEvo(NVDevEvoPtr pDevEvo, fail: - FreeFrameLockEvo(pDevEvo, pFrameLockEvo); + FreeFrameLockEvo(pFrameLockEvo); return NULL; } @@ -617,8 +624,8 @@ void nvAllocFrameLocksEvo(NVDevEvoPtr pDevEvo) } for (i = 0; i < ARRAY_LEN(attachedGsyncParams.gsyncIds); i++) { - NVFrameLockEvoPtr pFrameLockEvo; + NvBool badFirmware = FALSE; if (attachedGsyncParams.gsyncIds[i] == NV0000_CTRL_GSYNC_INVALID_ID) { continue; @@ -627,11 +634,20 @@ void nvAllocFrameLocksEvo(NVDevEvoPtr pDevEvo) pFrameLockEvo = FindFrameLock(attachedGsyncParams.gsyncIds[i]); if (pFrameLockEvo == NULL) { - pFrameLockEvo = AllocFrameLockEvo(pDevEvo, i, - attachedGsyncParams.gsyncIds[i]); + pFrameLockEvo = AllocFrameLockEvo(i, + attachedGsyncParams.gsyncIds[i], + &badFirmware); } if (pFrameLockEvo == NULL) { + if (badFirmware) { + nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, + "The firmware on this Quadro Sync card is not compatible " + "with the GPUs connected to it. Please visit " + " " + "for instructions on installing the correct firmware."); + pDevEvo->badFramelockFirmware = TRUE; + } continue; } @@ -654,7 +670,7 @@ void nvFreeFrameLocksEvo(NVDevEvoPtr pDevEvo) UnBindFrameLockFromDevEvo(pFrameLockEvo, pDevEvo); if (pFrameLockEvo->nGpuIds == 0) { - FreeFrameLockEvo(pDevEvo, pFrameLockEvo); + FreeFrameLockEvo(pFrameLockEvo); } } } @@ -2009,11 +2025,6 @@ static const struct { .get = NULL, .type = NV_KMS_ATTRIBUTE_TYPE_BOOLEAN, }, - [NV_KMS_DISP_ATTRIBUTE_ALLOW_FLIPLOCK] = { - .set = nvAllowFlipLockEvo, - .get = NULL, - .type = NV_KMS_ATTRIBUTE_TYPE_BOOLEAN, - }, [NV_KMS_DISP_ATTRIBUTE_QUERY_DP_AUX_LOG] = { .set = NULL, .get = nvRmQueryDpAuxLog, diff --git a/src/nvidia-modeset/src/nvkms-hal.c b/src/nvidia-modeset/src/nvkms-hal.c index e98f85ef90..16093e11ff 100644 --- a/src/nvidia-modeset/src/nvkms-hal.c +++ b/src/nvidia-modeset/src/nvkms-hal.c @@ -61,7 +61,6 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) _supportsDP13, \ _supportsHDMI20, \ _inputLutAppliesToBase, \ - _genericPageKind, \ _dpYCbCr422MaxBpc, \ _hdmiYCbCr422MaxBpc, \ _validNIsoFormatMask, \ @@ -90,7 +89,6 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) .maxWidthInBytes = _maxWidthInBytes, \ .maxWidthInPixels = _maxWidthInPixels, \ .maxHeight = _maxHeight, \ - .genericPageKind = _genericPageKind, \ .maxRasterWidth = DRF_MASK(NV ## _classPrefix ## 7D_HEAD_SET_RASTER_SIZE_WIDTH), \ .maxRasterHeight = DRF_MASK(NV ## _classPrefix ## 7D_HEAD_SET_RASTER_SIZE_HEIGHT),\ .dpYCbCr422MaxBpc = _dpYCbCr422MaxBpc, \ @@ -136,28 +134,6 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) */ #define NVD_CORE_CHANNEL_DMA_ARMED_SIZE 0x8000 - -/* - * The file - * https://github.com/NVIDIA/open-gpu-doc/blob/master/manuals/turing/tu104/dev_mmu.ref.txt - * defines: - * - * #define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x06 - * - * The file - * https://github.com/NVIDIA/open-gpu-doc/blob/master/manuals/volta/gv100/dev_mmu.ref.txt - * defines: - * - * #define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe - * - * Which correspond to the "generic" page kind used for non-compressed single- - * sample blocklinear color images on Turing+ and pre-Turing GPUs respectively. - * This is the only blocklinear memory layout display ever cares about. - */ -#define TURING_GENERIC_KIND 0x06 -#define FERMI_GENERIC_KIND 0xfe - - /* NVDisplay and later entries */ #define ENTRY_NVD(_coreClassPrefix, _windowClassPrefix, ...) \ ENTRY(_coreClassPrefix, __VA_ARGS__, \ @@ -177,33 +153,32 @@ enum NvKmsAllocDeviceStatus nvAssignEvoCaps(NVDevEvoPtr pDevEvo) const NVEvoCapsRec evoCaps; } dispTable[] = { /* - * hdmiYCbCr422MaxBpc-----------------------------------------+ - * dpYCbCr422MaxBpc---------------------------------------+ | - * genericPageKind---------------------+ | | - * inputLutAppliesToBase ---------+ | | | - * supportsHDMI20 -------------+ | | | | - * supportsDP13 ------------+ | | | | | - * pEvoHal --------------+ | | | | | | - * windowClassPrefix | | | | | | | - * classPrefix | | | | | | | | - * | | | | | | | | | + * hdmiYCbCr422MaxBpc--------------------+ + * dpYCbCr422MaxBpc------------------+ | + * inputLutAppliesToBase ---------+ | | + * supportsHDMI20 -------------+ | | | + * supportsDP13 ------------+ | | | | + * pEvoHal --------------+ | | | | | + * windowClassPrefix | | | | | | + * classPrefix | | | | | | | + * | | | | | | | | */ /* Ada */ - ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + ENTRY_NVD(C7, C6, &nvEvoC6, 1, 1, 0, 12, 12), /* Ampere */ - ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + ENTRY_NVD(C6, C6, &nvEvoC6, 1, 1, 0, 12, 12), /* Turing */ - ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 0, TURING_GENERIC_KIND, 12, 12), + ENTRY_NVD(C5, C5, &nvEvoC5, 1, 1, 0, 12, 12), /* Volta */ - ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 0, FERMI_GENERIC_KIND, 12, 12), + ENTRY_NVD(C3, C3, &nvEvoC3, 1, 1, 0, 12, 12), /* gp10x */ - ENTRY_EVO(98, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND, 12, 12), + ENTRY_EVO(98, &nvEvo94, 1, 1, 1, 12, 12), /* gp100 */ - ENTRY_EVO(97, &nvEvo94, 1, 1, 1, FERMI_GENERIC_KIND, 12, 12), + ENTRY_EVO(97, &nvEvo94, 1, 1, 1, 12, 12), /* gm20x */ - ENTRY_EVO(95, &nvEvo94, 0, 1, 1, FERMI_GENERIC_KIND, 8, 0), + ENTRY_EVO(95, &nvEvo94, 0, 1, 1, 8, 0), /* gm10x */ - ENTRY_EVO(94, &nvEvo94, 0, 0, 1, FERMI_GENERIC_KIND, 8, 0), + ENTRY_EVO(94, &nvEvo94, 0, 0, 1, 8, 0), }; int i; diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c index 6414dbcbc3..14a2a8cff8 100644 --- a/src/nvidia-modeset/src/nvkms-hdmi.c +++ b/src/nvidia-modeset/src/nvkms-hdmi.c @@ -238,7 +238,7 @@ NvBool nvDpyIsHdmiDepth30Evo(const NVDpyEvoRec *pDpyEvo) /*! * Updates the display's HDMI 2.0 capabilities to the RM. */ -void nvUpdateHdmiCaps(NVDpyEvoPtr pDpyEvo) +void nvSendHdmiCapsToRm(NVDpyEvoPtr pDpyEvo) { NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS params = { 0 }; NVParsedEdidEvoPtr pParsedEdid = &pDpyEvo->parsedEdid; @@ -256,7 +256,7 @@ void nvUpdateHdmiCaps(NVDpyEvoPtr pDpyEvo) params.caps = 0; /* - * nvUpdateHdmiCaps() gets called on dpy's connect/disconnect events + * nvSendHdmiCapsToRm() gets called on dpy's connect/disconnect events * to set/clear capabilities, clear capabilities if parsed edid * is not valid. */ @@ -1835,15 +1835,11 @@ NvBool nvHdmi204k60HzRGB444Allowed(const NVDpyEvoRec *pDpyEvo, void nvHdmiSetVRR(NVDispEvoPtr pDispEvo, NvU32 head, NvBool enable) { NVT_EXTENDED_METADATA_PACKET_INFOFRAME empInfoFrame; - NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL empCtrl; + NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL empCtrl = { 0 }; NVHDMIPKT_TC transmitControl; NVT_STATUS status; - nvkms_memset(&empCtrl, NVT_INFOFRAME_CTRL_DONTCARE, - sizeof(empCtrl)); - empCtrl.EnableVRR = enable; - empCtrl.EnableQMS = FALSE; status = NvTiming_ConstructExtendedMetadataPacketInfoframe(&empCtrl, &empInfoFrame); diff --git a/src/nvidia-modeset/src/nvkms-modepool.c b/src/nvidia-modeset/src/nvkms-modepool.c index 671e1a6eb4..07d75fa880 100644 --- a/src/nvidia-modeset/src/nvkms-modepool.c +++ b/src/nvidia-modeset/src/nvkms-modepool.c @@ -1646,6 +1646,10 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, NvU8 hdmiFrlBpc; NvBool ret = FALSE; + const NVColorFormatInfoRec supportedColorFormats = nvGetColorFormatInfo(pDpyEvo); + enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; + enum NvKmsDpyAttributeColorBpcValue colorBpc; + if (modeName[0] == '\0') { nvBuildModeName(pModeTimings->hVisible, pModeTimings->vVisible, localModeName, sizeof(localModeName)); @@ -1702,6 +1706,16 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, b2Heads1Or = nvEvoUse2Heads1OR(pDpyEvo, pTimingsEvo, pParams); + if (pTimingsEvo->yuv420Mode != NV_YUV420_MODE_NONE) { + colorSpace = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420; + colorBpc = NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_BPC_8; + } else if (!nvGetDefaultColorSpace(&supportedColorFormats, &colorSpace, + &colorBpc)) { + LogModeValidationEnd(pDispEvo, pInfoString, + "Failed to get default color space and Bpc"); + goto done; + } + if (nvDpyIsHdmiEvo(pDpyEvo)) { if (!nvHdmiFrlQueryConfig(pDpyEvo, &pKmsMode->timings, @@ -1716,8 +1730,8 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, goto done; } } else { - if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, b2Heads1Or, pDscInfo, - pParams)) { + if (!nvDPValidateModeEvo(pDpyEvo, pTimingsEvo, &colorSpace, &colorBpc, + b2Heads1Or, pDscInfo, pParams)) { LogModeValidationEnd(pDispEvo, pInfoString, "DP Bandwidth check failed"); goto done; @@ -1736,28 +1750,20 @@ static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo, /* Run the raster timings through IMP checking. */ - { - const NVColorFormatInfoRec colorFormats = - nvGetColorFormatInfo(pDpyEvo); - enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace; - enum NvKmsDpyAttributeColorBpcValue colorBpc; - - if (!nvGetDefaultColorSpace(&colorFormats, &colorSpace, &colorBpc) || - !nvConstructHwModeTimingsImpCheckEvo(pDpyEvo->pConnectorEvo, - pTimingsEvo, - (pDscInfo->type != - NV_DSC_INFO_EVO_TYPE_DISABLED), - b2Heads1Or, - colorSpace, - colorBpc, - pParams, - impOutTimings, - &impOutNumHeads, - pInfoString)) { - LogModeValidationEnd(pDispEvo, pInfoString, - "GPU extended capability check failed"); - goto done; - } + if (!nvConstructHwModeTimingsImpCheckEvo(pDpyEvo->pConnectorEvo, + pTimingsEvo, + (pDscInfo->type != + NV_DSC_INFO_EVO_TYPE_DISABLED), + b2Heads1Or, + colorSpace, + colorBpc, + pParams, + impOutTimings, + &impOutNumHeads, + pInfoString)) { + LogModeValidationEnd(pDispEvo, pInfoString, + "GPU extended capability check failed"); + goto done; } nvAssert(impOutNumHeads > 0); diff --git a/src/nvidia-modeset/src/nvkms-rm.c b/src/nvidia-modeset/src/nvkms-rm.c index 6768f8602c..b8ce0560f1 100644 --- a/src/nvidia-modeset/src/nvkms-rm.c +++ b/src/nvidia-modeset/src/nvkms-rm.c @@ -199,6 +199,9 @@ static NvBool QueryGpuCapabilities(NVDevEvoPtr pDevEvo) /* TODO: This cap bit should be queried from RM */ pDevEvo->requiresAllAllocationsInSysmem = pDevEvo->isSOCDisplay; + pDevEvo->supportsVblankSemControl = + !pDevEvo->isSOCDisplay && nvkms_vblank_sem_control(); + /* ctxDma{,Non}CoherentAllowed */ if (!pDevEvo->isSOCDisplay) { @@ -4250,9 +4253,10 @@ NvBool nvRmAllocDeviceEvo(NVDevEvoPtr pDevEvo, goto failure; } - if (!nvInitUnixRmHandleAllocator(&pDevEvo->handleAllocator, - nvEvoGlobal.clientHandle, - pRequest->deviceId + 1)) { + if (!nvInitUnixRmHandleAllocator( + &pDevEvo->handleAllocator, + nvEvoGlobal.clientHandle, + NVKMS_RM_HANDLE_SPACE_DEVICE(pRequest->deviceId))) { nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "Failed to initialize handles"); goto failure; } diff --git a/src/nvidia-modeset/src/nvkms-surface.c b/src/nvidia-modeset/src/nvkms-surface.c index c960505a62..d88b448b9e 100644 --- a/src/nvidia-modeset/src/nvkms-surface.c +++ b/src/nvidia-modeset/src/nvkms-surface.c @@ -1225,3 +1225,111 @@ void nvEvoUnregisterDeferredRequestFifo( nvFree(pDeferredRequestFifo); } + +static NvBool UpdateVblankSemControl( + NVDevEvoRec *pDevEvo, + NVVblankSemControl *pVblankSemControl, + NvBool enable) +{ + NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS params = { }; + + params.subDeviceInstance = pVblankSemControl->dispIndex; + params.head = pVblankSemControl->hwHead; + params.hMemory = pVblankSemControl->pSurfaceEvo->planes[0].rmHandle; + params.memoryOffset = pVblankSemControl->surfaceOffset; + params.bEnable = enable; + + return nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL, + ¶ms, sizeof(params)) == NVOS_STATUS_SUCCESS; +} + +NVVblankSemControl *nvEvoEnableVblankSemControl( + NVDevEvoRec *pDevEvo, + NVDispEvoRec *pDispEvo, + NvU32 hwHead, + NVSurfaceEvoRec *pSurfaceEvo, + NvU64 surfaceOffset) +{ + NVVblankSemControl *pVblankSemControl; + + if (!pDevEvo->supportsVblankSemControl) { + return NULL; + } + + /* + * We cannot enable VblankSemControl if the requested offset within the + * surface is too large. + */ + if (A_plus_B_greater_than_C_U64( + surfaceOffset, + sizeof(NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA), + pSurfaceEvo->planes[0].rmObjectSizeInBytes)) { + return NULL; + } + + if (nvEvoSurfaceRefCntsTooLarge(pSurfaceEvo)) { + return NULL; + } + + pVblankSemControl = nvCalloc(1, sizeof(*pVblankSemControl)); + + if (pVblankSemControl == NULL) { + return NULL; + } + + pVblankSemControl->hwHead = hwHead; + pVblankSemControl->dispIndex = pDispEvo->displayOwner; + pVblankSemControl->surfaceOffset = surfaceOffset; + pVblankSemControl->pSurfaceEvo = pSurfaceEvo; + + if (UpdateVblankSemControl(pDevEvo, + pVblankSemControl, + TRUE /* enable */)) { + nvEvoIncrementSurfaceRefCnts(pSurfaceEvo); + return pVblankSemControl; + } else { + nvFree(pVblankSemControl); + return NULL; + } +} + +NvBool nvEvoDisableVblankSemControl( + NVDevEvoRec *pDevEvo, + NVVblankSemControl *pVblankSemControl) +{ + if (!pDevEvo->supportsVblankSemControl) { + return FALSE; + } + + if (UpdateVblankSemControl(pDevEvo, + pVblankSemControl, + FALSE /* enable */)) { + nvEvoDecrementSurfaceRefCnts(pDevEvo, pVblankSemControl->pSurfaceEvo); + nvFree(pVblankSemControl); + return TRUE; + } else { + return FALSE; + } +} + +NvBool nvEvoAccelVblankSemControls( + NVDevEvoPtr pDevEvo, + NvU32 dispIndex, + NvU32 hwHeadMask) +{ + NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS params = { }; + + if (!pDevEvo->supportsVblankSemControl) { + return FALSE; + } + + params.subDeviceInstance = dispIndex; + params.headMask = hwHeadMask; + + return nvRmApiControl(nvEvoGlobal.clientHandle, + pDevEvo->displayCommonHandle, + NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS, + ¶ms, sizeof(params)) == NVOS_STATUS_SUCCESS; +} diff --git a/src/nvidia-modeset/src/nvkms-vrr.c b/src/nvidia-modeset/src/nvkms-vrr.c index 6fbc0af639..d10dea0113 100644 --- a/src/nvidia-modeset/src/nvkms-vrr.c +++ b/src/nvidia-modeset/src/nvkms-vrr.c @@ -262,21 +262,12 @@ void nvAdjustHwModeTimingsForVrrEvo(NVHwModeTimingsEvoPtr pTimings, const NvU32 vrrOverrideMinRefreshRate, const NvBool needsSwFramePacing) { + NvU32 timeoutMicroseconds; + if (vrrType == NVKMS_DPY_VRR_TYPE_NONE) { return; } - /* - * On G-SYNC panels, the back porch extension is used to indicate to - * the monitor that VRR is enabled. It is not necessary on - * Adaptive-Sync displays. - */ - if (vrrType == NVKMS_DPY_VRR_TYPE_GSYNC) { - pTimings->rasterSize.y += 2; - pTimings->rasterBlankEnd.y += 2; - pTimings->rasterBlankStart.y += 2; - } - // Allow overriding the EDID min refresh rate on Adaptive-Sync // displays. if (nvIsAdaptiveSyncDpyVrrType(vrrType) && vrrOverrideMinRefreshRate) { @@ -295,11 +286,30 @@ void nvAdjustHwModeTimingsForVrrEvo(NVHwModeTimingsEvoPtr pTimings, clampedMinRefreshRate = NV_MIN(clampedMinRefreshRate, maxMinRefreshRate); - pTimings->vrr.timeoutMicroseconds = 1000000 / - clampedMinRefreshRate; + timeoutMicroseconds = 1000000 / clampedMinRefreshRate; } else { - pTimings->vrr.timeoutMicroseconds = edidTimeoutMicroseconds; + timeoutMicroseconds = edidTimeoutMicroseconds; } + + // Disallow VRR if the refresh rate is less than 110% of the VRR minimum + // refresh rate. + if (nvGetRefreshRate10kHz(pTimings) < + (((NvU64) 1000000 * 11000) / timeoutMicroseconds)) { + return; + } + + /* + * On G-SYNC panels, the back porch extension is used to indicate to + * the monitor that VRR is enabled. It is not necessary on + * Adaptive-Sync displays. + */ + if (vrrType == NVKMS_DPY_VRR_TYPE_GSYNC) { + pTimings->rasterSize.y += 2; + pTimings->rasterBlankEnd.y += 2; + pTimings->rasterBlankStart.y += 2; + } + + pTimings->vrr.timeoutMicroseconds = timeoutMicroseconds; pTimings->vrr.needsSwFramePacing = needsSwFramePacing; pTimings->vrr.type = vrrType; } diff --git a/src/nvidia-modeset/src/nvkms.c b/src/nvidia-modeset/src/nvkms.c index 1038873e78..50c46bd357 100644 --- a/src/nvidia-modeset/src/nvkms.c +++ b/src/nvidia-modeset/src/nvkms.c @@ -145,6 +145,7 @@ struct NvKmsPerOpenDisp { struct NvKmsPerOpenConnector connector[NVKMS_MAX_CONNECTORS_PER_DISP]; NVEvoApiHandlesRec vblankSyncObjectHandles[NVKMS_MAX_HEADS_PER_DISP]; NVEvoApiHandlesRec vblankCallbackHandles[NVKMS_MAX_HEADS_PER_DISP]; + NVEvoApiHandlesRec vblankSemControlHandles; }; struct NvKmsPerOpenDev { @@ -697,6 +698,8 @@ static void ClearPerOpenDisp( nvEvoDestroyApiHandles(&pOpenDisp->vblankCallbackHandles[i]); } + nvEvoDestroyApiHandles(&pOpenDisp->vblankSemControlHandles); + nvEvoDestroyApiHandle(&pOpenDev->dispHandles, pOpenDisp->nvKmsApiHandle); nvkms_memset(pOpenDisp, 0, sizeof(*pOpenDisp)); @@ -762,8 +765,8 @@ static NvBool InitPerOpenDisp( /* Initialize the vblankCallbackHandles for each head. * - * The limit of VBLANK_SYNC_OBJECTS_PER_HEAD doesn't really apply here, but - * we need something. */ + * The initial value of VBLANK_SYNC_OBJECTS_PER_HEAD doesn't really apply + * here, but we need something. */ for (NvU32 i = 0; i < NVKMS_MAX_HEADS_PER_DISP; i++) { if (!nvEvoInitApiHandles(&pOpenDisp->vblankCallbackHandles[i], NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD)) { @@ -771,6 +774,15 @@ static NvBool InitPerOpenDisp( } } + /* Initialize the vblankSemControlHandles. + * + * The initial value of VBLANK_SYNC_OBJECTS_PER_HEAD doesn't really apply + * here, but we need something. */ + if (!nvEvoInitApiHandles(&pOpenDisp->vblankSemControlHandles, + NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD)) { + goto fail; + } + if (!AllocPerOpenFrameLock(pOpen, pOpenDisp)) { goto fail; } @@ -1444,7 +1456,6 @@ static NvBool AllocDevice(struct NvKmsPerOpen *pOpen, pParams->reply.maxWidthInPixels = pDevEvo->caps.maxWidthInPixels; pParams->reply.maxHeightInPixels = pDevEvo->caps.maxHeight; pParams->reply.cursorCompositionCaps = pDevEvo->caps.cursorCompositionCaps; - pParams->reply.genericPageKind = pDevEvo->caps.genericPageKind; pParams->reply.maxCursorSize = pDevEvo->cursorHal->caps.maxSize; @@ -1470,6 +1481,8 @@ static NvBool AllocDevice(struct NvKmsPerOpen *pOpen, pParams->reply.supportsVblankSyncObjects = pDevEvo->hal->caps.supportsVblankSyncObjects; + pParams->reply.supportsVblankSemControl = pDevEvo->supportsVblankSemControl; + pParams->reply.status = NVKMS_ALLOC_DEVICE_STATUS_SUCCESS; return TRUE; @@ -1554,12 +1567,46 @@ static void DisableRemainingVblankSyncObjects(struct NvKmsPerOpen *pOpen, } } +static void DisableRemainingVblankSemControls( + struct NvKmsPerOpen *pOpen, + struct NvKmsPerOpenDev *pOpenDev) +{ + struct NvKmsPerOpenDisp *pOpenDisp; + NvKmsGenericHandle dispHandle; + NVDevEvoPtr pDevEvo = pOpenDev->pDevEvo; + + nvAssert(pOpen->type == NvKmsPerOpenTypeIoctl); + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDev->dispHandles, + pOpenDisp, + dispHandle) { + + NVVblankSemControl *pVblankSemControl; + NvKmsGenericHandle vblankSemControlHandle; + + FOR_ALL_POINTERS_IN_EVO_API_HANDLES(&pOpenDisp->vblankSemControlHandles, + pVblankSemControl, + vblankSemControlHandle) { + NvBool ret = + nvEvoDisableVblankSemControl(pDevEvo, pVblankSemControl); + + if (!ret) { + nvAssert(!"implicit disable of vblank sem control failed."); + } + nvEvoDestroyApiHandle(&pOpenDisp->vblankSemControlHandles, + vblankSemControlHandle); + } + } +} + static void FreeDeviceReference(struct NvKmsPerOpen *pOpen, struct NvKmsPerOpenDev *pOpenDev) { /* Disable all client-owned vblank sync objects that still exist. */ DisableRemainingVblankSyncObjects(pOpen, pOpenDev); + DisableRemainingVblankSemControls(pOpen, pOpenDev); + FreeSwapGroups(pOpenDev); UnregisterDeferredRequestFifos(pOpenDev); @@ -4667,6 +4714,150 @@ static NvBool SetFlipLockGroup( return nvSetFlipLockGroup(pDevEvo, pRequest); } +static NvBool EnableVblankSemControl( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + struct NvKmsEnableVblankSemControlParams *pParams = pParamsVoid; + struct NvKmsPerOpenDev *pOpenDev; + struct NvKmsPerOpenDisp *pOpenDisp; + NVDevEvoPtr pDevEvo; + NVDispEvoRec *pDispEvo; + NVSurfaceEvoPtr pSurfaceEvo; + NVVblankSemControl *pVblankSemControl; + NvKmsVblankSemControlHandle vblankSemControlHandle; + NvU32 hwHead; + + if (!GetPerOpenDevAndDisp(pOpen, + pParams->request.deviceHandle, + pParams->request.dispHandle, + &pOpenDev, + &pOpenDisp)) { + return FALSE; + } + + pDevEvo = pOpenDev->pDevEvo; + pDispEvo = pOpenDisp->pDispEvo; + + pSurfaceEvo = + nvEvoGetSurfaceFromHandleNoDispHWAccessOk( + pDevEvo, + &pOpenDev->surfaceHandles, + pParams->request.surfaceHandle); + + if (pSurfaceEvo == NULL) { + return FALSE; + } + + hwHead = nvGetPrimaryHwHead(pDispEvo, pParams->request.head); + + if (hwHead == NV_INVALID_HEAD) { + return FALSE; + } + + pVblankSemControl = nvEvoEnableVblankSemControl( + pDevEvo, + pDispEvo, + hwHead, + pSurfaceEvo, + pParams->request.surfaceOffset); + + if (pVblankSemControl == NULL) { + return FALSE; + } + + vblankSemControlHandle = + nvEvoCreateApiHandle(&pOpenDisp->vblankSemControlHandles, + pVblankSemControl); + + if (vblankSemControlHandle == 0) { + (void)nvEvoDisableVblankSemControl(pDevEvo, pVblankSemControl); + return FALSE; + } + + pParams->reply.vblankSemControlHandle = vblankSemControlHandle; + + return TRUE; +} + +static NvBool DisableVblankSemControl( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + const struct NvKmsDisableVblankSemControlParams *pParams = pParamsVoid; + struct NvKmsPerOpenDev *pOpenDev; + struct NvKmsPerOpenDisp *pOpenDisp; + NVDevEvoPtr pDevEvo; + NVVblankSemControl *pVblankSemControl; + NvBool ret; + + if (!GetPerOpenDevAndDisp(pOpen, + pParams->request.deviceHandle, + pParams->request.dispHandle, + &pOpenDev, + &pOpenDisp)) { + return FALSE; + } + + pDevEvo = pOpenDev->pDevEvo; + + pVblankSemControl = + nvEvoGetPointerFromApiHandle(&pOpenDisp->vblankSemControlHandles, + pParams->request.vblankSemControlHandle); + if (pVblankSemControl == NULL) { + return FALSE; + } + + ret = nvEvoDisableVblankSemControl(pDevEvo, pVblankSemControl); + + if (ret) { + nvEvoDestroyApiHandle(&pOpenDisp->vblankSemControlHandles, + pParams->request.vblankSemControlHandle); + } + + return ret; +} + +static NvBool AccelVblankSemControls( + struct NvKmsPerOpen *pOpen, + void *pParamsVoid) +{ + const struct NvKmsAccelVblankSemControlsParams *pParams = pParamsVoid; + struct NvKmsPerOpenDev *pOpenDev; + struct NvKmsPerOpenDisp *pOpenDisp; + NVDevEvoPtr pDevEvo; + const NVDispEvoRec *pDispEvo; + NvU32 apiHead, hwHeadMask = 0; + + if (!GetPerOpenDevAndDisp(pOpen, + pParams->request.deviceHandle, + pParams->request.dispHandle, + &pOpenDev, + &pOpenDisp)) { + return FALSE; + } + + if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) { + return FALSE; + } + + pDevEvo = pOpenDev->pDevEvo; + pDispEvo = pOpenDisp->pDispEvo; + + FOR_ALL_HEADS(apiHead, pParams->request.headMask) { + NvU32 hwHead = nvGetPrimaryHwHead(pDispEvo, apiHead); + + if (hwHead != NV_INVALID_HEAD) { + hwHeadMask |= NVBIT(hwHead); + } + } + + return nvEvoAccelVblankSemControls( + pDevEvo, + pDispEvo->displayOwner, + hwHeadMask); +} + /*! * Perform the ioctl operation requested by the client. * @@ -4789,6 +4980,9 @@ NvBool nvKmsIoctl( ENTRY(NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT, DisableVblankSyncObject), ENTRY(NVKMS_IOCTL_NOTIFY_VBLANK, NotifyVblank), ENTRY(NVKMS_IOCTL_SET_FLIPLOCK_GROUP, SetFlipLockGroup), + ENTRY(NVKMS_IOCTL_ENABLE_VBLANK_SEM_CONTROL, EnableVblankSemControl), + ENTRY(NVKMS_IOCTL_DISABLE_VBLANK_SEM_CONTROL, DisableVblankSemControl), + ENTRY(NVKMS_IOCTL_ACCEL_VBLANK_SEM_CONTROLS, AccelVblankSemControls), }; struct NvKmsPerOpen *pOpen = pOpenVoid; @@ -5702,11 +5896,21 @@ ProcFsPrintHeads( outString(data, buffer); FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { + const NVLockGroup *pLockGroup = pDispEvo->pLockGroup; nvInitInfoString(&infoString, buffer, size); nvEvoLogInfoString(&infoString, " pDispEvo (dispIndex:%02d) : %p", dispIndex, pDispEvo); + if (pLockGroup != NULL) { + const NvBool flipLocked = nvIsLockGroupFlipLocked(pLockGroup); + nvEvoLogInfoString(&infoString, + " pLockGroup : %p", + pLockGroup); + nvEvoLogInfoString(&infoString, + " flipLock : %s", + flipLocked ? "yes" : "no"); + } outString(data, buffer); if (pDevEvo->coreInitMethodsPending) { diff --git a/src/nvidia/Makefile b/src/nvidia/Makefile index b29de89d6f..e2f1c67288 100644 --- a/src/nvidia/Makefile +++ b/src/nvidia/Makefile @@ -43,7 +43,6 @@ CFLAGS += -I $(SRC_COMMON)/inc CFLAGS += -I $(SRC_COMMON)/uproc/os/libos-v2.0.0/include CFLAGS += -I $(SRC_COMMON)/uproc/os/common/include -CFLAGS += -I $(SRC_COMMON)/uproc/os/libos-v2.0.0/debug CFLAGS += -I $(SRC_COMMON)/inc/swref CFLAGS += -I $(SRC_COMMON)/inc/swref/published @@ -94,6 +93,13 @@ ifeq ($(TARGET_ARCH),aarch64) CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics) endif +ifeq ($(TARGET_ARCH),riscv64) + CFLAGS += -march=rv64imac_zicsr_zifencei + CFLAGS += -mabi=lp64 + CFLAGS += -mcmodel=medany + CFLAGS += -mno-relax +endif + CFLAGS += -fno-pic CFLAGS += -D_LANGUAGE_C diff --git a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h index 046c681f92..f16ad579ea 100644 --- a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h +++ b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h @@ -272,6 +272,7 @@ typedef NvU8 FLCN_STATUS; #define FLCN_ERR_QUEUE_TASK_INVALID_EVENT_TYPE (0xE2U) #define FLCN_ERR_QUEUE_TASK_INVALID_UNIT_ID (0xE3U) #define FLCN_ERR_QUEUE_TASK_INVALID_CMD_TYPE (0xE4U) +#define FLCN_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE (0xE5U) // Posted write errors #define FLCN_ERR_POSTED_WRITE_FAILURE (0xF0U) diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h index d24af25ba7..d03b57b8af 100644 --- a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_nvdm_format.h @@ -21,8 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _FSP_NVDM_FORMAT_H_ -#define _FSP_NVDM_FORMAT_H_ +#ifndef FSP_NVDM_FORMAT_H +#define FSP_NVDM_FORMAT_H #include "fsp/fsp_mctp_format.h" #include "fsp/fsp_emem_channels.h" @@ -35,12 +35,15 @@ #define NVDM_TYPE_HULK 0x11 #define NVDM_TYPE_FIRMWARE_UPDATE 0x12 +#define NVDM_TYPE_PRC 0x13 #define NVDM_TYPE_COT 0x14 #define NVDM_TYPE_FSP_RESPONSE 0x15 +#define NVDM_TYPE_CAPS_QUERY 0x16 #define NVDM_TYPE_INFOROM 0x17 #define NVDM_TYPE_SMBPBI 0x18 #define NVDM_TYPE_ROMREAD 0x1A #define NVDM_TYPE_UEFI_RM 0x1C #define NVDM_TYPE_UEFI_XTL_DEBUG_INTR 0x1D +#define NVDM_TYPE_TNVL 0x1F -#endif // _FSP_NVDM_FORMAT_H_ +#endif // FSP_NVDM_FORMAT_H diff --git a/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_tnvl_rpc.h b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_tnvl_rpc.h new file mode 100644 index 0000000000..ec508e92d3 --- /dev/null +++ b/src/nvidia/arch/nvalloc/common/inc/fsp/fsp_tnvl_rpc.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _FSP_TNVL_RPC_H_ +#define _FSP_TNVL_RPC_H_ + +#define TNVL_CAPS_SUBMESSAGE_ID 0xFF + +#pragma pack(1) + + /*! + * @brief TNVL payload to query FSP capabilities + */ +typedef struct +{ + NvU8 subMessageId; +} TNVL_RPC_CAPS_PAYLOAD; + +/*! + * @brief TNVL response payload for FSP capability query + */ +typedef struct +{ + NvU8 nvdmType; + NVDM_PAYLOAD_COMMAND_RESPONSE cmdResponse; + NvU8 rspPayload[40]; +} TNVL_RPC_CAPS_RSP_PAYLOAD; + +#pragma pack() + +#endif // _FSP_TNVL_RPC_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h index 2ccc49cff3..a8735ecfb4 100644 --- a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_proxy_reg.h @@ -36,4 +36,8 @@ #define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_DISABLE 0x00000000 #define NVGSP_PROXY_REG_CONF_COMPUTE_DEV_MODE_ENABLE 0x00000001 +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE 4:3 +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NONE 0x00000000 +#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001 + #endif // NVGSP_PROXY_REG_H diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h index 7aba29a1de..00baecaea2 100644 --- a/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gspifpub.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -83,6 +83,24 @@ typedef struct GSP_RM_PARAMS NvU64 bootArgsOffset; } GSP_RM_PARAMS; +/*! + * @brief GSP-SPDM Parameters + * + * Parameters required to set up a communication mechanism between Kernel-RM + * and SPDM partition inside GSP. + */ +typedef struct GSP_SPDM_PARAMS +{ + // Physical Memory Aperture through which all addresses are accessed + GSP_DMA_TARGET target; + + // Physical offset in the memory aperture where SPDM payload is stored + NvU64 payloadBufferOffset; + + // Size of the above payload buffer + NvU32 payloadBufferSize; +} GSP_SPDM_PARAMS; + /*! * @brief GSP-CC Microcode Parameters for Boot Partitions */ @@ -91,6 +109,7 @@ typedef struct GSP_FMC_BOOT_PARAMS GSP_FMC_INIT_PARAMS initParams; GSP_ACR_BOOT_GSP_RM_PARAMS bootGspRmParams; GSP_RM_PARAMS gspRmParams; + GSP_SPDM_PARAMS gspSpdmParams; } GSP_FMC_BOOT_PARAMS; #endif // GSPIFPUB_H diff --git a/src/nvidia/arch/nvalloc/common/inc/nvcst.h b/src/nvidia/arch/nvalloc/common/inc/nvcst.h index d5d662a0ed..268f3c2a52 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvcst.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvcst.h @@ -89,9 +89,12 @@ CHIPSET_SETUP_FUNC(Amazon_Gravitron2_setupFunc) CHIPSET_SETUP_FUNC(Fujitsu_A64FX_setupFunc) CHIPSET_SETUP_FUNC(Ampere_Altra_setupFunc) CHIPSET_SETUP_FUNC(Arm_NeoverseN1_setupFunc) +CHIPSET_SETUP_FUNC(Ampere_AmpereOne_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T210_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_T194_setupFunc) CHIPSET_SETUP_FUNC(Nvidia_TH500_setupFunc) +CHIPSET_SETUP_FUNC(PLDA_XpressRichAXI_setupFunc) +CHIPSET_SETUP_FUNC(Riscv_generic_setupFunc) // Keep string length <=32 (including termination) to avoid string copy overflow @@ -265,6 +268,16 @@ CSINFO chipsetInfo[] = {PCI_VENDOR_ID_HYGON, 0x790E, CS_HYGON_C86, "Hygon-C86-7151", NULL}, {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX, "Marvell Octeon CN96xx", ARMV8_generic_setupFunc}, {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX, "Marvell Octeon CN98xx", ARMV8_generic_setupFunc}, + {PCI_VENDOR_ID_SIFIVE, 0x0000, CS_SIFIVE_FU740_C000, "SiFive FU740-000", Riscv_generic_setupFunc}, + {PCI_VENDOR_ID_PLDA, 0x1111, CS_PLDA_XPRESSRICH_AXI_REF, "XpressRich-AXI Ref Design", PLDA_XpressRichAXI_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, + {PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE, "Ampere AmpereOne", Ampere_AmpereOne_setupFunc}, /////////////////////////////////////////////////////////////////////////////////////////////////// @@ -300,6 +313,8 @@ VENDORNAME vendorName[] = {PCI_VENDOR_ID_CADENCE, "Cadence"}, {PCI_VENDOR_ID_ARM, "ARM"}, {PCI_VENDOR_ID_ALIBABA, "Alibaba"}, + {PCI_VENDOR_ID_SIFIVE, "SiFive"}, + {PCI_VENDOR_ID_PLDA, "PLDA"}, {0, "Unknown"} // Indicates end of the table }; @@ -363,6 +378,14 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx {PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian + {PCI_VENDOR_ID_AMPERE, 0xE200, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE201, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE202, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE203, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE204, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE205, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE206, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne + {PCI_VENDOR_ID_AMPERE, 0xE207, CS_AMPERE_AMPEREONE}, // Ampere AmpereOne // last element must have chipset CS_UNKNOWN (zero) {0, 0, CS_UNKNOWN} diff --git a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h index 28f6ef5f1e..3c7ddd87f8 100644 --- a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h +++ b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h @@ -238,6 +238,8 @@ 0x00000013 #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_PMGR_PWR_MODULE_LIMIT_INFO_GET \ 0x00000014 +#define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_MEMORY_CAPACITY_UTILIZATION_GET \ + 0x00000015 #define NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_POLL 0x000000ff @@ -635,7 +637,7 @@ /* MSGBOX data, capability dword structure */ #define NV_MSGBOX_DATA_REG 31:0 -#define NV_MSGBOX_DATA_CAP_COUNT 5 +#define NV_MSGBOX_DATA_CAP_COUNT 6 #define NV_MSGBOX_DATA_CAP_0 0 #define NV_MSGBOX_DATA_CAP_0_TEMP_GPU_0 0:0 @@ -961,6 +963,11 @@ #define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_4_MAX_DRAM_CAPACITY_V1_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_5 5 +#define NV_MSGBOX_DATA_CAP_5_MEMORY_CAPACITY_UTILIZATION 6:6 +#define NV_MSGBOX_DATA_CAP_5_MEMORY_CAPACITY_UTILIZATION_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_5_MEMORY_CAPACITY_UTILIZATION_AVAILABLE 0x00000001 + /* ECC counters */ #define NV_MSGBOX_DATA_ECC_CNT_16BIT_DBE 31:16 #define NV_MSGBOX_DATA_ECC_CNT_16BIT_SBE 16:0 @@ -2035,6 +2042,16 @@ typedef struct NvU32 clkMaxFreqMHz; } NV_MSGBOX_OOB_CLOCK_LIMIT_CTRL_PARAMS; +/*! + * This structure is used to hold parameters for + * NV_MSGBOX_CMD_ARG1_ASYNC_REQUEST_MEMORY_CAPACITY_UTILIZATION_GET + */ +typedef struct +{ + NvU32 capacityReservedMiB; //> NV_RM_TO_OS_PAGE_SHIFT) + \ ((((count) & ((1 << NV_RM_TO_OS_PAGE_SHIFT) - 1)) != 0) ? 1 : 0)) @@ -467,12 +466,6 @@ typedef struct nv_state_t NvHandle hDisp; } rmapi; - /* Bool to check if ISO iommu enabled */ - NvBool iso_iommu_present; - - /* Bool to check if NISO iommu enabled */ - NvBool niso_iommu_present; - /* Bool to check if dma-buf is supported */ NvBool dma_buf_supported; @@ -484,6 +477,22 @@ typedef struct nv_state_t /* Bool to check if the GPU has a coherent sysmem link */ NvBool coherent; + + /* + * NUMA node ID of the CPU to which the GPU is attached. + * Holds NUMA_NO_NODE on platforms that don't support NUMA configuration. + */ + NvS32 cpu_numa_node_id; + + struct { + /* Bool to check if ISO iommu enabled */ + NvBool iso_iommu_present; + /* Bool to check if NISO iommu enabled */ + NvBool niso_iommu_present; + /* Display SMMU Stream IDs */ + NvU32 dispIsoStreamId; + NvU32 dispNisoStreamId; + } iommus; } nv_state_t; // These define need to be in sync with defines in system.h @@ -613,10 +622,10 @@ typedef enum (((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0) #define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \ - ((nv)->iso_iommu_present) + ((nv)->iommus.iso_iommu_present) #define NV_SOC_IS_NISO_IOMMU_PRESENT(nv) \ - ((nv)->niso_iommu_present) + ((nv)->iommus.niso_iommu_present) /* * GPU add/remove events */ @@ -779,8 +788,6 @@ NV_STATUS NV_API_CALL nv_register_phys_pages (nv_state_t *, NvU64 *, NvU64, void NV_API_CALL nv_unregister_phys_pages (nv_state_t *, void *); NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, void **); -NV_STATUS NV_API_CALL nv_dma_map_pages (nv_dma_device_t *, NvU64, NvU64 *, NvBool, NvU32, void **); -NV_STATUS NV_API_CALL nv_dma_unmap_pages (nv_dma_device_t *, NvU64, NvU64 *, void **); NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, void **); NV_STATUS NV_API_CALL nv_dma_unmap_alloc (nv_dma_device_t *, NvU64, NvU64 *, void **); @@ -830,7 +837,7 @@ void NV_API_CALL nv_put_firmware(const void *); nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **); void NV_API_CALL nv_put_file_private(void *); -NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); +NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU64 *, NvU32 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *); NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**); @@ -877,9 +884,9 @@ struct drm_gem_object; NV_STATUS NV_API_CALL nv_dma_import_sgt (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *); void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *); -NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **); -NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **); -void NV_API_CALL nv_dma_release_dma_buf (void *, nv_dma_buf_t *); +NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, struct sg_table **, nv_dma_buf_t **); +NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, struct sg_table **, nv_dma_buf_t **); +void NV_API_CALL nv_dma_release_dma_buf (nv_dma_buf_t *); void NV_API_CALL nv_schedule_uvm_isr (nv_state_t *); @@ -895,6 +902,8 @@ typedef void (*nvTegraDceClientIpcCallback)(NvU32, NvU32, NvU32, void *, void *) NV_STATUS NV_API_CALL nv_get_num_phys_pages (void *, NvU32 *); NV_STATUS NV_API_CALL nv_get_phys_pages (void *, void *, NvU32 *); +void NV_API_CALL nv_get_disp_smmu_stream_ids (nv_state_t *, NvU32 *, NvU32 *); + /* * --------------------------------------------------------------------------- * @@ -921,6 +930,7 @@ NV_STATUS NV_API_CALL rm_ioctl (nvidia_stack_t *, nv_state_t * NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *); void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *); +NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t); NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *); @@ -940,6 +950,7 @@ void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char * char* NV_API_CALL rm_remove_spaces (const char *); char* NV_API_CALL rm_string_token (char **, const char); void NV_API_CALL rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool); +NV_STATUS NV_API_CALL rm_get_adapter_status_external(nvidia_stack_t *, nv_state_t *); NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *); void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *); diff --git a/src/nvidia/arch/nvalloc/unix/include/os-interface.h b/src/nvidia/arch/nvalloc/unix/include/os-interface.h index ffbf4e1f5a..9f7b8046ff 100644 --- a/src/nvidia/arch/nvalloc/unix/include/os-interface.h +++ b/src/nvidia/arch/nvalloc/unix/include/os-interface.h @@ -67,7 +67,6 @@ typedef struct os_wait_queue os_wait_queue; * --------------------------------------------------------------------------- */ -NvU64 NV_API_CALL os_get_num_phys_pages (void); NV_STATUS NV_API_CALL os_alloc_mem (void **, NvU64); void NV_API_CALL os_free_mem (void *); NV_STATUS NV_API_CALL os_get_current_time (NvU32 *, NvU32 *); @@ -105,7 +104,6 @@ void* NV_API_CALL os_map_kernel_space (NvU64, NvU64, NvU32); void NV_API_CALL os_unmap_kernel_space (void *, NvU64); void* NV_API_CALL os_map_user_space (NvU64, NvU64, NvU32, NvU32, void **); void NV_API_CALL os_unmap_user_space (void *, NvU64, void *); -NV_STATUS NV_API_CALL os_flush_cpu_cache (void); NV_STATUS NV_API_CALL os_flush_cpu_cache_all (void); NV_STATUS NV_API_CALL os_flush_user_cache (void); void NV_API_CALL os_flush_cpu_write_combine_buffer(void); @@ -230,14 +228,12 @@ extern NvBool os_dma_buf_enabled; * --------------------------------------------------------------------------- */ -#define NV_DBG_INFO 0x1 -#define NV_DBG_SETUP 0x2 +#define NV_DBG_INFO 0x0 +#define NV_DBG_SETUP 0x1 +#define NV_DBG_USERERRORS 0x2 #define NV_DBG_WARNINGS 0x3 #define NV_DBG_ERRORS 0x4 -#define NV_DBG_HW_ERRORS 0x5 -#define NV_DBG_FATAL 0x6 -#define NV_DBG_FORCE_LEVEL(level) ((level) | (1 << 8)) void NV_API_CALL out_string(const char *str); int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...); diff --git a/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c index 934bff13a3..e0079e30bc 100644 --- a/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c +++ b/src/nvidia/arch/nvalloc/unix/src/dynamic-power.c @@ -81,6 +81,7 @@ #include #include +#include #include #include "kernel/gpu/intr/intr.h" @@ -1129,8 +1130,8 @@ os_ref_dynamic_power( { default: case NV_DYNAMIC_POWER_STATE_IN_USE: - NV_PRINTF(LEVEL_ERROR, "NVRM: %s: Unexpected dynamic power state 0x%x\n", - __FUNCTION__, old_state); + NV_PRINTF(LEVEL_ERROR, "Unexpected dynamic power state 0x%x\n", + old_state); /* fallthrough */ case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: status = nv_indicate_not_idle(nv); @@ -1482,8 +1483,8 @@ static void timerCallbackForIdlePreConditions( NV_ASSERT(0); /* fallthrough */ case NV_DYNAMIC_POWER_STATE_IDLE_INDICATED: - NV_PRINTF(LEVEL_ERROR, "NVRM: %s: unexpected dynamic power state 0x%x\n", - __FUNCTION__, nvp->dynamic_power.state); + NV_PRINTF(LEVEL_ERROR, "unexpected dynamic power state 0x%x\n", + nvp->dynamic_power.state); /* fallthrough */ case NV_DYNAMIC_POWER_STATE_IN_USE: break; @@ -1740,7 +1741,7 @@ static NV_STATUS CreateDynamicPowerCallbacks( if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "NVRM: Error creating dynamic power precondition check callback\n"); + "Error creating dynamic power precondition check callback\n"); nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; nvp->dynamic_power.indicate_idle_event = NvP64_NULL; nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; @@ -1760,7 +1761,7 @@ static NV_STATUS CreateDynamicPowerCallbacks( if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "NVRM: Error creating callback to indicate GPU idle\n"); + "Error creating callback to indicate GPU idle\n"); nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; nvp->dynamic_power.indicate_idle_event = NvP64_NULL; nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; @@ -1780,7 +1781,7 @@ static NV_STATUS CreateDynamicPowerCallbacks( if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "NVRM: Error creating callback to decrease kernel refcount\n"); + "Error creating callback to decrease kernel refcount\n"); nvp->dynamic_power.idle_precondition_check_event = NvP64_NULL; nvp->dynamic_power.indicate_idle_event = NvP64_NULL; nvp->dynamic_power.remove_idle_holdoff = NvP64_NULL; @@ -1831,7 +1832,7 @@ static void RmScheduleCallbackForIdlePreConditionsUnderGpuLock( } else { - NV_PRINTF(LEVEL_ERROR, "NVRM: Error scheduling precondition callback\n"); + NV_PRINTF(LEVEL_ERROR, "Error scheduling precondition callback\n"); } } } @@ -1893,7 +1894,7 @@ static void RmScheduleCallbackToIndicateIdle( status = tmrCtrlCmdEventSchedule(pGpu, &scheduleEventParams); if (status != NV_OK) - NV_PRINTF(LEVEL_ERROR, "NVRM: Error scheduling indicate idle callback\n"); + NV_PRINTF(LEVEL_ERROR, "Error scheduling indicate idle callback\n"); } } @@ -1928,7 +1929,7 @@ static void RmScheduleCallbackToRemoveIdleHoldoff( if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "NVRM: Error scheduling kernel refcount decrement callback\n"); + "Error scheduling kernel refcount decrement callback\n"); } else { @@ -1956,7 +1957,7 @@ static NvBool RmCheckRtd3GcxSupport( if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED)) { - NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported for this arch\n"); + NV_PRINTF(LEVEL_NOTICE, "RTD3/GC6 is not supported for this arch\n"); return NV_FALSE; } @@ -1974,7 +1975,7 @@ static NvBool RmCheckRtd3GcxSupport( if (!bGC6Support && !bGCOFFSupport) { NV_PRINTF(LEVEL_NOTICE, - "NVRM: Disabling RTD3. [GC6 support=%d GCOFF support=%d]\n", + "Disabling RTD3. [GC6 support=%d GCOFF support=%d]\n", bGC6Support, bGCOFFSupport); return NV_FALSE; } @@ -1986,7 +1987,7 @@ static NvBool RmCheckRtd3GcxSupport( if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, - "NVRM: Failed to get Virtualization mode, status=0x%x\n", + "Failed to get Virtualization mode, status=0x%x\n", status); return NV_FALSE; } @@ -1994,7 +1995,7 @@ static NvBool RmCheckRtd3GcxSupport( if ((virtModeParams.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NONE) && (virtModeParams.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_NMOS)) { - NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported on VM\n"); + NV_PRINTF(LEVEL_NOTICE, "RTD3/GC6 is not supported on VM\n"); return NV_FALSE; } @@ -2025,7 +2026,7 @@ void RmInitDeferredDynamicPowerManagement( { nvp->dynamic_power.mode = NV_DYNAMIC_PM_NEVER; nvp->dynamic_power.b_fine_not_supported = NV_TRUE; - NV_PRINTF(LEVEL_NOTICE, "NVRM: RTD3/GC6 is not supported\n"); + NV_PRINTF(LEVEL_NOTICE, "RTD3/GC6 is not supported\n"); goto unlock; } osAddGpuDynPwrSupported(gpuGetInstance(pGpu)); @@ -2047,7 +2048,7 @@ void RmInitDeferredDynamicPowerManagement( } if (status != NV_OK) - NV_PRINTF(LEVEL_ERROR, "NVRM: Failed to register for dynamic power callbacks\n"); + NV_PRINTF(LEVEL_ERROR, "Failed to register for dynamic power callbacks\n"); } /*! @@ -2262,7 +2263,7 @@ NV_STATUS RmGcxPowerManagement( // GC6 3.0 is possible without AML override but due to changes required // for GCOFF-1.0 in SBIOS & HW, AML override is needed for GC6-3.0 also. // - NV_PRINTF(LEVEL_INFO,"NVRM: AML overrides present in Desktop"); + NV_PRINTF(LEVEL_INFO,"AML overrides present in Desktop"); } nv->d0_state_in_suspend = NV_FALSE; @@ -2382,9 +2383,8 @@ NV_STATUS RmGcxPowerManagement( { status = NV_ERR_NOT_SUPPORTED; NV_PRINTF(LEVEL_ERROR, - "NVRM: %s: System suspend failed with current system suspend configuration. " - "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n", - __FUNCTION__); + "System suspend failed with current system suspend configuration. " + "Please change the system suspend configuration to s2idle in /sys/power/mem_sleep.\n"); } } } @@ -2625,8 +2625,7 @@ void RmHandleDisplayChange( } else NV_PRINTF(LEVEL_ERROR, - "NVRM: %s: Failed to increment dynamic power refcount\n", - __FUNCTION__); + "Failed to increment dynamic power refcount\n"); } } @@ -2727,8 +2726,7 @@ static void RmQueueIdleSustainedWorkitem( if (status != NV_OK) { NV_PRINTF(LEVEL_WARNING, - "NVRM: %s: Failed to queue RmHandleIdleSustained() workitem.\n", - __FUNCTION__); + "Failed to queue RmHandleIdleSustained() workitem.\n"); RmScheduleCallbackForIdlePreConditionsUnderGpuLock(pGpu); return; } diff --git a/src/nvidia/arch/nvalloc/unix/src/escape.c b/src/nvidia/arch/nvalloc/unix/src/escape.c index df36fa7885..c005781b67 100644 --- a/src/nvidia/arch/nvalloc/unix/src/escape.c +++ b/src/nvidia/arch/nvalloc/unix/src/escape.c @@ -52,6 +52,8 @@ #include +#include + #define NV_CTL_DEVICE_ONLY(nv) \ { \ if (((nv)->flags & NV_FLAG_CONTROL) == 0) \ @@ -86,6 +88,9 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd, case NV00FD_CTRL_CMD_ATTACH_GPU: paramSize = sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS); break; + case NV00E0_CTRL_CMD_EXPORT_MEM: + paramSize = sizeof(NV00E0_CTRL_EXPORT_MEM_PARAMS); + break; default: return NV_OK; } @@ -106,6 +111,15 @@ static NV_STATUS RmGetDeviceFd(NVOS54_PARAMETERS *pApi, NvS32 *pFd, *pFd = (NvS32)pAttachGpuParams->devDescriptor; } break; + case NV00E0_CTRL_CMD_EXPORT_MEM: + { + NV00E0_CTRL_EXPORT_MEM_PARAMS *pExportMemParams = pKernelParams; + + // If hParent is client, no need to reference device. + *pSkipDeviceRef = (pExportMemParams->hParent == pApi->hClient); + *pFd = (NvS32)pExportMemParams->devDescriptor; + } + break; default: NV_ASSERT(0); break; diff --git a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c index b5aa0ffa8b..8b37200418 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c +++ b/src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c @@ -46,6 +46,8 @@ #include // NV_PMC_BOOT_1_VGPU #include "nvdevid.h" +#include "g_vgpu_chip_flags.h" // vGPU device names + #define NV_VFIO_PCI_BAR0_REGION_INDEX 0 #define NV_VFIO_PCI_BAR1_REGION_INDEX 1 #define NV_VFIO_PCI_BAR2_REGION_INDEX 2 @@ -63,16 +65,6 @@ NvBool hypervisorIsVgxHyper_IMPL(void) return os_is_vgx_hyper(); } -NvBool hypervisorIsAC_IMPL(void) -{ - return NV_FALSE; -} - -void hypervisorSetACSupported_IMPL(OBJHYPERVISOR *pHypervisor) -{ - pHypervisor->bIsACSupported = NV_TRUE; -} - NV_STATUS hypervisorInjectInterrupt_IMPL ( OBJHYPERVISOR *pHypervisor, @@ -208,7 +200,7 @@ static NV_STATUS get_available_instances( if (!(pKernelVgpuMgr->pgpuInfo[pgpuIndex].createdVfMask & NVBIT64(fnId))) { - if (kvgpumgrCheckVgpuTypeCreatable(&pKernelVgpuMgr->pgpuInfo[pgpuIndex], vgpuTypeInfo) == NV_OK) + if (kvgpumgrCheckVgpuTypeCreatable(pGpu, &pKernelVgpuMgr->pgpuInfo[pgpuIndex], vgpuTypeInfo) == NV_OK) *avail_instances = 1; } } @@ -216,7 +208,7 @@ static NV_STATUS get_available_instances( } else { - if (kvgpumgrCheckVgpuTypeCreatable(&pKernelVgpuMgr->pgpuInfo[pgpuIndex], vgpuTypeInfo) == NV_OK) + if (kvgpumgrCheckVgpuTypeCreatable(pGpu, &pKernelVgpuMgr->pgpuInfo[pgpuIndex], vgpuTypeInfo) == NV_OK) *avail_instances = vgpuTypeInfo->maxInstance - pKernelVgpuMgr->pgpuInfo[pgpuIndex].numCreatedVgpu; } @@ -620,6 +612,16 @@ NV_STATUS NV_API_CALL nv_vgpu_get_bar_info( if (status == NV_OK && value) bOverrideBar1Size = NV_TRUE; } + + if (gpuIsVfResizableBAR1Supported(pGpu)) + { + if ((*size > pGpu->sriovState.vfBarSize[1]) || + (!portStringCompare("Compute", (const char *)vgpuTypeInfo->vgpuClass, 7))) + { + *size = pGpu->sriovState.vfBarSize[1]; + } + } + if (bOverrideBar1Size) { NvU64 bar1SizeInBytes, guestBar1; NvU64 gpuBar1LowerLimit = 256 * 1024 * 1024; // bar1 lower limit for override_bar1_length parameter @@ -856,8 +858,17 @@ NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( numAreas, NULL, NULL); if (rmStatus == NV_OK) { - os_alloc_mem((void **)&vfRegionOffsets, sizeof(NvU64) * (*numAreas)); - os_alloc_mem((void **)&vfRegionSizes, sizeof (NvU64) * (*numAreas)); + rmStatus = os_alloc_mem((void **)&vfRegionOffsets, sizeof(NvU64) * (*numAreas)); + if (rmStatus != NV_OK) + goto cleanup; + + rmStatus = os_alloc_mem((void **)&vfRegionSizes, sizeof (NvU64) * (*numAreas)); + if (rmStatus != NV_OK) + { + os_free_mem(vfRegionOffsets); + goto cleanup; + } + if (vfRegionOffsets && vfRegionSizes) { rmStatus = kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, os_page_size, @@ -867,6 +878,11 @@ NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( *offsets = vfRegionOffsets; *sizes = vfRegionSizes; } + else + { + os_free_mem(vfRegionOffsets); + os_free_mem(vfRegionSizes); + } } else { @@ -916,8 +932,16 @@ NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap( { NvU32 i = 0; NvU64 *tmpOffset, *tmpSize; - os_alloc_mem((void **)offsets, sizeof(NvU64) * (*numAreas)); - os_alloc_mem((void **)sizes, sizeof (NvU64) * (*numAreas)); + rmStatus = os_alloc_mem((void **)offsets, sizeof(NvU64) * (*numAreas)); + if (rmStatus != NV_OK) + goto cleanup; + + rmStatus = os_alloc_mem((void **)sizes, sizeof (NvU64) * (*numAreas)); + if (rmStatus != NV_OK) + { + os_free_mem(*offsets); + goto cleanup; + } tmpOffset = *offsets; tmpSize = *sizes; @@ -1141,7 +1165,6 @@ NV_STATUS osIsVfioPciCorePresent(void) return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VFIO_PCI_CORE_PRESENT); } - void initVGXSpecificRegistry(OBJGPU *pGpu) { NvU32 data32; @@ -1165,12 +1188,14 @@ void initVGXSpecificRegistry(OBJGPU *pGpu) NV_STATUS rm_is_vgpu_supported_device( OS_GPU_INFO *pOsGpuInfo, - NvU32 pmc_boot_1 + NvU32 pmc_boot_1, + NvU32 pmc_boot_42 ) { OBJSYS *pSys = SYS_GET_INSTANCE(); OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); NvBool is_sriov_enabled = FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1); + NvU32 i; // if not running in vGPU mode (guest VM) return NV_OK if (!(pHypervisor && pHypervisor->bIsHVMGuest && @@ -1180,5 +1205,28 @@ NV_STATUS rm_is_vgpu_supported_device( return NV_OK; } - return NV_OK; + if (!is_sriov_enabled) + { + return NV_OK; + } + + if (os_is_grid_supported() && !gpumgrIsVgxRmFirmwareCapableChip(pmc_boot_42)) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (os_is_grid_supported()) + { + for (i = 0; i < NV_ARRAY_ELEMENTS(sVgpuUsmTypes); i++) + { + if (pOsGpuInfo->pci_info.device_id == sVgpuUsmTypes[i].ulDevID && + pOsGpuInfo->subsystem_vendor == sVgpuUsmTypes[i].ulSubSystemVendorID && + pOsGpuInfo->subsystem_id == sVgpuUsmTypes[i].ulSubID) + { + return NV_OK; + } + } + } + + return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c index c994433219..6c547a4922 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os.c +++ b/src/nvidia/arch/nvalloc/unix/src/os.c @@ -34,6 +34,7 @@ #include #include "gpu/gpu.h" +#include #include #include @@ -337,65 +338,6 @@ void osUnmapKernelSpace( os_unmap_kernel_space((void *)ptr, Size); } -void* osMapIOSpace( - RmPhysAddr Start, - NvU64 Size, - void ** pData, - NvU32 User, - NvU32 Mode, - NvU32 Protect -) -{ - - NvU64 offset; - NvU8 *addr; - - if (0 == Size) - { - NV_ASSERT(Size != 0); - return NULL; - } - - offset = (Start & ~os_page_mask); - Start &= os_page_mask; - Size = ((Size + offset + ~os_page_mask) & os_page_mask); - - if (User) - addr = os_map_user_space(Start, Size, Mode, Protect, pData); - else - addr = os_map_kernel_space(Start, Size, Mode); - if (addr != NULL) - return (addr + offset); - - return addr; -} - -void osUnmapIOSpace( - void *pAddress, - NvU64 Size, - void *pData, - NvU32 User -) -{ - NvU64 offset; - NvUPtr addr = (NvUPtr)pAddress; - - if (0 == Size) - { - NV_ASSERT(Size != 0); - return; - } - - offset = (addr & ~os_page_mask); - addr &= os_page_mask; - Size = ((Size + offset + ~os_page_mask) & os_page_mask); - - if (User) - os_unmap_user_space((void *)addr, Size, pData); - else - os_unmap_kernel_space((void *)addr, Size); -} - static NV_STATUS setNumaPrivData ( KernelMemorySystem *pKernelMemorySystem, @@ -406,36 +348,33 @@ static NV_STATUS setNumaPrivData NV_STATUS rmStatus = NV_OK; void *pAllocPrivate = NULL; NvU64 *addrArray = NULL; - NvU64 numOsPages = pMemDesc->PageCount; - - addrArray = pMemDesc->_pteArray; + NvU64 numPages = pMemDesc->PageCount; + NvU64 i; - if (NV_RM_PAGE_SIZE < os_page_size) + addrArray = portMemAllocNonPaged(numPages * sizeof(NvU64)); + if (addrArray == NULL) { - NvU64 numPages; - NvU64 i; + return NV_ERR_NO_MEMORY; + } - numPages = pMemDesc->PageCount; - addrArray = portMemAllocNonPaged(numPages * sizeof(NvU64)); - if (addrArray == NULL) - { - return NV_ERR_NO_MEMORY; - } + portMemCopy((void*)addrArray, + (numPages * sizeof(NvU64)), + (void*)memdescGetPteArray(pMemDesc, AT_CPU), + (numPages * sizeof(NvU64))); - portMemCopy((void*)addrArray, - (numPages * sizeof(NvU64)), (void*)pMemDesc->_pteArray, - (numPages * sizeof(NvU64))); + if (NV_RM_PAGE_SIZE < os_page_size) + { RmDeflateRmToOsPageArray(addrArray, numPages); - numOsPages = NV_RM_PAGES_TO_OS_PAGES(numPages); + numPages = NV_RM_PAGES_TO_OS_PAGES(numPages); + } - for (i = 0; i < numOsPages; i++) - { - // Update GPA to system physical address - addrArray[i] += pKernelMemorySystem->coherentCpuFbBase; - } + for (i = 0; i < numPages; i++) + { + // Update GPA to system physical address + addrArray[i] += pKernelMemorySystem->coherentCpuFbBase; } - rmStatus = nv_register_phys_pages(nv, addrArray, numOsPages, NV_MEMORY_CACHED, &pAllocPrivate); + rmStatus = nv_register_phys_pages(nv, addrArray, numPages, NV_MEMORY_CACHED, &pAllocPrivate); if (rmStatus != NV_OK) { goto errors; @@ -444,10 +383,7 @@ static NV_STATUS setNumaPrivData memdescSetMemData(pMemDesc, pAllocPrivate, NULL); errors: - if (NV_RM_PAGE_SIZE < os_page_size) - { - portMemFree(addrArray); - } + portMemFree(addrArray); return rmStatus; } @@ -851,32 +787,6 @@ static inline nv_dma_device_t* osGetDmaDeviceForMemDesc( pOsGpuInfo->niso_dma_dev : pOsGpuInfo->dma_dev; } -NV_STATUS osDmaMapPages( - OS_GPU_INFO *pOsGpuInfo, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - return nv_dma_map_pages( - osGetDmaDeviceForMemDesc(pOsGpuInfo, pMemDesc), - NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), - memdescGetPteArray(pMemDesc, AT_CPU), - memdescGetContiguity(pMemDesc, AT_CPU), - memdescGetCpuCacheAttrib(pMemDesc), - NULL); -} - -NV_STATUS osDmaUnmapPages( - OS_GPU_INFO *pOsGpuInfo, - MEMORY_DESCRIPTOR *pMemDesc -) -{ - return nv_dma_unmap_pages( - pOsGpuInfo->dma_dev, - NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount), - memdescGetPteArray(pMemDesc, AT_CPU), - NULL); -} - // // Set the DMA address size for the given GPU // @@ -1061,14 +971,21 @@ NV_STATUS osMapPciMemoryUser( ) { void *addr; - void *priv = NULL; + NvU64 offset = 0; + + NV_ASSERT_OR_RETURN(length != 0, NV_ERR_INVALID_ARGUMENT); + + offset = busAddress & (os_page_size - 1llu); + busAddress = NV_ALIGN_DOWN64(busAddress, os_page_size); + length = NV_ALIGN_UP64(busAddress + offset + length, os_page_size) - busAddress; - addr = osMapIOSpace(busAddress, length, &priv, NV_TRUE, modeFlag, Protect); + addr = os_map_user_space(busAddress, length, modeFlag, Protect, (void **) pPriv); - *pPriv = NV_PTR_TO_NvP64(priv); - *pVirtualAddress = NV_PTR_TO_NvP64(addr); + NV_ASSERT_OR_RETURN(addr != NULL, NV_ERR_INVALID_ADDRESS); - return (addr != NULL) ? NV_OK : NV_ERR_GENERIC; + *pVirtualAddress = (NvP64)(((NvU64) addr) + offset); + + return NV_OK; } void osUnmapPciMemoryUser( @@ -1078,12 +995,17 @@ void osUnmapPciMemoryUser( NvP64 pPriv ) { - void *addr, *priv; + NvU64 addr; + void *priv; - addr = NvP64_VALUE(virtualAddress); - priv = NvP64_VALUE(pPriv); + addr = (NvU64)(virtualAddress); + priv = (void*)(pPriv); - osUnmapIOSpace(addr, length, priv, NV_TRUE); + length = NV_ALIGN_UP64(addr + length, os_page_size); + addr = NV_ALIGN_DOWN64(addr, os_page_size); + length -= addr; + + os_unmap_user_space((void *)addr, length, priv); } NV_STATUS osMapPciMemoryKernelOld @@ -3819,7 +3741,7 @@ osGetAtsTargetAddressRange } else { - NV_STATUS status = nv_get_device_memory_config(nv, pAddrSysPhys, NULL, + NV_STATUS status = nv_get_device_memory_config(nv, pAddrSysPhys, NULL, NULL, pAddrWidth, NULL); if (status == NV_OK) { @@ -3856,6 +3778,7 @@ osGetFbNumaInfo ( OBJGPU *pGpu, NvU64 *pAddrPhys, + NvU64 *pAddrRsvdPhys, NvS32 *pNodeId ) { @@ -3871,7 +3794,8 @@ osGetFbNumaInfo nv = NV_GET_NV_STATE(pGpu); - NV_STATUS status = nv_get_device_memory_config(nv, NULL, pAddrPhys, NULL, pNodeId); + NV_STATUS status = nv_get_device_memory_config(nv, NULL, pAddrPhys, + pAddrRsvdPhys, NULL, pNodeId); return status; #endif @@ -4146,7 +4070,7 @@ osNumaOnliningEnabled // Note that this numaNodeId value fetched from Linux layer might not be // accurate since it is possible to overwrite it with regkey on some configs // - if (nv_get_device_memory_config(pOsGpuInfo, NULL, NULL, NULL, + if (nv_get_device_memory_config(pOsGpuInfo, NULL, NULL, NULL, NULL, &numaNodeId) != NV_OK) { return NV_FALSE; @@ -4724,7 +4648,8 @@ osRmCapRelease #define OS_RM_CAP_SYS_MIG_DIR 0 #define OS_RM_CAP_SYS_SMC_CONFIG_FILE 1 #define OS_RM_CAP_SYS_SMC_MONITOR_FILE 2 -#define OS_RM_CAP_SYS_COUNT 3 +#define OS_RM_CAP_SYS_FABRIC_IMEX_MGMT_FILE 3 +#define OS_RM_CAP_SYS_COUNT 4 NV_STATUS osRmCapRegisterSys @@ -4776,6 +4701,15 @@ osRmCapRegisterSys } ppCaps[OS_RM_CAP_SYS_SMC_MONITOR_FILE] = cap; + cap = os_nv_cap_create_file_entry(nvidia_caps_root, "fabric-imex-mgmt", OS_RUSR); + if (cap == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create imex file\n"); + status = NV_ERR_OPERATING_SYSTEM; + goto failed; + } + ppCaps[OS_RM_CAP_SYS_FABRIC_IMEX_MGMT_FILE] = cap; + return NV_OK; failed: @@ -4844,6 +4778,11 @@ osRmCapAcquire index = OS_RM_CAP_SYS_SMC_MONITOR_FILE; break; } + case NV_RM_CAP_SYS_FABRIC_IMEX_MGMT: + { + index = OS_RM_CAP_SYS_FABRIC_IMEX_MGMT_FILE; + break; + } default: { return NV_ERR_INVALID_ARGUMENT; diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c index 3d88348b36..eae43ed445 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osapi.c +++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c @@ -737,7 +737,10 @@ static NV_STATUS RmAccessRegistry( RM_LOCK_MODULES_GPU, &gpuMask); if (RmStatus != NV_OK) - return RmStatus; + { + gpuMask = 0; + goto done; + } GPU_RES_SET_THREAD_BC_STATE(pSubdevice); pGpu = GPU_RES_GET_GPU(pSubdevice); @@ -750,7 +753,10 @@ static NV_STATUS RmAccessRegistry( RM_LOCK_MODULES_GPU, &gpuMask); if (RmStatus != NV_OK) - return RmStatus; + { + gpuMask = 0; + goto done; + } GPU_RES_SET_THREAD_BC_STATE(pDevice); pGpu = GPU_RES_GET_GPU(pDevice); @@ -1442,6 +1448,117 @@ RmDmabufPutClientAndDevice( NV_ASSERT_OK(kmigmgrDecRefCount(pKernelMIGGpuInstance->pShare)); } +static NV_STATUS RmP2PDmaMapPagesCoherent( + nv_dma_device_t *peer, + NvU64 pageSize, + NvU32 pageCount, + NvU64 *pDmaAddresses, + void **ppPriv +) +{ + NV_STATUS status; + NvU64 *pOsDmaAddresses = NULL; + NvU32 osPagesPerP2PPage, osPageCount, count; + NvBool bDmaMapped = NV_FALSE; + NvU32 i, j, index; + + NV_ASSERT_OR_RETURN((pageSize >= os_page_size), NV_ERR_INVALID_ARGUMENT); + + if (pageSize == os_page_size) + { + return nv_dma_map_alloc(peer, pageCount, pDmaAddresses, NV_FALSE, ppPriv); + } + + // + // If P2P page_size returned from nvidia_p2p_get_pages is bigger than + // OS page size, the page array need to be inflated to correctly do the DMA mapping. + // For example, if page_size = 64K and OS page size = 4K, + // there are 16 OS pages to this 64K P2P page. + // + + osPagesPerP2PPage = pageSize / os_page_size; + osPageCount = osPagesPerP2PPage * pageCount; + + status = os_alloc_mem((void **)&pOsDmaAddresses, + (osPageCount * sizeof(NvU64))); + if (status != NV_OK) + { + goto failed; + } + + index = 0; + for (i = 0; i < pageCount; i++) + { + pOsDmaAddresses[index] = pDmaAddresses[i]; + index++; + + for (j = 1; j < osPagesPerP2PPage; j++) + { + pOsDmaAddresses[index] = pOsDmaAddresses[index - 1] + os_page_size; + index++; + } + } + + status = nv_dma_map_alloc(peer, osPageCount, pOsDmaAddresses, NV_FALSE, ppPriv); + if (status != NV_OK) + { + goto failed; + } + bDmaMapped = NV_TRUE; + + // + // The driver breaks down the size into submaps and dma-maps those individually. + // This may result in non-contiguous IOVA segments allocated to each submap. + // We check for OS page contiguity within the bigger pageSize since we need to + // return IOVA chunks at pageSize granularity. + // + count = 0; + for (i = 1; i < osPageCount; i++) + { + count++; + if (count == osPagesPerP2PPage) + { + count = 0; + continue; + } + + if (pOsDmaAddresses[i] != (pOsDmaAddresses[i - 1] + os_page_size)) + { + status = NV_ERR_INVALID_STATE; + goto failed; + } + } + + // + // Fill pDmaAddresses at pageSize granularity + // from expanded pOsDmaAddresses. + // + index = 0; + for (i = 0; i < pageCount; i++) + { + pDmaAddresses[i] = pOsDmaAddresses[index]; + index += osPagesPerP2PPage; + } + + os_free_mem(pOsDmaAddresses); + + return NV_OK; + +failed: + if (bDmaMapped) + { + NV_ASSERT_OK(nv_dma_unmap_alloc(peer, osPageCount, + pOsDmaAddresses, ppPriv)); + } + + if (pOsDmaAddresses != NULL) + { + os_free_mem(pOsDmaAddresses); + } + + return status; +} + static void RmHandleNvpcfEvents( nv_state_t *pNv @@ -1913,13 +2030,13 @@ static NV_STATUS RmSetUserMapAccessRange( return status; } -static NV_STATUS RmGetAllocPrivate(NvU32, NvU32, NvU64, NvU64, NvU32 *, void **, +static NV_STATUS RmGetAllocPrivate(RmClient *, NvU32, NvU64, NvU64, NvU32 *, void **, NvU64 *); static NV_STATUS RmValidateMmapRequest(nv_state_t *, NvU64, NvU64, NvU32 *); static NV_STATUS RmGetMmapPteArray( KernelMemorySystem *pKernelMemorySystem, - NvHandle hClient, + RsClient *pClient, NvHandle hMemory, nv_usermap_access_params_t *nvuap ) @@ -1942,12 +2059,14 @@ static NV_STATUS RmGetMmapPteArray( // If we're mapping a memory handle, we can get the data from the // descriptor (required if the allocation being mapped is discontiguous). // - if (serverutilGetResourceRefWithType(hClient, hMemory, classId(Memory), - &pResourceRef) == NV_OK) + if (clientGetResourceRef(pClient, hMemory, &pResourceRef) == NV_OK) { pMemory = dynamicCast(pResourceRef->pResource, Memory); - pMemDesc = pMemory->pMemDesc; - nvuap->contig = memdescGetContiguity(pMemDesc, AT_CPU); + if (pMemory != NULL) + { + pMemDesc = pMemory->pMemDesc; + nvuap->contig = memdescGetContiguity(pMemDesc, AT_CPU); + } } // @@ -2018,7 +2137,7 @@ static NV_STATUS RmGetMmapPteArray( /* Must be called with the API lock and the GPU locks */ static NV_STATUS RmCreateMmapContextLocked( - NvHandle hClient, + RmClient *pRmClient, NvHandle hDevice, NvHandle hMemory, NvP64 address, @@ -2031,6 +2150,7 @@ static NV_STATUS RmCreateMmapContextLocked( NV_STATUS status = NV_OK; void *pAllocPriv = NULL; OBJGPU *pGpu = NULL; + RsClient *pClient = staticCast(pRmClient, RsClient); KernelMemorySystem *pKernelMemorySystem = NULL; NvBool bCoherentAtsCpuOffset = NV_FALSE; nv_state_t *pNv = NULL; @@ -2038,19 +2158,14 @@ static NV_STATUS RmCreateMmapContextLocked( NvU32 prot = 0; NvU64 pageIndex = 0; nv_usermap_access_params_t *nvuap = NULL; - NvBool bClientMap = (hClient == hDevice); + NvBool bClientMap = (pClient->hClient == hDevice); if (!bClientMap) { - if (CliSetGpuContext(hClient, hDevice, &pGpu, NULL) != NV_OK) + if (CliSetGpuContext(pClient->hClient, hDevice, &pGpu, NULL) != NV_OK) { - RsClient *pClient; Subdevice *pSubdevice; - status = serverGetClientUnderLock(&g_resServ, hClient, &pClient); - if (status != NV_OK) - return status; - status = subdeviceGetByHandle(pClient, hDevice, &pSubdevice); if (status != NV_OK) return status; @@ -2104,7 +2219,7 @@ static NV_STATUS RmCreateMmapContextLocked( // Validate the mapping request by looking up the underlying sysmem // allocation. // - status = RmGetAllocPrivate(hClient, hMemory, addr, size, &prot, &pAllocPriv, + status = RmGetAllocPrivate(pRmClient, hMemory, addr, size, &prot, &pAllocPriv, &pageIndex); if (status != NV_OK) @@ -2119,7 +2234,7 @@ static NV_STATUS RmCreateMmapContextLocked( // if (bCoherentAtsCpuOffset) { - status = RmGetMmapPteArray(pKernelMemorySystem, hClient, hMemory, nvuap); + status = RmGetMmapPteArray(pKernelMemorySystem, pClient, hMemory, nvuap); if (status != NV_OK) { goto done; @@ -2170,25 +2285,30 @@ NV_STATUS rm_create_mmap_context( // LOCK: acquire API lock if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) == NV_OK) { - RmClient *pClient; + RmClient *pRmClient; - if (NV_OK != serverutilAcquireClient(hClient, LOCK_ACCESS_READ, &pClient)) + if (NV_OK != serverutilAcquireClient(hClient, LOCK_ACCESS_READ, &pRmClient)) + { + // UNLOCK: release API lock + rmapiLockRelease(); return NV_ERR_INVALID_CLIENT; + } - if (pClient->ProcID != osGetCurrentProcess()) + if (pRmClient->ProcID != osGetCurrentProcess()) { rmStatus = NV_ERR_INVALID_CLIENT; } // LOCK: acquire GPUs lock else if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) == NV_OK) { - rmStatus = RmCreateMmapContextLocked(hClient, hDevice, hMemory, - address, size, offset, cachingType, fd); + rmStatus = RmCreateMmapContextLocked(pRmClient, hDevice, + hMemory, address, size, offset, + cachingType, fd); // UNLOCK: release GPUs lock rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); } - serverutilReleaseClient(LOCK_ACCESS_READ, pClient); + serverutilReleaseClient(LOCK_ACCESS_READ, pRmClient); // UNLOCK: release API lock rmapiLockRelease(); @@ -2198,7 +2318,7 @@ NV_STATUS rm_create_mmap_context( } static NV_STATUS RmGetAllocPrivate( - NvU32 hClient, + RmClient *pRmClient, NvU32 hMemory, NvU64 offset, NvU64 length, @@ -2207,7 +2327,6 @@ static NV_STATUS RmGetAllocPrivate( NvU64 *pPageIndex ) { - RmClient *pClient; NV_STATUS rmStatus; PMEMORY_DESCRIPTOR pMemDesc; NvU32 pageOffset; @@ -2226,10 +2345,8 @@ static NV_STATUS RmGetAllocPrivate( NV_ASSERT_OR_RETURN(rmapiLockIsOwner(), NV_ERR_INVALID_LOCK_STATE); - if (NV_OK != serverutilAcquireClient(hClient, LOCK_ACCESS_READ, &pClient)) - return NV_ERR_INVALID_CLIENT; - - rmStatus = clientGetResourceRef(staticCast(pClient, RsClient), hMemory, &pResourceRef); + rmStatus = clientGetResourceRef(staticCast(pRmClient, RsClient), + hMemory, &pResourceRef); if (rmStatus != NV_OK) goto done; @@ -2301,8 +2418,6 @@ static NV_STATUS RmGetAllocPrivate( *ppPrivate = pMemData; done: - serverutilReleaseClient(LOCK_ACCESS_READ, pClient); - return rmStatus; } @@ -2358,6 +2473,26 @@ NV_STATUS rm_get_adapter_status( return rmStatus; } +NV_STATUS NV_API_CALL rm_get_adapter_status_external( + nvidia_stack_t *sp, + nv_state_t *pNv +) +{ + NV_STATUS rmStatus; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); + + if (rm_get_adapter_status(pNv, &rmStatus) != NV_OK) + { + rmStatus = NV_ERR_OPERATING_SYSTEM; + } + + NV_EXIT_RM_RUNTIME(sp,fp); + + return rmStatus; +} + NvBool NV_API_CALL rm_init_rm( nvidia_stack_t *sp ) @@ -3388,27 +3523,55 @@ NV_STATUS NV_API_CALL rm_is_supported_device( NULL); if (!bIsFirmwareCapable) { - nv_printf(NV_DBG_ERRORS, - "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" - "NVRM: installed in this system is not supported by open\n" - "NVRM: nvidia.ko because it does not include the required GPU\n" - "NVRM: System Processor (GSP).\n" - "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" - "NVRM: Firmware' sections in the driver README, available on\n" - "NVRM: the Linux graphics driver download page at\n" - "NVRM: www.nvidia.com.\n", - pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, - pNv->pci_info.function, pNv->pci_info.vendor_id, - pNv->pci_info.device_id, NV_VERSION_STRING); + if (hypervisorIsVgxHyper()) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this vGPU host system is not supported by\n" + "NVRM: open nvidia.ko.\n" + "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" + "NVRM: Firmware' sections in the NVIDIA Virtual GPU (vGPU)\n" + "NVRM: Software documentation, available at docs.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id, NV_VERSION_STRING); + } + else + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this system is not supported by open\n" + "NVRM: nvidia.ko because it does not include the required GPU\n" + "NVRM: System Processor (GSP).\n" + "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" + "NVRM: Firmware' sections in the driver README, available on\n" + "NVRM: the Linux graphics driver download page at\n" + "NVRM: www.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id, NV_VERSION_STRING); + } goto threadfree; } goto print_unsupported; } - rmStatus = rm_is_vgpu_supported_device(pNv, pmc_boot_1); + rmStatus = rm_is_vgpu_supported_device(pNv, pmc_boot_1, pmc_boot_42); if (rmStatus != NV_OK) - goto print_unsupported; + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA vGPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this system is not supported by open\n" + "NVRM: nvidia.ko.\n" + "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" + "NVRM: Firmware' sections in the NVIDIA Virtual GPU (vGPU)\n" + "NVRM: Software documentation, available at docs.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id, NV_VERSION_STRING); + goto threadfree; + } goto threadfree; print_unsupported: @@ -3855,8 +4018,12 @@ void RmI2cAddGpuPorts(nv_state_t * pNv) RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); NvU32 displayMask; NV_STATUS status; + OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv); NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS systemGetSupportedParams = { 0 }; + if (IS_VIRTUAL(pGpu)) + return; + // Make displayId as Invalid. for (x = 0; x < MAX_I2C_ADAPTERS; x++) { @@ -4233,10 +4400,8 @@ NV_STATUS NV_API_CALL rm_p2p_dma_map_pages( if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) { - NV_ASSERT(pageSize == os_page_size); - - rmStatus = nv_dma_map_alloc(peer, pageCount, pDmaAddresses, - NV_FALSE, ppPriv); + rmStatus = RmP2PDmaMapPagesCoherent(peer, pageSize, pageCount, + pDmaAddresses, ppPriv); } else { @@ -4611,6 +4776,47 @@ static void rm_set_firmware_logs( NV_EXIT_RM_RUNTIME(sp,fp); } +static NvBool rm_get_is_gsp_capable_vgpu( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + void *fp; + THREAD_STATE_NODE threadState; + NvBool isVgpu = NV_FALSE; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if ((pHypervisor != NULL) && pHypervisor->bIsHVMGuest) + { + GPUHWREG *reg_mapping; + reg_mapping = osMapKernelSpace(nv->regs->cpu_address, + os_page_size, + NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + + if (reg_mapping != NULL) + { + NvU32 pmc_boot_1 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_1); + NvU32 pmc_boot_42 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_42); + + osUnmapKernelSpace(reg_mapping, os_page_size); + + if (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1) && + gpumgrIsVgxRmFirmwareCapableChip(pmc_boot_42)) + { + isVgpu = NV_TRUE; + } + } + } + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return isVgpu; +} + void NV_API_CALL rm_set_rm_firmware_requested( nvidia_stack_t *sp, nv_state_t *nv @@ -4618,6 +4824,10 @@ void NV_API_CALL rm_set_rm_firmware_requested( { nv->request_firmware = NV_TRUE; nv->allow_fallback_to_monolithic_rm = NV_FALSE; + if (rm_get_is_gsp_capable_vgpu(sp, nv)) + { + nv->request_firmware = NV_FALSE; + } // Check if we want firmware logs if (nv->request_firmware) diff --git a/src/nvidia/arch/nvalloc/unix/src/osinit.c b/src/nvidia/arch/nvalloc/unix/src/osinit.c index 97bc1d9133..55f7ca4741 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osinit.c +++ b/src/nvidia/arch/nvalloc/unix/src/osinit.c @@ -103,6 +103,7 @@ typedef enum RM_INIT_GPU_LOAD_FAILED, RM_INIT_GPU_UNIVERSAL_VALIDATION_FAILED, RM_INIT_GPU_DMA_CONFIGURATION_FAILED, + RM_INIT_GPU_GPUMGR_EXPANDED_VISIBILITY_FAILED, /* vbios errors */ RM_INIT_VBIOS_FAILED = 0x30, @@ -190,7 +191,6 @@ static void initUnixSpecificRegistry(OBJGPU *); NvBool osRmInitRm(OBJOS *pOS) { OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU64 system_memory_size = (NvU64)-1; NV_PRINTF(LEVEL_INFO, "init rm\n"); @@ -274,13 +274,6 @@ NvBool osRmInitRm(OBJOS *pOS) return NV_FALSE; } - system_memory_size = NV_RM_PAGES_PER_OS_PAGE * os_get_num_phys_pages(); - - // if known, relay the number of system memory pages (in terms of RM page - // size) to the RM; this is needed for e.g. TurboCache parts. - if (system_memory_size != (NvU64)-1) - pOS->SystemMemorySize = system_memory_size; - // Setup any ThreadState defaults threadStateInitSetupFlags(THREAD_STATE_SETUP_FLAGS_ENABLED | THREAD_STATE_SETUP_FLAGS_TIMEOUT_ENABLED | @@ -420,6 +413,126 @@ osHandleGpuLost return NV_OK; } +/*! + * @brief Traverse bus topology till Gpu's root port. + * If any of the intermediate bridge has TB3 supported vendorId and hotplug + * capability(not necessarily same bridge), mark the Gpu as External Gpu. + * + * @params[in] pGpu OBJGPU pointer + * @params[in] pCl OBJCL pointer + * +* @return NV_OK +* Identified to be eGPU +* @return others + * Not an eGPU / error on identfying + * + */ +NvBool +RmCheckForExternalGpu +( + OBJGPU *pGpu, + OBJCL *pCl +) +{ + NvU8 bus; + NvU32 domain; + void *handleUp; + NvU8 busUp, devUp, funcUp; + NvU16 vendorIdUp, deviceIdUp; + NvU32 portCaps, pciCaps, slotCaps; + NvU32 PCIECapPtr; + RM_API *pRmApi; + NV_STATUS status, rmStatus; + NvBool bTb3Bridge = NV_FALSE, bSlotHotPlugSupport = NV_FALSE; + NvBool iseGPUBridge = NV_FALSE; + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + domain = gpuGetDomain(pGpu); + bus = gpuGetBus(pGpu); + do + { + // Find the upstream bridge + handleUp = clFindP2PBrdg(pCl, domain, bus, &busUp, &devUp, &funcUp, &vendorIdUp, &deviceIdUp); + if (!handleUp) + { + return iseGPUBridge; + } + + if (vendorIdUp == PCI_VENDOR_ID_INTEL) + { + // Check for the supported TB3(ThunderBolt 3) bridges. + NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS params = { 0 }; + + // LOCK: acquire GPUs lock + rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_INIT); + if (rmStatus != NV_OK) + { + return iseGPUBridge; + } + params.pciDeviceId = deviceIdUp; + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GET_EGPU_BRIDGE_INFO, + ¶ms, + sizeof(params)); + // UNLOCK: release GPUs lock + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error 0x%08x on eGPU Approval for Bridge ID: 0x%08x\n", status, deviceIdUp); + DBG_BREAKPOINT(); + return iseGPUBridge; + } + else + { + // Check for the approved eGPU BUS TB3 + if (params.iseGPUBridge && + params.approvedBusType == NV2080_CTRL_INTERNAL_EGPU_BUS_TYPE_TB3) + { + bTb3Bridge = NV_TRUE; + } + } + } + + if (NV_OK != clSetPortPcieCapOffset(pCl, handleUp, &PCIECapPtr)) + { + // PCIE bridge but no cap pointer. + break; + } + + // Get the PCIE capabilities. + pciCaps = osPciReadDword(handleUp, CL_PCIE_CAP - CL_PCIE_BEGIN + PCIECapPtr); + if (CL_PCIE_CAP_SLOT & pciCaps) + { + // Get the slot capabilities. + slotCaps = osPciReadDword(handleUp, CL_PCIE_SLOT_CAP - CL_PCIE_BEGIN + PCIECapPtr); + + if ((CL_PCIE_SLOT_CAP_HOTPLUG_CAPABLE & slotCaps) && + (CL_PCIE_SLOT_CAP_HOTPLUG_SURPRISE & slotCaps)) + { + bSlotHotPlugSupport = NV_TRUE; + } + } + + if (bTb3Bridge && bSlotHotPlugSupport) + { + iseGPUBridge = NV_TRUE; + break; + } + + bus = busUp; + + // Get port caps to check if PCIE bridge is the root port + portCaps = osPciReadDword(handleUp, CL_PCIE_CAP - CL_PCIE_BEGIN + PCIECapPtr); + + } while (!CL_IS_ROOT_PORT(portCaps)); + return iseGPUBridge; +} + /* * Initialize the required GPU information by doing RMAPI control calls * and store the same in the UNIX specific data structures. @@ -532,6 +645,8 @@ osInitNvMapping( nv_priv_t *nvp = NV_GET_NV_PRIV(nv); NvU32 deviceInstance; NvU32 data = 0; + NvU32 dispIsoStreamId; + NvU32 dispNisoStreamId; NV_PRINTF(LEVEL_INFO, "osInitNvMapping:\n"); @@ -550,8 +665,6 @@ osInitNvMapping( { NV_PRINTF(LEVEL_ERROR, "*** cannot allocate GPU lock\n"); RM_SET_ERROR(*status, RM_INIT_GPU_GPUMGR_ALLOC_GPU_FAILED); - // RM_BASIC_LOCK_MODEL: free GPU lock - rmGpuLockFree(*pDeviceReference); return; } @@ -610,6 +723,7 @@ osInitNvMapping( gpuAttachArg->instLength = nv->bars[NV_GPU_BAR_INDEX_IMEM].size; gpuAttachArg->iovaspaceId = nv->iovaspace_id; + gpuAttachArg->cpuNumaNodeId = nv->cpu_numa_node_id; } // @@ -703,6 +817,17 @@ osInitNvMapping( nv->preserve_vidmem_allocations = NV_TRUE; } + + // Check if SMMU can be enabled on PushBuffer Aperture + nv_get_disp_smmu_stream_ids(nv, &dispIsoStreamId, &dispNisoStreamId); + if (dispNisoStreamId != NV_U32_MAX) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS, NV_FALSE); + } + else + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS, NV_TRUE); + } } void osInitScalabilityOptions @@ -746,21 +871,6 @@ osTeardownScalability( return clTeardownPcie(pGpu, pCl); } -static void -populateDeviceAttributes( - OBJGPU *pGpu, - nv_state_t *nv -) -{ - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJCL *pCl = SYS_GET_CL(pSys); - - if ((pCl != NULL) && pCl->getProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU)) - { - nv->is_external_gpu = NV_TRUE; - } -} - static void RmSetConsolePreservationParams(OBJGPU *pGpu) { @@ -883,6 +993,8 @@ RmInitNvDevice( { // set the device context OBJGPU *pGpu = gpumgrGetGpu(deviceReference); + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJCL *pCl = SYS_GET_CL(pSys); nv_state_t *nv = NV_GET_NV_STATE(pGpu); nv_priv_t *nvp = NV_GET_NV_PRIV(nv); @@ -900,14 +1012,17 @@ RmInitNvDevice( return; } - os_disable_console_access(); - + // Configure eGPU setting + if (RmCheckForExternalGpu(pGpu, pCl)) + { + pCl->setProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU, NV_TRUE); + nv->is_external_gpu = NV_TRUE; + } status->rmStatus = gpumgrStateInitGpu(pGpu); if (status->rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "*** Cannot initialize the device\n"); RM_SET_ERROR(*status, RM_INIT_GPU_STATE_INIT_FAILED); - os_enable_console_access(); return; } nvp->flags |= NV_INIT_FLAG_GPU_STATE; @@ -937,13 +1052,10 @@ RmInitNvDevice( NV_PRINTF(LEVEL_ERROR, "*** Cannot load state into the device\n"); RM_SET_ERROR(*status, RM_INIT_GPU_LOAD_FAILED); - os_enable_console_access(); return; } nvp->flags |= NV_INIT_FLAG_GPU_STATE_LOAD; - os_enable_console_access(); - status->rmStatus = gpuPerformUniversalValidation_HAL(pGpu); if (status->rmStatus != NV_OK) { @@ -1160,6 +1272,7 @@ NvBool RmInitPrivateState( nv_priv_t *nvp; NvU32 gpuId; NvU32 pmc_boot_0 = 0; + NvU32 pmc_boot_1 = 0; NvU32 pmc_boot_42 = 0; NV_SET_NV_PRIV(pNv, NULL); @@ -1177,6 +1290,7 @@ NvBool RmInitPrivateState( } pmc_boot_0 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_0); + pmc_boot_1 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_1); pmc_boot_42 = NV_PRIV_REG_RD32(pNv->regs->map_u, NV_PMC_BOOT_42); os_unmap_kernel_space(pNv->regs->map_u, os_page_size); @@ -1204,6 +1318,7 @@ NvBool RmInitPrivateState( pNv->iovaspace_id = nv_requires_dma_remap(pNv) ? gpuId : NV_IOVA_DOMAIN_NONE; + pNv->cpu_numa_node_id = NV0000_CTRL_NO_NUMA_NODE; kvgpumgrAttachGpu(pNv->gpu_id); @@ -1216,6 +1331,7 @@ NvBool RmInitPrivateState( os_mem_set(nvp, 0, sizeof(*nvp)); nvp->status = NV_ERR_INVALID_STATE; nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_1 = pmc_boot_1; nvp->pmc_boot_42 = pmc_boot_42; NV_SET_NV_PRIV(pNv, nvp); @@ -1234,7 +1350,7 @@ void RmClearPrivateState( nv_i2c_adapter_entry_t i2c_adapters[MAX_I2C_ADAPTERS]; nv_dynamic_power_t dynamicPowerCopy; NvU32 x = 0; - NvU32 pmc_boot_0, pmc_boot_42; + NvU32 pmc_boot_0, pmc_boot_1, pmc_boot_42; // // Do not clear private state after GPU resets, it is used while @@ -1252,6 +1368,7 @@ void RmClearPrivateState( pRegistryCopy = nvp->pRegistry; dynamicPowerCopy = nvp->dynamic_power; pmc_boot_0 = nvp->pmc_boot_0; + pmc_boot_1 = nvp->pmc_boot_1; pmc_boot_42 = nvp->pmc_boot_42; for (x = 0; x < MAX_I2C_ADAPTERS; x++) @@ -1267,6 +1384,7 @@ void RmClearPrivateState( nvp->pRegistry = pRegistryCopy; nvp->dynamic_power = dynamicPowerCopy; nvp->pmc_boot_0 = pmc_boot_0; + nvp->pmc_boot_1 = pmc_boot_1; nvp->pmc_boot_42 = pmc_boot_42; for (x = 0; x < MAX_I2C_ADAPTERS; x++) @@ -1537,6 +1655,7 @@ NvBool RmInitAdapter( KernelDisplay *pKernelDisplay; const void *gspFwHandle = NULL; const void *gspFwLogHandle = NULL; + NvBool consoleDisabled = NV_FALSE; GSP_FIRMWARE gspFw = {0}; PORT_UNREFERENCED_VARIABLE(gspFw); @@ -1580,6 +1699,17 @@ NvBool RmInitAdapter( } } + // + // Initialization path requires expanded GPU visibility in GPUMGR + // in order to access the GPU undergoing initialization. + // + status.rmStatus = gpumgrThreadEnableExpandedGpuVisibility(); + if (status.rmStatus != NV_OK) + { + RM_SET_ERROR(status, RM_INIT_GPU_GPUMGR_EXPANDED_VISIBILITY_FAILED); + goto shutdown; + } + // initialize the RM device register mapping osInitNvMapping(nv, &devicereference, &status); if (! RM_INIT_SUCCESS(status.initStatus) ) @@ -1616,7 +1746,7 @@ NvBool RmInitAdapter( KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); if ((pKernelFsp != NULL) && !IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu)) { - status.rmStatus = kfspSendBootCommands_HAL(pGpu, pKernelFsp); + status.rmStatus = kfspPrepareAndSendBootCommands_HAL(pGpu, pKernelFsp); if (status.rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, "FSP boot command failed.\n"); @@ -1629,6 +1759,16 @@ NvBool RmInitAdapter( RmInitAcpiMethods(pOS, pSys, pGpu); + // + // For GPU driving console, disable console access here, to ensure no console + // writes through BAR1 can interfere with physical RM's setup of BAR1 + // + if (rm_get_uefi_console_status(nv)) + { + os_disable_console_access(); + consoleDisabled = NV_TRUE; + } + // // If GSP fw RM support is enabled then start the GSP microcode // (including the task running the full instance of the RM) and @@ -1668,10 +1808,8 @@ NvBool RmInitAdapter( if (IS_PASSTHRU(pGpu)) nv->flags |= NV_FLAG_PASSTHRU; - populateDeviceAttributes(pGpu, nv); - initVendorSpecificRegistry(pGpu, nv->pci_info.device_id); - if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu)) + if (!IS_VIRTUAL(pGpu)) { initNbsiTable(pGpu); } @@ -1704,6 +1842,18 @@ NvBool RmInitAdapter( goto shutdown; } + if (consoleDisabled) + { + os_enable_console_access(); + consoleDisabled = NV_FALSE; + } + + // + // Expanded GPU visibility in GPUMGR is no longer needed once the + // GPU is initialized. + // + gpumgrThreadDisableExpandedGpuVisibility(); + // LOCK: acquire GPUs lock status.rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT); @@ -1867,6 +2017,13 @@ NvBool RmInitAdapter( shutdown: nv->flags &= ~NV_FLAG_IN_RECOVERY; + gpumgrThreadDisableExpandedGpuVisibility(); + + if (consoleDisabled) + { + os_enable_console_access(); + } + // call ShutdownAdapter to undo anything we've done above RmShutdownAdapter(nv); @@ -1903,6 +2060,14 @@ void RmShutdownAdapter( // LOCK: acquire GPUs lock if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK) { + // + // Shutdown path requires expanded GPU visibility in GPUMGR in order + // to access the GPU undergoing shutdown which may not be fully + // initialized, and to continue accessing the GPU undergoing shutdown + // after state destroy. + // + NV_ASSERT_OK(gpumgrThreadEnableExpandedGpuVisibility()); + RmDestroyDeferredDynamicPowerManagement(nv); freeNbsiTable(pGpu); @@ -1952,6 +2117,12 @@ void RmShutdownAdapter( gpumgrDetachGpu(gpuInstance); gpumgrDestroyDevice(deviceInstance); + // + // Expanded GPU visibility in GPUMGR is no longer needed once the + // GPU is removed from GPUMGR. + // + gpumgrThreadDisableExpandedGpuVisibility(); + if (nvp->flags & NV_INIT_FLAG_DMA) { RmTeardownDeviceDma(nv); diff --git a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c index ca2474fdd5..f9e81f21cb 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c +++ b/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c @@ -791,7 +791,6 @@ _createMemdescFromDmaBuf OBJGPU *pGpu, NvU32 flags, nv_dma_buf_t *pImportPriv, - void *pUserPages, struct sg_table *pImportSgt, NvU32 size, MEMORY_DESCRIPTOR **ppMemDesc, @@ -802,12 +801,9 @@ _createMemdescFromDmaBuf _createMemdescFromDmaBufSgtHelper(pGpu, flags, pImportPriv, pImportSgt, size, ppMemDesc, ppPrivate, osDestroyOsDescriptorFromDmaBuf); - - NV_ASSERT(pUserPages == NULL); - if (rmStatus != NV_OK) { - nv_dma_release_dma_buf(NULL, pImportPriv); + nv_dma_release_dma_buf(pImportPriv); } return rmStatus; @@ -838,6 +834,23 @@ _createMemdescFromSgt return rmStatus; } +static nv_dma_device_t *GetDmaDeviceForImport +( + nv_state_t *nv, + NvU32 flags +) +{ + if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags) && + (nv->niso_dma_dev != NULL)) + { + return nv->niso_dma_dev; + } + else + { + return nv->dma_dev; + } +} + static NV_STATUS osCreateOsDescriptorFromFileHandle ( @@ -852,8 +865,8 @@ osCreateOsDescriptorFromFileHandle { NV_STATUS rmStatus = NV_OK; nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_dma_device_t *dma_dev = NULL; NvU32 size = 0; - void *pUserPages = NULL; nv_dma_buf_t *pImportPriv = NULL; struct sg_table *pImportSgt = NULL; NvS32 fd; @@ -867,8 +880,9 @@ osCreateOsDescriptorFromFileHandle return NV_ERR_INVALID_ARGUMENT; } - rmStatus = nv_dma_import_from_fd(nv->dma_dev, fd, &size, - &pUserPages, &pImportSgt, &pImportPriv); + dma_dev = GetDmaDeviceForImport(nv, flags); + rmStatus = nv_dma_import_from_fd(dma_dev, fd, &size, + &pImportSgt, &pImportPriv); if (rmStatus != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -878,7 +892,7 @@ osCreateOsDescriptorFromFileHandle } return _createMemdescFromDmaBuf(pGpu, flags, pImportPriv, - pUserPages, pImportSgt, + pImportSgt, size, ppMemDesc, ppPrivate); } @@ -929,24 +943,24 @@ osCreateOsDescriptorFromDmaBufPtr { NV_STATUS rmStatus = NV_OK; nv_state_t *nv = NV_GET_NV_STATE(pGpu); + nv_dma_device_t *dma_dev = NULL; NvU32 size = 0; - void *pUserPages = NULL; nv_dma_buf_t *pImportPriv = NULL; struct sg_table *pImportSgt = NULL; void *dmaBuf = (void*)((NvUPtr)pDescriptor); - rmStatus = nv_dma_import_dma_buf(nv->dma_dev, dmaBuf, &size, - &pUserPages, &pImportSgt, &pImportPriv); + dma_dev = GetDmaDeviceForImport(nv, flags); + rmStatus = nv_dma_import_dma_buf(dma_dev, dmaBuf, &size, + &pImportSgt, &pImportPriv); if (rmStatus != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "%s(): Error (%d) while trying to import dma_buf!\n", - __FUNCTION__, rmStatus); + NV_PRINTF_COND(rmStatus == NV_ERR_NOT_SUPPORTED, LEVEL_INFO, LEVEL_ERROR, + "Error (%d) while trying to import dma_buf!\n", rmStatus); return rmStatus; } return _createMemdescFromDmaBuf(pGpu, flags, pImportPriv, - pUserPages, pImportSgt, + pImportSgt, size, ppMemDesc, ppPrivate); } @@ -1061,7 +1075,7 @@ osDestroyOsDescriptorFromDmaBuf * SGT. */ - nv_dma_release_dma_buf(NULL, pImportPriv); + nv_dma_release_dma_buf(pImportPriv); } static void diff --git a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c index 04c1f4f271..77b10d1c71 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osnvlink.c +++ b/src/nvidia/arch/nvalloc/unix/src/osnvlink.c @@ -58,6 +58,7 @@ extern NvlStatus knvlinkCoreReadDiscoveryTokenCallback(struct nvlink_link *, NvU extern NvlStatus knvlinkCoreWriteDiscoveryTokenCallback(struct nvlink_link *, NvU64); extern void knvlinkCoreTrainingCompleteCallback(struct nvlink_link *); extern void knvlinkCoreGetUphyLoadCallback(struct nvlink_link *, NvBool*); +extern NvlStatus knvlinkCoreGetCciLinkModeCallback(struct nvlink_link *, NvU64 *); /*! * @brief Helper to allocate an alternate stack from within core RM. @@ -665,6 +666,15 @@ static NvlStatus NV_API_CALL rm_nvlink_ops_ali_training return status; } +static NvlStatus NV_API_CALL rm_nvlink_ops_get_cci_link_mode +( + struct nvlink_link *link, + NvU64 *mode +) +{ + return NVL_SUCCESS; +} + #endif /* defined(INCLUDE_NVLINK_LIB) */ const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void) @@ -691,6 +701,7 @@ const struct nvlink_link_handlers* osGetNvlinkLinkCallbacks(void) .read_discovery_token = rm_nvlink_ops_read_link_discovery_token, .training_complete = rm_nvlink_ops_training_complete, .get_uphy_load = rm_nvlink_get_uphy_load, + .get_cci_link_mode = rm_nvlink_ops_get_cci_link_mode, .ali_training = rm_nvlink_ops_ali_training, }; diff --git a/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c b/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c index 89fa016981..4b81443e51 100644 --- a/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c +++ b/src/nvidia/arch/nvalloc/unix/src/rm-gpu-ops.c @@ -84,14 +84,15 @@ NV_STATUS NV_API_CALL rm_gpu_ops_address_space_create ( gpuDeviceHandle device, NvU64 vaBase, NvU64 vaSize, + NvU32 enableAts, gpuAddressSpaceHandle *vaSpace, gpuAddressSpaceInfo *vaSpaceInfo) { NV_STATUS rmStatus; void *fp; NV_ENTER_RM_RUNTIME(sp,fp); - rmStatus = nvGpuOpsAddressSpaceCreate(device, vaBase, vaSize, vaSpace, - vaSpaceInfo); + rmStatus = nvGpuOpsAddressSpaceCreate(device, vaBase, vaSize, enableAts, + vaSpace, vaSpaceInfo); NV_EXIT_RM_RUNTIME(sp,fp); return rmStatus; } @@ -239,18 +240,6 @@ NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages( return rmStatus; } -NV_STATUS NV_API_CALL rm_gpu_ops_pma_unpin_pages( - nvidia_stack_t *sp, void *pPma, - NvU64 *pPages, NvLength pageCount, NvU64 pageSize) -{ - NV_STATUS rmStatus; - void *fp; - NV_ENTER_RM_RUNTIME(sp,fp); - rmStatus = nvGpuOpsPmaUnpinPages(pPma, pPages, pageCount, pageSize); - NV_EXIT_RM_RUNTIME(sp,fp); - return rmStatus; -} - NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_map( nvidia_stack_t *sp, gpuAddressSpaceHandle vaspace, NvU64 gpuOffset, NvLength length, void **cpuPtr, NvU64 pageSize) @@ -604,6 +593,18 @@ NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t return rmStatus; } +NV_STATUS NV_API_CALL rm_gpu_ops_toggle_prefetch_faults(nvidia_stack_t *sp, + gpuFaultInfo *pFaultInfo, + NvBool bEnable) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsTogglePrefetchFaults(pFaultInfo, bEnable); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *sp, gpuDeviceHandle device, gpuAccessCntrInfo *accessCntrInfo, @@ -869,6 +870,17 @@ NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *sp, return rmStatus; } +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_update(nvidia_stack_t *sp, + struct ccslContext_t *ctx) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsCcslContextUpdate(ctx); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} + NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *sp, struct ccslContext_t *ctx, NvU8 direction) @@ -972,3 +984,15 @@ NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_increment_iv(nvidia_stack_t *sp, NV_EXIT_RM_RUNTIME(sp,fp); return rmStatus; } + +NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_log_device_encryption(nvidia_stack_t *sp, + struct ccslContext_t *ctx, + NvU32 bufferSize) +{ + NV_STATUS rmStatus; + void *fp; + NV_ENTER_RM_RUNTIME(sp,fp); + rmStatus = nvGpuOpsLogDeviceEncryption(ctx, bufferSize); + NV_EXIT_RM_RUNTIME(sp,fp); + return rmStatus; +} diff --git a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c index 725d123021..558f5fd599 100644 --- a/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c +++ b/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c @@ -48,7 +48,6 @@ #include "rmobjexportimport.h" #include "nvlimits.h" #include "gpu/device/device.h" -#include "gpu/subdevice/subdevice.h" #include "gpu/mig_mgr/kernel_mig_manager.h" #include "gpu/mig_mgr/gpu_instance_subscription.h" @@ -331,8 +330,8 @@ NV_STATUS RmExportObject(NvHandle hSrcClient, NvHandle hSrcObject, NV_STATUS status; RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL); MIG_INSTANCE_REF ref = kmigmgrMakeNoMIGReference(); - NvU64 deviceMapIdx; - RmObjExportDevice *pObjExportDevice; + NvU64 deviceMapIdx = 0; + RmObjExportDevice *pObjExportDevice = NULL; RsResourceRef *pSrcResourceRef; RsResourceRef *pDeviceRef; diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_console.c b/src/nvidia/arch/nvalloc/unix/src/unix_console.c index 91cd331c69..6c5e50b3f0 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_console.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_console.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,6 +29,7 @@ #include #include #include +#include #include #include "vgpu/vgpu_events.h" @@ -83,28 +84,28 @@ RmSaveDisplayState NvBool use_vbios = NV_PRIMARY_VGA(nv) && RmGpuHasIOSpaceEnabled(nv); NvU32 eax, ebx; NV_STATUS status; - NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS unixConsoleParams = {0}; - + NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS preUnixConsoleParams = {0}; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS postUnixConsoleParams = {0}; if (IS_VIRTUAL(pGpu) || pKernelDisplay == NULL) { return; } - os_disable_console_access(); - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) { NV_PRINTF(LEVEL_INFO, "RM fallback doesn't support saving of efifb console\n"); - goto done; + return; } - unixConsoleParams.bSaveOrRestore = NV_TRUE; - unixConsoleParams.bUseVbios = use_vbios; + os_disable_console_access(); + + preUnixConsoleParams.bSave = NV_TRUE; + preUnixConsoleParams.bUseVbios = use_vbios; NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR,pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, - NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE, - &unixConsoleParams, sizeof(unixConsoleParams)), done); + NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE, + &preUnixConsoleParams, sizeof(preUnixConsoleParams)), done); if (use_vbios) { @@ -124,6 +125,14 @@ RmSaveDisplayState } } + postUnixConsoleParams.bSave = NV_TRUE; + postUnixConsoleParams.bUseVbios = use_vbios; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, + nv->rmapi.hSubDevice, + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE, + &postUnixConsoleParams, sizeof(postUnixConsoleParams)), done); + done: os_enable_console_access(); } @@ -140,8 +149,8 @@ static void RmRestoreDisplayState KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); NV_STATUS status; NvU32 eax, ebx; - NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS unixConsoleParams = {0}; - NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS restoreParams = {0}; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS preUnixConsoleParams = {0}; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS postUnixConsoleParams = {0}; NV_ASSERT_OR_RETURN_VOID(pKernelDisplay != NULL); @@ -160,8 +169,6 @@ static void RmRestoreDisplayState return; } - os_disable_console_access(); - // // Fix up DCB index VBIOS scratch registers. // The strategies employed are: @@ -175,34 +182,39 @@ static void RmRestoreDisplayState if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) { NV_PRINTF(LEVEL_INFO, "RM fallback doesn't support efifb console restore\n"); - goto done; + return; } - unixConsoleParams.bUseVbios = use_vbios; - unixConsoleParams.bSaveOrRestore = NV_FALSE; + os_disable_console_access(); + + preUnixConsoleParams.bUseVbios = use_vbios; + preUnixConsoleParams.bSave = NV_FALSE; NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, - NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE, - &unixConsoleParams, sizeof(unixConsoleParams)), done); - - eax = 0x4f02; - ebx = nvp->vga.vesaMode; + NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE, + &preUnixConsoleParams, sizeof(preUnixConsoleParams)), done); - if (NV_OK == unixCallVideoBIOS(pGpu, &eax, &ebx)) + if (use_vbios) { - restoreParams.bWriteCr = NV_TRUE; + eax = 0x4f02; + ebx = nvp->vga.vesaMode; + + if (NV_OK == unixCallVideoBIOS(pGpu, &eax, &ebx)) + { + postUnixConsoleParams.bVbiosCallSuccessful = NV_TRUE; + } } + postUnixConsoleParams.bSave = NV_FALSE; + postUnixConsoleParams.bUseVbios = use_vbios; + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice, - NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE, - &restoreParams, sizeof(restoreParams)), done); + NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE, + &postUnixConsoleParams, sizeof(postUnixConsoleParams)), done); done: - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_UEFI)) - { - } os_enable_console_access(); } diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c index 11f58efd98..76690602da 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "kernel/gpu/intr/intr.h" #include "gpu/bif/kernel_bif.h" @@ -34,7 +35,6 @@ #include #include "objtmr.h" - static NvBool osInterruptPending( OBJGPU *pGpu, NvBool *serviced, @@ -107,8 +107,11 @@ static NvBool osInterruptPending( pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); tlsIsrInit(pIsrAllocator); + // // For SWRL granular locking process the countdown timer interrupt. - if (pDeviceLockGpu->getProperty(pDeviceLockGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING)) + // GSP-RM handles SWRL interrupts if GSP-RM is active + // + if ((!IS_GSP_CLIENT(pGpu)) && (pGpu->getProperty(pGpu, PDB_PROP_GPU_SWRL_GRANULAR_LOCKING))) { threadStateInitISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); @@ -127,15 +130,43 @@ static NvBool osInterruptPending( continue; } - intrGetPendingStall_HAL(pGpu, pIntr, &intr0Pending, &threadState); OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - *serviced = tmrServiceSwrlWrapper(pGpu, pTmr, &intr0Pending, &threadState); + *serviced = tmrServiceSwrlWrapper(pGpu, pTmr, &threadState); } } threadStateFreeISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); } + // + // Service nonstall interrupts before possibly acquiring GPUs lock + // so that we don't unnecesarily hold the lock while servicing them. + // + if (pDeviceLockGpu->getProperty(pDeviceLockGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED) && + pDeviceLockGpu->getProperty(pDeviceLockGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) + { + threadStateInitISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + + gpuMask = gpumgrGetGpuMask(pDeviceLockGpu); + gpuInstance = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + pIntr = GPU_GET_INTR(pGpu); + if ((pIntr != NULL) && (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr))) + { + NvBool bCtxswLog = NV_FALSE; + intrGetPendingNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); + intrCheckFecsEventbufferPending(pGpu, pIntr, &intr1Pending, &bCtxswLog); + if (!bitVectorTestAllCleared(&intr1Pending)) + { + intrServiceNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); + *serviced = NV_TRUE; + } + } + } + threadStateFreeISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + } + // LOCK: try to acquire GPUs lock if (rmDeviceGpuLocksAcquire(pDeviceLockGpu, GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_ISR) == NV_OK) { @@ -222,31 +253,6 @@ static NvBool osInterruptPending( } } - if (pDeviceLockGpu->getProperty(pDeviceLockGpu, PDB_PROP_GPU_ALTERNATE_TREE_ENABLED) && - pDeviceLockGpu->getProperty(pDeviceLockGpu, PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS)) - { - threadStateInitISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); - - gpuMask = gpumgrGetGpuMask(pDeviceLockGpu); - gpuInstance = 0; - while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) - { - pIntr = GPU_GET_INTR(pGpu); - if ((pIntr != NULL) && (INTERRUPT_TYPE_HARDWARE == intrGetIntrEn(pIntr))) - { - NvBool bCtxswLog = NV_FALSE; - intrGetPendingNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); - intrCheckFecsEventbufferPending(pGpu, pIntr, &intr1Pending, &bCtxswLog); - if (!bitVectorTestAllCleared(&intr1Pending)) - { - intrServiceNonStall_HAL(pGpu, pIntr, &intr1Pending, &threadState); - *serviced = NV_TRUE; - } - } - } - threadStateFreeISRLockless(&threadState, pDeviceLockGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); - } - tlsIsrDestroy(pIsrAllocator); portMemAllocatorRelease(pIsrAllocator); @@ -593,6 +599,36 @@ NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults( status = NV_OK; goto done; } + else + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + PORT_MEM_ALLOCATOR *pIsrAllocator; + THREAD_STATE_NODE threadState; + NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer + + if (pKernelGmmu == NULL) + { + status = NV_ERR_OBJECT_NOT_FOUND; + goto done; + } + + // If MMU fault buffer is not enabled, return early + if (!gpuIsVoltaHubIntrSupported(pGpu)) + goto done; + + pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); + tlsIsrInit(pIsrAllocator); + threadStateInitISRAndDeferredIntHandler(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR); + + // Copies all valid packets in RM's and client's shadow buffer + status = kgmmuCopyMmuFaults_HAL(pGpu, pKernelGmmu, &threadState, faultsCopied, + NON_REPLAYABLE_FAULT_BUFFER); + + threadStateFreeISRAndDeferredIntHandler(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR); + tlsIsrDestroy(pIsrAllocator); + portMemAllocatorRelease(pIsrAllocator); + + } done: NV_EXIT_RM_RUNTIME(sp,fp); @@ -610,6 +646,20 @@ static NV_STATUS _rm_gpu_copy_mmu_faults_unlocked( THREAD_STATE_NODE *pThreadState ) { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + if (pKernelGmmu == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + // If MMU fault buffer is not enabled, return early + if (!gpuIsVoltaHubIntrSupported(pGpu)) + return NV_OK; + + // Copies all valid packets in RM's and client's shadow buffer + return kgmmuCopyMmuFaults_HAL(pGpu, pKernelGmmu, pThreadState, pFaultsCopied, + NON_REPLAYABLE_FAULT_BUFFER); return NV_OK; } @@ -693,3 +743,27 @@ NV_STATUS rm_gpu_handle_mmu_faults( return status; } +NvBool NV_API_CALL rm_is_msix_allowed( + nvidia_stack_t *sp, + nv_state_t *nv +) +{ + nv_priv_t *pNvp = NV_GET_NV_PRIV(nv); + THREAD_STATE_NODE threadState; + void *fp; + NvBool ret = NV_FALSE; + + NV_ENTER_RM_RUNTIME(sp,fp); + threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); + + if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK) + { + ret = gpumgrIsDeviceMsixAllowed(nv->regs->cpu_address, + pNvp->pmc_boot_1, pNvp->pmc_boot_42); + rmapiLockRelease(); + } + + threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); + NV_EXIT_RM_RUNTIME(sp,fp); + return ret; +} diff --git a/src/nvidia/exports_link_command.txt b/src/nvidia/exports_link_command.txt index 14b4780c3e..90911b19c7 100644 --- a/src/nvidia/exports_link_command.txt +++ b/src/nvidia/exports_link_command.txt @@ -23,6 +23,7 @@ --undefined=rm_isr --undefined=rm_isr_bh --undefined=rm_isr_bh_unlocked +--undefined=rm_is_msix_allowed --undefined=rm_perform_version_check --undefined=rm_power_management --undefined=rm_stop_user_channels @@ -48,6 +49,7 @@ --undefined=rm_parse_option_string --undefined=rm_remove_spaces --undefined=rm_string_token +--undefined=rm_get_adapter_status_external --undefined=rm_disable_gpu_state_persistence --undefined=pNVRM_ID --undefined=rm_p2p_get_pages @@ -89,6 +91,7 @@ --undefined=rm_gpu_ops_has_pending_non_replayable_faults --undefined=rm_gpu_ops_get_non_replayable_faults --undefined=rm_gpu_ops_flush_replayable_fault_buffer +--undefined=rm_gpu_ops_toggle_prefetch_faults --undefined=rm_gpu_ops_init_access_cntr_info --undefined=rm_gpu_ops_destroy_access_cntr_info --undefined=rm_gpu_ops_enable_access_cntr @@ -97,7 +100,6 @@ --undefined=rm_gpu_ops_pma_alloc_pages --undefined=rm_gpu_ops_pma_free_pages --undefined=rm_gpu_ops_pma_pin_pages ---undefined=rm_gpu_ops_pma_unpin_pages --undefined=rm_gpu_ops_pma_register_callbacks --undefined=rm_gpu_ops_pma_unregister_callbacks --undefined=rm_gpu_ops_dup_address_space @@ -127,10 +129,12 @@ --undefined=rm_gpu_ops_ccsl_encrypt_with_iv --undefined=rm_gpu_ops_ccsl_context_init --undefined=rm_gpu_ops_ccsl_context_clear +--undefined=rm_gpu_ops_ccsl_context_update --undefined=rm_gpu_ops_ccsl_rotate_iv --undefined=rm_gpu_ops_ccsl_decrypt --undefined=rm_gpu_ops_ccsl_query_message_pool --undefined=rm_gpu_ops_ccsl_increment_iv +--undefined=rm_gpu_ops_ccsl_log_device_encryption --undefined=rm_log_gpu_crash --undefined=rm_kernel_rmapi_op --undefined=nv_get_hypervisor_type diff --git a/src/nvidia/generated/g_access_cntr_buffer_nvoc.c b/src/nvidia/generated/g_access_cntr_buffer_nvoc.c index cda0060973..72d64bc662 100644 --- a/src/nvidia/generated/g_access_cntr_buffer_nvoc.c +++ b/src/nvidia/generated/g_access_cntr_buffer_nvoc.c @@ -171,10 +171,6 @@ static void __nvoc_thunk_RmResource_accesscntrControl_Epilogue(struct AccessCoun rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_accesscntrControlLookup(struct AccessCounterBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_accesscntrGetInternalObjectHandle(struct AccessCounterBuffer *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_AccessCounterBuffer_GpuResource.offset)); } @@ -207,6 +203,10 @@ static NvBool __nvoc_thunk_RsResource_accesscntrCanCopy(struct AccessCounterBuff return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_accesscntrIsPartialUnmapSupported(struct AccessCounterBuffer *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_accesscntrPreDestruct(struct AccessCounterBuffer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_AccessCounterBuffer_RsResource.offset)); } @@ -512,8 +512,6 @@ static void __nvoc_init_funcTable_AccessCounterBuffer_1(AccessCounterBuffer *pTh pThis->__accesscntrControl_Epilogue__ = &__nvoc_thunk_RmResource_accesscntrControl_Epilogue; - pThis->__accesscntrControlLookup__ = &__nvoc_thunk_RsResource_accesscntrControlLookup; - pThis->__accesscntrGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_accesscntrGetInternalObjectHandle; pThis->__accesscntrControl__ = &__nvoc_thunk_GpuResource_accesscntrControl; @@ -530,6 +528,8 @@ static void __nvoc_init_funcTable_AccessCounterBuffer_1(AccessCounterBuffer *pTh pThis->__accesscntrCanCopy__ = &__nvoc_thunk_RsResource_accesscntrCanCopy; + pThis->__accesscntrIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_accesscntrIsPartialUnmapSupported; + pThis->__accesscntrPreDestruct__ = &__nvoc_thunk_RsResource_accesscntrPreDestruct; pThis->__accesscntrIsDuplicate__ = &__nvoc_thunk_RsResource_accesscntrIsDuplicate; @@ -563,21 +563,26 @@ void __nvoc_init_AccessCounterBuffer(AccessCounterBuffer *pThis) { __nvoc_init_funcTable_AccessCounterBuffer(pThis); } -NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; AccessCounterBuffer *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(AccessCounterBuffer), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(AccessCounterBuffer)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_AccessCounterBuffer); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -592,16 +597,25 @@ NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer **ppThis, Dyn status = __nvoc_ctor_AccessCounterBuffer(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_AccessCounterBuffer_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_AccessCounterBuffer_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(AccessCounterBuffer)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h index db2fe7a185..40ad3f851d 100644 --- a/src/nvidia/generated/g_access_cntr_buffer_nvoc.h +++ b/src/nvidia/generated/g_access_cntr_buffer_nvoc.h @@ -42,11 +42,16 @@ extern "C" { /*! * RM internal class representing ACCESS_COUNTER_NOTIFY_BUFFER */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_ACCESS_CNTR_BUFFER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct AccessCounterBuffer { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -84,7 +89,6 @@ struct AccessCounterBuffer { NV_STATUS (*__accesscntrInternalControlForward__)(struct AccessCounterBuffer *, NvU32, void *, NvU32); NV_STATUS (*__accesscntrUnmapFrom__)(struct AccessCounterBuffer *, RS_RES_UNMAP_FROM_PARAMS *); void (*__accesscntrControl_Epilogue__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__accesscntrControlLookup__)(struct AccessCounterBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__accesscntrGetInternalObjectHandle__)(struct AccessCounterBuffer *); NV_STATUS (*__accesscntrControl__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__accesscntrGetMemInterMapParams__)(struct AccessCounterBuffer *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -93,6 +97,7 @@ struct AccessCounterBuffer { NV_STATUS (*__accesscntrUnregisterEvent__)(struct AccessCounterBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__accesscntrControlSerialization_Prologue__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__accesscntrCanCopy__)(struct AccessCounterBuffer *); + NvBool (*__accesscntrIsPartialUnmapSupported__)(struct AccessCounterBuffer *); void (*__accesscntrPreDestruct__)(struct AccessCounterBuffer *); NV_STATUS (*__accesscntrIsDuplicate__)(struct AccessCounterBuffer *, NvHandle, NvBool *); void (*__accesscntrControlSerialization_Epilogue__)(struct AccessCounterBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -156,7 +161,6 @@ NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer**, Dynamic*, #define accesscntrInternalControlForward(pGpuResource, command, pParams, size) accesscntrInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define accesscntrUnmapFrom(pResource, pParams) accesscntrUnmapFrom_DISPATCH(pResource, pParams) #define accesscntrControl_Epilogue(pResource, pCallContext, pParams) accesscntrControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define accesscntrControlLookup(pResource, pParams, ppEntry) accesscntrControlLookup_DISPATCH(pResource, pParams, ppEntry) #define accesscntrGetInternalObjectHandle(pGpuResource) accesscntrGetInternalObjectHandle_DISPATCH(pGpuResource) #define accesscntrControl(pGpuResource, pCallContext, pParams) accesscntrControl_DISPATCH(pGpuResource, pCallContext, pParams) #define accesscntrGetMemInterMapParams(pRmResource, pParams) accesscntrGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -165,6 +169,7 @@ NV_STATUS __nvoc_objCreate_AccessCounterBuffer(AccessCounterBuffer**, Dynamic*, #define accesscntrUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) accesscntrUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define accesscntrControlSerialization_Prologue(pResource, pCallContext, pParams) accesscntrControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define accesscntrCanCopy(pResource) accesscntrCanCopy_DISPATCH(pResource) +#define accesscntrIsPartialUnmapSupported(pResource) accesscntrIsPartialUnmapSupported_DISPATCH(pResource) #define accesscntrPreDestruct(pResource) accesscntrPreDestruct_DISPATCH(pResource) #define accesscntrIsDuplicate(pResource, hMemory, pDuplicate) accesscntrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define accesscntrControlSerialization_Epilogue(pResource, pCallContext, pParams) accesscntrControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -297,10 +302,6 @@ static inline void accesscntrControl_Epilogue_DISPATCH(struct AccessCounterBuffe pResource->__accesscntrControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS accesscntrControlLookup_DISPATCH(struct AccessCounterBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__accesscntrControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle accesscntrGetInternalObjectHandle_DISPATCH(struct AccessCounterBuffer *pGpuResource) { return pGpuResource->__accesscntrGetInternalObjectHandle__(pGpuResource); } @@ -333,6 +334,10 @@ static inline NvBool accesscntrCanCopy_DISPATCH(struct AccessCounterBuffer *pRes return pResource->__accesscntrCanCopy__(pResource); } +static inline NvBool accesscntrIsPartialUnmapSupported_DISPATCH(struct AccessCounterBuffer *pResource) { + return pResource->__accesscntrIsPartialUnmapSupported__(pResource); +} + static inline void accesscntrPreDestruct_DISPATCH(struct AccessCounterBuffer *pResource) { pResource->__accesscntrPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_allclasses.h b/src/nvidia/generated/g_allclasses.h index 65c1d132fe..8e7fe01795 100644 --- a/src/nvidia/generated/g_allclasses.h +++ b/src/nvidia/generated/g_allclasses.h @@ -58,9 +58,13 @@ #include // NV01_MEMORY_LIST_SYSTEM #include // NV01_MEMORY_LIST_FBMEM #include // NV01_MEMORY_LIST_OBJECT +#include // NV_IMEX_SESSION #include // NV01_MEMORY_FLA +#include // NV_MEMORY_EXPORT #include // NV_CE_UTILS #include // NV_MEMORY_FABRIC +#include // NV_MEMORY_FABRIC_IMPORT_V2 +#include // NV_MEMORY_FABRIC_IMPORTED_REF #include // FABRIC_VASPACE_A #include // NV_MEMORY_MULTICAST_FABRIC #include // IO_VASPACE_A @@ -175,11 +179,14 @@ #include // RM_USER_SHARED_DATA #include // GT200_DEBUGGER #include // NV40_I2C +#include // KEPLER_DEVICE_VGPU #include // NVA081_VGPU_CONFIG #include // NVA084_KERNEL_HOST_VGPU_DEVICE #include // NV0060_SYNC_GPU_BOOST #include // GP100_UVM_SW +#include // NVENC_SW_SESSION #include // NV_EVENT_BUFFER +#include // NVFBC_SW_SESSION #include // NV_CONFIDENTIAL_COMPUTE #include // NV_COUNTER_COLLECTION_UNIT #include // NV_SEMAPHORE_SURFACE @@ -327,10 +334,18 @@ #define NV01_MEMORY_LIST_OBJECT (0x00000083) #endif +#ifndef NV_IMEX_SESSION +#define NV_IMEX_SESSION (0x000000f1) +#endif + #ifndef NV01_MEMORY_FLA #define NV01_MEMORY_FLA (0x000000f3) #endif +#ifndef NV_MEMORY_EXPORT +#define NV_MEMORY_EXPORT (0x000000e0) +#endif + #ifndef NV_CE_UTILS #define NV_CE_UTILS (0x00000050) #endif @@ -339,6 +354,14 @@ #define NV_MEMORY_FABRIC (0x000000f8) #endif +#ifndef NV_MEMORY_FABRIC_IMPORT_V2 +#define NV_MEMORY_FABRIC_IMPORT_V2 (0x000000f9) +#endif + +#ifndef NV_MEMORY_FABRIC_IMPORTED_REF +#define NV_MEMORY_FABRIC_IMPORTED_REF (0x000000fb) +#endif + #ifndef FABRIC_VASPACE_A #define FABRIC_VASPACE_A (0x000000fc) #endif @@ -822,6 +845,10 @@ #define NV40_I2C (0x0000402c) #endif +#ifndef KEPLER_DEVICE_VGPU +#define KEPLER_DEVICE_VGPU (0x0000a080) +#endif + #ifndef NVA081_VGPU_CONFIG #define NVA081_VGPU_CONFIG (0x0000a081) #endif @@ -838,10 +865,18 @@ #define GP100_UVM_SW (0x0000c076) #endif +#ifndef NVENC_SW_SESSION +#define NVENC_SW_SESSION (0x0000a0bc) +#endif + #ifndef NV_EVENT_BUFFER #define NV_EVENT_BUFFER (0x000090cd) #endif +#ifndef NVFBC_SW_SESSION +#define NVFBC_SW_SESSION (0x0000a0bd) +#endif + #ifndef NV_CONFIDENTIAL_COMPUTE #define NV_CONFIDENTIAL_COMPUTE (0x0000cb33) #endif diff --git a/src/nvidia/generated/g_binary_api_nvoc.c b/src/nvidia/generated/g_binary_api_nvoc.c index 2b5ab8bf1d..dd151b6a7d 100644 --- a/src/nvidia/generated/g_binary_api_nvoc.c +++ b/src/nvidia/generated/g_binary_api_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_binapiControl_Epilogue(struct BinaryApi *pRe rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_binapiControlLookup(struct BinaryApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_binapiGetInternalObjectHandle(struct BinaryApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApi_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_binapiCanCopy(struct BinaryApi *pResource) return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_binapiIsPartialUnmapSupported(struct BinaryApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_binapiPreDestruct(struct BinaryApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApi_RsResource.offset)); } @@ -257,8 +257,6 @@ static void __nvoc_init_funcTable_BinaryApi_1(BinaryApi *pThis) { pThis->__binapiControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiControl_Epilogue; - pThis->__binapiControlLookup__ = &__nvoc_thunk_RsResource_binapiControlLookup; - pThis->__binapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiGetInternalObjectHandle; pThis->__binapiUnmap__ = &__nvoc_thunk_GpuResource_binapiUnmap; @@ -273,6 +271,8 @@ static void __nvoc_init_funcTable_BinaryApi_1(BinaryApi *pThis) { pThis->__binapiCanCopy__ = &__nvoc_thunk_RsResource_binapiCanCopy; + pThis->__binapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_binapiIsPartialUnmapSupported; + pThis->__binapiPreDestruct__ = &__nvoc_thunk_RsResource_binapiPreDestruct; pThis->__binapiIsDuplicate__ = &__nvoc_thunk_RsResource_binapiIsDuplicate; @@ -300,21 +300,26 @@ void __nvoc_init_BinaryApi(BinaryApi *pThis) { __nvoc_init_funcTable_BinaryApi(pThis); } -NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; BinaryApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(BinaryApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(BinaryApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_BinaryApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -329,16 +334,25 @@ NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_BinaryApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_BinaryApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_BinaryApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(BinaryApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -497,10 +511,6 @@ static void __nvoc_thunk_RmResource_binapiprivControl_Epilogue(struct BinaryApiP rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_binapiprivControlLookup(struct BinaryApiPrivileged *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle(struct BinaryApiPrivileged *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_BinaryApiPrivileged_GpuResource.offset)); } @@ -529,6 +539,10 @@ static NvBool __nvoc_thunk_RsResource_binapiprivCanCopy(struct BinaryApiPrivileg return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_binapiprivIsPartialUnmapSupported(struct BinaryApiPrivileged *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_binapiprivPreDestruct(struct BinaryApiPrivileged *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_BinaryApiPrivileged_RsResource.offset)); } @@ -613,8 +627,6 @@ static void __nvoc_init_funcTable_BinaryApiPrivileged_1(BinaryApiPrivileged *pTh pThis->__binapiprivControl_Epilogue__ = &__nvoc_thunk_RmResource_binapiprivControl_Epilogue; - pThis->__binapiprivControlLookup__ = &__nvoc_thunk_RsResource_binapiprivControlLookup; - pThis->__binapiprivGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_binapiprivGetInternalObjectHandle; pThis->__binapiprivUnmap__ = &__nvoc_thunk_GpuResource_binapiprivUnmap; @@ -629,6 +641,8 @@ static void __nvoc_init_funcTable_BinaryApiPrivileged_1(BinaryApiPrivileged *pTh pThis->__binapiprivCanCopy__ = &__nvoc_thunk_RsResource_binapiprivCanCopy; + pThis->__binapiprivIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_binapiprivIsPartialUnmapSupported; + pThis->__binapiprivPreDestruct__ = &__nvoc_thunk_RsResource_binapiprivPreDestruct; pThis->__binapiprivIsDuplicate__ = &__nvoc_thunk_RsResource_binapiprivIsDuplicate; @@ -657,21 +671,26 @@ void __nvoc_init_BinaryApiPrivileged(BinaryApiPrivileged *pThis) { __nvoc_init_funcTable_BinaryApiPrivileged(pThis); } -NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; BinaryApiPrivileged *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(BinaryApiPrivileged), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(BinaryApiPrivileged)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_BinaryApiPrivileged); pThis->__nvoc_base_BinaryApi.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -686,16 +705,25 @@ NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged **ppThis, Dyn status = __nvoc_ctor_BinaryApiPrivileged(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_BinaryApiPrivileged_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_BinaryApiPrivileged_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_BinaryApi.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(BinaryApiPrivileged)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_binary_api_nvoc.h b/src/nvidia/generated/g_binary_api_nvoc.h index ba9862968b..131de8db31 100644 --- a/src/nvidia/generated/g_binary_api_nvoc.h +++ b/src/nvidia/generated/g_binary_api_nvoc.h @@ -40,11 +40,16 @@ extern "C" { #include "resserv/rs_resource.h" #include "rmapi/control.h" + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_BINARY_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct BinaryApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -66,7 +71,6 @@ struct BinaryApi { NV_STATUS (*__binapiInternalControlForward__)(struct BinaryApi *, NvU32, void *, NvU32); NV_STATUS (*__binapiUnmapFrom__)(struct BinaryApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__binapiControl_Epilogue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__binapiControlLookup__)(struct BinaryApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__binapiGetInternalObjectHandle__)(struct BinaryApi *); NV_STATUS (*__binapiUnmap__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__binapiGetMemInterMapParams__)(struct BinaryApi *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -74,6 +78,7 @@ struct BinaryApi { NV_STATUS (*__binapiControlFilter__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiControlSerialization_Prologue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__binapiCanCopy__)(struct BinaryApi *); + NvBool (*__binapiIsPartialUnmapSupported__)(struct BinaryApi *); void (*__binapiPreDestruct__)(struct BinaryApi *); NV_STATUS (*__binapiIsDuplicate__)(struct BinaryApi *, NvHandle, NvBool *); void (*__binapiControlSerialization_Epilogue__)(struct BinaryApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -121,7 +126,6 @@ NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi**, Dynamic*, NvU32, struct CALL_C #define binapiInternalControlForward(pGpuResource, command, pParams, size) binapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define binapiUnmapFrom(pResource, pParams) binapiUnmapFrom_DISPATCH(pResource, pParams) #define binapiControl_Epilogue(pResource, pCallContext, pParams) binapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define binapiControlLookup(pResource, pParams, ppEntry) binapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define binapiGetInternalObjectHandle(pGpuResource) binapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define binapiUnmap(pGpuResource, pCallContext, pCpuMapping) binapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define binapiGetMemInterMapParams(pRmResource, pParams) binapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -129,6 +133,7 @@ NV_STATUS __nvoc_objCreate_BinaryApi(BinaryApi**, Dynamic*, NvU32, struct CALL_C #define binapiControlFilter(pResource, pCallContext, pParams) binapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define binapiControlSerialization_Prologue(pResource, pCallContext, pParams) binapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define binapiCanCopy(pResource) binapiCanCopy_DISPATCH(pResource) +#define binapiIsPartialUnmapSupported(pResource) binapiIsPartialUnmapSupported_DISPATCH(pResource) #define binapiPreDestruct(pResource) binapiPreDestruct_DISPATCH(pResource) #define binapiIsDuplicate(pResource, hMemory, pDuplicate) binapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define binapiControlSerialization_Epilogue(pResource, pCallContext, pParams) binapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -184,10 +189,6 @@ static inline void binapiControl_Epilogue_DISPATCH(struct BinaryApi *pResource, pResource->__binapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS binapiControlLookup_DISPATCH(struct BinaryApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__binapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle binapiGetInternalObjectHandle_DISPATCH(struct BinaryApi *pGpuResource) { return pGpuResource->__binapiGetInternalObjectHandle__(pGpuResource); } @@ -216,6 +217,10 @@ static inline NvBool binapiCanCopy_DISPATCH(struct BinaryApi *pResource) { return pResource->__binapiCanCopy__(pResource); } +static inline NvBool binapiIsPartialUnmapSupported_DISPATCH(struct BinaryApi *pResource) { + return pResource->__binapiIsPartialUnmapSupported__(pResource); +} + static inline void binapiPreDestruct_DISPATCH(struct BinaryApi *pResource) { pResource->__binapiPreDestruct__(pResource); } @@ -242,11 +247,16 @@ NV_STATUS binapiConstruct_IMPL(struct BinaryApi *arg_pResource, struct CALL_CONT #undef PRIVATE_FIELD + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_BINARY_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct BinaryApiPrivileged { const struct NVOC_RTTI *__nvoc_rtti; struct BinaryApi __nvoc_base_BinaryApi; @@ -269,7 +279,6 @@ struct BinaryApiPrivileged { NV_STATUS (*__binapiprivInternalControlForward__)(struct BinaryApiPrivileged *, NvU32, void *, NvU32); NV_STATUS (*__binapiprivUnmapFrom__)(struct BinaryApiPrivileged *, RS_RES_UNMAP_FROM_PARAMS *); void (*__binapiprivControl_Epilogue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__binapiprivControlLookup__)(struct BinaryApiPrivileged *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__binapiprivGetInternalObjectHandle__)(struct BinaryApiPrivileged *); NV_STATUS (*__binapiprivUnmap__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__binapiprivGetMemInterMapParams__)(struct BinaryApiPrivileged *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -277,6 +286,7 @@ struct BinaryApiPrivileged { NV_STATUS (*__binapiprivControlFilter__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__binapiprivControlSerialization_Prologue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__binapiprivCanCopy__)(struct BinaryApiPrivileged *); + NvBool (*__binapiprivIsPartialUnmapSupported__)(struct BinaryApiPrivileged *); void (*__binapiprivPreDestruct__)(struct BinaryApiPrivileged *); NV_STATUS (*__binapiprivIsDuplicate__)(struct BinaryApiPrivileged *, NvHandle, NvBool *); void (*__binapiprivControlSerialization_Epilogue__)(struct BinaryApiPrivileged *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -324,7 +334,6 @@ NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged**, Dynamic*, #define binapiprivInternalControlForward(pGpuResource, command, pParams, size) binapiprivInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define binapiprivUnmapFrom(pResource, pParams) binapiprivUnmapFrom_DISPATCH(pResource, pParams) #define binapiprivControl_Epilogue(pResource, pCallContext, pParams) binapiprivControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define binapiprivControlLookup(pResource, pParams, ppEntry) binapiprivControlLookup_DISPATCH(pResource, pParams, ppEntry) #define binapiprivGetInternalObjectHandle(pGpuResource) binapiprivGetInternalObjectHandle_DISPATCH(pGpuResource) #define binapiprivUnmap(pGpuResource, pCallContext, pCpuMapping) binapiprivUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define binapiprivGetMemInterMapParams(pRmResource, pParams) binapiprivGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -332,6 +341,7 @@ NV_STATUS __nvoc_objCreate_BinaryApiPrivileged(BinaryApiPrivileged**, Dynamic*, #define binapiprivControlFilter(pResource, pCallContext, pParams) binapiprivControlFilter_DISPATCH(pResource, pCallContext, pParams) #define binapiprivControlSerialization_Prologue(pResource, pCallContext, pParams) binapiprivControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define binapiprivCanCopy(pResource) binapiprivCanCopy_DISPATCH(pResource) +#define binapiprivIsPartialUnmapSupported(pResource) binapiprivIsPartialUnmapSupported_DISPATCH(pResource) #define binapiprivPreDestruct(pResource) binapiprivPreDestruct_DISPATCH(pResource) #define binapiprivIsDuplicate(pResource, hMemory, pDuplicate) binapiprivIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define binapiprivControlSerialization_Epilogue(pResource, pCallContext, pParams) binapiprivControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -387,10 +397,6 @@ static inline void binapiprivControl_Epilogue_DISPATCH(struct BinaryApiPrivilege pResource->__binapiprivControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS binapiprivControlLookup_DISPATCH(struct BinaryApiPrivileged *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__binapiprivControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle binapiprivGetInternalObjectHandle_DISPATCH(struct BinaryApiPrivileged *pGpuResource) { return pGpuResource->__binapiprivGetInternalObjectHandle__(pGpuResource); } @@ -419,6 +425,10 @@ static inline NvBool binapiprivCanCopy_DISPATCH(struct BinaryApiPrivileged *pRes return pResource->__binapiprivCanCopy__(pResource); } +static inline NvBool binapiprivIsPartialUnmapSupported_DISPATCH(struct BinaryApiPrivileged *pResource) { + return pResource->__binapiprivIsPartialUnmapSupported__(pResource); +} + static inline void binapiprivPreDestruct_DISPATCH(struct BinaryApiPrivileged *pResource) { pResource->__binapiprivPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c index 1474fbb910..0a6bdcf616 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_AD102.c @@ -35,2015 +35,2012 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 56832 -// COMPRESSED SIZE (bytes): 32065 +// COMPRESSED SIZE (bytes): 32024 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data[] = { - 0xed, 0xfd, 0x73, 0xcc, 0x2d, 0xcd, 0x1f, 0x00, 0xf0, 0x3d, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0x9b, 0xf7, 0xb1, 0x71, 0x1f, 0xdb, 0xb6, 0x8d, 0xfe, 0xaa, 0xb4, - 0x79, 0xd3, 0xa6, 0x7f, 0xb4, 0x49, 0x93, 0xf6, 0x7e, 0x92, 0xef, 0x99, 0x99, 0x3d, 0x9b, 0xcc, - 0xd9, 0x3d, 0x67, 0x77, 0x76, 0xb2, 0x3b, 0x73, 0x00, 0x00, 0xfe, 0xff, 0x9b, 0x5e, 0xf3, 0x3d, - 0x25, 0xc8, 0xef, 0x53, 0xa8, 0x47, 0xc4, 0x8c, 0x4a, 0xce, 0xaf, 0xae, 0x2f, 0x6e, 0x53, 0x5a, - 0x85, 0x6e, 0x37, 0xf7, 0x79, 0xe3, 0x21, 0xe1, 0x65, 0xd9, 0xf8, 0x56, 0x11, 0x37, 0x61, 0xee, - 0x44, 0x9d, 0xaf, 0x73, 0x4c, 0xa8, 0x5d, 0x84, 0x4a, 0x9c, 0xd4, 0x5d, 0x67, 0x40, 0xf1, 0x93, - 0x03, 0x5e, 0xb7, 0x1f, 0xf5, 0x95, 0xd1, 0xa0, 0xf8, 0x5b, 0xf6, 0x7b, 0xf7, 0x49, 0x77, 0xea, - 0x58, 0x2c, 0x75, 0x68, 0x27, 0x64, 0x8d, 0x4f, 0x9a, 0xcd, 0x35, 0xc5, 0x46, 0xfb, 0x86, 0xb0, - 0x25, 0x76, 0x32, 0x4b, 0x20, 0x64, 0x43, 0x18, 0x5f, 0x63, 0x2d, 0xb6, 0xd7, 0x7a, 0x79, 0x91, - 0xe2, 0xc5, 0x70, 0xcd, 0xc9, 0xe1, 0x95, 0x8e, 0x30, 0x77, 0x12, 0xba, 0xbe, 0xf5, 0x48, 0xf7, - 0x09, 0xa4, 0xe6, 0x9d, 0x20, 0x18, 0xa7, 0xcc, 0x60, 0xd4, 0xdc, 0xa2, 0x9f, 0xdc, 0x01, 0x09, - 0xbc, 0xa8, 0x1b, 0x14, 0x05, 0x8c, 0xe1, 0x2c, 0x87, 0x26, 0x46, 0x83, 0xff, 0x22, 0xc7, 0xf2, - 0x68, 0x58, 0x30, 0x11, 0xbb, 0xf5, 0xc5, 0x1a, 0xa2, 0x66, 0xcb, 0x84, 0xc4, 0x41, 0x6b, 0xd9, - 0xc3, 0x13, 0x52, 0x89, 0xc5, 0x84, 0xfc, 0xfc, 0x03, 0x98, 0x7e, 0x49, 0x37, 0x72, 0x4d, 0xe2, - 0xcb, 0x6c, 0xdf, 0x4d, 0x1a, 0x3f, 0xd8, 0xa7, 0x04, 0x61, 0x15, 0x0d, 0x65, 0xe2, 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0x37, 0xea, 0x42, 0x03, 0xf8, 0x3f, 0x7f, 0xff, 0x98, 0xff, 0xbb, 0x7a, 0x40, 0x20, + 0xfe, 0x9f, 0x6f, 0x9f, 0xf6, 0x7f, 0x57, 0xfe, 0xfb, 0xbf, 0x48, 0xff, 0x5f, 0x88, 0xfd, 0x2f, + 0xc4, 0xff, 0x17, 0x12, 0xff, 0x0b, 0xc9, 0xff, 0xcb, 0x3a, 0xe9, 0xff, 0xcb, 0x54, 0xe6, 0x3f, + 0xf5, 0xc8, 0xff, 0x5f, 0xeb, 0xd1, 0xf9, 0xbf, 0x9c, 0x03, 0x80, 0xff, 0x1d, 0x62, 0x00, 0x25, + 0x11, 0x06, 0x00, 0xa1, 0xff, 0x1d, 0x5e, 0x03, 0x47, 0x0b, 0x67, 0x73, 0x1b, 0x13, 0x67, 0x0b, + 0x23, 0x02, 0x13, 0x47, 0x47, 0x3b, 0x47, 0xa8, 0xff, 0x27, 0x4b, 0xff, 0x7f, 0xd7, 0xff, 0x01, + 0x25, 0x72, 0xec, 0x4b, 0x00, 0xde, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2054,7 +2051,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 56832, // uncompressed data size (bytes) - 32065, // compressed data size (bytes) + 32024, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2106,2015 +2103,2012 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 56832 -// COMPRESSED SIZE (bytes): 32067 +// COMPRESSED SIZE (bytes): 32027 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_image_prod_data[] = { - 0xed, 0xfd, 0x63, 0xac, 0x2c, 0xcd, 0x1b, 0x00, 0x70, 0x1e, 0xe3, 0x1e, 0xdb, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xbe, 0xc7, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xcf, 0xd9, 0x77, 0x95, - 0xdd, 0xfc, 0xb3, 0x9b, 0xfd, 0xb0, 0x9b, 0x6c, 0xb2, 0x7b, 0x7f, 0xc9, 0x33, 0x5d, 0xd5, 0xd3, - 0x99, 0x9a, 0xe9, 0x99, 0xae, 0xae, 0x4a, 0x77, 0xd5, 0x00, 0x00, 0xfc, 0xff, 0xb7, 0x95, 0x37, - 0x8d, 0xde, 0x5a, 0x38, 0x51, 0xc2, 0x6e, 0x47, 0xfc, 0x0c, 0xad, 0x54, 0xa6, 0xf7, 0x2c, 0xeb, - 0xc2, 0x64, 0x3f, 0x46, 0xf9, 0x0b, 0xff, 0xe3, 0x4c, 0x4a, 0xf7, 0x70, 0x32, 0x6a, 0x1d, 0x33, - 0xa2, 0x36, 0x79, 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0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4125,7 +4119,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 56832, // uncompressed data size (bytes) - 32067, // compressed data size (bytes) + 32027, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -4181,54 +4175,54 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_data[] = { - 0x6f, 0x15, 0x44, 0x15, 0x5e, 0x87, 0x74, 0x01, 0x2c, 0xbc, 0x8e, 0x44, 0x6d, 0x69, 0x63, 0xed, - 0xc3, 0xb5, 0xd6, 0xe7, 0x43, 0xb8, 0xdb, 0x74, 0x0e, 0x85, 0x22, 0x0a, 0xe7, 0xb7, 0x42, 0x14, - 0x76, 0xea, 0xc9, 0x6c, 0x22, 0xea, 0x03, 0x3c, 0x5a, 0x8d, 0x1f, 0xab, 0x1f, 0xd0, 0xfe, 0x7f, - 0xab, 0x97, 0xd2, 0xb3, 0x7c, 0x77, 0x26, 0xec, 0xa8, 0xf8, 0xc0, 0x39, 0xa2, 0xcb, 0xf5, 0x12, - 0xc7, 0xbb, 0xbe, 0x91, 0x65, 0xda, 0xc9, 0xba, 0xc4, 0x75, 0xe0, 0xc0, 0x42, 0xb2, 0xd2, 0xa9, - 0xba, 0x58, 0xa4, 0x2a, 0xbf, 0x9c, 0xd4, 0x51, 0x04, 0x3d, 0x0c, 0x8d, 0x1a, 0x1e, 0xc3, 0x22, - 0xfa, 0x48, 0x3a, 0x24, 0x1f, 0x47, 0x23, 0x1c, 0x22, 0xa6, 0xfe, 0xf7, 0xff, 0xbb, 0x72, 0x8a, - 0x71, 0x85, 0x58, 0x42, 0x8f, 0xb5, 0x43, 0xdb, 0x9d, 0x74, 0x9d, 0x7f, 0x2d, 0x49, 0x87, 0x20, - 0x9d, 0xa3, 0xc3, 0x07, 0x5f, 0x01, 0xbc, 0xdb, 0xae, 0x93, 0xb3, 0x49, 0x8d, 0xad, 0xe0, 0xb3, - 0x11, 0x4a, 0xda, 0x59, 0x9f, 0xdd, 0x5b, 0x68, 0xa2, 0x59, 0x14, 0xe1, 0x6f, 0xc2, 0x80, 0x20, - 0x53, 0x60, 0x84, 0x0e, 0x22, 0x5b, 0x4d, 0x74, 0x08, 0x6f, 0x3a, 0xb9, 0x65, 0x4f, 0xee, 0x8c, - 0xa0, 0xc5, 0xa6, 0x89, 0xbc, 0x4b, 0x6e, 0x55, 0x63, 0x1a, 0x81, 0xb9, 0x68, 0x1e, 0x58, 0x73, - 0xbf, 0x0b, 0xaf, 0x55, 0xf5, 0xb0, 0x9f, 0x6d, 0x86, 0xc4, 0xdd, 0x9d, 0x22, 0xe8, 0x30, 0x7e, - 0xe1, 0xd5, 0x55, 0xcd, 0xe9, 0x83, 0x94, 0xea, 0x62, 0x6f, 0x35, 0x45, 0xc9, 0x74, 0xf5, 0x46, - 0xb1, 0x74, 0xf2, 0xc4, 0x57, 0x36, 0x02, 0x29, 0x69, 0x50, 0x4a, 0x23, 0x47, 0x6f, 0xf0, 0x52, - 0x59, 0x15, 0xd1, 0x7f, 0x6a, 0xd0, 0x20, 0xcc, 0x79, 0xc0, 0xec, 0xd2, 0x11, 0xe2, 0xdd, 0xa5, - 0xa3, 0xda, 0x5a, 0x7c, 0xe0, 0x53, 0x80, 0xaf, 0x35, 0xa5, 0x0d, 0xb7, 0x5a, 0x3b, 0x6e, 0x01, - 0x3f, 0xec, 0x5e, 0xe8, 0xa2, 0x1b, 0xe5, 0xa4, 0x91, 0x8c, 0x14, 0xa8, 0x76, 0x2c, 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0x3f, 0x3d, 0x3e, 0xf6, 0x2a, 0x59, 0x0d, 0xff, 0x10, 0x3b, 0xcc, 0x19, - 0xbf, 0x46, 0x18, 0xca, 0x39, 0xea, 0xbc, 0x2e, 0x37, 0xe9, 0xed, 0x39, 0x34, 0xff, 0x74, 0xd1, - 0xd8, 0x82, 0xb8, 0xfd, 0x69, 0x68, 0x9d, 0x7b, 0x9a, 0xed, 0x8e, 0xa5, 0x11, 0x02, 0x82, 0x51, - 0x5a, 0x74, 0x8c, 0xd0, 0x86, 0x4a, 0x32, 0x6c, 0x26, 0x8c, 0x17, 0x6c, 0xaa, 0x5e, 0x3b, 0xf8, - 0x80, 0x53, 0x3d, 0xb8, 0x5c, 0x6a, 0x70, 0x02, 0xbf, 0xfb, 0xb2, 0x1d, 0x63, 0x9e, 0x7b, 0xd3, - 0x7e, 0xb8, 0x9a, 0xfa, 0xd3, 0xb0, 0x38, 0x2c, 0x73, 0xf9, 0xde, 0xfc, 0x70, 0x02, 0x56, 0xef, - 0x4c, 0xc2, 0xe2, 0x7e, 0xab, 0xa0, 0xd6, 0x99, 0x25, 0x18, 0xba, 0x1b, 0x7d, 0xf1, 0x80, 0x47, - 0x3f, 0x1c, 0x3f, 0x41, 0x0f, 0x70, 0xc2, 0xa3, 0xb5, 0x14, 0x90, 0xe8, 0x60, 0xc7, 0x6e, 0xec, - 0x8f, 0x6a, 0xe7, 0x3b, 0x17, 0x2f, 0x9c, 0x6f, 0x8e, 0x21, 0xd1, 0xb8, 0xde, 0x3e, 0xc7, 0x50, - 0x47, 0xc5, 0x98, 0xbb, 0x6f, 0x30, 0xdc, 0x35, 0x1c, 0xcb, 0xf2, 0x2d, 0xd3, 0x1b, 0x97, 0xc2, + 0xd9, 0xef, 0xae, 0x46, 0x3c, 0x17, 0x75, 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0x3d, 0x6b, 0xdf, 0x6b, 0x26, 0xa1, + 0xd5, 0x9c, 0x07, 0x51, 0xa2, 0x97, 0xbb, 0xfb, 0xe6, 0xcc, 0xd6, 0x2b, 0xd1, 0x8f, 0x40, 0x8b, + 0xe4, 0x14, 0x4d, 0x44, 0x0c, 0x7b, 0xc7, 0xdb, 0x27, 0x47, 0x77, 0x44, 0xdd, 0xec, 0xb9, 0xac, + 0x13, 0xa3, 0xfc, 0xec, 0x8d, 0x1e, 0xef, 0x48, 0x99, 0xa2, 0x93, 0x50, 0x6b, 0x9d, 0x4c, 0x18, + 0xd3, 0xff, 0x0a, 0x4a, 0x8c, 0x96, 0x0d, 0x8b, 0x84, 0x28, 0x0a, 0xf3, 0x07, 0xf8, 0xc0, 0x4a, + 0x6b, 0xc3, 0xde, 0x1f, 0x0f, 0xb2, 0x9f, 0xa9, 0xf9, 0x34, 0xed, 0xa9, 0xfd, 0xab, 0x16, 0x5b, + 0xaa, 0xc6, 0x78, 0xf0, 0x65, 0x54, 0x4e, 0x0b, 0x35, 0x25, 0x7e, 0x85, 0x0c, 0xea, 0xf7, 0xe5, + 0xd6, 0xdd, 0x91, 0x7a, 0x7e, 0x72, 0xc6, 0x57, 0x7f, 0xad, 0x45, 0xbe, 0x9f, 0xd1, 0xf9, 0x35, + 0x5a, 0x48, 0x96, 0xf8, 0x2e, 0xb2, 0x4a, 0xbf, 0x95, 0x8a, 0xfe, 0x13, 0xa7, 0x34, 0x70, 0x8b, + 0xa3, 0x4f, 0xc1, 0xd5, 0x4e, 0x0f, 0x1c, 0x8c, 0x45, 0x6e, 0x47, 0x8d, 0x79, 0xe3, 0xfb, 0x41, + 0x0a, 0x31, 0xdc, 0x42, 0x0f, 0x73, 0x2c, 0xb2, 0x9d, 0xb9, 0x31, 0xdd, 0x84, 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0xbb, 0x5c, 0x88, 0x73, 0x7e, 0x68, 0x74, 0xc1, 0x44, 0x98, 0x58, 0x66, 0xc8, 0x01, 0xbb, 0x48, + 0x0c, 0x5e, 0x02, 0x4f, 0x71, 0xd5, 0x21, 0x2b, 0xd7, 0x3f, 0x1b, 0xe4, 0xef, 0x0e, 0x9d, 0xd2, + 0xf8, 0xec, 0x0a, 0x1e, 0xe4, 0x7f, 0x08, 0x9e, 0x39, 0x80, 0x19, 0x66, 0x37, 0xf9, 0x52, 0x34, + 0xd2, 0x6c, 0x24, 0xa2, 0x98, 0xb1, 0xea, 0x4f, 0x87, 0x25, 0xaa, 0xe2, 0xa7, 0x2a, 0xa7, 0xd9, + 0xc6, 0xb6, 0xb8, 0x8c, 0x24, 0x37, 0xb6, 0xc1, 0x32, 0xdc, 0xde, 0x7b, 0x60, 0x17, 0x6c, 0xda, + 0x54, 0x05, 0x5b, 0x5a, 0xaf, 0x87, 0xbe, 0x25, 0xfc, 0x52, 0x1b, 0x0b, 0x0b, 0x55, 0xf1, 0x4c, + 0x80, 0x36, 0x4b, 0xc3, 0x26, 0x20, 0xdf, 0x32, 0x11, 0xc9, 0xd6, 0xd5, 0xb8, 0x42, 0xe4, 0x4a, + 0x98, 0xbf, 0x6f, 0x29, 0x9f, 0x53, 0x73, 0xd0, 0x18, 0xb3, 0xb4, 0xed, 0xb9, 0xe4, 0xed, 0x87, + 0xd2, 0xb8, 0x6d, 0xe7, 0x6a, 0xcb, 0xfb, 0x76, 0x32, 0xc8, 0xab, 0xf8, 0x50, 0x5b, 0xd9, 0x32, + 0x56, 0xb4, 0x50, 0x66, 0x7d, 0x2a, 0x2c, 0x01, 0xf0, 0xd0, 0x2a, 0xfa, 0x15, 0x1a, 0x94, 0x2b, + 0x61, 0x9e, 0x1e, 0x92, 0x53, 0x06, 0xf8, 0x55, 0x06, 0xc6, 0x11, 0xb1, 0xfe, 0x5f, 0x65, 0x08, + 0xcb, 0x83, 0x94, 0xaa, 0x7c, 0xfa, 0x0e, 0x90, 0x15, 0x08, 0x5d, 0xde, 0x7c, 0x2f, 0x78, 0x51, + 0xdb, 0x0c, 0xa1, 0xf9, 0xe4, 0x96, 0xab, 0xfc, 0xda, 0x66, 0x97, 0x70, 0xef, 0xf1, 0x5d, 0x73, + 0x9b, 0xa4, 0x5f, 0x01, 0x05, 0xe9, 0xfa, 0xb1, 0xb5, 0xd6, 0x32, 0x91, 0x00, 0x24, 0x18, 0x44, + 0xac, 0xfa, 0x2f, 0xb1, 0xb7, 0xf8, 0x45, 0x12, 0x96, 0x94, 0xe8, 0x6c, 0x32, 0x67, 0x7c, 0x39, + 0x06, 0x80, 0xfe, 0x4a, 0x82, 0x29, 0x89, 0xb6, 0x61, 0x7e, 0x78, 0xc6, 0x90, 0x68, 0x3d, 0xf0, + 0xb4, 0xd2, 0xb4, 0xf3, 0x49, 0x58, 0x55, 0x80, 0x87, 0x74, 0xec, 0x49, 0xd1, 0xba, 0x23, 0x27, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4261,54 +4255,54 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_AD102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_AD102_sig_prod_data[] = { - 0x5f, 0x8a, 0x41, 0x9e, 0x07, 0x83, 0x8a, 0xe0, 0xa8, 0x10, 0x61, 0x44, 0x15, 0x1f, 0x45, 0xed, - 0x2a, 0x26, 0x5f, 0x8a, 0x22, 0xf5, 0x94, 0x3e, 0x9d, 0xda, 0xc9, 0x3c, 0xc3, 0x7d, 0xb3, 0xa3, - 0x0e, 0xdc, 0xf5, 0x42, 0xd5, 0x73, 0xad, 0x4d, 0x53, 0xb4, 0x0d, 0x9e, 0xe9, 0x72, 0x58, 0x74, - 0x5d, 0x71, 0x65, 0x31, 0x54, 0xe0, 0x87, 0x32, 0x1c, 0x55, 0x65, 0x96, 0x5c, 0x8a, 0x56, 0xcf, - 0xdf, 0x70, 0xed, 0x9b, 0xd3, 0x7d, 0x8a, 0x5b, 0x3f, 0x5c, 0x27, 0xd5, 0x0d, 0x2e, 0x93, 0x38, - 0xc1, 0xef, 0xf2, 0x31, 0xa9, 0x05, 0x53, 0x4c, 0x2c, 0x58, 0xb6, 0xa2, 0xfb, 0x5b, 0x7c, 0x28, - 0xd5, 0x95, 0xe9, 0xe5, 0x52, 0x11, 0xe3, 0x8b, 0x7a, 0xd8, 0xd5, 0xfe, 0x8f, 0xcc, 0x17, 0x40, - 0x8a, 0x57, 0x7a, 0x70, 0xe2, 0xe2, 0xb0, 0x40, 0x0c, 0x89, 0xda, 0xc4, 0xee, 0x5f, 0xc1, 0x0d, - 0xdb, 0x17, 0x28, 0x2f, 0x9d, 0xe1, 0x92, 0xaf, 0xdf, 0xb0, 0x78, 0x6f, 0xfc, 0xfa, 0x02, 0xb8, - 0x7b, 0x49, 0x9b, 0x65, 0x54, 0x57, 0x47, 0x02, 0xf7, 0xf4, 0x1c, 0xaa, 0x82, 0xd5, 0xff, 0xe2, - 0x63, 0x69, 0x43, 0x42, 0x86, 0x3f, 0xe8, 0xd4, 0x75, 0x41, 0xc6, 0xee, 0x70, 0x5e, 0xde, 0x1d, - 0xa5, 0x08, 0x52, 0x5e, 0x7d, 0x77, 0xc7, 0x55, 0x6a, 0x65, 0xa6, 0x16, 0x2a, 0xb8, 0xc6, 0xab, - 0x25, 0x22, 0xdd, 0x0a, 0x41, 0x56, 0x29, 0xc7, 0x15, 0x59, 0xdd, 0x16, 0x20, 0x1b, 0x4d, 0x45, - 0x9f, 0x09, 0xe6, 0xd3, 0x57, 0xdb, 0x7c, 0xeb, 0x1a, 0x29, 0xc5, 0xbd, 0xc7, 0xc0, 0x03, 0x85, - 0xc2, 0x17, 0xd9, 0xef, 0xf9, 0x75, 0x4c, 0xdf, 0x26, 0xac, 0xe6, 0x9a, 0x48, 0xbc, 0x04, 0x43, - 0xbe, 0x65, 0x55, 0x31, 0x80, 0xfd, 0xff, 0xd5, 0x67, 0x2a, 0x26, 0x81, 0x5c, 0x99, 0xd9, 0x33, - 0x6f, 0x22, 0x98, 0xb4, 0x12, 0xfc, 0x58, 0xb8, 0x75, 0x3d, 0x23, 0x7a, 0x20, 0xdb, 0x3c, 0xb7, - 0xa2, 0x78, 0x98, 0xdc, 0x9a, 0xd3, 0xde, 0xfb, 0x74, 0xbc, 0x33, 0x30, 0x6e, 0x8f, 0x36, 0xbd, - 0xdc, 0xcd, 0xac, 0x1a, 0x06, 0x7e, 0xe5, 0xd1, 0xee, 0xac, 0x68, 0xc9, 0xd8, 0x58, 0xa6, 0xd2, - 0x1c, 0x6d, 0x94, 0x0a, 0x5d, 0x67, 0x05, 0x4f, 0x3d, 0xcd, 0x88, 0xa4, 0x1b, 0xde, 0xe2, 0xcd, - 0x47, 0x19, 0x4d, 0x22, 0xa7, 0xb0, 0xdb, 0x4f, 0xbc, 0x2d, 0xaa, 0xc9, 0x7e, 0xf1, 0xa9, 0x72, - 0xc3, 0x30, 0xe5, 0xf0, 0x7a, 0x84, 0xad, 0x6e, 0x52, 0x9c, 0x55, 0xec, 0x3b, 0xc9, 0x25, 0xe2, - 0x26, 0x56, 0x65, 0x07, 0x0d, 0x24, 0x8f, 0x37, 0xb4, 0x69, 0xeb, 0xf4, 0x2b, 0x7e, 0xd7, 0x13, - 0x2f, 0x0e, 0x64, 0xed, 0xac, 0xa8, 0x03, 0xb7, 0x8c, 0xcc, 0x27, 0x99, 0xf7, 0x58, 0x56, 0x38, - 0x7b, 0xca, 0xe6, 0x99, 0x10, 0xf0, 0xe5, 0x43, 0x07, 0x59, 0x5a, 0x10, 0x86, 0x61, 0x94, 0xef, - 0x1b, 0x80, 0x69, 0xd8, 0xeb, 0xce, 0x50, 0xc2, 0x18, 0x93, 0x93, 0x35, 0x1f, 0x76, 0x96, 0x54, - 0xac, 0xfb, 0x40, 0xe1, 0x5e, 0xee, 0xca, 0x7d, 0x2d, 0x4c, 0x8b, 0x3d, 0x7a, 0xb4, 0xa7, 0x82, - 0xe4, 0x63, 0xc2, 0x7e, 0xb4, 0xa3, 0x82, 0xf6, 0x09, 0xa4, 0x31, 0x74, 0xf0, 0x43, 0x85, 0x17, - 0xa3, 0x46, 0x5e, 0x0a, 0x8a, 0xbf, 0xc2, 0x39, 0x7a, 0x13, 0x96, 0x19, 0xe4, 0x99, 0x06, 0xa7, - 0x05, 0x27, 0x4c, 0x8c, 0xf0, 0x74, 0xb4, 0x86, 0x40, 0xdd, 0xe2, 0xb1, 0xbb, 0x96, 0x69, 0x54, - 0x70, 0xac, 0x72, 0xad, 0xa0, 0x8b, 0x9c, 0x28, 0x65, 0xa5, 0x3c, 0x14, 0x31, 0x98, 0x94, 0x4c, - 0xa0, 0x11, 0x89, 0x4a, 0xe0, 0x11, 0x94, 0x53, 0xd5, 0xca, 0x0b, 0x28, 0xa9, 0x0f, 0xad, 0x02, - 0x40, 0xfd, 0x34, 0x0c, 0x79, 0xbb, 0x1e, 0x05, 0x4e, 0x87, 0xce, 0x14, 0x62, 0x26, 0x3c, 0x04, - 0xec, 0x4d, 0x88, 0xb6, 0x39, 0x63, 0x67, 0xa5, 0x1b, 0xa8, 0x35, 0xa2, 0xcd, 0x7a, 0xbc, 0x56, - 0xbe, 0x84, 0x43, 0x04, 0x9e, 0x1f, 0x58, 0x36, 0x9e, 0xfe, 0xa7, 0xad, 0x84, 0x28, 0xe5, 0xeb, - 0xed, 0x4c, 0x74, 0xff, 0xce, 0xe7, 0x00, 0x9f, 0xaf, 0xb0, 0x7d, 0x6b, 0x44, 0x2a, 0x41, 0xe5, - 0x63, 0xd8, 0x1a, 0xa7, 0x88, 0xfb, 0x8d, 0x5e, 0x09, 0x32, 0x69, 0xe1, 0x41, 0x8d, 0x52, 0xa1, - 0x69, 0x87, 0x2f, 0x1d, 0xcf, 0x7a, 0x67, 0x6b, 0x0f, 0x77, 0xb3, 0xb7, 0x58, 0x25, 0xf9, 0x87, - 0x86, 0x27, 0x3a, 0x03, 0xd6, 0x6d, 0x6c, 0x09, 0x56, 0xa0, 0xc4, 0x14, 0x7d, 0x63, 0xff, 0x7e, - 0x2a, 0x2f, 0xb7, 0x7f, 0xac, 0xe8, 0x52, 0xca, 0x77, 0x4d, 0x2a, 0xc5, 0xfc, 0x66, 0xba, 0xd2, - 0xb3, 0xd4, 0x27, 0x69, 0x8f, 0x31, 0xd4, 0x25, 0xc1, 0x94, 0x26, 0x96, 0xed, 0x99, 0xfa, 0x4c, - 0x76, 0xf6, 0xb1, 0x8d, 0xee, 0x42, 0x73, 0xc1, 0xab, 0x44, 0xe1, 0x9e, 0x93, 0x84, 0x55, 0xb1, - 0xa5, 0x7b, 0x90, 0x1b, 0xb6, 0xa9, 0x73, 0x20, 0x87, 0x69, 0x2e, 0x5a, 0xe2, 0x0e, 0xe0, 0xbb, - 0xb3, 0xb4, 0x93, 0x90, 0x0b, 0xe2, 0x17, 0xd6, 0x1d, 0xcb, 0x50, 0xba, 0xc7, 0x1a, 0xfb, 0x83, - 0x7f, 0x1b, 0x50, 0xe4, 0x80, 0x6a, 0x70, 0xae, 0xa0, 0xde, 0xbd, 0xa7, 0x21, 0x15, 0x1f, 0xd0, - 0x37, 0x3c, 0xc3, 0x78, 0xed, 0x00, 0x8f, 0x26, 0x08, 0xc0, 0x18, 0x27, 0x1f, 0x19, 0xc7, 0x4a, - 0x3b, 0x38, 0xbb, 0xc6, 0x0d, 0x64, 0x65, 0xcd, 0x9e, 0xba, 0xb5, 0x5c, 0x12, 0xe9, 0x28, 0x61, - 0x2e, 0xf2, 0xb4, 0xb5, 0xc7, 0xb9, 0xf8, 0xb9, 0x2f, 0x3e, 0x2f, 0x42, 0x9d, 0x88, 0xb6, 0x6a, + 0x82, 0xec, 0xc2, 0x9a, 0x4c, 0x83, 0xc1, 0xc0, 0xa8, 0x1d, 0x9d, 0x2a, 0xae, 0xa7, 0x07, 0x71, + 0xfc, 0x03, 0xfb, 0x13, 0xbb, 0x52, 0xda, 0x12, 0x23, 0x32, 0x7a, 0xfb, 0xe8, 0x9c, 0x63, 0x18, + 0x74, 0x36, 0xad, 0xc3, 0x4f, 0x49, 0x0e, 0x4f, 0x95, 0xb6, 0xe6, 0x46, 0xc0, 0x53, 0x3b, 0xdd, + 0x31, 0xd3, 0x52, 0xdf, 0x56, 0x85, 0xa4, 0x6c, 0x29, 0x2f, 0x91, 0x5f, 0xa1, 0x60, 0x08, 0x7a, + 0x55, 0xd9, 0x6d, 0x6c, 0xa4, 0xc4, 0x6a, 0x18, 0x29, 0x55, 0x88, 0x4c, 0x47, 0x94, 0x30, 0x66, + 0xa2, 0x3c, 0x91, 0x9c, 0x6c, 0xe6, 0x4a, 0x5c, 0x1e, 0x2b, 0xf8, 0x1b, 0x55, 0x58, 0xed, 0xce, + 0x59, 0x1e, 0xea, 0x05, 0xcf, 0x60, 0x34, 0x41, 0xfe, 0xd0, 0x1a, 0xec, 0xd8, 0x51, 0x40, 0xe5, + 0x9e, 0x4a, 0x3b, 0x85, 0xdc, 0x74, 0xa9, 0xc6, 0xbd, 0xa1, 0xb7, 0x53, 0x22, 0xcf, 0x88, 0x18, + 0x0f, 0xff, 0xf9, 0xa8, 0x6d, 0xa4, 0x67, 0x31, 0x46, 0x35, 0x27, 0x59, 0x31, 0xea, 0xd7, 0x3d, + 0xae, 0xa9, 0x5a, 0xbc, 0x15, 0x57, 0xca, 0x9e, 0x70, 0x60, 0xf4, 0x25, 0xea, 0xcb, 0xb1, 0x43, + 0xa5, 0x87, 0x56, 0x22, 0xa0, 0xbb, 0x3c, 0x3f, 0xe1, 0x35, 0x33, 0x1a, 0x2d, 0xfa, 0x70, 0x08, + 0x54, 0xa9, 0x41, 0x41, 0x03, 0x18, 0x28, 0x32, 0x2b, 0xba, 0x6c, 0xe4, 0x60, 0x7d, 0xc1, 0x4b, + 0xc2, 0x41, 0x82, 0x02, 0x68, 0xef, 0x10, 0x3b, 0x76, 0x38, 0x9e, 0x2b, 0xbd, 0x86, 0xc5, 0x39, + 0x17, 0xbb, 0xa5, 0x26, 0x0c, 0xc4, 0x89, 0xca, 0x32, 0x96, 0x23, 0x72, 0x5f, 0x51, 0x9a, 0x62, + 0xe0, 0x2b, 0xd7, 0x62, 0x03, 0x2e, 0x1c, 0x88, 0x97, 0x0c, 0xe0, 0x09, 0x96, 0xf1, 0x83, 0xc7, + 0x3a, 0xd7, 0x50, 0xaa, 0x9f, 0xb8, 0xe1, 0x8a, 0x81, 0xa6, 0xfb, 0xfe, 0x3e, 0xd9, 0xd4, 0x02, + 0x41, 0xf0, 0xf5, 0x68, 0x91, 0xcc, 0x5b, 0xf4, 0xb8, 0x21, 0x4f, 0x1e, 0xc7, 0x27, 0xe5, 0xd4, + 0x6d, 0x49, 0x3a, 0x85, 0x3a, 0x5a, 0xc4, 0xab, 0xa0, 0xf9, 0xfa, 0x62, 0x8c, 0x42, 0x7f, 0x05, + 0xa1, 0x92, 0x91, 0x06, 0xb0, 0x2e, 0x4b, 0x36, 0x2d, 0xcd, 0xca, 0x30, 0x24, 0x51, 0xcc, 0x4f, + 0x26, 0x65, 0xbc, 0xf8, 0x87, 0xc7, 0xb7, 0x8f, 0x01, 0xf4, 0x95, 0xdf, 0x05, 0x72, 0x10, 0x59, + 0xec, 0x8e, 0xcf, 0x0a, 0xa6, 0x17, 0x97, 0x6c, 0x04, 0x21, 0x6c, 0x22, 0x5b, 0xda, 0x71, 0x86, + 0xda, 0x21, 0x8c, 0x0a, 0xfc, 0x0a, 0x1b, 0xc3, 0x8a, 0x8c, 0xe0, 0x00, 0x52, 0xc9, 0x13, 0xa0, + 0x3c, 0xf4, 0xf2, 0x44, 0x2b, 0xb5, 0x56, 0x11, 0x95, 0x1d, 0xde, 0xa6, 0x5b, 0x19, 0x64, 0x9d, + 0xd2, 0xf9, 0x70, 0x36, 0xff, 0xe4, 0x08, 0xdf, 0x3d, 0x86, 0xe7, 0x9b, 0x0c, 0x9d, 0x08, 0x58, + 0xa8, 0x8e, 0x29, 0xdf, 0x6c, 0xb2, 0x68, 0x69, 0xff, 0x2e, 0x42, 0x42, 0x22, 0xdb, 0x87, 0xc7, + 0x8e, 0x10, 0x09, 0xc4, 0x37, 0x06, 0xc4, 0xb2, 0xd7, 0x8b, 0xe3, 0x3f, 0x8d, 0x49, 0x4d, 0xfa, + 0xc5, 0xbb, 0xeb, 0x2d, 0x03, 0xc9, 0x29, 0x69, 0x36, 0xf8, 0x5d, 0x93, 0xeb, 0xdb, 0xd9, 0xd2, + 0xe0, 0x30, 0x01, 0x53, 0x8a, 0x95, 0xa2, 0x92, 0x6a, 0x3a, 0x9d, 0x04, 0x22, 0x3b, 0x48, 0xf9, + 0xd8, 0x19, 0x79, 0xa9, 0x10, 0x39, 0xa9, 0x14, 0x4b, 0xef, 0x77, 0x9a, 0x9d, 0xd7, 0x76, 0x02, + 0x1b, 0x6b, 0x47, 0x17, 0x56, 0xee, 0x2e, 0x99, 0xef, 0x15, 0x23, 0x79, 0x51, 0x77, 0xf1, 0x09, + 0x83, 0xc0, 0x3e, 0xa6, 0xdd, 0xaf, 0xb1, 0x3f, 0xd4, 0xe1, 0x52, 0xa5, 0x51, 0x0c, 0x67, 0x0a, + 0x72, 0x39, 0xbc, 0x6f, 0x0a, 0xb1, 0x82, 0x86, 0x75, 0xe8, 0x27, 0xca, 0xb5, 0xb7, 0xb9, 0x35, + 0x33, 0x12, 0xfd, 0x46, 0xd5, 0x63, 0xb9, 0x7a, 0xe1, 0x6c, 0xf2, 0x7c, 0xd1, 0xbe, 0xa8, 0x96, + 0xc7, 0x32, 0xec, 0xab, 0xd8, 0xba, 0x65, 0x6c, 0x25, 0xc1, 0x10, 0xfb, 0xa8, 0x65, 0x51, 0xe7, + 0x72, 0xbe, 0x0f, 0x00, 0xfd, 0x54, 0xc1, 0x75, 0xdb, 0xe2, 0x9a, 0xd5, 0x09, 0x98, 0x58, 0x53, + 0xc4, 0x9e, 0xfe, 0x75, 0xd6, 0x95, 0x3b, 0xba, 0xf4, 0xc6, 0x95, 0x60, 0x73, 0x56, 0xef, 0x8a, + 0xef, 0xd6, 0x62, 0xcf, 0x58, 0xe8, 0x68, 0x43, 0x9b, 0x84, 0x35, 0x1d, 0xfa, 0xd2, 0xaf, 0x84, + 0xc3, 0x2d, 0x5a, 0x11, 0x21, 0xa7, 0x91, 0x44, 0x72, 0x61, 0x21, 0x47, 0xec, 0x2b, 0x43, 0xc7, + 0xdb, 0x46, 0x13, 0x2e, 0xa2, 0x91, 0xec, 0x32, 0x06, 0x4b, 0xd9, 0x63, 0x8a, 0xae, 0x64, 0x47, + 0xa9, 0x0d, 0xf9, 0xba, 0x38, 0x14, 0xb0, 0xbd, 0xea, 0x6d, 0xe2, 0xcf, 0xe1, 0x31, 0x43, 0xe7, + 0xdf, 0x92, 0x11, 0xd6, 0x1f, 0x6e, 0xea, 0x29, 0x0c, 0x2e, 0xeb, 0xd9, 0x8a, 0x87, 0x34, 0x9c, + 0x78, 0x6a, 0x72, 0x5b, 0x83, 0x23, 0x16, 0x95, 0x49, 0xb1, 0xc0, 0xaa, 0xcf, 0x1c, 0x62, 0x81, + 0x30, 0xe7, 0x97, 0xc2, 0x37, 0xff, 0x5a, 0x19, 0x01, 0x53, 0xf3, 0xa9, 0xc0, 0xa2, 0x79, 0x2a, + 0x86, 0x2d, 0x1b, 0xde, 0x09, 0xba, 0x8d, 0x38, 0x27, 0x9e, 0x44, 0x16, 0x10, 0x67, 0xb0, 0xbc, + 0x5b, 0xd4, 0xb6, 0x87, 0xeb, 0x22, 0xe0, 0xe7, 0x0c, 0x9e, 0x7d, 0xfe, 0x27, 0x80, 0x77, 0x46, + 0x9f, 0x06, 0x3e, 0x4f, 0xbb, 0xa7, 0x3e, 0x8f, 0x0a, 0x1a, 0x49, 0xff, 0xca, 0xc9, 0xae, 0x4b, + 0xaf, 0x8e, 0x8d, 0x29, 0xd3, 0xea, 0xdf, 0x7c, 0x3b, 0x1f, 0x23, 0x08, 0x25, 0x53, 0x8a, 0xf4, + 0x28, 0xf9, 0x3d, 0xa2, 0xbb, 0xb8, 0x8c, 0x88, 0x80, 0x0e, 0x7e, 0xd6, 0x9c, 0xaa, 0x38, 0x43, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c index ec40be1469..5d095d01f2 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c @@ -35,2143 +35,2141 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 60160 -// COMPRESSED SIZE (bytes): 34118 +// COMPRESSED SIZE (bytes): 34088 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = { - 0x94, 0xfd, 0x53, 0xd0, 0x30, 0x4d, 0xcf, 0x06, 0x8a, 0xde, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, - 0x78, 0x6e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0x6b, 0x7d, 0xff, 0xae, 0xda, - 0x27, 0xef, 0x3e, 0x58, 0xb5, 0xe7, 0x24, 0xe9, 0x54, 0x75, 0x57, 0x7a, 0xa6, 0xba, 0x27, 0x9d, - 0xa4, 0xaf, 0x48, 0x02, 0x20, 0xcc, 0x66, 0x00, 0xc4, 0x29, 0x60, 0x00, 0xf4, 0x1c, 0xe7, 0x7f, - 0xb4, 0xfc, 0x02, 0x4a, 0x02, 0x20, 0xfe, 0x9f, 0x40, 0x03, 0x03, 0xe0, 0xff, 0xd3, 0x8c, 0x00, - 0x00, 0x00, 0xfc, 0x4d, 0x06, 0xf0, 0xa5, 0x07, 0x00, 0x78, 0x07, 0x7a, 0x07, 0xf8, 0x00, 0x8a, - 0x01, 0x00, 0x02, 0xe8, 0xdb, 0xdd, 0xfb, 0xfb, 0xfb, 0x83, 0x8f, 0x00, 0x00, 0x04, 0xf8, 0xcb, - 0x03, 0x69, 0x3a, 0x06, 0x60, 0x4e, 0xdf, 0x00, 0x6c, 0x4a, 0x06, 0xa0, 0x49, 0xdf, 0x00, 0xfa, - 0x1f, 0x21, 0x4d, 0xdf, 0x00, 0xfe, 0x1f, 0xc1, 0xfb, 0x5f, 0x5f, 0x80, 0xf4, 0x3c, 0xe0, 0x96, - 0x3d, 0xe0, 0xbe, 0xbc, 0xfc, 0xbd, 0xf4, 0x3c, 0xc0, 0xf4, 0x0c, 0xa0, 0x96, 0x3d, 0xc0, 0x96, - 0x0d, 0x20, 0xdf, 0x3d, 0x00, 0x00, 0x78, 0x46, 0x49, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x9f, 0xfd, 0x03, 0x1f, 0x77, - 0x6d, 0xda, 0x00, 0xeb, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x67, 0x7f, 0x03, + 0x92, 0x3f, 0xad, 0x2f, 0x00, 0xeb, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2182,7 +2180,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 60160, // uncompressed data size (bytes) - 34118, // compressed data size (bytes) + 34088, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2234,2143 +2232,2141 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 60160 -// COMPRESSED SIZE (bytes): 34118 +// COMPRESSED SIZE (bytes): 34083 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] = { - 0x94, 0xfd, 0x53, 0xb0, 0x30, 0x4d, 0xcf, 0x00, 0x8a, 0x2e, 0xdb, 0xb6, 0x6d, 0x3c, 0xcb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xda, 0xdf, 0x7f, 0xaa, 0xce, - 0xcd, 0x7b, 0x2e, 0x76, 0x9d, 0xb9, 0x49, 0x3a, 0x55, 0xdd, 0x95, 0xe9, 0x49, 0x4f, 0xa7, 0x93, - 0x74, 0x22, 0x01, 0x80, 0x30, 0x9b, 0x01, 0x10, 0x27, 0x8f, 0x01, 0xd0, 0x73, 0x9c, 0xff, 0xd1, - 0xf2, 0x0b, 0x28, 0x01, 0x80, 0xf8, 0x7f, 0x04, 0x75, 0x0c, 0x80, 0xff, 0x4f, 0x33, 0x02, 0x00, - 0x00, 0xf0, 0x37, 0x19, 0xc0, 0x97, 0x1e, 0x00, 0xe0, 0x1d, 0xe8, 0x1d, 0xe0, 0x03, 0x28, 0x06, - 0x00, 0x08, 0xa0, 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0xc7, 0x13, 0x1a, 0x6a, 0x2d, 0xa7, 0x63, 0x08, 0xfa, 0xf8, + 0xe3, 0x9c, 0x92, 0xff, 0x5b, 0x93, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xcf, 0xfe, 0x01, 0xcb, 0x60, - 0x93, 0x51, 0x00, 0xeb, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f, 0xfb, 0x1b, 0xd8, 0xb3, 0x8b, 0xa5, 0x00, + 0xeb, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4381,7 +4377,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 60160, // uncompressed data size (bytes) - 34118, // compressed data size (bytes) + 34083, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -4437,30 +4433,30 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_data[] = { - 0x07, 0x54, 0xf1, 0x04, 0x77, 0x79, 0xfb, 0xfe, 0x7d, 0x9c, 0xd5, 0x2f, 0xd1, 0xf2, 0x5f, 0xe7, - 0xe2, 0xc3, 0x37, 0xd2, 0x9a, 0xed, 0x62, 0xcf, 0xb3, 0x44, 0xf9, 0xdd, 0x07, 0x37, 0xad, 0x02, - 0x56, 0x94, 0x26, 0x42, 0x09, 0x29, 0x9b, 0xa0, 0x7d, 0xaf, 0x0b, 0xdb, 0xa6, 0xbe, 0x48, 0xbd, - 0x52, 0x75, 0x2c, 0xc5, 0x18, 0x9d, 0x6a, 0x86, 0x5d, 0x63, 0x04, 0x7e, 0x45, 0x8e, 0x20, 0xf3, - 0xe4, 0x8f, 0xb0, 0x90, 0x64, 0x5e, 0xf4, 0x04, 0x16, 0xce, 0x3d, 0x51, 0xb5, 0xd4, 0x80, 0xa0, - 0x2f, 0x1d, 0x5a, 0x43, 0xe1, 0x66, 0x7c, 0x1a, 0x49, 0xe1, 0xe3, 0x87, 0xd5, 0x30, 0xe6, 0x2f, - 0x89, 0xc8, 0xc0, 0xf8, 0x1d, 0xe0, 0xe7, 0xf9, 0xa5, 0x08, 0x71, 0xf8, 0x46, 0x07, 0xdd, 0x13, - 0x43, 0x6d, 0x41, 0x14, 0xc3, 0x8c, 0x01, 0x69, 0xda, 0x99, 0x8e, 0xbd, 0x44, 0xd7, 0xde, 0xca, - 0x4c, 0x5e, 0xc1, 0x5c, 0x7f, 0xaf, 0x5b, 0x0b, 0x41, 0x87, 0x1d, 0x90, 0x6c, 0x9e, 0xb9, 0x0b, - 0x33, 0xce, 0xf7, 0xfb, 0xf6, 0x2b, 0xfa, 0x88, 0x38, 0x55, 0x04, 0x25, 0x9f, 0xe3, 0xc5, 0x26, - 0xee, 0xdc, 0xf8, 0x83, 0x7d, 0xf2, 0x10, 0x3f, 0x75, 0x57, 0x79, 0x71, 0xcd, 0xc3, 0x1a, 0x32, - 0xcc, 0x2e, 0xad, 0x91, 0x11, 0x03, 0x86, 0xb6, 0x78, 0xe4, 0x43, 0x51, 0x3a, 0x34, 0xec, 0xf8, - 0x96, 0x1f, 0x6f, 0x9d, 0x19, 0x26, 0x1e, 0xb0, 0xd2, 0xfe, 0xb0, 0x86, 0x91, 0x5e, 0x2f, 0x2c, - 0xb7, 0x63, 0x7d, 0xf4, 0x83, 0x37, 0x3c, 0xd5, 0x8d, 0x9d, 0xac, 0x0b, 0x37, 0x21, 0x9b, 0xa7, - 0xe1, 0x53, 0xb1, 0x51, 0x01, 0x05, 0xeb, 0x48, 0xe4, 0x24, 0x1b, 0xff, 0x37, 0x73, 0xd2, 0xf4, - 0x26, 0xb7, 0x97, 0xb5, 0x33, 0x2e, 0xfc, 0x9a, 0x0a, 0xf7, 0x15, 0x06, 0x4a, 0xd3, 0xf7, 0x35, - 0xef, 0xa1, 0xfe, 0xeb, 0xc9, 0xe7, 0xde, 0x4f, 0xd7, 0x2d, 0x5a, 0xf9, 0xa6, 0x0b, 0x5e, 0x42, - 0x80, 0x31, 0x9c, 0x47, 0xbb, 0xbe, 0x26, 0x47, 0x71, 0x57, 0xe6, 0x86, 0xf4, 0x71, 0x91, 0x3b, - 0xed, 0x9d, 0xf5, 0x45, 0x3a, 0x63, 0x4c, 0xad, 0x85, 0xfa, 0xfb, 0x43, 0x6b, 0x05, 0x3d, 0x97, - 0x9f, 0x0f, 0xd0, 0xee, 0xb8, 0x26, 0x84, 0x65, 0x83, 0x91, 0x04, 0x99, 0x7a, 0x09, 0x31, 0xdc, - 0xdf, 0xc9, 0x16, 0xcd, 0x63, 0x54, 0x84, 0x16, 0xd8, 0x35, 0x79, 0x1f, 0xf0, 0xcb, 0x4b, 0x5a, - 0x41, 0xbd, 0xfb, 0xd1, 0x66, 0x2c, 0x3f, 0xe1, 0xdf, 0xbb, 0xec, 0xab, 0xe2, 0xc8, 0x07, 0x91, - 0x52, 0x9c, 0x3e, 0x2c, 0x65, 0x86, 0xdf, 0xd3, 0xfa, 0x1b, 0xfc, 0x84, 0xfb, 0x44, 0x4f, 0x9b, - 0xe0, 0xe7, 0xbe, 0xc8, 0xa6, 0x84, 0x39, 0x06, 0x04, 0x28, 0x8d, 0x50, 0x07, 0x61, 0xe4, 0x77, + 0x4c, 0x4f, 0xd4, 0xf7, 0x36, 0x43, 0x53, 0x84, 0x3d, 0x91, 0x9a, 0x11, 0xf7, 0x8e, 0xf5, 0xc5, + 0x17, 0x37, 0x38, 0x3b, 0x12, 0x4b, 0x4c, 0x40, 0xea, 0x0d, 0xda, 0xca, 0x8e, 0xf9, 0x6b, 0xed, + 0xdc, 0xf2, 0x1e, 0x79, 0x81, 0xf3, 0xa3, 0x5d, 0x2c, 0x30, 0xe0, 0x07, 0x7a, 0x05, 0x75, 0x0c, + 0xe8, 0xbc, 0x2d, 0x52, 0x39, 0xe1, 0xa2, 0x4a, 0xad, 0x0e, 0xd1, 0x83, 0xaf, 0x1f, 0xed, 0xb1, + 0xd5, 0xcf, 0x36, 0xc6, 0xc6, 0xfa, 0x0c, 0x7c, 0xf6, 0x63, 0x9b, 0xa5, 0x9d, 0xc2, 0x72, 0x41, + 0xba, 0x1e, 0xa3, 0x42, 0x6c, 0x5c, 0x8c, 0xea, 0x18, 0x68, 0xf1, 0x7c, 0xbc, 0x9b, 0x66, 0xcc, + 0x8c, 0x8a, 0x0a, 0x60, 0xec, 0x93, 0x0e, 0x02, 0xd2, 0x3d, 0xef, 0xe1, 0x3d, 0xb6, 0xd1, 0xf5, + 0x94, 0x12, 0xe3, 0xb3, 0x6f, 0x6c, 0x51, 0x53, 0x7c, 0x30, 0x36, 0x11, 0x4a, 0x0a, 0x37, 0xf7, + 0x68, 0x17, 0xbf, 0x88, 0x62, 0x65, 0x44, 0x40, 0xf9, 0x2d, 0x18, 0x7c, 0x0d, 0x77, 0x0f, 0xa5, + 0xe7, 0x80, 0x55, 0x6b, 0x59, 0xd4, 0x6e, 0x4d, 0x0d, 0x60, 0x67, 0x08, 0x2a, 0x47, 0xeb, 0xf6, + 0x87, 0xde, 0xd2, 0x89, 0xb0, 0xc5, 0xd1, 0x27, 0xd1, 0xb8, 0xf9, 0xf3, 0xea, 0x85, 0x6c, 0x49, + 0x00, 0x00, 0xf0, 0x4f, 0xef, 0xfe, 0x3b, 0xc8, 0x22, 0x57, 0xd2, 0xef, 0x01, 0xec, 0x59, 0x7b, + 0x15, 0xe6, 0x6b, 0x66, 0x9b, 0x10, 0xea, 0x5d, 0xdf, 0x6e, 0x01, 0x79, 0x66, 0x8f, 0x2f, 0x46, + 0xf2, 0x46, 0x20, 0x1a, 0x26, 0x4d, 0xe3, 0xca, 0x0a, 0xa9, 0x3e, 0x9b, 0xbe, 0xaf, 0x4b, 0x92, + 0x1a, 0x77, 0x32, 0x99, 0xdf, 0x14, 0x28, 0xc1, 0x25, 0x12, 0x00, 0xa3, 0x7e, 0xda, 0xcc, 0x49, + 0xd0, 0x82, 0xef, 0x17, 0xce, 0xda, 0x0f, 0xf5, 0xf7, 0x4a, 0x90, 0xd7, 0xc9, 0x1e, 0x69, 0x10, + 0x30, 0xb8, 0xec, 0x86, 0x60, 0xd1, 0xd9, 0xcf, 0x8c, 0x3a, 0x19, 0x39, 0x77, 0x8b, 0x8b, 0x09, + 0x42, 0xb4, 0xae, 0xc0, 0x6e, 0xf8, 0x89, 0x15, 0x7d, 0xfa, 0x1e, 0x2a, 0xdd, 0xcc, 0x81, 0x21, + 0xf6, 0x45, 0x6d, 0xf9, 0xd3, 0xda, 0xac, 0x75, 0xc7, 0x4d, 0x12, 0xd9, 0xc6, 0x42, 0xee, 0xa3, + 0xea, 0xb9, 0x63, 0x8e, 0xac, 0xd9, 0xac, 0x9c, 0xd8, 0x97, 0xb8, 0xbc, 0x4f, 0xfb, 0x6c, 0x35, + 0xa6, 0xae, 0xb7, 0x22, 0x41, 0x3a, 0xf2, 0xc6, 0xc7, 0x1d, 0x1d, 0x96, 0xf7, 0x61, 0xe2, 0xd8, + 0xe6, 0x15, 0xb5, 0x1f, 0xa3, 0x01, 0x6b, 0xf1, 0x96, 0xcc, 0xcc, 0x84, 0xf5, 0x0f, 0x5b, 0x47, + 0x1a, 0xa0, 0x98, 0x4b, 0x9d, 0x04, 0x2f, 0x90, 0x0f, 0x2e, 0x70, 0x75, 0x26, 0x3c, 0x03, 0x06, + 0xc1, 0x6c, 0xcd, 0x77, 0xb3, 0x56, 0x25, 0x3b, 0xca, 0x3d, 0x47, 0xd0, 0xfd, 0x8b, 0xa4, 0x65, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4493,30 +4489,30 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_prod_data[] = { - 0x05, 0x9e, 0x26, 0xca, 0x84, 0x64, 0x4f, 0x75, 0xc7, 0xdb, 0x4c, 0x63, 0x4f, 0x01, 0xb6, 0x28, - 0x12, 0x38, 0xe3, 0x14, 0x88, 0x50, 0x7e, 0xd5, 0x1f, 0xcb, 0xb2, 0xc0, 0x19, 0x00, 0x64, 0xda, - 0x9a, 0x8c, 0xad, 0xcc, 0xf3, 0xe7, 0x25, 0xc3, 0x5a, 0x5f, 0x9c, 0xe5, 0xcf, 0xfc, 0xed, 0x14, - 0x45, 0x25, 0x5e, 0x3b, 0x17, 0xce, 0x49, 0x06, 0xa3, 0xed, 0xfc, 0x00, 0x94, 0xef, 0x37, 0xe9, - 0x9b, 0xcf, 0x7c, 0xc8, 0xcc, 0x12, 0xb1, 0x0c, 0x96, 0xfc, 0x43, 0x9b, 0x00, 0x63, 0x57, 0xb7, - 0x37, 0x94, 0x61, 0xa8, 0xb1, 0x29, 0xd5, 0x62, 0x79, 0x60, 0xd1, 0x85, 0xdc, 0x18, 0x62, 0x04, - 0x8d, 0x15, 0xc3, 0xdf, 0xec, 0xa0, 0x20, 0x28, 0xb8, 0x6b, 0x04, 0x3c, 0x4a, 0xdc, 0x9e, 0x3d, - 0xe6, 0x50, 0x81, 0xee, 0x15, 0x0f, 0x39, 0xcd, 0x63, 0xbb, 0x2b, 0xf3, 0x96, 0xbe, 0x52, 0x37, - 0x8e, 0x83, 0x7b, 0x04, 0xdb, 0xf2, 0x62, 0x02, 0xb1, 0x49, 0xc3, 0x6d, 0x27, 0x80, 0x51, 0x4e, - 0x9a, 0x7e, 0xe1, 0x47, 0xeb, 0x87, 0xf7, 0xd6, 0x58, 0x5f, 0xcc, 0xe7, 0xec, 0x22, 0x4a, 0x2c, - 0xa2, 0x63, 0x4a, 0x2e, 0xed, 0x94, 0xf7, 0x07, 0xe3, 0x41, 0xd9, 0xbb, 0xa5, 0x4e, 0x4a, 0x24, - 0x14, 0xb2, 0x33, 0xfd, 0xaa, 0x72, 0x28, 0x7b, 0x9f, 0xd0, 0x79, 0xb7, 0x75, 0x82, 0xd7, 0x4d, - 0x45, 0x3c, 0xfd, 0xfe, 0x5b, 0x45, 0x1d, 0x76, 0x05, 0x30, 0x21, 0xbd, 0x47, 0x17, 0x16, 0xf2, - 0xcc, 0x77, 0xbe, 0x2c, 0xd7, 0x96, 0x6f, 0x2b, 0x0c, 0x66, 0x2a, 0x31, 0xa8, 0x9c, 0xe6, 0x25, - 0x25, 0x4d, 0xd8, 0x2c, 0xcb, 0x23, 0x82, 0x9c, 0x48, 0xcf, 0x4d, 0x44, 0x94, 0x61, 0xb7, 0x8b, - 0x71, 0x32, 0xab, 0x8d, 0xf8, 0x04, 0x37, 0x4c, 0xc0, 0xff, 0x12, 0x0f, 0x43, 0x25, 0x9a, 0x42, - 0x0a, 0x80, 0x26, 0x9a, 0xa3, 0xaf, 0xc5, 0x9c, 0x4b, 0x7e, 0x4c, 0xe9, 0xb9, 0x2c, 0x89, 0x4d, - 0xa9, 0xd1, 0x10, 0x9b, 0x66, 0xea, 0x4e, 0x4f, 0x7c, 0x80, 0x19, 0x7a, 0x86, 0x3f, 0x96, 0x96, - 0x84, 0xab, 0xb9, 0x7f, 0x8e, 0x2e, 0x96, 0x2b, 0xc3, 0x50, 0xef, 0x90, 0x40, 0x27, 0xb7, 0xa6, - 0x5c, 0xce, 0x52, 0x4c, 0x37, 0x39, 0xed, 0x2d, 0x94, 0xf0, 0x31, 0x4f, 0x46, 0x96, 0xad, 0x21, - 0x91, 0x3e, 0x54, 0xed, 0x5a, 0xf9, 0x50, 0xa9, 0xdf, 0xdc, 0x28, 0x5b, 0x3c, 0xf4, 0xbe, 0x47, - 0x03, 0xf5, 0xc4, 0xa3, 0x52, 0xa9, 0x5b, 0x99, 0xcc, 0xc9, 0x27, 0x3e, 0x5f, 0x7c, 0x2a, 0x1a, - 0x4b, 0xe2, 0xb4, 0xe4, 0x0f, 0x14, 0x03, 0x76, 0x19, 0x35, 0x22, 0x15, 0xb6, 0x1a, 0x32, 0xb5, - 0x68, 0x72, 0x0e, 0xef, 0xbf, 0x88, 0xc5, 0x5d, 0xfc, 0x19, 0x4b, 0xf2, 0x1c, 0xef, 0x35, 0x35, + 0xc0, 0xc8, 0x4a, 0xd0, 0x6b, 0x5c, 0xdc, 0x7b, 0xd3, 0x65, 0x33, 0x13, 0xb2, 0x28, 0x84, 0xe5, + 0x19, 0xfe, 0xa5, 0xb0, 0xf6, 0x13, 0xec, 0x00, 0xab, 0x9b, 0xcf, 0x23, 0xa6, 0x38, 0xea, 0x7c, + 0x57, 0x25, 0x0a, 0xdc, 0x83, 0x4c, 0x54, 0xe9, 0xb0, 0x95, 0x39, 0xd6, 0x85, 0x41, 0x94, 0x94, + 0xf9, 0x0e, 0xb3, 0x3e, 0x9e, 0x9b, 0xcf, 0x91, 0x1d, 0xfb, 0x63, 0x23, 0xd7, 0x81, 0x21, 0x2c, + 0xf0, 0x83, 0x80, 0x6b, 0x88, 0xab, 0x30, 0xdd, 0x35, 0x2e, 0x29, 0x0c, 0x99, 0xb3, 0x05, 0xd2, + 0x77, 0xb8, 0x41, 0x71, 0x2e, 0xc8, 0x62, 0xa9, 0x09, 0x69, 0x52, 0x5a, 0x84, 0x51, 0x6b, 0x36, + 0x70, 0x89, 0x52, 0x11, 0x09, 0x6c, 0xa0, 0xea, 0x8b, 0xee, 0xb3, 0xe9, 0x24, 0x54, 0xc6, 0x5f, + 0xac, 0xf0, 0x6d, 0xaf, 0x7c, 0xcd, 0x43, 0x2c, 0x12, 0xd2, 0xaa, 0xb9, 0x61, 0x3f, 0xaa, 0x89, + 0x4e, 0xd9, 0x59, 0xae, 0xb8, 0x6c, 0x3f, 0x2f, 0xbf, 0x6c, 0xa4, 0x32, 0x17, 0xf7, 0x67, 0x5e, + 0xc5, 0xd2, 0x2e, 0x52, 0x20, 0x8a, 0xda, 0x80, 0xa6, 0xe9, 0xd7, 0xae, 0xbc, 0x32, 0xce, 0xa2, + 0xd2, 0xc5, 0xc8, 0x05, 0x62, 0x08, 0x1f, 0x8e, 0xfa, 0x3e, 0xea, 0x13, 0x9f, 0x5c, 0x27, 0xa9, + 0xd4, 0xc3, 0xbd, 0x41, 0xbb, 0x55, 0xf5, 0x10, 0x7c, 0x36, 0x73, 0x01, 0x0b, 0xc5, 0x73, 0x82, + 0x1a, 0xe2, 0xcd, 0x77, 0x8d, 0x07, 0x2d, 0x39, 0x8b, 0x28, 0x1e, 0xe5, 0xa2, 0x6a, 0xfc, 0x13, + 0x05, 0x99, 0xa1, 0xe9, 0x4b, 0xe2, 0xb1, 0xb9, 0xa8, 0x23, 0x64, 0x4d, 0x7c, 0xca, 0x91, 0xbe, + 0xbe, 0x9c, 0x97, 0xec, 0x08, 0xfe, 0xf9, 0xc8, 0xae, 0xd9, 0x81, 0x97, 0xee, 0x43, 0xaa, 0x5f, + 0x49, 0x43, 0xf7, 0x93, 0x4b, 0x11, 0x50, 0x95, 0x1b, 0x62, 0xe5, 0x29, 0xf1, 0x6e, 0x94, 0x92, + 0x80, 0xb9, 0x44, 0x57, 0xb3, 0x3f, 0x16, 0xbf, 0x53, 0x29, 0x60, 0xb7, 0x79, 0x27, 0x3a, 0x85, + 0xa0, 0xfe, 0x72, 0xf6, 0xb1, 0x2b, 0xf8, 0x5e, 0x37, 0x64, 0x09, 0xb2, 0x40, 0x14, 0x92, 0xe8, + 0x4d, 0x65, 0x5d, 0xfa, 0xb8, 0xb1, 0xc9, 0x43, 0xe1, 0x80, 0xab, 0x98, 0x5f, 0x0a, 0x7b, 0xf9, + 0x38, 0x88, 0x0a, 0x01, 0x95, 0x88, 0x71, 0xea, 0xab, 0xe1, 0xdb, 0x26, 0x23, 0xcc, 0x86, 0x6b, + 0x15, 0x6f, 0xeb, 0xac, 0xff, 0xf4, 0xb2, 0xdf, 0xdb, 0x27, 0xe0, 0x38, 0xc5, 0xb3, 0x2b, 0x7a, + 0x3a, 0x5f, 0xaf, 0x47, 0xb6, 0xfb, 0xde, 0x70, 0x9f, 0xc1, 0x49, 0x05, 0x52, 0x5d, 0x63, 0xfa, + 0x96, 0xdd, 0x4a, 0x12, 0x7e, 0x68, 0x71, 0x6d, 0xcf, 0xf0, 0x94, 0x61, 0xd4, 0xd2, 0x59, 0x48, + 0xd2, 0x14, 0xa1, 0xe2, 0x75, 0xfd, 0x5f, 0xa0, 0x7c, 0x63, 0x43, 0x1a, 0xa0, 0x8e, 0xa4, 0x23, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c index 08d690ddff..54a085717f 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c @@ -35,2180 +35,2184 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 60416 -// COMPRESSED SIZE (bytes): 34714 +// COMPRESSED SIZE (bytes): 34769 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data[] = { - 0xe4, 0x9d, 0xd3, 0x96, 0x28, 0x4a, 0xcf, 0x68, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xab, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xdd, 0xff, 0x77, 0xbd, 0xcf, 0x23, 0x9c, - 0x7a, 0x82, 0x54, 0xc6, 0x48, 0x2a, 0x9c, 0x05, 0x00, 0xf0, 0xff, 0xf7, 0xd1, 0x6b, 0x7a, 0xa0, - 0x04, 0xf9, 0x7b, 0x0e, 0xf5, 0x88, 0x98, 0x51, 0xc9, 0xfe, 0xd3, 0xf5, 0xc5, 0x6d, 0x4c, 0x2b, - 0xd7, 0xed, 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0xdc, 0x0a, 0xa7, + 0xb8, 0xdd, 0xc5, 0xda, 0xa4, 0xc8, 0xff, 0x9a, 0x59, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f, - 0xf9, 0x0f, 0x94, 0xa6, 0x6a, 0x41, 0x00, 0xec, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0xf2, 0x3f, 0xba, 0x65, 0xe4, 0xee, 0x00, 0xec, 0x00, + 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2219,7 +2223,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 60416, // uncompressed data size (bytes) - 34714, // compressed data size (bytes) + 34769, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2271,2180 +2275,2184 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 60416 -// COMPRESSED SIZE (bytes): 34716 +// COMPRESSED SIZE (bytes): 34773 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] = { - 0xe4, 0x5d, 0xe3, 0x9a, 0x30, 0xbc, 0xae, 0x1d, 0xdb, 0xf6, 0xbc, 0x63, 0xdb, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x3e, 0xfb, 0xf7, 0x77, 0x0b, 0xa7, 0x57, - 0x90, 0xf6, 0x69, 0x56, 0x57, 0x9a, 0x64, 0x05, 0x00, 0xe0, 0xff, 0xf7, 0x9a, 0x09, 0x84, 0x41, - 0x62, 0x73, 0xcd, 0x20, 0xe7, 0x15, 0x24, 0x2b, 0x5c, 0x77, 0xb3, 0xb1, 0xc0, 0x5f, 0xe7, 0x9b, - 0xb2, 0xed, 0xe1, 0x37, 0xb0, 0x0e, 0xe0, 0x29, 0x2a, 0xe9, 0x54, 0x41, 0xec, 0x7a, 0xd2, 0xaf, - 0x4a, 0x26, 0x38, 0x66, 0x45, 0x5e, 0x30, 0xb0, 0xf9, 0xd5, 0x24, 0x18, 0xd9, 0x5f, 0xa4, 0x83, - 0x0c, 0x02, 0x1a, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xe0, 0x7f, 0xf2, 0x1f, 0xa7, 0x87, 0x36, 0x2c, 0x00, 0xec, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x9f, 0xfc, 0x0f, 0xa7, 0xce, 0xfc, + 0xab, 0x00, 0xec, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4455,7 +4463,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 60416, // uncompressed data size (bytes) - 34716, // compressed data size (bytes) + 34773, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -4511,54 +4519,54 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_data[] = { - 0x14, 0x5a, 0x11, 0xa8, 0xa7, 0x39, 0x9d, 0x3f, 0x64, 0xf8, 0xb9, 0x10, 0x02, 0x3e, 0x44, 0xb1, - 0x7f, 0x17, 0x1e, 0xaa, 0x8e, 0x7e, 0x8b, 0x0a, 0x9c, 0xf9, 0x4b, 0x59, 0x75, 0x7e, 0x3f, 0xe6, - 0xd6, 0x2d, 0x4a, 0xa6, 0xbd, 0x01, 0x82, 0x2c, 0xb7, 0x7e, 0x77, 0x13, 0x06, 0xd6, 0xd3, 0xbf, - 0x8c, 0xeb, 0x4f, 0x08, 0x6c, 0x33, 0xb8, 0x17, 0x33, 0x4f, 0x4c, 0x0e, 0x31, 0x03, 0x5a, 0xb2, - 0x02, 0x9e, 0x4b, 0x1a, 0x26, 0x53, 0x1c, 0x8f, 0x5c, 0xab, 0x85, 0xe4, 0xb5, 0x8a, 0x9e, 0xe0, - 0x42, 0xca, 0xf1, 0xb4, 0x5a, 0x27, 0x48, 0xfd, 0x53, 0xc0, 0x80, 0xc8, 0x3c, 0xa3, 0xfe, 0x36, - 0x78, 0x4b, 0xc2, 0x68, 0xdf, 0xc1, 0x4e, 0x41, 0x8e, 0x1b, 0xe1, 0x50, 0xa3, 0x7d, 0x14, 0x0e, - 0xa7, 0xc3, 0x1e, 0x08, 0x86, 0xf1, 0xc1, 0xe5, 0x3b, 0xaf, 0x9c, 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0xfe, 0x78, 0xdb, + 0xa2, 0x65, 0x8d, 0xdb, 0x8a, 0x64, 0xdc, 0x67, 0xb5, 0x84, 0x9b, 0x9e, 0x3c, 0x7b, 0xc8, 0xe3, + 0x46, 0xfc, 0x85, 0x9f, 0xd2, 0x32, 0x2b, 0xe2, 0x0e, 0xe8, 0xed, 0xb6, 0x9e, 0xb3, 0x90, 0xc5, + 0x7a, 0x83, 0x58, 0x6e, 0xa5, 0x72, 0x7e, 0xd6, 0x5e, 0xa5, 0x5b, 0x72, 0xd9, 0x0d, 0xc1, 0xb3, + 0x8e, 0xe5, 0xa5, 0x7d, 0x3e, 0x76, 0x4e, 0x27, 0xcb, 0xe5, 0x6c, 0xd8, 0x81, 0x43, 0x07, 0x8a, + 0x37, 0xda, 0x1b, 0x70, 0x99, 0x4d, 0x58, 0x3a, 0xef, 0xe4, 0x42, 0xfe, 0xc6, 0xd2, 0x5b, 0x33, + 0xcc, 0xbc, 0x4b, 0x6f, 0xae, 0x35, 0xdc, 0x7f, 0x7b, 0xa5, 0xea, 0xc3, 0x13, 0x4d, 0x7a, 0x2f, + 0xcb, 0xb5, 0x3d, 0x4a, 0xe7, 0x94, 0xb7, 0xf3, 0x98, 0x48, 0xac, 0x33, 0x74, 0xd6, 0xf1, 0x58, + 0xb0, 0x73, 0xe6, 0xf2, 0x57, 0x0f, 0x55, 0x96, 0x5e, 0x39, 0xaf, 0x36, 0x47, 0xfc, 0xd5, 0x3b, + 0x96, 0x6b, 0x55, 0x7e, 0x1f, 0xee, 0x9d, 0xef, 0x7b, 0x54, 0xf5, 0x53, 0x7b, 0xe6, 0x9a, 0xec, + 0xc5, 0x0c, 0x36, 0xe7, 0xa5, 0x36, 0x31, 0x8c, 0x82, 0x01, 0x05, 0x00, 0xe0, 0xe2, 0x5a, 0x2d, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c index e73fddf936..e55969a3e4 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c @@ -34,2046 +34,2111 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 57856 -// COMPRESSED SIZE (bytes): 32546 +// DATA SIZE (bytes): 59136 +// COMPRESSED SIZE (bytes): 33589 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data[] = { - 0xed, 0xdd, 0x43, 0xb0, 0x2d, 0x4d, 0x17, 0x30, 0xe8, 0x63, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x71, - 0x8f, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb8, 0xc7, 0x36, 0xfb, 0xfd, 0x7b, 0xd6, - 0xdf, 0xa4, 0x07, 0x1d, 0x3d, 0xbb, 0xcf, 0x24, 0x2b, 0x2b, 0x62, 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0x35, 0xa7, 0x66, 0x35, 0x9e, 0x36, 0xcd, 0x8e, + 0x96, 0x4e, 0xab, 0xd5, 0x1c, 0xed, 0xff, 0x9e, 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x9f, 0xfc, 0x01, 0x41, 0x23, 0x5e, + 0x1a, 0x00, 0xe7, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2083,8 +2148,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 57856, // uncompressed data size (bytes) - 32546, // compressed data size (bytes) + 59136, // uncompressed data size (bytes) + 33589, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2106,8 +2171,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x00, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x01, 0x81, 0xef, 0x07, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x05, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xb4, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x2d, 0x11, 0xc0, 0xa2, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2135,2045 +2200,2110 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 57856 -// COMPRESSED SIZE (bytes): 32543 +// DATA SIZE (bytes): 59136 +// COMPRESSED SIZE (bytes): 33584 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_prod_data[] = { - 0xed, 0xdd, 0x43, 0xb0, 0xe8, 0xce, 0x1b, 0x30, 0xe8, 0x63, 0xfb, 0x1e, 0xdb, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdc, 0x63, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0x39, 0xf3, 0xff, 0x66, - 0x37, 0xbf, 0xcd, 0x2c, 0xa6, 0x66, 0x77, 0x9f, 0x4d, 0xa7, 0x53, 0x95, 0xbc, 0x49, 0xa5, 0xd2, - 0x9d, 0xee, 0xaa, 0xf4, 0x2b, 0x01, 0x80, 0x30, 0x93, 0x0e, 0x10, 0x2b, 0x8f, 0x0a, 0xd0, 0x7d, - 0x94, 0xf7, 0xde, 0xfc, 0x03, 0x28, 0x01, 0x80, 0xf8, 0x7f, 0x76, 0xa8, 0xa3, 0x02, 0xfc, 0xdf, - 0xd5, 0x70, 0x00, 0x00, 0xc0, 0x9f, 0x24, 0x00, 0x1f, 0x3a, 0x00, 0x80, 0x37, 0xa0, 0x37, 0x80, - 0x77, 0xa0, 0x68, 0x00, 0x20, 0x80, 0xde, 0x9d, 0xdd, 0xdf, 0xdf, 0x5f, 0xf8, 0x70, 0x00, 0x40, - 0x80, 0xdf, 0x5c, 0x90, 0xc6, 0x23, 0x00, 0xa6, 0xb4, 0x75, 0xc0, 0xc6, 0x24, 0x00, 0xea, 0xb4, - 0x75, 0xa0, 0xff, 0x15, 0x24, 0x69, 0xeb, 0xc0, 0xff, 0x2b, 0x70, 0xff, 0x77, 0x2c, 0x40, 0x5a, - 0x2e, 0x70, 0xf3, 0x2e, 0x70, 0x6f, 0x6e, 0xde, 0x6e, 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0x7d, 0x69, 0xe8, 0xae, 0xcf, 0xdd, 0xe4, 0xcc, 0xaa, 0xd1, + 0x81, 0x69, 0xb5, 0xe4, 0xc7, 0x5e, 0x61, 0xa9, 0x28, 0x3b, 0xab, 0x9c, 0xcd, 0x08, 0x10, 0x6f, + 0x8d, 0xd7, 0x76, 0xfb, 0x1a, 0xfc, 0xc2, 0x2a, 0x4f, 0x5b, 0xcd, 0x35, 0xd3, 0xd6, 0xd7, 0xa3, + 0xcc, 0x45, 0xb5, 0xfc, 0x4c, 0x02, 0xef, 0x1b, 0x73, 0x99, 0x40, 0xbc, 0x63, 0x32, 0x33, 0xcb, + 0xdc, 0xfe, 0xf7, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe4, 0x0f, 0x90, 0x10, 0xa9, 0xc0, 0x00, 0xe7, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4183,8 +4313,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 57856, // uncompressed data size (bytes) - 32543, // compressed data size (bytes) + 59136, // uncompressed data size (bytes) + 33584, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -4206,8 +4336,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x00, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x01, 0x81, 0xef, 0x07, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x05, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xb4, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x2d, 0x11, 0xc0, 0xa2, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4240,7 +4370,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_data[] = { - 0x35, 0xf3, 0x0d, 0xc6, 0x2e, 0xd9, 0x46, 0x85, 0x11, 0x15, 0x02, 0xf4, 0x79, 0x66, 0x8c, 0x7f, + 0x0a, 0xb3, 0x76, 0x6d, 0x2b, 0x50, 0x73, 0x34, 0x87, 0x9f, 0xf5, 0xe3, 0xec, 0x24, 0xd8, 0x16, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4273,7 +4403,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_prod_data[] = { - 0x6f, 0xd9, 0x1c, 0x5f, 0x93, 0x33, 0x88, 0x10, 0x6f, 0x5d, 0xa8, 0x9b, 0xf4, 0xf6, 0x32, 0xdc, + 0xaf, 0x7e, 0x99, 0x48, 0x66, 0x6d, 0x9c, 0xf2, 0xb2, 0x63, 0x62, 0xf0, 0x82, 0x97, 0x9c, 0xa4, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4306,7 +4436,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_patch_loc_data[] = { - 0x00, 0x82, 0x00, 0x00, + 0x00, 0x87, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c index fbb95f852f..d57f16db04 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c @@ -34,2046 +34,2114 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 57856 -// COMPRESSED SIZE (bytes): 32550 +// DATA SIZE (bytes): 58880 +// COMPRESSED SIZE (bytes): 33639 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = { - 0xed, 0xdd, 0x43, 0xb4, 0xe8, 0x4c, 0x1b, 0x28, 0xe8, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xad, - 0xb3, 0x6d, 0xdb, 0xb6, 0x6d, 0xe3, 0x6c, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xee, 0x7f, 0x7b, 0xd6, - 0xdf, 0xb4, 0x07, 0x3d, 0x39, 0xcf, 0xa4, 0x52, 0x59, 0x2b, 0x79, 0x93, 0x95, 0x54, 0x25, 0x95, - 0x5a, 0xa9, 0x92, 0x04, 0x40, 0x98, 0xc9, 0x00, 0x88, 0x53, 0x40, 0x03, 0xe8, 0x3e, 0xca, 0x7f, - 0x6f, 0xfe, 0x01, 0x94, 0x04, 0x40, 0xfc, 0xbf, 0x2b, 0x34, 0xd0, 0x00, 0xfe, 0x9f, 0x6c, 0x04, - 0x00, 0x00, 0xe0, 0x4f, 0x32, 0x80, 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0x8e, + 0xdd, 0x30, 0x48, 0x35, 0x65, 0xce, 0x6d, 0xf4, 0xa4, 0xc7, 0x59, 0xca, 0x8b, 0x0c, 0xc7, 0x5b, + 0x6d, 0xb7, 0x3d, 0x25, 0x6a, 0x9b, 0xcf, 0x15, 0x04, 0xb7, 0xa9, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0xf9, 0x0b, 0x57, + 0xa7, 0x83, 0xf8, 0x00, 0xe6, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2083,8 +2151,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 57856, // uncompressed data size (bytes) - 32550, // compressed data size (bytes) + 58880, // uncompressed data size (bytes) + 33639, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2106,8 +2174,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x00, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x01, 0x81, 0xef, 0x07, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x01, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x34, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xef, 0x1f, 0x77, 0xe5, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2135,2046 +2203,2114 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 57856 -// COMPRESSED SIZE (bytes): 32550 +// DATA SIZE (bytes): 58880 +// COMPRESSED SIZE (bytes): 33639 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_prod_data[] = { - 0xed, 0xdd, 0x43, 0xb4, 0xe8, 0x4c, 0x1b, 0x28, 0xe8, 0x6d, 0xdb, 0xb6, 0x71, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xc6, 0xd9, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x36, 0xef, 0x7f, 0x7b, 0xd6, - 0xdf, 0xb4, 0x07, 0x3d, 0x39, 0xcf, 0xa4, 0x52, 0xc9, 0x4a, 0xde, 0x64, 0x65, 0x15, 0x92, 0xac, - 0x54, 0x49, 0x00, 0x20, 0xcc, 0xa4, 0x03, 0xc4, 0xca, 0xa3, 0x01, 0x74, 0x1f, 0xe5, 0xbd, 0x37, - 0xff, 0x00, 0x4a, 0x00, 0x20, 0xfe, 0xdf, 0x15, 0xea, 0x68, 0x00, 0xff, 0x4f, 0x36, 0x02, 0x00, - 0x00, 0xf0, 0x27, 0x09, 0xc0, 0x97, 0x0e, 0x00, 0xe0, 0x0d, 0xe8, 0x0d, 0xe0, 0x1d, 0xe8, 0x2f, - 0x00, 0x10, 0x40, 0xef, 0xce, 0xee, 0xef, 0xef, 0x2f, 0x7c, 0x04, 0x00, 0x20, 0xc0, 0x6f, 0x2e, - 0x48, 0xe3, 0x11, 0x00, 0x53, 0xda, 0x3a, 0x60, 0x63, 0x12, 0x00, 0x4d, 0xda, 0x3a, 0xd0, 0xff, - 0x12, 0xd2, 0xb4, 0x75, 0xe0, 0xff, 0x25, 0x78, 0xff, 0xdb, 0x17, 0x20, 0x2d, 0x17, 0xb8, 0x79, - 0x17, 0xb8, 0x37, 0x37, 0x6f, 0x37, 0x2d, 0x17, 0x30, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xcb, 0x3f, 0x1e, + 0xa9, 0x77, 0x95, 0x00, 0xe6, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4184,8 +4320,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 57856, // uncompressed data size (bytes) - 32550, // compressed data size (bytes) + 58880, // uncompressed data size (bytes) + 33639, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -4207,8 +4343,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x00, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0xd4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x01, 0x81, 0xef, 0x07, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x6e, 0x01, 0xe2, 0x24, 0x08, 0x13, 0x4c, 0x34, 0x43, 0x69, + 0x20, 0x00, 0x00, 0xef, 0x1f, 0x77, 0xe5, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4241,7 +4377,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_data[] = { - 0x75, 0xab, 0xe0, 0xf9, 0x23, 0xd4, 0x29, 0xe5, 0xd5, 0xf8, 0x2f, 0xb6, 0x1f, 0x26, 0x78, 0x4e, + 0xfb, 0x98, 0xf9, 0xe8, 0x29, 0x02, 0x05, 0x3b, 0xc0, 0xb5, 0x5f, 0x8b, 0xc5, 0x37, 0x99, 0xb0, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4274,7 +4410,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_prod_data[] = { - 0x8a, 0x45, 0xae, 0x9f, 0x1d, 0xc7, 0x75, 0xef, 0x43, 0x34, 0x5e, 0xb0, 0x34, 0xdd, 0xd2, 0x82, + 0xc8, 0xfd, 0x49, 0x0d, 0xbf, 0xab, 0xcd, 0x29, 0x89, 0x0a, 0x80, 0x5c, 0x9f, 0x66, 0x5b, 0x8a, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -4307,7 +4443,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_patch_loc_data[] = { - 0x00, 0x82, 0x00, 0x00, + 0x00, 0x86, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c index 87a52b14e9..6bf9a61df2 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c @@ -39,1273 +39,1273 @@ // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_dbg_data[] = { - 0xed, 0xdc, 0x73, 0x8c, 0x6d, 0x4d, 0x1b, 0x20, 0xfa, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, + 0xed, 0xdc, 0x63, 0x8c, 0x6d, 0xcd, 0x1b, 0x20, 0xfa, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0x69, 0xdb, 0xb6, 0x6d, 0x9c, 0xb6, 0x8d, 0xd3, 0xee, 0xd3, 0xb6, 0x6d, 0xdb, 0xb6, 0xef, 0x3b, - 0x77, 0xbe, 0xc9, 0x9d, 0xbc, 0xb9, 0x93, 0xf9, 0x63, 0x6e, 0x72, 0x93, 0x99, 0xfe, 0x25, 0x4f, - 0x56, 0xd5, 0xda, 0x95, 0x3c, 0xbb, 0xd6, 0xde, 0xd9, 0xa9, 0x5a, 0xab, 0x6a, 0x03, 0x00, 0xfc, - 0x9f, 0x4d, 0xef, 0xcf, 0x2d, 0x25, 0xc8, 0xf7, 0x43, 0x88, 0x7b, 0xf8, 0xa4, 0xca, 0xef, 0x6f, - 0x5d, 0x1f, 0xdc, 0x86, 0xd4, 0x32, 0xdd, 0x0e, 0xee, 0xd3, 0xfa, 0x7d, 0xc2, 0xf3, 0x92, 0x91, - 0x8d, 0x02, 0x6e, 0xc2, 0xec, 0xd1, 0x1a, 0x1f, 0xa7, 0xe8, 0x10, 0xdb, 0x70, 0x95, 0x58, 0xa9, - 0x9b, 0x36, 0xff, 0xc2, 0x07, 0x7b, 0xbc, 0x0e, 0x5f, 0xea, 0x0b, 0xa3, 0x3e, 0xf1, 0x97, 0xac, - 0xd7, 0x8e, 0xa3, 0x8e, 0x94, 0xe1, 0x18, 0xea, 0x90, 0x36, 0xc8, 0x2a, 0xef, 0x54, 0xeb, 0x4b, - 0x8a, 0xb5, 0x96, 0x35, 0x61, 0x0b, 0xec, 0x24, 0x96, 0x00, 0xc8, 0xba, 0x50, 0xbe, 0xfa, 0x6a, - 0x6c, 0xcf, 0xd5, 0xd2, 0x02, 0xc5, 0xb3, 0x81, 0xaa, 0xa3, 0xfd, 0x0b, 0x1d, 0x61, 0xee, 0x44, - 0x74, 0x7d, 0xab, 0xc1, 0x8e, 0x23, 0x48, 0xcd, 0x1b, 0x41, 0x30, 0x4e, 0x99, 0xbe, 0xc8, 0xe9, - 0x79, 0x5f, 0xb9, 0x3d, 0x12, 0x78, 0x51, 0x57, 0x28, 0x0a, 0x18, 0xc3, 0x29, 0x0e, 0x4d, 0x8c, - 0x3a, 0xbf, 0x79, 0x8e, 0xc5, 0xa1, 0xd0, 0x20, 0x22, 0x76, 0xab, 0xb3, 0x15, 0x44, 0xcd, 0xc6, - 0x51, 0x89, 0xbd, 0xa6, 0x92, 0xbb, 0x07, 0xa4, 0x22, 0xf3, 0x51, 0xf9, 0x99, 0x3b, 0x30, 0xfd, - 0xa2, 0x0e, 0xe4, 0xaa, 0x84, 0xa7, 0xa9, 0xae, 0xab, 0x54, 0x7e, 0xb0, 0x77, 0x09, 0xc2, 0x0a, - 0x1a, 0xca, 0x84, 0xde, 0x6a, 0x06, 0xff, 0xd9, 0xa1, 0x15, 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0x3b, 0xe9, 0xa2, - 0x1b, 0x80, 0x10, 0x2c, 0xe2, 0x74, 0x4d, 0x8d, 0xe3, 0x0f, 0x2d, 0xde, 0x6d, 0xba, 0xa7, 0xb0, - 0x9c, 0x5f, 0x5a, 0xa3, 0x15, 0xda, 0x47, 0x92, 0x1c, 0xea, 0xa1, 0x73, 0x40, 0xd5, 0xf2, 0xd2, - 0xcf, 0x69, 0x2c, 0x75, 0xbc, 0xcd, 0xa0, 0xeb, 0x75, 0xa6, 0x83, 0x8a, 0x47, 0x6f, 0x37, 0x66, - 0xc2, 0xa9, 0xb5, 0xeb, 0xf3, 0xeb, 0xee, 0xae, 0xa1, 0x2d, 0xbc, 0x2d, 0xd4, 0x08, 0xa7, 0x15, - 0xb8, 0x46, 0x4d, 0x5b, 0x48, 0x8c, 0xf8, 0x11, 0x5f, 0x36, 0x5c, 0x27, 0x35, 0xd5, 0x65, 0x0a, - 0x7c, 0x51, 0x4d, 0x75, 0x0c, 0x6c, 0x48, 0x79, 0xe4, 0xd9, 0xe3, 0xb8, 0x31, 0x98, 0x74, 0x67, - 0x4b, 0xa0, 0x92, 0xe5, 0x51, 0x81, 0xb2, 0x0e, 0x01, 0x51, 0xc5, 0xdd, 0x2f, 0xe1, 0xeb, 0x3b, - 0x4a, 0x7e, 0xd2, 0xe9, 0xbf, 0x2f, 0x0b, 0x84, 0x3a, 0xb7, 0x9d, 0xdb, 0x07, 0x9f, 0x3c, 0xb4, - 0xfb, 0x7b, 0xe2, 0x76, 0x17, 0xf8, 0xbc, 0xe4, 0x1c, 0x9d, 0x4e, 0x03, 0xde, 0x28, 0xc7, 0x17, - 0x3a, 0xc3, 0x01, 0x17, 0xa4, 0x29, 0x8b, 0x20, 0xfa, 0xdd, 0x9c, 0x97, 0x21, 0x6c, 0xfe, 0xa2, - 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0x9b, 0x59, 0x5a, 0xe2, 0x12, 0x59, 0x64, 0xbb, 0x59, 0xad, 0xa2, 0xa8, 0xf6, - 0x0b, 0x25, 0x58, 0x8d, 0xef, 0x8b, 0x1e, 0x2e, 0x81, 0x46, 0xee, 0x5c, 0xfe, 0x9b, 0xa4, 0x33, - 0xb4, 0x68, 0xd0, 0xe7, 0x8b, 0x95, 0xe1, 0xb7, 0x64, 0x02, 0x80, 0x1e, 0x4e, 0x4d, 0x13, 0xc8, - 0x73, 0x7c, 0xac, 0x61, 0x6a, 0x71, 0xfc, 0xd8, 0x9b, 0xc0, 0x29, 0x54, 0x4c, 0xbc, 0xe1, 0xc6, - 0x6c, 0x44, 0xec, 0xae, 0x03, 0x9e, 0x25, 0x71, 0x44, 0x09, 0xba, 0x42, 0x02, 0x9f, 0x5b, 0x6e, - 0xe7, 0x89, 0x6d, 0xc5, 0x60, 0x89, 0x18, 0xcd, 0xee, 0xd6, 0xaa, 0x72, 0xf4, 0xc5, 0xe4, 0x33, - 0xef, 0x42, 0x61, 0xb8, 0x4b, 0xb4, 0xf3, 0xc9, 0xd1, 0x6b, 0xd6, 0x6c, 0xc1, 0xb9, 0x21, 0x66, - 0x3e, 0x25, 0x86, 0x1d, 0x47, 0x7d, 0xab, 0x3b, 0x63, 0x09, 0x67, 0xfd, 0x3b, 0x11, 0x1a, 0x1a, - 0x83, 0xf1, 0xf0, 0x97, 0xe4, 0x2a, 0xbd, 0x80, 0x8c, 0x7a, 0x7e, 0xc5, 0x34, 0xc3, 0xad, 0x8b, - 0x03, 0xe9, 0x9b, 0xd1, 0xde, 0xc1, 0x9b, 0x3f, 0x78, 0x97, 0x01, 0xfb, 0x41, 0x8a, 0xdc, 0xe1, - 0x8a, 0x95, 0x39, 0x3a, 0x88, 0x7c, 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0x9e, + 0xea, 0x7f, 0xa1, 0x2f, 0x34, 0x80, 0xff, 0xfa, 0xfd, 0x63, 0xfe, 0xbb, 0x7e, 0x40, 0x20, 0xfe, + 0xc7, 0xed, 0xd3, 0xfe, 0xbb, 0x72, 0xfa, 0x3f, 0x91, 0xf1, 0x4f, 0x88, 0xff, 0x13, 0x12, 0xff, + 0x84, 0xe4, 0x3f, 0x21, 0xf5, 0x9f, 0xcf, 0x64, 0xfe, 0x73, 0x94, 0xfd, 0x57, 0x3f, 0x0a, 0xff, + 0xad, 0x1f, 0x99, 0xff, 0xfc, 0x06, 0x00, 0xff, 0x5c, 0x62, 0x00, 0x65, 0x51, 0x86, 0xff, 0x85, + 0x31, 0xfc, 0xef, 0xe4, 0xff, 0x02, 0x38, 0x87, 0xd9, 0xe0, 0x00, 0x9f, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1368,1278 +1368,1277 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_dbg_storage_pvt // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 40704 -// COMPRESSED SIZE (bytes): 20273 +// COMPRESSED SIZE (bytes): 20270 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data[] = { - 0xed, 0xdc, 0x73, 0x8c, 0xac, 0xcd, 0x1f, 0x20, 0xfa, 0xb1, 0xce, 0xd8, 0xb6, 0xad, 0x33, 0xb6, - 0x6d, 0xdb, 0xb6, 0xcd, 0x33, 0xb6, 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0xff, 0xef, 0xe7, + 0x53, 0xfd, 0x2f, 0xd4, 0x85, 0x06, 0xf0, 0x5f, 0x9f, 0x7f, 0xd4, 0x7f, 0x57, 0x0f, 0x08, 0xc4, + 0xff, 0xf8, 0xfc, 0x94, 0xff, 0x2e, 0x9f, 0xfa, 0x4f, 0xa4, 0xfd, 0x13, 0x62, 0xff, 0x84, 0xf8, + 0x3f, 0x21, 0xf1, 0x4f, 0x48, 0xfe, 0xe7, 0x31, 0xe9, 0xff, 0xa4, 0x32, 0xff, 0xaa, 0x47, 0xfe, + 0xbf, 0xd5, 0x23, 0xfd, 0x9f, 0xd7, 0x00, 0xe0, 0x9f, 0x2e, 0x06, 0x50, 0x12, 0x61, 0xf8, 0x5f, + 0x68, 0xc3, 0xff, 0x4e, 0xfe, 0x2f, 0x4b, 0x5b, 0xf9, 0xf8, 0x00, 0x9f, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2650,7 +2649,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 40704, // uncompressed data size (bytes) - 20273, // compressed data size (bytes) + 20270, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_AD102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2706,54 +2705,54 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_AD102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_AD102_sig_dbg_data[] = { - 0x23, 0xa1, 0x9f, 0x25, 0x68, 0xe0, 0x5d, 0xe1, 0xe2, 0xa2, 0x20, 0x2d, 0x8d, 0x6c, 0x88, 0x5f, - 0x7c, 0xe8, 0x9d, 0xd3, 0xb6, 0x3b, 0xf2, 0x25, 0xdf, 0x05, 0xc2, 0x8e, 0x6a, 0x9b, 0x0a, 0x19, - 0xe4, 0x8c, 0xc4, 0x38, 0xfc, 0xb5, 0x1d, 0x58, 0x09, 0x21, 0x90, 0x9e, 0xda, 0x61, 0x28, 0xce, - 0x13, 0x09, 0x3b, 0xda, 0xef, 0xf2, 0x0c, 0x86, 0xa5, 0x42, 0xa5, 0x9e, 0xb5, 0xf5, 0x8c, 0x9e, - 0x80, 0x87, 0x6d, 0x41, 0x27, 0xfb, 0x9e, 0xb4, 0x58, 0x67, 0x65, 0xa3, 0xfd, 0x9d, 0x4f, 0x0a, - 0xd3, 0xf0, 0x92, 0xfe, 0xd5, 0x25, 0x65, 0xca, 0x66, 0xa3, 0xdd, 0x1f, 0xaa, 0x72, 0x10, 0xc7, - 0x38, 0xaa, 0xd0, 0xf3, 0x48, 0x30, 0x6a, 0x9c, 0x76, 0x21, 0xa3, 0x15, 0x8d, 0x21, 0x04, 0xd6, - 0xe5, 0x71, 0x7b, 0x7e, 0x1e, 0x9f, 0x65, 0xb1, 0x4b, 0x55, 0x45, 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0xfd, 0xee, 0x2f, 0x81, 0x44, + 0x8e, 0xc9, 0xe5, 0xae, 0xd1, 0x43, 0xef, 0x91, 0x10, 0xf7, 0xf4, 0x68, 0x1e, 0x15, 0xf6, 0x7b, + 0x7f, 0x05, 0xc4, 0x55, 0x6d, 0x49, 0x24, 0xe0, 0x37, 0xdd, 0x09, 0x5e, 0xb5, 0x04, 0xf6, 0x63, + 0x65, 0xeb, 0xc1, 0xdb, 0x3f, 0xaa, 0xa8, 0x79, 0xfc, 0xda, 0x92, 0x12, 0x67, 0x2f, 0xd3, 0x59, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c index a80671222e..6ef7eebe01 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c @@ -35,1222 +35,1221 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 39936 -// COMPRESSED SIZE (bytes): 19390 +// COMPRESSED SIZE (bytes): 19376 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data[] = { - 0xed, 0xfb, 0x43, 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{ 39936, // uncompressed data size (bytes) - 19390, // compressed data size (bytes) + 19376, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1313,1222 +1312,1221 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_storage_pvt // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 39936 -// COMPRESSED SIZE (bytes): 19386 +// COMPRESSED SIZE (bytes): 19373 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data[] = { - 0xed, 0xfb, 0x43, 0x90, 0x28, 0x4d, 0xd7, 0x00, 0xea, 0xb6, 0x6d, 0xdb, 0xb6, 0xed, 0xdd, 0xb6, - 0x6d, 0xdb, 0xdc, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xed, 0xb6, 0xed, 0xfb, 0xfd, 0x37, - 0xe2, 0x4e, 0xde, 0xd9, 0x9d, 0x9c, 0xc1, 0x89, 0x7e, 0x26, 0x89, 0x88, 0xca, 0xc8, 0xaa, 0x8a, - 0xaa, 0x5a, 0x59, 0xb1, 0x52, 0x02, 0x00, 0x61, 0x26, 0x1d, 0x20, 0x56, 0x1e, 0x03, 0xa0, 0xfb, - 0x28, 0xef, 0xad, 0xf9, 0x1b, 0x50, 0x02, 0x00, 0xf1, 0xff, 0x3a, 0xd4, 0x31, 0x00, 0xfe, 0xbf, - 0xcd, 0x70, 0x00, 0x00, 0xc0, 0xef, 0x24, 0x00, 0x1f, 0x7a, 0x00, 0x80, 0x57, 0xa0, 0x57, 0x80, - 0x37, 0xa0, 0x68, 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0x05, 0xbc, 0xe0, 0xc4, 0x4c, 0x9f, 0xf8, 0x7b, 0x30, 0x24, 0xb5, 0x8f, + 0xbe, 0x86, 0x98, 0x10, 0x59, 0x03, 0x76, 0xe9, 0xc5, 0xde, 0x18, 0xf3, 0x65, 0x09, 0x5b, 0x32, + 0xc3, 0x01, 0xda, 0x5d, 0xfa, 0xd9, 0x8a, 0x85, 0xf9, 0x8a, 0x26, 0x76, 0x41, 0x53, 0x02, 0x24, + 0x76, 0x5b, 0x37, 0x79, 0xe4, 0xcf, 0x9b, 0xe7, 0x70, 0xe1, 0x80, 0x0e, 0xf1, 0x6b, 0x6e, 0xeb, + 0xb6, 0xcf, 0x4c, 0x33, 0x2f, 0x94, 0xe7, 0x69, 0xed, 0xfd, 0x38, 0xf1, 0xfd, 0x99, 0xf0, 0xae, + 0xc7, 0x76, 0x5c, 0x60, 0x43, 0xa3, 0x5d, 0xd9, 0x82, 0xf0, 0x97, 0xbb, 0x71, 0xeb, 0x45, 0xd2, + 0xbc, 0x4b, 0x84, 0x85, 0x13, 0x89, 0x3d, 0xa2, 0x34, 0xff, 0xce, 0x6e, 0x81, 0x87, 0x31, 0x8f, + 0x50, 0xef, 0x41, 0x2f, 0x53, 0xb8, 0x75, 0x80, 0xdb, 0x3d, 0x36, 0x13, 0xb7, 0x9f, 0x9d, 0xc3, + 0x40, 0xbd, 0x11, 0xe2, 0x1a, 0xf5, 0x19, 0x0b, 0x6e, 0x0a, 0x4f, 0x43, 0x13, 0xc2, 0x95, 0x57, + 0x58, 0xdd, 0x09, 0xf1, 0xe4, 0x42, 0xe6, 0x73, 0xc7, 0xf6, 0x66, 0xaa, 0x3b, 0x0b, 0x30, 0xcd, + 0xf3, 0xde, 0xa8, 0xfc, 0xff, 0xb7, 0xb5, 0x01, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, + 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, - 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0x7f, 0xc0, - 0xff, 0x07, 0x15, 0x28, 0x0a, 0x19, 0x00, 0x9c, 0x00, 0x00, + 0xff, 0x07, 0xfc, 0x7f, 0x00, 0x06, 0xa7, 0xca, 0xc6, 0x00, 0x9c, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2539,7 +2537,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 39936, // uncompressed data size (bytes) - 19386, // compressed data size (bytes) + 19373, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2595,30 +2593,30 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_data[] = { - 0x2c, 0xfb, 0x4d, 0x26, 0x9e, 0xb4, 0x3c, 0x9f, 0xfa, 0x9e, 0x62, 0xa3, 0x02, 0x40, 0x61, 0xda, - 0x5d, 0x68, 0xdf, 0xba, 0xf5, 0x2c, 0xa5, 0x7a, 0xf1, 0x52, 0x12, 0x84, 0x95, 0xf7, 0xa2, 0x1d, - 0x7f, 0x82, 0x42, 0x0a, 0xfd, 0xda, 0xd7, 0x0d, 0xbf, 0xba, 0x99, 0xf8, 0x7d, 0x2b, 0x57, 0x47, - 0x6b, 0xa0, 0x82, 0x6e, 0x26, 0x16, 0x8d, 0x85, 0xe9, 0x31, 0x6a, 0x81, 0x22, 0x5e, 0x80, 0x10, - 0x78, 0xe1, 0xce, 0xea, 0x6b, 0xfd, 0x41, 0x74, 0xbf, 0xdf, 0x20, 0xf5, 0x22, 0x57, 0xf6, 0x04, - 0xa1, 0xcc, 0x02, 0x6a, 0x0f, 0xad, 0xac, 0xb5, 0x57, 0x21, 0xce, 0x8c, 0x2c, 0x41, 0xc8, 0x40, - 0xdf, 0x24, 0xb9, 0x3c, 0x52, 0x26, 0x4d, 0xfe, 0xb6, 0x76, 0xce, 0x11, 0xc8, 0x94, 0x98, 0x84, - 0x56, 0xfa, 0xfc, 0x7c, 0x5e, 0xf4, 0xff, 0x50, 0x71, 0xb5, 0x3d, 0xa0, 0xef, 0xc9, 0xad, 0xe3, - 0x51, 0x24, 0xc9, 0xe4, 0x8d, 0x4f, 0x33, 0xef, 0xd2, 0x98, 0x6e, 0x70, 0xa1, 0xd3, 0x90, 0x6a, - 0x36, 0xc9, 0xab, 0xb4, 0x02, 0xc6, 0xe5, 0xb6, 0xc3, 0x7d, 0x0a, 0x57, 0x47, 0xcd, 0x98, 0x78, - 0xb3, 0xa5, 0x0d, 0xeb, 0x34, 0x6b, 0x6b, 0xa6, 0xc0, 0xd8, 0xb6, 0x30, 0xb5, 0x87, 0x2c, 0x67, - 0x48, 0xec, 0xe6, 0xd3, 0xff, 0x07, 0x39, 0x67, 0x6f, 0x24, 0x3a, 0xab, 0x5e, 0x45, 0x21, 0x26, - 0x3f, 0x9f, 0xef, 0xc6, 0x6a, 0xa0, 0x04, 0xa0, 0x93, 0xef, 0xcc, 0x7c, 0x04, 0x79, 0xc0, 0x1e, - 0x14, 0x27, 0x01, 0xd6, 0x5b, 0xab, 0x31, 0x55, 0x2f, 0x7a, 0xa7, 0x31, 0xe5, 0x1f, 0xab, 0x9b, - 0x6f, 0xd3, 0x0f, 0x8e, 0x2e, 0x7b, 0x7f, 0x79, 0x4f, 0x30, 0x76, 0x51, 0x2c, 0x5a, 0x38, 0xc9, - 0xb1, 0x03, 0xd9, 0xde, 0x0c, 0x31, 0xf1, 0x50, 0x5d, 0xbb, 0x21, 0xd4, 0xed, 0x07, 0x49, 0x26, - 0x59, 0x63, 0xd4, 0x9d, 0x88, 0x31, 0xce, 0xfb, 0x93, 0x4a, 0x0b, 0x5a, 0xda, 0x01, 0x47, 0x6e, - 0x36, 0x31, 0x6f, 0xf9, 0x79, 0xdf, 0xb2, 0xbe, 0xc5, 0xf9, 0x6b, 0xd4, 0xe5, 0x91, 0x14, 0x92, - 0x2f, 0xda, 0x1e, 0xed, 0x26, 0x01, 0x79, 0xad, 0xaa, 0x54, 0x4c, 0x07, 0x99, 0x6f, 0x33, 0xc1, - 0x2f, 0xf7, 0xef, 0x79, 0x32, 0xa6, 0x63, 0xf2, 0x87, 0xbb, 0x45, 0xd1, 0x39, 0x25, 0x62, 0x52, - 0x71, 0x5e, 0x3c, 0xff, 0xdf, 0x6b, 0x62, 0xa9, 0x7f, 0x0d, 0x5a, 0x41, 0x7d, 0x22, 0x94, 0x5c, - 0x84, 0x6b, 0xee, 0xa3, 0x5e, 0x7a, 0x6e, 0x93, 0x43, 0xbd, 0xee, 0x18, 0xda, 0x79, 0xf6, 0x53, - 0x46, 0x02, 0x3b, 0x28, 0xf1, 0x0a, 0x36, 0xe4, 0xa3, 0xf6, 0x62, 0x37, 0x30, 0x88, 0xa1, 0x58, - 0xe1, 0xa0, 0xc9, 0x54, 0xd3, 0xaf, 0x52, 0x85, 0x0d, 0xe9, 0xf6, 0xc5, 0xca, 0x5e, 0x7f, 0xbb, + 0x59, 0x2b, 0x23, 0xf8, 0x60, 0x39, 0x74, 0x66, 0x20, 0xe7, 0x07, 0x3e, 0x77, 0xb8, 0x0f, 0xd9, + 0x29, 0x60, 0x85, 0xca, 0xdd, 0xf6, 0xd4, 0x43, 0x03, 0x95, 0x7a, 0xf4, 0x9b, 0xac, 0xf0, 0x5d, + 0x8f, 0x84, 0x35, 0xe1, 0xd9, 0xef, 0xdc, 0xae, 0x68, 0xb7, 0x91, 0x8a, 0x52, 0x11, 0x8c, 0xea, + 0xdf, 0xf3, 0xa9, 0x9f, 0x14, 0x98, 0x5a, 0xf4, 0x1e, 0x16, 0x34, 0xb1, 0x31, 0xca, 0x92, 0x51, + 0x19, 0xaa, 0x26, 0xbe, 0x0d, 0x43, 0x9b, 0x62, 0xc7, 0xae, 0x3a, 0x16, 0x0a, 0x3d, 0x1a, 0x92, + 0x01, 0x55, 0x5f, 0x37, 0x95, 0x6a, 0x14, 0x90, 0x21, 0xd9, 0xe4, 0x42, 0x45, 0x67, 0xf2, 0xea, + 0xe4, 0x92, 0x87, 0x5d, 0xb1, 0x4f, 0x72, 0x69, 0x2c, 0x48, 0x42, 0x09, 0xc8, 0x33, 0xeb, 0xaa, + 0x96, 0xe6, 0xa2, 0xb5, 0x85, 0x61, 0xc0, 0x6e, 0xf6, 0xbf, 0xb4, 0xb2, 0xc0, 0xe7, 0x51, 0x97, + 0xe0, 0x00, 0x21, 0x05, 0x5d, 0xb0, 0xbd, 0x0b, 0x61, 0x7d, 0xc0, 0x68, 0x31, 0x32, 0xb9, 0x6c, + 0x0d, 0x0e, 0x1f, 0x2d, 0x0d, 0x49, 0x1c, 0xbc, 0x24, 0x55, 0xce, 0x6c, 0x97, 0x59, 0x9b, 0x32, + 0x94, 0xc4, 0xd1, 0x39, 0x5c, 0x08, 0x46, 0x2c, 0xfc, 0xb3, 0xda, 0xb9, 0x33, 0xb1, 0x3a, 0x0c, + 0xc6, 0x96, 0x80, 0x30, 0x80, 0xec, 0xbf, 0x98, 0x98, 0xec, 0x8f, 0xf0, 0xa5, 0xc6, 0xb5, 0xd0, + 0x8f, 0xa9, 0x04, 0x7a, 0x71, 0x26, 0xc5, 0x41, 0xd6, 0xa2, 0x44, 0x1b, 0xa9, 0x1d, 0x1f, 0x80, + 0x44, 0xe8, 0x37, 0xcd, 0x80, 0x78, 0xca, 0xf0, 0x3f, 0x72, 0x71, 0x7b, 0x98, 0x9d, 0xed, 0xe6, + 0xae, 0xca, 0x58, 0x7e, 0xaf, 0x36, 0xe0, 0x08, 0xa3, 0x9e, 0xa7, 0xe7, 0xea, 0x96, 0xd8, 0x86, + 0x96, 0xf9, 0xa7, 0x0c, 0x31, 0x31, 0xe1, 0xa0, 0x18, 0x03, 0x5f, 0xf9, 0xce, 0x6d, 0x0f, 0x19, + 0xf4, 0xd2, 0x0c, 0xa1, 0x1c, 0xfa, 0xb5, 0xe6, 0x1a, 0x9e, 0xfe, 0xc7, 0x9a, 0x93, 0x56, 0x94, + 0xda, 0x03, 0xbb, 0x8e, 0xbf, 0x87, 0x9a, 0x0f, 0xd4, 0x62, 0xb8, 0x4c, 0x57, 0x47, 0x9d, 0x6b, + 0x74, 0xed, 0x14, 0x0f, 0xb7, 0x62, 0x31, 0x05, 0x4b, 0x79, 0x68, 0x0f, 0x50, 0x9d, 0xb4, 0xc6, + 0x8f, 0xbe, 0x25, 0x97, 0xe0, 0x9f, 0x6e, 0x92, 0x03, 0x94, 0xde, 0x5c, 0x3b, 0x82, 0x74, 0x8a, + 0xb6, 0xda, 0xa1, 0x53, 0x44, 0x40, 0xcf, 0x1c, 0x9e, 0xe3, 0x58, 0x74, 0xea, 0x6d, 0x33, 0x2d, + 0xc4, 0x78, 0x73, 0xb4, 0xdc, 0x90, 0xeb, 0x31, 0x73, 0x71, 0xe9, 0x97, 0xc1, 0x13, 0x8b, 0x60, + 0x83, 0x9e, 0x61, 0xb7, 0xc5, 0x88, 0xf8, 0xac, 0x9c, 0x68, 0xbb, 0xf0, 0x11, 0xeb, 0xde, 0xc4, + 0x67, 0x01, 0xc1, 0x1a, 0x13, 0x48, 0xf8, 0x71, 0xa4, 0x92, 0xdf, 0x1d, 0x50, 0x76, 0xab, 0x07, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2651,30 +2649,30 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_data[] = { - 0x17, 0xca, 0x6a, 0xeb, 0x61, 0xb8, 0x00, 0x4f, 0x72, 0xb3, 0x5e, 0xc0, 0xc8, 0x61, 0xad, 0xbd, - 0x62, 0x73, 0x4a, 0x86, 0xa7, 0x9c, 0x60, 0xaf, 0x36, 0x60, 0x86, 0xb4, 0x47, 0x71, 0x30, 0x95, - 0xd6, 0xa2, 0xee, 0xde, 0x0e, 0x8d, 0x0a, 0xea, 0x42, 0xf3, 0xb5, 0xfa, 0xd5, 0xef, 0x3d, 0x0e, - 0xed, 0xc0, 0x18, 0x8e, 0xf3, 0xfd, 0x1c, 0xa3, 0x2c, 0x16, 0x1d, 0xe9, 0xcd, 0x48, 0x56, 0xc6, - 0x73, 0x78, 0x84, 0xb8, 0x55, 0x57, 0x93, 0xa7, 0xf6, 0x73, 0x72, 0x22, 0xb4, 0x18, 0xe1, 0x2e, - 0x83, 0x58, 0xdd, 0x08, 0x87, 0x83, 0x40, 0xe8, 0x67, 0x2b, 0xb3, 0x6c, 0x46, 0x47, 0xf1, 0xa8, - 0x3b, 0xa5, 0xd8, 0x5d, 0xeb, 0x0b, 0x50, 0xfb, 0xde, 0x7c, 0x25, 0xcb, 0xb1, 0x8c, 0x2b, 0xa3, - 0x61, 0x94, 0xee, 0xd4, 0x0e, 0xc5, 0x73, 0xda, 0xa4, 0xa6, 0x71, 0xf1, 0xd1, 0x5c, 0x52, 0x04, - 0xdc, 0x1a, 0x37, 0xf6, 0x25, 0xd6, 0xd1, 0x2d, 0x0b, 0x4c, 0xaa, 0x77, 0x36, 0xae, 0x81, 0x5b, - 0xa3, 0x61, 0x94, 0x4f, 0x7d, 0x6c, 0xe8, 0x2d, 0x7e, 0x5c, 0x02, 0xa3, 0x70, 0x51, 0x5b, 0xc1, - 0xda, 0xc2, 0xdb, 0xeb, 0xb6, 0xe7, 0x16, 0x5c, 0xf7, 0x6e, 0x0d, 0x03, 0x50, 0xb4, 0x70, 0xb6, - 0x57, 0xa9, 0xd0, 0xfe, 0x29, 0x7b, 0x10, 0x77, 0x60, 0xf7, 0x9b, 0x82, 0xfb, 0x70, 0x2f, 0x7d, - 0x10, 0x97, 0x22, 0x2a, 0x96, 0x98, 0xd3, 0xba, 0x0a, 0x11, 0x0e, 0xb7, 0xd2, 0x85, 0xe0, 0xb9, - 0x0d, 0x79, 0x10, 0xcc, 0x6e, 0x73, 0x6e, 0x1f, 0xd4, 0xa1, 0x0a, 0xf8, 0x1e, 0x32, 0x89, 0xa9, - 0x36, 0xa0, 0xf7, 0x26, 0x80, 0x76, 0x98, 0x2f, 0xa1, 0xda, 0xe7, 0xd8, 0xc8, 0x8a, 0x8a, 0x46, - 0x14, 0x67, 0x23, 0xdc, 0x36, 0x51, 0x6c, 0xad, 0x0d, 0x03, 0xc1, 0x64, 0x57, 0xce, 0x9d, 0xe1, - 0x1b, 0x68, 0x0d, 0x55, 0x00, 0xd9, 0x96, 0x3f, 0x08, 0x72, 0xb6, 0x56, 0xbf, 0xb4, 0xeb, 0x61, - 0xc9, 0x4c, 0xbe, 0x57, 0x98, 0x61, 0x27, 0xd4, 0xf2, 0xca, 0x00, 0x8e, 0x78, 0xa7, 0xf5, 0x07, - 0x9d, 0x64, 0xa6, 0xc3, 0xe1, 0xf3, 0x2b, 0xc4, 0x6f, 0xd8, 0x53, 0xbc, 0xb4, 0x4d, 0xbb, 0xc8, - 0xfc, 0xa3, 0xf4, 0xb7, 0x48, 0x67, 0xcb, 0x74, 0xba, 0xfd, 0x88, 0x2e, 0x78, 0x5c, 0xac, 0x2b, - 0x1c, 0xa6, 0x65, 0x81, 0xe2, 0xae, 0xff, 0x2d, 0xb4, 0x24, 0x53, 0x28, 0xb3, 0xae, 0x7e, 0x79, - 0xac, 0xfc, 0x17, 0x11, 0x8a, 0xc8, 0x9b, 0x97, 0x94, 0x6f, 0x70, 0xae, 0xd7, 0xea, 0x41, 0xcf, - 0xed, 0x29, 0x85, 0xf2, 0xe3, 0x37, 0x9f, 0x20, 0x91, 0x2d, 0xed, 0x79, 0xea, 0x7c, 0x28, 0x32, - 0x13, 0x99, 0x5b, 0x77, 0x3b, 0x8e, 0xbc, 0xc8, 0x8a, 0x0b, 0x32, 0xe3, 0x0e, 0x6f, 0x0d, 0x06, + 0x4d, 0xbb, 0x3a, 0xbd, 0x9c, 0xea, 0xcc, 0xc1, 0xa4, 0x42, 0x06, 0xb7, 0x73, 0x80, 0xb5, 0x17, + 0x4e, 0x2d, 0x9a, 0x93, 0x03, 0x0b, 0x7f, 0xf4, 0xd6, 0x78, 0x74, 0x3a, 0x82, 0x64, 0x51, 0xe8, + 0x69, 0x81, 0xdc, 0x28, 0x16, 0xc1, 0x35, 0x2e, 0xed, 0x1a, 0xf9, 0xa4, 0xe9, 0x50, 0xe6, 0x65, + 0x0f, 0x60, 0x71, 0x75, 0xd7, 0x89, 0xee, 0x96, 0x3a, 0x28, 0xfe, 0x4e, 0xdd, 0x57, 0x25, 0xf6, + 0xb8, 0xff, 0xd0, 0x01, 0xdb, 0x2d, 0xab, 0x48, 0xa8, 0x15, 0x66, 0x4d, 0x28, 0xb1, 0xbd, 0xb9, + 0xf3, 0x03, 0x6c, 0x9c, 0x47, 0x1b, 0x89, 0x81, 0x53, 0x53, 0xdb, 0x79, 0x72, 0x25, 0xaa, 0x28, + 0x37, 0xfb, 0x6f, 0xa8, 0xec, 0xe8, 0xce, 0x0e, 0xda, 0xd8, 0x58, 0xa7, 0xf9, 0x33, 0xe5, 0x68, + 0x26, 0x96, 0x63, 0x3c, 0xcb, 0x30, 0x46, 0x03, 0x38, 0xfa, 0xb0, 0x13, 0x4c, 0x43, 0x31, 0x87, + 0x50, 0xe8, 0x39, 0x8a, 0xe1, 0x88, 0x4c, 0x50, 0x34, 0xbd, 0x55, 0xf2, 0x21, 0xd0, 0x24, 0xf6, + 0xd6, 0xd5, 0x1d, 0xe7, 0x70, 0x82, 0x8e, 0x47, 0x15, 0xbe, 0x43, 0x06, 0xff, 0xd8, 0x61, 0x1e, + 0xf4, 0x84, 0xbb, 0x12, 0x9e, 0x96, 0xad, 0xd1, 0xc6, 0x18, 0xa6, 0x33, 0xea, 0x4f, 0x5d, 0xed, + 0x4d, 0xc7, 0x4e, 0xbf, 0x84, 0xb6, 0x31, 0xa6, 0xf5, 0xef, 0xaf, 0xfb, 0x41, 0xaa, 0x8b, 0xaf, + 0xa9, 0xed, 0x62, 0xc6, 0xd7, 0x96, 0xb9, 0x2f, 0x6b, 0x67, 0x16, 0xde, 0x2e, 0x09, 0x39, 0x0d, + 0xf4, 0x14, 0x23, 0xa5, 0xa9, 0xd7, 0xd3, 0x6b, 0x95, 0x65, 0xe6, 0x48, 0x49, 0x5e, 0xd8, 0x47, + 0x7b, 0x93, 0x2c, 0x28, 0x1d, 0x49, 0xba, 0x7c, 0x91, 0xe7, 0x75, 0xd3, 0x46, 0x2b, 0xb0, 0xb8, + 0x4e, 0x20, 0x9d, 0x02, 0xd0, 0x2d, 0x5c, 0xb1, 0xd4, 0xcb, 0xfd, 0xf1, 0xce, 0x16, 0x81, 0x32, + 0xda, 0x6f, 0x4f, 0xc4, 0xa1, 0xb8, 0x5b, 0xa7, 0xc6, 0x73, 0xa9, 0x9a, 0x4d, 0x8e, 0xc5, 0x93, + 0xcc, 0x38, 0xa2, 0x23, 0x19, 0xa5, 0xe1, 0x2b, 0x21, 0xe6, 0x1a, 0xcb, 0x6e, 0xf8, 0x1d, 0xc5, + 0x5b, 0x7e, 0x6a, 0xb6, 0x2c, 0x8a, 0xfd, 0xbe, 0x0c, 0x71, 0x03, 0x4e, 0x20, 0x2b, 0x59, 0x91, + 0x27, 0x94, 0xae, 0xa6, 0x0f, 0xab, 0x92, 0x3c, 0xa9, 0xd9, 0x2c, 0xcc, 0xd1, 0x64, 0xfd, 0x82, + 0x09, 0xff, 0xe4, 0x1b, 0xd3, 0xf6, 0x03, 0xc1, 0x30, 0x1a, 0x67, 0x51, 0xd6, 0xda, 0x5a, 0xa8, + 0xdd, 0xae, 0xb2, 0xe7, 0x67, 0x9b, 0x91, 0x7a, 0x55, 0xeb, 0x45, 0x88, 0xbd, 0x0a, 0x96, 0xd4, + 0x63, 0xe3, 0x24, 0xa9, 0xe8, 0x8a, 0xd0, 0x93, 0xf5, 0x7c, 0x30, 0xd8, 0x0e, 0xd4, 0x52, 0x56, + 0x39, 0x1e, 0x7e, 0x0b, 0xa9, 0x89, 0x04, 0x70, 0x83, 0xab, 0x3a, 0x48, 0xb2, 0x7f, 0x3b, 0xb6, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c index 67be5d69b7..241549e883 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c @@ -35,1257 +35,1252 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 40192 -// COMPRESSED SIZE (bytes): 19944 +// COMPRESSED SIZE (bytes): 19870 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data[] = { - 0xed, 0xdc, 0x43, 0x74, 0x28, 0x4c, 0xb0, 0x20, 0xe0, 0xd8, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xbe, 0xb1, 0x6d, 0xe3, 0xc6, 0x76, 0x72, 0x63, 0xdb, 0xd6, 0xcc, 0xfa, 0x9f, - 0xc5, 0x2c, 0x67, 0xce, 0x79, 0xf9, 0x76, 0xbd, 0xeb, 0xde, 0x54, 0xd7, 0xa9, 0xae, 0x6a, 0x00, - 0x80, 0xff, 0xd9, 0xf4, 0x9a, 0xee, 0x28, 0x41, 0x7e, 0x1e, 0x43, 0x3d, 0x22, 0xa6, 0x55, 0x72, - 0x7e, 0x74, 0x7d, 0x71, 0x1b, 0xd3, 0xca, 0x75, 0xbb, 0xb8, 0xcf, 0x1a, 0x0e, 0x08, 0x2f, 0x4a, - 0xc7, 0xfe, 0x15, 0x71, 0x13, 0xe6, 0x8e, 0xd7, 0xfa, 0x3a, 0xc7, 0x84, 0xda, 0x45, 0xa8, 0xc4, - 0x49, 0xdd, 0x76, 0x04, 0xfc, 0x79, 0x74, 0xc0, 0xeb, 0xf2, 0xa3, 0xbe, 0x34, 0x1a, 0x14, 0x7f, - 0xcd, 0x7e, 0xeb, 0x3a, 0xee, 0x4a, 0x1d, 0x8d, 0xa5, 0x0e, 0xed, 0x80, 0xac, 0xf6, 0x49, 0xb3, - 0xb9, 0xa2, 0xd8, 0x68, 0xdb, 0x10, 0xb6, 0xc4, 0x4e, 0x66, 0x09, 0x84, 0xac, 0x0f, 0xe3, 0x6b, - 0xa8, 0xc1, 0xf6, 0x5a, 0x2f, 0x2b, 0x52, 0x3c, 0x1f, 0xae, 0x3e, 0x3e, 0xb8, 0xd4, 0x11, 0xe6, - 0x4e, 0x42, 0xd7, 0xb7, 0x1e, 0xe9, 0x3a, 0x86, 0xd4, 0xbc, 0x15, 0x04, 0xe3, 0x94, 0x19, 0x8c, - 0x9a, 0x5d, 0xf4, 0x93, 0xdb, 0x27, 0x81, 0x17, 0x75, 0x83, 0xa2, 0x80, 0x31, 0x9c, 0xe1, 0xd0, - 0xc4, 0xa8, 0xf7, 0x5f, 0xe4, 0x58, 0xfe, 0x1b, 0x16, 0x4c, 0xc4, 0x6e, 0x7d, 0xbe, 0x86, 0xa8, - 0xd9, 0x3c, 0x2e, 0xb1, 0xdf, 0x52, 0x7a, 0xff, 0x88, 0x54, 0x6c, 0x31, 0x2e, 0x3f, 0x77, 0x0f, - 0xa6, 0x5f, 0xdc, 0x85, 0x5c, 0x9d, 0xf8, 0x3c, 0xd3, 0x7b, 0x9d, 0xc6, 0x0f, 0xf6, 0x21, 0x41, - 0x58, 0x49, 0x43, 0x99, 0x38, 0x50, 0xc3, 0x10, 0x30, 0xff, 0x77, 0x0d, 0x58, 0xc7, 0xa6, 0xf0, - 0xd4, 0x0d, 0x23, 0x52, 0xdc, 0x04, 0xce, 0xc5, 0x9f, 0x81, 0xfb, 0x9d, 0xd6, 0x7c, 0x74, 0xde, - 0x76, 0xbf, 0xb3, 0x70, 0x79, 0x4d, 0x0f, 0x6e, 0x1d, 0x55, 0x8d, 0x08, 0x92, 0xc0, 0x29, 0xdb, - 0x2f, 0x13, 0x10, 0xbb, 0x65, 0x55, 0x50, 0x65, 0x34, 0xa6, 0x61, 0xd1, 0x6b, 0xe5, 0xcd, 0x26, - 0xe5, 0x3a, 0x94, 0x19, 0x02, 0x86, 0x7a, 0x6c, 0xe5, 0xaf, 0xeb, 0xf1, 0x51, 0x73, 0x00, 0xa7, - 0x73, 0xad, 0x2f, 0x55, 0xe4, 0x77, 0x99, 0xe9, 0x18, 0x84, 0x65, 0x76, 0x32, 0x3a, 0x38, 0x95, - 0x1d, 0x41, 0xbd, 0xa0, 0x6e, 0x0f, 0xa9, 0xe0, 0x09, 0x0b, 0x13, 0x07, 0x58, 0xa9, 0x5b, 0x74, - 0xd6, 0x2d, 0x8b, 0xb6, 0x64, 0x09, 0xc5, 0x3f, 0xb3, 0x6a, 0x82, 0x61, 0xc8, 0x27, 0xe2, 0xc7, - 0x8f, 0x4f, 0x04, 0x5b, 0xd5, 0xbc, 0x4f, 0x0f, 0x9f, 0x72, 0x8e, 0xb5, 0x8d, 0x72, 0x62, 0x53, - 0x6b, 0x7c, 0x94, 0x80, 0x9d, 0xd0, 0xbf, 0xf3, 0xff, 0xde, 0x16, 0xf1, 0xfa, 0x76, 0xff, 0x52, - 0x06, 0x7d, 0x09, 0x95, 0xee, 0xbe, 0xcd, 0xd9, 0x84, 0xe2, 0x52, 0xfc, 0x73, 0x24, 0x78, 0xb9, - 0x97, 0x2e, 0xbe, 0x05, 0x08, 0xc5, 0x22, 0xce, 0xd0, 0xd4, 0x38, 0xf9, 0xd4, 0xe2, 0xdd, 0xa1, - 0x7b, 0x0e, 0xcf, 0x33, 0xd7, 0x1a, 0xaf, 0xd4, 0x3e, 0x96, 0xe4, 0x50, 0x0f, 0x5b, 0x00, 0xaa, - 0x91, 0x97, 0x7e, 0x49, 0x67, 0xa9, 0xe7, 0x6d, 0x05, 0xdd, 0xac, 0x37, 0x1d, 0x51, 0x3c, 0x7e, - 0xbf, 0x35, 0x13, 0x4e, 0xab, 0xdb, 0x5c, 0xdc, 0xf4, 0x70, 0x0b, 0x6b, 0xe3, 0x6d, 0xa3, 0x46, - 0x38, 0xab, 0xc4, 0x35, 0x6a, 0xd9, 0x46, 0x62, 0xc4, 0x8f, 0xfc, 0xb6, 0xe5, 0x3a, 0xad, 0xad, - 0x29, 0x57, 0xe0, 0x8b, 0x6e, 0xa9, 0x67, 0x60, 0x43, 0x2a, 0x20, 0xcf, 0x9d, 0xc4, 0x8d, 0xc5, - 0xa4, 0x3b, 0x5f, 0x01, 0x95, 0xac, 0x88, 0x0e, 0x92, 0x75, 0x0c, 0x8c, 0x2e, 0xe9, 0x7b, 0x8d, - 0xd8, 0xdc, 0x55, 0xf2, 0x97, 0xce, 0xc8, 0xb9, 0x2a, 0x12, 0xea, 0xd9, 0x71, 0xe9, 0x1c, 0x79, - 0xf6, 0xd4, 0x1e, 0xea, 0x8f, 0xdf, 0x5b, 0xe2, 0xf3, 0x96, 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kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1348,1257 +1343,1252 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_storage_pvt // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 40192 -// COMPRESSED SIZE (bytes): 19945 +// COMPRESSED SIZE (bytes): 19871 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data[] = { - 0xed, 0xdc, 0x43, 0x90, 0x20, 0x5d, 0xd4, 0x26, 0xe0, 0xb2, 0x6d, 0xdb, 0xe8, 0xb2, 0x6d, 0xab, - 0xcb, 0xb6, 0x6d, 0xdb, 0xec, 0xb2, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x31, 0xff, 0xfa, 0x9b, - 0xc5, 0x2c, 0x67, 0x22, 0xa6, 0x9e, 0x5d, 0xee, 0xf2, 0x46, 0x64, 0xbc, 0x79, 0x6e, 0xde, 0x73, - 0x12, 0x00, 0xe0, 0xff, 0x6f, 0x53, 0x01, 0x30, 0x48, 0x6c, 0x2e, 0x69, 0x14, 0xbc, 0x82, 0xe4, - 0xf9, 0xab, 0xae, 0xd6, 0xe6, 0xf8, 0xab, 0x7c, 0x13, 0x36, 0x5d, 0xfc, 0xfa, 0x56, 0xfe, 0x3c, - 0x05, 0x45, 0xed, 0xca, 0x88, 0x1d, 0x0f, 0x7a, 0x15, 0x89, 0x84, 0x87, 0xac, 0xc8, 0x73, 0xfa, - 0xd6, 0xdf, 0x1a, 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kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2665,54 +2655,54 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_data[] = { - 0xed, 0xcb, 0x3c, 0x4a, 0xe0, 0xdd, 0x80, 0xd4, 0xdf, 0xed, 0xd2, 0xed, 0x51, 0x63, 0x52, 0xf4, - 0x44, 0x88, 0x3b, 0xa1, 0x6d, 0xc5, 0x41, 0x16, 0xea, 0xb0, 0xea, 0xf8, 0xe4, 0xba, 0x71, 0x12, - 0xa3, 0x30, 0xe4, 0x8a, 0x4d, 0x49, 0xc3, 0x9c, 0xd6, 0xf2, 0x66, 0x45, 0xb0, 0x8a, 0xd9, 0xe1, - 0xd4, 0x79, 0x43, 0xf2, 0xef, 0x73, 0x96, 0xbb, 0xb6, 0xa9, 0x7b, 0xff, 0xdc, 0xb1, 0x6f, 0x09, - 0xfb, 0xac, 0x4a, 0xae, 0xa3, 0xbe, 0x93, 0x59, 0x3f, 0x41, 0xd0, 0x39, 0x74, 0xef, 0x13, 0x8e, - 0x53, 0x9f, 0xe9, 0x65, 0x4b, 0x89, 0x1e, 0xa5, 0xfe, 0x34, 0x76, 0x7d, 0xe5, 0xa4, 0x27, 0x5a, - 0xd6, 0x23, 0x4a, 0xfe, 0x48, 0xfd, 0x1e, 0x29, 0x9e, 0x0b, 0x46, 0xba, 0xdb, 0xa0, 0x77, 0x55, - 0x47, 0x9c, 0xb3, 0x7b, 0x69, 0xfc, 0xce, 0x48, 0xd6, 0x20, 0x85, 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0x16, 0x7a, 0xb5, 0xc5, 0x3c, 0xef, 0xda, 0x63, 0xb7, 0xdc, 0x0f, 0x2b, 0x35, 0x0c, 0x37, 0x4a, + 0xcb, 0xdb, 0xdf, 0x15, 0x63, 0x18, 0x05, 0x03, 0x0a, 0x00, 0x21, 0x51, 0xf1, 0xff, 0x00, 0x03, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2782,7 +2772,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 421, // compressed data size (bytes) + 418, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c index 02fea66523..f5dd06b909 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c @@ -34,1141 +34,1205 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 37888 -// COMPRESSED SIZE (bytes): 18073 +// DATA SIZE (bytes): 39168 +// COMPRESSED SIZE (bytes): 19091 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data[] = { - 0xed, 0xdb, 0x43, 0x90, 0x28, 0x4d, 0x17, 0x30, 0xe8, 0xb6, 0x6d, 0xdb, 0xb6, 0x7d, 0xdb, 0xb6, - 0x6d, 0xdb, 0x76, 0xf7, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb7, 0x6d, 0xdb, 0xb6, 0x7b, 0xbe, 0x7f, - 0x76, 0xf3, 0x6e, 0xfe, 0xdd, 0xac, 0xfa, 0xd9, 0x9c, 0xcc, 0x8a, 0xa8, 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0x4e, 0x92, 0xd3, 0x24, + 0xe4, 0xad, 0x6e, 0x0a, 0xa8, 0x52, 0x2c, 0x08, 0xec, 0xab, 0x38, 0xe5, 0xfe, 0xff, 0xbf, 0x95, + 0x01, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, + 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, + 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, + 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, + 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xe3, 0xc7, + 0x8f, 0x1f, 0x3f, 0x7e, 0xfc, 0xf8, 0xf1, 0xff, 0x91, 0xff, 0x0b, 0x41, 0x9c, 0x68, 0x2c, 0x00, + 0x99, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1178,8 +1242,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 37888, // uncompressed data size (bytes) - 18073, // compressed data size (bytes) + 39168, // uncompressed data size (bytes) + 19091, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1201,8 +1265,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x01, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x3e, 0x28, 0xef, 0x74, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1230,1141 +1294,1205 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 37888 -// COMPRESSED SIZE (bytes): 18074 +// DATA SIZE (bytes): 39168 +// COMPRESSED SIZE (bytes): 19090 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data[] = { - 0xed, 0xdb, 0x43, 0x90, 0x28, 0x4d, 0x17, 0x30, 0xe8, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xd6, - 0x6d, 0xde, 0xee, 0xbe, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x35, 0xdf, 0x3f, - 0xbb, 0x79, 0x37, 0xff, 0x6e, 0x56, 0xfd, 0x6c, 0x32, 0xb3, 0x22, 0xaa, 0x4e, 0x55, 0x54, 0x44, - 0xd5, 0xc9, 0x13, 0x99, 0x92, 0x00, 0x08, 0xd3, 0x69, 0x00, 0x31, 0x0a, 0x68, 0x00, 0x5d, 0x87, - 0xb9, 0x6f, 0x4d, 0xdf, 0x80, 0x92, 0x00, 0x88, 0xff, 0xe7, 0x80, 0x06, 0x1a, 0xc0, 0xff, 0x3b, - 0x0c, 0x03, 0x00, 0x00, 0xfc, 0x4e, 0x04, 0xf0, 0xa6, 0x07, 0x00, 0x78, 0x05, 0x7a, 0x05, 0x78, - 0x03, 0x8a, 0x02, 0x00, 0x02, 0xe8, 0xd9, 0xde, 0xf9, 0xf9, 0xf9, 0x81, 0x0f, 0x03, 0x00, 0x04, - 0xf8, 0xc9, 0x01, 0x69, 0x38, 0x04, 0x60, 0x4e, 0x5d, 0x03, 0x6c, 0x48, 0x04, 0xa0, 0x49, 0x5d, - 0x03, 0xfa, 0x5f, 0x43, 0x9a, 0xba, 0x06, 0xfc, 0xbf, 0x06, 0xef, 0x7f, 0xe7, 0x02, 0xa4, 0xe6, - 0x00, 0x37, 0xed, 0x00, 0xf7, 0xe4, 0xe4, 0xee, 0xa4, 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0xf5, + 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, + 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, - 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, - 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, - 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xff, 0x4f, - 0xfe, 0x1f, 0x37, 0x09, 0x78, 0xe4, 0x00, 0x94, 0x00, 0x00, + 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0x7f, 0xe4, 0xff, 0x02, 0x04, 0xce, 0xfd, 0x1a, 0x00, 0x99, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2374,8 +2502,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 37888, // uncompressed data size (bytes) - 18074, // compressed data size (bytes) + 39168, // uncompressed data size (bytes) + 19090, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2397,8 +2525,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x01, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x3e, 0x28, 0xef, 0x74, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2431,7 +2559,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_data[] = { - 0xaa, 0x97, 0x88, 0x63, 0x77, 0x3e, 0x00, 0x58, 0xef, 0x0c, 0xd6, 0x33, 0x73, 0xda, 0xe5, 0x37, + 0x4f, 0x53, 0x31, 0xb6, 0xe7, 0x97, 0x4c, 0x69, 0x83, 0xa2, 0x7e, 0xa5, 0xf4, 0x5f, 0x12, 0x11, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2464,7 +2592,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_data[] = { - 0x30, 0x82, 0x5a, 0x25, 0xb5, 0x02, 0xb7, 0x76, 0x45, 0xe1, 0xd6, 0x57, 0xb8, 0x1c, 0x3a, 0x7c, + 0x7b, 0x46, 0xca, 0x62, 0x4a, 0x8a, 0x77, 0x23, 0xfc, 0x18, 0xf4, 0xb5, 0xb5, 0xed, 0xda, 0xf7, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2497,7 +2625,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_patch_loc_data[] = { - 0x00, 0x49, 0x00, 0x00, + 0x00, 0x4e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c index 3074133ea4..0097d66444 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c @@ -34,1140 +34,1199 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 37888 -// COMPRESSED SIZE (bytes): 18059 +// DATA SIZE (bytes): 38912 +// COMPRESSED SIZE (bytes): 18998 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data[] = { - 0xed, 0xdb, 0x53, 0x90, 0x26, 0xcd, 0x17, 0x38, 0xe8, 0xb7, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xcd, 0x69, 0xdb, 0x3d, 0xd3, 0xb6, 0xa6, 0xa7, 0xdd, 0xfb, - 0xfb, 0xef, 0xdd, 0x7e, 0x37, 0x1b, 0x7b, 0xb3, 0x57, 0xfd, 0xdc, 0x9c, 0xcc, 0x8a, 0xa8, 0x3a, - 0x59, 0x51, 0x51, 0x15, 0x99, 0x19, 0xa7, 0xa4, 0x00, 0x88, 0x73, 0x59, 0x80, 0x04, 0x45, 0x74, - 0x40, 0xdf, 0x51, 0xe1, 0x6b, 0xdb, 0x17, 0x90, 0x14, 0x00, 0xe9, 0xff, 0x1c, 0xd0, 0x44, 0x07, - 0xfc, 0xdf, 0xdd, 0x28, 0x00, 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defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 37888, // uncompressed data size (bytes) - 18059, // compressed data size (bytes) + 38912, // uncompressed data size (bytes) + 18998, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1200,8 +1259,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x06, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x78, 0xb1, 0xb4, 0x67, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1229,1140 +1288,1199 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 37888 -// COMPRESSED SIZE (bytes): 18059 +// DATA SIZE (bytes): 38912 +// COMPRESSED SIZE (bytes): 18997 // static BINDATA_CONST NvU8 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0x40, 0xe9, 0xcf, 0xc5, + 0x57, 0xbc, 0x5c, 0x21, 0x43, 0xbd, 0xbe, 0x7f, 0x31, 0x6a, 0x96, 0x78, 0x86, 0x08, 0x66, 0xe1, + 0x28, 0xdf, 0xde, 0x09, 0x06, 0xf1, 0x04, 0x11, 0x82, 0xe1, 0x0a, 0x96, 0x9e, 0xcb, 0xd9, 0x64, + 0x0c, 0xc2, 0xb6, 0xe9, 0xc4, 0x3d, 0x8d, 0x54, 0xf6, 0xc9, 0x67, 0xa0, 0x1a, 0x9b, 0xef, 0x41, + 0x29, 0x29, 0x03, 0xe3, 0x54, 0x1e, 0x4f, 0xb6, 0x83, 0x79, 0x26, 0xcc, 0x1a, 0x5a, 0xff, 0xdd, + 0x0f, 0xb1, 0x05, 0xd5, 0x25, 0x9a, 0x44, 0x95, 0xb6, 0xaa, 0xa8, 0x32, 0xa3, 0x10, 0x28, 0x07, + 0xc7, 0x0d, 0xf0, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, - 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xff, - 0xc9, 0xff, 0x05, 0x5a, 0x8d, 0x9f, 0x19, 0x00, 0x94, 0x00, 0x00, + 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, + 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, + 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xbf, + 0x7e, 0xfd, 0xfa, 0xf5, 0xeb, 0xd7, 0xaf, 0x5f, 0xff, 0x3f, 0xf9, 0x7f, 0x00, 0x13, 0xb3, 0x62, + 0x2c, 0x00, 0x98, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2372,8 +2490,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 37888, // uncompressed data size (bytes) - 18059, // compressed data size (bytes) + 38912, // uncompressed data size (bytes) + 18997, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2395,8 +2513,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x76, 0x07, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0xb8, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x70, 0x9e, 0x6d, 0xce, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0xf6, 0x06, 0x62, 0x5f, 0x08, 0x13, 0x4c, 0x78, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x78, 0xb1, 0xb4, 0x67, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2429,7 +2547,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_data[] = { - 0x90, 0x8b, 0x47, 0x3e, 0x0f, 0xe9, 0xcf, 0x24, 0x6d, 0x88, 0xa2, 0x9d, 0x66, 0x30, 0x83, 0x68, + 0x58, 0xc4, 0x52, 0xae, 0x04, 0x6d, 0x68, 0x57, 0xa9, 0xfb, 0x93, 0x5c, 0xee, 0x1b, 0xbb, 0x5d, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2462,7 +2580,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_data[] = { - 0x72, 0xcd, 0xc4, 0x54, 0x9c, 0xb0, 0x49, 0xf1, 0xb5, 0x5c, 0xb9, 0x11, 0xfd, 0x56, 0x92, 0xeb, + 0xa1, 0x97, 0xbb, 0x61, 0xab, 0xe9, 0x61, 0x2e, 0x0e, 0x65, 0x34, 0x5a, 0x2a, 0xdf, 0xa9, 0xde, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2495,7 +2613,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_patch_loc_data[] = { - 0x00, 0x49, 0x00, 0x00, + 0x00, 0x4d, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c index fe660dd1a9..f1547e63f4 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveConcatenatedFMC_GH100.c @@ -34,10395 +34,10395 @@ // VAR NAME: N/A // COMPRESSION: NO // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 368640 +// DATA SIZE (bytes): 389120 // COMPRESSED SIZE (bytes): N/A // static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data[] = { - 0xe5, 0xf7, 0x83, 0xc5, 0x5b, 0xbb, 0x98, 0xaa, 0x7e, 0xf2, 0xf5, 0x27, 0xea, 0x7c, 0x6c, 0x16, - 0x29, 0x8d, 0x6e, 0xc1, 0x0f, 0x6d, 0x31, 0xc4, 0x40, 0x06, 0x22, 0xeb, 0x7c, 0x06, 0x97, 0x5e, - 0x1c, 0x8b, 0xc8, 0xb5, 0x17, 0xe6, 0x10, 0xcb, 0x17, 0x6f, 0x48, 0xcd, 0x49, 0xc6, 0x5f, 0xd9, - 0x23, 0xb6, 0x24, 0x87, 0x0f, 0x61, 0x62, 0xbe, 0x71, 0x9a, 0x53, 0x69, 0xc6, 0xfd, 0xdf, 0x69, - 0xce, 0x3e, 0xf6, 0xb7, 0x74, 0x72, 0x5f, 0x19, 0x6a, 0x25, 0x1b, 0xbd, 0xd2, 0x3a, 0x95, 0x04, - 0xac, 0xad, 0xa9, 0xb6, 0x0e, 0x05, 0xaa, 0x44, 0xb7, 0xcb, 0xb3, 0x6f, 0x22, 0x90, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -10535,9 +10535,9 @@ static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_d 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0xa0, 0x02, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x70, 0x04, 0x00, 0x00, 0x30, 0x01, 0x00, - 0x00, 0xe0, 0x03, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0xa0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0xd0, 0x01, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xa0, 0x02, 0x00, 0x00, 0x90, 0x01, 0x00, 0x00, 0xd0, 0x04, 0x00, 0x00, 0x20, 0x01, 0x00, + 0x00, 0x30, 0x04, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x00, 0xf0, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x30, 0x02, 0x00, 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -10791,12294 +10791,13574 @@ static BINDATA_CONST NvU8 kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_d 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x43, 0x3c, 0xbb, 0x1b, 0xdf, 0xa8, 0x70, 0x19, 0x7c, 0x23, 0x1c, 0x5f, 0x58, 0x12, 0x6c, 0x84, - 0x6e, 0xaf, 0x79, 0xdb, 0x1e, 0x4b, 0x0d, 0x39, 0x7f, 0xfd, 0x22, 0x39, 0x60, 0x79, 0x69, 0xcc, - 0x52, 0x81, 0x8a, 0xec, 0x8b, 0x9c, 0xdf, 0xbc, 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0x0a, 0x52, 0xb5, 0x79, 0xc1, 0xad, 0x8e, 0xc8, 0xcd, 0x41, 0x95, 0x0e, 0x01, + 0xa2, 0x21, 0x27, 0x9a, 0x02, 0x9b, 0x9d, 0x2b, 0x38, 0xe5, 0x0b, 0xf8, 0x26, 0x6e, 0x85, 0xf7, + 0x38, 0x80, 0x6b, 0xec, 0xd8, 0x31, 0xec, 0x99, 0x3b, 0x46, 0xe4, 0x74, 0x4d, 0xea, 0xd4, 0x14, + 0x33, 0xa2, 0xe6, 0xe5, 0xc1, 0xe3, 0x51, 0xe8, 0xd5, 0xdb, 0x4a, 0xe3, 0x16, 0x0d, 0x76, 0xa4, + 0x41, 0xae, 0x27, 0xc8, 0xb2, 0xe4, 0x07, 0x4f, 0x7d, 0xdf, 0x5c, 0x1c, 0x0c, 0x1b, 0xf2, 0xcf, + 0xb2, 0x65, 0x77, 0xe6, 0xd2, 0xf0, 0x1e, 0x60, 0xdc, 0xc0, 0x5d, 0x12, 0xdd, 0xe1, 0x83, 0xcd, + 0x2f, 0x40, 0x96, 0x5d, 0x36, 0x7c, 0x4d, 0xa1, 0xd9, 0x86, 0xf4, 0x77, 0x63, 0x3e, 0xe2, 0xa5, + 0xe0, 0xf7, 0x29, 0x55, 0xfb, 0x65, 0x43, 0x8f, 0x32, 0x76, 0x03, 0x65, 0x0f, 0xbd, 0xd7, 0x48, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -23088,8 +24368,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_storage #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 368640, // uncompressed data size (bytes) - 368640, // compressed data size (bytes) + 389120, // uncompressed data size (bytes) + 389120, // compressed data size (bytes) kgspBinArchiveConcatenatedFMC_GH100_ucode_image_prod_data, // compressed data pointer NV_FALSE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c index 0e7bcf927f..d262a5d91a 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c @@ -34,1812 +34,1901 @@ // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 28813 +// DATA SIZE (bytes): 36864 +// COMPRESSED SIZE (bytes): 30240 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data[] = { - 0xed, 0xf7, 0x53, 0xb4, 0x6d, 0x4d, 0xd6, 0x2d, 0x8a, 0x4e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0x5c, 0xd3, 0xc6, 0x9a, 0xb6, 0x6d, 0xdb, 0xb6, 0x71, 0x32, 0xff, 0x2f, - 0xf7, 0xde, 0xe7, 0x9c, 0x72, 0xdf, 0xee, 0x7d, 0xbb, 0x59, 0x4b, 0x19, 0x51, 0x23, 0x1a, 0x23, - 0x5a, 0xeb, 0x3d, 0xc6, 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defined(BINDATA_INCLUDE_DATA) @@ -1849,8 +1938,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 32768, // uncompressed data size (bytes) - 28813, // compressed data size (bytes) + 36864, // uncompressed data size (bytes) + 30240, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1868,13 +1957,13 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 43 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x86, 0x08, 0x16, 0x20, 0x2e, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x95, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, - 0x88, 0x20, 0x00, 0x06, 0x3c, 0x73, 0x3c, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x06, 0x20, 0xe2, 0x00, 0xe2, 0x0e, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, + 0x03, 0x8a, 0x1d, 0x80, 0xd8, 0x03, 0x88, 0x35, 0x19, 0x18, 0x18, 0xb1, 0xa9, 0x9b, 0x00, 0x11, + 0x04, 0x00, 0x6d, 0xde, 0x74, 0xe4, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1885,7 +1974,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 43, // compressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1902,1812 +1991,1901 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt; // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 28812 +// DATA SIZE (bytes): 36864 +// COMPRESSED SIZE (bytes): 30239 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data[] = { - 0xed, 0xf7, 0x53, 0xb4, 0x70, 0xbb, 0xd6, 0x2d, 0x00, 0x2e, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0xfa, - 0x96, 0x6d, 0xdb, 0xb6, 0xf5, 0x2d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb5, 0xff, 0xbb, - 0xcf, 0xbd, 0xb7, 0xaa, 0x5a, 0xbd, 0x55, 0xbd, 0xd5, 0xe9, 0xad, 0xcd, 0xf4, 0x64, 0x64, 0x20, - 0xc9, 0x98, 0x99, 0x33, 0x39, 0xbb, 0xb1, 0xa3, 0x4f, 0xe1, 0xbe, 0xb7, 0x03, 0x83, 0x3f, 0x00, - 0x6d, 0x76, 0x68, 0xf1, 0xbb, 0x1c, 0x29, 0xe2, 0xc3, 0x74, 0x08, 0xde, 0xdc, 0xef, 0xd7, 0x9d, - 0x4a, 0x30, 0x2f, 0xb0, 0xed, 0x62, 0x38, 0x6a, 0x92, 0x97, 0x56, 0x34, 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0xff, 0xe9, 0x1d, 0xc6, 0x9d, 0x6d, 0x4c, 0x9c, + 0x0f, 0x0e, 0x10, 0x6e, 0x44, 0xe4, 0xf6, 0xcf, 0x7e, 0xf3, 0xfc, 0xb3, 0x72, 0x7b, 0xc2, 0xff, + 0xfd, 0xfc, 0xfe, 0x1f, 0x27, 0x79, 0xca, 0xf5, 0x5f, 0x6f, 0xa8, 0xbf, 0x77, 0x64, 0x08, 0x00, + 0x40, 0x05, 0xee, 0x52, 0x94, 0x06, 0x25, 0x4f, 0x09, 0xf0, 0xff, 0xcb, 0x7b, 0x0e, 0xe8, 0xff, + 0xce, 0x97, 0xe8, 0x7f, 0x01, 0xe1, 0x6f, 0x32, 0xf8, 0xef, 0x0a, 0x30, 0xfe, 0xe1, 0xff, 0xb6, + 0x09, 0xfe, 0x1e, 0x10, 0xfc, 0x9f, 0x3e, 0x06, 0x06, 0x00, 0xff, 0x43, 0x34, 0xf0, 0xff, 0x9f, + 0xf6, 0x7f, 0x0d, 0x40, 0xfe, 0x1e, 0x52, 0xfc, 0x13, 0x08, 0xe2, 0xff, 0xb7, 0xfa, 0xfe, 0xdb, + 0x1f, 0xfc, 0xbf, 0x75, 0x8c, 0xff, 0xa1, 0x03, 0x02, 0xff, 0x8f, 0xfa, 0xfe, 0x57, 0x3d, 0x20, + 0xff, 0x53, 0x37, 0xf8, 0x6f, 0x1d, 0x18, 0xfc, 0xff, 0xd4, 0xff, 0x77, 0xbd, 0xa0, 0xff, 0x6b, + 0x3e, 0xc1, 0xff, 0xa8, 0x1b, 0xe8, 0x7f, 0xc4, 0xf9, 0x7f, 0x10, 0x00, 0x81, 0x7e, 0x7e, 0x7e, + 0x80, 0x89, 0x7e, 0xfe, 0xc1, 0xff, 0xbf, 0xc3, 0x43, 0x80, 0x20, 0xfe, 0x87, 0x08, 0x58, 0x40, + 0x02, 0xff, 0x8b, 0x01, 0xa0, 0xfe, 0x4b, 0x26, 0x30, 0x40, 0xfb, 0x5b, 0x7f, 0xf5, 0xff, 0x9b, + 0x45, 0x00, 0xfe, 0x66, 0x81, 0x7f, 0x98, 0xa4, 0x1c, 0xff, 0xbf, 0x98, 0xe2, 0x1f, 0xce, 0xff, + 0x07, 0x4d, 0x06, 0x58, 0xec, 0x84, 0xb5, 0x5c, 0x5b, 0x00, 0xa0, 0x7f, 0xcf, 0x03, 0xf9, 0x87, + 0x69, 0xfe, 0xdb, 0xfe, 0x27, 0x9f, 0x3d, 0xea, 0xdf, 0xec, 0xfc, 0x0f, 0xbb, 0xff, 0xc3, 0xff, + 0xab, 0x30, 0x91, 0xbf, 0xfb, 0x0b, 0x02, 0xf0, 0xef, 0xfe, 0xfb, 0x7f, 0x5b, 0x7f, 0xfc, 0x3f, + 0xbf, 0xbf, 0x60, 0xff, 0x3f, 0x7b, 0xe9, 0x5f, 0xfc, 0x8b, 0x7f, 0xf1, 0x2f, 0xfe, 0xc5, 0xbf, + 0xf8, 0x17, 0xff, 0x37, 0xe1, 0xff, 0x02, 0x26, 0x6a, 0xed, 0xd5, 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3717,8 +3895,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 32768, // uncompressed data size (bytes) - 28812, // compressed data size (bytes) + 36864, // uncompressed data size (bytes) + 30239, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3736,13 +3914,13 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 84 -// COMPRESSED SIZE (bytes): 43 +// COMPRESSED SIZE (bytes): 42 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x00, 0x82, 0x02, 0x06, 0x86, 0x08, 0x16, 0x20, 0x2e, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0xd8, 0x01, 0x88, 0x3d, 0x80, 0x58, 0x95, 0x81, 0x81, 0x11, 0x9b, 0xba, 0x06, - 0x88, 0x20, 0x00, 0x06, 0x3c, 0x73, 0x3c, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x06, 0x20, 0xe2, 0x00, 0xe2, 0x0e, 0x06, 0x06, 0x01, 0x06, 0x2c, 0x80, + 0x03, 0x8a, 0x1d, 0x80, 0xd8, 0x03, 0x88, 0x35, 0x19, 0x18, 0x18, 0xb1, 0xa9, 0x9b, 0x00, 0x11, + 0x04, 0x00, 0x6d, 0xde, 0x74, 0xe4, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3753,7 +3931,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 84, // uncompressed data size (bytes) - 43, // compressed data size (bytes) + 42, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_desc_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c index 1dc4353715..51650a4dc4 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GA102.c @@ -34,1043 +34,1132 @@ // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20480 -// COMPRESSED SIZE (bytes): 16512 +// DATA SIZE (bytes): 24576 +// COMPRESSED SIZE (bytes): 17932 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data[] = { - 0xed, 0xb7, 0x53, 0x94, 0x6d, 0x49, 0xbb, 0x05, 0x98, 0xb6, 0x6d, 0xdb, 0xb6, 0x9d, 0x79, 0xd2, - 0xb6, 0x4f, 0xda, 0xb6, 0x6d, 0xdb, 0xb6, 0x8d, 0x93, 0xb6, 0x6d, 0xdb, 0xb6, 0xba, 0xfe, 0x5b, - 0x75, 0xef, 0xed, 0xee, 0xd1, 0x6f, 0xdd, 0x6f, 0x5d, 0x73, 0x8c, 0x1d, 0x33, 0xe2, 0xd3, 0x8c, - 0x88, 0x6f, 0xaf, 0xb5, 0xc7, 0xce, 0x73, 0x70, 0xfb, 0x49, 0x23, 0x37, 0x85, 0x64, 0x9e, 0x0a, - 0x10, 0x55, 0xf4, 0x02, 0xbf, 0x24, 0x80, 0x18, 0xc2, 0x01, 0xa1, 0x1d, 0x7a, 0x3c, 0x8f, 0x02, - 0xf5, 0x10, 0xf6, 0x11, 0x01, 0xe0, 0x93, 0xd6, 0xd2, 0x4c, 0xf0, 0xdf, 0xc4, 0x10, 0x48, 0xec, - 0x45, 0x2a, 0xd3, 0xa0, 0xbc, 0xb0, 0x88, 0x63, 0x91, 0x5d, 0x89, 0x36, 0x08, 0x0a, 0xac, 0xe2, - 0x23, 0x5f, 0x61, 0x9a, 0x11, 0xea, 0x10, 0xa5, 0xe0, 0x4e, 0x7f, 0x7a, 0x46, 0x40, 0x0a, 0x9f, - 0x64, 0x91, 0x37, 0xb9, 0x91, 0x4e, 0xd2, 0xdd, 0x3c, 0xca, 0x2f, 0x4e, 0x01, 0x88, 0x7a, 0x1b, - 0x9a, 0x05, 0x7e, 0x0d, 0xa2, 0xb1, 0xdb, 0x4a, 0xc0, 0x63, 0xf4, 0x16, 0xae, 0xed, 0x97, 0x24, - 0x91, 0x01, 0xb2, 0x31, 0x59, 0xbe, 0xb7, 0x28, 0xd4, 0x3a, 0x74, 0xbd, 0x07, 0x95, 0x79, 0x91, - 0x86, 0x48, 0x85, 0x23, 0x34, 0x80, 0x43, 0xf5, 0x2d, 0x4f, 0x0a, 0xfe, 0x83, 0x60, 0x6e, 0x3c, - 0xed, 0x10, 0xc9, 0xf6, 0x91, 0x10, 0xec, 0x5f, 0x09, 0xe1, 0xf0, 0x24, 0x9c, 0xa7, 0x07, 0x89, - 0x14, 0x98, 0x6a, 0x64, 0xa1, 0x0f, 0xbc, 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#endif // defined(BINDATA_INCLUDE_DATA) @@ -1080,8 +1169,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20480, // uncompressed data size (bytes) - 16512, // compressed data size (bytes) + 24576, // uncompressed data size (bytes) + 17932, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1103,9 +1192,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_data[] = { - 0x63, 0x65, 0x00, 0x02, 0x07, 0x06, 0x86, 0x08, 0x16, 0x20, 0x76, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0xaa, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x05, 0x40, - 0x04, 0x01, 0xce, 0xa8, 0x04, 0xe4, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x00, 0x06, 0x86, 0x06, 0x0e, 0x20, 0x8e, 0x60, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0x9a, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x25, 0x40, + 0x04, 0x01, 0xd4, 0x4b, 0xa9, 0xea, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1133,1044 +1222,1132 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_desc_dbg_storage_pvt; // VAR NAME: N/A // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 20480 -// COMPRESSED SIZE (bytes): 16514 +// DATA SIZE (bytes): 24576 +// COMPRESSED SIZE (bytes): 17934 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data[] = { - 0xed, 0xb7, 0x53, 0x94, 0x65, 0x4b, 0xbb, 0x05, 0xb8, 0xd3, 0xae, 0xb4, 0x6d, 0xdb, 0x36, 0x2a, - 0x6d, 0xdb, 0x36, 0x2a, 0x6d, 0xdb, 0x99, 0x95, 0xb6, 0x6d, 0xdb, 0xb6, 0x2b, 0x6d, 0xdb, 0x99, - 0x7d, 0xfe, 0x7b, 0xce, 0xbd, 0xb7, 0xbb, 0x47, 0xbf, 0x75, 0xbf, 0xf5, 0x99, 0x63, 0xec, 0x98, - 0x11, 0x9f, 0x66, 0x44, 0x7c, 0x6b, 0xad, 0x31, 0x76, 0x27, 0xcc, 0x52, 0x7e, 0x83, 0x7f, 0xb7, - 0x62, 0x86, 0x74, 0xca, 0x11, 0xe2, 0xa0, 0x54, 0x69, 0xbb, 0xbb, 0x25, 0x3b, 0x72, 0xe9, 0x98, - 0x9b, 0xf5, 0x20, 0x92, 0x7c, 0x55, 0xa6, 0xd4, 0xfa, 0xc6, 0x68, 0xd3, 0xb8, 0x4f, 0x4c, 0x92, - 0xb1, 0xb7, 0x65, 0xd9, 0xbe, 0x5e, 0x71, 0xcc, 0x15, 0x39, 0xf4, 0x85, 0x9b, 0x9a, 0xe0, 0xa0, - 0x57, 0x63, 0x8d, 0xe3, 0xef, 0xd0, 0x45, 0x9f, 0xc5, 0x4d, 0xea, 0xc8, 0xc8, 0xf6, 0x25, 0xc2, - 0xd8, 0x18, 0xa7, 0xe5, 0x9a, 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0x95, 0x12, 0xfe, 0x8b, 0xa9, 0xfe, 0x70, + 0xee, 0x1f, 0xd4, 0x19, 0xe2, 0x70, 0x12, 0x57, 0xf1, 0xac, 0x01, 0x20, 0x7e, 0xcf, 0x03, 0xff, + 0xc3, 0x74, 0xff, 0xb6, 0xff, 0xe4, 0xb3, 0x47, 0xff, 0xcd, 0xce, 0x7f, 0xd8, 0xfd, 0x0f, 0xff, + 0x57, 0x61, 0x68, 0xbf, 0xfb, 0x0b, 0x1a, 0xe4, 0x77, 0xff, 0xfd, 0xdf, 0xd6, 0x6f, 0xf8, 0xe7, + 0xf7, 0x17, 0xec, 0xff, 0xb3, 0x97, 0xfe, 0xc1, 0x3f, 0xf8, 0x07, 0xff, 0xe0, 0x1f, 0xfc, 0x83, + 0x7f, 0xf0, 0xbf, 0x09, 0xff, 0x0b, 0x48, 0xe1, 0x8a, 0xe3, 0x00, 0x60, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -2180,8 +2357,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 20480, // uncompressed data size (bytes) - 16514, // compressed data size (bytes) + 24576, // uncompressed data size (bytes) + 17934, // compressed data size (bytes) kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -2203,9 +2380,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GA102_ucode_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GA102_ucode_desc_prod_data[] = { - 0x63, 0x65, 0x00, 0x02, 0x07, 0x06, 0x86, 0x08, 0x16, 0x20, 0x76, 0x61, 0x60, 0x10, 0x60, 0xc0, - 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0xaa, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x05, 0x40, - 0x04, 0x01, 0xce, 0xa8, 0x04, 0xe4, 0x54, 0x00, 0x00, 0x00, + 0x63, 0x65, 0x00, 0x82, 0x00, 0x06, 0x86, 0x06, 0x0e, 0x20, 0x8e, 0x60, 0x60, 0x10, 0x60, 0xc0, + 0x02, 0x38, 0xa0, 0x18, 0x24, 0x29, 0x01, 0xc4, 0x9a, 0x0c, 0x0c, 0x8c, 0xd8, 0xd4, 0x25, 0x40, + 0x04, 0x01, 0xd4, 0x4b, 0xa9, 0xea, 0x54, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c index 391372c51f..9e6f789f99 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c @@ -63,10318 +63,10318 @@ static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_dbg_data[] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x99, 0x15, 0xd8, 0x38, 0x95, 0x6c, 0x98, 0x5e, 0x89, 0xc0, 0x53, 0x2d, 0x54, 0x4c, 0x9b, 0x50, - 0x31, 0xf1, 0xee, 0xad, 0xc5, 0xc8, 0x0b, 0x32, 0x88, 0x24, 0x4a, 0xa9, 0xe5, 0xf0, 0x9c, 0x2b, - 0x34, 0x1e, 0x37, 0x2e, 0x2a, 0x4a, 0xae, 0xc9, 0x8f, 0x4b, 0xd2, 0x4c, 0x56, 0xfb, 0x2d, 0x05, - 0x61, 0x20, 0x04, 0x38, 0x67, 0xf9, 0xb1, 0x41, 0xad, 0x02, 0x56, 0xb7, 0xd2, 0x9c, 0x3c, 0x57, - 0x10, 0xff, 0xda, 0xcf, 0xcb, 0xde, 0xc0, 0x62, 0x2a, 0x26, 0x3a, 0x8a, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -10601,10342 +10601,10342 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_GH100_ucode_desc_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_GH100_ucode_image_prod_data[] = { - 0x12, 0x19, 0xeb, 0x11, 0xfe, 0xee, 0x8f, 0xca, 0xa7, 0x53, 0x54, 0xe4, 0x1a, 0x47, 0xf3, 0xce, - 0xa9, 0x8a, 0x8a, 0x1b, 0xc1, 0xa2, 0xce, 0x49, 0x05, 0xc0, 0xa1, 0x6e, 0x22, 0xf2, 0xab, 0x67, - 0x65, 0x5c, 0xc3, 0xeb, 0x23, 0xe3, 0x03, 0x5b, 0x5a, 0xca, 0x9c, 0xd5, 0xac, 0x98, 0x0b, 0xfe, - 0xa1, 0xab, 0x31, 0xad, 0xbc, 0x37, 0xa9, 0xa8, 0x6c, 0x56, 0x8f, 0xe8, 0x39, 0x5e, 0x1e, 0xea, - 0x22, 0xb0, 0x19, 0x5b, 0x29, 0xc6, 0xeb, 0x58, 0x3e, 0xd9, 0x29, 0xf5, 0x62, 0xb3, 0xe2, 0xb8, - 0xa6, 0xc5, 0x7b, 0x67, 0xb5, 0xc3, 0xea, 0x1a, 0x6b, 0xfc, 0x9e, 0xa1, 0xea, 0x8b, 0x2b, 0xc3, - 0xa3, 0xd4, 0x06, 0xd7, 0x8e, 0x0b, 0xf1, 0xa2, 0xe6, 0x25, 0x8f, 0x35, 0xee, 0xf3, 0x9e, 0x07, - 0x11, 0xca, 0x74, 0xdb, 0x46, 0x72, 0x98, 0x0e, 0x8b, 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0x64, 0x6b, + 0x67, 0xfb, 0xd6, 0x0b, 0x45, 0x40, 0x74, 0x56, 0xb3, 0x62, 0x1c, 0xe6, 0xcf, 0xc7, 0x2b, 0x5b, + 0x0f, 0xbb, 0x56, 0xc8, 0xee, 0x6d, 0xe8, 0x6d, 0x97, 0x47, 0x49, 0x63, 0x3d, 0x00, 0x30, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c index fc82174fd3..e4f6597d33 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100.c @@ -43,10391 +43,10391 @@ static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_imag 0x00, 0x00, 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0xc4, 0x27, 0x7f, 0x0a, 0x47, 0x67, 0x55, 0xee, 0x20, 0x57, + 0x0d, 0x1d, 0x82, 0xfa, 0xb2, 0xb6, 0x3c, 0x11, 0x6a, 0x89, 0xf1, 0x4f, 0x96, 0xd8, 0xc7, 0xd0, + 0x62, 0x93, 0x54, 0xbc, 0x6d, 0x16, 0x44, 0xf7, 0x20, 0x13, 0xa5, 0xb3, 0x24, 0x5e, 0xff, 0xc8, + 0x18, 0x8f, 0x0a, 0x18, 0xe6, 0x69, 0xf3, 0x9b, 0x07, 0x65, 0x88, 0xce, 0xa0, 0x48, 0xae, 0xb9, + 0xea, 0x0f, 0x91, 0x0d, 0x00, 0x7c, 0xea, 0xcd, 0xd2, 0x19, 0xa1, 0xb7, 0x4a, 0x50, 0x3a, 0xee, + 0xaf, 0x48, 0xee, 0x24, 0x53, 0x4f, 0xbb, 0xfe, 0xb1, 0x5b, 0x27, 0xdd, 0x80, 0xf8, 0x87, 0xfd, + 0xa2, 0xf1, 0x9b, 0x90, 0x54, 0x1f, 0x66, 0x92, 0x0b, 0xc9, 0xfb, 0x25, 0xae, 0x6a, 0xa0, 0x81, + 0xc2, 0x6f, 0x79, 0xf4, 0x8e, 0x02, 0xcb, 0x24, 0x25, 0xf8, 0x81, 0xe7, 0x3a, 0xf0, 0xd6, 0xd9, + 0x5b, 0xb2, 0x2b, 0x09, 0xc6, 0x1f, 0x2d, 0xd3, 0x64, 0xc8, 0x76, 0x00, 0x32, 0x12, 0x6d, 0xfa, + 0xf6, 0xc3, 0x76, 0xd1, 0x40, 0xef, 0x7e, 0xc1, 0x5e, 0xbd, 0x8d, 0x6a, 0x40, 0xa2, 0xce, 0x1c, + 0xe4, 0x29, 0x5f, 0x21, 0x68, 0x98, 0x74, 0xbf, 0xf5, 0x97, 0x6c, 0x59, 0x98, 0x1d, 0x0f, 0x19, + 0x09, 0xbe, 0xa9, 0x80, 0xcd, 0x26, 0x34, 0x76, 0x44, 0xd5, 0xf3, 0x8e, 0xcd, 0x65, 0x67, 0x78, + 0x4a, 0x74, 0x12, 0xc6, 0x26, 0xbb, 0x5c, 0x03, 0x28, 0x4f, 0x32, 0x45, 0x63, 0x24, 0x5c, 0x12, + 0x50, 0x09, 0xe2, 0x35, 0x3d, 0xa8, 0x50, 0x26, 0xb7, 0xf6, 0x93, 0x4a, 0x2d, 0x2d, 0xea, 0x16, + 0x84, 0x87, 0xdf, 0xfd, 0x53, 0xf1, 0xf9, 0x5e, 0x5e, 0x09, 0x0c, 0x5e, 0x23, 0xf7, 0xb6, 0xba, + 0x34, 0xe6, 0xed, 0xb2, 0x41, 0x11, 0xd6, 0x0e, 0xaa, 0xe2, 0x29, 0x41, 0xd5, 0x26, 0x76, 0x8b, + 0x5a, 0x91, 0x1d, 0x90, 0x19, 0x91, 0x5b, 0xea, 0x8a, 0x03, 0xe3, 0x3e, 0x5f, 0x23, 0x25, 0xf9, + 0x97, 0x0a, 0x15, 0xed, 0x32, 0xd3, 0xeb, 0x25, 0x7c, 0x17, 0xf3, 0x03, 0xb5, 0x49, 0xa7, 0xf4, + 0x4b, 0x69, 0x8c, 0xc4, 0xbb, 0x73, 0xe6, 0x24, 0x0d, 0x01, 0xb7, 0x1c, 0x09, 0xf2, 0xa6, 0x6d, + 0x26, 0xcd, 0x1e, 0xa4, 0x52, 0x4a, 0xf9, 0xeb, 0xf5, 0xab, 0x19, 0x77, 0xf1, 0x85, 0xec, 0x56, + 0x9b, 0xa5, 0xac, 0xb8, 0x01, 0xfd, 0x5f, 0x4b, 0xf9, 0x07, 0x83, 0xc6, 0x6e, 0x41, 0x5d, 0xd6, + 0x9e, 0x11, 0x9a, 0xde, 0x1c, 0x2c, 0x60, 0xd7, 0xda, 0x95, 0x3d, 0x80, 0x61, 0x0b, 0x6d, 0x0c, + 0x1e, 0x3e, 0x74, 0x84, 0xe2, 0xd5, 0xd7, 0x22, 0x5b, 0x42, 0xf3, 0x80, 0x77, 0x93, 0xbf, 0xb7, + 0x3d, 0x24, 0x1d, 0x89, 0x65, 0x98, 0xae, 0x89, 0x26, 0xd0, 0xac, 0xae, 0x96, 0xa2, 0x14, 0x11, + 0x45, 0x7d, 0x30, 0x04, 0xf7, 0xc5, 0x9a, 0x82, 0x91, 0xd1, 0x2f, 0xce, 0x94, 0x81, 0x03, 0xe7, + 0xf4, 0xd8, 0x65, 0xa7, 0x97, 0x13, 0xe3, 0xb3, 0x2b, 0xd0, 0x8d, 0x7f, 0x63, 0xdb, 0xcf, 0xf5, + 0x9f, 0xea, 0xeb, 0x18, 0xd7, 0xef, 0xc3, 0x12, 0xbd, 0x87, 0x30, 0xd0, 0xab, 0xfc, 0x2c, 0x6f, + 0xa5, 0xe4, 0xd7, 0x2a, 0x8b, 0x06, 0xe8, 0x72, 0xe0, 0x76, 0x02, 0x08, 0xf4, 0x09, 0x66, 0xd6, + 0x6f, 0x15, 0x65, 0x3c, 0xc1, 0x75, 0xab, 0x9e, 0xcf, 0x11, 0x5e, 0x9c, 0xe9, 0x84, 0xda, 0xac, + 0x3a, 0x3a, 0xd7, 0x03, 0xab, 0x96, 0xa8, 0xd0, 0xcc, 0x60, 0x1d, 0xc3, 0x5d, 0x53, 0xaf, 0xce, + 0x59, 0xb1, 0xb6, 0x96, 0x0e, 0x17, 0xb1, 0x93, 0xf0, 0x58, 0xae, 0x13, 0x7c, 0x9a, 0xcf, 0xdb, + 0xaf, 0x64, 0x5b, 0x1a, 0x1c, 0x8a, 0x9e, 0xe9, 0x02, 0x96, 0xc3, 0xbe, 0x84, 0x23, 0xef, 0xce, + 0x78, 0x24, 0x5a, 0x85, 0x4e, 0x5e, 0xa2, 0x07, 0x6c, 0xb2, 0x56, 0x00, 0x7b, 0x6b, 0xee, 0xff, + 0x40, 0xf3, 0xa6, 0x28, 0x91, 0x10, 0x86, 0x49, 0x49, 0x0b, 0x01, 0x75, 0x32, 0xf1, 0xbe, 0xf6, + 0xfc, 0xd6, 0xba, 0x75, 0x60, 0xfc, 0x73, 0xad, 0x42, 0x78, 0x52, 0x96, 0x4f, 0x4e, 0xef, 0x74, + 0x4a, 0x2c, 0xa0, 0x81, 0x73, 0x40, 0x67, 0xa9, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10460,9 +10460,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_image_stor // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0xa1, 0x93, 0x1e, 0x90, 0x92, 0x3a, 0x33, 0x50, 0x5c, 0xe1, 0x32, 0x92, 0x8b, 0xcf, 0x80, 0x55, - 0x66, 0x11, 0x7d, 0xc2, 0x7e, 0xe1, 0xd6, 0x18, 0x9c, 0x14, 0xe9, 0x2f, 0xb3, 0xcb, 0x05, 0xc1, - 0x20, 0xc4, 0xb2, 0x26, 0xa0, 0x7c, 0x1a, 0xaf, 0x8e, 0x4c, 0x0f, 0x0f, 0xea, 0x4a, 0xf2, 0x4d, + 0x6b, 0xf9, 0x70, 0x36, 0x59, 0xd2, 0x4a, 0x9d, 0x83, 0x12, 0x7d, 0x71, 0x5e, 0xbf, 0x05, 0xa5, + 0xfd, 0x37, 0xbe, 0xde, 0x39, 0xb9, 0x9a, 0xd7, 0x87, 0x8f, 0xc6, 0x9f, 0xa6, 0xbb, 0x21, 0x27, + 0xb5, 0x61, 0xa8, 0xaa, 0xad, 0x62, 0x64, 0xbd, 0xe9, 0x20, 0xe8, 0xba, 0x7e, 0x90, 0x3a, 0xc2, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10495,30 +10495,30 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_hash_stora // static BINDATA_CONST NvU8 kgspBinArchiveGspRmCcFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x80, 0xaf, 0xa9, 0x02, 0xb2, 0xb3, 0x77, 0xf8, 0xa3, 0x6d, 0x35, 0x24, 0x7f, 0x44, 0x39, 0x42, - 0x93, 0x08, 0xc8, 0xf1, 0xfd, 0x74, 0xfa, 0xe3, 0x11, 0x11, 0x64, 0xc4, 0x1f, 0x2c, 0xf4, 0x6b, - 0x3c, 0xd5, 0x7a, 0xaf, 0x33, 0x79, 0x9e, 0xf7, 0xf5, 0x78, 0xdc, 0xbe, 0xb7, 0x99, 0xea, 0x30, - 0x25, 0x21, 0xe7, 0x1b, 0xa4, 0x80, 0xa4, 0x6e, 0x57, 0xe1, 0x65, 0x3b, 0x3f, 0xe6, 0xc5, 0x40, - 0x03, 0x27, 0xf9, 0x91, 0x3c, 0xa7, 0xee, 0xe9, 0x15, 0xe3, 0x20, 0x1d, 0x72, 0xd4, 0x01, 0x14, - 0x10, 0xb5, 0x1d, 0x30, 0xe5, 0x99, 0x09, 0xf7, 0x5e, 0x77, 0x2a, 0xb3, 0x89, 0xbb, 0x24, 0x9d, - 0x45, 0x3f, 0xf8, 0x85, 0x8c, 0x6c, 0xa9, 0x63, 0xc0, 0x63, 0x09, 0x06, 0x71, 0x2c, 0xaa, 0x7c, - 0x98, 0xf6, 0x4d, 0x41, 0xf2, 0xa4, 0xc9, 0x25, 0x58, 0xc1, 0x61, 0x8b, 0xb7, 0x05, 0xfd, 0x57, - 0x24, 0x0b, 0x10, 0xb6, 0x1e, 0xf9, 0x91, 0x2f, 0xfa, 0xcd, 0x9a, 0x30, 0x69, 0x0f, 0x26, 0x8f, - 0xdc, 0x1e, 0x77, 0x0a, 0xcf, 0xcd, 0xeb, 0x11, 0x9f, 0xe6, 0x13, 0xc6, 0x98, 0x6b, 0x6b, 0x2d, - 0x35, 0xc6, 0x7d, 0x17, 0x5d, 0xac, 0x17, 0xc4, 0x3d, 0x38, 0x21, 0x94, 0x5e, 0x4e, 0x70, 0x11, - 0x19, 0x6b, 0xf8, 0x28, 0x1f, 0xed, 0xf3, 0x2f, 0xbc, 0x22, 0x13, 0x84, 0xd7, 0xef, 0xbe, 0x38, - 0x96, 0x18, 0x81, 0xe9, 0x61, 0x6b, 0x54, 0x16, 0x92, 0xa5, 0xf3, 0xb9, 0x0b, 0x16, 0x53, 0xe2, - 0x1f, 0xd5, 0xd7, 0x90, 0x41, 0x81, 0xc2, 0x53, 0x07, 0xad, 0x5c, 0x3f, 0xce, 0xa3, 0x83, 0xf2, - 0x63, 0x7e, 0xba, 0xdf, 0x8d, 0x79, 0x59, 0x8d, 0x55, 0x6e, 0xab, 0x2c, 0x8f, 0xf8, 0xed, 0x54, - 0xc4, 0x78, 0x76, 0x62, 0xdb, 0x07, 0x9f, 0x87, 0xd4, 0x99, 0x13, 0xc7, 0xf3, 0x60, 0x83, 0x96, - 0x91, 0x0b, 0xba, 0xbf, 0x0b, 0x61, 0xad, 0xd0, 0xf4, 0xaa, 0xcd, 0xba, 0x63, 0xb4, 0xae, 0xb7, - 0xbf, 0xb0, 0xdf, 0x63, 0x3c, 0xdc, 0xfa, 0xea, 0xe6, 0x3c, 0xcd, 0x0a, 0xa5, 0xc9, 0x3c, 0x04, - 0x9b, 0x80, 0x0f, 0x32, 0x38, 0x11, 0xdf, 0x26, 0xf7, 0xc2, 0xba, 0x5f, 0xe7, 0xdb, 0xb0, 0x97, - 0x72, 0x94, 0x11, 0x8b, 0x4e, 0x81, 0xdd, 0xf8, 0x7f, 0x74, 0x55, 0xdd, 0x0c, 0xc2, 0xe4, 0xd3, - 0xb9, 0x41, 0xe9, 0xd4, 0x98, 0x0f, 0x65, 0x16, 0xa7, 0x38, 0x99, 0x2f, 0x9e, 0xf3, 0x55, 0x41, - 0xa5, 0x6c, 0xc6, 0xc1, 0x1b, 0xb9, 0x16, 0xbb, 0x62, 0x2e, 0x96, 0xad, 0x94, 0xd2, 0xe3, 0x75, - 0xc2, 0x0b, 0xf4, 0x86, 0xac, 0x22, 0xc9, 0x4f, 0x8f, 0x9d, 0x11, 0xe9, 0x4e, 0x09, 0x95, 0x71, - 0x3d, 0xc7, 0x5a, 0x6c, 0x52, 0x94, 0x6d, 0x2e, 0x8c, 0xf4, 0xce, 0xa6, 0x87, 0xa1, 0xf2, 0xd0, + 0x92, 0x7a, 0xe0, 0x82, 0x25, 0xf1, 0x81, 0x43, 0x77, 0xbf, 0x91, 0x7c, 0x9e, 0xa4, 0xdd, 0x7e, + 0xcb, 0xbe, 0x6e, 0x74, 0x84, 0xbe, 0x23, 0x19, 0x39, 0x42, 0x95, 0x3d, 0xa7, 0xd7, 0x12, 0xe2, + 0x19, 0x7c, 0x3e, 0x5a, 0x25, 0xaf, 0xe4, 0x3d, 0xfd, 0x71, 0xd3, 0x8a, 0x2c, 0x96, 0x30, 0x97, + 0xf1, 0x12, 0xba, 0x98, 0x36, 0xc5, 0x26, 0xf9, 0xa6, 0x4b, 0xb2, 0xb7, 0x0d, 0xd3, 0x3d, 0xf1, + 0xc0, 0x0b, 0xc7, 0x33, 0xc8, 0x23, 0xef, 0x94, 0x7a, 0xc1, 0xe6, 0x0f, 0x8f, 0xba, 0x6a, 0x85, + 0x83, 0xbf, 0xf8, 0xb8, 0xd5, 0xfb, 0x86, 0x46, 0x87, 0xe2, 0x3d, 0x73, 0xb1, 0x88, 0x03, 0x4a, + 0xc2, 0xdf, 0xbf, 0x7e, 0xcb, 0xb0, 0x82, 0x87, 0xd5, 0x8d, 0x39, 0xb4, 0xe9, 0xb3, 0xc4, 0xfc, + 0x1b, 0xe2, 0xa1, 0x89, 0xc9, 0x78, 0xc4, 0x66, 0x25, 0x9f, 0x84, 0xba, 0x78, 0x40, 0x60, 0x5d, + 0x27, 0x44, 0x66, 0xd8, 0x76, 0xd2, 0x54, 0x19, 0x76, 0xc9, 0xe0, 0xc7, 0xaf, 0xc4, 0x6f, 0x7f, + 0x6c, 0x4a, 0x76, 0xc7, 0x29, 0x44, 0x8f, 0xeb, 0x46, 0x19, 0x9b, 0x84, 0xd1, 0x16, 0x9d, 0xc9, + 0x6d, 0xfb, 0x3e, 0xb9, 0x74, 0x3b, 0x4d, 0xf0, 0x2b, 0x8c, 0x22, 0x2d, 0xdd, 0x82, 0x1a, 0x69, + 0x4d, 0xbf, 0xdf, 0x72, 0xe0, 0x48, 0xf4, 0x3b, 0x27, 0x82, 0x77, 0x9e, 0xb7, 0x5f, 0x12, 0xd8, + 0x7f, 0xb4, 0xc3, 0x51, 0x9d, 0x7a, 0x5d, 0xbe, 0x8f, 0x2e, 0x6f, 0x48, 0x68, 0xde, 0xc4, 0x96, + 0x7f, 0x6c, 0xc2, 0xcf, 0xc3, 0xb6, 0x96, 0x82, 0x7a, 0xeb, 0x14, 0xc8, 0xe2, 0x95, 0x00, 0xb4, + 0x59, 0x33, 0xb4, 0x99, 0xba, 0xa3, 0xa7, 0x8b, 0xc2, 0x12, 0xca, 0x05, 0xc1, 0x07, 0xbf, 0xfd, + 0x25, 0x5f, 0xe4, 0xbc, 0x48, 0xc4, 0xd3, 0x72, 0x7a, 0xd5, 0x17, 0x46, 0x7f, 0x39, 0x73, 0x89, + 0x37, 0xbf, 0x3d, 0x57, 0xd8, 0x76, 0x03, 0x06, 0xbd, 0x54, 0xb0, 0xe6, 0x5b, 0x19, 0x2b, 0x32, + 0x83, 0xb5, 0x7c, 0x09, 0x77, 0x8d, 0xa3, 0x72, 0x44, 0xaf, 0x00, 0x92, 0x5f, 0x61, 0x3d, 0xda, + 0x6f, 0x64, 0xb4, 0x04, 0x20, 0xb7, 0x70, 0x39, 0xdf, 0xdf, 0xa0, 0x3e, 0xc8, 0x25, 0x41, 0x90, + 0xe1, 0xf4, 0x3e, 0x43, 0x3d, 0x4e, 0xb8, 0xb0, 0x8e, 0xf2, 0xed, 0x34, 0x89, 0x4f, 0xa0, 0x4c, + 0x23, 0x37, 0x3b, 0x77, 0x62, 0x97, 0x6b, 0xba, 0xae, 0xb6, 0xad, 0xec, 0x21, 0x29, 0x5c, 0x86, + 0x14, 0xe4, 0x2b, 0x03, 0x3e, 0x96, 0xb1, 0x79, 0x84, 0x81, 0xf3, 0x16, 0x3e, 0x38, 0xee, 0x7d, + 0xf8, 0x6e, 0xe2, 0xae, 0x90, 0x0a, 0x3e, 0xb5, 0xb5, 0x35, 0x20, 0x43, 0x51, 0xb5, 0x3d, 0x0d, + 0xdf, 0xd5, 0x58, 0x3e, 0x55, 0x07, 0xe3, 0x68, 0x36, 0x99, 0x43, 0x3a, 0x3e, 0x20, 0x2c, 0x4d, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c index ea1a5ec7f4..0c7002ec3c 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c @@ -43,10183 +43,10183 @@ static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -10243,143 +10243,143 @@ static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x15, 0xd8, 0x38, 0x95, 0x6c, 0x98, 0x5e, - 0x89, 0xc0, 0x53, 0x2d, 0x54, 0x4c, 0x9b, 0x50, 0x31, 0xf1, 0xee, 0xad, 0xc5, 0xc8, 0x0b, 0x32, - 0x88, 0x24, 0x4a, 0xa9, 0xe5, 0xf0, 0x9c, 0x2b, 0x34, 0x1e, 0x37, 0x2e, 0x2a, 0x4a, 0xae, 0xc9, - 0x8f, 0x4b, 0xd2, 0x4c, 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defined(BINDATA_INCLUDE_DATA) @@ -10412,9 +10412,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_image_stora // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_data[] = { - 0x36, 0x00, 0x33, 0x10, 0xa8, 0xcd, 0x15, 0x1f, 0xf7, 0xb0, 0x68, 0xe2, 0xb8, 0x70, 0x81, 0x0a, - 0x03, 0x81, 0x25, 0xa8, 0x4d, 0x6e, 0x50, 0xb5, 0xf7, 0x87, 0x10, 0x61, 0xc9, 0xa8, 0x0e, 0x42, - 0xbd, 0xa5, 0x5a, 0x43, 0x7d, 0x0a, 0xd2, 0xd8, 0xb1, 0x06, 0x64, 0x1a, 0xae, 0x0c, 0x72, 0x39, + 0x7d, 0x21, 0xc9, 0x0d, 0x9a, 0x60, 0xa3, 0xb2, 0x2e, 0xab, 0x93, 0x37, 0x79, 0x00, 0xdf, 0x74, + 0x8e, 0x99, 0xba, 0xae, 0x8a, 0xa1, 0x9a, 0x6f, 0x45, 0xcb, 0x0c, 0xfa, 0x89, 0x76, 0xf9, 0xd5, + 0x62, 0x42, 0x66, 0x6e, 0x09, 0x32, 0xfc, 0x5e, 0xa4, 0x3d, 0xe2, 0x4c, 0x57, 0x8b, 0x96, 0x54, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10447,30 +10447,30 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_hash_storag // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwDebugSigned_GH100_ucode_sig_data[] = { - 0x3a, 0xeb, 0xf2, 0x68, 0x7f, 0x35, 0x78, 0xef, 0x56, 0x3e, 0x5a, 0xa3, 0x0c, 0x93, 0x6a, 0x5c, - 0xa0, 0x33, 0xab, 0xee, 0x34, 0x34, 0x48, 0x0f, 0x99, 0x6d, 0x19, 0x13, 0x4a, 0x75, 0x51, 0xaf, - 0x8c, 0x12, 0x8b, 0x3c, 0x55, 0x1a, 0x9a, 0x54, 0x62, 0xc5, 0x51, 0xfa, 0x65, 0xdf, 0xbc, 0x85, - 0x9d, 0x67, 0x9d, 0x73, 0xa2, 0x9d, 0xe2, 0xc6, 0xb4, 0x04, 0xd0, 0xe8, 0x76, 0xe3, 0x3a, 0xcf, - 0x2e, 0xb0, 0x35, 0x62, 0x05, 0x95, 0xc2, 0x6b, 0x94, 0x84, 0xa9, 0x20, 0x9f, 0xa5, 0x1d, 0xc1, - 0x65, 0xe7, 0x02, 0xd9, 0x82, 0xe9, 0xd5, 0x02, 0x6f, 0xd5, 0x3b, 0x51, 0x9b, 0xe5, 0xcc, 0x59, - 0x2f, 0xc9, 0xf0, 0x84, 0xd2, 0x15, 0x1d, 0xaf, 0xdb, 0xe6, 0x8a, 0x61, 0x95, 0x7d, 0x49, 0x1f, - 0x17, 0xf2, 0x4d, 0xfc, 0x2a, 0xcf, 0x57, 0x2b, 0x8a, 0x68, 0x1b, 0xd7, 0x98, 0x6c, 0x47, 0xb0, - 0x76, 0xd0, 0xd5, 0xb4, 0xf4, 0xbf, 0x26, 0x9c, 0xba, 0xd9, 0x23, 0x40, 0xe7, 0x47, 0x17, 0xb7, - 0x49, 0xa6, 0x1f, 0x90, 0x31, 0xa8, 0xea, 0x22, 0x53, 0x81, 0xe9, 0x9b, 0xae, 0xb9, 0x92, 0x8f, - 0x2c, 0x44, 0x64, 0x6c, 0x1c, 0x58, 0x90, 0x28, 0x6f, 0xdd, 0xb2, 0x32, 0x2f, 0x35, 0x01, 0xbe, - 0xda, 0xcb, 0x50, 0xfa, 0xd9, 0x0c, 0x47, 0x30, 0xaa, 0x80, 0x98, 0xe2, 0xb6, 0x03, 0x73, 0x94, - 0x2f, 0x5e, 0xfb, 0x2c, 0xe9, 0xf7, 0x9c, 0xff, 0x30, 0x9e, 0xa0, 0xfa, 0x54, 0xc1, 0xe6, 0xb7, - 0x66, 0x21, 0x3b, 0x5e, 0xc9, 0x60, 0xd9, 0x9e, 0xc1, 0xc4, 0xda, 0x6c, 0x54, 0xce, 0x27, 0x92, - 0xde, 0x1f, 0x4a, 0xc4, 0x53, 0xd8, 0x17, 0xca, 0xce, 0xaa, 0x3d, 0x4d, 0x70, 0xf2, 0xf0, 0xdb, - 0xd6, 0xe3, 0xa2, 0x63, 0x9b, 0x45, 0xaf, 0x8c, 0xb1, 0x4f, 0x6c, 0x4f, 0x5a, 0xde, 0xc2, 0x49, - 0xab, 0x4a, 0x83, 0x25, 0xa6, 0x97, 0x25, 0x0e, 0xe6, 0xd1, 0x2d, 0xd3, 0xce, 0xa5, 0xd2, 0x17, - 0x5d, 0x46, 0xc0, 0x0a, 0xe7, 0x5c, 0x10, 0x6f, 0xf2, 0xfe, 0x7f, 0x77, 0x2e, 0x4d, 0x64, 0xfa, - 0xf0, 0x1b, 0xab, 0x99, 0xde, 0x44, 0x36, 0x22, 0xe0, 0x5a, 0x45, 0x2e, 0xaa, 0x71, 0x46, 0xca, - 0x51, 0x09, 0x9a, 0x22, 0x72, 0x8f, 0xe0, 0xe3, 0xb9, 0x56, 0xe0, 0xa3, 0xf5, 0x6f, 0x7a, 0x00, - 0x1c, 0x2f, 0x9c, 0x48, 0x1b, 0x9d, 0xac, 0xd1, 0x5b, 0x33, 0x15, 0x13, 0x09, 0x8a, 0xc6, 0x30, - 0xd9, 0x7d, 0x5b, 0x74, 0x6b, 0x7b, 0x18, 0x13, 0x6f, 0x83, 0xd7, 0x93, 0xf2, 0x42, 0xe8, 0x9a, - 0xbf, 0x35, 0xb9, 0xf2, 0x55, 0x3a, 0x2f, 0x15, 0x8b, 0xf2, 0xee, 0x5c, 0x95, 0xcb, 0x92, 0x21, - 0xf5, 0x8d, 0xb5, 0xa9, 0x43, 0x0c, 0x75, 0xc7, 0x27, 0xe7, 0xc5, 0x84, 0x45, 0xf4, 0x0f, 0x04, + 0x29, 0x8c, 0xed, 0xad, 0xd9, 0x52, 0x8f, 0x7c, 0xcc, 0x50, 0xd4, 0x32, 0x1e, 0xcd, 0x55, 0xba, + 0x86, 0x43, 0x4c, 0xb7, 0x74, 0xf8, 0x4c, 0xd4, 0xf7, 0x26, 0x64, 0x0b, 0x48, 0x5a, 0xf0, 0x8d, + 0x4f, 0xff, 0x82, 0x1f, 0xac, 0x1d, 0x77, 0xee, 0x7a, 0x8b, 0xd9, 0xfc, 0x83, 0x2e, 0x8e, 0x36, + 0x6d, 0x82, 0x1f, 0x6f, 0x21, 0x36, 0x7d, 0xb5, 0x51, 0xdb, 0x18, 0x08, 0xb8, 0xe3, 0x6a, 0x71, + 0xbb, 0x36, 0x05, 0x36, 0x89, 0x3c, 0x20, 0x77, 0xed, 0x50, 0x26, 0x15, 0x90, 0x9b, 0x83, 0xcb, + 0x5f, 0x06, 0x8e, 0xf5, 0xb2, 0x0b, 0xd2, 0x58, 0x46, 0x48, 0xe4, 0x6a, 0xbf, 0xbd, 0x04, 0xde, + 0x4e, 0xe1, 0xd4, 0x38, 0x4d, 0x8f, 0x78, 0x25, 0xf4, 0x54, 0xef, 0x64, 0x8c, 0x0b, 0xad, 0x62, + 0x5a, 0x2c, 0x40, 0x92, 0xd7, 0x7c, 0x07, 0xe1, 0x0d, 0x2b, 0x6d, 0x09, 0xbb, 0x2a, 0xd1, 0x74, + 0xaf, 0x2f, 0x23, 0xa8, 0x5e, 0xb2, 0x88, 0x37, 0xc8, 0xd8, 0x24, 0xef, 0x25, 0x6b, 0xee, 0xf1, + 0x35, 0x52, 0xf6, 0xcc, 0xab, 0xf8, 0xf8, 0x5b, 0x87, 0xe7, 0x0d, 0xc7, 0x33, 0x74, 0x39, 0xa2, + 0xb9, 0x3c, 0xa4, 0xf4, 0x1a, 0xd8, 0x11, 0x99, 0x43, 0x38, 0x09, 0x9c, 0x3a, 0xd7, 0x73, 0x60, + 0xdc, 0x43, 0xe8, 0x05, 0x03, 0x2f, 0xe5, 0x1d, 0x75, 0x88, 0xa8, 0x68, 0xfb, 0xf4, 0x40, 0xb2, + 0x29, 0x43, 0x55, 0xe7, 0x84, 0x8f, 0x7a, 0x37, 0x5a, 0x8f, 0x15, 0x89, 0x1f, 0x5d, 0xd4, 0x63, + 0x78, 0x85, 0xe1, 0x1d, 0x9f, 0x08, 0x97, 0xbb, 0xf7, 0xd8, 0x65, 0xb0, 0x23, 0x4e, 0xfe, 0x54, + 0xc5, 0x99, 0x2b, 0xda, 0xfe, 0xe0, 0x23, 0x1e, 0x25, 0x91, 0x67, 0xdf, 0x19, 0x1f, 0x92, 0xdc, + 0x37, 0x3a, 0x34, 0xd4, 0x0f, 0xf0, 0x50, 0x46, 0xba, 0x78, 0xf4, 0x4a, 0xb6, 0x3a, 0x8e, 0xdf, + 0xe6, 0xf2, 0x18, 0x75, 0x3a, 0x77, 0x3c, 0x62, 0x7b, 0xf2, 0x60, 0x87, 0x8e, 0x6d, 0x59, 0x94, + 0x04, 0x20, 0xbd, 0xd8, 0xcb, 0xac, 0xfa, 0x50, 0x3a, 0x08, 0xa7, 0xd9, 0xb5, 0x93, 0x3e, 0x41, + 0xc5, 0x33, 0x01, 0xae, 0x9b, 0x4f, 0x2e, 0x00, 0x4b, 0x68, 0xa8, 0x44, 0x65, 0x5b, 0xc2, 0x69, + 0x18, 0xbb, 0x55, 0x3b, 0x66, 0x6e, 0x22, 0xc6, 0xca, 0xec, 0xb6, 0xee, 0x58, 0x17, 0x0d, 0x70, + 0x6d, 0xfd, 0xea, 0x72, 0x49, 0x47, 0x14, 0x02, 0x22, 0xea, 0x99, 0xeb, 0x41, 0x77, 0x7e, 0x7b, + 0x28, 0x3b, 0x4e, 0xe2, 0xa7, 0x31, 0x8e, 0x5c, 0x88, 0xdd, 0xc1, 0x73, 0x04, 0x31, 0xc9, 0xfa, + 0x48, 0x5f, 0x39, 0x7e, 0x47, 0x16, 0xa5, 0x46, 0x73, 0xbb, 0xec, 0x64, 0x33, 0x51, 0x10, 0x12, + 0x73, 0x54, 0xd3, 0x5f, 0x29, 0x87, 0x16, 0xd7, 0xfc, 0xfd, 0x7d, 0x93, 0x6e, 0x96, 0x76, 0xb4, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c index 188d0b52a6..d4b08c2210 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100.c @@ -43,10343 +43,10343 @@ static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_ 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b, 0x7c, 0xa5, 0x6d, 0x59, 0xeb, 0x0b, 0x38, - 0xba, 0xbb, 0xa4, 0x90, 0xa0, 0xd8, 0x10, 0xd6, 0xee, 0x20, 0x1c, 0x57, 0x52, 0x71, 0xe5, 0xd7, - 0x34, 0x17, 0x2d, 0x7c, 0x03, 0x74, 0x27, 0x65, 0x31, 0x61, 0xa5, 0x34, 0x63, 0xe2, 0x34, 0xb6, - 0x6d, 0x3f, 0xa5, 0x84, 0x69, 0xb4, 0x67, 0xc5, 0x13, 0xd0, 0x45, 0xc9, 0x1b, 0x29, 0x29, 0x0d, - 0xbe, 0x28, 0xa4, 0x5e, 0xb9, 0x07, 0x77, 0xfa, 0xd2, 0x33, 0x3f, 0xd0, 0x28, 0x8b, 0xcf, 0x90, - 0x02, 0x72, 0xc0, 0xc4, 0x79, 0xe5, 0x86, 0x93, 0xdf, 0xcb, 0xd0, 0xc3, 0x0c, 0x23, 0x2e, 0xcf, - 0x26, 0x0c, 0x72, 0x53, 0x71, 0x6e, 0xbd, 0xac, 0xd5, 0xdf, 0xeb, 0x7c, 0x78, 0x2d, 0xf9, 0x7a, - 0x48, 0x78, 0xf7, 0xc9, 0x62, 0xc5, 0xf8, 0xdc, 0x48, 0x86, 0xf0, 0x14, 0x65, 0xf6, 0x79, 0x82, - 0x4d, 0xd7, 0x68, 0x51, 0x3f, 0x5a, 0x58, 0x48, 0x28, 0x31, 0x4c, 0x47, 0xdb, 0xc8, 0x52, 0x6d, - 0xd3, 0x32, 0x0b, 0x40, 0xf9, 0x72, 0x74, 0xb7, 0xb0, 0x74, 0x1a, 0x5c, 0x09, 0x4f, 0x33, 0xe3, - 0xb8, 0xe6, 0x11, 0x8f, 0xdf, 0xa9, 0x48, 0x2f, 0x98, 0x22, 0x27, 0xe1, 0x0b, 0x50, 0x47, 0x15, - 0x6a, 0xde, 0x3d, 0x44, 0xed, 0xd9, 0x0b, 0x9f, 0x15, 0xfe, 0x0e, 0x27, 0x0d, 0x47, 0x7c, 0x22, - 0x06, 0x90, 0xa4, 0xbc, 0xd4, 0xbc, 0x51, 0xa0, 0x0c, 0xf8, 0x35, 0x47, 0x6d, 0x24, 0xdc, 0x6d, - 0xa6, 0xc7, 0xf6, 0x16, 0xb2, 0x36, 0x1d, 0x27, 0x19, 0x83, 0xfa, 0x25, 0x4f, 0x84, 0xcd, 0xb4, - 0x00, 0x1f, 0x0d, 0x5c, 0xc5, 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0x30, + 0xf2, 0xdc, 0xb2, 0x33, 0xbf, 0xc0, 0xda, 0x98, 0x7c, 0x30, 0x7c, 0x95, 0xad, 0xec, 0x27, 0x31, + 0xaa, 0x67, 0x17, 0x7e, 0x6f, 0xfb, 0x7a, 0xbb, 0xcb, 0x1d, 0xb0, 0xd5, 0x11, 0x80, 0xbc, 0xaf, + 0x4e, 0x18, 0xfc, 0x6a, 0x47, 0x45, 0x80, 0xf6, 0x2b, 0x55, 0x80, 0xeb, 0xea, 0xea, 0xda, 0x1b, + 0x11, 0x88, 0x3b, 0xc3, 0x16, 0xac, 0xa4, 0x15, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10412,9 +10412,9 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_image_storag // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_data[] = { - 0x11, 0x06, 0xc0, 0x0f, 0x68, 0xd6, 0xf8, 0x5f, 0xc4, 0xdc, 0x3d, 0x53, 0x62, 0x76, 0x9a, 0xee, - 0x68, 0xe3, 0xb4, 0xf9, 0x53, 0x5f, 0x3a, 0xb9, 0xd0, 0xa9, 0x25, 0x40, 0x2e, 0x5f, 0xc8, 0x69, - 0x3d, 0x67, 0x43, 0x03, 0xf8, 0x4f, 0x23, 0xc7, 0x73, 0xbe, 0x53, 0x31, 0xfb, 0xed, 0x4f, 0x27, + 0x76, 0x76, 0x30, 0xdb, 0x81, 0xc4, 0x73, 0x4e, 0x49, 0xd8, 0x4c, 0x5f, 0x35, 0xb2, 0x10, 0xd9, + 0xd3, 0x74, 0xb7, 0x8e, 0xd1, 0xb6, 0x7f, 0x07, 0xe2, 0xdf, 0x2c, 0xb2, 0xbf, 0xd5, 0xd3, 0xd4, + 0x3a, 0xc6, 0xee, 0xb2, 0xfc, 0x09, 0xea, 0x9d, 0x6d, 0x1c, 0xcd, 0x5b, 0x97, 0xa8, 0x19, 0x8e, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -10447,30 +10447,30 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_hash_storage // static BINDATA_CONST NvU8 kgspBinArchiveGspRmFmcGfwProdSigned_GH100_ucode_sig_data[] = { - 0x5a, 0x1a, 0x0a, 0xc7, 0x55, 0x52, 0x15, 0x22, 0xa1, 0xe9, 0xf9, 0xc7, 0x95, 0xd2, 0xb0, 0x19, - 0xaa, 0x73, 0x57, 0xe3, 0xc3, 0x13, 0x79, 0x1f, 0x5d, 0x37, 0x9f, 0x97, 0x4d, 0x85, 0x8f, 0x4b, - 0x29, 0x4c, 0x86, 0x37, 0xa2, 0x1c, 0x05, 0x98, 0x6d, 0xf8, 0x70, 0x1a, 0x0a, 0x9a, 0xc1, 0xd2, - 0x17, 0xba, 0x51, 0x99, 0x1f, 0xd8, 0x26, 0x93, 0xb6, 0x87, 0x65, 0x10, 0x7b, 0xc6, 0xc1, 0x79, - 0x37, 0x1c, 0xa4, 0x57, 0xa8, 0x06, 0xb9, 0x3f, 0xbd, 0xa9, 0xbf, 0xc6, 0xd0, 0xf2, 0xa2, 0xbf, - 0x4a, 0xb2, 0x7b, 0xfc, 0x78, 0x89, 0x20, 0x9d, 0x1e, 0xf6, 0xdf, 0x5d, 0x66, 0x12, 0x16, 0xdb, - 0x41, 0x71, 0xe0, 0x9c, 0xd4, 0xd7, 0xf1, 0x24, 0xfd, 0xbb, 0x4f, 0x39, 0x75, 0x34, 0x4e, 0x52, - 0x44, 0x5b, 0xa8, 0xa6, 0x53, 0x0b, 0x64, 0x35, 0x0a, 0xbf, 0x3c, 0xd3, 0xdf, 0x02, 0x48, 0xfa, - 0xf4, 0xae, 0x4d, 0xee, 0x50, 0xc8, 0x4a, 0x0e, 0x84, 0x63, 0x8d, 0xd8, 0x53, 0x5d, 0x64, 0x9f, - 0x3a, 0x29, 0xe9, 0x8e, 0xdc, 0xfa, 0xc2, 0x54, 0xb5, 0x67, 0xef, 0x21, 0x5d, 0xcf, 0xf9, 0x29, - 0xae, 0x9d, 0x6d, 0x92, 0xb1, 0x7d, 0x47, 0x4e, 0xe2, 0xe1, 0x5c, 0x13, 0x95, 0x4a, 0x8d, 0x41, - 0x02, 0xb4, 0xce, 0x26, 0x30, 0x95, 0x92, 0x58, 0x83, 0xff, 0x5a, 0x05, 0x88, 0x25, 0x5b, 0xc6, - 0xca, 0x26, 0xdc, 0x9b, 0x3b, 0xf7, 0x0c, 0x74, 0xd4, 0xc0, 0x8d, 0xcd, 0x33, 0xb8, 0xd0, 0x7a, - 0x3b, 0xa2, 0x3b, 0xe7, 0x72, 0xe8, 0x38, 0x42, 0x3d, 0x88, 0xa1, 0x10, 0x01, 0xae, 0xb1, 0xa0, - 0xb6, 0x86, 0x16, 0xe9, 0x35, 0xee, 0x30, 0x3d, 0x83, 0xbe, 0x1b, 0x4f, 0xae, 0xba, 0xa2, 0x82, - 0x7e, 0x85, 0xe9, 0x18, 0xe6, 0xa8, 0x43, 0xda, 0xbe, 0x56, 0x72, 0x81, 0x8c, 0x7d, 0xe5, 0xf2, - 0xf0, 0x9f, 0xdc, 0x87, 0xc5, 0x38, 0x38, 0x52, 0x9d, 0x22, 0x2d, 0x65, 0x4f, 0xee, 0xab, 0x22, - 0x96, 0xcc, 0xe8, 0xe7, 0xb7, 0xf0, 0xe9, 0x5d, 0x19, 0x62, 0x9f, 0x06, 0xbb, 0xa5, 0xcd, 0x91, - 0x8e, 0xbe, 0x04, 0x83, 0x5b, 0x85, 0x66, 0x98, 0x71, 0xed, 0xf9, 0x25, 0x5e, 0xd4, 0x5c, 0xd6, - 0x0b, 0x78, 0x40, 0x30, 0xad, 0x29, 0x0d, 0x8d, 0xb0, 0x5b, 0xf8, 0xe8, 0xb8, 0xb8, 0xdd, 0xc3, - 0xb3, 0x6c, 0xfb, 0x0d, 0xd0, 0x5f, 0x05, 0x09, 0xdf, 0x06, 0x81, 0x33, 0x61, 0xce, 0x01, 0x39, - 0x86, 0xa1, 0x1e, 0xca, 0x4b, 0x98, 0x88, 0x8d, 0xd5, 0xb5, 0x1d, 0xcd, 0x67, 0x99, 0xa1, 0x22, - 0x72, 0xd2, 0x0b, 0xed, 0x8e, 0x39, 0x09, 0x7a, 0xa6, 0x92, 0xe2, 0xf1, 0xe9, 0x0f, 0x99, 0xe0, - 0xb8, 0x93, 0x35, 0x5d, 0x98, 0x2d, 0x06, 0xa0, 0x44, 0x6b, 0xfd, 0xb4, 0x6a, 0xcc, 0x42, 0xd9, + 0x1d, 0x87, 0xee, 0x36, 0xe8, 0xa9, 0x50, 0x7b, 0x99, 0x1f, 0x8b, 0x2d, 0xae, 0x1e, 0xdc, 0xcd, + 0xaa, 0x0a, 0xc8, 0x16, 0x0d, 0x07, 0x85, 0x3f, 0xfb, 0x37, 0xbe, 0x04, 0xe9, 0x41, 0x72, 0x8c, + 0xc7, 0x6d, 0x89, 0x2e, 0xa3, 0xc2, 0xce, 0x99, 0x1c, 0xed, 0x46, 0xbc, 0xb2, 0xd4, 0x19, 0x2e, + 0x57, 0x04, 0xce, 0x31, 0x41, 0x2b, 0xbd, 0xb0, 0xb6, 0x6b, 0xad, 0x82, 0x47, 0x05, 0x9d, 0xa7, + 0xe1, 0x93, 0x1c, 0x6e, 0xa9, 0xef, 0x7b, 0x4b, 0x80, 0x33, 0xd2, 0x81, 0x7b, 0xe7, 0x7f, 0x90, + 0xdb, 0xc3, 0x1d, 0xbb, 0xa5, 0x6e, 0xf9, 0x5d, 0xbf, 0x65, 0x91, 0xa0, 0xdd, 0xe9, 0xbd, 0xc5, + 0xf9, 0x85, 0x8c, 0x61, 0x69, 0x22, 0x31, 0x0b, 0x24, 0x7e, 0x70, 0x3c, 0x97, 0xc7, 0xd4, 0xa1, + 0x82, 0xd4, 0x51, 0x74, 0x3f, 0xed, 0xb8, 0xe0, 0xb5, 0xad, 0x27, 0x90, 0x29, 0x38, 0xad, 0x3a, + 0xb9, 0x3e, 0x39, 0x2c, 0x08, 0xdd, 0xa0, 0xb9, 0x19, 0x73, 0x4b, 0x70, 0x84, 0x7e, 0x6b, 0x81, + 0x33, 0xf1, 0xeb, 0x91, 0xbd, 0x1c, 0x7d, 0xe1, 0x76, 0x9f, 0x5a, 0x66, 0x38, 0x94, 0xfa, 0xad, + 0xf2, 0x9a, 0x6b, 0xb7, 0xfd, 0x79, 0xf3, 0x53, 0xa2, 0x34, 0x3b, 0x22, 0x12, 0xc1, 0xad, 0x54, + 0xf8, 0xcc, 0x2f, 0x50, 0xf6, 0x57, 0x8e, 0xac, 0x35, 0x58, 0x21, 0xee, 0x10, 0xc7, 0x4a, 0x77, + 0x0e, 0x2a, 0xdc, 0xa7, 0x87, 0x58, 0xcc, 0x89, 0x66, 0x5e, 0x15, 0xc1, 0x93, 0x9d, 0xfa, 0x4a, + 0xb2, 0xf2, 0xba, 0x77, 0x7c, 0x98, 0x8c, 0xd4, 0xa2, 0xb8, 0xac, 0x1f, 0x29, 0x11, 0x79, 0x97, + 0x52, 0x98, 0xe6, 0xd5, 0xed, 0x9a, 0x2c, 0xf3, 0xfc, 0xcd, 0x6b, 0x1c, 0xf8, 0xff, 0xb0, 0x9a, + 0x1e, 0x4a, 0xec, 0x2b, 0x44, 0xa2, 0xac, 0xcb, 0x8c, 0xe3, 0xda, 0x9e, 0x43, 0x4e, 0xd9, 0x8e, + 0xcf, 0x94, 0x1c, 0x14, 0xe3, 0x72, 0x93, 0xda, 0x33, 0x71, 0x8c, 0xe5, 0x0b, 0x76, 0xd3, 0xcf, + 0xfe, 0x9b, 0x81, 0x15, 0x3f, 0x83, 0x44, 0x20, 0xf8, 0xe1, 0x3b, 0x98, 0x2e, 0x47, 0xe0, 0x63, + 0xc8, 0x87, 0x59, 0x91, 0x78, 0x8b, 0xe7, 0x95, 0x49, 0xcf, 0xa4, 0xf8, 0x1b, 0x0c, 0xaa, 0x6a, + 0x02, 0x83, 0xf8, 0x75, 0xfa, 0x4d, 0x5c, 0x04, 0x47, 0x7a, 0x8e, 0x8f, 0xd2, 0x32, 0x93, 0xa3, + 0x28, 0x60, 0x82, 0xd6, 0xda, 0x12, 0xeb, 0x1d, 0xec, 0xc7, 0x3c, 0x05, 0x41, 0x0c, 0xbd, 0xf7, + 0x5b, 0x5c, 0x0d, 0x7a, 0x0c, 0x28, 0xb0, 0x5f, 0xe9, 0x7e, 0xe8, 0x02, 0x7e, 0x0d, 0x74, 0xed, + 0x8a, 0xdd, 0xa3, 0x3f, 0x29, 0x25, 0xd2, 0xd9, 0x43, 0xd7, 0x3a, 0x97, 0x91, 0x60, 0x7e, 0xd0, + 0xaa, 0x7f, 0x8d, 0xef, 0x8e, 0x2d, 0x95, 0x02, 0x49, 0xd7, 0x53, 0x8f, 0xad, 0x18, 0x37, 0x3e, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c b/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c index 567195e016..db7003c227 100644 --- a/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c +++ b/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c @@ -35,401 +35,400 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 7424 -// COMPRESSED SIZE (bytes): 6242 +// COMPRESSED SIZE (bytes): 6233 // static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x80, 0xd2, 0xad, 0x71, 0x77, 0x77, 0x0b, 0xee, 0xee, 0x4e, 0xf0, - 0xe0, 0x3a, 0x83, 0x3b, 0x04, 0x77, 0x1b, 0x2c, 0xb8, 0x24, 0x24, 0xc8, 0xe0, 0xee, 0x6e, 0x01, - 0x02, 0x0c, 0xc1, 0x5d, 0x06, 0x77, 0x0b, 0xee, 0xee, 0xfa, 0xee, 0xfa, 0x6e, 0xde, 0xf2, 0x7f, - 0x55, 0xef, 0xff, 0x76, 0x67, 0xd1, 0xab, 0xee, 0x3a, 0xe7, 0x54, 0x35, 0x0c, 0xcc, 0xff, 0xdf, - 0x88, 0xd1, 0xe6, 0x8c, 0xd4, 0x06, 0x79, 0x26, 0x44, 0xba, 0xc4, 0xe8, 0xfe, 0x50, 0xb9, 0x6c, - 0x0b, 0x2d, 0xba, 0x75, 0xa3, 0xea, 0x08, 0x66, 0x3b, 0xb5, 0xec, 0x55, 0x7c, 0xcc, 0x7a, 0xea, - 0xd8, 0xef, 0x48, 0x1d, 0xfa, 0xce, 0x16, 0xd9, 0x86, 0x5a, 0x0d, 0x02, 0x3b, 0x9d, 0x31, 0xaf, - 0xb4, 0xae, 0xc8, 0x39, 0x90, 0x27, 0xf3, 0x87, 0xa1, 0xd6, 0x47, 0x49, 0x36, 0xd4, 0x90, 0x07, - 0x2c, 0x97, 0x15, 0x6a, 0x1d, 0xf7, 0x57, 0xef, 0xef, 0x9c, 0x1a, 0xcb, 0x89, 0x25, 0x11, 0x9b, - 0x39, 0x0e, 0x74, 0xec, 0xa3, 0x02, 0x2e, 0x65, 0x90, 0x44, 0xbe, 0xf4, 0xc6, 0x41, 0x67, 0x83, - 0xd5, 0xb7, 0xe9, 0xb1, 0xe5, 0x7d, 0xd0, 0x98, 0x31, 0x2c, 0x26, 0x85, 0x01, 0x24, 0xf5, 0x21, - 0x4d, 0xc6, 0xcb, 0xfa, 0x1e, 0xb4, 0x5e, 0x64, 0x70, 0x5a, 0x28, 0xa9, 0xa4, 0xed, 0x18, 0x92, - 0xdb, 0xcd, 0xa5, 0xd7, 0xb7, 0x78, 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0x75, 0x8c, 0x5c, 0x00, 0x16, 0x70, 0xed, 0x97, 0xe1, 0x52, 0x2c, + 0xbc, 0x00, 0xd7, 0x00, 0xe2, 0xf4, 0x93, 0x71, 0xae, 0xa0, 0x6b, 0x34, 0x72, 0x0d, 0xbd, 0xa6, + 0x30, 0xef, 0xff, 0xd7, 0xeb, 0xff, 0xe9, 0xff, 0xcb, 0xff, 0xf2, 0xbf, 0xfc, 0x4f, 0xf2, 0x7f, + 0x00, 0xee, 0xa3, 0xe8, 0xf7, 0x00, 0x1d, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -440,7 +439,7 @@ BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 7424, // uncompressed data size (bytes) - 6242, // compressed data size (bytes) + 6233, // compressed data size (bytes) ksec2BinArchiveSecurescrubUcode_AD10X_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -492,401 +491,400 @@ BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_header_dbg_storage_pvt // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 7424 -// COMPRESSED SIZE (bytes): 6246 +// COMPRESSED SIZE (bytes): 6233 // static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_image_prod_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x00, 0x97, 0xad, 0xf1, 0xe0, 0x04, 0x0d, 0x16, 0x34, 0x58, 0x90, - 0xe0, 0xee, 0xc1, 0x02, 0x8d, 0x36, 0xee, 0x04, 0x1a, 0x0d, 0x0e, 0xc1, 0xdd, 0xb5, 0x71, 0x77, - 0x97, 0x34, 0x8d, 0x04, 0x82, 0xbb, 0xa4, 0x71, 0x77, 0x09, 0x16, 0xdc, 0x1b, 0x0b, 0x34, 0xcc, - 0x5b, 0xff, 0x9b, 0xb7, 0x9c, 0xa9, 0x9a, 0xf9, 0x76, 0x77, 0x71, 0x57, 0xe7, 0xd4, 0x3d, 0xa7, - 0xea, 0x22, 0x21, 0xfd, 0xef, 0xc6, 0xc4, 0x86, 0xb1, 0x55, 0x43, 0x82, 0xeb, 0xcd, 0xcb, 0x8b, - 0x9c, 0x88, 0x29, 0x23, 0xe0, 0xcb, 0xd9, 0x4f, 0xc7, 0xda, 0xc9, 0xfb, 0xc1, 0xc1, 0x14, 0x8d, - 0xc4, 0x03, 0xe3, 0x0d, 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+895,7 @@ BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 7424, // uncompressed data size (bytes) - 6246, // compressed data size (bytes) + 6233, // compressed data size (bytes) ksec2BinArchiveSecurescrubUcode_AD10X_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -953,54 +951,54 @@ BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_header_prod_storage_pv // static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_data[] = { - 0xd0, 0x17, 0xc0, 0x36, 0x32, 0xbc, 0x2a, 0xbc, 0x68, 0x11, 0xa0, 0x27, 0x05, 0x9d, 0x73, 0xff, - 0x55, 0xe0, 0x63, 0x92, 0x06, 0x82, 0xbd, 0xfd, 0xc3, 0xf5, 0xcf, 0x46, 0xa8, 0xbc, 0x9f, 0xec, - 0x0c, 0x78, 0x57, 0x79, 0xbf, 0x79, 0x07, 0xa3, 0x8b, 0x27, 0x33, 0x8c, 0x71, 0x98, 0x44, 0x42, - 0x9b, 0x1b, 0xae, 0x39, 0xf4, 0x18, 0xbd, 0x9b, 0xc3, 0xb0, 0xca, 0x44, 0x22, 0xb8, 0x5a, 0x50, - 0x18, 0x27, 0x0d, 0x09, 0x44, 0xc1, 0x6d, 0xfd, 0x35, 0x11, 0xfe, 0x9f, 0xe8, 0x98, 0x37, 0xb5, - 0xb6, 0xca, 0x4c, 0xf5, 0x64, 0x05, 0x24, 0x3f, 0x7c, 0xaf, 0x4a, 0x25, 0x11, 0x3d, 0x03, 0xda, - 0x0b, 0x74, 0xef, 0x37, 0xe9, 0xf9, 0x73, 0xaa, 0xe4, 0x1f, 0xa9, 0xf5, 0x19, 0x8b, 0x29, 0xb9, - 0x38, 0x15, 0x7a, 0xac, 0xe5, 0xe1, 0x58, 0x46, 0x19, 0xfb, 0x9b, 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0x91, 0xf3, 0xa3, 0xcb, 0x05, + 0x66, 0x03, 0xd3, 0xbf, 0x5f, 0x4e, 0xe5, 0x44, 0x86, 0xac, 0x27, 0xb9, 0xe7, 0x37, 0xb0, 0x5a, + 0x1e, 0x5d, 0x69, 0x6b, 0x44, 0xc5, 0x63, 0xb7, 0x30, 0x24, 0xac, 0x88, 0x74, 0x09, 0x17, 0x03, + 0xd7, 0xf2, 0x78, 0xab, 0xa5, 0xcb, 0xf4, 0x9b, 0x7c, 0x22, 0x91, 0xeb, 0x93, 0xd6, 0x30, 0x58, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_ccsl_nvoc.h b/src/nvidia/generated/g_ccsl_nvoc.h index 0e8146facb..554cdcda42 100644 --- a/src/nvidia/generated/g_ccsl_nvoc.h +++ b/src/nvidia/generated/g_ccsl_nvoc.h @@ -47,11 +47,16 @@ extern "C" { * CCSL module header. * * * ****************************************************************************/ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CCSL_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Ccsl { const struct NVOC_RTTI *__nvoc_rtti; struct Ccsl *__nvoc_pbase_Ccsl; @@ -97,6 +102,12 @@ NV_STATUS ccslContextInitViaKeyId_KERNEL(struct ConfidentialCompute *pConfComput #define ccslContextInitViaKeyId(pConfCompute, ppCtx, globalKeyId) ccslContextInitViaKeyId_KERNEL(pConfCompute, ppCtx, globalKeyId) #define ccslContextInitViaKeyId_HAL(pConfCompute, ppCtx, globalKeyId) ccslContextInitViaKeyId(pConfCompute, ppCtx, globalKeyId) +NV_STATUS ccslContextUpdate_KERNEL(pCcslContext ctx); + + +#define ccslContextUpdate(ctx) ccslContextUpdate_KERNEL(ctx) +#define ccslContextUpdate_HAL(ctx) ccslContextUpdate(ctx) + NV_STATUS ccslRotateIv_IMPL(pCcslContext ctx, NvU8 direction); @@ -139,6 +150,12 @@ NV_STATUS ccslIncrementIv_IMPL(pCcslContext pCtx, NvU8 direction, NvU64 incremen #define ccslIncrementIv(pCtx, direction, increment, iv) ccslIncrementIv_IMPL(pCtx, direction, increment, iv) #define ccslIncrementIv_HAL(pCtx, direction, increment, iv) ccslIncrementIv(pCtx, direction, increment, iv) +NV_STATUS ccslLogDeviceEncryption_IMPL(pCcslContext pCtx, NvU32 bufferSize); + + +#define ccslLogDeviceEncryption(pCtx, bufferSize) ccslLogDeviceEncryption_IMPL(pCtx, bufferSize) +#define ccslLogDeviceEncryption_HAL(pCtx, bufferSize) ccslLogDeviceEncryption(pCtx, bufferSize) + void ccslContextClear_IMPL(pCcslContext ctx); #define ccslContextClear(ctx) ccslContextClear_IMPL(ctx) diff --git a/src/nvidia/generated/g_ce_utils_nvoc.c b/src/nvidia/generated/g_ce_utils_nvoc.c index 2396e0d51b..57aeec3f15 100644 --- a/src/nvidia/generated/g_ce_utils_nvoc.c +++ b/src/nvidia/generated/g_ce_utils_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_CeUtils(CeUtils *pThis) { __nvoc_init_funcTable_CeUtils(pThis); } -NV_STATUS __nvoc_objCreate_CeUtils(CeUtils **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams) { +NV_STATUS __nvoc_objCreate_CeUtils(CeUtils **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance, NV0050_ALLOCATION_PARAMETERS * arg_pAllocParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; CeUtils *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CeUtils), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(CeUtils)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CeUtils); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_CeUtils(CeUtils **ppThis, Dynamic *pParent, NvU32 cre status = __nvoc_ctor_CeUtils(pThis, arg_pGpu, arg_pKernelMIGGPUInstance, arg_pAllocParams); if (status != NV_OK) goto __nvoc_objCreate_CeUtils_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_CeUtils_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(CeUtils)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -164,3 +178,429 @@ NV_STATUS __nvoc_objCreateDynamic_CeUtils(CeUtils **ppThis, Dynamic *pParent, Nv return status; } +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x2eb528 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtilsApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_CeUtilsApi(CeUtilsApi*); +void __nvoc_init_funcTable_CeUtilsApi(CeUtilsApi*); +NV_STATUS __nvoc_ctor_CeUtilsApi(CeUtilsApi*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_CeUtilsApi(CeUtilsApi*); +void __nvoc_dtor_CeUtilsApi(CeUtilsApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_CeUtilsApi; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtilsApi_CeUtilsApi = { + /*pClassDef=*/ &__nvoc_class_def_CeUtilsApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_CeUtilsApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtilsApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CeUtilsApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtilsApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CeUtilsApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtilsApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CeUtilsApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtilsApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CeUtilsApi, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_CeUtilsApi_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(CeUtilsApi, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_CeUtilsApi = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_CeUtilsApi_CeUtilsApi, + &__nvoc_rtti_CeUtilsApi_GpuResource, + &__nvoc_rtti_CeUtilsApi_RmResource, + &__nvoc_rtti_CeUtilsApi_RmResourceCommon, + &__nvoc_rtti_CeUtilsApi_RsResource, + &__nvoc_rtti_CeUtilsApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtilsApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(CeUtilsApi), + /*classId=*/ classId(CeUtilsApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "CeUtilsApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_CeUtilsApi, + /*pCastInfo=*/ &__nvoc_castinfo_CeUtilsApi, + /*pExportInfo=*/ &__nvoc_export_info_CeUtilsApi +}; + +static NvBool __nvoc_thunk_GpuResource_ceutilsapiShareCallback(struct CeUtilsApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_CeUtilsApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_ceutilsapiCheckMemInterUnmap(struct CeUtilsApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_CeUtilsApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_ceutilsapiMapTo(struct CeUtilsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_ceutilsapiGetMapAddrSpace(struct CeUtilsApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_CeUtilsApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_ceutilsapiGetRefCount(struct CeUtilsApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_ceutilsapiAddAdditionalDependants(struct RsClient *pClient, struct CeUtilsApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_ceutilsapiControl_Prologue(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_ceutilsapiGetRegBaseOffsetAndSize(struct CeUtilsApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_CeUtilsApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_ceutilsapiInternalControlForward(struct CeUtilsApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_CeUtilsApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_ceutilsapiUnmapFrom(struct CeUtilsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_ceutilsapiControl_Epilogue(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RmResource.offset), pCallContext, pParams); +} + +static NvHandle __nvoc_thunk_GpuResource_ceutilsapiGetInternalObjectHandle(struct CeUtilsApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_CeUtilsApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_ceutilsapiControl(struct CeUtilsApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_CeUtilsApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_ceutilsapiUnmap(struct CeUtilsApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_CeUtilsApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_ceutilsapiGetMemInterMapParams(struct CeUtilsApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_CeUtilsApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_ceutilsapiGetMemoryMappingDescriptor(struct CeUtilsApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_CeUtilsApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_ceutilsapiControlFilter(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_ceutilsapiControlSerialization_Prologue(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_ceutilsapiCanCopy(struct CeUtilsApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset)); +} + +static NvBool __nvoc_thunk_RsResource_ceutilsapiIsPartialUnmapSupported(struct CeUtilsApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_ceutilsapiPreDestruct(struct CeUtilsApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_ceutilsapiIsDuplicate(struct CeUtilsApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_ceutilsapiControlSerialization_Epilogue(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_ceutilsapiMap(struct CeUtilsApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_CeUtilsApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_ceutilsapiAccessCallback(struct CeUtilsApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_CeUtilsApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_CeUtilsApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) ceutilsapiCtrlCmdMemset_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + /*flags=*/ 0x804u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x500101u, + /*paramSize=*/ sizeof(NV0050_CTRL_MEMSET_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_CeUtilsApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "ceutilsapiCtrlCmdMemset" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) ceutilsapiCtrlCmdMemcopy_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + /*flags=*/ 0x804u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x500102u, + /*paramSize=*/ sizeof(NV0050_CTRL_MEMCOPY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_CeUtilsApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "ceutilsapiCtrlCmdMemcopy" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) ceutilsapiCtrlCmdCheckProgress_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + /*flags=*/ 0x804u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x500103u, + /*paramSize=*/ sizeof(NV0050_CTRL_CHECK_PROGRESS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_CeUtilsApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "ceutilsapiCtrlCmdCheckProgress" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_CeUtilsApi = +{ + /*numEntries=*/ 3, + /*pExportEntries=*/ __nvoc_exported_method_def_CeUtilsApi +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_CeUtilsApi(CeUtilsApi *pThis) { + __nvoc_ceutilsapiDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_CeUtilsApi(CeUtilsApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_CeUtilsApi(CeUtilsApi *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_CeUtilsApi_fail_GpuResource; + __nvoc_init_dataField_CeUtilsApi(pThis); + + status = __nvoc_ceutilsapiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_CeUtilsApi_fail__init; + goto __nvoc_ctor_CeUtilsApi_exit; // Success + +__nvoc_ctor_CeUtilsApi_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_CeUtilsApi_fail_GpuResource: +__nvoc_ctor_CeUtilsApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_CeUtilsApi_1(CeUtilsApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + pThis->__ceutilsapiCtrlCmdMemset__ = &ceutilsapiCtrlCmdMemset_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + pThis->__ceutilsapiCtrlCmdMemcopy__ = &ceutilsapiCtrlCmdMemcopy_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x804u) + pThis->__ceutilsapiCtrlCmdCheckProgress__ = &ceutilsapiCtrlCmdCheckProgress_IMPL; +#endif + + pThis->__ceutilsapiShareCallback__ = &__nvoc_thunk_GpuResource_ceutilsapiShareCallback; + + pThis->__ceutilsapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_ceutilsapiCheckMemInterUnmap; + + pThis->__ceutilsapiMapTo__ = &__nvoc_thunk_RsResource_ceutilsapiMapTo; + + pThis->__ceutilsapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_ceutilsapiGetMapAddrSpace; + + pThis->__ceutilsapiGetRefCount__ = &__nvoc_thunk_RsResource_ceutilsapiGetRefCount; + + pThis->__ceutilsapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_ceutilsapiAddAdditionalDependants; + + pThis->__ceutilsapiControl_Prologue__ = &__nvoc_thunk_RmResource_ceutilsapiControl_Prologue; + + pThis->__ceutilsapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_ceutilsapiGetRegBaseOffsetAndSize; + + pThis->__ceutilsapiInternalControlForward__ = &__nvoc_thunk_GpuResource_ceutilsapiInternalControlForward; + + pThis->__ceutilsapiUnmapFrom__ = &__nvoc_thunk_RsResource_ceutilsapiUnmapFrom; + + pThis->__ceutilsapiControl_Epilogue__ = &__nvoc_thunk_RmResource_ceutilsapiControl_Epilogue; + + pThis->__ceutilsapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_ceutilsapiGetInternalObjectHandle; + + pThis->__ceutilsapiControl__ = &__nvoc_thunk_GpuResource_ceutilsapiControl; + + pThis->__ceutilsapiUnmap__ = &__nvoc_thunk_GpuResource_ceutilsapiUnmap; + + pThis->__ceutilsapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_ceutilsapiGetMemInterMapParams; + + pThis->__ceutilsapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_ceutilsapiGetMemoryMappingDescriptor; + + pThis->__ceutilsapiControlFilter__ = &__nvoc_thunk_RsResource_ceutilsapiControlFilter; + + pThis->__ceutilsapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_ceutilsapiControlSerialization_Prologue; + + pThis->__ceutilsapiCanCopy__ = &__nvoc_thunk_RsResource_ceutilsapiCanCopy; + + pThis->__ceutilsapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_ceutilsapiIsPartialUnmapSupported; + + pThis->__ceutilsapiPreDestruct__ = &__nvoc_thunk_RsResource_ceutilsapiPreDestruct; + + pThis->__ceutilsapiIsDuplicate__ = &__nvoc_thunk_RsResource_ceutilsapiIsDuplicate; + + pThis->__ceutilsapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_ceutilsapiControlSerialization_Epilogue; + + pThis->__ceutilsapiMap__ = &__nvoc_thunk_GpuResource_ceutilsapiMap; + + pThis->__ceutilsapiAccessCallback__ = &__nvoc_thunk_RmResource_ceutilsapiAccessCallback; +} + +void __nvoc_init_funcTable_CeUtilsApi(CeUtilsApi *pThis) { + __nvoc_init_funcTable_CeUtilsApi_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_CeUtilsApi(CeUtilsApi *pThis) { + pThis->__nvoc_pbase_CeUtilsApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_CeUtilsApi(pThis); +} + +NV_STATUS __nvoc_objCreate_CeUtilsApi(CeUtilsApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ + NV_STATUS status; + Object *pParentObj = NULL; + CeUtilsApi *pThis; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CeUtilsApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(CeUtilsApi)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CeUtilsApi); + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + // Link the child into the parent if there is one unless flagged not to do so. + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_CeUtilsApi(pThis); + status = __nvoc_ctor_CeUtilsApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_CeUtilsApi_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_CeUtilsApi_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(CeUtilsApi)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_CeUtilsApi(CeUtilsApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_CeUtilsApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_ce_utils_nvoc.h b/src/nvidia/generated/g_ce_utils_nvoc.h index f25b85c6cf..ed140f5b04 100644 --- a/src/nvidia/generated/g_ce_utils_nvoc.h +++ b/src/nvidia/generated/g_ce_utils_nvoc.h @@ -74,11 +74,16 @@ typedef struct KernelChannel KernelChannel; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CE_UTILS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct CeUtils { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -178,33 +183,238 @@ static inline void ceutilsServiceInterrupts(struct CeUtils *pCeUtils) { -#if defined(DEBUG) || defined (DEVELOP) -NVOC_PREFIX(ceutilsapi) class CeUtilsApi : GpuResource -{ -public: - NV_STATUS ceutilsapiConstruct(CeUtilsApi *pCeUtilsApi, CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams) - : GpuResource(pCallContext, pParams); - void ceutilsapiDestruct(CeUtilsApi *pCeUtilsApi); +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_CE_UTILS_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif - // - // Below APIs are only provided for SRT testing, thus only available for debug or - // develop driver builds - // - // - RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMSET, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) - NV_STATUS ceutilsapiCtrlCmdMemset(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams); +struct CeUtilsApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct CeUtilsApi *__nvoc_pbase_CeUtilsApi; + NV_STATUS (*__ceutilsapiCtrlCmdMemset__)(struct CeUtilsApi *, NV0050_CTRL_MEMSET_PARAMS *); + NV_STATUS (*__ceutilsapiCtrlCmdMemcopy__)(struct CeUtilsApi *, NV0050_CTRL_MEMCOPY_PARAMS *); + NV_STATUS (*__ceutilsapiCtrlCmdCheckProgress__)(struct CeUtilsApi *, NV0050_CTRL_CHECK_PROGRESS_PARAMS *); + NvBool (*__ceutilsapiShareCallback__)(struct CeUtilsApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__ceutilsapiCheckMemInterUnmap__)(struct CeUtilsApi *, NvBool); + NV_STATUS (*__ceutilsapiMapTo__)(struct CeUtilsApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__ceutilsapiGetMapAddrSpace__)(struct CeUtilsApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__ceutilsapiGetRefCount__)(struct CeUtilsApi *); + void (*__ceutilsapiAddAdditionalDependants__)(struct RsClient *, struct CeUtilsApi *, RsResourceRef *); + NV_STATUS (*__ceutilsapiControl_Prologue__)(struct CeUtilsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__ceutilsapiGetRegBaseOffsetAndSize__)(struct CeUtilsApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__ceutilsapiInternalControlForward__)(struct CeUtilsApi *, NvU32, void *, NvU32); + NV_STATUS (*__ceutilsapiUnmapFrom__)(struct CeUtilsApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__ceutilsapiControl_Epilogue__)(struct CeUtilsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvHandle (*__ceutilsapiGetInternalObjectHandle__)(struct CeUtilsApi *); + NV_STATUS (*__ceutilsapiControl__)(struct CeUtilsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__ceutilsapiUnmap__)(struct CeUtilsApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__ceutilsapiGetMemInterMapParams__)(struct CeUtilsApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__ceutilsapiGetMemoryMappingDescriptor__)(struct CeUtilsApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__ceutilsapiControlFilter__)(struct CeUtilsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__ceutilsapiControlSerialization_Prologue__)(struct CeUtilsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__ceutilsapiCanCopy__)(struct CeUtilsApi *); + NvBool (*__ceutilsapiIsPartialUnmapSupported__)(struct CeUtilsApi *); + void (*__ceutilsapiPreDestruct__)(struct CeUtilsApi *); + NV_STATUS (*__ceutilsapiIsDuplicate__)(struct CeUtilsApi *, NvHandle, NvBool *); + void (*__ceutilsapiControlSerialization_Epilogue__)(struct CeUtilsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__ceutilsapiMap__)(struct CeUtilsApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__ceutilsapiAccessCallback__)(struct CeUtilsApi *, struct RsClient *, void *, RsAccessRight); + struct CeUtils *pCeUtils; +}; - RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMCOPY, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) - NV_STATUS ceutilsapiCtrlCmdMemcopy(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams); +#ifndef __NVOC_CLASS_CeUtilsApi_TYPEDEF__ +#define __NVOC_CLASS_CeUtilsApi_TYPEDEF__ +typedef struct CeUtilsApi CeUtilsApi; +#endif /* __NVOC_CLASS_CeUtilsApi_TYPEDEF__ */ - RMCTRL_EXPORT(NV0050_CTRL_CMD_CHECK_PROGRESS, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) - NV_STATUS ceutilsapiCtrlCmdCheckProgress(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams); +#ifndef __nvoc_class_id_CeUtilsApi +#define __nvoc_class_id_CeUtilsApi 0x2eb528 +#endif /* __nvoc_class_id_CeUtilsApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_CeUtilsApi; + +#define __staticCast_CeUtilsApi(pThis) \ + ((pThis)->__nvoc_pbase_CeUtilsApi) + +#ifdef __nvoc_ce_utils_h_disabled +#define __dynamicCast_CeUtilsApi(pThis) ((CeUtilsApi*)NULL) +#else //__nvoc_ce_utils_h_disabled +#define __dynamicCast_CeUtilsApi(pThis) \ + ((CeUtilsApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(CeUtilsApi))) +#endif //__nvoc_ce_utils_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_CeUtilsApi(CeUtilsApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_CeUtilsApi(CeUtilsApi**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_CeUtilsApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_CeUtilsApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define ceutilsapiCtrlCmdMemset(pCeUtilsApi, pParams) ceutilsapiCtrlCmdMemset_DISPATCH(pCeUtilsApi, pParams) +#define ceutilsapiCtrlCmdMemcopy(pCeUtilsApi, pParams) ceutilsapiCtrlCmdMemcopy_DISPATCH(pCeUtilsApi, pParams) +#define ceutilsapiCtrlCmdCheckProgress(pCeUtilsApi, pParams) ceutilsapiCtrlCmdCheckProgress_DISPATCH(pCeUtilsApi, pParams) +#define ceutilsapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) ceutilsapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define ceutilsapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) ceutilsapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define ceutilsapiMapTo(pResource, pParams) ceutilsapiMapTo_DISPATCH(pResource, pParams) +#define ceutilsapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) ceutilsapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define ceutilsapiGetRefCount(pResource) ceutilsapiGetRefCount_DISPATCH(pResource) +#define ceutilsapiAddAdditionalDependants(pClient, pResource, pReference) ceutilsapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define ceutilsapiControl_Prologue(pResource, pCallContext, pParams) ceutilsapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define ceutilsapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) ceutilsapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define ceutilsapiInternalControlForward(pGpuResource, command, pParams, size) ceutilsapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define ceutilsapiUnmapFrom(pResource, pParams) ceutilsapiUnmapFrom_DISPATCH(pResource, pParams) +#define ceutilsapiControl_Epilogue(pResource, pCallContext, pParams) ceutilsapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define ceutilsapiGetInternalObjectHandle(pGpuResource) ceutilsapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define ceutilsapiControl(pGpuResource, pCallContext, pParams) ceutilsapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define ceutilsapiUnmap(pGpuResource, pCallContext, pCpuMapping) ceutilsapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define ceutilsapiGetMemInterMapParams(pRmResource, pParams) ceutilsapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define ceutilsapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) ceutilsapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define ceutilsapiControlFilter(pResource, pCallContext, pParams) ceutilsapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define ceutilsapiControlSerialization_Prologue(pResource, pCallContext, pParams) ceutilsapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define ceutilsapiCanCopy(pResource) ceutilsapiCanCopy_DISPATCH(pResource) +#define ceutilsapiIsPartialUnmapSupported(pResource) ceutilsapiIsPartialUnmapSupported_DISPATCH(pResource) +#define ceutilsapiPreDestruct(pResource) ceutilsapiPreDestruct_DISPATCH(pResource) +#define ceutilsapiIsDuplicate(pResource, hMemory, pDuplicate) ceutilsapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define ceutilsapiControlSerialization_Epilogue(pResource, pCallContext, pParams) ceutilsapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define ceutilsapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) ceutilsapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define ceutilsapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) ceutilsapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS ceutilsapiCtrlCmdMemset_IMPL(struct CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams); + +static inline NV_STATUS ceutilsapiCtrlCmdMemset_DISPATCH(struct CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams) { + return pCeUtilsApi->__ceutilsapiCtrlCmdMemset__(pCeUtilsApi, pParams); +} + +NV_STATUS ceutilsapiCtrlCmdMemcopy_IMPL(struct CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams); + +static inline NV_STATUS ceutilsapiCtrlCmdMemcopy_DISPATCH(struct CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams) { + return pCeUtilsApi->__ceutilsapiCtrlCmdMemcopy__(pCeUtilsApi, pParams); +} + +NV_STATUS ceutilsapiCtrlCmdCheckProgress_IMPL(struct CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams); + +static inline NV_STATUS ceutilsapiCtrlCmdCheckProgress_DISPATCH(struct CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams) { + return pCeUtilsApi->__ceutilsapiCtrlCmdCheckProgress__(pCeUtilsApi, pParams); +} + +static inline NvBool ceutilsapiShareCallback_DISPATCH(struct CeUtilsApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__ceutilsapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS ceutilsapiCheckMemInterUnmap_DISPATCH(struct CeUtilsApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__ceutilsapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS ceutilsapiMapTo_DISPATCH(struct CeUtilsApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__ceutilsapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS ceutilsapiGetMapAddrSpace_DISPATCH(struct CeUtilsApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__ceutilsapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 ceutilsapiGetRefCount_DISPATCH(struct CeUtilsApi *pResource) { + return pResource->__ceutilsapiGetRefCount__(pResource); +} + +static inline void ceutilsapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct CeUtilsApi *pResource, RsResourceRef *pReference) { + pResource->__ceutilsapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS ceutilsapiControl_Prologue_DISPATCH(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ceutilsapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS ceutilsapiGetRegBaseOffsetAndSize_DISPATCH(struct CeUtilsApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__ceutilsapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS ceutilsapiInternalControlForward_DISPATCH(struct CeUtilsApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__ceutilsapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS ceutilsapiUnmapFrom_DISPATCH(struct CeUtilsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__ceutilsapiUnmapFrom__(pResource, pParams); +} + +static inline void ceutilsapiControl_Epilogue_DISPATCH(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ceutilsapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NvHandle ceutilsapiGetInternalObjectHandle_DISPATCH(struct CeUtilsApi *pGpuResource) { + return pGpuResource->__ceutilsapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS ceutilsapiControl_DISPATCH(struct CeUtilsApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__ceutilsapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS ceutilsapiUnmap_DISPATCH(struct CeUtilsApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__ceutilsapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS ceutilsapiGetMemInterMapParams_DISPATCH(struct CeUtilsApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__ceutilsapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS ceutilsapiGetMemoryMappingDescriptor_DISPATCH(struct CeUtilsApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__ceutilsapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS ceutilsapiControlFilter_DISPATCH(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ceutilsapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS ceutilsapiControlSerialization_Prologue_DISPATCH(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__ceutilsapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool ceutilsapiCanCopy_DISPATCH(struct CeUtilsApi *pResource) { + return pResource->__ceutilsapiCanCopy__(pResource); +} + +static inline NvBool ceutilsapiIsPartialUnmapSupported_DISPATCH(struct CeUtilsApi *pResource) { + return pResource->__ceutilsapiIsPartialUnmapSupported__(pResource); +} + +static inline void ceutilsapiPreDestruct_DISPATCH(struct CeUtilsApi *pResource) { + pResource->__ceutilsapiPreDestruct__(pResource); +} + +static inline NV_STATUS ceutilsapiIsDuplicate_DISPATCH(struct CeUtilsApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__ceutilsapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void ceutilsapiControlSerialization_Epilogue_DISPATCH(struct CeUtilsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__ceutilsapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS ceutilsapiMap_DISPATCH(struct CeUtilsApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__ceutilsapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool ceutilsapiAccessCallback_DISPATCH(struct CeUtilsApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__ceutilsapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS ceutilsapiConstruct_IMPL(struct CeUtilsApi *arg_pCeUtilsApi, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_ceutilsapiConstruct(arg_pCeUtilsApi, arg_pCallContext, arg_pParams) ceutilsapiConstruct_IMPL(arg_pCeUtilsApi, arg_pCallContext, arg_pParams) +void ceutilsapiDestruct_IMPL(struct CeUtilsApi *pCeUtilsApi); + +#define __nvoc_ceutilsapiDestruct(pCeUtilsApi) ceutilsapiDestruct_IMPL(pCeUtilsApi) +#undef PRIVATE_FIELD - CeUtils *pCeUtils; -}; -#endif #endif // CE_UTILS_H diff --git a/src/nvidia/generated/g_channel_descendant_nvoc.c b/src/nvidia/generated/g_channel_descendant_nvoc.c index 5a4f0db14b..8f942e7ef9 100644 --- a/src/nvidia/generated/g_channel_descendant_nvoc.c +++ b/src/nvidia/generated/g_channel_descendant_nvoc.c @@ -163,10 +163,6 @@ static void __nvoc_thunk_RmResource_chandesControl_Epilogue(struct ChannelDescen rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_chandesControlLookup(struct ChannelDescendant *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_chandesGetInternalObjectHandle(struct ChannelDescendant *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ChannelDescendant_GpuResource.offset)); } @@ -203,6 +199,10 @@ static NvBool __nvoc_thunk_RsResource_chandesCanCopy(struct ChannelDescendant *p return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_chandesIsPartialUnmapSupported(struct ChannelDescendant *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_chandesPreDestruct(struct ChannelDescendant *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ChannelDescendant_RsResource.offset)); } @@ -319,8 +319,6 @@ static void __nvoc_init_funcTable_ChannelDescendant_1(ChannelDescendant *pThis, pThis->__chandesControl_Epilogue__ = &__nvoc_thunk_RmResource_chandesControl_Epilogue; - pThis->__chandesControlLookup__ = &__nvoc_thunk_RsResource_chandesControlLookup; - pThis->__chandesGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_chandesGetInternalObjectHandle; pThis->__chandesControl__ = &__nvoc_thunk_GpuResource_chandesControl; @@ -339,6 +337,8 @@ static void __nvoc_init_funcTable_ChannelDescendant_1(ChannelDescendant *pThis, pThis->__chandesCanCopy__ = &__nvoc_thunk_RsResource_chandesCanCopy; + pThis->__chandesIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_chandesIsPartialUnmapSupported; + pThis->__chandesPreDestruct__ = &__nvoc_thunk_RsResource_chandesPreDestruct; pThis->__chandesIsDuplicate__ = &__nvoc_thunk_RsResource_chandesIsDuplicate; @@ -374,23 +374,31 @@ void __nvoc_init_ChannelDescendant(ChannelDescendant *pThis, RmHalspecOwner *pRm __nvoc_init_funcTable_ChannelDescendant(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams, PARAM_TO_ENGDESC_FUNCTION * arg_pParamToEngDescFn) { +NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams, PARAM_TO_ENGDESC_FUNCTION * arg_pParamToEngDescFn) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ChannelDescendant *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ChannelDescendant), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ChannelDescendant)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ChannelDescendant); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -408,16 +416,25 @@ NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant **ppThis, Dynamic status = __nvoc_ctor_ChannelDescendant(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams, arg_pParamToEngDescFn); if (status != NV_OK) goto __nvoc_objCreate_ChannelDescendant_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ChannelDescendant_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ChannelDescendant)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_channel_descendant_nvoc.h b/src/nvidia/generated/g_channel_descendant_nvoc.h index b3a38bfe28..6fead0185f 100644 --- a/src/nvidia/generated/g_channel_descendant_nvoc.h +++ b/src/nvidia/generated/g_channel_descendant_nvoc.h @@ -105,11 +105,16 @@ typedef ENGDESCRIPTOR PARAM_TO_ENGDESC_FUNCTION(OBJGPU *pGpu, NvU32 externalClas /*! * Abstract base class for descendants of XXX_CHANNEL_DMA (Channel) */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CHANNEL_DESCENDANT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ChannelDescendant { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -137,7 +142,6 @@ struct ChannelDescendant { NV_STATUS (*__chandesInternalControlForward__)(struct ChannelDescendant *, NvU32, void *, NvU32); NV_STATUS (*__chandesUnmapFrom__)(struct ChannelDescendant *, RS_RES_UNMAP_FROM_PARAMS *); void (*__chandesControl_Epilogue__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__chandesControlLookup__)(struct ChannelDescendant *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__chandesGetInternalObjectHandle__)(struct ChannelDescendant *); NV_STATUS (*__chandesControl__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__chandesUnmap__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -147,6 +151,7 @@ struct ChannelDescendant { NV_STATUS (*__chandesUnregisterEvent__)(struct ChannelDescendant *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__chandesControlSerialization_Prologue__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__chandesCanCopy__)(struct ChannelDescendant *); + NvBool (*__chandesIsPartialUnmapSupported__)(struct ChannelDescendant *); void (*__chandesPreDestruct__)(struct ChannelDescendant *); NV_STATUS (*__chandesIsDuplicate__)(struct ChannelDescendant *, NvHandle, NvBool *); void (*__chandesControlSerialization_Epilogue__)(struct ChannelDescendant *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -204,7 +209,6 @@ NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant**, Dynamic*, NvU3 #define chandesInternalControlForward(pGpuResource, command, pParams, size) chandesInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define chandesUnmapFrom(pResource, pParams) chandesUnmapFrom_DISPATCH(pResource, pParams) #define chandesControl_Epilogue(pResource, pCallContext, pParams) chandesControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define chandesControlLookup(pResource, pParams, ppEntry) chandesControlLookup_DISPATCH(pResource, pParams, ppEntry) #define chandesGetInternalObjectHandle(pGpuResource) chandesGetInternalObjectHandle_DISPATCH(pGpuResource) #define chandesControl(pGpuResource, pCallContext, pParams) chandesControl_DISPATCH(pGpuResource, pCallContext, pParams) #define chandesUnmap(pGpuResource, pCallContext, pCpuMapping) chandesUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -214,6 +218,7 @@ NV_STATUS __nvoc_objCreate_ChannelDescendant(ChannelDescendant**, Dynamic*, NvU3 #define chandesUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) chandesUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define chandesControlSerialization_Prologue(pResource, pCallContext, pParams) chandesControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define chandesCanCopy(pResource) chandesCanCopy_DISPATCH(pResource) +#define chandesIsPartialUnmapSupported(pResource) chandesIsPartialUnmapSupported_DISPATCH(pResource) #define chandesPreDestruct(pResource) chandesPreDestruct_DISPATCH(pResource) #define chandesIsDuplicate(pResource, hMemory, pDuplicate) chandesIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define chandesControlSerialization_Epilogue(pResource, pCallContext, pParams) chandesControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -317,10 +322,6 @@ static inline void chandesControl_Epilogue_DISPATCH(struct ChannelDescendant *pR pResource->__chandesControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS chandesControlLookup_DISPATCH(struct ChannelDescendant *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__chandesControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle chandesGetInternalObjectHandle_DISPATCH(struct ChannelDescendant *pGpuResource) { return pGpuResource->__chandesGetInternalObjectHandle__(pGpuResource); } @@ -357,6 +358,10 @@ static inline NvBool chandesCanCopy_DISPATCH(struct ChannelDescendant *pResource return pResource->__chandesCanCopy__(pResource); } +static inline NvBool chandesIsPartialUnmapSupported_DISPATCH(struct ChannelDescendant *pResource) { + return pResource->__chandesIsPartialUnmapSupported__(pResource); +} + static inline void chandesPreDestruct_DISPATCH(struct ChannelDescendant *pResource) { pResource->__chandesPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_chips2halspec_nvoc.c b/src/nvidia/generated/g_chips2halspec_nvoc.c index aa5805511b..eccbf9a6b9 100644 --- a/src/nvidia/generated/g_chips2halspec_nvoc.c +++ b/src/nvidia/generated/g_chips2halspec_nvoc.c @@ -112,8 +112,13 @@ void __nvoc_init_halspec_TegraChipHal(TegraChipHal *pTegraChipHal, TEGRA_CHIP_TY void __nvoc_init_halspec_RmVariantHal(RmVariantHal *pRmVariantHal, RM_RUNTIME_VARIANT rmVariant) { + // VF + if(rmVariant == 0x1) + { + pRmVariantHal->__nvoc_HalVarIdx = 0; + } // PF_KERNEL_ONLY - if(rmVariant == 0x2) + else if(rmVariant == 0x2) { pRmVariantHal->__nvoc_HalVarIdx = 1; } diff --git a/src/nvidia/generated/g_chipset_nvoc.c b/src/nvidia/generated/g_chipset_nvoc.c index a130ace4d1..301e926504 100644 --- a/src/nvidia/generated/g_chipset_nvoc.c +++ b/src/nvidia/generated/g_chipset_nvoc.c @@ -111,21 +111,26 @@ void __nvoc_init_OBJCL(OBJCL *pThis) { __nvoc_init_funcTable_OBJCL(pThis); } -NV_STATUS __nvoc_objCreate_OBJCL(OBJCL **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJCL(OBJCL **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJCL *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJCL), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJCL)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJCL); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -140,16 +145,25 @@ NV_STATUS __nvoc_objCreate_OBJCL(OBJCL **ppThis, Dynamic *pParent, NvU32 createF status = __nvoc_ctor_OBJCL(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJCL_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJCL_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJCL)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_chipset_nvoc.h b/src/nvidia/generated/g_chipset_nvoc.h index c12d133125..1eaea35cb1 100644 --- a/src/nvidia/generated/g_chipset_nvoc.h +++ b/src/nvidia/generated/g_chipset_nvoc.h @@ -245,11 +245,16 @@ struct BUSTOPOLOGYINFO typedef struct GspSystemInfo GspSystemInfo; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CHIPSET_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJCL { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_client_nvoc.c b/src/nvidia/generated/g_client_nvoc.c index a3c457c5be..26b7f838ce 100644 --- a/src/nvidia/generated/g_client_nvoc.c +++ b/src/nvidia/generated/g_client_nvoc.c @@ -119,21 +119,26 @@ void __nvoc_init_UserInfo(UserInfo *pThis) { __nvoc_init_funcTable_UserInfo(pThis); } -NV_STATUS __nvoc_objCreate_UserInfo(UserInfo **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_UserInfo(UserInfo **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; UserInfo *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UserInfo), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(UserInfo)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UserInfo); pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -148,16 +153,25 @@ NV_STATUS __nvoc_objCreate_UserInfo(UserInfo **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_UserInfo(pThis); if (status != NV_OK) goto __nvoc_objCreate_UserInfo_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_UserInfo_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(UserInfo)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -242,8 +256,8 @@ static NV_STATUS __nvoc_thunk_RmClient_clientInterMap(struct RsClient *pClient, return rmclientInterMap((struct RmClient *)(((unsigned char *)pClient) - __nvoc_rtti_RmClient_RsClient.offset), pMapperRef, pMappableRef, pParams); } -static void __nvoc_thunk_RmClient_clientInterUnmap(struct RsClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams) { - rmclientInterUnmap((struct RmClient *)(((unsigned char *)pClient) - __nvoc_rtti_RmClient_RsClient.offset), pMapperRef, pParams); +static NV_STATUS __nvoc_thunk_RmClient_clientInterUnmap(struct RsClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams) { + return rmclientInterUnmap((struct RmClient *)(((unsigned char *)pClient) - __nvoc_rtti_RmClient_RsClient.offset), pMapperRef, pParams); } static NV_STATUS __nvoc_thunk_RmClient_clientPostProcessPendingFreeList(struct RsClient *pClient, struct RsResourceRef **ppFirstLowPriRef) { @@ -363,21 +377,26 @@ void __nvoc_init_RmClient(RmClient *pThis) { __nvoc_init_funcTable_RmClient(pThis); } -NV_STATUS __nvoc_objCreate_RmClient(RmClient **ppThis, Dynamic *pParent, NvU32 createFlags, struct PORT_MEM_ALLOCATOR * arg_pAllocator, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_RmClient(RmClient **ppThis, Dynamic *pParent, NvU32 createFlags, struct PORT_MEM_ALLOCATOR * arg_pAllocator, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RmClient *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmClient), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RmClient)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmClient); pThis->__nvoc_base_RsClient.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -392,16 +411,25 @@ NV_STATUS __nvoc_objCreate_RmClient(RmClient **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_RmClient(pThis, arg_pAllocator, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_RmClient_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RmClient_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsClient.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RmClient)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_client_nvoc.h b/src/nvidia/generated/g_client_nvoc.h index 5269682367..0340d0a1be 100644 --- a/src/nvidia/generated/g_client_nvoc.h +++ b/src/nvidia/generated/g_client_nvoc.h @@ -49,11 +49,16 @@ typedef struct _def_client_system_event_info CLI_SYSTEM_EVENT_INFO, *PCLI_SYSTEM * This ref-counted object is shared by all clients that were registered under * the same user and is used to identify clients from the same user. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CLIENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct UserInfo { const struct NVOC_RTTI *__nvoc_rtti; struct RsShared __nvoc_base_RsShared; @@ -109,11 +114,16 @@ void userinfoDestruct_IMPL(struct UserInfo *pUserInfo); #define RMAPI_CLIENT_DEBUGGER_STATE_COMPUTE_ACTIVE 0x00000001 #define RMAPI_CLIENT_DEBUGGER_STATE_DEBUG_ACTIVE 0x00000002 + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CLIENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RmClient { const struct NVOC_RTTI *__nvoc_rtti; struct RsClient __nvoc_base_RsClient; @@ -123,7 +133,7 @@ struct RmClient { NV_STATUS (*__rmclientValidate__)(struct RmClient *, const API_SECURITY_INFO *); NV_STATUS (*__rmclientFreeResource__)(struct RmClient *, struct RsServer *, struct RS_RES_FREE_PARAMS_INTERNAL *); NV_STATUS (*__rmclientInterMap__)(struct RmClient *, struct RsResourceRef *, struct RsResourceRef *, struct RS_INTER_MAP_PARAMS *); - void (*__rmclientInterUnmap__)(struct RmClient *, struct RsResourceRef *, struct RS_INTER_UNMAP_PARAMS *); + NV_STATUS (*__rmclientInterUnmap__)(struct RmClient *, struct RsResourceRef *, struct RS_INTER_UNMAP_PARAMS *); NV_STATUS (*__rmclientPostProcessPendingFreeList__)(struct RmClient *, struct RsResourceRef **); RS_PRIV_LEVEL (*__rmclientGetCachedPrivilege__)(struct RmClient *); NvBool (*__rmclientIsAdmin__)(struct RmClient *, RS_PRIV_LEVEL); @@ -206,10 +216,10 @@ static inline NV_STATUS rmclientInterMap_DISPATCH(struct RmClient *pClient, stru return pClient->__rmclientInterMap__(pClient, pMapperRef, pMappableRef, pParams); } -void rmclientInterUnmap_IMPL(struct RmClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams); +NV_STATUS rmclientInterUnmap_IMPL(struct RmClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams); -static inline void rmclientInterUnmap_DISPATCH(struct RmClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams) { - pClient->__rmclientInterUnmap__(pClient, pMapperRef, pParams); +static inline NV_STATUS rmclientInterUnmap_DISPATCH(struct RmClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams) { + return pClient->__rmclientInterUnmap__(pClient, pMapperRef, pParams); } NV_STATUS rmclientPostProcessPendingFreeList_IMPL(struct RmClient *pClient, struct RsResourceRef **ppFirstLowPriRef); diff --git a/src/nvidia/generated/g_client_resource_nvoc.c b/src/nvidia/generated/g_client_resource_nvoc.c index 2594be91b7..47478a522a 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.c +++ b/src/nvidia/generated/g_client_resource_nvoc.c @@ -158,6 +158,10 @@ static NvBool __nvoc_thunk_RsResource_cliresCanCopy(struct RmClientResource *pRe return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_cliresIsPartialUnmapSupported(struct RmClientResource *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_cliresPreDestruct(struct RmClientResource *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset)); } @@ -182,10 +186,6 @@ static struct NotifShare *__nvoc_thunk_Notifier_cliresGetNotificationShare(struc return notifyGetNotificationShare((struct Notifier *)(((unsigned char *)pNotifier) + __nvoc_rtti_RmClientResource_Notifier.offset)); } -static NV_STATUS __nvoc_thunk_RsResource_cliresControlLookup(struct RmClientResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_cliresMap(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmClientResource_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -231,21 +231,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemSetMemorySize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x107u, - /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "cliresCtrlCmdSystemSetMemorySize" -#endif - }, - { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -260,7 +245,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetClassList" #endif }, - { /* [4] */ + { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x805u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -275,7 +260,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetLockTimes" #endif }, - { /* [5] */ + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -290,7 +275,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemNotifyEvent" #endif }, - { /* [6] */ + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -305,7 +290,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetPlatformType" #endif }, - { /* [7] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -320,7 +305,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemDebugCtrlRmMsg" #endif }, - { /* [8] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -335,7 +320,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsControl" #endif }, - { /* [9] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -350,7 +335,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsBatchControl" #endif }, - { /* [10] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -365,13 +350,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetHwbcInfo" #endif }, - { /* [11] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [10] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x127u, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS), @@ -380,7 +365,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCaps" #endif }, - { /* [12] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -395,13 +380,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsCtrl" #endif }, - { /* [13] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + { /* [12] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x12bu, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS), @@ -410,7 +395,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetP2pCapsV2" #endif }, - { /* [14] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -425,7 +410,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetPerfSensorCounters" #endif }, - { /* [15] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -440,7 +425,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsCallAcpi" #endif }, - { /* [16] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -455,7 +440,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGetExtendedPerfSensorCounters" #endif }, - { /* [17] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -470,7 +455,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemGpsGetFrmData" #endif }, - { /* [18] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -485,7 +470,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSystemExecuteAcpiMethod" #endif }, - { /* [19] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -498,6 +483,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "cliresCtrlCmdSystemGpsSetFrmData" +#endif + }, + { /* [19] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetVgxSystemInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*flags=*/ 0x11u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x133u, + /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdSystemGetVgxSystemInfo" #endif }, { /* [20] */ @@ -591,12 +591,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + /*flags=*/ 0x810u, /*accessRight=*/0x0u, /*methodId=*/ 0x13au, /*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS), @@ -1161,6 +1161,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient #endif }, { /* [64] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuAsyncAttachId_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x289u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuAsyncAttachId" +#endif + }, + { /* [65] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdGpuWaitAttachId_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x290u, + /*paramSize=*/ sizeof(NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdGpuWaitAttachId" +#endif + }, + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1175,7 +1205,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetAttachedIds" #endif }, - { /* [65] */ + { /* [67] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1190,7 +1220,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGsyncGetIdInfo" #endif }, - { /* [66] */ + { /* [68] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdDiagProfileRpc_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x488u, + /*paramSize=*/ sizeof(NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdDiagProfileRpc" +#endif + }, + { /* [69] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdDiagDumpRpc_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x489u, + /*paramSize=*/ sizeof(NV0000_CTRL_DIAG_DUMP_RPC_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdDiagDumpRpc" +#endif + }, + { /* [70] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1205,7 +1265,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventSetNotification" #endif }, - { /* [67] */ + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1220,7 +1280,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdEventGetSystemEventStatus" #endif }, - { /* [68] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1235,7 +1295,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDumpSize" #endif }, - { /* [69] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1250,7 +1310,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetDump" #endif }, - { /* [70] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1265,7 +1325,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetTimestamp" #endif }, - { /* [71] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1280,7 +1340,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogInfo" #endif }, - { /* [72] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1295,7 +1355,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlogBufferInfo" #endif }, - { /* [73] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1310,7 +1370,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetNvlog" #endif }, - { /* [74] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1325,7 +1385,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdNvdGetRcerrRpt" #endif }, - { /* [75] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1340,7 +1400,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSetSubProcessID" #endif }, - { /* [76] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1355,7 +1415,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdDisableSubProcessUserdIsolation" #endif }, - { /* [77] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1370,7 +1430,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostInfo" #endif }, - { /* [78] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1385,7 +1445,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupCreate" #endif }, - { /* [79] */ + { /* [83] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1400,7 +1460,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupDestroy" #endif }, - { /* [80] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1415,7 +1475,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdSyncGpuBoostGroupInfo" #endif }, - { /* [81] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1430,7 +1490,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctSetAccountingState" #endif }, - { /* [82] */ + { /* [86] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1445,7 +1505,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingState" #endif }, - { /* [83] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1460,7 +1520,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetProcAccountingInfo" #endif }, - { /* [84] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1475,7 +1535,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctGetAccountingPids" #endif }, - { /* [85] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1490,7 +1550,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdGpuAcctClearAccountingData" #endif }, - { /* [86] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1505,7 +1565,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdVgpuGetStartData" #endif }, - { /* [87] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1520,7 +1580,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAddrSpaceType" #endif }, - { /* [88] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1535,7 +1595,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetHandleInfo" #endif }, - { /* [89] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1550,7 +1610,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetAccessRights" #endif }, - { /* [90] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1565,7 +1625,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientSetInheritedSharePolicy" #endif }, - { /* [91] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1580,7 +1640,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientGetChildHandle" #endif }, - { /* [92] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1595,7 +1655,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdClientShareObject" #endif }, - { /* [93] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1610,7 +1670,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdObjectsAreDuplicates" #endif }, - { /* [94] */ + { /* [98] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) cliresCtrlCmdClientSubscribeToImexChannel_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xd08u, + /*paramSize=*/ sizeof(NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "cliresCtrlCmdClientSubscribeToImexChannel" +#endif + }, + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1625,7 +1700,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixFlushUserCache" #endif }, - { /* [95] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1640,7 +1715,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectToFd" #endif }, - { /* [96] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1655,7 +1730,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixImportObjectFromFd" #endif }, - { /* [97] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1670,7 +1745,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixGetExportObjectInfo" #endif }, - { /* [98] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1685,7 +1760,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixCreateExportObjectFd" #endif }, - { /* [99] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1700,7 +1775,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient /*func=*/ "cliresCtrlCmdOsUnixExportObjectsToFd" #endif }, - { /* [100] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1720,7 +1795,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient const struct NVOC_EXPORT_INFO __nvoc_export_info_RmClientResource = { - /*numEntries=*/ 101, + /*numEntries=*/ 106, /*pExportEntries=*/ __nvoc_exported_method_def_RmClientResource }; @@ -1799,10 +1874,6 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetChipsetInfo__ = &cliresCtrlCmdSystemGetChipsetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - pThis->__cliresCtrlCmdSystemSetMemorySize__ = &cliresCtrlCmdSystemSetMemorySize_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x805u) pThis->__cliresCtrlCmdSystemGetLockTimes__ = &cliresCtrlCmdSystemGetLockTimes_IMPL; #endif @@ -1835,15 +1906,15 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetHwbcInfo__ = &cliresCtrlCmdSystemGetHwbcInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__cliresCtrlCmdSystemGetP2pCaps__ = &cliresCtrlCmdSystemGetP2pCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__cliresCtrlCmdSystemGetP2pCapsV2__ = &cliresCtrlCmdSystemGetP2pCapsV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__cliresCtrlCmdSystemGetP2pCapsMatrix__ = &cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL; #endif @@ -1871,6 +1942,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdSystemGetExtendedPerfSensorCounters__ = &cliresCtrlCmdSystemGetExtendedPerfSensorCounters_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + pThis->__cliresCtrlCmdSystemGetVgxSystemInfo__ = &cliresCtrlCmdSystemGetVgxSystemInfo_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) pThis->__cliresCtrlCmdSystemGetGpusPowerStatus__ = &cliresCtrlCmdSystemGetGpusPowerStatus_IMPL; #endif @@ -1951,6 +2026,10 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdObjectsAreDuplicates__ = &cliresCtrlCmdObjectsAreDuplicates_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__cliresCtrlCmdClientSubscribeToImexChannel__ = &cliresCtrlCmdClientSubscribeToImexChannel_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__cliresCtrlCmdGpuGetAttachedIds__ = &cliresCtrlCmdGpuGetAttachedIds_IMPL; #endif @@ -1983,6 +2062,14 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGpuAttachIds__ = &cliresCtrlCmdGpuAttachIds_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__cliresCtrlCmdGpuAsyncAttachId__ = &cliresCtrlCmdGpuAsyncAttachId_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__cliresCtrlCmdGpuWaitAttachId__ = &cliresCtrlCmdGpuWaitAttachId_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__cliresCtrlCmdGpuDetachIds__ = &cliresCtrlCmdGpuDetachIds_IMPL; #endif @@ -2051,6 +2138,14 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCtrlCmdGsyncGetIdInfo__ = &cliresCtrlCmdGsyncGetIdInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdDiagProfileRpc__ = &cliresCtrlCmdDiagProfileRpc_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__cliresCtrlCmdDiagDumpRpc__ = &cliresCtrlCmdDiagDumpRpc_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__cliresCtrlCmdEventSetNotification__ = &cliresCtrlCmdEventSetNotification_IMPL; #endif @@ -2211,6 +2306,8 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresCanCopy__ = &__nvoc_thunk_RsResource_cliresCanCopy; + pThis->__cliresIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_cliresIsPartialUnmapSupported; + pThis->__cliresPreDestruct__ = &__nvoc_thunk_RsResource_cliresPreDestruct; pThis->__cliresUnmapFrom__ = &__nvoc_thunk_RsResource_cliresUnmapFrom; @@ -2223,8 +2320,6 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) { pThis->__cliresGetNotificationShare__ = &__nvoc_thunk_Notifier_cliresGetNotificationShare; - pThis->__cliresControlLookup__ = &__nvoc_thunk_RsResource_cliresControlLookup; - pThis->__cliresMap__ = &__nvoc_thunk_RsResource_cliresMap; pThis->__cliresGetOrAllocNotifShare__ = &__nvoc_thunk_Notifier_cliresGetOrAllocNotifShare; @@ -2251,21 +2346,26 @@ void __nvoc_init_RmClientResource(RmClientResource *pThis) { __nvoc_init_funcTable_RmClientResource(pThis); } -NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RmClientResource *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmClientResource), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RmClientResource)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmClientResource); pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -2280,16 +2380,25 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource **ppThis, Dynamic * status = __nvoc_ctor_RmClientResource(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_RmClientResource_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RmClientResource_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsClientResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RmClientResource)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_client_resource_nvoc.h b/src/nvidia/generated/g_client_resource_nvoc.h index 469d25be55..daeb8aafc0 100644 --- a/src/nvidia/generated/g_client_resource_nvoc.h +++ b/src/nvidia/generated/g_client_resource_nvoc.h @@ -57,11 +57,16 @@ extern "C" { #include "ctrl/ctrl0000/ctrl0000unix.h" #endif + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CLIENT_RESOURCE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RmClientResource { const struct NVOC_RTTI *__nvoc_rtti; struct RsClientResource __nvoc_base_RsClientResource; @@ -83,7 +88,6 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdSystemGetBuildVersionV2__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemExecuteAcpiMethod__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetChipsetInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS *); - NV_STATUS (*__cliresCtrlCmdSystemSetMemorySize__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetLockTimes__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetClassList__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemNotifyEvent__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS *); @@ -101,6 +105,7 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdSystemGpsCallAcpi__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_CALL_ACPI_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetExtendedPerfSensorCounters__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS *); + NV_STATUS (*__cliresCtrlCmdSystemGetVgxSystemInfo__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetGpusPowerStatus__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetPrivilegedStatus__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS *); NV_STATUS (*__cliresCtrlCmdSystemGetFabricStatus__)(struct RmClientResource *, NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS *); @@ -121,6 +126,7 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdClientShareObject__)(struct RmClientResource *, NV0000_CTRL_CLIENT_SHARE_OBJECT_PARAMS *); NV_STATUS (*__cliresCtrlCmdClientGetChildHandle__)(struct RmClientResource *, NV0000_CTRL_CMD_CLIENT_GET_CHILD_HANDLE_PARAMS *); NV_STATUS (*__cliresCtrlCmdObjectsAreDuplicates__)(struct RmClientResource *, NV0000_CTRL_CLIENT_OBJECTS_ARE_DUPLICATES_PARAMS *); + NV_STATUS (*__cliresCtrlCmdClientSubscribeToImexChannel__)(struct RmClientResource *, NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetAttachedIds__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetIdInfo__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ID_INFO_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetIdInfoV2__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS *); @@ -129,6 +135,8 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdGpuGetActiveDeviceIds__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_ACTIVE_DEVICE_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetProbedIds__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuAttachIds__)(struct RmClientResource *, NV0000_CTRL_GPU_ATTACH_IDS_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuAsyncAttachId__)(struct RmClientResource *, NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS *); + NV_STATUS (*__cliresCtrlCmdGpuWaitAttachId__)(struct RmClientResource *, NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuDetachIds__)(struct RmClientResource *, NV0000_CTRL_GPU_DETACH_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetSvmSize__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS *); NV_STATUS (*__cliresCtrlCmdGpuGetPciInfo__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS *); @@ -146,6 +154,8 @@ struct RmClientResource { NV_STATUS (*__cliresCtrlCmdGpuGetVideoLinks__)(struct RmClientResource *, NV0000_CTRL_GPU_GET_VIDEO_LINKS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGsyncGetAttachedIds__)(struct RmClientResource *, NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS *); NV_STATUS (*__cliresCtrlCmdGsyncGetIdInfo__)(struct RmClientResource *, NV0000_CTRL_GSYNC_GET_ID_INFO_PARAMS *); + NV_STATUS (*__cliresCtrlCmdDiagProfileRpc__)(struct RmClientResource *, NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS *); + NV_STATUS (*__cliresCtrlCmdDiagDumpRpc__)(struct RmClientResource *, NV0000_CTRL_DIAG_DUMP_RPC_PARAMS *); NV_STATUS (*__cliresCtrlCmdEventSetNotification__)(struct RmClientResource *, NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS *); NV_STATUS (*__cliresCtrlCmdEventGetSystemEventStatus__)(struct RmClientResource *, NV0000_CTRL_GET_SYSTEM_EVENT_STATUS_PARAMS *); NV_STATUS (*__cliresCtrlCmdOsUnixExportObjectToFd__)(struct RmClientResource *, NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS *); @@ -189,13 +199,13 @@ struct RmClientResource { NV_STATUS (*__cliresUnregisterEvent__)(struct RmClientResource *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__cliresControlSerialization_Prologue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__cliresCanCopy__)(struct RmClientResource *); + NvBool (*__cliresIsPartialUnmapSupported__)(struct RmClientResource *); void (*__cliresPreDestruct__)(struct RmClientResource *); NV_STATUS (*__cliresUnmapFrom__)(struct RmClientResource *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__cliresIsDuplicate__)(struct RmClientResource *, NvHandle, NvBool *); void (*__cliresControlSerialization_Epilogue__)(struct RmClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__cliresGetNotificationListPtr__)(struct RmClientResource *); struct NotifShare *(*__cliresGetNotificationShare__)(struct RmClientResource *); - NV_STATUS (*__cliresControlLookup__)(struct RmClientResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__cliresMap__)(struct RmClientResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__cliresGetOrAllocNotifShare__)(struct RmClientResource *, NvHandle, NvHandle, struct NotifShare **); }; @@ -237,7 +247,6 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdSystemGetBuildVersionV2(pRmCliRes, pParams) cliresCtrlCmdSystemGetBuildVersionV2_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemExecuteAcpiMethod(pRmCliRes, pAcpiMethodParams) cliresCtrlCmdSystemExecuteAcpiMethod_DISPATCH(pRmCliRes, pAcpiMethodParams) #define cliresCtrlCmdSystemGetChipsetInfo(pRmCliRes, pChipsetInfo) cliresCtrlCmdSystemGetChipsetInfo_DISPATCH(pRmCliRes, pChipsetInfo) -#define cliresCtrlCmdSystemSetMemorySize(pRmCliRes, pParams) cliresCtrlCmdSystemSetMemorySize_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetLockTimes(pRmCliRes, pParams) cliresCtrlCmdSystemGetLockTimes_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetClassList(pRmCliRes, pParams) cliresCtrlCmdSystemGetClassList_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemNotifyEvent(pRmCliRes, pParams) cliresCtrlCmdSystemNotifyEvent_DISPATCH(pRmCliRes, pParams) @@ -255,6 +264,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdSystemGpsCallAcpi(pRmCliRes, pParams) cliresCtrlCmdSystemGpsCallAcpi_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemGetPerfSensorCounters_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetExtendedPerfSensorCounters(pRmCliRes, pParams) cliresCtrlCmdSystemGetExtendedPerfSensorCounters_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdSystemGetVgxSystemInfo(pRmCliRes, pParams) cliresCtrlCmdSystemGetVgxSystemInfo_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetGpusPowerStatus(pRmCliRes, pGpusPowerStatus) cliresCtrlCmdSystemGetGpusPowerStatus_DISPATCH(pRmCliRes, pGpusPowerStatus) #define cliresCtrlCmdSystemGetPrivilegedStatus(pRmCliRes, pParams) cliresCtrlCmdSystemGetPrivilegedStatus_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdSystemGetFabricStatus(pRmCliRes, pParams) cliresCtrlCmdSystemGetFabricStatus_DISPATCH(pRmCliRes, pParams) @@ -275,6 +285,7 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdClientShareObject(pRmCliRes, pParams) cliresCtrlCmdClientShareObject_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdClientGetChildHandle(pRmCliRes, pParams) cliresCtrlCmdClientGetChildHandle_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdObjectsAreDuplicates(pRmCliRes, pParams) cliresCtrlCmdObjectsAreDuplicates_DISPATCH(pRmCliRes, pParams) +#define cliresCtrlCmdClientSubscribeToImexChannel(pRmCliRes, pParams) cliresCtrlCmdClientSubscribeToImexChannel_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdGpuGetAttachedIds(pRmCliRes, pGpuAttachedIds) cliresCtrlCmdGpuGetAttachedIds_DISPATCH(pRmCliRes, pGpuAttachedIds) #define cliresCtrlCmdGpuGetIdInfo(pRmCliRes, pGpuIdInfoParams) cliresCtrlCmdGpuGetIdInfo_DISPATCH(pRmCliRes, pGpuIdInfoParams) #define cliresCtrlCmdGpuGetIdInfoV2(pRmCliRes, pGpuIdInfoParams) cliresCtrlCmdGpuGetIdInfoV2_DISPATCH(pRmCliRes, pGpuIdInfoParams) @@ -283,6 +294,8 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdGpuGetActiveDeviceIds(pRmCliRes, pActiveDeviceIdsParams) cliresCtrlCmdGpuGetActiveDeviceIds_DISPATCH(pRmCliRes, pActiveDeviceIdsParams) #define cliresCtrlCmdGpuGetProbedIds(pRmCliRes, pGpuProbedIds) cliresCtrlCmdGpuGetProbedIds_DISPATCH(pRmCliRes, pGpuProbedIds) #define cliresCtrlCmdGpuAttachIds(pRmCliRes, pGpuAttachIds) cliresCtrlCmdGpuAttachIds_DISPATCH(pRmCliRes, pGpuAttachIds) +#define cliresCtrlCmdGpuAsyncAttachId(pRmCliRes, pAsyncAttachIdParams) cliresCtrlCmdGpuAsyncAttachId_DISPATCH(pRmCliRes, pAsyncAttachIdParams) +#define cliresCtrlCmdGpuWaitAttachId(pRmCliRes, pWaitAttachIdParams) cliresCtrlCmdGpuWaitAttachId_DISPATCH(pRmCliRes, pWaitAttachIdParams) #define cliresCtrlCmdGpuDetachIds(pRmCliRes, pGpuDetachIds) cliresCtrlCmdGpuDetachIds_DISPATCH(pRmCliRes, pGpuDetachIds) #define cliresCtrlCmdGpuGetSvmSize(pRmCliRes, pSvmSizeGetParams) cliresCtrlCmdGpuGetSvmSize_DISPATCH(pRmCliRes, pSvmSizeGetParams) #define cliresCtrlCmdGpuGetPciInfo(pRmCliRes, pPciInfoParams) cliresCtrlCmdGpuGetPciInfo_DISPATCH(pRmCliRes, pPciInfoParams) @@ -300,6 +313,8 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresCtrlCmdGpuGetVideoLinks(pRmCliRes, pParams) cliresCtrlCmdGpuGetVideoLinks_DISPATCH(pRmCliRes, pParams) #define cliresCtrlCmdGsyncGetAttachedIds(pRmCliRes, pGsyncAttachedIds) cliresCtrlCmdGsyncGetAttachedIds_DISPATCH(pRmCliRes, pGsyncAttachedIds) #define cliresCtrlCmdGsyncGetIdInfo(pRmCliRes, pGsyncIdInfoParams) cliresCtrlCmdGsyncGetIdInfo_DISPATCH(pRmCliRes, pGsyncIdInfoParams) +#define cliresCtrlCmdDiagProfileRpc(pRmCliRes, pRpcProfileParams) cliresCtrlCmdDiagProfileRpc_DISPATCH(pRmCliRes, pRpcProfileParams) +#define cliresCtrlCmdDiagDumpRpc(pRmCliRes, pRpcDumpParams) cliresCtrlCmdDiagDumpRpc_DISPATCH(pRmCliRes, pRpcDumpParams) #define cliresCtrlCmdEventSetNotification(pRmCliRes, pEventSetNotificationParams) cliresCtrlCmdEventSetNotification_DISPATCH(pRmCliRes, pEventSetNotificationParams) #define cliresCtrlCmdEventGetSystemEventStatus(pRmCliRes, pSystemEventStatusParams) cliresCtrlCmdEventGetSystemEventStatus_DISPATCH(pRmCliRes, pSystemEventStatusParams) #define cliresCtrlCmdOsUnixExportObjectToFd(pRmCliRes, pParams) cliresCtrlCmdOsUnixExportObjectToFd_DISPATCH(pRmCliRes, pParams) @@ -343,13 +358,13 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32, #define cliresUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) cliresUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define cliresControlSerialization_Prologue(pResource, pCallContext, pParams) cliresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define cliresCanCopy(pResource) cliresCanCopy_DISPATCH(pResource) +#define cliresIsPartialUnmapSupported(pResource) cliresIsPartialUnmapSupported_DISPATCH(pResource) #define cliresPreDestruct(pResource) cliresPreDestruct_DISPATCH(pResource) #define cliresUnmapFrom(pResource, pParams) cliresUnmapFrom_DISPATCH(pResource, pParams) #define cliresIsDuplicate(pResource, hMemory, pDuplicate) cliresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define cliresControlSerialization_Epilogue(pResource, pCallContext, pParams) cliresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define cliresGetNotificationListPtr(pNotifier) cliresGetNotificationListPtr_DISPATCH(pNotifier) #define cliresGetNotificationShare(pNotifier) cliresGetNotificationShare_DISPATCH(pNotifier) -#define cliresControlLookup(pResource, pParams, ppEntry) cliresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define cliresMap(pResource, pCallContext, pParams, pCpuMapping) cliresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define cliresGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) cliresGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) NvBool cliresAccessCallback_IMPL(struct RmClientResource *pRmCliRes, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight); @@ -406,12 +421,6 @@ static inline NV_STATUS cliresCtrlCmdSystemGetChipsetInfo_DISPATCH(struct RmClie return pRmCliRes->__cliresCtrlCmdSystemGetChipsetInfo__(pRmCliRes, pChipsetInfo); } -NV_STATUS cliresCtrlCmdSystemSetMemorySize_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS *pParams); - -static inline NV_STATUS cliresCtrlCmdSystemSetMemorySize_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS *pParams) { - return pRmCliRes->__cliresCtrlCmdSystemSetMemorySize__(pRmCliRes, pParams); -} - NV_STATUS cliresCtrlCmdSystemGetLockTimes_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *pParams); static inline NV_STATUS cliresCtrlCmdSystemGetLockTimes_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *pParams) { @@ -514,6 +523,12 @@ static inline NV_STATUS cliresCtrlCmdSystemGetExtendedPerfSensorCounters_DISPATC return pRmCliRes->__cliresCtrlCmdSystemGetExtendedPerfSensorCounters__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdSystemGetVgxSystemInfo_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdSystemGetVgxSystemInfo_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdSystemGetVgxSystemInfo__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdSystemGetGpusPowerStatus_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS *pGpusPowerStatus); static inline NV_STATUS cliresCtrlCmdSystemGetGpusPowerStatus_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS *pGpusPowerStatus) { @@ -634,6 +649,12 @@ static inline NV_STATUS cliresCtrlCmdObjectsAreDuplicates_DISPATCH(struct RmClie return pRmCliRes->__cliresCtrlCmdObjectsAreDuplicates__(pRmCliRes, pParams); } +NV_STATUS cliresCtrlCmdClientSubscribeToImexChannel_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS *pParams); + +static inline NV_STATUS cliresCtrlCmdClientSubscribeToImexChannel_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS *pParams) { + return pRmCliRes->__cliresCtrlCmdClientSubscribeToImexChannel__(pRmCliRes, pParams); +} + NV_STATUS cliresCtrlCmdGpuGetAttachedIds_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS *pGpuAttachedIds); static inline NV_STATUS cliresCtrlCmdGpuGetAttachedIds_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS *pGpuAttachedIds) { @@ -682,6 +703,18 @@ static inline NV_STATUS cliresCtrlCmdGpuAttachIds_DISPATCH(struct RmClientResour return pRmCliRes->__cliresCtrlCmdGpuAttachIds__(pRmCliRes, pGpuAttachIds); } +NV_STATUS cliresCtrlCmdGpuAsyncAttachId_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS *pAsyncAttachIdParams); + +static inline NV_STATUS cliresCtrlCmdGpuAsyncAttachId_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS *pAsyncAttachIdParams) { + return pRmCliRes->__cliresCtrlCmdGpuAsyncAttachId__(pRmCliRes, pAsyncAttachIdParams); +} + +NV_STATUS cliresCtrlCmdGpuWaitAttachId_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS *pWaitAttachIdParams); + +static inline NV_STATUS cliresCtrlCmdGpuWaitAttachId_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS *pWaitAttachIdParams) { + return pRmCliRes->__cliresCtrlCmdGpuWaitAttachId__(pRmCliRes, pWaitAttachIdParams); +} + NV_STATUS cliresCtrlCmdGpuDetachIds_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_DETACH_IDS_PARAMS *pGpuDetachIds); static inline NV_STATUS cliresCtrlCmdGpuDetachIds_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_GPU_DETACH_IDS_PARAMS *pGpuDetachIds) { @@ -784,6 +817,18 @@ static inline NV_STATUS cliresCtrlCmdGsyncGetIdInfo_DISPATCH(struct RmClientReso return pRmCliRes->__cliresCtrlCmdGsyncGetIdInfo__(pRmCliRes, pGsyncIdInfoParams); } +NV_STATUS cliresCtrlCmdDiagProfileRpc_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS *pRpcProfileParams); + +static inline NV_STATUS cliresCtrlCmdDiagProfileRpc_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS *pRpcProfileParams) { + return pRmCliRes->__cliresCtrlCmdDiagProfileRpc__(pRmCliRes, pRpcProfileParams); +} + +NV_STATUS cliresCtrlCmdDiagDumpRpc_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_DIAG_DUMP_RPC_PARAMS *pRpcDumpParams); + +static inline NV_STATUS cliresCtrlCmdDiagDumpRpc_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_DIAG_DUMP_RPC_PARAMS *pRpcDumpParams) { + return pRmCliRes->__cliresCtrlCmdDiagDumpRpc__(pRmCliRes, pRpcDumpParams); +} + NV_STATUS cliresCtrlCmdEventSetNotification_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS *pEventSetNotificationParams); static inline NV_STATUS cliresCtrlCmdEventSetNotification_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_EVENT_SET_NOTIFICATION_PARAMS *pEventSetNotificationParams) { @@ -1022,6 +1067,10 @@ static inline NvBool cliresCanCopy_DISPATCH(struct RmClientResource *pResource) return pResource->__cliresCanCopy__(pResource); } +static inline NvBool cliresIsPartialUnmapSupported_DISPATCH(struct RmClientResource *pResource) { + return pResource->__cliresIsPartialUnmapSupported__(pResource); +} + static inline void cliresPreDestruct_DISPATCH(struct RmClientResource *pResource) { pResource->__cliresPreDestruct__(pResource); } @@ -1046,10 +1095,6 @@ static inline struct NotifShare *cliresGetNotificationShare_DISPATCH(struct RmCl return pNotifier->__cliresGetNotificationShare__(pNotifier); } -static inline NV_STATUS cliresControlLookup_DISPATCH(struct RmClientResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__cliresControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS cliresMap_DISPATCH(struct RmClientResource *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__cliresMap__(pResource, pCallContext, pParams, pCpuMapping); } @@ -1073,7 +1118,8 @@ NV_STATUS CliGetSystemP2pCaps(NvU32 *gpuIds, NvU32 *p2pOptimalReadCEs, NvU32 *p2pOptimalWriteCEs, NvU8 *p2pCapsStatus, - NvU32 *pBusPeerIds); + NvU32 *pBusPeerIds, + NvU32 *pBusEgmPeerIds); #endif diff --git a/src/nvidia/generated/g_compute_instance_subscription_nvoc.c b/src/nvidia/generated/g_compute_instance_subscription_nvoc.c index abf094f084..971b5fd35f 100644 --- a/src/nvidia/generated/g_compute_instance_subscription_nvoc.c +++ b/src/nvidia/generated/g_compute_instance_subscription_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_cisubscriptionControl_Epilogue(struct Comput rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_cisubscriptionControlLookup(struct ComputeInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle(struct ComputeInstanceSubscription *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ComputeInstanceSubscription_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RmResource_cisubscriptionControlSerialization_Prol return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_cisubscriptionIsPartialUnmapSupported(struct ComputeInstanceSubscription *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_cisubscriptionPreDestruct(struct ComputeInstanceSubscription *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ComputeInstanceSubscription_RsResource.offset)); } @@ -286,8 +286,6 @@ static void __nvoc_init_funcTable_ComputeInstanceSubscription_1(ComputeInstanceS pThis->__cisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_cisubscriptionControl_Epilogue; - pThis->__cisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_cisubscriptionControlLookup; - pThis->__cisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_cisubscriptionGetInternalObjectHandle; pThis->__cisubscriptionControl__ = &__nvoc_thunk_GpuResource_cisubscriptionControl; @@ -302,6 +300,8 @@ static void __nvoc_init_funcTable_ComputeInstanceSubscription_1(ComputeInstanceS pThis->__cisubscriptionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_cisubscriptionControlSerialization_Prologue; + pThis->__cisubscriptionIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_cisubscriptionIsPartialUnmapSupported; + pThis->__cisubscriptionPreDestruct__ = &__nvoc_thunk_RsResource_cisubscriptionPreDestruct; pThis->__cisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_cisubscriptionIsDuplicate; @@ -329,21 +329,26 @@ void __nvoc_init_ComputeInstanceSubscription(ComputeInstanceSubscription *pThis) __nvoc_init_funcTable_ComputeInstanceSubscription(pThis); } -NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscription **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscription **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ComputeInstanceSubscription *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ComputeInstanceSubscription), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ComputeInstanceSubscription)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ComputeInstanceSubscription); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -358,16 +363,25 @@ NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscripti status = __nvoc_ctor_ComputeInstanceSubscription(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ComputeInstanceSubscription_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ComputeInstanceSubscription_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ComputeInstanceSubscription)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h index bffa743f80..df20f5562f 100644 --- a/src/nvidia/generated/g_compute_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_compute_instance_subscription_nvoc.h @@ -50,11 +50,16 @@ extern "C" { // Type Definitions // **************************************************************************** + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_COMPUTE_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ComputeInstanceSubscription { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -77,7 +82,6 @@ struct ComputeInstanceSubscription { NV_STATUS (*__cisubscriptionInternalControlForward__)(struct ComputeInstanceSubscription *, NvU32, void *, NvU32); NV_STATUS (*__cisubscriptionUnmapFrom__)(struct ComputeInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); void (*__cisubscriptionControl_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__cisubscriptionControlLookup__)(struct ComputeInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__cisubscriptionGetInternalObjectHandle__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionControl__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionUnmap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -85,6 +89,7 @@ struct ComputeInstanceSubscription { NV_STATUS (*__cisubscriptionGetMemoryMappingDescriptor__)(struct ComputeInstanceSubscription *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__cisubscriptionControlFilter__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionControlSerialization_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__cisubscriptionIsPartialUnmapSupported__)(struct ComputeInstanceSubscription *); void (*__cisubscriptionPreDestruct__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionIsDuplicate__)(struct ComputeInstanceSubscription *, NvHandle, NvBool *); void (*__cisubscriptionControlSerialization_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -116,7 +121,6 @@ struct ComputeInstanceSubscription_PRIVATE { NV_STATUS (*__cisubscriptionInternalControlForward__)(struct ComputeInstanceSubscription *, NvU32, void *, NvU32); NV_STATUS (*__cisubscriptionUnmapFrom__)(struct ComputeInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); void (*__cisubscriptionControl_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__cisubscriptionControlLookup__)(struct ComputeInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__cisubscriptionGetInternalObjectHandle__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionControl__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionUnmap__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -124,6 +128,7 @@ struct ComputeInstanceSubscription_PRIVATE { NV_STATUS (*__cisubscriptionGetMemoryMappingDescriptor__)(struct ComputeInstanceSubscription *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__cisubscriptionControlFilter__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__cisubscriptionControlSerialization_Prologue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__cisubscriptionIsPartialUnmapSupported__)(struct ComputeInstanceSubscription *); void (*__cisubscriptionPreDestruct__)(struct ComputeInstanceSubscription *); NV_STATUS (*__cisubscriptionIsDuplicate__)(struct ComputeInstanceSubscription *, NvHandle, NvBool *); void (*__cisubscriptionControlSerialization_Epilogue__)(struct ComputeInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -174,7 +179,6 @@ NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscripti #define cisubscriptionInternalControlForward(pGpuResource, command, pParams, size) cisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define cisubscriptionUnmapFrom(pResource, pParams) cisubscriptionUnmapFrom_DISPATCH(pResource, pParams) #define cisubscriptionControl_Epilogue(pResource, pCallContext, pParams) cisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define cisubscriptionControlLookup(pResource, pParams, ppEntry) cisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define cisubscriptionGetInternalObjectHandle(pGpuResource) cisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) #define cisubscriptionControl(pGpuResource, pCallContext, pParams) cisubscriptionControl_DISPATCH(pGpuResource, pCallContext, pParams) #define cisubscriptionUnmap(pGpuResource, pCallContext, pCpuMapping) cisubscriptionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -182,6 +186,7 @@ NV_STATUS __nvoc_objCreate_ComputeInstanceSubscription(ComputeInstanceSubscripti #define cisubscriptionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) cisubscriptionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define cisubscriptionControlFilter(pResource, pCallContext, pParams) cisubscriptionControlFilter_DISPATCH(pResource, pCallContext, pParams) #define cisubscriptionControlSerialization_Prologue(pResource, pCallContext, pParams) cisubscriptionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define cisubscriptionIsPartialUnmapSupported(pResource) cisubscriptionIsPartialUnmapSupported_DISPATCH(pResource) #define cisubscriptionPreDestruct(pResource) cisubscriptionPreDestruct_DISPATCH(pResource) #define cisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) cisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define cisubscriptionControlSerialization_Epilogue(pResource, pCallContext, pParams) cisubscriptionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -243,10 +248,6 @@ static inline void cisubscriptionControl_Epilogue_DISPATCH(struct ComputeInstanc pResource->__cisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS cisubscriptionControlLookup_DISPATCH(struct ComputeInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__cisubscriptionControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle cisubscriptionGetInternalObjectHandle_DISPATCH(struct ComputeInstanceSubscription *pGpuResource) { return pGpuResource->__cisubscriptionGetInternalObjectHandle__(pGpuResource); } @@ -275,6 +276,10 @@ static inline NV_STATUS cisubscriptionControlSerialization_Prologue_DISPATCH(str return pResource->__cisubscriptionControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool cisubscriptionIsPartialUnmapSupported_DISPATCH(struct ComputeInstanceSubscription *pResource) { + return pResource->__cisubscriptionIsPartialUnmapSupported__(pResource); +} + static inline void cisubscriptionPreDestruct_DISPATCH(struct ComputeInstanceSubscription *pResource) { pResource->__cisubscriptionPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_conf_compute_api_nvoc.c b/src/nvidia/generated/g_conf_compute_api_nvoc.c index fabcbd929e..aaada168dd 100644 --- a/src/nvidia/generated/g_conf_compute_api_nvoc.c +++ b/src/nvidia/generated/g_conf_compute_api_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_confComputeApiAddAdditionalDependants(struct resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_confComputeApiUnmapFrom(struct ConfidentialComputeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_confComputeApiControlSerialization_Prologue(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_confComputeApiUnmap(struct Confidential return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_confComputeApiIsPartialUnmapSupported(struct ConfidentialComputeApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_confComputeApiPreDestruct(struct ConfidentialComputeApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_confComputeApiControl_Epilogue(struct Confid rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_confComputeApiControlLookup(struct ConfidentialComputeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_confComputeApiUnmapFrom(struct ConfidentialComputeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConfidentialComputeApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_confComputeApiMap(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -175,6 +175,36 @@ static NvBool __nvoc_thunk_RmResource_confComputeApiAccessCallback(struct Confid static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_ConfidentialComputeApi[] = { { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdSystemSetSecurityPolicy_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc56f010du, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdSystemSetSecurityPolicy" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) confComputeApiCtrlCmdSystemGetSecurityPolicy_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc56f010eu, + /*paramSize=*/ sizeof(NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ConfidentialComputeApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "confComputeApiCtrlCmdSystemGetSecurityPolicy" +#endif + }, + { /* [2] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -189,7 +219,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Confiden /*func=*/ "confComputeApiCtrlCmdSystemGetCapabilities" #endif }, - { /* [1] */ + { /* [3] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -204,7 +234,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Confiden /*func=*/ "confComputeApiCtrlCmdSystemGetGpusState" #endif }, - { /* [2] */ + { /* [4] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -219,7 +249,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Confiden /*func=*/ "confComputeApiCtrlCmdSystemSetGpusState" #endif }, - { /* [3] */ + { /* [5] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -234,7 +264,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Confiden /*func=*/ "confComputeApiCtrlCmdGpuGetVidmemSize" #endif }, - { /* [4] */ + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -249,7 +279,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Confiden /*func=*/ "confComputeApiCtrlCmdGpuSetVidmemSize" #endif }, - { /* [5] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -264,7 +294,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Confiden /*func=*/ "confComputeApiCtrlCmdGetGpuCertificate" #endif }, - { /* [6] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -279,7 +309,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Confiden /*func=*/ "confComputeApiCtrlCmdGetGpuAttestationReport" #endif }, - { /* [7] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -299,7 +329,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Confiden const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialComputeApi = { - /*numEntries=*/ 8, + /*numEntries=*/ 10, /*pExportEntries=*/ __nvoc_exported_method_def_ConfidentialComputeApi }; @@ -368,6 +398,14 @@ static void __nvoc_init_funcTable_ConfidentialComputeApi_1(ConfidentialComputeAp pThis->__confComputeApiCtrlCmdGpuGetNumSecureChannels__ = &confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__confComputeApiCtrlCmdSystemGetSecurityPolicy__ = &confComputeApiCtrlCmdSystemGetSecurityPolicy_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__confComputeApiCtrlCmdSystemSetSecurityPolicy__ = &confComputeApiCtrlCmdSystemSetSecurityPolicy_IMPL; +#endif + pThis->__confComputeApiShareCallback__ = &__nvoc_thunk_RmResource_confComputeApiShareCallback; pThis->__confComputeApiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_confComputeApiCheckMemInterUnmap; @@ -384,8 +422,6 @@ static void __nvoc_init_funcTable_ConfidentialComputeApi_1(ConfidentialComputeAp pThis->__confComputeApiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_confComputeApiAddAdditionalDependants; - pThis->__confComputeApiUnmapFrom__ = &__nvoc_thunk_RsResource_confComputeApiUnmapFrom; - pThis->__confComputeApiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_confComputeApiControlSerialization_Prologue; pThis->__confComputeApiControl_Prologue__ = &__nvoc_thunk_RmResource_confComputeApiControl_Prologue; @@ -394,6 +430,8 @@ static void __nvoc_init_funcTable_ConfidentialComputeApi_1(ConfidentialComputeAp pThis->__confComputeApiUnmap__ = &__nvoc_thunk_RsResource_confComputeApiUnmap; + pThis->__confComputeApiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_confComputeApiIsPartialUnmapSupported; + pThis->__confComputeApiPreDestruct__ = &__nvoc_thunk_RsResource_confComputeApiPreDestruct; pThis->__confComputeApiMapTo__ = &__nvoc_thunk_RsResource_confComputeApiMapTo; @@ -404,7 +442,7 @@ static void __nvoc_init_funcTable_ConfidentialComputeApi_1(ConfidentialComputeAp pThis->__confComputeApiControl_Epilogue__ = &__nvoc_thunk_RmResource_confComputeApiControl_Epilogue; - pThis->__confComputeApiControlLookup__ = &__nvoc_thunk_RsResource_confComputeApiControlLookup; + pThis->__confComputeApiUnmapFrom__ = &__nvoc_thunk_RsResource_confComputeApiUnmapFrom; pThis->__confComputeApiMap__ = &__nvoc_thunk_RsResource_confComputeApiMap; @@ -426,21 +464,26 @@ void __nvoc_init_ConfidentialComputeApi(ConfidentialComputeApi *pThis) { __nvoc_init_funcTable_ConfidentialComputeApi(pThis); } -NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ConfidentialComputeApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConfidentialComputeApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ConfidentialComputeApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConfidentialComputeApi); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -455,16 +498,25 @@ NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi **ppThi status = __nvoc_ctor_ConfidentialComputeApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ConfidentialComputeApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ConfidentialComputeApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ConfidentialComputeApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_conf_compute_api_nvoc.h b/src/nvidia/generated/g_conf_compute_api_nvoc.h index 560c8bd49a..193819b588 100644 --- a/src/nvidia/generated/g_conf_compute_api_nvoc.h +++ b/src/nvidia/generated/g_conf_compute_api_nvoc.h @@ -37,6 +37,7 @@ extern "C" { #include "gpu/gpu.h" #include "rmapi/resource.h" #include "ctrl/ctrlcb33.h" +#include "ctrl/ctrlc56f.h" #include "gpu_mgr/gpu_mgr.h" #include "gpu/conf_compute/conf_compute.h" @@ -47,11 +48,16 @@ extern "C" { * * ****************************************************************************/ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CONF_COMPUTE_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ConfidentialComputeApi { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -68,6 +74,8 @@ struct ConfidentialComputeApi { NV_STATUS (*__confComputeApiCtrlCmdGetGpuCertificate__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_CERTIFICATE_PARAMS *); NV_STATUS (*__confComputeApiCtrlCmdGetGpuAttestationReport__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GET_GPU_ATTESTATION_REPORT_PARAMS *); NV_STATUS (*__confComputeApiCtrlCmdGpuGetNumSecureChannels__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdSystemGetSecurityPolicy__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS *); + NV_STATUS (*__confComputeApiCtrlCmdSystemSetSecurityPolicy__)(struct ConfidentialComputeApi *, NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS *); NvBool (*__confComputeApiShareCallback__)(struct ConfidentialComputeApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__confComputeApiCheckMemInterUnmap__)(struct ConfidentialComputeApi *, NvBool); NV_STATUS (*__confComputeApiControl__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -76,17 +84,17 @@ struct ConfidentialComputeApi { NvU32 (*__confComputeApiGetRefCount__)(struct ConfidentialComputeApi *); NV_STATUS (*__confComputeApiControlFilter__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__confComputeApiAddAdditionalDependants__)(struct RsClient *, struct ConfidentialComputeApi *, RsResourceRef *); - NV_STATUS (*__confComputeApiUnmapFrom__)(struct ConfidentialComputeApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__confComputeApiControlSerialization_Prologue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__confComputeApiControl_Prologue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__confComputeApiCanCopy__)(struct ConfidentialComputeApi *); NV_STATUS (*__confComputeApiUnmap__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__confComputeApiIsPartialUnmapSupported__)(struct ConfidentialComputeApi *); void (*__confComputeApiPreDestruct__)(struct ConfidentialComputeApi *); NV_STATUS (*__confComputeApiMapTo__)(struct ConfidentialComputeApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__confComputeApiIsDuplicate__)(struct ConfidentialComputeApi *, NvHandle, NvBool *); void (*__confComputeApiControlSerialization_Epilogue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__confComputeApiControl_Epilogue__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__confComputeApiControlLookup__)(struct ConfidentialComputeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__confComputeApiUnmapFrom__)(struct ConfidentialComputeApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__confComputeApiMap__)(struct ConfidentialComputeApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__confComputeApiAccessCallback__)(struct ConfidentialComputeApi *, struct RsClient *, void *, RsAccessRight); struct CONF_COMPUTE_CAPS *pCcCaps; @@ -128,6 +136,8 @@ NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi**, Dyna #define confComputeApiCtrlCmdGetGpuCertificate(pConfComputeApi, pParams) confComputeApiCtrlCmdGetGpuCertificate_DISPATCH(pConfComputeApi, pParams) #define confComputeApiCtrlCmdGetGpuAttestationReport(pConfComputeApi, pParams) confComputeApiCtrlCmdGetGpuAttestationReport_DISPATCH(pConfComputeApi, pParams) #define confComputeApiCtrlCmdGpuGetNumSecureChannels(pConfComputeApi, pParams) confComputeApiCtrlCmdGpuGetNumSecureChannels_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdSystemGetSecurityPolicy(pConfComputeApi, pParams) confComputeApiCtrlCmdSystemGetSecurityPolicy_DISPATCH(pConfComputeApi, pParams) +#define confComputeApiCtrlCmdSystemSetSecurityPolicy(pConfComputeApi, pParams) confComputeApiCtrlCmdSystemSetSecurityPolicy_DISPATCH(pConfComputeApi, pParams) #define confComputeApiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) confComputeApiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define confComputeApiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) confComputeApiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define confComputeApiControl(pResource, pCallContext, pParams) confComputeApiControl_DISPATCH(pResource, pCallContext, pParams) @@ -136,17 +146,17 @@ NV_STATUS __nvoc_objCreate_ConfidentialComputeApi(ConfidentialComputeApi**, Dyna #define confComputeApiGetRefCount(pResource) confComputeApiGetRefCount_DISPATCH(pResource) #define confComputeApiControlFilter(pResource, pCallContext, pParams) confComputeApiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define confComputeApiAddAdditionalDependants(pClient, pResource, pReference) confComputeApiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define confComputeApiUnmapFrom(pResource, pParams) confComputeApiUnmapFrom_DISPATCH(pResource, pParams) #define confComputeApiControlSerialization_Prologue(pResource, pCallContext, pParams) confComputeApiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define confComputeApiControl_Prologue(pResource, pCallContext, pParams) confComputeApiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define confComputeApiCanCopy(pResource) confComputeApiCanCopy_DISPATCH(pResource) #define confComputeApiUnmap(pResource, pCallContext, pCpuMapping) confComputeApiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define confComputeApiIsPartialUnmapSupported(pResource) confComputeApiIsPartialUnmapSupported_DISPATCH(pResource) #define confComputeApiPreDestruct(pResource) confComputeApiPreDestruct_DISPATCH(pResource) #define confComputeApiMapTo(pResource, pParams) confComputeApiMapTo_DISPATCH(pResource, pParams) #define confComputeApiIsDuplicate(pResource, hMemory, pDuplicate) confComputeApiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define confComputeApiControlSerialization_Epilogue(pResource, pCallContext, pParams) confComputeApiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define confComputeApiControl_Epilogue(pResource, pCallContext, pParams) confComputeApiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define confComputeApiControlLookup(pResource, pParams, ppEntry) confComputeApiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define confComputeApiUnmapFrom(pResource, pParams) confComputeApiUnmapFrom_DISPATCH(pResource, pParams) #define confComputeApiMap(pResource, pCallContext, pParams, pCpuMapping) confComputeApiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define confComputeApiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) confComputeApiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS confComputeApiCtrlCmdSystemGetCapabilities_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS *pParams); @@ -197,6 +207,18 @@ static inline NV_STATUS confComputeApiCtrlCmdGpuGetNumSecureChannels_DISPATCH(st return pConfComputeApi->__confComputeApiCtrlCmdGpuGetNumSecureChannels__(pConfComputeApi, pParams); } +NV_STATUS confComputeApiCtrlCmdSystemGetSecurityPolicy_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdSystemGetSecurityPolicy_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdSystemGetSecurityPolicy__(pConfComputeApi, pParams); +} + +NV_STATUS confComputeApiCtrlCmdSystemSetSecurityPolicy_IMPL(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS *pParams); + +static inline NV_STATUS confComputeApiCtrlCmdSystemSetSecurityPolicy_DISPATCH(struct ConfidentialComputeApi *pConfComputeApi, NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS *pParams) { + return pConfComputeApi->__confComputeApiCtrlCmdSystemSetSecurityPolicy__(pConfComputeApi, pParams); +} + static inline NvBool confComputeApiShareCallback_DISPATCH(struct ConfidentialComputeApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pResource->__confComputeApiShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -229,10 +251,6 @@ static inline void confComputeApiAddAdditionalDependants_DISPATCH(struct RsClien pResource->__confComputeApiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS confComputeApiUnmapFrom_DISPATCH(struct ConfidentialComputeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__confComputeApiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS confComputeApiControlSerialization_Prologue_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__confComputeApiControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -249,6 +267,10 @@ static inline NV_STATUS confComputeApiUnmap_DISPATCH(struct ConfidentialComputeA return pResource->__confComputeApiUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool confComputeApiIsPartialUnmapSupported_DISPATCH(struct ConfidentialComputeApi *pResource) { + return pResource->__confComputeApiIsPartialUnmapSupported__(pResource); +} + static inline void confComputeApiPreDestruct_DISPATCH(struct ConfidentialComputeApi *pResource) { pResource->__confComputeApiPreDestruct__(pResource); } @@ -269,8 +291,8 @@ static inline void confComputeApiControl_Epilogue_DISPATCH(struct ConfidentialCo pResource->__confComputeApiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS confComputeApiControlLookup_DISPATCH(struct ConfidentialComputeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__confComputeApiControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS confComputeApiUnmapFrom_DISPATCH(struct ConfidentialComputeApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__confComputeApiUnmapFrom__(pResource, pParams); } static inline NV_STATUS confComputeApiMap_DISPATCH(struct ConfidentialComputeApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_conf_compute_nvoc.c b/src/nvidia/generated/g_conf_compute_nvoc.c index 0dfdaf1067..d1edb3b1ce 100644 --- a/src/nvidia/generated/g_conf_compute_nvoc.c +++ b/src/nvidia/generated/g_conf_compute_nvoc.c @@ -86,10 +86,6 @@ static NV_STATUS __nvoc_thunk_ConfidentialCompute_engstateStatePreUnload(struct return confComputeStatePreUnload(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_ConfidentialCompute_engstateStateDestroy(struct OBJGPU *pGpu, struct OBJENGSTATE *pConfCompute) { - confComputeStateDestroy(pGpu, (struct ConfidentialCompute *)(((unsigned char *)pConfCompute) - __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStateLoad(POBJGPU pGpu, struct ConfidentialCompute *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); } @@ -106,6 +102,10 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStatePostUnload(POBJGPU pGp return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset), arg0); } +static void __nvoc_thunk_OBJENGSTATE_confComputeStateDestroy(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + engstateStateDestroy(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); +} + static NV_STATUS __nvoc_thunk_OBJENGSTATE_confComputeStateInitUnlocked(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { return engstateStateInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_ConfidentialCompute_OBJENGSTATE.offset)); } @@ -130,6 +130,7 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_ConfidentialCompute = void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); void __nvoc_dtor_ConfidentialCompute(ConfidentialCompute *pThis) { + __nvoc_confComputeDestruct(pThis); __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -145,6 +146,16 @@ void __nvoc_init_dataField_ConfidentialCompute(ConfidentialCompute *pThis, RmHal PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + // NVOC Property Hal field -- PDB_PROP_CONFCOMPUTE_IS_MISSING + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_IS_MISSING, ((NvBool)(0 == 0))); + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_IS_MISSING, ((NvBool)(0 != 0))); + } pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENABLED, ((NvBool)(0 != 0))); pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED, ((NvBool)(0 != 0))); pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED, ((NvBool)(0 != 0))); @@ -152,8 +163,7 @@ void __nvoc_init_dataField_ConfidentialCompute(ConfidentialCompute *pThis, RmHal pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT, ((NvBool)(0 != 0))); pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED, ((NvBool)(0 == 0))); pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, ((NvBool)(0 != 0))); - pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY, ((NvBool)(0 != 0))); - pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED, ((NvBool)(0 != 0))); + pThis->setProperty(pThis, PDB_PROP_CONFCOMPUTE_MULTI_GPU_PROTECTED_PCIE_MODE_ENABLED, ((NvBool)(0 != 0))); } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -184,19 +194,54 @@ static void __nvoc_init_funcTable_ConfidentialCompute_1(ConfidentialCompute *pTh pThis->__confComputeConstructEngine__ = &confComputeConstructEngine_IMPL; + // Hal function -- confComputeDestruct + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__confComputeDestruct__ = &confComputeDestruct_KERNEL; + } + // default + else + { + pThis->__confComputeDestruct__ = &confComputeDestruct_b3696a; + } + // Hal function -- confComputeStatePreInitLocked - pThis->__confComputeStatePreInitLocked__ = &confComputeStatePreInitLocked_IMPL; + pThis->__confComputeStatePreInitLocked__ = &confComputeStatePreInitLocked_56cd7a; pThis->__confComputeStateInitLocked__ = &confComputeStateInitLocked_IMPL; // Hal function -- confComputeStatePostLoad - pThis->__confComputeStatePostLoad__ = &confComputeStatePostLoad_IMPL; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__confComputeStatePostLoad__ = &confComputeStatePostLoad_IMPL; + } + // default + else + { + pThis->__confComputeStatePostLoad__ = &confComputeStatePostLoad_56cd7a; + } // Hal function -- confComputeStatePreUnload - pThis->__confComputeStatePreUnload__ = &confComputeStatePreUnload_56cd7a; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__confComputeStatePreUnload__ = &confComputeStatePreUnload_KERNEL; + } + // default + else + { + pThis->__confComputeStatePreUnload__ = &confComputeStatePreUnload_56cd7a; + } - // Hal function -- confComputeStateDestroy - pThis->__confComputeStateDestroy__ = &confComputeStateDestroy_IMPL; + // Hal function -- confComputeSetErrorState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__confComputeSetErrorState__ = &confComputeSetErrorState_KERNEL; + } + // default + else + { + pThis->__confComputeSetErrorState__ = &confComputeSetErrorState_b3696a; + } // Hal function -- confComputeKeyStoreRetrieveViaChannel if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ @@ -264,6 +309,17 @@ static void __nvoc_init_funcTable_ConfidentialCompute_1(ConfidentialCompute *pTh pThis->__confComputeIsGpuCcCapable__ = &confComputeIsGpuCcCapable_491d52; } + // Hal function -- confComputeEstablishSpdmSessionAndKeys + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__confComputeEstablishSpdmSessionAndKeys__ = &confComputeEstablishSpdmSessionAndKeys_KERNEL; + } + // default + else + { + pThis->__confComputeEstablishSpdmSessionAndKeys__ = &confComputeEstablishSpdmSessionAndKeys_46f6a7; + } + // Hal function -- confComputeKeyStoreDepositIvMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -351,8 +407,6 @@ static void __nvoc_init_funcTable_ConfidentialCompute_1(ConfidentialCompute *pTh pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_ConfidentialCompute_engstateStatePreUnload; - pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_ConfidentialCompute_engstateStateDestroy; - pThis->__confComputeStateLoad__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateLoad; pThis->__confComputeStateUnload__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateUnload; @@ -361,6 +415,8 @@ static void __nvoc_init_funcTable_ConfidentialCompute_1(ConfidentialCompute *pTh pThis->__confComputeStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_confComputeStatePostUnload; + pThis->__confComputeStateDestroy__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateDestroy; + pThis->__confComputeStateInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_confComputeStateInitUnlocked; pThis->__confComputeInitMissing__ = &__nvoc_thunk_OBJENGSTATE_confComputeInitMissing; @@ -383,23 +439,31 @@ void __nvoc_init_ConfidentialCompute(ConfidentialCompute *pThis, RmHalspecOwner __nvoc_init_funcTable_ConfidentialCompute(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ConfidentialCompute *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConfidentialCompute), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ConfidentialCompute)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConfidentialCompute); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -417,16 +481,25 @@ NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute **ppThis, Dyn status = __nvoc_ctor_ConfidentialCompute(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_ConfidentialCompute_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ConfidentialCompute_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ConfidentialCompute)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_conf_compute_nvoc.h b/src/nvidia/generated/g_conf_compute_nvoc.h index a5de3246f8..9d0f70fcf2 100644 --- a/src/nvidia/generated/g_conf_compute_nvoc.h +++ b/src/nvidia/generated/g_conf_compute_nvoc.h @@ -44,6 +44,7 @@ extern "C" { #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/intr/engine_idx.h" #include "kernel/gpu/conf_compute/ccsl_context.h" +#include "objtmr.h" /****************************************************************************\ * * @@ -51,11 +52,16 @@ extern "C" { * * ****************************************************************************/ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CONF_COMPUTE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ConfidentialCompute { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -63,17 +69,19 @@ struct ConfidentialCompute { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct ConfidentialCompute *__nvoc_pbase_ConfidentialCompute; NV_STATUS (*__confComputeConstructEngine__)(struct OBJGPU *, struct ConfidentialCompute *, ENGDESCRIPTOR); + void (*__confComputeDestruct__)(struct ConfidentialCompute *); NV_STATUS (*__confComputeStatePreInitLocked__)(struct OBJGPU *, struct ConfidentialCompute *); NV_STATUS (*__confComputeStateInitLocked__)(struct OBJGPU *, struct ConfidentialCompute *); NV_STATUS (*__confComputeStatePostLoad__)(struct OBJGPU *, struct ConfidentialCompute *, NvU32); NV_STATUS (*__confComputeStatePreUnload__)(struct OBJGPU *, struct ConfidentialCompute *, NvU32); - void (*__confComputeStateDestroy__)(struct OBJGPU *, struct ConfidentialCompute *); + void (*__confComputeSetErrorState__)(struct OBJGPU *, struct ConfidentialCompute *); NV_STATUS (*__confComputeKeyStoreRetrieveViaChannel__)(struct ConfidentialCompute *, struct KernelChannel *, ROTATE_IV_TYPE, NvBool, CC_KMB *); NV_STATUS (*__confComputeKeyStoreRetrieveViaKeyId__)(struct ConfidentialCompute *, NvU32, ROTATE_IV_TYPE, NvBool, CC_KMB *); NV_STATUS (*__confComputeDeriveSecrets__)(struct ConfidentialCompute *, NvU32); NvBool (*__confComputeIsSpdmEnabled__)(struct OBJGPU *, struct ConfidentialCompute *); NvBool (*__confComputeIsDebugModeEnabled__)(struct OBJGPU *, struct ConfidentialCompute *); NvBool (*__confComputeIsGpuCcCapable__)(struct OBJGPU *, struct ConfidentialCompute *); + NV_STATUS (*__confComputeEstablishSpdmSessionAndKeys__)(struct OBJGPU *, struct ConfidentialCompute *); void (*__confComputeKeyStoreDepositIvMask__)(struct ConfidentialCompute *, NvU32, void *); NV_STATUS (*__confComputeKeyStoreInit__)(struct ConfidentialCompute *); void (*__confComputeKeyStoreDeinit__)(struct ConfidentialCompute *); @@ -85,6 +93,7 @@ struct ConfidentialCompute { NV_STATUS (*__confComputeStateUnload__)(POBJGPU, struct ConfidentialCompute *, NvU32); NV_STATUS (*__confComputeStatePreLoad__)(POBJGPU, struct ConfidentialCompute *, NvU32); NV_STATUS (*__confComputeStatePostUnload__)(POBJGPU, struct ConfidentialCompute *, NvU32); + void (*__confComputeStateDestroy__)(POBJGPU, struct ConfidentialCompute *); NV_STATUS (*__confComputeStateInitUnlocked__)(POBJGPU, struct ConfidentialCompute *); void (*__confComputeInitMissing__)(POBJGPU, struct ConfidentialCompute *); NV_STATUS (*__confComputeStatePreInitUnlocked__)(POBJGPU, struct ConfidentialCompute *); @@ -96,8 +105,7 @@ struct ConfidentialCompute { NvBool PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT; NvBool PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED; NvBool PDB_PROP_CONFCOMPUTE_SPDM_ENABLED; - NvBool PDB_PROP_CONFCOMPUTE_ENCRYPT_READY; - NvBool PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED; + NvBool PDB_PROP_CONFCOMPUTE_MULTI_GPU_PROTECTED_PCIE_MODE_ENABLED; NvU32 gspProxyRegkeys; struct Spdm *pSpdm; NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS ccStaticInfo; @@ -105,7 +113,9 @@ struct ConfidentialCompute { struct ccslContext_t *pDmaCcslCtx; struct ccslContext_t *pNonReplayableFaultCcslCtx; struct ccslContext_t *pReplayableFaultCcslCtx; - PORT_SPINLOCK *pAesEngineLock; + NvBool bAcceptClientRequest; + PTMR_EVENT pGspHeartbeatTimer; + NvU32 heartbeatPeriodSec; NvU8 PRIVATE_FIELD(m_exportMasterKey)[32]; void *PRIVATE_FIELD(m_keySlot); }; @@ -131,22 +141,20 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_ConfidentialCompute; ((ConfidentialCompute*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ConfidentialCompute))) #endif //__nvoc_conf_compute_h_disabled -#define PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED_BASE_CAST -#define PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED #define PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED_BASE_CAST #define PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_APM_FEATURE_ENABLED #define PDB_PROP_CONFCOMPUTE_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. #define PDB_PROP_CONFCOMPUTE_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING #define PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT_BASE_CAST #define PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT_BASE_NAME PDB_PROP_CONFCOMPUTE_ENABLE_EARLY_INIT -#define PDB_PROP_CONFCOMPUTE_ENCRYPT_READY_BASE_CAST -#define PDB_PROP_CONFCOMPUTE_ENCRYPT_READY_BASE_NAME PDB_PROP_CONFCOMPUTE_ENCRYPT_READY #define PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED_BASE_CAST #define PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_GPUS_READY_CHECK_ENABLED #define PDB_PROP_CONFCOMPUTE_ENABLED_BASE_CAST #define PDB_PROP_CONFCOMPUTE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_ENABLED #define PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED_BASE_CAST #define PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED +#define PDB_PROP_CONFCOMPUTE_MULTI_GPU_PROTECTED_PCIE_MODE_ENABLED_BASE_CAST +#define PDB_PROP_CONFCOMPUTE_MULTI_GPU_PROTECTED_PCIE_MODE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_MULTI_GPU_PROTECTED_PCIE_MODE_ENABLED #define PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED_BASE_CAST #define PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED_BASE_NAME PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED #define PDB_PROP_CONFCOMPUTE_SPDM_ENABLED_BASE_CAST @@ -159,6 +167,7 @@ NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute**, Dynamic*, __nvoc_objCreate_ConfidentialCompute((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define confComputeConstructEngine(pGpu, pConfCompute, engDesc) confComputeConstructEngine_DISPATCH(pGpu, pConfCompute, engDesc) +#define __nvoc_confComputeDestruct(pConfCompute) confComputeDestruct_DISPATCH(pConfCompute) #define confComputeStatePreInitLocked(pGpu, pConfCompute) confComputeStatePreInitLocked_DISPATCH(pGpu, pConfCompute) #define confComputeStatePreInitLocked_HAL(pGpu, pConfCompute) confComputeStatePreInitLocked_DISPATCH(pGpu, pConfCompute) #define confComputeStateInitLocked(pGpu, pConfCompute) confComputeStateInitLocked_DISPATCH(pGpu, pConfCompute) @@ -166,8 +175,8 @@ NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute**, Dynamic*, #define confComputeStatePostLoad_HAL(pGpu, pConfCompute, flags) confComputeStatePostLoad_DISPATCH(pGpu, pConfCompute, flags) #define confComputeStatePreUnload(pGpu, pConfCompute, flags) confComputeStatePreUnload_DISPATCH(pGpu, pConfCompute, flags) #define confComputeStatePreUnload_HAL(pGpu, pConfCompute, flags) confComputeStatePreUnload_DISPATCH(pGpu, pConfCompute, flags) -#define confComputeStateDestroy(pGpu, pConfCompute) confComputeStateDestroy_DISPATCH(pGpu, pConfCompute) -#define confComputeStateDestroy_HAL(pGpu, pConfCompute) confComputeStateDestroy_DISPATCH(pGpu, pConfCompute) +#define confComputeSetErrorState(pGpu, pConfCompute) confComputeSetErrorState_DISPATCH(pGpu, pConfCompute) +#define confComputeSetErrorState_HAL(pGpu, pConfCompute) confComputeSetErrorState_DISPATCH(pGpu, pConfCompute) #define confComputeKeyStoreRetrieveViaChannel(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaChannel_DISPATCH(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) #define confComputeKeyStoreRetrieveViaChannel_HAL(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaChannel_DISPATCH(pConfCompute, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) #define confComputeKeyStoreRetrieveViaKeyId(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) confComputeKeyStoreRetrieveViaKeyId_DISPATCH(pConfCompute, globalKeyId, rotateOperation, includeSecrets, keyMaterialBundle) @@ -180,6 +189,8 @@ NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute**, Dynamic*, #define confComputeIsDebugModeEnabled_HAL(pGpu, pConfCompute) confComputeIsDebugModeEnabled_DISPATCH(pGpu, pConfCompute) #define confComputeIsGpuCcCapable(pGpu, pConfCompute) confComputeIsGpuCcCapable_DISPATCH(pGpu, pConfCompute) #define confComputeIsGpuCcCapable_HAL(pGpu, pConfCompute) confComputeIsGpuCcCapable_DISPATCH(pGpu, pConfCompute) +#define confComputeEstablishSpdmSessionAndKeys(pGpu, pConfCompute) confComputeEstablishSpdmSessionAndKeys_DISPATCH(pGpu, pConfCompute) +#define confComputeEstablishSpdmSessionAndKeys_HAL(pGpu, pConfCompute) confComputeEstablishSpdmSessionAndKeys_DISPATCH(pGpu, pConfCompute) #define confComputeKeyStoreDepositIvMask(pConfCompute, globalKeyId, ivMask) confComputeKeyStoreDepositIvMask_DISPATCH(pConfCompute, globalKeyId, ivMask) #define confComputeKeyStoreDepositIvMask_HAL(pConfCompute, globalKeyId, ivMask) confComputeKeyStoreDepositIvMask_DISPATCH(pConfCompute, globalKeyId, ivMask) #define confComputeKeyStoreInit(pConfCompute) confComputeKeyStoreInit_DISPATCH(pConfCompute) @@ -198,6 +209,7 @@ NV_STATUS __nvoc_objCreate_ConfidentialCompute(ConfidentialCompute**, Dynamic*, #define confComputeStateUnload(pGpu, pEngstate, arg0) confComputeStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define confComputeStatePreLoad(pGpu, pEngstate, arg0) confComputeStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define confComputeStatePostUnload(pGpu, pEngstate, arg0) confComputeStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) +#define confComputeStateDestroy(pGpu, pEngstate) confComputeStateDestroy_DISPATCH(pGpu, pEngstate) #define confComputeStateInitUnlocked(pGpu, pEngstate) confComputeStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define confComputeInitMissing(pGpu, pEngstate) confComputeInitMissing_DISPATCH(pGpu, pEngstate) #define confComputeStatePreInitUnlocked(pGpu, pEngstate) confComputeStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) @@ -218,56 +230,26 @@ static inline NV_STATUS confComputeEarlyInit(struct OBJGPU *pGpu, struct Confide #define confComputeEarlyInit_HAL(pGpu, pConfCompute) confComputeEarlyInit(pGpu, pConfCompute) -NV_STATUS confComputeStartEncryption_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); - +NV_STATUS confComputeConstructEngine_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc); -#ifdef __nvoc_conf_compute_h_disabled -static inline NV_STATUS confComputeStartEncryption(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { - NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS confComputeConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc) { + return pConfCompute->__confComputeConstructEngine__(pGpu, pConfCompute, engDesc); } -#else //__nvoc_conf_compute_h_disabled -#define confComputeStartEncryption(pGpu, pConfCompute) confComputeStartEncryption_KERNEL(pGpu, pConfCompute) -#endif //__nvoc_conf_compute_h_disabled - -#define confComputeStartEncryption_HAL(pGpu, pConfCompute) confComputeStartEncryption(pGpu, pConfCompute) - -NV_STATUS confComputeStopEncryption_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); +void confComputeDestruct_KERNEL(struct ConfidentialCompute *pConfCompute); -#ifdef __nvoc_conf_compute_h_disabled -static inline NV_STATUS confComputeStopEncryption(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { - NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline void confComputeDestruct_b3696a(struct ConfidentialCompute *pConfCompute) { + return; } -#else //__nvoc_conf_compute_h_disabled -#define confComputeStopEncryption(pGpu, pConfCompute) confComputeStopEncryption_KERNEL(pGpu, pConfCompute) -#endif //__nvoc_conf_compute_h_disabled - -#define confComputeStopEncryption_HAL(pGpu, pConfCompute) confComputeStopEncryption(pGpu, pConfCompute) -NV_STATUS confComputeEstablishSpdmSessionAndKeys_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); - - -#ifdef __nvoc_conf_compute_h_disabled -static inline NV_STATUS confComputeEstablishSpdmSessionAndKeys(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { - NV_ASSERT_FAILED_PRECOMP("ConfidentialCompute was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline void confComputeDestruct_DISPATCH(struct ConfidentialCompute *pConfCompute) { + pConfCompute->__confComputeDestruct__(pConfCompute); } -#else //__nvoc_conf_compute_h_disabled -#define confComputeEstablishSpdmSessionAndKeys(pGpu, pConfCompute) confComputeEstablishSpdmSessionAndKeys_KERNEL(pGpu, pConfCompute) -#endif //__nvoc_conf_compute_h_disabled -#define confComputeEstablishSpdmSessionAndKeys_HAL(pGpu, pConfCompute) confComputeEstablishSpdmSessionAndKeys(pGpu, pConfCompute) - -NV_STATUS confComputeConstructEngine_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc); - -static inline NV_STATUS confComputeConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc) { - return pConfCompute->__confComputeConstructEngine__(pGpu, pConfCompute, engDesc); +static inline NV_STATUS confComputeStatePreInitLocked_56cd7a(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return NV_OK; } -NV_STATUS confComputeStatePreInitLocked_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); - static inline NV_STATUS confComputeStatePreInitLocked_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { return pConfCompute->__confComputeStatePreInitLocked__(pGpu, pConfCompute); } @@ -280,10 +262,16 @@ static inline NV_STATUS confComputeStateInitLocked_DISPATCH(struct OBJGPU *pGpu, NV_STATUS confComputeStatePostLoad_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags); +static inline NV_STATUS confComputeStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags) { + return NV_OK; +} + static inline NV_STATUS confComputeStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags) { return pConfCompute->__confComputeStatePostLoad__(pGpu, pConfCompute, flags); } +NV_STATUS confComputeStatePreUnload_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags); + static inline NV_STATUS confComputeStatePreUnload_56cd7a(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute, NvU32 flags) { return NV_OK; } @@ -292,10 +280,14 @@ static inline NV_STATUS confComputeStatePreUnload_DISPATCH(struct OBJGPU *pGpu, return pConfCompute->__confComputeStatePreUnload__(pGpu, pConfCompute, flags); } -void confComputeStateDestroy_IMPL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); +void confComputeSetErrorState_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); -static inline void confComputeStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { - pConfCompute->__confComputeStateDestroy__(pGpu, pConfCompute); +static inline void confComputeSetErrorState_b3696a(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return; +} + +static inline void confComputeSetErrorState_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + pConfCompute->__confComputeSetErrorState__(pGpu, pConfCompute); } NV_STATUS confComputeKeyStoreRetrieveViaChannel_GH100(struct ConfidentialCompute *pConfCompute, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); @@ -360,6 +352,16 @@ static inline NvBool confComputeIsGpuCcCapable_DISPATCH(struct OBJGPU *pGpu, str return pConfCompute->__confComputeIsGpuCcCapable__(pGpu, pConfCompute); } +NV_STATUS confComputeEstablishSpdmSessionAndKeys_KERNEL(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute); + +static inline NV_STATUS confComputeEstablishSpdmSessionAndKeys_46f6a7(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS confComputeEstablishSpdmSessionAndKeys_DISPATCH(struct OBJGPU *pGpu, struct ConfidentialCompute *pConfCompute) { + return pConfCompute->__confComputeEstablishSpdmSessionAndKeys__(pGpu, pConfCompute); +} + void confComputeKeyStoreDepositIvMask_GH100(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask); static inline void confComputeKeyStoreDepositIvMask_b3696a(struct ConfidentialCompute *pConfCompute, NvU32 globalKeyId, void *ivMask) { @@ -446,6 +448,10 @@ static inline NV_STATUS confComputeStatePostUnload_DISPATCH(POBJGPU pGpu, struct return pEngstate->__confComputeStatePostUnload__(pGpu, pEngstate, arg0); } +static inline void confComputeStateDestroy_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { + pEngstate->__confComputeStateDestroy__(pGpu, pEngstate); +} + static inline NV_STATUS confComputeStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct ConfidentialCompute *pEngstate) { return pEngstate->__confComputeStateInitUnlocked__(pGpu, pEngstate); } diff --git a/src/nvidia/generated/g_console_mem_nvoc.c b/src/nvidia/generated/g_console_mem_nvoc.c index 6a38d1988c..c5ae52f2d5 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.c +++ b/src/nvidia/generated/g_console_mem_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_conmemControl_Epilogue(struct ConsoleMemory rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_conmemControlLookup(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_conmemControl(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_conmemControlSerialization_Prologue(str return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_conmemIsPartialUnmapSupported(struct ConsoleMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ConsoleMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_conmemIsReady(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ConsoleMemory_Memory.offset), bCopyConstructorContext); } @@ -261,8 +261,6 @@ static void __nvoc_init_funcTable_ConsoleMemory_1(ConsoleMemory *pThis) { pThis->__conmemControl_Epilogue__ = &__nvoc_thunk_RmResource_conmemControl_Epilogue; - pThis->__conmemControlLookup__ = &__nvoc_thunk_RsResource_conmemControlLookup; - pThis->__conmemControl__ = &__nvoc_thunk_Memory_conmemControl; pThis->__conmemUnmap__ = &__nvoc_thunk_Memory_conmemUnmap; @@ -275,6 +273,8 @@ static void __nvoc_init_funcTable_ConsoleMemory_1(ConsoleMemory *pThis) { pThis->__conmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_conmemControlSerialization_Prologue; + pThis->__conmemIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_conmemIsPartialUnmapSupported; + pThis->__conmemIsReady__ = &__nvoc_thunk_Memory_conmemIsReady; pThis->__conmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_conmemCheckCopyPermissions; @@ -306,21 +306,26 @@ void __nvoc_init_ConsoleMemory(ConsoleMemory *pThis) { __nvoc_init_funcTable_ConsoleMemory(pThis); } -NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ConsoleMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ConsoleMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ConsoleMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ConsoleMemory); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -335,16 +340,25 @@ NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory **ppThis, Dynamic *pParen status = __nvoc_ctor_ConsoleMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ConsoleMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ConsoleMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ConsoleMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_console_mem_nvoc.h b/src/nvidia/generated/g_console_mem_nvoc.h index d24312b218..e03dd0de81 100644 --- a/src/nvidia/generated/g_console_mem_nvoc.h +++ b/src/nvidia/generated/g_console_mem_nvoc.h @@ -39,11 +39,16 @@ extern "C" { /*! * This class is used to create hMemory referencing reserved console memory */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CONSOLE_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ConsoleMemory { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -65,13 +70,13 @@ struct ConsoleMemory { NvBool (*__conmemIsGpuMapAllowed__)(struct ConsoleMemory *, struct OBJGPU *); NV_STATUS (*__conmemUnmapFrom__)(struct ConsoleMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__conmemControl_Epilogue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__conmemControlLookup__)(struct ConsoleMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__conmemControl__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemUnmap__)(struct ConsoleMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__conmemGetMemInterMapParams__)(struct ConsoleMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__conmemGetMemoryMappingDescriptor__)(struct ConsoleMemory *, MEMORY_DESCRIPTOR **); NV_STATUS (*__conmemControlFilter__)(struct ConsoleMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__conmemControlSerialization_Prologue__)(struct ConsoleMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__conmemIsPartialUnmapSupported__)(struct ConsoleMemory *); NV_STATUS (*__conmemIsReady__)(struct ConsoleMemory *, NvBool); NV_STATUS (*__conmemCheckCopyPermissions__)(struct ConsoleMemory *, struct OBJGPU *, struct Device *); void (*__conmemPreDestruct__)(struct ConsoleMemory *); @@ -121,13 +126,13 @@ NV_STATUS __nvoc_objCreate_ConsoleMemory(ConsoleMemory**, Dynamic*, NvU32, CALL_ #define conmemIsGpuMapAllowed(pMemory, pGpu) conmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define conmemUnmapFrom(pResource, pParams) conmemUnmapFrom_DISPATCH(pResource, pParams) #define conmemControl_Epilogue(pResource, pCallContext, pParams) conmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define conmemControlLookup(pResource, pParams, ppEntry) conmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define conmemControl(pMemory, pCallContext, pParams) conmemControl_DISPATCH(pMemory, pCallContext, pParams) #define conmemUnmap(pMemory, pCallContext, pCpuMapping) conmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define conmemGetMemInterMapParams(pMemory, pParams) conmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define conmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) conmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define conmemControlFilter(pResource, pCallContext, pParams) conmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define conmemControlSerialization_Prologue(pResource, pCallContext, pParams) conmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define conmemIsPartialUnmapSupported(pResource) conmemIsPartialUnmapSupported_DISPATCH(pResource) #define conmemIsReady(pMemory, bCopyConstructorContext) conmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define conmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) conmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define conmemPreDestruct(pResource) conmemPreDestruct_DISPATCH(pResource) @@ -185,10 +190,6 @@ static inline void conmemControl_Epilogue_DISPATCH(struct ConsoleMemory *pResour pResource->__conmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS conmemControlLookup_DISPATCH(struct ConsoleMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__conmemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS conmemControl_DISPATCH(struct ConsoleMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__conmemControl__(pMemory, pCallContext, pParams); } @@ -213,6 +214,10 @@ static inline NV_STATUS conmemControlSerialization_Prologue_DISPATCH(struct Cons return pResource->__conmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool conmemIsPartialUnmapSupported_DISPATCH(struct ConsoleMemory *pResource) { + return pResource->__conmemIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS conmemIsReady_DISPATCH(struct ConsoleMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__conmemIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_context_dma_nvoc.c b/src/nvidia/generated/g_context_dma_nvoc.c index 6645d6ef53..f8bd10d394 100644 --- a/src/nvidia/generated/g_context_dma_nvoc.c +++ b/src/nvidia/generated/g_context_dma_nvoc.c @@ -142,10 +142,6 @@ static void __nvoc_thunk_RmResource_ctxdmaControl_Epilogue(struct ContextDma *pR rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControlLookup(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_ctxdmaControl(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset), pCallContext, pParams); } @@ -178,6 +174,10 @@ static NvBool __nvoc_thunk_RsResource_ctxdmaCanCopy(struct ContextDma *pResource return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_ctxdmaIsPartialUnmapSupported(struct ContextDma *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_ctxdmaPreDestruct(struct ContextDma *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ContextDma_RsResource.offset)); } @@ -346,8 +346,6 @@ static void __nvoc_init_funcTable_ContextDma_1(ContextDma *pThis) { pThis->__ctxdmaControl_Epilogue__ = &__nvoc_thunk_RmResource_ctxdmaControl_Epilogue; - pThis->__ctxdmaControlLookup__ = &__nvoc_thunk_RsResource_ctxdmaControlLookup; - pThis->__ctxdmaControl__ = &__nvoc_thunk_RsResource_ctxdmaControl; pThis->__ctxdmaUnmap__ = &__nvoc_thunk_RsResource_ctxdmaUnmap; @@ -364,6 +362,8 @@ static void __nvoc_init_funcTable_ContextDma_1(ContextDma *pThis) { pThis->__ctxdmaCanCopy__ = &__nvoc_thunk_RsResource_ctxdmaCanCopy; + pThis->__ctxdmaIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_ctxdmaIsPartialUnmapSupported; + pThis->__ctxdmaPreDestruct__ = &__nvoc_thunk_RsResource_ctxdmaPreDestruct; pThis->__ctxdmaIsDuplicate__ = &__nvoc_thunk_RsResource_ctxdmaIsDuplicate; @@ -398,21 +398,26 @@ void __nvoc_init_ContextDma(ContextDma *pThis) { __nvoc_init_funcTable_ContextDma(pThis); } -NV_STATUS __nvoc_objCreate_ContextDma(ContextDma **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ContextDma(ContextDma **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ContextDma *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ContextDma), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ContextDma)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ContextDma); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -427,16 +432,25 @@ NV_STATUS __nvoc_objCreate_ContextDma(ContextDma **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_ContextDma(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ContextDma_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ContextDma_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ContextDma)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_context_dma_nvoc.h b/src/nvidia/generated/g_context_dma_nvoc.h index 56232ee02a..02184472fc 100644 --- a/src/nvidia/generated/g_context_dma_nvoc.h +++ b/src/nvidia/generated/g_context_dma_nvoc.h @@ -70,11 +70,16 @@ typedef struct Memory Memory; /*! * RM internal class representing NV01_CONTEXT_DMA */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CONTEXT_DMA_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ContextDma { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -101,7 +106,6 @@ struct ContextDma { void (*__ctxdmaAddAdditionalDependants__)(struct RsClient *, struct ContextDma *, RsResourceRef *); NV_STATUS (*__ctxdmaControl_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__ctxdmaControl_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__ctxdmaControlLookup__)(struct ContextDma *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__ctxdmaControl__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ctxdmaUnmap__)(struct ContextDma *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__ctxdmaGetMemInterMapParams__)(struct ContextDma *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -110,6 +114,7 @@ struct ContextDma { NV_STATUS (*__ctxdmaUnregisterEvent__)(struct ContextDma *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__ctxdmaControlSerialization_Prologue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ctxdmaCanCopy__)(struct ContextDma *); + NvBool (*__ctxdmaIsPartialUnmapSupported__)(struct ContextDma *); void (*__ctxdmaPreDestruct__)(struct ContextDma *); NV_STATUS (*__ctxdmaIsDuplicate__)(struct ContextDma *, NvHandle, NvBool *); void (*__ctxdmaControlSerialization_Epilogue__)(struct ContextDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -180,7 +185,6 @@ NV_STATUS __nvoc_objCreate_ContextDma(ContextDma**, Dynamic*, NvU32, struct CALL #define ctxdmaAddAdditionalDependants(pClient, pResource, pReference) ctxdmaAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define ctxdmaControl_Prologue(pResource, pCallContext, pParams) ctxdmaControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaControl_Epilogue(pResource, pCallContext, pParams) ctxdmaControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define ctxdmaControlLookup(pResource, pParams, ppEntry) ctxdmaControlLookup_DISPATCH(pResource, pParams, ppEntry) #define ctxdmaControl(pResource, pCallContext, pParams) ctxdmaControl_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaUnmap(pResource, pCallContext, pCpuMapping) ctxdmaUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define ctxdmaGetMemInterMapParams(pRmResource, pParams) ctxdmaGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -189,6 +193,7 @@ NV_STATUS __nvoc_objCreate_ContextDma(ContextDma**, Dynamic*, NvU32, struct CALL #define ctxdmaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ctxdmaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define ctxdmaControlSerialization_Prologue(pResource, pCallContext, pParams) ctxdmaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ctxdmaCanCopy(pResource) ctxdmaCanCopy_DISPATCH(pResource) +#define ctxdmaIsPartialUnmapSupported(pResource) ctxdmaIsPartialUnmapSupported_DISPATCH(pResource) #define ctxdmaPreDestruct(pResource) ctxdmaPreDestruct_DISPATCH(pResource) #define ctxdmaIsDuplicate(pResource, hMemory, pDuplicate) ctxdmaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define ctxdmaControlSerialization_Epilogue(pResource, pCallContext, pParams) ctxdmaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -270,10 +275,6 @@ static inline void ctxdmaControl_Epilogue_DISPATCH(struct ContextDma *pResource, pResource->__ctxdmaControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS ctxdmaControlLookup_DISPATCH(struct ContextDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__ctxdmaControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS ctxdmaControl_DISPATCH(struct ContextDma *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__ctxdmaControl__(pResource, pCallContext, pParams); } @@ -306,6 +307,10 @@ static inline NvBool ctxdmaCanCopy_DISPATCH(struct ContextDma *pResource) { return pResource->__ctxdmaCanCopy__(pResource); } +static inline NvBool ctxdmaIsPartialUnmapSupported_DISPATCH(struct ContextDma *pResource) { + return pResource->__ctxdmaIsPartialUnmapSupported__(pResource); +} + static inline void ctxdmaPreDestruct_DISPATCH(struct ContextDma *pResource) { pResource->__ctxdmaPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_crashcat_engine_nvoc.h b/src/nvidia/generated/g_crashcat_engine_nvoc.h index d866da5afc..08839cb449 100644 --- a/src/nvidia/generated/g_crashcat_engine_nvoc.h +++ b/src/nvidia/generated/g_crashcat_engine_nvoc.h @@ -79,11 +79,16 @@ MAKE_INTRUSIVE_MAP(CrashCatRegisteredBufferMap, CrashCatBufferDescriptor, regist MAKE_INTRUSIVE_MAP(CrashCatMappedBufferMap, CrashCatBufferDescriptor, mappedBufferMapNode); // Base class for engine-specific accessors - must be implemented by the host codebase. + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct CrashCatEngine { const struct NVOC_RTTI *__nvoc_rtti; struct CrashCatEngine *__nvoc_pbase_CrashCatEngine; diff --git a/src/nvidia/generated/g_crashcat_queue_nvoc.c b/src/nvidia/generated/g_crashcat_queue_nvoc.c index 848502c2d8..1506e2d957 100644 --- a/src/nvidia/generated/g_crashcat_queue_nvoc.c +++ b/src/nvidia/generated/g_crashcat_queue_nvoc.c @@ -119,23 +119,31 @@ void __nvoc_init_CrashCatQueue(CrashCatQueue *pThis, CrashCatWayfinder *pCrashca __nvoc_init_funcTable_CrashCatQueue(pThis, pCrashcatWayfinder); } -NV_STATUS __nvoc_objCreate_CrashCatQueue(CrashCatQueue **ppThis, Dynamic *pParent, NvU32 createFlags, CrashCatQueueConfig * arg_pQueueConfig) { +NV_STATUS __nvoc_objCreate_CrashCatQueue(CrashCatQueue **ppThis, Dynamic *pParent, NvU32 createFlags, CrashCatQueueConfig * arg_pQueueConfig) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; CrashCatQueue *pThis; CrashCatWayfinder *pCrashcatWayfinder; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CrashCatQueue), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(CrashCatQueue)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CrashCatQueue); pThis->__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_Object); @@ -153,16 +161,25 @@ NV_STATUS __nvoc_objCreate_CrashCatQueue(CrashCatQueue **ppThis, Dynamic *pParen status = __nvoc_ctor_CrashCatQueue(pThis, pCrashcatWayfinder, arg_pQueueConfig); if (status != NV_OK) goto __nvoc_objCreate_CrashCatQueue_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_CrashCatQueue_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(CrashCatQueue)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_crashcat_queue_nvoc.h b/src/nvidia/generated/g_crashcat_queue_nvoc.h index d4f19ebc15..9a10bf01b1 100644 --- a/src/nvidia/generated/g_crashcat_queue_nvoc.h +++ b/src/nvidia/generated/g_crashcat_queue_nvoc.h @@ -73,11 +73,16 @@ typedef struct NvU32 getRegOffset; } CrashCatQueueConfig; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CRASHCAT_QUEUE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct CrashCatQueue { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_crashcat_report_nvoc.c b/src/nvidia/generated/g_crashcat_report_nvoc.c index 76dac11b32..62c2a34db3 100644 --- a/src/nvidia/generated/g_crashcat_report_nvoc.c +++ b/src/nvidia/generated/g_crashcat_report_nvoc.c @@ -125,23 +125,31 @@ static void __nvoc_init_funcTable_CrashCatReport_1(CrashCatReport *pThis) { PORT_UNREFERENCED_VARIABLE(reportHal_HalVarIdx); // Hal function -- crashcatReportLogReporter - if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* CrashCatReportHal: V1_GENERIC */ + if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* CrashCatReportHal: V1_LIBOS2 */ { - pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_GENERIC; + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_LIBOS2; + } + else if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000004UL) )) /* CrashCatReportHal: V1_LIBOS3 */ + { + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_LIBOS3; } else { - pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_LIBOS2; + pThis->__crashcatReportLogReporter__ = &crashcatReportLogReporter_V1_GENERIC; } // Hal function -- crashcatReportLogSource - if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* CrashCatReportHal: V1_GENERIC */ + if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* CrashCatReportHal: V1_LIBOS2 */ { - pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_GENERIC; + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_LIBOS2; + } + else if (( ((reportHal_HalVarIdx >> 5) == 0UL) && ((1UL << (reportHal_HalVarIdx & 0x1f)) & 0x00000004UL) )) /* CrashCatReportHal: V1_LIBOS3 */ + { + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_LIBOS3; } else { - pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_LIBOS2; + pThis->__crashcatReportLogSource__ = &crashcatReportLogSource_V1_GENERIC; } } @@ -160,21 +168,26 @@ void __nvoc_init_CrashCatReport(CrashCatReport *pThis, } NV_STATUS __nvoc_objCreate_CrashCatReport(CrashCatReport **ppThis, Dynamic *pParent, NvU32 createFlags, - NV_CRASHCAT_PACKET_FORMAT_VERSION CrashCatReportHal_version, CrashCatImplementer CrashCatReportHal_implementer, void ** arg_ppReportBytes, NvLength arg_bytesRemaining) { + NV_CRASHCAT_PACKET_FORMAT_VERSION CrashCatReportHal_version, CrashCatImplementer CrashCatReportHal_implementer, void ** arg_ppReportBytes, NvLength arg_bytesRemaining) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; CrashCatReport *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CrashCatReport), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(CrashCatReport)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CrashCatReport); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -189,16 +202,25 @@ NV_STATUS __nvoc_objCreate_CrashCatReport(CrashCatReport **ppThis, Dynamic *pPar status = __nvoc_ctor_CrashCatReport(pThis, arg_ppReportBytes, arg_bytesRemaining); if (status != NV_OK) goto __nvoc_objCreate_CrashCatReport_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_CrashCatReport_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(CrashCatReport)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_crashcat_report_nvoc.h b/src/nvidia/generated/g_crashcat_report_nvoc.h index af03bb060e..71f40a22fe 100644 --- a/src/nvidia/generated/g_crashcat_report_nvoc.h +++ b/src/nvidia/generated/g_crashcat_report_nvoc.h @@ -62,16 +62,22 @@ struct CrashCatReportHal { typedef struct CrashCatReportHal CrashCatReportHal; void __nvoc_init_halspec_CrashCatReportHal(CrashCatReportHal*, NV_CRASHCAT_PACKET_FORMAT_VERSION, CrashCatImplementer); + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct __nvoc_inner_struc_CrashCatReport_1__ { NvCrashCatReport_V1 report; NvCrashCatRiscv64CsrState_V1 riscv64CsrState; NvCrashCatRiscv64GprState_V1 riscv64GprState; - NvCrashCatRiscv64Trace_V1 *pRiscv64Trace; + NvCrashCatRiscv64Trace_V1 *pRiscv64StackTrace; + NvCrashCatRiscv64Trace_V1 *pRiscv64PcTrace; NvCrashCatIo32State_V1 *pIo32State; }; @@ -236,18 +242,18 @@ static inline void crashcatReportLogRiscv64GprState(struct CrashCatReport *arg0) #define crashcatReportLogRiscv64GprState_HAL(arg0) crashcatReportLogRiscv64GprState(arg0) -void crashcatReportLogRiscv64Trace_V1(struct CrashCatReport *arg0); +void crashcatReportLogRiscv64Traces_V1(struct CrashCatReport *arg0); #ifdef __nvoc_crashcat_report_h_disabled -static inline void crashcatReportLogRiscv64Trace(struct CrashCatReport *arg0) { +static inline void crashcatReportLogRiscv64Traces(struct CrashCatReport *arg0) { NV_ASSERT_FAILED_PRECOMP("CrashCatReport was disabled!"); } #else //__nvoc_crashcat_report_h_disabled -#define crashcatReportLogRiscv64Trace(arg0) crashcatReportLogRiscv64Trace_V1(arg0) +#define crashcatReportLogRiscv64Traces(arg0) crashcatReportLogRiscv64Traces_V1(arg0) #endif //__nvoc_crashcat_report_h_disabled -#define crashcatReportLogRiscv64Trace_HAL(arg0) crashcatReportLogRiscv64Trace(arg0) +#define crashcatReportLogRiscv64Traces_HAL(arg0) crashcatReportLogRiscv64Traces(arg0) void crashcatReportLogIo32State_V1(struct CrashCatReport *arg0); @@ -266,6 +272,8 @@ void crashcatReportLogReporter_V1_GENERIC(struct CrashCatReport *arg0); void crashcatReportLogReporter_V1_LIBOS2(struct CrashCatReport *arg0); +void crashcatReportLogReporter_V1_LIBOS3(struct CrashCatReport *arg0); + static inline void crashcatReportLogReporter_DISPATCH(struct CrashCatReport *arg0) { arg0->__crashcatReportLogReporter__(arg0); } @@ -274,6 +282,8 @@ void crashcatReportLogSource_V1_GENERIC(struct CrashCatReport *arg0); void crashcatReportLogSource_V1_LIBOS2(struct CrashCatReport *arg0); +void crashcatReportLogSource_V1_LIBOS3(struct CrashCatReport *arg0); + static inline void crashcatReportLogSource_DISPATCH(struct CrashCatReport *arg0) { arg0->__crashcatReportLogSource__(arg0); } @@ -347,8 +357,8 @@ void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64GprState)(struct CrashCatRepo #endif //__nvoc_crashcat_report_h_disabled #ifndef __nvoc_crashcat_report_h_disabled -#undef crashcatReportLogRiscv64Trace -void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64Trace)(struct CrashCatReport *arg0); +#undef crashcatReportLogRiscv64Traces +void NVOC_PRIVATE_FUNCTION(crashcatReportLogRiscv64Traces)(struct CrashCatReport *arg0); #endif //__nvoc_crashcat_report_h_disabled #ifndef __nvoc_crashcat_report_h_disabled diff --git a/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c b/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c index f0be337d19..8110e314a3 100644 --- a/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c +++ b/src/nvidia/generated/g_crashcat_wayfinder_nvoc.c @@ -130,21 +130,26 @@ void __nvoc_init_CrashCatWayfinder(CrashCatWayfinder *pThis, } NV_STATUS __nvoc_objCreate_CrashCatWayfinder(CrashCatWayfinder **ppThis, Dynamic *pParent, NvU32 createFlags, - NV_CRASHCAT_WAYFINDER_VERSION CrashCatWayfinderHal_version, NvU32 arg_wfl0) { + NV_CRASHCAT_WAYFINDER_VERSION CrashCatWayfinderHal_version, NvU32 arg_wfl0) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; CrashCatWayfinder *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(CrashCatWayfinder), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(CrashCatWayfinder)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_CrashCatWayfinder); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -159,16 +164,25 @@ NV_STATUS __nvoc_objCreate_CrashCatWayfinder(CrashCatWayfinder **ppThis, Dynamic status = __nvoc_ctor_CrashCatWayfinder(pThis, arg_wfl0); if (status != NV_OK) goto __nvoc_objCreate_CrashCatWayfinder_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_CrashCatWayfinder_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(CrashCatWayfinder)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h b/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h index 1ea98b9dea..97b48faba6 100644 --- a/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h +++ b/src/nvidia/generated/g_crashcat_wayfinder_nvoc.h @@ -68,11 +68,16 @@ struct CrashCatWayfinderHal { typedef struct CrashCatWayfinderHal CrashCatWayfinderHal; void __nvoc_init_halspec_CrashCatWayfinderHal(CrashCatWayfinderHal*, NV_CRASHCAT_WAYFINDER_VERSION); + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_CRASHCAT_WAYFINDER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct __nvoc_inner_struc_CrashCatWayfinder_1__ { NvCrashCatWayfinderL0_V1 wfl0; NvCrashCatWayfinderL1_V1 wfl1; diff --git a/src/nvidia/generated/g_dbgbuffer_nvoc.c b/src/nvidia/generated/g_dbgbuffer_nvoc.c index b67f44d785..84d715d91b 100644 --- a/src/nvidia/generated/g_dbgbuffer_nvoc.c +++ b/src/nvidia/generated/g_dbgbuffer_nvoc.c @@ -149,10 +149,6 @@ static void __nvoc_thunk_RmResource_dbgbufControl_Epilogue(struct DebugBufferApi rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dbgbufControlLookup(struct DebugBufferApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle(struct DebugBufferApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DebugBufferApi_GpuResource.offset)); } @@ -177,6 +173,10 @@ static NvBool __nvoc_thunk_RsResource_dbgbufCanCopy(struct DebugBufferApi *pReso return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dbgbufIsPartialUnmapSupported(struct DebugBufferApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dbgbufPreDestruct(struct DebugBufferApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DebugBufferApi_RsResource.offset)); } @@ -268,8 +268,6 @@ static void __nvoc_init_funcTable_DebugBufferApi_1(DebugBufferApi *pThis) { pThis->__dbgbufControl_Epilogue__ = &__nvoc_thunk_RmResource_dbgbufControl_Epilogue; - pThis->__dbgbufControlLookup__ = &__nvoc_thunk_RsResource_dbgbufControlLookup; - pThis->__dbgbufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dbgbufGetInternalObjectHandle; pThis->__dbgbufControl__ = &__nvoc_thunk_GpuResource_dbgbufControl; @@ -282,6 +280,8 @@ static void __nvoc_init_funcTable_DebugBufferApi_1(DebugBufferApi *pThis) { pThis->__dbgbufCanCopy__ = &__nvoc_thunk_RsResource_dbgbufCanCopy; + pThis->__dbgbufIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dbgbufIsPartialUnmapSupported; + pThis->__dbgbufPreDestruct__ = &__nvoc_thunk_RsResource_dbgbufPreDestruct; pThis->__dbgbufIsDuplicate__ = &__nvoc_thunk_RsResource_dbgbufIsDuplicate; @@ -307,21 +307,26 @@ void __nvoc_init_DebugBufferApi(DebugBufferApi *pThis) { __nvoc_init_funcTable_DebugBufferApi(pThis); } -NV_STATUS __nvoc_objCreate_DebugBufferApi(DebugBufferApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DebugBufferApi(DebugBufferApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DebugBufferApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DebugBufferApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DebugBufferApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DebugBufferApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -336,16 +341,25 @@ NV_STATUS __nvoc_objCreate_DebugBufferApi(DebugBufferApi **ppThis, Dynamic *pPar status = __nvoc_ctor_DebugBufferApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DebugBufferApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DebugBufferApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DebugBufferApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_dbgbuffer_nvoc.h b/src/nvidia/generated/g_dbgbuffer_nvoc.h index 5e1bd7a644..b33fff6f2c 100644 --- a/src/nvidia/generated/g_dbgbuffer_nvoc.h +++ b/src/nvidia/generated/g_dbgbuffer_nvoc.h @@ -47,11 +47,16 @@ extern "C" { /*! * RM internal class representing NV40_DEBUG_BUFFER */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DBGBUFFER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DebugBufferApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -75,13 +80,13 @@ struct DebugBufferApi { NV_STATUS (*__dbgbufInternalControlForward__)(struct DebugBufferApi *, NvU32, void *, NvU32); NV_STATUS (*__dbgbufUnmapFrom__)(struct DebugBufferApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dbgbufControl_Epilogue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dbgbufControlLookup__)(struct DebugBufferApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__dbgbufGetInternalObjectHandle__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufControl__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dbgbufGetMemInterMapParams__)(struct DebugBufferApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dbgbufControlFilter__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dbgbufControlSerialization_Prologue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dbgbufCanCopy__)(struct DebugBufferApi *); + NvBool (*__dbgbufIsPartialUnmapSupported__)(struct DebugBufferApi *); void (*__dbgbufPreDestruct__)(struct DebugBufferApi *); NV_STATUS (*__dbgbufIsDuplicate__)(struct DebugBufferApi *, NvHandle, NvBool *); void (*__dbgbufControlSerialization_Epilogue__)(struct DebugBufferApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -131,13 +136,13 @@ NV_STATUS __nvoc_objCreate_DebugBufferApi(DebugBufferApi**, Dynamic*, NvU32, CAL #define dbgbufInternalControlForward(pGpuResource, command, pParams, size) dbgbufInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dbgbufUnmapFrom(pResource, pParams) dbgbufUnmapFrom_DISPATCH(pResource, pParams) #define dbgbufControl_Epilogue(pResource, pCallContext, pParams) dbgbufControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dbgbufControlLookup(pResource, pParams, ppEntry) dbgbufControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dbgbufGetInternalObjectHandle(pGpuResource) dbgbufGetInternalObjectHandle_DISPATCH(pGpuResource) #define dbgbufControl(pGpuResource, pCallContext, pParams) dbgbufControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dbgbufGetMemInterMapParams(pRmResource, pParams) dbgbufGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dbgbufControlFilter(pResource, pCallContext, pParams) dbgbufControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dbgbufControlSerialization_Prologue(pResource, pCallContext, pParams) dbgbufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dbgbufCanCopy(pResource) dbgbufCanCopy_DISPATCH(pResource) +#define dbgbufIsPartialUnmapSupported(pResource) dbgbufIsPartialUnmapSupported_DISPATCH(pResource) #define dbgbufPreDestruct(pResource) dbgbufPreDestruct_DISPATCH(pResource) #define dbgbufIsDuplicate(pResource, hMemory, pDuplicate) dbgbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dbgbufControlSerialization_Epilogue(pResource, pCallContext, pParams) dbgbufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -206,10 +211,6 @@ static inline void dbgbufControl_Epilogue_DISPATCH(struct DebugBufferApi *pResou pResource->__dbgbufControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dbgbufControlLookup_DISPATCH(struct DebugBufferApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dbgbufControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle dbgbufGetInternalObjectHandle_DISPATCH(struct DebugBufferApi *pGpuResource) { return pGpuResource->__dbgbufGetInternalObjectHandle__(pGpuResource); } @@ -234,6 +235,10 @@ static inline NvBool dbgbufCanCopy_DISPATCH(struct DebugBufferApi *pResource) { return pResource->__dbgbufCanCopy__(pResource); } +static inline NvBool dbgbufIsPartialUnmapSupported_DISPATCH(struct DebugBufferApi *pResource) { + return pResource->__dbgbufIsPartialUnmapSupported__(pResource); +} + static inline void dbgbufPreDestruct_DISPATCH(struct DebugBufferApi *pResource) { pResource->__dbgbufPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_dce_client_nvoc.h b/src/nvidia/generated/g_dce_client_nvoc.h index f03e892198..b5bb169b79 100644 --- a/src/nvidia/generated/g_dce_client_nvoc.h +++ b/src/nvidia/generated/g_dce_client_nvoc.h @@ -53,11 +53,16 @@ extern "C" { * Defines the structure used to contain all generic information related to * the DceClient. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DCE_CLIENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJDCECLIENTRM { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; diff --git a/src/nvidia/generated/g_deferred_api_nvoc.c b/src/nvidia/generated/g_deferred_api_nvoc.c index 66946ab61e..d70c6a6fef 100644 --- a/src/nvidia/generated/g_deferred_api_nvoc.c +++ b/src/nvidia/generated/g_deferred_api_nvoc.c @@ -180,10 +180,6 @@ static void __nvoc_thunk_RmResource_defapiControl_Epilogue(struct DeferredApiObj rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_defapiControlLookup(struct DeferredApiObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_defapiGetInternalObjectHandle(struct DeferredApiObject *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DeferredApiObject_GpuResource.offset)); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_defapiCanCopy(struct DeferredApiObject *pR return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_defapiIsPartialUnmapSupported(struct DeferredApiObject *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_defapiPreDestruct(struct DeferredApiObject *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DeferredApiObject_RsResource.offset)); } @@ -270,12 +270,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Deferred #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) defapiCtrlCmdRemoveApi_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x50800102u, /*paramSize=*/ sizeof(NV5080_CTRL_REMOVE_API_PARAMS), @@ -285,12 +285,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Deferred #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) defapiCtrlCmdDeferredApiV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x50800103u, /*paramSize=*/ sizeof(NV5080_CTRL_DEFERRED_API_V2_PARAMS), @@ -349,11 +349,11 @@ static void __nvoc_init_funcTable_DeferredApiObject_1(DeferredApiObject *pThis) pThis->__defapiCtrlCmdDeferredApi__ = &defapiCtrlCmdDeferredApi_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) pThis->__defapiCtrlCmdDeferredApiV2__ = &defapiCtrlCmdDeferredApiV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) pThis->__defapiCtrlCmdRemoveApi__ = &defapiCtrlCmdRemoveApi_IMPL; #endif @@ -387,8 +387,6 @@ static void __nvoc_init_funcTable_DeferredApiObject_1(DeferredApiObject *pThis) pThis->__defapiControl_Epilogue__ = &__nvoc_thunk_RmResource_defapiControl_Epilogue; - pThis->__defapiControlLookup__ = &__nvoc_thunk_RsResource_defapiControlLookup; - pThis->__defapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_defapiGetInternalObjectHandle; pThis->__defapiControl__ = &__nvoc_thunk_GpuResource_defapiControl; @@ -407,6 +405,8 @@ static void __nvoc_init_funcTable_DeferredApiObject_1(DeferredApiObject *pThis) pThis->__defapiCanCopy__ = &__nvoc_thunk_RsResource_defapiCanCopy; + pThis->__defapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_defapiIsPartialUnmapSupported; + pThis->__defapiPreDestruct__ = &__nvoc_thunk_RsResource_defapiPreDestruct; pThis->__defapiIsDuplicate__ = &__nvoc_thunk_RsResource_defapiIsDuplicate; @@ -441,23 +441,31 @@ void __nvoc_init_DeferredApiObject(DeferredApiObject *pThis, RmHalspecOwner *pRm __nvoc_init_funcTable_DeferredApiObject(pThis); } -NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DeferredApiObject *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DeferredApiObject), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DeferredApiObject)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DeferredApiObject); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -475,16 +483,25 @@ NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject **ppThis, Dynamic status = __nvoc_ctor_DeferredApiObject(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DeferredApiObject_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DeferredApiObject_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DeferredApiObject)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_deferred_api_nvoc.h b/src/nvidia/generated/g_deferred_api_nvoc.h index 17843b5b43..3647e14be6 100644 --- a/src/nvidia/generated/g_deferred_api_nvoc.h +++ b/src/nvidia/generated/g_deferred_api_nvoc.h @@ -57,11 +57,16 @@ typedef struct _def_deferred_api_info /*! * RM internal class representing NV50_DEFERRED_API_CLASS */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DEFERRED_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DeferredApiObject { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -92,7 +97,6 @@ struct DeferredApiObject { NV_STATUS (*__defapiInternalControlForward__)(struct DeferredApiObject *, NvU32, void *, NvU32); NV_STATUS (*__defapiUnmapFrom__)(struct DeferredApiObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__defapiControl_Epilogue__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__defapiControlLookup__)(struct DeferredApiObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__defapiGetInternalObjectHandle__)(struct DeferredApiObject *); NV_STATUS (*__defapiControl__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__defapiUnmap__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -102,6 +106,7 @@ struct DeferredApiObject { NV_STATUS (*__defapiUnregisterEvent__)(struct DeferredApiObject *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__defapiControlSerialization_Prologue__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__defapiCanCopy__)(struct DeferredApiObject *); + NvBool (*__defapiIsPartialUnmapSupported__)(struct DeferredApiObject *); void (*__defapiPreDestruct__)(struct DeferredApiObject *); NV_STATUS (*__defapiIsDuplicate__)(struct DeferredApiObject *, NvHandle, NvBool *); void (*__defapiControlSerialization_Epilogue__)(struct DeferredApiObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -159,7 +164,6 @@ NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject**, Dynamic*, NvU3 #define defapiInternalControlForward(pGpuResource, command, pParams, size) defapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define defapiUnmapFrom(pResource, pParams) defapiUnmapFrom_DISPATCH(pResource, pParams) #define defapiControl_Epilogue(pResource, pCallContext, pParams) defapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define defapiControlLookup(pResource, pParams, ppEntry) defapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define defapiGetInternalObjectHandle(pGpuResource) defapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define defapiControl(pGpuResource, pCallContext, pParams) defapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define defapiUnmap(pGpuResource, pCallContext, pCpuMapping) defapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -169,6 +173,7 @@ NV_STATUS __nvoc_objCreate_DeferredApiObject(DeferredApiObject**, Dynamic*, NvU3 #define defapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) defapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define defapiControlSerialization_Prologue(pResource, pCallContext, pParams) defapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define defapiCanCopy(pResource) defapiCanCopy_DISPATCH(pResource) +#define defapiIsPartialUnmapSupported(pResource) defapiIsPartialUnmapSupported_DISPATCH(pResource) #define defapiPreDestruct(pResource) defapiPreDestruct_DISPATCH(pResource) #define defapiIsDuplicate(pResource, hMemory, pDuplicate) defapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define defapiControlSerialization_Epilogue(pResource, pCallContext, pParams) defapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -258,10 +263,6 @@ static inline void defapiControl_Epilogue_DISPATCH(struct DeferredApiObject *pRe pResource->__defapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS defapiControlLookup_DISPATCH(struct DeferredApiObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__defapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle defapiGetInternalObjectHandle_DISPATCH(struct DeferredApiObject *pGpuResource) { return pGpuResource->__defapiGetInternalObjectHandle__(pGpuResource); } @@ -298,6 +299,10 @@ static inline NvBool defapiCanCopy_DISPATCH(struct DeferredApiObject *pResource) return pResource->__defapiCanCopy__(pResource); } +static inline NvBool defapiIsPartialUnmapSupported_DISPATCH(struct DeferredApiObject *pResource) { + return pResource->__defapiIsPartialUnmapSupported__(pResource); +} + static inline void defapiPreDestruct_DISPATCH(struct DeferredApiObject *pResource) { pResource->__defapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_device_nvoc.c b/src/nvidia/generated/g_device_nvoc.c index 67edd39ddc..5460f8a225 100644 --- a/src/nvidia/generated/g_device_nvoc.c +++ b/src/nvidia/generated/g_device_nvoc.c @@ -23,10 +23,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; -void __nvoc_init_Device(Device*); -void __nvoc_init_funcTable_Device(Device*); -NV_STATUS __nvoc_ctor_Device(Device*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); -void __nvoc_init_dataField_Device(Device*); +void __nvoc_init_Device(Device*, RmHalspecOwner* ); +void __nvoc_init_funcTable_Device(Device*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_Device(Device*, RmHalspecOwner* , struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_Device(Device*, RmHalspecOwner* ); void __nvoc_dtor_Device(Device*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_Device; @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_deviceControl_Epilogue(struct Device *pResou rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_deviceControlLookup(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_deviceGetInternalObjectHandle(struct Device *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Device_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_deviceCanCopy(struct Device *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_deviceIsPartialUnmapSupported(struct Device *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_devicePreDestruct(struct Device *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Device_RsResource.offset)); } @@ -382,6 +382,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuVirtualizationSwitchToVga_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x800290u, + /*paramSize=*/ 0, + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdGpuVirtualizationSwitchToVga" +#endif + }, + { /* [13] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetSriovCaps_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) @@ -394,7 +409,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetSriovCaps" #endif }, - { /* [13] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -409,7 +424,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetClasslistV2" #endif }, - { /* [14] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -424,13 +439,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetFindSubDeviceHandle" #endif }, - { /* [15] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) + { /* [16] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetBrandCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) - /*flags=*/ 0x211u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) + /*flags=*/ 0x2211u, /*accessRight=*/0x0u, /*methodId=*/ 0x800294u, /*paramSize=*/ sizeof(NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS), @@ -439,7 +454,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuGetBrandCaps" #endif }, - { /* [16] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -454,7 +469,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdGpuSetVgpuVfBar1Size" #endif }, - { /* [17] */ + { /* [18] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuSetVgpuHeterogeneousMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x800297u, + /*paramSize=*/ sizeof(NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdGpuSetVgpuHeterogeneousMode" +#endif + }, + { /* [19] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdGpuGetVgpuHeterogeneousMode_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x800298u, + /*paramSize=*/ sizeof(NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdGpuGetVgpuHeterogeneousMode" +#endif + }, + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -469,7 +514,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCaps" #endif }, - { /* [18] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -484,7 +529,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfo" #endif }, - { /* [19] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -499,7 +544,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetTpcPartitionMode" #endif }, - { /* [20] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -514,7 +559,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [21] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -529,7 +574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [22] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -544,7 +589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [23] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -559,7 +604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCaps" #endif }, - { /* [24] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -574,7 +619,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCompbitStoreInfo" #endif }, - { /* [25] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -589,7 +634,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFbGetCapsV2" #endif }, - { /* [26] */ + { /* [29] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + /*flags=*/ 0x11u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x801308u, + /*paramSize=*/ sizeof(NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdSetDefaultVidmemPhysicality" +#endif + }, + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -604,7 +664,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCaps" #endif }, - { /* [27] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -619,7 +679,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdHostGetCapsV2" #endif }, - { /* [28] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -634,7 +694,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCaps" #endif }, - { /* [29] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -649,7 +709,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartSelectedChannels" #endif }, - { /* [30] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -664,7 +724,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetEngineContextProperties" #endif }, - { /* [31] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -679,7 +739,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetChannelList" #endif }, - { /* [32] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -694,7 +754,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetLatencyBufferSize" #endif }, - { /* [33] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -709,7 +769,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoSetChannelProperties" #endif }, - { /* [34] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -724,7 +784,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStopRunlist" #endif }, - { /* [35] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -739,7 +799,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoStartRunlist" #endif }, - { /* [36] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -754,7 +814,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoGetCapsV2" #endif }, - { /* [37] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -769,7 +829,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdFifoIdleChannels" #endif }, - { /* [38] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -784,13 +844,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPteInfo" #endif }, - { /* [39] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [43] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) deviceCtrlCmdDmaFlush_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdDmaFlush_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x801805u, /*paramSize=*/ sizeof(NV0080_CTRL_DMA_FLUSH_PARAMS), @@ -799,7 +859,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaFlush" #endif }, - { /* [40] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -814,7 +874,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaAdvSchedGetVaCaps" #endif }, - { /* [41] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -829,7 +889,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetPdeInfo" #endif }, - { /* [42] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -844,7 +904,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPteInfo" #endif }, - { /* [43] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -859,7 +919,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [44] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -874,7 +934,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaGetCaps" #endif }, - { /* [45] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -889,7 +949,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetVASpaceSize" #endif }, - { /* [46] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -904,7 +964,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUpdatePde2" #endif }, - { /* [47] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -919,7 +979,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaEnablePrivilegedRange" #endif }, - { /* [48] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -934,7 +994,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetDefaultVASpace" #endif }, - { /* [49] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -949,7 +1009,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaSetPageDirectory" #endif }, - { /* [50] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x140004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -964,28 +1024,43 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdDmaUnsetPageDirectory" #endif }, - { /* [51] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) + { /* [55] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) deviceCtrlCmdMsencGetCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdKPerfCudaLimitSetControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, - /*methodId=*/ 0x801b01u, - /*paramSize=*/ sizeof(NV0080_CTRL_MSENC_GET_CAPS_PARAMS), + /*methodId=*/ 0x801909u, + /*paramSize=*/ sizeof(NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "deviceCtrlCmdMsencGetCaps" + /*func=*/ "deviceCtrlCmdKPerfCudaLimitSetControl" #endif }, - { /* [52] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) + { /* [56] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdMsencGetCapsV2_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a10u) + /*flags=*/ 0x400a10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x801b02u, + /*paramSize=*/ sizeof(NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "deviceCtrlCmdMsencGetCapsV2" +#endif + }, + { /* [57] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) deviceCtrlCmdBspGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) - /*flags=*/ 0xa10u, + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdBspGetCapsV2_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a10u) + /*flags=*/ 0x400a10u, /*accessRight=*/0x0u, /*methodId=*/ 0x801c02u, /*paramSize=*/ sizeof(NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2), @@ -994,7 +1069,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdBspGetCapsV2" #endif }, - { /* [53] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1009,7 +1084,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTSwitch" #endif }, - { /* [54] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1024,13 +1099,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdOsUnixVTGetFBInfo" #endif }, - { /* [55] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [60] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) deviceCtrlCmdNvjpgGetCapsV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) deviceCtrlCmdNvjpgGetCapsV2_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x801f02u, /*paramSize=*/ sizeof(NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS), @@ -1039,7 +1114,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdNvjpgGetCapsV2" #endif }, - { /* [56] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1054,22 +1129,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] /*func=*/ "deviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [57] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x802006u, - /*paramSize=*/ sizeof(NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount" -#endif - }, - { /* [58] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1089,7 +1149,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[] const struct NVOC_EXPORT_INFO __nvoc_export_info_Device = { - /*numEntries=*/ 59, + /*numEntries=*/ 63, /*pExportEntries=*/ __nvoc_exported_method_def_Device }; @@ -1100,16 +1160,21 @@ void __nvoc_dtor_Device(Device *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); } -void __nvoc_init_dataField_Device(Device *pThis) { +void __nvoc_init_dataField_Device(Device *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); } NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); -NV_STATUS __nvoc_ctor_Device(Device *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_ctor_Device(Device *pThis, RmHalspecOwner *pRmhalspecowner, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_Device_fail_GpuResource; - __nvoc_init_dataField_Device(pThis); + __nvoc_init_dataField_Device(pThis, pRmhalspecowner); status = __nvoc_deviceConstruct(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_Device_fail__init; @@ -1123,8 +1188,13 @@ NV_STATUS __nvoc_ctor_Device(Device *pThis, struct CALL_CONTEXT * arg_pCallConte return status; } -static void __nvoc_init_funcTable_Device_1(Device *pThis) { +static void __nvoc_init_funcTable_Device_1(Device *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); pThis->__deviceControl__ = &deviceControl_IMPL; @@ -1162,9 +1232,15 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdDmaUnsetPageDirectory__ = &deviceCtrlCmdDmaUnsetPageDirectory_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__deviceCtrlCmdDmaFlush__ = &deviceCtrlCmdDmaFlush_IMPL; -#endif + // Hal function -- deviceCtrlCmdDmaFlush + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__deviceCtrlCmdDmaFlush__ = &deviceCtrlCmdDmaFlush_VF; + } + else + { + pThis->__deviceCtrlCmdDmaFlush__ = &deviceCtrlCmdDmaFlush_5baef9; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) pThis->__deviceCtrlCmdDmaAdvSchedGetVaCaps__ = &deviceCtrlCmdDmaAdvSchedGetVaCaps_IMPL; @@ -1234,6 +1310,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdFbGetCapsV2__ = &deviceCtrlCmdFbGetCapsV2_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + pThis->__deviceCtrlCmdSetDefaultVidmemPhysicality__ = &deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) pThis->__deviceCtrlCmdFifoGetCaps__ = &deviceCtrlCmdFifoGetCaps_IMPL; #endif @@ -1282,6 +1362,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdHostGetCapsV2__ = &deviceCtrlCmdHostGetCapsV2_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + pThis->__deviceCtrlCmdKPerfCudaLimitSetControl__ = &deviceCtrlCmdKPerfCudaLimitSetControl_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe50u) pThis->__deviceCtrlCmdInternalPerfCudaLimitSetControl__ = &deviceCtrlCmdInternalPerfCudaLimitSetControl_IMPL; #endif @@ -1290,10 +1374,6 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdInternalPerfCudaLimitDisable__ = &deviceCtrlCmdInternalPerfCudaLimitDisable_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount__ = &deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__deviceCtrlCmdGpuGetClasslist__ = &deviceCtrlCmdGpuGetClasslist_IMPL; #endif @@ -1334,30 +1414,60 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCtrlCmdGpuGetVgxCaps__ = &deviceCtrlCmdGpuGetVgxCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2211u) pThis->__deviceCtrlCmdGpuGetBrandCaps__ = &deviceCtrlCmdGpuGetBrandCaps_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__deviceCtrlCmdGpuGetSriovCaps__ = &deviceCtrlCmdGpuGetSriovCaps_IMPL; + pThis->__deviceCtrlCmdGpuVirtualizationSwitchToVga__ = &deviceCtrlCmdGpuVirtualizationSwitchToVga_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) - pThis->__deviceCtrlCmdGpuGetFindSubDeviceHandle__ = &deviceCtrlCmdGpuGetFindSubDeviceHandle_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__deviceCtrlCmdGpuSetVgpuHeterogeneousMode__ = &deviceCtrlCmdGpuSetVgpuHeterogeneousMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - pThis->__deviceCtrlCmdMsencGetCaps__ = &deviceCtrlCmdMsencGetCaps_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__deviceCtrlCmdGpuGetVgpuHeterogeneousMode__ = &deviceCtrlCmdGpuGetVgpuHeterogeneousMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) - pThis->__deviceCtrlCmdBspGetCapsV2__ = &deviceCtrlCmdBspGetCapsV2_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__deviceCtrlCmdGpuGetSriovCaps__ = &deviceCtrlCmdGpuGetSriovCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__deviceCtrlCmdNvjpgGetCapsV2__ = &deviceCtrlCmdNvjpgGetCapsV2_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__deviceCtrlCmdGpuGetFindSubDeviceHandle__ = &deviceCtrlCmdGpuGetFindSubDeviceHandle_IMPL; #endif + // Hal function -- deviceCtrlCmdMsencGetCapsV2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__deviceCtrlCmdMsencGetCapsV2__ = &deviceCtrlCmdMsencGetCapsV2_VF; + } + else + { + pThis->__deviceCtrlCmdMsencGetCapsV2__ = &deviceCtrlCmdMsencGetCapsV2_5baef9; + } + + // Hal function -- deviceCtrlCmdBspGetCapsV2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__deviceCtrlCmdBspGetCapsV2__ = &deviceCtrlCmdBspGetCapsV2_VF; + } + else + { + pThis->__deviceCtrlCmdBspGetCapsV2__ = &deviceCtrlCmdBspGetCapsV2_5baef9; + } + + // Hal function -- deviceCtrlCmdNvjpgGetCapsV2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__deviceCtrlCmdNvjpgGetCapsV2__ = &deviceCtrlCmdNvjpgGetCapsV2_VF; + } + else + { + pThis->__deviceCtrlCmdNvjpgGetCapsV2__ = &deviceCtrlCmdNvjpgGetCapsV2_c04480; + } + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) pThis->__deviceCtrlCmdOsUnixVTSwitch__ = &deviceCtrlCmdOsUnixVTSwitch_IMPL; #endif @@ -1390,8 +1500,6 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceControl_Epilogue__ = &__nvoc_thunk_RmResource_deviceControl_Epilogue; - pThis->__deviceControlLookup__ = &__nvoc_thunk_RsResource_deviceControlLookup; - pThis->__deviceGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_deviceGetInternalObjectHandle; pThis->__deviceUnmap__ = &__nvoc_thunk_GpuResource_deviceUnmap; @@ -1406,6 +1514,8 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceCanCopy__ = &__nvoc_thunk_RsResource_deviceCanCopy; + pThis->__deviceIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_deviceIsPartialUnmapSupported; + pThis->__devicePreDestruct__ = &__nvoc_thunk_RsResource_devicePreDestruct; pThis->__deviceIsDuplicate__ = &__nvoc_thunk_RsResource_deviceIsDuplicate; @@ -1417,12 +1527,12 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis) { pThis->__deviceAccessCallback__ = &__nvoc_thunk_RmResource_deviceAccessCallback; } -void __nvoc_init_funcTable_Device(Device *pThis) { - __nvoc_init_funcTable_Device_1(pThis); +void __nvoc_init_funcTable_Device(Device *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_Device_1(pThis, pRmhalspecowner); } void __nvoc_init_GpuResource(GpuResource*); -void __nvoc_init_Device(Device *pThis) { +void __nvoc_init_Device(Device *pThis, RmHalspecOwner *pRmhalspecowner) { pThis->__nvoc_pbase_Device = pThis; pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; @@ -1430,25 +1540,34 @@ void __nvoc_init_Device(Device *pThis) { pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); - __nvoc_init_funcTable_Device(pThis); + __nvoc_init_funcTable_Device(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_Device(Device **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_Device(Device **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Device *pThis; + RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Device), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Device)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Device); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -1458,20 +1577,33 @@ NV_STATUS __nvoc_objCreate_Device(Device **ppThis, Dynamic *pParent, NvU32 creat pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; } - __nvoc_init_Device(pThis); - status = __nvoc_ctor_Device(pThis, arg_pCallContext, arg_pParams); + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_Device(pThis, pRmhalspecowner); + status = __nvoc_ctor_Device(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_Device_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Device_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Device)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_device_nvoc.h b/src/nvidia/generated/g_device_nvoc.h index 03bc22c868..ca1e139c44 100644 --- a/src/nvidia/generated/g_device_nvoc.h +++ b/src/nvidia/generated/g_device_nvoc.h @@ -42,6 +42,7 @@ extern "C" { #include "rmapi/control.h" #include "containers/btree.h" +#include "gpu/gpu_halspec.h" #include "gpu/gpu_resource.h" #include "mem_mgr/vaspace.h" @@ -67,11 +68,16 @@ typedef struct OBJVASPACE OBJVASPACE; * semantics; that is, operations involving a device are applied to all GPUs * in the device. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DEVICE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Device { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -109,6 +115,7 @@ struct Device { NV_STATUS (*__deviceCtrlCmdFbGetCompbitStoreInfo__)(struct Device *, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *); NV_STATUS (*__deviceCtrlCmdFbGetCaps__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdFbGetCapsV2__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_V2_PARAMS *); + NV_STATUS (*__deviceCtrlCmdSetDefaultVidmemPhysicality__)(struct Device *, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoGetCaps__)(struct Device *, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoGetCapsV2__)(struct Device *, NV0080_CTRL_FIFO_GET_CAPS_V2_PARAMS *); NV_STATUS (*__deviceCtrlCmdFifoStartSelectedChannels__)(struct Device *, NV0080_CTRL_FIFO_START_SELECTED_CHANNELS_PARAMS *); @@ -121,9 +128,9 @@ struct Device { NV_STATUS (*__deviceCtrlCmdFifoIdleChannels__)(struct Device *, NV0080_CTRL_FIFO_IDLE_CHANNELS_PARAMS *); NV_STATUS (*__deviceCtrlCmdHostGetCaps__)(struct Device *, NV0080_CTRL_HOST_GET_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdHostGetCapsV2__)(struct Device *, NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS *); + NV_STATUS (*__deviceCtrlCmdKPerfCudaLimitSetControl__)(struct Device *, NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS *); NV_STATUS (*__deviceCtrlCmdInternalPerfCudaLimitSetControl__)(struct Device *, NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS *); NV_STATUS (*__deviceCtrlCmdInternalPerfCudaLimitDisable__)(struct Device *); - NV_STATUS (*__deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount__)(struct Device *, NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetClasslist__)(struct Device *, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetClasslistV2__)(struct Device *, NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetNumSubdevices__)(struct Device *, NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS *); @@ -135,9 +142,12 @@ struct Device { NV_STATUS (*__deviceCtrlCmdGpuSetSparseTextureComputeMode__)(struct Device *, NV0080_CTRL_GPU_SET_SPARSE_TEXTURE_COMPUTE_MODE_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetVgxCaps__)(struct Device *, NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetBrandCaps__)(struct Device *, NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *); + NV_STATUS (*__deviceCtrlCmdGpuVirtualizationSwitchToVga__)(struct Device *); + NV_STATUS (*__deviceCtrlCmdGpuSetVgpuHeterogeneousMode__)(struct Device *, NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS *); + NV_STATUS (*__deviceCtrlCmdGpuGetVgpuHeterogeneousMode__)(struct Device *, NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetSriovCaps__)(struct Device *, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *); NV_STATUS (*__deviceCtrlCmdGpuGetFindSubDeviceHandle__)(struct Device *, NV0080_CTRL_GPU_FIND_SUBDEVICE_HANDLE_PARAM *); - NV_STATUS (*__deviceCtrlCmdMsencGetCaps__)(struct Device *, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *); + NV_STATUS (*__deviceCtrlCmdMsencGetCapsV2__)(struct Device *, NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *); NV_STATUS (*__deviceCtrlCmdBspGetCapsV2__)(struct Device *, NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 *); NV_STATUS (*__deviceCtrlCmdNvjpgGetCapsV2__)(struct Device *, NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS *); NV_STATUS (*__deviceCtrlCmdOsUnixVTSwitch__)(struct Device *, NV0080_CTRL_OS_UNIX_VT_SWITCH_PARAMS *); @@ -152,7 +162,6 @@ struct Device { NV_STATUS (*__deviceGetRegBaseOffsetAndSize__)(struct Device *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__deviceUnmapFrom__)(struct Device *, RS_RES_UNMAP_FROM_PARAMS *); void (*__deviceControl_Epilogue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__deviceControlLookup__)(struct Device *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__deviceGetInternalObjectHandle__)(struct Device *); NV_STATUS (*__deviceUnmap__)(struct Device *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__deviceGetMemInterMapParams__)(struct Device *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -160,6 +169,7 @@ struct Device { NV_STATUS (*__deviceControlFilter__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__deviceControlSerialization_Prologue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__deviceCanCopy__)(struct Device *); + NvBool (*__deviceIsPartialUnmapSupported__)(struct Device *); void (*__devicePreDestruct__)(struct Device *); NV_STATUS (*__deviceIsDuplicate__)(struct Device *, NvHandle, NvBool *); void (*__deviceControlSerialization_Epilogue__)(struct Device *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -182,6 +192,7 @@ struct Device { NvU64 vaLimitInternal; NvU64 vaSize; NvU32 vaMode; + NvU32 defaultVidmemPhysicalityOverride; struct KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; }; @@ -224,6 +235,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCtrlCmdDmaSetPageDirectory(pDevice, pParams) deviceCtrlCmdDmaSetPageDirectory_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaUnsetPageDirectory(pDevice, pParams) deviceCtrlCmdDmaUnsetPageDirectory_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaFlush(pDevice, flushParams) deviceCtrlCmdDmaFlush_DISPATCH(pDevice, flushParams) +#define deviceCtrlCmdDmaFlush_HAL(pDevice, flushParams) deviceCtrlCmdDmaFlush_DISPATCH(pDevice, flushParams) #define deviceCtrlCmdDmaAdvSchedGetVaCaps(pDevice, pParams) deviceCtrlCmdDmaAdvSchedGetVaCaps_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaGetPdeInfo(pDevice, pParams) deviceCtrlCmdDmaGetPdeInfo_DISPATCH(pDevice, pParams) #define deviceCtrlCmdDmaSetPteInfo(pDevice, pParams) deviceCtrlCmdDmaSetPteInfo_DISPATCH(pDevice, pParams) @@ -241,6 +253,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCtrlCmdFbGetCompbitStoreInfo(pDevice, pCompbitStoreParams) deviceCtrlCmdFbGetCompbitStoreInfo_DISPATCH(pDevice, pCompbitStoreParams) #define deviceCtrlCmdFbGetCaps(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCaps_DISPATCH(pDevice, pFbCapsParams) #define deviceCtrlCmdFbGetCapsV2(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCapsV2_DISPATCH(pDevice, pFbCapsParams) +#define deviceCtrlCmdSetDefaultVidmemPhysicality(pDevice, pParams) deviceCtrlCmdSetDefaultVidmemPhysicality_DISPATCH(pDevice, pParams) #define deviceCtrlCmdFifoGetCaps(pDevice, pFifoCapsParams) deviceCtrlCmdFifoGetCaps_DISPATCH(pDevice, pFifoCapsParams) #define deviceCtrlCmdFifoGetCapsV2(pDevice, pFifoCapsParams) deviceCtrlCmdFifoGetCapsV2_DISPATCH(pDevice, pFifoCapsParams) #define deviceCtrlCmdFifoStartSelectedChannels(pDevice, pStartSel) deviceCtrlCmdFifoStartSelectedChannels_DISPATCH(pDevice, pStartSel) @@ -253,9 +266,9 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCtrlCmdFifoIdleChannels(pDevice, pParams) deviceCtrlCmdFifoIdleChannels_DISPATCH(pDevice, pParams) #define deviceCtrlCmdHostGetCaps(pDevice, pHostCapsParams) deviceCtrlCmdHostGetCaps_DISPATCH(pDevice, pHostCapsParams) #define deviceCtrlCmdHostGetCapsV2(pDevice, pHostCapsParamsV2) deviceCtrlCmdHostGetCapsV2_DISPATCH(pDevice, pHostCapsParamsV2) +#define deviceCtrlCmdKPerfCudaLimitSetControl(pDevice, pParams) deviceCtrlCmdKPerfCudaLimitSetControl_DISPATCH(pDevice, pParams) #define deviceCtrlCmdInternalPerfCudaLimitSetControl(pDevice, pParams) deviceCtrlCmdInternalPerfCudaLimitSetControl_DISPATCH(pDevice, pParams) #define deviceCtrlCmdInternalPerfCudaLimitDisable(pDevice) deviceCtrlCmdInternalPerfCudaLimitDisable_DISPATCH(pDevice) -#define deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount(pDevice, pParams) deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount_DISPATCH(pDevice, pParams) #define deviceCtrlCmdGpuGetClasslist(pDevice, pClassListParams) deviceCtrlCmdGpuGetClasslist_DISPATCH(pDevice, pClassListParams) #define deviceCtrlCmdGpuGetClasslistV2(pDevice, pParams) deviceCtrlCmdGpuGetClasslistV2_DISPATCH(pDevice, pParams) #define deviceCtrlCmdGpuGetNumSubdevices(pDevice, pSubDeviceCountParams) deviceCtrlCmdGpuGetNumSubdevices_DISPATCH(pDevice, pSubDeviceCountParams) @@ -267,11 +280,17 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceCtrlCmdGpuSetSparseTextureComputeMode(pDevice, pModeParams) deviceCtrlCmdGpuSetSparseTextureComputeMode_DISPATCH(pDevice, pModeParams) #define deviceCtrlCmdGpuGetVgxCaps(pDevice, pParams) deviceCtrlCmdGpuGetVgxCaps_DISPATCH(pDevice, pParams) #define deviceCtrlCmdGpuGetBrandCaps(pDevice, pParams) deviceCtrlCmdGpuGetBrandCaps_DISPATCH(pDevice, pParams) +#define deviceCtrlCmdGpuVirtualizationSwitchToVga(pDevice) deviceCtrlCmdGpuVirtualizationSwitchToVga_DISPATCH(pDevice) +#define deviceCtrlCmdGpuSetVgpuHeterogeneousMode(pDevice, pParams) deviceCtrlCmdGpuSetVgpuHeterogeneousMode_DISPATCH(pDevice, pParams) +#define deviceCtrlCmdGpuGetVgpuHeterogeneousMode(pDevice, pParams) deviceCtrlCmdGpuGetVgpuHeterogeneousMode_DISPATCH(pDevice, pParams) #define deviceCtrlCmdGpuGetSriovCaps(pDevice, pParams) deviceCtrlCmdGpuGetSriovCaps_DISPATCH(pDevice, pParams) #define deviceCtrlCmdGpuGetFindSubDeviceHandle(pDevice, pParams) deviceCtrlCmdGpuGetFindSubDeviceHandle_DISPATCH(pDevice, pParams) -#define deviceCtrlCmdMsencGetCaps(pDevice, pMsencCapsParams) deviceCtrlCmdMsencGetCaps_DISPATCH(pDevice, pMsencCapsParams) +#define deviceCtrlCmdMsencGetCapsV2(pDevice, pMsencCapsParams) deviceCtrlCmdMsencGetCapsV2_DISPATCH(pDevice, pMsencCapsParams) +#define deviceCtrlCmdMsencGetCapsV2_HAL(pDevice, pMsencCapsParams) deviceCtrlCmdMsencGetCapsV2_DISPATCH(pDevice, pMsencCapsParams) #define deviceCtrlCmdBspGetCapsV2(pDevice, pBspCapParams) deviceCtrlCmdBspGetCapsV2_DISPATCH(pDevice, pBspCapParams) +#define deviceCtrlCmdBspGetCapsV2_HAL(pDevice, pBspCapParams) deviceCtrlCmdBspGetCapsV2_DISPATCH(pDevice, pBspCapParams) #define deviceCtrlCmdNvjpgGetCapsV2(pDevice, pNvjpgCapsParams) deviceCtrlCmdNvjpgGetCapsV2_DISPATCH(pDevice, pNvjpgCapsParams) +#define deviceCtrlCmdNvjpgGetCapsV2_HAL(pDevice, pNvjpgCapsParams) deviceCtrlCmdNvjpgGetCapsV2_DISPATCH(pDevice, pNvjpgCapsParams) #define deviceCtrlCmdOsUnixVTSwitch(pDevice, pParams) deviceCtrlCmdOsUnixVTSwitch_DISPATCH(pDevice, pParams) #define deviceCtrlCmdOsUnixVTGetFBInfo(pDevice, pParams) deviceCtrlCmdOsUnixVTGetFBInfo_DISPATCH(pDevice, pParams) #define deviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) deviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) @@ -284,7 +303,6 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) deviceGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define deviceUnmapFrom(pResource, pParams) deviceUnmapFrom_DISPATCH(pResource, pParams) #define deviceControl_Epilogue(pResource, pCallContext, pParams) deviceControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define deviceControlLookup(pResource, pParams, ppEntry) deviceControlLookup_DISPATCH(pResource, pParams, ppEntry) #define deviceGetInternalObjectHandle(pGpuResource) deviceGetInternalObjectHandle_DISPATCH(pGpuResource) #define deviceUnmap(pGpuResource, pCallContext, pCpuMapping) deviceUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define deviceGetMemInterMapParams(pRmResource, pParams) deviceGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -292,6 +310,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT #define deviceControlFilter(pResource, pCallContext, pParams) deviceControlFilter_DISPATCH(pResource, pCallContext, pParams) #define deviceControlSerialization_Prologue(pResource, pCallContext, pParams) deviceControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define deviceCanCopy(pResource) deviceCanCopy_DISPATCH(pResource) +#define deviceIsPartialUnmapSupported(pResource) deviceIsPartialUnmapSupported_DISPATCH(pResource) #define devicePreDestruct(pResource) devicePreDestruct_DISPATCH(pResource) #define deviceIsDuplicate(pResource, hMemory, pDuplicate) deviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define deviceControlSerialization_Epilogue(pResource, pCallContext, pParams) deviceControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -357,7 +376,11 @@ static inline NV_STATUS deviceCtrlCmdDmaUnsetPageDirectory_DISPATCH(struct Devic return pDevice->__deviceCtrlCmdDmaUnsetPageDirectory__(pDevice, pParams); } -NV_STATUS deviceCtrlCmdDmaFlush_IMPL(struct Device *pDevice, NV0080_CTRL_DMA_FLUSH_PARAMS *flushParams); +NV_STATUS deviceCtrlCmdDmaFlush_VF(struct Device *pDevice, NV0080_CTRL_DMA_FLUSH_PARAMS *flushParams); + +static inline NV_STATUS deviceCtrlCmdDmaFlush_5baef9(struct Device *pDevice, NV0080_CTRL_DMA_FLUSH_PARAMS *flushParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS deviceCtrlCmdDmaFlush_DISPATCH(struct Device *pDevice, NV0080_CTRL_DMA_FLUSH_PARAMS *flushParams) { return pDevice->__deviceCtrlCmdDmaFlush__(pDevice, flushParams); @@ -465,6 +488,12 @@ static inline NV_STATUS deviceCtrlCmdFbGetCapsV2_DISPATCH(struct Device *pDevice return pDevice->__deviceCtrlCmdFbGetCapsV2__(pDevice, pFbCapsParams); } +NV_STATUS deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL(struct Device *pDevice, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams); + +static inline NV_STATUS deviceCtrlCmdSetDefaultVidmemPhysicality_DISPATCH(struct Device *pDevice, NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams) { + return pDevice->__deviceCtrlCmdSetDefaultVidmemPhysicality__(pDevice, pParams); +} + NV_STATUS deviceCtrlCmdFifoGetCaps_IMPL(struct Device *pDevice, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *pFifoCapsParams); static inline NV_STATUS deviceCtrlCmdFifoGetCaps_DISPATCH(struct Device *pDevice, NV0080_CTRL_FIFO_GET_CAPS_PARAMS *pFifoCapsParams) { @@ -537,6 +566,12 @@ static inline NV_STATUS deviceCtrlCmdHostGetCapsV2_DISPATCH(struct Device *pDevi return pDevice->__deviceCtrlCmdHostGetCapsV2__(pDevice, pHostCapsParamsV2); } +NV_STATUS deviceCtrlCmdKPerfCudaLimitSetControl_IMPL(struct Device *pDevice, NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS *pParams); + +static inline NV_STATUS deviceCtrlCmdKPerfCudaLimitSetControl_DISPATCH(struct Device *pDevice, NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS *pParams) { + return pDevice->__deviceCtrlCmdKPerfCudaLimitSetControl__(pDevice, pParams); +} + NV_STATUS deviceCtrlCmdInternalPerfCudaLimitSetControl_IMPL(struct Device *pDevice, NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS *pParams); static inline NV_STATUS deviceCtrlCmdInternalPerfCudaLimitSetControl_DISPATCH(struct Device *pDevice, NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS *pParams) { @@ -549,12 +584,6 @@ static inline NV_STATUS deviceCtrlCmdInternalPerfCudaLimitDisable_DISPATCH(struc return pDevice->__deviceCtrlCmdInternalPerfCudaLimitDisable__(pDevice); } -NV_STATUS deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount_IMPL(struct Device *pDevice, NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS *pParams); - -static inline NV_STATUS deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount_DISPATCH(struct Device *pDevice, NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS *pParams) { - return pDevice->__deviceCtrlCmdInternalPerfGetUnderpoweredGpuCount__(pDevice, pParams); -} - NV_STATUS deviceCtrlCmdGpuGetClasslist_IMPL(struct Device *pDevice, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *pClassListParams); static inline NV_STATUS deviceCtrlCmdGpuGetClasslist_DISPATCH(struct Device *pDevice, NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS *pClassListParams) { @@ -621,6 +650,24 @@ static inline NV_STATUS deviceCtrlCmdGpuGetBrandCaps_DISPATCH(struct Device *pDe return pDevice->__deviceCtrlCmdGpuGetBrandCaps__(pDevice, pParams); } +NV_STATUS deviceCtrlCmdGpuVirtualizationSwitchToVga_IMPL(struct Device *pDevice); + +static inline NV_STATUS deviceCtrlCmdGpuVirtualizationSwitchToVga_DISPATCH(struct Device *pDevice) { + return pDevice->__deviceCtrlCmdGpuVirtualizationSwitchToVga__(pDevice); +} + +NV_STATUS deviceCtrlCmdGpuSetVgpuHeterogeneousMode_IMPL(struct Device *pDevice, NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS *pParams); + +static inline NV_STATUS deviceCtrlCmdGpuSetVgpuHeterogeneousMode_DISPATCH(struct Device *pDevice, NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS *pParams) { + return pDevice->__deviceCtrlCmdGpuSetVgpuHeterogeneousMode__(pDevice, pParams); +} + +NV_STATUS deviceCtrlCmdGpuGetVgpuHeterogeneousMode_IMPL(struct Device *pDevice, NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS *pParams); + +static inline NV_STATUS deviceCtrlCmdGpuGetVgpuHeterogeneousMode_DISPATCH(struct Device *pDevice, NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS *pParams) { + return pDevice->__deviceCtrlCmdGpuGetVgpuHeterogeneousMode__(pDevice, pParams); +} + NV_STATUS deviceCtrlCmdGpuGetSriovCaps_IMPL(struct Device *pDevice, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams); static inline NV_STATUS deviceCtrlCmdGpuGetSriovCaps_DISPATCH(struct Device *pDevice, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *pParams) { @@ -633,19 +680,31 @@ static inline NV_STATUS deviceCtrlCmdGpuGetFindSubDeviceHandle_DISPATCH(struct D return pDevice->__deviceCtrlCmdGpuGetFindSubDeviceHandle__(pDevice, pParams); } -NV_STATUS deviceCtrlCmdMsencGetCaps_IMPL(struct Device *pDevice, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *pMsencCapsParams); +NV_STATUS deviceCtrlCmdMsencGetCapsV2_VF(struct Device *pDevice, NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *pMsencCapsParams); + +static inline NV_STATUS deviceCtrlCmdMsencGetCapsV2_5baef9(struct Device *pDevice, NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *pMsencCapsParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} -static inline NV_STATUS deviceCtrlCmdMsencGetCaps_DISPATCH(struct Device *pDevice, NV0080_CTRL_MSENC_GET_CAPS_PARAMS *pMsencCapsParams) { - return pDevice->__deviceCtrlCmdMsencGetCaps__(pDevice, pMsencCapsParams); +static inline NV_STATUS deviceCtrlCmdMsencGetCapsV2_DISPATCH(struct Device *pDevice, NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *pMsencCapsParams) { + return pDevice->__deviceCtrlCmdMsencGetCapsV2__(pDevice, pMsencCapsParams); } -NV_STATUS deviceCtrlCmdBspGetCapsV2_IMPL(struct Device *pDevice, NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 *pBspCapParams); +NV_STATUS deviceCtrlCmdBspGetCapsV2_VF(struct Device *pDevice, NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 *pBspCapParams); + +static inline NV_STATUS deviceCtrlCmdBspGetCapsV2_5baef9(struct Device *pDevice, NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 *pBspCapParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS deviceCtrlCmdBspGetCapsV2_DISPATCH(struct Device *pDevice, NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 *pBspCapParams) { return pDevice->__deviceCtrlCmdBspGetCapsV2__(pDevice, pBspCapParams); } -NV_STATUS deviceCtrlCmdNvjpgGetCapsV2_IMPL(struct Device *pDevice, NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS *pNvjpgCapsParams); +NV_STATUS deviceCtrlCmdNvjpgGetCapsV2_VF(struct Device *pDevice, NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS *pNvjpgCapsParams); + +static inline NV_STATUS deviceCtrlCmdNvjpgGetCapsV2_c04480(struct Device *pDevice, NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS *pNvjpgCapsParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS deviceCtrlCmdNvjpgGetCapsV2_DISPATCH(struct Device *pDevice, NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS *pNvjpgCapsParams) { return pDevice->__deviceCtrlCmdNvjpgGetCapsV2__(pDevice, pNvjpgCapsParams); @@ -703,10 +762,6 @@ static inline void deviceControl_Epilogue_DISPATCH(struct Device *pResource, str pResource->__deviceControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS deviceControlLookup_DISPATCH(struct Device *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__deviceControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle deviceGetInternalObjectHandle_DISPATCH(struct Device *pGpuResource) { return pGpuResource->__deviceGetInternalObjectHandle__(pGpuResource); } @@ -735,6 +790,10 @@ static inline NvBool deviceCanCopy_DISPATCH(struct Device *pResource) { return pResource->__deviceCanCopy__(pResource); } +static inline NvBool deviceIsPartialUnmapSupported_DISPATCH(struct Device *pResource) { + return pResource->__deviceIsPartialUnmapSupported__(pResource); +} + static inline void devicePreDestruct_DISPATCH(struct Device *pResource) { pResource->__devicePreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_disp_capabilities_nvoc.c b/src/nvidia/generated/g_disp_capabilities_nvoc.c index c5a8e6742f..66aab01249 100644 --- a/src/nvidia/generated/g_disp_capabilities_nvoc.c +++ b/src/nvidia/generated/g_disp_capabilities_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_dispcapControl_Epilogue(struct DispCapabilit rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispcapControlLookup(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_dispcapGetInternalObjectHandle(struct DispCapabilities *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispCapabilities_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_dispcapCanCopy(struct DispCapabilities *pR return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispcapIsPartialUnmapSupported(struct DispCapabilities *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispcapPreDestruct(struct DispCapabilities *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCapabilities_RsResource.offset)); } @@ -255,8 +255,6 @@ static void __nvoc_init_funcTable_DispCapabilities_1(DispCapabilities *pThis) { pThis->__dispcapControl_Epilogue__ = &__nvoc_thunk_RmResource_dispcapControl_Epilogue; - pThis->__dispcapControlLookup__ = &__nvoc_thunk_RsResource_dispcapControlLookup; - pThis->__dispcapGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispcapGetInternalObjectHandle; pThis->__dispcapControl__ = &__nvoc_thunk_GpuResource_dispcapControl; @@ -273,6 +271,8 @@ static void __nvoc_init_funcTable_DispCapabilities_1(DispCapabilities *pThis) { pThis->__dispcapCanCopy__ = &__nvoc_thunk_RsResource_dispcapCanCopy; + pThis->__dispcapIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispcapIsPartialUnmapSupported; + pThis->__dispcapPreDestruct__ = &__nvoc_thunk_RsResource_dispcapPreDestruct; pThis->__dispcapIsDuplicate__ = &__nvoc_thunk_RsResource_dispcapIsDuplicate; @@ -300,21 +300,26 @@ void __nvoc_init_DispCapabilities(DispCapabilities *pThis) { __nvoc_init_funcTable_DispCapabilities(pThis); } -NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispCapabilities *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispCapabilities), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispCapabilities)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispCapabilities); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -329,16 +334,25 @@ NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities **ppThis, Dynamic * status = __nvoc_ctor_DispCapabilities(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DispCapabilities_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispCapabilities_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispCapabilities)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_disp_capabilities_nvoc.h b/src/nvidia/generated/g_disp_capabilities_nvoc.h index e1bf07f37d..accfcbaf8f 100644 --- a/src/nvidia/generated/g_disp_capabilities_nvoc.h +++ b/src/nvidia/generated/g_disp_capabilities_nvoc.h @@ -46,11 +46,16 @@ extern "C" { /*! * RM internal class representing NVXXXX_DISP_CAPABILITIES */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_CAPABILITIES_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispCapabilities { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -71,7 +76,6 @@ struct DispCapabilities { NV_STATUS (*__dispcapInternalControlForward__)(struct DispCapabilities *, NvU32, void *, NvU32); NV_STATUS (*__dispcapUnmapFrom__)(struct DispCapabilities *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispcapControl_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispcapControlLookup__)(struct DispCapabilities *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__dispcapGetInternalObjectHandle__)(struct DispCapabilities *); NV_STATUS (*__dispcapControl__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcapUnmap__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -80,6 +84,7 @@ struct DispCapabilities { NV_STATUS (*__dispcapControlFilter__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcapControlSerialization_Prologue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispcapCanCopy__)(struct DispCapabilities *); + NvBool (*__dispcapIsPartialUnmapSupported__)(struct DispCapabilities *); void (*__dispcapPreDestruct__)(struct DispCapabilities *); NV_STATUS (*__dispcapIsDuplicate__)(struct DispCapabilities *, NvHandle, NvBool *); void (*__dispcapControlSerialization_Epilogue__)(struct DispCapabilities *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -128,7 +133,6 @@ NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities**, Dynamic*, NvU32, #define dispcapInternalControlForward(pGpuResource, command, pParams, size) dispcapInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispcapUnmapFrom(pResource, pParams) dispcapUnmapFrom_DISPATCH(pResource, pParams) #define dispcapControl_Epilogue(pResource, pCallContext, pParams) dispcapControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispcapControlLookup(pResource, pParams, ppEntry) dispcapControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispcapGetInternalObjectHandle(pGpuResource) dispcapGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispcapControl(pGpuResource, pCallContext, pParams) dispcapControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispcapUnmap(pGpuResource, pCallContext, pCpuMapping) dispcapUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -137,6 +141,7 @@ NV_STATUS __nvoc_objCreate_DispCapabilities(DispCapabilities**, Dynamic*, NvU32, #define dispcapControlFilter(pResource, pCallContext, pParams) dispcapControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispcapControlSerialization_Prologue(pResource, pCallContext, pParams) dispcapControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispcapCanCopy(pResource) dispcapCanCopy_DISPATCH(pResource) +#define dispcapIsPartialUnmapSupported(pResource) dispcapIsPartialUnmapSupported_DISPATCH(pResource) #define dispcapPreDestruct(pResource) dispcapPreDestruct_DISPATCH(pResource) #define dispcapIsDuplicate(pResource, hMemory, pDuplicate) dispcapIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispcapControlSerialization_Epilogue(pResource, pCallContext, pParams) dispcapControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -188,10 +193,6 @@ static inline void dispcapControl_Epilogue_DISPATCH(struct DispCapabilities *pRe pResource->__dispcapControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispcapControlLookup_DISPATCH(struct DispCapabilities *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispcapControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle dispcapGetInternalObjectHandle_DISPATCH(struct DispCapabilities *pGpuResource) { return pGpuResource->__dispcapGetInternalObjectHandle__(pGpuResource); } @@ -224,6 +225,10 @@ static inline NvBool dispcapCanCopy_DISPATCH(struct DispCapabilities *pResource) return pResource->__dispcapCanCopy__(pResource); } +static inline NvBool dispcapIsPartialUnmapSupported_DISPATCH(struct DispCapabilities *pResource) { + return pResource->__dispcapIsPartialUnmapSupported__(pResource); +} + static inline void dispcapPreDestruct_DISPATCH(struct DispCapabilities *pResource) { pResource->__dispcapPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_disp_channel_nvoc.c b/src/nvidia/generated/g_disp_channel_nvoc.c index e4d8c6c11a..af1f42d0cf 100644 --- a/src/nvidia/generated/g_disp_channel_nvoc.c +++ b/src/nvidia/generated/g_disp_channel_nvoc.c @@ -163,10 +163,6 @@ static void __nvoc_thunk_RmResource_dispchnControl_Epilogue(struct DispChannel * rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispchnControlLookup(struct DispChannel *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_dispchnGetInternalObjectHandle(struct DispChannel *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannel_GpuResource.offset)); } @@ -203,6 +199,10 @@ static NvBool __nvoc_thunk_RsResource_dispchnCanCopy(struct DispChannel *pResour return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispchnIsPartialUnmapSupported(struct DispChannel *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispchnPreDestruct(struct DispChannel *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannel_RsResource.offset)); } @@ -305,8 +305,6 @@ static void __nvoc_init_funcTable_DispChannel_1(DispChannel *pThis) { pThis->__dispchnControl_Epilogue__ = &__nvoc_thunk_RmResource_dispchnControl_Epilogue; - pThis->__dispchnControlLookup__ = &__nvoc_thunk_RsResource_dispchnControlLookup; - pThis->__dispchnGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispchnGetInternalObjectHandle; pThis->__dispchnControl__ = &__nvoc_thunk_GpuResource_dispchnControl; @@ -325,6 +323,8 @@ static void __nvoc_init_funcTable_DispChannel_1(DispChannel *pThis) { pThis->__dispchnCanCopy__ = &__nvoc_thunk_RsResource_dispchnCanCopy; + pThis->__dispchnIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispchnIsPartialUnmapSupported; + pThis->__dispchnPreDestruct__ = &__nvoc_thunk_RsResource_dispchnPreDestruct; pThis->__dispchnIsDuplicate__ = &__nvoc_thunk_RsResource_dispchnIsDuplicate; @@ -360,21 +360,26 @@ void __nvoc_init_DispChannel(DispChannel *pThis) { __nvoc_init_funcTable_DispChannel(pThis); } -NV_STATUS __nvoc_objCreate_DispChannel(DispChannel **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams, NvU32 arg_isDma) { +NV_STATUS __nvoc_objCreate_DispChannel(DispChannel **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams, NvU32 arg_isDma) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispChannel *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannel), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispChannel)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannel); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -389,16 +394,25 @@ NV_STATUS __nvoc_objCreate_DispChannel(DispChannel **ppThis, Dynamic *pParent, N status = __nvoc_ctor_DispChannel(pThis, arg_pCallContext, arg_pParams, arg_isDma); if (status != NV_OK) goto __nvoc_objCreate_DispChannel_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispChannel_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispChannel)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -580,10 +594,6 @@ static void __nvoc_thunk_RmResource_dispchnpioControl_Epilogue(struct DispChanne rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispchnpioControlLookup(struct DispChannelPio *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_dispchnpioGetInternalObjectHandle(struct DispChannelPio *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannelPio_GpuResource.offset)); } @@ -620,6 +630,10 @@ static NvBool __nvoc_thunk_RsResource_dispchnpioCanCopy(struct DispChannelPio *p return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispchnpioIsPartialUnmapSupported(struct DispChannelPio *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispchnpioPreDestruct(struct DispChannelPio *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelPio_RsResource.offset)); } @@ -712,8 +726,6 @@ static void __nvoc_init_funcTable_DispChannelPio_1(DispChannelPio *pThis) { pThis->__dispchnpioControl_Epilogue__ = &__nvoc_thunk_RmResource_dispchnpioControl_Epilogue; - pThis->__dispchnpioControlLookup__ = &__nvoc_thunk_RsResource_dispchnpioControlLookup; - pThis->__dispchnpioGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispchnpioGetInternalObjectHandle; pThis->__dispchnpioControl__ = &__nvoc_thunk_GpuResource_dispchnpioControl; @@ -732,6 +744,8 @@ static void __nvoc_init_funcTable_DispChannelPio_1(DispChannelPio *pThis) { pThis->__dispchnpioCanCopy__ = &__nvoc_thunk_RsResource_dispchnpioCanCopy; + pThis->__dispchnpioIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispchnpioIsPartialUnmapSupported; + pThis->__dispchnpioPreDestruct__ = &__nvoc_thunk_RsResource_dispchnpioPreDestruct; pThis->__dispchnpioIsDuplicate__ = &__nvoc_thunk_RsResource_dispchnpioIsDuplicate; @@ -766,21 +780,26 @@ void __nvoc_init_DispChannelPio(DispChannelPio *pThis) { __nvoc_init_funcTable_DispChannelPio(pThis); } -NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispChannelPio *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannelPio), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispChannelPio)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannelPio); pThis->__nvoc_base_DispChannel.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -795,16 +814,25 @@ NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio **ppThis, Dynamic *pPar status = __nvoc_ctor_DispChannelPio(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DispChannelPio_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispChannelPio_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_DispChannel.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispChannelPio)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -985,10 +1013,6 @@ static void __nvoc_thunk_RmResource_dispchndmaControl_Epilogue(struct DispChanne rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispchndmaControlLookup(struct DispChannelDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_dispchndmaGetInternalObjectHandle(struct DispChannelDma *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispChannelDma_GpuResource.offset)); } @@ -1025,6 +1049,10 @@ static NvBool __nvoc_thunk_RsResource_dispchndmaCanCopy(struct DispChannelDma *p return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispchndmaIsPartialUnmapSupported(struct DispChannelDma *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispchndmaPreDestruct(struct DispChannelDma *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispChannelDma_RsResource.offset)); } @@ -1117,8 +1145,6 @@ static void __nvoc_init_funcTable_DispChannelDma_1(DispChannelDma *pThis) { pThis->__dispchndmaControl_Epilogue__ = &__nvoc_thunk_RmResource_dispchndmaControl_Epilogue; - pThis->__dispchndmaControlLookup__ = &__nvoc_thunk_RsResource_dispchndmaControlLookup; - pThis->__dispchndmaGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispchndmaGetInternalObjectHandle; pThis->__dispchndmaControl__ = &__nvoc_thunk_GpuResource_dispchndmaControl; @@ -1137,6 +1163,8 @@ static void __nvoc_init_funcTable_DispChannelDma_1(DispChannelDma *pThis) { pThis->__dispchndmaCanCopy__ = &__nvoc_thunk_RsResource_dispchndmaCanCopy; + pThis->__dispchndmaIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispchndmaIsPartialUnmapSupported; + pThis->__dispchndmaPreDestruct__ = &__nvoc_thunk_RsResource_dispchndmaPreDestruct; pThis->__dispchndmaIsDuplicate__ = &__nvoc_thunk_RsResource_dispchndmaIsDuplicate; @@ -1171,21 +1199,26 @@ void __nvoc_init_DispChannelDma(DispChannelDma *pThis) { __nvoc_init_funcTable_DispChannelDma(pThis); } -NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispChannelDma *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispChannelDma), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispChannelDma)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispChannelDma); pThis->__nvoc_base_DispChannel.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1200,16 +1233,25 @@ NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma **ppThis, Dynamic *pPar status = __nvoc_ctor_DispChannelDma(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DispChannelDma_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispChannelDma_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_DispChannel.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispChannelDma)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_disp_channel_nvoc.h b/src/nvidia/generated/g_disp_channel_nvoc.h index f57fde60c2..d3b2be709b 100644 --- a/src/nvidia/generated/g_disp_channel_nvoc.h +++ b/src/nvidia/generated/g_disp_channel_nvoc.h @@ -72,11 +72,16 @@ typedef struct DispObject DispObject; /*! * Base class for display channels */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_CHANNEL_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispChannel { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -102,7 +107,6 @@ struct DispChannel { NV_STATUS (*__dispchnInternalControlForward__)(struct DispChannel *, NvU32, void *, NvU32); NV_STATUS (*__dispchnUnmapFrom__)(struct DispChannel *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispchnControl_Epilogue__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispchnControlLookup__)(struct DispChannel *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__dispchnGetInternalObjectHandle__)(struct DispChannel *); NV_STATUS (*__dispchnControl__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchnUnmap__)(struct DispChannel *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -112,6 +116,7 @@ struct DispChannel { NV_STATUS (*__dispchnUnregisterEvent__)(struct DispChannel *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__dispchnControlSerialization_Prologue__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchnCanCopy__)(struct DispChannel *); + NvBool (*__dispchnIsPartialUnmapSupported__)(struct DispChannel *); void (*__dispchnPreDestruct__)(struct DispChannel *); NV_STATUS (*__dispchnIsDuplicate__)(struct DispChannel *, NvHandle, NvBool *); void (*__dispchnControlSerialization_Epilogue__)(struct DispChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -170,7 +175,6 @@ NV_STATUS __nvoc_objCreate_DispChannel(DispChannel**, Dynamic*, NvU32, struct CA #define dispchnInternalControlForward(pGpuResource, command, pParams, size) dispchnInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispchnUnmapFrom(pResource, pParams) dispchnUnmapFrom_DISPATCH(pResource, pParams) #define dispchnControl_Epilogue(pResource, pCallContext, pParams) dispchnControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispchnControlLookup(pResource, pParams, ppEntry) dispchnControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispchnGetInternalObjectHandle(pGpuResource) dispchnGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispchnControl(pGpuResource, pCallContext, pParams) dispchnControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispchnUnmap(pGpuResource, pCallContext, pCpuMapping) dispchnUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -180,6 +184,7 @@ NV_STATUS __nvoc_objCreate_DispChannel(DispChannel**, Dynamic*, NvU32, struct CA #define dispchnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispchnControlSerialization_Prologue(pResource, pCallContext, pParams) dispchnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchnCanCopy(pResource) dispchnCanCopy_DISPATCH(pResource) +#define dispchnIsPartialUnmapSupported(pResource) dispchnIsPartialUnmapSupported_DISPATCH(pResource) #define dispchnPreDestruct(pResource) dispchnPreDestruct_DISPATCH(pResource) #define dispchnIsDuplicate(pResource, hMemory, pDuplicate) dispchnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispchnControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -241,10 +246,6 @@ static inline void dispchnControl_Epilogue_DISPATCH(struct DispChannel *pResourc pResource->__dispchnControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispchnControlLookup_DISPATCH(struct DispChannel *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispchnControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle dispchnGetInternalObjectHandle_DISPATCH(struct DispChannel *pGpuResource) { return pGpuResource->__dispchnGetInternalObjectHandle__(pGpuResource); } @@ -281,6 +282,10 @@ static inline NvBool dispchnCanCopy_DISPATCH(struct DispChannel *pResource) { return pResource->__dispchnCanCopy__(pResource); } +static inline NvBool dispchnIsPartialUnmapSupported_DISPATCH(struct DispChannel *pResource) { + return pResource->__dispchnIsPartialUnmapSupported__(pResource); +} + static inline void dispchnPreDestruct_DISPATCH(struct DispChannel *pResource) { pResource->__dispchnPreDestruct__(pResource); } @@ -364,11 +369,16 @@ NV_STATUS dispchnGetByHandle_IMPL(struct RsClient *pClient, NvHandle hDisplayCha /*! * RM internal class representing XXX_XXX_CHANNEL_PIO */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_CHANNEL_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispChannelPio { const struct NVOC_RTTI *__nvoc_rtti; struct DispChannel __nvoc_base_DispChannel; @@ -394,7 +404,6 @@ struct DispChannelPio { NV_STATUS (*__dispchnpioInternalControlForward__)(struct DispChannelPio *, NvU32, void *, NvU32); NV_STATUS (*__dispchnpioUnmapFrom__)(struct DispChannelPio *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispchnpioControl_Epilogue__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispchnpioControlLookup__)(struct DispChannelPio *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__dispchnpioGetInternalObjectHandle__)(struct DispChannelPio *); NV_STATUS (*__dispchnpioControl__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchnpioUnmap__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -404,6 +413,7 @@ struct DispChannelPio { NV_STATUS (*__dispchnpioUnregisterEvent__)(struct DispChannelPio *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__dispchnpioControlSerialization_Prologue__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchnpioCanCopy__)(struct DispChannelPio *); + NvBool (*__dispchnpioIsPartialUnmapSupported__)(struct DispChannelPio *); void (*__dispchnpioPreDestruct__)(struct DispChannelPio *); NV_STATUS (*__dispchnpioIsDuplicate__)(struct DispChannelPio *, NvHandle, NvBool *); void (*__dispchnpioControlSerialization_Epilogue__)(struct DispChannelPio *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -454,7 +464,6 @@ NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio**, Dynamic*, NvU32, str #define dispchnpioInternalControlForward(pGpuResource, command, pParams, size) dispchnpioInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispchnpioUnmapFrom(pResource, pParams) dispchnpioUnmapFrom_DISPATCH(pResource, pParams) #define dispchnpioControl_Epilogue(pResource, pCallContext, pParams) dispchnpioControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispchnpioControlLookup(pResource, pParams, ppEntry) dispchnpioControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispchnpioGetInternalObjectHandle(pGpuResource) dispchnpioGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispchnpioControl(pGpuResource, pCallContext, pParams) dispchnpioControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispchnpioUnmap(pGpuResource, pCallContext, pCpuMapping) dispchnpioUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -464,6 +473,7 @@ NV_STATUS __nvoc_objCreate_DispChannelPio(DispChannelPio**, Dynamic*, NvU32, str #define dispchnpioUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchnpioUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispchnpioControlSerialization_Prologue(pResource, pCallContext, pParams) dispchnpioControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchnpioCanCopy(pResource) dispchnpioCanCopy_DISPATCH(pResource) +#define dispchnpioIsPartialUnmapSupported(pResource) dispchnpioIsPartialUnmapSupported_DISPATCH(pResource) #define dispchnpioPreDestruct(pResource) dispchnpioPreDestruct_DISPATCH(pResource) #define dispchnpioIsDuplicate(pResource, hMemory, pDuplicate) dispchnpioIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispchnpioControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchnpioControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -523,10 +533,6 @@ static inline void dispchnpioControl_Epilogue_DISPATCH(struct DispChannelPio *pR pResource->__dispchnpioControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispchnpioControlLookup_DISPATCH(struct DispChannelPio *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispchnpioControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle dispchnpioGetInternalObjectHandle_DISPATCH(struct DispChannelPio *pGpuResource) { return pGpuResource->__dispchnpioGetInternalObjectHandle__(pGpuResource); } @@ -563,6 +569,10 @@ static inline NvBool dispchnpioCanCopy_DISPATCH(struct DispChannelPio *pResource return pResource->__dispchnpioCanCopy__(pResource); } +static inline NvBool dispchnpioIsPartialUnmapSupported_DISPATCH(struct DispChannelPio *pResource) { + return pResource->__dispchnpioIsPartialUnmapSupported__(pResource); +} + static inline void dispchnpioPreDestruct_DISPATCH(struct DispChannelPio *pResource) { pResource->__dispchnpioPreDestruct__(pResource); } @@ -600,11 +610,16 @@ NV_STATUS dispchnpioConstruct_IMPL(struct DispChannelPio *arg_pDispChannelPio, s /*! * RM internal class representing XXX_XXX_CHANNEL_DMA */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_CHANNEL_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispChannelDma { const struct NVOC_RTTI *__nvoc_rtti; struct DispChannel __nvoc_base_DispChannel; @@ -630,7 +645,6 @@ struct DispChannelDma { NV_STATUS (*__dispchndmaInternalControlForward__)(struct DispChannelDma *, NvU32, void *, NvU32); NV_STATUS (*__dispchndmaUnmapFrom__)(struct DispChannelDma *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispchndmaControl_Epilogue__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispchndmaControlLookup__)(struct DispChannelDma *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__dispchndmaGetInternalObjectHandle__)(struct DispChannelDma *); NV_STATUS (*__dispchndmaControl__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispchndmaUnmap__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -640,6 +654,7 @@ struct DispChannelDma { NV_STATUS (*__dispchndmaUnregisterEvent__)(struct DispChannelDma *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__dispchndmaControlSerialization_Prologue__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispchndmaCanCopy__)(struct DispChannelDma *); + NvBool (*__dispchndmaIsPartialUnmapSupported__)(struct DispChannelDma *); void (*__dispchndmaPreDestruct__)(struct DispChannelDma *); NV_STATUS (*__dispchndmaIsDuplicate__)(struct DispChannelDma *, NvHandle, NvBool *); void (*__dispchndmaControlSerialization_Epilogue__)(struct DispChannelDma *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -690,7 +705,6 @@ NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma**, Dynamic*, NvU32, str #define dispchndmaInternalControlForward(pGpuResource, command, pParams, size) dispchndmaInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispchndmaUnmapFrom(pResource, pParams) dispchndmaUnmapFrom_DISPATCH(pResource, pParams) #define dispchndmaControl_Epilogue(pResource, pCallContext, pParams) dispchndmaControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispchndmaControlLookup(pResource, pParams, ppEntry) dispchndmaControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispchndmaGetInternalObjectHandle(pGpuResource) dispchndmaGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispchndmaControl(pGpuResource, pCallContext, pParams) dispchndmaControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispchndmaUnmap(pGpuResource, pCallContext, pCpuMapping) dispchndmaUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -700,6 +714,7 @@ NV_STATUS __nvoc_objCreate_DispChannelDma(DispChannelDma**, Dynamic*, NvU32, str #define dispchndmaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispchndmaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispchndmaControlSerialization_Prologue(pResource, pCallContext, pParams) dispchndmaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispchndmaCanCopy(pResource) dispchndmaCanCopy_DISPATCH(pResource) +#define dispchndmaIsPartialUnmapSupported(pResource) dispchndmaIsPartialUnmapSupported_DISPATCH(pResource) #define dispchndmaPreDestruct(pResource) dispchndmaPreDestruct_DISPATCH(pResource) #define dispchndmaIsDuplicate(pResource, hMemory, pDuplicate) dispchndmaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispchndmaControlSerialization_Epilogue(pResource, pCallContext, pParams) dispchndmaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -759,10 +774,6 @@ static inline void dispchndmaControl_Epilogue_DISPATCH(struct DispChannelDma *pR pResource->__dispchndmaControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispchndmaControlLookup_DISPATCH(struct DispChannelDma *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispchndmaControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle dispchndmaGetInternalObjectHandle_DISPATCH(struct DispChannelDma *pGpuResource) { return pGpuResource->__dispchndmaGetInternalObjectHandle__(pGpuResource); } @@ -799,6 +810,10 @@ static inline NvBool dispchndmaCanCopy_DISPATCH(struct DispChannelDma *pResource return pResource->__dispchndmaCanCopy__(pResource); } +static inline NvBool dispchndmaIsPartialUnmapSupported_DISPATCH(struct DispChannelDma *pResource) { + return pResource->__dispchndmaIsPartialUnmapSupported__(pResource); +} + static inline void dispchndmaPreDestruct_DISPATCH(struct DispChannelDma *pResource) { pResource->__dispchndmaPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.c b/src/nvidia/generated/g_disp_inst_mem_nvoc.c index f19fab2c4c..a6cd516c0e 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.c +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.c @@ -189,23 +189,31 @@ void __nvoc_init_DisplayInstanceMemory(DisplayInstanceMemory *pThis, RmHalspecOw __nvoc_init_funcTable_DisplayInstanceMemory(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_DisplayInstanceMemory(DisplayInstanceMemory **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_DisplayInstanceMemory(DisplayInstanceMemory **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DisplayInstanceMemory *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DisplayInstanceMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DisplayInstanceMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DisplayInstanceMemory); pThis->__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_Object); @@ -223,16 +231,25 @@ NV_STATUS __nvoc_objCreate_DisplayInstanceMemory(DisplayInstanceMemory **ppThis, status = __nvoc_ctor_DisplayInstanceMemory(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_DisplayInstanceMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DisplayInstanceMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DisplayInstanceMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_disp_inst_mem_nvoc.h b/src/nvidia/generated/g_disp_inst_mem_nvoc.h index 1125df9b2d..00e8dd86aa 100644 --- a/src/nvidia/generated/g_disp_inst_mem_nvoc.h +++ b/src/nvidia/generated/g_disp_inst_mem_nvoc.h @@ -82,11 +82,16 @@ typedef struct struct DispChannel *pDispChannel; } SW_HASH_TABLE_ENTRY; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_INST_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DisplayInstanceMemory { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_disp_objs_nvoc.c b/src/nvidia/generated/g_disp_objs_nvoc.c index c8fa41b62b..7d66dfad09 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.c +++ b/src/nvidia/generated/g_disp_objs_nvoc.c @@ -146,10 +146,6 @@ static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmapFrom(struct DisplayApi *pRe return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispapiControlLookup(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_dispapiUnmap(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset), pCallContext, pCpuMapping); } @@ -178,6 +174,10 @@ static NvBool __nvoc_thunk_RsResource_dispapiCanCopy(struct DisplayApi *pResourc return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispapiIsPartialUnmapSupported(struct DisplayApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispapiPreDestruct(struct DisplayApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DisplayApi_RsResource.offset)); } @@ -290,8 +290,6 @@ static void __nvoc_init_funcTable_DisplayApi_1(DisplayApi *pThis, RmHalspecOwner pThis->__dispapiUnmapFrom__ = &__nvoc_thunk_RsResource_dispapiUnmapFrom; - pThis->__dispapiControlLookup__ = &__nvoc_thunk_RsResource_dispapiControlLookup; - pThis->__dispapiUnmap__ = &__nvoc_thunk_RsResource_dispapiUnmap; pThis->__dispapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_dispapiGetMemInterMapParams; @@ -306,6 +304,8 @@ static void __nvoc_init_funcTable_DisplayApi_1(DisplayApi *pThis, RmHalspecOwner pThis->__dispapiCanCopy__ = &__nvoc_thunk_RsResource_dispapiCanCopy; + pThis->__dispapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispapiIsPartialUnmapSupported; + pThis->__dispapiPreDestruct__ = &__nvoc_thunk_RsResource_dispapiPreDestruct; pThis->__dispapiIsDuplicate__ = &__nvoc_thunk_RsResource_dispapiIsDuplicate; @@ -340,23 +340,31 @@ void __nvoc_init_DisplayApi(DisplayApi *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_DisplayApi(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DisplayApi *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DisplayApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DisplayApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DisplayApi); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -374,16 +382,25 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_DisplayApi(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DisplayApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DisplayApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DisplayApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -543,10 +560,6 @@ static void __nvoc_thunk_DisplayApi_dispobjControl_Epilogue(struct DispObject *p dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispobjControlLookup(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_DisplayApi_dispobjControl(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispObject_DisplayApi.offset), pCallContext, pParams); } @@ -579,6 +592,10 @@ static NvBool __nvoc_thunk_RsResource_dispobjCanCopy(struct DispObject *pResourc return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispobjIsPartialUnmapSupported(struct DispObject *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispobjPreDestruct(struct DispObject *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispObject_RsResource.offset)); } @@ -1235,8 +1252,6 @@ static void __nvoc_init_funcTable_DispObject_1(DispObject *pThis, RmHalspecOwner pThis->__dispobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispobjControl_Epilogue; - pThis->__dispobjControlLookup__ = &__nvoc_thunk_RsResource_dispobjControlLookup; - pThis->__dispobjControl__ = &__nvoc_thunk_DisplayApi_dispobjControl; pThis->__dispobjUnmap__ = &__nvoc_thunk_RsResource_dispobjUnmap; @@ -1253,6 +1268,8 @@ static void __nvoc_init_funcTable_DispObject_1(DispObject *pThis, RmHalspecOwner pThis->__dispobjCanCopy__ = &__nvoc_thunk_RsResource_dispobjCanCopy; + pThis->__dispobjIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispobjIsPartialUnmapSupported; + pThis->__dispobjPreDestruct__ = &__nvoc_thunk_RsResource_dispobjPreDestruct; pThis->__dispobjIsDuplicate__ = &__nvoc_thunk_RsResource_dispobjIsDuplicate; @@ -1286,23 +1303,31 @@ void __nvoc_init_DispObject(DispObject *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_DispObject(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_DispObject(DispObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DispObject(DispObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispObject *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispObject), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispObject)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispObject); pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -1320,16 +1345,25 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_DispObject(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DispObject_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispObject_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispObject)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -1498,10 +1532,6 @@ static void __nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue(struct NvDispApi * dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_RsResource_nvdispapiControlLookup(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_DisplayApi_nvdispapiControl(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_NvDispApi_DisplayApi.offset), pCallContext, pParams); } @@ -1534,6 +1564,10 @@ static NvBool __nvoc_thunk_RsResource_nvdispapiCanCopy(struct NvDispApi *pResour return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_nvdispapiIsPartialUnmapSupported(struct NvDispApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_nvdispapiPreDestruct(struct NvDispApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvDispApi_RsResource.offset)); } @@ -1762,8 +1796,6 @@ static void __nvoc_init_funcTable_NvDispApi_1(NvDispApi *pThis) { pThis->__nvdispapiControl_Epilogue__ = &__nvoc_thunk_DisplayApi_nvdispapiControl_Epilogue; - pThis->__nvdispapiControlLookup__ = &__nvoc_thunk_RsResource_nvdispapiControlLookup; - pThis->__nvdispapiControl__ = &__nvoc_thunk_DisplayApi_nvdispapiControl; pThis->__nvdispapiUnmap__ = &__nvoc_thunk_RsResource_nvdispapiUnmap; @@ -1780,6 +1812,8 @@ static void __nvoc_init_funcTable_NvDispApi_1(NvDispApi *pThis) { pThis->__nvdispapiCanCopy__ = &__nvoc_thunk_RsResource_nvdispapiCanCopy; + pThis->__nvdispapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_nvdispapiIsPartialUnmapSupported; + pThis->__nvdispapiPreDestruct__ = &__nvoc_thunk_RsResource_nvdispapiPreDestruct; pThis->__nvdispapiIsDuplicate__ = &__nvoc_thunk_RsResource_nvdispapiIsDuplicate; @@ -1814,23 +1848,31 @@ void __nvoc_init_NvDispApi(NvDispApi *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_NvDispApi(pThis); } -NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; NvDispApi *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvDispApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(NvDispApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvDispApi); pThis->__nvoc_base_DispObject.__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_DispObject.__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -1848,16 +1890,25 @@ NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_NvDispApi(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_NvDispApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_NvDispApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_DispObject.__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(NvDispApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -2017,10 +2068,6 @@ static void __nvoc_thunk_DisplayApi_dispswobjControl_Epilogue(struct DispSwObj * dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispswobjControlLookup(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_DisplayApi_dispswobjControl(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispSwObj_DisplayApi.offset), pCallContext, pParams); } @@ -2053,6 +2100,10 @@ static NvBool __nvoc_thunk_RsResource_dispswobjCanCopy(struct DispSwObj *pResour return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispswobjIsPartialUnmapSupported(struct DispSwObj *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispswobjPreDestruct(struct DispSwObj *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObj_RsResource.offset)); } @@ -2224,8 +2275,6 @@ static void __nvoc_init_funcTable_DispSwObj_1(DispSwObj *pThis) { pThis->__dispswobjControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispswobjControl_Epilogue; - pThis->__dispswobjControlLookup__ = &__nvoc_thunk_RsResource_dispswobjControlLookup; - pThis->__dispswobjControl__ = &__nvoc_thunk_DisplayApi_dispswobjControl; pThis->__dispswobjUnmap__ = &__nvoc_thunk_RsResource_dispswobjUnmap; @@ -2242,6 +2291,8 @@ static void __nvoc_init_funcTable_DispSwObj_1(DispSwObj *pThis) { pThis->__dispswobjCanCopy__ = &__nvoc_thunk_RsResource_dispswobjCanCopy; + pThis->__dispswobjIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispswobjIsPartialUnmapSupported; + pThis->__dispswobjPreDestruct__ = &__nvoc_thunk_RsResource_dispswobjPreDestruct; pThis->__dispswobjIsDuplicate__ = &__nvoc_thunk_RsResource_dispswobjIsDuplicate; @@ -2275,23 +2326,31 @@ void __nvoc_init_DispSwObj(DispSwObj *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_DispSwObj(pThis); } -NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispSwObj *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSwObj), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispSwObj)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSwObj); pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -2309,16 +2368,25 @@ NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_DispSwObj(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DispSwObj_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispSwObj_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispSwObj)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -2478,10 +2546,6 @@ static void __nvoc_thunk_DisplayApi_dispcmnControl_Epilogue(struct DispCommon *p dispapiControl_Epilogue((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pRsParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispcmnControlLookup(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_DisplayApi_dispcmnControl(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return dispapiControl((struct DisplayApi *)(((unsigned char *)pDisplayApi) + __nvoc_rtti_DispCommon_DisplayApi.offset), pCallContext, pParams); } @@ -2514,6 +2578,10 @@ static NvBool __nvoc_thunk_RsResource_dispcmnCanCopy(struct DispCommon *pResourc return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispcmnIsPartialUnmapSupported(struct DispCommon *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispcmnPreDestruct(struct DispCommon *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispCommon_RsResource.offset)); } @@ -2999,6 +3067,36 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm #endif }, { /* [30] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdVblankSemControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x73019fu, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdVblankSemControl" +#endif + }, + { /* [31] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdAccelVblankSemControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x7301a2u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdAccelVblankSemControl" +#endif + }, + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3013,7 +3111,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetI2cPortid" #endif }, - { /* [31] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3028,7 +3126,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetType" #endif }, - { /* [32] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3043,7 +3141,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificFakeDevice" #endif }, - { /* [33] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3058,7 +3156,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetEdidV2" #endif }, - { /* [34] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3073,7 +3171,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetEdidV2" #endif }, - { /* [35] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3088,7 +3186,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetConnectorData" #endif }, - { /* [36] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3103,7 +3201,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiEnable" #endif }, - { /* [37] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3118,7 +3216,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificCtrlHdmi" #endif }, - { /* [38] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3133,7 +3231,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiAudioMutestream" #endif }, - { /* [39] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3148,7 +3246,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetAcpiIdMapping" #endif }, - { /* [40] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3163,7 +3261,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetAcpiDodDisplayPortAttachment" #endif }, - { /* [41] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3178,7 +3276,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetAllHeadMask" #endif }, - { /* [42] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3193,7 +3291,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacket" #endif }, - { /* [43] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3208,7 +3306,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetOdPacketCtrl" #endif }, - { /* [44] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3223,7 +3321,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetPclkLimit" #endif }, - { /* [45] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3238,7 +3336,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificOrGetInfo" #endif }, - { /* [46] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3253,7 +3351,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetBacklightBrightness" #endif }, - { /* [47] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3268,7 +3366,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetBacklightBrightness" #endif }, - { /* [48] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3283,7 +3381,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiSinkCaps" #endif }, - { /* [49] */ + { /* [51] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3298,7 +3396,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetMonitorPower" #endif }, - { /* [50] */ + { /* [52] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3313,7 +3411,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig" #endif }, - { /* [51] */ + { /* [53] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3328,7 +3426,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificApplyEdidOverrideV2" #endif }, - { /* [52] */ + { /* [54] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3343,7 +3441,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiGpuCaps" #endif }, - { /* [53] */ + { /* [55] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3358,7 +3456,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDisplayChange" #endif }, - { /* [54] */ + { /* [56] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3373,7 +3471,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetHdmiScdcData" #endif }, - { /* [55] */ + { /* [57] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3388,7 +3486,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificIsDirectmodeDisplay" #endif }, - { /* [56] */ + { /* [58] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3403,7 +3501,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation" #endif }, - { /* [57] */ + { /* [59] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3418,7 +3516,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificSetSharedGenericPacket" #endif }, - { /* [58] */ + { /* [60] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3433,7 +3531,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificAcquireSharedGenericPacket" #endif }, - { /* [59] */ + { /* [61] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3448,7 +3546,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificReleaseSharedGenericPacket" #endif }, - { /* [60] */ + { /* [62] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3463,7 +3561,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDispI2cReadWrite" #endif }, - { /* [61] */ + { /* [63] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3478,7 +3576,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment" #endif }, - { /* [62] */ + { /* [64] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3493,7 +3591,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay" #endif }, - { /* [63] */ + { /* [65] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3508,7 +3606,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdInternalGetHotplugUnplugState" #endif }, - { /* [64] */ + { /* [66] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3523,7 +3621,67 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdInternalVRRSetRgLineActive" #endif }, - { /* [65] */ + { /* [67] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdInternalDfpGetDispMuxStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730404u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdInternalDfpGetDispMuxStatus" +#endif + }, + { /* [68] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdInternalVblankSemControl_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730405u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdInternalVblankSemControl" +#endif + }, + { /* [69] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdInternalDfpSwitchDispMux_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730460u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdInternalDfpSwitchDispMux" +#endif + }, + { /* [70] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdFrlConfigMacroPad_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x730502u, + /*paramSize=*/ sizeof(NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdFrlConfigMacroPad" +#endif + }, + { /* [71] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3538,7 +3696,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetInfo" #endif }, - { /* [66] */ + { /* [72] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3553,7 +3711,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDisplayportDongleInfo" #endif }, - { /* [67] */ + { /* [73] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3568,7 +3726,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetEldAudioCaps" #endif }, - { /* [68] */ + { /* [74] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3583,7 +3741,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetSpreadSpectrum" #endif }, - { /* [69] */ + { /* [75] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3598,7 +3756,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpUpdateDynamicDfpCache" #endif }, - { /* [70] */ + { /* [76] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3613,7 +3771,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSetAudioEnable" #endif }, - { /* [71] */ + { /* [77] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3628,7 +3786,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpAssignSor" #endif }, - { /* [72] */ + { /* [78] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3643,7 +3801,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetPadlinkMask" #endif }, - { /* [73] */ + { /* [79] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3658,7 +3816,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetLcdGpioPinNum" #endif }, - { /* [74] */ + { /* [80] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3673,7 +3831,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpConfigTwoHeadOneOr" #endif }, - { /* [75] */ + { /* [81] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3688,7 +3846,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpDscCrcControl" #endif }, - { /* [76] */ + { /* [82] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3703,13 +3861,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInitMuxData" #endif }, - { /* [77] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + { /* [83] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpSwitchDispMux_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, /*accessRight=*/0x0u, /*methodId=*/ 0x731160u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS), @@ -3718,7 +3876,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpSwitchDispMux" #endif }, - { /* [78] */ + { /* [84] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3733,7 +3891,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPreDispMuxOperations" #endif }, - { /* [79] */ + { /* [85] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3748,13 +3906,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpRunPostDispMuxOperations" #endif }, - { /* [80] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + { /* [86] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpGetDispMuxStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) - /*flags=*/ 0x200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + /*flags=*/ 0x0u, /*accessRight=*/0x0u, /*methodId=*/ 0x731163u, /*paramSize=*/ sizeof(NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS), @@ -3763,7 +3921,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDispMuxStatus" #endif }, - { /* [81] */ + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3778,7 +3936,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetDsiModeTiming" #endif }, - { /* [82] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x202u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3793,7 +3951,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpGetFixedModeTiming" #endif }, - { /* [83] */ + { /* [89] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdDfpEdpDriverUnload_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + /*flags=*/ 0x212u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x731174u, + /*paramSize=*/ sizeof(NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "dispcmnCtrlCmdDfpEdpDriverUnload" +#endif + }, + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3808,7 +3981,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchCtrl" #endif }, - { /* [84] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3823,7 +3996,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchSetSema" #endif }, - { /* [85] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3838,7 +4011,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpCtrl" #endif }, - { /* [86] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3853,7 +4026,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLaneData" #endif }, - { /* [87] */ + { /* [94] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3868,7 +4041,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetLaneData" #endif }, - { /* [88] */ + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3883,7 +4056,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTestpattern" #endif }, - { /* [89] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3898,7 +4071,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [90] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3913,7 +4086,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data" #endif }, - { /* [91] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3928,7 +4101,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpMainLinkCtrl" #endif }, - { /* [92] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3943,7 +4116,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAudioMuteStream" #endif }, - { /* [93] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3958,7 +4131,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetAudioMuteStream" #endif }, - { /* [94] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3973,7 +4146,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpASSRCtrl" #endif }, - { /* [95] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3988,7 +4161,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyAllocateDisplayId" #endif }, - { /* [96] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4003,7 +4176,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpTopologyFreeDisplayId" #endif }, - { /* [97] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4018,7 +4191,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetLinkConfig" #endif }, - { /* [98] */ + { /* [105] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4033,7 +4206,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetEDPData" #endif }, - { /* [99] */ + { /* [106] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4048,7 +4221,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigStream" #endif }, - { /* [100] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4063,7 +4236,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetRateGov" #endif }, - { /* [101] */ + { /* [108] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4078,7 +4251,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetManualDisplayPort" #endif }, - { /* [102] */ + { /* [109] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4093,7 +4266,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetEcf" #endif }, - { /* [103] */ + { /* [110] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4108,7 +4281,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSendACT" #endif }, - { /* [104] */ + { /* [111] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x206u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4123,7 +4296,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetCaps" #endif }, - { /* [105] */ + { /* [112] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4138,7 +4311,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGenerateFakeInterrupt" #endif }, - { /* [106] */ + { /* [113] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4153,7 +4326,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigRadScratchReg" #endif }, - { /* [107] */ + { /* [114] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4168,7 +4341,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigSingleHeadMultiStream" #endif }, - { /* [108] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4183,7 +4356,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerSelect" #endif }, - { /* [109] */ + { /* [116] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4198,7 +4371,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetTriggerAll" #endif }, - { /* [110] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4213,7 +4386,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetAuxLogData" #endif }, - { /* [111] */ + { /* [118] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4228,7 +4401,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigIndexedLinkRates" #endif }, - { /* [112] */ + { /* [119] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4243,7 +4416,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetStereoMSAProperties" #endif }, - { /* [113] */ + { /* [120] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4258,7 +4431,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigureFec" #endif }, - { /* [114] */ + { /* [121] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4273,7 +4446,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpConfigMacroPad" #endif }, - { /* [115] */ + { /* [122] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4288,7 +4461,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpAuxchI2cTransferCtrl" #endif }, - { /* [116] */ + { /* [123] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4303,7 +4476,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpEnableVrr" #endif }, - { /* [117] */ + { /* [124] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4318,7 +4491,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetGenericInfoframe" #endif }, - { /* [118] */ + { /* [125] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4333,7 +4506,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpGetMsaAttributes" #endif }, - { /* [119] */ + { /* [126] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4348,7 +4521,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpInternalLcdOverdrive" #endif }, - { /* [120] */ + { /* [127] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4363,7 +4536,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDpSetMSAPropertiesv2" #endif }, - { /* [121] */ + { /* [128] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4378,7 +4551,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy" #endif }, - { /* [122] */ + { /* [129] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4393,7 +4566,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm /*func=*/ "dispcmnCtrlCmdPsrGetSrPanelInfo" #endif }, - { /* [123] */ + { /* [130] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4413,7 +4586,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm const struct NVOC_EXPORT_INFO __nvoc_export_info_DispCommon = { - /*numEntries=*/ 124, + /*numEntries=*/ 131, /*pExportEntries=*/ __nvoc_exported_method_def_DispCommon }; @@ -4485,6 +4658,18 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdInternalVRRSetRgLineActive__ = &dispcmnCtrlCmdInternalVRRSetRgLineActive_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) + pThis->__dispcmnCtrlCmdVblankSemControl__ = &dispcmnCtrlCmdVblankSemControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__dispcmnCtrlCmdInternalVblankSemControl__ = &dispcmnCtrlCmdInternalVblankSemControl_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__dispcmnCtrlCmdAccelVblankSemControl__ = &dispcmnCtrlCmdAccelVblankSemControl_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8204u) pThis->__dispcmnCtrlCmdDpEnableVrr__ = &dispcmnCtrlCmdDpEnableVrr_IMPL; #endif @@ -4541,10 +4726,14 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdPsrGetSrPanelInfo__ = &dispcmnCtrlCmdPsrGetSrPanelInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) pThis->__dispcmnCtrlCmdDfpSwitchDispMux__ = &dispcmnCtrlCmdDfpSwitchDispMux_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__dispcmnCtrlCmdInternalDfpSwitchDispMux__ = &dispcmnCtrlCmdInternalDfpSwitchDispMux_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__dispcmnCtrlCmdDfpRunPreDispMuxOperations__ = &dispcmnCtrlCmdDfpRunPreDispMuxOperations_IMPL; #endif @@ -4553,10 +4742,14 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDfpRunPostDispMuxOperations__ = &dispcmnCtrlCmdDfpRunPostDispMuxOperations_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) pThis->__dispcmnCtrlCmdDfpGetDispMuxStatus__ = &dispcmnCtrlCmdDfpGetDispMuxStatus_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__dispcmnCtrlCmdInternalDfpGetDispMuxStatus__ = &dispcmnCtrlCmdInternalDfpGetDispMuxStatus_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDfpInternalLcdOverdrive__ = &dispcmnCtrlCmdDfpInternalLcdOverdrive_IMPL; #endif @@ -4769,6 +4962,10 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__ = &dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) + pThis->__dispcmnCtrlCmdDfpEdpDriverUnload__ = &dispcmnCtrlCmdDfpEdpDriverUnload_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__dispcmnCtrlCmdDfpGetInfo__ = &dispcmnCtrlCmdDfpGetInfo_IMPL; #endif @@ -4933,6 +5130,10 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCtrlCmdDpGetMsaAttributes__ = &dispcmnCtrlCmdDpGetMsaAttributes_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__dispcmnCtrlCmdFrlConfigMacroPad__ = &dispcmnCtrlCmdFrlConfigMacroPad_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) pThis->__dispcmnCtrlCmdDpConfigMacroPad__ = &dispcmnCtrlCmdDpConfigMacroPad_IMPL; #endif @@ -4965,8 +5166,6 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnControl_Epilogue__ = &__nvoc_thunk_DisplayApi_dispcmnControl_Epilogue; - pThis->__dispcmnControlLookup__ = &__nvoc_thunk_RsResource_dispcmnControlLookup; - pThis->__dispcmnControl__ = &__nvoc_thunk_DisplayApi_dispcmnControl; pThis->__dispcmnUnmap__ = &__nvoc_thunk_RsResource_dispcmnUnmap; @@ -4983,6 +5182,8 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) { pThis->__dispcmnCanCopy__ = &__nvoc_thunk_RsResource_dispcmnCanCopy; + pThis->__dispcmnIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispcmnIsPartialUnmapSupported; + pThis->__dispcmnPreDestruct__ = &__nvoc_thunk_RsResource_dispcmnPreDestruct; pThis->__dispcmnIsDuplicate__ = &__nvoc_thunk_RsResource_dispcmnIsDuplicate; @@ -5016,23 +5217,31 @@ void __nvoc_init_DispCommon(DispCommon *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_DispCommon(pThis); } -NV_STATUS __nvoc_objCreate_DispCommon(DispCommon **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DispCommon(DispCommon **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispCommon *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispCommon), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispCommon)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispCommon); pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -5050,16 +5259,25 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_DispCommon(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DispCommon_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispCommon_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_DisplayApi.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispCommon)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_disp_objs_nvoc.h b/src/nvidia/generated/g_disp_objs_nvoc.h index 4952c8ec23..040c03f7ca 100644 --- a/src/nvidia/generated/g_disp_objs_nvoc.h +++ b/src/nvidia/generated/g_disp_objs_nvoc.h @@ -55,6 +55,7 @@ extern "C" { #include "ctrl/ctrlc370/ctrlc370chnc.h" #include "ctrl/ctrlc370/ctrlc370event.h" #include "ctrl/ctrlc370/ctrlc370rg.h" +#include "ctrl/ctrlc370/ctrlc370or.h" #include "ctrl/ctrlc370/ctrlc370verif.h" #include "ctrl/ctrlc372/ctrlc372base.h" #include "ctrl/ctrlc372/ctrlc372chnc.h" @@ -88,11 +89,16 @@ typedef struct DispChannel DispChannel; /*! * Base class for many of display's RsResource subclasses */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_OBJS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DisplayApi { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -115,7 +121,6 @@ struct DisplayApi { NvU32 (*__dispapiGetRefCount__)(struct DisplayApi *); void (*__dispapiAddAdditionalDependants__)(struct RsClient *, struct DisplayApi *, RsResourceRef *); NV_STATUS (*__dispapiUnmapFrom__)(struct DisplayApi *, RS_RES_UNMAP_FROM_PARAMS *); - NV_STATUS (*__dispapiControlLookup__)(struct DisplayApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispapiUnmap__)(struct DisplayApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispapiGetMemInterMapParams__)(struct DisplayApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__dispapiGetMemoryMappingDescriptor__)(struct DisplayApi *, struct MEMORY_DESCRIPTOR **); @@ -123,6 +128,7 @@ struct DisplayApi { NV_STATUS (*__dispapiUnregisterEvent__)(struct DisplayApi *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__dispapiControlSerialization_Prologue__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispapiCanCopy__)(struct DisplayApi *); + NvBool (*__dispapiIsPartialUnmapSupported__)(struct DisplayApi *); void (*__dispapiPreDestruct__)(struct DisplayApi *); NV_STATUS (*__dispapiIsDuplicate__)(struct DisplayApi *, NvHandle, NvBool *); void (*__dispapiControlSerialization_Epilogue__)(struct DisplayApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -178,7 +184,6 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi**, Dynamic*, NvU32, struct CALL #define dispapiGetRefCount(pResource) dispapiGetRefCount_DISPATCH(pResource) #define dispapiAddAdditionalDependants(pClient, pResource, pReference) dispapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define dispapiUnmapFrom(pResource, pParams) dispapiUnmapFrom_DISPATCH(pResource, pParams) -#define dispapiControlLookup(pResource, pParams, ppEntry) dispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispapiUnmap(pResource, pCallContext, pCpuMapping) dispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispapiGetMemInterMapParams(pRmResource, pParams) dispapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define dispapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) dispapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) @@ -186,6 +191,7 @@ NV_STATUS __nvoc_objCreate_DisplayApi(DisplayApi**, Dynamic*, NvU32, struct CALL #define dispapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispapiControlSerialization_Prologue(pResource, pCallContext, pParams) dispapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispapiCanCopy(pResource) dispapiCanCopy_DISPATCH(pResource) +#define dispapiIsPartialUnmapSupported(pResource) dispapiIsPartialUnmapSupported_DISPATCH(pResource) #define dispapiPreDestruct(pResource) dispapiPreDestruct_DISPATCH(pResource) #define dispapiIsDuplicate(pResource, hMemory, pDuplicate) dispapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispapiControlSerialization_Epilogue(pResource, pCallContext, pParams) dispapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -257,10 +263,6 @@ static inline NV_STATUS dispapiUnmapFrom_DISPATCH(struct DisplayApi *pResource, return pResource->__dispapiUnmapFrom__(pResource, pParams); } -static inline NV_STATUS dispapiControlLookup_DISPATCH(struct DisplayApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispapiUnmap_DISPATCH(struct DisplayApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__dispapiUnmap__(pResource, pCallContext, pCpuMapping); } @@ -289,6 +291,10 @@ static inline NvBool dispapiCanCopy_DISPATCH(struct DisplayApi *pResource) { return pResource->__dispapiCanCopy__(pResource); } +static inline NvBool dispapiIsPartialUnmapSupported_DISPATCH(struct DisplayApi *pResource) { + return pResource->__dispapiIsPartialUnmapSupported__(pResource); +} + static inline void dispapiPreDestruct_DISPATCH(struct DisplayApi *pResource) { pResource->__dispapiPreDestruct__(pResource); } @@ -344,11 +350,16 @@ static inline NV_STATUS dispapiCtrlCmdEventSetNotification(struct DisplayApi *pD * Only one instance of this class is allowed per-GPU. Multi-instance restrictions * are enforced by resource_list.h */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_OBJS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispObject { const struct NVOC_RTTI *__nvoc_rtti; struct DisplayApi __nvoc_base_DisplayApi; @@ -399,7 +410,6 @@ struct DispObject { NV_STATUS (*__dispobjControl_Prologue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispobjUnmapFrom__)(struct DispObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispobjControl_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispobjControlLookup__)(struct DispObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispobjControl__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispobjUnmap__)(struct DispObject *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispobjGetMemInterMapParams__)(struct DispObject *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -408,6 +418,7 @@ struct DispObject { NV_STATUS (*__dispobjUnregisterEvent__)(struct DispObject *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__dispobjControlSerialization_Prologue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispobjCanCopy__)(struct DispObject *); + NvBool (*__dispobjIsPartialUnmapSupported__)(struct DispObject *); void (*__dispobjPreDestruct__)(struct DispObject *); NV_STATUS (*__dispobjIsDuplicate__)(struct DispObject *, NvHandle, NvBool *); void (*__dispobjControlSerialization_Epilogue__)(struct DispObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -485,7 +496,6 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject**, Dynamic*, NvU32, struct CALL #define dispobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispobjUnmapFrom(pResource, pParams) dispobjUnmapFrom_DISPATCH(pResource, pParams) #define dispobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) -#define dispobjControlLookup(pResource, pParams, ppEntry) dispobjControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispobjControl(pDisplayApi, pCallContext, pParams) dispobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) #define dispobjUnmap(pResource, pCallContext, pCpuMapping) dispobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispobjGetMemInterMapParams(pRmResource, pParams) dispobjGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -494,6 +504,7 @@ NV_STATUS __nvoc_objCreate_DispObject(DispObject**, Dynamic*, NvU32, struct CALL #define dispobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispobjControlSerialization_Prologue(pResource, pCallContext, pParams) dispobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispobjCanCopy(pResource) dispobjCanCopy_DISPATCH(pResource) +#define dispobjIsPartialUnmapSupported(pResource) dispobjIsPartialUnmapSupported_DISPATCH(pResource) #define dispobjPreDestruct(pResource) dispobjPreDestruct_DISPATCH(pResource) #define dispobjIsDuplicate(pResource, hMemory, pDuplicate) dispobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispobjControlSerialization_Epilogue(pResource, pCallContext, pParams) dispobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -729,10 +740,6 @@ static inline void dispobjControl_Epilogue_DISPATCH(struct DispObject *pDisplayA pDisplayApi->__dispobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispobjControlLookup_DISPATCH(struct DispObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispobjControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispobjControl_DISPATCH(struct DispObject *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pDisplayApi->__dispobjControl__(pDisplayApi, pCallContext, pParams); } @@ -765,6 +772,10 @@ static inline NvBool dispobjCanCopy_DISPATCH(struct DispObject *pResource) { return pResource->__dispobjCanCopy__(pResource); } +static inline NvBool dispobjIsPartialUnmapSupported_DISPATCH(struct DispObject *pResource) { + return pResource->__dispobjIsPartialUnmapSupported__(pResource); +} + static inline void dispobjPreDestruct_DISPATCH(struct DispObject *pResource) { pResource->__dispobjPreDestruct__(pResource); } @@ -833,11 +844,16 @@ static inline NvBool dispobjGetRmFreeFlags(struct DispObject *pDispObject) { * Only one instance of this class is allowed per-GPU. Multi-instance restrictions * are enforced by resource_list.h */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_OBJS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct NvDispApi { const struct NVOC_RTTI *__nvoc_rtti; struct DispObject __nvoc_base_DispObject; @@ -867,7 +883,6 @@ struct NvDispApi { NV_STATUS (*__nvdispapiControl_Prologue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvdispapiUnmapFrom__)(struct NvDispApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nvdispapiControl_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__nvdispapiControlLookup__)(struct NvDispApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__nvdispapiControl__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nvdispapiUnmap__)(struct NvDispApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__nvdispapiGetMemInterMapParams__)(struct NvDispApi *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -876,6 +891,7 @@ struct NvDispApi { NV_STATUS (*__nvdispapiUnregisterEvent__)(struct NvDispApi *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__nvdispapiControlSerialization_Prologue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvdispapiCanCopy__)(struct NvDispApi *); + NvBool (*__nvdispapiIsPartialUnmapSupported__)(struct NvDispApi *); void (*__nvdispapiPreDestruct__)(struct NvDispApi *); NV_STATUS (*__nvdispapiIsDuplicate__)(struct NvDispApi *, NvHandle, NvBool *); void (*__nvdispapiControlSerialization_Epilogue__)(struct NvDispApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -930,7 +946,6 @@ NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi**, Dynamic*, NvU32, struct CALL_C #define nvdispapiControl_Prologue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define nvdispapiUnmapFrom(pResource, pParams) nvdispapiUnmapFrom_DISPATCH(pResource, pParams) #define nvdispapiControl_Epilogue(pDisplayApi, pCallContext, pRsParams) nvdispapiControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) -#define nvdispapiControlLookup(pResource, pParams, ppEntry) nvdispapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define nvdispapiControl(pDisplayApi, pCallContext, pParams) nvdispapiControl_DISPATCH(pDisplayApi, pCallContext, pParams) #define nvdispapiUnmap(pResource, pCallContext, pCpuMapping) nvdispapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define nvdispapiGetMemInterMapParams(pRmResource, pParams) nvdispapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -939,6 +954,7 @@ NV_STATUS __nvoc_objCreate_NvDispApi(NvDispApi**, Dynamic*, NvU32, struct CALL_C #define nvdispapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvdispapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define nvdispapiControlSerialization_Prologue(pResource, pCallContext, pParams) nvdispapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvdispapiCanCopy(pResource) nvdispapiCanCopy_DISPATCH(pResource) +#define nvdispapiIsPartialUnmapSupported(pResource) nvdispapiIsPartialUnmapSupported_DISPATCH(pResource) #define nvdispapiPreDestruct(pResource) nvdispapiPreDestruct_DISPATCH(pResource) #define nvdispapiIsDuplicate(pResource, hMemory, pDuplicate) nvdispapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define nvdispapiControlSerialization_Epilogue(pResource, pCallContext, pParams) nvdispapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -1028,10 +1044,6 @@ static inline void nvdispapiControl_Epilogue_DISPATCH(struct NvDispApi *pDisplay pDisplayApi->__nvdispapiControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS nvdispapiControlLookup_DISPATCH(struct NvDispApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__nvdispapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS nvdispapiControl_DISPATCH(struct NvDispApi *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pDisplayApi->__nvdispapiControl__(pDisplayApi, pCallContext, pParams); } @@ -1064,6 +1076,10 @@ static inline NvBool nvdispapiCanCopy_DISPATCH(struct NvDispApi *pResource) { return pResource->__nvdispapiCanCopy__(pResource); } +static inline NvBool nvdispapiIsPartialUnmapSupported_DISPATCH(struct NvDispApi *pResource) { + return pResource->__nvdispapiIsPartialUnmapSupported__(pResource); +} + static inline void nvdispapiPreDestruct_DISPATCH(struct NvDispApi *pResource) { pResource->__nvdispapiPreDestruct__(pResource); } @@ -1108,11 +1124,16 @@ NV_STATUS nvdispapiConstruct_IMPL(struct NvDispApi *arg_pNvdispApi, struct CALL_ * * Multi-instance restrictions are enforced by resource_list.h */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_OBJS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispSwObj { const struct NVOC_RTTI *__nvoc_rtti; struct DisplayApi __nvoc_base_DisplayApi; @@ -1138,7 +1159,6 @@ struct DispSwObj { NV_STATUS (*__dispswobjControl_Prologue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispswobjUnmapFrom__)(struct DispSwObj *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispswobjControl_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispswobjControlLookup__)(struct DispSwObj *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispswobjControl__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispswobjUnmap__)(struct DispSwObj *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispswobjGetMemInterMapParams__)(struct DispSwObj *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -1147,6 +1167,7 @@ struct DispSwObj { NV_STATUS (*__dispswobjUnregisterEvent__)(struct DispSwObj *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__dispswobjControlSerialization_Prologue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispswobjCanCopy__)(struct DispSwObj *); + NvBool (*__dispswobjIsPartialUnmapSupported__)(struct DispSwObj *); void (*__dispswobjPreDestruct__)(struct DispSwObj *); NV_STATUS (*__dispswobjIsDuplicate__)(struct DispSwObj *, NvHandle, NvBool *); void (*__dispswobjControlSerialization_Epilogue__)(struct DispSwObj *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -1198,7 +1219,6 @@ NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj**, Dynamic*, NvU32, struct CALL_C #define dispswobjControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispswobjUnmapFrom(pResource, pParams) dispswobjUnmapFrom_DISPATCH(pResource, pParams) #define dispswobjControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispswobjControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) -#define dispswobjControlLookup(pResource, pParams, ppEntry) dispswobjControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispswobjControl(pDisplayApi, pCallContext, pParams) dispswobjControl_DISPATCH(pDisplayApi, pCallContext, pParams) #define dispswobjUnmap(pResource, pCallContext, pCpuMapping) dispswobjUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispswobjGetMemInterMapParams(pRmResource, pParams) dispswobjGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -1207,6 +1227,7 @@ NV_STATUS __nvoc_objCreate_DispSwObj(DispSwObj**, Dynamic*, NvU32, struct CALL_C #define dispswobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispswobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispswobjControlSerialization_Prologue(pResource, pCallContext, pParams) dispswobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispswobjCanCopy(pResource) dispswobjCanCopy_DISPATCH(pResource) +#define dispswobjIsPartialUnmapSupported(pResource) dispswobjIsPartialUnmapSupported_DISPATCH(pResource) #define dispswobjPreDestruct(pResource) dispswobjPreDestruct_DISPATCH(pResource) #define dispswobjIsDuplicate(pResource, hMemory, pDuplicate) dispswobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispswobjControlSerialization_Epilogue(pResource, pCallContext, pParams) dispswobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -1278,10 +1299,6 @@ static inline void dispswobjControl_Epilogue_DISPATCH(struct DispSwObj *pDisplay pDisplayApi->__dispswobjControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispswobjControlLookup_DISPATCH(struct DispSwObj *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispswobjControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispswobjControl_DISPATCH(struct DispSwObj *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pDisplayApi->__dispswobjControl__(pDisplayApi, pCallContext, pParams); } @@ -1314,6 +1331,10 @@ static inline NvBool dispswobjCanCopy_DISPATCH(struct DispSwObj *pResource) { return pResource->__dispswobjCanCopy__(pResource); } +static inline NvBool dispswobjIsPartialUnmapSupported_DISPATCH(struct DispSwObj *pResource) { + return pResource->__dispswobjIsPartialUnmapSupported__(pResource); +} + static inline void dispswobjPreDestruct_DISPATCH(struct DispSwObj *pResource) { pResource->__dispswobjPreDestruct__(pResource); } @@ -1354,11 +1375,16 @@ NV_STATUS dispswobjConstruct_IMPL(struct DispSwObj *arg_pDispSwObj, struct CALL_ * Only one instance of this class is allowed per-GPU. Multi-instance restrictions * are enforced by resource_list.h */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_OBJS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispCommon { const struct NVOC_RTTI *__nvoc_rtti; struct DisplayApi __nvoc_base_DisplayApi; @@ -1379,6 +1405,9 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdSystemVrrDisplayInfo__)(struct DispCommon *, NV0073_CTRL_SYSTEM_VRR_DISPLAY_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdVRRSetRgLineActive__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdInternalVRRSetRgLineActive__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdVblankSemControl__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdInternalVblankSemControl__)(struct DispCommon *, NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdAccelVblankSemControl__)(struct DispCommon *, NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpEnableVrr__)(struct DispCommon *, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdClearELVBlock__)(struct DispCommon *, NV0073_CTRL_SYSTEM_CLEAR_ELV_BLOCK_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificDisplayChange__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISPLAY_CHANGE_PARAMS *); @@ -1394,9 +1423,11 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdSpecificSetBacklightBrightness__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdPsrGetSrPanelInfo__)(struct DispCommon *, NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSwitchDispMux__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdInternalDfpSwitchDispMux__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRunPreDispMuxOperations__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpRunPostDispMuxOperations__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_RUN_POST_DISP_MUX_OPERATIONS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDispMuxStatus__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdInternalDfpGetDispMuxStatus__)(struct DispCommon *, NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpInternalLcdOverdrive__)(struct DispCommon *, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy__)(struct DispCommon *, NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSystemExecuteAcpiMethod__)(struct DispCommon *, NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_PARAMS *); @@ -1450,6 +1481,7 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdSpecificDispI2cReadWrite__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_DISP_I2C_READ_WRITE_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment__)(struct DispCommon *, NV0073_CTRL_SPECIFIC_GET_VALID_HEAD_WINDOW_ASSIGNMENT_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__)(struct DispCommon *, NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdDfpEdpDriverUnload__)(struct DispCommon *, NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpGetDisplayportDongleInfo__)(struct DispCommon *, NV0073_CTRL_DFP_GET_DISPLAYPORT_DONGLE_INFO_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDfpSetEldAudioCaps__)(struct DispCommon *, NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS *); @@ -1491,6 +1523,7 @@ struct DispCommon { NV_STATUS (*__dispcmnCtrlCmdDpConfigureFec__)(struct DispCommon *, NV0073_CTRL_CMD_DP_CONFIGURE_FEC_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGetGenericInfoframe__)(struct DispCommon *, NV0073_CTRL_DP_GET_GENERIC_INFOFRAME_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGetMsaAttributes__)(struct DispCommon *, NV0073_CTRL_DP_GET_MSA_ATTRIBUTES_PARAMS *); + NV_STATUS (*__dispcmnCtrlCmdFrlConfigMacroPad__)(struct DispCommon *, NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpConfigMacroPad__)(struct DispCommon *, NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data__)(struct DispCommon *, NV0073_CTRL_DP_SET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS *); NV_STATUS (*__dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data__)(struct DispCommon *, NV0073_CTRL_DP_GET_PREEMPHASIS_DRIVECURRENT_POSTCURSOR2_DATA_PARAMS *); @@ -1504,7 +1537,6 @@ struct DispCommon { NV_STATUS (*__dispcmnControl_Prologue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcmnUnmapFrom__)(struct DispCommon *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispcmnControl_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispcmnControlLookup__)(struct DispCommon *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__dispcmnControl__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispcmnUnmap__)(struct DispCommon *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__dispcmnGetMemInterMapParams__)(struct DispCommon *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -1513,6 +1545,7 @@ struct DispCommon { NV_STATUS (*__dispcmnUnregisterEvent__)(struct DispCommon *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__dispcmnControlSerialization_Prologue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispcmnCanCopy__)(struct DispCommon *); + NvBool (*__dispcmnIsPartialUnmapSupported__)(struct DispCommon *); void (*__dispcmnPreDestruct__)(struct DispCommon *); NV_STATUS (*__dispcmnIsDuplicate__)(struct DispCommon *, NvHandle, NvBool *); void (*__dispcmnControlSerialization_Epilogue__)(struct DispCommon *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -1561,6 +1594,9 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSystemVrrDisplayInfo(pDispCommon, pParams) dispcmnCtrlCmdSystemVrrDisplayInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdVRRSetRgLineActive(pDispCommon, pParams) dispcmnCtrlCmdVRRSetRgLineActive_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdInternalVRRSetRgLineActive(pDispCommon, pParams) dispcmnCtrlCmdInternalVRRSetRgLineActive_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdVblankSemControl(pDispCommon, pParams) dispcmnCtrlCmdVblankSemControl_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdInternalVblankSemControl(pDispCommon, pParams) dispcmnCtrlCmdInternalVblankSemControl_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdAccelVblankSemControl(pDispCommon, pParams) dispcmnCtrlCmdAccelVblankSemControl_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpEnableVrr(pDispCommon, pParams) dispcmnCtrlCmdDpEnableVrr_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdClearELVBlock(pDispCommon, pParams) dispcmnCtrlCmdClearELVBlock_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificDisplayChange(pDispCommon, pParams) dispcmnCtrlCmdSpecificDisplayChange_DISPATCH(pDispCommon, pParams) @@ -1576,9 +1612,11 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSpecificSetBacklightBrightness(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetBacklightBrightness_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdPsrGetSrPanelInfo(pDispCommon, pParams) dispcmnCtrlCmdPsrGetSrPanelInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSwitchDispMux(pDispCommon, pParams) dispcmnCtrlCmdDfpSwitchDispMux_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdInternalDfpSwitchDispMux(pDispCommon, pParams) dispcmnCtrlCmdInternalDfpSwitchDispMux_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRunPreDispMuxOperations(pDispCommon, pParams) dispcmnCtrlCmdDfpRunPreDispMuxOperations_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpRunPostDispMuxOperations(pDispCommon, pParams) dispcmnCtrlCmdDfpRunPostDispMuxOperations_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDispMuxStatus(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDispMuxStatus_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdInternalDfpGetDispMuxStatus(pDispCommon, pParams) dispcmnCtrlCmdInternalDfpGetDispMuxStatus_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpInternalLcdOverdrive(pDispCommon, pParams) dispcmnCtrlCmdDfpInternalLcdOverdrive_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy(pDispCommon, pParams) dispcmnCtrlCmdDfpExecuteInternalLcdOverDrivePolicy_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSystemExecuteAcpiMethod(pDispCommon, pAcpiMethodParams) dispcmnCtrlCmdSystemExecuteAcpiMethod_DISPATCH(pDispCommon, pAcpiMethodParams) @@ -1632,6 +1670,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdSpecificDispI2cReadWrite(pDispCommon, pParams) dispcmnCtrlCmdSpecificDispI2cReadWrite_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment(pDispCommon, pParams) dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdSpecificSetHdmiAudioMutestream(pDispCommon, pParams) dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdDfpEdpDriverUnload(pDispCommon, pParams) dispcmnCtrlCmdDfpEdpDriverUnload_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpGetDisplayportDongleInfo(pDispCommon, pParams) dispcmnCtrlCmdDfpGetDisplayportDongleInfo_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDfpSetEldAudioCaps(pDispCommon, pEldAudioCapsParams) dispcmnCtrlCmdDfpSetEldAudioCaps_DISPATCH(pDispCommon, pEldAudioCapsParams) @@ -1673,6 +1712,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnCtrlCmdDpConfigureFec(pDispCommon, pParams) dispcmnCtrlCmdDpConfigureFec_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGetGenericInfoframe(pDispCommon, pParams) dispcmnCtrlCmdDpGetGenericInfoframe_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGetMsaAttributes(pDispCommon, pParams) dispcmnCtrlCmdDpGetMsaAttributes_DISPATCH(pDispCommon, pParams) +#define dispcmnCtrlCmdFrlConfigMacroPad(pDispCommon, pParams) dispcmnCtrlCmdFrlConfigMacroPad_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpConfigMacroPad(pDispCommon, pParams) dispcmnCtrlCmdDpConfigMacroPad_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data(pDispCommon, pParams) dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data_DISPATCH(pDispCommon, pParams) #define dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data(pDispCommon, pParams) dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data_DISPATCH(pDispCommon, pParams) @@ -1686,7 +1726,6 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnControl_Prologue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Prologue_DISPATCH(pDisplayApi, pCallContext, pRsParams) #define dispcmnUnmapFrom(pResource, pParams) dispcmnUnmapFrom_DISPATCH(pResource, pParams) #define dispcmnControl_Epilogue(pDisplayApi, pCallContext, pRsParams) dispcmnControl_Epilogue_DISPATCH(pDisplayApi, pCallContext, pRsParams) -#define dispcmnControlLookup(pResource, pParams, ppEntry) dispcmnControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispcmnControl(pDisplayApi, pCallContext, pParams) dispcmnControl_DISPATCH(pDisplayApi, pCallContext, pParams) #define dispcmnUnmap(pResource, pCallContext, pCpuMapping) dispcmnUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define dispcmnGetMemInterMapParams(pRmResource, pParams) dispcmnGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -1695,6 +1734,7 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL #define dispcmnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispcmnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispcmnControlSerialization_Prologue(pResource, pCallContext, pParams) dispcmnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispcmnCanCopy(pResource) dispcmnCanCopy_DISPATCH(pResource) +#define dispcmnIsPartialUnmapSupported(pResource) dispcmnIsPartialUnmapSupported_DISPATCH(pResource) #define dispcmnPreDestruct(pResource) dispcmnPreDestruct_DISPATCH(pResource) #define dispcmnIsDuplicate(pResource, hMemory, pDuplicate) dispcmnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispcmnControlSerialization_Epilogue(pResource, pCallContext, pParams) dispcmnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -1756,6 +1796,24 @@ static inline NV_STATUS dispcmnCtrlCmdInternalVRRSetRgLineActive_DISPATCH(struct return pDispCommon->__dispcmnCtrlCmdInternalVRRSetRgLineActive__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdVblankSemControl_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdVblankSemControl_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdVblankSemControl__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdInternalVblankSemControl_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdInternalVblankSemControl_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdInternalVblankSemControl__(pDispCommon, pParams); +} + +NV_STATUS dispcmnCtrlCmdAccelVblankSemControl_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdAccelVblankSemControl_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdAccelVblankSemControl__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDpEnableVrr_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDpEnableVrr_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_ENABLE_VRR_PARAMS *pParams) { @@ -1846,6 +1904,12 @@ static inline NV_STATUS dispcmnCtrlCmdDfpSwitchDispMux_DISPATCH(struct DispCommo return pDispCommon->__dispcmnCtrlCmdDfpSwitchDispMux__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdInternalDfpSwitchDispMux_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdInternalDfpSwitchDispMux_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdInternalDfpSwitchDispMux__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpRunPreDispMuxOperations_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpRunPreDispMuxOperations_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_RUN_PRE_DISP_MUX_OPERATIONS_PARAMS *pParams) { @@ -1864,6 +1928,12 @@ static inline NV_STATUS dispcmnCtrlCmdDfpGetDispMuxStatus_DISPATCH(struct DispCo return pDispCommon->__dispcmnCtrlCmdDfpGetDispMuxStatus__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdInternalDfpGetDispMuxStatus_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdInternalDfpGetDispMuxStatus_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdInternalDfpGetDispMuxStatus__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpInternalLcdOverdrive_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpInternalLcdOverdrive_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_AUXCH_OD_CTRL_PARAMS *pParams) { @@ -2182,6 +2252,12 @@ static inline NV_STATUS dispcmnCtrlCmdSpecificSetHdmiAudioMutestream_DISPATCH(st return pDispCommon->__dispcmnCtrlCmdSpecificSetHdmiAudioMutestream__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdDfpEdpDriverUnload_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdDfpEdpDriverUnload_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdDfpEdpDriverUnload__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDfpGetInfo_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDfpGetInfo_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_DFP_GET_INFO_PARAMS *pParams) { @@ -2428,6 +2504,12 @@ static inline NV_STATUS dispcmnCtrlCmdDpGetMsaAttributes_DISPATCH(struct DispCom return pDispCommon->__dispcmnCtrlCmdDpGetMsaAttributes__(pDispCommon, pParams); } +NV_STATUS dispcmnCtrlCmdFrlConfigMacroPad_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS *pParams); + +static inline NV_STATUS dispcmnCtrlCmdFrlConfigMacroPad_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS *pParams) { + return pDispCommon->__dispcmnCtrlCmdFrlConfigMacroPad__(pDispCommon, pParams); +} + NV_STATUS dispcmnCtrlCmdDpConfigMacroPad_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS *pParams); static inline NV_STATUS dispcmnCtrlCmdDpConfigMacroPad_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_CMD_DP_CONFIG_MACRO_PAD_PARAMS *pParams) { @@ -2486,10 +2568,6 @@ static inline void dispcmnControl_Epilogue_DISPATCH(struct DispCommon *pDisplayA pDisplayApi->__dispcmnControl_Epilogue__(pDisplayApi, pCallContext, pRsParams); } -static inline NV_STATUS dispcmnControlLookup_DISPATCH(struct DispCommon *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispcmnControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS dispcmnControl_DISPATCH(struct DispCommon *pDisplayApi, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pDisplayApi->__dispcmnControl__(pDisplayApi, pCallContext, pParams); } @@ -2522,6 +2600,10 @@ static inline NvBool dispcmnCanCopy_DISPATCH(struct DispCommon *pResource) { return pResource->__dispcmnCanCopy__(pResource); } +static inline NvBool dispcmnIsPartialUnmapSupported_DISPATCH(struct DispCommon *pResource) { + return pResource->__dispcmnIsPartialUnmapSupported__(pResource); +} + static inline void dispcmnPreDestruct_DISPATCH(struct DispCommon *pResource) { pResource->__dispcmnPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_disp_sf_user_nvoc.c b/src/nvidia/generated/g_disp_sf_user_nvoc.c index a8503abc58..0e0fdb02f5 100644 --- a/src/nvidia/generated/g_disp_sf_user_nvoc.c +++ b/src/nvidia/generated/g_disp_sf_user_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_dispsfControl_Epilogue(struct DispSfUser *pR rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispsfControlLookup(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_dispsfGetInternalObjectHandle(struct DispSfUser *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSfUser_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_dispsfCanCopy(struct DispSfUser *pResource return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispsfIsPartialUnmapSupported(struct DispSfUser *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispsfPreDestruct(struct DispSfUser *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSfUser_RsResource.offset)); } @@ -255,8 +255,6 @@ static void __nvoc_init_funcTable_DispSfUser_1(DispSfUser *pThis) { pThis->__dispsfControl_Epilogue__ = &__nvoc_thunk_RmResource_dispsfControl_Epilogue; - pThis->__dispsfControlLookup__ = &__nvoc_thunk_RsResource_dispsfControlLookup; - pThis->__dispsfGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispsfGetInternalObjectHandle; pThis->__dispsfControl__ = &__nvoc_thunk_GpuResource_dispsfControl; @@ -273,6 +271,8 @@ static void __nvoc_init_funcTable_DispSfUser_1(DispSfUser *pThis) { pThis->__dispsfCanCopy__ = &__nvoc_thunk_RsResource_dispsfCanCopy; + pThis->__dispsfIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispsfIsPartialUnmapSupported; + pThis->__dispsfPreDestruct__ = &__nvoc_thunk_RsResource_dispsfPreDestruct; pThis->__dispsfIsDuplicate__ = &__nvoc_thunk_RsResource_dispsfIsDuplicate; @@ -300,21 +300,26 @@ void __nvoc_init_DispSfUser(DispSfUser *pThis) { __nvoc_init_funcTable_DispSfUser(pThis); } -NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispSfUser *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSfUser), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispSfUser)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSfUser); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -329,16 +334,25 @@ NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_DispSfUser(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DispSfUser_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispSfUser_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispSfUser)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_disp_sf_user_nvoc.h b/src/nvidia/generated/g_disp_sf_user_nvoc.h index 275e88d969..cd4fe02bdb 100644 --- a/src/nvidia/generated/g_disp_sf_user_nvoc.h +++ b/src/nvidia/generated/g_disp_sf_user_nvoc.h @@ -46,11 +46,16 @@ extern "C" { /*! * RM internal class representing NVXXXX_DISP_SF_USER */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISP_SF_USER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispSfUser { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -71,7 +76,6 @@ struct DispSfUser { NV_STATUS (*__dispsfInternalControlForward__)(struct DispSfUser *, NvU32, void *, NvU32); NV_STATUS (*__dispsfUnmapFrom__)(struct DispSfUser *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispsfControl_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispsfControlLookup__)(struct DispSfUser *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__dispsfGetInternalObjectHandle__)(struct DispSfUser *); NV_STATUS (*__dispsfControl__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispsfUnmap__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -80,6 +84,7 @@ struct DispSfUser { NV_STATUS (*__dispsfControlFilter__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispsfControlSerialization_Prologue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispsfCanCopy__)(struct DispSfUser *); + NvBool (*__dispsfIsPartialUnmapSupported__)(struct DispSfUser *); void (*__dispsfPreDestruct__)(struct DispSfUser *); NV_STATUS (*__dispsfIsDuplicate__)(struct DispSfUser *, NvHandle, NvBool *); void (*__dispsfControlSerialization_Epilogue__)(struct DispSfUser *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -128,7 +133,6 @@ NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser**, Dynamic*, NvU32, struct CALL #define dispsfInternalControlForward(pGpuResource, command, pParams, size) dispsfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispsfUnmapFrom(pResource, pParams) dispsfUnmapFrom_DISPATCH(pResource, pParams) #define dispsfControl_Epilogue(pResource, pCallContext, pParams) dispsfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispsfControlLookup(pResource, pParams, ppEntry) dispsfControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispsfGetInternalObjectHandle(pGpuResource) dispsfGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispsfControl(pGpuResource, pCallContext, pParams) dispsfControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispsfUnmap(pGpuResource, pCallContext, pCpuMapping) dispsfUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -137,6 +141,7 @@ NV_STATUS __nvoc_objCreate_DispSfUser(DispSfUser**, Dynamic*, NvU32, struct CALL #define dispsfControlFilter(pResource, pCallContext, pParams) dispsfControlFilter_DISPATCH(pResource, pCallContext, pParams) #define dispsfControlSerialization_Prologue(pResource, pCallContext, pParams) dispsfControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispsfCanCopy(pResource) dispsfCanCopy_DISPATCH(pResource) +#define dispsfIsPartialUnmapSupported(pResource) dispsfIsPartialUnmapSupported_DISPATCH(pResource) #define dispsfPreDestruct(pResource) dispsfPreDestruct_DISPATCH(pResource) #define dispsfIsDuplicate(pResource, hMemory, pDuplicate) dispsfIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispsfControlSerialization_Epilogue(pResource, pCallContext, pParams) dispsfControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -188,10 +193,6 @@ static inline void dispsfControl_Epilogue_DISPATCH(struct DispSfUser *pResource, pResource->__dispsfControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispsfControlLookup_DISPATCH(struct DispSfUser *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispsfControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle dispsfGetInternalObjectHandle_DISPATCH(struct DispSfUser *pGpuResource) { return pGpuResource->__dispsfGetInternalObjectHandle__(pGpuResource); } @@ -224,6 +225,10 @@ static inline NvBool dispsfCanCopy_DISPATCH(struct DispSfUser *pResource) { return pResource->__dispsfCanCopy__(pResource); } +static inline NvBool dispsfIsPartialUnmapSupported_DISPATCH(struct DispSfUser *pResource) { + return pResource->__dispsfIsPartialUnmapSupported__(pResource); +} + static inline void dispsfPreDestruct_DISPATCH(struct DispSfUser *pResource) { pResource->__dispsfPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_dispsw_nvoc.c b/src/nvidia/generated/g_dispsw_nvoc.c index e728944840..064567b932 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.c +++ b/src/nvidia/generated/g_dispsw_nvoc.c @@ -176,10 +176,6 @@ static void __nvoc_thunk_RmResource_dispswControl_Epilogue(struct DispSwObject * rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_dispswControlLookup(struct DispSwObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_dispswGetInternalObjectHandle(struct DispSwObject *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DispSwObject_GpuResource.offset)); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_dispswCanCopy(struct DispSwObject *pResour return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_dispswIsPartialUnmapSupported(struct DispSwObject *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_dispswPreDestruct(struct DispSwObject *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DispSwObject_RsResource.offset)); } @@ -356,8 +356,6 @@ static void __nvoc_init_funcTable_DispSwObject_1(DispSwObject *pThis, RmHalspecO pThis->__dispswControl_Epilogue__ = &__nvoc_thunk_RmResource_dispswControl_Epilogue; - pThis->__dispswControlLookup__ = &__nvoc_thunk_RsResource_dispswControlLookup; - pThis->__dispswGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_dispswGetInternalObjectHandle; pThis->__dispswControl__ = &__nvoc_thunk_GpuResource_dispswControl; @@ -378,6 +376,8 @@ static void __nvoc_init_funcTable_DispSwObject_1(DispSwObject *pThis, RmHalspecO pThis->__dispswCanCopy__ = &__nvoc_thunk_RsResource_dispswCanCopy; + pThis->__dispswIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_dispswIsPartialUnmapSupported; + pThis->__dispswPreDestruct__ = &__nvoc_thunk_RsResource_dispswPreDestruct; pThis->__dispswIsDuplicate__ = &__nvoc_thunk_RsResource_dispswIsDuplicate; @@ -412,23 +412,31 @@ void __nvoc_init_DispSwObject(DispSwObject *pThis, RmHalspecOwner *pRmhalspecown __nvoc_init_funcTable_DispSwObject(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DispSwObject *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DispSwObject), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DispSwObject)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DispSwObject); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -446,16 +454,25 @@ NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject **ppThis, Dynamic *pParent, status = __nvoc_ctor_DispSwObject(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DispSwObject_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DispSwObject_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DispSwObject)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_dispsw_nvoc.h b/src/nvidia/generated/g_dispsw_nvoc.h index 8b0f0c8fe1..9a34176cbe 100644 --- a/src/nvidia/generated/g_dispsw_nvoc.h +++ b/src/nvidia/generated/g_dispsw_nvoc.h @@ -104,11 +104,16 @@ NV_STATUS dispswReleaseSemaphoreAndNotifierFill(struct OBJGPU *pGpu, /*! * RM internal class representing GF100_DISP_SW */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_DISPSW_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DispSwObject { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -136,7 +141,6 @@ struct DispSwObject { NV_STATUS (*__dispswInternalControlForward__)(struct DispSwObject *, NvU32, void *, NvU32); NV_STATUS (*__dispswUnmapFrom__)(struct DispSwObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__dispswControl_Epilogue__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__dispswControlLookup__)(struct DispSwObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__dispswGetInternalObjectHandle__)(struct DispSwObject *); NV_STATUS (*__dispswControl__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__dispswUnmap__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -147,6 +151,7 @@ struct DispSwObject { NV_STATUS (*__dispswUnregisterEvent__)(struct DispSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__dispswControlSerialization_Prologue__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__dispswCanCopy__)(struct DispSwObject *); + NvBool (*__dispswIsPartialUnmapSupported__)(struct DispSwObject *); void (*__dispswPreDestruct__)(struct DispSwObject *); NV_STATUS (*__dispswIsDuplicate__)(struct DispSwObject *, NvHandle, NvBool *); void (*__dispswControlSerialization_Epilogue__)(struct DispSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -204,7 +209,6 @@ NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject**, Dynamic*, NvU32, CALL_CO #define dispswInternalControlForward(pGpuResource, command, pParams, size) dispswInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define dispswUnmapFrom(pResource, pParams) dispswUnmapFrom_DISPATCH(pResource, pParams) #define dispswControl_Epilogue(pResource, pCallContext, pParams) dispswControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define dispswControlLookup(pResource, pParams, ppEntry) dispswControlLookup_DISPATCH(pResource, pParams, ppEntry) #define dispswGetInternalObjectHandle(pGpuResource) dispswGetInternalObjectHandle_DISPATCH(pGpuResource) #define dispswControl(pGpuResource, pCallContext, pParams) dispswControl_DISPATCH(pGpuResource, pCallContext, pParams) #define dispswUnmap(pGpuResource, pCallContext, pCpuMapping) dispswUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -215,6 +219,7 @@ NV_STATUS __nvoc_objCreate_DispSwObject(DispSwObject**, Dynamic*, NvU32, CALL_CO #define dispswUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) dispswUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define dispswControlSerialization_Prologue(pResource, pCallContext, pParams) dispswControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define dispswCanCopy(pResource) dispswCanCopy_DISPATCH(pResource) +#define dispswIsPartialUnmapSupported(pResource) dispswIsPartialUnmapSupported_DISPATCH(pResource) #define dispswPreDestruct(pResource) dispswPreDestruct_DISPATCH(pResource) #define dispswIsDuplicate(pResource, hMemory, pDuplicate) dispswIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define dispswControlSerialization_Epilogue(pResource, pCallContext, pParams) dispswControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -288,10 +293,6 @@ static inline void dispswControl_Epilogue_DISPATCH(struct DispSwObject *pResourc pResource->__dispswControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS dispswControlLookup_DISPATCH(struct DispSwObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__dispswControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle dispswGetInternalObjectHandle_DISPATCH(struct DispSwObject *pGpuResource) { return pGpuResource->__dispswGetInternalObjectHandle__(pGpuResource); } @@ -332,6 +333,10 @@ static inline NvBool dispswCanCopy_DISPATCH(struct DispSwObject *pResource) { return pResource->__dispswCanCopy__(pResource); } +static inline NvBool dispswIsPartialUnmapSupported_DISPATCH(struct DispSwObject *pResource) { + return pResource->__dispswIsPartialUnmapSupported__(pResource); +} + static inline void dispswPreDestruct_DISPATCH(struct DispSwObject *pResource) { pResource->__dispswPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_egm_mem_nvoc.c b/src/nvidia/generated/g_egm_mem_nvoc.c index 284d4b967d..d2b855da93 100644 --- a/src/nvidia/generated/g_egm_mem_nvoc.c +++ b/src/nvidia/generated/g_egm_mem_nvoc.c @@ -146,10 +146,6 @@ static void __nvoc_thunk_RmResource_egmmemControl_Epilogue(struct ExtendedGpuMem rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_egmmemControlLookup(struct ExtendedGpuMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_egmmemControl(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), pCallContext, pParams); } @@ -178,6 +174,10 @@ static NvBool __nvoc_thunk_StandardMemory_egmmemCanCopy(struct ExtendedGpuMemory return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_ExtendedGpuMemory_StandardMemory.offset)); } +static NvBool __nvoc_thunk_RsResource_egmmemIsPartialUnmapSupported(struct ExtendedGpuMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ExtendedGpuMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_egmmemIsReady(struct ExtendedGpuMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_ExtendedGpuMemory_Memory.offset), bCopyConstructorContext); } @@ -266,8 +266,6 @@ static void __nvoc_init_funcTable_ExtendedGpuMemory_1(ExtendedGpuMemory *pThis) pThis->__egmmemControl_Epilogue__ = &__nvoc_thunk_RmResource_egmmemControl_Epilogue; - pThis->__egmmemControlLookup__ = &__nvoc_thunk_RsResource_egmmemControlLookup; - pThis->__egmmemControl__ = &__nvoc_thunk_Memory_egmmemControl; pThis->__egmmemUnmap__ = &__nvoc_thunk_Memory_egmmemUnmap; @@ -282,6 +280,8 @@ static void __nvoc_init_funcTable_ExtendedGpuMemory_1(ExtendedGpuMemory *pThis) pThis->__egmmemCanCopy__ = &__nvoc_thunk_StandardMemory_egmmemCanCopy; + pThis->__egmmemIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_egmmemIsPartialUnmapSupported; + pThis->__egmmemIsReady__ = &__nvoc_thunk_Memory_egmmemIsReady; pThis->__egmmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_egmmemCheckCopyPermissions; @@ -314,21 +314,26 @@ void __nvoc_init_ExtendedGpuMemory(ExtendedGpuMemory *pThis) { __nvoc_init_funcTable_ExtendedGpuMemory(pThis); } -NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ExtendedGpuMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ExtendedGpuMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ExtendedGpuMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ExtendedGpuMemory); pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -343,16 +348,25 @@ NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory **ppThis, Dynamic status = __nvoc_ctor_ExtendedGpuMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ExtendedGpuMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ExtendedGpuMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ExtendedGpuMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_egm_mem_nvoc.h b/src/nvidia/generated/g_egm_mem_nvoc.h index eb5aed7e21..834dd9828b 100644 --- a/src/nvidia/generated/g_egm_mem_nvoc.h +++ b/src/nvidia/generated/g_egm_mem_nvoc.h @@ -42,11 +42,16 @@ extern "C" { * Allocator for Extended GPU Memory (EGM) * EGM is CPU_MEM accessed like peer GPU_MEM */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_EGM_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ExtendedGpuMemory { const struct NVOC_RTTI *__nvoc_rtti; struct StandardMemory __nvoc_base_StandardMemory; @@ -68,7 +73,6 @@ struct ExtendedGpuMemory { NvBool (*__egmmemIsGpuMapAllowed__)(struct ExtendedGpuMemory *, struct OBJGPU *); NV_STATUS (*__egmmemUnmapFrom__)(struct ExtendedGpuMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__egmmemControl_Epilogue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__egmmemControlLookup__)(struct ExtendedGpuMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__egmmemControl__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__egmmemUnmap__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__egmmemGetMemInterMapParams__)(struct ExtendedGpuMemory *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -76,6 +80,7 @@ struct ExtendedGpuMemory { NV_STATUS (*__egmmemControlFilter__)(struct ExtendedGpuMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__egmmemControlSerialization_Prologue__)(struct ExtendedGpuMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__egmmemCanCopy__)(struct ExtendedGpuMemory *); + NvBool (*__egmmemIsPartialUnmapSupported__)(struct ExtendedGpuMemory *); NV_STATUS (*__egmmemIsReady__)(struct ExtendedGpuMemory *, NvBool); NV_STATUS (*__egmmemCheckCopyPermissions__)(struct ExtendedGpuMemory *, struct OBJGPU *, struct Device *); void (*__egmmemPreDestruct__)(struct ExtendedGpuMemory *); @@ -124,7 +129,6 @@ NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory**, Dynamic*, NvU3 #define egmmemIsGpuMapAllowed(pMemory, pGpu) egmmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define egmmemUnmapFrom(pResource, pParams) egmmemUnmapFrom_DISPATCH(pResource, pParams) #define egmmemControl_Epilogue(pResource, pCallContext, pParams) egmmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define egmmemControlLookup(pResource, pParams, ppEntry) egmmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define egmmemControl(pMemory, pCallContext, pParams) egmmemControl_DISPATCH(pMemory, pCallContext, pParams) #define egmmemUnmap(pMemory, pCallContext, pCpuMapping) egmmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define egmmemGetMemInterMapParams(pMemory, pParams) egmmemGetMemInterMapParams_DISPATCH(pMemory, pParams) @@ -132,6 +136,7 @@ NV_STATUS __nvoc_objCreate_ExtendedGpuMemory(ExtendedGpuMemory**, Dynamic*, NvU3 #define egmmemControlFilter(pResource, pCallContext, pParams) egmmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define egmmemControlSerialization_Prologue(pResource, pCallContext, pParams) egmmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define egmmemCanCopy(pStandardMemory) egmmemCanCopy_DISPATCH(pStandardMemory) +#define egmmemIsPartialUnmapSupported(pResource) egmmemIsPartialUnmapSupported_DISPATCH(pResource) #define egmmemIsReady(pMemory, bCopyConstructorContext) egmmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define egmmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) egmmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define egmmemPreDestruct(pResource) egmmemPreDestruct_DISPATCH(pResource) @@ -183,10 +188,6 @@ static inline void egmmemControl_Epilogue_DISPATCH(struct ExtendedGpuMemory *pRe pResource->__egmmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS egmmemControlLookup_DISPATCH(struct ExtendedGpuMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__egmmemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS egmmemControl_DISPATCH(struct ExtendedGpuMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__egmmemControl__(pMemory, pCallContext, pParams); } @@ -215,6 +216,10 @@ static inline NvBool egmmemCanCopy_DISPATCH(struct ExtendedGpuMemory *pStandardM return pStandardMemory->__egmmemCanCopy__(pStandardMemory); } +static inline NvBool egmmemIsPartialUnmapSupported_DISPATCH(struct ExtendedGpuMemory *pResource) { + return pResource->__egmmemIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS egmmemIsReady_DISPATCH(struct ExtendedGpuMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__egmmemIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_eng_desc_nvoc.h b/src/nvidia/generated/g_eng_desc_nvoc.h index 4d1e65d50b..6cdb0527d2 100644 --- a/src/nvidia/generated/g_eng_desc_nvoc.h +++ b/src/nvidia/generated/g_eng_desc_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -548,6 +548,18 @@ typedef struct OBJDPU OBJDPU; #endif /* __nvoc_class_id_OBJDPU */ +struct OBJDIP; + +#ifndef __NVOC_CLASS_OBJDIP_TYPEDEF__ +#define __NVOC_CLASS_OBJDIP_TYPEDEF__ +typedef struct OBJDIP OBJDIP; +#endif /* __NVOC_CLASS_OBJDIP_TYPEDEF__ */ + +#ifndef __nvoc_class_id_OBJDIP +#define __nvoc_class_id_OBJDIP 0x1cc271 +#endif /* __nvoc_class_id_OBJDIP */ + + struct Fan; #ifndef __NVOC_CLASS_Fan_TYPEDEF__ @@ -716,16 +728,16 @@ typedef struct OBJVGA OBJVGA; #endif /* __nvoc_class_id_OBJVGA */ -struct OBJSTEREO; +struct Stereo; -#ifndef __NVOC_CLASS_OBJSTEREO_TYPEDEF__ -#define __NVOC_CLASS_OBJSTEREO_TYPEDEF__ -typedef struct OBJSTEREO OBJSTEREO; -#endif /* __NVOC_CLASS_OBJSTEREO_TYPEDEF__ */ +#ifndef __NVOC_CLASS_Stereo_TYPEDEF__ +#define __NVOC_CLASS_Stereo_TYPEDEF__ +typedef struct Stereo Stereo; +#endif /* __NVOC_CLASS_Stereo_TYPEDEF__ */ -#ifndef __nvoc_class_id_OBJSTEREO -#define __nvoc_class_id_OBJSTEREO 0x9fd931 -#endif /* __nvoc_class_id_OBJSTEREO */ +#ifndef __nvoc_class_id_Stereo +#define __nvoc_class_id_Stereo 0xbbc45d +#endif /* __nvoc_class_id_Stereo */ struct OBJOR; @@ -1028,6 +1040,18 @@ typedef struct Nvlink Nvlink; #endif /* __nvoc_class_id_Nvlink */ +struct KernelHwpm; + +#ifndef __NVOC_CLASS_KernelHwpm_TYPEDEF__ +#define __NVOC_CLASS_KernelHwpm_TYPEDEF__ +typedef struct KernelHwpm KernelHwpm; +#endif /* __NVOC_CLASS_KernelHwpm_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelHwpm +#define __nvoc_class_id_KernelHwpm 0xc8c00f +#endif /* __nvoc_class_id_KernelHwpm */ + + struct OBJHWPM; #ifndef __NVOC_CLASS_OBJHWPM_TYPEDEF__ @@ -1402,6 +1426,7 @@ typedef struct KernelCcu KernelCcu; #define ENG_KERNEL_DISPLAY MKENGDESC(classId(KernelDisplay), 0) #define ENG_DISP MKENGDESC(classId(OBJDISP), 0) #define ENG_DPU MKENGDESC(classId(OBJDPU), 0) +#define ENG_DIP MKENGDESC(classId(OBJDIP), 0) #define ENG_FAN MKENGDESC(classId(Fan), 0) #define ENG_INST MKENGDESC(classId(DisplayInstanceMemory), 0) #define ENG_KERNEL_HEAD MKENGDESC(classId(KernelHead), 0) @@ -1416,7 +1441,7 @@ typedef struct KernelCcu KernelCcu; #define ENG_PIOR MKENGDESC(classId(OBJPIOR), 0) #define ENG_HEAD MKENGDESC(classId(OBJHEAD), 0) #define ENG_VGA MKENGDESC(classId(OBJVGA), 0) -#define ENG_STEREO MKENGDESC(classId(OBJSTEREO), 0) +#define ENG_STEREO MKENGDESC(classId(Stereo), 0) #define ENG_OR MKENGDESC(classId(OBJOR), 0) #define ENG_BSP MKENGDESC(classId(OBJBSP), 0) #define ENG_CIPHER MKENGDESC(classId(OBJCIPHER), 0) @@ -1442,6 +1467,7 @@ typedef struct KernelCcu KernelCcu; #define ENG_GPULOG MKENGDESC(classId(OBJGPULOG), 0) #define ENG_NVLINK MKENGDESC(classId(Nvlink), 0) #define ENG_HWPM MKENGDESC(classId(OBJHWPM), 0) +#define ENG_KERNEL_HWPM MKENGDESC(classId(KernelHwpm), 0) #define ENG_GPUMON MKENGDESC(classId(OBJGPUMON), 0) #define ENG_GRIDDISPLAYLESS MKENGDESC(classId(OBJGRIDDISPLAYLESS), 0) #define ENG_VMMU MKENGDESC(classId(OBJVMMU), 0) @@ -1463,6 +1489,8 @@ typedef struct KernelCcu KernelCcu; #define ENG_CONF_COMPUTE MKENGDESC(classId(ConfidentialCompute), 0) #define ENG_KERNEL_CCU MKENGDESC(classId(KernelCcu), 0) +// Indexed GSPLITE Engine Tag Reference + // Indexed CE engine tag reference #define ENG_CE(x) MKENGDESC(classId(OBJCE), x) #define ENG_CE__SIZE_1 10 diff --git a/src/nvidia/generated/g_eng_state_nvoc.c b/src/nvidia/generated/g_eng_state_nvoc.c index 1b8ae6583c..7714a91a3f 100644 --- a/src/nvidia/generated/g_eng_state_nvoc.c +++ b/src/nvidia/generated/g_eng_state_nvoc.c @@ -132,21 +132,26 @@ void __nvoc_init_OBJENGSTATE(OBJENGSTATE *pThis) { __nvoc_init_funcTable_OBJENGSTATE(pThis); } -NV_STATUS __nvoc_objCreate_OBJENGSTATE(OBJENGSTATE **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJENGSTATE(OBJENGSTATE **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJENGSTATE *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJENGSTATE), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJENGSTATE)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJENGSTATE); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -161,16 +166,25 @@ NV_STATUS __nvoc_objCreate_OBJENGSTATE(OBJENGSTATE **ppThis, Dynamic *pParent, N status = __nvoc_ctor_OBJENGSTATE(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJENGSTATE_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJENGSTATE_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJENGSTATE)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_eng_state_nvoc.h b/src/nvidia/generated/g_eng_state_nvoc.h index 72d5f8c45b..6605f1958f 100644 --- a/src/nvidia/generated/g_eng_state_nvoc.h +++ b/src/nvidia/generated/g_eng_state_nvoc.h @@ -92,11 +92,16 @@ typedef struct OBJENGSTATE *POBJENGSTATE; * Defines the structure used to contain all generic information related to * the OBJENGSTATE. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_ENG_STATE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJENGSTATE { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_event_buffer_nvoc.c b/src/nvidia/generated/g_event_buffer_nvoc.c index 61083ee548..1ec1915104 100644 --- a/src/nvidia/generated/g_event_buffer_nvoc.c +++ b/src/nvidia/generated/g_event_buffer_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_eventbufferAddAdditionalDependants(struct Rs resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmapFrom(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_eventbufferControlSerialization_Prologue(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmap(struct EventBuffer *pR return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_eventbufferIsPartialUnmapSupported(struct EventBuffer *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_eventbufferPreDestruct(struct EventBuffer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_eventbufferControl_Epilogue(struct EventBuff rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_eventbufferControlLookup(struct EventBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_eventbufferUnmapFrom(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_EventBuffer_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_eventbufferMap(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -308,8 +308,6 @@ static void __nvoc_init_funcTable_EventBuffer_1(EventBuffer *pThis) { pThis->__eventbufferAddAdditionalDependants__ = &__nvoc_thunk_RsResource_eventbufferAddAdditionalDependants; - pThis->__eventbufferUnmapFrom__ = &__nvoc_thunk_RsResource_eventbufferUnmapFrom; - pThis->__eventbufferControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_eventbufferControlSerialization_Prologue; pThis->__eventbufferControl_Prologue__ = &__nvoc_thunk_RmResource_eventbufferControl_Prologue; @@ -318,6 +316,8 @@ static void __nvoc_init_funcTable_EventBuffer_1(EventBuffer *pThis) { pThis->__eventbufferUnmap__ = &__nvoc_thunk_RsResource_eventbufferUnmap; + pThis->__eventbufferIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_eventbufferIsPartialUnmapSupported; + pThis->__eventbufferPreDestruct__ = &__nvoc_thunk_RsResource_eventbufferPreDestruct; pThis->__eventbufferMapTo__ = &__nvoc_thunk_RsResource_eventbufferMapTo; @@ -328,7 +328,7 @@ static void __nvoc_init_funcTable_EventBuffer_1(EventBuffer *pThis) { pThis->__eventbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_eventbufferControl_Epilogue; - pThis->__eventbufferControlLookup__ = &__nvoc_thunk_RsResource_eventbufferControlLookup; + pThis->__eventbufferUnmapFrom__ = &__nvoc_thunk_RsResource_eventbufferUnmapFrom; pThis->__eventbufferMap__ = &__nvoc_thunk_RsResource_eventbufferMap; @@ -350,21 +350,26 @@ void __nvoc_init_EventBuffer(EventBuffer *pThis) { __nvoc_init_funcTable_EventBuffer(pThis); } -NV_STATUS __nvoc_objCreate_EventBuffer(EventBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_EventBuffer(EventBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; EventBuffer *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(EventBuffer), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(EventBuffer)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_EventBuffer); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -379,16 +384,25 @@ NV_STATUS __nvoc_objCreate_EventBuffer(EventBuffer **ppThis, Dynamic *pParent, N status = __nvoc_ctor_EventBuffer(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_EventBuffer_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_EventBuffer_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(EventBuffer)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_event_buffer_nvoc.h b/src/nvidia/generated/g_event_buffer_nvoc.h index 545d77172f..4c1dc9b775 100644 --- a/src/nvidia/generated/g_event_buffer_nvoc.h +++ b/src/nvidia/generated/g_event_buffer_nvoc.h @@ -68,11 +68,16 @@ typedef struct } EVENT_BUFFER_MAP_INFO; // This class shares buffers between kernel and usermode + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_EVENT_BUFFER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct EventBuffer { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -93,17 +98,17 @@ struct EventBuffer { NvU32 (*__eventbufferGetRefCount__)(struct EventBuffer *); NV_STATUS (*__eventbufferControlFilter__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventbufferAddAdditionalDependants__)(struct RsClient *, struct EventBuffer *, RsResourceRef *); - NV_STATUS (*__eventbufferUnmapFrom__)(struct EventBuffer *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__eventbufferControlSerialization_Prologue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventbufferControl_Prologue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__eventbufferCanCopy__)(struct EventBuffer *); NV_STATUS (*__eventbufferUnmap__)(struct EventBuffer *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__eventbufferIsPartialUnmapSupported__)(struct EventBuffer *); void (*__eventbufferPreDestruct__)(struct EventBuffer *); NV_STATUS (*__eventbufferMapTo__)(struct EventBuffer *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__eventbufferIsDuplicate__)(struct EventBuffer *, NvHandle, NvBool *); void (*__eventbufferControlSerialization_Epilogue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventbufferControl_Epilogue__)(struct EventBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__eventbufferControlLookup__)(struct EventBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__eventbufferUnmapFrom__)(struct EventBuffer *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__eventbufferMap__)(struct EventBuffer *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__eventbufferAccessCallback__)(struct EventBuffer *, struct RsClient *, void *, RsAccessRight); struct MEMORY_DESCRIPTOR *pHeaderDesc; @@ -168,17 +173,17 @@ NV_STATUS __nvoc_objCreate_EventBuffer(EventBuffer**, Dynamic*, NvU32, struct CA #define eventbufferGetRefCount(pResource) eventbufferGetRefCount_DISPATCH(pResource) #define eventbufferControlFilter(pResource, pCallContext, pParams) eventbufferControlFilter_DISPATCH(pResource, pCallContext, pParams) #define eventbufferAddAdditionalDependants(pClient, pResource, pReference) eventbufferAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define eventbufferUnmapFrom(pResource, pParams) eventbufferUnmapFrom_DISPATCH(pResource, pParams) #define eventbufferControlSerialization_Prologue(pResource, pCallContext, pParams) eventbufferControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControl_Prologue(pResource, pCallContext, pParams) eventbufferControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferCanCopy(pResource) eventbufferCanCopy_DISPATCH(pResource) #define eventbufferUnmap(pResource, pCallContext, pCpuMapping) eventbufferUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define eventbufferIsPartialUnmapSupported(pResource) eventbufferIsPartialUnmapSupported_DISPATCH(pResource) #define eventbufferPreDestruct(pResource) eventbufferPreDestruct_DISPATCH(pResource) #define eventbufferMapTo(pResource, pParams) eventbufferMapTo_DISPATCH(pResource, pParams) #define eventbufferIsDuplicate(pResource, hMemory, pDuplicate) eventbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define eventbufferControlSerialization_Epilogue(pResource, pCallContext, pParams) eventbufferControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventbufferControl_Epilogue(pResource, pCallContext, pParams) eventbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define eventbufferControlLookup(pResource, pParams, ppEntry) eventbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define eventbufferUnmapFrom(pResource, pParams) eventbufferUnmapFrom_DISPATCH(pResource, pParams) #define eventbufferMap(pResource, pCallContext, pParams, pCpuMapping) eventbufferMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define eventbufferAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) eventbufferAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS eventbuffertBufferCtrlCmdEnableEvent_IMPL(struct EventBuffer *pEventBuffer, NV_EVENT_BUFFER_CTRL_CMD_ENABLE_EVENTS_PARAMS *pEnableParams); @@ -237,10 +242,6 @@ static inline void eventbufferAddAdditionalDependants_DISPATCH(struct RsClient * pResource->__eventbufferAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS eventbufferUnmapFrom_DISPATCH(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__eventbufferUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS eventbufferControlSerialization_Prologue_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__eventbufferControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -257,6 +258,10 @@ static inline NV_STATUS eventbufferUnmap_DISPATCH(struct EventBuffer *pResource, return pResource->__eventbufferUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool eventbufferIsPartialUnmapSupported_DISPATCH(struct EventBuffer *pResource) { + return pResource->__eventbufferIsPartialUnmapSupported__(pResource); +} + static inline void eventbufferPreDestruct_DISPATCH(struct EventBuffer *pResource) { pResource->__eventbufferPreDestruct__(pResource); } @@ -277,8 +282,8 @@ static inline void eventbufferControl_Epilogue_DISPATCH(struct EventBuffer *pRes pResource->__eventbufferControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS eventbufferControlLookup_DISPATCH(struct EventBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__eventbufferControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS eventbufferUnmapFrom_DISPATCH(struct EventBuffer *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__eventbufferUnmapFrom__(pResource, pParams); } static inline NV_STATUS eventbufferMap_DISPATCH(struct EventBuffer *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_event_nvoc.c b/src/nvidia/generated/g_event_nvoc.c index 8f61342e2b..b0811405cd 100644 --- a/src/nvidia/generated/g_event_nvoc.c +++ b/src/nvidia/generated/g_event_nvoc.c @@ -119,21 +119,26 @@ void __nvoc_init_NotifShare(NotifShare *pThis) { __nvoc_init_funcTable_NotifShare(pThis); } -NV_STATUS __nvoc_objCreate_NotifShare(NotifShare **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_NotifShare(NotifShare **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; NotifShare *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NotifShare), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(NotifShare)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NotifShare); pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -148,16 +153,25 @@ NV_STATUS __nvoc_objCreate_NotifShare(NotifShare **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_NotifShare(pThis); if (status != NV_OK) goto __nvoc_objCreate_NotifShare_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_NotifShare_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(NotifShare)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -280,10 +294,6 @@ static void __nvoc_thunk_RsResource_eventAddAdditionalDependants(struct RsClient resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_eventUnmapFrom(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_eventControlSerialization_Prologue(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); } @@ -300,6 +310,10 @@ static NV_STATUS __nvoc_thunk_RsResource_eventUnmap(struct Event *pResource, str return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_eventIsPartialUnmapSupported(struct Event *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_eventPreDestruct(struct Event *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset)); } @@ -320,8 +334,8 @@ static void __nvoc_thunk_RmResource_eventControl_Epilogue(struct Event *pResourc rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_eventControlLookup(struct Event *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_eventUnmapFrom(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Event_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_eventMap(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -387,8 +401,6 @@ static void __nvoc_init_funcTable_Event_1(Event *pThis) { pThis->__eventAddAdditionalDependants__ = &__nvoc_thunk_RsResource_eventAddAdditionalDependants; - pThis->__eventUnmapFrom__ = &__nvoc_thunk_RsResource_eventUnmapFrom; - pThis->__eventControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_eventControlSerialization_Prologue; pThis->__eventControl_Prologue__ = &__nvoc_thunk_RmResource_eventControl_Prologue; @@ -397,6 +409,8 @@ static void __nvoc_init_funcTable_Event_1(Event *pThis) { pThis->__eventUnmap__ = &__nvoc_thunk_RsResource_eventUnmap; + pThis->__eventIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_eventIsPartialUnmapSupported; + pThis->__eventPreDestruct__ = &__nvoc_thunk_RsResource_eventPreDestruct; pThis->__eventMapTo__ = &__nvoc_thunk_RsResource_eventMapTo; @@ -407,7 +421,7 @@ static void __nvoc_init_funcTable_Event_1(Event *pThis) { pThis->__eventControl_Epilogue__ = &__nvoc_thunk_RmResource_eventControl_Epilogue; - pThis->__eventControlLookup__ = &__nvoc_thunk_RsResource_eventControlLookup; + pThis->__eventUnmapFrom__ = &__nvoc_thunk_RsResource_eventUnmapFrom; pThis->__eventMap__ = &__nvoc_thunk_RsResource_eventMap; @@ -429,21 +443,26 @@ void __nvoc_init_Event(Event *pThis) { __nvoc_init_funcTable_Event(pThis); } -NV_STATUS __nvoc_objCreate_Event(Event **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_Event(Event **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Event *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Event), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Event)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Event); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -458,16 +477,25 @@ NV_STATUS __nvoc_objCreate_Event(Event **ppThis, Dynamic *pParent, NvU32 createF status = __nvoc_ctor_Event(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_Event_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Event_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Event)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_event_nvoc.h b/src/nvidia/generated/g_event_nvoc.h index 098ca2d670..7843c3b34a 100644 --- a/src/nvidia/generated/g_event_nvoc.h +++ b/src/nvidia/generated/g_event_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -101,11 +101,16 @@ struct _def_client_system_event_info * Instances of this class are ref-counted and will be kept alive until * the notifier and all of its events have been freed. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_EVENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct NotifShare { const struct NVOC_RTTI *__nvoc_rtti; struct RsShared __nvoc_base_RsShared; @@ -158,11 +163,16 @@ void shrnotifDestruct_IMPL(struct NotifShare *pNotifShare); /** * This class represents event notification consumers */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_EVENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Event { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -179,17 +189,17 @@ struct Event { NvU32 (*__eventGetRefCount__)(struct Event *); NV_STATUS (*__eventControlFilter__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventAddAdditionalDependants__)(struct RsClient *, struct Event *, RsResourceRef *); - NV_STATUS (*__eventUnmapFrom__)(struct Event *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__eventControlSerialization_Prologue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__eventControl_Prologue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__eventCanCopy__)(struct Event *); NV_STATUS (*__eventUnmap__)(struct Event *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__eventIsPartialUnmapSupported__)(struct Event *); void (*__eventPreDestruct__)(struct Event *); NV_STATUS (*__eventMapTo__)(struct Event *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__eventIsDuplicate__)(struct Event *, NvHandle, NvBool *); void (*__eventControlSerialization_Epilogue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__eventControl_Epilogue__)(struct Event *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__eventControlLookup__)(struct Event *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__eventUnmapFrom__)(struct Event *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__eventMap__)(struct Event *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__eventAccessCallback__)(struct Event *, struct RsClient *, void *, RsAccessRight); struct NotifShare *pNotifierShare; @@ -234,17 +244,17 @@ NV_STATUS __nvoc_objCreate_Event(Event**, Dynamic*, NvU32, struct CALL_CONTEXT * #define eventGetRefCount(pResource) eventGetRefCount_DISPATCH(pResource) #define eventControlFilter(pResource, pCallContext, pParams) eventControlFilter_DISPATCH(pResource, pCallContext, pParams) #define eventAddAdditionalDependants(pClient, pResource, pReference) eventAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define eventUnmapFrom(pResource, pParams) eventUnmapFrom_DISPATCH(pResource, pParams) #define eventControlSerialization_Prologue(pResource, pCallContext, pParams) eventControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventControl_Prologue(pResource, pCallContext, pParams) eventControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define eventCanCopy(pResource) eventCanCopy_DISPATCH(pResource) #define eventUnmap(pResource, pCallContext, pCpuMapping) eventUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define eventIsPartialUnmapSupported(pResource) eventIsPartialUnmapSupported_DISPATCH(pResource) #define eventPreDestruct(pResource) eventPreDestruct_DISPATCH(pResource) #define eventMapTo(pResource, pParams) eventMapTo_DISPATCH(pResource, pParams) #define eventIsDuplicate(pResource, hMemory, pDuplicate) eventIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define eventControlSerialization_Epilogue(pResource, pCallContext, pParams) eventControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define eventControl_Epilogue(pResource, pCallContext, pParams) eventControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define eventControlLookup(pResource, pParams, ppEntry) eventControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define eventUnmapFrom(pResource, pParams) eventUnmapFrom_DISPATCH(pResource, pParams) #define eventMap(pResource, pCallContext, pParams, pCpuMapping) eventMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define eventAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) eventAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool eventShareCallback_DISPATCH(struct Event *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -279,10 +289,6 @@ static inline void eventAddAdditionalDependants_DISPATCH(struct RsClient *pClien pResource->__eventAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS eventUnmapFrom_DISPATCH(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__eventUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS eventControlSerialization_Prologue_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__eventControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -299,6 +305,10 @@ static inline NV_STATUS eventUnmap_DISPATCH(struct Event *pResource, struct CALL return pResource->__eventUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool eventIsPartialUnmapSupported_DISPATCH(struct Event *pResource) { + return pResource->__eventIsPartialUnmapSupported__(pResource); +} + static inline void eventPreDestruct_DISPATCH(struct Event *pResource) { pResource->__eventPreDestruct__(pResource); } @@ -319,8 +329,8 @@ static inline void eventControl_Epilogue_DISPATCH(struct Event *pResource, struc pResource->__eventControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS eventControlLookup_DISPATCH(struct Event *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__eventControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS eventUnmapFrom_DISPATCH(struct Event *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__eventUnmapFrom__(pResource, pParams); } static inline NV_STATUS eventMap_DISPATCH(struct Event *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -348,17 +358,25 @@ static inline NV_STATUS eventInit(struct Event *pEvent, struct CALL_CONTEXT *pCa #define eventInit(pEvent, pCallContext, hNotifierClient, hNotifierResource, pppEventNotification) eventInit_IMPL(pEvent, pCallContext, hNotifierClient, hNotifierResource, pppEventNotification) #endif //__nvoc_event_h_disabled +NV_STATUS eventGetByHandle_IMPL(struct RsClient *pClient, NvHandle hEvent, NvU32 *pNotifyIndex); + +#define eventGetByHandle(pClient, hEvent, pNotifyIndex) eventGetByHandle_IMPL(pClient, hEvent, pNotifyIndex) #undef PRIVATE_FIELD /** * Mix-in interface for resources that send notifications to events */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_EVENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct INotifier { const struct NVOC_RTTI *__nvoc_rtti; struct INotifier *__nvoc_pbase_INotifier; @@ -445,11 +463,16 @@ static inline PEVENTNOTIFICATION inotifyGetNotificationList(struct INotifier *pN /** * Basic implementation for event notification mix-in */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_EVENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Notifier { const struct NVOC_RTTI *__nvoc_rtti; struct INotifier __nvoc_base_INotifier; diff --git a/src/nvidia/generated/g_fabric_nvoc.c b/src/nvidia/generated/g_fabric_nvoc.c index f41c01dd1a..9ef09a2fd8 100644 --- a/src/nvidia/generated/g_fabric_nvoc.c +++ b/src/nvidia/generated/g_fabric_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_Fabric(Fabric *pThis) { __nvoc_init_funcTable_Fabric(pThis); } -NV_STATUS __nvoc_objCreate_Fabric(Fabric **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_Fabric(Fabric **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Fabric *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Fabric), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Fabric)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Fabric); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_Fabric(Fabric **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_Fabric(pThis); if (status != NV_OK) goto __nvoc_objCreate_Fabric_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Fabric_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Fabric)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_fabric_nvoc.h b/src/nvidia/generated/g_fabric_nvoc.h index 5cda67c475..3ee4c1488c 100644 --- a/src/nvidia/generated/g_fabric_nvoc.h +++ b/src/nvidia/generated/g_fabric_nvoc.h @@ -48,6 +48,13 @@ extern "C" { #include "class/cl000f.h" #include "ctrl/ctrl000f.h" +#include "core/thread_state.h" +#include "rmapi/event.h" +#include "rmapi/resource.h" +#include "containers/list.h" +#include "nvCpuUuid.h" +#include "ctrl/ctrl00f1.h" + // **************************************************************************** @@ -68,6 +75,13 @@ typedef struct MAKE_MULTIMAP(FabricCache, FabricCacheEntry); +#define NV_FABRIC_INVALID_NODE_ID ((NvU16) 0xFFFF) + +MAKE_LIST(FabricEventListV2, NV00F1_CTRL_FABRIC_EVENT); + +// Callbacks +void fabricWakeUpThreadCallback(void *pData); + #include "nvlink_inband_msg.h" void fabricMulticastWaitOnTeamCleanupCallback(void *pCbData); @@ -75,19 +89,35 @@ void fabricMulticastWaitOnTeamCleanupCallback(void *pCbData); // // The Fabric object is used to encapsulate the NVLink fabric // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_FABRIC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Fabric { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct Fabric *__nvoc_pbase_Fabric; - NvU32 flags; - PORT_MUTEX *pMulticastFabricOpsMutex; - FabricCache fabricMulticastCache; + PORT_RWLOCK *pFabricImportModuleLock; + PORT_RWLOCK *pMulticastFabricModuleLock; + NvU32 PRIVATE_FIELD(flags); + FabricEventListV2 PRIVATE_FIELD(fabricEventListV2); + PORT_RWLOCK *PRIVATE_FIELD(pListLock); + FabricCache PRIVATE_FIELD(importCache); + PORT_RWLOCK *PRIVATE_FIELD(pImportCacheLock); + FabricCache PRIVATE_FIELD(unimportCache); + PORT_RWLOCK *PRIVATE_FIELD(pUnimportCacheLock); + NvP64 PRIVATE_FIELD(pOsImexEvent); + NvU16 PRIVATE_FIELD(nodeId); + volatile NvU64 PRIVATE_FIELD(eventId); + FabricCache PRIVATE_FIELD(fabricMulticastCache); + PORT_RWLOCK *PRIVATE_FIELD(pMulticastFabriCacheLock); }; #ifndef __NVOC_CLASS_Fabric_TYPEDEF__ @@ -145,88 +175,259 @@ static inline NvU32 fabricGetFmSessionFlags(struct Fabric *pFabric) { #define fabricGetFmSessionFlags(pFabric) fabricGetFmSessionFlags_IMPL(pFabric) #endif //__nvoc_fabric_h_disabled -void fabricMulticastFabricOpsMutexAcquire_IMPL(struct Fabric *pFabric); +NV_STATUS fabricSetImexEvent_IMPL(struct Fabric *pFabric, NvP64 pOsEvent); + +#ifdef __nvoc_fabric_h_disabled +static inline NV_STATUS fabricSetImexEvent(struct Fabric *pFabric, NvP64 pOsEvent) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_h_disabled +#define fabricSetImexEvent(pFabric, pOsEvent) fabricSetImexEvent_IMPL(pFabric, pOsEvent) +#endif //__nvoc_fabric_h_disabled + +NvP64 fabricGetImexEvent_IMPL(struct Fabric *pFabric); + +#ifdef __nvoc_fabric_h_disabled +static inline NvP64 fabricGetImexEvent(struct Fabric *pFabric) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return 0; +} +#else //__nvoc_fabric_h_disabled +#define fabricGetImexEvent(pFabric) fabricGetImexEvent_IMPL(pFabric) +#endif //__nvoc_fabric_h_disabled + +void fabricSetNodeId_IMPL(struct Fabric *pFabric, NvU16 nodeId); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricSetNodeId(struct Fabric *pFabric, NvU16 nodeId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricSetNodeId(pFabric, nodeId) fabricSetNodeId_IMPL(pFabric, nodeId) +#endif //__nvoc_fabric_h_disabled + +NvU16 fabricGetNodeId_IMPL(struct Fabric *pFabric); + +#ifdef __nvoc_fabric_h_disabled +static inline NvU16 fabricGetNodeId(struct Fabric *pFabric) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return 0; +} +#else //__nvoc_fabric_h_disabled +#define fabricGetNodeId(pFabric) fabricGetNodeId_IMPL(pFabric) +#endif //__nvoc_fabric_h_disabled + +NV_STATUS fabricPostEventsV2_IMPL(struct Fabric *pFabric, NV00F1_CTRL_FABRIC_EVENT *pEvents, NvU32 numEvents); + +#ifdef __nvoc_fabric_h_disabled +static inline NV_STATUS fabricPostEventsV2(struct Fabric *pFabric, NV00F1_CTRL_FABRIC_EVENT *pEvents, NvU32 numEvents) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_h_disabled +#define fabricPostEventsV2(pFabric, pEvents, numEvents) fabricPostEventsV2_IMPL(pFabric, pEvents, numEvents) +#endif //__nvoc_fabric_h_disabled + +NvBool fabricExtractEventsV2_IMPL(struct Fabric *pFabric, NV00F1_CTRL_FABRIC_EVENT *pEventArray, NvU32 *pNumEvents); + +#ifdef __nvoc_fabric_h_disabled +static inline NvBool fabricExtractEventsV2(struct Fabric *pFabric, NV00F1_CTRL_FABRIC_EVENT *pEventArray, NvU32 *pNumEvents) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NV_FALSE; +} +#else //__nvoc_fabric_h_disabled +#define fabricExtractEventsV2(pFabric, pEventArray, pNumEvents) fabricExtractEventsV2_IMPL(pFabric, pEventArray, pNumEvents) +#endif //__nvoc_fabric_h_disabled + +void fabricFlushUnhandledEvents_IMPL(struct Fabric *pFabric); #ifdef __nvoc_fabric_h_disabled -static inline void fabricMulticastFabricOpsMutexAcquire(struct Fabric *pFabric) { +static inline void fabricFlushUnhandledEvents(struct Fabric *pFabric) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); } #else //__nvoc_fabric_h_disabled -#define fabricMulticastFabricOpsMutexAcquire(pFabric) fabricMulticastFabricOpsMutexAcquire_IMPL(pFabric) +#define fabricFlushUnhandledEvents(pFabric) fabricFlushUnhandledEvents_IMPL(pFabric) #endif //__nvoc_fabric_h_disabled -void fabricMulticastFabricOpsMutexRelease_IMPL(struct Fabric *pFabric); +NvU64 fabricGenerateEventId_IMPL(struct Fabric *pFabric); #ifdef __nvoc_fabric_h_disabled -static inline void fabricMulticastFabricOpsMutexRelease(struct Fabric *pFabric) { +static inline NvU64 fabricGenerateEventId(struct Fabric *pFabric) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return 0; } #else //__nvoc_fabric_h_disabled -#define fabricMulticastFabricOpsMutexRelease(pFabric) fabricMulticastFabricOpsMutexRelease_IMPL(pFabric) +#define fabricGenerateEventId(pFabric) fabricGenerateEventId_IMPL(pFabric) #endif //__nvoc_fabric_h_disabled -NV_STATUS fabricMulticastSetupCacheInsertUnderLock_IMPL(struct Fabric *pFabric, NvU64 requesId, void *pData); +NV_STATUS fabricImportCacheInsert_IMPL(struct Fabric *pFabric, const NvUuid *pExportUuid, NvU64 key, void *pData); #ifdef __nvoc_fabric_h_disabled -static inline NV_STATUS fabricMulticastSetupCacheInsertUnderLock(struct Fabric *pFabric, NvU64 requesId, void *pData) { +static inline NV_STATUS fabricImportCacheInsert(struct Fabric *pFabric, const NvUuid *pExportUuid, NvU64 key, void *pData) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_fabric_h_disabled -#define fabricMulticastSetupCacheInsertUnderLock(pFabric, requesId, pData) fabricMulticastSetupCacheInsertUnderLock_IMPL(pFabric, requesId, pData) +#define fabricImportCacheInsert(pFabric, pExportUuid, key, pData) fabricImportCacheInsert_IMPL(pFabric, pExportUuid, key, pData) #endif //__nvoc_fabric_h_disabled -void fabricMulticastSetupCacheDeleteUnderLock_IMPL(struct Fabric *pFabric, NvU64 requesId); +void fabricImportCacheDelete_IMPL(struct Fabric *pFabric, const NvUuid *pExportUuid, NvU64 key); #ifdef __nvoc_fabric_h_disabled -static inline void fabricMulticastSetupCacheDeleteUnderLock(struct Fabric *pFabric, NvU64 requesId) { +static inline void fabricImportCacheDelete(struct Fabric *pFabric, const NvUuid *pExportUuid, NvU64 key) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); } #else //__nvoc_fabric_h_disabled -#define fabricMulticastSetupCacheDeleteUnderLock(pFabric, requesId) fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requesId) +#define fabricImportCacheDelete(pFabric, pExportUuid, key) fabricImportCacheDelete_IMPL(pFabric, pExportUuid, key) #endif //__nvoc_fabric_h_disabled -void *fabricMulticastSetupCacheGetUnderLock_IMPL(struct Fabric *pFabric, NvU64 requestId); +void *fabricImportCacheGet_IMPL(struct Fabric *pFabric, const NvUuid *pExportUuid, NvU64 key); #ifdef __nvoc_fabric_h_disabled -static inline void *fabricMulticastSetupCacheGetUnderLock(struct Fabric *pFabric, NvU64 requestId) { +static inline void *fabricImportCacheGet(struct Fabric *pFabric, const NvUuid *pExportUuid, NvU64 key) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); return NULL; } #else //__nvoc_fabric_h_disabled -#define fabricMulticastSetupCacheGetUnderLock(pFabric, requestId) fabricMulticastSetupCacheGetUnderLock_IMPL(pFabric, requestId) +#define fabricImportCacheGet(pFabric, pExportUuid, key) fabricImportCacheGet_IMPL(pFabric, pExportUuid, key) +#endif //__nvoc_fabric_h_disabled + +void fabricImportCacheClear_IMPL(struct Fabric *pFabric); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricImportCacheClear(struct Fabric *pFabric) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricImportCacheClear(pFabric) fabricImportCacheClear_IMPL(pFabric) #endif //__nvoc_fabric_h_disabled -NV_STATUS fabricMulticastCleanupCacheInsertUnderLock_IMPL(struct Fabric *pFabric, NvU64 requesId, void *pData); +NV_STATUS fabricUnimportCacheInsert_IMPL(struct Fabric *pFabric, NvU64 unimportEventId, void *pData); #ifdef __nvoc_fabric_h_disabled -static inline NV_STATUS fabricMulticastCleanupCacheInsertUnderLock(struct Fabric *pFabric, NvU64 requesId, void *pData) { +static inline NV_STATUS fabricUnimportCacheInsert(struct Fabric *pFabric, NvU64 unimportEventId, void *pData) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_fabric_h_disabled -#define fabricMulticastCleanupCacheInsertUnderLock(pFabric, requesId, pData) fabricMulticastCleanupCacheInsertUnderLock_IMPL(pFabric, requesId, pData) +#define fabricUnimportCacheInsert(pFabric, unimportEventId, pData) fabricUnimportCacheInsert_IMPL(pFabric, unimportEventId, pData) #endif //__nvoc_fabric_h_disabled -void fabricMulticastCleanupCacheDeleteUnderLock_IMPL(struct Fabric *pFabric, NvU64 requesId); +void fabricUnimportCacheDelete_IMPL(struct Fabric *pFabric, NvU64 unimportEventId); #ifdef __nvoc_fabric_h_disabled -static inline void fabricMulticastCleanupCacheDeleteUnderLock(struct Fabric *pFabric, NvU64 requesId) { +static inline void fabricUnimportCacheDelete(struct Fabric *pFabric, NvU64 unimportEventId) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); } #else //__nvoc_fabric_h_disabled -#define fabricMulticastCleanupCacheDeleteUnderLock(pFabric, requesId) fabricMulticastCleanupCacheDeleteUnderLock_IMPL(pFabric, requesId) +#define fabricUnimportCacheDelete(pFabric, unimportEventId) fabricUnimportCacheDelete_IMPL(pFabric, unimportEventId) #endif //__nvoc_fabric_h_disabled -void *fabricMulticastCleanupCacheGetUnderLock_IMPL(struct Fabric *pFabric, NvU64 requestId); +void *fabricUnimportCacheGet_IMPL(struct Fabric *pFabric, NvU64 unimportEventId); #ifdef __nvoc_fabric_h_disabled -static inline void *fabricMulticastCleanupCacheGetUnderLock(struct Fabric *pFabric, NvU64 requestId) { +static inline void *fabricUnimportCacheGet(struct Fabric *pFabric, NvU64 unimportEventId) { NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); return NULL; } #else //__nvoc_fabric_h_disabled -#define fabricMulticastCleanupCacheGetUnderLock(pFabric, requestId) fabricMulticastCleanupCacheGetUnderLock_IMPL(pFabric, requestId) +#define fabricUnimportCacheGet(pFabric, unimportEventId) fabricUnimportCacheGet_IMPL(pFabric, unimportEventId) +#endif //__nvoc_fabric_h_disabled + +void fabricUnimportCacheIterateAll_IMPL(struct Fabric *pFabric, void (*pCb)(void *)); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricUnimportCacheIterateAll(struct Fabric *pFabric, void (*pCb)(void *)) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricUnimportCacheIterateAll(pFabric, pCb) fabricUnimportCacheIterateAll_IMPL(pFabric, pCb) +#endif //__nvoc_fabric_h_disabled + +NvBool fabricUnimportCacheInvokeCallback_IMPL(struct Fabric *pFabric, NvU64 unimportEventId, void (*pCb)(void *)); + +#ifdef __nvoc_fabric_h_disabled +static inline NvBool fabricUnimportCacheInvokeCallback(struct Fabric *pFabric, NvU64 unimportEventId, void (*pCb)(void *)) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NV_FALSE; +} +#else //__nvoc_fabric_h_disabled +#define fabricUnimportCacheInvokeCallback(pFabric, unimportEventId, pCb) fabricUnimportCacheInvokeCallback_IMPL(pFabric, unimportEventId, pCb) +#endif //__nvoc_fabric_h_disabled + +NV_STATUS fabricMulticastSetupCacheInsert_IMPL(struct Fabric *pFabric, NvU64 requesId, void *pData); + +#ifdef __nvoc_fabric_h_disabled +static inline NV_STATUS fabricMulticastSetupCacheInsert(struct Fabric *pFabric, NvU64 requesId, void *pData) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastSetupCacheInsert(pFabric, requesId, pData) fabricMulticastSetupCacheInsert_IMPL(pFabric, requesId, pData) +#endif //__nvoc_fabric_h_disabled + +void fabricMulticastSetupCacheDelete_IMPL(struct Fabric *pFabric, NvU64 requesId); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricMulticastSetupCacheDelete(struct Fabric *pFabric, NvU64 requesId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastSetupCacheDelete(pFabric, requesId) fabricMulticastSetupCacheDelete_IMPL(pFabric, requesId) +#endif //__nvoc_fabric_h_disabled + +void *fabricMulticastSetupCacheGet_IMPL(struct Fabric *pFabric, NvU64 requestId); + +#ifdef __nvoc_fabric_h_disabled +static inline void *fabricMulticastSetupCacheGet(struct Fabric *pFabric, NvU64 requestId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NULL; +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastSetupCacheGet(pFabric, requestId) fabricMulticastSetupCacheGet_IMPL(pFabric, requestId) +#endif //__nvoc_fabric_h_disabled + +NV_STATUS fabricMulticastCleanupCacheInsert_IMPL(struct Fabric *pFabric, NvU64 requesId, void *pData); + +#ifdef __nvoc_fabric_h_disabled +static inline NV_STATUS fabricMulticastCleanupCacheInsert(struct Fabric *pFabric, NvU64 requesId, void *pData) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastCleanupCacheInsert(pFabric, requesId, pData) fabricMulticastCleanupCacheInsert_IMPL(pFabric, requesId, pData) +#endif //__nvoc_fabric_h_disabled + +void fabricMulticastCleanupCacheDelete_IMPL(struct Fabric *pFabric, NvU64 requesId); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricMulticastCleanupCacheDelete(struct Fabric *pFabric, NvU64 requesId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastCleanupCacheDelete(pFabric, requesId) fabricMulticastCleanupCacheDelete_IMPL(pFabric, requesId) +#endif //__nvoc_fabric_h_disabled + +void *fabricMulticastCleanupCacheGet_IMPL(struct Fabric *pFabric, NvU64 requestId); + +#ifdef __nvoc_fabric_h_disabled +static inline void *fabricMulticastCleanupCacheGet(struct Fabric *pFabric, NvU64 requestId) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); + return NULL; +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastCleanupCacheGet(pFabric, requestId) fabricMulticastCleanupCacheGet_IMPL(pFabric, requestId) +#endif //__nvoc_fabric_h_disabled + +void fabricMulticastCleanupCacheInvokeCallback_IMPL(struct Fabric *pFabric, NvU64 requestId, void (*pCb)(void *)); + +#ifdef __nvoc_fabric_h_disabled +static inline void fabricMulticastCleanupCacheInvokeCallback(struct Fabric *pFabric, NvU64 requestId, void (*pCb)(void *)) { + NV_ASSERT_FAILED_PRECOMP("Fabric was disabled!"); +} +#else //__nvoc_fabric_h_disabled +#define fabricMulticastCleanupCacheInvokeCallback(pFabric, requestId, pCb) fabricMulticastCleanupCacheInvokeCallback_IMPL(pFabric, requestId, pCb) #endif //__nvoc_fabric_h_disabled #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.c b/src/nvidia/generated/g_fabric_vaspace_nvoc.c index 1ecfc0ed4e..2d01a165ff 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.c +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.c @@ -142,7 +142,7 @@ static PMEMORY_DESCRIPTOR __nvoc_thunk_OBJVASPACE_fabricvaspaceGetKernelPageDirB return vaspaceGetKernelPageDirBase((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu); } -static NvU64 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetMapPageSize(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJVASPACE_fabricvaspaceGetMapPageSize(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock) { return vaspaceGetMapPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_FABRIC_VASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } @@ -308,21 +308,26 @@ void __nvoc_init_FABRIC_VASPACE(FABRIC_VASPACE *pThis) { __nvoc_init_funcTable_FABRIC_VASPACE(pThis); } -NV_STATUS __nvoc_objCreate_FABRIC_VASPACE(FABRIC_VASPACE **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_FABRIC_VASPACE(FABRIC_VASPACE **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; FABRIC_VASPACE *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FABRIC_VASPACE), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(FABRIC_VASPACE)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FABRIC_VASPACE); pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -337,16 +342,25 @@ NV_STATUS __nvoc_objCreate_FABRIC_VASPACE(FABRIC_VASPACE **ppThis, Dynamic *pPar status = __nvoc_ctor_FABRIC_VASPACE(pThis); if (status != NV_OK) goto __nvoc_objCreate_FABRIC_VASPACE_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_FABRIC_VASPACE_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(FABRIC_VASPACE)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_fabric_vaspace_nvoc.h b/src/nvidia/generated/g_fabric_vaspace_nvoc.h index 97a51e9a3c..76eed91eca 100644 --- a/src/nvidia/generated/g_fabric_vaspace_nvoc.h +++ b/src/nvidia/generated/g_fabric_vaspace_nvoc.h @@ -45,7 +45,6 @@ extern "C" { #include "core/core.h" #include "mem_mgr/vaspace.h" #include "mem_mgr/gpu_vaspace.h" -#include "gpu/mem_mgr/heap.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "ctrl/ctrl0080/ctrl0080dma.h" #include "ctrl/ctrl90f1.h" @@ -67,11 +66,16 @@ typedef struct /*! * RM-registered/managed Fabric virtual address space. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_FABRIC_VASPACE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct FABRIC_VASPACE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJVASPACE __nvoc_base_OBJVASPACE; @@ -97,7 +101,7 @@ struct FABRIC_VASPACE { NvU64 (*__fabricvaspaceGetVaLimit__)(struct FABRIC_VASPACE *); PMEMORY_DESCRIPTOR (*__fabricvaspaceGetPageDirBase__)(struct FABRIC_VASPACE *, struct OBJGPU *); PMEMORY_DESCRIPTOR (*__fabricvaspaceGetKernelPageDirBase__)(struct FABRIC_VASPACE *, struct OBJGPU *); - NvU64 (*__fabricvaspaceGetMapPageSize__)(struct FABRIC_VASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__fabricvaspaceGetMapPageSize__)(struct FABRIC_VASPACE *, struct OBJGPU *, struct EMEMBLOCK *); struct OBJEHEAP *(*__fabricvaspaceGetHeap__)(struct FABRIC_VASPACE *); NvBool (*__fabricvaspaceIsFaultCapable__)(struct FABRIC_VASPACE *); NvU64 (*__fabricvaspaceGetVaStart__)(struct FABRIC_VASPACE *); @@ -273,7 +277,7 @@ static inline PMEMORY_DESCRIPTOR fabricvaspaceGetKernelPageDirBase_DISPATCH(stru return pVAS->__fabricvaspaceGetKernelPageDirBase__(pVAS, pGpu); } -static inline NvU64 fabricvaspaceGetMapPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 fabricvaspaceGetMapPageSize_DISPATCH(struct FABRIC_VASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock) { return pVAS->__fabricvaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff --git a/src/nvidia/generated/g_fbsr_nvoc.c b/src/nvidia/generated/g_fbsr_nvoc.c index ef154762a7..ad6ed2d55c 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.c +++ b/src/nvidia/generated/g_fbsr_nvoc.c @@ -152,23 +152,31 @@ void __nvoc_init_OBJFBSR(OBJFBSR *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_OBJFBSR(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_OBJFBSR(OBJFBSR **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJFBSR(OBJFBSR **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJFBSR *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJFBSR), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJFBSR)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJFBSR); pThis->__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_Object); @@ -186,16 +194,25 @@ NV_STATUS __nvoc_objCreate_OBJFBSR(OBJFBSR **ppThis, Dynamic *pParent, NvU32 cre status = __nvoc_ctor_OBJFBSR(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_OBJFBSR_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJFBSR_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJFBSR)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_fbsr_nvoc.h b/src/nvidia/generated/g_fbsr_nvoc.h index 477749c6df..d9b0b88ec8 100644 --- a/src/nvidia/generated/g_fbsr_nvoc.h +++ b/src/nvidia/generated/g_fbsr_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -91,11 +91,16 @@ typedef struct OBJFBSR OBJFBSR; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_FBSR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJFBSR { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_fecs_event_list_nvoc.h b/src/nvidia/generated/g_fecs_event_list_nvoc.h index 8294b64aa7..3b5eb097ee 100644 --- a/src/nvidia/generated/g_fecs_event_list_nvoc.h +++ b/src/nvidia/generated/g_fecs_event_list_nvoc.h @@ -60,6 +60,18 @@ typedef struct KernelGraphics KernelGraphics; #endif /* __nvoc_class_id_KernelGraphics */ +struct KernelGraphicsManager; + +#ifndef __NVOC_CLASS_KernelGraphicsManager_TYPEDEF__ +#define __NVOC_CLASS_KernelGraphicsManager_TYPEDEF__ +typedef struct KernelGraphicsManager KernelGraphicsManager; +#endif /* __NVOC_CLASS_KernelGraphicsManager_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelGraphicsManager +#define __nvoc_class_id_KernelGraphicsManager 0xd22179 +#endif /* __nvoc_class_id_KernelGraphicsManager */ + + struct EventBuffer; #ifndef __NVOC_CLASS_EventBuffer_TYPEDEF__ @@ -165,6 +177,7 @@ void fecsClearRoutingInfo(OBJGPU *, struct KernelGraphics *); /*! Opaque FECS event buffer private data */ typedef struct KGRAPHICS_FECS_TRACE_INFO KGRAPHICS_FECS_TRACE_INFO; +typedef struct KGRMGR_FECS_GLOBAL_TRACE_INFO KGRMGR_FECS_GLOBAL_TRACE_INFO; NV_STATUS fecsCtxswLoggingInit ( @@ -175,6 +188,15 @@ NV_STATUS fecsCtxswLoggingInit void fecsCtxswLoggingTeardown(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics); +NV_STATUS fecsGlobalLoggingInit +( + OBJGPU *pGpu, + struct KernelGraphicsManager *pKernelGraphicsManager, + KGRMGR_FECS_GLOBAL_TRACE_INFO **ppFecsGlobalTraceInfo +); + +void fecsGlobalLoggingTeardown(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); + /*! set num records to process per intr */ void fecsSetRecordsPerIntr ( @@ -243,6 +265,11 @@ NvBool fecsClearIntrPendingIfPending(OBJGPU *pGpu, struct KernelGraphics *pKerne /*! Atomically check is intr callback pending */ NvBool fecsIsIntrPending(OBJGPU *pGpu, struct KernelGraphics *pKernelGraphics); +/*! Retrieve or modify Ctxsw logging consumer count */ +NvS16 fecsGetCtxswLogConsumerCount(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); +NV_STATUS fecsDecrementCtxswLogConsumerCount(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); +NV_STATUS fecsIncrementCtxswLogConsumerCount(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); + /*! Opaque VGPU fecs event buffer private data */ typedef struct VGPU_FECS_TRACE_STAGING_BUFFER VGPU_FECS_TRACE_STAGING_BUFFER; @@ -257,6 +284,9 @@ void fecsSetVgpuStagingBuffer VGPU_FECS_TRACE_STAGING_BUFFER *pStagingBuffer ); +/*! Retreive map of logging consumers */ +FecsEventBufferBindMultiMap *fecsGetEventBufferBindMultiMap(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); + #endif // _FECS_EVENT_LIST_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_fla_mem_nvoc.c b/src/nvidia/generated/g_fla_mem_nvoc.c index a15846913b..fb12801881 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.c +++ b/src/nvidia/generated/g_fla_mem_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_flamemControl_Epilogue(struct FlaMemory *pRe rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_flamemControlLookup(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_flamemControl(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_flamemControlSerialization_Prologue(str return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_flamemIsPartialUnmapSupported(struct FlaMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FlaMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_flamemIsReady(struct FlaMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_FlaMemory_Memory.offset), bCopyConstructorContext); } @@ -264,8 +264,6 @@ static void __nvoc_init_funcTable_FlaMemory_1(FlaMemory *pThis) { pThis->__flamemControl_Epilogue__ = &__nvoc_thunk_RmResource_flamemControl_Epilogue; - pThis->__flamemControlLookup__ = &__nvoc_thunk_RsResource_flamemControlLookup; - pThis->__flamemControl__ = &__nvoc_thunk_Memory_flamemControl; pThis->__flamemUnmap__ = &__nvoc_thunk_Memory_flamemUnmap; @@ -278,6 +276,8 @@ static void __nvoc_init_funcTable_FlaMemory_1(FlaMemory *pThis) { pThis->__flamemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_flamemControlSerialization_Prologue; + pThis->__flamemIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_flamemIsPartialUnmapSupported; + pThis->__flamemIsReady__ = &__nvoc_thunk_Memory_flamemIsReady; pThis->__flamemCheckCopyPermissions__ = &__nvoc_thunk_Memory_flamemCheckCopyPermissions; @@ -309,21 +309,26 @@ void __nvoc_init_FlaMemory(FlaMemory *pThis) { __nvoc_init_funcTable_FlaMemory(pThis); } -NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; FlaMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FlaMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(FlaMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FlaMemory); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -338,16 +343,25 @@ NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_FlaMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_FlaMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_FlaMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(FlaMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_fla_mem_nvoc.h b/src/nvidia/generated/g_fla_mem_nvoc.h index 30f743b1c9..c667d3d581 100644 --- a/src/nvidia/generated/g_fla_mem_nvoc.h +++ b/src/nvidia/generated/g_fla_mem_nvoc.h @@ -39,11 +39,16 @@ extern "C" { /*! * This class is used by the FLA clients to allocate FLA memory handle */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_FLA_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct FlaMemory { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -66,13 +71,13 @@ struct FlaMemory { NvBool (*__flamemIsGpuMapAllowed__)(struct FlaMemory *, struct OBJGPU *); NV_STATUS (*__flamemUnmapFrom__)(struct FlaMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__flamemControl_Epilogue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__flamemControlLookup__)(struct FlaMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__flamemControl__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemUnmap__)(struct FlaMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__flamemGetMemInterMapParams__)(struct FlaMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__flamemGetMemoryMappingDescriptor__)(struct FlaMemory *, MEMORY_DESCRIPTOR **); NV_STATUS (*__flamemControlFilter__)(struct FlaMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__flamemControlSerialization_Prologue__)(struct FlaMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__flamemIsPartialUnmapSupported__)(struct FlaMemory *); NV_STATUS (*__flamemIsReady__)(struct FlaMemory *, NvBool); NV_STATUS (*__flamemCheckCopyPermissions__)(struct FlaMemory *, struct OBJGPU *, struct Device *); void (*__flamemPreDestruct__)(struct FlaMemory *); @@ -126,13 +131,13 @@ NV_STATUS __nvoc_objCreate_FlaMemory(FlaMemory**, Dynamic*, NvU32, CALL_CONTEXT #define flamemIsGpuMapAllowed(pMemory, pGpu) flamemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define flamemUnmapFrom(pResource, pParams) flamemUnmapFrom_DISPATCH(pResource, pParams) #define flamemControl_Epilogue(pResource, pCallContext, pParams) flamemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define flamemControlLookup(pResource, pParams, ppEntry) flamemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define flamemControl(pMemory, pCallContext, pParams) flamemControl_DISPATCH(pMemory, pCallContext, pParams) #define flamemUnmap(pMemory, pCallContext, pCpuMapping) flamemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define flamemGetMemInterMapParams(pMemory, pParams) flamemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define flamemGetMemoryMappingDescriptor(pMemory, ppMemDesc) flamemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define flamemControlFilter(pResource, pCallContext, pParams) flamemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define flamemControlSerialization_Prologue(pResource, pCallContext, pParams) flamemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define flamemIsPartialUnmapSupported(pResource) flamemIsPartialUnmapSupported_DISPATCH(pResource) #define flamemIsReady(pMemory, bCopyConstructorContext) flamemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define flamemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) flamemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define flamemPreDestruct(pResource) flamemPreDestruct_DISPATCH(pResource) @@ -196,10 +201,6 @@ static inline void flamemControl_Epilogue_DISPATCH(struct FlaMemory *pResource, pResource->__flamemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS flamemControlLookup_DISPATCH(struct FlaMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__flamemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS flamemControl_DISPATCH(struct FlaMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__flamemControl__(pMemory, pCallContext, pParams); } @@ -224,6 +225,10 @@ static inline NV_STATUS flamemControlSerialization_Prologue_DISPATCH(struct FlaM return pResource->__flamemControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool flamemIsPartialUnmapSupported_DISPATCH(struct FlaMemory *pResource) { + return pResource->__flamemIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS flamemIsReady_DISPATCH(struct FlaMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__flamemIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_fm_session_api_nvoc.c b/src/nvidia/generated/g_fm_session_api_nvoc.c index e02f9452c8..3263985193 100644 --- a/src/nvidia/generated/g_fm_session_api_nvoc.c +++ b/src/nvidia/generated/g_fm_session_api_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants(struct R resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmapFrom(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmap(struct FmSessionApi * return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_fmsessionapiIsPartialUnmapSupported(struct FmSessionApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_fmsessionapiPreDestruct(struct FmSessionApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_fmsessionapiControl_Epilogue(struct FmSessio rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiControlLookup(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiUnmapFrom(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_FmSessionApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_fmsessionapiMap(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -270,8 +270,6 @@ static void __nvoc_init_funcTable_FmSessionApi_1(FmSessionApi *pThis) { pThis->__fmsessionapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_fmsessionapiAddAdditionalDependants; - pThis->__fmsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_fmsessionapiUnmapFrom; - pThis->__fmsessionapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControlSerialization_Prologue; pThis->__fmsessionapiControl_Prologue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Prologue; @@ -280,6 +278,8 @@ static void __nvoc_init_funcTable_FmSessionApi_1(FmSessionApi *pThis) { pThis->__fmsessionapiUnmap__ = &__nvoc_thunk_RsResource_fmsessionapiUnmap; + pThis->__fmsessionapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_fmsessionapiIsPartialUnmapSupported; + pThis->__fmsessionapiPreDestruct__ = &__nvoc_thunk_RsResource_fmsessionapiPreDestruct; pThis->__fmsessionapiMapTo__ = &__nvoc_thunk_RsResource_fmsessionapiMapTo; @@ -290,7 +290,7 @@ static void __nvoc_init_funcTable_FmSessionApi_1(FmSessionApi *pThis) { pThis->__fmsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_fmsessionapiControl_Epilogue; - pThis->__fmsessionapiControlLookup__ = &__nvoc_thunk_RsResource_fmsessionapiControlLookup; + pThis->__fmsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_fmsessionapiUnmapFrom; pThis->__fmsessionapiMap__ = &__nvoc_thunk_RsResource_fmsessionapiMap; @@ -312,21 +312,26 @@ void __nvoc_init_FmSessionApi(FmSessionApi *pThis) { __nvoc_init_funcTable_FmSessionApi(pThis); } -NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; FmSessionApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(FmSessionApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(FmSessionApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_FmSessionApi); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -341,16 +346,25 @@ NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi **ppThis, Dynamic *pParent, status = __nvoc_ctor_FmSessionApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_FmSessionApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_FmSessionApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(FmSessionApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_fm_session_api_nvoc.h b/src/nvidia/generated/g_fm_session_api_nvoc.h index 03a312a1a6..497aaadacb 100644 --- a/src/nvidia/generated/g_fm_session_api_nvoc.h +++ b/src/nvidia/generated/g_fm_session_api_nvoc.h @@ -63,11 +63,16 @@ extern "C" { // - FmSessionApi can be allocated only by privileged clients. // - RmApi lock must be held. // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_FM_SESSION_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct FmSessionApi { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -86,17 +91,17 @@ struct FmSessionApi { NvU32 (*__fmsessionapiGetRefCount__)(struct FmSessionApi *); NV_STATUS (*__fmsessionapiControlFilter__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__fmsessionapiAddAdditionalDependants__)(struct RsClient *, struct FmSessionApi *, RsResourceRef *); - NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__fmsessionapiControlSerialization_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__fmsessionapiControl_Prologue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__fmsessionapiCanCopy__)(struct FmSessionApi *); NV_STATUS (*__fmsessionapiUnmap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__fmsessionapiIsPartialUnmapSupported__)(struct FmSessionApi *); void (*__fmsessionapiPreDestruct__)(struct FmSessionApi *); NV_STATUS (*__fmsessionapiMapTo__)(struct FmSessionApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__fmsessionapiIsDuplicate__)(struct FmSessionApi *, NvHandle, NvBool *); void (*__fmsessionapiControlSerialization_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__fmsessionapiControl_Epilogue__)(struct FmSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__fmsessionapiControlLookup__)(struct FmSessionApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__fmsessionapiUnmapFrom__)(struct FmSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__fmsessionapiMap__)(struct FmSessionApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__fmsessionapiAccessCallback__)(struct FmSessionApi *, struct RsClient *, void *, RsAccessRight); NvU64 dupedCapDescriptor; @@ -140,17 +145,17 @@ NV_STATUS __nvoc_objCreate_FmSessionApi(FmSessionApi**, Dynamic*, NvU32, struct #define fmsessionapiGetRefCount(pResource) fmsessionapiGetRefCount_DISPATCH(pResource) #define fmsessionapiControlFilter(pResource, pCallContext, pParams) fmsessionapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiAddAdditionalDependants(pClient, pResource, pReference) fmsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) #define fmsessionapiControlSerialization_Prologue(pResource, pCallContext, pParams) fmsessionapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiControl_Prologue(pResource, pCallContext, pParams) fmsessionapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiCanCopy(pResource) fmsessionapiCanCopy_DISPATCH(pResource) #define fmsessionapiUnmap(pResource, pCallContext, pCpuMapping) fmsessionapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define fmsessionapiIsPartialUnmapSupported(pResource) fmsessionapiIsPartialUnmapSupported_DISPATCH(pResource) #define fmsessionapiPreDestruct(pResource) fmsessionapiPreDestruct_DISPATCH(pResource) #define fmsessionapiMapTo(pResource, pParams) fmsessionapiMapTo_DISPATCH(pResource, pParams) #define fmsessionapiIsDuplicate(pResource, hMemory, pDuplicate) fmsessionapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define fmsessionapiControlSerialization_Epilogue(pResource, pCallContext, pParams) fmsessionapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define fmsessionapiControl_Epilogue(pResource, pCallContext, pParams) fmsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define fmsessionapiControlLookup(pResource, pParams, ppEntry) fmsessionapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define fmsessionapiUnmapFrom(pResource, pParams) fmsessionapiUnmapFrom_DISPATCH(pResource, pParams) #define fmsessionapiMap(pResource, pCallContext, pParams, pCpuMapping) fmsessionapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define fmsessionapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) fmsessionapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS fmsessionapiCtrlCmdSetFmState_IMPL(struct FmSessionApi *pFmSessionApi); @@ -197,10 +202,6 @@ static inline void fmsessionapiAddAdditionalDependants_DISPATCH(struct RsClient pResource->__fmsessionapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS fmsessionapiUnmapFrom_DISPATCH(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__fmsessionapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS fmsessionapiControlSerialization_Prologue_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__fmsessionapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -217,6 +218,10 @@ static inline NV_STATUS fmsessionapiUnmap_DISPATCH(struct FmSessionApi *pResourc return pResource->__fmsessionapiUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool fmsessionapiIsPartialUnmapSupported_DISPATCH(struct FmSessionApi *pResource) { + return pResource->__fmsessionapiIsPartialUnmapSupported__(pResource); +} + static inline void fmsessionapiPreDestruct_DISPATCH(struct FmSessionApi *pResource) { pResource->__fmsessionapiPreDestruct__(pResource); } @@ -237,8 +242,8 @@ static inline void fmsessionapiControl_Epilogue_DISPATCH(struct FmSessionApi *pR pResource->__fmsessionapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS fmsessionapiControlLookup_DISPATCH(struct FmSessionApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__fmsessionapiControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS fmsessionapiUnmapFrom_DISPATCH(struct FmSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__fmsessionapiUnmapFrom__(pResource, pParams); } static inline NV_STATUS fmsessionapiMap_DISPATCH(struct FmSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_generic_engine_nvoc.c b/src/nvidia/generated/g_generic_engine_nvoc.c index feb297172b..8355fe819a 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.c +++ b/src/nvidia/generated/g_generic_engine_nvoc.c @@ -145,10 +145,6 @@ static void __nvoc_thunk_RmResource_genapiControl_Epilogue(struct GenericEngineA rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_genapiControlLookup(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_genapiGetInternalObjectHandle(struct GenericEngineApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GenericEngineApi_GpuResource.offset)); } @@ -177,6 +173,10 @@ static NvBool __nvoc_thunk_RsResource_genapiCanCopy(struct GenericEngineApi *pRe return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_genapiIsPartialUnmapSupported(struct GenericEngineApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_genapiPreDestruct(struct GenericEngineApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GenericEngineApi_RsResource.offset)); } @@ -215,12 +215,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GenericE #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0x90e60102u, /*paramSize=*/ sizeof(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS), @@ -296,7 +296,7 @@ static void __nvoc_init_funcTable_GenericEngineApi_1(GenericEngineApi *pThis) { pThis->__genapiCtrlCmdMasterGetErrorIntrOffsetMask__ = &genapiCtrlCmdMasterGetErrorIntrOffsetMask_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask__ = &genapiCtrlCmdMasterGetVirtualFunctionErrorContIntrMask_IMPL; #endif @@ -330,8 +330,6 @@ static void __nvoc_init_funcTable_GenericEngineApi_1(GenericEngineApi *pThis) { pThis->__genapiControl_Epilogue__ = &__nvoc_thunk_RmResource_genapiControl_Epilogue; - pThis->__genapiControlLookup__ = &__nvoc_thunk_RsResource_genapiControlLookup; - pThis->__genapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_genapiGetInternalObjectHandle; pThis->__genapiUnmap__ = &__nvoc_thunk_GpuResource_genapiUnmap; @@ -346,6 +344,8 @@ static void __nvoc_init_funcTable_GenericEngineApi_1(GenericEngineApi *pThis) { pThis->__genapiCanCopy__ = &__nvoc_thunk_RsResource_genapiCanCopy; + pThis->__genapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_genapiIsPartialUnmapSupported; + pThis->__genapiPreDestruct__ = &__nvoc_thunk_RsResource_genapiPreDestruct; pThis->__genapiIsDuplicate__ = &__nvoc_thunk_RsResource_genapiIsDuplicate; @@ -371,21 +371,26 @@ void __nvoc_init_GenericEngineApi(GenericEngineApi *pThis) { __nvoc_init_funcTable_GenericEngineApi(pThis); } -NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GenericEngineApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GenericEngineApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GenericEngineApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GenericEngineApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -400,16 +405,25 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi **ppThis, Dynamic * status = __nvoc_ctor_GenericEngineApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_GenericEngineApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GenericEngineApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GenericEngineApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_generic_engine_nvoc.h b/src/nvidia/generated/g_generic_engine_nvoc.h index 9cf3e8cf09..01c9f3ee34 100644 --- a/src/nvidia/generated/g_generic_engine_nvoc.h +++ b/src/nvidia/generated/g_generic_engine_nvoc.h @@ -43,11 +43,16 @@ extern "C" { * GF100_SUBDEVICE_GRAPHICS and GF100_SUBDEVICE_FB). Classes are primarily used * for exposing BAR0 mappings and controls. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GENERIC_ENGINE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GenericEngineApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -73,7 +78,6 @@ struct GenericEngineApi { NV_STATUS (*__genapiInternalControlForward__)(struct GenericEngineApi *, NvU32, void *, NvU32); NV_STATUS (*__genapiUnmapFrom__)(struct GenericEngineApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__genapiControl_Epilogue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__genapiControlLookup__)(struct GenericEngineApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__genapiGetInternalObjectHandle__)(struct GenericEngineApi *); NV_STATUS (*__genapiUnmap__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__genapiGetMemInterMapParams__)(struct GenericEngineApi *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -81,6 +85,7 @@ struct GenericEngineApi { NV_STATUS (*__genapiControlFilter__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__genapiControlSerialization_Prologue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__genapiCanCopy__)(struct GenericEngineApi *); + NvBool (*__genapiIsPartialUnmapSupported__)(struct GenericEngineApi *); void (*__genapiPreDestruct__)(struct GenericEngineApi *); NV_STATUS (*__genapiIsDuplicate__)(struct GenericEngineApi *, NvHandle, NvBool *); void (*__genapiControlSerialization_Epilogue__)(struct GenericEngineApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -131,7 +136,6 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi**, Dynamic*, NvU32, #define genapiInternalControlForward(pGpuResource, command, pParams, size) genapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define genapiUnmapFrom(pResource, pParams) genapiUnmapFrom_DISPATCH(pResource, pParams) #define genapiControl_Epilogue(pResource, pCallContext, pParams) genapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define genapiControlLookup(pResource, pParams, ppEntry) genapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define genapiGetInternalObjectHandle(pGpuResource) genapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define genapiUnmap(pGpuResource, pCallContext, pCpuMapping) genapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define genapiGetMemInterMapParams(pRmResource, pParams) genapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -139,6 +143,7 @@ NV_STATUS __nvoc_objCreate_GenericEngineApi(GenericEngineApi**, Dynamic*, NvU32, #define genapiControlFilter(pResource, pCallContext, pParams) genapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define genapiControlSerialization_Prologue(pResource, pCallContext, pParams) genapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define genapiCanCopy(pResource) genapiCanCopy_DISPATCH(pResource) +#define genapiIsPartialUnmapSupported(pResource) genapiIsPartialUnmapSupported_DISPATCH(pResource) #define genapiPreDestruct(pResource) genapiPreDestruct_DISPATCH(pResource) #define genapiIsDuplicate(pResource, hMemory, pDuplicate) genapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define genapiControlSerialization_Epilogue(pResource, pCallContext, pParams) genapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -219,10 +224,6 @@ static inline void genapiControl_Epilogue_DISPATCH(struct GenericEngineApi *pRes pResource->__genapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS genapiControlLookup_DISPATCH(struct GenericEngineApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__genapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle genapiGetInternalObjectHandle_DISPATCH(struct GenericEngineApi *pGpuResource) { return pGpuResource->__genapiGetInternalObjectHandle__(pGpuResource); } @@ -251,6 +252,10 @@ static inline NvBool genapiCanCopy_DISPATCH(struct GenericEngineApi *pResource) return pResource->__genapiCanCopy__(pResource); } +static inline NvBool genapiIsPartialUnmapSupported_DISPATCH(struct GenericEngineApi *pResource) { + return pResource->__genapiIsPartialUnmapSupported__(pResource); +} + static inline void genapiPreDestruct_DISPATCH(struct GenericEngineApi *pResource) { pResource->__genapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_gpu_access_nvoc.c b/src/nvidia/generated/g_gpu_access_nvoc.c index 507bec0d4b..cdc69ce58b 100644 --- a/src/nvidia/generated/g_gpu_access_nvoc.c +++ b/src/nvidia/generated/g_gpu_access_nvoc.c @@ -191,21 +191,26 @@ void __nvoc_init_IoAperture(IoAperture *pThis) { __nvoc_init_funcTable_IoAperture(pThis); } -NV_STATUS __nvoc_objCreate_IoAperture(IoAperture **ppThis, Dynamic *pParent, NvU32 createFlags, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length) { +NV_STATUS __nvoc_objCreate_IoAperture(IoAperture **ppThis, Dynamic *pParent, NvU32 createFlags, struct IoAperture * arg_pParentAperture, OBJGPU * arg_pGpu, NvU32 arg_deviceIndex, NvU32 arg_deviceInstance, DEVICE_MAPPING * arg_pMapping, NvU32 arg_mappingStartAddr, NvU32 arg_offset, NvU32 arg_length) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; IoAperture *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(IoAperture), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(IoAperture)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_IoAperture); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -220,16 +225,25 @@ NV_STATUS __nvoc_objCreate_IoAperture(IoAperture **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_IoAperture(pThis, arg_pParentAperture, arg_pGpu, arg_deviceIndex, arg_deviceInstance, arg_pMapping, arg_mappingStartAddr, arg_offset, arg_length); if (status != NV_OK) goto __nvoc_objCreate_IoAperture_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_IoAperture_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(IoAperture)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -435,21 +449,26 @@ void __nvoc_init_SwBcAperture(SwBcAperture *pThis) { __nvoc_init_funcTable_SwBcAperture(pThis); } -NV_STATUS __nvoc_objCreate_SwBcAperture(SwBcAperture **ppThis, Dynamic *pParent, NvU32 createFlags, struct IoAperture * arg_pApertures, NvU32 arg_numApertures) { +NV_STATUS __nvoc_objCreate_SwBcAperture(SwBcAperture **ppThis, Dynamic *pParent, NvU32 createFlags, struct IoAperture * arg_pApertures, NvU32 arg_numApertures) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; SwBcAperture *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SwBcAperture), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(SwBcAperture)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SwBcAperture); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -464,16 +483,25 @@ NV_STATUS __nvoc_objCreate_SwBcAperture(SwBcAperture **ppThis, Dynamic *pParent, status = __nvoc_ctor_SwBcAperture(pThis, arg_pApertures, arg_numApertures); if (status != NV_OK) goto __nvoc_objCreate_SwBcAperture_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_SwBcAperture_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(SwBcAperture)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_access_nvoc.h b/src/nvidia/generated/g_gpu_access_nvoc.h index 10457ddcca..7c7a3b2163 100644 --- a/src/nvidia/generated/g_gpu_access_nvoc.h +++ b/src/nvidia/generated/g_gpu_access_nvoc.h @@ -380,11 +380,16 @@ void gpuRegWr32Uc_dumpinfo(const char *func, const char *addrStr, const char *v #define FLD_SF_IDX_DEF(s,f,c,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_DEF(s,f,c,i)) #define FLD_SF_IDX_NUM(s,f,n,i,l) (((l) & ~SF_SHIFTMASK(NV ## s ## f(i))) | SF_IDX_NUM(s,f,n,i)) + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_ACCESS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct IoAperture { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -514,11 +519,16 @@ NV_STATUS ioaprtConstruct_IMPL(struct IoAperture *arg_pAperture, struct IoApertu // In-place construct wrapper NV_STATUS ioaprtInit(struct IoAperture *pAperture, struct IoAperture *pParentAperture, NvU32 offset, NvU32 length); + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_ACCESS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct SwBcAperture { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_gpu_acct_nvoc.c b/src/nvidia/generated/g_gpu_acct_nvoc.c index aa519c9dcf..5c9f7e7ee4 100644 --- a/src/nvidia/generated/g_gpu_acct_nvoc.c +++ b/src/nvidia/generated/g_gpu_acct_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_GpuAccounting(GpuAccounting *pThis) { __nvoc_init_funcTable_GpuAccounting(pThis); } -NV_STATUS __nvoc_objCreate_GpuAccounting(GpuAccounting **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_GpuAccounting(GpuAccounting **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GpuAccounting *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuAccounting), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GpuAccounting)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuAccounting); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_GpuAccounting(GpuAccounting **ppThis, Dynamic *pParen status = __nvoc_ctor_GpuAccounting(pThis); if (status != NV_OK) goto __nvoc_objCreate_GpuAccounting_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GpuAccounting_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GpuAccounting)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_acct_nvoc.h b/src/nvidia/generated/g_gpu_acct_nvoc.h index 96debcb13f..91b557ab2b 100644 --- a/src/nvidia/generated/g_gpu_acct_nvoc.h +++ b/src/nvidia/generated/g_gpu_acct_nvoc.h @@ -124,11 +124,16 @@ typedef struct GPUACCT_VM_INSTANCE_INFO vmInstanceInfo[MAX_VGPU_DEVICES_PER_PGPU]; } GPUACCT_GPU_INSTANCE_INFO; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_ACCT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GpuAccounting { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c index aee661c35f..6cfcb3d50f 100644 --- a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c +++ b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_OBJGPUBOOSTMGR(OBJGPUBOOSTMGR *pThis) { __nvoc_init_funcTable_OBJGPUBOOSTMGR(pThis); } -NV_STATUS __nvoc_objCreate_OBJGPUBOOSTMGR(OBJGPUBOOSTMGR **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJGPUBOOSTMGR(OBJGPUBOOSTMGR **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJGPUBOOSTMGR *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUBOOSTMGR), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJGPUBOOSTMGR)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUBOOSTMGR); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_OBJGPUBOOSTMGR(OBJGPUBOOSTMGR **ppThis, Dynamic *pPar status = __nvoc_ctor_OBJGPUBOOSTMGR(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJGPUBOOSTMGR_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJGPUBOOSTMGR_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJGPUBOOSTMGR)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h index 4e72d95358..bcce325777 100644 --- a/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_boost_mgr_nvoc.h @@ -89,18 +89,22 @@ typedef struct SYNC_GPU_BOOST_GROUP NvBool bBridgeless; } SYNC_GPU_BOOST_GROUP; -typedef struct OBJGPUBOOSTMGR *POBJGPUBOOSTMGR; /*! * This is the Sync Gpu Boost Manager for RM. It keeps track of the * Sync Gpu Boost Groups defined for the system and provides various methods related * to their management. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_BOOST_MGR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJGPUBOOSTMGR { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_gpu_class_list.c b/src/nvidia/generated/g_gpu_class_list.c index a579eda6f9..395d2d38ab 100644 --- a/src/nvidia/generated/g_gpu_class_list.c +++ b/src/nvidia/generated/g_gpu_class_list.c @@ -45,6 +45,7 @@ gpuGetClassDescriptorList_TU102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -110,6 +111,7 @@ gpuGetClassDescriptorList_TU104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -176,6 +178,7 @@ gpuGetClassDescriptorList_TU106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -243,6 +246,7 @@ gpuGetClassDescriptorList_TU116(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -308,6 +312,7 @@ gpuGetClassDescriptorList_TU117(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -392,6 +397,7 @@ gpuGetClassDescriptorList_GA100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -456,6 +462,7 @@ gpuGetClassDescriptorList_GA102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -527,6 +534,7 @@ gpuGetClassDescriptorList_GA103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -598,6 +606,7 @@ gpuGetClassDescriptorList_GA104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -669,6 +678,7 @@ gpuGetClassDescriptorList_GA106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -740,6 +750,7 @@ gpuGetClassDescriptorList_GA107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -811,6 +822,7 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -854,7 +866,7 @@ gpuGetClassDescriptorList_AD102(POBJGPU pGpu, NvU32 *pNumClassDescriptors) #define HALAD102_NUM_CLASS_DESCS (sizeof(halAD102ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - #define HALAD102_NUM_CLASSES 59 + #define HALAD102_NUM_CLASSES 60 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD102_NUM_CLASSES); @@ -890,6 +902,7 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -933,7 +946,7 @@ gpuGetClassDescriptorList_AD103(POBJGPU pGpu, NvU32 *pNumClassDescriptors) #define HALAD103_NUM_CLASS_DESCS (sizeof(halAD103ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - #define HALAD103_NUM_CLASSES 59 + #define HALAD103_NUM_CLASSES 60 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD103_NUM_CLASSES); @@ -969,6 +982,7 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -1012,7 +1026,7 @@ gpuGetClassDescriptorList_AD104(POBJGPU pGpu, NvU32 *pNumClassDescriptors) #define HALAD104_NUM_CLASS_DESCS (sizeof(halAD104ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - #define HALAD104_NUM_CLASSES 59 + #define HALAD104_NUM_CLASSES 60 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD104_NUM_CLASSES); @@ -1048,6 +1062,7 @@ gpuGetClassDescriptorList_AD106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -1091,7 +1106,7 @@ gpuGetClassDescriptorList_AD106(POBJGPU pGpu, NvU32 *pNumClassDescriptors) #define HALAD106_NUM_CLASS_DESCS (sizeof(halAD106ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - #define HALAD106_NUM_CLASSES 59 + #define HALAD106_NUM_CLASSES 60 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD106_NUM_CLASSES); @@ -1127,6 +1142,7 @@ gpuGetClassDescriptorList_AD107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { GF100_ZBC_CLEAR, ENG_KERNEL_MEMORY_SYSTEM }, { GP100_UVM_SW, ENG_SW }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, @@ -1170,7 +1186,7 @@ gpuGetClassDescriptorList_AD107(POBJGPU pGpu, NvU32 *pNumClassDescriptors) #define HALAD107_NUM_CLASS_DESCS (sizeof(halAD107ClassDescriptorList) / sizeof(CLASSDESCRIPTOR)) - #define HALAD107_NUM_CLASSES 59 + #define HALAD107_NUM_CLASSES 60 ct_assert(NV0080_CTRL_GPU_CLASSLIST_MAX_SIZE >= HALAD107_NUM_CLASSES); @@ -1219,6 +1235,7 @@ gpuGetClassDescriptorList_GH100(POBJGPU pGpu, NvU32 *pNumClassDescriptors) { HOPPER_SEC2_WORK_LAUNCH_A, ENG_SEC2 }, { HOPPER_USERMODE_A, ENG_GPU }, { KEPLER_CHANNEL_GROUP_A, ENG_KERNEL_FIFO }, + { KEPLER_DEVICE_VGPU, ENG_GPU }, { KEPLER_INLINE_TO_MEMORY_B, ENG_GR(0) }, { MMU_FAULT_BUFFER, ENG_GR(0) }, { NV0060_SYNC_GPU_BOOST, ENG_GPU }, diff --git a/src/nvidia/generated/g_gpu_db_nvoc.c b/src/nvidia/generated/g_gpu_db_nvoc.c index f39488484f..d71351dc26 100644 --- a/src/nvidia/generated/g_gpu_db_nvoc.c +++ b/src/nvidia/generated/g_gpu_db_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_GpuDb(GpuDb *pThis) { __nvoc_init_funcTable_GpuDb(pThis); } -NV_STATUS __nvoc_objCreate_GpuDb(GpuDb **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_GpuDb(GpuDb **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GpuDb *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuDb), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GpuDb)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuDb); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_GpuDb(GpuDb **ppThis, Dynamic *pParent, NvU32 createF status = __nvoc_ctor_GpuDb(pThis); if (status != NV_OK) goto __nvoc_objCreate_GpuDb_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GpuDb_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GpuDb)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_db_nvoc.h b/src/nvidia/generated/g_gpu_db_nvoc.h index 90f25eaf41..42d33ff1ea 100644 --- a/src/nvidia/generated/g_gpu_db_nvoc.h +++ b/src/nvidia/generated/g_gpu_db_nvoc.h @@ -91,11 +91,16 @@ typedef struct MAKE_LIST(GpuInfoList, GPU_INFO_LIST_NODE); + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_DB_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GpuDb { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_gpu_group_nvoc.c b/src/nvidia/generated/g_gpu_group_nvoc.c index 984180bebf..5636517e3d 100644 --- a/src/nvidia/generated/g_gpu_group_nvoc.c +++ b/src/nvidia/generated/g_gpu_group_nvoc.c @@ -103,21 +103,26 @@ void __nvoc_init_OBJGPUGRP(OBJGPUGRP *pThis) { __nvoc_init_funcTable_OBJGPUGRP(pThis); } -NV_STATUS __nvoc_objCreate_OBJGPUGRP(OBJGPUGRP **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJGPUGRP(OBJGPUGRP **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJGPUGRP *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUGRP), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJGPUGRP)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUGRP); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -132,16 +137,25 @@ NV_STATUS __nvoc_objCreate_OBJGPUGRP(OBJGPUGRP **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_OBJGPUGRP(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJGPUGRP_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJGPUGRP_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJGPUGRP)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_group_nvoc.h b/src/nvidia/generated/g_gpu_group_nvoc.h index 4d1886d034..18ac1223b6 100644 --- a/src/nvidia/generated/g_gpu_group_nvoc.h +++ b/src/nvidia/generated/g_gpu_group_nvoc.h @@ -116,24 +116,17 @@ typedef struct _def_vid_link_node NvU32 ChildDrPort; } SLILINKNODE; -typedef struct OBJGPUGRP *POBJGPUGRP; - -#ifndef __NVOC_CLASS_OBJGPUGRP_TYPEDEF__ -#define __NVOC_CLASS_OBJGPUGRP_TYPEDEF__ -typedef struct OBJGPUGRP OBJGPUGRP; -#endif /* __NVOC_CLASS_OBJGPUGRP_TYPEDEF__ */ - -#ifndef __nvoc_class_id_OBJGPUGRP -#define __nvoc_class_id_OBJGPUGRP 0xe40531 -#endif /* __nvoc_class_id_OBJGPUGRP */ - +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_GROUP_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJGPUGRP { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_gpu_halspec_nvoc.h b/src/nvidia/generated/g_gpu_halspec_nvoc.h index 2889c83ba7..926b0df9ab 100644 --- a/src/nvidia/generated/g_gpu_halspec_nvoc.h +++ b/src/nvidia/generated/g_gpu_halspec_nvoc.h @@ -36,11 +36,16 @@ extern "C" { #include "g_chips2halspec.h" // NVOC halspec, generated by rmconfig.pl + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_HALSPEC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RmHalspecOwner { const struct NVOC_RTTI *__nvoc_rtti; struct RmHalspecOwner *__nvoc_pbase_RmHalspecOwner; diff --git a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c index 0c4743d6e7..5de123bae1 100644 --- a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c +++ b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_gisubscriptionControl_Epilogue(struct GPUIns rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gisubscriptionControlLookup(struct GPUInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle(struct GPUInstanceSubscription *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_GPUInstanceSubscription_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RmResource_gisubscriptionControlSerialization_Prol return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_gisubscriptionIsPartialUnmapSupported(struct GPUInstanceSubscription *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_gisubscriptionPreDestruct(struct GPUInstanceSubscription *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GPUInstanceSubscription_RsResource.offset)); } @@ -302,6 +302,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GPUInsta /*pClassInfo=*/ &(__nvoc_class_def_GPUInstanceSubscription.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity" +#endif + }, + { /* [7] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) gisubscriptionCtrlCmdGetUuid_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xc63701aau, + /*paramSize=*/ sizeof(NVC637_CTRL_GET_UUID_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_GPUInstanceSubscription.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "gisubscriptionCtrlCmdGetUuid" #endif }, @@ -309,7 +324,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_GPUInsta const struct NVOC_EXPORT_INFO __nvoc_export_info_GPUInstanceSubscription = { - /*numEntries=*/ 7, + /*numEntries=*/ 8, /*pExportEntries=*/ __nvoc_exported_method_def_GPUInstanceSubscription }; @@ -376,6 +391,10 @@ static void __nvoc_init_funcTable_GPUInstanceSubscription_1(GPUInstanceSubscript pThis->__gisubscriptionCtrlCmdExecPartitionsImport__ = &gisubscriptionCtrlCmdExecPartitionsImport_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__gisubscriptionCtrlCmdGetUuid__ = &gisubscriptionCtrlCmdGetUuid_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_GPUInstanceSubscription_resCanCopy; pThis->__gisubscriptionShareCallback__ = &__nvoc_thunk_GpuResource_gisubscriptionShareCallback; @@ -400,8 +419,6 @@ static void __nvoc_init_funcTable_GPUInstanceSubscription_1(GPUInstanceSubscript pThis->__gisubscriptionControl_Epilogue__ = &__nvoc_thunk_RmResource_gisubscriptionControl_Epilogue; - pThis->__gisubscriptionControlLookup__ = &__nvoc_thunk_RsResource_gisubscriptionControlLookup; - pThis->__gisubscriptionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_gisubscriptionGetInternalObjectHandle; pThis->__gisubscriptionControl__ = &__nvoc_thunk_GpuResource_gisubscriptionControl; @@ -416,6 +433,8 @@ static void __nvoc_init_funcTable_GPUInstanceSubscription_1(GPUInstanceSubscript pThis->__gisubscriptionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gisubscriptionControlSerialization_Prologue; + pThis->__gisubscriptionIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_gisubscriptionIsPartialUnmapSupported; + pThis->__gisubscriptionPreDestruct__ = &__nvoc_thunk_RsResource_gisubscriptionPreDestruct; pThis->__gisubscriptionIsDuplicate__ = &__nvoc_thunk_RsResource_gisubscriptionIsDuplicate; @@ -443,21 +462,26 @@ void __nvoc_init_GPUInstanceSubscription(GPUInstanceSubscription *pThis) { __nvoc_init_funcTable_GPUInstanceSubscription(pThis); } -NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GPUInstanceSubscription *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GPUInstanceSubscription), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GPUInstanceSubscription)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GPUInstanceSubscription); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -472,16 +496,25 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription **ppT status = __nvoc_ctor_GPUInstanceSubscription(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_GPUInstanceSubscription_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GPUInstanceSubscription_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GPUInstanceSubscription)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h index 9d766eef22..8f9c1c74b5 100644 --- a/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h +++ b/src/nvidia/generated/g_gpu_instance_subscription_nvoc.h @@ -49,11 +49,16 @@ extern "C" { // Type Definitions // **************************************************************************** + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GPUInstanceSubscription { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -71,6 +76,7 @@ struct GPUInstanceSubscription { NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsGetActiveIds__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsExport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsImport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdGetUuid__)(struct GPUInstanceSubscription *, NVC637_CTRL_GET_UUID_PARAMS *); NvBool (*__gisubscriptionShareCallback__)(struct GPUInstanceSubscription *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__gisubscriptionCheckMemInterUnmap__)(struct GPUInstanceSubscription *, NvBool); NV_STATUS (*__gisubscriptionMapTo__)(struct GPUInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); @@ -82,7 +88,6 @@ struct GPUInstanceSubscription { NV_STATUS (*__gisubscriptionInternalControlForward__)(struct GPUInstanceSubscription *, NvU32, void *, NvU32); NV_STATUS (*__gisubscriptionUnmapFrom__)(struct GPUInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); void (*__gisubscriptionControl_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gisubscriptionControlLookup__)(struct GPUInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__gisubscriptionGetInternalObjectHandle__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionControl__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionUnmap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -90,6 +95,7 @@ struct GPUInstanceSubscription { NV_STATUS (*__gisubscriptionGetMemoryMappingDescriptor__)(struct GPUInstanceSubscription *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__gisubscriptionControlFilter__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionControlSerialization_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__gisubscriptionIsPartialUnmapSupported__)(struct GPUInstanceSubscription *); void (*__gisubscriptionPreDestruct__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionIsDuplicate__)(struct GPUInstanceSubscription *, NvHandle, NvBool *); void (*__gisubscriptionControlSerialization_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -118,6 +124,7 @@ struct GPUInstanceSubscription_PRIVATE { NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsGetActiveIds__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_GET_ACTIVE_IDS_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsExport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); NV_STATUS (*__gisubscriptionCtrlCmdExecPartitionsImport__)(struct GPUInstanceSubscription *, NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *); + NV_STATUS (*__gisubscriptionCtrlCmdGetUuid__)(struct GPUInstanceSubscription *, NVC637_CTRL_GET_UUID_PARAMS *); NvBool (*__gisubscriptionShareCallback__)(struct GPUInstanceSubscription *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__gisubscriptionCheckMemInterUnmap__)(struct GPUInstanceSubscription *, NvBool); NV_STATUS (*__gisubscriptionMapTo__)(struct GPUInstanceSubscription *, RS_RES_MAP_TO_PARAMS *); @@ -129,7 +136,6 @@ struct GPUInstanceSubscription_PRIVATE { NV_STATUS (*__gisubscriptionInternalControlForward__)(struct GPUInstanceSubscription *, NvU32, void *, NvU32); NV_STATUS (*__gisubscriptionUnmapFrom__)(struct GPUInstanceSubscription *, RS_RES_UNMAP_FROM_PARAMS *); void (*__gisubscriptionControl_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gisubscriptionControlLookup__)(struct GPUInstanceSubscription *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__gisubscriptionGetInternalObjectHandle__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionControl__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionUnmap__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -137,6 +143,7 @@ struct GPUInstanceSubscription_PRIVATE { NV_STATUS (*__gisubscriptionGetMemoryMappingDescriptor__)(struct GPUInstanceSubscription *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__gisubscriptionControlFilter__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gisubscriptionControlSerialization_Prologue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__gisubscriptionIsPartialUnmapSupported__)(struct GPUInstanceSubscription *); void (*__gisubscriptionPreDestruct__)(struct GPUInstanceSubscription *); NV_STATUS (*__gisubscriptionIsDuplicate__)(struct GPUInstanceSubscription *, NvHandle, NvBool *); void (*__gisubscriptionControlSerialization_Epilogue__)(struct GPUInstanceSubscription *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -184,6 +191,7 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription**, Dy #define gisubscriptionCtrlCmdExecPartitionsGetActiveIds(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsGetActiveIds_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsExport(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsExport_DISPATCH(arg0, arg1) #define gisubscriptionCtrlCmdExecPartitionsImport(arg0, arg1) gisubscriptionCtrlCmdExecPartitionsImport_DISPATCH(arg0, arg1) +#define gisubscriptionCtrlCmdGetUuid(arg0, arg1) gisubscriptionCtrlCmdGetUuid_DISPATCH(arg0, arg1) #define gisubscriptionShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) gisubscriptionShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define gisubscriptionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) gisubscriptionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define gisubscriptionMapTo(pResource, pParams) gisubscriptionMapTo_DISPATCH(pResource, pParams) @@ -195,7 +203,6 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription**, Dy #define gisubscriptionInternalControlForward(pGpuResource, command, pParams, size) gisubscriptionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define gisubscriptionUnmapFrom(pResource, pParams) gisubscriptionUnmapFrom_DISPATCH(pResource, pParams) #define gisubscriptionControl_Epilogue(pResource, pCallContext, pParams) gisubscriptionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define gisubscriptionControlLookup(pResource, pParams, ppEntry) gisubscriptionControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gisubscriptionGetInternalObjectHandle(pGpuResource) gisubscriptionGetInternalObjectHandle_DISPATCH(pGpuResource) #define gisubscriptionControl(pGpuResource, pCallContext, pParams) gisubscriptionControl_DISPATCH(pGpuResource, pCallContext, pParams) #define gisubscriptionUnmap(pGpuResource, pCallContext, pCpuMapping) gisubscriptionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -203,6 +210,7 @@ NV_STATUS __nvoc_objCreate_GPUInstanceSubscription(GPUInstanceSubscription**, Dy #define gisubscriptionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) gisubscriptionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define gisubscriptionControlFilter(pResource, pCallContext, pParams) gisubscriptionControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gisubscriptionControlSerialization_Prologue(pResource, pCallContext, pParams) gisubscriptionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gisubscriptionIsPartialUnmapSupported(pResource) gisubscriptionIsPartialUnmapSupported_DISPATCH(pResource) #define gisubscriptionPreDestruct(pResource) gisubscriptionPreDestruct_DISPATCH(pResource) #define gisubscriptionIsDuplicate(pResource, hMemory, pDuplicate) gisubscriptionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gisubscriptionControlSerialization_Epilogue(pResource, pCallContext, pParams) gisubscriptionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -256,6 +264,12 @@ static inline NV_STATUS gisubscriptionCtrlCmdExecPartitionsImport_DISPATCH(struc return arg0->__gisubscriptionCtrlCmdExecPartitionsImport__(arg0, arg1); } +NV_STATUS gisubscriptionCtrlCmdGetUuid_IMPL(struct GPUInstanceSubscription *arg0, NVC637_CTRL_GET_UUID_PARAMS *arg1); + +static inline NV_STATUS gisubscriptionCtrlCmdGetUuid_DISPATCH(struct GPUInstanceSubscription *arg0, NVC637_CTRL_GET_UUID_PARAMS *arg1) { + return arg0->__gisubscriptionCtrlCmdGetUuid__(arg0, arg1); +} + static inline NvBool gisubscriptionShareCallback_DISPATCH(struct GPUInstanceSubscription *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__gisubscriptionShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -300,10 +314,6 @@ static inline void gisubscriptionControl_Epilogue_DISPATCH(struct GPUInstanceSub pResource->__gisubscriptionControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gisubscriptionControlLookup_DISPATCH(struct GPUInstanceSubscription *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gisubscriptionControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle gisubscriptionGetInternalObjectHandle_DISPATCH(struct GPUInstanceSubscription *pGpuResource) { return pGpuResource->__gisubscriptionGetInternalObjectHandle__(pGpuResource); } @@ -332,6 +342,10 @@ static inline NV_STATUS gisubscriptionControlSerialization_Prologue_DISPATCH(str return pResource->__gisubscriptionControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool gisubscriptionIsPartialUnmapSupported_DISPATCH(struct GPUInstanceSubscription *pResource) { + return pResource->__gisubscriptionIsPartialUnmapSupported__(pResource); +} + static inline void gisubscriptionPreDestruct_DISPATCH(struct GPUInstanceSubscription *pResource) { pResource->__gisubscriptionPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c index 627c208e71..e4635a1afc 100644 --- a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c +++ b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_gpumgmtapiAddAdditionalDependants(struct RsC resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmapFrom(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Prologue(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmap(struct GpuManagementApi return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_gpumgmtapiIsPartialUnmapSupported(struct GpuManagementApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_gpumgmtapiPreDestruct(struct GpuManagementApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_gpumgmtapiControl_Epilogue(struct GpuManagem rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiControlLookup(struct GpuManagementApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiUnmapFrom(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuManagementApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_gpumgmtapiMap(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -251,8 +251,6 @@ static void __nvoc_init_funcTable_GpuManagementApi_1(GpuManagementApi *pThis) { pThis->__gpumgmtapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpumgmtapiAddAdditionalDependants; - pThis->__gpumgmtapiUnmapFrom__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmapFrom; - pThis->__gpumgmtapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpumgmtapiControlSerialization_Prologue; pThis->__gpumgmtapiControl_Prologue__ = &__nvoc_thunk_RmResource_gpumgmtapiControl_Prologue; @@ -261,6 +259,8 @@ static void __nvoc_init_funcTable_GpuManagementApi_1(GpuManagementApi *pThis) { pThis->__gpumgmtapiUnmap__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmap; + pThis->__gpumgmtapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_gpumgmtapiIsPartialUnmapSupported; + pThis->__gpumgmtapiPreDestruct__ = &__nvoc_thunk_RsResource_gpumgmtapiPreDestruct; pThis->__gpumgmtapiMapTo__ = &__nvoc_thunk_RsResource_gpumgmtapiMapTo; @@ -271,7 +271,7 @@ static void __nvoc_init_funcTable_GpuManagementApi_1(GpuManagementApi *pThis) { pThis->__gpumgmtapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gpumgmtapiControl_Epilogue; - pThis->__gpumgmtapiControlLookup__ = &__nvoc_thunk_RsResource_gpumgmtapiControlLookup; + pThis->__gpumgmtapiUnmapFrom__ = &__nvoc_thunk_RsResource_gpumgmtapiUnmapFrom; pThis->__gpumgmtapiMap__ = &__nvoc_thunk_RsResource_gpumgmtapiMap; @@ -293,21 +293,26 @@ void __nvoc_init_GpuManagementApi(GpuManagementApi *pThis) { __nvoc_init_funcTable_GpuManagementApi(pThis); } -NV_STATUS __nvoc_objCreate_GpuManagementApi(GpuManagementApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_GpuManagementApi(GpuManagementApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GpuManagementApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuManagementApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GpuManagementApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuManagementApi); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -322,16 +327,25 @@ NV_STATUS __nvoc_objCreate_GpuManagementApi(GpuManagementApi **ppThis, Dynamic * status = __nvoc_ctor_GpuManagementApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_GpuManagementApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GpuManagementApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GpuManagementApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h index 4d8ca1b5c1..6fa2b0b8df 100644 --- a/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgmt_api_nvoc.h @@ -47,11 +47,16 @@ extern "C" { // and persistent GPU state // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_MGMT_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GpuManagementApi { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -69,17 +74,17 @@ struct GpuManagementApi { NvU32 (*__gpumgmtapiGetRefCount__)(struct GpuManagementApi *); NV_STATUS (*__gpumgmtapiControlFilter__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpumgmtapiAddAdditionalDependants__)(struct RsClient *, struct GpuManagementApi *, RsResourceRef *); - NV_STATUS (*__gpumgmtapiUnmapFrom__)(struct GpuManagementApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__gpumgmtapiControlSerialization_Prologue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpumgmtapiControl_Prologue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gpumgmtapiCanCopy__)(struct GpuManagementApi *); NV_STATUS (*__gpumgmtapiUnmap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__gpumgmtapiIsPartialUnmapSupported__)(struct GpuManagementApi *); void (*__gpumgmtapiPreDestruct__)(struct GpuManagementApi *); NV_STATUS (*__gpumgmtapiMapTo__)(struct GpuManagementApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__gpumgmtapiIsDuplicate__)(struct GpuManagementApi *, NvHandle, NvBool *); void (*__gpumgmtapiControlSerialization_Epilogue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpumgmtapiControl_Epilogue__)(struct GpuManagementApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gpumgmtapiControlLookup__)(struct GpuManagementApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__gpumgmtapiUnmapFrom__)(struct GpuManagementApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__gpumgmtapiMap__)(struct GpuManagementApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__gpumgmtapiAccessCallback__)(struct GpuManagementApi *, struct RsClient *, void *, RsAccessRight); }; @@ -121,17 +126,17 @@ NV_STATUS __nvoc_objCreate_GpuManagementApi(GpuManagementApi**, Dynamic*, NvU32, #define gpumgmtapiGetRefCount(pResource) gpumgmtapiGetRefCount_DISPATCH(pResource) #define gpumgmtapiControlFilter(pResource, pCallContext, pParams) gpumgmtapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiAddAdditionalDependants(pClient, pResource, pReference) gpumgmtapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define gpumgmtapiUnmapFrom(pResource, pParams) gpumgmtapiUnmapFrom_DISPATCH(pResource, pParams) #define gpumgmtapiControlSerialization_Prologue(pResource, pCallContext, pParams) gpumgmtapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControl_Prologue(pResource, pCallContext, pParams) gpumgmtapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiCanCopy(pResource) gpumgmtapiCanCopy_DISPATCH(pResource) #define gpumgmtapiUnmap(pResource, pCallContext, pCpuMapping) gpumgmtapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define gpumgmtapiIsPartialUnmapSupported(pResource) gpumgmtapiIsPartialUnmapSupported_DISPATCH(pResource) #define gpumgmtapiPreDestruct(pResource) gpumgmtapiPreDestruct_DISPATCH(pResource) #define gpumgmtapiMapTo(pResource, pParams) gpumgmtapiMapTo_DISPATCH(pResource, pParams) #define gpumgmtapiIsDuplicate(pResource, hMemory, pDuplicate) gpumgmtapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gpumgmtapiControlSerialization_Epilogue(pResource, pCallContext, pParams) gpumgmtapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpumgmtapiControl_Epilogue(pResource, pCallContext, pParams) gpumgmtapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define gpumgmtapiControlLookup(pResource, pParams, ppEntry) gpumgmtapiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gpumgmtapiUnmapFrom(pResource, pParams) gpumgmtapiUnmapFrom_DISPATCH(pResource, pParams) #define gpumgmtapiMap(pResource, pCallContext, pParams, pCpuMapping) gpumgmtapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define gpumgmtapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpumgmtapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS gpumgmtapiCtrlCmdSetShutdownState_IMPL(struct GpuManagementApi *pGpuMgmt, NV0020_CTRL_GPU_MGMT_SET_SHUTDOWN_STATE_PARAMS *pParams); @@ -172,10 +177,6 @@ static inline void gpumgmtapiAddAdditionalDependants_DISPATCH(struct RsClient *p pResource->__gpumgmtapiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS gpumgmtapiUnmapFrom_DISPATCH(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gpumgmtapiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS gpumgmtapiControlSerialization_Prologue_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gpumgmtapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -192,6 +193,10 @@ static inline NV_STATUS gpumgmtapiUnmap_DISPATCH(struct GpuManagementApi *pResou return pResource->__gpumgmtapiUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool gpumgmtapiIsPartialUnmapSupported_DISPATCH(struct GpuManagementApi *pResource) { + return pResource->__gpumgmtapiIsPartialUnmapSupported__(pResource); +} + static inline void gpumgmtapiPreDestruct_DISPATCH(struct GpuManagementApi *pResource) { pResource->__gpumgmtapiPreDestruct__(pResource); } @@ -212,8 +217,8 @@ static inline void gpumgmtapiControl_Epilogue_DISPATCH(struct GpuManagementApi * pResource->__gpumgmtapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpumgmtapiControlLookup_DISPATCH(struct GpuManagementApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gpumgmtapiControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS gpumgmtapiUnmapFrom_DISPATCH(struct GpuManagementApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gpumgmtapiUnmapFrom__(pResource, pParams); } static inline NV_STATUS gpumgmtapiMap_DISPATCH(struct GpuManagementApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.c b/src/nvidia/generated/g_gpu_mgr_nvoc.c index 832a2b7e82..9b8e503566 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.c +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_OBJGPUMGR(OBJGPUMGR *pThis) { __nvoc_init_funcTable_OBJGPUMGR(pThis); } -NV_STATUS __nvoc_objCreate_OBJGPUMGR(OBJGPUMGR **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJGPUMGR(OBJGPUMGR **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJGPUMGR *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUMGR), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJGPUMGR)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUMGR); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_OBJGPUMGR(OBJGPUMGR **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_OBJGPUMGR(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJGPUMGR_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJGPUMGR_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJGPUMGR)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.h b/src/nvidia/generated/g_gpu_mgr_nvoc.h index 1a84702be6..ebfbfd2b4a 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.h @@ -127,6 +127,8 @@ typedef struct CONF_COMPUTE_CAPS NvBool bCCFeatureEnabled; NvBool bDevToolsModeEnabled; NvBool bAcceptClientRequest; + NvBool bMultiGpuProtectedPcieModeEnabled; + NvBool bFatalFailure; } CONF_COMPUTE_CAPS; // @@ -140,14 +142,6 @@ typedef struct CONF_COMPUTE_CAPS #define SLI_BT_VIDLINK 0 #define SLI_BT_NVLINK 1 -/*! - * SLI link detection HAL flag defines for Sli/Vid/NvLink link detection HAL functions. - */ -#define GPU_LINK_DETECTION_HAL_STUB 0 -#define GPU_LINK_DETECTION_HAL_GK104 1 -#define GPU_LINK_DETECTION_HAL_GP100 2 -#define GPU_LINK_DETECTION_HAL_GP102 3 - // // GPU NVLINK reduced bandwidth mode // @@ -271,11 +265,16 @@ typedef struct PCIEP2PCAPSINFO } PCIEP2PCAPSINFO; MAKE_INTRUSIVE_LIST(pcieP2PCapsInfoList, PCIEP2PCAPSINFO, node); + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_MGR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJGPUMGR { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -476,6 +475,7 @@ typedef struct GPUATTACHARG NvU32 socChipId0; NvU32 iovaspaceId; NvBool bRequestFwClientRm; + NvS32 cpuNumaNodeId; // // The SOC-specific fields above are legacy fields that were added for @@ -489,6 +489,10 @@ typedef struct GPUATTACHARG SOCGPUATTACHARG socDeviceArgs; } GPUATTACHARG; +NV_STATUS gpumgrThreadEnableExpandedGpuVisibility(void); +void gpumgrThreadDisableExpandedGpuVisibility(void); +NvBool gpumgrThreadHasExpandedGpuVisibility(void); + NV_STATUS gpumgrGetGpuAttachInfo(NvU32 *pGpuCnt, NvU32 *pGpuMask); NV_STATUS gpumgrGetProbedGpuIds(NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *); NV_STATUS gpumgrGetProbedGpuDomainBusDevice(NvU32 gpuId, NvU64 *gpuDomainBusDevice); @@ -517,6 +521,7 @@ void gpumgrGetRmFirmwarePolicy(NvU32 chipId, NvU32 pmcBoot42, NvBool bIsS NvBool gpumgrGetRmFirmwareLogsEnabled(NvU32 enableFirmwareLogsRegVal); NvBool gpumgrIsDeviceRmFirmwareCapable(NvU16 devId, NvU32 pmcBoot42, NvBool bIsSoc, NvBool *pbEnableByDefault); +NvBool gpumgrIsVgxRmFirmwareCapableChip(NvU32 pmcBoot42); NV_STATUS gpumgrAttachGpu(NvU32 deviceInstance, GPUATTACHARG *); NV_STATUS gpumgrDetachGpu(NvU32 deviceInstance); OBJGPU* gpumgrGetNextGpu(NvU32 gpuMask, NvU32 *pStartIndex); @@ -556,6 +561,7 @@ struct OBJGPUGRP* gpumgrGetGpuGrpFromInstance(NvU32 gpugrpInstance); NV_STATUS gpumgrModifyGpuDrainState(NvU32 gpuId, NvBool bEnable, NvBool bRemove, NvBool bLinkDisable); NV_STATUS gpumgrQueryGpuDrainState(NvU32 gpuId, NvBool *pBEnable, NvBool *pBRemove); NvBool gpumgrIsGpuPointerValid(OBJGPU *pGpu); +NvBool gpumgrIsGpuPointerAttached(OBJGPU *pGpu); NvU32 gpumgrGetGrpMaskFromGpuInst(NvU32 gpuInst); void gpumgrAddDeviceMaskToGpuInstTable(NvU32 gpuMask); void gpumgrClearDeviceMaskFromGpuInstTable(NvU32 gpuMask); @@ -564,6 +570,7 @@ void gpumgrSetGpuRelease(void); NvU8 gpumgrGetGpuBridgeType(void); NvBool gpumgrAreAllGpusInOffloadMode(void); NvBool gpumgrIsSafeToReadGpuInfo(void); +NvBool gpumgrIsDeviceMsixAllowed(RmPhysAddr bar0BaseAddr, NvU32 pmcBoot1, NvU32 pmcBoot42); // // gpumgrIsSubDeviceCountOne diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index 3da98be859..472cc2dee3 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -25,7 +25,7 @@ void __nvoc_init_OBJGPU(OBJGPU*, TEGRA_CHIP_TYPE TegraChipHal_tegraType, NvU32 DispIpHal_ipver); void __nvoc_init_funcTable_OBJGPU(OBJGPU*); -NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU*, NvU32 arg_gpuInstance); +NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU*, NvU32 arg_gpuInstance, NvU32 arg_gpuId, NvUuid * arg_pUuid); void __nvoc_init_dataField_OBJGPU(OBJGPU*); void __nvoc_dtor_OBJGPU(OBJGPU*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_OBJGPU; @@ -199,6 +199,28 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_IS_COT_ENABLED, ((NvBool)(0 != 0))); } + // Hal field -- bIsFlexibleFlaSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bIsFlexibleFlaSupported = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bIsFlexibleFlaSupported = ((NvBool)(0 != 0)); + } + + // NVOC Property Hal field -- PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED, ((NvBool)(0 != 0))); + } + // NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { @@ -273,12 +295,18 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->setProperty(pThis, PDB_PROP_GPU_IS_SOC_SDM, ((NvBool)(0 != 0))); } - pThis->boardId = ~0; + // NVOC Property Hal field -- PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS + pThis->setProperty(pThis, PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS, ((NvBool)(0 == 0))); + pThis->setProperty(pThis, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, ((NvBool)(0 != 0))); pThis->deviceInstance = 32; // Hal field -- isVirtual - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->isVirtual = ((NvBool)(0 == 0)); + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->isVirtual = ((NvBool)(0 != 0)); } @@ -288,6 +316,10 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { { pThis->isGspClient = ((NvBool)(0 == 0)); } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->isGspClient = ((NvBool)(0 != 0)); + } pThis->bIsDebugModeEnabled = ((NvBool)(0 != 0)); @@ -297,6 +329,8 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->boardInfo = ((void *)0); + pThis->bIsMigRm = ((NvBool)(0 != 0)); + // Hal field -- bUnifiedMemorySpaceEnabled // default { @@ -357,8 +391,6 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { pThis->bInstanceMemoryAlwaysCached = ((NvBool)(0 != 0)); } - pThis->bIsGeforce = ((NvBool)(0 == 0)); - // Hal field -- bComputePolicyTimesliceSupported if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { @@ -389,12 +421,29 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } pThis->bIsGspOwnedFaultBuffersEnabled = ((NvBool)(0 != 0)); + + // Hal field -- bVfResizableBAR1Supported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->bVfResizableBAR1Supported = ((NvBool)(0 == 0)); + } + // default + else + { + pThis->bVfResizableBAR1Supported = ((NvBool)(0 != 0)); + } + + // Hal field -- bVoltaHubIntrSupported + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->bVoltaHubIntrSupported = ((NvBool)(0 == 0)); + } } NV_STATUS __nvoc_ctor_Object(Object* ); NV_STATUS __nvoc_ctor_RmHalspecOwner(RmHalspecOwner* ); NV_STATUS __nvoc_ctor_OBJTRACEABLE(OBJTRACEABLE* ); -NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU *pThis, NvU32 arg_gpuInstance) { +NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU *pThis, NvU32 arg_gpuInstance, NvU32 arg_gpuId, NvUuid * arg_pUuid) { NV_STATUS status = NV_OK; status = __nvoc_ctor_Object(&pThis->__nvoc_base_Object); if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_Object; @@ -404,7 +453,7 @@ NV_STATUS __nvoc_ctor_OBJGPU(OBJGPU *pThis, NvU32 arg_gpuInstance) { if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail_OBJTRACEABLE; __nvoc_init_dataField_OBJGPU(pThis); - status = __nvoc_gpuConstruct(pThis, arg_gpuInstance); + status = __nvoc_gpuConstruct(pThis, arg_gpuInstance, arg_gpuId, arg_pUuid); if (status != NV_OK) goto __nvoc_ctor_OBJGPU_fail__init; goto __nvoc_ctor_OBJGPU_exit; // Success @@ -434,7 +483,14 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { // Hal function -- gpuConstructDeviceInfoTable if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_VGPUSTUB; + } + else + { + pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_FWCLIENT; + } } // default else @@ -442,6 +498,96 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuConstructDeviceInfoTable__ = &gpuConstructDeviceInfoTable_56cd7a; } + // Hal function -- gpuGetNameString + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetNameString__ = &gpuGetNameString_VGPUSTUB; + } + else + { + pThis->__gpuGetNameString__ = &gpuGetNameString_KERNEL; + } + + // Hal function -- gpuGetShortNameString + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetShortNameString__ = &gpuGetShortNameString_VGPUSTUB; + } + else + { + pThis->__gpuGetShortNameString__ = &gpuGetShortNameString_KERNEL; + } + + // Hal function -- gpuInitBranding + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuInitBranding__ = &gpuInitBranding_VGPUSTUB; + } + else + { + pThis->__gpuInitBranding__ = &gpuInitBranding_FWCLIENT; + } + + // Hal function -- gpuInitProperties + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuInitProperties__ = &gpuInitProperties_b3696a; + } + else + { + pThis->__gpuInitProperties__ = &gpuInitProperties_FWCLIENT; + } + + // Hal function -- gpuBuildKernelVideoEngineList + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuBuildKernelVideoEngineList__ = &gpuBuildKernelVideoEngineList_56cd7a; + } + else + { + pThis->__gpuBuildKernelVideoEngineList__ = &gpuBuildKernelVideoEngineList_IMPL; + } + + // Hal function -- gpuInitVideoLogging + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuInitVideoLogging__ = &gpuInitVideoLogging_56cd7a; + } + else + { + pThis->__gpuInitVideoLogging__ = &gpuInitVideoLogging_IMPL; + } + + // Hal function -- gpuFreeVideoLogging + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuFreeVideoLogging__ = &gpuFreeVideoLogging_b3696a; + } + else + { + pThis->__gpuFreeVideoLogging__ = &gpuFreeVideoLogging_IMPL; + } + + // Hal function -- gpuDestroyKernelVideoEngineList + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuDestroyKernelVideoEngineList__ = &gpuDestroyKernelVideoEngineList_b3696a; + } + else + { + pThis->__gpuDestroyKernelVideoEngineList__ = &gpuDestroyKernelVideoEngineList_IMPL; + } + + // Hal function -- gpuPowerOff + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuPowerOff__ = &gpuPowerOff_46f6a7; + } + else + { + pThis->__gpuPowerOff__ = &gpuPowerOff_KERNEL; + } + // Hal function -- gpuWriteBusConfigReg if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -523,6 +669,46 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuGetIdInfo__ = &gpuGetIdInfo_GM107; } + // Hal function -- gpuGenGidData + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGenGidData__ = &gpuGenGidData_VGPUSTUB; + } + else + { + pThis->__gpuGenGidData__ = &gpuGenGidData_FWCLIENT; + } + + // Hal function -- gpuGetChipSubRev + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetChipSubRev__ = &gpuGetChipSubRev_4a4dee; + } + else + { + pThis->__gpuGetChipSubRev__ = &gpuGetChipSubRev_FWCLIENT; + } + + // Hal function -- gpuGetSkuInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetSkuInfo__ = &gpuGetSkuInfo_VGPUSTUB; + } + else + { + pThis->__gpuGetSkuInfo__ = &gpuGetSkuInfo_92bfc3; + } + + // Hal function -- gpuGetRegBaseOffset + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetRegBaseOffset__ = &gpuGetRegBaseOffset_TU102; + } + else + { + pThis->__gpuGetRegBaseOffset__ = &gpuGetRegBaseOffset_FWCLIENT; + } + // Hal function -- gpuHandleSanityCheckRegReadError if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -544,6 +730,23 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuHandleSecFault__ = &gpuHandleSecFault_b3696a; } + // Hal function -- gpuSanityCheckVirtRegAccess + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuSanityCheckVirtRegAccess__ = &gpuSanityCheckVirtRegAccess_GH100; + } + else + { + pThis->__gpuSanityCheckVirtRegAccess__ = &gpuSanityCheckVirtRegAccess_TU102; + } + } + else + { + pThis->__gpuSanityCheckVirtRegAccess__ = &gpuSanityCheckVirtRegAccess_56cd7a; + } + // Hal function -- gpuGetChildrenPresent if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000040UL) )) /* ChipHal: TU104 */ { @@ -618,6 +821,56 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuGetPhysAddrWidth__ = &gpuGetPhysAddrWidth_TU102; } + // Hal function -- gpuInitSriov + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuInitSriov__ = &gpuInitSriov_VGPUSTUB; + } + else + { + pThis->__gpuInitSriov__ = &gpuInitSriov_FWCLIENT; + } + + // Hal function -- gpuDeinitSriov + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuDeinitSriov__ = &gpuDeinitSriov_56cd7a; + } + else + { + pThis->__gpuDeinitSriov__ = &gpuDeinitSriov_FWCLIENT; + } + + // Hal function -- gpuCreateDefaultClientShare + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuCreateDefaultClientShare__ = &gpuCreateDefaultClientShare_VGPUSTUB; + } + else + { + pThis->__gpuCreateDefaultClientShare__ = &gpuCreateDefaultClientShare_56cd7a; + } + + // Hal function -- gpuDestroyDefaultClientShare + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuDestroyDefaultClientShare__ = &gpuDestroyDefaultClientShare_VGPUSTUB; + } + else + { + pThis->__gpuDestroyDefaultClientShare__ = &gpuDestroyDefaultClientShare_b3696a; + } + + // Hal function -- gpuGetVmmuSegmentSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetVmmuSegmentSize__ = &gpuGetVmmuSegmentSize_13cd8d; + } + else + { + pThis->__gpuGetVmmuSegmentSize__ = &gpuGetVmmuSegmentSize_72c522; + } + // Hal function -- gpuFuseSupportsDisplay if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { @@ -632,6 +885,36 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; } + // Hal function -- gpuGetActiveFBIOs + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetActiveFBIOs__ = &gpuGetActiveFBIOs_VGPUSTUB; + } + else + { + pThis->__gpuGetActiveFBIOs__ = &gpuGetActiveFBIOs_FWCLIENT; + } + + // Hal function -- gpuCheckPageRetirementSupport + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuCheckPageRetirementSupport__ = &gpuCheckPageRetirementSupport_VGPUSTUB; + } + else + { + pThis->__gpuCheckPageRetirementSupport__ = &gpuCheckPageRetirementSupport_GSPCLIENT; + } + + // Hal function -- gpuIsInternalSku + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuIsInternalSku__ = &gpuIsInternalSku_491d52; + } + else + { + pThis->__gpuIsInternalSku__ = &gpuIsInternalSku_FWCLIENT; + } + // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { @@ -643,14 +926,62 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuClearFbhubPoisonIntrForBug2924523__ = &gpuClearFbhubPoisonIntrForBug2924523_56cd7a; } - // Hal function -- gpuReadDeviceId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // Hal function -- gpuCheckIfFbhubPoisonIntrPending + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GH100; + pThis->__gpuCheckIfFbhubPoisonIntrPending__ = &gpuCheckIfFbhubPoisonIntrPending_GA100; } + // default else { - pThis->__gpuReadDeviceId__ = &gpuReadDeviceId_GM107; + pThis->__gpuCheckIfFbhubPoisonIntrPending__ = &gpuCheckIfFbhubPoisonIntrPending_491d52; + } + + // Hal function -- gpuGetSriovCaps + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetSriovCaps__ = &gpuGetSriovCaps_46f6a7; + } + else + { + pThis->__gpuGetSriovCaps__ = &gpuGetSriovCaps_TU102; + } + + // Hal function -- gpuCheckIsP2PAllocated + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__gpuCheckIsP2PAllocated__ = &gpuCheckIsP2PAllocated_108313; + } + else + { + pThis->__gpuCheckIsP2PAllocated__ = &gpuCheckIsP2PAllocated_GA100; + } + } + else + { + pThis->__gpuCheckIsP2PAllocated__ = &gpuCheckIsP2PAllocated_491d52; + } + + // Hal function -- gpuPrePowerOff + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuPrePowerOff__ = &gpuPrePowerOff_46f6a7; + } + else + { + pThis->__gpuPrePowerOff__ = &gpuPrePowerOff_56cd7a; + } + + // Hal function -- gpuVerifyExistence + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuVerifyExistence__ = &gpuVerifyExistence_56cd7a; + } + else + { + pThis->__gpuVerifyExistence__ = &gpuVerifyExistence_IMPL; } // Hal function -- gpuGetFlaVasSize @@ -667,6 +998,27 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { pThis->__gpuGetFlaVasSize__ = &gpuGetFlaVasSize_GA100; } + // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_GH100; + } + // default + else + { + pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_491d52; + } + + // Hal function -- gpuIsGlobalPoisonFuseEnabled + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuIsGlobalPoisonFuseEnabled__ = &gpuIsGlobalPoisonFuseEnabled_VGPUSTUB; + } + else + { + pThis->__gpuIsGlobalPoisonFuseEnabled__ = &gpuIsGlobalPoisonFuseEnabled_FWCLIENT; + } + // Hal function -- gpuDetermineSelfHostedMode if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -679,25 +1031,41 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { } // Hal function -- gpuDetermineMIGSupport - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_GH100; + pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a; } - // default else { - pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_GH100; + } + // default + else + { + pThis->__gpuDetermineMIGSupport__ = &gpuDetermineMIGSupport_b3696a; + } } - // Hal function -- gpuIsAtsSupportedWithSmcMemPartitioning - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // Hal function -- gpuInitOptimusSettings + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_GH100; + pThis->__gpuInitOptimusSettings__ = &gpuInitOptimusSettings_56cd7a; } - // default else { - pThis->__gpuIsAtsSupportedWithSmcMemPartitioning__ = &gpuIsAtsSupportedWithSmcMemPartitioning_491d52; + pThis->__gpuInitOptimusSettings__ = &gpuInitOptimusSettings_IMPL; + } + + // Hal function -- gpuDeinitOptimusSettings + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuDeinitOptimusSettings__ = &gpuDeinitOptimusSettings_56cd7a; + } + else + { + pThis->__gpuDeinitOptimusSettings__ = &gpuDeinitOptimusSettings_IMPL; } // Hal function -- gpuIsSliCapableWithoutDisplay @@ -712,14 +1080,21 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { } // Hal function -- gpuIsCCEnabledInHw - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GH100; + pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52; } - // default else { - pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GH100; + } + // default + else + { + pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52; + } } // Hal function -- gpuIsDevModeEnabledInHw @@ -743,6 +1118,73 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { pThis->__gpuIsCtxBufAllocInPmaSupported__ = &gpuIsCtxBufAllocInPmaSupported_491d52; } + + // Hal function -- gpuUpdateErrorContainmentState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__gpuUpdateErrorContainmentState__ = &gpuUpdateErrorContainmentState_f91eed; + } + else + { + pThis->__gpuUpdateErrorContainmentState__ = &gpuUpdateErrorContainmentState_GA100; + } + } + else + { + pThis->__gpuUpdateErrorContainmentState__ = &gpuUpdateErrorContainmentState_c04480; + } + + // Hal function -- gpuCheckEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__gpuCheckEccCounts__ = &gpuCheckEccCounts_TU102; + } + // default + else + { + pThis->__gpuCheckEccCounts__ = &gpuCheckEccCounts_d44104; + } + + // Hal function -- gpuClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__gpuClearEccCounts__ = &gpuClearEccCounts_TU102; + } + // default + else + { + pThis->__gpuClearEccCounts__ = &gpuClearEccCounts_ac1694; + } + + // Hal function -- gpuWaitForGfwBootComplete + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_5baef9; + } + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_TU102; + } + // default + else + { + pThis->__gpuWaitForGfwBootComplete__ = &gpuWaitForGfwBootComplete_5baef9; + } + } + + // Hal function -- gpuGetIsCmpSku + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__gpuGetIsCmpSku__ = &gpuGetIsCmpSku_491d52; + } + else + { + pThis->__gpuGetIsCmpSku__ = &gpuGetIsCmpSku_ceaee8; + } } void __nvoc_init_funcTable_OBJGPU(OBJGPU *pThis) { @@ -771,21 +1213,26 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 creat NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, TEGRA_CHIP_TYPE TegraChipHal_tegraType, - NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance) { + NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance, NvU32 arg_gpuId, NvUuid * arg_pUuid) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJGPU *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPU), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJGPU)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPU); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -797,19 +1244,28 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU32 creat } __nvoc_init_OBJGPU(pThis, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver); - status = __nvoc_ctor_OBJGPU(pThis, arg_gpuInstance); + status = __nvoc_ctor_OBJGPU(pThis, arg_gpuInstance, arg_gpuId, arg_pUuid); if (status != NV_OK) goto __nvoc_objCreate_OBJGPU_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJGPU_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJGPU)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -824,8 +1280,10 @@ NV_STATUS __nvoc_objCreateDynamic_OBJGPU(OBJGPU **ppThis, Dynamic *pParent, NvU3 TEGRA_CHIP_TYPE TegraChipHal_tegraType = va_arg(args, TEGRA_CHIP_TYPE); NvU32 DispIpHal_ipver = va_arg(args, NvU32); NvU32 arg_gpuInstance = va_arg(args, NvU32); + NvU32 arg_gpuId = va_arg(args, NvU32); + NvUuid * arg_pUuid = va_arg(args, NvUuid *); - status = __nvoc_objCreate_OBJGPU(ppThis, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance); + status = __nvoc_objCreate_OBJGPU(ppThis, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance, arg_gpuId, arg_pUuid); return status; } diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 5bfbcc4863..5aa73345b6 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -60,6 +60,7 @@ typedef struct GPUATTACHARG GPUATTACHARG; * */ #include "ctrl/ctrl0000/ctrl0000system.h" #include "ctrl/ctrl0080/ctrl0080gpu.h" // NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS (form hal) +#include "ctrl/ctrl2080/ctrl2080bios.h" #include "ctrl/ctrl2080/ctrl2080internal.h" // NV2080_CTRL_CMD_INTERNAL_MAX_BSPS/NVENCS #include "ctrl/ctrl2080/ctrl2080ecc.h" #include "ctrl/ctrl2080/ctrl2080nvd.h" @@ -77,28 +78,27 @@ typedef struct GPUATTACHARG GPUATTACHARG; #include "platform/acpi_common.h" #include "gpu/gpu_acpi_data.h" -#include "platform/sli/sli.h" #include "core/core.h" -#include "core/system.h" -#include "core/info_block.h" #include "core/hal.h" -#include "nvoc/utility.h" -#include "gpu/mem_mgr/mem_desc.h" -#include "gpu/gpu_resource_desc.h" +#include "core/system.h" #include "diagnostics/traceable.h" -#include "gpu/gpu_uuid.h" -#include "prereq_tracker/prereq_tracker.h" +#include "gpu/error_cont.h" #include "gpu/gpu_halspec.h" +#include "gpu/gpu_resource_desc.h" +#include "gpu/gpu_uuid.h" +#include "gpu/mem_mgr/mem_desc.h" #include "kernel/gpu/gpu_engine_type.h" +#include "nvoc/utility.h" +#include "prereq_tracker/prereq_tracker.h" + +#include "kernel/disp/nvfbc_session.h" +#include "kernel/gpu/nvenc/nvencsession.h" #include "rmapi/control.h" #include "rmapi/event.h" #include "rmapi/rmapi.h" -#include "kernel/gpu/gr/fecs_event_list.h" -#include "class/cl90cdfecs.h" - #include "gpuvideo/videoeventlist.h" #include "gpu/gpu_fabric_probe.h" @@ -312,7 +312,6 @@ typedef struct NV2080_CTRL_GPU_REG_OP NV2080_CTRL_GPU_REG_OP; typedef enum { - BRANDING_TYPE_UNCACHED, BRANDING_TYPE_NONE, BRANDING_TYPE_QUADRO_GENERIC, BRANDING_TYPE_QUADRO_AD, @@ -669,6 +668,15 @@ typedef struct OBJGPU *pGpu; // Mapping from the local pinset number (i.e. array index) to peer GPU NvU32 pinset; // Mapping from the local pinset number (i.e. array index) to peer pinset number } _GPU_SLI_PEER; +#define DR_PINSET_COUNT 2 + +/*! + * SLI link detection HAL flag defines for Sli/Vid/NvLink link detection HAL functions. + */ +#define GPU_LINK_DETECTION_HAL_STUB 0 +#define GPU_LINK_DETECTION_HAL_GK104 1 +#define GPU_LINK_DETECTION_HAL_GP100 2 +#define GPU_LINK_DETECTION_HAL_GP102 3 // @@ -681,6 +689,7 @@ typedef struct #define GPU_STATE_FLAGS_PM_SUSPEND NVBIT(3) #define GPU_STATE_FLAGS_PM_HIBERNATE NVBIT(4) #define GPU_STATE_FLAGS_GC6_TRANSITION NVBIT(5) // To be used with GPU_STATE_FLAGS_PRESERVING. +#define GPU_STATE_FLAGS_FAST_UNLOAD NVBIT(6) // Used during windows restart, skips stateDestroy steps #define GPU_STATE_DEFAULT 0 // Default flags for destructive state loads // and unloads @@ -820,7 +829,7 @@ typedef struct #define GPU_MAX_NVJPGS 8 #define GPU_MAX_HSHUBS 5 #define GPU_MAX_OFAS 1 - +#define GPU_MAX_GSPLITES 4 // // Macro defines for OBJGPU fields -- Macro defines inside NVOC class block is // gone after NVOC preprocessing stage. For macros used outside gpu/gpu.h should @@ -890,11 +899,16 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO DEVICE_INFO2_ENTRY; // // The actual GPU object definition // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJGPU { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -905,6 +919,15 @@ struct OBJGPU { struct OBJTRACEABLE *__nvoc_pbase_OBJTRACEABLE; struct OBJGPU *__nvoc_pbase_OBJGPU; NV_STATUS (*__gpuConstructDeviceInfoTable__)(struct OBJGPU *); + NV_STATUS (*__gpuGetNameString__)(struct OBJGPU *, NvU32, void *); + NV_STATUS (*__gpuGetShortNameString__)(struct OBJGPU *, NvU8 *); + NV_STATUS (*__gpuInitBranding__)(struct OBJGPU *); + void (*__gpuInitProperties__)(struct OBJGPU *); + NV_STATUS (*__gpuBuildKernelVideoEngineList__)(struct OBJGPU *); + NV_STATUS (*__gpuInitVideoLogging__)(struct OBJGPU *); + void (*__gpuFreeVideoLogging__)(struct OBJGPU *); + void (*__gpuDestroyKernelVideoEngineList__)(struct OBJGPU *); + NV_STATUS (*__gpuPowerOff__)(struct OBJGPU *); NV_STATUS (*__gpuWriteBusConfigReg__)(struct OBJGPU *, NvU32, NvU32); NV_STATUS (*__gpuReadBusConfigReg__)(struct OBJGPU *, NvU32, NvU32 *); NV_STATUS (*__gpuReadBusConfigRegEx__)(struct OBJGPU *, NvU32, NvU32 *, THREAD_STATE_NODE *); @@ -913,22 +936,47 @@ struct OBJGPU { NV_STATUS (*__gpuWriteFunctionConfigRegEx__)(struct OBJGPU *, NvU32, NvU32, NvU32, THREAD_STATE_NODE *); NV_STATUS (*__gpuReadVgpuConfigReg__)(struct OBJGPU *, NvU32, NvU32 *); void (*__gpuGetIdInfo__)(struct OBJGPU *); + NV_STATUS (*__gpuGenGidData__)(struct OBJGPU *, NvU8 *, NvU32, NvU32); + NvU8 (*__gpuGetChipSubRev__)(struct OBJGPU *); + NV_STATUS (*__gpuGetSkuInfo__)(struct OBJGPU *, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *); + NV_STATUS (*__gpuGetRegBaseOffset__)(struct OBJGPU *, NvU32, NvU32 *); void (*__gpuHandleSanityCheckRegReadError__)(struct OBJGPU *, NvU32, NvU32); void (*__gpuHandleSecFault__)(struct OBJGPU *); + NV_STATUS (*__gpuSanityCheckVirtRegAccess__)(struct OBJGPU *, NvU32); const GPUCHILDPRESENT *(*__gpuGetChildrenPresent__)(struct OBJGPU *, NvU32 *); const CLASSDESCRIPTOR *(*__gpuGetClassDescriptorList__)(struct OBJGPU *, NvU32 *); NvU32 (*__gpuGetPhysAddrWidth__)(struct OBJGPU *, NV_ADDRESS_SPACE); + NV_STATUS (*__gpuInitSriov__)(struct OBJGPU *); + NV_STATUS (*__gpuDeinitSriov__)(struct OBJGPU *); + NV_STATUS (*__gpuCreateDefaultClientShare__)(struct OBJGPU *); + void (*__gpuDestroyDefaultClientShare__)(struct OBJGPU *); + NvU64 (*__gpuGetVmmuSegmentSize__)(struct OBJGPU *); NvBool (*__gpuFuseSupportsDisplay__)(struct OBJGPU *); + NvU32 (*__gpuGetActiveFBIOs__)(struct OBJGPU *); + NvBool (*__gpuCheckPageRetirementSupport__)(struct OBJGPU *); + NvBool (*__gpuIsInternalSku__)(struct OBJGPU *); NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *); - void (*__gpuReadDeviceId__)(struct OBJGPU *, NvU32 *, NvU32 *); + NvBool (*__gpuCheckIfFbhubPoisonIntrPending__)(struct OBJGPU *); + NV_STATUS (*__gpuGetSriovCaps__)(struct OBJGPU *, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *); + NvBool (*__gpuCheckIsP2PAllocated__)(struct OBJGPU *); + NV_STATUS (*__gpuPrePowerOff__)(struct OBJGPU *); + NV_STATUS (*__gpuVerifyExistence__)(struct OBJGPU *); NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool); + NvBool (*__gpuIsAtsSupportedWithSmcMemPartitioning__)(struct OBJGPU *); + NvBool (*__gpuIsGlobalPoisonFuseEnabled__)(struct OBJGPU *); void (*__gpuDetermineSelfHostedMode__)(struct OBJGPU *); void (*__gpuDetermineMIGSupport__)(struct OBJGPU *); - NvBool (*__gpuIsAtsSupportedWithSmcMemPartitioning__)(struct OBJGPU *); + NV_STATUS (*__gpuInitOptimusSettings__)(struct OBJGPU *); + NV_STATUS (*__gpuDeinitOptimusSettings__)(struct OBJGPU *); NvBool (*__gpuIsSliCapableWithoutDisplay__)(struct OBJGPU *); NvBool (*__gpuIsCCEnabledInHw__)(struct OBJGPU *); NvBool (*__gpuIsDevModeEnabledInHw__)(struct OBJGPU *); NvBool (*__gpuIsCtxBufAllocInPmaSupported__)(struct OBJGPU *); + NV_STATUS (*__gpuUpdateErrorContainmentState__)(struct OBJGPU *, NV_ERROR_CONT_ERR_ID, NV_ERROR_CONT_LOCATION, NvU32 *); + void (*__gpuCheckEccCounts__)(struct OBJGPU *); + NV_STATUS (*__gpuClearEccCounts__)(struct OBJGPU *); + NV_STATUS (*__gpuWaitForGfwBootComplete__)(struct OBJGPU *); + NvBool (*__gpuGetIsCmpSku__)(struct OBJGPU *); NvBool PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED; NvBool bVideoLinkDisabled; GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; @@ -971,6 +1019,8 @@ struct OBJGPU { NvBool PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED; NvBool PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED; NvBool PDB_PROP_GPU_IS_COT_ENABLED; + NvBool bIsFlexibleFlaSupported; + NvBool PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED; NvBool PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE; NvBool PDB_PROP_GPU_SWRL_GRANULAR_LOCKING; NvBool PDB_PROP_GPU_IN_SLI_LINK_CODEPATH; @@ -1012,6 +1062,7 @@ struct OBJGPU { NvBool PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS; NvBool PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU; NvBool PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA; + NvBool PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE; NvBool PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED; NvBool PDB_PROP_GPU_NV_USERMODE_ENABLED; NvBool PDB_PROP_GPU_IN_FATAL_ERROR; @@ -1026,12 +1077,14 @@ struct OBJGPU { NvBool PDB_PROP_GPU_SKIP_TABLE_CE_MAP; NvBool PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF; NvBool PDB_PROP_GPU_IS_SOC_SDM; + NvBool PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS; NvBool PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL; + NvBool PDB_PROP_GPU_FASTPATH_SEQ_ENABLED; OS_GPU_INFO *pOsGpuInfo; OS_RM_CAPS *pOsRmCaps; NvU32 halImpl; void *hPci; - GpuEngineEventNotificationList *engineNonstallIntrEventNotifications[63]; + GpuEngineEventNotificationList *engineNonstallIntrEventNotifications[64]; NvBool bIsSOC; NvU32 gpuInstance; NvU32 gpuDisabled; @@ -1040,6 +1093,7 @@ struct OBJGPU { NvU32 deviceInstance; NvU32 subdeviceInstance; NvS32 numaNodeId; + NvS32 cpuNumaNodeId; _GPU_UUID gpuUuid; NvU32 gpuPhysicalId; NvU32 gpuTerminatedLinkMask; @@ -1059,7 +1113,6 @@ struct OBJGPU { NvU32 pmcEnable; NvU32 pmcRmOwnsIntrMask; NvBool testIntr; - NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS *gspSupportedEngines; NvU32 numCEs; NvU32 ceFaultMethodBufferSize; NvBool isVirtual; @@ -1083,7 +1136,6 @@ struct OBJGPU { NvBool bIsDebugModeEnabled; NvU32 masterFromSLIConfig; NvU32 sliStatus; - PENG_INFO_LINK_NODE infoList; struct OBJOS *pOS; struct OBJHAL *pHal; struct KernelBif *pKernelBif; @@ -1111,6 +1163,7 @@ struct OBJGPU { struct NvDebugDump *pNvd; struct KernelNvlink *pKernelNvlink; struct OBJGPUMON *pGpuMon; + struct KernelHwpm *pKernelHwpm; struct OBJSWENG *pSwEng; struct KernelFsp *pKernelFsp; struct ConfidentialCompute *pConfCompute; @@ -1125,6 +1178,7 @@ struct OBJGPU { RmCtrlDeferredCmd pRmCtrlDeferredCmd[2]; ACPI_DATA acpi; ACPI_METHOD_DATA acpiMethodData; + NvBool bSystemHasMux; NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS backLightMethodData; NvU32 activeFifoEventMthdNotifiers; struct Falcon *constructedFalcons[70]; @@ -1174,6 +1228,7 @@ struct OBJGPU { NvBool bIsRtlsim; NvBool bIsPassthru; NvBool bIsVirtualWithSriov; + NvBool bIsMigRm; NvU32 P2PPeerGpuCount; GPU_P2P_PEER_GPU_CAPS P2PPeerGpuCaps[32]; NvBool bIsSelfHosted; @@ -1196,13 +1251,12 @@ struct OBJGPU { NvBool bInstLoc47bitPaWar; NvU32 instVprOverrides; NvU32 optimizeUseCaseOverride; - NvS16 fecsCtxswLogConsumerCount; NvS16 videoCtxswLogConsumerCount; - EventBufferMap vgpuFecsTraceStagingBindings; - FecsEventBufferBindMultiMap fecsEventBufferBindingsUid; - TMR_EVENT *pFecsTimerEvent; VideoEventBufferBindMultiMap videoEventBufferBindingsUid; TMR_EVENT *pVideoTimerEvent; + NVENC_SESSION_LIST nvencSessionList; + NvU32 encSessionStatsReportingState; + NVFBC_SESSION_LIST nvfbcSessionList; struct OBJVASPACE *pFabricVAS; NvBool bPipelinedPteMemEnabled; NvBool bIsBarPteInSysmemSupported; @@ -1217,15 +1271,15 @@ struct OBJGPU { NvBool bGeforceSmb; NvBool bIsGeforce; NvBool bIsQuadro; + NvBool bIsQuadroAD; NvBool bIsVgx; NvBool bIsNvidiaNvs; NvBool bIsTitan; NvBool bIsTesla; - NvBool bIsAC; - BRANDING_TYPE brandingCache; NvBool bComputePolicyTimesliceSupported; NvBool bGlobalPoisonFuseEnabled; RmPhysAddr simAccessBufPhysAddr; + RmPhysAddr notifyOpSharedSurfacePhysAddr; NvU32 fabricProbeRegKeyOverride; NvU8 fabricProbeRetryDelay; NvU8 fabricProbeSlowdownThreshold; @@ -1235,6 +1289,9 @@ struct OBJGPU { NvBool bGpuNvEncAv1Supported; _GPU_SLI_PEER peer[2]; NvBool bIsGspOwnedFaultBuffersEnabled; + NvBool bVfResizableBAR1Supported; + NvBool bVoltaHubIntrSupported; + NvBool bAmpereErrorContainmentXidEnabled; _GPU_GC6_STATE gc6State; }; @@ -1259,62 +1316,38 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; ((OBJGPU*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJGPU))) #endif //__nvoc_gpu_h_disabled -#define PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL_BASE_CAST -#define PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL_BASE_NAME PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL #define PDB_PROP_GPU_RTD3_GC6_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_RTD3_GC6_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GC6_SUPPORTED #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_CAST #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU_BASE_NAME PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU -#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_CAST -#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_NAME PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K -#define PDB_PROP_GPU_INACCESSIBLE_BASE_CAST -#define PDB_PROP_GPU_INACCESSIBLE_BASE_NAME PDB_PROP_GPU_INACCESSIBLE -#define PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH_BASE_CAST -#define PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH_BASE_NAME PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH +#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST +#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP #define PDB_PROP_GPU_IN_FATAL_ERROR_BASE_CAST #define PDB_PROP_GPU_IN_FATAL_ERROR_BASE_NAME PDB_PROP_GPU_IN_FATAL_ERROR #define PDB_PROP_GPU_VGA_ENABLED_BASE_CAST #define PDB_PROP_GPU_VGA_ENABLED_BASE_NAME PDB_PROP_GPU_VGA_ENABLED -#define PDB_PROP_GPU_IN_PM_RESUME_CODEPATH_BASE_CAST -#define PDB_PROP_GPU_IN_PM_RESUME_CODEPATH_BASE_NAME PDB_PROP_GPU_IN_PM_RESUME_CODEPATH +#define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_CAST +#define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_NAME PDB_PROP_GPU_COHERENT_CPU_MAPPING #define PDB_PROP_GPU_IN_STANDBY_BASE_CAST #define PDB_PROP_GPU_IN_STANDBY_BASE_NAME PDB_PROP_GPU_IN_STANDBY #define PDB_PROP_GPU_IS_COT_ENABLED_BASE_CAST #define PDB_PROP_GPU_IS_COT_ENABLED_BASE_NAME PDB_PROP_GPU_IS_COT_ENABLED -#define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_CAST -#define PDB_PROP_GPU_COHERENT_CPU_MAPPING_BASE_NAME PDB_PROP_GPU_COHERENT_CPU_MAPPING #define PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED_BASE_CAST #define PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED_BASE_NAME PDB_PROP_GPU_HIGH_SPEED_BRIDGE_CONNECTED -#define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_CAST -#define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY -#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_CAST -#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED #define PDB_PROP_GPU_SLI_LINK_ACTIVE_BASE_CAST #define PDB_PROP_GPU_SLI_LINK_ACTIVE_BASE_NAME PDB_PROP_GPU_SLI_LINK_ACTIVE -#define PDB_PROP_GPU_IN_TCC_MODE_BASE_CAST -#define PDB_PROP_GPU_IN_TCC_MODE_BASE_NAME PDB_PROP_GPU_IN_TCC_MODE -#define PDB_PROP_GPU_C2C_SYSMEM_BASE_CAST -#define PDB_PROP_GPU_C2C_SYSMEM_BASE_NAME PDB_PROP_GPU_C2C_SYSMEM +#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_CAST +#define PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L0S_UNSUPPORTED #define PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING_BASE_CAST #define PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING_BASE_NAME PDB_PROP_GPU_SECONDARY_BUS_RESET_PENDING #define PDB_PROP_GPU_IN_GC6_RESET_BASE_CAST #define PDB_PROP_GPU_IN_GC6_RESET_BASE_NAME PDB_PROP_GPU_IN_GC6_RESET -#define PDB_PROP_GPU_HYBRID_MGPU_BASE_CAST -#define PDB_PROP_GPU_HYBRID_MGPU_BASE_NAME PDB_PROP_GPU_HYBRID_MGPU #define PDB_PROP_GPU_3D_CONTROLLER_BASE_CAST #define PDB_PROP_GPU_3D_CONTROLLER_BASE_NAME PDB_PROP_GPU_3D_CONTROLLER -#define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_CAST -#define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED -#define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_CAST -#define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE -#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_CAST -#define PDB_PROP_GPU_SKIP_TABLE_CE_MAP_BASE_NAME PDB_PROP_GPU_SKIP_TABLE_CE_MAP -#define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_CAST -#define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_NAME PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED -#define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_CAST -#define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_NAME PDB_PROP_GPU_RM_UNLINKED_SLI #define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_CAST #define PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL_BASE_NAME PDB_PROP_GPU_FORCE_PERF_BIOS_LEVEL +#define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_CAST +#define PDB_PROP_GPU_RM_UNLINKED_SLI_BASE_NAME PDB_PROP_GPU_RM_UNLINKED_SLI #define PDB_PROP_GPU_IS_UEFI_BASE_CAST #define PDB_PROP_GPU_IS_UEFI_BASE_NAME PDB_PROP_GPU_IS_UEFI #define PDB_PROP_GPU_IN_SECONDARY_BUS_RESET_BASE_CAST @@ -1323,26 +1356,96 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_OPTIMIZE_SPARSE_TEXTURE_BY_DEFAULT_BASE_NAME PDB_PROP_GPU_OPTIMIZE_SPARSE_TEXTURE_BY_DEFAULT #define PDB_PROP_GPU_IS_CONNECTED_BASE_CAST #define PDB_PROP_GPU_IS_CONNECTED_BASE_NAME PDB_PROP_GPU_IS_CONNECTED +#define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_CAST +#define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_RTD3_GC6_ACTIVE +#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_CAST +#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_CC_FEATURE_CAPABLE +#define PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT_BASE_CAST +#define PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT_BASE_NAME PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT +#define PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED_BASE_NAME PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED +#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_CAST +#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERING +#define PDB_PROP_GPU_BAR1_BAR2_DISABLED_BASE_CAST +#define PDB_PROP_GPU_BAR1_BAR2_DISABLED_BASE_NAME PDB_PROP_GPU_BAR1_BAR2_DISABLED +#define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_CAST +#define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_NAME PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE +#define PDB_PROP_GPU_ACCOUNTING_ON_BASE_CAST +#define PDB_PROP_GPU_ACCOUNTING_ON_BASE_NAME PDB_PROP_GPU_ACCOUNTING_ON +#define PDB_PROP_GPU_FAST_GC6_ACTIVE_BASE_CAST +#define PDB_PROP_GPU_FAST_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_FAST_GC6_ACTIVE +#define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_CAST +#define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERED +#define PDB_PROP_GPU_IN_FULLCHIP_RESET_BASE_CAST +#define PDB_PROP_GPU_IN_FULLCHIP_RESET_BASE_NAME PDB_PROP_GPU_IN_FULLCHIP_RESET +#define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_CAST +#define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_NAME PDB_PROP_GPU_NV_USERMODE_ENABLED +#define PDB_PROP_GPU_IN_SLI_LINK_CODEPATH_BASE_CAST +#define PDB_PROP_GPU_IN_SLI_LINK_CODEPATH_BASE_NAME PDB_PROP_GPU_IN_SLI_LINK_CODEPATH +#define PDB_PROP_GPU_IS_GEMINI_BASE_CAST +#define PDB_PROP_GPU_IS_GEMINI_BASE_NAME PDB_PROP_GPU_IS_GEMINI +#define PDB_PROP_GPU_STATE_INITIALIZED_BASE_CAST +#define PDB_PROP_GPU_STATE_INITIALIZED_BASE_NAME PDB_PROP_GPU_STATE_INITIALIZED +#define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_CAST +#define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_NAME PDB_PROP_GPU_GSYNC_III_ATTACHED +#define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_CAST +#define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_NAME PDB_PROP_GPU_QSYNC_II_ATTACHED +#define PDB_PROP_GPU_IS_SOC_SDM_BASE_CAST +#define PDB_PROP_GPU_IS_SOC_SDM_BASE_NAME PDB_PROP_GPU_IS_SOC_SDM +#define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_CAST +#define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_NAME PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM +#define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED +#define PDB_PROP_GPU_EMULATION_BASE_CAST +#define PDB_PROP_GPU_EMULATION_BASE_NAME PDB_PROP_GPU_EMULATION +#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_CAST +#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_APM_FEATURE_CAPABLE +#define PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST_BASE_CAST +#define PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST_BASE_NAME PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST +#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED +#define PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL_BASE_CAST +#define PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL_BASE_NAME PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL +#define PDB_PROP_GPU_INACCESSIBLE_BASE_CAST +#define PDB_PROP_GPU_INACCESSIBLE_BASE_NAME PDB_PROP_GPU_INACCESSIBLE +#define PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH_BASE_CAST +#define PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH_BASE_NAME PDB_PROP_GPU_DO_NOT_CHECK_REG_ACCESS_IN_PM_CODEPATH +#define PDB_PROP_GPU_IN_PM_RESUME_CODEPATH_BASE_CAST +#define PDB_PROP_GPU_IN_PM_RESUME_CODEPATH_BASE_NAME PDB_PROP_GPU_IN_PM_RESUME_CODEPATH +#define PDB_PROP_GPU_FASTPATH_SEQ_ENABLED_BASE_CAST +#define PDB_PROP_GPU_FASTPATH_SEQ_ENABLED_BASE_NAME PDB_PROP_GPU_FASTPATH_SEQ_ENABLED +#define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_CAST +#define PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY +#define PDB_PROP_GPU_IN_TCC_MODE_BASE_CAST +#define PDB_PROP_GPU_IN_TCC_MODE_BASE_NAME PDB_PROP_GPU_IN_TCC_MODE +#define PDB_PROP_GPU_C2C_SYSMEM_BASE_CAST +#define PDB_PROP_GPU_C2C_SYSMEM_BASE_NAME PDB_PROP_GPU_C2C_SYSMEM +#define PDB_PROP_GPU_HYBRID_MGPU_BASE_CAST +#define PDB_PROP_GPU_HYBRID_MGPU_BASE_NAME PDB_PROP_GPU_HYBRID_MGPU +#define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED +#define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_CAST +#define PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_MSHYBRID_GC6_ACTIVE +#define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED_BASE_NAME PDB_PROP_GPU_VC_CAPABILITY_SUPPORTED #define PDB_PROP_GPU_IS_PLX_PRESENT_BASE_CAST #define PDB_PROP_GPU_IS_PLX_PRESENT_BASE_NAME PDB_PROP_GPU_IS_PLX_PRESENT #define PDB_PROP_GPU_NVLINK_SYSMEM_BASE_CAST #define PDB_PROP_GPU_NVLINK_SYSMEM_BASE_NAME PDB_PROP_GPU_NVLINK_SYSMEM +#define PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED_BASE_CAST +#define PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED_BASE_NAME PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED #define PDB_PROP_GPU_IS_MOBILE_BASE_CAST #define PDB_PROP_GPU_IS_MOBILE_BASE_NAME PDB_PROP_GPU_IS_MOBILE -#define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_CAST -#define PDB_PROP_GPU_RTD3_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_RTD3_GC6_ACTIVE -#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_CAST -#define PDB_PROP_GPU_CC_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_CC_FEATURE_CAPABLE #define PDB_PROP_GPU_ALTERNATE_TREE_ENABLED_BASE_CAST #define PDB_PROP_GPU_ALTERNATE_TREE_ENABLED_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_ENABLED #define PDB_PROP_GPU_PERSISTENT_SW_STATE_BASE_CAST #define PDB_PROP_GPU_PERSISTENT_SW_STATE_BASE_NAME PDB_PROP_GPU_PERSISTENT_SW_STATE #define PDB_PROP_GPU_IN_PM_CODEPATH_BASE_CAST #define PDB_PROP_GPU_IN_PM_CODEPATH_BASE_NAME PDB_PROP_GPU_IN_PM_CODEPATH -#define PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT_BASE_CAST -#define PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT_BASE_NAME PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT #define PDB_PROP_GPU_UPSTREAM_PORT_L1_UNSUPPORTED_BASE_CAST #define PDB_PROP_GPU_UPSTREAM_PORT_L1_UNSUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L1_UNSUPPORTED +#define PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE_BASE_CAST +#define PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE_BASE_NAME PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE #define PDB_PROP_GPU_BEHIND_BR03_BASE_CAST #define PDB_PROP_GPU_BEHIND_BR03_BASE_NAME PDB_PROP_GPU_BEHIND_BR03 #define PDB_PROP_GPU_BEHIND_BR04_BASE_CAST @@ -1351,68 +1454,38 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_MIG_SUPPORTED_BASE_NAME PDB_PROP_GPU_MIG_SUPPORTED #define PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE_BASE_CAST #define PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE_BASE_NAME PDB_PROP_GPU_IN_BUGCHECK_CALLBACK_ROUTINE -#define PDB_PROP_GPU_BAR1_BAR2_DISABLED_BASE_CAST -#define PDB_PROP_GPU_BAR1_BAR2_DISABLED_BASE_NAME PDB_PROP_GPU_BAR1_BAR2_DISABLED -#define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_CAST -#define PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE_BASE_NAME PDB_PROP_GPU_CAN_OPTIMIZE_COMPUTE_USE_CASE #define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_CAST #define PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE_BASE_NAME PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE -#define PDB_PROP_GPU_ACCOUNTING_ON_BASE_CAST -#define PDB_PROP_GPU_ACCOUNTING_ON_BASE_NAME PDB_PROP_GPU_ACCOUNTING_ON #define PDB_PROP_GPU_IN_HIBERNATE_BASE_CAST #define PDB_PROP_GPU_IN_HIBERNATE_BASE_NAME PDB_PROP_GPU_IN_HIBERNATE #define PDB_PROP_GPU_BROKEN_FB_BASE_CAST #define PDB_PROP_GPU_BROKEN_FB_BASE_NAME PDB_PROP_GPU_BROKEN_FB -#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_CAST -#define PDB_PROP_GPU_GCOFF_STATE_ENTERING_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERING +#define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_CAST +#define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_NAME PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT #define PDB_PROP_GPU_IN_TIMEOUT_RECOVERY_BASE_CAST #define PDB_PROP_GPU_IN_TIMEOUT_RECOVERY_BASE_NAME PDB_PROP_GPU_IN_TIMEOUT_RECOVERY -#define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_CAST -#define PDB_PROP_GPU_GCOFF_STATE_ENTERED_BASE_NAME PDB_PROP_GPU_GCOFF_STATE_ENTERED -#define PDB_PROP_GPU_FAST_GC6_ACTIVE_BASE_CAST -#define PDB_PROP_GPU_FAST_GC6_ACTIVE_BASE_NAME PDB_PROP_GPU_FAST_GC6_ACTIVE -#define PDB_PROP_GPU_IN_FULLCHIP_RESET_BASE_CAST -#define PDB_PROP_GPU_IN_FULLCHIP_RESET_BASE_NAME PDB_PROP_GPU_IN_FULLCHIP_RESET #define PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA_BASE_CAST #define PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA_BASE_NAME PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA_BASE_CAST #define PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA_BASE_NAME PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA -#define PDB_PROP_GPU_IN_SLI_LINK_CODEPATH_BASE_CAST -#define PDB_PROP_GPU_IN_SLI_LINK_CODEPATH_BASE_NAME PDB_PROP_GPU_IN_SLI_LINK_CODEPATH #define PDB_PROP_GPU_IS_BR03_PRESENT_BASE_CAST #define PDB_PROP_GPU_IS_BR03_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR03_PRESENT -#define PDB_PROP_GPU_IS_GEMINI_BASE_CAST -#define PDB_PROP_GPU_IS_GEMINI_BASE_NAME PDB_PROP_GPU_IS_GEMINI -#define PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED_BASE_CAST -#define PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED_BASE_NAME PDB_PROP_GPU_UNIX_DYNAMIC_POWER_SUPPORTED -#define PDB_PROP_GPU_STATE_INITIALIZED_BASE_CAST -#define PDB_PROP_GPU_STATE_INITIALIZED_BASE_NAME PDB_PROP_GPU_STATE_INITIALIZED -#define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_CAST -#define PDB_PROP_GPU_NV_USERMODE_ENABLED_BASE_NAME PDB_PROP_GPU_NV_USERMODE_ENABLED -#define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_CAST -#define PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT_BASE_NAME PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT -#define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_CAST -#define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS -#define PDB_PROP_GPU_IS_MXM_3X_BASE_CAST -#define PDB_PROP_GPU_IS_MXM_3X_BASE_NAME PDB_PROP_GPU_IS_MXM_3X -#define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_CAST -#define PDB_PROP_GPU_GSYNC_III_ATTACHED_BASE_NAME PDB_PROP_GPU_GSYNC_III_ATTACHED -#define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_CAST -#define PDB_PROP_GPU_QSYNC_II_ATTACHED_BASE_NAME PDB_PROP_GPU_QSYNC_II_ATTACHED #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_CAST #define PDB_PROP_GPU_IS_BR04_PRESENT_BASE_NAME PDB_PROP_GPU_IS_BR04_PRESENT -#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_CAST -#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_NAME PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_CAST #define PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE_BASE_NAME PDB_PROP_GPU_OPTIMUS_GOLD_CFG_SPACE_RESTORE -#define PDB_PROP_GPU_IS_SOC_SDM_BASE_CAST -#define PDB_PROP_GPU_IS_SOC_SDM_BASE_NAME PDB_PROP_GPU_IS_SOC_SDM -#define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_CAST -#define PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM_BASE_NAME PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM +#define PDB_PROP_GPU_IS_MXM_3X_BASE_CAST +#define PDB_PROP_GPU_IS_MXM_3X_BASE_NAME PDB_PROP_GPU_IS_MXM_3X +#define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_CAST +#define PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS_BASE_NAME PDB_PROP_GPU_ALTERNATE_TREE_HANDLE_LOCKLESS +#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_CAST +#define PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF_BASE_NAME PDB_PROP_GPU_CHIP_SUPPORTS_RTD3_DEF +#define PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS_BASE_CAST +#define PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS_BASE_NAME PDB_PROP_GPU_DISP_PB_REQUIRES_SMMU_BYPASS #define PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED_BASE_CAST #define PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED_BASE_NAME PDB_PROP_GPU_NVLINK_P2P_LOOPBACK_DISABLED -#define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED_BASE_CAST -#define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_SUPPORTED +#define PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED_BASE_CAST +#define PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED #define PDB_PROP_GPU_ZERO_FB_BASE_CAST #define PDB_PROP_GPU_ZERO_FB_BASE_NAME PDB_PROP_GPU_ZERO_FB #define PDB_PROP_GPU_SWRL_GRANULAR_LOCKING_BASE_CAST @@ -1421,14 +1494,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK_BASE_NAME PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK #define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_CAST #define PDB_PROP_GPU_TEGRA_SOC_IGPU_BASE_NAME PDB_PROP_GPU_TEGRA_SOC_IGPU -#define PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED_BASE_CAST -#define PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_RTD3_GCOFF_SUPPORTED #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_CAST #define PDB_PROP_GPU_ATS_SUPPORTED_BASE_NAME PDB_PROP_GPU_ATS_SUPPORTED -#define PDB_PROP_GPU_EMULATION_BASE_CAST -#define PDB_PROP_GPU_EMULATION_BASE_NAME PDB_PROP_GPU_EMULATION -#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_CAST -#define PDB_PROP_GPU_APM_FEATURE_CAPABLE_BASE_NAME PDB_PROP_GPU_APM_FEATURE_CAPABLE #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_CAST #define PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS_BASE_NAME PDB_PROP_GPU_IGNORE_REPLAYABLE_FAULTS #define PDB_PROP_GPU_PRIMARY_DEVICE_BASE_CAST @@ -1439,12 +1506,10 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJGPU; #define PDB_PROP_GPU_BEHIND_BRIDGE_BASE_NAME PDB_PROP_GPU_BEHIND_BRIDGE #define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY_BASE_CAST #define PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY_BASE_NAME PDB_PROP_GPU_UPSTREAM_PORT_L1_POR_MOBILE_ONLY -#define PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST_BASE_CAST -#define PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST_BASE_NAME PDB_PROP_GPU_ENABLE_REG_ACCESS_IN_LOW_POWER_FOR_SIM_SRTEST +#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_CAST +#define PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K_BASE_NAME PDB_PROP_GPU_VGPU_BIG_PAGE_SIZE_64K #define PDB_PROP_GPU_IS_LOST_BASE_CAST #define PDB_PROP_GPU_IS_LOST_BASE_NAME PDB_PROP_GPU_IS_LOST -#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_CAST -#define PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED_BASE_NAME PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED #define PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX_BASE_CAST #define PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX_BASE_NAME PDB_PROP_GPU_EXTENDED_GSP_RM_INITIALIZATION_TIMEOUT_FOR_VGX @@ -1454,12 +1519,30 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, NvU32 ChipHal_arch, NvU32 ChipHal_impl, NvU32 ChipHal_hidrev, RM_RUNTIME_VARIANT RmVariantHal_rmVariant, TEGRA_CHIP_TYPE TegraChipHal_tegraType, - NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance); -#define __objCreate_OBJGPU(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance) \ - __nvoc_objCreate_OBJGPU((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance) + NvU32 DispIpHal_ipver, NvU32 arg_gpuInstance, NvU32 arg_gpuId, NvUuid * arg_pUuid); +#define __objCreate_OBJGPU(ppNewObj, pParent, createFlags, ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance, arg_gpuId, arg_pUuid) \ + __nvoc_objCreate_OBJGPU((ppNewObj), staticCast((pParent), Dynamic), (createFlags), ChipHal_arch, ChipHal_impl, ChipHal_hidrev, RmVariantHal_rmVariant, TegraChipHal_tegraType, DispIpHal_ipver, arg_gpuInstance, arg_gpuId, arg_pUuid) #define gpuConstructDeviceInfoTable(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) #define gpuConstructDeviceInfoTable_HAL(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) +#define gpuGetNameString(pGpu, arg0, arg1) gpuGetNameString_DISPATCH(pGpu, arg0, arg1) +#define gpuGetNameString_HAL(pGpu, arg0, arg1) gpuGetNameString_DISPATCH(pGpu, arg0, arg1) +#define gpuGetShortNameString(pGpu, arg0) gpuGetShortNameString_DISPATCH(pGpu, arg0) +#define gpuGetShortNameString_HAL(pGpu, arg0) gpuGetShortNameString_DISPATCH(pGpu, arg0) +#define gpuInitBranding(pGpu) gpuInitBranding_DISPATCH(pGpu) +#define gpuInitBranding_HAL(pGpu) gpuInitBranding_DISPATCH(pGpu) +#define gpuInitProperties(pGpu) gpuInitProperties_DISPATCH(pGpu) +#define gpuInitProperties_HAL(pGpu) gpuInitProperties_DISPATCH(pGpu) +#define gpuBuildKernelVideoEngineList(pGpu) gpuBuildKernelVideoEngineList_DISPATCH(pGpu) +#define gpuBuildKernelVideoEngineList_HAL(pGpu) gpuBuildKernelVideoEngineList_DISPATCH(pGpu) +#define gpuInitVideoLogging(pGpu) gpuInitVideoLogging_DISPATCH(pGpu) +#define gpuInitVideoLogging_HAL(pGpu) gpuInitVideoLogging_DISPATCH(pGpu) +#define gpuFreeVideoLogging(pGpu) gpuFreeVideoLogging_DISPATCH(pGpu) +#define gpuFreeVideoLogging_HAL(pGpu) gpuFreeVideoLogging_DISPATCH(pGpu) +#define gpuDestroyKernelVideoEngineList(pGpu) gpuDestroyKernelVideoEngineList_DISPATCH(pGpu) +#define gpuDestroyKernelVideoEngineList_HAL(pGpu) gpuDestroyKernelVideoEngineList_DISPATCH(pGpu) +#define gpuPowerOff(pGpu) gpuPowerOff_DISPATCH(pGpu) +#define gpuPowerOff_HAL(pGpu) gpuPowerOff_DISPATCH(pGpu) #define gpuWriteBusConfigReg(pGpu, index, value) gpuWriteBusConfigReg_DISPATCH(pGpu, index, value) #define gpuWriteBusConfigReg_HAL(pGpu, index, value) gpuWriteBusConfigReg_DISPATCH(pGpu, index, value) #define gpuReadBusConfigReg(pGpu, index, data) gpuReadBusConfigReg_DISPATCH(pGpu, index, data) @@ -1476,30 +1559,70 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, #define gpuReadVgpuConfigReg_HAL(pGpu, index, data) gpuReadVgpuConfigReg_DISPATCH(pGpu, index, data) #define gpuGetIdInfo(pGpu) gpuGetIdInfo_DISPATCH(pGpu) #define gpuGetIdInfo_HAL(pGpu) gpuGetIdInfo_DISPATCH(pGpu) +#define gpuGenGidData(pGpu, pGidData, gidSize, gidFlags) gpuGenGidData_DISPATCH(pGpu, pGidData, gidSize, gidFlags) +#define gpuGenGidData_HAL(pGpu, pGidData, gidSize, gidFlags) gpuGenGidData_DISPATCH(pGpu, pGidData, gidSize, gidFlags) +#define gpuGetChipSubRev(pGpu) gpuGetChipSubRev_DISPATCH(pGpu) +#define gpuGetChipSubRev_HAL(pGpu) gpuGetChipSubRev_DISPATCH(pGpu) +#define gpuGetSkuInfo(pGpu, pParams) gpuGetSkuInfo_DISPATCH(pGpu, pParams) +#define gpuGetSkuInfo_HAL(pGpu, pParams) gpuGetSkuInfo_DISPATCH(pGpu, pParams) +#define gpuGetRegBaseOffset(pGpu, arg0, arg1) gpuGetRegBaseOffset_DISPATCH(pGpu, arg0, arg1) +#define gpuGetRegBaseOffset_HAL(pGpu, arg0, arg1) gpuGetRegBaseOffset_DISPATCH(pGpu, arg0, arg1) #define gpuHandleSanityCheckRegReadError(pGpu, addr, value) gpuHandleSanityCheckRegReadError_DISPATCH(pGpu, addr, value) #define gpuHandleSanityCheckRegReadError_HAL(pGpu, addr, value) gpuHandleSanityCheckRegReadError_DISPATCH(pGpu, addr, value) #define gpuHandleSecFault(pGpu) gpuHandleSecFault_DISPATCH(pGpu) #define gpuHandleSecFault_HAL(pGpu) gpuHandleSecFault_DISPATCH(pGpu) +#define gpuSanityCheckVirtRegAccess(pGpu, arg0) gpuSanityCheckVirtRegAccess_DISPATCH(pGpu, arg0) +#define gpuSanityCheckVirtRegAccess_HAL(pGpu, arg0) gpuSanityCheckVirtRegAccess_DISPATCH(pGpu, arg0) #define gpuGetChildrenPresent(pGpu, pNumEntries) gpuGetChildrenPresent_DISPATCH(pGpu, pNumEntries) #define gpuGetChildrenPresent_HAL(pGpu, pNumEntries) gpuGetChildrenPresent_DISPATCH(pGpu, pNumEntries) #define gpuGetClassDescriptorList(pGpu, arg0) gpuGetClassDescriptorList_DISPATCH(pGpu, arg0) #define gpuGetClassDescriptorList_HAL(pGpu, arg0) gpuGetClassDescriptorList_DISPATCH(pGpu, arg0) #define gpuGetPhysAddrWidth(pGpu, arg0) gpuGetPhysAddrWidth_DISPATCH(pGpu, arg0) #define gpuGetPhysAddrWidth_HAL(pGpu, arg0) gpuGetPhysAddrWidth_DISPATCH(pGpu, arg0) +#define gpuInitSriov(pGpu) gpuInitSriov_DISPATCH(pGpu) +#define gpuInitSriov_HAL(pGpu) gpuInitSriov_DISPATCH(pGpu) +#define gpuDeinitSriov(pGpu) gpuDeinitSriov_DISPATCH(pGpu) +#define gpuDeinitSriov_HAL(pGpu) gpuDeinitSriov_DISPATCH(pGpu) +#define gpuCreateDefaultClientShare(pGpu) gpuCreateDefaultClientShare_DISPATCH(pGpu) +#define gpuCreateDefaultClientShare_HAL(pGpu) gpuCreateDefaultClientShare_DISPATCH(pGpu) +#define gpuDestroyDefaultClientShare(pGpu) gpuDestroyDefaultClientShare_DISPATCH(pGpu) +#define gpuDestroyDefaultClientShare_HAL(pGpu) gpuDestroyDefaultClientShare_DISPATCH(pGpu) +#define gpuGetVmmuSegmentSize(pGpu) gpuGetVmmuSegmentSize_DISPATCH(pGpu) +#define gpuGetVmmuSegmentSize_HAL(pGpu) gpuGetVmmuSegmentSize_DISPATCH(pGpu) #define gpuFuseSupportsDisplay(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) #define gpuFuseSupportsDisplay_HAL(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) +#define gpuGetActiveFBIOs(pGpu) gpuGetActiveFBIOs_DISPATCH(pGpu) +#define gpuGetActiveFBIOs_HAL(pGpu) gpuGetActiveFBIOs_DISPATCH(pGpu) +#define gpuCheckPageRetirementSupport(pGpu) gpuCheckPageRetirementSupport_DISPATCH(pGpu) +#define gpuCheckPageRetirementSupport_HAL(pGpu) gpuCheckPageRetirementSupport_DISPATCH(pGpu) +#define gpuIsInternalSku(pGpu) gpuIsInternalSku_DISPATCH(pGpu) +#define gpuIsInternalSku_HAL(pGpu) gpuIsInternalSku_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) -#define gpuReadDeviceId(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) -#define gpuReadDeviceId_HAL(pGpu, arg0, arg1) gpuReadDeviceId_DISPATCH(pGpu, arg0, arg1) +#define gpuCheckIfFbhubPoisonIntrPending(pGpu) gpuCheckIfFbhubPoisonIntrPending_DISPATCH(pGpu) +#define gpuCheckIfFbhubPoisonIntrPending_HAL(pGpu) gpuCheckIfFbhubPoisonIntrPending_DISPATCH(pGpu) +#define gpuGetSriovCaps(pGpu, arg0) gpuGetSriovCaps_DISPATCH(pGpu, arg0) +#define gpuGetSriovCaps_HAL(pGpu, arg0) gpuGetSriovCaps_DISPATCH(pGpu, arg0) +#define gpuCheckIsP2PAllocated(pGpu) gpuCheckIsP2PAllocated_DISPATCH(pGpu) +#define gpuCheckIsP2PAllocated_HAL(pGpu) gpuCheckIsP2PAllocated_DISPATCH(pGpu) +#define gpuPrePowerOff(pGpu) gpuPrePowerOff_DISPATCH(pGpu) +#define gpuPrePowerOff_HAL(pGpu) gpuPrePowerOff_DISPATCH(pGpu) +#define gpuVerifyExistence(pGpu) gpuVerifyExistence_DISPATCH(pGpu) +#define gpuVerifyExistence_HAL(pGpu) gpuVerifyExistence_DISPATCH(pGpu) #define gpuGetFlaVasSize(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) #define gpuGetFlaVasSize_HAL(pGpu, bNvswitchVirtualization) gpuGetFlaVasSize_DISPATCH(pGpu, bNvswitchVirtualization) +#define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) +#define gpuIsAtsSupportedWithSmcMemPartitioning_HAL(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) +#define gpuIsGlobalPoisonFuseEnabled(pGpu) gpuIsGlobalPoisonFuseEnabled_DISPATCH(pGpu) +#define gpuIsGlobalPoisonFuseEnabled_HAL(pGpu) gpuIsGlobalPoisonFuseEnabled_DISPATCH(pGpu) #define gpuDetermineSelfHostedMode(pGpu) gpuDetermineSelfHostedMode_DISPATCH(pGpu) #define gpuDetermineSelfHostedMode_HAL(pGpu) gpuDetermineSelfHostedMode_DISPATCH(pGpu) #define gpuDetermineMIGSupport(pGpu) gpuDetermineMIGSupport_DISPATCH(pGpu) #define gpuDetermineMIGSupport_HAL(pGpu) gpuDetermineMIGSupport_DISPATCH(pGpu) -#define gpuIsAtsSupportedWithSmcMemPartitioning(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) -#define gpuIsAtsSupportedWithSmcMemPartitioning_HAL(pGpu) gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(pGpu) +#define gpuInitOptimusSettings(pGpu) gpuInitOptimusSettings_DISPATCH(pGpu) +#define gpuInitOptimusSettings_HAL(pGpu) gpuInitOptimusSettings_DISPATCH(pGpu) +#define gpuDeinitOptimusSettings(pGpu) gpuDeinitOptimusSettings_DISPATCH(pGpu) +#define gpuDeinitOptimusSettings_HAL(pGpu) gpuDeinitOptimusSettings_DISPATCH(pGpu) #define gpuIsSliCapableWithoutDisplay(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu) #define gpuIsSliCapableWithoutDisplay_HAL(pGpu) gpuIsSliCapableWithoutDisplay_DISPATCH(pGpu) #define gpuIsCCEnabledInHw(pGpu) gpuIsCCEnabledInHw_DISPATCH(pGpu) @@ -1508,6 +1631,16 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, #define gpuIsDevModeEnabledInHw_HAL(pGpu) gpuIsDevModeEnabledInHw_DISPATCH(pGpu) #define gpuIsCtxBufAllocInPmaSupported(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu) #define gpuIsCtxBufAllocInPmaSupported_HAL(pGpu) gpuIsCtxBufAllocInPmaSupported_DISPATCH(pGpu) +#define gpuUpdateErrorContainmentState(pGpu, arg0, arg1, arg2) gpuUpdateErrorContainmentState_DISPATCH(pGpu, arg0, arg1, arg2) +#define gpuUpdateErrorContainmentState_HAL(pGpu, arg0, arg1, arg2) gpuUpdateErrorContainmentState_DISPATCH(pGpu, arg0, arg1, arg2) +#define gpuCheckEccCounts(pGpu) gpuCheckEccCounts_DISPATCH(pGpu) +#define gpuCheckEccCounts_HAL(pGpu) gpuCheckEccCounts_DISPATCH(pGpu) +#define gpuClearEccCounts(pGpu) gpuClearEccCounts_DISPATCH(pGpu) +#define gpuClearEccCounts_HAL(pGpu) gpuClearEccCounts_DISPATCH(pGpu) +#define gpuWaitForGfwBootComplete(pGpu) gpuWaitForGfwBootComplete_DISPATCH(pGpu) +#define gpuWaitForGfwBootComplete_HAL(pGpu) gpuWaitForGfwBootComplete_DISPATCH(pGpu) +#define gpuGetIsCmpSku(pGpu) gpuGetIsCmpSku_DISPATCH(pGpu) +#define gpuGetIsCmpSku_HAL(pGpu) gpuGetIsCmpSku_DISPATCH(pGpu) static inline NV_STATUS gpuConstructPhysical_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } @@ -1581,294 +1714,108 @@ static inline NV_STATUS gpuStateDestroy(struct OBJGPU *pGpu) { #define gpuStateDestroy_HAL(pGpu) gpuStateDestroy(pGpu) -static inline NV_STATUS gpuApplyOverrides_46f6a7(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS gpuPowerManagementEnterPreUnloadPhysical_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; } +NV_STATUS gpuPowerManagementEnterPreUnloadPhysical_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuApplyOverrides(struct OBJGPU *pGpu, NvU32 arg0, NvU32 arg1) { +static inline NV_STATUS gpuPowerManagementEnterPreUnloadPhysical(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuApplyOverrides(pGpu, arg0, arg1) gpuApplyOverrides_46f6a7(pGpu, arg0, arg1) +#define gpuPowerManagementEnterPreUnloadPhysical(pGpu) gpuPowerManagementEnterPreUnloadPhysical_56cd7a(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuApplyOverrides_HAL(pGpu, arg0, arg1) gpuApplyOverrides(pGpu, arg0, arg1) +#define gpuPowerManagementEnterPreUnloadPhysical_HAL(pGpu) gpuPowerManagementEnterPreUnloadPhysical(pGpu) -static inline NV_STATUS gpuInitDevinitOverridesFromRegistry_56cd7a(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuPowerManagementEnterPostUnloadPhysical_56cd7a(struct OBJGPU *pGpu, NvU32 newLevel) { return NV_OK; } +NV_STATUS gpuPowerManagementEnterPostUnloadPhysical_IMPL(struct OBJGPU *pGpu, NvU32 newLevel); + #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuInitDevinitOverridesFromRegistry(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuPowerManagementEnterPostUnloadPhysical(struct OBJGPU *pGpu, NvU32 newLevel) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuInitDevinitOverridesFromRegistry(pGpu) gpuInitDevinitOverridesFromRegistry_56cd7a(pGpu) +#define gpuPowerManagementEnterPostUnloadPhysical(pGpu, newLevel) gpuPowerManagementEnterPostUnloadPhysical_56cd7a(pGpu, newLevel) #endif //__nvoc_gpu_h_disabled -#define gpuInitDevinitOverridesFromRegistry_HAL(pGpu) gpuInitDevinitOverridesFromRegistry(pGpu) +#define gpuPowerManagementEnterPostUnloadPhysical_HAL(pGpu, newLevel) gpuPowerManagementEnterPostUnloadPhysical(pGpu, newLevel) -static inline NV_STATUS gpuApplyDevinitReg032Override_46f6a7(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS gpuPowerManagementResumePreLoadPhysical_56cd7a(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) { + return NV_OK; } +NV_STATUS gpuPowerManagementResumePreLoadPhysical_IMPL(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags); + #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuApplyDevinitReg032Override(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { +static inline NV_STATUS gpuPowerManagementResumePreLoadPhysical(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuApplyDevinitReg032Override(pGpu, arg0, arg1) gpuApplyDevinitReg032Override_46f6a7(pGpu, arg0, arg1) +#define gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags) gpuPowerManagementResumePreLoadPhysical_56cd7a(pGpu, oldLevel, flags) #endif //__nvoc_gpu_h_disabled -#define gpuApplyDevinitReg032Override_HAL(pGpu, arg0, arg1) gpuApplyDevinitReg032Override(pGpu, arg0, arg1) +#define gpuPowerManagementResumePreLoadPhysical_HAL(pGpu, oldLevel, flags) gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags) -static inline NV_STATUS gpuCheckPCIIDMismatch_56cd7a(struct OBJGPU *pGpu, struct OBJVBIOS *arg0) { +static inline NV_STATUS gpuPowerManagementResumePostLoadPhysical_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } +NV_STATUS gpuPowerManagementResumePostLoadPhysical_IMPL(struct OBJGPU *pGpu); + #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuCheckPCIIDMismatch(struct OBJGPU *pGpu, struct OBJVBIOS *arg0) { +static inline NV_STATUS gpuPowerManagementResumePostLoadPhysical(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuCheckPCIIDMismatch(pGpu, arg0) gpuCheckPCIIDMismatch_56cd7a(pGpu, arg0) +#define gpuPowerManagementResumePostLoadPhysical(pGpu) gpuPowerManagementResumePostLoadPhysical_56cd7a(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuCheckPCIIDMismatch_HAL(pGpu, arg0) gpuCheckPCIIDMismatch(pGpu, arg0) +#define gpuPowerManagementResumePostLoadPhysical_HAL(pGpu) gpuPowerManagementResumePostLoadPhysical(pGpu) -static inline NvBool gpuCheckGpuIDMismatch_491d52(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { - return ((NvBool)(0 != 0)); +static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx_46f6a7(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) { + return NV_ERR_NOT_SUPPORTED; } #ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuCheckGpuIDMismatch(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { +static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_FALSE; + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuCheckGpuIDMismatch(pGpu, arg0, arg1) gpuCheckGpuIDMismatch_491d52(pGpu, arg0, arg1) +#define gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx_46f6a7(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) #endif //__nvoc_gpu_h_disabled -#define gpuCheckGpuIDMismatch_HAL(pGpu, arg0, arg1) gpuCheckGpuIDMismatch(pGpu, arg0, arg1) +#define gpuInitializeMemDescFromPromotedCtx_HAL(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) -static inline NV_STATUS gpuPowerManagementEnterPreUnloadPhysical_56cd7a(struct OBJGPU *pGpu) { - return NV_OK; +static inline void gpuSetThreadBcState_b3696a(struct OBJGPU *pGpu, NvBool arg0) { + return; } -NV_STATUS gpuPowerManagementEnterPreUnloadPhysical_IMPL(struct OBJGPU *pGpu); - #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuPowerManagementEnterPreUnloadPhysical(struct OBJGPU *pGpu) { +static inline void gpuSetThreadBcState(struct OBJGPU *pGpu, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuPowerManagementEnterPreUnloadPhysical(pGpu) gpuPowerManagementEnterPreUnloadPhysical_56cd7a(pGpu) +#define gpuSetThreadBcState(pGpu, arg0) gpuSetThreadBcState_b3696a(pGpu, arg0) #endif //__nvoc_gpu_h_disabled -#define gpuPowerManagementEnterPreUnloadPhysical_HAL(pGpu) gpuPowerManagementEnterPreUnloadPhysical(pGpu) - -static inline NV_STATUS gpuPowerManagementEnterPostUnloadPhysical_56cd7a(struct OBJGPU *pGpu, NvU32 newLevel) { - return NV_OK; -} - -NV_STATUS gpuPowerManagementEnterPostUnloadPhysical_IMPL(struct OBJGPU *pGpu, NvU32 newLevel); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuPowerManagementEnterPostUnloadPhysical(struct OBJGPU *pGpu, NvU32 newLevel) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuPowerManagementEnterPostUnloadPhysical(pGpu, newLevel) gpuPowerManagementEnterPostUnloadPhysical_56cd7a(pGpu, newLevel) -#endif //__nvoc_gpu_h_disabled - -#define gpuPowerManagementEnterPostUnloadPhysical_HAL(pGpu, newLevel) gpuPowerManagementEnterPostUnloadPhysical(pGpu, newLevel) - -static inline NV_STATUS gpuPowerManagementResumePreLoadPhysical_56cd7a(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) { - return NV_OK; -} - -NV_STATUS gpuPowerManagementResumePreLoadPhysical_IMPL(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuPowerManagementResumePreLoadPhysical(struct OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags) gpuPowerManagementResumePreLoadPhysical_56cd7a(pGpu, oldLevel, flags) -#endif //__nvoc_gpu_h_disabled - -#define gpuPowerManagementResumePreLoadPhysical_HAL(pGpu, oldLevel, flags) gpuPowerManagementResumePreLoadPhysical(pGpu, oldLevel, flags) - -static inline NV_STATUS gpuPowerManagementResumePostLoadPhysical_56cd7a(struct OBJGPU *pGpu) { - return NV_OK; -} - -NV_STATUS gpuPowerManagementResumePostLoadPhysical_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuPowerManagementResumePostLoadPhysical(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuPowerManagementResumePostLoadPhysical(pGpu) gpuPowerManagementResumePostLoadPhysical_56cd7a(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuPowerManagementResumePostLoadPhysical_HAL(pGpu) gpuPowerManagementResumePostLoadPhysical(pGpu) - -static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx_46f6a7(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) { - return NV_ERR_NOT_SUPPORTED; -} - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuInitializeMemDescFromPromotedCtx(struct OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, NvU64 gpuPhysAddr, NvU64 size, NvU32 physAttr, NvBool bIsCallingContextVgpuPlugin) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx_46f6a7(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) -#endif //__nvoc_gpu_h_disabled - -#define gpuInitializeMemDescFromPromotedCtx_HAL(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) gpuInitializeMemDescFromPromotedCtx(pGpu, ppMemDesc, gpuPhysAddr, size, physAttr, bIsCallingContextVgpuPlugin) - -NV_STATUS gpuGetNameString_KERNEL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); - -NV_STATUS gpuGetNameString_IMPL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuGetNameString(struct OBJGPU *pGpu, NvU32 arg0, void *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetNameString(pGpu, arg0, arg1) gpuGetNameString_KERNEL(pGpu, arg0, arg1) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetNameString_HAL(pGpu, arg0, arg1) gpuGetNameString(pGpu, arg0, arg1) - -NV_STATUS gpuGetShortNameString_KERNEL(struct OBJGPU *pGpu, NvU8 *arg0); - -NV_STATUS gpuGetShortNameString_IMPL(struct OBJGPU *pGpu, NvU8 *arg0); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuGetShortNameString(struct OBJGPU *pGpu, NvU8 *arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetShortNameString(pGpu, arg0) gpuGetShortNameString_KERNEL(pGpu, arg0) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetShortNameString_HAL(pGpu, arg0) gpuGetShortNameString(pGpu, arg0) - -void gpuInitBranding_FWCLIENT(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuInitBranding(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuInitBranding(pGpu) gpuInitBranding_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuInitBranding_HAL(pGpu) gpuInitBranding(pGpu) - -BRANDING_TYPE gpuDetectBranding_FWCLIENT(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline BRANDING_TYPE gpuDetectBranding(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - BRANDING_TYPE ret; - portMemSet(&ret, 0, sizeof(BRANDING_TYPE)); - return ret; -} -#else //__nvoc_gpu_h_disabled -#define gpuDetectBranding(pGpu) gpuDetectBranding_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuDetectBranding_HAL(pGpu) gpuDetectBranding(pGpu) - -COMPUTE_BRANDING_TYPE gpuDetectComputeBranding_FWCLIENT(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline COMPUTE_BRANDING_TYPE gpuDetectComputeBranding(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - COMPUTE_BRANDING_TYPE ret; - portMemSet(&ret, 0, sizeof(COMPUTE_BRANDING_TYPE)); - return ret; -} -#else //__nvoc_gpu_h_disabled -#define gpuDetectComputeBranding(pGpu) gpuDetectComputeBranding_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuDetectComputeBranding_HAL(pGpu) gpuDetectComputeBranding(pGpu) - -BRANDING_TYPE gpuDetectVgxBranding_FWCLIENT(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline BRANDING_TYPE gpuDetectVgxBranding(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - BRANDING_TYPE ret; - portMemSet(&ret, 0, sizeof(BRANDING_TYPE)); - return ret; -} -#else //__nvoc_gpu_h_disabled -#define gpuDetectVgxBranding(pGpu) gpuDetectVgxBranding_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuDetectVgxBranding_HAL(pGpu) gpuDetectVgxBranding(pGpu) - -void gpuInitProperties_FWCLIENT(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuInitProperties(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuInitProperties(pGpu) gpuInitProperties_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuInitProperties_HAL(pGpu) gpuInitProperties(pGpu) - -static inline void gpuSetThreadBcState_b3696a(struct OBJGPU *pGpu, NvBool arg0) { - return; -} - - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuSetThreadBcState(struct OBJGPU *pGpu, NvBool arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuSetThreadBcState(pGpu, arg0) gpuSetThreadBcState_b3696a(pGpu, arg0) -#endif //__nvoc_gpu_h_disabled - -#define gpuSetThreadBcState_HAL(pGpu, arg0) gpuSetThreadBcState(pGpu, arg0) +#define gpuSetThreadBcState_HAL(pGpu, arg0) gpuSetThreadBcState(pGpu, arg0) static inline void gpuDeterminePersistantIllumSettings_b3696a(struct OBJGPU *pGpu) { return; @@ -1928,60 +1875,6 @@ static inline void gpuDestroyGenericKernelFalconList(struct OBJGPU *pGpu) { #define gpuDestroyGenericKernelFalconList_HAL(pGpu) gpuDestroyGenericKernelFalconList(pGpu) -NV_STATUS gpuBuildKernelVideoEngineList_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuBuildKernelVideoEngineList(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuBuildKernelVideoEngineList(pGpu) gpuBuildKernelVideoEngineList_IMPL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuBuildKernelVideoEngineList_HAL(pGpu) gpuBuildKernelVideoEngineList(pGpu) - -NV_STATUS gpuInitVideoLogging_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuInitVideoLogging(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuInitVideoLogging(pGpu) gpuInitVideoLogging_IMPL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuInitVideoLogging_HAL(pGpu) gpuInitVideoLogging(pGpu) - -void gpuFreeVideoLogging_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuFreeVideoLogging(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuFreeVideoLogging(pGpu) gpuFreeVideoLogging_IMPL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuFreeVideoLogging_HAL(pGpu) gpuFreeVideoLogging(pGpu) - -void gpuDestroyKernelVideoEngineList_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuDestroyKernelVideoEngineList(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuDestroyKernelVideoEngineList(pGpu) gpuDestroyKernelVideoEngineList_IMPL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuDestroyKernelVideoEngineList_HAL(pGpu) gpuDestroyKernelVideoEngineList(pGpu) - struct GenericKernelFalcon *gpuGetGenericKernelFalconForEngine_IMPL(struct OBJGPU *pGpu, ENGDESCRIPTOR arg0); @@ -2160,22 +2053,6 @@ static inline NV_STATUS gpuIsDeviceMarkedForDrainAndReset(struct OBJGPU *pGpu, N #define gpuIsDeviceMarkedForDrainAndReset_HAL(pGpu, pbDrainRecommended) gpuIsDeviceMarkedForDrainAndReset(pGpu, pbDrainRecommended) -static inline NvU32 gpuGetSliFingerPinsetMask_4a4dee(struct OBJGPU *pGpu) { - return 0; -} - - -#ifdef __nvoc_gpu_h_disabled -static inline NvU32 gpuGetSliFingerPinsetMask(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return 0; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetSliFingerPinsetMask(pGpu) gpuGetSliFingerPinsetMask_4a4dee(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetSliFingerPinsetMask_HAL(pGpu) gpuGetSliFingerPinsetMask(pGpu) - static inline NV_STATUS gpuPrivSecInitRegistryOverrides_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } @@ -2192,35 +2069,6 @@ static inline NV_STATUS gpuPrivSecInitRegistryOverrides(struct OBJGPU *pGpu) { #define gpuPrivSecInitRegistryOverrides_HAL(pGpu) gpuPrivSecInitRegistryOverrides(pGpu) -static inline void gpuDestroyOverrides_b3696a(struct OBJGPU *pGpu) { - return; -} - - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuDestroyOverrides(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuDestroyOverrides(pGpu) gpuDestroyOverrides_b3696a(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuDestroyOverrides_HAL(pGpu) gpuDestroyOverrides(pGpu) - -NV_STATUS gpuPowerOff_KERNEL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuPowerOff(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuPowerOff(pGpu) gpuPowerOff_KERNEL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuPowerOff_HAL(pGpu) gpuPowerOff(pGpu) - NV_STATUS gpuSetPower_GM107(struct OBJGPU *pGpu, NvU32 arg1, NvU32 arg2, NvU32 arg3); @@ -2268,56 +2116,6 @@ static inline NvU32 gpuGetDeviceIDList(struct OBJGPU *pGpu, DEVICE_ID_MAPPING ** #define gpuGetDeviceIDList_HAL(pGpu, arg0) gpuGetDeviceIDList(pGpu, arg0) -NV_STATUS gpuGenGidData_FWCLIENT(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags); - -NV_STATUS gpuGenGidData_GK104(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuGenGidData(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuGenGidData(pGpu, pGidData, gidSize, gidFlags) gpuGenGidData_FWCLIENT(pGpu, pGidData, gidSize, gidFlags) -#endif //__nvoc_gpu_h_disabled - -#define gpuGenGidData_HAL(pGpu, pGidData, gidSize, gidFlags) gpuGenGidData(pGpu, pGidData, gidSize, gidFlags) - -NvU8 gpuGetChipSubRev_FWCLIENT(struct OBJGPU *pGpu); - -NvU8 gpuGetChipSubRev_GK104(struct OBJGPU *pGpu); - -NvU8 gpuGetChipSubRev_GA100(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NvU8 gpuGetChipSubRev(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return 0; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetChipSubRev(pGpu) gpuGetChipSubRev_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetChipSubRev_HAL(pGpu) gpuGetChipSubRev(pGpu) - -NvU32 gpuGetEmulationRev1_FWCLIENT(struct OBJGPU *pGpu); - -NvU32 gpuGetEmulationRev1_GM107(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NvU32 gpuGetEmulationRev1(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return 0; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetEmulationRev1(pGpu) gpuGetEmulationRev1_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetEmulationRev1_HAL(pGpu) gpuGetEmulationRev1(pGpu) - static inline NV_STATUS gpuPerformUniversalValidation_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } @@ -2350,29 +2148,7 @@ static inline NvU32 gpuGetVirtRegPhysOffset(struct OBJGPU *pGpu) { #define gpuGetVirtRegPhysOffset_HAL(pGpu) gpuGetVirtRegPhysOffset(pGpu) -NV_STATUS gpuGetRegBaseOffset_FWCLIENT(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1); - -NV_STATUS gpuGetRegBaseOffset_TU102(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuGetRegBaseOffset(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetRegBaseOffset(pGpu, arg0, arg1) gpuGetRegBaseOffset_FWCLIENT(pGpu, arg0, arg1) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetRegBaseOffset_HAL(pGpu, arg0, arg1) gpuGetRegBaseOffset(pGpu, arg0, arg1) - -static inline void gpuGetSanityCheckRegReadError_b3696a(struct OBJGPU *pGpu, NvU32 value, const char **pErrorString) { - return; -} - -void gpuGetSanityCheckRegReadError_GK104(struct OBJGPU *pGpu, NvU32 value, const char **pErrorString); - -void gpuGetSanityCheckRegReadError_GA100(struct OBJGPU *pGpu, NvU32 value, const char **pErrorString); +void gpuGetSanityCheckRegReadError_GM107(struct OBJGPU *pGpu, NvU32 value, const char **pErrorString); #ifdef __nvoc_gpu_h_disabled @@ -2380,31 +2156,11 @@ static inline void gpuGetSanityCheckRegReadError(struct OBJGPU *pGpu, NvU32 valu NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); } #else //__nvoc_gpu_h_disabled -#define gpuGetSanityCheckRegReadError(pGpu, value, pErrorString) gpuGetSanityCheckRegReadError_b3696a(pGpu, value, pErrorString) +#define gpuGetSanityCheckRegReadError(pGpu, value, pErrorString) gpuGetSanityCheckRegReadError_GM107(pGpu, value, pErrorString) #endif //__nvoc_gpu_h_disabled #define gpuGetSanityCheckRegReadError_HAL(pGpu, value, pErrorString) gpuGetSanityCheckRegReadError(pGpu, value, pErrorString) -static inline NV_STATUS gpuSanityCheckVirtRegAccess_56cd7a(struct OBJGPU *pGpu, NvU32 arg0) { - return NV_OK; -} - -NV_STATUS gpuSanityCheckVirtRegAccess_TU102(struct OBJGPU *pGpu, NvU32 arg0); - -NV_STATUS gpuSanityCheckVirtRegAccess_GH100(struct OBJGPU *pGpu, NvU32 arg0); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuSanityCheckVirtRegAccess(struct OBJGPU *pGpu, NvU32 arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuSanityCheckVirtRegAccess(pGpu, arg0) gpuSanityCheckVirtRegAccess_56cd7a(pGpu, arg0) -#endif //__nvoc_gpu_h_disabled - -#define gpuSanityCheckVirtRegAccess_HAL(pGpu, arg0) gpuSanityCheckVirtRegAccess(pGpu, arg0) - NV_STATUS gpuInitRegistryOverrides_KERNEL(struct OBJGPU *pGpu); @@ -2419,334 +2175,156 @@ static inline NV_STATUS gpuInitRegistryOverrides(struct OBJGPU *pGpu) { #define gpuInitRegistryOverrides_HAL(pGpu) gpuInitRegistryOverrides(pGpu) -NV_STATUS gpuInitInstLocOverrides_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuInitInstLocOverrides(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuInitInstLocOverrides(pGpu) gpuInitInstLocOverrides_IMPL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuInitInstLocOverrides_HAL(pGpu) gpuInitInstLocOverrides(pGpu) - -const GPUCHILDORDER *gpuGetChildrenOrder_GM200(struct OBJGPU *pGpu, NvU32 *pNumEntries); - - -#ifdef __nvoc_gpu_h_disabled -static inline const GPUCHILDORDER *gpuGetChildrenOrder(struct OBJGPU *pGpu, NvU32 *pNumEntries) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NULL; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetChildrenOrder(pGpu, pNumEntries) gpuGetChildrenOrder_GM200(pGpu, pNumEntries) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetChildrenOrder_HAL(pGpu, pNumEntries) gpuGetChildrenOrder(pGpu, pNumEntries) - -NV_STATUS gpuInitSriov_FWCLIENT(struct OBJGPU *pGpu); - -NV_STATUS gpuInitSriov_TU102(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuInitSriov(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuInitSriov(pGpu) gpuInitSriov_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuInitSriov_HAL(pGpu) gpuInitSriov(pGpu) - -NV_STATUS gpuDeinitSriov_FWCLIENT(struct OBJGPU *pGpu); - -NV_STATUS gpuDeinitSriov_TU102(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuDeinitSriov(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuDeinitSriov(pGpu) gpuDeinitSriov_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuDeinitSriov_HAL(pGpu) gpuDeinitSriov(pGpu) - -static inline NV_STATUS gpuCreateDefaultClientShare_56cd7a(struct OBJGPU *pGpu) { - return NV_OK; -} - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuCreateDefaultClientShare(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuCreateDefaultClientShare(pGpu) gpuCreateDefaultClientShare_56cd7a(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuCreateDefaultClientShare_HAL(pGpu) gpuCreateDefaultClientShare(pGpu) - -static inline void gpuDestroyDefaultClientShare_b3696a(struct OBJGPU *pGpu) { - return; -} - - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuDestroyDefaultClientShare(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuDestroyDefaultClientShare(pGpu) gpuDestroyDefaultClientShare_b3696a(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuDestroyDefaultClientShare_HAL(pGpu) gpuDestroyDefaultClientShare(pGpu) - -static inline NvU64 gpuGetVmmuSegmentSize_72c522(struct OBJGPU *pGpu) { - return pGpu->vmmuSegmentSize; -} - - -#ifdef __nvoc_gpu_h_disabled -static inline NvU64 gpuGetVmmuSegmentSize(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return 0; -} -#else //__nvoc_gpu_h_disabled -#define gpuGetVmmuSegmentSize(pGpu) gpuGetVmmuSegmentSize_72c522(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetVmmuSegmentSize_HAL(pGpu) gpuGetVmmuSegmentSize(pGpu) - -void gpuGetTerminatedLinkMask_GA100(struct OBJGPU *pGpu, NvU32 arg0); - - -#ifdef __nvoc_gpu_h_disabled -static inline void gpuGetTerminatedLinkMask(struct OBJGPU *pGpu, NvU32 arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); -} -#else //__nvoc_gpu_h_disabled -#define gpuGetTerminatedLinkMask(pGpu, arg0) gpuGetTerminatedLinkMask_GA100(pGpu, arg0) -#endif //__nvoc_gpu_h_disabled - -#define gpuGetTerminatedLinkMask_HAL(pGpu, arg0) gpuGetTerminatedLinkMask(pGpu, arg0) - -NV_STATUS gpuJtVersionSanityCheck_TU102(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuJtVersionSanityCheck(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuJtVersionSanityCheck(pGpu) gpuJtVersionSanityCheck_TU102(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuJtVersionSanityCheck_HAL(pGpu) gpuJtVersionSanityCheck(pGpu) - -static inline NvBool gpuCompletedGC6PowerOff_cbe027(struct OBJGPU *pGpu) { - return ((NvBool)(0 == 0)); -} - -NvBool gpuCompletedGC6PowerOff_GV100(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuCompletedGC6PowerOff(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_FALSE; -} -#else //__nvoc_gpu_h_disabled -#define gpuCompletedGC6PowerOff(pGpu) gpuCompletedGC6PowerOff_cbe027(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuCompletedGC6PowerOff_HAL(pGpu) gpuCompletedGC6PowerOff(pGpu) - -static inline NvBool gpuIsACPIPatchRequiredForBug2473619_491d52(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - - -#ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuIsACPIPatchRequiredForBug2473619(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_FALSE; -} -#else //__nvoc_gpu_h_disabled -#define gpuIsACPIPatchRequiredForBug2473619(pGpu) gpuIsACPIPatchRequiredForBug2473619_491d52(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuIsACPIPatchRequiredForBug2473619_HAL(pGpu) gpuIsACPIPatchRequiredForBug2473619(pGpu) - -NvU32 gpuGetActiveFBIOs_FWCLIENT(struct OBJGPU *pGpu); - -NvU32 gpuGetActiveFBIOs_GM107(struct OBJGPU *pGpu); +NV_STATUS gpuInitInstLocOverrides_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled -static inline NvU32 gpuGetActiveFBIOs(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuInitInstLocOverrides(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return 0; + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuGetActiveFBIOs(pGpu) gpuGetActiveFBIOs_FWCLIENT(pGpu) +#define gpuInitInstLocOverrides(pGpu) gpuInitInstLocOverrides_IMPL(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuGetActiveFBIOs_HAL(pGpu) gpuGetActiveFBIOs(pGpu) +#define gpuInitInstLocOverrides_HAL(pGpu) gpuInitInstLocOverrides(pGpu) -static inline NvBool gpuIsDebuggerActive_8031b9(struct OBJGPU *pGpu) { - return pGpu->bIsDebugModeEnabled; -} +const GPUCHILDORDER *gpuGetChildrenOrder_GM200(struct OBJGPU *pGpu, NvU32 *pNumEntries); #ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuIsDebuggerActive(struct OBJGPU *pGpu) { +static inline const GPUCHILDORDER *gpuGetChildrenOrder(struct OBJGPU *pGpu, NvU32 *pNumEntries) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_FALSE; + return NULL; } #else //__nvoc_gpu_h_disabled -#define gpuIsDebuggerActive(pGpu) gpuIsDebuggerActive_8031b9(pGpu) +#define gpuGetChildrenOrder(pGpu, pNumEntries) gpuGetChildrenOrder_GM200(pGpu, pNumEntries) #endif //__nvoc_gpu_h_disabled -#define gpuIsDebuggerActive_HAL(pGpu) gpuIsDebuggerActive(pGpu) +#define gpuGetChildrenOrder_HAL(pGpu, pNumEntries) gpuGetChildrenOrder(pGpu, pNumEntries) -NV_STATUS gpuExecGrCtxRegops_GK104(struct OBJGPU *pGpu, struct Graphics *arg0, struct KernelChannel *arg1, NV2080_CTRL_GPU_REG_OP *pRegOps, NvU32 regOpCount, RMTIMEOUT *pTimeout, NvBool bStopCtxsw); +void gpuGetTerminatedLinkMask_GA100(struct OBJGPU *pGpu, NvU32 arg0); #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuExecGrCtxRegops(struct OBJGPU *pGpu, struct Graphics *arg0, struct KernelChannel *arg1, NV2080_CTRL_GPU_REG_OP *pRegOps, NvU32 regOpCount, RMTIMEOUT *pTimeout, NvBool bStopCtxsw) { +static inline void gpuGetTerminatedLinkMask(struct OBJGPU *pGpu, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuExecGrCtxRegops(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) gpuExecGrCtxRegops_GK104(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) +#define gpuGetTerminatedLinkMask(pGpu, arg0) gpuGetTerminatedLinkMask_GA100(pGpu, arg0) #endif //__nvoc_gpu_h_disabled -#define gpuExecGrCtxRegops_HAL(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) gpuExecGrCtxRegops(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) +#define gpuGetTerminatedLinkMask_HAL(pGpu, arg0) gpuGetTerminatedLinkMask(pGpu, arg0) -NV_STATUS gpuExtdevConstruct_GK104(struct OBJGPU *pGpu); +NV_STATUS gpuJtVersionSanityCheck_TU102(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuExtdevConstruct(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuJtVersionSanityCheck(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuExtdevConstruct(pGpu) gpuExtdevConstruct_GK104(pGpu) +#define gpuJtVersionSanityCheck(pGpu) gpuJtVersionSanityCheck_TU102(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuExtdevConstruct_HAL(pGpu) gpuExtdevConstruct(pGpu) - -NvU32 gpuReadBAR1Size_FWCLIENT(struct OBJGPU *pGpu); +#define gpuJtVersionSanityCheck_HAL(pGpu) gpuJtVersionSanityCheck(pGpu) -NvU32 gpuReadBAR1Size_TU102(struct OBJGPU *pGpu); +static inline NvBool gpuCompletedGC6PowerOff_cbe027(struct OBJGPU *pGpu) { + return ((NvBool)(0 == 0)); +} -NvU32 gpuReadBAR1Size_GH100(struct OBJGPU *pGpu); +NvBool gpuCompletedGC6PowerOff_GV100(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled -static inline NvU32 gpuReadBAR1Size(struct OBJGPU *pGpu) { +static inline NvBool gpuCompletedGC6PowerOff(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return 0; + return NV_FALSE; } #else //__nvoc_gpu_h_disabled -#define gpuReadBAR1Size(pGpu) gpuReadBAR1Size_FWCLIENT(pGpu) +#define gpuCompletedGC6PowerOff(pGpu) gpuCompletedGC6PowerOff_cbe027(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuReadBAR1Size_HAL(pGpu) gpuReadBAR1Size(pGpu) - -NvBool gpuCheckPageRetirementSupport_GSPCLIENT(struct OBJGPU *pGpu); +#define gpuCompletedGC6PowerOff_HAL(pGpu) gpuCompletedGC6PowerOff(pGpu) -NvBool gpuCheckPageRetirementSupport_GV100(struct OBJGPU *pGpu); +static inline NvBool gpuIsACPIPatchRequiredForBug2473619_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} #ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuCheckPageRetirementSupport(struct OBJGPU *pGpu) { +static inline NvBool gpuIsACPIPatchRequiredForBug2473619(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_FALSE; } #else //__nvoc_gpu_h_disabled -#define gpuCheckPageRetirementSupport(pGpu) gpuCheckPageRetirementSupport_GSPCLIENT(pGpu) +#define gpuIsACPIPatchRequiredForBug2473619(pGpu) gpuIsACPIPatchRequiredForBug2473619_491d52(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuCheckPageRetirementSupport_HAL(pGpu) gpuCheckPageRetirementSupport(pGpu) - -NvBool gpuIsInternalSku_FWCLIENT(struct OBJGPU *pGpu); +#define gpuIsACPIPatchRequiredForBug2473619_HAL(pGpu) gpuIsACPIPatchRequiredForBug2473619(pGpu) -NvBool gpuIsInternalSku_GP100(struct OBJGPU *pGpu); +static inline NvBool gpuIsDebuggerActive_8031b9(struct OBJGPU *pGpu) { + return pGpu->bIsDebugModeEnabled; +} #ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuIsInternalSku(struct OBJGPU *pGpu) { +static inline NvBool gpuIsDebuggerActive(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_FALSE; } #else //__nvoc_gpu_h_disabled -#define gpuIsInternalSku(pGpu) gpuIsInternalSku_FWCLIENT(pGpu) +#define gpuIsDebuggerActive(pGpu) gpuIsDebuggerActive_8031b9(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuIsInternalSku_HAL(pGpu) gpuIsInternalSku(pGpu) +#define gpuIsDebuggerActive_HAL(pGpu) gpuIsDebuggerActive(pGpu) + +static inline NV_STATUS gpuGetFipsStatus_46f6a7(struct OBJGPU *pGpu, NvBool *bFipsEnabled) { + return NV_ERR_NOT_SUPPORTED; +} -NV_STATUS gpuGetSriovCaps_TU102(struct OBJGPU *pGpu, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *arg0); +NV_STATUS gpuGetFipsStatus_GH100(struct OBJGPU *pGpu, NvBool *bFipsEnabled); #ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuGetSriovCaps(struct OBJGPU *pGpu, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *arg0) { +static inline NV_STATUS gpuGetFipsStatus(struct OBJGPU *pGpu, NvBool *bFipsEnabled) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuGetSriovCaps(pGpu, arg0) gpuGetSriovCaps_TU102(pGpu, arg0) +#define gpuGetFipsStatus(pGpu, bFipsEnabled) gpuGetFipsStatus_46f6a7(pGpu, bFipsEnabled) #endif //__nvoc_gpu_h_disabled -#define gpuGetSriovCaps_HAL(pGpu, arg0) gpuGetSriovCaps(pGpu, arg0) - -static inline NvBool gpuCheckIsP2PAllocated_491d52(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); -} - -NvBool gpuCheckIsP2PAllocated_GA100(struct OBJGPU *pGpu); +#define gpuGetFipsStatus_HAL(pGpu, bFipsEnabled) gpuGetFipsStatus(pGpu, bFipsEnabled) -static inline NvBool gpuCheckIsP2PAllocated_108313(struct OBJGPU *pGpu) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); -} +NV_STATUS gpuExecGrCtxRegops_GK104(struct OBJGPU *pGpu, struct Graphics *arg0, struct KernelChannel *arg1, NV2080_CTRL_GPU_REG_OP *pRegOps, NvU32 regOpCount, RMTIMEOUT *pTimeout, NvBool bStopCtxsw); #ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuCheckIsP2PAllocated(struct OBJGPU *pGpu) { +static inline NV_STATUS gpuExecGrCtxRegops(struct OBJGPU *pGpu, struct Graphics *arg0, struct KernelChannel *arg1, NV2080_CTRL_GPU_REG_OP *pRegOps, NvU32 regOpCount, RMTIMEOUT *pTimeout, NvBool bStopCtxsw) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_FALSE; + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuCheckIsP2PAllocated(pGpu) gpuCheckIsP2PAllocated_491d52(pGpu) +#define gpuExecGrCtxRegops(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) gpuExecGrCtxRegops_GK104(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) #endif //__nvoc_gpu_h_disabled -#define gpuCheckIsP2PAllocated_HAL(pGpu) gpuCheckIsP2PAllocated(pGpu) +#define gpuExecGrCtxRegops_HAL(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) gpuExecGrCtxRegops(pGpu, arg0, arg1, pRegOps, regOpCount, pTimeout, bStopCtxsw) -static inline void gpuDecodeDeviceInfoTableGroupId_b3696a(struct OBJGPU *pGpu, DEVICE_INFO2_ENTRY *pEntry, NvU32 *pDeviceAccum) { - return; -} +NV_STATUS gpuExtdevConstruct_GK104(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled -static inline void gpuDecodeDeviceInfoTableGroupId(struct OBJGPU *pGpu, DEVICE_INFO2_ENTRY *pEntry, NvU32 *pDeviceAccum) { +static inline NV_STATUS gpuExtdevConstruct(struct OBJGPU *pGpu) { NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_gpu_h_disabled -#define gpuDecodeDeviceInfoTableGroupId(pGpu, pEntry, pDeviceAccum) gpuDecodeDeviceInfoTableGroupId_b3696a(pGpu, pEntry, pDeviceAccum) +#define gpuExtdevConstruct(pGpu) gpuExtdevConstruct_GK104(pGpu) #endif //__nvoc_gpu_h_disabled -#define gpuDecodeDeviceInfoTableGroupId_HAL(pGpu, pEntry, pDeviceAccum) gpuDecodeDeviceInfoTableGroupId(pGpu, pEntry, pDeviceAccum) +#define gpuExtdevConstruct_HAL(pGpu) gpuExtdevConstruct(pGpu) static inline NV_STATUS gpuGc6EntryPstateCheck_56cd7a(struct OBJGPU *pGpu) { return NV_OK; @@ -2782,38 +2360,6 @@ static inline NV_STATUS gpuWaitGC6Ready(struct OBJGPU *pGpu) { #define gpuWaitGC6Ready_HAL(pGpu) gpuWaitGC6Ready(pGpu) -static inline NV_STATUS gpuPrePowerOff_56cd7a(struct OBJGPU *pGpu) { - return NV_OK; -} - -NV_STATUS gpuPrePowerOff_GM107(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuPrePowerOff(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuPrePowerOff(pGpu) gpuPrePowerOff_56cd7a(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuPrePowerOff_HAL(pGpu) gpuPrePowerOff(pGpu) - -NV_STATUS gpuVerifyExistence_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuVerifyExistence(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuVerifyExistence(pGpu) gpuVerifyExistence_IMPL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuVerifyExistence_HAL(pGpu) gpuVerifyExistence(pGpu) - static inline void gpuResetVFRegisters_b3696a(struct OBJGPU *pGpu, NvU32 gfid) { return; } @@ -2889,7 +2435,7 @@ static inline void gpuDetectNvlinkLinkFromGpus(struct OBJGPU *pGpu, NvU32 gpuCou #define gpuDetectNvlinkLinkFromGpus_HAL(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) gpuDetectNvlinkLinkFromGpus(pGpu, gpuCount, gpuMaskArg, pSliLinkOutputMask, pSliLinkCircular, pSliLinkEndsMask, pVidLinkCount) -NvU32 gpuGetLitterValues_FWCLIENT(struct OBJGPU *pGpu, NvU32 index); +NvU32 gpuGetLitterValues_KERNEL(struct OBJGPU *pGpu, NvU32 index); NvU32 gpuGetLitterValues_TU102(struct OBJGPU *pGpu, NvU32 index); @@ -2908,53 +2454,11 @@ static inline NvU32 gpuGetLitterValues(struct OBJGPU *pGpu, NvU32 index) { return 0; } #else //__nvoc_gpu_h_disabled -#define gpuGetLitterValues(pGpu, index) gpuGetLitterValues_FWCLIENT(pGpu, index) +#define gpuGetLitterValues(pGpu, index) gpuGetLitterValues_KERNEL(pGpu, index) #endif //__nvoc_gpu_h_disabled #define gpuGetLitterValues_HAL(pGpu, index) gpuGetLitterValues(pGpu, index) -NvBool gpuIsGlobalPoisonFuseEnabled_FWCLIENT(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NvBool gpuIsGlobalPoisonFuseEnabled(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_FALSE; -} -#else //__nvoc_gpu_h_disabled -#define gpuIsGlobalPoisonFuseEnabled(pGpu) gpuIsGlobalPoisonFuseEnabled_FWCLIENT(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuIsGlobalPoisonFuseEnabled_HAL(pGpu) gpuIsGlobalPoisonFuseEnabled(pGpu) - -NV_STATUS gpuInitOptimusSettings_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuInitOptimusSettings(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuInitOptimusSettings(pGpu) gpuInitOptimusSettings_IMPL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuInitOptimusSettings_HAL(pGpu) gpuInitOptimusSettings(pGpu) - -NV_STATUS gpuDeinitOptimusSettings_IMPL(struct OBJGPU *pGpu); - - -#ifdef __nvoc_gpu_h_disabled -static inline NV_STATUS gpuDeinitOptimusSettings(struct OBJGPU *pGpu) { - NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_gpu_h_disabled -#define gpuDeinitOptimusSettings(pGpu) gpuDeinitOptimusSettings_IMPL(pGpu) -#endif //__nvoc_gpu_h_disabled - -#define gpuDeinitOptimusSettings_HAL(pGpu) gpuDeinitOptimusSettings(pGpu) - static inline NV_STATUS gpuSetCacheOnlyModeOverrides_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } @@ -3035,18 +2539,126 @@ static inline NV_STATUS gpuLoadFailurePathTest(struct OBJGPU *pGpu, NvU32 engSta #define gpuLoadFailurePathTest_HAL(pGpu, engStage, engDescIdx, bStopTest) gpuLoadFailurePathTest(pGpu, engStage, engDescIdx, bStopTest) +static inline NV_STATUS gpuSetPartitionErrorAttribution_c04480(struct OBJGPU *pGpu, NV_ERROR_CONT_ERR_ID arg0, NV_ERROR_CONT_LOCATION arg1, NvU32 arg2) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +NV_STATUS gpuSetPartitionErrorAttribution_GA100(struct OBJGPU *pGpu, NV_ERROR_CONT_ERR_ID arg0, NV_ERROR_CONT_LOCATION arg1, NvU32 arg2); + + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuSetPartitionErrorAttribution(struct OBJGPU *pGpu, NV_ERROR_CONT_ERR_ID arg0, NV_ERROR_CONT_LOCATION arg1, NvU32 arg2) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuSetPartitionErrorAttribution(pGpu, arg0, arg1, arg2) gpuSetPartitionErrorAttribution_c04480(pGpu, arg0, arg1, arg2) +#endif //__nvoc_gpu_h_disabled + +#define gpuSetPartitionErrorAttribution_HAL(pGpu, arg0, arg1, arg2) gpuSetPartitionErrorAttribution(pGpu, arg0, arg1, arg2) + NV_STATUS gpuConstructDeviceInfoTable_FWCLIENT(struct OBJGPU *pGpu); +NV_STATUS gpuConstructDeviceInfoTable_VGPUSTUB(struct OBJGPU *pGpu); + static inline NV_STATUS gpuConstructDeviceInfoTable_56cd7a(struct OBJGPU *pGpu) { return NV_OK; } -NV_STATUS gpuConstructDeviceInfoTable_GA100(struct OBJGPU *pGpu); - static inline NV_STATUS gpuConstructDeviceInfoTable_DISPATCH(struct OBJGPU *pGpu) { return pGpu->__gpuConstructDeviceInfoTable__(pGpu); } +NV_STATUS gpuGetNameString_VGPUSTUB(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); + +NV_STATUS gpuGetNameString_KERNEL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); + +NV_STATUS gpuGetNameString_IMPL(struct OBJGPU *pGpu, NvU32 arg0, void *arg1); + +static inline NV_STATUS gpuGetNameString_DISPATCH(struct OBJGPU *pGpu, NvU32 arg0, void *arg1) { + return pGpu->__gpuGetNameString__(pGpu, arg0, arg1); +} + +NV_STATUS gpuGetShortNameString_VGPUSTUB(struct OBJGPU *pGpu, NvU8 *arg0); + +NV_STATUS gpuGetShortNameString_KERNEL(struct OBJGPU *pGpu, NvU8 *arg0); + +NV_STATUS gpuGetShortNameString_IMPL(struct OBJGPU *pGpu, NvU8 *arg0); + +static inline NV_STATUS gpuGetShortNameString_DISPATCH(struct OBJGPU *pGpu, NvU8 *arg0) { + return pGpu->__gpuGetShortNameString__(pGpu, arg0); +} + +NV_STATUS gpuInitBranding_FWCLIENT(struct OBJGPU *pGpu); + +NV_STATUS gpuInitBranding_VGPUSTUB(struct OBJGPU *pGpu); + +NV_STATUS gpuInitBranding_IMPL(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuInitBranding_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuInitBranding__(pGpu); +} + +void gpuInitProperties_FWCLIENT(struct OBJGPU *pGpu); + +static inline void gpuInitProperties_b3696a(struct OBJGPU *pGpu) { + return; +} + +static inline void gpuInitProperties_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuInitProperties__(pGpu); +} + +NV_STATUS gpuBuildKernelVideoEngineList_IMPL(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuBuildKernelVideoEngineList_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +static inline NV_STATUS gpuBuildKernelVideoEngineList_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuBuildKernelVideoEngineList__(pGpu); +} + +NV_STATUS gpuInitVideoLogging_IMPL(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuInitVideoLogging_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +static inline NV_STATUS gpuInitVideoLogging_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuInitVideoLogging__(pGpu); +} + +void gpuFreeVideoLogging_IMPL(struct OBJGPU *pGpu); + +static inline void gpuFreeVideoLogging_b3696a(struct OBJGPU *pGpu) { + return; +} + +static inline void gpuFreeVideoLogging_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuFreeVideoLogging__(pGpu); +} + +void gpuDestroyKernelVideoEngineList_IMPL(struct OBJGPU *pGpu); + +static inline void gpuDestroyKernelVideoEngineList_b3696a(struct OBJGPU *pGpu) { + return; +} + +static inline void gpuDestroyKernelVideoEngineList_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuDestroyKernelVideoEngineList__(pGpu); +} + +NV_STATUS gpuPowerOff_KERNEL(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuPowerOff_46f6a7(struct OBJGPU *pGpu) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS gpuPowerOff_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuPowerOff__(pGpu); +} + NV_STATUS gpuWriteBusConfigReg_GM107(struct OBJGPU *pGpu, NvU32 index, NvU32 value); NV_STATUS gpuWriteBusConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 value); @@ -3117,8 +2729,51 @@ void gpuGetIdInfo_GM107(struct OBJGPU *pGpu); void gpuGetIdInfo_GH100(struct OBJGPU *pGpu); -static inline void gpuGetIdInfo_DISPATCH(struct OBJGPU *pGpu) { - pGpu->__gpuGetIdInfo__(pGpu); +static inline void gpuGetIdInfo_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuGetIdInfo__(pGpu); +} + +NV_STATUS gpuGenGidData_VGPUSTUB(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags); + +NV_STATUS gpuGenGidData_FWCLIENT(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags); + +NV_STATUS gpuGenGidData_GK104(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags); + +static inline NV_STATUS gpuGenGidData_DISPATCH(struct OBJGPU *pGpu, NvU8 *pGidData, NvU32 gidSize, NvU32 gidFlags) { + return pGpu->__gpuGenGidData__(pGpu, pGidData, gidSize, gidFlags); +} + +NvU8 gpuGetChipSubRev_FWCLIENT(struct OBJGPU *pGpu); + +static inline NvU8 gpuGetChipSubRev_4a4dee(struct OBJGPU *pGpu) { + return 0; +} + +NvU8 gpuGetChipSubRev_GK104(struct OBJGPU *pGpu); + +NvU8 gpuGetChipSubRev_GA100(struct OBJGPU *pGpu); + +static inline NvU8 gpuGetChipSubRev_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuGetChipSubRev__(pGpu); +} + +static inline NV_STATUS gpuGetSkuInfo_92bfc3(struct OBJGPU *pGpu, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS gpuGetSkuInfo_VGPUSTUB(struct OBJGPU *pGpu, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pParams); + +static inline NV_STATUS gpuGetSkuInfo_DISPATCH(struct OBJGPU *pGpu, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pParams) { + return pGpu->__gpuGetSkuInfo__(pGpu, pParams); +} + +NV_STATUS gpuGetRegBaseOffset_FWCLIENT(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1); + +NV_STATUS gpuGetRegBaseOffset_TU102(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1); + +static inline NV_STATUS gpuGetRegBaseOffset_DISPATCH(struct OBJGPU *pGpu, NvU32 arg0, NvU32 *arg1) { + return pGpu->__gpuGetRegBaseOffset__(pGpu, arg0, arg1); } void gpuHandleSanityCheckRegReadError_GM107(struct OBJGPU *pGpu, NvU32 addr, NvU32 value); @@ -3139,6 +2794,18 @@ static inline void gpuHandleSecFault_DISPATCH(struct OBJGPU *pGpu) { pGpu->__gpuHandleSecFault__(pGpu); } +static inline NV_STATUS gpuSanityCheckVirtRegAccess_56cd7a(struct OBJGPU *pGpu, NvU32 arg0) { + return NV_OK; +} + +NV_STATUS gpuSanityCheckVirtRegAccess_TU102(struct OBJGPU *pGpu, NvU32 arg0); + +NV_STATUS gpuSanityCheckVirtRegAccess_GH100(struct OBJGPU *pGpu, NvU32 arg0); + +static inline NV_STATUS gpuSanityCheckVirtRegAccess_DISPATCH(struct OBJGPU *pGpu, NvU32 arg0) { + return pGpu->__gpuSanityCheckVirtRegAccess__(pGpu, arg0); +} + const GPUCHILDPRESENT *gpuGetChildrenPresent_TU102(struct OBJGPU *pGpu, NvU32 *pNumEntries); const GPUCHILDPRESENT *gpuGetChildrenPresent_TU104(struct OBJGPU *pGpu, NvU32 *pNumEntries); @@ -3185,6 +2852,61 @@ static inline NvU32 gpuGetPhysAddrWidth_DISPATCH(struct OBJGPU *pGpu, NV_ADDRESS return pGpu->__gpuGetPhysAddrWidth__(pGpu, arg0); } +NV_STATUS gpuInitSriov_VGPUSTUB(struct OBJGPU *pGpu); + +NV_STATUS gpuInitSriov_FWCLIENT(struct OBJGPU *pGpu); + +NV_STATUS gpuInitSriov_TU102(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuInitSriov_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuInitSriov__(pGpu); +} + +static inline NV_STATUS gpuDeinitSriov_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuDeinitSriov_FWCLIENT(struct OBJGPU *pGpu); + +NV_STATUS gpuDeinitSriov_TU102(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuDeinitSriov_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuDeinitSriov__(pGpu); +} + +NV_STATUS gpuCreateDefaultClientShare_VGPUSTUB(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuCreateDefaultClientShare_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +static inline NV_STATUS gpuCreateDefaultClientShare_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuCreateDefaultClientShare__(pGpu); +} + +void gpuDestroyDefaultClientShare_VGPUSTUB(struct OBJGPU *pGpu); + +static inline void gpuDestroyDefaultClientShare_b3696a(struct OBJGPU *pGpu) { + return; +} + +static inline void gpuDestroyDefaultClientShare_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuDestroyDefaultClientShare__(pGpu); +} + +static inline NvU64 gpuGetVmmuSegmentSize_13cd8d(struct OBJGPU *pGpu) { + NV_ASSERT_PRECOMP(0); + return 0; +} + +static inline NvU64 gpuGetVmmuSegmentSize_72c522(struct OBJGPU *pGpu) { + return pGpu->vmmuSegmentSize; +} + +static inline NvU64 gpuGetVmmuSegmentSize_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuGetVmmuSegmentSize__(pGpu); +} + NvBool gpuFuseSupportsDisplay_GM107(struct OBJGPU *pGpu); NvBool gpuFuseSupportsDisplay_GA100(struct OBJGPU *pGpu); @@ -3197,6 +2919,38 @@ static inline NvBool gpuFuseSupportsDisplay_DISPATCH(struct OBJGPU *pGpu) { return pGpu->__gpuFuseSupportsDisplay__(pGpu); } +NvU32 gpuGetActiveFBIOs_VGPUSTUB(struct OBJGPU *pGpu); + +NvU32 gpuGetActiveFBIOs_FWCLIENT(struct OBJGPU *pGpu); + +NvU32 gpuGetActiveFBIOs_GM107(struct OBJGPU *pGpu); + +static inline NvU32 gpuGetActiveFBIOs_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuGetActiveFBIOs__(pGpu); +} + +NvBool gpuCheckPageRetirementSupport_VGPUSTUB(struct OBJGPU *pGpu); + +NvBool gpuCheckPageRetirementSupport_GSPCLIENT(struct OBJGPU *pGpu); + +NvBool gpuCheckPageRetirementSupport_GV100(struct OBJGPU *pGpu); + +static inline NvBool gpuCheckPageRetirementSupport_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuCheckPageRetirementSupport__(pGpu); +} + +static inline NvBool gpuIsInternalSku_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +NvBool gpuIsInternalSku_FWCLIENT(struct OBJGPU *pGpu); + +NvBool gpuIsInternalSku_GP100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsInternalSku_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsInternalSku__(pGpu); +} + NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_GA100(struct OBJGPU *pGpu); static inline NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_56cd7a(struct OBJGPU *pGpu) { @@ -3207,12 +2961,62 @@ static inline NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(struct OBJ return pGpu->__gpuClearFbhubPoisonIntrForBug2924523__(pGpu); } -void gpuReadDeviceId_GM107(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); +NvBool gpuCheckIfFbhubPoisonIntrPending_GA100(struct OBJGPU *pGpu); + +static inline NvBool gpuCheckIfFbhubPoisonIntrPending_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuCheckIfFbhubPoisonIntrPending_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuCheckIfFbhubPoisonIntrPending__(pGpu); +} + +static inline NV_STATUS gpuGetSriovCaps_46f6a7(struct OBJGPU *pGpu, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *arg0) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS gpuGetSriovCaps_TU102(struct OBJGPU *pGpu, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *arg0); + +static inline NV_STATUS gpuGetSriovCaps_DISPATCH(struct OBJGPU *pGpu, NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS *arg0) { + return pGpu->__gpuGetSriovCaps__(pGpu, arg0); +} + +static inline NvBool gpuCheckIsP2PAllocated_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +NvBool gpuCheckIsP2PAllocated_GA100(struct OBJGPU *pGpu); + +static inline NvBool gpuCheckIsP2PAllocated_108313(struct OBJGPU *pGpu) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + +static inline NvBool gpuCheckIsP2PAllocated_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuCheckIsP2PAllocated__(pGpu); +} + +static inline NV_STATUS gpuPrePowerOff_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +static inline NV_STATUS gpuPrePowerOff_46f6a7(struct OBJGPU *pGpu) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS gpuPrePowerOff_GM107(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuPrePowerOff_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuPrePowerOff__(pGpu); +} + +static inline NV_STATUS gpuVerifyExistence_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} -void gpuReadDeviceId_GH100(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1); +NV_STATUS gpuVerifyExistence_IMPL(struct OBJGPU *pGpu); -static inline void gpuReadDeviceId_DISPATCH(struct OBJGPU *pGpu, NvU32 *arg0, NvU32 *arg1) { - pGpu->__gpuReadDeviceId__(pGpu, arg0, arg1); +static inline NV_STATUS gpuVerifyExistence_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuVerifyExistence__(pGpu); } NvU64 gpuGetFlaVasSize_GA100(struct OBJGPU *pGpu, NvBool bNvswitchVirtualization); @@ -3227,6 +3031,24 @@ static inline NvU64 gpuGetFlaVasSize_DISPATCH(struct OBJGPU *pGpu, NvBool bNvswi return pGpu->__gpuGetFlaVasSize__(pGpu, bNvswitchVirtualization); } +NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(struct OBJGPU *pGpu); + +static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsAtsSupportedWithSmcMemPartitioning__(pGpu); +} + +NvBool gpuIsGlobalPoisonFuseEnabled_VGPUSTUB(struct OBJGPU *pGpu); + +NvBool gpuIsGlobalPoisonFuseEnabled_FWCLIENT(struct OBJGPU *pGpu); + +static inline NvBool gpuIsGlobalPoisonFuseEnabled_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuIsGlobalPoisonFuseEnabled__(pGpu); +} + void gpuDetermineSelfHostedMode_PHYSICAL_GH100(struct OBJGPU *pGpu); static inline void gpuDetermineSelfHostedMode_b3696a(struct OBJGPU *pGpu) { @@ -3249,14 +3071,24 @@ static inline void gpuDetermineMIGSupport_DISPATCH(struct OBJGPU *pGpu) { pGpu->__gpuDetermineMIGSupport__(pGpu); } -NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(struct OBJGPU *pGpu); +static inline NV_STATUS gpuInitOptimusSettings_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} -static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_491d52(struct OBJGPU *pGpu) { - return ((NvBool)(0 != 0)); +NV_STATUS gpuInitOptimusSettings_IMPL(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuInitOptimusSettings_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuInitOptimusSettings__(pGpu); } -static inline NvBool gpuIsAtsSupportedWithSmcMemPartitioning_DISPATCH(struct OBJGPU *pGpu) { - return pGpu->__gpuIsAtsSupportedWithSmcMemPartitioning__(pGpu); +static inline NV_STATUS gpuDeinitOptimusSettings_56cd7a(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuDeinitOptimusSettings_IMPL(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuDeinitOptimusSettings_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuDeinitOptimusSettings__(pGpu); } static inline NvBool gpuIsSliCapableWithoutDisplay_cbe027(struct OBJGPU *pGpu) { @@ -3271,12 +3103,12 @@ static inline NvBool gpuIsSliCapableWithoutDisplay_DISPATCH(struct OBJGPU *pGpu) return pGpu->__gpuIsSliCapableWithoutDisplay__(pGpu); } -NvBool gpuIsCCEnabledInHw_GH100(struct OBJGPU *pGpu); - static inline NvBool gpuIsCCEnabledInHw_491d52(struct OBJGPU *pGpu) { return ((NvBool)(0 != 0)); } +NvBool gpuIsCCEnabledInHw_GH100(struct OBJGPU *pGpu); + static inline NvBool gpuIsCCEnabledInHw_DISPATCH(struct OBJGPU *pGpu) { return pGpu->__gpuIsCCEnabledInHw__(pGpu); } @@ -3301,6 +3133,65 @@ static inline NvBool gpuIsCtxBufAllocInPmaSupported_DISPATCH(struct OBJGPU *pGpu return pGpu->__gpuIsCtxBufAllocInPmaSupported__(pGpu); } +static inline NV_STATUS gpuUpdateErrorContainmentState_c04480(struct OBJGPU *pGpu, NV_ERROR_CONT_ERR_ID arg0, NV_ERROR_CONT_LOCATION arg1, NvU32 *arg2) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +NV_STATUS gpuUpdateErrorContainmentState_GA100(struct OBJGPU *pGpu, NV_ERROR_CONT_ERR_ID arg0, NV_ERROR_CONT_LOCATION arg1, NvU32 *arg2); + +static inline NV_STATUS gpuUpdateErrorContainmentState_f91eed(struct OBJGPU *pGpu, NV_ERROR_CONT_ERR_ID arg0, NV_ERROR_CONT_LOCATION arg1, NvU32 *arg2) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_OK); +} + +static inline NV_STATUS gpuUpdateErrorContainmentState_DISPATCH(struct OBJGPU *pGpu, NV_ERROR_CONT_ERR_ID arg0, NV_ERROR_CONT_LOCATION arg1, NvU32 *arg2) { + return pGpu->__gpuUpdateErrorContainmentState__(pGpu, arg0, arg1, arg2); +} + +static inline void gpuCheckEccCounts_d44104(struct OBJGPU *pGpu) { + return; +} + +void gpuCheckEccCounts_TU102(struct OBJGPU *pGpu); + +static inline void gpuCheckEccCounts_DISPATCH(struct OBJGPU *pGpu) { + pGpu->__gpuCheckEccCounts__(pGpu); +} + +static inline NV_STATUS gpuClearEccCounts_ac1694(struct OBJGPU *pGpu) { + return NV_OK; +} + +NV_STATUS gpuClearEccCounts_TU102(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuClearEccCounts_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuClearEccCounts__(pGpu); +} + +NV_STATUS gpuWaitForGfwBootComplete_TU102(struct OBJGPU *pGpu); + +static inline NV_STATUS gpuWaitForGfwBootComplete_5baef9(struct OBJGPU *pGpu) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS gpuWaitForGfwBootComplete_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuWaitForGfwBootComplete__(pGpu); +} + +static inline NvBool gpuGetIsCmpSku_ceaee8(struct OBJGPU *pGpu) { + NV_ASSERT_PRECOMP(0); + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuGetIsCmpSku_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +NvBool gpuGetIsCmpSku_GV100(struct OBJGPU *pGpu); + +static inline NvBool gpuGetIsCmpSku_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuGetIsCmpSku__(pGpu); +} + static inline PENGDESCRIPTOR gpuGetInitEngineDescriptors(struct OBJGPU *pGpu) { return pGpu->engineOrder.pEngineInitDescriptors; } @@ -3506,10 +3397,6 @@ static inline NvBool gpuIsVgxBranded(struct OBJGPU *pGpu) { return pGpu->bIsVgx; } -static inline NvBool gpuIsACBranded(struct OBJGPU *pGpu) { - return pGpu->bIsAC; -} - static inline NvBool gpuIsNvidiaNvsBranded(struct OBJGPU *pGpu) { return pGpu->bIsNvidiaNvs; } @@ -3534,6 +3421,18 @@ static inline NvBool gpuIsNonPowerOf2ChannelCountSupported(struct OBJGPU *pGpu) return pGpu->bNonPowerOf2ChannelCountSupported; } +static inline NvBool gpuIsVfResizableBAR1Supported(struct OBJGPU *pGpu) { + return pGpu->bVfResizableBAR1Supported; +} + +static inline NvBool gpuIsVoltaHubIntrSupported(struct OBJGPU *pGpu) { + return pGpu->bVoltaHubIntrSupported; +} + +static inline NvBool gpuIsAmpereErrorContainmentXidEnabled(struct OBJGPU *pGpu) { + return pGpu->bAmpereErrorContainmentXidEnabled; +} + static inline NvBool gpuIsSelfHosted(struct OBJGPU *pGpu) { return pGpu->bIsSelfHosted; } @@ -3542,9 +3441,9 @@ static inline NvBool gpuIsGspOwnedFaultBuffersEnabled(struct OBJGPU *pGpu) { return pGpu->bIsGspOwnedFaultBuffersEnabled; } -NV_STATUS gpuConstruct_IMPL(struct OBJGPU *arg_pGpu, NvU32 arg_gpuInstance); +NV_STATUS gpuConstruct_IMPL(struct OBJGPU *arg_pGpu, NvU32 arg_gpuInstance, NvU32 arg_gpuId, NvUuid *arg_pUuid); -#define __nvoc_gpuConstruct(arg_pGpu, arg_gpuInstance) gpuConstruct_IMPL(arg_pGpu, arg_gpuInstance) +#define __nvoc_gpuConstruct(arg_pGpu, arg_gpuInstance, arg_gpuId, arg_pUuid) gpuConstruct_IMPL(arg_pGpu, arg_gpuInstance, arg_gpuId, arg_pUuid) NV_STATUS gpuBindHalLegacy_IMPL(struct OBJGPU *pGpu, NvU32 chipId0, NvU32 chipId1, NvU32 socChipId0); #ifdef __nvoc_gpu_h_disabled @@ -3957,6 +3856,45 @@ void gpuGetNv2080EngineTypeList_IMPL(RM_ENGINE_TYPE *pRmEngineList, NvU32 engine NV_STATUS gpuGetRmEngineTypeCapMask_IMPL(NvU32 *NV2080EngineTypeCap, NvU32 capSize, NvU32 *RmEngineTypeCap); #define gpuGetRmEngineTypeCapMask(NV2080EngineTypeCap, capSize, RmEngineTypeCap) gpuGetRmEngineTypeCapMask_IMPL(NV2080EngineTypeCap, capSize, RmEngineTypeCap) +BRANDING_TYPE gpuDetectBranding_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline BRANDING_TYPE gpuDetectBranding(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + BRANDING_TYPE ret; + portMemSet(&ret, 0, sizeof(BRANDING_TYPE)); + return ret; +} +#else //__nvoc_gpu_h_disabled +#define gpuDetectBranding(pGpu) gpuDetectBranding_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +COMPUTE_BRANDING_TYPE gpuDetectComputeBranding_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline COMPUTE_BRANDING_TYPE gpuDetectComputeBranding(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + COMPUTE_BRANDING_TYPE ret; + portMemSet(&ret, 0, sizeof(COMPUTE_BRANDING_TYPE)); + return ret; +} +#else //__nvoc_gpu_h_disabled +#define gpuDetectComputeBranding(pGpu) gpuDetectComputeBranding_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + +BRANDING_TYPE gpuDetectVgxBranding_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline BRANDING_TYPE gpuDetectVgxBranding(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + BRANDING_TYPE ret; + portMemSet(&ret, 0, sizeof(BRANDING_TYPE)); + return ret; +} +#else //__nvoc_gpu_h_disabled +#define gpuDetectVgxBranding(pGpu) gpuDetectVgxBranding_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + NvU32 gpuGetGpuMask_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -4400,6 +4338,17 @@ static inline NvBool gpuIsCCDevToolsModeEnabled(struct OBJGPU *pGpu) { #define gpuIsCCDevToolsModeEnabled(pGpu) gpuIsCCDevToolsModeEnabled_IMPL(pGpu) #endif //__nvoc_gpu_h_disabled +NvBool gpuIsCCMultiGpuProtectedPcieModeEnabled_IMPL(struct OBJGPU *pGpu); + +#ifdef __nvoc_gpu_h_disabled +static inline NvBool gpuIsCCMultiGpuProtectedPcieModeEnabled(struct OBJGPU *pGpu) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_FALSE; +} +#else //__nvoc_gpu_h_disabled +#define gpuIsCCMultiGpuProtectedPcieModeEnabled(pGpu) gpuIsCCMultiGpuProtectedPcieModeEnabled_IMPL(pGpu) +#endif //__nvoc_gpu_h_disabled + NvBool gpuIsOnTheBus_IMPL(struct OBJGPU *pGpu); #ifdef __nvoc_gpu_h_disabled @@ -4476,6 +4425,17 @@ static inline void gpuInitChipInfo(struct OBJGPU *pGpu) { #define gpuInitChipInfo(pGpu) gpuInitChipInfo_IMPL(pGpu) #endif //__nvoc_gpu_h_disabled +NV_STATUS gpuGetChipDetails_IMPL(struct OBJGPU *pGpu, NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS *arg0); + +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuGetChipDetails(struct OBJGPU *pGpu, NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS *arg0) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuGetChipDetails(pGpu, arg0) gpuGetChipDetails_IMPL(pGpu, arg0) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuSanityCheckRegRead_IMPL(struct OBJGPU *pGpu, NvU32 addr, NvU32 size, void *pValue); #ifdef __nvoc_gpu_h_disabled @@ -4664,6 +4624,8 @@ static NvU32 gpuGetNumCEs(struct OBJGPU *pGpu) // IS_SILICON Real hardware // IS_VIRTUAL RM is running within a guest VM // IS_GSP_CLIENT RM is a GSP/DCE client with GPU support offloaded to GSP/DCE +// IS_DCE_CLIENT RM is specifically a DCE client with GPU support offloaded +// to DCE (subset of IS_GSP_CLIENT) // #define IS_EMULATION(pGpu) ((pGpu)->getProperty((pGpu), PDB_PROP_GPU_EMULATION)) @@ -4674,19 +4636,28 @@ static NvU32 gpuGetNumCEs(struct OBJGPU *pGpu) #define IS_SILICON(pGpu) (!(IS_EMULATION(pGpu) || IS_SIMULATION(pGpu))) #define IS_PASSTHRU(pGpu) ((pGpu)->bIsPassthru) #define IS_GSP_CLIENT(pGpu) ((RMCFG_FEATURE_GSP_CLIENT_RM || RMCFG_FEATURE_DCE_CLIENT_RM) && (pGpu)->isGspClient) -#define IS_VIRTUAL(pGpu) NV_FALSE -#define IS_VIRTUAL_WITH_SRIOV(pGpu) NV_FALSE -#define IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu) NV_FALSE -#define IS_VIRTUAL_WITH_FULL_SRIOV(pGpu) NV_FALSE -#define IS_VIRTUAL_WITHOUT_SRIOV(pGpu) NV_FALSE -#define IS_SRIOV_HEAVY(pGpu) NV_FALSE -#define IS_SRIOV_HEAVY_GUEST(pGpu) NV_FALSE -#define IS_SRIOV_FULL_GUEST(pGpu) NV_FALSE -#define IS_SRIOV_HEAVY_HOST(pGpu) NV_FALSE +#define IS_DCE_CLIENT(pGpu) (RMCFG_FEATURE_DCE_CLIENT_RM && IS_GSP_CLIENT(pGpu)) +// +// We expect GSP_CLIENT_RM and DCE_CLIENT_RM to be exclusive in RMCFG because we +// use this above to differentiate between them. This allows a compile time +// check for RMCFG_FEATURE_DCE_CLIENT_RM instead of a runtime check for +// IsT234DorBetter(pGpu) +// +ct_assert(!(RMCFG_FEATURE_GSP_CLIENT_RM && RMCFG_FEATURE_DCE_CLIENT_RM)); +#define IS_VIRTUAL(pGpu) ((pGpu)->isVirtual) +#define IS_VIRTUAL_WITH_SRIOV(pGpu) ((pGpu)->bIsVirtualWithSriov) +#define IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu) (IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) +#define IS_VIRTUAL_WITH_FULL_SRIOV(pGpu) (IS_VIRTUAL_WITH_SRIOV(pGpu) && !IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu)) +#define IS_VIRTUAL_WITHOUT_SRIOV(pGpu) (IS_VIRTUAL(pGpu) && !IS_VIRTUAL_WITH_SRIOV(pGpu)) +#define IS_SRIOV_HEAVY(pGpu) (gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) +#define IS_SRIOV_HEAVY_GUEST(pGpu) ((IS_VIRTUAL_WITH_SRIOV(pGpu)) && IS_SRIOV_HEAVY(pGpu)) +#define IS_SRIOV_FULL_GUEST(pGpu) ((IS_VIRTUAL_WITH_SRIOV(pGpu)) && !IS_SRIOV_HEAVY(pGpu)) +#define IS_SRIOV_HEAVY_HOST(pGpu) ((hypervisorIsVgxHyper()) && IS_SRIOV_HEAVY(pGpu)) #define IS_SRIOV_FULL_HOST(pGpu) ((hypervisorIsVgxHyper()) && gpuIsSriovEnabled(pGpu) && !IS_SRIOV_HEAVY(pGpu)) #define IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) ((pGpu)->bVgpuGspPluginOffloadEnabled) #define IS_SRIOV_WITH_VGPU_GSP_ENABLED(pGpu) (gpuIsSriovEnabled(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_SRIOV_HEAVY(pGpu)) #define IS_SRIOV_WITH_VGPU_GSP_DISABLED(pGpu) (gpuIsSriovEnabled(pGpu) && !IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_SRIOV_HEAVY(pGpu)) +#define IS_MIG_RM(pGpu) ((pGpu)->bIsMigRm) extern GPU_CHILD_ITER gpuGetPossibleEngDescriptorIter(void); extern NvBool gpuGetNextPossibleEngDescriptor(GPU_CHILD_ITER *pIt, ENGDESCRIPTOR *pEngDesc); @@ -4754,6 +4725,67 @@ NV_STATUS gpuValidateRegOps(struct OBJGPU *, NV2080_CTRL_GPU_REG_OP *, NvU32, Nv ((NULL == pGpu) || \ pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TIMEOUT_RECOVERY)) +//****************************************************************************** +// POWER SANITY CHECKS +//****************************************************************************** +// +// Make sure the GPU is in full power or resuming from D3 state. Else, +// bailout from the calling function. An exception for systems, which support +// surprise removal feature. See Bugs 440565, 479003, and 499228.DO NOT IGNORE +// OR REMOVE THIS ASSERT. If you have problems with it, please talk to cplummer. +// +// bAllowWithoutSysmemAccess: Allow this RM Control when sysmem access is not available +// from the GPU. SHould be NV_TRUE only for NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS +// +// On systems supporting surprise removal, if the GPU is in D3 cold +// and still attached we would consider it a true D3 cold state +// and return NOT_FULL_POWER. See bug 1679965. +// +// +#define API_GPU_FULL_POWER_SANITY_CHECK(pGpu, bGpuAccess, bAllowWithoutSysmemAccess) \ + if ((!gpuIsGpuFullPower(pGpu)) && \ + (!(pGpu)->getProperty((pGpu), \ + PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ + { \ + DBG_BREAKPOINT(); \ + if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ + } \ + else if (gpuIsSurpriseRemovalSupported(pGpu) && \ + (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ + } \ + } \ + if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ + } + +#define API_GPU_FULL_POWER_SANITY_CHECK_OR_GOTO(pGpu, bGpuAccess, bAllowWithoutSysmemAccess, status, tag) \ + if ((!gpuIsGpuFullPower(pGpu)) && \ + (!(pGpu)->getProperty((pGpu), \ + PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ + { \ + DBG_BREAKPOINT(); \ + if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ + { \ + status = NV_ERR_GPU_NOT_FULL_POWER; \ + goto tag; \ + } \ + else if (gpuIsSurpriseRemovalSupported(pGpu) && \ + (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ + { \ + status = NV_ERR_GPU_NOT_FULL_POWER; \ + goto tag; \ + } \ + } \ + if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ + { \ + return NV_ERR_GPU_NOT_FULL_POWER; \ + } + // // Identifiers for gpuGetRegBaseOffset HAL interface. // @@ -4773,14 +4805,6 @@ ct_assert(NV_REG_BASE_LAST < NV2080_CTRL_INTERNAL_GET_CHIP_INFO_REG_BASE_MAX); // #define GPU_REG_VALUE_INVALID 0xFFFFFFFF -// -// Hal InfoBlock access interface -// -#define gpuGetInfoBlock(pGpu, pListHead, dataId) getInfoPtr(pListHead, dataId) -#define gpuAddInfoBlock(pGpu, ppListHead, dataId, size) addInfoPtr(ppListHead, dataId, size) -#define gpuDeleteInfoBlock(pGpu, ppListHead, dataId) deleteInfoPtr(ppListHead, dataId); -#define gpuTestInfoBlock(pGpu, pListHead, dataId) testInfoPtr(pListHead, dataId); - typedef struct _vgpu_static_info VGPU_STATIC_INFO; typedef struct GspStaticConfigInfo_t GspStaticConfigInfo; @@ -4795,6 +4819,13 @@ NV_STATUS gpuSimEscapeWriteBuffer(struct OBJGPU *, const char *path, NvU32 Index NV_STATUS gpuSimEscapeRead(struct OBJGPU *, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value); NV_STATUS gpuSimEscapeReadBuffer(struct OBJGPU *, const char *path, NvU32 Index, NvU32 Size, void* pBuffer); +// +// This function needs to be called when OBJGPU is not created. HAL +// infrastructure can’t be used for this case, so it has been added manually. +// It will be invoked directly by gpumgrIsDeviceMsixAllowed(). +// +NvBool gpuIsMsixAllowed_TU102(RmPhysAddr bar0BaseAddr); + #endif // _OBJGPU_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_gpu_resource_nvoc.c b/src/nvidia/generated/g_gpu_resource_nvoc.c index 5ba1800136..c0125bbc84 100644 --- a/src/nvidia/generated/g_gpu_resource_nvoc.c +++ b/src/nvidia/generated/g_gpu_resource_nvoc.c @@ -124,10 +124,6 @@ static void __nvoc_thunk_RsResource_gpuresAddAdditionalDependants(struct RsClien resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_gpuresUnmapFrom(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_gpuresControlSerialization_Prologue(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); } @@ -140,6 +136,10 @@ static NvBool __nvoc_thunk_RsResource_gpuresCanCopy(struct GpuResource *pResourc return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_gpuresIsPartialUnmapSupported(struct GpuResource *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_gpuresPreDestruct(struct GpuResource *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset)); } @@ -160,8 +160,8 @@ static void __nvoc_thunk_RmResource_gpuresControl_Epilogue(struct GpuResource *p rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gpuresControlLookup(struct GpuResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_gpuresUnmapFrom(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuResource_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_gpuresAccessCallback(struct GpuResource *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { @@ -242,14 +242,14 @@ static void __nvoc_init_funcTable_GpuResource_1(GpuResource *pThis) { pThis->__gpuresAddAdditionalDependants__ = &__nvoc_thunk_RsResource_gpuresAddAdditionalDependants; - pThis->__gpuresUnmapFrom__ = &__nvoc_thunk_RsResource_gpuresUnmapFrom; - pThis->__gpuresControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpuresControlSerialization_Prologue; pThis->__gpuresControl_Prologue__ = &__nvoc_thunk_RmResource_gpuresControl_Prologue; pThis->__gpuresCanCopy__ = &__nvoc_thunk_RsResource_gpuresCanCopy; + pThis->__gpuresIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_gpuresIsPartialUnmapSupported; + pThis->__gpuresPreDestruct__ = &__nvoc_thunk_RsResource_gpuresPreDestruct; pThis->__gpuresMapTo__ = &__nvoc_thunk_RsResource_gpuresMapTo; @@ -260,7 +260,7 @@ static void __nvoc_init_funcTable_GpuResource_1(GpuResource *pThis) { pThis->__gpuresControl_Epilogue__ = &__nvoc_thunk_RmResource_gpuresControl_Epilogue; - pThis->__gpuresControlLookup__ = &__nvoc_thunk_RsResource_gpuresControlLookup; + pThis->__gpuresUnmapFrom__ = &__nvoc_thunk_RsResource_gpuresUnmapFrom; pThis->__gpuresAccessCallback__ = &__nvoc_thunk_RmResource_gpuresAccessCallback; } @@ -280,21 +280,26 @@ void __nvoc_init_GpuResource(GpuResource *pThis) { __nvoc_init_funcTable_GpuResource(pThis); } -NV_STATUS __nvoc_objCreate_GpuResource(GpuResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_GpuResource(GpuResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GpuResource *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuResource), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GpuResource)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuResource); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -309,16 +314,25 @@ NV_STATUS __nvoc_objCreate_GpuResource(GpuResource **ppThis, Dynamic *pParent, N status = __nvoc_ctor_GpuResource(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_GpuResource_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GpuResource_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GpuResource)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_resource_nvoc.h b/src/nvidia/generated/g_gpu_resource_nvoc.h index 74efd213dd..bbc6a9d2c6 100644 --- a/src/nvidia/generated/g_gpu_resource_nvoc.h +++ b/src/nvidia/generated/g_gpu_resource_nvoc.h @@ -85,11 +85,16 @@ typedef struct Subdevice Subdevice; /*! * Abstract base class for common CPU mapping operations */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_RESOURCE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GpuResource { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -112,16 +117,16 @@ struct GpuResource { NvU32 (*__gpuresGetRefCount__)(struct GpuResource *); NV_STATUS (*__gpuresControlFilter__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpuresAddAdditionalDependants__)(struct RsClient *, struct GpuResource *, RsResourceRef *); - NV_STATUS (*__gpuresUnmapFrom__)(struct GpuResource *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__gpuresControlSerialization_Prologue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpuresControl_Prologue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gpuresCanCopy__)(struct GpuResource *); + NvBool (*__gpuresIsPartialUnmapSupported__)(struct GpuResource *); void (*__gpuresPreDestruct__)(struct GpuResource *); NV_STATUS (*__gpuresMapTo__)(struct GpuResource *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__gpuresIsDuplicate__)(struct GpuResource *, NvHandle, NvBool *); void (*__gpuresControlSerialization_Epilogue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__gpuresControl_Epilogue__)(struct GpuResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gpuresControlLookup__)(struct GpuResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__gpuresUnmapFrom__)(struct GpuResource *, RS_RES_UNMAP_FROM_PARAMS *); NvBool (*__gpuresAccessCallback__)(struct GpuResource *, struct RsClient *, void *, RsAccessRight); struct OBJGPUGRP *pGpuGrp; struct OBJGPU *pGpu; @@ -172,16 +177,16 @@ NV_STATUS __nvoc_objCreate_GpuResource(GpuResource**, Dynamic*, NvU32, struct CA #define gpuresGetRefCount(pResource) gpuresGetRefCount_DISPATCH(pResource) #define gpuresControlFilter(pResource, pCallContext, pParams) gpuresControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gpuresAddAdditionalDependants(pClient, pResource, pReference) gpuresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define gpuresUnmapFrom(pResource, pParams) gpuresUnmapFrom_DISPATCH(pResource, pParams) #define gpuresControlSerialization_Prologue(pResource, pCallContext, pParams) gpuresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControl_Prologue(pResource, pCallContext, pParams) gpuresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gpuresCanCopy(pResource) gpuresCanCopy_DISPATCH(pResource) +#define gpuresIsPartialUnmapSupported(pResource) gpuresIsPartialUnmapSupported_DISPATCH(pResource) #define gpuresPreDestruct(pResource) gpuresPreDestruct_DISPATCH(pResource) #define gpuresMapTo(pResource, pParams) gpuresMapTo_DISPATCH(pResource, pParams) #define gpuresIsDuplicate(pResource, hMemory, pDuplicate) gpuresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gpuresControlSerialization_Epilogue(pResource, pCallContext, pParams) gpuresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define gpuresControl_Epilogue(pResource, pCallContext, pParams) gpuresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define gpuresControlLookup(pResource, pParams, ppEntry) gpuresControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define gpuresUnmapFrom(pResource, pParams) gpuresUnmapFrom_DISPATCH(pResource, pParams) #define gpuresAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) gpuresAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS gpuresControl_IMPL(struct GpuResource *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); @@ -255,10 +260,6 @@ static inline void gpuresAddAdditionalDependants_DISPATCH(struct RsClient *pClie pResource->__gpuresAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS gpuresUnmapFrom_DISPATCH(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__gpuresUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS gpuresControlSerialization_Prologue_DISPATCH(struct GpuResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__gpuresControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -271,6 +272,10 @@ static inline NvBool gpuresCanCopy_DISPATCH(struct GpuResource *pResource) { return pResource->__gpuresCanCopy__(pResource); } +static inline NvBool gpuresIsPartialUnmapSupported_DISPATCH(struct GpuResource *pResource) { + return pResource->__gpuresIsPartialUnmapSupported__(pResource); +} + static inline void gpuresPreDestruct_DISPATCH(struct GpuResource *pResource) { pResource->__gpuresPreDestruct__(pResource); } @@ -291,8 +296,8 @@ static inline void gpuresControl_Epilogue_DISPATCH(struct GpuResource *pResource pResource->__gpuresControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpuresControlLookup_DISPATCH(struct GpuResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gpuresControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS gpuresUnmapFrom_DISPATCH(struct GpuResource *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__gpuresUnmapFrom__(pResource, pParams); } static inline NvBool gpuresAccessCallback_DISPATCH(struct GpuResource *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c index f06581b0c8..cee3c06440 100644 --- a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_gpushareddataControl_Epilogue(struct GpuUser rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gpushareddataControlLookup(struct GpuUserSharedData *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_gpushareddataControl(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_gpushareddataControlSerialization_Prolo return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_gpushareddataIsPartialUnmapSupported(struct GpuUserSharedData *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GpuUserSharedData_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_gpushareddataIsReady(struct GpuUserSharedData *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_GpuUserSharedData_Memory.offset), bCopyConstructorContext); } @@ -290,8 +290,6 @@ static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) pThis->__gpushareddataControl_Epilogue__ = &__nvoc_thunk_RmResource_gpushareddataControl_Epilogue; - pThis->__gpushareddataControlLookup__ = &__nvoc_thunk_RsResource_gpushareddataControlLookup; - pThis->__gpushareddataControl__ = &__nvoc_thunk_Memory_gpushareddataControl; pThis->__gpushareddataUnmap__ = &__nvoc_thunk_Memory_gpushareddataUnmap; @@ -304,6 +302,8 @@ static void __nvoc_init_funcTable_GpuUserSharedData_1(GpuUserSharedData *pThis) pThis->__gpushareddataControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_gpushareddataControlSerialization_Prologue; + pThis->__gpushareddataIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_gpushareddataIsPartialUnmapSupported; + pThis->__gpushareddataIsReady__ = &__nvoc_thunk_Memory_gpushareddataIsReady; pThis->__gpushareddataCheckCopyPermissions__ = &__nvoc_thunk_Memory_gpushareddataCheckCopyPermissions; @@ -335,21 +335,26 @@ void __nvoc_init_GpuUserSharedData(GpuUserSharedData *pThis) { __nvoc_init_funcTable_GpuUserSharedData(pThis); } -NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GpuUserSharedData *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GpuUserSharedData), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GpuUserSharedData)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GpuUserSharedData); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -364,16 +369,25 @@ NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData **ppThis, Dynamic status = __nvoc_ctor_GpuUserSharedData(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_GpuUserSharedData_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GpuUserSharedData_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GpuUserSharedData)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h index 89c9750be8..34ffd8598a 100644 --- a/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h +++ b/src/nvidia/generated/g_gpu_user_shared_data_nvoc.h @@ -47,11 +47,16 @@ extern "C" { /*! * RM internal class representing RM_USER_SHARED_DATA */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_USER_SHARED_DATA_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GpuUserSharedData { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -74,13 +79,13 @@ struct GpuUserSharedData { NvBool (*__gpushareddataIsGpuMapAllowed__)(struct GpuUserSharedData *, struct OBJGPU *); NV_STATUS (*__gpushareddataUnmapFrom__)(struct GpuUserSharedData *, RS_RES_UNMAP_FROM_PARAMS *); void (*__gpushareddataControl_Epilogue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gpushareddataControlLookup__)(struct GpuUserSharedData *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__gpushareddataControl__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpushareddataUnmap__)(struct GpuUserSharedData *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__gpushareddataGetMemInterMapParams__)(struct GpuUserSharedData *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__gpushareddataGetMemoryMappingDescriptor__)(struct GpuUserSharedData *, MEMORY_DESCRIPTOR **); NV_STATUS (*__gpushareddataControlFilter__)(struct GpuUserSharedData *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gpushareddataControlSerialization_Prologue__)(struct GpuUserSharedData *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__gpushareddataIsPartialUnmapSupported__)(struct GpuUserSharedData *); NV_STATUS (*__gpushareddataIsReady__)(struct GpuUserSharedData *, NvBool); NV_STATUS (*__gpushareddataCheckCopyPermissions__)(struct GpuUserSharedData *, struct OBJGPU *, struct Device *); void (*__gpushareddataPreDestruct__)(struct GpuUserSharedData *); @@ -132,13 +137,13 @@ NV_STATUS __nvoc_objCreate_GpuUserSharedData(GpuUserSharedData**, Dynamic*, NvU3 #define gpushareddataIsGpuMapAllowed(pMemory, pGpu) gpushareddataIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define gpushareddataUnmapFrom(pResource, pParams) gpushareddataUnmapFrom_DISPATCH(pResource, pParams) #define gpushareddataControl_Epilogue(pResource, pCallContext, pParams) gpushareddataControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define gpushareddataControlLookup(pResource, pParams, ppEntry) gpushareddataControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gpushareddataControl(pMemory, pCallContext, pParams) gpushareddataControl_DISPATCH(pMemory, pCallContext, pParams) #define gpushareddataUnmap(pMemory, pCallContext, pCpuMapping) gpushareddataUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define gpushareddataGetMemInterMapParams(pMemory, pParams) gpushareddataGetMemInterMapParams_DISPATCH(pMemory, pParams) #define gpushareddataGetMemoryMappingDescriptor(pMemory, ppMemDesc) gpushareddataGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define gpushareddataControlFilter(pResource, pCallContext, pParams) gpushareddataControlFilter_DISPATCH(pResource, pCallContext, pParams) #define gpushareddataControlSerialization_Prologue(pResource, pCallContext, pParams) gpushareddataControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define gpushareddataIsPartialUnmapSupported(pResource) gpushareddataIsPartialUnmapSupported_DISPATCH(pResource) #define gpushareddataIsReady(pMemory, bCopyConstructorContext) gpushareddataIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define gpushareddataCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) gpushareddataCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define gpushareddataPreDestruct(pResource) gpushareddataPreDestruct_DISPATCH(pResource) @@ -202,10 +207,6 @@ static inline void gpushareddataControl_Epilogue_DISPATCH(struct GpuUserSharedDa pResource->__gpushareddataControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gpushareddataControlLookup_DISPATCH(struct GpuUserSharedData *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gpushareddataControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS gpushareddataControl_DISPATCH(struct GpuUserSharedData *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__gpushareddataControl__(pMemory, pCallContext, pParams); } @@ -230,6 +231,10 @@ static inline NV_STATUS gpushareddataControlSerialization_Prologue_DISPATCH(stru return pResource->__gpushareddataControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool gpushareddataIsPartialUnmapSupported_DISPATCH(struct GpuUserSharedData *pResource) { + return pResource->__gpushareddataIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS gpushareddataIsReady_DISPATCH(struct GpuUserSharedData *pMemory, NvBool bCopyConstructorContext) { return pMemory->__gpushareddataIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.c b/src/nvidia/generated/g_gpu_vaspace_nvoc.c index 0ceee5a36b..b788e30382 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.c +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.c @@ -102,7 +102,7 @@ static struct OBJEHEAP *__nvoc_thunk_OBJGVASPACE_vaspaceGetHeap(struct OBJVASPAC return gvaspaceGetHeap((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset)); } -static NvU64 __nvoc_thunk_OBJGVASPACE_vaspaceGetMapPageSize(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJGVASPACE_vaspaceGetMapPageSize(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock) { return gvaspaceGetMapPageSize((struct OBJGVASPACE *)(((unsigned char *)pVAS) - __nvoc_rtti_OBJGVASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } @@ -342,21 +342,26 @@ void __nvoc_init_OBJGVASPACE(OBJGVASPACE *pThis) { __nvoc_init_funcTable_OBJGVASPACE(pThis); } -NV_STATUS __nvoc_objCreate_OBJGVASPACE(OBJGVASPACE **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJGVASPACE(OBJGVASPACE **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJGVASPACE *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGVASPACE), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJGVASPACE)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGVASPACE); pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -371,16 +376,25 @@ NV_STATUS __nvoc_objCreate_OBJGVASPACE(OBJGVASPACE **ppThis, Dynamic *pParent, N status = __nvoc_ctor_OBJGVASPACE(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJGVASPACE_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJGVASPACE_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJGVASPACE)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gpu_vaspace_nvoc.h b/src/nvidia/generated/g_gpu_vaspace_nvoc.h index e9fb7a1b38..54f3e898e6 100644 --- a/src/nvidia/generated/g_gpu_vaspace_nvoc.h +++ b/src/nvidia/generated/g_gpu_vaspace_nvoc.h @@ -210,11 +210,16 @@ struct MMU_WALK_USER_CTX /*! * RM-registered/managed GPU virtual address space. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GPU_VASPACE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJGVASPACE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJVASPACE __nvoc_base_OBJVASPACE; @@ -230,7 +235,7 @@ struct OBJGVASPACE { NV_STATUS (*__gvaspaceMap__)(struct OBJGVASPACE *, struct OBJGPU *, const NvU64, const NvU64, const MMU_MAP_TARGET *, const VAS_MAP_FLAGS); void (*__gvaspaceUnmap__)(struct OBJGVASPACE *, struct OBJGPU *, const NvU64, const NvU64); struct OBJEHEAP *(*__gvaspaceGetHeap__)(struct OBJGVASPACE *); - NvU64 (*__gvaspaceGetMapPageSize__)(struct OBJGVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__gvaspaceGetMapPageSize__)(struct OBJGVASPACE *, struct OBJGPU *, struct EMEMBLOCK *); NvU64 (*__gvaspaceGetBigPageSize__)(struct OBJGVASPACE *); NvU32 (*__gvaspaceGetFlags__)(struct OBJGVASPACE *); NvBool (*__gvaspaceIsMirrored__)(struct OBJGVASPACE *); @@ -386,9 +391,9 @@ static inline struct OBJEHEAP *gvaspaceGetHeap_DISPATCH(struct OBJGVASPACE *pVAS return pVAS->__gvaspaceGetHeap__(pVAS); } -NvU64 gvaspaceGetMapPageSize_IMPL(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock); +NvU64 gvaspaceGetMapPageSize_IMPL(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock); -static inline NvU64 gvaspaceGetMapPageSize_DISPATCH(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 gvaspaceGetMapPageSize_DISPATCH(struct OBJGVASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock) { return pVAS->__gvaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff --git a/src/nvidia/generated/g_gsync_api_nvoc.c b/src/nvidia/generated/g_gsync_api_nvoc.c index cb4f80aea1..dfa3e92813 100644 --- a/src/nvidia/generated/g_gsync_api_nvoc.c +++ b/src/nvidia/generated/g_gsync_api_nvoc.c @@ -146,10 +146,6 @@ static void __nvoc_thunk_RmResource_gsyncapiControl_Epilogue(struct GSyncApi *pR rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_gsyncapiControlLookup(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_gsyncapiUnmap(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset), pCallContext, pCpuMapping); } @@ -178,6 +174,10 @@ static NvBool __nvoc_thunk_RsResource_gsyncapiCanCopy(struct GSyncApi *pResource return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_gsyncapiIsPartialUnmapSupported(struct GSyncApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_gsyncapiPreDestruct(struct GSyncApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_GSyncApi_RsResource.offset)); } @@ -835,8 +835,6 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiControl_Epilogue__ = &__nvoc_thunk_RmResource_gsyncapiControl_Epilogue; - pThis->__gsyncapiControlLookup__ = &__nvoc_thunk_RsResource_gsyncapiControlLookup; - pThis->__gsyncapiUnmap__ = &__nvoc_thunk_RsResource_gsyncapiUnmap; pThis->__gsyncapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_gsyncapiGetMemInterMapParams; @@ -851,6 +849,8 @@ static void __nvoc_init_funcTable_GSyncApi_1(GSyncApi *pThis) { pThis->__gsyncapiCanCopy__ = &__nvoc_thunk_RsResource_gsyncapiCanCopy; + pThis->__gsyncapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_gsyncapiIsPartialUnmapSupported; + pThis->__gsyncapiPreDestruct__ = &__nvoc_thunk_RsResource_gsyncapiPreDestruct; pThis->__gsyncapiIsDuplicate__ = &__nvoc_thunk_RsResource_gsyncapiIsDuplicate; @@ -885,21 +885,26 @@ void __nvoc_init_GSyncApi(GSyncApi *pThis) { __nvoc_init_funcTable_GSyncApi(pThis); } -NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GSyncApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GSyncApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GSyncApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GSyncApi); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -914,16 +919,25 @@ NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_GSyncApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_GSyncApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GSyncApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GSyncApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gsync_api_nvoc.h b/src/nvidia/generated/g_gsync_api_nvoc.h index a6b6bc2870..041255be57 100644 --- a/src/nvidia/generated/g_gsync_api_nvoc.h +++ b/src/nvidia/generated/g_gsync_api_nvoc.h @@ -43,11 +43,16 @@ extern "C" { /* ------------------------ Macros & Defines ------------------------------- */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GSYNC_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GSyncApi { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -99,7 +104,6 @@ struct GSyncApi { NV_STATUS (*__gsyncapiControl_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__gsyncapiUnmapFrom__)(struct GSyncApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__gsyncapiControl_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__gsyncapiControlLookup__)(struct GSyncApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__gsyncapiUnmap__)(struct GSyncApi *, struct CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__gsyncapiGetMemInterMapParams__)(struct GSyncApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__gsyncapiGetMemoryMappingDescriptor__)(struct GSyncApi *, struct MEMORY_DESCRIPTOR **); @@ -107,6 +111,7 @@ struct GSyncApi { NV_STATUS (*__gsyncapiUnregisterEvent__)(struct GSyncApi *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__gsyncapiControlSerialization_Prologue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__gsyncapiCanCopy__)(struct GSyncApi *); + NvBool (*__gsyncapiIsPartialUnmapSupported__)(struct GSyncApi *); void (*__gsyncapiPreDestruct__)(struct GSyncApi *); NV_STATUS (*__gsyncapiIsDuplicate__)(struct GSyncApi *, NvHandle, NvBool *); void (*__gsyncapiControlSerialization_Epilogue__)(struct GSyncApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -190,7 +195,6 @@ NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi**, Dynamic*, NvU32, struct CALL_CON #define gsyncapiControl_Prologue(pResource, pCallContext, pParams) gsyncapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gsyncapiUnmapFrom(pResource, pParams) gsyncapiUnmapFrom_DISPATCH(pResource, pParams) #define gsyncapiControl_Epilogue(pResource, pCallContext, pParams) gsyncapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define gsyncapiControlLookup(pResource, pParams, ppEntry) gsyncapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define gsyncapiUnmap(pResource, pCallContext, pCpuMapping) gsyncapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) #define gsyncapiGetMemInterMapParams(pRmResource, pParams) gsyncapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define gsyncapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) gsyncapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) @@ -198,6 +202,7 @@ NV_STATUS __nvoc_objCreate_GSyncApi(GSyncApi**, Dynamic*, NvU32, struct CALL_CON #define gsyncapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) gsyncapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define gsyncapiControlSerialization_Prologue(pResource, pCallContext, pParams) gsyncapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define gsyncapiCanCopy(pResource) gsyncapiCanCopy_DISPATCH(pResource) +#define gsyncapiIsPartialUnmapSupported(pResource) gsyncapiIsPartialUnmapSupported_DISPATCH(pResource) #define gsyncapiPreDestruct(pResource) gsyncapiPreDestruct_DISPATCH(pResource) #define gsyncapiIsDuplicate(pResource, hMemory, pDuplicate) gsyncapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define gsyncapiControlSerialization_Epilogue(pResource, pCallContext, pParams) gsyncapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -425,10 +430,6 @@ static inline void gsyncapiControl_Epilogue_DISPATCH(struct GSyncApi *pResource, pResource->__gsyncapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS gsyncapiControlLookup_DISPATCH(struct GSyncApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__gsyncapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS gsyncapiUnmap_DISPATCH(struct GSyncApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pResource->__gsyncapiUnmap__(pResource, pCallContext, pCpuMapping); } @@ -457,6 +458,10 @@ static inline NvBool gsyncapiCanCopy_DISPATCH(struct GSyncApi *pResource) { return pResource->__gsyncapiCanCopy__(pResource); } +static inline NvBool gsyncapiIsPartialUnmapSupported_DISPATCH(struct GSyncApi *pResource) { + return pResource->__gsyncapiIsPartialUnmapSupported__(pResource); +} + static inline void gsyncapiPreDestruct_DISPATCH(struct GSyncApi *pResource) { pResource->__gsyncapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_gsync_nvoc.c b/src/nvidia/generated/g_gsync_nvoc.c index 8333a89958..5d69b38cac 100644 --- a/src/nvidia/generated/g_gsync_nvoc.c +++ b/src/nvidia/generated/g_gsync_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_OBJGSYNCMGR(OBJGSYNCMGR *pThis) { __nvoc_init_funcTable_OBJGSYNCMGR(pThis); } -NV_STATUS __nvoc_objCreate_OBJGSYNCMGR(OBJGSYNCMGR **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJGSYNCMGR(OBJGSYNCMGR **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJGSYNCMGR *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGSYNCMGR), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJGSYNCMGR)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGSYNCMGR); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_OBJGSYNCMGR(OBJGSYNCMGR **ppThis, Dynamic *pParent, N status = __nvoc_ctor_OBJGSYNCMGR(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJGSYNCMGR_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJGSYNCMGR_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJGSYNCMGR)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_gsync_nvoc.h b/src/nvidia/generated/g_gsync_nvoc.h index bf46da9a75..33f54eaa65 100644 --- a/src/nvidia/generated/g_gsync_nvoc.h +++ b/src/nvidia/generated/g_gsync_nvoc.h @@ -219,11 +219,16 @@ typedef struct _def_gsync { typedef struct OBJGSYNCMGR *POBJGSYNCMGR; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_GSYNC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJGSYNCMGR { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_hal.h b/src/nvidia/generated/g_hal.h index 63f98f2914..7e7ef9184f 100644 --- a/src/nvidia/generated/g_hal.h +++ b/src/nvidia/generated/g_hal.h @@ -25,6 +25,7 @@ typedef struct RPCSTRUCTURECOPY_HAL_IFACES *PRPCSTRUCTURECOPY_HAL_IFACES; typedef struct { void (*rpcHalIfacesSetupFn)(PRPC_HAL_IFACES pRpcHal); + void (*rpcstructurecopyHalIfacesSetupFn)(PRPCSTRUCTURECOPY_HAL_IFACES pRpcstructurecopyHal); } HAL_IFACE_SETUP, *PHAL_IFACE_SETUP; diff --git a/src/nvidia/generated/g_hal_mgr_nvoc.c b/src/nvidia/generated/g_hal_mgr_nvoc.c index c6bc509954..ba566946c7 100644 --- a/src/nvidia/generated/g_hal_mgr_nvoc.c +++ b/src/nvidia/generated/g_hal_mgr_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_OBJHALMGR(OBJHALMGR *pThis) { __nvoc_init_funcTable_OBJHALMGR(pThis); } -NV_STATUS __nvoc_objCreate_OBJHALMGR(OBJHALMGR **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJHALMGR(OBJHALMGR **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJHALMGR *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHALMGR), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJHALMGR)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHALMGR); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_OBJHALMGR(OBJHALMGR **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_OBJHALMGR(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJHALMGR_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJHALMGR_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJHALMGR)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_hal_mgr_nvoc.h b/src/nvidia/generated/g_hal_mgr_nvoc.h index 4a4bd80776..5df3423ed5 100644 --- a/src/nvidia/generated/g_hal_mgr_nvoc.h +++ b/src/nvidia/generated/g_hal_mgr_nvoc.h @@ -35,7 +35,6 @@ extern "C" { #define _HAL_MGR_H_ #include "core/core.h" -#include "core/info_block.h" #include "core/hal.h" #define HALMGR_GET_HAL(p, halid) halmgrGetHal((p), halid) @@ -53,11 +52,16 @@ typedef struct OBJHALMGR OBJHALMGR; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_HAL_MGR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJHALMGR { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_hal_nvoc.c b/src/nvidia/generated/g_hal_nvoc.c index a4b5bb321a..5ef27d29ac 100644 --- a/src/nvidia/generated/g_hal_nvoc.c +++ b/src/nvidia/generated/g_hal_nvoc.c @@ -103,21 +103,26 @@ void __nvoc_init_OBJHAL(OBJHAL *pThis) { __nvoc_init_funcTable_OBJHAL(pThis); } -NV_STATUS __nvoc_objCreate_OBJHAL(OBJHAL **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJHAL(OBJHAL **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJHAL *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHAL), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJHAL)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHAL); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -132,16 +137,25 @@ NV_STATUS __nvoc_objCreate_OBJHAL(OBJHAL **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_OBJHAL(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJHAL_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJHAL_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJHAL)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_hal_nvoc.h b/src/nvidia/generated/g_hal_nvoc.h index ee7711340f..94be7c40a7 100644 --- a/src/nvidia/generated/g_hal_nvoc.h +++ b/src/nvidia/generated/g_hal_nvoc.h @@ -42,7 +42,6 @@ extern "C" { \***************************************************************************/ #include "core/core.h" -#include "core/info_block.h" // // HAL Info Block Id: @@ -78,11 +77,16 @@ typedef struct OBJHAL OBJHAL; #endif /* __nvoc_class_id_OBJHAL */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_HAL_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJHAL { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_hal_private.h b/src/nvidia/generated/g_hal_private.h index f90562ec9b..f415cb9ac8 100644 --- a/src/nvidia/generated/g_hal_private.h +++ b/src/nvidia/generated/g_hal_private.h @@ -67,6 +67,7 @@ // pull in private headers for each engine #include "g_rpc_private.h" +#include "g_rpcstructurecopy_private.h" // @@ -81,6 +82,7 @@ NV_STATUS registerHalModule(NvU32, const HAL_IFACE_SETUP *); static const HAL_IFACE_SETUP halIface_TU102 = { rpcHalIfacesSetup_TU102, + rpcstructurecopyHalIfacesSetup_TU102, }; @@ -96,6 +98,7 @@ NV_STATUS registerHalModule_TU102(void) static const HAL_IFACE_SETUP halIface_TU104 = { rpcHalIfacesSetup_TU104, + rpcstructurecopyHalIfacesSetup_TU104, }; @@ -111,6 +114,7 @@ NV_STATUS registerHalModule_TU104(void) static const HAL_IFACE_SETUP halIface_TU106 = { rpcHalIfacesSetup_TU106, + rpcstructurecopyHalIfacesSetup_TU106, }; @@ -126,6 +130,7 @@ NV_STATUS registerHalModule_TU106(void) static const HAL_IFACE_SETUP halIface_TU116 = { rpcHalIfacesSetup_TU116, + rpcstructurecopyHalIfacesSetup_TU116, }; @@ -141,6 +146,7 @@ NV_STATUS registerHalModule_TU116(void) static const HAL_IFACE_SETUP halIface_TU117 = { rpcHalIfacesSetup_TU117, + rpcstructurecopyHalIfacesSetup_TU117, }; @@ -156,6 +162,7 @@ NV_STATUS registerHalModule_TU117(void) static const HAL_IFACE_SETUP halIface_GA100 = { rpcHalIfacesSetup_GA100, + rpcstructurecopyHalIfacesSetup_GA100, }; @@ -171,6 +178,7 @@ NV_STATUS registerHalModule_GA100(void) static const HAL_IFACE_SETUP halIface_GA102 = { rpcHalIfacesSetup_GA102, + rpcstructurecopyHalIfacesSetup_GA102, }; @@ -186,6 +194,7 @@ NV_STATUS registerHalModule_GA102(void) static const HAL_IFACE_SETUP halIface_GA103 = { rpcHalIfacesSetup_GA103, + rpcstructurecopyHalIfacesSetup_GA103, }; @@ -201,6 +210,7 @@ NV_STATUS registerHalModule_GA103(void) static const HAL_IFACE_SETUP halIface_GA104 = { rpcHalIfacesSetup_GA104, + rpcstructurecopyHalIfacesSetup_GA104, }; @@ -216,6 +226,7 @@ NV_STATUS registerHalModule_GA104(void) static const HAL_IFACE_SETUP halIface_GA106 = { rpcHalIfacesSetup_GA106, + rpcstructurecopyHalIfacesSetup_GA106, }; @@ -231,6 +242,7 @@ NV_STATUS registerHalModule_GA106(void) static const HAL_IFACE_SETUP halIface_GA107 = { rpcHalIfacesSetup_GA107, + rpcstructurecopyHalIfacesSetup_GA107, }; @@ -246,6 +258,7 @@ NV_STATUS registerHalModule_GA107(void) static const HAL_IFACE_SETUP halIface_AD102 = { rpcHalIfacesSetup_AD102, + rpcstructurecopyHalIfacesSetup_AD102, }; @@ -261,6 +274,7 @@ NV_STATUS registerHalModule_AD102(void) static const HAL_IFACE_SETUP halIface_AD103 = { rpcHalIfacesSetup_AD103, + rpcstructurecopyHalIfacesSetup_AD103, }; @@ -276,6 +290,7 @@ NV_STATUS registerHalModule_AD103(void) static const HAL_IFACE_SETUP halIface_AD104 = { rpcHalIfacesSetup_AD104, + rpcstructurecopyHalIfacesSetup_AD104, }; @@ -291,6 +306,7 @@ NV_STATUS registerHalModule_AD104(void) static const HAL_IFACE_SETUP halIface_AD106 = { rpcHalIfacesSetup_AD106, + rpcstructurecopyHalIfacesSetup_AD106, }; @@ -306,6 +322,7 @@ NV_STATUS registerHalModule_AD106(void) static const HAL_IFACE_SETUP halIface_AD107 = { rpcHalIfacesSetup_AD107, + rpcstructurecopyHalIfacesSetup_AD107, }; @@ -321,6 +338,7 @@ NV_STATUS registerHalModule_AD107(void) static const HAL_IFACE_SETUP halIface_GH100 = { rpcHalIfacesSetup_GH100, + rpcstructurecopyHalIfacesSetup_GH100, }; diff --git a/src/nvidia/generated/g_hal_stubs.h b/src/nvidia/generated/g_hal_stubs.h index 3b1a934807..9d7a6534c2 100644 --- a/src/nvidia/generated/g_hal_stubs.h +++ b/src/nvidia/generated/g_hal_stubs.h @@ -13,6 +13,7 @@ // pull in private headers for each engine #include "g_rpc_private.h" +#include "g_rpcstructurecopy_private.h" #include "g_hal.h" @@ -493,44 +494,6 @@ NvBool gpioIsFeatureAvailableHal_MISSING( return NV_FALSE; } -// GPIO:hal:GET_PWM_CONTROL_HAL - GPIO disabled -NV_STATUS gpioGetPwmControlHal_MISSING( - POBJGPIO pGpio, - NvU32 gpioPin, - NvU32 *pFlags, - NvU32 *pPeriod, - NvU32 *pDutyCycle, - NvU32 halIndex -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -// GPIO:hal:SET_PWM_CONTROL_HAL - GPIO disabled -NV_STATUS gpioSetPwmControlHal_MISSING( - POBJGPIO pGpio, - NvU32 gpioPin, - NvU32 *pFlags, - NvU32 *pPeriod, - NvU32 *pDutyCycle, - NvU32 halIndex, - NvBool bSkipPinInit -) -{ - return NV_ERR_NOT_SUPPORTED; -} - -// GPIO:hal:GET_PWM_PARAMETERS_HAL - GPIO disabled -NV_STATUS gpioGetPwmParametersHal_MISSING( - POBJGPIO pGpio, - NvU32 gpioPin, - NvU32 *pMaxPeriod, - NvU32 halIndex -) -{ - return NV_ERR_NOT_SUPPORTED; -} - // GPIO:hal:GET_FUNC_PWM_SENSE - GPIO disabled NvU32 gpioGetFuncPwmSense_MISSING( POBJGPIO pGpio, @@ -676,6 +639,18 @@ NvU32 gpioInitAndGetPinNum_FWCLIENT( return (NvU32) 0; } +// RPC:hal:CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFifoSetupVfZombieSubctxPdb_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + // RPC:hal:VGPU_PF_REG_READ32 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcVgpuPfRegRead32_STUB( POBJGPU pGpu, @@ -688,6 +663,18 @@ NV_STATUS rpcVgpuPfRegRead32_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } +// RPC:hal:CTRL_BUS_UNSET_P2P_MAPPING - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlBusUnsetP2pMapping_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + // RPC:hal:DUMP_PROTOBUF_COMPONENT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcDumpProtobufComponent_STUB( POBJGPU pGpu, @@ -724,6 +711,28 @@ NV_STATUS rpcAllocMemory_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } +// RPC:hal:CTRL_DBG_READ_SINGLE_SM_ERROR_STATE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgReadSingleSmErrorState_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:DISABLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcDisableChannels_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvU32 arg3 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + // RPC:hal:GPU_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X NV_STATUS rpcGpuExecRegOps_STUB( POBJGPU pGpu, @@ -737,206 +746,1958 @@ NV_STATUS rpcGpuExecRegOps_STUB( return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_INIT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcRmfsInit_STUB( +// RPC:hal:CTRL_GPU_PROMOTE_CTX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpuPromoteCtx_STUB( POBJGPU pGpu, POBJRPC pRpc, - PMEMORY_DESCRIPTOR arg3 + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNSET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcUnsetPageDirectory_STUB( +// RPC:hal:CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgSetNextStopTriggerType_STUB( POBJGPU pGpu, POBJRPC pRpc, NvHandle arg3, NvHandle arg4, - NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pArg5 + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GET_GSP_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcGetGspStaticInfo_STUB( +// RPC:hal:ALLOC_SHARE_DEVICE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcAllocShareDevice_STUB( POBJGPU pGpu, - POBJRPC pRpc + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvHandle arg5, + NvHandle arg6, + NvHandle arg7, + NvU32 arg8, + NvU32 arg9, + NvU64 arg10, + NvU32 arg11 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GSP_SET_SYSTEM_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcGspSetSystemInfo_STUB( +// RPC:hal:CTRL_PREEMPT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlPreempt_STUB( POBJGPU pGpu, - POBJRPC pRpc + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_CLEANUP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcRmfsCleanup_STUB( +// RPC:hal:CTRL_GPU_INITIALIZE_CTX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpuInitializeCtx_STUB( POBJGPU pGpu, - POBJRPC pRpc + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:SET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcSetPageDirectory_STUB( +// RPC:hal:CTRL_RESERVE_PM_AREA_SMPC - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlReservePmAreaSmpc_STUB( POBJGPU pGpu, POBJRPC pRpc, NvHandle arg3, NvHandle arg4, - NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pArg5 + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNLOADING_GUEST_DRIVER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcUnloadingGuestDriver_STUB( +// RPC:hal:CTRL_GPU_MIGRATABLE_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpuMigratableOps_STUB( POBJGPU pGpu, POBJRPC pRpc, - NvBool arg3, - NvBool arg4, - NvU32 arg5 + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:SET_REGISTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcSetRegistry_STUB( +// RPC:hal:CTRL_DBG_SET_MODE_ERRBAR_DEBUG - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgSetModeErrbarDebug_STUB( POBJGPU pGpu, - POBJRPC pRpc + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_CLOSE_QUEUE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcRmfsCloseQueue_STUB( +// RPC:hal:CTRL_PMA_STREAM_UPDATE_GET_PUT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlPmaStreamUpdateGetPut_STUB( POBJGPU pGpu, - POBJRPC pRpc + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:GET_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcGetStaticInfo_STUB( +// RPC:hal:CTRL_FABRIC_MEMORY_DESCRIBE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFabricMemoryDescribe_STUB( POBJGPU pGpu, - POBJRPC pRpc + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:IDLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcIdleChannels_STUB( - OBJGPU *pArg1, +// RPC:hal:ALLOC_CHANNEL_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcAllocChannelDma_STUB( + POBJGPU pGpu, POBJRPC pRpc, - NvHandle *phclients, - NvHandle *phdevices, - NvHandle *phchannels, - NvU32 nentries, - NvU32 flags, - NvU32 timeout + NvHandle arg3, + NvHandle arg4, + NvHandle arg5, + NvU32 arg6, + NV_CHANNEL_ALLOC_PARAMS *pArg7, + NvU32 *pArg8 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UPDATE_BAR_PDE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcUpdateBarPde_STUB( +// RPC:hal:CTRL_SET_ZBC_DEPTH_CLEAR - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlSetZbcDepthClear_STUB( POBJGPU pGpu, POBJRPC pRpc, - NV_RPC_UPDATE_PDE_BAR_TYPE arg3, - NvU64 arg4, - NvU64 arg5 + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:MAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcMapMemoryDma_STUB( +// RPC:hal:CTRL_RESET_ISOLATED_CHANNEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlResetIsolatedChannel_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DMA_SET_DEFAULT_VASPACE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDmaSetDefaultVaspace_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:ALLOC_SUBDEVICE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcAllocSubdevice_STUB( POBJGPU pGpu, POBJRPC pRpc, NvHandle arg3, NvHandle arg4, NvHandle arg5, - NvHandle arg6, - NvU64 arg7, - NvU64 arg8, - NvU32 arg9, - NvU64 *pArg10 + NvU32 arg6, + NvU32 arg7 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:UNMAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcUnmapMemoryDma_STUB( +// RPC:hal:FREE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcFree_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvHandle arg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:DMA_CONTROL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcDmaControl_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvU32 arg5, + void *pArg6, + NvU32 arg7 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgClearSingleSmErrorState_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:UNSET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcUnsetPageDirectory_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:GET_GSP_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcGetGspStaticInfo_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:SAVE_HIBERNATION_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcSaveHibernationData_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:DUP_OBJECT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcDupObject_STUB( POBJGPU pGpu, POBJRPC pRpc, NvHandle arg3, NvHandle arg4, NvHandle arg5, NvHandle arg6, - NvU32 arg7, - NvU64 arg8 + NvHandle arg7, + NvU32 arg8 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:GSP_SET_SYSTEM_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcGspSetSystemInfo_STUB( + POBJGPU pGpu, + POBJRPC pRpc ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPC:hal:RMFS_TEST - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -NV_STATUS rpcRmfsTest_STUB( +// RPC:hal:CTRL_PM_AREA_PC_SAMPLER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlPmAreaPcSampler_STUB( POBJGPU pGpu, POBJRPC pRpc, - NvU32 arg3, - NvU32 arg4, + NvHandle arg3, + NvHandle arg4, NvU32 arg5, - NvU32 arg6 + void *pArg6 ) { return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS - RPCSTRUCTURECOPY disabled -NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB( - NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *data, - NvU8 *stream, - NvU32 streamSize, - NvU32 *offset +// RPC:hal:CTRL_DBG_SET_EXCEPTION_MASK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgSetExceptionMask_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { - return NV_OK; + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS - RPCSTRUCTURECOPY disabled -NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB( - NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *data, - NvU8 *stream, - NvU32 streamSize, - NvU32 *offset +// RPC:hal:CTRL_VASPACE_COPY_SERVER_RESERVED_PDES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlVaspaceCopyServerReservedPdes_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { - return NV_OK; + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; } -// RPCSTRUCTURECOPY:hal:IGRP_IP_VERSIONS_GET_INFO - RPCSTRUCTURECOPY disabled -NV_STATUS rpcstructurecopy_iGrp_ipVersions_getInfo_STUB( - IGRP_IP_VERSIONS_TABLE_INFO *pArg1 +// RPC:hal:CTRL_GR_CTXSW_PREEMPTION_BIND - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGrCtxswPreemptionBind_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 ) { - return NV_ERR_NOT_SUPPORTED; + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_ALLOC_PMA_STREAM - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlAllocPmaStream_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_RESERVE_HWPM_LEGACY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlReserveHwpmLegacy_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_INTERNAL_QUIESCE_PMA_CHANNEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlInternalQuiescePmaChannel_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_PERF_RATED_TDP_GET_STATUS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlPerfRatedTdpGetStatus_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_BUS_SET_P2P_MAPPING - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlBusSetP2pMapping_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GPU_GET_INFO_V2 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpuGetInfoV2_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_HS_CREDITS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetHsCredits_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GR_SET_CTXSW_PREEMPTION_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGrSetCtxswPreemptionMode_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_B0CC_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlB0ccExecRegOps_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GRMGR_GET_GR_FS_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGrmgrGetGrFsInfo_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_ZBC_CLEAR_TABLE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetZbcClearTable_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CLEANUP_SURFACE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCleanupSurface_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pArg3 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_SET_TIMESLICE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlSetTimeslice_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GPU_QUERY_ECC_STATUS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpuQueryEccStatus_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_GET_MODE_MMU_DEBUG - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgGetModeMmuDebug_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgClearAllSmErrorStates_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:VGPU_GSP_RING_DOORBELL - TU10X, GA100 +NV_STATUS rpcVgpuGspRingDoorbell_STUB( + POBJGPU pGpu, + NvU32 arg2 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GR_SET_TPC_PARTITION_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGrSetTpcPartitionMode_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_TOTAL_HS_CREDITS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetTotalHsCredits_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlInternalPromoteFaultMethodBuffers_STUB( + OBJGPU *pArg1, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_FB_GET_INFO_V2 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFbGetInfoV2_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:VGPU_GSP_WRITE_SCRATCH_REGISTER - TU10X, GA100 +NV_STATUS rpcVgpuGspWriteScratchRegister_STUB( + POBJGPU pGpu, + NvU64 arg2 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:SET_PAGE_DIRECTORY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcSetPageDirectory_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_P2P_CAPS_V2 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetP2pCapsV2_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + void *pArg3 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_NVLINK_GET_INBAND_RECEIVED_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlNvlinkGetInbandReceivedData_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pArg3, + NvU16 arg4, + NvBool *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_CE_PCE_MASK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetCePceMask_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_NVLINK_PEER_ID_MASK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetNvlinkPeerIdMask_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GPU_EVICT_CTX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpuEvictCtx_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_MMU_DEBUG_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetMmuDebugMode_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:INVALIDATE_TLB - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcInvalidateTlb_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvU64 arg3, + NvU32 arg4 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgSetSingleSmSingleStep_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:UNLOADING_GUEST_DRIVER - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcUnloadingGuestDriver_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvBool arg3, + NvBool arg4, + NvU32 arg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:GET_CONSOLIDATED_GR_STATIC_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcGetConsolidatedGrStaticInfo_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:SWITCH_TO_VGA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcSwitchToVga_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_RESET_CHANNEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlResetChannel_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GPFIFO_SCHEDULE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpfifoSchedule_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvU32 arg5, + void *pArg6 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:SET_REGISTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcSetRegistry_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_NVLINK_STATUS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetNvlinkStatus_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:GET_STATIC_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcGetStaticData_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GR_GET_TPC_PARTITION_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGrGetTpcPartitionMode_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_STOP_CHANNEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlStopChannel_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:SET_SURFACE_PROPERTIES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcSetSurfaceProperties_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES *pArg4, + NvBool arg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_TIMER_SET_GR_TICK_FREQ - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlTimerSetGrTickFreq_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:ALLOC_EVENT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcAllocEvent_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvHandle arg5, + NvHandle arg6, + NvHandle arg7, + NvU32 arg8, + NvU32 arg9 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GR_PC_SAMPLING_MODE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGrPcSamplingMode_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_MC_SERVICE_INTERRUPTS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlMcServiceInterrupts_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_READ_ALL_SM_ERROR_STATES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgReadAllSmErrorStates_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_SET_ZBC_COLOR_CLEAR - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlSetZbcColorClear_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:GET_ENCODER_CAPACITY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcGetEncoderCapacity_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvU32 *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_P2P_CAPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetP2pCaps_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:PERF_GET_LEVEL_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcPerfGetLevelInfo_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS *pArg5, + NV2080_CTRL_PERF_GET_CLK_INFO *pArg6 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:ALLOC_OBJECT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcAllocObject_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvHandle arg5, + NvU32 arg6, + void *pArg7 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GPU_HANDLE_VF_PRI_FAULT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpuHandleVfPriFault_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:RM_API_CONTROL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcRmApiControl_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvU32 arg5, + void *pArg6, + NvU32 arg7 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_FABRIC_MEM_STATS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFabricMemStats_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GR_CTXSW_ZCULL_BIND - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGrCtxswZcullBind_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlInternalMemsysSetZbcReferenced_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_PERF_RATED_TDP_SET_CONTROL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlPerfRatedTdpSetControl_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_EXEC_PARTITIONS_CREATE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlExecPartitionsCreate_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGpfifoGetWorkSubmitToken_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:IDLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcIdleChannels_STUB( + OBJGPU *pArg1, + POBJRPC pRpc, + NvHandle *phclients, + NvHandle *phdevices, + NvHandle *phchannels, + NvU32 nentries, + NvU32 flags, + NvU32 timeout +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlCmdInternalGpuStartFabricProbe_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS *pArg3 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:GET_BRAND_CAPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcGetBrandCaps_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvU32 arg5, + void *pArg6, + NvU32 arg7 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:RESTORE_HIBERNATION_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcRestoreHibernationData_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFlaSetupInstanceMemBlock_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlInternalSriovPromotePmaStream_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_FB_GET_FS_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFbGetFsInfo_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_SET_CHANNEL_INTERLEAVE_LEVEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlSetChannelInterleaveLevel_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_RESUME_CONTEXT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgResumeContext_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:ALLOC_ROOT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcAllocRoot_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_FIFO_DISABLE_CHANNELS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFifoDisableChannels_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_SET_HS_CREDITS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlSetHsCredits_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:GET_ENGINE_UTILIZATION - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcGetEngineUtilization_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvU32 arg5, + void *pArg6, + NvU32 arg7 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_ZBC_CLEAR_TABLE_ENTRY - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetZbcClearTableEntry_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_NVENC_SW_SESSION_UPDATE_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlNvencSwSessionUpdateInfo_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_SUSPEND_CONTEXT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgSuspendContext_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_GET_P2P_CAPS_MATRIX - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlGetP2pCapsMatrix_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_EXEC_REG_OPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgExecRegOps_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_FREE_PMA_STREAM - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFreePmaStream_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_SET_TSG_INTERLEAVE_LEVEL - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlSetTsgInterleaveLevel_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:LOG - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcLog_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + const char *pArg3, + NvU32 arg4 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_EXEC_PARTITIONS_DELETE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlExecPartitionsDelete_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_PERF_BOOST - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlPerfBoost_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_DBG_SET_MODE_MMU_DEBUG - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlDbgSetModeMmuDebug_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_FIFO_SET_CHANNEL_PROPERTIES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlFifoSetChannelProperties_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_SUBDEVICE_GET_P2P_CAPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlSubdeviceGetP2pCaps_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + void *pArg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:UPDATE_BAR_PDE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcUpdateBarPde_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NV_RPC_UPDATE_PDE_BAR_TYPE arg3, + NvU64 arg4, + NvU64 arg5 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:CTRL_BIND_PM_RESOURCES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcCtrlBindPmResources_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:MAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcMapMemoryDma_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvHandle arg5, + NvHandle arg6, + NvU64 arg7, + NvU64 arg8, + NvU32 arg9, + NvU64 *pArg10 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:UNMAP_MEMORY_DMA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcUnmapMemoryDma_STUB( + POBJGPU pGpu, + POBJRPC pRpc, + NvHandle arg3, + NvHandle arg4, + NvHandle arg5, + NvHandle arg6, + NvU32 arg7, + NvU64 arg8 +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPC:hal:SET_GUEST_SYSTEM_INFO_EXT - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS rpcSetGuestSystemInfoExt_STUB( + POBJGPU pGpu, + POBJRPC pRpc +) +{ + return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB( + NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB( + NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB( + NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_P2P_CAPABILITY_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB( + VGPU_P2P_CAPABILITY_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB( + NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NVA080_CTRL_VGPU_GET_CONFIG_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB( + NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB( + NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB( + NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB( + NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_GPU_GET_GID_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB( + NV2080_CTRL_GPU_GET_GID_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB( + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB( + NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB( + VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_FB_GET_LTC_INFO_FOR_FBP - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB( + VGPU_FB_GET_LTC_INFO_FOR_FBP *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_STATIC_DATA - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_STATIC_DATA_STUB( + VGPU_STATIC_DATA *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB( + NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB( + NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB( + NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_FIFO_GET_DEVICE_INFO_TABLE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB( + VGPU_FIFO_GET_DEVICE_INFO_TABLE *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB( + NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_BSP_GET_CAPS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_BSP_GET_CAPS_STUB( + VGPU_BSP_GET_CAPS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB( + NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:GPU_PARTITION_INFO - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_GPU_PARTITION_INFO_STUB( + GPU_PARTITION_INFO *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB( + NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB( + NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB( + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB( + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_STATIC_PROPERTIES - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_STATIC_PROPERTIES_STUB( + VGPU_STATIC_PROPERTIES *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_BUS_GET_INFO_V2_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB( + NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB( + NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB( + NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_FLA_GET_RANGE_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB( + NV2080_CTRL_FLA_GET_RANGE_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB( + NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB( + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_CE_GET_CAPS_V2 - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_CE_GET_CAPS_V2_STUB( + VGPU_CE_GET_CAPS_V2 *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:VGPU_GET_LATENCY_BUFFER_SIZE - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB( + VGPU_GET_LATENCY_BUFFER_SIZE *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; +} + +// RPCSTRUCTURECOPY:hal:NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS - TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +NV_STATUS deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB( + NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *data, + NvU8 *stream, + NvU32 streamSize, + NvU32 *offset +) +{ + return NV_OK; } diff --git a/src/nvidia/generated/g_hda_codec_api_nvoc.c b/src/nvidia/generated/g_hda_codec_api_nvoc.c index aeacf574f0..20ceab5afe 100644 --- a/src/nvidia/generated/g_hda_codec_api_nvoc.c +++ b/src/nvidia/generated/g_hda_codec_api_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_hdacodecControl_Epilogue(struct Hdacodec *pR rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_hdacodecControlLookup(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle(struct Hdacodec *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Hdacodec_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_hdacodecCanCopy(struct Hdacodec *pResource return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_hdacodecIsPartialUnmapSupported(struct Hdacodec *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_hdacodecPreDestruct(struct Hdacodec *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Hdacodec_RsResource.offset)); } @@ -253,8 +253,6 @@ static void __nvoc_init_funcTable_Hdacodec_1(Hdacodec *pThis) { pThis->__hdacodecControl_Epilogue__ = &__nvoc_thunk_RmResource_hdacodecControl_Epilogue; - pThis->__hdacodecControlLookup__ = &__nvoc_thunk_RsResource_hdacodecControlLookup; - pThis->__hdacodecGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_hdacodecGetInternalObjectHandle; pThis->__hdacodecControl__ = &__nvoc_thunk_GpuResource_hdacodecControl; @@ -271,6 +269,8 @@ static void __nvoc_init_funcTable_Hdacodec_1(Hdacodec *pThis) { pThis->__hdacodecCanCopy__ = &__nvoc_thunk_RsResource_hdacodecCanCopy; + pThis->__hdacodecIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_hdacodecIsPartialUnmapSupported; + pThis->__hdacodecPreDestruct__ = &__nvoc_thunk_RsResource_hdacodecPreDestruct; pThis->__hdacodecIsDuplicate__ = &__nvoc_thunk_RsResource_hdacodecIsDuplicate; @@ -298,21 +298,26 @@ void __nvoc_init_Hdacodec(Hdacodec *pThis) { __nvoc_init_funcTable_Hdacodec(pThis); } -NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Hdacodec *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Hdacodec), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Hdacodec)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Hdacodec); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -327,16 +332,25 @@ NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_Hdacodec(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_Hdacodec_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Hdacodec_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Hdacodec)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_hda_codec_api_nvoc.h b/src/nvidia/generated/g_hda_codec_api_nvoc.h index 0fb4cc5c04..5e8da2e3c7 100644 --- a/src/nvidia/generated/g_hda_codec_api_nvoc.h +++ b/src/nvidia/generated/g_hda_codec_api_nvoc.h @@ -40,11 +40,16 @@ extern "C" { #include "ctrl/ctrl90ec.h" #include "gpu/gpu_resource.h" + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_HDA_CODEC_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Hdacodec { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -65,7 +70,6 @@ struct Hdacodec { NV_STATUS (*__hdacodecInternalControlForward__)(struct Hdacodec *, NvU32, void *, NvU32); NV_STATUS (*__hdacodecUnmapFrom__)(struct Hdacodec *, RS_RES_UNMAP_FROM_PARAMS *); void (*__hdacodecControl_Epilogue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__hdacodecControlLookup__)(struct Hdacodec *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__hdacodecGetInternalObjectHandle__)(struct Hdacodec *); NV_STATUS (*__hdacodecControl__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hdacodecUnmap__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -74,6 +78,7 @@ struct Hdacodec { NV_STATUS (*__hdacodecControlFilter__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hdacodecControlSerialization_Prologue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__hdacodecCanCopy__)(struct Hdacodec *); + NvBool (*__hdacodecIsPartialUnmapSupported__)(struct Hdacodec *); void (*__hdacodecPreDestruct__)(struct Hdacodec *); NV_STATUS (*__hdacodecIsDuplicate__)(struct Hdacodec *, NvHandle, NvBool *); void (*__hdacodecControlSerialization_Epilogue__)(struct Hdacodec *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -120,7 +125,6 @@ NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec**, Dynamic*, NvU32, struct CALL_CON #define hdacodecInternalControlForward(pGpuResource, command, pParams, size) hdacodecInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define hdacodecUnmapFrom(pResource, pParams) hdacodecUnmapFrom_DISPATCH(pResource, pParams) #define hdacodecControl_Epilogue(pResource, pCallContext, pParams) hdacodecControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define hdacodecControlLookup(pResource, pParams, ppEntry) hdacodecControlLookup_DISPATCH(pResource, pParams, ppEntry) #define hdacodecGetInternalObjectHandle(pGpuResource) hdacodecGetInternalObjectHandle_DISPATCH(pGpuResource) #define hdacodecControl(pGpuResource, pCallContext, pParams) hdacodecControl_DISPATCH(pGpuResource, pCallContext, pParams) #define hdacodecUnmap(pGpuResource, pCallContext, pCpuMapping) hdacodecUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -129,6 +133,7 @@ NV_STATUS __nvoc_objCreate_Hdacodec(Hdacodec**, Dynamic*, NvU32, struct CALL_CON #define hdacodecControlFilter(pResource, pCallContext, pParams) hdacodecControlFilter_DISPATCH(pResource, pCallContext, pParams) #define hdacodecControlSerialization_Prologue(pResource, pCallContext, pParams) hdacodecControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define hdacodecCanCopy(pResource) hdacodecCanCopy_DISPATCH(pResource) +#define hdacodecIsPartialUnmapSupported(pResource) hdacodecIsPartialUnmapSupported_DISPATCH(pResource) #define hdacodecPreDestruct(pResource) hdacodecPreDestruct_DISPATCH(pResource) #define hdacodecIsDuplicate(pResource, hMemory, pDuplicate) hdacodecIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define hdacodecControlSerialization_Epilogue(pResource, pCallContext, pParams) hdacodecControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -178,10 +183,6 @@ static inline void hdacodecControl_Epilogue_DISPATCH(struct Hdacodec *pResource, pResource->__hdacodecControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS hdacodecControlLookup_DISPATCH(struct Hdacodec *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__hdacodecControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle hdacodecGetInternalObjectHandle_DISPATCH(struct Hdacodec *pGpuResource) { return pGpuResource->__hdacodecGetInternalObjectHandle__(pGpuResource); } @@ -214,6 +215,10 @@ static inline NvBool hdacodecCanCopy_DISPATCH(struct Hdacodec *pResource) { return pResource->__hdacodecCanCopy__(pResource); } +static inline NvBool hdacodecIsPartialUnmapSupported_DISPATCH(struct Hdacodec *pResource) { + return pResource->__hdacodecIsPartialUnmapSupported__(pResource); +} + static inline void hdacodecPreDestruct_DISPATCH(struct Hdacodec *pResource) { pResource->__hdacodecPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_heap_nvoc.c b/src/nvidia/generated/g_heap_nvoc.c index bdd853d0c1..b187663f67 100644 --- a/src/nvidia/generated/g_heap_nvoc.c +++ b/src/nvidia/generated/g_heap_nvoc.c @@ -104,21 +104,26 @@ void __nvoc_init_Heap(Heap *pThis) { __nvoc_init_funcTable_Heap(pThis); } -NV_STATUS __nvoc_objCreate_Heap(Heap **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_Heap(Heap **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Heap *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Heap), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Heap)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Heap); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -133,16 +138,25 @@ NV_STATUS __nvoc_objCreate_Heap(Heap **ppThis, Dynamic *pParent, NvU32 createFla status = __nvoc_ctor_Heap(pThis); if (status != NV_OK) goto __nvoc_objCreate_Heap_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Heap_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Heap)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_heap_nvoc.h b/src/nvidia/generated/g_heap_nvoc.h index 2c7ad137a8..d213fd79ff 100644 --- a/src/nvidia/generated/g_heap_nvoc.h +++ b/src/nvidia/generated/g_heap_nvoc.h @@ -272,11 +272,16 @@ typedef struct #define SHUFFLE_STRIDE_MAX 5 + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_HEAP_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Heap { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_host_eng_nvoc.h b/src/nvidia/generated/g_host_eng_nvoc.h index 050909957a..6a440d163e 100644 --- a/src/nvidia/generated/g_host_eng_nvoc.h +++ b/src/nvidia/generated/g_host_eng_nvoc.h @@ -49,11 +49,16 @@ typedef struct OBJHOSTENG *POBJHOSTENG; /*! * Interface class for all Hosteng modules. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_HOST_ENG_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJHOSTENG { const struct NVOC_RTTI *__nvoc_rtti; struct OBJHOSTENG *__nvoc_pbase_OBJHOSTENG; diff --git a/src/nvidia/generated/g_hw_resources_nvoc.c b/src/nvidia/generated/g_hw_resources_nvoc.c index b634caa793..ceb609af4a 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.c +++ b/src/nvidia/generated/g_hw_resources_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_hwresControl_Epilogue(struct MemoryHwResourc rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_hwresControlLookup(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_hwresControl(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_hwresControlSerialization_Prologue(stru return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_hwresIsPartialUnmapSupported(struct MemoryHwResources *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryHwResources_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_hwresIsReady(struct MemoryHwResources *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryHwResources_Memory.offset), bCopyConstructorContext); } @@ -262,8 +262,6 @@ static void __nvoc_init_funcTable_MemoryHwResources_1(MemoryHwResources *pThis) pThis->__hwresControl_Epilogue__ = &__nvoc_thunk_RmResource_hwresControl_Epilogue; - pThis->__hwresControlLookup__ = &__nvoc_thunk_RsResource_hwresControlLookup; - pThis->__hwresControl__ = &__nvoc_thunk_Memory_hwresControl; pThis->__hwresUnmap__ = &__nvoc_thunk_Memory_hwresUnmap; @@ -276,6 +274,8 @@ static void __nvoc_init_funcTable_MemoryHwResources_1(MemoryHwResources *pThis) pThis->__hwresControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_hwresControlSerialization_Prologue; + pThis->__hwresIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_hwresIsPartialUnmapSupported; + pThis->__hwresIsReady__ = &__nvoc_thunk_Memory_hwresIsReady; pThis->__hwresCheckCopyPermissions__ = &__nvoc_thunk_Memory_hwresCheckCopyPermissions; @@ -307,21 +307,26 @@ void __nvoc_init_MemoryHwResources(MemoryHwResources *pThis) { __nvoc_init_funcTable_MemoryHwResources(pThis); } -NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MemoryHwResources *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryHwResources), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MemoryHwResources)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryHwResources); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -336,16 +341,25 @@ NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources **ppThis, Dynamic status = __nvoc_ctor_MemoryHwResources(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MemoryHwResources_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MemoryHwResources_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MemoryHwResources)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_hw_resources_nvoc.h b/src/nvidia/generated/g_hw_resources_nvoc.h index b8052b7fbe..a51213bcb3 100644 --- a/src/nvidia/generated/g_hw_resources_nvoc.h +++ b/src/nvidia/generated/g_hw_resources_nvoc.h @@ -39,11 +39,16 @@ extern "C" { /*! * Allocator for normal virtual, video and system memory */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_HW_RESOURCES_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MemoryHwResources { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -65,13 +70,13 @@ struct MemoryHwResources { NvBool (*__hwresIsGpuMapAllowed__)(struct MemoryHwResources *, struct OBJGPU *); NV_STATUS (*__hwresUnmapFrom__)(struct MemoryHwResources *, RS_RES_UNMAP_FROM_PARAMS *); void (*__hwresControl_Epilogue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__hwresControlLookup__)(struct MemoryHwResources *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__hwresControl__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresUnmap__)(struct MemoryHwResources *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__hwresGetMemInterMapParams__)(struct MemoryHwResources *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__hwresGetMemoryMappingDescriptor__)(struct MemoryHwResources *, MEMORY_DESCRIPTOR **); NV_STATUS (*__hwresControlFilter__)(struct MemoryHwResources *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__hwresControlSerialization_Prologue__)(struct MemoryHwResources *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__hwresIsPartialUnmapSupported__)(struct MemoryHwResources *); NV_STATUS (*__hwresIsReady__)(struct MemoryHwResources *, NvBool); NV_STATUS (*__hwresCheckCopyPermissions__)(struct MemoryHwResources *, struct OBJGPU *, struct Device *); void (*__hwresPreDestruct__)(struct MemoryHwResources *); @@ -121,13 +126,13 @@ NV_STATUS __nvoc_objCreate_MemoryHwResources(MemoryHwResources**, Dynamic*, NvU3 #define hwresIsGpuMapAllowed(pMemory, pGpu) hwresIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define hwresUnmapFrom(pResource, pParams) hwresUnmapFrom_DISPATCH(pResource, pParams) #define hwresControl_Epilogue(pResource, pCallContext, pParams) hwresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define hwresControlLookup(pResource, pParams, ppEntry) hwresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define hwresControl(pMemory, pCallContext, pParams) hwresControl_DISPATCH(pMemory, pCallContext, pParams) #define hwresUnmap(pMemory, pCallContext, pCpuMapping) hwresUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define hwresGetMemInterMapParams(pMemory, pParams) hwresGetMemInterMapParams_DISPATCH(pMemory, pParams) #define hwresGetMemoryMappingDescriptor(pMemory, ppMemDesc) hwresGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define hwresControlFilter(pResource, pCallContext, pParams) hwresControlFilter_DISPATCH(pResource, pCallContext, pParams) #define hwresControlSerialization_Prologue(pResource, pCallContext, pParams) hwresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define hwresIsPartialUnmapSupported(pResource) hwresIsPartialUnmapSupported_DISPATCH(pResource) #define hwresIsReady(pMemory, bCopyConstructorContext) hwresIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define hwresCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) hwresCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define hwresPreDestruct(pResource) hwresPreDestruct_DISPATCH(pResource) @@ -185,10 +190,6 @@ static inline void hwresControl_Epilogue_DISPATCH(struct MemoryHwResources *pRes pResource->__hwresControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS hwresControlLookup_DISPATCH(struct MemoryHwResources *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__hwresControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS hwresControl_DISPATCH(struct MemoryHwResources *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__hwresControl__(pMemory, pCallContext, pParams); } @@ -213,6 +214,10 @@ static inline NV_STATUS hwresControlSerialization_Prologue_DISPATCH(struct Memor return pResource->__hwresControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool hwresIsPartialUnmapSupported_DISPATCH(struct MemoryHwResources *pResource) { + return pResource->__hwresIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS hwresIsReady_DISPATCH(struct MemoryHwResources *pMemory, NvBool bCopyConstructorContext) { return pMemory->__hwresIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_hypervisor_nvoc.c b/src/nvidia/generated/g_hypervisor_nvoc.c index fe6c775d75..2ddfc57b60 100644 --- a/src/nvidia/generated/g_hypervisor_nvoc.c +++ b/src/nvidia/generated/g_hypervisor_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_OBJHYPERVISOR(OBJHYPERVISOR *pThis) { __nvoc_init_funcTable_OBJHYPERVISOR(pThis); } -NV_STATUS __nvoc_objCreate_OBJHYPERVISOR(OBJHYPERVISOR **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJHYPERVISOR(OBJHYPERVISOR **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJHYPERVISOR *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJHYPERVISOR), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJHYPERVISOR)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJHYPERVISOR); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_OBJHYPERVISOR(OBJHYPERVISOR **ppThis, Dynamic *pParen status = __nvoc_ctor_OBJHYPERVISOR(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJHYPERVISOR_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJHYPERVISOR_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJHYPERVISOR)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_hypervisor_nvoc.h b/src/nvidia/generated/g_hypervisor_nvoc.h index 5d66a5672e..c9b6c1e8f9 100644 --- a/src/nvidia/generated/g_hypervisor_nvoc.h +++ b/src/nvidia/generated/g_hypervisor_nvoc.h @@ -72,11 +72,16 @@ typedef struct OBJHYPERVISOR OBJHYPERVISOR; typedef struct HOST_VGPU_DEVICE HOST_VGPU_DEVICE; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_HYPERVISOR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJHYPERVISOR { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -88,7 +93,6 @@ struct OBJHYPERVISOR { HYPERVISOR_TYPE type; NvBool bIsHypervHost; NvBool bIsHypervVgpuSupported; - NvBool bIsACSupported; }; #ifndef __NVOC_CLASS_OBJHYPERVISOR_TYPEDEF__ @@ -154,25 +158,6 @@ static inline void hypervisorSetHypervVgpuSupported(struct OBJHYPERVISOR *arg0) #define hypervisorSetHypervVgpuSupported_HAL(arg0) hypervisorSetHypervVgpuSupported(arg0) -NvBool hypervisorIsAC_IMPL(void); - - -#define hypervisorIsAC() hypervisorIsAC_IMPL() -#define hypervisorIsAC_HAL() hypervisorIsAC() - -void hypervisorSetACSupported_IMPL(struct OBJHYPERVISOR *arg0); - - -#ifdef __nvoc_hypervisor_h_disabled -static inline void hypervisorSetACSupported(struct OBJHYPERVISOR *arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJHYPERVISOR was disabled!"); -} -#else //__nvoc_hypervisor_h_disabled -#define hypervisorSetACSupported(arg0) hypervisorSetACSupported_IMPL(arg0) -#endif //__nvoc_hypervisor_h_disabled - -#define hypervisorSetACSupported_HAL(arg0) hypervisorSetACSupported(arg0) - NvBool hypervisorCheckForObjectAccess_IMPL(NvHandle hClient); #define hypervisorCheckForObjectAccess(hClient) hypervisorCheckForObjectAccess_IMPL(hClient) diff --git a/src/nvidia/generated/g_i2c_api_nvoc.c b/src/nvidia/generated/g_i2c_api_nvoc.c index f91095630e..b37a782863 100644 --- a/src/nvidia/generated/g_i2c_api_nvoc.c +++ b/src/nvidia/generated/g_i2c_api_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_i2capiControl_Epilogue(struct I2cApi *pResou rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_i2capiControlLookup(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle(struct I2cApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_I2cApi_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_i2capiCanCopy(struct I2cApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_i2capiIsPartialUnmapSupported(struct I2cApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_i2capiPreDestruct(struct I2cApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_I2cApi_RsResource.offset)); } @@ -358,8 +358,6 @@ static void __nvoc_init_funcTable_I2cApi_1(I2cApi *pThis) { pThis->__i2capiControl_Epilogue__ = &__nvoc_thunk_RmResource_i2capiControl_Epilogue; - pThis->__i2capiControlLookup__ = &__nvoc_thunk_RsResource_i2capiControlLookup; - pThis->__i2capiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_i2capiGetInternalObjectHandle; pThis->__i2capiControl__ = &__nvoc_thunk_GpuResource_i2capiControl; @@ -376,6 +374,8 @@ static void __nvoc_init_funcTable_I2cApi_1(I2cApi *pThis) { pThis->__i2capiCanCopy__ = &__nvoc_thunk_RsResource_i2capiCanCopy; + pThis->__i2capiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_i2capiIsPartialUnmapSupported; + pThis->__i2capiPreDestruct__ = &__nvoc_thunk_RsResource_i2capiPreDestruct; pThis->__i2capiIsDuplicate__ = &__nvoc_thunk_RsResource_i2capiIsDuplicate; @@ -403,21 +403,26 @@ void __nvoc_init_I2cApi(I2cApi *pThis) { __nvoc_init_funcTable_I2cApi(pThis); } -NV_STATUS __nvoc_objCreate_I2cApi(I2cApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_I2cApi(I2cApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; I2cApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(I2cApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(I2cApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_I2cApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -432,16 +437,25 @@ NV_STATUS __nvoc_objCreate_I2cApi(I2cApi **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_I2cApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_I2cApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_I2cApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(I2cApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_i2c_api_nvoc.h b/src/nvidia/generated/g_i2c_api_nvoc.h index 23f546cef8..8bbd35eb5d 100644 --- a/src/nvidia/generated/g_i2c_api_nvoc.h +++ b/src/nvidia/generated/g_i2c_api_nvoc.h @@ -41,11 +41,16 @@ extern "C" { /*! * RM internal class representing NV40_I2C (child of SubDevice) */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_I2C_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct I2cApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -71,7 +76,6 @@ struct I2cApi { NV_STATUS (*__i2capiInternalControlForward__)(struct I2cApi *, NvU32, void *, NvU32); NV_STATUS (*__i2capiUnmapFrom__)(struct I2cApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__i2capiControl_Epilogue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__i2capiControlLookup__)(struct I2cApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__i2capiGetInternalObjectHandle__)(struct I2cApi *); NV_STATUS (*__i2capiControl__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__i2capiUnmap__)(struct I2cApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -80,6 +84,7 @@ struct I2cApi { NV_STATUS (*__i2capiControlFilter__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__i2capiControlSerialization_Prologue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__i2capiCanCopy__)(struct I2cApi *); + NvBool (*__i2capiIsPartialUnmapSupported__)(struct I2cApi *); void (*__i2capiPreDestruct__)(struct I2cApi *); NV_STATUS (*__i2capiIsDuplicate__)(struct I2cApi *, NvHandle, NvBool *); void (*__i2capiControlSerialization_Epilogue__)(struct I2cApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -131,7 +136,6 @@ NV_STATUS __nvoc_objCreate_I2cApi(I2cApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define i2capiInternalControlForward(pGpuResource, command, pParams, size) i2capiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define i2capiUnmapFrom(pResource, pParams) i2capiUnmapFrom_DISPATCH(pResource, pParams) #define i2capiControl_Epilogue(pResource, pCallContext, pParams) i2capiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define i2capiControlLookup(pResource, pParams, ppEntry) i2capiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define i2capiGetInternalObjectHandle(pGpuResource) i2capiGetInternalObjectHandle_DISPATCH(pGpuResource) #define i2capiControl(pGpuResource, pCallContext, pParams) i2capiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define i2capiUnmap(pGpuResource, pCallContext, pCpuMapping) i2capiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -140,6 +144,7 @@ NV_STATUS __nvoc_objCreate_I2cApi(I2cApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define i2capiControlFilter(pResource, pCallContext, pParams) i2capiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define i2capiControlSerialization_Prologue(pResource, pCallContext, pParams) i2capiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define i2capiCanCopy(pResource) i2capiCanCopy_DISPATCH(pResource) +#define i2capiIsPartialUnmapSupported(pResource) i2capiIsPartialUnmapSupported_DISPATCH(pResource) #define i2capiPreDestruct(pResource) i2capiPreDestruct_DISPATCH(pResource) #define i2capiIsDuplicate(pResource, hMemory, pDuplicate) i2capiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define i2capiControlSerialization_Epilogue(pResource, pCallContext, pParams) i2capiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -219,10 +224,6 @@ static inline void i2capiControl_Epilogue_DISPATCH(struct I2cApi *pResource, str pResource->__i2capiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS i2capiControlLookup_DISPATCH(struct I2cApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__i2capiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle i2capiGetInternalObjectHandle_DISPATCH(struct I2cApi *pGpuResource) { return pGpuResource->__i2capiGetInternalObjectHandle__(pGpuResource); } @@ -255,6 +256,10 @@ static inline NvBool i2capiCanCopy_DISPATCH(struct I2cApi *pResource) { return pResource->__i2capiCanCopy__(pResource); } +static inline NvBool i2capiIsPartialUnmapSupported_DISPATCH(struct I2cApi *pResource) { + return pResource->__i2capiIsPartialUnmapSupported__(pResource); +} + static inline void i2capiPreDestruct_DISPATCH(struct I2cApi *pResource) { pResource->__i2capiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_imex_session_api_nvoc.c b/src/nvidia/generated/g_imex_session_api_nvoc.c new file mode 100644 index 0000000000..f455bdb9aa --- /dev/null +++ b/src/nvidia/generated/g_imex_session_api_nvoc.c @@ -0,0 +1,401 @@ +#define NVOC_IMEX_SESSION_API_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_imex_session_api_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xb4748b = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ImexSessionApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +void __nvoc_init_ImexSessionApi(ImexSessionApi*); +void __nvoc_init_funcTable_ImexSessionApi(ImexSessionApi*); +NV_STATUS __nvoc_ctor_ImexSessionApi(ImexSessionApi*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_ImexSessionApi(ImexSessionApi*); +void __nvoc_dtor_ImexSessionApi(ImexSessionApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ImexSessionApi; + +static const struct NVOC_RTTI __nvoc_rtti_ImexSessionApi_ImexSessionApi = { + /*pClassDef=*/ &__nvoc_class_def_ImexSessionApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_ImexSessionApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_ImexSessionApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ImexSessionApi, __nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ImexSessionApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ImexSessionApi, __nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ImexSessionApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ImexSessionApi, __nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_ImexSessionApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(ImexSessionApi, __nvoc_base_RmResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_ImexSessionApi = { + /*numRelatives=*/ 5, + /*relatives=*/ { + &__nvoc_rtti_ImexSessionApi_ImexSessionApi, + &__nvoc_rtti_ImexSessionApi_RmResource, + &__nvoc_rtti_ImexSessionApi_RmResourceCommon, + &__nvoc_rtti_ImexSessionApi_RsResource, + &__nvoc_rtti_ImexSessionApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_ImexSessionApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(ImexSessionApi), + /*classId=*/ classId(ImexSessionApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "ImexSessionApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_ImexSessionApi, + /*pCastInfo=*/ &__nvoc_castinfo_ImexSessionApi, + /*pExportInfo=*/ &__nvoc_export_info_ImexSessionApi +}; + +static NvBool __nvoc_thunk_RmResource_imexsessionapiShareCallback(struct ImexSessionApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_imexsessionapiCheckMemInterUnmap(struct ImexSessionApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_imexsessionapiControl(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_imexsessionapiGetMemInterMapParams(struct ImexSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_imexsessionapiGetMemoryMappingDescriptor(struct ImexSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), ppMemDesc); +} + +static NvU32 __nvoc_thunk_RsResource_imexsessionapiGetRefCount(struct ImexSessionApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_imexsessionapiControlFilter(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_imexsessionapiAddAdditionalDependants(struct RsClient *pClient, struct ImexSessionApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_imexsessionapiControlSerialization_Prologue(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_imexsessionapiControl_Prologue(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_imexsessionapiCanCopy(struct ImexSessionApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_imexsessionapiUnmap(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset), pCallContext, pCpuMapping); +} + +static NvBool __nvoc_thunk_RsResource_imexsessionapiIsPartialUnmapSupported(struct ImexSessionApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_imexsessionapiPreDestruct(struct ImexSessionApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_imexsessionapiMapTo(struct ImexSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_imexsessionapiIsDuplicate(struct ImexSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_imexsessionapiControlSerialization_Epilogue(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmResource_imexsessionapiControl_Epilogue(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_imexsessionapiUnmapFrom(struct ImexSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_imexsessionapiMap(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RsResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_imexsessionapiAccessCallback(struct ImexSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ImexSessionApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_ImexSessionApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) imexsessionapiCtrlCmdGetFabricEvents_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf10001u, + /*paramSize=*/ sizeof(NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ImexSessionApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "imexsessionapiCtrlCmdGetFabricEvents" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) imexsessionapiCtrlCmdFinishMemUnimport_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf10002u, + /*paramSize=*/ sizeof(NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ImexSessionApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "imexsessionapiCtrlCmdFinishMemUnimport" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) imexsessionapiCtrlCmdDisableImporters_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf10003u, + /*paramSize=*/ sizeof(NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ImexSessionApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "imexsessionapiCtrlCmdDisableImporters" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_ImexSessionApi = +{ + /*numEntries=*/ 3, + /*pExportEntries=*/ __nvoc_exported_method_def_ImexSessionApi +}; + +void __nvoc_dtor_RmResource(RmResource*); +void __nvoc_dtor_ImexSessionApi(ImexSessionApi *pThis) { + __nvoc_imexsessionapiDestruct(pThis); + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_ImexSessionApi(ImexSessionApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RmResource(RmResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_ImexSessionApi(ImexSessionApi *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_RmResource(&pThis->__nvoc_base_RmResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ImexSessionApi_fail_RmResource; + __nvoc_init_dataField_ImexSessionApi(pThis); + + status = __nvoc_imexsessionapiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_ImexSessionApi_fail__init; + goto __nvoc_ctor_ImexSessionApi_exit; // Success + +__nvoc_ctor_ImexSessionApi_fail__init: + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); +__nvoc_ctor_ImexSessionApi_fail_RmResource: +__nvoc_ctor_ImexSessionApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_ImexSessionApi_1(ImexSessionApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__imexsessionapiCtrlCmdGetFabricEvents__ = &imexsessionapiCtrlCmdGetFabricEvents_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__imexsessionapiCtrlCmdFinishMemUnimport__ = &imexsessionapiCtrlCmdFinishMemUnimport_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__imexsessionapiCtrlCmdDisableImporters__ = &imexsessionapiCtrlCmdDisableImporters_IMPL; +#endif + + pThis->__imexsessionapiShareCallback__ = &__nvoc_thunk_RmResource_imexsessionapiShareCallback; + + pThis->__imexsessionapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_imexsessionapiCheckMemInterUnmap; + + pThis->__imexsessionapiControl__ = &__nvoc_thunk_RsResource_imexsessionapiControl; + + pThis->__imexsessionapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_imexsessionapiGetMemInterMapParams; + + pThis->__imexsessionapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_imexsessionapiGetMemoryMappingDescriptor; + + pThis->__imexsessionapiGetRefCount__ = &__nvoc_thunk_RsResource_imexsessionapiGetRefCount; + + pThis->__imexsessionapiControlFilter__ = &__nvoc_thunk_RsResource_imexsessionapiControlFilter; + + pThis->__imexsessionapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_imexsessionapiAddAdditionalDependants; + + pThis->__imexsessionapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_imexsessionapiControlSerialization_Prologue; + + pThis->__imexsessionapiControl_Prologue__ = &__nvoc_thunk_RmResource_imexsessionapiControl_Prologue; + + pThis->__imexsessionapiCanCopy__ = &__nvoc_thunk_RsResource_imexsessionapiCanCopy; + + pThis->__imexsessionapiUnmap__ = &__nvoc_thunk_RsResource_imexsessionapiUnmap; + + pThis->__imexsessionapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_imexsessionapiIsPartialUnmapSupported; + + pThis->__imexsessionapiPreDestruct__ = &__nvoc_thunk_RsResource_imexsessionapiPreDestruct; + + pThis->__imexsessionapiMapTo__ = &__nvoc_thunk_RsResource_imexsessionapiMapTo; + + pThis->__imexsessionapiIsDuplicate__ = &__nvoc_thunk_RsResource_imexsessionapiIsDuplicate; + + pThis->__imexsessionapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_imexsessionapiControlSerialization_Epilogue; + + pThis->__imexsessionapiControl_Epilogue__ = &__nvoc_thunk_RmResource_imexsessionapiControl_Epilogue; + + pThis->__imexsessionapiUnmapFrom__ = &__nvoc_thunk_RsResource_imexsessionapiUnmapFrom; + + pThis->__imexsessionapiMap__ = &__nvoc_thunk_RsResource_imexsessionapiMap; + + pThis->__imexsessionapiAccessCallback__ = &__nvoc_thunk_RmResource_imexsessionapiAccessCallback; +} + +void __nvoc_init_funcTable_ImexSessionApi(ImexSessionApi *pThis) { + __nvoc_init_funcTable_ImexSessionApi_1(pThis); +} + +void __nvoc_init_RmResource(RmResource*); +void __nvoc_init_ImexSessionApi(ImexSessionApi *pThis) { + pThis->__nvoc_pbase_ImexSessionApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_RmResource; + __nvoc_init_RmResource(&pThis->__nvoc_base_RmResource); + __nvoc_init_funcTable_ImexSessionApi(pThis); +} + +NV_STATUS __nvoc_objCreate_ImexSessionApi(ImexSessionApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ + NV_STATUS status; + Object *pParentObj = NULL; + ImexSessionApi *pThis; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ImexSessionApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(ImexSessionApi)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ImexSessionApi); + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + // Link the child into the parent if there is one unless flagged not to do so. + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_ImexSessionApi(pThis); + status = __nvoc_ctor_ImexSessionApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_ImexSessionApi_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_ImexSessionApi_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(ImexSessionApi)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_ImexSessionApi(ImexSessionApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_ImexSessionApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_imex_session_api_nvoc.h b/src/nvidia/generated/g_imex_session_api_nvoc.h new file mode 100644 index 0000000000..fc1f8b1137 --- /dev/null +++ b/src/nvidia/generated/g_imex_session_api_nvoc.h @@ -0,0 +1,283 @@ +#ifndef _G_IMEX_SESSION_API_NVOC_H_ +#define _G_IMEX_SESSION_API_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions managing the IMEX session + * + *****************************************************************************/ + +#include "g_imex_session_api_nvoc.h" + +#ifndef IMEX_SESSION_API_H +#define IMEX_SESSION_API_H + +#include "rmapi/resource.h" + +#include "ctrl/ctrl00f1.h" + +// **************************************************************************** +// Type Definitions +// **************************************************************************** + +// +// IMEX session information +// +// A client which owns ImexSessionApi is identified as IMEX daemon in RM land. +// The privileged daemon manages (IMport/EXport) RM resources such as memory, +// across the nodes, in multinode systems. +// +// Key attributes of ImexSessionApi class: +// - There can be only one instance of ImexSessionApi system-wide. This ensures that +// there is only one IMEX daemon running in the node exclusively. +// - hClient is parent of ImexSessionApi. +// - Only privileged user be allowed to allocate ImexSessionApi. +// - RmApi lock must be held. This class should not communicate with a GPU. +// + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_IMEX_SESSION_API_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif + +struct ImexSessionApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct RmResource __nvoc_base_RmResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct ImexSessionApi *__nvoc_pbase_ImexSessionApi; + NV_STATUS (*__imexsessionapiCtrlCmdGetFabricEvents__)(struct ImexSessionApi *, NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS *); + NV_STATUS (*__imexsessionapiCtrlCmdFinishMemUnimport__)(struct ImexSessionApi *, NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS *); + NV_STATUS (*__imexsessionapiCtrlCmdDisableImporters__)(struct ImexSessionApi *, NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS *); + NvBool (*__imexsessionapiShareCallback__)(struct ImexSessionApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__imexsessionapiCheckMemInterUnmap__)(struct ImexSessionApi *, NvBool); + NV_STATUS (*__imexsessionapiControl__)(struct ImexSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__imexsessionapiGetMemInterMapParams__)(struct ImexSessionApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__imexsessionapiGetMemoryMappingDescriptor__)(struct ImexSessionApi *, struct MEMORY_DESCRIPTOR **); + NvU32 (*__imexsessionapiGetRefCount__)(struct ImexSessionApi *); + NV_STATUS (*__imexsessionapiControlFilter__)(struct ImexSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__imexsessionapiAddAdditionalDependants__)(struct RsClient *, struct ImexSessionApi *, RsResourceRef *); + NV_STATUS (*__imexsessionapiControlSerialization_Prologue__)(struct ImexSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__imexsessionapiControl_Prologue__)(struct ImexSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__imexsessionapiCanCopy__)(struct ImexSessionApi *); + NV_STATUS (*__imexsessionapiUnmap__)(struct ImexSessionApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__imexsessionapiIsPartialUnmapSupported__)(struct ImexSessionApi *); + void (*__imexsessionapiPreDestruct__)(struct ImexSessionApi *); + NV_STATUS (*__imexsessionapiMapTo__)(struct ImexSessionApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__imexsessionapiIsDuplicate__)(struct ImexSessionApi *, NvHandle, NvBool *); + void (*__imexsessionapiControlSerialization_Epilogue__)(struct ImexSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__imexsessionapiControl_Epilogue__)(struct ImexSessionApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__imexsessionapiUnmapFrom__)(struct ImexSessionApi *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__imexsessionapiMap__)(struct ImexSessionApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__imexsessionapiAccessCallback__)(struct ImexSessionApi *, struct RsClient *, void *, RsAccessRight); + NvU64 dupedCapDescriptor; + NvU32 PRIVATE_FIELD(flags); +}; + +#ifndef __NVOC_CLASS_ImexSessionApi_TYPEDEF__ +#define __NVOC_CLASS_ImexSessionApi_TYPEDEF__ +typedef struct ImexSessionApi ImexSessionApi; +#endif /* __NVOC_CLASS_ImexSessionApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ImexSessionApi +#define __nvoc_class_id_ImexSessionApi 0xb4748b +#endif /* __nvoc_class_id_ImexSessionApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_ImexSessionApi; + +#define __staticCast_ImexSessionApi(pThis) \ + ((pThis)->__nvoc_pbase_ImexSessionApi) + +#ifdef __nvoc_imex_session_api_h_disabled +#define __dynamicCast_ImexSessionApi(pThis) ((ImexSessionApi*)NULL) +#else //__nvoc_imex_session_api_h_disabled +#define __dynamicCast_ImexSessionApi(pThis) \ + ((ImexSessionApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(ImexSessionApi))) +#endif //__nvoc_imex_session_api_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_ImexSessionApi(ImexSessionApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_ImexSessionApi(ImexSessionApi**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_ImexSessionApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_ImexSessionApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define imexsessionapiCtrlCmdGetFabricEvents(pImexSessionApi, pParams) imexsessionapiCtrlCmdGetFabricEvents_DISPATCH(pImexSessionApi, pParams) +#define imexsessionapiCtrlCmdFinishMemUnimport(pImexSessionApi, pParams) imexsessionapiCtrlCmdFinishMemUnimport_DISPATCH(pImexSessionApi, pParams) +#define imexsessionapiCtrlCmdDisableImporters(pImexSessionApi, pParams) imexsessionapiCtrlCmdDisableImporters_DISPATCH(pImexSessionApi, pParams) +#define imexsessionapiShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) imexsessionapiShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define imexsessionapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) imexsessionapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define imexsessionapiControl(pResource, pCallContext, pParams) imexsessionapiControl_DISPATCH(pResource, pCallContext, pParams) +#define imexsessionapiGetMemInterMapParams(pRmResource, pParams) imexsessionapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define imexsessionapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) imexsessionapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define imexsessionapiGetRefCount(pResource) imexsessionapiGetRefCount_DISPATCH(pResource) +#define imexsessionapiControlFilter(pResource, pCallContext, pParams) imexsessionapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define imexsessionapiAddAdditionalDependants(pClient, pResource, pReference) imexsessionapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define imexsessionapiControlSerialization_Prologue(pResource, pCallContext, pParams) imexsessionapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define imexsessionapiControl_Prologue(pResource, pCallContext, pParams) imexsessionapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define imexsessionapiCanCopy(pResource) imexsessionapiCanCopy_DISPATCH(pResource) +#define imexsessionapiUnmap(pResource, pCallContext, pCpuMapping) imexsessionapiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define imexsessionapiIsPartialUnmapSupported(pResource) imexsessionapiIsPartialUnmapSupported_DISPATCH(pResource) +#define imexsessionapiPreDestruct(pResource) imexsessionapiPreDestruct_DISPATCH(pResource) +#define imexsessionapiMapTo(pResource, pParams) imexsessionapiMapTo_DISPATCH(pResource, pParams) +#define imexsessionapiIsDuplicate(pResource, hMemory, pDuplicate) imexsessionapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define imexsessionapiControlSerialization_Epilogue(pResource, pCallContext, pParams) imexsessionapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define imexsessionapiControl_Epilogue(pResource, pCallContext, pParams) imexsessionapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define imexsessionapiUnmapFrom(pResource, pParams) imexsessionapiUnmapFrom_DISPATCH(pResource, pParams) +#define imexsessionapiMap(pResource, pCallContext, pParams, pCpuMapping) imexsessionapiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) +#define imexsessionapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) imexsessionapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS imexsessionapiCtrlCmdGetFabricEvents_IMPL(struct ImexSessionApi *pImexSessionApi, NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS *pParams); + +static inline NV_STATUS imexsessionapiCtrlCmdGetFabricEvents_DISPATCH(struct ImexSessionApi *pImexSessionApi, NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS *pParams) { + return pImexSessionApi->__imexsessionapiCtrlCmdGetFabricEvents__(pImexSessionApi, pParams); +} + +NV_STATUS imexsessionapiCtrlCmdFinishMemUnimport_IMPL(struct ImexSessionApi *pImexSessionApi, NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS *pParams); + +static inline NV_STATUS imexsessionapiCtrlCmdFinishMemUnimport_DISPATCH(struct ImexSessionApi *pImexSessionApi, NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS *pParams) { + return pImexSessionApi->__imexsessionapiCtrlCmdFinishMemUnimport__(pImexSessionApi, pParams); +} + +NV_STATUS imexsessionapiCtrlCmdDisableImporters_IMPL(struct ImexSessionApi *pImexSessionApi, NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS *pParams); + +static inline NV_STATUS imexsessionapiCtrlCmdDisableImporters_DISPATCH(struct ImexSessionApi *pImexSessionApi, NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS *pParams) { + return pImexSessionApi->__imexsessionapiCtrlCmdDisableImporters__(pImexSessionApi, pParams); +} + +static inline NvBool imexsessionapiShareCallback_DISPATCH(struct ImexSessionApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__imexsessionapiShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS imexsessionapiCheckMemInterUnmap_DISPATCH(struct ImexSessionApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__imexsessionapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS imexsessionapiControl_DISPATCH(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__imexsessionapiControl__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS imexsessionapiGetMemInterMapParams_DISPATCH(struct ImexSessionApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__imexsessionapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS imexsessionapiGetMemoryMappingDescriptor_DISPATCH(struct ImexSessionApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__imexsessionapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NvU32 imexsessionapiGetRefCount_DISPATCH(struct ImexSessionApi *pResource) { + return pResource->__imexsessionapiGetRefCount__(pResource); +} + +static inline NV_STATUS imexsessionapiControlFilter_DISPATCH(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__imexsessionapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline void imexsessionapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct ImexSessionApi *pResource, RsResourceRef *pReference) { + pResource->__imexsessionapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS imexsessionapiControlSerialization_Prologue_DISPATCH(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__imexsessionapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS imexsessionapiControl_Prologue_DISPATCH(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__imexsessionapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool imexsessionapiCanCopy_DISPATCH(struct ImexSessionApi *pResource) { + return pResource->__imexsessionapiCanCopy__(pResource); +} + +static inline NV_STATUS imexsessionapiUnmap_DISPATCH(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__imexsessionapiUnmap__(pResource, pCallContext, pCpuMapping); +} + +static inline NvBool imexsessionapiIsPartialUnmapSupported_DISPATCH(struct ImexSessionApi *pResource) { + return pResource->__imexsessionapiIsPartialUnmapSupported__(pResource); +} + +static inline void imexsessionapiPreDestruct_DISPATCH(struct ImexSessionApi *pResource) { + pResource->__imexsessionapiPreDestruct__(pResource); +} + +static inline NV_STATUS imexsessionapiMapTo_DISPATCH(struct ImexSessionApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__imexsessionapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS imexsessionapiIsDuplicate_DISPATCH(struct ImexSessionApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__imexsessionapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void imexsessionapiControlSerialization_Epilogue_DISPATCH(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__imexsessionapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline void imexsessionapiControl_Epilogue_DISPATCH(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__imexsessionapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS imexsessionapiUnmapFrom_DISPATCH(struct ImexSessionApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__imexsessionapiUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS imexsessionapiMap_DISPATCH(struct ImexSessionApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pResource->__imexsessionapiMap__(pResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool imexsessionapiAccessCallback_DISPATCH(struct ImexSessionApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__imexsessionapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS imexsessionapiConstruct_IMPL(struct ImexSessionApi *arg_pImexSessionApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_imexsessionapiConstruct(arg_pImexSessionApi, arg_pCallContext, arg_pParams) imexsessionapiConstruct_IMPL(arg_pImexSessionApi, arg_pCallContext, arg_pParams) +void imexsessionapiDestruct_IMPL(struct ImexSessionApi *pImexSessionApi); + +#define __nvoc_imexsessionapiDestruct(pImexSessionApi) imexsessionapiDestruct_IMPL(pImexSessionApi) +#undef PRIVATE_FIELD + + +void rcAndDisableOutstandingClientsWithImportedMemory(OBJGPU *pGpu, NvU16 nodeId); + +#endif // IMEX_SESSION_API_H + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_IMEX_SESSION_API_NVOC_H_ diff --git a/src/nvidia/generated/g_intr_nvoc.c b/src/nvidia/generated/g_intr_nvoc.c index c756e72338..edc76e781b 100644 --- a/src/nvidia/generated/g_intr_nvoc.c +++ b/src/nvidia/generated/g_intr_nvoc.c @@ -249,14 +249,24 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec pThis->__intrDecodeStallIntrEn__ = &intrDecodeStallIntrEn_4a4dee; } - // Hal function -- intrGetNonStallBaseVector - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + // Hal function -- intrServiceVirtual + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__intrServiceVirtual__ = &intrServiceVirtual_f2d351; + } + else + { + pThis->__intrServiceVirtual__ = &intrServiceVirtual_TU102; + } + + // Hal function -- intrTriggerPrivDoorbell + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_TU102; + pThis->__intrTriggerPrivDoorbell__ = &intrTriggerPrivDoorbell_5baef9; } else { - pThis->__intrGetNonStallBaseVector__ = &intrGetNonStallBaseVector_c067f9; + pThis->__intrTriggerPrivDoorbell__ = &intrTriggerPrivDoorbell_TU102; } // Hal function -- intrGetUvmSharedLeafEnDisableMask @@ -283,31 +293,31 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec // Hal function -- intrReadRegTopEnSet if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_TU102; + pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_CPU_TU102; } else { - pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_GA102; + pThis->__intrReadRegTopEnSet__ = &intrReadRegTopEnSet_CPU_GA102; } // Hal function -- intrWriteRegTopEnSet if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_TU102; + pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_CPU_TU102; } else { - pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_GA102; + pThis->__intrWriteRegTopEnSet__ = &intrWriteRegTopEnSet_CPU_GA102; } // Hal function -- intrWriteRegTopEnClear if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ { - pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_TU102; + pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_CPU_TU102; } else { - pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_GA102; + pThis->__intrWriteRegTopEnClear__ = &intrWriteRegTopEnClear_CPU_GA102; } // Hal function -- intrGetNumLeaves @@ -376,6 +386,33 @@ static void __nvoc_init_funcTable_Intr_1(Intr *pThis, RmHalspecOwner *pRmhalspec // Hal function -- intrStateUnload pThis->__intrStateUnload__ = &intrStateUnload_TU102; + // Hal function -- intrInitSubtreeMap + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ && (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ )) + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__intrInitSubtreeMap__ = &intrInitSubtreeMap_GH100; + } + else + { + pThis->__intrInitSubtreeMap__ = &intrInitSubtreeMap_TU102; + } + } + else + { + pThis->__intrInitSubtreeMap__ = &intrInitSubtreeMap_395e98; + } + + // Hal function -- intrInitInterruptTable + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__intrInitInterruptTable__ = &intrInitInterruptTable_VIRTUAL; + } + else + { + pThis->__intrInitInterruptTable__ = &intrInitInterruptTable_KERNEL; + } + // Hal function -- intrSetIntrMask if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -448,23 +485,31 @@ void __nvoc_init_Intr(Intr *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_Intr(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Intr *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Intr), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Intr)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Intr); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -482,16 +527,25 @@ NV_STATUS __nvoc_objCreate_Intr(Intr **ppThis, Dynamic *pParent, NvU32 createFla status = __nvoc_ctor_Intr(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_Intr_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Intr_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Intr)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_intr_nvoc.h b/src/nvidia/generated/g_intr_nvoc.h index 9acb41e1c3..5a9a48f05b 100644 --- a/src/nvidia/generated/g_intr_nvoc.h +++ b/src/nvidia/generated/g_intr_nvoc.h @@ -255,11 +255,16 @@ typedef struct Device Device; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_INTR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Intr { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -271,7 +276,8 @@ struct Intr { NV_STATUS (*__intrStateInitLocked__)(OBJGPU *, struct Intr *); void (*__intrStateDestroy__)(OBJGPU *, struct Intr *); NvU32 (*__intrDecodeStallIntrEn__)(OBJGPU *, struct Intr *, NvU32); - NvU32 (*__intrGetNonStallBaseVector__)(OBJGPU *, struct Intr *); + void (*__intrServiceVirtual__)(OBJGPU *, struct Intr *); + NV_STATUS (*__intrTriggerPrivDoorbell__)(OBJGPU *, struct Intr *, NvU32); NvU64 (*__intrGetUvmSharedLeafEnDisableMask__)(OBJGPU *, struct Intr *); void (*__intrSetDisplayInterruptEnable__)(OBJGPU *, struct Intr *, NvBool, struct THREAD_STATE_NODE *); NvU32 (*__intrReadRegTopEnSet__)(OBJGPU *, struct Intr *, NvU32, struct THREAD_STATE_NODE *); @@ -284,6 +290,8 @@ struct Intr { void (*__intrSanityCheckEngineIntrNotificationVector__)(OBJGPU *, struct Intr *, NvU32, NvU16); NV_STATUS (*__intrStateLoad__)(OBJGPU *, struct Intr *, NvU32); NV_STATUS (*__intrStateUnload__)(OBJGPU *, struct Intr *, NvU32); + NV_STATUS (*__intrInitSubtreeMap__)(OBJGPU *, struct Intr *); + NV_STATUS (*__intrInitInterruptTable__)(OBJGPU *, struct Intr *); NV_STATUS (*__intrSetIntrMask__)(OBJGPU *, struct Intr *, union MC_ENGINE_BITVECTOR *, struct THREAD_STATE_NODE *); void (*__intrSetIntrEnInHw__)(OBJGPU *, struct Intr *, NvU32, struct THREAD_STATE_NODE *); NvU32 (*__intrGetIntrEnFromHw__)(OBJGPU *, struct Intr *, struct THREAD_STATE_NODE *); @@ -311,7 +319,7 @@ struct Intr { NvU32 displayIntrVector; NvU64 intrTopEnMask; InterruptTable intrTable; - IntrServiceRecord intrServiceTable[168]; + IntrServiceRecord intrServiceTable[171]; InterruptEntry *(vectorToMcIdx[1]); NvLength vectorToMcIdxCounts[1]; NvBool bDefaultNonstallNotify; @@ -384,8 +392,10 @@ NV_STATUS __nvoc_objCreate_Intr(Intr**, Dynamic*, NvU32); #define intrStateDestroy(pGpu, pIntr) intrStateDestroy_DISPATCH(pGpu, pIntr) #define intrDecodeStallIntrEn(pGpu, pIntr, arg0) intrDecodeStallIntrEn_DISPATCH(pGpu, pIntr, arg0) #define intrDecodeStallIntrEn_HAL(pGpu, pIntr, arg0) intrDecodeStallIntrEn_DISPATCH(pGpu, pIntr, arg0) -#define intrGetNonStallBaseVector(pGpu, pIntr) intrGetNonStallBaseVector_DISPATCH(pGpu, pIntr) -#define intrGetNonStallBaseVector_HAL(pGpu, pIntr) intrGetNonStallBaseVector_DISPATCH(pGpu, pIntr) +#define intrServiceVirtual(pGpu, pIntr) intrServiceVirtual_DISPATCH(pGpu, pIntr) +#define intrServiceVirtual_HAL(pGpu, pIntr) intrServiceVirtual_DISPATCH(pGpu, pIntr) +#define intrTriggerPrivDoorbell(pGpu, pIntr, gfid) intrTriggerPrivDoorbell_DISPATCH(pGpu, pIntr, gfid) +#define intrTriggerPrivDoorbell_HAL(pGpu, pIntr, gfid) intrTriggerPrivDoorbell_DISPATCH(pGpu, pIntr, gfid) #define intrGetUvmSharedLeafEnDisableMask(pGpu, pIntr) intrGetUvmSharedLeafEnDisableMask_DISPATCH(pGpu, pIntr) #define intrGetUvmSharedLeafEnDisableMask_HAL(pGpu, pIntr) intrGetUvmSharedLeafEnDisableMask_DISPATCH(pGpu, pIntr) #define intrSetDisplayInterruptEnable(pGpu, pIntr, bEnable, pThreadState) intrSetDisplayInterruptEnable_DISPATCH(pGpu, pIntr, bEnable, pThreadState) @@ -410,6 +420,10 @@ NV_STATUS __nvoc_objCreate_Intr(Intr**, Dynamic*, NvU32); #define intrStateLoad_HAL(pGpu, pIntr, arg0) intrStateLoad_DISPATCH(pGpu, pIntr, arg0) #define intrStateUnload(pGpu, pIntr, arg0) intrStateUnload_DISPATCH(pGpu, pIntr, arg0) #define intrStateUnload_HAL(pGpu, pIntr, arg0) intrStateUnload_DISPATCH(pGpu, pIntr, arg0) +#define intrInitSubtreeMap(pGpu, pIntr) intrInitSubtreeMap_DISPATCH(pGpu, pIntr) +#define intrInitSubtreeMap_HAL(pGpu, pIntr) intrInitSubtreeMap_DISPATCH(pGpu, pIntr) +#define intrInitInterruptTable(pGpu, pIntr) intrInitInterruptTable_DISPATCH(pGpu, pIntr) +#define intrInitInterruptTable_HAL(pGpu, pIntr) intrInitInterruptTable_DISPATCH(pGpu, pIntr) #define intrSetIntrMask(pGpu, pIntr, arg0, arg1) intrSetIntrMask_DISPATCH(pGpu, pIntr, arg0, arg1) #define intrSetIntrMask_HAL(pGpu, pIntr, arg0, arg1) intrSetIntrMask_DISPATCH(pGpu, pIntr, arg0, arg1) #define intrSetIntrEnInHw(pGpu, pIntr, arg0, arg1) intrSetIntrEnInHw_DISPATCH(pGpu, pIntr, arg0, arg1) @@ -693,40 +707,6 @@ static inline void intrClearLeafVector(OBJGPU *pGpu, struct Intr *pIntr, NvU32 v #define intrClearLeafVector_HAL(pGpu, pIntr, vector, pThreadState) intrClearLeafVector(pGpu, pIntr, vector, pThreadState) -static inline void intrClearCpuLeafVector_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { - return; -} - -void intrClearCpuLeafVector_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); - - -#ifdef __nvoc_intr_h_disabled -static inline void intrClearCpuLeafVector(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); -} -#else //__nvoc_intr_h_disabled -#define intrClearCpuLeafVector(pGpu, pIntr, vector, pThreadState) intrClearCpuLeafVector_b3696a(pGpu, pIntr, vector, pThreadState) -#endif //__nvoc_intr_h_disabled - -#define intrClearCpuLeafVector_HAL(pGpu, pIntr, vector, pThreadState) intrClearCpuLeafVector(pGpu, pIntr, vector, pThreadState) - -static inline void intrWriteCpuRegLeaf_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - return; -} - -void intrWriteCpuRegLeaf_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); - - -#ifdef __nvoc_intr_h_disabled -static inline void intrWriteCpuRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); -} -#else //__nvoc_intr_h_disabled -#define intrWriteCpuRegLeaf(pGpu, pIntr, arg0, arg1, arg2) intrWriteCpuRegLeaf_b3696a(pGpu, pIntr, arg0, arg1, arg2) -#endif //__nvoc_intr_h_disabled - -#define intrWriteCpuRegLeaf_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteCpuRegLeaf(pGpu, pIntr, arg0, arg1, arg2) - NvBool intrIsVectorPending_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 vector, struct THREAD_STATE_NODE *pThreadState); @@ -795,19 +775,6 @@ static inline void intrDisableStallSWIntr(OBJGPU *pGpu, struct Intr *pIntr) { #define intrDisableStallSWIntr_HAL(pGpu, pIntr) intrDisableStallSWIntr(pGpu, pIntr) -void intrServiceVirtual_TU102(OBJGPU *pGpu, struct Intr *pIntr); - - -#ifdef __nvoc_intr_h_disabled -static inline void intrServiceVirtual(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); -} -#else //__nvoc_intr_h_disabled -#define intrServiceVirtual(pGpu, pIntr) intrServiceVirtual_TU102(pGpu, pIntr) -#endif //__nvoc_intr_h_disabled - -#define intrServiceVirtual_HAL(pGpu, pIntr) intrServiceVirtual(pGpu, pIntr) - static inline void intrResetIntrRegistersForVF_b3696a(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { return; } @@ -879,20 +846,6 @@ static inline NV_STATUS intrTriggerCpuDoorbellForVF(OBJGPU *pGpu, struct Intr *p #define intrTriggerCpuDoorbellForVF_HAL(pGpu, pIntr, gfid) intrTriggerCpuDoorbellForVF(pGpu, pIntr, gfid) -NV_STATUS intrTriggerPrivDoorbell_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid); - - -#ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrTriggerPrivDoorbell(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intr_h_disabled -#define intrTriggerPrivDoorbell(pGpu, pIntr, gfid) intrTriggerPrivDoorbell_TU102(pGpu, pIntr, gfid) -#endif //__nvoc_intr_h_disabled - -#define intrTriggerPrivDoorbell_HAL(pGpu, pIntr, gfid) intrTriggerPrivDoorbell(pGpu, pIntr, gfid) - void intrRetriggerTopLevel_TU102(OBJGPU *pGpu, struct Intr *pIntr); @@ -961,7 +914,9 @@ static inline NV_STATUS intrCacheIntrFields(OBJGPU *pGpu, struct Intr *pIntr) { #define intrCacheIntrFields_HAL(pGpu, pIntr) intrCacheIntrFields(pGpu, pIntr) -NvU32 intrReadRegLeafEnSet_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); +NvU32 intrReadRegLeafEnSet_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + +NvU32 intrReadRegLeafEnSet_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); #ifdef __nvoc_intr_h_disabled @@ -970,12 +925,14 @@ static inline NvU32 intrReadRegLeafEnSet(OBJGPU *pGpu, struct Intr *pIntr, NvU32 return 0; } #else //__nvoc_intr_h_disabled -#define intrReadRegLeafEnSet(pGpu, pIntr, arg0, arg1) intrReadRegLeafEnSet_TU102(pGpu, pIntr, arg0, arg1) +#define intrReadRegLeafEnSet(pGpu, pIntr, arg0, arg1) intrReadRegLeafEnSet_CPU_TU102(pGpu, pIntr, arg0, arg1) #endif //__nvoc_intr_h_disabled #define intrReadRegLeafEnSet_HAL(pGpu, pIntr, arg0, arg1) intrReadRegLeafEnSet(pGpu, pIntr, arg0, arg1) -NvU32 intrReadRegLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); +NvU32 intrReadRegLeaf_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + +NvU32 intrReadRegLeaf_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); #ifdef __nvoc_intr_h_disabled @@ -984,12 +941,14 @@ static inline NvU32 intrReadRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0 return 0; } #else //__nvoc_intr_h_disabled -#define intrReadRegLeaf(pGpu, pIntr, arg0, arg1) intrReadRegLeaf_TU102(pGpu, pIntr, arg0, arg1) +#define intrReadRegLeaf(pGpu, pIntr, arg0, arg1) intrReadRegLeaf_CPU_TU102(pGpu, pIntr, arg0, arg1) #endif //__nvoc_intr_h_disabled #define intrReadRegLeaf_HAL(pGpu, pIntr, arg0, arg1) intrReadRegLeaf(pGpu, pIntr, arg0, arg1) -NvU32 intrReadRegTop_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); +NvU32 intrReadRegTop_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + +NvU32 intrReadRegTop_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); #ifdef __nvoc_intr_h_disabled @@ -998,12 +957,14 @@ static inline NvU32 intrReadRegTop(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, return 0; } #else //__nvoc_intr_h_disabled -#define intrReadRegTop(pGpu, pIntr, arg0, arg1) intrReadRegTop_TU102(pGpu, pIntr, arg0, arg1) +#define intrReadRegTop(pGpu, pIntr, arg0, arg1) intrReadRegTop_CPU_TU102(pGpu, pIntr, arg0, arg1) #endif //__nvoc_intr_h_disabled #define intrReadRegTop_HAL(pGpu, pIntr, arg0, arg1) intrReadRegTop(pGpu, pIntr, arg0, arg1) -void intrWriteRegLeafEnSet_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); +void intrWriteRegLeafEnSet_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +void intrWriteRegLeafEnSet_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); #ifdef __nvoc_intr_h_disabled @@ -1011,12 +972,14 @@ static inline void intrWriteRegLeafEnSet(OBJGPU *pGpu, struct Intr *pIntr, NvU32 NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); } #else //__nvoc_intr_h_disabled -#define intrWriteRegLeafEnSet(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeafEnSet_TU102(pGpu, pIntr, arg0, arg1, arg2) +#define intrWriteRegLeafEnSet(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeafEnSet_CPU_TU102(pGpu, pIntr, arg0, arg1, arg2) #endif //__nvoc_intr_h_disabled #define intrWriteRegLeafEnSet_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeafEnSet(pGpu, pIntr, arg0, arg1, arg2) -void intrWriteRegLeafEnClear_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); +void intrWriteRegLeafEnClear_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +void intrWriteRegLeafEnClear_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); #ifdef __nvoc_intr_h_disabled @@ -1024,12 +987,14 @@ static inline void intrWriteRegLeafEnClear(OBJGPU *pGpu, struct Intr *pIntr, NvU NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); } #else //__nvoc_intr_h_disabled -#define intrWriteRegLeafEnClear(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeafEnClear_TU102(pGpu, pIntr, arg0, arg1, arg2) +#define intrWriteRegLeafEnClear(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeafEnClear_CPU_TU102(pGpu, pIntr, arg0, arg1, arg2) #endif //__nvoc_intr_h_disabled #define intrWriteRegLeafEnClear_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeafEnClear(pGpu, pIntr, arg0, arg1, arg2) -void intrWriteRegLeaf_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); +void intrWriteRegLeaf_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +void intrWriteRegLeaf_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); #ifdef __nvoc_intr_h_disabled @@ -1037,7 +1002,7 @@ static inline void intrWriteRegLeaf(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0 NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); } #else //__nvoc_intr_h_disabled -#define intrWriteRegLeaf(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeaf_TU102(pGpu, pIntr, arg0, arg1, arg2) +#define intrWriteRegLeaf(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeaf_CPU_TU102(pGpu, pIntr, arg0, arg1, arg2) #endif //__nvoc_intr_h_disabled #define intrWriteRegLeaf_HAL(pGpu, pIntr, arg0, arg1, arg2) intrWriteRegLeaf(pGpu, pIntr, arg0, arg1, arg2) @@ -1091,40 +1056,6 @@ static inline NV_STATUS intrInitAnyInterruptTable(OBJGPU *pGpu, struct Intr *pIn #define intrInitAnyInterruptTable_HAL(pGpu, pIntr, pIntrTable, initFlags) intrInitAnyInterruptTable(pGpu, pIntr, pIntrTable, initFlags) -static inline NV_STATUS intrInitSubtreeMap_395e98(OBJGPU *pGpu, struct Intr *pIntr) { - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS intrInitSubtreeMap_TU102(OBJGPU *pGpu, struct Intr *pIntr); - -NV_STATUS intrInitSubtreeMap_GH100(OBJGPU *pGpu, struct Intr *pIntr); - - -#ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitSubtreeMap(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intr_h_disabled -#define intrInitSubtreeMap(pGpu, pIntr) intrInitSubtreeMap_395e98(pGpu, pIntr) -#endif //__nvoc_intr_h_disabled - -#define intrInitSubtreeMap_HAL(pGpu, pIntr) intrInitSubtreeMap(pGpu, pIntr) - -NV_STATUS intrInitInterruptTable_KERNEL(OBJGPU *pGpu, struct Intr *pIntr); - - -#ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrInitInterruptTable(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intr_h_disabled -#define intrInitInterruptTable(pGpu, pIntr) intrInitInterruptTable_KERNEL(pGpu, pIntr) -#endif //__nvoc_intr_h_disabled - -#define intrInitInterruptTable_HAL(pGpu, pIntr) intrInitInterruptTable(pGpu, pIntr) - NV_STATUS intrGetInterruptTable_IMPL(OBJGPU *pGpu, struct Intr *pIntr, InterruptTable **ppIntrTable); @@ -1343,74 +1274,6 @@ static inline NV_STATUS intrGetNvlinkIntrMaskOffset(OBJGPU *pGpu, struct Intr *p #define intrGetNvlinkIntrMaskOffset_HAL(pGpu, pIntr, arg0, arg1) intrGetNvlinkIntrMaskOffset(pGpu, pIntr, arg0, arg1) -static inline NV_STATUS intrGetEccVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - -NV_STATUS intrGetEccVirtualFunctionIntrMask_TU102(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); - -NV_STATUS intrGetEccVirtualFunctionIntrMask_GA100(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); - -NV_STATUS intrGetEccVirtualFunctionIntrMask_GH100(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0); - - -#ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrGetEccVirtualFunctionIntrMask(OBJGPU *pGpu, struct Intr *pIntr, struct Device *pDevice, NvU32 *arg0) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intr_h_disabled -#define intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, pDevice, arg0) intrGetEccVirtualFunctionIntrMask_5baef9(pGpu, pIntr, pDevice, arg0) -#endif //__nvoc_intr_h_disabled - -#define intrGetEccVirtualFunctionIntrMask_HAL(pGpu, pIntr, pDevice, arg0) intrGetEccVirtualFunctionIntrMask(pGpu, pIntr, pDevice, arg0) - -static inline NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_5baef9(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - -NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1); - -NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_GA100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1); - -NV_STATUS intrGetNvlinkVirtualFunctionIntrMask_GH100(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1); - - -#ifdef __nvoc_intr_h_disabled -static inline NV_STATUS intrGetNvlinkVirtualFunctionIntrMask(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 *arg1) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_intr_h_disabled -#define intrGetNvlinkVirtualFunctionIntrMask(pGpu, pIntr, arg0, arg1) intrGetNvlinkVirtualFunctionIntrMask_5baef9(pGpu, pIntr, arg0, arg1) -#endif //__nvoc_intr_h_disabled - -#define intrGetNvlinkVirtualFunctionIntrMask_HAL(pGpu, pIntr, arg0, arg1) intrGetNvlinkVirtualFunctionIntrMask(pGpu, pIntr, arg0, arg1) - -static inline NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll_5baef9(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); -} - -NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll_GA100(OBJGPU *pGpu, struct Intr *pIntr); - -NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll_GA102(OBJGPU *pGpu, struct Intr *pIntr); - -static inline NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll_4a4dee(OBJGPU *pGpu, struct Intr *pIntr) { - return 0; -} - - -#ifdef __nvoc_intr_h_disabled -static inline NvU32 intrGetEccVirtualFunctionIntrSmcMaskAll(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); - return 0; -} -#else //__nvoc_intr_h_disabled -#define intrGetEccVirtualFunctionIntrSmcMaskAll(pGpu, pIntr) intrGetEccVirtualFunctionIntrSmcMaskAll_5baef9(pGpu, pIntr) -#endif //__nvoc_intr_h_disabled - -#define intrGetEccVirtualFunctionIntrSmcMaskAll_HAL(pGpu, pIntr) intrGetEccVirtualFunctionIntrSmcMaskAll(pGpu, pIntr) - static inline NvBool intrRequiresPossibleErrorNotifier_491d52(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *pEngines) { return ((NvBool)(0 != 0)); } @@ -1433,8 +1296,8 @@ static inline NvBool intrRequiresPossibleErrorNotifier(OBJGPU *pGpu, struct Intr #define intrRequiresPossibleErrorNotifier_HAL(pGpu, pIntr, pEngines) intrRequiresPossibleErrorNotifier(pGpu, pIntr, pEngines) -static inline NvU32 intrReadErrCont_491d52(OBJGPU *pGpu, struct Intr *pIntr) { - return ((NvBool)(0 != 0)); +static inline NvU32 intrReadErrCont_4a4dee(OBJGPU *pGpu, struct Intr *pIntr) { + return 0; } NvU32 intrReadErrCont_TU102(OBJGPU *pGpu, struct Intr *pIntr); @@ -1446,7 +1309,7 @@ static inline NvU32 intrReadErrCont(OBJGPU *pGpu, struct Intr *pIntr) { return 0; } #else //__nvoc_intr_h_disabled -#define intrReadErrCont(pGpu, pIntr) intrReadErrCont_491d52(pGpu, pIntr) +#define intrReadErrCont(pGpu, pIntr) intrReadErrCont_4a4dee(pGpu, pIntr) #endif //__nvoc_intr_h_disabled #define intrReadErrCont_HAL(pGpu, pIntr) intrReadErrCont(pGpu, pIntr) @@ -1555,14 +1418,24 @@ static inline NvU32 intrDecodeStallIntrEn_DISPATCH(OBJGPU *pGpu, struct Intr *pI return pIntr->__intrDecodeStallIntrEn__(pGpu, pIntr, arg0); } -NvU32 intrGetNonStallBaseVector_TU102(OBJGPU *pGpu, struct Intr *pIntr); +static inline void intrServiceVirtual_f2d351(OBJGPU *pGpu, struct Intr *pIntr) { + NV_ASSERT_PRECOMP(0); +} -static inline NvU32 intrGetNonStallBaseVector_c067f9(OBJGPU *pGpu, struct Intr *pIntr) { - NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +void intrServiceVirtual_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +static inline void intrServiceVirtual_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { + pIntr->__intrServiceVirtual__(pGpu, pIntr); } -static inline NvU32 intrGetNonStallBaseVector_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { - return pIntr->__intrGetNonStallBaseVector__(pGpu, pIntr); +static inline NV_STATUS intrTriggerPrivDoorbell_5baef9(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +NV_STATUS intrTriggerPrivDoorbell_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid); + +static inline NV_STATUS intrTriggerPrivDoorbell_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 gfid) { + return pIntr->__intrTriggerPrivDoorbell__(pGpu, pIntr, gfid); } NvU64 intrGetUvmSharedLeafEnDisableMask_TU102(OBJGPU *pGpu, struct Intr *pIntr); @@ -1583,25 +1456,37 @@ static inline void intrSetDisplayInterruptEnable_DISPATCH(OBJGPU *pGpu, struct I pIntr->__intrSetDisplayInterruptEnable__(pGpu, pIntr, bEnable, pThreadState); } -NvU32 intrReadRegTopEnSet_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); +NvU32 intrReadRegTopEnSet_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + +NvU32 intrReadRegTopEnSet_CPU_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); -NvU32 intrReadRegTopEnSet_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); +NvU32 intrReadRegTopEnSet_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); + +NvU32 intrReadRegTopEnSet_GSP_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1); static inline NvU32 intrReadRegTopEnSet_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, struct THREAD_STATE_NODE *arg1) { return pIntr->__intrReadRegTopEnSet__(pGpu, pIntr, arg0, arg1); } -void intrWriteRegTopEnSet_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); +void intrWriteRegTopEnSet_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +void intrWriteRegTopEnSet_CPU_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); -void intrWriteRegTopEnSet_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); +void intrWriteRegTopEnSet_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +void intrWriteRegTopEnSet_GSP_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); static inline void intrWriteRegTopEnSet_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { pIntr->__intrWriteRegTopEnSet__(pGpu, pIntr, arg0, arg1, arg2); } -void intrWriteRegTopEnClear_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); +void intrWriteRegTopEnClear_CPU_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +void intrWriteRegTopEnClear_CPU_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); + +void intrWriteRegTopEnClear_GSP_TU102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); -void intrWriteRegTopEnClear_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); +void intrWriteRegTopEnClear_GSP_GA102(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2); static inline void intrWriteRegTopEnClear_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr, NvU32 arg0, NvU32 arg1, struct THREAD_STATE_NODE *arg2) { pIntr->__intrWriteRegTopEnClear__(pGpu, pIntr, arg0, arg1, arg2); @@ -1667,6 +1552,26 @@ static inline NV_STATUS intrStateUnload_DISPATCH(OBJGPU *pGpu, struct Intr *pInt return pIntr->__intrStateUnload__(pGpu, pIntr, arg0); } +static inline NV_STATUS intrInitSubtreeMap_395e98(OBJGPU *pGpu, struct Intr *pIntr) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS intrInitSubtreeMap_TU102(OBJGPU *pGpu, struct Intr *pIntr); + +NV_STATUS intrInitSubtreeMap_GH100(OBJGPU *pGpu, struct Intr *pIntr); + +static inline NV_STATUS intrInitSubtreeMap_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { + return pIntr->__intrInitSubtreeMap__(pGpu, pIntr); +} + +NV_STATUS intrInitInterruptTable_VIRTUAL(OBJGPU *pGpu, struct Intr *pIntr); + +NV_STATUS intrInitInterruptTable_KERNEL(OBJGPU *pGpu, struct Intr *pIntr); + +static inline NV_STATUS intrInitInterruptTable_DISPATCH(OBJGPU *pGpu, struct Intr *pIntr) { + return pIntr->__intrInitInterruptTable__(pGpu, pIntr); +} + NV_STATUS intrSetIntrMask_GP100(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1); static inline NV_STATUS intrSetIntrMask_46f6a7(OBJGPU *pGpu, struct Intr *pIntr, union MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { @@ -1903,6 +1808,17 @@ static inline void intrConvertPmcIntrMaskToEngineMask(OBJGPU *pGpu, struct Intr #define intrConvertPmcIntrMaskToEngineMask(pGpu, pIntr, arg0, arg1) intrConvertPmcIntrMaskToEngineMask_IMPL(pGpu, pIntr, arg0, arg1) #endif //__nvoc_intr_h_disabled +INTR_TABLE_ENTRY *intrGetInterruptTableEntryFromEngineId_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU16 mcEngineId, NvBool bNonStall); + +#ifdef __nvoc_intr_h_disabled +static inline INTR_TABLE_ENTRY *intrGetInterruptTableEntryFromEngineId(OBJGPU *pGpu, struct Intr *pIntr, NvU16 mcEngineId, NvBool bNonStall) { + NV_ASSERT_FAILED_PRECOMP("Intr was disabled!"); + return NULL; +} +#else //__nvoc_intr_h_disabled +#define intrGetInterruptTableEntryFromEngineId(pGpu, pIntr, mcEngineId, bNonStall) intrGetInterruptTableEntryFromEngineId_IMPL(pGpu, pIntr, mcEngineId, bNonStall) +#endif //__nvoc_intr_h_disabled + NvU32 intrGetVectorFromEngineId_IMPL(OBJGPU *pGpu, struct Intr *pIntr, NvU16 mcEngineId, NvBool bNonStall); #ifdef __nvoc_intr_h_disabled diff --git a/src/nvidia/generated/g_intr_service_nvoc.h b/src/nvidia/generated/g_intr_service_nvoc.h index d2b7cbe785..751dc14245 100644 --- a/src/nvidia/generated/g_intr_service_nvoc.h +++ b/src/nvidia/generated/g_intr_service_nvoc.h @@ -76,11 +76,16 @@ typedef struct { NvU16 engineIdx; } IntrServiceServiceNotificationInterruptArguments; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_INTR_SERVICE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct IntrService { const struct NVOC_RTTI *__nvoc_rtti; struct IntrService *__nvoc_pbase_IntrService; @@ -122,9 +127,9 @@ NV_STATUS __nvoc_objCreate_IntrService(IntrService**, Dynamic*, NvU32); #define intrservClearInterrupt(pGpu, pIntrService, pParams) intrservClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceInterrupt(pGpu, pIntrService, pParams) intrservServiceInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define intrservServiceNotificationInterrupt(pGpu, pIntrService, pParams) intrservServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) -void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[168]); +void intrservRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[171]); -static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[168]) { +static inline void intrservRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct IntrService *pIntrService, IntrServiceRecord pRecords[171]) { pIntrService->__intrservRegisterIntrService__(pGpu, pIntrService, pRecords); } diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.c b/src/nvidia/generated/g_io_vaspace_nvoc.c index e6fbc65856..6314faa86b 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.c +++ b/src/nvidia/generated/g_io_vaspace_nvoc.c @@ -130,7 +130,7 @@ static PMEMORY_DESCRIPTOR __nvoc_thunk_OBJVASPACE_iovaspaceGetKernelPageDirBase( return vaspaceGetKernelPageDirBase((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu); } -static NvU64 __nvoc_thunk_OBJVASPACE_iovaspaceGetMapPageSize(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static NvU64 __nvoc_thunk_OBJVASPACE_iovaspaceGetMapPageSize(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock) { return vaspaceGetMapPageSize((struct OBJVASPACE *)(((unsigned char *)pVAS) + __nvoc_rtti_OBJIOVASPACE_OBJVASPACE.offset), pGpu, pMemBlock); } @@ -304,21 +304,26 @@ void __nvoc_init_OBJIOVASPACE(OBJIOVASPACE *pThis) { __nvoc_init_funcTable_OBJIOVASPACE(pThis); } -NV_STATUS __nvoc_objCreate_OBJIOVASPACE(OBJIOVASPACE **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJIOVASPACE(OBJIOVASPACE **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJIOVASPACE *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJIOVASPACE), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJIOVASPACE)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJIOVASPACE); pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -333,16 +338,25 @@ NV_STATUS __nvoc_objCreate_OBJIOVASPACE(OBJIOVASPACE **ppThis, Dynamic *pParent, status = __nvoc_ctor_OBJIOVASPACE(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJIOVASPACE_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJIOVASPACE_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJVASPACE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJIOVASPACE)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_io_vaspace_nvoc.h b/src/nvidia/generated/g_io_vaspace_nvoc.h index 0e1af752b6..02dc1e941b 100644 --- a/src/nvidia/generated/g_io_vaspace_nvoc.h +++ b/src/nvidia/generated/g_io_vaspace_nvoc.h @@ -135,11 +135,16 @@ struct IOVAMAPPING /*! * Virtual address space for a system's IOMMU translation. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_IO_VASPACE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJIOVASPACE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJVASPACE __nvoc_base_OBJVASPACE; @@ -162,7 +167,7 @@ struct OBJIOVASPACE { NV_STATUS (*__iovaspaceGetPteInfo__)(struct OBJIOVASPACE *, struct OBJGPU *, NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS *, RmPhysAddr *); PMEMORY_DESCRIPTOR (*__iovaspaceGetPageDirBase__)(struct OBJIOVASPACE *, struct OBJGPU *); PMEMORY_DESCRIPTOR (*__iovaspaceGetKernelPageDirBase__)(struct OBJIOVASPACE *, struct OBJGPU *); - NvU64 (*__iovaspaceGetMapPageSize__)(struct OBJIOVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__iovaspaceGetMapPageSize__)(struct OBJIOVASPACE *, struct OBJGPU *, struct EMEMBLOCK *); struct OBJEHEAP *(*__iovaspaceGetHeap__)(struct OBJIOVASPACE *); NvBool (*__iovaspaceIsFaultCapable__)(struct OBJIOVASPACE *); void (*__iovaspaceUnmap__)(struct OBJIOVASPACE *, struct OBJGPU *, const NvU64, const NvU64); @@ -315,7 +320,7 @@ static inline PMEMORY_DESCRIPTOR iovaspaceGetKernelPageDirBase_DISPATCH(struct O return pVAS->__iovaspaceGetKernelPageDirBase__(pVAS, pGpu); } -static inline NvU64 iovaspaceGetMapPageSize_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 iovaspaceGetMapPageSize_DISPATCH(struct OBJIOVASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock) { return pVAS->__iovaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff --git a/src/nvidia/generated/g_ioaccess_nvoc.h b/src/nvidia/generated/g_ioaccess_nvoc.h index ed83014794..51eaa3c4d2 100644 --- a/src/nvidia/generated/g_ioaccess_nvoc.h +++ b/src/nvidia/generated/g_ioaccess_nvoc.h @@ -59,11 +59,16 @@ extern "C" { #define REG_WR32_UC(ap, addr, val) regaprtWriteReg32Uc(staticCast(ap, RegisterAperture), addr, val) #define REG_VALID(ap, addr) regaprtIsRegValid (staticCast(ap, RegisterAperture), addr) + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_IOACCESS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RegisterAperture { const struct NVOC_RTTI *__nvoc_rtti; struct RegisterAperture *__nvoc_pbase_RegisterAperture; diff --git a/src/nvidia/generated/g_journal_nvoc.c b/src/nvidia/generated/g_journal_nvoc.c index 2cee605388..a4c15137af 100644 --- a/src/nvidia/generated/g_journal_nvoc.c +++ b/src/nvidia/generated/g_journal_nvoc.c @@ -129,21 +129,26 @@ void __nvoc_init_OBJRCDB(OBJRCDB *pThis) { __nvoc_init_funcTable_OBJRCDB(pThis); } -NV_STATUS __nvoc_objCreate_OBJRCDB(OBJRCDB **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJRCDB(OBJRCDB **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJRCDB *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJRCDB), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJRCDB)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJRCDB); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -158,16 +163,25 @@ NV_STATUS __nvoc_objCreate_OBJRCDB(OBJRCDB **ppThis, Dynamic *pParent, NvU32 cre status = __nvoc_ctor_OBJRCDB(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJRCDB_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJRCDB_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJRCDB)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_journal_nvoc.h b/src/nvidia/generated/g_journal_nvoc.h index ec95e134ae..944349ca1a 100644 --- a/src/nvidia/generated/g_journal_nvoc.h +++ b/src/nvidia/generated/g_journal_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -137,11 +137,26 @@ typedef struct typedef struct { NvU32 id; // record id + volatile NvS32 inUse; // indicates the record is actively being used. NV2080_NOCAT_JOURNAL_GPU_STATE nocatGpuState; // contains the state of the // associated GPU if there is one, NV2080_NOCAT_JOURNAL_ENTRY nocatJournalEntry; // the NOCAT report data -- IDs, diag data etc. } RM_NOCAT_JOURNAL_ENTRY; +typedef struct +{ + NvU64 timestamp NV_ALIGN_BYTES(8); + NvU8 recType; + NvU32 bugcheck; + const char *pSource; + NvU32 subsystem; + NvU64 errorCode NV_ALIGN_BYTES(8); + NvU32 diagBufferLen; + const NvU8 *pDiagBuffer; + const char *pFaultingEngine; + NvU32 tdrReason; +} NOCAT_JOURNAL_PARAMS; + #define ASSERT_CALL_STACK_SIZE 10 #define NOCAT_CACHE_FRESHNESS_PERIOD_MS 10ULL typedef struct @@ -156,7 +171,7 @@ typedef struct _nocatQueueDescriptor NvU32 nextRecordId; NvU32 nextReportedId; NvU32 nocatLastRecordType; - NvBool journalLocked; + NvU64 lockTimestamp; NvU32 lastRecordId[NV2080_NOCAT_JOURNAL_REC_TYPE_COUNT]; RM_NOCAT_ASSERT_DIAG_BUFFER lastAssertData; NvU8 tag[NV2080_NOCAT_JOURNAL_MAX_STR_LEN]; @@ -167,11 +182,16 @@ typedef struct _nocatQueueDescriptor NvU32 nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COUNTER_COUNT]; } nocatQueueDescriptor; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_JOURNAL_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJRCDB { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -346,25 +366,26 @@ static inline void rcdbDestroyRingBuffer(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE #define rcdbDestroyRingBuffer(pRcdb, type) rcdbDestroyRingBuffer_IMPL(pRcdb, type) #endif //__nvoc_journal_h_disabled -void rcdbAddRecToRingBuffer_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord); +RmRCCommonJournal_RECORD *rcdbAddRecToRingBuffer_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord); #ifdef __nvoc_journal_h_disabled -static inline void rcdbAddRecToRingBuffer(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord) { +static inline RmRCCommonJournal_RECORD *rcdbAddRecToRingBuffer(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type, NvU32 recordSize, NvU8 *pRecord) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); + return NULL; } #else //__nvoc_journal_h_disabled #define rcdbAddRecToRingBuffer(pGpu, pRcdb, type, recordSize, pRecord) rcdbAddRecToRingBuffer_IMPL(pGpu, pRcdb, type, recordSize, pRecord) #endif //__nvoc_journal_h_disabled -NvU32 rcdbGetOcaRecordSize_IMPL(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type); +NvU32 rcdbGetOcaRecordSizeWithHeader_IMPL(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type); #ifdef __nvoc_journal_h_disabled -static inline NvU32 rcdbGetOcaRecordSize(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type) { +static inline NvU32 rcdbGetOcaRecordSizeWithHeader(struct OBJRCDB *pRcdb, RMCD_RECORD_TYPE type) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); return 0; } #else //__nvoc_journal_h_disabled -#define rcdbGetOcaRecordSize(pRcdb, type) rcdbGetOcaRecordSize_IMPL(pRcdb, type) +#define rcdbGetOcaRecordSizeWithHeader(pRcdb, type) rcdbGetOcaRecordSizeWithHeader_IMPL(pRcdb, type) #endif //__nvoc_journal_h_disabled NvU32 rcdbDumpJournal_IMPL(struct OBJRCDB *pRcdb, struct OBJGPU *pGpu, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, const PRB_FIELD_DESC *pFieldDesc); @@ -433,17 +454,28 @@ static inline NV_STATUS rcdbGetRcDiagRecBoundaries(struct OBJRCDB *pRcdb, NvU16 #define rcdbGetRcDiagRecBoundaries(pRcdb, arg0, arg1, arg2, arg3) rcdbGetRcDiagRecBoundaries_IMPL(pRcdb, arg0, arg1, arg2, arg3) #endif //__nvoc_journal_h_disabled -NV_STATUS rcdbAddRcDiagRec_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0); +RmRCCommonJournal_RECORD *rcdbAddRcDiagRec_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0); #ifdef __nvoc_journal_h_disabled -static inline NV_STATUS rcdbAddRcDiagRec(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0) { +static inline RmRCCommonJournal_RECORD *rcdbAddRcDiagRec(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRcDiag_RECORD *arg0) { NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return NULL; } #else //__nvoc_journal_h_disabled #define rcdbAddRcDiagRec(pGpu, pRcdb, arg0) rcdbAddRcDiagRec_IMPL(pGpu, pRcdb, arg0) #endif //__nvoc_journal_h_disabled +RmRCCommonJournal_RECORD *rcdbAddRcDiagRecFromGsp_IMPL(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRCCommonJournal_RECORD *arg0, RmRcDiag_RECORD *arg1); + +#ifdef __nvoc_journal_h_disabled +static inline RmRCCommonJournal_RECORD *rcdbAddRcDiagRecFromGsp(struct OBJGPU *pGpu, struct OBJRCDB *pRcdb, RmRCCommonJournal_RECORD *arg0, RmRcDiag_RECORD *arg1) { + NV_ASSERT_FAILED_PRECOMP("OBJRCDB was disabled!"); + return NULL; +} +#else //__nvoc_journal_h_disabled +#define rcdbAddRcDiagRecFromGsp(pGpu, pRcdb, arg0, arg1) rcdbAddRcDiagRecFromGsp_IMPL(pGpu, pRcdb, arg0, arg1) +#endif //__nvoc_journal_h_disabled + NV_STATUS rcdbGetRcDiagRec_IMPL(struct OBJRCDB *pRcdb, NvU16 arg0, RmRCCommonJournal_RECORD **arg1, NvU32 arg2, NvU32 arg3); #ifdef __nvoc_journal_h_disabled @@ -475,18 +507,6 @@ void rcdbCleanupNocatGpuCache_IMPL(struct OBJGPU *pGpu); #undef PRIVATE_FIELD -typedef struct -{ - NvU8 recType; - NvU32 bugcheck; - const char *pSource; - NvU32 subsystem; - NvU64 errorCode NV_ALIGN_BYTES(8); - NvU32 diagBufferLen; - NvU8 *pDiagBuffer; - const char *pFaultingEngine; - NvU32 tdrReason; -} NOCAT_JOURNAL_PARAMS; NV_STATUS rcdbAddRmDclMsg(void* msg, NvU16 size, const PRB_FIELD_DESC *fieldDesc); NV_STATUS rcdbAddRmEngDump(struct OBJGPU *pGpu, NvU32 component); @@ -496,9 +516,11 @@ void rcdbAddCrashedFalcon(struct Falcon *pFlcn); NV_STATUS rcdbAddAssertJournalRec(void* pGpu, void** ppRec, NvU8 jGroup, NvU8 type, NvU16 size, NvU32 level, NvU64 key); + NV_STATUS rcdbAddAssertJournalRecWithLine(void *pVoidGpu, NvU32 lineNum, void** ppRec, NvU8 jGroup, NvU8 type, NvU16 size, NvU32 level, NvU64 key); +/*! insert a record into the NOCAT Journal */ NvU32 rcdbNocatInsertNocatError(struct OBJGPU *pGpu, NOCAT_JOURNAL_PARAMS *nocatJournalEntry); @@ -520,12 +542,6 @@ NvU32 rcdbNocatInsertTDRError(struct OBJGPU *pGpu, NvU8 *pDiagBuffer, NvU32 diagBufferLen, NvU32 tdrReason, const char *pFaultingApp); -NV_STATUS rcdbNocatInitRCErrorEvent(NOCAT_JOURNAL_PARAMS *nocatJournalEntry); -NvU32 rcdbNocatInsertRCError(struct OBJGPU* pGpu, - NvU32 subsystem, NvU64 errorCode, - NvU32 rcDiagRecStartIdx, NvU32 rcDiagRecEndIdx, - void* pAppId); - NV_STATUS rcdbReportNextNocatJournalEntry(NV2080_NOCAT_JOURNAL_RECORD* pReport); NV_STATUS rcdbSetNocatTdrReason(NV2080CtrlNocatJournalDataTdrReason *pReasonData); diff --git a/src/nvidia/generated/g_kern_bus_nvoc.c b/src/nvidia/generated/g_kern_bus_nvoc.c index bea3643f30..336a911802 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.c +++ b/src/nvidia/generated/g_kern_bus_nvoc.c @@ -254,6 +254,16 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal function -- kbusInitBarsSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusInitBarsSize__ = &kbusInitBarsSize_VGPUSTUB; + } + else + { + pThis->__kbusInitBarsSize__ = &kbusInitBarsSize_KERNEL; + } + pThis->__kbusConstructEngine__ = &kbusConstructEngine_IMPL; // Hal function -- kbusStatePreInitLocked @@ -282,6 +292,136 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * // Hal function -- kbusStateDestroy pThis->__kbusStateDestroy__ = &kbusStateDestroy_GM107; + // Hal function -- kbusMapBar2Aperture + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusMapBar2Aperture__ = &kbusMapBar2Aperture_VBAR2_SRIOV; + } + else + { + pThis->__kbusMapBar2Aperture__ = &kbusMapBar2Aperture_VBAR2; + } + + // Hal function -- kbusValidateBar2ApertureMapping + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusValidateBar2ApertureMapping__ = &kbusValidateBar2ApertureMapping_VBAR2_SRIOV; + } + else + { + pThis->__kbusValidateBar2ApertureMapping__ = &kbusValidateBar2ApertureMapping_VBAR2; + } + + // Hal function -- kbusUnmapBar2ApertureWithFlags + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusUnmapBar2ApertureWithFlags__ = &kbusUnmapBar2ApertureWithFlags_VBAR2_SRIOV; + } + else + { + pThis->__kbusUnmapBar2ApertureWithFlags__ = &kbusUnmapBar2ApertureWithFlags_VBAR2; + } + + // Hal function -- kbusGetVaLimitForBar2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusGetVaLimitForBar2__ = &kbusGetVaLimitForBar2_IMPL; + } + else + { + pThis->__kbusGetVaLimitForBar2__ = &kbusGetVaLimitForBar2_FWCLIENT; + } + + // Hal function -- kbusCalcCpuInvisibleBar2Range + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusCalcCpuInvisibleBar2Range__ = &kbusCalcCpuInvisibleBar2Range_GP100; + } + else + { + pThis->__kbusCalcCpuInvisibleBar2Range__ = &kbusCalcCpuInvisibleBar2Range_f2d351; + } + + // Hal function -- kbusCalcCpuInvisibleBar2ApertureSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusCalcCpuInvisibleBar2ApertureSize__ = &kbusCalcCpuInvisibleBar2ApertureSize_GV100; + } + else + { + pThis->__kbusCalcCpuInvisibleBar2ApertureSize__ = &kbusCalcCpuInvisibleBar2ApertureSize_13cd8d; + } + + // Hal function -- kbusCommitBar2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusCommitBar2__ = &kbusCommitBar2_GM107; + } + else + { + pThis->__kbusCommitBar2__ = &kbusCommitBar2_KERNEL; + } + + // Hal function -- kbusRewritePTEsForExistingMapping + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusRewritePTEsForExistingMapping__ = &kbusRewritePTEsForExistingMapping_VBAR2; + } + else + { + pThis->__kbusRewritePTEsForExistingMapping__ = &kbusRewritePTEsForExistingMapping_92bfc3; + } + + // Hal function -- kbusPatchBar1Pdb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusPatchBar1Pdb__ = &kbusPatchBar1Pdb_56cd7a; + } + else + { + pThis->__kbusPatchBar1Pdb__ = &kbusPatchBar1Pdb_GSPCLIENT; + } + + // Hal function -- kbusPatchBar2Pdb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusPatchBar2Pdb__ = &kbusPatchBar2Pdb_56cd7a; + } + else + { + pThis->__kbusPatchBar2Pdb__ = &kbusPatchBar2Pdb_GSPCLIENT; + } + + // Hal function -- kbusConstructVirtualBar2CpuInvisibleHeap + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusConstructVirtualBar2CpuInvisibleHeap__ = &kbusConstructVirtualBar2CpuInvisibleHeap_VBAR2; + } + else + { + pThis->__kbusConstructVirtualBar2CpuInvisibleHeap__ = &kbusConstructVirtualBar2CpuInvisibleHeap_56cd7a; + } + + // Hal function -- kbusMapCpuInvisibleBar2Aperture + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusMapCpuInvisibleBar2Aperture__ = &kbusMapCpuInvisibleBar2Aperture_VBAR2; + } + else + { + pThis->__kbusMapCpuInvisibleBar2Aperture__ = &kbusMapCpuInvisibleBar2Aperture_46f6a7; + } + + // Hal function -- kbusUnmapCpuInvisibleBar2Aperture + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusUnmapCpuInvisibleBar2Aperture__ = &kbusUnmapCpuInvisibleBar2Aperture_VBAR2; + } + else + { + pThis->__kbusUnmapCpuInvisibleBar2Aperture__ = &kbusUnmapCpuInvisibleBar2Aperture_b3696a; + } + // Hal function -- kbusTeardownBar2CpuAperture if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -343,6 +483,25 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusGetPeerId__ = &kbusGetPeerId_GP100; } + // Hal function -- kbusGetNvlinkPeerId + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__kbusGetNvlinkPeerId__ = &kbusGetNvlinkPeerId_GA100; + } + // default + else + { + pThis->__kbusGetNvlinkPeerId__ = &kbusGetNvlinkPeerId_c732fb; + } + } + // default + else + { + pThis->__kbusGetNvlinkPeerId__ = &kbusGetNvlinkPeerId_c732fb; + } + // Hal function -- kbusGetNvSwitchPeerId if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { @@ -375,17 +534,24 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusGetNvlinkP2PPeerId - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ - { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_VGPU; } else { - pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000060UL) )) /* ChipHal: TU102 | TU104 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GP100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000380UL) )) /* ChipHal: TU106 | TU116 | TU117 */ + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_56cd7a; + } + else + { + pThis->__kbusGetNvlinkP2PPeerId__ = &kbusGetNvlinkP2PPeerId_GA100; + } } // Hal function -- kbusWriteP2PWmbTag @@ -738,6 +904,16 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusSetupBindFla__ = &kbusSetupBindFla_46f6a7; } + // Hal function -- kbusSendSysmembarSingle + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusSendSysmembarSingle__ = &kbusSendSysmembarSingle_56cd7a; + } + else + { + pThis->__kbusSendSysmembarSingle__ = &kbusSendSysmembarSingle_KERNEL; + } + // Hal function -- kbusCacheBAR1ResizeSize_WAR_BUG_3249028 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -786,6 +962,16 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusUseDirectSysmemMap__ = &kbusUseDirectSysmemMap_GA100; } + // Hal function -- kbusMemCopyBar0Window + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusMemCopyBar0Window__ = &kbusMemCopyBar0Window_46f6a7; + } + else + { + pThis->__kbusMemCopyBar0Window__ = &kbusMemCopyBar0Window_GM107; + } + // Hal function -- kbusWriteBAR0WindowBase if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -817,13 +1003,20 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * } // Hal function -- kbusSetBAR0WindowVidOffset - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GH100; + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_56cd7a; } else { - pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GM107; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GH100; + } + else + { + pThis->__kbusSetBAR0WindowVidOffset__ = &kbusSetBAR0WindowVidOffset_GM107; + } } // Hal function -- kbusGetBAR0WindowVidOffset @@ -836,14 +1029,165 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusGetBAR0WindowVidOffset__ = &kbusGetBAR0WindowVidOffset_GM107; } + // Hal function -- kbusSetupBar0WindowBeforeBar2Bootstrap + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusSetupBar0WindowBeforeBar2Bootstrap__ = &kbusSetupBar0WindowBeforeBar2Bootstrap_56cd7a; + } + else + { + pThis->__kbusSetupBar0WindowBeforeBar2Bootstrap__ = &kbusSetupBar0WindowBeforeBar2Bootstrap_GM107; + } + + // Hal function -- kbusRestoreBar0WindowAfterBar2Bootstrap + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusRestoreBar0WindowAfterBar2Bootstrap__ = &kbusRestoreBar0WindowAfterBar2Bootstrap_b3696a; + } + else + { + pThis->__kbusRestoreBar0WindowAfterBar2Bootstrap__ = &kbusRestoreBar0WindowAfterBar2Bootstrap_GM107; + } + // Hal function -- kbusVerifyBar2 - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GH100; + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_56cd7a; } else { - pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GM107; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GH100; + } + else + { + pThis->__kbusVerifyBar2__ = &kbusVerifyBar2_GM107; + } + } + + // Hal function -- kbusBar2BootStrapInPhysicalMode + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusBar2BootStrapInPhysicalMode__ = &kbusBar2BootStrapInPhysicalMode_VGPUSTUB; + } + else + { + pThis->__kbusBar2BootStrapInPhysicalMode__ = &kbusBar2BootStrapInPhysicalMode_56cd7a; + } + + // Hal function -- kbusBindBar2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusBindBar2__ = &kbusBindBar2_GH100; + } + else + { + pThis->__kbusBindBar2__ = &kbusBindBar2_TU102; + } + } + else + { + pThis->__kbusBindBar2__ = &kbusBindBar2_5baef9; + } + + // Hal function -- kbusInstBlkWriteAddrLimit + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbusInstBlkWriteAddrLimit__ = &kbusInstBlkWriteAddrLimit_GP100; + } + else + { + pThis->__kbusInstBlkWriteAddrLimit__ = &kbusInstBlkWriteAddrLimit_b3696a; + } + } + else + { + pThis->__kbusInstBlkWriteAddrLimit__ = &kbusInstBlkWriteAddrLimit_f2d351; + } + + // Hal function -- kbusInitInstBlk + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusInitInstBlk__ = &kbusInitInstBlk_GP100; + } + else + { + pThis->__kbusInitInstBlk__ = &kbusInitInstBlk_ac1694; + } + + // Hal function -- kbusBar2InstBlkWrite + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusBar2InstBlkWrite__ = &kbusBar2InstBlkWrite_GP100; + } + else + { + pThis->__kbusBar2InstBlkWrite__ = &kbusBar2InstBlkWrite_d44104; + } + + // Hal function -- kbusSetupBar2PageTablesAtBottomOfFb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusSetupBar2PageTablesAtBottomOfFb__ = &kbusSetupBar2PageTablesAtBottomOfFb_GM107; + } + else + { + pThis->__kbusSetupBar2PageTablesAtBottomOfFb__ = &kbusSetupBar2PageTablesAtBottomOfFb_22ba1e; + } + + // Hal function -- kbusTeardownBar2PageTablesAtBottomOfFb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusTeardownBar2PageTablesAtBottomOfFb__ = &kbusTeardownBar2PageTablesAtBottomOfFb_GM107; + } + else + { + pThis->__kbusTeardownBar2PageTablesAtBottomOfFb__ = &kbusTeardownBar2PageTablesAtBottomOfFb_566dba; + } + + // Hal function -- kbusSetupBar2InstBlkAtBottomOfFb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusSetupBar2InstBlkAtBottomOfFb__ = &kbusSetupBar2InstBlkAtBottomOfFb_GM107; + } + else + { + pThis->__kbusSetupBar2InstBlkAtBottomOfFb__ = &kbusSetupBar2InstBlkAtBottomOfFb_22ba1e; + } + + // Hal function -- kbusTeardownBar2InstBlkAtBottomOfFb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusTeardownBar2InstBlkAtBottomOfFb__ = &kbusTeardownBar2InstBlkAtBottomOfFb_GM107; + } + else + { + pThis->__kbusTeardownBar2InstBlkAtBottomOfFb__ = &kbusTeardownBar2InstBlkAtBottomOfFb_566dba; + } + + // Hal function -- kbusSetupBar2PageTablesAtTopOfFb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusSetupBar2PageTablesAtTopOfFb__ = &kbusSetupBar2PageTablesAtTopOfFb_GM107; + } + else + { + pThis->__kbusSetupBar2PageTablesAtTopOfFb__ = &kbusSetupBar2PageTablesAtTopOfFb_22ba1e; + } + + // Hal function -- kbusCommitBar2PDEs + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusCommitBar2PDEs__ = &kbusCommitBar2PDEs_GM107; + } + else + { + pThis->__kbusCommitBar2PDEs__ = &kbusCommitBar2PDEs_22ba1e; } // Hal function -- kbusVerifyCoherentLink @@ -857,6 +1201,26 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusVerifyCoherentLink__ = &kbusVerifyCoherentLink_56cd7a; } + // Hal function -- kbusTeardownMailbox + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusTeardownMailbox__ = &kbusTeardownMailbox_GH100; + } + else + { + pThis->__kbusTeardownMailbox__ = &kbusTeardownMailbox_GM107; + } + + // Hal function -- kbusBar1InstBlkVasUpdate + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbusBar1InstBlkVasUpdate__ = &kbusBar1InstBlkVasUpdate_GM107; + } + else + { + pThis->__kbusBar1InstBlkVasUpdate__ = &kbusBar1InstBlkVasUpdate_56cd7a; + } + // Hal function -- kbusFlushPcieForBar0Doorbell if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -911,6 +1275,45 @@ static void __nvoc_init_funcTable_KernelBus_1(KernelBus *pThis, RmHalspecOwner * pThis->__kbusTeardownCoherentCpuMapping__ = &kbusTeardownCoherentCpuMapping_d44104; } + // Hal function -- kbusBar1InstBlkBind + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusBar1InstBlkBind__ = &kbusBar1InstBlkBind_GH100; + } + else + { + pThis->__kbusBar1InstBlkBind__ = &kbusBar1InstBlkBind_TU102; + } + } + else + { + pThis->__kbusBar1InstBlkBind__ = &kbusBar1InstBlkBind_92bfc3; + } + + // Hal function -- kbusGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusGetEccCounts__ = &kbusGetEccCounts_GH100; + } + // default + else + { + pThis->__kbusGetEccCounts__ = &kbusGetEccCounts_4a4dee; + } + + // Hal function -- kbusClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbusClearEccCounts__ = &kbusClearEccCounts_GH100; + } + // default + else + { + pThis->__kbusClearEccCounts__ = &kbusClearEccCounts_b3696a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBus_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelBus_engstateStatePreInitLocked; @@ -971,23 +1374,31 @@ void __nvoc_init_KernelBus(KernelBus *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelBus(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelBus(KernelBus **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelBus(KernelBus **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelBus *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelBus), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelBus)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelBus); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -1005,16 +1416,25 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_KernelBus(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelBus_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelBus_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelBus)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kern_bus_nvoc.h b/src/nvidia/generated/g_kern_bus_nvoc.h index 230a870606..4d92b8672a 100644 --- a/src/nvidia/generated/g_kern_bus_nvoc.h +++ b/src/nvidia/generated/g_kern_bus_nvoc.h @@ -116,6 +116,10 @@ typedef enum #define BUS_MAP_FB_FLAGS_NV5X_INVALID ~(BUS_MAP_FB_FLAGS_MAP_RSVD_BAR1 | BUS_MAP_FB_FLAGS_DISABLE_ENCRYPTION) +// Inst Block +#define FERMI_PHYSADDR_WIDTH 40 // PA max address is 40 bits +#define GF100_BUS_INSTANCEBLOCK_SHIFT (FERMI_PHYSADDR_WIDTH - DRF_SIZE(NV_PBUS_BAR2_BLOCK_PTR)) + // // kbusFlush flags // @@ -187,11 +191,16 @@ typedef struct Device Device; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERN_BUS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct __nvoc_inner_struc_KernelBus_1__ { RmPhysAddr physAddr; NvU64 apertureLength; @@ -221,6 +230,8 @@ struct __nvoc_inner_struc_KernelBus_2__ { NvU64 pteBase; NvU64 instBlockBase; MEMORY_DESCRIPTOR *pInstBlkMemDesc; + MEMORY_DESCRIPTOR *pInstBlkMemDescForBootstrap; + MMU_WALK *pWalkForBootstrap; NvU64 pdeBaseForBootstrap; MEMORY_DESCRIPTOR *pPDEMemDescForBootstrap; NvU64 pteBaseForBootstrap; @@ -316,6 +327,7 @@ struct KernelBus { struct Object *__nvoc_pbase_Object; struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelBus *__nvoc_pbase_KernelBus; + NV_STATUS (*__kbusInitBarsSize__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusConstructEngine__)(struct OBJGPU *, struct KernelBus *, ENGDESCRIPTOR); NV_STATUS (*__kbusStatePreInitLocked__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusStateInitLocked__)(struct OBJGPU *, struct KernelBus *); @@ -326,12 +338,26 @@ struct KernelBus { NV_STATUS (*__kbusStateUnload__)(struct OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusStatePostUnload__)(struct OBJGPU *, struct KernelBus *, NvU32); void (*__kbusStateDestroy__)(struct OBJGPU *, struct KernelBus *); + NvU8 *(*__kbusMapBar2Aperture__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU32); + NvU8 *(*__kbusValidateBar2ApertureMapping__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU8 *); + void (*__kbusUnmapBar2ApertureWithFlags__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU8 **, NvU32); + NvU64 (*__kbusGetVaLimitForBar2__)(struct OBJGPU *, struct KernelBus *); + void (*__kbusCalcCpuInvisibleBar2Range__)(struct OBJGPU *, struct KernelBus *, NvU32); + NvU32 (*__kbusCalcCpuInvisibleBar2ApertureSize__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusCommitBar2__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusRewritePTEsForExistingMapping__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *); + NV_STATUS (*__kbusPatchBar1Pdb__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusPatchBar2Pdb__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusConstructVirtualBar2CpuInvisibleHeap__)(struct KernelBus *, NvU32); + NV_STATUS (*__kbusMapCpuInvisibleBar2Aperture__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU64 *, NvU64, NvU32, NvU32); + void (*__kbusUnmapCpuInvisibleBar2Aperture__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvU64, NvU32); NV_STATUS (*__kbusTeardownBar2CpuAperture__)(struct OBJGPU *, struct KernelBus *, NvU32); void (*__kbusGetP2PMailboxAttributes__)(struct OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32 *); NV_STATUS (*__kbusCreateP2PMapping__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32 *, NvU32 *, NvU32); NV_STATUS (*__kbusRemoveP2PMapping__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *, struct KernelBus *, NvU32, NvU32, NvU32); NvU32 (*__kbusGetEgmPeerId__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *); NvU32 (*__kbusGetPeerId__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *); + NvU32 (*__kbusGetNvlinkPeerId__)(struct OBJGPU *, struct KernelBus *, struct OBJGPU *); NvU32 (*__kbusGetNvSwitchPeerId__)(struct OBJGPU *, struct KernelBus *); NvU32 (*__kbusGetUnusedPciePeerId__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusIsPeerIdValid__)(struct OBJGPU *, struct KernelBus *, NvU32); @@ -367,22 +393,42 @@ struct KernelBus { NV_STATUS (*__kbusValidateFlaBaseAddress__)(struct OBJGPU *, struct KernelBus *, NvU64); NV_STATUS (*__kbusSetupUnbindFla__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusSetupBindFla__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusSendSysmembarSingle__)(struct OBJGPU *, struct KernelBus *); void (*__kbusCacheBAR1ResizeSize_WAR_BUG_3249028__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusRestoreBAR1ResizeSize_WAR_BUG_3249028__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusIsDirectMappingAllowed__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU32, NvBool *); NV_STATUS (*__kbusUseDirectSysmemMap__)(struct OBJGPU *, struct KernelBus *, MEMORY_DESCRIPTOR *, NvBool *); + NV_STATUS (*__kbusMemCopyBar0Window__)(struct OBJGPU *, struct KernelBus *, RmPhysAddr, void *, NvLength, NvBool); NV_STATUS (*__kbusWriteBAR0WindowBase__)(struct OBJGPU *, struct KernelBus *, NvU32); NvU32 (*__kbusReadBAR0WindowBase__)(struct OBJGPU *, struct KernelBus *); NvBool (*__kbusValidateBAR0WindowBase__)(struct OBJGPU *, struct KernelBus *, NvU32); NV_STATUS (*__kbusSetBAR0WindowVidOffset__)(struct OBJGPU *, struct KernelBus *, NvU64); NvU64 (*__kbusGetBAR0WindowVidOffset__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusSetupBar0WindowBeforeBar2Bootstrap__)(struct OBJGPU *, struct KernelBus *, NvU64 *); + void (*__kbusRestoreBar0WindowAfterBar2Bootstrap__)(struct OBJGPU *, struct KernelBus *, NvU64); NV_STATUS (*__kbusVerifyBar2__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU8 *, NvU64, NvU64); + NV_STATUS (*__kbusBar2BootStrapInPhysicalMode__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusBindBar2__)(struct OBJGPU *, struct KernelBus *, BAR2_MODE); + void (*__kbusInstBlkWriteAddrLimit__)(struct OBJGPU *, struct KernelBus *, NvBool, NvU64, NvU8 *, NvU64); + NV_STATUS (*__kbusInitInstBlk__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, PMEMORY_DESCRIPTOR, NvU64, NvU64, struct OBJVASPACE *); + void (*__kbusBar2InstBlkWrite__)(struct OBJGPU *, struct KernelBus *, NvU8 *, PMEMORY_DESCRIPTOR, NvU64, NvU64); + NV_STATUS (*__kbusSetupBar2PageTablesAtBottomOfFb__)(struct OBJGPU *, struct KernelBus *, NvU32); + void (*__kbusTeardownBar2PageTablesAtBottomOfFb__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusSetupBar2InstBlkAtBottomOfFb__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR, NvU64, NvU64, NvU32); + void (*__kbusTeardownBar2InstBlkAtBottomOfFb__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusSetupBar2PageTablesAtTopOfFb__)(struct OBJGPU *, struct KernelBus *, NvU32); + NV_STATUS (*__kbusCommitBar2PDEs__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusVerifyCoherentLink__)(struct OBJGPU *, struct KernelBus *); + void (*__kbusTeardownMailbox__)(struct OBJGPU *, struct KernelBus *); + NV_STATUS (*__kbusBar1InstBlkVasUpdate__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusFlushPcieForBar0Doorbell__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusCreateCoherentCpuMapping__)(struct OBJGPU *, struct KernelBus *, NvU64, NvBool); NvU8 *(*__kbusMapCoherentCpuMapping__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusUnmapCoherentCpuMapping__)(struct OBJGPU *, struct KernelBus *, PMEMORY_DESCRIPTOR); void (*__kbusTeardownCoherentCpuMapping__)(struct OBJGPU *, struct KernelBus *, NvBool); + NV_STATUS (*__kbusBar1InstBlkBind__)(struct OBJGPU *, struct KernelBus *); + NvU32 (*__kbusGetEccCounts__)(struct OBJGPU *, struct KernelBus *); + void (*__kbusClearEccCounts__)(struct OBJGPU *, struct KernelBus *); NV_STATUS (*__kbusStateInitUnlocked__)(POBJGPU, struct KernelBus *); void (*__kbusInitMissing__)(POBJGPU, struct KernelBus *); NV_STATUS (*__kbusStatePreInitUnlocked__)(POBJGPU, struct KernelBus *); @@ -403,6 +449,7 @@ struct KernelBus { NvBool bFlaSupported; NvBool bFlaEnabled; NvBool bFlaDummyPageEnabled; + NvBool bForceFlaTraffic; NvU8 bar1ResizeSizeIndex; struct __nvoc_inner_struc_KernelBus_5__ coherentCpuMapping; NvU64 coherentLinkTestBufferBase; @@ -443,6 +490,8 @@ struct KernelBus { NvU32 PDEBAR2Attr; NvU32 InstBlkAperture; NvU32 InstBlkAttr; + NvBool bInstProtectedMem; + NvBool bForceBarAccessOnHcc; }; #ifndef __NVOC_CLASS_KernelBus_TYPEDEF__ @@ -479,6 +528,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define __objCreate_KernelBus(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_KernelBus((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) +#define kbusInitBarsSize(pGpu, pKernelBus) kbusInitBarsSize_DISPATCH(pGpu, pKernelBus) +#define kbusInitBarsSize_HAL(pGpu, pKernelBus) kbusInitBarsSize_DISPATCH(pGpu, pKernelBus) #define kbusConstructEngine(pGpu, pKernelBus, arg0) kbusConstructEngine_DISPATCH(pGpu, pKernelBus, arg0) #define kbusStatePreInitLocked(pGpu, pKernelBus) kbusStatePreInitLocked_DISPATCH(pGpu, pKernelBus) #define kbusStatePreInitLocked_HAL(pGpu, pKernelBus) kbusStatePreInitLocked_DISPATCH(pGpu, pKernelBus) @@ -497,6 +548,32 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusStatePostUnload_HAL(pGpu, pKernelBus, flags) kbusStatePostUnload_DISPATCH(pGpu, pKernelBus, flags) #define kbusStateDestroy(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) #define kbusStateDestroy_HAL(pGpu, pKernelBus) kbusStateDestroy_DISPATCH(pGpu, pKernelBus) +#define kbusMapBar2Aperture(pGpu, pKernelBus, pMemDesc, transfer_flags) kbusMapBar2Aperture_DISPATCH(pGpu, pKernelBus, pMemDesc, transfer_flags) +#define kbusMapBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, transfer_flags) kbusMapBar2Aperture_DISPATCH(pGpu, pKernelBus, pMemDesc, transfer_flags) +#define kbusValidateBar2ApertureMapping(pGpu, pKernelBus, pMemDesc, p) kbusValidateBar2ApertureMapping_DISPATCH(pGpu, pKernelBus, pMemDesc, p) +#define kbusValidateBar2ApertureMapping_HAL(pGpu, pKernelBus, pMemDesc, p) kbusValidateBar2ApertureMapping_DISPATCH(pGpu, pKernelBus, pMemDesc, p) +#define kbusUnmapBar2ApertureWithFlags(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) kbusUnmapBar2ApertureWithFlags_DISPATCH(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) +#define kbusUnmapBar2ApertureWithFlags_HAL(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) kbusUnmapBar2ApertureWithFlags_DISPATCH(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) +#define kbusGetVaLimitForBar2(pGpu, pKernelBus) kbusGetVaLimitForBar2_DISPATCH(pGpu, pKernelBus) +#define kbusGetVaLimitForBar2_HAL(pGpu, pKernelBus) kbusGetVaLimitForBar2_DISPATCH(pGpu, pKernelBus) +#define kbusCalcCpuInvisibleBar2Range(pGpu, pKernelBus, gfid) kbusCalcCpuInvisibleBar2Range_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusCalcCpuInvisibleBar2Range_HAL(pGpu, pKernelBus, gfid) kbusCalcCpuInvisibleBar2Range_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusCalcCpuInvisibleBar2ApertureSize(pGpu, pKernelBus) kbusCalcCpuInvisibleBar2ApertureSize_DISPATCH(pGpu, pKernelBus) +#define kbusCalcCpuInvisibleBar2ApertureSize_HAL(pGpu, pKernelBus) kbusCalcCpuInvisibleBar2ApertureSize_DISPATCH(pGpu, pKernelBus) +#define kbusCommitBar2(pGpu, pKernelBus, flags) kbusCommitBar2_DISPATCH(pGpu, pKernelBus, flags) +#define kbusCommitBar2_HAL(pGpu, pKernelBus, flags) kbusCommitBar2_DISPATCH(pGpu, pKernelBus, flags) +#define kbusRewritePTEsForExistingMapping(pGpu, pKernelBus, pMemDesc) kbusRewritePTEsForExistingMapping_DISPATCH(pGpu, pKernelBus, pMemDesc) +#define kbusRewritePTEsForExistingMapping_HAL(pGpu, pKernelBus, pMemDesc) kbusRewritePTEsForExistingMapping_DISPATCH(pGpu, pKernelBus, pMemDesc) +#define kbusPatchBar1Pdb(pGpu, pKernelBus) kbusPatchBar1Pdb_DISPATCH(pGpu, pKernelBus) +#define kbusPatchBar1Pdb_HAL(pGpu, pKernelBus) kbusPatchBar1Pdb_DISPATCH(pGpu, pKernelBus) +#define kbusPatchBar2Pdb(pGpu, pKernelBus) kbusPatchBar2Pdb_DISPATCH(pGpu, pKernelBus) +#define kbusPatchBar2Pdb_HAL(pGpu, pKernelBus) kbusPatchBar2Pdb_DISPATCH(pGpu, pKernelBus) +#define kbusConstructVirtualBar2CpuInvisibleHeap(pKernelBus, gfid) kbusConstructVirtualBar2CpuInvisibleHeap_DISPATCH(pKernelBus, gfid) +#define kbusConstructVirtualBar2CpuInvisibleHeap_HAL(pKernelBus, gfid) kbusConstructVirtualBar2CpuInvisibleHeap_DISPATCH(pKernelBus, gfid) +#define kbusMapCpuInvisibleBar2Aperture(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) kbusMapCpuInvisibleBar2Aperture_DISPATCH(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) +#define kbusMapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) kbusMapCpuInvisibleBar2Aperture_DISPATCH(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) +#define kbusUnmapCpuInvisibleBar2Aperture(pGpu, pKernelBus, pMemDesc, vAddr, gfid) kbusUnmapCpuInvisibleBar2Aperture_DISPATCH(pGpu, pKernelBus, pMemDesc, vAddr, gfid) +#define kbusUnmapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, vAddr, gfid) kbusUnmapCpuInvisibleBar2Aperture_DISPATCH(pGpu, pKernelBus, pMemDesc, vAddr, gfid) #define kbusTeardownBar2CpuAperture(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_DISPATCH(pGpu, pKernelBus, gfid) #define kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, gfid) kbusTeardownBar2CpuAperture_DISPATCH(pGpu, pKernelBus, gfid) #define kbusGetP2PWriteMailboxAddressSize(pGpu) kbusGetP2PWriteMailboxAddressSize_STATIC_DISPATCH(pGpu) @@ -511,6 +588,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusGetEgmPeerId_HAL(pLocalGpu, pLocalKernelBus, pRemoteGpu) kbusGetEgmPeerId_DISPATCH(pLocalGpu, pLocalKernelBus, pRemoteGpu) #define kbusGetPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) #define kbusGetPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) +#define kbusGetNvlinkPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetNvlinkPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) +#define kbusGetNvlinkPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetNvlinkPeerId_DISPATCH(pGpu, pKernelBus, pPeerGpu) #define kbusGetNvSwitchPeerId(pGpu, pKernelBus) kbusGetNvSwitchPeerId_DISPATCH(pGpu, pKernelBus) #define kbusGetNvSwitchPeerId_HAL(pGpu, pKernelBus) kbusGetNvSwitchPeerId_DISPATCH(pGpu, pKernelBus) #define kbusGetUnusedPciePeerId(pGpu, pKernelBus) kbusGetUnusedPciePeerId_DISPATCH(pGpu, pKernelBus) @@ -581,6 +660,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusSetupUnbindFla_HAL(pGpu, pKernelBus) kbusSetupUnbindFla_DISPATCH(pGpu, pKernelBus) #define kbusSetupBindFla(pGpu, pKernelBus, gfid) kbusSetupBindFla_DISPATCH(pGpu, pKernelBus, gfid) #define kbusSetupBindFla_HAL(pGpu, pKernelBus, gfid) kbusSetupBindFla_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusSendSysmembarSingle(pGpu, pKernelBus) kbusSendSysmembarSingle_DISPATCH(pGpu, pKernelBus) +#define kbusSendSysmembarSingle_HAL(pGpu, pKernelBus) kbusSendSysmembarSingle_DISPATCH(pGpu, pKernelBus) #define kbusCacheBAR1ResizeSize_WAR_BUG_3249028(pGpu, pKernelBus) kbusCacheBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(pGpu, pKernelBus) #define kbusCacheBAR1ResizeSize_WAR_BUG_3249028_HAL(pGpu, pKernelBus) kbusCacheBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(pGpu, pKernelBus) #define kbusRestoreBAR1ResizeSize_WAR_BUG_3249028(pGpu, pKernelBus) kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_DISPATCH(pGpu, pKernelBus) @@ -589,6 +670,8 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusIsDirectMappingAllowed_HAL(pGpu, pKernelBus, arg0, arg1, arg2) kbusIsDirectMappingAllowed_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2) #define kbusUseDirectSysmemMap(pGpu, pKernelBus, arg0, arg1) kbusUseDirectSysmemMap_DISPATCH(pGpu, pKernelBus, arg0, arg1) #define kbusUseDirectSysmemMap_HAL(pGpu, pKernelBus, arg0, arg1) kbusUseDirectSysmemMap_DISPATCH(pGpu, pKernelBus, arg0, arg1) +#define kbusMemCopyBar0Window(pGpu, pKernelBus, physAddr, pData, copySize, bRead) kbusMemCopyBar0Window_DISPATCH(pGpu, pKernelBus, physAddr, pData, copySize, bRead) +#define kbusMemCopyBar0Window_HAL(pGpu, pKernelBus, physAddr, pData, copySize, bRead) kbusMemCopyBar0Window_DISPATCH(pGpu, pKernelBus, physAddr, pData, copySize, bRead) #define kbusWriteBAR0WindowBase(pGpu, pKernelBus, base) kbusWriteBAR0WindowBase_DISPATCH(pGpu, pKernelBus, base) #define kbusWriteBAR0WindowBase_HAL(pGpu, pKernelBus, base) kbusWriteBAR0WindowBase_DISPATCH(pGpu, pKernelBus, base) #define kbusReadBAR0WindowBase(pGpu, pKernelBus) kbusReadBAR0WindowBase_DISPATCH(pGpu, pKernelBus) @@ -599,10 +682,40 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, vidOffset) kbusSetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus, vidOffset) #define kbusGetBAR0WindowVidOffset(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus) #define kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus) kbusGetBAR0WindowVidOffset_DISPATCH(pGpu, pKernelBus) +#define kbusSetupBar0WindowBeforeBar2Bootstrap(pGpu, pKernelBus, arg0) kbusSetupBar0WindowBeforeBar2Bootstrap_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusSetupBar0WindowBeforeBar2Bootstrap_HAL(pGpu, pKernelBus, arg0) kbusSetupBar0WindowBeforeBar2Bootstrap_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusRestoreBar0WindowAfterBar2Bootstrap(pGpu, pKernelBus, arg0) kbusRestoreBar0WindowAfterBar2Bootstrap_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusRestoreBar0WindowAfterBar2Bootstrap_HAL(pGpu, pKernelBus, arg0) kbusRestoreBar0WindowAfterBar2Bootstrap_DISPATCH(pGpu, pKernelBus, arg0) #define kbusVerifyBar2(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_DISPATCH(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) #define kbusVerifyBar2_HAL(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) kbusVerifyBar2_DISPATCH(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size) +#define kbusBar2BootStrapInPhysicalMode(pGpu, pKernelBus) kbusBar2BootStrapInPhysicalMode_DISPATCH(pGpu, pKernelBus) +#define kbusBar2BootStrapInPhysicalMode_HAL(pGpu, pKernelBus) kbusBar2BootStrapInPhysicalMode_DISPATCH(pGpu, pKernelBus) +#define kbusBindBar2(pGpu, pKernelBus, arg0) kbusBindBar2_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusBindBar2_HAL(pGpu, pKernelBus, arg0) kbusBindBar2_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusInstBlkWriteAddrLimit(pGpu, pKernelBus, arg0, arg1, arg2, arg3) kbusInstBlkWriteAddrLimit_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2, arg3) +#define kbusInstBlkWriteAddrLimit_HAL(pGpu, pKernelBus, arg0, arg1, arg2, arg3) kbusInstBlkWriteAddrLimit_DISPATCH(pGpu, pKernelBus, arg0, arg1, arg2, arg3) +#define kbusInitInstBlk(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) kbusInitInstBlk_DISPATCH(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) +#define kbusInitInstBlk_HAL(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) kbusInitInstBlk_DISPATCH(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) +#define kbusBar2InstBlkWrite(pGpu, pKernelBus, pMap, pPDB, vaLimit, bigPageSize) kbusBar2InstBlkWrite_DISPATCH(pGpu, pKernelBus, pMap, pPDB, vaLimit, bigPageSize) +#define kbusBar2InstBlkWrite_HAL(pGpu, pKernelBus, pMap, pPDB, vaLimit, bigPageSize) kbusBar2InstBlkWrite_DISPATCH(pGpu, pKernelBus, pMap, pPDB, vaLimit, bigPageSize) +#define kbusSetupBar2PageTablesAtBottomOfFb(pGpu, pKernelBus, gfid) kbusSetupBar2PageTablesAtBottomOfFb_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusSetupBar2PageTablesAtBottomOfFb_HAL(pGpu, pKernelBus, gfid) kbusSetupBar2PageTablesAtBottomOfFb_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusTeardownBar2PageTablesAtBottomOfFb(pGpu, pKernelBus, gfid) kbusTeardownBar2PageTablesAtBottomOfFb_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusTeardownBar2PageTablesAtBottomOfFb_HAL(pGpu, pKernelBus, gfid) kbusTeardownBar2PageTablesAtBottomOfFb_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusSetupBar2InstBlkAtBottomOfFb(pGpu, pKernelBus, pPDB, vaLimit, bigPageSize, gfid) kbusSetupBar2InstBlkAtBottomOfFb_DISPATCH(pGpu, pKernelBus, pPDB, vaLimit, bigPageSize, gfid) +#define kbusSetupBar2InstBlkAtBottomOfFb_HAL(pGpu, pKernelBus, pPDB, vaLimit, bigPageSize, gfid) kbusSetupBar2InstBlkAtBottomOfFb_DISPATCH(pGpu, pKernelBus, pPDB, vaLimit, bigPageSize, gfid) +#define kbusTeardownBar2InstBlkAtBottomOfFb(pGpu, pKernelBus, gfid) kbusTeardownBar2InstBlkAtBottomOfFb_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusTeardownBar2InstBlkAtBottomOfFb_HAL(pGpu, pKernelBus, gfid) kbusTeardownBar2InstBlkAtBottomOfFb_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusSetupBar2PageTablesAtTopOfFb(pGpu, pKernelBus, gfid) kbusSetupBar2PageTablesAtTopOfFb_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusSetupBar2PageTablesAtTopOfFb_HAL(pGpu, pKernelBus, gfid) kbusSetupBar2PageTablesAtTopOfFb_DISPATCH(pGpu, pKernelBus, gfid) +#define kbusCommitBar2PDEs(pGpu, pKernelBus) kbusCommitBar2PDEs_DISPATCH(pGpu, pKernelBus) +#define kbusCommitBar2PDEs_HAL(pGpu, pKernelBus) kbusCommitBar2PDEs_DISPATCH(pGpu, pKernelBus) #define kbusVerifyCoherentLink(pGpu, pKernelBus) kbusVerifyCoherentLink_DISPATCH(pGpu, pKernelBus) #define kbusVerifyCoherentLink_HAL(pGpu, pKernelBus) kbusVerifyCoherentLink_DISPATCH(pGpu, pKernelBus) +#define kbusTeardownMailbox(pGpu, pKernelBus) kbusTeardownMailbox_DISPATCH(pGpu, pKernelBus) +#define kbusTeardownMailbox_HAL(pGpu, pKernelBus) kbusTeardownMailbox_DISPATCH(pGpu, pKernelBus) +#define kbusBar1InstBlkVasUpdate(pGpu, pKernelBus) kbusBar1InstBlkVasUpdate_DISPATCH(pGpu, pKernelBus) +#define kbusBar1InstBlkVasUpdate_HAL(pGpu, pKernelBus) kbusBar1InstBlkVasUpdate_DISPATCH(pGpu, pKernelBus) #define kbusFlushPcieForBar0Doorbell(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_DISPATCH(pGpu, pKernelBus) #define kbusFlushPcieForBar0Doorbell_HAL(pGpu, pKernelBus) kbusFlushPcieForBar0Doorbell_DISPATCH(pGpu, pKernelBus) #define kbusCreateCoherentCpuMapping(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) kbusCreateCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, numaOnlineMemorySize, bFlush) @@ -613,37 +726,43 @@ NV_STATUS __nvoc_objCreate_KernelBus(KernelBus**, Dynamic*, NvU32); #define kbusUnmapCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusUnmapCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) #define kbusTeardownCoherentCpuMapping_HAL(pGpu, pKernelBus, arg0) kbusTeardownCoherentCpuMapping_DISPATCH(pGpu, pKernelBus, arg0) +#define kbusBar1InstBlkBind(pGpu, pKernelBus) kbusBar1InstBlkBind_DISPATCH(pGpu, pKernelBus) +#define kbusBar1InstBlkBind_HAL(pGpu, pKernelBus) kbusBar1InstBlkBind_DISPATCH(pGpu, pKernelBus) +#define kbusGetEccCounts(pGpu, pKernelBus) kbusGetEccCounts_DISPATCH(pGpu, pKernelBus) +#define kbusGetEccCounts_HAL(pGpu, pKernelBus) kbusGetEccCounts_DISPATCH(pGpu, pKernelBus) +#define kbusClearEccCounts(pGpu, pKernelBus) kbusClearEccCounts_DISPATCH(pGpu, pKernelBus) +#define kbusClearEccCounts_HAL(pGpu, pKernelBus) kbusClearEccCounts_DISPATCH(pGpu, pKernelBus) #define kbusStateInitUnlocked(pGpu, pEngstate) kbusStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbusInitMissing(pGpu, pEngstate) kbusInitMissing_DISPATCH(pGpu, pEngstate) #define kbusStatePreInitUnlocked(pGpu, pEngstate) kbusStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kbusIsPresent(pGpu, pEngstate) kbusIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS kbusInitBarsSize_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); +NV_STATUS kbusConstructHal_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitBarsSize(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NV_STATUS kbusConstructHal(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusInitBarsSize(pGpu, pKernelBus) kbusInitBarsSize_KERNEL(pGpu, pKernelBus) +#define kbusConstructHal(pGpu, pKernelBus) kbusConstructHal_GM107(pGpu, pKernelBus) #endif //__nvoc_kern_bus_h_disabled -#define kbusInitBarsSize_HAL(pGpu, pKernelBus) kbusInitBarsSize(pGpu, pKernelBus) +#define kbusConstructHal_HAL(pGpu, pKernelBus) kbusConstructHal(pGpu, pKernelBus) -NV_STATUS kbusConstructHal_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvU64 kbusGetBar1ResvdVA_TU102(struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusConstructHal(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvU64 kbusGetBar1ResvdVA(struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return 0; } #else //__nvoc_kern_bus_h_disabled -#define kbusConstructHal(pGpu, pKernelBus) kbusConstructHal_GM107(pGpu, pKernelBus) +#define kbusGetBar1ResvdVA(pKernelBus) kbusGetBar1ResvdVA_TU102(pKernelBus) #endif //__nvoc_kern_bus_h_disabled -#define kbusConstructHal_HAL(pGpu, pKernelBus) kbusConstructHal(pGpu, pKernelBus) +#define kbusGetBar1ResvdVA_HAL(pKernelBus) kbusGetBar1ResvdVA(pKernelBus) NV_STATUS kbusStateInitLockedKernel_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); @@ -677,52 +796,33 @@ static inline NV_STATUS kbusStateInitLockedPhysical(struct OBJGPU *pGpu, struct #define kbusStateInitLockedPhysical_HAL(pGpu, pKernelBus) kbusStateInitLockedPhysical(pGpu, pKernelBus) -NvU8 *kbusMapBar2Aperture_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); - -NvU8 *kbusMapBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvU8 *kbusMapBar2Aperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NULL; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusMapBar2Aperture(pGpu, pKernelBus, pMemDesc, transfer_flags) kbusMapBar2Aperture_VBAR2(pGpu, pKernelBus, pMemDesc, transfer_flags) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusMapBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, transfer_flags) kbusMapBar2Aperture(pGpu, pKernelBus, pMemDesc, transfer_flags) - -NvU8 *kbusValidateBar2ApertureMapping_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); - -NvU8 *kbusValidateBar2ApertureMapping_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); +NV_STATUS kbusMemoryCopy_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, PMEMORY_DESCRIPTOR arg2, NvU64 arg3, NvU64 arg4); #ifdef __nvoc_kern_bus_h_disabled -static inline NvU8 *kbusValidateBar2ApertureMapping(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p) { +static inline NV_STATUS kbusMemoryCopy(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, PMEMORY_DESCRIPTOR arg2, NvU64 arg3, NvU64 arg4) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NULL; + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusValidateBar2ApertureMapping(pGpu, pKernelBus, pMemDesc, p) kbusValidateBar2ApertureMapping_VBAR2(pGpu, pKernelBus, pMemDesc, p) +#define kbusMemoryCopy(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4) kbusMemoryCopy_GM107(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4) #endif //__nvoc_kern_bus_h_disabled -#define kbusValidateBar2ApertureMapping_HAL(pGpu, pKernelBus, pMemDesc, p) kbusValidateBar2ApertureMapping(pGpu, pKernelBus, pMemDesc, p) - -void kbusUnmapBar2ApertureWithFlags_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); +#define kbusMemoryCopy_HAL(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4) kbusMemoryCopy(pGpu, pKernelBus, arg0, arg1, arg2, arg3, arg4) -void kbusUnmapBar2ApertureWithFlags_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); +NV_STATUS kbusPrepareForXVEReset_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline void kbusUnmapBar2ApertureWithFlags(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags) { +static inline NV_STATUS kbusPrepareForXVEReset(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kern_bus_h_disabled -#define kbusUnmapBar2ApertureWithFlags(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) kbusUnmapBar2ApertureWithFlags_VBAR2(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) +#define kbusPrepareForXVEReset(pGpu, pKernelBus) kbusPrepareForXVEReset_GM107(pGpu, pKernelBus) #endif //__nvoc_kern_bus_h_disabled -#define kbusUnmapBar2ApertureWithFlags_HAL(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) kbusUnmapBar2ApertureWithFlags(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags) +#define kbusPrepareForXVEReset_HAL(pGpu, pKernelBus) kbusPrepareForXVEReset(pGpu, pKernelBus) NV_STATUS kbusUpdateRmAperture_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR arg0, NvU64 arg1, NvU64 arg2, NvU32 arg3); @@ -794,35 +894,23 @@ static inline NvU32 kbusGetSizeOfBar2PageDirs(struct OBJGPU *pGpu, struct Kernel #define kbusGetSizeOfBar2PageDirs_HAL(pGpu, pKernelBus) kbusGetSizeOfBar2PageDirs(pGpu, pKernelBus) -NvU64 kbusGetVaLimitForBar2_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); - -NvU64 kbusGetVaLimitForBar2_PHYSICAL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvU64 kbusGetVaLimitForBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return 0; +static inline NvU64 kbusGetCpuInvisibleBar2BaseAdjust_cb032a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return 0ULL; } -#else //__nvoc_kern_bus_h_disabled -#define kbusGetVaLimitForBar2(pGpu, pKernelBus) kbusGetVaLimitForBar2_KERNEL(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled -#define kbusGetVaLimitForBar2_HAL(pGpu, pKernelBus) kbusGetVaLimitForBar2(pGpu, pKernelBus) - -NV_STATUS kbusCommitBar2_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); +NvU64 kbusGetCpuInvisibleBar2BaseAdjust_TU102(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusCommitBar2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { +static inline NvU64 kbusGetCpuInvisibleBar2BaseAdjust(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return 0; } #else //__nvoc_kern_bus_h_disabled -#define kbusCommitBar2(pGpu, pKernelBus, flags) kbusCommitBar2_KERNEL(pGpu, pKernelBus, flags) +#define kbusGetCpuInvisibleBar2BaseAdjust(pGpu, pKernelBus) kbusGetCpuInvisibleBar2BaseAdjust_cb032a(pGpu, pKernelBus) #endif //__nvoc_kern_bus_h_disabled -#define kbusCommitBar2_HAL(pGpu, pKernelBus, flags) kbusCommitBar2(pGpu, pKernelBus, flags) +#define kbusGetCpuInvisibleBar2BaseAdjust_HAL(pGpu, pKernelBus) kbusGetCpuInvisibleBar2BaseAdjust(pGpu, pKernelBus) MMU_WALK *kbusGetBar2GmmuWalker_GM107(struct KernelBus *pKernelBus); @@ -852,34 +940,6 @@ static inline const struct GMMU_FMT *kbusGetBar2GmmuFmt(struct KernelBus *pKerne #define kbusGetBar2GmmuFmt_HAL(pKernelBus) kbusGetBar2GmmuFmt(pKernelBus) -NV_STATUS kbusPatchBar1Pdb_GSPCLIENT(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusPatchBar1Pdb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusPatchBar1Pdb(pGpu, pKernelBus) kbusPatchBar1Pdb_GSPCLIENT(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusPatchBar1Pdb_HAL(pGpu, pKernelBus) kbusPatchBar1Pdb(pGpu, pKernelBus) - -NV_STATUS kbusPatchBar2Pdb_GSPCLIENT(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusPatchBar2Pdb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusPatchBar2Pdb(pGpu, pKernelBus) kbusPatchBar2Pdb_GSPCLIENT(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusPatchBar2Pdb_HAL(pGpu, pKernelBus) kbusPatchBar2Pdb(pGpu, pKernelBus) - NV_STATUS kbusSetBarsApertureSize_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); @@ -976,59 +1036,6 @@ static inline NV_STATUS kbusConstructVirtualBar2CpuVisibleHeap(struct KernelBus #define kbusConstructVirtualBar2CpuVisibleHeap_HAL(pKernelBus, gfid) kbusConstructVirtualBar2CpuVisibleHeap(pKernelBus, gfid) -static inline NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap_56cd7a(struct KernelBus *pKernelBus, NvU32 gfid) { - return NV_OK; -} - -NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap_VBAR2(struct KernelBus *pKernelBus, NvU32 gfid); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap(struct KernelBus *pKernelBus, NvU32 gfid) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusConstructVirtualBar2CpuInvisibleHeap(pKernelBus, gfid) kbusConstructVirtualBar2CpuInvisibleHeap_56cd7a(pKernelBus, gfid) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusConstructVirtualBar2CpuInvisibleHeap_HAL(pKernelBus, gfid) kbusConstructVirtualBar2CpuInvisibleHeap(pKernelBus, gfid) - -static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture_46f6a7(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS kbusMapCpuInvisibleBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusMapCpuInvisibleBar2Aperture(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) kbusMapCpuInvisibleBar2Aperture_46f6a7(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusMapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) kbusMapCpuInvisibleBar2Aperture(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid) - -static inline void kbusUnmapCpuInvisibleBar2Aperture_b3696a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { - return; -} - -void kbusUnmapCpuInvisibleBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline void kbusUnmapCpuInvisibleBar2Aperture(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); -} -#else //__nvoc_kern_bus_h_disabled -#define kbusUnmapCpuInvisibleBar2Aperture(pGpu, pKernelBus, pMemDesc, vAddr, gfid) kbusUnmapCpuInvisibleBar2Aperture_b3696a(pGpu, pKernelBus, pMemDesc, vAddr, gfid) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusUnmapCpuInvisibleBar2Aperture_HAL(pGpu, pKernelBus, pMemDesc, vAddr, gfid) kbusUnmapCpuInvisibleBar2Aperture(pGpu, pKernelBus, pMemDesc, vAddr, gfid) - NV_STATUS kbusSetupCpuPointerForBusFlush_GV100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); @@ -1140,24 +1147,6 @@ static inline void kbusDestroyPeerAccess(struct OBJGPU *pGpu, struct KernelBus * #define kbusDestroyPeerAccess_HAL(pGpu, pKernelBus, peerNum) kbusDestroyPeerAccess(pGpu, pKernelBus, peerNum) -NvU32 kbusGetNvlinkPeerId_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu); - -static inline NvU32 kbusGetNvlinkPeerId_c732fb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu) { - return 4294967295U; -} - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NvU32 kbusGetNvlinkPeerId(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return 0; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusGetNvlinkPeerId(pGpu, pKernelBus, pPeerGpu) kbusGetNvlinkPeerId_c732fb(pGpu, pKernelBus, pPeerGpu) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusGetNvlinkPeerId_HAL(pGpu, pKernelBus, pPeerGpu) kbusGetNvlinkPeerId(pGpu, pKernelBus, pPeerGpu) - NvU32 kbusGetPeerIdFromTable_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 locPeerIdx, NvU32 remPeerIdx); @@ -1310,20 +1299,6 @@ static inline NV_STATUS kbusFlushSingle(struct OBJGPU *pGpu, struct KernelBus *p #define kbusFlushSingle_HAL(pGpu, pKernelBus, flags) kbusFlushSingle(pGpu, pKernelBus, flags) -NV_STATUS kbusSendSysmembarSingle_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSendSysmembarSingle(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusSendSysmembarSingle(pGpu, pKernelBus) kbusSendSysmembarSingle_KERNEL(pGpu, pKernelBus) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusSendSysmembarSingle_HAL(pGpu, pKernelBus) kbusSendSysmembarSingle(pGpu, pKernelBus) - void kbusInitPciBars_GM107(struct KernelBus *pKernelBus); @@ -1365,20 +1340,6 @@ static inline NV_STATUS kbusMemAccessBar0Window(struct OBJGPU *pGpu, struct Kern #define kbusMemAccessBar0Window_HAL(pGpu, pKernelBus, physAddr, pData, accessSize, bRead, addrSpace) kbusMemAccessBar0Window(pGpu, pKernelBus, physAddr, pData, accessSize, bRead, addrSpace) -NV_STATUS kbusMemCopyBar0Window_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusMemCopyBar0Window(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusMemCopyBar0Window(pGpu, pKernelBus, physAddr, pData, copySize, bRead) kbusMemCopyBar0Window_GM107(pGpu, pKernelBus, physAddr, pData, copySize, bRead) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusMemCopyBar0Window_HAL(pGpu, pKernelBus, physAddr, pData, copySize, bRead) kbusMemCopyBar0Window(pGpu, pKernelBus, physAddr, pData, copySize, bRead) - NvU64 kbusGetBAR0WindowAddress_GM107(struct KernelBus *pKernelBus); @@ -1393,33 +1354,6 @@ static inline NvU64 kbusGetBAR0WindowAddress(struct KernelBus *pKernelBus) { #define kbusGetBAR0WindowAddress_HAL(pKernelBus) kbusGetBAR0WindowAddress(pKernelBus) -NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusSetupBar0WindowBeforeBar2Bootstrap(pGpu, pKernelBus, arg0) kbusSetupBar0WindowBeforeBar2Bootstrap_GM107(pGpu, pKernelBus, arg0) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusSetupBar0WindowBeforeBar2Bootstrap_HAL(pGpu, pKernelBus, arg0) kbusSetupBar0WindowBeforeBar2Bootstrap(pGpu, pKernelBus, arg0) - -void kbusRestoreBar0WindowAfterBar2Bootstrap_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0); - - -#ifdef __nvoc_kern_bus_h_disabled -static inline void kbusRestoreBar0WindowAfterBar2Bootstrap(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); -} -#else //__nvoc_kern_bus_h_disabled -#define kbusRestoreBar0WindowAfterBar2Bootstrap(pGpu, pKernelBus, arg0) kbusRestoreBar0WindowAfterBar2Bootstrap_GM107(pGpu, pKernelBus, arg0) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusRestoreBar0WindowAfterBar2Bootstrap_HAL(pGpu, pKernelBus, arg0) kbusRestoreBar0WindowAfterBar2Bootstrap(pGpu, pKernelBus, arg0) - NV_STATUS kbusInitBar2_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); @@ -1545,53 +1479,33 @@ static inline struct OBJVASPACE *kbusGetBar1VASpace(struct OBJGPU *pGpu, struct #define kbusGetBar1VASpace_HAL(pGpu, pKernelBus) kbusGetBar1VASpace(pGpu, pKernelBus) -static inline NV_STATUS kbusInitInstBlk_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { - return NV_OK; -} - - -#ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusInitInstBlk(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { - NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_bus_h_disabled -#define kbusInitInstBlk(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) kbusInitInstBlk_56cd7a(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) -#endif //__nvoc_kern_bus_h_disabled - -#define kbusInitInstBlk_HAL(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) kbusInitInstBlk(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS) - -static inline NV_STATUS kbusBar1InstBlkVasUpdate_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { - return NV_OK; -} - -NV_STATUS kbusBar1InstBlkVasUpdate_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); +NvBool kbusCheckEngine_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc); #ifdef __nvoc_kern_bus_h_disabled -static inline NV_STATUS kbusBar1InstBlkVasUpdate(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { +static inline NvBool kbusCheckEngine(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return NV_FALSE; } #else //__nvoc_kern_bus_h_disabled -#define kbusBar1InstBlkVasUpdate(pGpu, pKernelBus) kbusBar1InstBlkVasUpdate_56cd7a(pGpu, pKernelBus) +#define kbusCheckEngine(pGpu, pKernelBus, desc) kbusCheckEngine_KERNEL(pGpu, pKernelBus, desc) #endif //__nvoc_kern_bus_h_disabled -#define kbusBar1InstBlkVasUpdate_HAL(pGpu, pKernelBus) kbusBar1InstBlkVasUpdate(pGpu, pKernelBus) +#define kbusCheckEngine_HAL(pGpu, pKernelBus, desc) kbusCheckEngine(pGpu, pKernelBus, desc) -NvBool kbusCheckEngine_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc); +NvBool kbusCheckEngineWithOrderList_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc, NvBool bCheckEngineOrder); #ifdef __nvoc_kern_bus_h_disabled -static inline NvBool kbusCheckEngine(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc) { +static inline NvBool kbusCheckEngineWithOrderList(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR desc, NvBool bCheckEngineOrder) { NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); return NV_FALSE; } #else //__nvoc_kern_bus_h_disabled -#define kbusCheckEngine(pGpu, pKernelBus, desc) kbusCheckEngine_KERNEL(pGpu, pKernelBus, desc) +#define kbusCheckEngineWithOrderList(pGpu, pKernelBus, desc, bCheckEngineOrder) kbusCheckEngineWithOrderList_KERNEL(pGpu, pKernelBus, desc, bCheckEngineOrder) #endif //__nvoc_kern_bus_h_disabled -#define kbusCheckEngine_HAL(pGpu, pKernelBus, desc) kbusCheckEngine(pGpu, pKernelBus, desc) +#define kbusCheckEngineWithOrderList_HAL(pGpu, pKernelBus, desc, bCheckEngineOrder) kbusCheckEngineWithOrderList(pGpu, pKernelBus, desc, bCheckEngineOrder) NV_STATUS kbusFlush_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); @@ -1622,6 +1536,14 @@ static inline void kbusTeardownCoherentCpuMappingAcr(struct OBJGPU *pGpu, struct #define kbusTeardownCoherentCpuMappingAcr_HAL(pGpu, pKernelBus) kbusTeardownCoherentCpuMappingAcr(pGpu, pKernelBus) +NV_STATUS kbusInitBarsSize_VGPUSTUB(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +NV_STATUS kbusInitBarsSize_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusInitBarsSize_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusInitBarsSize__(pGpu, pKernelBus); +} + NV_STATUS kbusConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR arg0); static inline NV_STATUS kbusConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, ENGDESCRIPTOR arg0) { @@ -1682,6 +1604,128 @@ static inline void kbusStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct KernelB pKernelBus->__kbusStateDestroy__(pGpu, pKernelBus); } +NvU8 *kbusMapBar2Aperture_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); + +NvU8 *kbusMapBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags); + +static inline NvU8 *kbusMapBar2Aperture_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU32 transfer_flags) { + return pKernelBus->__kbusMapBar2Aperture__(pGpu, pKernelBus, pMemDesc, transfer_flags); +} + +NvU8 *kbusValidateBar2ApertureMapping_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); + +NvU8 *kbusValidateBar2ApertureMapping_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p); + +static inline NvU8 *kbusValidateBar2ApertureMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 *p) { + return pKernelBus->__kbusValidateBar2ApertureMapping__(pGpu, pKernelBus, pMemDesc, p); +} + +void kbusUnmapBar2ApertureWithFlags_VBAR2_SRIOV(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); + +void kbusUnmapBar2ApertureWithFlags_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags); + +static inline void kbusUnmapBar2ApertureWithFlags_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU8 **pCpuPtr, NvU32 flags) { + pKernelBus->__kbusUnmapBar2ApertureWithFlags__(pGpu, pKernelBus, pMemDesc, pCpuPtr, flags); +} + +NvU64 kbusGetVaLimitForBar2_FWCLIENT(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +NvU64 kbusGetVaLimitForBar2_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvU64 kbusGetVaLimitForBar2_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusGetVaLimitForBar2__(pGpu, pKernelBus); +} + +static inline void kbusCalcCpuInvisibleBar2Range_f2d351(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); +} + +void kbusCalcCpuInvisibleBar2Range_GP100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline void kbusCalcCpuInvisibleBar2Range_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + pKernelBus->__kbusCalcCpuInvisibleBar2Range__(pGpu, pKernelBus, gfid); +} + +static inline NvU32 kbusCalcCpuInvisibleBar2ApertureSize_13cd8d(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + NV_ASSERT_PRECOMP(0); + return 0; +} + +NvU32 kbusCalcCpuInvisibleBar2ApertureSize_GV100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvU32 kbusCalcCpuInvisibleBar2ApertureSize_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusCalcCpuInvisibleBar2ApertureSize__(pGpu, pKernelBus); +} + +NV_STATUS kbusCommitBar2_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); + +NV_STATUS kbusCommitBar2_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags); + +static inline NV_STATUS kbusCommitBar2_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 flags) { + return pKernelBus->__kbusCommitBar2__(pGpu, pKernelBus, flags); +} + +static inline NV_STATUS kbusRewritePTEsForExistingMapping_92bfc3(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kbusRewritePTEsForExistingMapping_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc); + +static inline NV_STATUS kbusRewritePTEsForExistingMapping_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc) { + return pKernelBus->__kbusRewritePTEsForExistingMapping__(pGpu, pKernelBus, pMemDesc); +} + +NV_STATUS kbusPatchBar1Pdb_GSPCLIENT(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusPatchBar1Pdb_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +static inline NV_STATUS kbusPatchBar1Pdb_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusPatchBar1Pdb__(pGpu, pKernelBus); +} + +NV_STATUS kbusPatchBar2Pdb_GSPCLIENT(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusPatchBar2Pdb_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +static inline NV_STATUS kbusPatchBar2Pdb_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusPatchBar2Pdb__(pGpu, pKernelBus); +} + +static inline NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap_56cd7a(struct KernelBus *pKernelBus, NvU32 gfid) { + return NV_OK; +} + +NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap_VBAR2(struct KernelBus *pKernelBus, NvU32 gfid); + +static inline NV_STATUS kbusConstructVirtualBar2CpuInvisibleHeap_DISPATCH(struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusConstructVirtualBar2CpuInvisibleHeap__(pKernelBus, gfid); +} + +static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture_46f6a7(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kbusMapCpuInvisibleBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid); + +static inline NV_STATUS kbusMapCpuInvisibleBar2Aperture_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 *pVaddr, NvU64 allocSize, NvU32 allocFlags, NvU32 gfid) { + return pKernelBus->__kbusMapCpuInvisibleBar2Aperture__(pGpu, pKernelBus, pMemDesc, pVaddr, allocSize, allocFlags, gfid); +} + +static inline void kbusUnmapCpuInvisibleBar2Aperture_b3696a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { + return; +} + +void kbusUnmapCpuInvisibleBar2Aperture_VBAR2(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid); + +static inline void kbusUnmapCpuInvisibleBar2Aperture_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, MEMORY_DESCRIPTOR *pMemDesc, NvU64 vAddr, NvU32 gfid) { + pKernelBus->__kbusUnmapCpuInvisibleBar2Aperture__(pGpu, pKernelBus, pMemDesc, vAddr, gfid); +} + NV_STATUS kbusTeardownBar2CpuAperture_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); NV_STATUS kbusTeardownBar2CpuAperture_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); @@ -1740,6 +1784,16 @@ static inline NvU32 kbusGetPeerId_DISPATCH(struct OBJGPU *pGpu, struct KernelBus return pKernelBus->__kbusGetPeerId__(pGpu, pKernelBus, pPeerGpu); } +NvU32 kbusGetNvlinkPeerId_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu); + +static inline NvU32 kbusGetNvlinkPeerId_c732fb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu) { + return 4294967295U; +} + +static inline NvU32 kbusGetNvlinkPeerId_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, struct OBJGPU *pPeerGpu) { + return pKernelBus->__kbusGetNvlinkPeerId__(pGpu, pKernelBus, pPeerGpu); +} + NvU32 kbusGetNvSwitchPeerId_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); static inline NvU32 kbusGetNvSwitchPeerId_c732fb(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { @@ -1766,6 +1820,8 @@ static inline NV_STATUS kbusIsPeerIdValid_DISPATCH(struct OBJGPU *pGpu, struct K return pKernelBus->__kbusIsPeerIdValid__(pGpu, pKernelBus, peerId); } +NV_STATUS kbusGetNvlinkP2PPeerId_VGPU(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); + NV_STATUS kbusGetNvlinkP2PPeerId_GP100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); NV_STATUS kbusGetNvlinkP2PPeerId_GA100(struct OBJGPU *pGpu0, struct KernelBus *pKernelBus0, struct OBJGPU *pGpu1, struct KernelBus *pKernelBus1, NvU32 *nvlinkPeer, NvU32 attributes); @@ -2096,6 +2152,16 @@ static inline NV_STATUS kbusSetupBindFla_DISPATCH(struct OBJGPU *pGpu, struct Ke return pKernelBus->__kbusSetupBindFla__(pGpu, pKernelBus, gfid); } +static inline NV_STATUS kbusSendSysmembarSingle_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +NV_STATUS kbusSendSysmembarSingle_KERNEL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusSendSysmembarSingle_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusSendSysmembarSingle__(pGpu, pKernelBus); +} + void kbusCacheBAR1ResizeSize_WAR_BUG_3249028_GA100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); void kbusCacheBAR1ResizeSize_WAR_BUG_3249028_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); @@ -2136,6 +2202,16 @@ static inline NV_STATUS kbusUseDirectSysmemMap_DISPATCH(struct OBJGPU *pGpu, str return pKernelBus->__kbusUseDirectSysmemMap__(pGpu, pKernelBus, arg0, arg1); } +NV_STATUS kbusMemCopyBar0Window_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead); + +static inline NV_STATUS kbusMemCopyBar0Window_46f6a7(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbusMemCopyBar0Window_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, RmPhysAddr physAddr, void *pData, NvLength copySize, NvBool bRead) { + return pKernelBus->__kbusMemCopyBar0Window__(pGpu, pKernelBus, physAddr, pData, copySize, bRead); +} + NV_STATUS kbusWriteBAR0WindowBase_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base); static inline NV_STATUS kbusWriteBAR0WindowBase_395e98(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 base) { @@ -2168,6 +2244,10 @@ static inline NvBool kbusValidateBAR0WindowBase_DISPATCH(struct OBJGPU *pGpu, st return pKernelBus->__kbusValidateBAR0WindowBase__(pGpu, pKernelBus, base); } +static inline NV_STATUS kbusSetBAR0WindowVidOffset_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset) { + return NV_OK; +} + NV_STATUS kbusSetBAR0WindowVidOffset_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); NV_STATUS kbusSetBAR0WindowVidOffset_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 vidOffset); @@ -2184,6 +2264,30 @@ static inline NvU64 kbusGetBAR0WindowVidOffset_DISPATCH(struct OBJGPU *pGpu, str return pKernelBus->__kbusGetBAR0WindowVidOffset__(pGpu, pKernelBus); } +static inline NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0) { + return NV_OK; +} + +NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0); + +static inline NV_STATUS kbusSetupBar0WindowBeforeBar2Bootstrap_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 *arg0) { + return pKernelBus->__kbusSetupBar0WindowBeforeBar2Bootstrap__(pGpu, pKernelBus, arg0); +} + +static inline void kbusRestoreBar0WindowAfterBar2Bootstrap_b3696a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0) { + return; +} + +void kbusRestoreBar0WindowAfterBar2Bootstrap_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0); + +static inline void kbusRestoreBar0WindowAfterBar2Bootstrap_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU64 arg0) { + pKernelBus->__kbusRestoreBar0WindowAfterBar2Bootstrap__(pGpu, pKernelBus, arg0); +} + +static inline NV_STATUS kbusVerifyBar2_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size) { + return NV_OK; +} + NV_STATUS kbusVerifyBar2_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); NV_STATUS kbusVerifyBar2_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR memDescIn, NvU8 *pCpuPtrIn, NvU64 offset, NvU64 size); @@ -2192,6 +2296,140 @@ static inline NV_STATUS kbusVerifyBar2_DISPATCH(struct OBJGPU *pGpu, struct Kern return pKernelBus->__kbusVerifyBar2__(pGpu, pKernelBus, memDescIn, pCpuPtrIn, offset, size); } +NV_STATUS kbusBar2BootStrapInPhysicalMode_VGPUSTUB(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusBar2BootStrapInPhysicalMode_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +static inline NV_STATUS kbusBar2BootStrapInPhysicalMode_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusBar2BootStrapInPhysicalMode__(pGpu, pKernelBus); +} + +static inline NV_STATUS kbusBindBar2_5baef9(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, BAR2_MODE arg0) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +NV_STATUS kbusBindBar2_TU102(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, BAR2_MODE arg0); + +NV_STATUS kbusBindBar2_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, BAR2_MODE arg0); + +static inline NV_STATUS kbusBindBar2_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, BAR2_MODE arg0) { + return pKernelBus->__kbusBindBar2__(pGpu, pKernelBus, arg0); +} + +static inline void kbusInstBlkWriteAddrLimit_f2d351(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0, NvU64 arg1, NvU8 *arg2, NvU64 arg3) { + NV_ASSERT_PRECOMP(0); +} + +void kbusInstBlkWriteAddrLimit_GP100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0, NvU64 arg1, NvU8 *arg2, NvU64 arg3); + +static inline void kbusInstBlkWriteAddrLimit_b3696a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0, NvU64 arg1, NvU8 *arg2, NvU64 arg3) { + return; +} + +static inline void kbusInstBlkWriteAddrLimit_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvBool arg0, NvU64 arg1, NvU8 *arg2, NvU64 arg3) { + pKernelBus->__kbusInstBlkWriteAddrLimit__(pGpu, pKernelBus, arg0, arg1, arg2, arg3); +} + +static inline NV_STATUS kbusInitInstBlk_ac1694(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { + return NV_OK; +} + +NV_STATUS kbusInitInstBlk_GP100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS); + +static inline NV_STATUS kbusInitInstBlk_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pInstBlkMemDesc, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, struct OBJVASPACE *pVAS) { + return pKernelBus->__kbusInitInstBlk__(pGpu, pKernelBus, pInstBlkMemDesc, pPDB, vaLimit, bigPageSize, pVAS); +} + +static inline void kbusBar2InstBlkWrite_d44104(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pMap, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize) { + return; +} + +void kbusBar2InstBlkWrite_GP100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pMap, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize); + +static inline void kbusBar2InstBlkWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU8 *pMap, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize) { + pKernelBus->__kbusBar2InstBlkWrite__(pGpu, pKernelBus, pMap, pPDB, vaLimit, bigPageSize); +} + +static inline NV_STATUS kbusSetupBar2PageTablesAtBottomOfFb_22ba1e(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + { + return NV_ERR_NOT_SUPPORTED; + } +} + +NV_STATUS kbusSetupBar2PageTablesAtBottomOfFb_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline NV_STATUS kbusSetupBar2PageTablesAtBottomOfFb_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusSetupBar2PageTablesAtBottomOfFb__(pGpu, pKernelBus, gfid); +} + +static inline void kbusTeardownBar2PageTablesAtBottomOfFb_566dba(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + { + return; + } +} + +void kbusTeardownBar2PageTablesAtBottomOfFb_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline void kbusTeardownBar2PageTablesAtBottomOfFb_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + pKernelBus->__kbusTeardownBar2PageTablesAtBottomOfFb__(pGpu, pKernelBus, gfid); +} + +static inline NV_STATUS kbusSetupBar2InstBlkAtBottomOfFb_22ba1e(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + { + return NV_ERR_NOT_SUPPORTED; + } +} + +NV_STATUS kbusSetupBar2InstBlkAtBottomOfFb_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, NvU32 gfid); + +static inline NV_STATUS kbusSetupBar2InstBlkAtBottomOfFb_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, PMEMORY_DESCRIPTOR pPDB, NvU64 vaLimit, NvU64 bigPageSize, NvU32 gfid) { + return pKernelBus->__kbusSetupBar2InstBlkAtBottomOfFb__(pGpu, pKernelBus, pPDB, vaLimit, bigPageSize, gfid); +} + +static inline void kbusTeardownBar2InstBlkAtBottomOfFb_566dba(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + { + return; + } +} + +void kbusTeardownBar2InstBlkAtBottomOfFb_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline void kbusTeardownBar2InstBlkAtBottomOfFb_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + pKernelBus->__kbusTeardownBar2InstBlkAtBottomOfFb__(pGpu, pKernelBus, gfid); +} + +static inline NV_STATUS kbusSetupBar2PageTablesAtTopOfFb_22ba1e(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + { + return NV_ERR_NOT_SUPPORTED; + } +} + +NV_STATUS kbusSetupBar2PageTablesAtTopOfFb_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid); + +static inline NV_STATUS kbusSetupBar2PageTablesAtTopOfFb_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus, NvU32 gfid) { + return pKernelBus->__kbusSetupBar2PageTablesAtTopOfFb__(pGpu, pKernelBus, gfid); +} + +static inline NV_STATUS kbusCommitBar2PDEs_22ba1e(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + NV_ASSERT_PRECOMP(0); + { + return NV_ERR_NOT_SUPPORTED; + } +} + +NV_STATUS kbusCommitBar2PDEs_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusCommitBar2PDEs_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusCommitBar2PDEs__(pGpu, pKernelBus); +} + static inline NV_STATUS kbusVerifyCoherentLink_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { return NV_OK; } @@ -2202,6 +2440,24 @@ static inline NV_STATUS kbusVerifyCoherentLink_DISPATCH(struct OBJGPU *pGpu, str return pKernelBus->__kbusVerifyCoherentLink__(pGpu, pKernelBus); } +void kbusTeardownMailbox_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +void kbusTeardownMailbox_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline void kbusTeardownMailbox_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + pKernelBus->__kbusTeardownMailbox__(pGpu, pKernelBus); +} + +static inline NV_STATUS kbusBar1InstBlkVasUpdate_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return NV_OK; +} + +NV_STATUS kbusBar1InstBlkVasUpdate_GM107(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusBar1InstBlkVasUpdate_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusBar1InstBlkVasUpdate__(pGpu, pKernelBus); +} + NV_STATUS kbusFlushPcieForBar0Doorbell_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); static inline NV_STATUS kbusFlushPcieForBar0Doorbell_56cd7a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { @@ -2252,6 +2508,39 @@ static inline void kbusTeardownCoherentCpuMapping_DISPATCH(struct OBJGPU *pGpu, pKernelBus->__kbusTeardownCoherentCpuMapping__(pGpu, pKernelBus, arg0); } +static inline NV_STATUS kbusBar1InstBlkBind_92bfc3(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kbusBar1InstBlkBind_TU102(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +NV_STATUS kbusBar1InstBlkBind_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NV_STATUS kbusBar1InstBlkBind_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusBar1InstBlkBind__(pGpu, pKernelBus); +} + +NvU32 kbusGetEccCounts_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline NvU32 kbusGetEccCounts_4a4dee(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return 0; +} + +static inline NvU32 kbusGetEccCounts_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return pKernelBus->__kbusGetEccCounts__(pGpu, pKernelBus); +} + +void kbusClearEccCounts_GH100(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +static inline void kbusClearEccCounts_b3696a(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + return; +} + +static inline void kbusClearEccCounts_DISPATCH(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + pKernelBus->__kbusClearEccCounts__(pGpu, pKernelBus); +} + static inline NV_STATUS kbusStateInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelBus *pEngstate) { return pEngstate->__kbusStateInitUnlocked__(pGpu, pEngstate); } @@ -2505,6 +2794,17 @@ static inline NvU8 *kbusCpuOffsetInBar2WindowGet(struct OBJGPU *pGpu, struct Ker #define kbusCpuOffsetInBar2WindowGet(pGpu, pKernelBus, pMemDesc) kbusCpuOffsetInBar2WindowGet_IMPL(pGpu, pKernelBus, pMemDesc) #endif //__nvoc_kern_bus_h_disabled +NvU64 kbusGetVfBar0SizeBytes_IMPL(struct OBJGPU *pGpu, struct KernelBus *pKernelBus); + +#ifdef __nvoc_kern_bus_h_disabled +static inline NvU64 kbusGetVfBar0SizeBytes(struct OBJGPU *pGpu, struct KernelBus *pKernelBus) { + NV_ASSERT_FAILED_PRECOMP("KernelBus was disabled!"); + return 0; +} +#else //__nvoc_kern_bus_h_disabled +#define kbusGetVfBar0SizeBytes(pGpu, pKernelBus) kbusGetVfBar0SizeBytes_IMPL(pGpu, pKernelBus) +#endif //__nvoc_kern_bus_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kern_disp_nvoc.c b/src/nvidia/generated/g_kern_disp_nvoc.c index efd6798a82..9e3c275d43 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.c +++ b/src/nvidia/generated/g_kern_disp_nvoc.c @@ -99,7 +99,7 @@ static NV_STATUS __nvoc_thunk_KernelDisplay_engstateStateUnload(OBJGPU *pGpu, st return kdispStateUnload(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[168]) { +static void __nvoc_thunk_KernelDisplay_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelDisplay, IntrServiceRecord pRecords[171]) { kdispRegisterIntrService(pGpu, (struct KernelDisplay *)(((unsigned char *)pKernelDisplay) - __nvoc_rtti_KernelDisplay_IntrService.offset), pRecords); } @@ -179,13 +179,17 @@ void __nvoc_init_dataField_KernelDisplay(KernelDisplay *pThis, RmHalspecOwner *p PORT_UNREFERENCED_VARIABLE(dispIpHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KDISP_IS_MISSING - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->setProperty(pThis, PDB_PROP_KDISP_IS_MISSING, ((NvBool)(0 == 0))); + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { pThis->setProperty(pThis, PDB_PROP_KDISP_IS_MISSING, ((NvBool)(0 != 0))); } // NVOC Property Hal field -- PDB_PROP_KDISP_IMP_ENABLE - if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ && (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ )) + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ && (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000003UL) )) /* RmVariantHal: VF | PF_KERNEL_ONLY */ )) { pThis->setProperty(pThis, PDB_PROP_KDISP_IMP_ENABLE, ((NvBool)(0 == 0))); } @@ -389,6 +393,17 @@ static void __nvoc_init_funcTable_KernelDisplay_1(KernelDisplay *pThis, RmHalspe pThis->__kdispInitRegistryOverrides__ = &kdispInitRegistryOverrides_IMPL; } + // Hal function -- kdispGetPBTargetAperture + if (( ((dispIpHal_HalVarIdx >> 5) == 0UL) && ((1UL << (dispIpHal_HalVarIdx & 0x1f)) & 0x00004c00UL) )) /* DispIpHal: DISPv0400 | DISPv0401 | DISPv0404 */ + { + pThis->__kdispGetPBTargetAperture__ = &kdispGetPBTargetAperture_v03_00; + } + // default + else + { + pThis->__kdispGetPBTargetAperture__ = &kdispGetPBTargetAperture_15a734; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelDisplay_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_KernelDisplay_engstateStatePreInitLocked; @@ -442,23 +457,31 @@ void __nvoc_init_KernelDisplay(KernelDisplay *pThis, RmHalspecOwner *pRmhalspeco __nvoc_init_funcTable_KernelDisplay(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelDisplay *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelDisplay), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelDisplay)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelDisplay); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -476,16 +499,25 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay **ppThis, Dynamic *pParen status = __nvoc_ctor_KernelDisplay(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelDisplay_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelDisplay_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelDisplay)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kern_disp_nvoc.h b/src/nvidia/generated/g_kern_disp_nvoc.h index 86db29748c..0f702199c3 100644 --- a/src/nvidia/generated/g_kern_disp_nvoc.h +++ b/src/nvidia/generated/g_kern_disp_nvoc.h @@ -54,6 +54,11 @@ extern "C" { typedef NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS KernelDisplayStaticInfo; +typedef struct +{ + NvU32 kHeadVblankCount[OBJ_MAX_HEADS]; +} KernelDisplaySharedMem; + struct DispChannel; #ifndef __NVOC_CLASS_DispChannel_TYPEDEF__ @@ -87,11 +92,16 @@ typedef struct RgLineCallback RgLineCallback; * interfaces which do not manage the underlying Display hardware can be * managed by this object. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERN_DISP_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelDisplay { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -121,6 +131,7 @@ struct KernelDisplay { NV_STATUS (*__kdispGetRgScanLock__)(OBJGPU *, struct KernelDisplay *, NvU32, OBJGPU *, NvU32, NvBool *, NvU32 *, NvBool *, NvU32 *); NV_STATUS (*__kdispDetectSliLink__)(struct KernelDisplay *, OBJGPU *, OBJGPU *, NvU32, NvU32); void (*__kdispInitRegistryOverrides__)(OBJGPU *, struct KernelDisplay *); + NvU32 (*__kdispGetPBTargetAperture__)(OBJGPU *, struct KernelDisplay *, NvU32, NvU32); NV_STATUS (*__kdispServiceNotificationInterrupt__)(OBJGPU *, struct KernelDisplay *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kdispStatePreLoad__)(POBJGPU, struct KernelDisplay *, NvU32); NV_STATUS (*__kdispStatePostUnload__)(POBJGPU, struct KernelDisplay *, NvU32); @@ -148,6 +159,8 @@ struct KernelDisplay { NvHandle hInternalDevice; NvHandle hInternalSubdevice; NvHandle hDispCommonHandle; + MEMORY_DESCRIPTOR *pSharedMemDesc; + KernelDisplaySharedMem *pSharedData; }; #ifndef __NVOC_CLASS_KernelDisplay_TYPEDEF__ @@ -223,6 +236,8 @@ NV_STATUS __nvoc_objCreate_KernelDisplay(KernelDisplay**, Dynamic*, NvU32); #define kdispDetectSliLink_HAL(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) kdispDetectSliLink_DISPATCH(pKernelDisplay, pParentGpu, pChildGpu, ParentDrPort, ChildDrPort) #define kdispInitRegistryOverrides(pGpu, pKernelDisplay) kdispInitRegistryOverrides_DISPATCH(pGpu, pKernelDisplay) #define kdispInitRegistryOverrides_HAL(pGpu, pKernelDisplay) kdispInitRegistryOverrides_DISPATCH(pGpu, pKernelDisplay) +#define kdispGetPBTargetAperture(pGpu, pKernelDisplay, memAddrSpace, cacheSnoop) kdispGetPBTargetAperture_DISPATCH(pGpu, pKernelDisplay, memAddrSpace, cacheSnoop) +#define kdispGetPBTargetAperture_HAL(pGpu, pKernelDisplay, memAddrSpace, cacheSnoop) kdispGetPBTargetAperture_DISPATCH(pGpu, pKernelDisplay, memAddrSpace, cacheSnoop) #define kdispServiceNotificationInterrupt(pGpu, pIntrService, pParams) kdispServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kdispStatePreLoad(pGpu, pEngstate, arg0) kdispStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kdispStatePostUnload(pGpu, pEngstate, arg0) kdispStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -568,6 +583,33 @@ static inline void kdispDestroyCommonHandle(struct KernelDisplay *pKernelDisplay #define kdispDestroyCommonHandle_HAL(pKernelDisplay) kdispDestroyCommonHandle(pKernelDisplay) +NV_STATUS kdispAllocateSharedMem_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline NV_STATUS kdispAllocateSharedMem(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_disp_h_disabled +#define kdispAllocateSharedMem(pGpu, pKernelDisplay) kdispAllocateSharedMem_IMPL(pGpu, pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispAllocateSharedMem_HAL(pGpu, pKernelDisplay) kdispAllocateSharedMem(pGpu, pKernelDisplay) + +void kdispFreeSharedMem_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay); + + +#ifdef __nvoc_kern_disp_h_disabled +static inline void kdispFreeSharedMem(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); +} +#else //__nvoc_kern_disp_h_disabled +#define kdispFreeSharedMem(pGpu, pKernelDisplay) kdispFreeSharedMem_IMPL(pGpu, pKernelDisplay) +#endif //__nvoc_kern_disp_h_disabled + +#define kdispFreeSharedMem_HAL(pGpu, pKernelDisplay) kdispFreeSharedMem(pGpu, pKernelDisplay) + NV_STATUS kdispConstructEngine_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, ENGDESCRIPTOR engDesc); static inline NV_STATUS kdispConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, ENGDESCRIPTOR engDesc) { @@ -604,9 +646,9 @@ static inline NV_STATUS kdispStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelDis return pKernelDisplay->__kdispStateUnload__(pGpu, pKernelDisplay, flags); } -void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[168]); +void kdispRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[171]); -static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[168]) { +static inline void kdispRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, IntrServiceRecord pRecords[171]) { pKernelDisplay->__kdispRegisterIntrService__(pGpu, pKernelDisplay, pRecords); } @@ -753,6 +795,16 @@ static inline void kdispInitRegistryOverrides_DISPATCH(OBJGPU *pGpu, struct Kern pKernelDisplay->__kdispInitRegistryOverrides__(pGpu, pKernelDisplay); } +NvU32 kdispGetPBTargetAperture_v03_00(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 memAddrSpace, NvU32 cacheSnoop); + +static inline NvU32 kdispGetPBTargetAperture_15a734(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 memAddrSpace, NvU32 cacheSnoop) { + return 0U; +} + +static inline NvU32 kdispGetPBTargetAperture_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 memAddrSpace, NvU32 cacheSnoop) { + return pKernelDisplay->__kdispGetPBTargetAperture__(pGpu, pKernelDisplay, memAddrSpace, cacheSnoop); +} + static inline NV_STATUS kdispServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelDisplay *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { return pIntrService->__kdispServiceNotificationInterrupt__(pGpu, pIntrService, pParams); } @@ -828,6 +880,16 @@ static inline NV_STATUS kdispGetIntChnClsForHwCls(struct KernelDisplay *pKernelD #define kdispGetIntChnClsForHwCls(pKernelDisplay, hwClass, pDispChnClass) kdispGetIntChnClsForHwCls_IMPL(pKernelDisplay, hwClass, pDispChnClass) #endif //__nvoc_kern_disp_h_disabled +void kdispNotifyCommonEvent_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 notifyIndex, void *pNotifyParams); + +#ifdef __nvoc_kern_disp_h_disabled +static inline void kdispNotifyCommonEvent(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 notifyIndex, void *pNotifyParams) { + NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!"); +} +#else //__nvoc_kern_disp_h_disabled +#define kdispNotifyCommonEvent(pGpu, pKernelDisplay, notifyIndex, pNotifyParams) kdispNotifyCommonEvent_IMPL(pGpu, pKernelDisplay, notifyIndex, pNotifyParams) +#endif //__nvoc_kern_disp_h_disabled + void kdispNotifyEvent_IMPL(OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 notifyIndex, void *pNotifyParams, NvU32 notifyParamsSize, NvV32 info32, NvV16 info16); #ifdef __nvoc_kern_disp_h_disabled @@ -863,6 +925,15 @@ dispdeviceFillVgaSavedDisplayState( OBJGPU *pGpu, NvBool workspaceBaseValid ); +/*! PushBuffer Target Aperture Types */ +typedef enum +{ + IOVA, + PHYS_NVM, + PHYS_PCI, + PHYS_PCI_COHERENT +} PBTARGETAPERTURE; + static NV_INLINE struct KernelHead* kdispGetHead ( diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.c b/src/nvidia/generated/g_kern_fsp_nvoc.c index 763ecadd07..648e5807d6 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.c +++ b/src/nvidia/generated/g_kern_fsp_nvoc.c @@ -158,7 +158,7 @@ void __nvoc_init_dataField_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspe } // NVOC Property Hal field -- PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000003UL) )) /* RmVariantHal: VF | PF_KERNEL_ONLY */ { pThis->setProperty(pThis, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM, ((NvBool)(0 == 0))); } @@ -192,6 +192,8 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * pThis->__kfspConstructEngine__ = &kfspConstructEngine_IMPL; + pThis->__kfspCleanupBootState__ = &kfspCleanupBootState_IMPL; + pThis->__kfspStateDestroy__ = &kfspStateDestroy_IMPL; pThis->__kfspSecureReset__ = &kfspSecureReset_IMPL; @@ -219,6 +221,16 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * pThis->__kfspGspFmcIsEnforced__ = &kfspGspFmcIsEnforced_491d52; } + // Hal function -- kfspPrepareBootCommands + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspPrepareBootCommands__ = &kfspPrepareBootCommands_GH100; + } + else + { + pThis->__kfspPrepareBootCommands__ = &kfspPrepareBootCommands_ac1694; + } + // Hal function -- kfspSendBootCommands if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -229,6 +241,16 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * pThis->__kfspSendBootCommands__ = &kfspSendBootCommands_ac1694; } + // Hal function -- kfspPrepareAndSendBootCommands + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspPrepareAndSendBootCommands__ = &kfspPrepareAndSendBootCommands_GH100; + } + else + { + pThis->__kfspPrepareAndSendBootCommands__ = &kfspPrepareAndSendBootCommands_ac1694; + } + // Hal function -- kfspWaitForSecureBoot if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -452,6 +474,26 @@ static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner * pThis->__kfspRequiresBug3957833WAR__ = &kfspRequiresBug3957833WAR_491d52; } + // Hal function -- kfspFrtsSysmemLocationProgram + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspFrtsSysmemLocationProgram__ = &kfspFrtsSysmemLocationProgram_GH100; + } + else + { + pThis->__kfspFrtsSysmemLocationProgram__ = &kfspFrtsSysmemLocationProgram_395e98; + } + + // Hal function -- kfspFrtsSysmemLocationClear + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfspFrtsSysmemLocationClear__ = &kfspFrtsSysmemLocationClear_GH100; + } + else + { + pThis->__kfspFrtsSysmemLocationClear__ = &kfspFrtsSysmemLocationClear_d44104; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelFsp_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelFsp_engstateStateDestroy; @@ -494,23 +536,31 @@ void __nvoc_init_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelFsp(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelFsp *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelFsp), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelFsp)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelFsp); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -528,16 +578,25 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_KernelFsp(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelFsp_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelFsp_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelFsp)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kern_fsp_nvoc.h b/src/nvidia/generated/g_kern_fsp_nvoc.h index 2c72b33cef..218706bb24 100644 --- a/src/nvidia/generated/g_kern_fsp_nvoc.h +++ b/src/nvidia/generated/g_kern_fsp_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -118,11 +118,16 @@ typedef enum MCTP_PACKET_STATE_SINGLE_PACKET } MCTP_PACKET_STATE; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERN_FSP_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelFsp { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -130,6 +135,7 @@ struct KernelFsp { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelFsp *__nvoc_pbase_KernelFsp; NV_STATUS (*__kfspConstructEngine__)(struct OBJGPU *, struct KernelFsp *, ENGDESCRIPTOR); + void (*__kfspCleanupBootState__)(struct OBJGPU *, struct KernelFsp *); void (*__kfspStateDestroy__)(struct OBJGPU *, struct KernelFsp *); void (*__kfspSecureReset__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspSendPacket__)(struct OBJGPU *, struct KernelFsp *, NvU8 *, NvU32); @@ -139,7 +145,9 @@ struct KernelFsp { NvBool (*__kfspIsMsgQueueEmpty__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspPollForResponse__)(struct OBJGPU *, struct KernelFsp *); NvBool (*__kfspGspFmcIsEnforced__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspPrepareBootCommands__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspSendBootCommands__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspPrepareAndSendBootCommands__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspWaitForSecureBoot__)(struct OBJGPU *, struct KernelFsp *); NvU32 (*__kfspGetRmChannelSize__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspConfigEmemc__)(struct OBJGPU *, struct KernelFsp *, NvU32, NvBool, NvBool); @@ -162,6 +170,8 @@ struct KernelFsp { NvBool (*__kfspCheckGspSecureScratch__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspWaitForGspTargetMaskReleased__)(struct OBJGPU *, struct KernelFsp *); NvBool (*__kfspRequiresBug3957833WAR__)(struct OBJGPU *, struct KernelFsp *); + NV_STATUS (*__kfspFrtsSysmemLocationProgram__)(struct OBJGPU *, struct KernelFsp *); + void (*__kfspFrtsSysmemLocationClear__)(struct OBJGPU *, struct KernelFsp *); NV_STATUS (*__kfspStateLoad__)(POBJGPU, struct KernelFsp *, NvU32); NV_STATUS (*__kfspStateUnload__)(POBJGPU, struct KernelFsp *, NvU32); NV_STATUS (*__kfspStateInitLocked__)(POBJGPU, struct KernelFsp *); @@ -228,6 +238,7 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp**, Dynamic*, NvU32); __nvoc_objCreate_KernelFsp((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kfspConstructEngine(pGpu, pKernelFsp, arg0) kfspConstructEngine_DISPATCH(pGpu, pKernelFsp, arg0) +#define kfspCleanupBootState(pGpu, pKernelFsp) kfspCleanupBootState_DISPATCH(pGpu, pKernelFsp) #define kfspStateDestroy(pGpu, pKernelFsp) kfspStateDestroy_DISPATCH(pGpu, pKernelFsp) #define kfspSecureReset(pGpu, pKernelFsp) kfspSecureReset_DISPATCH(pGpu, pKernelFsp) #define kfspSendPacket(pGpu, pKernelFsp, pPacket, packetSize) kfspSendPacket_DISPATCH(pGpu, pKernelFsp, pPacket, packetSize) @@ -238,8 +249,12 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp**, Dynamic*, NvU32); #define kfspPollForResponse(pGpu, pKernelFsp) kfspPollForResponse_DISPATCH(pGpu, pKernelFsp) #define kfspGspFmcIsEnforced(pGpu, pKernelFsp) kfspGspFmcIsEnforced_DISPATCH(pGpu, pKernelFsp) #define kfspGspFmcIsEnforced_HAL(pGpu, pKernelFsp) kfspGspFmcIsEnforced_DISPATCH(pGpu, pKernelFsp) +#define kfspPrepareBootCommands(pGpu, pKernelFsp) kfspPrepareBootCommands_DISPATCH(pGpu, pKernelFsp) +#define kfspPrepareBootCommands_HAL(pGpu, pKernelFsp) kfspPrepareBootCommands_DISPATCH(pGpu, pKernelFsp) #define kfspSendBootCommands(pGpu, pKernelFsp) kfspSendBootCommands_DISPATCH(pGpu, pKernelFsp) #define kfspSendBootCommands_HAL(pGpu, pKernelFsp) kfspSendBootCommands_DISPATCH(pGpu, pKernelFsp) +#define kfspPrepareAndSendBootCommands(pGpu, pKernelFsp) kfspPrepareAndSendBootCommands_DISPATCH(pGpu, pKernelFsp) +#define kfspPrepareAndSendBootCommands_HAL(pGpu, pKernelFsp) kfspPrepareAndSendBootCommands_DISPATCH(pGpu, pKernelFsp) #define kfspWaitForSecureBoot(pGpu, pKernelFsp) kfspWaitForSecureBoot_DISPATCH(pGpu, pKernelFsp) #define kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp) kfspWaitForSecureBoot_DISPATCH(pGpu, pKernelFsp) #define kfspGetRmChannelSize(pGpu, pKernelFsp) kfspGetRmChannelSize_DISPATCH(pGpu, pKernelFsp) @@ -284,6 +299,10 @@ NV_STATUS __nvoc_objCreate_KernelFsp(KernelFsp**, Dynamic*, NvU32); #define kfspWaitForGspTargetMaskReleased_HAL(pGpu, pKernelFsp) kfspWaitForGspTargetMaskReleased_DISPATCH(pGpu, pKernelFsp) #define kfspRequiresBug3957833WAR(pGpu, pKernelFsp) kfspRequiresBug3957833WAR_DISPATCH(pGpu, pKernelFsp) #define kfspRequiresBug3957833WAR_HAL(pGpu, pKernelFsp) kfspRequiresBug3957833WAR_DISPATCH(pGpu, pKernelFsp) +#define kfspFrtsSysmemLocationProgram(pGpu, pKernelFsp) kfspFrtsSysmemLocationProgram_DISPATCH(pGpu, pKernelFsp) +#define kfspFrtsSysmemLocationProgram_HAL(pGpu, pKernelFsp) kfspFrtsSysmemLocationProgram_DISPATCH(pGpu, pKernelFsp) +#define kfspFrtsSysmemLocationClear(pGpu, pKernelFsp) kfspFrtsSysmemLocationClear_DISPATCH(pGpu, pKernelFsp) +#define kfspFrtsSysmemLocationClear_HAL(pGpu, pKernelFsp) kfspFrtsSysmemLocationClear_DISPATCH(pGpu, pKernelFsp) #define kfspStateLoad(pGpu, pEngstate, arg0) kfspStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kfspStateUnload(pGpu, pEngstate, arg0) kfspStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define kfspStateInitLocked(pGpu, pEngstate) kfspStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -302,6 +321,12 @@ static inline NV_STATUS kfspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct return pKernelFsp->__kfspConstructEngine__(pGpu, pKernelFsp, arg0); } +void kfspCleanupBootState_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline void kfspCleanupBootState_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + pKernelFsp->__kfspCleanupBootState__(pGpu, pKernelFsp); +} + void kfspStateDestroy_IMPL(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); static inline void kfspStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { @@ -360,6 +385,16 @@ static inline NvBool kfspGspFmcIsEnforced_DISPATCH(struct OBJGPU *pGpu, struct K return pKernelFsp->__kfspGspFmcIsEnforced__(pGpu, pKernelFsp); } +NV_STATUS kfspPrepareBootCommands_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspPrepareBootCommands_ac1694(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return NV_OK; +} + +static inline NV_STATUS kfspPrepareBootCommands_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspPrepareBootCommands__(pGpu, pKernelFsp); +} + NV_STATUS kfspSendBootCommands_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); static inline NV_STATUS kfspSendBootCommands_ac1694(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { @@ -370,6 +405,16 @@ static inline NV_STATUS kfspSendBootCommands_DISPATCH(struct OBJGPU *pGpu, struc return pKernelFsp->__kfspSendBootCommands__(pGpu, pKernelFsp); } +NV_STATUS kfspPrepareAndSendBootCommands_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspPrepareAndSendBootCommands_ac1694(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return NV_OK; +} + +static inline NV_STATUS kfspPrepareAndSendBootCommands_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspPrepareAndSendBootCommands__(pGpu, pKernelFsp); +} + NV_STATUS kfspWaitForSecureBoot_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); static inline NV_STATUS kfspWaitForSecureBoot_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { @@ -590,6 +635,26 @@ static inline NvBool kfspRequiresBug3957833WAR_DISPATCH(struct OBJGPU *pGpu, str return pKernelFsp->__kfspRequiresBug3957833WAR__(pGpu, pKernelFsp); } +NV_STATUS kfspFrtsSysmemLocationProgram_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline NV_STATUS kfspFrtsSysmemLocationProgram_395e98(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfspFrtsSysmemLocationProgram_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return pKernelFsp->__kfspFrtsSysmemLocationProgram__(pGpu, pKernelFsp); +} + +void kfspFrtsSysmemLocationClear_GH100(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp); + +static inline void kfspFrtsSysmemLocationClear_d44104(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + return; +} + +static inline void kfspFrtsSysmemLocationClear_DISPATCH(struct OBJGPU *pGpu, struct KernelFsp *pKernelFsp) { + pKernelFsp->__kfspFrtsSysmemLocationClear__(pGpu, pKernelFsp); +} + static inline NV_STATUS kfspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelFsp *pEngstate, NvU32 arg0) { return pEngstate->__kfspStateLoad__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.c b/src/nvidia/generated/g_kern_gmmu_nvoc.c index cb124cf357..7452aad5ad 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.c +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.c @@ -83,6 +83,14 @@ static NV_STATUS __nvoc_thunk_KernelGmmu_engstateStateInitLocked(OBJGPU *pGpu, s return kgmmuStateInitLocked(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } +static NV_STATUS __nvoc_thunk_KernelGmmu_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelGmmu, NvU32 arg0) { + return kgmmuStateLoad(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_KernelGmmu_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelGmmu, NvU32 arg0) { + return kgmmuStateUnload(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); +} + static NV_STATUS __nvoc_thunk_KernelGmmu_engstateStatePostLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelGmmu, NvU32 arg0) { return kgmmuStatePostLoad(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); } @@ -95,24 +103,20 @@ static void __nvoc_thunk_KernelGmmu_engstateStateDestroy(OBJGPU *pGpu, struct OB kgmmuStateDestroy(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[168]) { +static void __nvoc_thunk_KernelGmmu_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceRecord arg0[171]) { kgmmuRegisterIntrService(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), arg0); } -static NvU32 __nvoc_thunk_KernelGmmu_intrservServiceInterrupt(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceServiceInterruptArguments *pParams) { - return kgmmuServiceInterrupt(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStateLoad(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { - return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); +static NvBool __nvoc_thunk_KernelGmmu_intrservClearInterrupt(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceClearInterruptArguments *pParams) { + return kgmmuClearInterrupt(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStateUnload(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { - return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset), arg0); +static NvU32 __nvoc_thunk_KernelGmmu_intrservServiceInterrupt(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceServiceInterruptArguments *pParams) { + return kgmmuServiceInterrupt(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); } -static NV_STATUS __nvoc_thunk_IntrService_kgmmuServiceNotificationInterrupt(struct OBJGPU *pGpu, struct KernelGmmu *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { - return intrservServiceNotificationInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); +static NV_STATUS __nvoc_thunk_KernelGmmu_intrservServiceNotificationInterrupt(OBJGPU *pGpu, struct IntrService *pKernelGmmu, IntrServiceServiceNotificationInterruptArguments *pParams) { + return kgmmuServiceNotificationInterrupt(pGpu, (struct KernelGmmu *)(((unsigned char *)pKernelGmmu) - __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStatePreLoad(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { @@ -139,10 +143,6 @@ static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgmmuStatePreInitUnlocked(POBJGPU pGpu return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } -static NvBool __nvoc_thunk_IntrService_kgmmuClearInterrupt(struct OBJGPU *pGpu, struct KernelGmmu *pIntrService, IntrServiceClearInterruptArguments *pParams) { - return intrservClearInterrupt(pGpu, (struct IntrService *)(((unsigned char *)pIntrService) + __nvoc_rtti_KernelGmmu_IntrService.offset), pParams); -} - static NvBool __nvoc_thunk_OBJENGSTATE_kgmmuIsPresent(POBJGPU pGpu, struct KernelGmmu *pEngstate) { return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGmmu_OBJENGSTATE.offset)); } @@ -179,6 +179,7 @@ void __nvoc_init_dataField_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhals { pThis->setProperty(pThis, PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED, ((NvBool)(0 == 0))); } + pThis->setProperty(pThis, PDB_PROP_KGMMU_REDUCE_NR_FAULT_BUFFER_SIZE, ((NvBool)(0 != 0))); // Hal field -- defaultBigPageSize if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ @@ -256,6 +257,10 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuStateInitLocked__ = &kgmmuStateInitLocked_IMPL; + pThis->__kgmmuStateLoad__ = &kgmmuStateLoad_IMPL; + + pThis->__kgmmuStateUnload__ = &kgmmuStateUnload_IMPL; + // Hal function -- kgmmuStatePostLoad pThis->__kgmmuStatePostLoad__ = &kgmmuStatePostLoad_IMPL; @@ -266,8 +271,13 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuRegisterIntrService__ = &kgmmuRegisterIntrService_IMPL; + pThis->__kgmmuClearInterrupt__ = &kgmmuClearInterrupt_IMPL; + pThis->__kgmmuServiceInterrupt__ = &kgmmuServiceInterrupt_IMPL; + // Hal function -- kgmmuServiceNotificationInterrupt + pThis->__kgmmuServiceNotificationInterrupt__ = &kgmmuServiceNotificationInterrupt_56cd7a; + // Hal function -- kgmmuInstBlkVaLimitGet if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -442,6 +452,16 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuIssueReplayableFaultBufferFlush__ = &kgmmuIssueReplayableFaultBufferFlush_46f6a7; } + // Hal function -- kgmmuToggleFaultOnPrefetch + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuToggleFaultOnPrefetch__ = &kgmmuToggleFaultOnPrefetch_GH100; + } + else + { + pThis->__kgmmuToggleFaultOnPrefetch__ = &kgmmuToggleFaultOnPrefetch_46f6a7; + } + // Hal function -- kgmmuFaultBufferAllocSharedMemory if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -493,10 +513,519 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuReadShadowBufPutIndex__ = &kgmmuReadShadowBufPutIndex_4a4dee; } + // Hal function -- kgmmuIsFaultEngineBar1 + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuIsFaultEngineBar1__ = &kgmmuIsFaultEngineBar1_GH100; + } + else + { + pThis->__kgmmuIsFaultEngineBar1__ = &kgmmuIsFaultEngineBar1_TU102; + } + + // Hal function -- kgmmuIsFaultEngineBar2 + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuIsFaultEngineBar2__ = &kgmmuIsFaultEngineBar2_GH100; + } + else + { + pThis->__kgmmuIsFaultEngineBar2__ = &kgmmuIsFaultEngineBar2_TU102; + } + + // Hal function -- kgmmuIsFaultEnginePhysical + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuIsFaultEnginePhysical__ = &kgmmuIsFaultEnginePhysical_GH100; + } + else + { + pThis->__kgmmuIsFaultEnginePhysical__ = &kgmmuIsFaultEnginePhysical_GV100; + } + + // Hal function -- kgmmuCopyMmuFaults + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuCopyMmuFaults__ = &kgmmuCopyMmuFaults_GV100; + } + else + { + pThis->__kgmmuCopyMmuFaults__ = &kgmmuCopyMmuFaults_92bfc3; + } + + // Hal function -- kgmmuParseFaultPacket + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuParseFaultPacket__ = &kgmmuParseFaultPacket_GV100; + } + else + { + pThis->__kgmmuParseFaultPacket__ = &kgmmuParseFaultPacket_92bfc3; + } + + // Hal function -- kgmmuFaultBufferClearPackets + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultBufferClearPackets__ = &kgmmuFaultBufferClearPackets_GV100; + } + else + { + pThis->__kgmmuFaultBufferClearPackets__ = &kgmmuFaultBufferClearPackets_f2d351; + } + + // Hal function -- kgmmuFaultBufferGetFault + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultBufferGetFault__ = &kgmmuFaultBufferGetFault_GV100; + } + else + { + pThis->__kgmmuFaultBufferGetFault__ = &kgmmuFaultBufferGetFault_dc3e6c; + } + + // Hal function -- kgmmuCopyFaultPacketToClientShadowBuffer + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuCopyFaultPacketToClientShadowBuffer__ = &kgmmuCopyFaultPacketToClientShadowBuffer_GH100; + } + else + { + pThis->__kgmmuCopyFaultPacketToClientShadowBuffer__ = &kgmmuCopyFaultPacketToClientShadowBuffer_GV100; + } + } + else + { + pThis->__kgmmuCopyFaultPacketToClientShadowBuffer__ = &kgmmuCopyFaultPacketToClientShadowBuffer_13cd8d; + } + + // Hal function -- kgmmuIsReplayableShadowFaultBufferFull + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuIsReplayableShadowFaultBufferFull__ = &kgmmuIsReplayableShadowFaultBufferFull_GH100; + } + // default + else + { + pThis->__kgmmuIsReplayableShadowFaultBufferFull__ = &kgmmuIsReplayableShadowFaultBufferFull_491d52; + } + } + else + { + pThis->__kgmmuIsReplayableShadowFaultBufferFull__ = &kgmmuIsReplayableShadowFaultBufferFull_ceaee8; + } + + // Hal function -- kgmmuReadClientShadowBufPutIndex + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuReadClientShadowBufPutIndex__ = &kgmmuReadClientShadowBufPutIndex_GH100; + } + // default + else + { + pThis->__kgmmuReadClientShadowBufPutIndex__ = &kgmmuReadClientShadowBufPutIndex_4a4dee; + } + } + else + { + pThis->__kgmmuReadClientShadowBufPutIndex__ = &kgmmuReadClientShadowBufPutIndex_13cd8d; + } + + // Hal function -- kgmmuWriteClientShadowBufPutIndex + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuWriteClientShadowBufPutIndex__ = &kgmmuWriteClientShadowBufPutIndex_GH100; + } + // default + else + { + pThis->__kgmmuWriteClientShadowBufPutIndex__ = &kgmmuWriteClientShadowBufPutIndex_b3696a; + } + } + else + { + pThis->__kgmmuWriteClientShadowBufPutIndex__ = &kgmmuWriteClientShadowBufPutIndex_f2d351; + } + + // Hal function -- kgmmuGetMinCeEngineId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuGetMinCeEngineId__ = &kgmmuGetMinCeEngineId_GH100; + } + else + { + pThis->__kgmmuGetMinCeEngineId__ = &kgmmuGetMinCeEngineId_GV100; + } + + // Hal function -- kgmmuGetMaxCeEngineId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuGetMaxCeEngineId__ = &kgmmuGetMaxCeEngineId_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kgmmuGetMaxCeEngineId__ = &kgmmuGetMaxCeEngineId_GV100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgmmuGetMaxCeEngineId__ = &kgmmuGetMaxCeEngineId_AD102; + } + else + { + pThis->__kgmmuGetMaxCeEngineId__ = &kgmmuGetMaxCeEngineId_GA100; + } + + // Hal function -- kgmmuFaultBufferMap + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultBufferMap__ = &kgmmuFaultBufferMap_IMPL; + } + else + { + pThis->__kgmmuFaultBufferMap__ = &kgmmuFaultBufferMap_92bfc3; + } + + // Hal function -- kgmmuFaultBufferUnmap + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultBufferUnmap__ = &kgmmuFaultBufferUnmap_IMPL; + } + else + { + pThis->__kgmmuFaultBufferUnmap__ = &kgmmuFaultBufferUnmap_92bfc3; + } + + // Hal function -- kgmmuFaultBufferInit + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultBufferInit__ = &kgmmuFaultBufferInit_GV100; + } + else + { + pThis->__kgmmuFaultBufferInit__ = &kgmmuFaultBufferInit_56cd7a; + } + + // Hal function -- kgmmuFaultBufferDestroy + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultBufferDestroy__ = &kgmmuFaultBufferDestroy_GV100; + } + else + { + pThis->__kgmmuFaultBufferDestroy__ = &kgmmuFaultBufferDestroy_56cd7a; + } + + // Hal function -- kgmmuFaultBufferLoad + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultBufferLoad__ = &kgmmuFaultBufferLoad_GV100; + } + else + { + pThis->__kgmmuFaultBufferLoad__ = &kgmmuFaultBufferLoad_ac1694; + } + + // Hal function -- kgmmuFaultBufferUnload + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultBufferUnload__ = &kgmmuFaultBufferUnload_GV100; + } + else + { + pThis->__kgmmuFaultBufferUnload__ = &kgmmuFaultBufferUnload_ac1694; + } + + // Hal function -- kgmmuEnableFaultBuffer + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuEnableFaultBuffer__ = &kgmmuEnableFaultBuffer_GV100; + } + else + { + pThis->__kgmmuEnableFaultBuffer__ = &kgmmuEnableFaultBuffer_395e98; + } + + // Hal function -- kgmmuDisableFaultBuffer + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuDisableFaultBuffer__ = &kgmmuDisableFaultBuffer_GV100; + } + else + { + pThis->__kgmmuDisableFaultBuffer__ = &kgmmuDisableFaultBuffer_92bfc3; + } + + // Hal function -- kgmmuSetAndGetDefaultFaultBufferSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuSetAndGetDefaultFaultBufferSize__ = &kgmmuSetAndGetDefaultFaultBufferSize_TU102; + } + else + { + pThis->__kgmmuSetAndGetDefaultFaultBufferSize__ = &kgmmuSetAndGetDefaultFaultBufferSize_13cd8d; + } + + // Hal function -- kgmmuReadMmuFaultInstHiLo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuReadMmuFaultInstHiLo__ = &kgmmuReadMmuFaultInstHiLo_TU102; + } + else + { + pThis->__kgmmuReadMmuFaultInstHiLo__ = &kgmmuReadMmuFaultInstHiLo_f2d351; + } + + // Hal function -- kgmmuReadMmuFaultAddrHiLo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuReadMmuFaultAddrHiLo__ = &kgmmuReadMmuFaultAddrHiLo_TU102; + } + else + { + pThis->__kgmmuReadMmuFaultAddrHiLo__ = &kgmmuReadMmuFaultAddrHiLo_f2d351; + } + + // Hal function -- kgmmuReadMmuFaultInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuReadMmuFaultInfo__ = &kgmmuReadMmuFaultInfo_TU102; + } + else + { + pThis->__kgmmuReadMmuFaultInfo__ = &kgmmuReadMmuFaultInfo_a547a8; + } + + // Hal function -- kgmmuWriteMmuFaultBufferSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuWriteMmuFaultBufferSize__ = &kgmmuWriteMmuFaultBufferSize_TU102; + } + else + { + pThis->__kgmmuWriteMmuFaultBufferSize__ = &kgmmuWriteMmuFaultBufferSize_f2d351; + } + + // Hal function -- kgmmuWriteMmuFaultBufferHiLo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuWriteMmuFaultBufferHiLo__ = &kgmmuWriteMmuFaultBufferHiLo_TU102; + } + else + { + pThis->__kgmmuWriteMmuFaultBufferHiLo__ = &kgmmuWriteMmuFaultBufferHiLo_f2d351; + } + + // Hal function -- kgmmuEnableMmuFaultInterrupts + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuEnableMmuFaultInterrupts__ = &kgmmuEnableMmuFaultInterrupts_46f6a7; + } + else + { + pThis->__kgmmuEnableMmuFaultInterrupts__ = &kgmmuEnableMmuFaultInterrupts_92bfc3; + } + + // Hal function -- kgmmuDisableMmuFaultInterrupts + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuDisableMmuFaultInterrupts__ = &kgmmuDisableMmuFaultInterrupts_46f6a7; + } + else + { + pThis->__kgmmuDisableMmuFaultInterrupts__ = &kgmmuDisableMmuFaultInterrupts_92bfc3; + } + + // Hal function -- kgmmuEnableMmuFaultOverflowIntr + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuEnableMmuFaultOverflowIntr__ = &kgmmuEnableMmuFaultOverflowIntr_46f6a7; + } + else + { + pThis->__kgmmuEnableMmuFaultOverflowIntr__ = &kgmmuEnableMmuFaultOverflowIntr_92bfc3; + } + + // Hal function -- kgmmuSignExtendFaultAddress + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgmmuSignExtendFaultAddress__ = &kgmmuSignExtendFaultAddress_GH100; + } + else + { + pThis->__kgmmuSignExtendFaultAddress__ = &kgmmuSignExtendFaultAddress_GV100; + } + } + else + { + pThis->__kgmmuSignExtendFaultAddress__ = &kgmmuSignExtendFaultAddress_f2d351; + } + + // Hal function -- kgmmuGetFaultType + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuGetFaultType__ = &kgmmuGetFaultType_GV100; + } + else + { + pThis->__kgmmuGetFaultType__ = &kgmmuGetFaultType_92bfc3; + } + + // Hal function -- kgmmuIsP2PUnboundInstFault + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kgmmuIsP2PUnboundInstFault__ = &kgmmuIsP2PUnboundInstFault_491d52; + } + else + { + pThis->__kgmmuIsP2PUnboundInstFault__ = &kgmmuIsP2PUnboundInstFault_GA100; + } + } + else + { + pThis->__kgmmuIsP2PUnboundInstFault__ = &kgmmuIsP2PUnboundInstFault_92bfc3; + } + + // Hal function -- kgmmuServiceVfPriFaults + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuServiceVfPriFaults__ = &kgmmuServiceVfPriFaults_IMPL; + } + else + { + pThis->__kgmmuServiceVfPriFaults__ = &kgmmuServiceVfPriFaults_92bfc3; + } + + // Hal function -- kgmmuTestVidmemAccessBitBufferError + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuTestVidmemAccessBitBufferError__ = &kgmmuTestVidmemAccessBitBufferError_491d52; + } + else + { + pThis->__kgmmuTestVidmemAccessBitBufferError__ = &kgmmuTestVidmemAccessBitBufferError_ceaee8; + } + + // Hal function -- kgmmuDisableVidmemAccessBitBuf + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuDisableVidmemAccessBitBuf__ = &kgmmuDisableVidmemAccessBitBuf_b3696a; + } + else + { + pThis->__kgmmuDisableVidmemAccessBitBuf__ = &kgmmuDisableVidmemAccessBitBuf_e426af; + } + + // Hal function -- kgmmuEnableVidmemAccessBitBuf + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuEnableVidmemAccessBitBuf__ = &kgmmuEnableVidmemAccessBitBuf_46f6a7; + } + else + { + pThis->__kgmmuEnableVidmemAccessBitBuf__ = &kgmmuEnableVidmemAccessBitBuf_92bfc3; + } + + // Hal function -- kgmmuClearAccessCounterWriteNak + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuClearAccessCounterWriteNak__ = &kgmmuClearAccessCounterWriteNak_b3696a; + } + else + { + pThis->__kgmmuClearAccessCounterWriteNak__ = &kgmmuClearAccessCounterWriteNak_e426af; + } + + // Hal function -- kgmmuServiceMthdBuffFaultInBar2Fault + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuServiceMthdBuffFaultInBar2Fault__ = &kgmmuServiceMthdBuffFaultInBar2Fault_56cd7a; + } + else + { + pThis->__kgmmuServiceMthdBuffFaultInBar2Fault__ = &kgmmuServiceMthdBuffFaultInBar2Fault_92bfc3; + } + + // Hal function -- kgmmuFaultCancelTargeted + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultCancelTargeted__ = &kgmmuFaultCancelTargeted_VF; + } + else + { + pThis->__kgmmuFaultCancelTargeted__ = &kgmmuFaultCancelTargeted_92bfc3; + } + + // Hal function -- kgmmuFaultCancelIssueInvalidate + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuFaultCancelIssueInvalidate__ = &kgmmuFaultCancelIssueInvalidate_GP100; + } + else + { + pThis->__kgmmuFaultCancelIssueInvalidate__ = &kgmmuFaultCancelIssueInvalidate_92bfc3; + } + + // Hal function -- kgmmuServiceMmuFault + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kgmmuServiceMmuFault__ = &kgmmuServiceMmuFault_GV100; + } + else + { + pThis->__kgmmuServiceMmuFault__ = &kgmmuServiceMmuFault_GA100; + } + + // Hal function -- kgmmuServiceUnboundInstBlockFault + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgmmuServiceUnboundInstBlockFault__ = &kgmmuServiceUnboundInstBlockFault_56cd7a; + } + else + { + pThis->__kgmmuServiceUnboundInstBlockFault__ = &kgmmuServiceUnboundInstBlockFault_92bfc3; + } + + // Hal function -- kgmmuGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kgmmuGetEccCounts__ = &kgmmuGetEccCounts_TU102; + } + // default + else + { + pThis->__kgmmuGetEccCounts__ = &kgmmuGetEccCounts_4a4dee; + } + + // Hal function -- kgmmuClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kgmmuClearEccCounts__ = &kgmmuClearEccCounts_TU102; + } + // default + else + { + pThis->__kgmmuClearEccCounts__ = &kgmmuClearEccCounts_b3696a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGmmu_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelGmmu_engstateStateInitLocked; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelGmmu_engstateStateLoad; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelGmmu_engstateStateUnload; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelGmmu_engstateStatePostLoad; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelGmmu_engstateStatePreUnload; @@ -505,13 +1034,11 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__nvoc_base_IntrService.__intrservRegisterIntrService__ = &__nvoc_thunk_KernelGmmu_intrservRegisterIntrService; - pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelGmmu_intrservServiceInterrupt; + pThis->__nvoc_base_IntrService.__intrservClearInterrupt__ = &__nvoc_thunk_KernelGmmu_intrservClearInterrupt; - pThis->__kgmmuStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStateLoad; - - pThis->__kgmmuStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStateUnload; + pThis->__nvoc_base_IntrService.__intrservServiceInterrupt__ = &__nvoc_thunk_KernelGmmu_intrservServiceInterrupt; - pThis->__kgmmuServiceNotificationInterrupt__ = &__nvoc_thunk_IntrService_kgmmuServiceNotificationInterrupt; + pThis->__nvoc_base_IntrService.__intrservServiceNotificationInterrupt__ = &__nvoc_thunk_KernelGmmu_intrservServiceNotificationInterrupt; pThis->__kgmmuStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStatePreLoad; @@ -525,8 +1052,6 @@ static void __nvoc_init_funcTable_KernelGmmu_1(KernelGmmu *pThis, RmHalspecOwner pThis->__kgmmuStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_kgmmuStatePreInitUnlocked; - pThis->__kgmmuClearInterrupt__ = &__nvoc_thunk_IntrService_kgmmuClearInterrupt; - pThis->__kgmmuIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgmmuIsPresent; } @@ -546,23 +1071,31 @@ void __nvoc_init_KernelGmmu(KernelGmmu *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_KernelGmmu(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelGmmu *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGmmu), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelGmmu)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGmmu); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -580,16 +1113,25 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_KernelGmmu(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelGmmu_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelGmmu_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelGmmu)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.h b/src/nvidia/generated/g_kern_gmmu_nvoc.h index e5f92b7e09..eb4d72e3ba 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.h +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.h @@ -54,6 +54,7 @@ extern "C" { #include "containers/queue.h" #include "gpu/eng_state.h" #include "gpu/intr/intr_service.h" +#include "gpu/fifo/kernel_fifo.h" #include "gpu/mem_mgr/virt_mem_allocator_common.h" // RM_PAGE_SIZE_64K #include "mmu/mmu_walk.h" @@ -66,6 +67,8 @@ typedef struct COMPR_INFO COMPR_INFO; typedef struct GVAS_GPU_STATE GVAS_GPU_STATE; +typedef struct _fifo_mmu_exception_data FIFO_MMU_EXCEPTION_DATA; + /*! * Family of GMMU formats sharing the same version and PDE/PTE defines * but with differing big page sizes. @@ -151,12 +154,6 @@ struct HW_FAULT_BUFFER */ typedef struct { - /*! - * The value updated by GSP-RM to notify CPU-RM that - * a successful flush has happened - */ - NvU32 flushBufferSeqNum; - /*! * The GET index of replayable shadow buffer. This * is updated by UVM driver and read by GSP-RM @@ -312,13 +309,67 @@ typedef struct NvU8 *pInstBlk; // VA of instance block. } INST_BLK_INIT_PARAMS, *PINST_BLK_INIT_PARAMS; +typedef enum +{ + fault_invalidPde = 0x00000000, + fault_invalidPdeSize = 0x00000001, + fault_invalidPte = 0x00000002, + fault_limitViolation = 0x00000003, + fault_unboundInstBlock = 0x00000004, + fault_privViolation = 0x00000005, + fault_write = 0x00000006, + fault_read = 0x00000007, + fault_pitchMaskViolation = 0x00000008, + fault_workCreation = 0x00000009, + fault_unsupportedAperture = 0x0000000a, + fault_compressionFailure = 0x0000000b, + fault_cc_violation = 0x0000000b, + fault_unsupportedKind = 0x0000000c, + fault_regionViolation = 0x0000000d, + fault_poison = 0x0000000e, + fault_atomic = 0x0000000f +} FAULT_TYPE; + +typedef struct +{ + INST_BLOCK_DESC mmuFaultInstBlock; + NvU64 mmuFaultAddress; + NvU64 mmuFaultTimestamp; + FAULT_TYPE mmuFaultType; + NvU32 mmuFaultAccessType; + NvU32 mmuFaultEngineId; + NvU32 mmuFaultClientId; + NvU32 mmuFaultClientType; + NvU32 mmuFaultGpcId; + NvU8 bFaultEntryValid : 1; + NvU8 bFaultInProtectedMode : 1; + NvU8 bFaultTypeReplayable : 1; + NvU8 bReplayableFaultEn : 1; +} MMU_FAULT_BUFFER_ENTRY; + +/*! + * This structure contains information needed for targetted fault cancel + * This is passed in by UVM using SW methods (cl0076.h) + */ +typedef struct +{ + NvU32 clientId; + NvU32 gpcId; + INST_BLOCK_DESC instBlock; +} GMMU_FAULT_CANCEL_INFO; + #define VMMU_MAX_GFID 64 + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelGmmu { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -329,11 +380,15 @@ struct KernelGmmu { struct KernelGmmu *__nvoc_pbase_KernelGmmu; NV_STATUS (*__kgmmuConstructEngine__)(OBJGPU *, struct KernelGmmu *, ENGDESCRIPTOR); NV_STATUS (*__kgmmuStateInitLocked__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuStateLoad__)(OBJGPU *, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuStateUnload__)(OBJGPU *, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStatePostLoad__)(OBJGPU *, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStatePreUnload__)(OBJGPU *, struct KernelGmmu *, NvU32); void (*__kgmmuStateDestroy__)(OBJGPU *, struct KernelGmmu *); void (*__kgmmuRegisterIntrService__)(OBJGPU *, struct KernelGmmu *, IntrServiceRecord *); + NvBool (*__kgmmuClearInterrupt__)(OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); NvU32 (*__kgmmuServiceInterrupt__)(OBJGPU *, struct KernelGmmu *, IntrServiceServiceInterruptArguments *); + NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kgmmuInstBlkVaLimitGet__)(struct KernelGmmu *, struct OBJVASPACE *, NvU32, INST_BLK_INIT_PARAMS *, NvU32 *, NvU64 *); NvU32 (*__kgmmuSetTlbInvalidateMembarWarParameters__)(OBJGPU *, struct KernelGmmu *, TLB_INVALIDATE_PARAMS *); NV_STATUS (*__kgmmuSetTlbInvalidationScope__)(OBJGPU *, struct KernelGmmu *, NvU32, TLB_INVALIDATE_PARAMS *); @@ -351,25 +406,70 @@ struct KernelGmmu { NV_STATUS (*__kgmmuTranslatePdePcfFromHw__)(struct KernelGmmu *, NvU32, GMMU_APERTURE, NvU32 *); NV_STATUS (*__kgmmuGetFaultRegisterMappings__)(OBJGPU *, struct KernelGmmu *, NvU32, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvU32 *, NvP64 *); NV_STATUS (*__kgmmuIssueReplayableFaultBufferFlush__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuToggleFaultOnPrefetch__)(OBJGPU *, struct KernelGmmu *, NvBool); NV_STATUS (*__kgmmuFaultBufferAllocSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); void (*__kgmmuFaultBufferFreeSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); NvU32 (*__kgmmuReadShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); - NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); - NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); - NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); + NvBool (*__kgmmuIsFaultEngineBar1__)(struct KernelGmmu *, NvU32); + NvBool (*__kgmmuIsFaultEngineBar2__)(struct KernelGmmu *, NvU32); + NvBool (*__kgmmuIsFaultEnginePhysical__)(struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuCopyMmuFaults__)(OBJGPU *, struct KernelGmmu *, struct THREAD_STATE_NODE *, NvU32 *, FAULT_BUFFER_TYPE); + NV_STATUS (*__kgmmuParseFaultPacket__)(OBJGPU *, struct KernelGmmu *, NvP64, NvP64); + void (*__kgmmuFaultBufferClearPackets__)(OBJGPU *, struct KernelGmmu *, struct HW_FAULT_BUFFER *, NvU32, NvU32); + GMMU_FAULT_PACKET *(*__kgmmuFaultBufferGetFault__)(OBJGPU *, struct KernelGmmu *, struct HW_FAULT_BUFFER *, NvU32); + NvU32 (*__kgmmuCopyFaultPacketToClientShadowBuffer__)(OBJGPU *, struct KernelGmmu *, struct GMMU_FAULT_BUFFER *, FAULT_BUFFER_TYPE, NvU32, NvU32, NvU32, struct THREAD_STATE_NODE *, NvU32 *); + NvBool (*__kgmmuIsReplayableShadowFaultBufferFull__)(OBJGPU *, struct KernelGmmu *, GMMU_CLIENT_SHADOW_FAULT_BUFFER *, NvU32, NvU32); + NvU32 (*__kgmmuReadClientShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, NvU32, FAULT_BUFFER_TYPE); + void (*__kgmmuWriteClientShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, NvU32, FAULT_BUFFER_TYPE, NvU32); + NvU32 (*__kgmmuGetMinCeEngineId__)(struct KernelGmmu *); + NvU32 (*__kgmmuGetMaxCeEngineId__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferMap__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuFaultBufferUnmap__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuFaultBufferInit__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferDestroy__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferLoad__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuFaultBufferUnload__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuEnableFaultBuffer__)(OBJGPU *, struct KernelGmmu *, NvU32, NvBool, NvU32); + NV_STATUS (*__kgmmuDisableFaultBuffer__)(OBJGPU *, struct KernelGmmu *, NvU32, NvBool, NvU32); + NvU32 (*__kgmmuSetAndGetDefaultFaultBufferSize__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE, NvU32); + void (*__kgmmuReadMmuFaultInstHiLo__)(OBJGPU *, struct KernelGmmu *, NvU32 *, NvU32 *); + void (*__kgmmuReadMmuFaultAddrHiLo__)(OBJGPU *, struct KernelGmmu *, NvU32 *, NvU32 *); + NvU32 (*__kgmmuReadMmuFaultInfo__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuWriteMmuFaultBufferSize__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32, NvU32); + void (*__kgmmuWriteMmuFaultBufferHiLo__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32, NvU32, NvU32); + NV_STATUS (*__kgmmuEnableMmuFaultInterrupts__)(OBJGPU *, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuDisableMmuFaultInterrupts__)(OBJGPU *, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuEnableMmuFaultOverflowIntr__)(OBJGPU *, struct KernelGmmu *, NvU32); + void (*__kgmmuSignExtendFaultAddress__)(OBJGPU *, struct KernelGmmu *, NvU64 *); + NV_STATUS (*__kgmmuGetFaultType__)(OBJGPU *, struct KernelGmmu *, NvU32, FAULT_TYPE *); + NvBool (*__kgmmuIsP2PUnboundInstFault__)(struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuServiceVfPriFaults__)(OBJGPU *, struct KernelGmmu *, NvU32); + NvBool (*__kgmmuTestVidmemAccessBitBufferError__)(OBJGPU *, struct KernelGmmu *, NvU32); + void (*__kgmmuDisableVidmemAccessBitBuf__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuEnableVidmemAccessBitBuf__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuClearAccessCounterWriteNak__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuServiceMthdBuffFaultInBar2Fault__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultCancelTargeted__)(OBJGPU *, struct KernelGmmu *, GMMU_FAULT_CANCEL_INFO *); + NV_STATUS (*__kgmmuFaultCancelIssueInvalidate__)(OBJGPU *, struct KernelGmmu *, GMMU_FAULT_CANCEL_INFO *, TLB_INVALIDATE_PARAMS *, NvBool); + NV_STATUS (*__kgmmuServiceMmuFault__)(OBJGPU *, struct KernelGmmu *, NvP64, FIFO_MMU_EXCEPTION_DATA *); + NV_STATUS (*__kgmmuServiceUnboundInstBlockFault__)(OBJGPU *, struct KernelGmmu *, NvP64, FIFO_MMU_EXCEPTION_DATA *); + NvU32 (*__kgmmuGetEccCounts__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuClearEccCounts__)(OBJGPU *, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStatePostUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateInitUnlocked__)(POBJGPU, struct KernelGmmu *); void (*__kgmmuInitMissing__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitLocked__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitUnlocked__)(POBJGPU, struct KernelGmmu *); - NvBool (*__kgmmuClearInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); NvBool (*__kgmmuIsPresent__)(POBJGPU, struct KernelGmmu *); NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; - const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; + NvBool PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE; + NvBool PDB_PROP_KGMMU_REDUCE_NR_FAULT_BUFFER_SIZE; + NvBool bReportFlaTranslationXid; + NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; NvU64 defaultBigPageSize; NvU32 uvmSharedIntrRmOwnsMask; GMMU_FMT_FAMILY *PRIVATE_FIELD(pFmtFamilies)[3]; @@ -391,6 +491,8 @@ struct KernelGmmu { MEMORY_DESCRIPTOR *PRIVATE_FIELD(pWarPageDirectory0); struct GMMU_FAULT_BUFFER PRIVATE_FIELD(mmuFaultBuffer)[64]; NvU64 PRIVATE_FIELD(sysmemBaseAddress); + NvU32 PRIVATE_FIELD(minCeMmuFaultId); + NvU32 PRIVATE_FIELD(maxCeMmuFaultId); NvBool PRIVATE_FIELD(bHugePageSupported); NvBool PRIVATE_FIELD(bPageSize512mbSupported); NvBool PRIVATE_FIELD(bBug2720120WarEnabled); @@ -407,11 +509,15 @@ struct KernelGmmu_PRIVATE { struct KernelGmmu *__nvoc_pbase_KernelGmmu; NV_STATUS (*__kgmmuConstructEngine__)(OBJGPU *, struct KernelGmmu *, ENGDESCRIPTOR); NV_STATUS (*__kgmmuStateInitLocked__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuStateLoad__)(OBJGPU *, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuStateUnload__)(OBJGPU *, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStatePostLoad__)(OBJGPU *, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStatePreUnload__)(OBJGPU *, struct KernelGmmu *, NvU32); void (*__kgmmuStateDestroy__)(OBJGPU *, struct KernelGmmu *); void (*__kgmmuRegisterIntrService__)(OBJGPU *, struct KernelGmmu *, IntrServiceRecord *); + NvBool (*__kgmmuClearInterrupt__)(OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); NvU32 (*__kgmmuServiceInterrupt__)(OBJGPU *, struct KernelGmmu *, IntrServiceServiceInterruptArguments *); + NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); NV_STATUS (*__kgmmuInstBlkVaLimitGet__)(struct KernelGmmu *, struct OBJVASPACE *, NvU32, INST_BLK_INIT_PARAMS *, NvU32 *, NvU64 *); NvU32 (*__kgmmuSetTlbInvalidateMembarWarParameters__)(OBJGPU *, struct KernelGmmu *, TLB_INVALIDATE_PARAMS *); NV_STATUS (*__kgmmuSetTlbInvalidationScope__)(OBJGPU *, struct KernelGmmu *, NvU32, TLB_INVALIDATE_PARAMS *); @@ -429,25 +535,70 @@ struct KernelGmmu_PRIVATE { NV_STATUS (*__kgmmuTranslatePdePcfFromHw__)(struct KernelGmmu *, NvU32, GMMU_APERTURE, NvU32 *); NV_STATUS (*__kgmmuGetFaultRegisterMappings__)(OBJGPU *, struct KernelGmmu *, NvU32, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvP64 *, NvU32 *, NvP64 *); NV_STATUS (*__kgmmuIssueReplayableFaultBufferFlush__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuToggleFaultOnPrefetch__)(OBJGPU *, struct KernelGmmu *, NvBool); NV_STATUS (*__kgmmuFaultBufferAllocSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); void (*__kgmmuFaultBufferFreeSharedMemory__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); NV_STATUS (*__kgmmuSetupWarForBug2720120__)(struct KernelGmmu *, GMMU_FMT_FAMILY *); NvU32 (*__kgmmuGetGraphicsEngineId__)(struct KernelGmmu *); NvU32 (*__kgmmuReadShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE); - NV_STATUS (*__kgmmuStateLoad__)(POBJGPU, struct KernelGmmu *, NvU32); - NV_STATUS (*__kgmmuStateUnload__)(POBJGPU, struct KernelGmmu *, NvU32); - NV_STATUS (*__kgmmuServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceServiceNotificationInterruptArguments *); + NvBool (*__kgmmuIsFaultEngineBar1__)(struct KernelGmmu *, NvU32); + NvBool (*__kgmmuIsFaultEngineBar2__)(struct KernelGmmu *, NvU32); + NvBool (*__kgmmuIsFaultEnginePhysical__)(struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuCopyMmuFaults__)(OBJGPU *, struct KernelGmmu *, struct THREAD_STATE_NODE *, NvU32 *, FAULT_BUFFER_TYPE); + NV_STATUS (*__kgmmuParseFaultPacket__)(OBJGPU *, struct KernelGmmu *, NvP64, NvP64); + void (*__kgmmuFaultBufferClearPackets__)(OBJGPU *, struct KernelGmmu *, struct HW_FAULT_BUFFER *, NvU32, NvU32); + GMMU_FAULT_PACKET *(*__kgmmuFaultBufferGetFault__)(OBJGPU *, struct KernelGmmu *, struct HW_FAULT_BUFFER *, NvU32); + NvU32 (*__kgmmuCopyFaultPacketToClientShadowBuffer__)(OBJGPU *, struct KernelGmmu *, struct GMMU_FAULT_BUFFER *, FAULT_BUFFER_TYPE, NvU32, NvU32, NvU32, struct THREAD_STATE_NODE *, NvU32 *); + NvBool (*__kgmmuIsReplayableShadowFaultBufferFull__)(OBJGPU *, struct KernelGmmu *, GMMU_CLIENT_SHADOW_FAULT_BUFFER *, NvU32, NvU32); + NvU32 (*__kgmmuReadClientShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, NvU32, FAULT_BUFFER_TYPE); + void (*__kgmmuWriteClientShadowBufPutIndex__)(OBJGPU *, struct KernelGmmu *, NvU32, FAULT_BUFFER_TYPE, NvU32); + NvU32 (*__kgmmuGetMinCeEngineId__)(struct KernelGmmu *); + NvU32 (*__kgmmuGetMaxCeEngineId__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferMap__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuFaultBufferUnmap__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuFaultBufferInit__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferDestroy__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultBufferLoad__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuFaultBufferUnload__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuEnableFaultBuffer__)(OBJGPU *, struct KernelGmmu *, NvU32, NvBool, NvU32); + NV_STATUS (*__kgmmuDisableFaultBuffer__)(OBJGPU *, struct KernelGmmu *, NvU32, NvBool, NvU32); + NvU32 (*__kgmmuSetAndGetDefaultFaultBufferSize__)(OBJGPU *, struct KernelGmmu *, FAULT_BUFFER_TYPE, NvU32); + void (*__kgmmuReadMmuFaultInstHiLo__)(OBJGPU *, struct KernelGmmu *, NvU32 *, NvU32 *); + void (*__kgmmuReadMmuFaultAddrHiLo__)(OBJGPU *, struct KernelGmmu *, NvU32 *, NvU32 *); + NvU32 (*__kgmmuReadMmuFaultInfo__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuWriteMmuFaultBufferSize__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32, NvU32); + void (*__kgmmuWriteMmuFaultBufferHiLo__)(OBJGPU *, struct KernelGmmu *, NvU32, NvU32, NvU32, NvU32); + NV_STATUS (*__kgmmuEnableMmuFaultInterrupts__)(OBJGPU *, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuDisableMmuFaultInterrupts__)(OBJGPU *, struct KernelGmmu *, NvU32); + NV_STATUS (*__kgmmuEnableMmuFaultOverflowIntr__)(OBJGPU *, struct KernelGmmu *, NvU32); + void (*__kgmmuSignExtendFaultAddress__)(OBJGPU *, struct KernelGmmu *, NvU64 *); + NV_STATUS (*__kgmmuGetFaultType__)(OBJGPU *, struct KernelGmmu *, NvU32, FAULT_TYPE *); + NvBool (*__kgmmuIsP2PUnboundInstFault__)(struct KernelGmmu *, NvU32, NvU32); + NV_STATUS (*__kgmmuServiceVfPriFaults__)(OBJGPU *, struct KernelGmmu *, NvU32); + NvBool (*__kgmmuTestVidmemAccessBitBufferError__)(OBJGPU *, struct KernelGmmu *, NvU32); + void (*__kgmmuDisableVidmemAccessBitBuf__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuEnableVidmemAccessBitBuf__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuClearAccessCounterWriteNak__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuServiceMthdBuffFaultInBar2Fault__)(OBJGPU *, struct KernelGmmu *); + NV_STATUS (*__kgmmuFaultCancelTargeted__)(OBJGPU *, struct KernelGmmu *, GMMU_FAULT_CANCEL_INFO *); + NV_STATUS (*__kgmmuFaultCancelIssueInvalidate__)(OBJGPU *, struct KernelGmmu *, GMMU_FAULT_CANCEL_INFO *, TLB_INVALIDATE_PARAMS *, NvBool); + NV_STATUS (*__kgmmuServiceMmuFault__)(OBJGPU *, struct KernelGmmu *, NvP64, FIFO_MMU_EXCEPTION_DATA *); + NV_STATUS (*__kgmmuServiceUnboundInstBlockFault__)(OBJGPU *, struct KernelGmmu *, NvP64, FIFO_MMU_EXCEPTION_DATA *); + NvU32 (*__kgmmuGetEccCounts__)(OBJGPU *, struct KernelGmmu *); + void (*__kgmmuClearEccCounts__)(OBJGPU *, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreLoad__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStatePostUnload__)(POBJGPU, struct KernelGmmu *, NvU32); NV_STATUS (*__kgmmuStateInitUnlocked__)(POBJGPU, struct KernelGmmu *); void (*__kgmmuInitMissing__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitLocked__)(POBJGPU, struct KernelGmmu *); NV_STATUS (*__kgmmuStatePreInitUnlocked__)(POBJGPU, struct KernelGmmu *); - NvBool (*__kgmmuClearInterrupt__)(struct OBJGPU *, struct KernelGmmu *, IntrServiceClearInterruptArguments *); NvBool (*__kgmmuIsPresent__)(POBJGPU, struct KernelGmmu *); NvBool PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED; NvBool PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED; - const NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; + NvBool PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE; + NvBool PDB_PROP_KGMMU_REDUCE_NR_FAULT_BUFFER_SIZE; + NvBool bReportFlaTranslationXid; + NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; NvU64 defaultBigPageSize; NvU32 uvmSharedIntrRmOwnsMask; GMMU_FMT_FAMILY *pFmtFamilies[3]; @@ -469,6 +620,8 @@ struct KernelGmmu_PRIVATE { MEMORY_DESCRIPTOR *pWarPageDirectory0; struct GMMU_FAULT_BUFFER mmuFaultBuffer[64]; NvU64 sysmemBaseAddress; + NvU32 minCeMmuFaultId; + NvU32 maxCeMmuFaultId; NvBool bHugePageSupported; NvBool bPageSize512mbSupported; NvBool bBug2720120WarEnabled; @@ -496,10 +649,14 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelGmmu; ((KernelGmmu*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelGmmu))) #endif //__nvoc_kern_gmmu_h_disabled +#define PDB_PROP_KGMMU_REDUCE_NR_FAULT_BUFFER_SIZE_BASE_CAST +#define PDB_PROP_KGMMU_REDUCE_NR_FAULT_BUFFER_SIZE_BASE_NAME PDB_PROP_KGMMU_REDUCE_NR_FAULT_BUFFER_SIZE #define PDB_PROP_KGMMU_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. #define PDB_PROP_KGMMU_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING #define PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED_BASE_CAST #define PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED_BASE_NAME PDB_PROP_KGMMU_SYSMEM_FAULT_BUFFER_GPU_UNCACHED +#define PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE_BASE_CAST +#define PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE_BASE_NAME PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE #define PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED_BASE_CAST #define PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED_BASE_NAME PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED @@ -511,13 +668,18 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuConstructEngine(pGpu, pKernelGmmu, arg0) kgmmuConstructEngine_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuStateInitLocked(pGpu, pKernelGmmu) kgmmuStateInitLocked_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuStateLoad(pGpu, pKernelGmmu, arg0) kgmmuStateLoad_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuStateUnload(pGpu, pKernelGmmu, arg0) kgmmuStateUnload_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuStatePostLoad(pGpu, pKernelGmmu, arg0) kgmmuStatePostLoad_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuStatePostLoad_HAL(pGpu, pKernelGmmu, arg0) kgmmuStatePostLoad_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuStatePreUnload(pGpu, pKernelGmmu, arg0) kgmmuStatePreUnload_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuStatePreUnload_HAL(pGpu, pKernelGmmu, arg0) kgmmuStatePreUnload_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuStateDestroy(pGpu, pKernelGmmu) kgmmuStateDestroy_DISPATCH(pGpu, pKernelGmmu) #define kgmmuRegisterIntrService(pGpu, pKernelGmmu, arg0) kgmmuRegisterIntrService_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuClearInterrupt(pGpu, pKernelGmmu, pParams) kgmmuClearInterrupt_DISPATCH(pGpu, pKernelGmmu, pParams) #define kgmmuServiceInterrupt(pGpu, pKernelGmmu, pParams) kgmmuServiceInterrupt_DISPATCH(pGpu, pKernelGmmu, pParams) +#define kgmmuServiceNotificationInterrupt(pGpu, pKernelGmmu, pParams) kgmmuServiceNotificationInterrupt_DISPATCH(pGpu, pKernelGmmu, pParams) +#define kgmmuServiceNotificationInterrupt_HAL(pGpu, pKernelGmmu, pParams) kgmmuServiceNotificationInterrupt_DISPATCH(pGpu, pKernelGmmu, pParams) #define kgmmuInstBlkVaLimitGet(pKernelGmmu, pVAS, subctxId, pParams, pOffset, pData) kgmmuInstBlkVaLimitGet_DISPATCH(pKernelGmmu, pVAS, subctxId, pParams, pOffset, pData) #define kgmmuInstBlkVaLimitGet_HAL(pKernelGmmu, pVAS, subctxId, pParams, pOffset, pData) kgmmuInstBlkVaLimitGet_DISPATCH(pKernelGmmu, pVAS, subctxId, pParams, pOffset, pData) #define kgmmuSetTlbInvalidateMembarWarParameters(pGpu, pKernelGmmu, pParams) kgmmuSetTlbInvalidateMembarWarParameters_DISPATCH(pGpu, pKernelGmmu, pParams) @@ -552,6 +714,8 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuGetFaultRegisterMappings_HAL(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) kgmmuGetFaultRegisterMappings_DISPATCH(pGpu, pKernelGmmu, index, pFaultBufferGet, pFaultBufferPut, pFaultBufferInfo, faultIntr, faultIntrSet, faultIntrClear, faultMask, pPrefetchCtrl) #define kgmmuIssueReplayableFaultBufferFlush(pGpu, pKernelGmmu) kgmmuIssueReplayableFaultBufferFlush_DISPATCH(pGpu, pKernelGmmu) #define kgmmuIssueReplayableFaultBufferFlush_HAL(pGpu, pKernelGmmu) kgmmuIssueReplayableFaultBufferFlush_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuToggleFaultOnPrefetch(pGpu, pKernelGmmu, bEnable) kgmmuToggleFaultOnPrefetch_DISPATCH(pGpu, pKernelGmmu, bEnable) +#define kgmmuToggleFaultOnPrefetch_HAL(pGpu, pKernelGmmu, bEnable) kgmmuToggleFaultOnPrefetch_DISPATCH(pGpu, pKernelGmmu, bEnable) #define kgmmuFaultBufferAllocSharedMemory(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferAllocSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuFaultBufferAllocSharedMemory_HAL(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferAllocSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) #define kgmmuFaultBufferFreeSharedMemory(pGpu, pKernelGmmu, arg0) kgmmuFaultBufferFreeSharedMemory_DISPATCH(pGpu, pKernelGmmu, arg0) @@ -562,17 +726,119 @@ NV_STATUS __nvoc_objCreate_KernelGmmu(KernelGmmu**, Dynamic*, NvU32); #define kgmmuGetGraphicsEngineId_HAL(pKernelGmmu) kgmmuGetGraphicsEngineId_DISPATCH(pKernelGmmu) #define kgmmuReadShadowBufPutIndex(pGpu, pKernelGmmu, type) kgmmuReadShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, type) #define kgmmuReadShadowBufPutIndex_HAL(pGpu, pKernelGmmu, type) kgmmuReadShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, type) -#define kgmmuStateLoad(pGpu, pEngstate, arg0) kgmmuStateLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kgmmuStateUnload(pGpu, pEngstate, arg0) kgmmuStateUnload_DISPATCH(pGpu, pEngstate, arg0) -#define kgmmuServiceNotificationInterrupt(pGpu, pIntrService, pParams) kgmmuServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams) +#define kgmmuIsFaultEngineBar1(pKernelGmmu, arg0) kgmmuIsFaultEngineBar1_DISPATCH(pKernelGmmu, arg0) +#define kgmmuIsFaultEngineBar1_HAL(pKernelGmmu, arg0) kgmmuIsFaultEngineBar1_DISPATCH(pKernelGmmu, arg0) +#define kgmmuIsFaultEngineBar2(pKernelGmmu, arg0) kgmmuIsFaultEngineBar2_DISPATCH(pKernelGmmu, arg0) +#define kgmmuIsFaultEngineBar2_HAL(pKernelGmmu, arg0) kgmmuIsFaultEngineBar2_DISPATCH(pKernelGmmu, arg0) +#define kgmmuIsFaultEnginePhysical(pKernelGmmu, arg0) kgmmuIsFaultEnginePhysical_DISPATCH(pKernelGmmu, arg0) +#define kgmmuIsFaultEnginePhysical_HAL(pKernelGmmu, arg0) kgmmuIsFaultEnginePhysical_DISPATCH(pKernelGmmu, arg0) +#define kgmmuCopyMmuFaults(pGpu, pKernelGmmu, pThreadState, entriesCopied, type) kgmmuCopyMmuFaults_DISPATCH(pGpu, pKernelGmmu, pThreadState, entriesCopied, type) +#define kgmmuCopyMmuFaults_HAL(pGpu, pKernelGmmu, pThreadState, entriesCopied, type) kgmmuCopyMmuFaults_DISPATCH(pGpu, pKernelGmmu, pThreadState, entriesCopied, type) +#define kgmmuParseFaultPacket(pGpu, pKernelGmmu, pFaultPacket, pParsedFaultEntry) kgmmuParseFaultPacket_DISPATCH(pGpu, pKernelGmmu, pFaultPacket, pParsedFaultEntry) +#define kgmmuParseFaultPacket_HAL(pGpu, pKernelGmmu, pFaultPacket, pParsedFaultEntry) kgmmuParseFaultPacket_DISPATCH(pGpu, pKernelGmmu, pFaultPacket, pParsedFaultEntry) +#define kgmmuFaultBufferClearPackets(pGpu, pKernelGmmu, pFaultBuffer, beginIdx, numFaultPackets) kgmmuFaultBufferClearPackets_DISPATCH(pGpu, pKernelGmmu, pFaultBuffer, beginIdx, numFaultPackets) +#define kgmmuFaultBufferClearPackets_HAL(pGpu, pKernelGmmu, pFaultBuffer, beginIdx, numFaultPackets) kgmmuFaultBufferClearPackets_DISPATCH(pGpu, pKernelGmmu, pFaultBuffer, beginIdx, numFaultPackets) +#define kgmmuFaultBufferGetFault(pGpu, pKernelGmmu, pFaultBuffer, idx) kgmmuFaultBufferGetFault_DISPATCH(pGpu, pKernelGmmu, pFaultBuffer, idx) +#define kgmmuFaultBufferGetFault_HAL(pGpu, pKernelGmmu, pFaultBuffer, idx) kgmmuFaultBufferGetFault_DISPATCH(pGpu, pKernelGmmu, pFaultBuffer, idx) +#define kgmmuCopyFaultPacketToClientShadowBuffer(pGpu, pKernelGmmu, pFaultBuffer, type, getIndex, shadowBufPutIndex, maxBufferEntries, pThreadState, pFaultsCopied) kgmmuCopyFaultPacketToClientShadowBuffer_DISPATCH(pGpu, pKernelGmmu, pFaultBuffer, type, getIndex, shadowBufPutIndex, maxBufferEntries, pThreadState, pFaultsCopied) +#define kgmmuCopyFaultPacketToClientShadowBuffer_HAL(pGpu, pKernelGmmu, pFaultBuffer, type, getIndex, shadowBufPutIndex, maxBufferEntries, pThreadState, pFaultsCopied) kgmmuCopyFaultPacketToClientShadowBuffer_DISPATCH(pGpu, pKernelGmmu, pFaultBuffer, type, getIndex, shadowBufPutIndex, maxBufferEntries, pThreadState, pFaultsCopied) +#define kgmmuIsReplayableShadowFaultBufferFull(pGpu, pKernelGmmu, pClientFaultBuf, shadowBufPutIndex, maxBufferEntries) kgmmuIsReplayableShadowFaultBufferFull_DISPATCH(pGpu, pKernelGmmu, pClientFaultBuf, shadowBufPutIndex, maxBufferEntries) +#define kgmmuIsReplayableShadowFaultBufferFull_HAL(pGpu, pKernelGmmu, pClientFaultBuf, shadowBufPutIndex, maxBufferEntries) kgmmuIsReplayableShadowFaultBufferFull_DISPATCH(pGpu, pKernelGmmu, pClientFaultBuf, shadowBufPutIndex, maxBufferEntries) +#define kgmmuReadClientShadowBufPutIndex(pGpu, pKernelGmmu, gfid, type) kgmmuReadClientShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, gfid, type) +#define kgmmuReadClientShadowBufPutIndex_HAL(pGpu, pKernelGmmu, gfid, type) kgmmuReadClientShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, gfid, type) +#define kgmmuWriteClientShadowBufPutIndex(pGpu, pKernelGmmu, gfid, type, putIndex) kgmmuWriteClientShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, gfid, type, putIndex) +#define kgmmuWriteClientShadowBufPutIndex_HAL(pGpu, pKernelGmmu, gfid, type, putIndex) kgmmuWriteClientShadowBufPutIndex_DISPATCH(pGpu, pKernelGmmu, gfid, type, putIndex) +#define kgmmuGetMinCeEngineId(pKernelGmmu) kgmmuGetMinCeEngineId_DISPATCH(pKernelGmmu) +#define kgmmuGetMinCeEngineId_HAL(pKernelGmmu) kgmmuGetMinCeEngineId_DISPATCH(pKernelGmmu) +#define kgmmuGetMaxCeEngineId(pGpu, pKernelGmmu) kgmmuGetMaxCeEngineId_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuGetMaxCeEngineId_HAL(pGpu, pKernelGmmu) kgmmuGetMaxCeEngineId_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFaultBufferMap(pGpu, pKernelGmmu, index, gfid) kgmmuFaultBufferMap_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuFaultBufferMap_HAL(pGpu, pKernelGmmu, index, gfid) kgmmuFaultBufferMap_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuFaultBufferUnmap(pGpu, pKernelGmmu, index, gfid) kgmmuFaultBufferUnmap_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuFaultBufferUnmap_HAL(pGpu, pKernelGmmu, index, gfid) kgmmuFaultBufferUnmap_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuFaultBufferInit(pGpu, pKernelGmmu) kgmmuFaultBufferInit_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFaultBufferInit_HAL(pGpu, pKernelGmmu) kgmmuFaultBufferInit_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFaultBufferDestroy(pGpu, pKernelGmmu) kgmmuFaultBufferDestroy_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFaultBufferDestroy_HAL(pGpu, pKernelGmmu) kgmmuFaultBufferDestroy_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFaultBufferLoad(pGpu, pKernelGmmu, index, gfid) kgmmuFaultBufferLoad_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuFaultBufferLoad_HAL(pGpu, pKernelGmmu, index, gfid) kgmmuFaultBufferLoad_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuFaultBufferUnload(pGpu, pKernelGmmu, index, gfid) kgmmuFaultBufferUnload_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuFaultBufferUnload_HAL(pGpu, pKernelGmmu, index, gfid) kgmmuFaultBufferUnload_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuEnableFaultBuffer(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid) kgmmuEnableFaultBuffer_DISPATCH(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid) +#define kgmmuEnableFaultBuffer_HAL(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid) kgmmuEnableFaultBuffer_DISPATCH(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid) +#define kgmmuDisableFaultBuffer(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid) kgmmuDisableFaultBuffer_DISPATCH(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid) +#define kgmmuDisableFaultBuffer_HAL(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid) kgmmuDisableFaultBuffer_DISPATCH(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid) +#define kgmmuSetAndGetDefaultFaultBufferSize(pGpu, pKernelGmmu, index, gfid) kgmmuSetAndGetDefaultFaultBufferSize_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuSetAndGetDefaultFaultBufferSize_HAL(pGpu, pKernelGmmu, index, gfid) kgmmuSetAndGetDefaultFaultBufferSize_DISPATCH(pGpu, pKernelGmmu, index, gfid) +#define kgmmuReadMmuFaultInstHiLo(pGpu, pKernelGmmu, arg0, arg1) kgmmuReadMmuFaultInstHiLo_DISPATCH(pGpu, pKernelGmmu, arg0, arg1) +#define kgmmuReadMmuFaultInstHiLo_HAL(pGpu, pKernelGmmu, arg0, arg1) kgmmuReadMmuFaultInstHiLo_DISPATCH(pGpu, pKernelGmmu, arg0, arg1) +#define kgmmuReadMmuFaultAddrHiLo(pGpu, pKernelGmmu, arg0, arg1) kgmmuReadMmuFaultAddrHiLo_DISPATCH(pGpu, pKernelGmmu, arg0, arg1) +#define kgmmuReadMmuFaultAddrHiLo_HAL(pGpu, pKernelGmmu, arg0, arg1) kgmmuReadMmuFaultAddrHiLo_DISPATCH(pGpu, pKernelGmmu, arg0, arg1) +#define kgmmuReadMmuFaultInfo(pGpu, pKernelGmmu) kgmmuReadMmuFaultInfo_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuReadMmuFaultInfo_HAL(pGpu, pKernelGmmu) kgmmuReadMmuFaultInfo_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuWriteMmuFaultBufferSize(pGpu, pKernelGmmu, arg0, arg1, gfid) kgmmuWriteMmuFaultBufferSize_DISPATCH(pGpu, pKernelGmmu, arg0, arg1, gfid) +#define kgmmuWriteMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, arg0, arg1, gfid) kgmmuWriteMmuFaultBufferSize_DISPATCH(pGpu, pKernelGmmu, arg0, arg1, gfid) +#define kgmmuWriteMmuFaultBufferHiLo(pGpu, pKernelGmmu, arg0, arg1, arg2, gfid) kgmmuWriteMmuFaultBufferHiLo_DISPATCH(pGpu, pKernelGmmu, arg0, arg1, arg2, gfid) +#define kgmmuWriteMmuFaultBufferHiLo_HAL(pGpu, pKernelGmmu, arg0, arg1, arg2, gfid) kgmmuWriteMmuFaultBufferHiLo_DISPATCH(pGpu, pKernelGmmu, arg0, arg1, arg2, gfid) +#define kgmmuEnableMmuFaultInterrupts(pGpu, pKernelGmmu, index) kgmmuEnableMmuFaultInterrupts_DISPATCH(pGpu, pKernelGmmu, index) +#define kgmmuEnableMmuFaultInterrupts_HAL(pGpu, pKernelGmmu, index) kgmmuEnableMmuFaultInterrupts_DISPATCH(pGpu, pKernelGmmu, index) +#define kgmmuDisableMmuFaultInterrupts(pGpu, pKernelGmmu, index) kgmmuDisableMmuFaultInterrupts_DISPATCH(pGpu, pKernelGmmu, index) +#define kgmmuDisableMmuFaultInterrupts_HAL(pGpu, pKernelGmmu, index) kgmmuDisableMmuFaultInterrupts_DISPATCH(pGpu, pKernelGmmu, index) +#define kgmmuEnableMmuFaultOverflowIntr(pGpu, pKernelGmmu, index) kgmmuEnableMmuFaultOverflowIntr_DISPATCH(pGpu, pKernelGmmu, index) +#define kgmmuEnableMmuFaultOverflowIntr_HAL(pGpu, pKernelGmmu, index) kgmmuEnableMmuFaultOverflowIntr_DISPATCH(pGpu, pKernelGmmu, index) +#define kgmmuSignExtendFaultAddress(pGpu, pKernelGmmu, pMmuFaultAddress) kgmmuSignExtendFaultAddress_DISPATCH(pGpu, pKernelGmmu, pMmuFaultAddress) +#define kgmmuSignExtendFaultAddress_HAL(pGpu, pKernelGmmu, pMmuFaultAddress) kgmmuSignExtendFaultAddress_DISPATCH(pGpu, pKernelGmmu, pMmuFaultAddress) +#define kgmmuGetFaultType(pGpu, pKernelGmmu, fault, pMmuFaultType) kgmmuGetFaultType_DISPATCH(pGpu, pKernelGmmu, fault, pMmuFaultType) +#define kgmmuGetFaultType_HAL(pGpu, pKernelGmmu, fault, pMmuFaultType) kgmmuGetFaultType_DISPATCH(pGpu, pKernelGmmu, fault, pMmuFaultType) +#define kgmmuIsP2PUnboundInstFault(pKernelGmmu, arg0, arg1) kgmmuIsP2PUnboundInstFault_DISPATCH(pKernelGmmu, arg0, arg1) +#define kgmmuIsP2PUnboundInstFault_HAL(pKernelGmmu, arg0, arg1) kgmmuIsP2PUnboundInstFault_DISPATCH(pKernelGmmu, arg0, arg1) +#define kgmmuServiceVfPriFaults(pGpu, pKernelGmmu, faultType) kgmmuServiceVfPriFaults_DISPATCH(pGpu, pKernelGmmu, faultType) +#define kgmmuServiceVfPriFaults_HAL(pGpu, pKernelGmmu, faultType) kgmmuServiceVfPriFaults_DISPATCH(pGpu, pKernelGmmu, faultType) +#define kgmmuTestVidmemAccessBitBufferError(pGpu, pKernelGmmu, arg0) kgmmuTestVidmemAccessBitBufferError_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuTestVidmemAccessBitBufferError_HAL(pGpu, pKernelGmmu, arg0) kgmmuTestVidmemAccessBitBufferError_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuDisableVidmemAccessBitBuf(pGpu, pKernelGmmu) kgmmuDisableVidmemAccessBitBuf_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuDisableVidmemAccessBitBuf_HAL(pGpu, pKernelGmmu) kgmmuDisableVidmemAccessBitBuf_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuEnableVidmemAccessBitBuf(pGpu, pKernelGmmu) kgmmuEnableVidmemAccessBitBuf_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuEnableVidmemAccessBitBuf_HAL(pGpu, pKernelGmmu) kgmmuEnableVidmemAccessBitBuf_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuClearAccessCounterWriteNak(pGpu, pKernelGmmu) kgmmuClearAccessCounterWriteNak_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuClearAccessCounterWriteNak_HAL(pGpu, pKernelGmmu) kgmmuClearAccessCounterWriteNak_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuServiceMthdBuffFaultInBar2Fault(pGpu, pKernelGmmu) kgmmuServiceMthdBuffFaultInBar2Fault_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuServiceMthdBuffFaultInBar2Fault_HAL(pGpu, pKernelGmmu) kgmmuServiceMthdBuffFaultInBar2Fault_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuFaultCancelTargeted(pGpu, pKernelGmmu, arg0) kgmmuFaultCancelTargeted_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuFaultCancelTargeted_HAL(pGpu, pKernelGmmu, arg0) kgmmuFaultCancelTargeted_DISPATCH(pGpu, pKernelGmmu, arg0) +#define kgmmuFaultCancelIssueInvalidate(pGpu, pKernelGmmu, pCancelInfo, pParams, bGlobal) kgmmuFaultCancelIssueInvalidate_DISPATCH(pGpu, pKernelGmmu, pCancelInfo, pParams, bGlobal) +#define kgmmuFaultCancelIssueInvalidate_HAL(pGpu, pKernelGmmu, pCancelInfo, pParams, bGlobal) kgmmuFaultCancelIssueInvalidate_DISPATCH(pGpu, pKernelGmmu, pCancelInfo, pParams, bGlobal) +#define kgmmuServiceMmuFault(pGpu, pKernelGmmu, pParsedFaultInfo, pMmuExceptionData) kgmmuServiceMmuFault_DISPATCH(pGpu, pKernelGmmu, pParsedFaultInfo, pMmuExceptionData) +#define kgmmuServiceMmuFault_HAL(pGpu, pKernelGmmu, pParsedFaultInfo, pMmuExceptionData) kgmmuServiceMmuFault_DISPATCH(pGpu, pKernelGmmu, pParsedFaultInfo, pMmuExceptionData) +#define kgmmuServiceUnboundInstBlockFault(pGpu, pKernelGmmu, arg0, arg1) kgmmuServiceUnboundInstBlockFault_DISPATCH(pGpu, pKernelGmmu, arg0, arg1) +#define kgmmuServiceUnboundInstBlockFault_HAL(pGpu, pKernelGmmu, arg0, arg1) kgmmuServiceUnboundInstBlockFault_DISPATCH(pGpu, pKernelGmmu, arg0, arg1) +#define kgmmuGetEccCounts(pGpu, pKernelGmmu) kgmmuGetEccCounts_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuGetEccCounts_HAL(pGpu, pKernelGmmu) kgmmuGetEccCounts_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuClearEccCounts(pGpu, pKernelGmmu) kgmmuClearEccCounts_DISPATCH(pGpu, pKernelGmmu) +#define kgmmuClearEccCounts_HAL(pGpu, pKernelGmmu) kgmmuClearEccCounts_DISPATCH(pGpu, pKernelGmmu) #define kgmmuStatePreLoad(pGpu, pEngstate, arg0) kgmmuStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStatePostUnload(pGpu, pEngstate, arg0) kgmmuStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgmmuStateInitUnlocked(pGpu, pEngstate) kgmmuStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kgmmuInitMissing(pGpu, pEngstate) kgmmuInitMissing_DISPATCH(pGpu, pEngstate) #define kgmmuStatePreInitLocked(pGpu, pEngstate) kgmmuStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kgmmuStatePreInitUnlocked(pGpu, pEngstate) kgmmuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) -#define kgmmuClearInterrupt(pGpu, pIntrService, pParams) kgmmuClearInterrupt_DISPATCH(pGpu, pIntrService, pParams) #define kgmmuIsPresent(pGpu, pEngstate) kgmmuIsPresent_DISPATCH(pGpu, pEngstate) +static inline NvU32 kgmmuService_4a4dee(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return 0; +} + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NvU32 kgmmuService(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return 0; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuService(pGpu, pKernelGmmu) kgmmuService_4a4dee(pGpu, pKernelGmmu) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuService_HAL(pGpu, pKernelGmmu) kgmmuService(pGpu, pKernelGmmu) + NvU64 kgmmuGetMaxBigPageSize_GM107(struct KernelGmmu *pKernelGmmu); @@ -675,20 +941,6 @@ static inline NvU64 kgmmuGetBigPageSize(struct KernelGmmu *pKernelGmmu) { #define kgmmuGetBigPageSize_HAL(pKernelGmmu) kgmmuGetBigPageSize(pKernelGmmu) -NV_STATUS kgmmuInitStaticInfo_KERNEL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo); - - -#ifdef __nvoc_kern_gmmu_h_disabled -static inline NV_STATUS kgmmuInitStaticInfo(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo) { - NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_gmmu_h_disabled -#define kgmmuInitStaticInfo(pGpu, pKernelGmmu, pStaticInfo) kgmmuInitStaticInfo_KERNEL(pGpu, pKernelGmmu, pStaticInfo) -#endif //__nvoc_kern_gmmu_h_disabled - -#define kgmmuInitStaticInfo_HAL(pGpu, pKernelGmmu, pStaticInfo) kgmmuInitStaticInfo(pGpu, pKernelGmmu, pStaticInfo) - void kgmmuFmtInitCaps_GM20X(struct KernelGmmu *pKernelGmmu, struct GMMU_FMT *pFmt); @@ -879,6 +1131,20 @@ static inline NV_STATUS kgmmuReadFaultBufferGetPtr(OBJGPU *pGpu, struct KernelGm #define kgmmuReadFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, index, pGetOffset, arg0) kgmmuReadFaultBufferGetPtr(pGpu, pKernelGmmu, index, pGetOffset, arg0) +NV_STATUS kgmmuWriteFaultBufferGetPtr_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 getValue, struct THREAD_STATE_NODE *arg0); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuWriteFaultBufferGetPtr(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 getValue, struct THREAD_STATE_NODE *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuWriteFaultBufferGetPtr(pGpu, pKernelGmmu, index, getValue, arg0) kgmmuWriteFaultBufferGetPtr_TU102(pGpu, pKernelGmmu, index, getValue, arg0) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuWriteFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, index, getValue, arg0) kgmmuWriteFaultBufferGetPtr(pGpu, pKernelGmmu, index, getValue, arg0) + NV_STATUS kgmmuReadFaultBufferPutPtr_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 *pPutOffset, struct THREAD_STATE_NODE *arg0); @@ -1057,6 +1323,138 @@ static inline void kgmmuClearReplayableFaultIntr(OBJGPU *pGpu, struct KernelGmmu #define kgmmuClearReplayableFaultIntr_HAL(pGpu, pKernelGmmu, arg0) kgmmuClearReplayableFaultIntr(pGpu, pKernelGmmu, arg0) +void kgmmuPrintFaultInfo_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, FIFO_MMU_EXCEPTION_DATA *arg1); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline void kgmmuPrintFaultInfo(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, FIFO_MMU_EXCEPTION_DATA *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuPrintFaultInfo(pGpu, pKernelGmmu, arg0, arg1) kgmmuPrintFaultInfo_TU102(pGpu, pKernelGmmu, arg0, arg1) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuPrintFaultInfo_HAL(pGpu, pKernelGmmu, arg0, arg1) kgmmuPrintFaultInfo(pGpu, pKernelGmmu, arg0, arg1) + +static inline NV_STATUS kgmmuInitCeMmuFaultIdRange_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return NV_OK; +} + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuInitCeMmuFaultIdRange(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuInitCeMmuFaultIdRange(pGpu, pKernelGmmu) kgmmuInitCeMmuFaultIdRange_56cd7a(pGpu, pKernelGmmu) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuInitCeMmuFaultIdRange_HAL(pGpu, pKernelGmmu) kgmmuInitCeMmuFaultIdRange(pGpu, pKernelGmmu) + +NV_STATUS kgmmuServiceNonReplayableFault_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuServiceNonReplayableFault(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuServiceNonReplayableFault(pGpu, pKernelGmmu) kgmmuServiceNonReplayableFault_GV100(pGpu, pKernelGmmu) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuServiceNonReplayableFault_HAL(pGpu, pKernelGmmu) kgmmuServiceNonReplayableFault(pGpu, pKernelGmmu) + +NV_STATUS kgmmuHandleNonReplayableFaultPacket_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_PACKET *arg0); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuHandleNonReplayableFaultPacket(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_PACKET *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuHandleNonReplayableFaultPacket(pGpu, pKernelGmmu, arg0) kgmmuHandleNonReplayableFaultPacket_GV100(pGpu, pKernelGmmu, arg0) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuHandleNonReplayableFaultPacket_HAL(pGpu, pKernelGmmu, arg0) kgmmuHandleNonReplayableFaultPacket(pGpu, pKernelGmmu, arg0) + +NV_STATUS kgmmuNotifyNonReplayableFault_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuNotifyNonReplayableFault(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuNotifyNonReplayableFault(pGpu, pKernelGmmu, arg0) kgmmuNotifyNonReplayableFault_GV100(pGpu, pKernelGmmu, arg0) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuNotifyNonReplayableFault_HAL(pGpu, pKernelGmmu, arg0) kgmmuNotifyNonReplayableFault(pGpu, pKernelGmmu, arg0) + +NvU32 kgmmuGetFaultInfoFromFaultPckt_GV100(struct KernelGmmu *pKernelGmmu, MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NvU32 kgmmuGetFaultInfoFromFaultPckt(struct KernelGmmu *pKernelGmmu, MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return 0; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuGetFaultInfoFromFaultPckt(pKernelGmmu, pParsedFaultEntry) kgmmuGetFaultInfoFromFaultPckt_GV100(pKernelGmmu, pParsedFaultEntry) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuGetFaultInfoFromFaultPckt_HAL(pKernelGmmu, pParsedFaultEntry) kgmmuGetFaultInfoFromFaultPckt(pKernelGmmu, pParsedFaultEntry) + +static inline NV_STATUS kgmmuServiceChannelMmuFault_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData, struct KernelChannel *pKernelChannel) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuServiceChannelMmuFault_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData, struct KernelChannel *pKernelChannel); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuServiceChannelMmuFault(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData, struct KernelChannel *pKernelChannel) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuServiceChannelMmuFault(pGpu, pKernelGmmu, pParsedFaultEntry, pMmuExceptionData, pKernelChannel) kgmmuServiceChannelMmuFault_92bfc3(pGpu, pKernelGmmu, pParsedFaultEntry, pMmuExceptionData, pKernelChannel) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuServiceChannelMmuFault_HAL(pGpu, pKernelGmmu, pParsedFaultEntry, pMmuExceptionData, pKernelChannel) kgmmuServiceChannelMmuFault(pGpu, pKernelGmmu, pParsedFaultEntry, pMmuExceptionData, pKernelChannel) + +NV_STATUS kgmmuServicePriFaults_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuServicePriFaults(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuServicePriFaults(pGpu, pKernelGmmu) kgmmuServicePriFaults_GV100(pGpu, pKernelGmmu) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuServicePriFaults_HAL(pGpu, pKernelGmmu) kgmmuServicePriFaults(pGpu, pKernelGmmu) + +NV_STATUS kgmmuCheckAndDecideBigPageSize_GP100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuCheckAndDecideBigPageSize(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuCheckAndDecideBigPageSize(pGpu, pKernelGmmu) kgmmuCheckAndDecideBigPageSize_GP100(pGpu, pKernelGmmu) +#endif //__nvoc_kern_gmmu_h_disabled + +#define kgmmuCheckAndDecideBigPageSize_HAL(pGpu, pKernelGmmu) kgmmuCheckAndDecideBigPageSize(pGpu, pKernelGmmu) + NV_STATUS kgmmuConstructEngine_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, ENGDESCRIPTOR arg0); static inline NV_STATUS kgmmuConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, ENGDESCRIPTOR arg0) { @@ -1069,6 +1467,18 @@ static inline NV_STATUS kgmmuStateInitLocked_DISPATCH(OBJGPU *pGpu, struct Kerne return pKernelGmmu->__kgmmuStateInitLocked__(pGpu, pKernelGmmu); } +NV_STATUS kgmmuStateLoad_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +static inline NV_STATUS kgmmuStateLoad_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return pKernelGmmu->__kgmmuStateLoad__(pGpu, pKernelGmmu, arg0); +} + +NV_STATUS kgmmuStateUnload_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +static inline NV_STATUS kgmmuStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return pKernelGmmu->__kgmmuStateUnload__(pGpu, pKernelGmmu, arg0); +} + NV_STATUS kgmmuStatePostLoad_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0); static inline NV_STATUS kgmmuStatePostLoad_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { @@ -1087,18 +1497,32 @@ static inline void kgmmuStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *p pKernelGmmu->__kgmmuStateDestroy__(pGpu, pKernelGmmu); } -void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[168]); +void kgmmuRegisterIntrService_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[171]); -static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[168]) { +static inline void kgmmuRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceRecord arg0[171]) { pKernelGmmu->__kgmmuRegisterIntrService__(pGpu, pKernelGmmu, arg0); } +NvBool kgmmuClearInterrupt_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceClearInterruptArguments *pParams); + +static inline NvBool kgmmuClearInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceClearInterruptArguments *pParams) { + return pKernelGmmu->__kgmmuClearInterrupt__(pGpu, pKernelGmmu, pParams); +} + NvU32 kgmmuServiceInterrupt_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceServiceInterruptArguments *pParams); static inline NvU32 kgmmuServiceInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceServiceInterruptArguments *pParams) { return pKernelGmmu->__kgmmuServiceInterrupt__(pGpu, pKernelGmmu, pParams); } +static inline NV_STATUS kgmmuServiceNotificationInterrupt_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceServiceNotificationInterruptArguments *pParams) { + return NV_OK; +} + +static inline NV_STATUS kgmmuServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, IntrServiceServiceNotificationInterruptArguments *pParams) { + return pKernelGmmu->__kgmmuServiceNotificationInterrupt__(pGpu, pKernelGmmu, pParams); +} + NV_STATUS kgmmuInstBlkVaLimitGet_GV100(struct KernelGmmu *pKernelGmmu, struct OBJVASPACE *pVAS, NvU32 subctxId, INST_BLK_INIT_PARAMS *pParams, NvU32 *pOffset, NvU64 *pData); static inline NV_STATUS kgmmuInstBlkVaLimitGet_f03539(struct KernelGmmu *pKernelGmmu, struct OBJVASPACE *pVAS, NvU32 subctxId, INST_BLK_INIT_PARAMS *pParams, NvU32 *pOffset, NvU64 *pData) { @@ -1258,6 +1682,16 @@ static inline NV_STATUS kgmmuIssueReplayableFaultBufferFlush_DISPATCH(OBJGPU *pG return pKernelGmmu->__kgmmuIssueReplayableFaultBufferFlush__(pGpu, pKernelGmmu); } +NV_STATUS kgmmuToggleFaultOnPrefetch_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool bEnable); + +static inline NV_STATUS kgmmuToggleFaultOnPrefetch_46f6a7(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool bEnable) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuToggleFaultOnPrefetch_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvBool bEnable) { + return pKernelGmmu->__kgmmuToggleFaultOnPrefetch__(pGpu, pKernelGmmu, bEnable); +} + NV_STATUS kgmmuFaultBufferAllocSharedMemory_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0); static inline NV_STATUS kgmmuFaultBufferAllocSharedMemory_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE arg0) { @@ -1306,16 +1740,511 @@ static inline NvU32 kgmmuReadShadowBufPutIndex_DISPATCH(OBJGPU *pGpu, struct Ker return pKernelGmmu->__kgmmuReadShadowBufPutIndex__(pGpu, pKernelGmmu, type); } -static inline NV_STATUS kgmmuStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { - return pEngstate->__kgmmuStateLoad__(pGpu, pEngstate, arg0); +NvBool kgmmuIsFaultEngineBar1_TU102(struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +NvBool kgmmuIsFaultEngineBar1_GH100(struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +static inline NvBool kgmmuIsFaultEngineBar1_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return pKernelGmmu->__kgmmuIsFaultEngineBar1__(pKernelGmmu, arg0); +} + +NvBool kgmmuIsFaultEngineBar2_TU102(struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +NvBool kgmmuIsFaultEngineBar2_GH100(struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +static inline NvBool kgmmuIsFaultEngineBar2_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return pKernelGmmu->__kgmmuIsFaultEngineBar2__(pKernelGmmu, arg0); +} + +NvBool kgmmuIsFaultEnginePhysical_GV100(struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +NvBool kgmmuIsFaultEnginePhysical_GH100(struct KernelGmmu *pKernelGmmu, NvU32 arg0); + +static inline NvBool kgmmuIsFaultEnginePhysical_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return pKernelGmmu->__kgmmuIsFaultEnginePhysical__(pKernelGmmu, arg0); +} + +static inline NV_STATUS kgmmuCopyMmuFaults_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *pThreadState, NvU32 *entriesCopied, FAULT_BUFFER_TYPE type) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuCopyMmuFaults_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *pThreadState, NvU32 *entriesCopied, FAULT_BUFFER_TYPE type); + +static inline NV_STATUS kgmmuCopyMmuFaults_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *pThreadState, NvU32 *entriesCopied, FAULT_BUFFER_TYPE type) { + return pKernelGmmu->__kgmmuCopyMmuFaults__(pGpu, pKernelGmmu, pThreadState, entriesCopied, type); +} + +static inline NV_STATUS kgmmuParseFaultPacket_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 pFaultPacket, NvP64 pParsedFaultEntry) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuParseFaultPacket_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 pFaultPacket, NvP64 pParsedFaultEntry); + +static inline NV_STATUS kgmmuParseFaultPacket_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 pFaultPacket, NvP64 pParsedFaultEntry) { + return pKernelGmmu->__kgmmuParseFaultPacket__(pGpu, pKernelGmmu, pFaultPacket, pParsedFaultEntry); +} + +static inline void kgmmuFaultBufferClearPackets_f2d351(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct HW_FAULT_BUFFER *pFaultBuffer, NvU32 beginIdx, NvU32 numFaultPackets) { + NV_ASSERT_PRECOMP(0); +} + +void kgmmuFaultBufferClearPackets_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct HW_FAULT_BUFFER *pFaultBuffer, NvU32 beginIdx, NvU32 numFaultPackets); + +static inline void kgmmuFaultBufferClearPackets_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct HW_FAULT_BUFFER *pFaultBuffer, NvU32 beginIdx, NvU32 numFaultPackets) { + pKernelGmmu->__kgmmuFaultBufferClearPackets__(pGpu, pKernelGmmu, pFaultBuffer, beginIdx, numFaultPackets); +} + +static inline GMMU_FAULT_PACKET *kgmmuFaultBufferGetFault_dc3e6c(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct HW_FAULT_BUFFER *pFaultBuffer, NvU32 idx) { + NV_ASSERT_PRECOMP(0); + return ((void *)0); +} + +GMMU_FAULT_PACKET *kgmmuFaultBufferGetFault_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct HW_FAULT_BUFFER *pFaultBuffer, NvU32 idx); + +static inline GMMU_FAULT_PACKET *kgmmuFaultBufferGetFault_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct HW_FAULT_BUFFER *pFaultBuffer, NvU32 idx) { + return pKernelGmmu->__kgmmuFaultBufferGetFault__(pGpu, pKernelGmmu, pFaultBuffer, idx); +} + +static inline NvU32 kgmmuCopyFaultPacketToClientShadowBuffer_13cd8d(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct GMMU_FAULT_BUFFER *pFaultBuffer, FAULT_BUFFER_TYPE type, NvU32 getIndex, NvU32 shadowBufPutIndex, NvU32 maxBufferEntries, struct THREAD_STATE_NODE *pThreadState, NvU32 *pFaultsCopied) { + NV_ASSERT_PRECOMP(0); + return 0; +} + +NvU32 kgmmuCopyFaultPacketToClientShadowBuffer_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct GMMU_FAULT_BUFFER *pFaultBuffer, FAULT_BUFFER_TYPE type, NvU32 getIndex, NvU32 shadowBufPutIndex, NvU32 maxBufferEntries, struct THREAD_STATE_NODE *pThreadState, NvU32 *pFaultsCopied); + +NvU32 kgmmuCopyFaultPacketToClientShadowBuffer_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct GMMU_FAULT_BUFFER *pFaultBuffer, FAULT_BUFFER_TYPE type, NvU32 getIndex, NvU32 shadowBufPutIndex, NvU32 maxBufferEntries, struct THREAD_STATE_NODE *pThreadState, NvU32 *pFaultsCopied); + +static inline NvU32 kgmmuCopyFaultPacketToClientShadowBuffer_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct GMMU_FAULT_BUFFER *pFaultBuffer, FAULT_BUFFER_TYPE type, NvU32 getIndex, NvU32 shadowBufPutIndex, NvU32 maxBufferEntries, struct THREAD_STATE_NODE *pThreadState, NvU32 *pFaultsCopied) { + return pKernelGmmu->__kgmmuCopyFaultPacketToClientShadowBuffer__(pGpu, pKernelGmmu, pFaultBuffer, type, getIndex, shadowBufPutIndex, maxBufferEntries, pThreadState, pFaultsCopied); +} + +static inline NvBool kgmmuIsReplayableShadowFaultBufferFull_ceaee8(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientFaultBuf, NvU32 shadowBufPutIndex, NvU32 maxBufferEntries) { + NV_ASSERT_PRECOMP(0); + return ((NvBool)(0 != 0)); +} + +NvBool kgmmuIsReplayableShadowFaultBufferFull_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientFaultBuf, NvU32 shadowBufPutIndex, NvU32 maxBufferEntries); + +static inline NvBool kgmmuIsReplayableShadowFaultBufferFull_491d52(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientFaultBuf, NvU32 shadowBufPutIndex, NvU32 maxBufferEntries) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kgmmuIsReplayableShadowFaultBufferFull_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientFaultBuf, NvU32 shadowBufPutIndex, NvU32 maxBufferEntries) { + return pKernelGmmu->__kgmmuIsReplayableShadowFaultBufferFull__(pGpu, pKernelGmmu, pClientFaultBuf, shadowBufPutIndex, maxBufferEntries); +} + +static inline NvU32 kgmmuReadClientShadowBufPutIndex_13cd8d(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid, FAULT_BUFFER_TYPE type) { + NV_ASSERT_PRECOMP(0); + return 0; +} + +NvU32 kgmmuReadClientShadowBufPutIndex_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid, FAULT_BUFFER_TYPE type); + +static inline NvU32 kgmmuReadClientShadowBufPutIndex_4a4dee(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid, FAULT_BUFFER_TYPE type) { + return 0; +} + +static inline NvU32 kgmmuReadClientShadowBufPutIndex_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid, FAULT_BUFFER_TYPE type) { + return pKernelGmmu->__kgmmuReadClientShadowBufPutIndex__(pGpu, pKernelGmmu, gfid, type); +} + +static inline void kgmmuWriteClientShadowBufPutIndex_f2d351(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid, FAULT_BUFFER_TYPE type, NvU32 putIndex) { + NV_ASSERT_PRECOMP(0); +} + +void kgmmuWriteClientShadowBufPutIndex_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid, FAULT_BUFFER_TYPE type, NvU32 putIndex); + +static inline void kgmmuWriteClientShadowBufPutIndex_b3696a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid, FAULT_BUFFER_TYPE type, NvU32 putIndex) { + return; +} + +static inline void kgmmuWriteClientShadowBufPutIndex_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 gfid, FAULT_BUFFER_TYPE type, NvU32 putIndex) { + pKernelGmmu->__kgmmuWriteClientShadowBufPutIndex__(pGpu, pKernelGmmu, gfid, type, putIndex); +} + +NvU32 kgmmuGetMinCeEngineId_GV100(struct KernelGmmu *pKernelGmmu); + +NvU32 kgmmuGetMinCeEngineId_GH100(struct KernelGmmu *pKernelGmmu); + +static inline NvU32 kgmmuGetMinCeEngineId_DISPATCH(struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuGetMinCeEngineId__(pKernelGmmu); +} + +NvU32 kgmmuGetMaxCeEngineId_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +NvU32 kgmmuGetMaxCeEngineId_GA100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +NvU32 kgmmuGetMaxCeEngineId_AD102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +NvU32 kgmmuGetMaxCeEngineId_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NvU32 kgmmuGetMaxCeEngineId_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuGetMaxCeEngineId__(pGpu, pKernelGmmu); +} + +static inline NV_STATUS kgmmuFaultBufferMap_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuFaultBufferMap_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid); + +static inline NV_STATUS kgmmuFaultBufferMap_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid) { + return pKernelGmmu->__kgmmuFaultBufferMap__(pGpu, pKernelGmmu, index, gfid); +} + +static inline NV_STATUS kgmmuFaultBufferUnmap_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuFaultBufferUnmap_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid); + +static inline NV_STATUS kgmmuFaultBufferUnmap_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid) { + return pKernelGmmu->__kgmmuFaultBufferUnmap__(pGpu, pKernelGmmu, index, gfid); +} + +static inline NV_STATUS kgmmuFaultBufferInit_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return NV_OK; +} + +NV_STATUS kgmmuFaultBufferInit_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NV_STATUS kgmmuFaultBufferInit_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuFaultBufferInit__(pGpu, pKernelGmmu); +} + +static inline NV_STATUS kgmmuFaultBufferDestroy_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return NV_OK; +} + +NV_STATUS kgmmuFaultBufferDestroy_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NV_STATUS kgmmuFaultBufferDestroy_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuFaultBufferDestroy__(pGpu, pKernelGmmu); +} + +static inline NV_STATUS kgmmuFaultBufferLoad_ac1694(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid) { + return NV_OK; +} + +NV_STATUS kgmmuFaultBufferLoad_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid); + +static inline NV_STATUS kgmmuFaultBufferLoad_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid) { + return pKernelGmmu->__kgmmuFaultBufferLoad__(pGpu, pKernelGmmu, index, gfid); +} + +static inline NV_STATUS kgmmuFaultBufferUnload_ac1694(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid) { + return NV_OK; +} + +NV_STATUS kgmmuFaultBufferUnload_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid); + +static inline NV_STATUS kgmmuFaultBufferUnload_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvU32 gfid) { + return pKernelGmmu->__kgmmuFaultBufferUnload__(pGpu, pKernelGmmu, index, gfid); +} + +static inline NV_STATUS kgmmuEnableFaultBuffer_395e98(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvBool bIsErrorRecovery, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuEnableFaultBuffer_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvBool bIsErrorRecovery, NvU32 gfid); + +static inline NV_STATUS kgmmuEnableFaultBuffer_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvBool bIsErrorRecovery, NvU32 gfid) { + return pKernelGmmu->__kgmmuEnableFaultBuffer__(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid); +} + +static inline NV_STATUS kgmmuDisableFaultBuffer_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvBool bIsErrorRecovery, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuDisableFaultBuffer_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvBool bIsErrorRecovery, NvU32 gfid); + +static inline NV_STATUS kgmmuDisableFaultBuffer_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index, NvBool bIsErrorRecovery, NvU32 gfid) { + return pKernelGmmu->__kgmmuDisableFaultBuffer__(pGpu, pKernelGmmu, index, bIsErrorRecovery, gfid); +} + +static inline NvU32 kgmmuSetAndGetDefaultFaultBufferSize_13cd8d(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE index, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + return 0; +} + +NvU32 kgmmuSetAndGetDefaultFaultBufferSize_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE index, NvU32 gfid); + +static inline NvU32 kgmmuSetAndGetDefaultFaultBufferSize_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, FAULT_BUFFER_TYPE index, NvU32 gfid) { + return pKernelGmmu->__kgmmuSetAndGetDefaultFaultBufferSize__(pGpu, pKernelGmmu, index, gfid); +} + +static inline void kgmmuReadMmuFaultInstHiLo_f2d351(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 *arg0, NvU32 *arg1) { + NV_ASSERT_PRECOMP(0); } -static inline NV_STATUS kgmmuStateUnload_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { - return pEngstate->__kgmmuStateUnload__(pGpu, pEngstate, arg0); +void kgmmuReadMmuFaultInstHiLo_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 *arg0, NvU32 *arg1); + +static inline void kgmmuReadMmuFaultInstHiLo_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 *arg0, NvU32 *arg1) { + pKernelGmmu->__kgmmuReadMmuFaultInstHiLo__(pGpu, pKernelGmmu, arg0, arg1); +} + +static inline void kgmmuReadMmuFaultAddrHiLo_f2d351(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 *arg0, NvU32 *arg1) { + NV_ASSERT_PRECOMP(0); +} + +void kgmmuReadMmuFaultAddrHiLo_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 *arg0, NvU32 *arg1); + +static inline void kgmmuReadMmuFaultAddrHiLo_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 *arg0, NvU32 *arg1) { + pKernelGmmu->__kgmmuReadMmuFaultAddrHiLo__(pGpu, pKernelGmmu, arg0, arg1); +} + +static inline NvU32 kgmmuReadMmuFaultInfo_a547a8(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_PRECOMP(0); + return -1; +} + +NvU32 kgmmuReadMmuFaultInfo_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NvU32 kgmmuReadMmuFaultInfo_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuReadMmuFaultInfo__(pGpu, pKernelGmmu); +} + +static inline void kgmmuWriteMmuFaultBufferSize_f2d351(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); +} + +void kgmmuWriteMmuFaultBufferSize_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1, NvU32 gfid); + +static inline void kgmmuWriteMmuFaultBufferSize_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1, NvU32 gfid) { + pKernelGmmu->__kgmmuWriteMmuFaultBufferSize__(pGpu, pKernelGmmu, arg0, arg1, gfid); +} + +static inline void kgmmuWriteMmuFaultBufferHiLo_f2d351(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); +} + +void kgmmuWriteMmuFaultBufferHiLo_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU32 gfid); + +static inline void kgmmuWriteMmuFaultBufferHiLo_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1, NvU32 arg2, NvU32 gfid) { + pKernelGmmu->__kgmmuWriteMmuFaultBufferHiLo__(pGpu, pKernelGmmu, arg0, arg1, arg2, gfid); } -static inline NV_STATUS kgmmuServiceNotificationInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelGmmu *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) { - return pIntrService->__kgmmuServiceNotificationInterrupt__(pGpu, pIntrService, pParams); +static inline NV_STATUS kgmmuEnableMmuFaultInterrupts_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuEnableMmuFaultInterrupts_46f6a7(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuEnableMmuFaultInterrupts_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + return pKernelGmmu->__kgmmuEnableMmuFaultInterrupts__(pGpu, pKernelGmmu, index); +} + +static inline NV_STATUS kgmmuDisableMmuFaultInterrupts_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuDisableMmuFaultInterrupts_46f6a7(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuDisableMmuFaultInterrupts_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + return pKernelGmmu->__kgmmuDisableMmuFaultInterrupts__(pGpu, pKernelGmmu, index); +} + +static inline NV_STATUS kgmmuEnableMmuFaultOverflowIntr_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuEnableMmuFaultOverflowIntr_46f6a7(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuEnableMmuFaultOverflowIntr_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 index) { + return pKernelGmmu->__kgmmuEnableMmuFaultOverflowIntr__(pGpu, pKernelGmmu, index); +} + +static inline void kgmmuSignExtendFaultAddress_f2d351(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU64 *pMmuFaultAddress) { + NV_ASSERT_PRECOMP(0); +} + +void kgmmuSignExtendFaultAddress_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU64 *pMmuFaultAddress); + +void kgmmuSignExtendFaultAddress_GH100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU64 *pMmuFaultAddress); + +static inline void kgmmuSignExtendFaultAddress_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU64 *pMmuFaultAddress) { + pKernelGmmu->__kgmmuSignExtendFaultAddress__(pGpu, pKernelGmmu, pMmuFaultAddress); +} + +static inline NV_STATUS kgmmuGetFaultType_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 fault, FAULT_TYPE *pMmuFaultType) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuGetFaultType_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 fault, FAULT_TYPE *pMmuFaultType); + +static inline NV_STATUS kgmmuGetFaultType_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 fault, FAULT_TYPE *pMmuFaultType) { + return pKernelGmmu->__kgmmuGetFaultType__(pGpu, pKernelGmmu, fault, pMmuFaultType); +} + +static inline NvBool kgmmuIsP2PUnboundInstFault_92bfc3(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NvBool kgmmuIsP2PUnboundInstFault_GA100(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1); + +static inline NvBool kgmmuIsP2PUnboundInstFault_491d52(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kgmmuIsP2PUnboundInstFault_DISPATCH(struct KernelGmmu *pKernelGmmu, NvU32 arg0, NvU32 arg1) { + return pKernelGmmu->__kgmmuIsP2PUnboundInstFault__(pKernelGmmu, arg0, arg1); +} + +NV_STATUS kgmmuServiceVfPriFaults_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 faultType); + +static inline NV_STATUS kgmmuServiceVfPriFaults_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 faultType) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuServiceVfPriFaults_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 faultType) { + return pKernelGmmu->__kgmmuServiceVfPriFaults__(pGpu, pKernelGmmu, faultType); +} + +static inline NvBool kgmmuTestVidmemAccessBitBufferError_491d52(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool kgmmuTestVidmemAccessBitBufferError_ceaee8(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + NV_ASSERT_PRECOMP(0); + return ((NvBool)(0 != 0)); +} + +static inline NvBool kgmmuTestVidmemAccessBitBufferError_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvU32 arg0) { + return pKernelGmmu->__kgmmuTestVidmemAccessBitBufferError__(pGpu, pKernelGmmu, arg0); +} + +static inline void kgmmuDisableVidmemAccessBitBuf_b3696a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return; +} + +static inline void kgmmuDisableVidmemAccessBitBuf_e426af(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_PRECOMP(0); + return; +} + +static inline void kgmmuDisableVidmemAccessBitBuf_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + pKernelGmmu->__kgmmuDisableVidmemAccessBitBuf__(pGpu, pKernelGmmu); +} + +static inline NV_STATUS kgmmuEnableVidmemAccessBitBuf_46f6a7(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuEnableVidmemAccessBitBuf_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuEnableVidmemAccessBitBuf_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuEnableVidmemAccessBitBuf__(pGpu, pKernelGmmu); +} + +static inline void kgmmuClearAccessCounterWriteNak_b3696a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return; +} + +static inline void kgmmuClearAccessCounterWriteNak_e426af(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_PRECOMP(0); + return; +} + +static inline void kgmmuClearAccessCounterWriteNak_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + pKernelGmmu->__kgmmuClearAccessCounterWriteNak__(pGpu, pKernelGmmu); +} + +static inline NV_STATUS kgmmuServiceMthdBuffFaultInBar2Fault_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return NV_OK; +} + +static inline NV_STATUS kgmmuServiceMthdBuffFaultInBar2Fault_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuServiceMthdBuffFaultInBar2Fault_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuServiceMthdBuffFaultInBar2Fault__(pGpu, pKernelGmmu); +} + +NV_STATUS kgmmuFaultCancelTargeted_VF(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_CANCEL_INFO *arg0); + +static inline NV_STATUS kgmmuFaultCancelTargeted_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_CANCEL_INFO *arg0) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuFaultCancelTargeted_GP100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_CANCEL_INFO *arg0); + +static inline NV_STATUS kgmmuFaultCancelTargeted_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_CANCEL_INFO *arg0) { + return pKernelGmmu->__kgmmuFaultCancelTargeted__(pGpu, pKernelGmmu, arg0); +} + +static inline NV_STATUS kgmmuFaultCancelIssueInvalidate_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_CANCEL_INFO *pCancelInfo, TLB_INVALIDATE_PARAMS *pParams, NvBool bGlobal) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgmmuFaultCancelIssueInvalidate_GP100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_CANCEL_INFO *pCancelInfo, TLB_INVALIDATE_PARAMS *pParams, NvBool bGlobal); + +static inline NV_STATUS kgmmuFaultCancelIssueInvalidate_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, GMMU_FAULT_CANCEL_INFO *pCancelInfo, TLB_INVALIDATE_PARAMS *pParams, NvBool bGlobal) { + return pKernelGmmu->__kgmmuFaultCancelIssueInvalidate__(pGpu, pKernelGmmu, pCancelInfo, pParams, bGlobal); +} + +NV_STATUS kgmmuServiceMmuFault_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 pParsedFaultInfo, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData); + +NV_STATUS kgmmuServiceMmuFault_GA100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 pParsedFaultInfo, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData); + +static inline NV_STATUS kgmmuServiceMmuFault_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 pParsedFaultInfo, FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData) { + return pKernelGmmu->__kgmmuServiceMmuFault__(pGpu, pKernelGmmu, pParsedFaultInfo, pMmuExceptionData); +} + +static inline NV_STATUS kgmmuServiceUnboundInstBlockFault_56cd7a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 arg0, FIFO_MMU_EXCEPTION_DATA *arg1) { + return NV_OK; +} + +static inline NV_STATUS kgmmuServiceUnboundInstBlockFault_92bfc3(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 arg0, FIFO_MMU_EXCEPTION_DATA *arg1) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kgmmuServiceUnboundInstBlockFault_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvP64 arg0, FIFO_MMU_EXCEPTION_DATA *arg1) { + return pKernelGmmu->__kgmmuServiceUnboundInstBlockFault__(pGpu, pKernelGmmu, arg0, arg1); +} + +NvU32 kgmmuGetEccCounts_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline NvU32 kgmmuGetEccCounts_4a4dee(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return 0; +} + +static inline NvU32 kgmmuGetEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return pKernelGmmu->__kgmmuGetEccCounts__(pGpu, pKernelGmmu); +} + +void kgmmuClearEccCounts_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +static inline void kgmmuClearEccCounts_b3696a(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + return; +} + +static inline void kgmmuClearEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + pKernelGmmu->__kgmmuClearEccCounts__(pGpu, pKernelGmmu); } static inline NV_STATUS kgmmuStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate, NvU32 arg0) { @@ -1342,10 +2271,6 @@ static inline NV_STATUS kgmmuStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct return pEngstate->__kgmmuStatePreInitUnlocked__(pGpu, pEngstate); } -static inline NvBool kgmmuClearInterrupt_DISPATCH(struct OBJGPU *pGpu, struct KernelGmmu *pIntrService, IntrServiceClearInterruptArguments *pParams) { - return pIntrService->__kgmmuClearInterrupt__(pGpu, pIntrService, pParams); -} - static inline NvBool kgmmuIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGmmu *pEngstate) { return pEngstate->__kgmmuIsPresent__(pGpu, pEngstate); } @@ -1542,6 +2467,28 @@ static inline const struct GMMU_FMT *kgmmuFmtGetLatestSupportedFormat(OBJGPU *pG #define kgmmuFmtGetLatestSupportedFormat(pGpu, pKernelGmmu) kgmmuFmtGetLatestSupportedFormat_IMPL(pGpu, pKernelGmmu) #endif //__nvoc_kern_gmmu_h_disabled +NvU32 kgmmuGetFaultBufferReservedFbSpaceSize_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NvU32 kgmmuGetFaultBufferReservedFbSpaceSize(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return 0; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuGetFaultBufferReservedFbSpaceSize(pGpu, pKernelGmmu) kgmmuGetFaultBufferReservedFbSpaceSize_IMPL(pGpu, pKernelGmmu) +#endif //__nvoc_kern_gmmu_h_disabled + +NV_STATUS kgmmuFaultBufferReplayableSetup_IMPL(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvHandle arg0, NvHandle arg1, NvU32 arg2, RmPhysAddr *arg3); + +#ifdef __nvoc_kern_gmmu_h_disabled +static inline NV_STATUS kgmmuFaultBufferReplayableSetup(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, NvHandle arg0, NvHandle arg1, NvU32 arg2, RmPhysAddr *arg3) { + NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_gmmu_h_disabled +#define kgmmuFaultBufferReplayableSetup(pGpu, pKernelGmmu, arg0, arg1, arg2, arg3) kgmmuFaultBufferReplayableSetup_IMPL(pGpu, pKernelGmmu, arg0, arg1, arg2, arg3) +#endif //__nvoc_kern_gmmu_h_disabled + NvU64 kgmmuGetMinBigPageSize_IMPL(struct KernelGmmu *pKernelGmmu); #ifdef __nvoc_kern_gmmu_h_disabled diff --git a/src/nvidia/generated/g_kern_hwpm_common_defs_nvoc.c b/src/nvidia/generated/g_kern_hwpm_common_defs_nvoc.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/nvidia/generated/g_kern_hwpm_common_defs_nvoc.h b/src/nvidia/generated/g_kern_hwpm_common_defs_nvoc.h new file mode 100644 index 0000000000..c21e1d7e40 --- /dev/null +++ b/src/nvidia/generated/g_kern_hwpm_common_defs_nvoc.h @@ -0,0 +1,76 @@ +#ifndef _G_KERN_HWPM_COMMON_DEFS_NVOC_H_ +#define _G_KERN_HWPM_COMMON_DEFS_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef KERN_HWPM_COMMON_DEFS_H +#define KERN_HWPM_COMMON_DEFS_H + +#include "lib/ref_count.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" + +#define NV_HWPM_STREAM_FLAGS_CPUVA_EXTERNAL 0x0001 + +typedef struct +{ + struct OBJREFCNT *pPmaVasRefcnt; + struct OBJREFCNT *pHwpmIbBindRefcnt; + struct OBJVASPACE *pPmaVAS; + NvBool bPmaVasRequested; + MEMORY_DESCRIPTOR *pInstBlkMemDesc; + NvBool hwpmIbBindState; +} HWPM_STREAMOUT_STATE; + +typedef struct +{ + MEMORY_DESCRIPTOR *pRecordBufDesc; + MEMORY_DESCRIPTOR *pNumBytesBufDesc; + RsResourceRef *pMemoryPmaBufferRef; + RsResourceRef *pMemoryPmaAvailBytesRef; + NvU64 vaddr; + NvU64 size; + NvU64 vaddrRecordBuf; + NvU64 vaddrNumBytesBuf; + NvP64 pNumBytesCpuAddr; + NvP64 pNumBytesCpuAddrPriv; + NvU32 pmaChannelIdx; + NvU32 bValid; + NvU32 flags; + NvBool bMemBytesBufferAccessAllowed; +} HWPM_PMA_STREAM; + +#define MAX_PMA_CREDIT_POOL 2 + +#endif // KERN_HWPM_COMMON_DEFS_H + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_KERN_HWPM_COMMON_DEFS_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_hwpm_nvoc.c b/src/nvidia/generated/g_kern_hwpm_nvoc.c new file mode 100644 index 0000000000..652d57090e --- /dev/null +++ b/src/nvidia/generated/g_kern_hwpm_nvoc.c @@ -0,0 +1,311 @@ +#define NVOC_KERN_HWPM_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_kern_hwpm_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xc8c00f = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHwpm; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJENGSTATE; + +void __nvoc_init_KernelHwpm(KernelHwpm*, RmHalspecOwner* ); +void __nvoc_init_funcTable_KernelHwpm(KernelHwpm*, RmHalspecOwner* ); +NV_STATUS __nvoc_ctor_KernelHwpm(KernelHwpm*, RmHalspecOwner* ); +void __nvoc_init_dataField_KernelHwpm(KernelHwpm*, RmHalspecOwner* ); +void __nvoc_dtor_KernelHwpm(KernelHwpm*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHwpm; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHwpm_KernelHwpm = { + /*pClassDef=*/ &__nvoc_class_def_KernelHwpm, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_KernelHwpm, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHwpm_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHwpm, __nvoc_base_OBJENGSTATE.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_KernelHwpm_OBJENGSTATE = { + /*pClassDef=*/ &__nvoc_class_def_OBJENGSTATE, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(KernelHwpm, __nvoc_base_OBJENGSTATE), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_KernelHwpm = { + /*numRelatives=*/ 3, + /*relatives=*/ { + &__nvoc_rtti_KernelHwpm_KernelHwpm, + &__nvoc_rtti_KernelHwpm_OBJENGSTATE, + &__nvoc_rtti_KernelHwpm_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHwpm = +{ + /*classInfo=*/ { + /*size=*/ sizeof(KernelHwpm), + /*classId=*/ classId(KernelHwpm), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "KernelHwpm", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_KernelHwpm, + /*pCastInfo=*/ &__nvoc_castinfo_KernelHwpm, + /*pExportInfo=*/ &__nvoc_export_info_KernelHwpm +}; + +static NV_STATUS __nvoc_thunk_KernelHwpm_engstateStateInitUnlocked(OBJGPU *pGpu, struct OBJENGSTATE *pKernelHwpm) { + return khwpmStateInitUnlocked(pGpu, (struct KernelHwpm *)(((unsigned char *)pKernelHwpm) - __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset)); +} + +static void __nvoc_thunk_KernelHwpm_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelHwpm) { + khwpmStateDestroy(pGpu, (struct KernelHwpm *)(((unsigned char *)pKernelHwpm) - __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStateLoad(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStateUnload(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStateInitLocked(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStatePreLoad(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStatePostUnload(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return engstateStatePostUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStatePreUnload(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return engstateStatePreUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset), arg0); +} + +static void __nvoc_thunk_OBJENGSTATE_khwpmInitMissing(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + engstateInitMissing(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStatePreInitLocked(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + return engstateStatePreInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStatePreInitUnlocked(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset)); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmStatePostLoad(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset), arg0); +} + +static NV_STATUS __nvoc_thunk_OBJENGSTATE_khwpmConstructEngine(POBJGPU pGpu, struct KernelHwpm *pEngstate, ENGDESCRIPTOR arg0) { + return engstateConstructEngine(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset), arg0); +} + +static NvBool __nvoc_thunk_OBJENGSTATE_khwpmIsPresent(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelHwpm_OBJENGSTATE.offset)); +} + +const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHwpm = +{ + /*numEntries=*/ 0, + /*pExportEntries=*/ 0 +}; + +void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_dtor_KernelHwpm(KernelHwpm *pThis) { + __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_KernelHwpm(KernelHwpm *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + + // NVOC Property Hal field -- PDB_PROP_KHWPM_MULTIPLE_PMA_SUPPORTED + // default + { + pThis->setProperty(pThis, PDB_PROP_KHWPM_MULTIPLE_PMA_SUPPORTED, ((NvBool)(0 != 0))); + } +} + +NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); +NV_STATUS __nvoc_ctor_KernelHwpm(KernelHwpm *pThis, RmHalspecOwner *pRmhalspecowner) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + if (status != NV_OK) goto __nvoc_ctor_KernelHwpm_fail_OBJENGSTATE; + __nvoc_init_dataField_KernelHwpm(pThis, pRmhalspecowner); + goto __nvoc_ctor_KernelHwpm_exit; // Success + +__nvoc_ctor_KernelHwpm_fail_OBJENGSTATE: +__nvoc_ctor_KernelHwpm_exit: + + return status; +} + +static void __nvoc_init_funcTable_KernelHwpm_1(KernelHwpm *pThis, RmHalspecOwner *pRmhalspecowner) { + ChipHal *chipHal = &pRmhalspecowner->chipHal; + const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx; + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(chipHal); + PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + + pThis->__khwpmStateInitUnlocked__ = &khwpmStateInitUnlocked_IMPL; + + pThis->__khwpmStateDestroy__ = &khwpmStateDestroy_IMPL; + + // Hal function -- khwpmGetCblockInfo + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__khwpmGetCblockInfo__ = &khwpmGetCblockInfo_GH100; + } + else + { + pThis->__khwpmGetCblockInfo__ = &khwpmGetCblockInfo_GM107; + } + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitUnlocked__ = &__nvoc_thunk_KernelHwpm_engstateStateInitUnlocked; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelHwpm_engstateStateDestroy; + + pThis->__khwpmStateLoad__ = &__nvoc_thunk_OBJENGSTATE_khwpmStateLoad; + + pThis->__khwpmStateUnload__ = &__nvoc_thunk_OBJENGSTATE_khwpmStateUnload; + + pThis->__khwpmStateInitLocked__ = &__nvoc_thunk_OBJENGSTATE_khwpmStateInitLocked; + + pThis->__khwpmStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_khwpmStatePreLoad; + + pThis->__khwpmStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_khwpmStatePostUnload; + + pThis->__khwpmStatePreUnload__ = &__nvoc_thunk_OBJENGSTATE_khwpmStatePreUnload; + + pThis->__khwpmInitMissing__ = &__nvoc_thunk_OBJENGSTATE_khwpmInitMissing; + + pThis->__khwpmStatePreInitLocked__ = &__nvoc_thunk_OBJENGSTATE_khwpmStatePreInitLocked; + + pThis->__khwpmStatePreInitUnlocked__ = &__nvoc_thunk_OBJENGSTATE_khwpmStatePreInitUnlocked; + + pThis->__khwpmStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_khwpmStatePostLoad; + + pThis->__khwpmConstructEngine__ = &__nvoc_thunk_OBJENGSTATE_khwpmConstructEngine; + + pThis->__khwpmIsPresent__ = &__nvoc_thunk_OBJENGSTATE_khwpmIsPresent; +} + +void __nvoc_init_funcTable_KernelHwpm(KernelHwpm *pThis, RmHalspecOwner *pRmhalspecowner) { + __nvoc_init_funcTable_KernelHwpm_1(pThis, pRmhalspecowner); +} + +void __nvoc_init_OBJENGSTATE(OBJENGSTATE*); +void __nvoc_init_KernelHwpm(KernelHwpm *pThis, RmHalspecOwner *pRmhalspecowner) { + pThis->__nvoc_pbase_KernelHwpm = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object; + pThis->__nvoc_pbase_OBJENGSTATE = &pThis->__nvoc_base_OBJENGSTATE; + __nvoc_init_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); + __nvoc_init_funcTable_KernelHwpm(pThis, pRmhalspecowner); +} + +NV_STATUS __nvoc_objCreate_KernelHwpm(KernelHwpm **ppThis, Dynamic *pParent, NvU32 createFlags) +{ + NV_STATUS status; + Object *pParentObj = NULL; + KernelHwpm *pThis; + RmHalspecOwner *pRmhalspecowner; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHwpm), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(KernelHwpm)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHwpm); + + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.pParent = NULL; + } + + if ((pRmhalspecowner = dynamicCast(pParent, RmHalspecOwner)) == NULL) + pRmhalspecowner = objFindAncestorOfType(RmHalspecOwner, pParent); + NV_ASSERT_OR_RETURN(pRmhalspecowner != NULL, NV_ERR_INVALID_ARGUMENT); + + __nvoc_init_KernelHwpm(pThis, pRmhalspecowner); + status = __nvoc_ctor_KernelHwpm(pThis, pRmhalspecowner); + if (status != NV_OK) goto __nvoc_objCreate_KernelHwpm_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_KernelHwpm_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(KernelHwpm)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_KernelHwpm(KernelHwpm **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + + status = __nvoc_objCreate_KernelHwpm(ppThis, pParent, createFlags); + + return status; +} + diff --git a/src/nvidia/generated/g_kern_hwpm_nvoc.h b/src/nvidia/generated/g_kern_hwpm_nvoc.h new file mode 100644 index 0000000000..ec336c54e5 --- /dev/null +++ b/src/nvidia/generated/g_kern_hwpm_nvoc.h @@ -0,0 +1,293 @@ +#ifndef _G_KERN_HWPM_NVOC_H_ +#define _G_KERN_HWPM_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_kern_hwpm_nvoc.h" + +#ifndef KERNEL_HWPM_H +#define KERNEL_HWPM_H + +/****************************************************************************** + * + * Kernel Hwpm module header + * This file contains functions managing HWPM on CPU RM + * + ******************************************************************************/ + +#include "gpu/gpu.h" +#include "gpu/eng_state.h" +#include "gpu/hwpm/kern_hwpm_power.h" +#include "gpu/hwpm/kern_hwpm_common_defs.h" + +#define INVALID_PMA_CHANNEL_IDX NV_U32_MAX + +// default values for the perf vaspace base and size +#define PERF_VASPACE_BASE (4*1024*1024*1024ULL) +#define PERF_VASPACE_SIZE (1024*1024*1024*1024ULL) + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_KERN_HWPM_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif + +struct KernelHwpm { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelHwpm *__nvoc_pbase_KernelHwpm; + NV_STATUS (*__khwpmStateInitUnlocked__)(OBJGPU *, struct KernelHwpm *); + void (*__khwpmStateDestroy__)(OBJGPU *, struct KernelHwpm *); + void (*__khwpmGetCblockInfo__)(OBJGPU *, struct KernelHwpm *, NvU32 *, NvU32 *); + NV_STATUS (*__khwpmStateLoad__)(POBJGPU, struct KernelHwpm *, NvU32); + NV_STATUS (*__khwpmStateUnload__)(POBJGPU, struct KernelHwpm *, NvU32); + NV_STATUS (*__khwpmStateInitLocked__)(POBJGPU, struct KernelHwpm *); + NV_STATUS (*__khwpmStatePreLoad__)(POBJGPU, struct KernelHwpm *, NvU32); + NV_STATUS (*__khwpmStatePostUnload__)(POBJGPU, struct KernelHwpm *, NvU32); + NV_STATUS (*__khwpmStatePreUnload__)(POBJGPU, struct KernelHwpm *, NvU32); + void (*__khwpmInitMissing__)(POBJGPU, struct KernelHwpm *); + NV_STATUS (*__khwpmStatePreInitLocked__)(POBJGPU, struct KernelHwpm *); + NV_STATUS (*__khwpmStatePreInitUnlocked__)(POBJGPU, struct KernelHwpm *); + NV_STATUS (*__khwpmStatePostLoad__)(POBJGPU, struct KernelHwpm *, NvU32); + NV_STATUS (*__khwpmConstructEngine__)(POBJGPU, struct KernelHwpm *, ENGDESCRIPTOR); + NvBool (*__khwpmIsPresent__)(POBJGPU, struct KernelHwpm *); + NvBool PDB_PROP_KHWPM_MULTIPLE_PMA_SUPPORTED; + NvU32 numPma; + NvU32 maxCblocks; + NvU32 maxCblocksPerPma; + NvU32 maxPmaChannels; + NvU32 maxChannelPerCblock; + HWPM_STREAMOUT_STATE *streamoutState; + NvU64 vaSpaceBase; + NvU64 vaSpaceSize; +}; + +#ifndef __NVOC_CLASS_KernelHwpm_TYPEDEF__ +#define __NVOC_CLASS_KernelHwpm_TYPEDEF__ +typedef struct KernelHwpm KernelHwpm; +#endif /* __NVOC_CLASS_KernelHwpm_TYPEDEF__ */ + +#ifndef __nvoc_class_id_KernelHwpm +#define __nvoc_class_id_KernelHwpm 0xc8c00f +#endif /* __nvoc_class_id_KernelHwpm */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelHwpm; + +#define __staticCast_KernelHwpm(pThis) \ + ((pThis)->__nvoc_pbase_KernelHwpm) + +#ifdef __nvoc_kern_hwpm_h_disabled +#define __dynamicCast_KernelHwpm(pThis) ((KernelHwpm*)NULL) +#else //__nvoc_kern_hwpm_h_disabled +#define __dynamicCast_KernelHwpm(pThis) \ + ((KernelHwpm*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(KernelHwpm))) +#endif //__nvoc_kern_hwpm_h_disabled + +#define PDB_PROP_KHWPM_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. +#define PDB_PROP_KHWPM_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING +#define PDB_PROP_KHWPM_MULTIPLE_PMA_SUPPORTED_BASE_CAST +#define PDB_PROP_KHWPM_MULTIPLE_PMA_SUPPORTED_BASE_NAME PDB_PROP_KHWPM_MULTIPLE_PMA_SUPPORTED + +NV_STATUS __nvoc_objCreateDynamic_KernelHwpm(KernelHwpm**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_KernelHwpm(KernelHwpm**, Dynamic*, NvU32); +#define __objCreate_KernelHwpm(ppNewObj, pParent, createFlags) \ + __nvoc_objCreate_KernelHwpm((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) + +#define khwpmStateInitUnlocked(pGpu, pKernelHwpm) khwpmStateInitUnlocked_DISPATCH(pGpu, pKernelHwpm) +#define khwpmStateDestroy(pGpu, pKernelHwpm) khwpmStateDestroy_DISPATCH(pGpu, pKernelHwpm) +#define khwpmGetCblockInfo(pGpu, pKernelHwpm, arg0, arg1) khwpmGetCblockInfo_DISPATCH(pGpu, pKernelHwpm, arg0, arg1) +#define khwpmGetCblockInfo_HAL(pGpu, pKernelHwpm, arg0, arg1) khwpmGetCblockInfo_DISPATCH(pGpu, pKernelHwpm, arg0, arg1) +#define khwpmStateLoad(pGpu, pEngstate, arg0) khwpmStateLoad_DISPATCH(pGpu, pEngstate, arg0) +#define khwpmStateUnload(pGpu, pEngstate, arg0) khwpmStateUnload_DISPATCH(pGpu, pEngstate, arg0) +#define khwpmStateInitLocked(pGpu, pEngstate) khwpmStateInitLocked_DISPATCH(pGpu, pEngstate) +#define khwpmStatePreLoad(pGpu, pEngstate, arg0) khwpmStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) +#define khwpmStatePostUnload(pGpu, pEngstate, arg0) khwpmStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) +#define khwpmStatePreUnload(pGpu, pEngstate, arg0) khwpmStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) +#define khwpmInitMissing(pGpu, pEngstate) khwpmInitMissing_DISPATCH(pGpu, pEngstate) +#define khwpmStatePreInitLocked(pGpu, pEngstate) khwpmStatePreInitLocked_DISPATCH(pGpu, pEngstate) +#define khwpmStatePreInitUnlocked(pGpu, pEngstate) khwpmStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) +#define khwpmStatePostLoad(pGpu, pEngstate, arg0) khwpmStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) +#define khwpmConstructEngine(pGpu, pEngstate, arg0) khwpmConstructEngine_DISPATCH(pGpu, pEngstate, arg0) +#define khwpmIsPresent(pGpu, pEngstate) khwpmIsPresent_DISPATCH(pGpu, pEngstate) +static inline NV_STATUS khwpmPmaStreamSriovSetGfid_56cd7a(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0, NvU32 arg1) { + return NV_OK; +} + +NV_STATUS khwpmPmaStreamSriovSetGfid_GA100(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0, NvU32 arg1); + +NV_STATUS khwpmPmaStreamSriovSetGfid_GH100(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0, NvU32 arg1); + +static inline NV_STATUS khwpmPmaStreamSriovSetGfid_92bfc3(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0, NvU32 arg1) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + + +#ifdef __nvoc_kern_hwpm_h_disabled +static inline NV_STATUS khwpmPmaStreamSriovSetGfid(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0, NvU32 arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelHwpm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_hwpm_h_disabled +#define khwpmPmaStreamSriovSetGfid(pGpu, pKernelHwpm, arg0, arg1) khwpmPmaStreamSriovSetGfid_56cd7a(pGpu, pKernelHwpm, arg0, arg1) +#endif //__nvoc_kern_hwpm_h_disabled + +#define khwpmPmaStreamSriovSetGfid_HAL(pGpu, pKernelHwpm, arg0, arg1) khwpmPmaStreamSriovSetGfid(pGpu, pKernelHwpm, arg0, arg1) + +NV_STATUS khwpmStateInitUnlocked_IMPL(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm); + +static inline NV_STATUS khwpmStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm) { + return pKernelHwpm->__khwpmStateInitUnlocked__(pGpu, pKernelHwpm); +} + +void khwpmStateDestroy_IMPL(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm); + +static inline void khwpmStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm) { + pKernelHwpm->__khwpmStateDestroy__(pGpu, pKernelHwpm); +} + +void khwpmGetCblockInfo_GM107(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 *arg0, NvU32 *arg1); + +void khwpmGetCblockInfo_GH100(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 *arg0, NvU32 *arg1); + +static inline void khwpmGetCblockInfo_DISPATCH(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 *arg0, NvU32 *arg1) { + pKernelHwpm->__khwpmGetCblockInfo__(pGpu, pKernelHwpm, arg0, arg1); +} + +static inline NV_STATUS khwpmStateLoad_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return pEngstate->__khwpmStateLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS khwpmStateUnload_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return pEngstate->__khwpmStateUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS khwpmStateInitLocked_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + return pEngstate->__khwpmStateInitLocked__(pGpu, pEngstate); +} + +static inline NV_STATUS khwpmStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return pEngstate->__khwpmStatePreLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS khwpmStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return pEngstate->__khwpmStatePostUnload__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS khwpmStatePreUnload_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return pEngstate->__khwpmStatePreUnload__(pGpu, pEngstate, arg0); +} + +static inline void khwpmInitMissing_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + pEngstate->__khwpmInitMissing__(pGpu, pEngstate); +} + +static inline NV_STATUS khwpmStatePreInitLocked_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + return pEngstate->__khwpmStatePreInitLocked__(pGpu, pEngstate); +} + +static inline NV_STATUS khwpmStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + return pEngstate->__khwpmStatePreInitUnlocked__(pGpu, pEngstate); +} + +static inline NV_STATUS khwpmStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate, NvU32 arg0) { + return pEngstate->__khwpmStatePostLoad__(pGpu, pEngstate, arg0); +} + +static inline NV_STATUS khwpmConstructEngine_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate, ENGDESCRIPTOR arg0) { + return pEngstate->__khwpmConstructEngine__(pGpu, pEngstate, arg0); +} + +static inline NvBool khwpmIsPresent_DISPATCH(POBJGPU pGpu, struct KernelHwpm *pEngstate) { + return pEngstate->__khwpmIsPresent__(pGpu, pEngstate); +} + +NV_STATUS khwpmStreamoutAllocPmaStream_IMPL(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU64 arg0, MEMORY_DESCRIPTOR *arg1, MEMORY_DESCRIPTOR *arg2, NvU32 arg3, HWPM_PMA_STREAM *arg4); + +#ifdef __nvoc_kern_hwpm_h_disabled +static inline NV_STATUS khwpmStreamoutAllocPmaStream(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU64 arg0, MEMORY_DESCRIPTOR *arg1, MEMORY_DESCRIPTOR *arg2, NvU32 arg3, HWPM_PMA_STREAM *arg4) { + NV_ASSERT_FAILED_PRECOMP("KernelHwpm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_hwpm_h_disabled +#define khwpmStreamoutAllocPmaStream(pGpu, pKernelHwpm, arg0, arg1, arg2, arg3, arg4) khwpmStreamoutAllocPmaStream_IMPL(pGpu, pKernelHwpm, arg0, arg1, arg2, arg3, arg4) +#endif //__nvoc_kern_hwpm_h_disabled + +NV_STATUS khwpmStreamoutFreePmaStream_IMPL(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU64 arg0, HWPM_PMA_STREAM *arg1, NvU32 arg2); + +#ifdef __nvoc_kern_hwpm_h_disabled +static inline NV_STATUS khwpmStreamoutFreePmaStream(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU64 arg0, HWPM_PMA_STREAM *arg1, NvU32 arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelHwpm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_hwpm_h_disabled +#define khwpmStreamoutFreePmaStream(pGpu, pKernelHwpm, arg0, arg1, arg2) khwpmStreamoutFreePmaStream_IMPL(pGpu, pKernelHwpm, arg0, arg1, arg2) +#endif //__nvoc_kern_hwpm_h_disabled + +NV_STATUS khwpmStreamoutCreatePmaVaSpace_IMPL(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0); + +#ifdef __nvoc_kern_hwpm_h_disabled +static inline NV_STATUS khwpmStreamoutCreatePmaVaSpace(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelHwpm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_hwpm_h_disabled +#define khwpmStreamoutCreatePmaVaSpace(pGpu, pKernelHwpm, arg0) khwpmStreamoutCreatePmaVaSpace_IMPL(pGpu, pKernelHwpm, arg0) +#endif //__nvoc_kern_hwpm_h_disabled + +NV_STATUS khwpmStreamoutFreePmaVaSpace_IMPL(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0); + +#ifdef __nvoc_kern_hwpm_h_disabled +static inline NV_STATUS khwpmStreamoutFreePmaVaSpace(OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelHwpm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_hwpm_h_disabled +#define khwpmStreamoutFreePmaVaSpace(pGpu, pKernelHwpm, arg0) khwpmStreamoutFreePmaVaSpace_IMPL(pGpu, pKernelHwpm, arg0) +#endif //__nvoc_kern_hwpm_h_disabled + +#undef PRIVATE_FIELD + + +NV_STATUS khwpmGetRequestCgStatusMask(NvU32 *pCgStatusMask, HWPM_POWER_REQUEST_FEATURES_PARAMS *pParams); + +#endif // KERNEL_HWPM_H + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_KERN_HWPM_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_hwpm_power_nvoc.c b/src/nvidia/generated/g_kern_hwpm_power_nvoc.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/nvidia/generated/g_kern_hwpm_power_nvoc.h b/src/nvidia/generated/g_kern_hwpm_power_nvoc.h new file mode 100644 index 0000000000..ad4ac51f07 --- /dev/null +++ b/src/nvidia/generated/g_kern_hwpm_power_nvoc.h @@ -0,0 +1,70 @@ +#ifndef _G_KERN_HWPM_POWER_NVOC_H_ +#define _G_KERN_HWPM_POWER_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef KERN_HWPM_POWER_H +#define KERN_HWPM_POWER_H + +#include "nvtypes.h" + +typedef struct HWPM_POWER_REQUEST_FEATURES_PARAMS +{ + NvU32 globalStatus; + NvU32 controlMask; + NvU32 statusMask; +} HWPM_POWER_REQUEST_FEATURES_PARAMS; + +/* Valid fields for the controlMask and statusMask parameters */ +#define HWPM_POWER_FEATURE_MASK_ELCG 1:0 +#define HWPM_POWER_FEATURE_MASK_BLCG 3:2 +#define HWPM_POWER_FEATURE_MASK_SLCG 5:4 + +/* + * The following are temporary fields for the controlMask and statusMask + * parameters. They are required to reference count their respective features + * until the existing RM controls can be safely updated, and the definitions + * for these features will be removed soon after that. + */ +#define HWPM_POWER_FEATURE_MASK_ELPG 7:6 +#define HWPM_POWER_FEATURE_MASK_IDLE_SLOWDOWN 9:8 + +/* Possible values for fields in the statusMask parameter */ +#define HWPM_POWER_FEATURE_REQUEST_FULFILLED (0x00000000) +#define HWPM_POWER_FEATURE_REQUEST_REJECTED (0x00000001) +#define HWPM_POWER_FEATURE_REQUEST_NOT_SUPPORTED (0x00000002) +#define HWPM_POWER_FEATURE_REQUEST_FAILED (0x00000003) + +#endif // KERN_HWPM_POWER_H + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_KERN_HWPM_POWER_NVOC_H_ diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.c b/src/nvidia/generated/g_kern_mem_sys_nvoc.c index 40502648fd..a8ca0b5d57 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.c +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.c @@ -82,20 +82,20 @@ static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStatePostLoad(OBJGPU *p return kmemsysStatePostLoad(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStatePreUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem, NvU32 flags) { - return kmemsysStatePreUnload(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); +static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStateLoad(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem, NvU32 flags) { + return kmemsysStateLoad(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelMemorySystem_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem) { - kmemsysStateDestroy(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); +static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStatePreUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem, NvU32 flags) { + return kmemsysStatePreUnload(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStateLoad(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), arg0); +static NV_STATUS __nvoc_thunk_KernelMemorySystem_engstateStateUnload(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem, NvU32 flags) { + return kmemsysStateUnload(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStateUnload(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset), arg0); +static void __nvoc_thunk_KernelMemorySystem_engstateStateDestroy(OBJGPU *pGpu, struct OBJENGSTATE *pKernelMemorySystem) { + kmemsysStateDestroy(pGpu, (struct KernelMemorySystem *)(((unsigned char *)pKernelMemorySystem) - __nvoc_rtti_KernelMemorySystem_OBJENGSTATE.offset)); } static NV_STATUS __nvoc_thunk_OBJENGSTATE_kmemsysStatePostUnload(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { @@ -168,6 +168,12 @@ void __nvoc_init_dataField_KernelMemorySystem(KernelMemorySystem *pThis, RmHalsp pThis->bL2CleanFbPull = ((NvBool)(0 == 0)); } + // Hal field -- l2WriteMode + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->l2WriteMode = FB_CACHE_WRITE_MODE_WRITETHROUGH; + } + // Hal field -- bPreserveComptagBackingStoreOnSuspend pThis->bPreserveComptagBackingStoreOnSuspend = ((NvBool)(0 != 0)); @@ -181,6 +187,19 @@ void __nvoc_init_dataField_KernelMemorySystem(KernelMemorySystem *pThis, RmHalsp { pThis->bBug3656943WAR = ((NvBool)(0 != 0)); } + + // Hal field -- overrideToGMK + pThis->overrideToGMK = 0; + + // Hal field -- bDisablePlcForCertainOffsetsBug3046774 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->bDisablePlcForCertainOffsetsBug3046774 = ((NvBool)(0 != 0)); + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->bDisablePlcForCertainOffsetsBug3046774 = ((NvBool)(0 != 0)); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -217,8 +236,30 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysStatePostLoad__ = &kmemsysStatePostLoad_IMPL; + // Hal function -- kmemsysStateLoad + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmemsysStateLoad__ = &kmemsysStateLoad_VF; + } + // default + else + { + pThis->__kmemsysStateLoad__ = &kmemsysStateLoad_ac1694; + } + pThis->__kmemsysStatePreUnload__ = &kmemsysStatePreUnload_IMPL; + // Hal function -- kmemsysStateUnload + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmemsysStateUnload__ = &kmemsysStateUnload_VF; + } + // default + else + { + pThis->__kmemsysStateUnload__ = &kmemsysStateUnload_ac1694; + } + pThis->__kmemsysStateDestroy__ = &kmemsysStateDestroy_IMPL; // Hal function -- kmemsysGetFbNumaInfo @@ -241,6 +282,16 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysReadUsableFbSize__ = &kmemsysReadUsableFbSize_GA102; } + // Hal function -- kmemsysGetUsableFbSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmemsysGetUsableFbSize__ = &kmemsysGetUsableFbSize_5baef9; + } + else + { + pThis->__kmemsysGetUsableFbSize__ = &kmemsysGetUsableFbSize_KERNEL; + } + // Hal function -- kmemsysCacheOp if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -302,64 +353,109 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis } // Hal function -- kmemsysInitFlushSysmemBuffer - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GM107; + pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_56cd7a; } else { - pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GA100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GM107; + } + else + { + pThis->__kmemsysInitFlushSysmemBuffer__ = &kmemsysInitFlushSysmemBuffer_GA100; + } } // Hal function -- kmemsysProgramSysmemFlushBuffer - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_b3696a; + } + else { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GH100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GM107; + } + else + { + pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GA100; + } } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + + // Hal function -- kmemsysGetFlushSysmemBufferAddrShift + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GM107; + pThis->__kmemsysGetFlushSysmemBufferAddrShift__ = &kmemsysGetFlushSysmemBufferAddrShift_4a4dee; } else { - pThis->__kmemsysProgramSysmemFlushBuffer__ = &kmemsysProgramSysmemFlushBuffer_GA100; + pThis->__kmemsysGetFlushSysmemBufferAddrShift__ = &kmemsysGetFlushSysmemBufferAddrShift_GM107; } // Hal function -- kmemsysIsPagePLCable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA102; + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_cbe027; } - // default else { - pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_510167; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_GA102; + } + // default + else + { + pThis->__kmemsysIsPagePLCable__ = &kmemsysIsPagePLCable_510167; + } } // Hal function -- kmemsysReadMIGMemoryCfg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_GA100; + pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_46f6a7; } - // default else { - pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_46f6a7; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_GA100; + } + // default + else + { + pThis->__kmemsysReadMIGMemoryCfg__ = &kmemsysReadMIGMemoryCfg_46f6a7; + } } // Hal function -- kmemsysInitMIGMemoryPartitionTable - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_GA100; + pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_56cd7a; } - // default else { - pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_56cd7a; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_GA100; + } + // default + else + { + pThis->__kmemsysInitMIGMemoryPartitionTable__ = &kmemsysInitMIGMemoryPartitionTable_56cd7a; + } } // Hal function -- kmemsysSwizzIdToVmmuSegmentsRange @@ -405,6 +501,17 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysNumaRemoveAllMemory__ = &kmemsysNumaRemoveAllMemory_b3696a; } + // Hal function -- kmemsysPopulateMIGGPUInstanceMemConfig + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmemsysPopulateMIGGPUInstanceMemConfig__ = &kmemsysPopulateMIGGPUInstanceMemConfig_56cd7a; + } + else + { + // default + pThis->__kmemsysPopulateMIGGPUInstanceMemConfig__ = &kmemsysPopulateMIGGPUInstanceMemConfig_KERNEL; + } + // Hal function -- kmemsysSetupAllAtsPeers if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -436,26 +543,91 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__kmemsysAssertFbAckTimeoutPending__ = &kmemsysAssertFbAckTimeoutPending_491d52; } - // Hal function -- kmemsysCheckEccCounts + // Hal function -- kmemsysGetMaxFbpas + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000020UL) )) /* ChipHal: TU102 */ + { + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_GA100; + } + // default + else + { + pThis->__kmemsysGetMaxFbpas__ = &kmemsysGetMaxFbpas_4a4dee; + } + + // Hal function -- kmemsysGetEccDedCountSize if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysCheckEccCounts__ = &kmemsysCheckEccCounts_GH100; + pThis->__kmemsysGetEccDedCountSize__ = &kmemsysGetEccDedCountSize_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000420UL) )) /* ChipHal: TU102 | GA100 */ + { + pThis->__kmemsysGetEccDedCountSize__ = &kmemsysGetEccDedCountSize_TU102; } // default else { - pThis->__kmemsysCheckEccCounts__ = &kmemsysCheckEccCounts_b3696a; + pThis->__kmemsysGetEccDedCountSize__ = &kmemsysGetEccDedCountSize_4a4dee; } - // Hal function -- kmemsysClearEccCounts + // Hal function -- kmemsysGetEccDedCountRegAddr if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { - pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_GH100; + pThis->__kmemsysGetEccDedCountRegAddr__ = &kmemsysGetEccDedCountRegAddr_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000420UL) )) /* ChipHal: TU102 | GA100 */ + { + pThis->__kmemsysGetEccDedCountRegAddr__ = &kmemsysGetEccDedCountRegAddr_TU102; + } + // default + else + { + pThis->__kmemsysGetEccDedCountRegAddr__ = &kmemsysGetEccDedCountRegAddr_4a4dee; + } + + // Hal function -- kmemsysGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kmemsysGetEccCounts__ = &kmemsysGetEccCounts_TU102; } // default else { - pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_56cd7a; + pThis->__kmemsysGetEccCounts__ = &kmemsysGetEccCounts_b3696a; + } + + // Hal function -- kmemsysClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000420UL) )) /* ChipHal: TU102 | GA100 | GH100 */ + { + pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_TU102; + } + // default + else + { + pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_b3696a; + } + + // Hal function -- kmemsysGetMaximumBlacklistPages + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kmemsysGetMaximumBlacklistPages__ = &kmemsysGetMaximumBlacklistPages_GM107; + } + else + { + pThis->__kmemsysGetMaximumBlacklistPages__ = &kmemsysGetMaximumBlacklistPages_GA100; + } + + // Hal function -- kmemsysGetFbInfos + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmemsysGetFbInfos__ = &kmemsysGetFbInfos_VF; + } + else + { + pThis->__kmemsysGetFbInfos__ = &kmemsysGetFbInfos_ac1694; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMemorySystem_engstateConstructEngine; @@ -466,13 +638,13 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelMemorySystem_engstateStatePostLoad; - pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelMemorySystem_engstateStatePreUnload; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelMemorySystem_engstateStateLoad; - pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelMemorySystem_engstateStateDestroy; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelMemorySystem_engstateStatePreUnload; - pThis->__kmemsysStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStateLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelMemorySystem_engstateStateUnload; - pThis->__kmemsysStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStateUnload; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelMemorySystem_engstateStateDestroy; pThis->__kmemsysStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kmemsysStatePostUnload; @@ -500,23 +672,31 @@ void __nvoc_init_KernelMemorySystem(KernelMemorySystem *pThis, RmHalspecOwner *p __nvoc_init_funcTable_KernelMemorySystem(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelMemorySystem *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMemorySystem), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelMemorySystem)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMemorySystem); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -534,16 +714,25 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem **ppThis, Dynam status = __nvoc_ctor_KernelMemorySystem(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelMemorySystem_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelMemorySystem_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelMemorySystem)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kern_mem_sys_nvoc.h b/src/nvidia/generated/g_kern_mem_sys_nvoc.h index 1ee2484bce..36f6bb0431 100644 --- a/src/nvidia/generated/g_kern_mem_sys_nvoc.h +++ b/src/nvidia/generated/g_kern_mem_sys_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -40,7 +40,9 @@ extern "C" { #include "containers/map.h" #include "gpu/mem_mgr/heap_base.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "ctrl/ctrl2080/ctrl2080fb.h" #include "ctrl/ctrl2080/ctrl2080internal.h" +#include "ctrl/ctrl2080/ctrl2080fb.h" // // FB Cache (opcode, mem target) defines used by kmemsysCacheOp hal API // @@ -186,11 +188,16 @@ typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS MEMORY_SYSTEM_STATI * tables/allocations should live in MemoryManager. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERN_MEM_SYS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelMemorySystem { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -201,10 +208,13 @@ struct KernelMemorySystem { NV_STATUS (*__kmemsysStateInitLocked__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysStatePreLoad__)(OBJGPU *, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStatePostLoad__)(OBJGPU *, struct KernelMemorySystem *, NvU32); + NV_STATUS (*__kmemsysStateLoad__)(OBJGPU *, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStatePreUnload__)(OBJGPU *, struct KernelMemorySystem *, NvU32); + NV_STATUS (*__kmemsysStateUnload__)(OBJGPU *, struct KernelMemorySystem *, NvU32); void (*__kmemsysStateDestroy__)(OBJGPU *, struct KernelMemorySystem *); - NV_STATUS (*__kmemsysGetFbNumaInfo__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *, NvS32 *); + NV_STATUS (*__kmemsysGetFbNumaInfo__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *, NvU64 *, NvS32 *); NV_STATUS (*__kmemsysReadUsableFbSize__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *); + NV_STATUS (*__kmemsysGetUsableFbSize__)(OBJGPU *, struct KernelMemorySystem *, NvU64 *); NV_STATUS (*__kmemsysCacheOp__)(OBJGPU *, struct KernelMemorySystem *, PMEMORY_DESCRIPTOR, FB_CACHE_MEMTYPE, FB_CACHE_OP); NV_STATUS (*__kmemsysDoCacheOp__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32, NvU32, PRMTIMEOUT); NvU32 (*__kmemsysReadL2SysmemInvalidateReg__)(OBJGPU *, struct KernelMemorySystem *); @@ -213,6 +223,7 @@ struct KernelMemorySystem { void (*__kmemsysWriteL2PeermemInvalidateReg__)(OBJGPU *, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysInitFlushSysmemBuffer__)(OBJGPU *, struct KernelMemorySystem *); void (*__kmemsysProgramSysmemFlushBuffer__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetFlushSysmemBufferAddrShift__)(OBJGPU *, struct KernelMemorySystem *); NvBool (*__kmemsysIsPagePLCable__)(OBJGPU *, struct KernelMemorySystem *, NvU64, NvU64); NV_STATUS (*__kmemsysReadMIGMemoryCfg__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysInitMIGMemoryPartitionTable__)(OBJGPU *, struct KernelMemorySystem *); @@ -220,13 +231,17 @@ struct KernelMemorySystem { NV_STATUS (*__kmemsysNumaAddMemory__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU64, NvU64, NvS32 *); void (*__kmemsysNumaRemoveMemory__)(OBJGPU *, struct KernelMemorySystem *, NvU32); void (*__kmemsysNumaRemoveAllMemory__)(OBJGPU *, struct KernelMemorySystem *); + NV_STATUS (*__kmemsysPopulateMIGGPUInstanceMemConfig__)(OBJGPU *, struct KernelMemorySystem *); NV_STATUS (*__kmemsysSetupAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); void (*__kmemsysRemoveAllAtsPeers__)(OBJGPU *, struct KernelMemorySystem *); NvBool (*__kmemsysAssertFbAckTimeoutPending__)(OBJGPU *, struct KernelMemorySystem *); - void (*__kmemsysCheckEccCounts__)(OBJGPU *, struct KernelMemorySystem *); - NV_STATUS (*__kmemsysClearEccCounts__)(OBJGPU *, struct KernelMemorySystem *); - NV_STATUS (*__kmemsysStateLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32); - NV_STATUS (*__kmemsysStateUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); + NvU32 (*__kmemsysGetMaxFbpas__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetEccDedCountSize__)(OBJGPU *, struct KernelMemorySystem *); + NvU32 (*__kmemsysGetEccDedCountRegAddr__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32); + void (*__kmemsysGetEccCounts__)(OBJGPU *, struct KernelMemorySystem *, NvU32 *, NvU32 *); + void (*__kmemsysClearEccCounts__)(OBJGPU *, struct KernelMemorySystem *); + NvU16 (*__kmemsysGetMaximumBlacklistPages__)(OBJGPU *, struct KernelMemorySystem *); + NV_STATUS (*__kmemsysGetFbInfos__)(OBJGPU *, struct KernelMemorySystem *, struct RsClient *, Device *, NvHandle, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *, NvU64 *); NV_STATUS (*__kmemsysStatePostUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32); NV_STATUS (*__kmemsysStateInitUnlocked__)(POBJGPU, struct KernelMemorySystem *); void (*__kmemsysInitMissing__)(POBJGPU, struct KernelMemorySystem *); @@ -237,8 +252,11 @@ struct KernelMemorySystem { NvBool bGpuCacheEnable; NvBool bNumaNodesAdded; NvBool bL2CleanFbPull; + NvU32 l2WriteMode; NvBool bPreserveComptagBackingStoreOnSuspend; NvBool bBug3656943WAR; + NvU32 overrideToGMK; + NvBool bDisablePlcForCertainOffsetsBug3046774; const MEMORY_SYSTEM_STATIC_CONFIG *pStaticConfig; MEM_PARTITION_NUMA_INFO *memPartitionNumaInfo; MIG_MEM_BOUNDARY_CONFIG_TABLE memBoundaryCfgTable; @@ -246,10 +264,14 @@ struct KernelMemorySystem { NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS migMemoryPartitionTable; PMEMORY_DESCRIPTOR pSysmemFlushBufferMemDesc; NvU64 sysmemFlushBuffer; + NvU64 fbOverrideStartKb; NvU64 coherentCpuFbBase; NvU64 coherentCpuFbEnd; + NvU64 coherentRsvdFbBase; NvU64 numaOnlineBase; NvU64 numaOnlineSize; + NvU64 numaMigPartitionSize[15]; + NvBool bNumaMigPartitionSizeEnumerated; }; #ifndef __NVOC_CLASS_KernelMemorySystem_TYPEDEF__ @@ -286,12 +308,18 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysStateInitLocked(pGpu, pKernelMemorySystem) kmemsysStateInitLocked_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysStatePreLoad(pGpu, pKernelMemorySystem, flags) kmemsysStatePreLoad_DISPATCH(pGpu, pKernelMemorySystem, flags) #define kmemsysStatePostLoad(pGpu, pKernelMemorySystem, flags) kmemsysStatePostLoad_DISPATCH(pGpu, pKernelMemorySystem, flags) +#define kmemsysStateLoad(pGpu, pKernelMemorySystem, flags) kmemsysStateLoad_DISPATCH(pGpu, pKernelMemorySystem, flags) +#define kmemsysStateLoad_HAL(pGpu, pKernelMemorySystem, flags) kmemsysStateLoad_DISPATCH(pGpu, pKernelMemorySystem, flags) #define kmemsysStatePreUnload(pGpu, pKernelMemorySystem, flags) kmemsysStatePreUnload_DISPATCH(pGpu, pKernelMemorySystem, flags) +#define kmemsysStateUnload(pGpu, pKernelMemorySystem, flags) kmemsysStateUnload_DISPATCH(pGpu, pKernelMemorySystem, flags) +#define kmemsysStateUnload_HAL(pGpu, pKernelMemorySystem, flags) kmemsysStateUnload_DISPATCH(pGpu, pKernelMemorySystem, flags) #define kmemsysStateDestroy(pGpu, pKernelMemorySystem) kmemsysStateDestroy_DISPATCH(pGpu, pKernelMemorySystem) -#define kmemsysGetFbNumaInfo(pGpu, pKernelMemorySystem, physAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, numaNodeId) -#define kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, physAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, numaNodeId) +#define kmemsysGetFbNumaInfo(pGpu, pKernelMemorySystem, physAddr, rsvdPhysAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, rsvdPhysAddr, numaNodeId) +#define kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, physAddr, rsvdPhysAddr, numaNodeId) kmemsysGetFbNumaInfo_DISPATCH(pGpu, pKernelMemorySystem, physAddr, rsvdPhysAddr, numaNodeId) #define kmemsysReadUsableFbSize(pGpu, pKernelMemorySystem, pFbSize) kmemsysReadUsableFbSize_DISPATCH(pGpu, pKernelMemorySystem, pFbSize) #define kmemsysReadUsableFbSize_HAL(pGpu, pKernelMemorySystem, pFbSize) kmemsysReadUsableFbSize_DISPATCH(pGpu, pKernelMemorySystem, pFbSize) +#define kmemsysGetUsableFbSize(pGpu, pKernelMemorySystem, pFbSize) kmemsysGetUsableFbSize_DISPATCH(pGpu, pKernelMemorySystem, pFbSize) +#define kmemsysGetUsableFbSize_HAL(pGpu, pKernelMemorySystem, pFbSize) kmemsysGetUsableFbSize_DISPATCH(pGpu, pKernelMemorySystem, pFbSize) #define kmemsysCacheOp(pGpu, pKernelMemorySystem, arg0, arg1, operation) kmemsysCacheOp_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1, operation) #define kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, arg0, arg1, operation) kmemsysCacheOp_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1, operation) #define kmemsysDoCacheOp(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) kmemsysDoCacheOp_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1, arg2, arg3) @@ -308,6 +336,8 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysInitFlushSysmemBuffer_HAL(pGpu, pKernelMemorySystem) kmemsysInitFlushSysmemBuffer_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysProgramSysmemFlushBuffer(pGpu, pKernelMemorySystem) kmemsysProgramSysmemFlushBuffer_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysProgramSysmemFlushBuffer_HAL(pGpu, pKernelMemorySystem) kmemsysProgramSysmemFlushBuffer_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetFlushSysmemBufferAddrShift(pGpu, pKernelMemorySystem) kmemsysGetFlushSysmemBufferAddrShift_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem) kmemsysGetFlushSysmemBufferAddrShift_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysIsPagePLCable(pGpu, KernelMemorySystem, physAddr, pageSize) kmemsysIsPagePLCable_DISPATCH(pGpu, KernelMemorySystem, physAddr, pageSize) #define kmemsysIsPagePLCable_HAL(pGpu, KernelMemorySystem, physAddr, pageSize) kmemsysIsPagePLCable_DISPATCH(pGpu, KernelMemorySystem, physAddr, pageSize) #define kmemsysReadMIGMemoryCfg(pGpu, pKernelMemorySystem) kmemsysReadMIGMemoryCfg_DISPATCH(pGpu, pKernelMemorySystem) @@ -322,38 +352,34 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv #define kmemsysNumaRemoveMemory_HAL(pGpu, pKernelMemorySystem, swizzId) kmemsysNumaRemoveMemory_DISPATCH(pGpu, pKernelMemorySystem, swizzId) #define kmemsysNumaRemoveAllMemory(pGpu, pKernelMemorySystem) kmemsysNumaRemoveAllMemory_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysNumaRemoveAllMemory_HAL(pGpu, pKernelMemorySystem) kmemsysNumaRemoveAllMemory_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysPopulateMIGGPUInstanceMemConfig(pGpu, pKernelMemorySystem) kmemsysPopulateMIGGPUInstanceMemConfig_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem) kmemsysPopulateMIGGPUInstanceMemConfig_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysSetupAllAtsPeers(pGpu, pKernelMemorySystem) kmemsysSetupAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysSetupAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysSetupAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysRemoveAllAtsPeers(pGpu, pKernelMemorySystem) kmemsysRemoveAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysRemoveAllAtsPeers_HAL(pGpu, pKernelMemorySystem) kmemsysRemoveAllAtsPeers_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysAssertFbAckTimeoutPending(pGpu, pKernelMemorySystem) kmemsysAssertFbAckTimeoutPending_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysAssertFbAckTimeoutPending_HAL(pGpu, pKernelMemorySystem) kmemsysAssertFbAckTimeoutPending_DISPATCH(pGpu, pKernelMemorySystem) -#define kmemsysCheckEccCounts(pGpu, pKernelMemorySystem) kmemsysCheckEccCounts_DISPATCH(pGpu, pKernelMemorySystem) -#define kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem) kmemsysCheckEccCounts_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetMaxFbpas(pGpu, pKernelMemorySystem) kmemsysGetMaxFbpas_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetMaxFbpas_HAL(pGpu, pKernelMemorySystem) kmemsysGetMaxFbpas_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountSize(pGpu, pKernelMemorySystem) kmemsysGetEccDedCountSize_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountSize_HAL(pGpu, pKernelMemorySystem) kmemsysGetEccDedCountSize_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetEccDedCountRegAddr(pGpu, pKernelMemorySystem, fbpa, subp) kmemsysGetEccDedCountRegAddr_DISPATCH(pGpu, pKernelMemorySystem, fbpa, subp) +#define kmemsysGetEccDedCountRegAddr_HAL(pGpu, pKernelMemorySystem, fbpa, subp) kmemsysGetEccDedCountRegAddr_DISPATCH(pGpu, pKernelMemorySystem, fbpa, subp) +#define kmemsysGetEccCounts(pGpu, pKernelMemorySystem, arg0, arg1) kmemsysGetEccCounts_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1) +#define kmemsysGetEccCounts_HAL(pGpu, pKernelMemorySystem, arg0, arg1) kmemsysGetEccCounts_DISPATCH(pGpu, pKernelMemorySystem, arg0, arg1) #define kmemsysClearEccCounts(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem) #define kmemsysClearEccCounts_HAL(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem) -#define kmemsysStateLoad(pGpu, pEngstate, arg0) kmemsysStateLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kmemsysStateUnload(pGpu, pEngstate, arg0) kmemsysStateUnload_DISPATCH(pGpu, pEngstate, arg0) +#define kmemsysGetMaximumBlacklistPages(pGpu, pKernelMemorySystem) kmemsysGetMaximumBlacklistPages_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetMaximumBlacklistPages_HAL(pGpu, pKernelMemorySystem) kmemsysGetMaximumBlacklistPages_DISPATCH(pGpu, pKernelMemorySystem) +#define kmemsysGetFbInfos(arg0, arg1, arg2, arg3, hSubdevice, pParams, pFbInfoListIndicesUnset) kmemsysGetFbInfos_DISPATCH(arg0, arg1, arg2, arg3, hSubdevice, pParams, pFbInfoListIndicesUnset) +#define kmemsysGetFbInfos_HAL(arg0, arg1, arg2, arg3, hSubdevice, pParams, pFbInfoListIndicesUnset) kmemsysGetFbInfos_DISPATCH(arg0, arg1, arg2, arg3, hSubdevice, pParams, pFbInfoListIndicesUnset) #define kmemsysStatePostUnload(pGpu, pEngstate, arg0) kmemsysStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kmemsysStateInitUnlocked(pGpu, pEngstate) kmemsysStateInitUnlocked_DISPATCH(pGpu, pEngstate) #define kmemsysInitMissing(pGpu, pEngstate) kmemsysInitMissing_DISPATCH(pGpu, pEngstate) #define kmemsysStatePreInitLocked(pGpu, pEngstate) kmemsysStatePreInitLocked_DISPATCH(pGpu, pEngstate) #define kmemsysStatePreInitUnlocked(pGpu, pEngstate) kmemsysStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kmemsysIsPresent(pGpu, pEngstate) kmemsysIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS kmemsysGetUsableFbSize_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize); - - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline NV_STATUS kmemsysGetUsableFbSize(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysGetUsableFbSize(pGpu, pKernelMemorySystem, pFbSize) kmemsysGetUsableFbSize_KERNEL(pGpu, pKernelMemorySystem, pFbSize) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysGetUsableFbSize_HAL(pGpu, pKernelMemorySystem, pFbSize) kmemsysGetUsableFbSize(pGpu, pKernelMemorySystem, pFbSize) - static inline void kmemsysAssertSysmemFlushBufferValid_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { return; } @@ -375,20 +401,6 @@ static inline void kmemsysAssertSysmemFlushBufferValid(OBJGPU *pGpu, struct Kern #define kmemsysAssertSysmemFlushBufferValid_HAL(pGpu, pKernelMemorySystem) kmemsysAssertSysmemFlushBufferValid(pGpu, pKernelMemorySystem) -NvU32 kmemsysGetFlushSysmemBufferAddrShift_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); - - -#ifdef __nvoc_kern_mem_sys_h_disabled -static inline NvU32 kmemsysGetFlushSysmemBufferAddrShift(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); - return 0; -} -#else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysGetFlushSysmemBufferAddrShift(pGpu, pKernelMemorySystem) kmemsysGetFlushSysmemBufferAddrShift_GM107(pGpu, pKernelMemorySystem) -#endif //__nvoc_kern_mem_sys_h_disabled - -#define kmemsysGetFlushSysmemBufferAddrShift_HAL(pGpu, pKernelMemorySystem) kmemsysGetFlushSysmemBufferAddrShift(pGpu, pKernelMemorySystem) - NV_STATUS kmemsysInitStaticConfig_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, MEMORY_SYSTEM_STATIC_CONFIG *pConfig); @@ -496,33 +508,51 @@ static inline void kmemsysFreeComprResources(OBJGPU *pGpu, struct KernelMemorySy #define kmemsysFreeComprResources_HAL(pGpu, pKernelMemorySystem, hwResId) kmemsysFreeComprResources(pGpu, pKernelMemorySystem, hwResId) -NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); +NvBool kmemsysNeedInvalidateGpuCacheOnMap_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bIsVolatile, NvU32 aperture); #ifdef __nvoc_kern_mem_sys_h_disabled -static inline NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { +static inline NvBool kmemsysNeedInvalidateGpuCacheOnMap(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bIsVolatile, NvU32 aperture) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return NV_FALSE; } #else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysPopulateMIGGPUInstanceMemConfig(pGpu, pKernelMemorySystem) kmemsysPopulateMIGGPUInstanceMemConfig_KERNEL(pGpu, pKernelMemorySystem) +#define kmemsysNeedInvalidateGpuCacheOnMap(pGpu, pKernelMemorySystem, bIsVolatile, aperture) kmemsysNeedInvalidateGpuCacheOnMap_GV100(pGpu, pKernelMemorySystem, bIsVolatile, aperture) #endif //__nvoc_kern_mem_sys_h_disabled -#define kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem) kmemsysPopulateMIGGPUInstanceMemConfig(pGpu, pKernelMemorySystem) +#define kmemsysNeedInvalidateGpuCacheOnMap_HAL(pGpu, pKernelMemorySystem, bIsVolatile, aperture) kmemsysNeedInvalidateGpuCacheOnMap(pGpu, pKernelMemorySystem, bIsVolatile, aperture) -NvBool kmemsysNeedInvalidateGpuCacheOnMap_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bIsVolatile, NvU32 aperture); +static inline NvBool kmemsysCbcIsSafe_cbe027(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return ((NvBool)(0 == 0)); +} #ifdef __nvoc_kern_mem_sys_h_disabled -static inline NvBool kmemsysNeedInvalidateGpuCacheOnMap(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvBool bIsVolatile, NvU32 aperture) { +static inline NvBool kmemsysCbcIsSafe(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); return NV_FALSE; } #else //__nvoc_kern_mem_sys_h_disabled -#define kmemsysNeedInvalidateGpuCacheOnMap(pGpu, pKernelMemorySystem, bIsVolatile, aperture) kmemsysNeedInvalidateGpuCacheOnMap_GV100(pGpu, pKernelMemorySystem, bIsVolatile, aperture) +#define kmemsysCbcIsSafe(pGpu, pKernelMemorySystem) kmemsysCbcIsSafe_cbe027(pGpu, pKernelMemorySystem) #endif //__nvoc_kern_mem_sys_h_disabled -#define kmemsysNeedInvalidateGpuCacheOnMap_HAL(pGpu, pKernelMemorySystem, bIsVolatile, aperture) kmemsysNeedInvalidateGpuCacheOnMap(pGpu, pKernelMemorySystem, bIsVolatile, aperture) +#define kmemsysCbcIsSafe_HAL(pGpu, pKernelMemorySystem) kmemsysCbcIsSafe(pGpu, pKernelMemorySystem) + +static inline NV_STATUS kmemsysPrepareForXVEReset_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return NV_OK; +} + + +#ifdef __nvoc_kern_mem_sys_h_disabled +static inline NV_STATUS kmemsysPrepareForXVEReset(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + NV_ASSERT_FAILED_PRECOMP("KernelMemorySystem was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_mem_sys_h_disabled +#define kmemsysPrepareForXVEReset(pGpu, pKernelMemorySystem) kmemsysPrepareForXVEReset_56cd7a(pGpu, pKernelMemorySystem) +#endif //__nvoc_kern_mem_sys_h_disabled + +#define kmemsysPrepareForXVEReset_HAL(pGpu, pKernelMemorySystem) kmemsysPrepareForXVEReset(pGpu, pKernelMemorySystem) NV_STATUS kmemsysConstructEngine_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, ENGDESCRIPTOR arg0); @@ -548,26 +578,46 @@ static inline NV_STATUS kmemsysStatePostLoad_DISPATCH(OBJGPU *pGpu, struct Kerne return pKernelMemorySystem->__kmemsysStatePostLoad__(pGpu, pKernelMemorySystem, flags); } +NV_STATUS kmemsysStateLoad_VF(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags); + +static inline NV_STATUS kmemsysStateLoad_ac1694(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { + return NV_OK; +} + +static inline NV_STATUS kmemsysStateLoad_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { + return pKernelMemorySystem->__kmemsysStateLoad__(pGpu, pKernelMemorySystem, flags); +} + NV_STATUS kmemsysStatePreUnload_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags); static inline NV_STATUS kmemsysStatePreUnload_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { return pKernelMemorySystem->__kmemsysStatePreUnload__(pGpu, pKernelMemorySystem, flags); } +NV_STATUS kmemsysStateUnload_VF(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags); + +static inline NV_STATUS kmemsysStateUnload_ac1694(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { + return NV_OK; +} + +static inline NV_STATUS kmemsysStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 flags) { + return pKernelMemorySystem->__kmemsysStateUnload__(pGpu, pKernelMemorySystem, flags); +} + void kmemsysStateDestroy_IMPL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); static inline void kmemsysStateDestroy_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { pKernelMemorySystem->__kmemsysStateDestroy__(pGpu, pKernelMemorySystem); } -NV_STATUS kmemsysGetFbNumaInfo_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *physAddr, NvS32 *numaNodeId); +NV_STATUS kmemsysGetFbNumaInfo_GV100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *physAddr, NvU64 *rsvdPhysAddr, NvS32 *numaNodeId); -static inline NV_STATUS kmemsysGetFbNumaInfo_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *physAddr, NvS32 *numaNodeId) { +static inline NV_STATUS kmemsysGetFbNumaInfo_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *physAddr, NvU64 *rsvdPhysAddr, NvS32 *numaNodeId) { return NV_OK; } -static inline NV_STATUS kmemsysGetFbNumaInfo_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *physAddr, NvS32 *numaNodeId) { - return pKernelMemorySystem->__kmemsysGetFbNumaInfo__(pGpu, pKernelMemorySystem, physAddr, numaNodeId); +static inline NV_STATUS kmemsysGetFbNumaInfo_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *physAddr, NvU64 *rsvdPhysAddr, NvS32 *numaNodeId) { + return pKernelMemorySystem->__kmemsysGetFbNumaInfo__(pGpu, pKernelMemorySystem, physAddr, rsvdPhysAddr, numaNodeId); } NV_STATUS kmemsysReadUsableFbSize_GP102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize); @@ -578,6 +628,16 @@ static inline NV_STATUS kmemsysReadUsableFbSize_DISPATCH(OBJGPU *pGpu, struct Ke return pKernelMemorySystem->__kmemsysReadUsableFbSize__(pGpu, pKernelMemorySystem, pFbSize); } +NV_STATUS kmemsysGetUsableFbSize_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize); + +static inline NV_STATUS kmemsysGetUsableFbSize_5baef9(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kmemsysGetUsableFbSize_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU64 *pFbSize) { + return pKernelMemorySystem->__kmemsysGetUsableFbSize__(pGpu, pKernelMemorySystem, pFbSize); +} + NV_STATUS kmemsysCacheOp_GM200(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation); NV_STATUS kmemsysCacheOp_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, PMEMORY_DESCRIPTOR arg0, FB_CACHE_MEMTYPE arg1, FB_CACHE_OP operation); @@ -634,6 +694,10 @@ static inline void kmemsysWriteL2PeermemInvalidateReg_DISPATCH(OBJGPU *pGpu, str pKernelMemorySystem->__kmemsysWriteL2PeermemInvalidateReg__(pGpu, pKernelMemorySystem, arg0); } +static inline NV_STATUS kmemsysInitFlushSysmemBuffer_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return NV_OK; +} + NV_STATUS kmemsysInitFlushSysmemBuffer_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); NV_STATUS kmemsysInitFlushSysmemBuffer_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); @@ -642,6 +706,10 @@ static inline NV_STATUS kmemsysInitFlushSysmemBuffer_DISPATCH(OBJGPU *pGpu, stru return pKernelMemorySystem->__kmemsysInitFlushSysmemBuffer__(pGpu, pKernelMemorySystem); } +static inline void kmemsysProgramSysmemFlushBuffer_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return; +} + void kmemsysProgramSysmemFlushBuffer_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); void kmemsysProgramSysmemFlushBuffer_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); @@ -652,6 +720,20 @@ static inline void kmemsysProgramSysmemFlushBuffer_DISPATCH(OBJGPU *pGpu, struct pKernelMemorySystem->__kmemsysProgramSysmemFlushBuffer__(pGpu, pKernelMemorySystem); } +static inline NvU32 kmemsysGetFlushSysmemBufferAddrShift_4a4dee(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return 0; +} + +NvU32 kmemsysGetFlushSysmemBufferAddrShift_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysGetFlushSysmemBufferAddrShift_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysGetFlushSysmemBufferAddrShift__(pGpu, pKernelMemorySystem); +} + +static inline NvBool kmemsysIsPagePLCable_cbe027(OBJGPU *pGpu, struct KernelMemorySystem *KernelMemorySystem, NvU64 physAddr, NvU64 pageSize) { + return ((NvBool)(0 == 0)); +} + NvBool kmemsysIsPagePLCable_GA100(OBJGPU *pGpu, struct KernelMemorySystem *KernelMemorySystem, NvU64 physAddr, NvU64 pageSize); NvBool kmemsysIsPagePLCable_GA102(OBJGPU *pGpu, struct KernelMemorySystem *KernelMemorySystem, NvU64 physAddr, NvU64 pageSize); @@ -722,6 +804,16 @@ static inline void kmemsysNumaRemoveAllMemory_DISPATCH(OBJGPU *pGpu, struct Kern pKernelMemorySystem->__kmemsysNumaRemoveAllMemory__(pGpu, pKernelMemorySystem); } +static inline NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return NV_OK; +} + +NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig_KERNEL(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NV_STATUS kmemsysPopulateMIGGPUInstanceMemConfig_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysPopulateMIGGPUInstanceMemConfig__(pGpu, pKernelMemorySystem); +} + static inline NV_STATUS kmemsysSetupAllAtsPeers_46f6a7(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { return NV_ERR_NOT_SUPPORTED; } @@ -752,32 +844,78 @@ static inline NvBool kmemsysAssertFbAckTimeoutPending_DISPATCH(OBJGPU *pGpu, str return pKernelMemorySystem->__kmemsysAssertFbAckTimeoutPending__(pGpu, pKernelMemorySystem); } -void kmemsysCheckEccCounts_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); +NvU32 kmemsysGetMaxFbpas_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); -static inline void kmemsysCheckEccCounts_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { +NvU32 kmemsysGetMaxFbpas_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysGetMaxFbpas_4a4dee(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return 0; +} + +static inline NvU32 kmemsysGetMaxFbpas_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysGetMaxFbpas__(pGpu, pKernelMemorySystem); +} + +NvU32 kmemsysGetEccDedCountSize_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +NvU32 kmemsysGetEccDedCountSize_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU32 kmemsysGetEccDedCountSize_4a4dee(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return 0; +} + +static inline NvU32 kmemsysGetEccDedCountSize_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysGetEccDedCountSize__(pGpu, pKernelMemorySystem); +} + +NvU32 kmemsysGetEccDedCountRegAddr_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp); + +NvU32 kmemsysGetEccDedCountRegAddr_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp); + +static inline NvU32 kmemsysGetEccDedCountRegAddr_4a4dee(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp) { + return 0; +} + +static inline NvU32 kmemsysGetEccDedCountRegAddr_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 fbpa, NvU32 subp) { + return pKernelMemorySystem->__kmemsysGetEccDedCountRegAddr__(pGpu, pKernelMemorySystem, fbpa, subp); +} + +void kmemsysGetEccCounts_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 *arg0, NvU32 *arg1); + +static inline void kmemsysGetEccCounts_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 *arg0, NvU32 *arg1) { return; } -static inline void kmemsysCheckEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - pKernelMemorySystem->__kmemsysCheckEccCounts__(pGpu, pKernelMemorySystem); +static inline void kmemsysGetEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem, NvU32 *arg0, NvU32 *arg1) { + pKernelMemorySystem->__kmemsysGetEccCounts__(pGpu, pKernelMemorySystem, arg0, arg1); } -NV_STATUS kmemsysClearEccCounts_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); +void kmemsysClearEccCounts_TU102(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); -static inline NV_STATUS kmemsysClearEccCounts_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - return NV_OK; +static inline void kmemsysClearEccCounts_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return; } -static inline NV_STATUS kmemsysClearEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { - return pKernelMemorySystem->__kmemsysClearEccCounts__(pGpu, pKernelMemorySystem); +static inline void kmemsysClearEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + pKernelMemorySystem->__kmemsysClearEccCounts__(pGpu, pKernelMemorySystem); } -static inline NV_STATUS kmemsysStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return pEngstate->__kmemsysStateLoad__(pGpu, pEngstate, arg0); +NvU16 kmemsysGetMaximumBlacklistPages_GM107(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +NvU16 kmemsysGetMaximumBlacklistPages_GA100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem); + +static inline NvU16 kmemsysGetMaximumBlacklistPages_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) { + return pKernelMemorySystem->__kmemsysGetMaximumBlacklistPages__(pGpu, pKernelMemorySystem); } -static inline NV_STATUS kmemsysStateUnload_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { - return pEngstate->__kmemsysStateUnload__(pGpu, pEngstate, arg0); +static inline NV_STATUS kmemsysGetFbInfos_ac1694(OBJGPU *arg0, struct KernelMemorySystem *arg1, struct RsClient *arg2, Device *arg3, NvHandle hSubdevice, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams, NvU64 *pFbInfoListIndicesUnset) { + return NV_OK; +} + +NV_STATUS kmemsysGetFbInfos_VF(OBJGPU *arg0, struct KernelMemorySystem *arg1, struct RsClient *arg2, Device *arg3, NvHandle hSubdevice, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams, NvU64 *pFbInfoListIndicesUnset); + +static inline NV_STATUS kmemsysGetFbInfos_DISPATCH(OBJGPU *arg0, struct KernelMemorySystem *arg1, struct RsClient *arg2, Device *arg3, NvHandle hSubdevice, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams, NvU64 *pFbInfoListIndicesUnset) { + return arg1->__kmemsysGetFbInfos__(arg0, arg1, arg2, arg3, hSubdevice, pParams, pFbInfoListIndicesUnset); } static inline NV_STATUS kmemsysStatePostUnload_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, NvU32 arg0) { diff --git a/src/nvidia/generated/g_kern_perf_nvoc.c b/src/nvidia/generated/g_kern_perf_nvoc.c index 12ab9fc9dd..d6168ad633 100644 --- a/src/nvidia/generated/g_kern_perf_nvoc.c +++ b/src/nvidia/generated/g_kern_perf_nvoc.c @@ -175,6 +175,17 @@ static void __nvoc_init_funcTable_KernelPerf_1(KernelPerf *pThis, RmHalspecOwner pThis->__kperfStateDestroy__ = &kperfStateDestroy_IMPL; + // Hal function -- kperfGpuBoostSyncStateInit + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kperfGpuBoostSyncStateInit__ = &kperfGpuBoostSyncStateInit_56cd7a; + } + // default + else + { + pThis->__kperfGpuBoostSyncStateInit__ = &kperfGpuBoostSyncStateInit_IMPL; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelPerf_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelPerf_engstateStateInitLocked; @@ -217,23 +228,31 @@ void __nvoc_init_KernelPerf(KernelPerf *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_KernelPerf(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelPerf *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelPerf), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelPerf)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelPerf); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -251,16 +270,25 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_KernelPerf(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelPerf_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelPerf_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelPerf)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kern_perf_nvoc.h b/src/nvidia/generated/g_kern_perf_nvoc.h index 84ab453c5e..7e9e75d82e 100644 --- a/src/nvidia/generated/g_kern_perf_nvoc.h +++ b/src/nvidia/generated/g_kern_perf_nvoc.h @@ -61,11 +61,16 @@ extern "C" { * interfaces which do not manage the underlying Perf hardware can be * managed by this object. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERN_PERF_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelPerf { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -77,6 +82,7 @@ struct KernelPerf { NV_STATUS (*__kperfStateLoad__)(struct OBJGPU *, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStateUnload__)(struct OBJGPU *, struct KernelPerf *, NvU32); void (*__kperfStateDestroy__)(struct OBJGPU *, struct KernelPerf *); + NV_STATUS (*__kperfGpuBoostSyncStateInit__)(struct OBJGPU *, struct KernelPerf *); NV_STATUS (*__kperfStatePreLoad__)(POBJGPU, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStatePostUnload__)(POBJGPU, struct KernelPerf *, NvU32); NV_STATUS (*__kperfStatePreUnload__)(POBJGPU, struct KernelPerf *, NvU32); @@ -125,6 +131,8 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf**, Dynamic*, NvU32); #define kperfStateLoad(pGpu, pKernelPerf, flags) kperfStateLoad_DISPATCH(pGpu, pKernelPerf, flags) #define kperfStateUnload(pGpu, pKernelPerf, flags) kperfStateUnload_DISPATCH(pGpu, pKernelPerf, flags) #define kperfStateDestroy(pGpu, pKernelPerf) kperfStateDestroy_DISPATCH(pGpu, pKernelPerf) +#define kperfGpuBoostSyncStateInit(pGpu, pKernelPerf) kperfGpuBoostSyncStateInit_DISPATCH(pGpu, pKernelPerf) +#define kperfGpuBoostSyncStateInit_HAL(pGpu, pKernelPerf) kperfGpuBoostSyncStateInit_DISPATCH(pGpu, pKernelPerf) #define kperfStatePreLoad(pGpu, pEngstate, arg0) kperfStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kperfStatePostUnload(pGpu, pEngstate, arg0) kperfStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kperfStatePreUnload(pGpu, pEngstate, arg0) kperfStatePreUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -134,34 +142,6 @@ NV_STATUS __nvoc_objCreate_KernelPerf(KernelPerf**, Dynamic*, NvU32); #define kperfStatePreInitUnlocked(pGpu, pEngstate) kperfStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kperfStatePostLoad(pGpu, pEngstate, arg0) kperfStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kperfIsPresent(pGpu, pEngstate) kperfIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS kperfGpuBoostSyncStateInit_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); - - -#ifdef __nvoc_kern_perf_h_disabled -static inline NV_STATUS kperfGpuBoostSyncStateInit(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { - NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_perf_h_disabled -#define kperfGpuBoostSyncStateInit(pGpu, pKernelPerf) kperfGpuBoostSyncStateInit_IMPL(pGpu, pKernelPerf) -#endif //__nvoc_kern_perf_h_disabled - -#define kperfGpuBoostSyncStateInit_HAL(pGpu, pKernelPerf) kperfGpuBoostSyncStateInit(pGpu, pKernelPerf) - -NV_STATUS kperfBoostSet_3x(struct KernelPerf *pKernelPerf, struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams); - - -#ifdef __nvoc_kern_perf_h_disabled -static inline NV_STATUS kperfBoostSet(struct KernelPerf *pKernelPerf, struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams) { - NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kern_perf_h_disabled -#define kperfBoostSet(pKernelPerf, pSubdevice, pBoostParams) kperfBoostSet_3x(pKernelPerf, pSubdevice, pBoostParams) -#endif //__nvoc_kern_perf_h_disabled - -#define kperfBoostSet_HAL(pKernelPerf, pSubdevice, pBoostParams) kperfBoostSet(pKernelPerf, pSubdevice, pBoostParams) - NV_STATUS kperfConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, ENGDESCRIPTOR engDesc); static inline NV_STATUS kperfConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, ENGDESCRIPTOR engDesc) { @@ -192,6 +172,16 @@ static inline void kperfStateDestroy_DISPATCH(struct OBJGPU *pGpu, struct Kernel pKernelPerf->__kperfStateDestroy__(pGpu, pKernelPerf); } +static inline NV_STATUS kperfGpuBoostSyncStateInit_56cd7a(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { + return NV_OK; +} + +NV_STATUS kperfGpuBoostSyncStateInit_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf); + +static inline NV_STATUS kperfGpuBoostSyncStateInit_DISPATCH(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf) { + return pKernelPerf->__kperfGpuBoostSyncStateInit__(pGpu, pKernelPerf); +} + static inline NV_STATUS kperfStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelPerf *pEngstate, NvU32 arg0) { return pEngstate->__kperfStatePreLoad__(pGpu, pEngstate, arg0); } @@ -250,6 +240,17 @@ static inline NV_STATUS kperfDoSyncGpuBoostLimits(struct OBJGPU *pGpu, struct Ke #define kperfDoSyncGpuBoostLimits(pGpu, pKernelPerf, pParams) kperfDoSyncGpuBoostLimits_IMPL(pGpu, pKernelPerf, pParams) #endif //__nvoc_kern_perf_h_disabled +NV_STATUS kperfBoostSet_IMPL(struct KernelPerf *pKernelPerf, struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams); + +#ifdef __nvoc_kern_perf_h_disabled +static inline NV_STATUS kperfBoostSet(struct KernelPerf *pKernelPerf, struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams) { + NV_ASSERT_FAILED_PRECOMP("KernelPerf was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kern_perf_h_disabled +#define kperfBoostSet(pKernelPerf, pSubdevice, pBoostParams) kperfBoostSet_IMPL(pKernelPerf, pSubdevice, pBoostParams) +#endif //__nvoc_kern_perf_h_disabled + NV_STATUS kperfReentrancy_IMPL(struct OBJGPU *pGpu, struct KernelPerf *pKernelPerf, NvU32 function, NvBool bSet); #ifdef __nvoc_kern_perf_h_disabled diff --git a/src/nvidia/generated/g_kern_perfbuffer_nvoc.c b/src/nvidia/generated/g_kern_perfbuffer_nvoc.c index a99446f149..0e422794a3 100644 --- a/src/nvidia/generated/g_kern_perfbuffer_nvoc.c +++ b/src/nvidia/generated/g_kern_perfbuffer_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_perfbufferControl_Epilogue(struct PerfBuffer rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_perfbufferControlLookup(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle(struct PerfBuffer *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_PerfBuffer_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_perfbufferCanCopy(struct PerfBuffer *pReso return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_perfbufferIsPartialUnmapSupported(struct PerfBuffer *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_perfbufferPreDestruct(struct PerfBuffer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PerfBuffer_RsResource.offset)); } @@ -242,6 +242,16 @@ static void __nvoc_init_funcTable_PerfBuffer_1(PerfBuffer *pThis, RmHalspecOwner PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal function -- perfbufferConstructHal + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__perfbufferConstructHal__ = &perfbufferConstructHal_46f6a7; + } + else + { + pThis->__perfbufferConstructHal__ = &perfbufferConstructHal_KERNEL; + } + pThis->__perfbufferShareCallback__ = &__nvoc_thunk_GpuResource_perfbufferShareCallback; pThis->__perfbufferCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_perfbufferCheckMemInterUnmap; @@ -264,8 +274,6 @@ static void __nvoc_init_funcTable_PerfBuffer_1(PerfBuffer *pThis, RmHalspecOwner pThis->__perfbufferControl_Epilogue__ = &__nvoc_thunk_RmResource_perfbufferControl_Epilogue; - pThis->__perfbufferControlLookup__ = &__nvoc_thunk_RsResource_perfbufferControlLookup; - pThis->__perfbufferGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_perfbufferGetInternalObjectHandle; pThis->__perfbufferControl__ = &__nvoc_thunk_GpuResource_perfbufferControl; @@ -282,6 +290,8 @@ static void __nvoc_init_funcTable_PerfBuffer_1(PerfBuffer *pThis, RmHalspecOwner pThis->__perfbufferCanCopy__ = &__nvoc_thunk_RsResource_perfbufferCanCopy; + pThis->__perfbufferIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_perfbufferIsPartialUnmapSupported; + pThis->__perfbufferPreDestruct__ = &__nvoc_thunk_RsResource_perfbufferPreDestruct; pThis->__perfbufferIsDuplicate__ = &__nvoc_thunk_RsResource_perfbufferIsDuplicate; @@ -309,23 +319,31 @@ void __nvoc_init_PerfBuffer(PerfBuffer *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_PerfBuffer(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; PerfBuffer *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PerfBuffer), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(PerfBuffer)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PerfBuffer); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -343,16 +361,25 @@ NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_PerfBuffer(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_PerfBuffer_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_PerfBuffer_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(PerfBuffer)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kern_perfbuffer_nvoc.h b/src/nvidia/generated/g_kern_perfbuffer_nvoc.h index 57cd134b73..07b17e774e 100644 --- a/src/nvidia/generated/g_kern_perfbuffer_nvoc.h +++ b/src/nvidia/generated/g_kern_perfbuffer_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,11 +41,16 @@ extern "C" { /*! * Definition of PerfBuffer resource class */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERN_PERFBUFFER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct PerfBuffer { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -55,6 +60,7 @@ struct PerfBuffer { struct RmResource *__nvoc_pbase_RmResource; struct GpuResource *__nvoc_pbase_GpuResource; struct PerfBuffer *__nvoc_pbase_PerfBuffer; + NV_STATUS (*__perfbufferConstructHal__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); NvBool (*__perfbufferShareCallback__)(struct PerfBuffer *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__perfbufferCheckMemInterUnmap__)(struct PerfBuffer *, NvBool); NV_STATUS (*__perfbufferMapTo__)(struct PerfBuffer *, RS_RES_MAP_TO_PARAMS *); @@ -66,7 +72,6 @@ struct PerfBuffer { NV_STATUS (*__perfbufferInternalControlForward__)(struct PerfBuffer *, NvU32, void *, NvU32); NV_STATUS (*__perfbufferUnmapFrom__)(struct PerfBuffer *, RS_RES_UNMAP_FROM_PARAMS *); void (*__perfbufferControl_Epilogue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__perfbufferControlLookup__)(struct PerfBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__perfbufferGetInternalObjectHandle__)(struct PerfBuffer *); NV_STATUS (*__perfbufferControl__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__perfbufferUnmap__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -75,6 +80,7 @@ struct PerfBuffer { NV_STATUS (*__perfbufferControlFilter__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__perfbufferControlSerialization_Prologue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__perfbufferCanCopy__)(struct PerfBuffer *); + NvBool (*__perfbufferIsPartialUnmapSupported__)(struct PerfBuffer *); void (*__perfbufferPreDestruct__)(struct PerfBuffer *); NV_STATUS (*__perfbufferIsDuplicate__)(struct PerfBuffer *, NvHandle, NvBool *); void (*__perfbufferControlSerialization_Epilogue__)(struct PerfBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -111,6 +117,8 @@ NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer**, Dynamic*, NvU32, struct CALL #define __objCreate_PerfBuffer(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_PerfBuffer((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) +#define perfbufferConstructHal(pResource, pCallContext, pParams) perfbufferConstructHal_DISPATCH(pResource, pCallContext, pParams) +#define perfbufferConstructHal_HAL(pResource, pCallContext, pParams) perfbufferConstructHal_DISPATCH(pResource, pCallContext, pParams) #define perfbufferShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) perfbufferShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define perfbufferCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) perfbufferCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define perfbufferMapTo(pResource, pParams) perfbufferMapTo_DISPATCH(pResource, pParams) @@ -122,7 +130,6 @@ NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer**, Dynamic*, NvU32, struct CALL #define perfbufferInternalControlForward(pGpuResource, command, pParams, size) perfbufferInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define perfbufferUnmapFrom(pResource, pParams) perfbufferUnmapFrom_DISPATCH(pResource, pParams) #define perfbufferControl_Epilogue(pResource, pCallContext, pParams) perfbufferControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define perfbufferControlLookup(pResource, pParams, ppEntry) perfbufferControlLookup_DISPATCH(pResource, pParams, ppEntry) #define perfbufferGetInternalObjectHandle(pGpuResource) perfbufferGetInternalObjectHandle_DISPATCH(pGpuResource) #define perfbufferControl(pGpuResource, pCallContext, pParams) perfbufferControl_DISPATCH(pGpuResource, pCallContext, pParams) #define perfbufferUnmap(pGpuResource, pCallContext, pCpuMapping) perfbufferUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -131,31 +138,28 @@ NV_STATUS __nvoc_objCreate_PerfBuffer(PerfBuffer**, Dynamic*, NvU32, struct CALL #define perfbufferControlFilter(pResource, pCallContext, pParams) perfbufferControlFilter_DISPATCH(pResource, pCallContext, pParams) #define perfbufferControlSerialization_Prologue(pResource, pCallContext, pParams) perfbufferControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define perfbufferCanCopy(pResource) perfbufferCanCopy_DISPATCH(pResource) +#define perfbufferIsPartialUnmapSupported(pResource) perfbufferIsPartialUnmapSupported_DISPATCH(pResource) #define perfbufferPreDestruct(pResource) perfbufferPreDestruct_DISPATCH(pResource) #define perfbufferIsDuplicate(pResource, hMemory, pDuplicate) perfbufferIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define perfbufferControlSerialization_Epilogue(pResource, pCallContext, pParams) perfbufferControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define perfbufferMap(pGpuResource, pCallContext, pParams, pCpuMapping) perfbufferMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define perfbufferAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) perfbufferAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS perfbufferConstructHal_KERNEL(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); +static inline void perfbufferDestruct_b3696a(struct PerfBuffer *pResource) { + return; +} -#ifdef __nvoc_kern_perfbuffer_h_disabled -static inline NV_STATUS perfbufferConstructHal(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - NV_ASSERT_FAILED_PRECOMP("PerfBuffer was disabled!"); +#define __nvoc_perfbufferDestruct(pResource) perfbufferDestruct_b3696a(pResource) +NV_STATUS perfbufferConstructHal_KERNEL(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS perfbufferConstructHal_46f6a7(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_kern_perfbuffer_h_disabled -#define perfbufferConstructHal(pResource, pCallContext, pParams) perfbufferConstructHal_KERNEL(pResource, pCallContext, pParams) -#endif //__nvoc_kern_perfbuffer_h_disabled - -#define perfbufferConstructHal_HAL(pResource, pCallContext, pParams) perfbufferConstructHal(pResource, pCallContext, pParams) -static inline void perfbufferDestruct_b3696a(struct PerfBuffer *pResource) { - return; +static inline NV_STATUS perfbufferConstructHal_DISPATCH(struct PerfBuffer *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return pResource->__perfbufferConstructHal__(pResource, pCallContext, pParams); } - -#define __nvoc_perfbufferDestruct(pResource) perfbufferDestruct_b3696a(pResource) static inline NvBool perfbufferShareCallback_DISPATCH(struct PerfBuffer *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__perfbufferShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -200,10 +204,6 @@ static inline void perfbufferControl_Epilogue_DISPATCH(struct PerfBuffer *pResou pResource->__perfbufferControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS perfbufferControlLookup_DISPATCH(struct PerfBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__perfbufferControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle perfbufferGetInternalObjectHandle_DISPATCH(struct PerfBuffer *pGpuResource) { return pGpuResource->__perfbufferGetInternalObjectHandle__(pGpuResource); } @@ -236,6 +236,10 @@ static inline NvBool perfbufferCanCopy_DISPATCH(struct PerfBuffer *pResource) { return pResource->__perfbufferCanCopy__(pResource); } +static inline NvBool perfbufferIsPartialUnmapSupported_DISPATCH(struct PerfBuffer *pResource) { + return pResource->__perfbufferIsPartialUnmapSupported__(pResource); +} + static inline void perfbufferPreDestruct_DISPATCH(struct PerfBuffer *pResource) { pResource->__perfbufferPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.c b/src/nvidia/generated/g_kern_pmu_nvoc.c index da2eacd063..f96dec021e 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.c +++ b/src/nvidia/generated/g_kern_pmu_nvoc.c @@ -204,21 +204,26 @@ void __nvoc_init_KernelPmu(KernelPmu *pThis) { __nvoc_init_funcTable_KernelPmu(pThis); } -NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelPmu *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelPmu), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelPmu)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelPmu); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -233,16 +238,25 @@ NV_STATUS __nvoc_objCreate_KernelPmu(KernelPmu **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_KernelPmu(pThis); if (status != NV_OK) goto __nvoc_objCreate_KernelPmu_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelPmu_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelPmu)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kern_pmu_nvoc.h b/src/nvidia/generated/g_kern_pmu_nvoc.h index d0de5c0e91..51f8e5864f 100644 --- a/src/nvidia/generated/g_kern_pmu_nvoc.h +++ b/src/nvidia/generated/g_kern_pmu_nvoc.h @@ -53,11 +53,16 @@ extern "C" { * interfaces which do not manage the underlying Pmu hardware can be * managed by this object. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERN_PMU_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelPmu { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index b383be4a3a..2a3142d0db 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -175,6 +175,12 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe pThis->setProperty(pThis, PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI, ((NvBool)(0 == 0))); } + // NVOC Property Hal field -- PDB_PROP_KBIF_ALLOW_REARM_MSI_FOR_VF + // default + { + pThis->setProperty(pThis, PDB_PROP_KBIF_ALLOW_REARM_MSI_FOR_VF, ((NvBool)(0 != 0))); + } + // NVOC Property Hal field -- PDB_PROP_KBIF_P2P_READS_DISABLED // default { @@ -198,6 +204,23 @@ void __nvoc_init_dataField_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspe pThis->setProperty(pThis, PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944, ((NvBool)(0 != 0))); } pThis->setProperty(pThis, PDB_PROP_KBIF_SUPPORT_NONCOHERENT, ((NvBool)(0 == 0))); + + // NVOC Property Hal field -- PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->setProperty(pThis, PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED, ((NvBool)(0 == 0))); + } + + // NVOC Property Hal field -- PDB_PROP_KBIF_FLR_PRE_CONDITIONING_REQUIRED + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->setProperty(pThis, PDB_PROP_KBIF_FLR_PRE_CONDITIONING_REQUIRED, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_KBIF_FLR_PRE_CONDITIONING_REQUIRED, ((NvBool)(0 != 0))); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -234,11 +257,58 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifStateLoad__ = &kbifStateLoad_IMPL; // Hal function -- kbifStatePostLoad - pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_IMPL; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_56cd7a; + } + else + { + pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_IMPL; + } // Hal function -- kbifStateUnload pThis->__kbifStateUnload__ = &kbifStateUnload_IMPL; + // Hal function -- kbifGetBusIntfType + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbifGetBusIntfType__ = &kbifGetBusIntfType_28ceda; + } + else + { + pThis->__kbifGetBusIntfType__ = &kbifGetBusIntfType_2f2c74; + } + + // Hal function -- kbifInitDmaCaps + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kbifInitDmaCaps__ = &kbifInitDmaCaps_VGPUSTUB; + } + else + { + pThis->__kbifInitDmaCaps__ = &kbifInitDmaCaps_IMPL; + } + + // Hal function -- kbifSavePcieConfigRegisters + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifSavePcieConfigRegisters__ = &kbifSavePcieConfigRegisters_GH100; + } + else + { + pThis->__kbifSavePcieConfigRegisters__ = &kbifSavePcieConfigRegisters_GM107; + } + + // Hal function -- kbifRestorePcieConfigRegisters + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifRestorePcieConfigRegisters__ = &kbifRestorePcieConfigRegisters_GH100; + } + else + { + pThis->__kbifRestorePcieConfigRegisters__ = &kbifRestorePcieConfigRegisters_GM107; + } + // Hal function -- kbifGetXveStatusBits if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -391,14 +461,21 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } // Hal function -- kbifInitRelaxedOrderingFromEmulatedConfigSpace - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100; + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a; } - // default else { - pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100; + } + // default + else + { + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a; + } } // Hal function -- kbifEnableNoSnoop @@ -422,14 +499,21 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } // Hal function -- kbifProbePcieReqAtomicCaps - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_GH100; + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_b3696a; } - // default else { - pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_b3696a; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_GH100; + } + // default + else + { + pThis->__kbifProbePcieReqAtomicCaps__ = &kbifProbePcieReqAtomicCaps_b3696a; + } } // Hal function -- kbifEnablePcieAtomics @@ -443,6 +527,16 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifEnablePcieAtomics__ = &kbifEnablePcieAtomics_b3696a; } + // Hal function -- kbifDoFunctionLevelReset + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifDoFunctionLevelReset__ = &kbifDoFunctionLevelReset_GH100; + } + else + { + pThis->__kbifDoFunctionLevelReset__ = &kbifDoFunctionLevelReset_TU102; + } + // Hal function -- kbifInitXveRegMap if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -463,6 +557,39 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifGetMSIXTableVectorControlSize__ = &kbifGetMSIXTableVectorControlSize_TU102; } + // Hal function -- kbifSaveMsixTable + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifSaveMsixTable__ = &kbifSaveMsixTable_GH100; + } + // default + else + { + pThis->__kbifSaveMsixTable__ = &kbifSaveMsixTable_46f6a7; + } + + // Hal function -- kbifRestoreMsixTable + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifRestoreMsixTable__ = &kbifRestoreMsixTable_GH100; + } + // default + else + { + pThis->__kbifRestoreMsixTable__ = &kbifRestoreMsixTable_46f6a7; + } + + // Hal function -- kbifConfigAccessWait + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifConfigAccessWait__ = &kbifConfigAccessWait_GH100; + } + // default + else + { + pThis->__kbifConfigAccessWait__ = &kbifConfigAccessWait_46f6a7; + } + // Hal function -- kbifGetPciConfigSpacePriMirror if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -495,13 +622,20 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * } // Hal function -- kbifStopSysMemRequests - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kbifStopSysMemRequests__ = &kbifStopSysMemRequests_GH100; + pThis->__kbifStopSysMemRequests__ = &kbifStopSysMemRequests_56cd7a; } else { - pThis->__kbifStopSysMemRequests__ = &kbifStopSysMemRequests_GM107; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifStopSysMemRequests__ = &kbifStopSysMemRequests_GH100; + } + else + { + pThis->__kbifStopSysMemRequests__ = &kbifStopSysMemRequests_GM107; + } } // Hal function -- kbifWaitForTransactionsComplete @@ -614,6 +748,48 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifInit__ = &kbifInit_GM107; } + // Hal function -- kbifGetValidEnginesToReset + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kbifGetValidEnginesToReset__ = &kbifGetValidEnginesToReset_TU102; + } + else + { + pThis->__kbifGetValidEnginesToReset__ = &kbifGetValidEnginesToReset_GA100; + } + + // Hal function -- kbifGetValidDeviceEnginesToReset + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + { + pThis->__kbifGetValidDeviceEnginesToReset__ = &kbifGetValidDeviceEnginesToReset_15a734; + } + else + { + pThis->__kbifGetValidDeviceEnginesToReset__ = &kbifGetValidDeviceEnginesToReset_GA100; + } + + // Hal function -- kbifGetEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifGetEccCounts__ = &kbifGetEccCounts_GH100; + } + // default + else + { + pThis->__kbifGetEccCounts__ = &kbifGetEccCounts_4a4dee; + } + + // Hal function -- kbifClearEccCounts + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kbifClearEccCounts__ = &kbifClearEccCounts_GH100; + } + // default + else + { + pThis->__kbifClearEccCounts__ = &kbifClearEccCounts_56cd7a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelBif_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelBif_engstateStateInitLocked; @@ -656,23 +832,31 @@ void __nvoc_init_KernelBif(KernelBif *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelBif(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelBif(KernelBif **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelBif(KernelBif **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelBif *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelBif), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelBif)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelBif); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -690,16 +874,25 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_KernelBif(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelBif_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelBif_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelBif)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index 0a1d2697c4..ece2135a98 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -74,8 +74,9 @@ typedef enum BUS_OPTIONS { BUS_OPTIONS_DEV_CONTROL_STATUS = 0, BUS_OPTIONS_LINK_CONTROL_STATUS, - BUS_OPTIONS_LINK_CAPABILITIES - + BUS_OPTIONS_LINK_CAPABILITIES, + BUS_OPTIONS_DEV_CONTROL_STATUS_2, + BUS_OPTIONS_L1_PM_SUBSTATES_CTRL_1 } BUS_OPTIONS; // @@ -118,11 +119,16 @@ typedef struct typedef struct KERNEL_HOST_VGPU_DEVICE KERNEL_HOST_VGPU_DEVICE; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_BIF_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelBif { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -134,6 +140,10 @@ struct KernelBif { NV_STATUS (*__kbifStateLoad__)(struct OBJGPU *, struct KernelBif *, NvU32); NV_STATUS (*__kbifStatePostLoad__)(struct OBJGPU *, struct KernelBif *, NvU32); NV_STATUS (*__kbifStateUnload__)(struct OBJGPU *, struct KernelBif *, NvU32); + NvU32 (*__kbifGetBusIntfType__)(struct KernelBif *); + void (*__kbifInitDmaCaps__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifSavePcieConfigRegisters__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifRestorePcieConfigRegisters__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifGetXveStatusBits__)(struct OBJGPU *, struct KernelBif *, NvU32 *, NvU32 *); NV_STATUS (*__kbifClearXveStatus__)(struct OBJGPU *, struct KernelBif *, NvU32 *); NV_STATUS (*__kbifGetXveAerBits__)(struct OBJGPU *, struct KernelBif *, NvU32 *); @@ -154,8 +164,12 @@ struct KernelBif { void (*__kbifApplyWARBug3208922__)(struct OBJGPU *, struct KernelBif *); void (*__kbifProbePcieReqAtomicCaps__)(struct OBJGPU *, struct KernelBif *); void (*__kbifEnablePcieAtomics__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifDoFunctionLevelReset__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifInitXveRegMap__)(struct OBJGPU *, struct KernelBif *, NvU8); NvU32 (*__kbifGetMSIXTableVectorControlSize__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifSaveMsixTable__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifRestoreMsixTable__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifConfigAccessWait__)(struct OBJGPU *, struct KernelBif *, RMTIMEOUT *); NV_STATUS (*__kbifGetPciConfigSpacePriMirror__)(struct OBJGPU *, struct KernelBif *, NvU32 *, NvU32 *); NV_STATUS (*__kbifGetBusOptionsAddr__)(struct OBJGPU *, struct KernelBif *, BUS_OPTIONS, NvU32 *); NV_STATUS (*__kbifPreOsGlobalErotGrantRequest__)(struct OBJGPU *, struct KernelBif *); @@ -170,6 +184,10 @@ struct KernelBif { NV_STATUS (*__kbifRestoreBarsAndCommand__)(struct OBJGPU *, struct KernelBif *); void (*__kbifStoreBarRegOffsets__)(struct OBJGPU *, struct KernelBif *, NvU32); NV_STATUS (*__kbifInit__)(struct OBJGPU *, struct KernelBif *); + NvU32 (*__kbifGetValidEnginesToReset__)(struct OBJGPU *, struct KernelBif *); + NvU32 (*__kbifGetValidDeviceEnginesToReset__)(struct OBJGPU *, struct KernelBif *); + NvU32 (*__kbifGetEccCounts__)(struct OBJGPU *, struct KernelBif *); + NV_STATUS (*__kbifClearEccCounts__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifStatePreLoad__)(POBJGPU, struct KernelBif *, NvU32); NV_STATUS (*__kbifStatePostUnload__)(POBJGPU, struct KernelBif *, NvU32); void (*__kbifStateDestroy__)(POBJGPU, struct KernelBif *); @@ -186,6 +204,7 @@ struct KernelBif { NvBool PDB_PROP_KBIF_IS_MSIX_CACHED; NvBool PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN; NvBool PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI; + NvBool PDB_PROP_KBIF_ALLOW_REARM_MSI_FOR_VF; NvBool PDB_PROP_KBIF_IS_C2C_LINK_UP; NvBool PDB_PROP_KBIF_P2P_READS_DISABLED; NvBool PDB_PROP_KBIF_P2P_WRITES_DISABLED; @@ -198,6 +217,10 @@ struct KernelBif { NvBool PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED; NvBool PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION; NvBool PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE; + NvBool PDB_PROP_KBIF_SECONDARY_BUS_RESET_SUPPORTED; + NvBool PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED; + NvBool PDB_PROP_KBIF_FORCE_PCIE_CONFIG_SAVE; + NvBool PDB_PROP_KBIF_FLR_PRE_CONDITIONING_REQUIRED; NvU32 dmaCaps; RmPhysAddr dmaWindowStartAddress; NvU32 p2pOverride; @@ -205,7 +228,11 @@ struct KernelBif { NvBool peerMappingOverride; NvBool EnteredRecoverySinceErrorsLastChecked; KBIF_CACHE_DATA cacheData; + NvBool bPreparingFunctionLevelReset; + NvBool bInFunctionLevelReset; NvU32 osPcieAtomicsOpMask; + NvBool bForceDisableFLR; + NvU32 flrDevInitTimeoutScale; KBIF_XVE_REGMAP_REF xveRegmapRef[2]; NvBool bMnocAvailable; NvU32 barRegOffsets[7]; @@ -236,20 +263,36 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBif; #define PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF_BASE_NAME PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF #define PDB_PROP_KBIF_IS_C2C_LINK_UP_BASE_CAST #define PDB_PROP_KBIF_IS_C2C_LINK_UP_BASE_NAME PDB_PROP_KBIF_IS_C2C_LINK_UP +#define PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI_BASE_CAST +#define PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI_BASE_NAME PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI +#define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_CAST +#define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_NAME PDB_PROP_KBIF_IS_MSI_ENABLED +#define PDB_PROP_KBIF_FORCE_PCIE_CONFIG_SAVE_BASE_CAST +#define PDB_PROP_KBIF_FORCE_PCIE_CONFIG_SAVE_BASE_NAME PDB_PROP_KBIF_FORCE_PCIE_CONFIG_SAVE +#define PDB_PROP_KBIF_PCIE_GEN4_CAPABLE_BASE_CAST +#define PDB_PROP_KBIF_PCIE_GEN4_CAPABLE_BASE_NAME PDB_PROP_KBIF_PCIE_GEN4_CAPABLE +#define PDB_PROP_KBIF_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. +#define PDB_PROP_KBIF_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING +#define PDB_PROP_KBIF_IS_MSI_CACHED_BASE_CAST +#define PDB_PROP_KBIF_IS_MSI_CACHED_BASE_NAME PDB_PROP_KBIF_IS_MSI_CACHED +#define PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION_BASE_CAST +#define PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION_BASE_NAME PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION +#define PDB_PROP_KBIF_ALLOW_REARM_MSI_FOR_VF_BASE_CAST +#define PDB_PROP_KBIF_ALLOW_REARM_MSI_FOR_VF_BASE_NAME PDB_PROP_KBIF_ALLOW_REARM_MSI_FOR_VF +#define PDB_PROP_KBIF_SUPPORT_NONCOHERENT_BASE_CAST +#define PDB_PROP_KBIF_SUPPORT_NONCOHERENT_BASE_NAME PDB_PROP_KBIF_SUPPORT_NONCOHERENT #define PDB_PROP_KBIF_IS_MSIX_ENABLED_BASE_CAST #define PDB_PROP_KBIF_IS_MSIX_ENABLED_BASE_NAME PDB_PROP_KBIF_IS_MSIX_ENABLED #define PDB_PROP_KBIF_P2P_WRITES_DISABLED_BASE_CAST #define PDB_PROP_KBIF_P2P_WRITES_DISABLED_BASE_NAME PDB_PROP_KBIF_P2P_WRITES_DISABLED #define PDB_PROP_KBIF_FLR_SUPPORTED_BASE_CAST #define PDB_PROP_KBIF_FLR_SUPPORTED_BASE_NAME PDB_PROP_KBIF_FLR_SUPPORTED -#define PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI_BASE_CAST -#define PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI_BASE_NAME PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI -#define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_CAST -#define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_NAME PDB_PROP_KBIF_IS_MSI_ENABLED -#define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_CAST -#define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_NAME PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE #define PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED_BASE_CAST #define PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED_BASE_NAME PDB_PROP_KBIF_SYSTEM_ACCESS_DISABLED +#define PDB_PROP_KBIF_FLR_PRE_CONDITIONING_REQUIRED_BASE_CAST +#define PDB_PROP_KBIF_FLR_PRE_CONDITIONING_REQUIRED_BASE_NAME PDB_PROP_KBIF_FLR_PRE_CONDITIONING_REQUIRED +#define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_CAST +#define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_NAME PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE #define PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE_BASE_CAST #define PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE_BASE_NAME PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE #define PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED_BASE_CAST @@ -258,20 +301,14 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBif; #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_NAME PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944 #define PDB_PROP_KBIF_IS_MSIX_CACHED_BASE_CAST #define PDB_PROP_KBIF_IS_MSIX_CACHED_BASE_NAME PDB_PROP_KBIF_IS_MSIX_CACHED -#define PDB_PROP_KBIF_PCIE_GEN4_CAPABLE_BASE_CAST -#define PDB_PROP_KBIF_PCIE_GEN4_CAPABLE_BASE_NAME PDB_PROP_KBIF_PCIE_GEN4_CAPABLE -#define PDB_PROP_KBIF_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE. -#define PDB_PROP_KBIF_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING #define PDB_PROP_KBIF_P2P_READS_DISABLED_BASE_CAST #define PDB_PROP_KBIF_P2P_READS_DISABLED_BASE_NAME PDB_PROP_KBIF_P2P_READS_DISABLED +#define PDB_PROP_KBIF_SECONDARY_BUS_RESET_SUPPORTED_BASE_CAST +#define PDB_PROP_KBIF_SECONDARY_BUS_RESET_SUPPORTED_BASE_NAME PDB_PROP_KBIF_SECONDARY_BUS_RESET_SUPPORTED #define PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN_BASE_CAST #define PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN_BASE_NAME PDB_PROP_KBIF_IS_FMODEL_MSI_BROKEN -#define PDB_PROP_KBIF_IS_MSI_CACHED_BASE_CAST -#define PDB_PROP_KBIF_IS_MSI_CACHED_BASE_NAME PDB_PROP_KBIF_IS_MSI_CACHED -#define PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION_BASE_CAST -#define PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION_BASE_NAME PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION -#define PDB_PROP_KBIF_SUPPORT_NONCOHERENT_BASE_CAST -#define PDB_PROP_KBIF_SUPPORT_NONCOHERENT_BASE_NAME PDB_PROP_KBIF_SUPPORT_NONCOHERENT +#define PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED_BASE_CAST +#define PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED_BASE_NAME PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED NV_STATUS __nvoc_objCreateDynamic_KernelBif(KernelBif**, Dynamic*, NvU32, va_list); @@ -287,6 +324,14 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifStatePostLoad_HAL(pGpu, pKernelBif, arg0) kbifStatePostLoad_DISPATCH(pGpu, pKernelBif, arg0) #define kbifStateUnload(pGpu, pKernelBif, arg0) kbifStateUnload_DISPATCH(pGpu, pKernelBif, arg0) #define kbifStateUnload_HAL(pGpu, pKernelBif, arg0) kbifStateUnload_DISPATCH(pGpu, pKernelBif, arg0) +#define kbifGetBusIntfType(pKernelBif) kbifGetBusIntfType_DISPATCH(pKernelBif) +#define kbifGetBusIntfType_HAL(pKernelBif) kbifGetBusIntfType_DISPATCH(pKernelBif) +#define kbifInitDmaCaps(pGpu, pKernelBif) kbifInitDmaCaps_DISPATCH(pGpu, pKernelBif) +#define kbifInitDmaCaps_HAL(pGpu, pKernelBif) kbifInitDmaCaps_DISPATCH(pGpu, pKernelBif) +#define kbifSavePcieConfigRegisters(pGpu, pKernelBif) kbifSavePcieConfigRegisters_DISPATCH(pGpu, pKernelBif) +#define kbifSavePcieConfigRegisters_HAL(pGpu, pKernelBif) kbifSavePcieConfigRegisters_DISPATCH(pGpu, pKernelBif) +#define kbifRestorePcieConfigRegisters(pGpu, pKernelBif) kbifRestorePcieConfigRegisters_DISPATCH(pGpu, pKernelBif) +#define kbifRestorePcieConfigRegisters_HAL(pGpu, pKernelBif) kbifRestorePcieConfigRegisters_DISPATCH(pGpu, pKernelBif) #define kbifGetXveStatusBits(pGpu, pKernelBif, pBits, pStatus) kbifGetXveStatusBits_DISPATCH(pGpu, pKernelBif, pBits, pStatus) #define kbifGetXveStatusBits_HAL(pGpu, pKernelBif, pBits, pStatus) kbifGetXveStatusBits_DISPATCH(pGpu, pKernelBif, pBits, pStatus) #define kbifClearXveStatus(pGpu, pKernelBif, pStatus) kbifClearXveStatus_DISPATCH(pGpu, pKernelBif, pStatus) @@ -327,10 +372,18 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifProbePcieReqAtomicCaps_HAL(pGpu, pKernelBif) kbifProbePcieReqAtomicCaps_DISPATCH(pGpu, pKernelBif) #define kbifEnablePcieAtomics(pGpu, pKernelBif) kbifEnablePcieAtomics_DISPATCH(pGpu, pKernelBif) #define kbifEnablePcieAtomics_HAL(pGpu, pKernelBif) kbifEnablePcieAtomics_DISPATCH(pGpu, pKernelBif) +#define kbifDoFunctionLevelReset(pGpu, pKernelBif) kbifDoFunctionLevelReset_DISPATCH(pGpu, pKernelBif) +#define kbifDoFunctionLevelReset_HAL(pGpu, pKernelBif) kbifDoFunctionLevelReset_DISPATCH(pGpu, pKernelBif) #define kbifInitXveRegMap(pGpu, pKernelBif, arg0) kbifInitXveRegMap_DISPATCH(pGpu, pKernelBif, arg0) #define kbifInitXveRegMap_HAL(pGpu, pKernelBif, arg0) kbifInitXveRegMap_DISPATCH(pGpu, pKernelBif, arg0) #define kbifGetMSIXTableVectorControlSize(pGpu, pKernelBif) kbifGetMSIXTableVectorControlSize_DISPATCH(pGpu, pKernelBif) #define kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif) kbifGetMSIXTableVectorControlSize_DISPATCH(pGpu, pKernelBif) +#define kbifSaveMsixTable(pGpu, pKernelBif) kbifSaveMsixTable_DISPATCH(pGpu, pKernelBif) +#define kbifSaveMsixTable_HAL(pGpu, pKernelBif) kbifSaveMsixTable_DISPATCH(pGpu, pKernelBif) +#define kbifRestoreMsixTable(pGpu, pKernelBif) kbifRestoreMsixTable_DISPATCH(pGpu, pKernelBif) +#define kbifRestoreMsixTable_HAL(pGpu, pKernelBif) kbifRestoreMsixTable_DISPATCH(pGpu, pKernelBif) +#define kbifConfigAccessWait(pGpu, pKernelBif, pTimeout) kbifConfigAccessWait_DISPATCH(pGpu, pKernelBif, pTimeout) +#define kbifConfigAccessWait_HAL(pGpu, pKernelBif, pTimeout) kbifConfigAccessWait_DISPATCH(pGpu, pKernelBif, pTimeout) #define kbifGetPciConfigSpacePriMirror(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) #define kbifGetPciConfigSpacePriMirror_HAL(pGpu, pKernelBif, pMirrorBase, pMirrorSize) kbifGetPciConfigSpacePriMirror_DISPATCH(pGpu, pKernelBif, pMirrorBase, pMirrorSize) #define kbifGetBusOptionsAddr(pGpu, pKernelBif, options, addrReg) kbifGetBusOptionsAddr_DISPATCH(pGpu, pKernelBif, options, addrReg) @@ -359,6 +412,14 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifStoreBarRegOffsets_HAL(pGpu, pKernelBif, arg0) kbifStoreBarRegOffsets_DISPATCH(pGpu, pKernelBif, arg0) #define kbifInit(pGpu, pKernelBif) kbifInit_DISPATCH(pGpu, pKernelBif) #define kbifInit_HAL(pGpu, pKernelBif) kbifInit_DISPATCH(pGpu, pKernelBif) +#define kbifGetValidEnginesToReset(pGpu, pKernelBif) kbifGetValidEnginesToReset_DISPATCH(pGpu, pKernelBif) +#define kbifGetValidEnginesToReset_HAL(pGpu, pKernelBif) kbifGetValidEnginesToReset_DISPATCH(pGpu, pKernelBif) +#define kbifGetValidDeviceEnginesToReset(pGpu, pKernelBif) kbifGetValidDeviceEnginesToReset_DISPATCH(pGpu, pKernelBif) +#define kbifGetValidDeviceEnginesToReset_HAL(pGpu, pKernelBif) kbifGetValidDeviceEnginesToReset_DISPATCH(pGpu, pKernelBif) +#define kbifGetEccCounts(pGpu, pKernelBif) kbifGetEccCounts_DISPATCH(pGpu, pKernelBif) +#define kbifGetEccCounts_HAL(pGpu, pKernelBif) kbifGetEccCounts_DISPATCH(pGpu, pKernelBif) +#define kbifClearEccCounts(pGpu, pKernelBif) kbifClearEccCounts_DISPATCH(pGpu, pKernelBif) +#define kbifClearEccCounts_HAL(pGpu, pKernelBif) kbifClearEccCounts_DISPATCH(pGpu, pKernelBif) #define kbifStatePreLoad(pGpu, pEngstate, arg0) kbifStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbifStatePostUnload(pGpu, pEngstate, arg0) kbifStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kbifStateDestroy(pGpu, pEngstate) kbifStateDestroy_DISPATCH(pGpu, pEngstate) @@ -372,74 +433,73 @@ void kbifDestruct_GM107(struct KernelBif *pKernelBif); #define __nvoc_kbifDestruct(pKernelBif) kbifDestruct_GM107(pKernelBif) -static inline NvU32 kbifGetBusIntfType_2f2c74(struct KernelBif *pKernelBif) { - return (3); -} +void kbifClearConfigErrors_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool arg0, NvU32 arg1); #ifdef __nvoc_kernel_bif_h_disabled -static inline NvU32 kbifGetBusIntfType(struct KernelBif *pKernelBif) { +static inline void kbifClearConfigErrors(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool arg0, NvU32 arg1) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); - return 0; } #else //__nvoc_kernel_bif_h_disabled -#define kbifGetBusIntfType(pKernelBif) kbifGetBusIntfType_2f2c74(pKernelBif) +#define kbifClearConfigErrors(pGpu, pKernelBif, arg0, arg1) kbifClearConfigErrors_IMPL(pGpu, pKernelBif, arg0, arg1) #endif //__nvoc_kernel_bif_h_disabled -#define kbifGetBusIntfType_HAL(pKernelBif) kbifGetBusIntfType(pKernelBif) +#define kbifClearConfigErrors_HAL(pGpu, pKernelBif, arg0, arg1) kbifClearConfigErrors(pGpu, pKernelBif, arg0, arg1) -void kbifInitDmaCaps_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +void kbifDisableP2PTransactions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); #ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifInitDmaCaps(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { +static inline void kbifDisableP2PTransactions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); } #else //__nvoc_kernel_bif_h_disabled -#define kbifInitDmaCaps(pGpu, pKernelBif) kbifInitDmaCaps_IMPL(pGpu, pKernelBif) +#define kbifDisableP2PTransactions(pGpu, pKernelBif) kbifDisableP2PTransactions_TU102(pGpu, pKernelBif) #endif //__nvoc_kernel_bif_h_disabled -#define kbifInitDmaCaps_HAL(pGpu, pKernelBif) kbifInitDmaCaps(pGpu, pKernelBif) +#define kbifDisableP2PTransactions_HAL(pGpu, pKernelBif) kbifDisableP2PTransactions(pGpu, pKernelBif) -void kbifClearConfigErrors_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool arg0, NvU32 arg1); +NV_STATUS kbifGetVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 osPageSize, NvU32 *pNumAreas, NvU64 *pOffsets, NvU64 *pSizes); #ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifClearConfigErrors(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool arg0, NvU32 arg1) { +static inline NV_STATUS kbifGetVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 osPageSize, NvU32 *pNumAreas, NvU64 *pOffsets, NvU64 *pSizes) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifClearConfigErrors(pGpu, pKernelBif, arg0, arg1) kbifClearConfigErrors_IMPL(pGpu, pKernelBif, arg0, arg1) +#define kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) kbifGetVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) #endif //__nvoc_kernel_bif_h_disabled -#define kbifClearConfigErrors_HAL(pGpu, pKernelBif, arg0, arg1) kbifClearConfigErrors(pGpu, pKernelBif, arg0, arg1) +#define kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) -void kbifDisableP2PTransactions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); +NV_STATUS kbifSaveMSIXVectorControlMasks_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *arg0); #ifdef __nvoc_kernel_bif_h_disabled -static inline void kbifDisableP2PTransactions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { +static inline NV_STATUS kbifSaveMSIXVectorControlMasks(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifDisableP2PTransactions(pGpu, pKernelBif) kbifDisableP2PTransactions_TU102(pGpu, pKernelBif) +#define kbifSaveMSIXVectorControlMasks(pGpu, pKernelBif, arg0) kbifSaveMSIXVectorControlMasks_TU102(pGpu, pKernelBif, arg0) #endif //__nvoc_kernel_bif_h_disabled -#define kbifDisableP2PTransactions_HAL(pGpu, pKernelBif) kbifDisableP2PTransactions(pGpu, pKernelBif) +#define kbifSaveMSIXVectorControlMasks_HAL(pGpu, pKernelBif, arg0) kbifSaveMSIXVectorControlMasks(pGpu, pKernelBif, arg0) -NV_STATUS kbifGetVFSparseMmapRegions_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 osPageSize, NvU32 *pNumAreas, NvU64 *pOffsets, NvU64 *pSizes); +NV_STATUS kbifRestoreMSIXVectorControlMasks_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); #ifdef __nvoc_kernel_bif_h_disabled -static inline NV_STATUS kbifGetVFSparseMmapRegions(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, NvU64 osPageSize, NvU32 *pNumAreas, NvU64 *pOffsets, NvU64 *pSizes) { +static inline NV_STATUS kbifRestoreMSIXVectorControlMasks(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_bif_h_disabled -#define kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) kbifGetVFSparseMmapRegions_TU102(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) +#define kbifRestoreMSIXVectorControlMasks(pGpu, pKernelBif, arg0) kbifRestoreMSIXVectorControlMasks_TU102(pGpu, pKernelBif, arg0) #endif //__nvoc_kernel_bif_h_disabled -#define kbifGetVFSparseMmapRegions_HAL(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) kbifGetVFSparseMmapRegions(pGpu, pKernelBif, pKernelHostVgpuDevice, osPageSize, pNumAreas, pOffsets, pSizes) +#define kbifRestoreMSIXVectorControlMasks_HAL(pGpu, pKernelBif, arg0) kbifRestoreMSIXVectorControlMasks(pGpu, pKernelBif, arg0) NV_STATUS kbifDisableSysmemAccess_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bDisable); @@ -488,6 +548,10 @@ static inline NV_STATUS kbifStateLoad_DISPATCH(struct OBJGPU *pGpu, struct Kerne return pKernelBif->__kbifStateLoad__(pGpu, pKernelBif, arg0); } +static inline NV_STATUS kbifStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return NV_OK; +} + NV_STATUS kbifStatePostLoad_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); static inline NV_STATUS kbifStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { @@ -500,6 +564,42 @@ static inline NV_STATUS kbifStateUnload_DISPATCH(struct OBJGPU *pGpu, struct Ker return pKernelBif->__kbifStateUnload__(pGpu, pKernelBif, arg0); } +static inline NvU32 kbifGetBusIntfType_28ceda(struct KernelBif *pKernelBif) { + return (1); +} + +static inline NvU32 kbifGetBusIntfType_2f2c74(struct KernelBif *pKernelBif) { + return (3); +} + +static inline NvU32 kbifGetBusIntfType_DISPATCH(struct KernelBif *pKernelBif) { + return pKernelBif->__kbifGetBusIntfType__(pKernelBif); +} + +void kbifInitDmaCaps_VGPUSTUB(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +void kbifInitDmaCaps_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline void kbifInitDmaCaps_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + pKernelBif->__kbifInitDmaCaps__(pGpu, pKernelBif); +} + +NV_STATUS kbifSavePcieConfigRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NV_STATUS kbifSavePcieConfigRegisters_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifSavePcieConfigRegisters_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifSavePcieConfigRegisters__(pGpu, pKernelBif); +} + +NV_STATUS kbifRestorePcieConfigRegisters_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NV_STATUS kbifRestorePcieConfigRegisters_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifRestorePcieConfigRegisters_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifRestorePcieConfigRegisters__(pGpu, pKernelBif); +} + NV_STATUS kbifGetXveStatusBits_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus); NV_STATUS kbifGetXveStatusBits_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pBits, NvU32 *pStatus); @@ -680,6 +780,14 @@ static inline void kbifEnablePcieAtomics_DISPATCH(struct OBJGPU *pGpu, struct Ke pKernelBif->__kbifEnablePcieAtomics__(pGpu, pKernelBif); } +NV_STATUS kbifDoFunctionLevelReset_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NV_STATUS kbifDoFunctionLevelReset_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifDoFunctionLevelReset_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifDoFunctionLevelReset__(pGpu, pKernelBif); +} + NV_STATUS kbifInitXveRegMap_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg0); NV_STATUS kbifInitXveRegMap_GA102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg0); @@ -696,6 +804,36 @@ static inline NvU32 kbifGetMSIXTableVectorControlSize_DISPATCH(struct OBJGPU *pG return pKernelBif->__kbifGetMSIXTableVectorControlSize__(pGpu, pKernelBif); } +NV_STATUS kbifSaveMsixTable_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifSaveMsixTable_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbifSaveMsixTable_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifSaveMsixTable__(pGpu, pKernelBif); +} + +NV_STATUS kbifRestoreMsixTable_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifRestoreMsixTable_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbifRestoreMsixTable_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifRestoreMsixTable__(pGpu, pKernelBif); +} + +NV_STATUS kbifConfigAccessWait_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, RMTIMEOUT *pTimeout); + +static inline NV_STATUS kbifConfigAccessWait_46f6a7(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, RMTIMEOUT *pTimeout) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kbifConfigAccessWait_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, RMTIMEOUT *pTimeout) { + return pKernelBif->__kbifConfigAccessWait__(pGpu, pKernelBif, pTimeout); +} + NV_STATUS kbifGetPciConfigSpacePriMirror_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); NV_STATUS kbifGetPciConfigSpacePriMirror_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 *pMirrorBase, NvU32 *pMirrorSize); @@ -722,6 +860,10 @@ static inline NV_STATUS kbifPreOsGlobalErotGrantRequest_DISPATCH(struct OBJGPU * return pKernelBif->__kbifPreOsGlobalErotGrantRequest__(pGpu, pKernelBif); } +static inline NV_STATUS kbifStopSysMemRequests_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bStop) { + return NV_OK; +} + NV_STATUS kbifStopSysMemRequests_GM107(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bStop); NV_STATUS kbifStopSysMemRequests_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool bStop); @@ -818,6 +960,44 @@ static inline NV_STATUS kbifInit_DISPATCH(struct OBJGPU *pGpu, struct KernelBif return pKernelBif->__kbifInit__(pGpu, pKernelBif); } +NvU32 kbifGetValidEnginesToReset_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +NvU32 kbifGetValidEnginesToReset_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NvU32 kbifGetValidEnginesToReset_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifGetValidEnginesToReset__(pGpu, pKernelBif); +} + +NvU32 kbifGetValidDeviceEnginesToReset_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NvU32 kbifGetValidDeviceEnginesToReset_15a734(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return 0U; +} + +static inline NvU32 kbifGetValidDeviceEnginesToReset_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifGetValidDeviceEnginesToReset__(pGpu, pKernelBif); +} + +NvU32 kbifGetEccCounts_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NvU32 kbifGetEccCounts_4a4dee(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return 0; +} + +static inline NvU32 kbifGetEccCounts_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifGetEccCounts__(pGpu, pKernelBif); +} + +NV_STATUS kbifClearEccCounts_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +static inline NV_STATUS kbifClearEccCounts_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return NV_OK; +} + +static inline NV_STATUS kbifClearEccCounts_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + return pKernelBif->__kbifClearEccCounts__(pGpu, pKernelBif); +} + static inline NV_STATUS kbifStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { return pEngstate->__kbifStatePreLoad__(pGpu, pEngstate, arg0); } @@ -940,6 +1120,39 @@ static inline NvU32 kbifGetGpuLinkControlStatus(struct OBJGPU *pGpu, struct Kern #define kbifGetGpuLinkControlStatus(pGpu, pKernelBif) kbifGetGpuLinkControlStatus_IMPL(pGpu, pKernelBif) #endif //__nvoc_kernel_bif_h_disabled +NvU32 kbifGetGpuDevControlStatus_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NvU32 kbifGetGpuDevControlStatus(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return 0; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetGpuDevControlStatus(pGpu, pKernelBif) kbifGetGpuDevControlStatus_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + +NvU32 kbifGetGpuDevControlStatus2_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NvU32 kbifGetGpuDevControlStatus2(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return 0; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetGpuDevControlStatus2(pGpu, pKernelBif) kbifGetGpuDevControlStatus2_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + +NvU32 kbifGetGpuL1PmSubstatesCtrl1_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); + +#ifdef __nvoc_kernel_bif_h_disabled +static inline NvU32 kbifGetGpuL1PmSubstatesCtrl1(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { + NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!"); + return 0; +} +#else //__nvoc_kernel_bif_h_disabled +#define kbifGetGpuL1PmSubstatesCtrl1(pGpu, pKernelBif) kbifGetGpuL1PmSubstatesCtrl1_IMPL(pGpu, pKernelBif) +#endif //__nvoc_kernel_bif_h_disabled + NvBool kbifIsPciBusFamily_IMPL(struct KernelBif *pKernelBif); #ifdef __nvoc_kernel_bif_h_disabled diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.c b/src/nvidia/generated/g_kernel_ccu_api_nvoc.c index 14370bfc97..23f4046c56 100644 --- a/src/nvidia/generated/g_kernel_ccu_api_nvoc.c +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.c @@ -149,10 +149,6 @@ static void __nvoc_thunk_RmResource_kccuapiControl_Epilogue(struct KernelCcuApi rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kccuapiControlLookup(struct KernelCcuApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle(struct KernelCcuApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCcuApi_GpuResource.offset)); } @@ -177,6 +173,10 @@ static NvBool __nvoc_thunk_RsResource_kccuapiCanCopy(struct KernelCcuApi *pResou return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_kccuapiIsPartialUnmapSupported(struct KernelCcuApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_kccuapiPreDestruct(struct KernelCcuApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCcuApi_RsResource.offset)); } @@ -353,8 +353,6 @@ static void __nvoc_init_funcTable_KernelCcuApi_1(KernelCcuApi *pThis) { pThis->__kccuapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kccuapiControl_Epilogue; - pThis->__kccuapiControlLookup__ = &__nvoc_thunk_RsResource_kccuapiControlLookup; - pThis->__kccuapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kccuapiGetInternalObjectHandle; pThis->__kccuapiControl__ = &__nvoc_thunk_GpuResource_kccuapiControl; @@ -367,6 +365,8 @@ static void __nvoc_init_funcTable_KernelCcuApi_1(KernelCcuApi *pThis) { pThis->__kccuapiCanCopy__ = &__nvoc_thunk_RsResource_kccuapiCanCopy; + pThis->__kccuapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_kccuapiIsPartialUnmapSupported; + pThis->__kccuapiPreDestruct__ = &__nvoc_thunk_RsResource_kccuapiPreDestruct; pThis->__kccuapiIsDuplicate__ = &__nvoc_thunk_RsResource_kccuapiIsDuplicate; @@ -392,21 +392,26 @@ void __nvoc_init_KernelCcuApi(KernelCcuApi *pThis) { __nvoc_init_funcTable_KernelCcuApi(pThis); } -NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelCcuApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCcuApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelCcuApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCcuApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -421,16 +426,25 @@ NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi **ppThis, Dynamic *pParent, status = __nvoc_ctor_KernelCcuApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelCcuApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelCcuApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelCcuApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h index 9fbcbfbcac..edc07fd650 100644 --- a/src/nvidia/generated/g_kernel_ccu_api_nvoc.h +++ b/src/nvidia/generated/g_kernel_ccu_api_nvoc.h @@ -43,11 +43,16 @@ extern "C" { * * ****************************************************************************/ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CCU_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelCcuApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -75,13 +80,13 @@ struct KernelCcuApi { NV_STATUS (*__kccuapiInternalControlForward__)(struct KernelCcuApi *, NvU32, void *, NvU32); NV_STATUS (*__kccuapiUnmapFrom__)(struct KernelCcuApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kccuapiControl_Epilogue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kccuapiControlLookup__)(struct KernelCcuApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__kccuapiGetInternalObjectHandle__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiControl__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kccuapiGetMemInterMapParams__)(struct KernelCcuApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__kccuapiControlFilter__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kccuapiControlSerialization_Prologue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kccuapiCanCopy__)(struct KernelCcuApi *); + NvBool (*__kccuapiIsPartialUnmapSupported__)(struct KernelCcuApi *); void (*__kccuapiPreDestruct__)(struct KernelCcuApi *); NV_STATUS (*__kccuapiIsDuplicate__)(struct KernelCcuApi *, NvHandle, NvBool *); void (*__kccuapiControlSerialization_Epilogue__)(struct KernelCcuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -134,13 +139,13 @@ NV_STATUS __nvoc_objCreate_KernelCcuApi(KernelCcuApi**, Dynamic*, NvU32, struct #define kccuapiInternalControlForward(pGpuResource, command, pParams, size) kccuapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kccuapiUnmapFrom(pResource, pParams) kccuapiUnmapFrom_DISPATCH(pResource, pParams) #define kccuapiControl_Epilogue(pResource, pCallContext, pParams) kccuapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kccuapiControlLookup(pResource, pParams, ppEntry) kccuapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kccuapiGetInternalObjectHandle(pGpuResource) kccuapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define kccuapiControl(pGpuResource, pCallContext, pParams) kccuapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define kccuapiGetMemInterMapParams(pRmResource, pParams) kccuapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define kccuapiControlFilter(pResource, pCallContext, pParams) kccuapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kccuapiControlSerialization_Prologue(pResource, pCallContext, pParams) kccuapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kccuapiCanCopy(pResource) kccuapiCanCopy_DISPATCH(pResource) +#define kccuapiIsPartialUnmapSupported(pResource) kccuapiIsPartialUnmapSupported_DISPATCH(pResource) #define kccuapiPreDestruct(pResource) kccuapiPreDestruct_DISPATCH(pResource) #define kccuapiIsDuplicate(pResource, hMemory, pDuplicate) kccuapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kccuapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kccuapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -233,10 +238,6 @@ static inline void kccuapiControl_Epilogue_DISPATCH(struct KernelCcuApi *pResour pResource->__kccuapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS kccuapiControlLookup_DISPATCH(struct KernelCcuApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kccuapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle kccuapiGetInternalObjectHandle_DISPATCH(struct KernelCcuApi *pGpuResource) { return pGpuResource->__kccuapiGetInternalObjectHandle__(pGpuResource); } @@ -261,6 +262,10 @@ static inline NvBool kccuapiCanCopy_DISPATCH(struct KernelCcuApi *pResource) { return pResource->__kccuapiCanCopy__(pResource); } +static inline NvBool kccuapiIsPartialUnmapSupported_DISPATCH(struct KernelCcuApi *pResource) { + return pResource->__kccuapiIsPartialUnmapSupported__(pResource); +} + static inline void kccuapiPreDestruct_DISPATCH(struct KernelCcuApi *pResource) { pResource->__kccuapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.c b/src/nvidia/generated/g_kernel_ccu_nvoc.c index df0a042fb4..32f63b6e99 100644 --- a/src/nvidia/generated/g_kernel_ccu_nvoc.c +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.c @@ -130,7 +130,6 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelCcu = void __nvoc_dtor_OBJENGSTATE(OBJENGSTATE*); void __nvoc_dtor_KernelCcu(KernelCcu *pThis) { - __nvoc_kccuDestruct(pThis); __nvoc_dtor_OBJENGSTATE(&pThis->__nvoc_base_OBJENGSTATE); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -146,6 +145,16 @@ void __nvoc_init_dataField_KernelCcu(KernelCcu *pThis, RmHalspecOwner *pRmhalspe PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); + + // NVOC Property Hal field -- PDB_PROP_KCCU_IS_MISSING + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->setProperty(pThis, PDB_PROP_KCCU_IS_MISSING, ((NvBool)(0 == 0))); + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->setProperty(pThis, PDB_PROP_KCCU_IS_MISSING, ((NvBool)(0 != 0))); + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -174,7 +183,6 @@ static void __nvoc_init_funcTable_KernelCcu_1(KernelCcu *pThis, RmHalspecOwner * PORT_UNREFERENCED_VARIABLE(chipHal); PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); - // Hal function -- kccuConstructEngine pThis->__kccuConstructEngine__ = &kccuConstructEngine_IMPL; pThis->__kccuStateLoad__ = &kccuStateLoad_IMPL; @@ -234,23 +242,31 @@ void __nvoc_init_KernelCcu(KernelCcu *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelCcu(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelCcu *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCcu), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelCcu)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCcu); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -268,16 +284,25 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_KernelCcu(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelCcu_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelCcu_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelCcu)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_ccu_nvoc.h b/src/nvidia/generated/g_kernel_ccu_nvoc.h index b918bf7ab8..f3f3da5be8 100644 --- a/src/nvidia/generated/g_kernel_ccu_nvoc.h +++ b/src/nvidia/generated/g_kernel_ccu_nvoc.h @@ -43,6 +43,7 @@ extern "C" { #include "gpu/gpu.h" #include "gpu/eng_state.h" +#include "gpu_mgr/gpu_mgr.h" // GPUMGR_MAX_GPU_INSTANCES #include "rmapi/rmapi.h" #include "objtmr.h" #include "ctrl/ctrlcbca.h" @@ -102,11 +103,16 @@ typedef struct SHARED_BUFFER_MAP_INFO *pKernelMapInfo; // Shared buffer kernel map info } CCU_SHRBUF; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CCU_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelCcu { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -165,7 +171,6 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu**, Dynamic*, NvU32); __nvoc_objCreate_KernelCcu((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kccuConstructEngine(pGpu, pKernelCcu, engDesc) kccuConstructEngine_DISPATCH(pGpu, pKernelCcu, engDesc) -#define kccuConstructEngine_HAL(pGpu, pKernelCcu, engDesc) kccuConstructEngine_DISPATCH(pGpu, pKernelCcu, engDesc) #define kccuStateLoad(arg0, arg1, flags) kccuStateLoad_DISPATCH(arg0, arg1, flags) #define kccuStateUnload(arg0, arg1, flags) kccuStateUnload_DISPATCH(arg0, arg1, flags) #define kccuMigShrBufHandler(arg0, arg1, bMigEnabled) kccuMigShrBufHandler_DISPATCH(arg0, arg1, bMigEnabled) @@ -181,10 +186,6 @@ NV_STATUS __nvoc_objCreate_KernelCcu(KernelCcu**, Dynamic*, NvU32); #define kccuStatePreInitUnlocked(pGpu, pEngstate) kccuStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kccuStatePostLoad(pGpu, pEngstate, arg0) kccuStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kccuIsPresent(pGpu, pEngstate) kccuIsPresent_DISPATCH(pGpu, pEngstate) -void kccuDestruct_IMPL(struct KernelCcu *arg0); - - -#define __nvoc_kccuDestruct(arg0) kccuDestruct_IMPL(arg0) NV_STATUS kccuConstructEngine_IMPL(OBJGPU *pGpu, struct KernelCcu *pKernelCcu, ENGDESCRIPTOR engDesc); static inline NV_STATUS kccuConstructEngine_DISPATCH(OBJGPU *pGpu, struct KernelCcu *pKernelCcu, ENGDESCRIPTOR engDesc) { diff --git a/src/nvidia/generated/g_kernel_ce_context_nvoc.c b/src/nvidia/generated/g_kernel_ce_context_nvoc.c index 1e161dfcfd..c24f103c05 100644 --- a/src/nvidia/generated/g_kernel_ce_context_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_context_nvoc.c @@ -172,10 +172,6 @@ static void __nvoc_thunk_RmResource_kcectxControl_Epilogue(struct KernelCeContex rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kcectxControlLookup(struct KernelCeContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_ChannelDescendant_kcectxGetSwMethods(struct KernelCeContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_KernelCeContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_kcectxCanCopy(struct KernelCeContext *pRes return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_kcectxIsPartialUnmapSupported(struct KernelCeContext *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_kcectxPreDestruct(struct KernelCeContext *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCeContext_RsResource.offset)); } @@ -313,8 +313,6 @@ static void __nvoc_init_funcTable_KernelCeContext_1(KernelCeContext *pThis) { pThis->__kcectxControl_Epilogue__ = &__nvoc_thunk_RmResource_kcectxControl_Epilogue; - pThis->__kcectxControlLookup__ = &__nvoc_thunk_RsResource_kcectxControlLookup; - pThis->__kcectxGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_kcectxGetSwMethods; pThis->__kcectxGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kcectxGetInternalObjectHandle; @@ -337,6 +335,8 @@ static void __nvoc_init_funcTable_KernelCeContext_1(KernelCeContext *pThis) { pThis->__kcectxCanCopy__ = &__nvoc_thunk_RsResource_kcectxCanCopy; + pThis->__kcectxIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_kcectxIsPartialUnmapSupported; + pThis->__kcectxPreDestruct__ = &__nvoc_thunk_RsResource_kcectxPreDestruct; pThis->__kcectxIsDuplicate__ = &__nvoc_thunk_RsResource_kcectxIsDuplicate; @@ -371,23 +371,31 @@ void __nvoc_init_KernelCeContext(KernelCeContext *pThis, RmHalspecOwner *pRmhals __nvoc_init_funcTable_KernelCeContext(pThis); } -NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelCeContext *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCeContext), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelCeContext)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCeContext); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -405,16 +413,25 @@ NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext **ppThis, Dynamic *pP status = __nvoc_ctor_KernelCeContext(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelCeContext_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelCeContext_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelCeContext)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_ce_context_nvoc.h b/src/nvidia/generated/g_kernel_ce_context_nvoc.h index 5b33c83b88..983ce7dc91 100644 --- a/src/nvidia/generated/g_kernel_ce_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_context_nvoc.h @@ -45,11 +45,16 @@ ENGDESCRIPTOR kceGetEngineDescFromAllocParams(struct OBJGPU *pGpu, NvU32 externa /*! * RM internal class representing XXX_DMA_COPY_A */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CE_CONTEXT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelCeContext { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -75,7 +80,6 @@ struct KernelCeContext { NV_STATUS (*__kcectxInternalControlForward__)(struct KernelCeContext *, NvU32, void *, NvU32); NV_STATUS (*__kcectxUnmapFrom__)(struct KernelCeContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kcectxControl_Epilogue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kcectxControlLookup__)(struct KernelCeContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kcectxGetSwMethods__)(struct KernelCeContext *, const METHOD **, NvU32 *); NvHandle (*__kcectxGetInternalObjectHandle__)(struct KernelCeContext *); NV_STATUS (*__kcectxControl__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -87,6 +91,7 @@ struct KernelCeContext { NV_STATUS (*__kcectxUnregisterEvent__)(struct KernelCeContext *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__kcectxControlSerialization_Prologue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kcectxCanCopy__)(struct KernelCeContext *); + NvBool (*__kcectxIsPartialUnmapSupported__)(struct KernelCeContext *); void (*__kcectxPreDestruct__)(struct KernelCeContext *); NV_STATUS (*__kcectxIsDuplicate__)(struct KernelCeContext *, NvHandle, NvBool *); void (*__kcectxControlSerialization_Epilogue__)(struct KernelCeContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -137,7 +142,6 @@ NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext**, Dynamic*, NvU32, C #define kcectxInternalControlForward(pGpuResource, command, pParams, size) kcectxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kcectxUnmapFrom(pResource, pParams) kcectxUnmapFrom_DISPATCH(pResource, pParams) #define kcectxControl_Epilogue(pResource, pCallContext, pParams) kcectxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kcectxControlLookup(pResource, pParams, ppEntry) kcectxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kcectxGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) kcectxGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) #define kcectxGetInternalObjectHandle(pGpuResource) kcectxGetInternalObjectHandle_DISPATCH(pGpuResource) #define kcectxControl(pGpuResource, pCallContext, pParams) kcectxControl_DISPATCH(pGpuResource, pCallContext, pParams) @@ -149,6 +153,7 @@ NV_STATUS __nvoc_objCreate_KernelCeContext(KernelCeContext**, Dynamic*, NvU32, C #define kcectxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kcectxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define kcectxControlSerialization_Prologue(pResource, pCallContext, pParams) kcectxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kcectxCanCopy(pResource) kcectxCanCopy_DISPATCH(pResource) +#define kcectxIsPartialUnmapSupported(pResource) kcectxIsPartialUnmapSupported_DISPATCH(pResource) #define kcectxPreDestruct(pResource) kcectxPreDestruct_DISPATCH(pResource) #define kcectxIsDuplicate(pResource, hMemory, pDuplicate) kcectxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kcectxControlSerialization_Epilogue(pResource, pCallContext, pParams) kcectxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -208,10 +213,6 @@ static inline void kcectxControl_Epilogue_DISPATCH(struct KernelCeContext *pReso pResource->__kcectxControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS kcectxControlLookup_DISPATCH(struct KernelCeContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kcectxControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS kcectxGetSwMethods_DISPATCH(struct KernelCeContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__kcectxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -256,6 +257,10 @@ static inline NvBool kcectxCanCopy_DISPATCH(struct KernelCeContext *pResource) { return pResource->__kcectxCanCopy__(pResource); } +static inline NvBool kcectxIsPartialUnmapSupported_DISPATCH(struct KernelCeContext *pResource) { + return pResource->__kcectxIsPartialUnmapSupported__(pResource); +} + static inline void kcectxPreDestruct_DISPATCH(struct KernelCeContext *pResource) { pResource->__kcectxPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.c b/src/nvidia/generated/g_kernel_ce_nvoc.c index e42f5c642d..e5144c5ec5 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.c +++ b/src/nvidia/generated/g_kernel_ce_nvoc.c @@ -91,7 +91,7 @@ static NV_STATUS __nvoc_thunk_KernelCE_engstateStateUnload(OBJGPU *pGpu, struct return kceStateUnload(pGpu, (struct KernelCE *)(((unsigned char *)pKCe) - __nvoc_rtti_KernelCE_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[168]) { +static void __nvoc_thunk_KernelCE_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[171]) { kceRegisterIntrService(arg0, (struct KernelCE *)(((unsigned char *)arg1) - __nvoc_rtti_KernelCE_IntrService.offset), arg2); } @@ -221,6 +221,16 @@ static void __nvoc_init_funcTable_KernelCE_1(KernelCE *pThis, RmHalspecOwner *pR pThis->__kceServiceNotificationInterrupt__ = &kceServiceNotificationInterrupt_IMPL; + // Hal function -- kceGetP2PCes + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kceGetP2PCes__ = &kceGetP2PCes_GH100; + } + else + { + pThis->__kceGetP2PCes__ = &kceGetP2PCes_GV100; + } + // Hal function -- kceGetNvlinkAutoConfigCeValues if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -475,23 +485,31 @@ void __nvoc_init_KernelCE(KernelCE *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelCE(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelCE *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCE), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelCE)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCE); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -509,16 +527,25 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_KernelCE(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelCE_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelCE_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelCE)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.h b/src/nvidia/generated/g_kernel_ce_nvoc.h index d0d09f1879..577568019d 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_nvoc.h @@ -35,7 +35,6 @@ extern "C" { #define KERNEL_CE_H #include "core/core.h" -#include "core/info_block.h" #include "ctrl/ctrl2080/ctrl2080ce.h" #include "gpu/eng_state.h" #include "gpu/gpu_halspec.h" @@ -43,6 +42,8 @@ extern "C" { #include "kernel/gpu/intr/intr_service.h" #include "gpu/ce/kernel_ce_shared.h" +typedef struct NVLINK_TOPOLOGY_PARAMS NVLINK_TOPOLOGY_PARAMS; + #define MAX_CE_CNT 18 /* @@ -94,11 +95,16 @@ typedef struct NVLINK_CE_AUTO_CONFIG_TABLE // This class provides Kernel-RM interface and state tracking for Copy Engine. // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelCE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -113,6 +119,7 @@ struct KernelCE { NV_STATUS (*__kceStateUnload__)(OBJGPU *, struct KernelCE *, NvU32); void (*__kceRegisterIntrService__)(OBJGPU *, struct KernelCE *, IntrServiceRecord *); NV_STATUS (*__kceServiceNotificationInterrupt__)(OBJGPU *, struct KernelCE *, IntrServiceServiceNotificationInterruptArguments *); + NV_STATUS (*__kceGetP2PCes__)(struct KernelCE *, OBJGPU *, NvU32, NvU32 *); NV_STATUS (*__kceGetNvlinkAutoConfigCeValues__)(OBJGPU *, struct KernelCE *, NvU32 *, NvU32 *, NvU32 *); NvBool (*__kceGetNvlinkMaxTopoForTable__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, void *, NvU32, NvU32 *); NvBool (*__kceIsCurrentMaxTopology__)(OBJGPU *, struct KernelCE *, struct NVLINK_TOPOLOGY_PARAMS *, NvU32 *, NvU32 *); @@ -190,6 +197,8 @@ NV_STATUS __nvoc_objCreate_KernelCE(KernelCE**, Dynamic*, NvU32); #define kceStateUnload_HAL(pGpu, pKCe, flags) kceStateUnload_DISPATCH(pGpu, pKCe, flags) #define kceRegisterIntrService(arg0, arg1, arg2) kceRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define kceServiceNotificationInterrupt(arg0, arg1, arg2) kceServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) +#define kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_DISPATCH(arg0, pGpu, gpuMask, nvlinkP2PCeMask) +#define kceGetP2PCes_HAL(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_DISPATCH(arg0, pGpu, gpuMask, nvlinkP2PCeMask) #define kceGetNvlinkAutoConfigCeValues(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) #define kceGetNvlinkAutoConfigCeValues_HAL(pGpu, pKCe, arg0, arg1, arg2) kceGetNvlinkAutoConfigCeValues_DISPATCH(pGpu, pKCe, arg0, arg1, arg2) #define kceGetNvlinkMaxTopoForTable(pGpu, pKCe, arg0, arg1, arg2, arg3) kceGetNvlinkMaxTopoForTable_DISPATCH(pGpu, pKCe, arg0, arg1, arg2, arg3) @@ -305,20 +314,6 @@ static inline NvBool kceIsCeNvlinkP2P(OBJGPU *pGpu, struct KernelCE *pKCe) { #define kceIsCeNvlinkP2P_HAL(pGpu, pKCe) kceIsCeNvlinkP2P(pGpu, pKCe) -NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); - - -#ifdef __nvoc_kernel_ce_h_disabled -static inline NV_STATUS kceGetP2PCes(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { - NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_ce_h_disabled -#define kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes_GV100(arg0, pGpu, gpuMask, nvlinkP2PCeMask) -#endif //__nvoc_kernel_ce_h_disabled - -#define kceGetP2PCes_HAL(arg0, pGpu, gpuMask, nvlinkP2PCeMask) kceGetP2PCes(arg0, pGpu, gpuMask, nvlinkP2PCeMask) - void kceGetSysmemRWLCEs_GV100(struct KernelCE *arg0, NvU32 *rd, NvU32 *wr); @@ -385,9 +380,9 @@ static inline NV_STATUS kceStateUnload_DISPATCH(OBJGPU *pGpu, struct KernelCE *p return pKCe->__kceStateUnload__(pGpu, pKCe, flags); } -void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[168]); +void kceRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[171]); -static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[168]) { +static inline void kceRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelCE *arg1, IntrServiceRecord arg2[171]) { arg1->__kceRegisterIntrService__(arg0, arg1, arg2); } @@ -397,6 +392,14 @@ static inline NV_STATUS kceServiceNotificationInterrupt_DISPATCH(OBJGPU *arg0, s return arg1->__kceServiceNotificationInterrupt__(arg0, arg1, arg2); } +NV_STATUS kceGetP2PCes_GV100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); + +NV_STATUS kceGetP2PCes_GH100(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask); + +static inline NV_STATUS kceGetP2PCes_DISPATCH(struct KernelCE *arg0, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) { + return arg0->__kceGetP2PCes__(arg0, pGpu, gpuMask, nvlinkP2PCeMask); +} + NV_STATUS kceGetNvlinkAutoConfigCeValues_TU102(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); NV_STATUS kceGetNvlinkAutoConfigCeValues_GA100(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *arg0, NvU32 *arg1, NvU32 *arg2); @@ -639,6 +642,16 @@ NV_STATUS kceGetFaultMethodBufferSize_IMPL(OBJGPU *pGpu, NvU32 *size); NV_STATUS kceGetAvailableHubPceMask_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, NVLINK_TOPOLOGY_PARAMS *pTopoParams); #define kceGetAvailableHubPceMask(pGpu, pKCe, pTopoParams) kceGetAvailableHubPceMask_IMPL(pGpu, pKCe, pTopoParams) +void kceGetAvailableGrceLceMask_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *grceLceMask); + +#ifdef __nvoc_kernel_ce_h_disabled +static inline void kceGetAvailableGrceLceMask(OBJGPU *pGpu, struct KernelCE *pKCe, NvU32 *grceLceMask) { + NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); +} +#else //__nvoc_kernel_ce_h_disabled +#define kceGetAvailableGrceLceMask(pGpu, pKCe, grceLceMask) kceGetAvailableGrceLceMask_IMPL(pGpu, pKCe, grceLceMask) +#endif //__nvoc_kernel_ce_h_disabled + void kceGetNvlinkCaps_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, NvU8 *pKCeCaps); #ifdef __nvoc_kernel_ce_h_disabled diff --git a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c index 2e509deb1c..d2d12bba0f 100644 --- a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.c @@ -145,10 +145,6 @@ static void __nvoc_thunk_RmResource_kchangrpapiControl_Epilogue(struct KernelCha rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kchangrpapiControlLookup(struct KernelChannelGroupApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle(struct KernelChannelGroupApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannelGroupApi_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RmResource_kchangrpapiControlSerialization_Prologu return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_kchangrpapiIsPartialUnmapSupported(struct KernelChannelGroupApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_kchangrpapiPreDestruct(struct KernelChannelGroupApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannelGroupApi_RsResource.offset)); } @@ -577,8 +577,6 @@ static void __nvoc_init_funcTable_KernelChannelGroupApi_1(KernelChannelGroupApi pThis->__kchangrpapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kchangrpapiControl_Epilogue; - pThis->__kchangrpapiControlLookup__ = &__nvoc_thunk_RsResource_kchangrpapiControlLookup; - pThis->__kchangrpapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kchangrpapiGetInternalObjectHandle; pThis->__kchangrpapiUnmap__ = &__nvoc_thunk_GpuResource_kchangrpapiUnmap; @@ -591,6 +589,8 @@ static void __nvoc_init_funcTable_KernelChannelGroupApi_1(KernelChannelGroupApi pThis->__kchangrpapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kchangrpapiControlSerialization_Prologue; + pThis->__kchangrpapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_kchangrpapiIsPartialUnmapSupported; + pThis->__kchangrpapiPreDestruct__ = &__nvoc_thunk_RsResource_kchangrpapiPreDestruct; pThis->__kchangrpapiIsDuplicate__ = &__nvoc_thunk_RsResource_kchangrpapiIsDuplicate; @@ -618,21 +618,26 @@ void __nvoc_init_KernelChannelGroupApi(KernelChannelGroupApi *pThis) { __nvoc_init_funcTable_KernelChannelGroupApi(pThis); } -NV_STATUS __nvoc_objCreate_KernelChannelGroupApi(KernelChannelGroupApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelChannelGroupApi(KernelChannelGroupApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelChannelGroupApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannelGroupApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelChannelGroupApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannelGroupApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -647,16 +652,25 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroupApi(KernelChannelGroupApi **ppThis, status = __nvoc_ctor_KernelChannelGroupApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelChannelGroupApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelChannelGroupApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelChannelGroupApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h index c78fa4f285..8953a6aa41 100644 --- a/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_group_api_nvoc.h @@ -69,11 +69,16 @@ typedef struct KernelChannelGroup KernelChannelGroup; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CHANNEL_GROUP_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelChannelGroupApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -113,13 +118,13 @@ struct KernelChannelGroupApi { NV_STATUS (*__kchangrpapiInternalControlForward__)(struct KernelChannelGroupApi *, NvU32, void *, NvU32); NV_STATUS (*__kchangrpapiUnmapFrom__)(struct KernelChannelGroupApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kchangrpapiControl_Epilogue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kchangrpapiControlLookup__)(struct KernelChannelGroupApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__kchangrpapiGetInternalObjectHandle__)(struct KernelChannelGroupApi *); NV_STATUS (*__kchangrpapiUnmap__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__kchangrpapiGetMemInterMapParams__)(struct KernelChannelGroupApi *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__kchangrpapiGetMemoryMappingDescriptor__)(struct KernelChannelGroupApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kchangrpapiControlFilter__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchangrpapiControlSerialization_Prologue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__kchangrpapiIsPartialUnmapSupported__)(struct KernelChannelGroupApi *); void (*__kchangrpapiPreDestruct__)(struct KernelChannelGroupApi *); NV_STATUS (*__kchangrpapiIsDuplicate__)(struct KernelChannelGroupApi *, NvHandle, NvBool *); void (*__kchangrpapiControlSerialization_Epilogue__)(struct KernelChannelGroupApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -192,13 +197,13 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroupApi(KernelChannelGroupApi**, Dynami #define kchangrpapiInternalControlForward(pGpuResource, command, pParams, size) kchangrpapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kchangrpapiUnmapFrom(pResource, pParams) kchangrpapiUnmapFrom_DISPATCH(pResource, pParams) #define kchangrpapiControl_Epilogue(pResource, pCallContext, pParams) kchangrpapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kchangrpapiControlLookup(pResource, pParams, ppEntry) kchangrpapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kchangrpapiGetInternalObjectHandle(pGpuResource) kchangrpapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define kchangrpapiUnmap(pGpuResource, pCallContext, pCpuMapping) kchangrpapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define kchangrpapiGetMemInterMapParams(pRmResource, pParams) kchangrpapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define kchangrpapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kchangrpapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define kchangrpapiControlFilter(pResource, pCallContext, pParams) kchangrpapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kchangrpapiControlSerialization_Prologue(pResource, pCallContext, pParams) kchangrpapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kchangrpapiIsPartialUnmapSupported(pResource) kchangrpapiIsPartialUnmapSupported_DISPATCH(pResource) #define kchangrpapiPreDestruct(pResource) kchangrpapiPreDestruct_DISPATCH(pResource) #define kchangrpapiIsDuplicate(pResource, hMemory, pDuplicate) kchangrpapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kchangrpapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kchangrpapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -370,10 +375,6 @@ static inline void kchangrpapiControl_Epilogue_DISPATCH(struct KernelChannelGrou pResource->__kchangrpapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS kchangrpapiControlLookup_DISPATCH(struct KernelChannelGroupApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kchangrpapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle kchangrpapiGetInternalObjectHandle_DISPATCH(struct KernelChannelGroupApi *pGpuResource) { return pGpuResource->__kchangrpapiGetInternalObjectHandle__(pGpuResource); } @@ -398,6 +399,10 @@ static inline NV_STATUS kchangrpapiControlSerialization_Prologue_DISPATCH(struct return pResource->__kchangrpapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool kchangrpapiIsPartialUnmapSupported_DISPATCH(struct KernelChannelGroupApi *pResource) { + return pResource->__kchangrpapiIsPartialUnmapSupported__(pResource); +} + static inline void kchangrpapiPreDestruct_DISPATCH(struct KernelChannelGroupApi *pResource) { pResource->__kchangrpapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_channel_group_nvoc.c b/src/nvidia/generated/g_kernel_channel_group_nvoc.c index 82d86f7213..37fed4a189 100644 --- a/src/nvidia/generated/g_kernel_channel_group_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_group_nvoc.c @@ -137,23 +137,31 @@ void __nvoc_init_KernelChannelGroup(KernelChannelGroup *pThis, RmHalspecOwner *p __nvoc_init_funcTable_KernelChannelGroup(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelChannelGroup(KernelChannelGroup **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelChannelGroup(KernelChannelGroup **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelChannelGroup *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannelGroup), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelChannelGroup)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannelGroup); pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); @@ -171,16 +179,25 @@ NV_STATUS __nvoc_objCreate_KernelChannelGroup(KernelChannelGroup **ppThis, Dynam status = __nvoc_ctor_KernelChannelGroup(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelChannelGroup_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelChannelGroup_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelChannelGroup)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_channel_group_nvoc.h b/src/nvidia/generated/g_kernel_channel_group_nvoc.h index 4332b4040a..2886b9b723 100644 --- a/src/nvidia/generated/g_kernel_channel_group_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_group_nvoc.h @@ -109,11 +109,16 @@ typedef struct _HW_ENG_FAULT_METHOD_BUFFER * Instances of this class are ref-counted and will be kept alive until * all TSG copies have been freed. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CHANNEL_GROUP_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelChannelGroup { const struct NVOC_RTTI *__nvoc_rtti; struct RsShared __nvoc_base_RsShared; diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.c b/src/nvidia/generated/g_kernel_channel_nvoc.c index c4280f8373..7f2730c718 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_nvoc.c @@ -175,10 +175,6 @@ static void __nvoc_thunk_RmResource_kchannelControl_Epilogue(struct KernelChanne rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kchannelControlLookup(struct KernelChannel *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_kchannelGetInternalObjectHandle(struct KernelChannel *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelChannel_GpuResource.offset)); } @@ -207,6 +203,10 @@ static NvBool __nvoc_thunk_RsResource_kchannelCanCopy(struct KernelChannel *pRes return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_kchannelIsPartialUnmapSupported(struct KernelChannel *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_kchannelPreDestruct(struct KernelChannel *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelChannel_RsResource.offset)); } @@ -298,12 +298,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [4] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdResetIsolatedChannel_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) - /*flags=*/ 0x2210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, /*accessRight=*/0x0u, /*methodId=*/ 0x506f0105u, /*paramSize=*/ sizeof(NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS), @@ -313,6 +313,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdInternalResetIsolatedChannel_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + /*flags=*/ 0x2610u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x506f0106u, + /*paramSize=*/ sizeof(NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelChannel.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kchannelCtrlCmdInternalResetIsolatedChannel" +#endif + }, + { /* [6] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -327,7 +342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineid" #endif }, - { /* [6] */ + { /* [7] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -342,7 +357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannel" #endif }, - { /* [7] */ + { /* [8] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -357,7 +372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetDeferRCState" #endif }, - { /* [8] */ + { /* [9] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -372,7 +387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetMmuFaultInfo" #endif }, - { /* [9] */ + { /* [10] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -387,7 +402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdEventSetNotification" #endif }, - { /* [10] */ + { /* [11] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -402,7 +417,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineidA06F" #endif }, - { /* [11] */ + { /* [12] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -417,7 +432,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannelA06F" #endif }, - { /* [12] */ + { /* [13] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -432,7 +447,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpFifoSchedule" #endif }, - { /* [13] */ + { /* [14] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -447,7 +462,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdBind" #endif }, - { /* [14] */ + { /* [15] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -462,7 +477,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetMmuFaultInfoA06F" #endif }, - { /* [15] */ + { /* [16] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -477,7 +492,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdSetErrorNotifier" #endif }, - { /* [16] */ + { /* [17] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x110u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -492,7 +507,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdSetInterleaveLevel" #endif }, - { /* [17] */ + { /* [18] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -507,7 +522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdRestartRunlist" #endif }, - { /* [18] */ + { /* [19] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -522,7 +537,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdStopChannel" #endif }, - { /* [19] */ + { /* [20] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -537,7 +552,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineidA16F" #endif }, - { /* [20] */ + { /* [21] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -552,7 +567,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannelA16F" #endif }, - { /* [21] */ + { /* [22] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -567,7 +582,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpFifoScheduleA16F" #endif }, - { /* [22] */ + { /* [23] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -582,7 +597,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineidA26F" #endif }, - { /* [23] */ + { /* [24] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -597,7 +612,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannelA26F" #endif }, - { /* [24] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -612,7 +627,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelFCtrlCmdGpFifoScheduleA26F" #endif }, - { /* [25] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -627,7 +642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineidB06F" #endif }, - { /* [26] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -642,7 +657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannelB06F" #endif }, - { /* [27] */ + { /* [28] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -657,7 +672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpFifoScheduleB06F" #endif }, - { /* [28] */ + { /* [29] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -672,7 +687,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdBindB06F" #endif }, - { /* [29] */ + { /* [30] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -687,7 +702,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetEngineCtxSize" #endif }, - { /* [30] */ + { /* [31] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -702,7 +717,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetEngineCtxData" #endif }, - { /* [31] */ + { /* [32] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x42204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -717,7 +732,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdMigrateEngineCtxData" #endif }, - { /* [32] */ + { /* [33] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -732,7 +747,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetEngineCtxState" #endif }, - { /* [33] */ + { /* [34] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -747,7 +762,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetChannelHwState" #endif }, - { /* [34] */ + { /* [35] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -762,7 +777,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdSetChannelHwState" #endif }, - { /* [35] */ + { /* [36] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -777,7 +792,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdSaveEngineCtxData" #endif }, - { /* [36] */ + { /* [37] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -792,7 +807,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdRestoreEngineCtxData" #endif }, - { /* [37] */ + { /* [38] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -807,7 +822,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineidC06F" #endif }, - { /* [38] */ + { /* [39] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -822,7 +837,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannelC06F" #endif }, - { /* [39] */ + { /* [40] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -837,7 +852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpFifoScheduleC06F" #endif }, - { /* [40] */ + { /* [41] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -852,7 +867,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdBindC06F" #endif }, - { /* [41] */ + { /* [42] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -867,7 +882,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetClassEngineidC36F" #endif }, - { /* [42] */ + { /* [43] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -882,7 +897,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdResetChannelC36F" #endif }, - { /* [43] */ + { /* [44] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -897,7 +912,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpFifoScheduleC36F" #endif }, - { /* [44] */ + { /* [45] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -912,7 +927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdBindC36F" #endif }, - { /* [45] */ + { /* [46] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -927,7 +942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpfifoGetWorkSubmitToken" #endif }, - { /* [46] */ + { /* [47] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -942,7 +957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpfifoUpdateFaultMethodBuffer" #endif }, - { /* [47] */ + { /* [48] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -957,7 +972,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGpfifoSetWorkSubmitTokenNotifIndex" #endif }, - { /* [48] */ + { /* [49] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -972,7 +987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh /*func=*/ "kchannelCtrlCmdGetKmb" #endif }, - { /* [49] */ + { /* [50] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -992,7 +1007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelChannel = { - /*numEntries=*/ 50, + /*numEntries=*/ 51, /*pExportEntries=*/ __nvoc_exported_method_def_KernelChannel }; @@ -1088,10 +1103,14 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelIsUserdAddrSizeValid__ = &kchannelIsUserdAddrSizeValid_GA100; } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__kchannelCtrlCmdResetIsolatedChannel__ = &kchannelCtrlCmdResetIsolatedChannel_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) + pThis->__kchannelCtrlCmdInternalResetIsolatedChannel__ = &kchannelCtrlCmdInternalResetIsolatedChannel_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__kchannelCtrlCmdGetClassEngineid__ = &kchannelCtrlCmdGetClassEngineid_IMPL; #endif @@ -1265,10 +1284,24 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe #endif // Hal function -- kchannelCtrlCmdGetKmb - pThis->__kchannelCtrlCmdGetKmb__ = &kchannelCtrlCmdGetKmb_KERNEL; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kchannelCtrlCmdGetKmb__ = &kchannelCtrlCmdGetKmb_46f6a7; + } + else + { + pThis->__kchannelCtrlCmdGetKmb__ = &kchannelCtrlCmdGetKmb_KERNEL; + } // Hal function -- kchannelCtrlRotateSecureChannelIv - pThis->__kchannelCtrlRotateSecureChannelIv__ = &kchannelCtrlRotateSecureChannelIv_KERNEL; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kchannelCtrlRotateSecureChannelIv__ = &kchannelCtrlRotateSecureChannelIv_46f6a7; + } + else + { + pThis->__kchannelCtrlRotateSecureChannelIv__ = &kchannelCtrlRotateSecureChannelIv_KERNEL; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__kchannelCtrlGetTpcPartitionMode__ = &kchannelCtrlGetTpcPartitionMode_a094e1; @@ -1286,6 +1319,16 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCtrlProgramVidmemPromote__ = &kchannelCtrlProgramVidmemPromote_a094e1; #endif + // Hal function -- kchannelRetrieveKmb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kchannelRetrieveKmb__ = &kchannelRetrieveKmb_56cd7a; + } + else + { + pThis->__kchannelRetrieveKmb__ = &kchannelRetrieveKmb_KERNEL; + } + pThis->__nvoc_base_GpuResource.__gpuresMap__ = &__nvoc_thunk_KernelChannel_gpuresMap; pThis->__nvoc_base_GpuResource.__gpuresUnmap__ = &__nvoc_thunk_KernelChannel_gpuresUnmap; @@ -1318,8 +1361,6 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelControl_Epilogue__ = &__nvoc_thunk_RmResource_kchannelControl_Epilogue; - pThis->__kchannelControlLookup__ = &__nvoc_thunk_RsResource_kchannelControlLookup; - pThis->__kchannelGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kchannelGetInternalObjectHandle; pThis->__kchannelControl__ = &__nvoc_thunk_GpuResource_kchannelControl; @@ -1334,6 +1375,8 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCanCopy__ = &__nvoc_thunk_RsResource_kchannelCanCopy; + pThis->__kchannelIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_kchannelIsPartialUnmapSupported; + pThis->__kchannelPreDestruct__ = &__nvoc_thunk_RsResource_kchannelPreDestruct; pThis->__kchannelIsDuplicate__ = &__nvoc_thunk_RsResource_kchannelIsDuplicate; @@ -1367,23 +1410,31 @@ void __nvoc_init_KernelChannel(KernelChannel *pThis, RmHalspecOwner *pRmhalspeco __nvoc_init_funcTable_KernelChannel(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelChannel *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelChannel), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelChannel)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelChannel); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -1401,16 +1452,25 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel **ppThis, Dynamic *pParen status = __nvoc_ctor_KernelChannel(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelChannel_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelChannel_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelChannel)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.h b/src/nvidia/generated/g_kernel_channel_nvoc.h index 93c38fd1a7..6380ee2a6a 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.h +++ b/src/nvidia/generated/g_kernel_channel_nvoc.h @@ -191,11 +191,16 @@ typedef struct _def_instance_block /*! * Class for the kernel side of a Channel object. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CHANNEL_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelChannel { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -216,6 +221,7 @@ struct KernelChannel { NV_STATUS (*__kchannelCreateUserMemDesc__)(struct OBJGPU *, struct KernelChannel *); NvBool (*__kchannelIsUserdAddrSizeValid__)(struct KernelChannel *, NvU32, NvU32); NV_STATUS (*__kchannelCtrlCmdResetIsolatedChannel__)(struct KernelChannel *, NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *); + NV_STATUS (*__kchannelCtrlCmdInternalResetIsolatedChannel__)(struct KernelChannel *, NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS *); NV_STATUS (*__kchannelCtrlCmdGetClassEngineid__)(struct KernelChannel *, NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS *); NV_STATUS (*__kchannelCtrlCmdResetChannel__)(struct KernelChannel *, NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *); NV_STATUS (*__kchannelCtrlCmdGetDeferRCState__)(struct KernelChannel *, NV906F_CTRL_CMD_GET_DEFER_RC_STATE_PARAMS *); @@ -265,6 +271,7 @@ struct KernelChannel { NV_STATUS (*__kchannelCtrlSetTpcPartitionMode__)(struct KernelChannel *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); NV_STATUS (*__kchannelCtrlGetMMUDebugMode__)(struct KernelChannel *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); NV_STATUS (*__kchannelCtrlProgramVidmemPromote__)(struct KernelChannel *, NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS *); + NV_STATUS (*__kchannelRetrieveKmb__)(struct OBJGPU *, struct KernelChannel *, ROTATE_IV_TYPE, NvBool, CC_KMB *); NvBool (*__kchannelShareCallback__)(struct KernelChannel *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__kchannelGetOrAllocNotifShare__)(struct KernelChannel *, NvHandle, NvHandle, struct NotifShare **); NV_STATUS (*__kchannelMapTo__)(struct KernelChannel *, RS_RES_MAP_TO_PARAMS *); @@ -276,7 +283,6 @@ struct KernelChannel { NV_STATUS (*__kchannelInternalControlForward__)(struct KernelChannel *, NvU32, void *, NvU32); NV_STATUS (*__kchannelUnmapFrom__)(struct KernelChannel *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kchannelControl_Epilogue__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kchannelControlLookup__)(struct KernelChannel *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__kchannelGetInternalObjectHandle__)(struct KernelChannel *); NV_STATUS (*__kchannelControl__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kchannelGetMemoryMappingDescriptor__)(struct KernelChannel *, struct MEMORY_DESCRIPTOR **); @@ -284,6 +290,7 @@ struct KernelChannel { NV_STATUS (*__kchannelUnregisterEvent__)(struct KernelChannel *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__kchannelControlSerialization_Prologue__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kchannelCanCopy__)(struct KernelChannel *); + NvBool (*__kchannelIsPartialUnmapSupported__)(struct KernelChannel *); void (*__kchannelPreDestruct__)(struct KernelChannel *); NV_STATUS (*__kchannelIsDuplicate__)(struct KernelChannel *, NvHandle, NvBool *); void (*__kchannelControlSerialization_Epilogue__)(struct KernelChannel *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -292,6 +299,7 @@ struct KernelChannel { NvBool (*__kchannelAccessCallback__)(struct KernelChannel *, struct RsClient *, void *, RsAccessRight); NvU16 nextObjectClassID; struct KernelChannel *pNextBindKernelChannel; + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData; NvHandle hErrorContext; MEMORY_DESCRIPTOR *pErrContextMemDesc; ErrorNotifierType errorContextType; @@ -316,10 +324,11 @@ struct KernelChannel { MEMORY_DESCRIPTOR *pUserdSubDeviceMemDesc[8]; NvBool bClientAllocatedUserD; NvU32 swState[8]; + NvBool bIsRcPending[8]; NvU32 ProcessID; NvU32 SubProcessID; NvU32 bcStateCurrent; - NvU32 notifyIndex[2]; + NvU32 notifyIndex[3]; NvU32 *pNotifyActions; NvU64 userdLength; NvBool bSkipCtxBufferAlloc; @@ -329,6 +338,7 @@ struct KernelChannel { NvU32 runqueue; RM_ENGINE_TYPE engineType; CC_KMB clientKmb; + MEMORY_DESCRIPTOR *pEncStatsBufMemDesc; NvBool bCCSecureChannel; }; @@ -370,6 +380,7 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelIsUserdAddrSizeValid(pKernelChannel, userdAddrLo, userdAddrHi) kchannelIsUserdAddrSizeValid_DISPATCH(pKernelChannel, userdAddrLo, userdAddrHi) #define kchannelIsUserdAddrSizeValid_HAL(pKernelChannel, userdAddrLo, userdAddrHi) kchannelIsUserdAddrSizeValid_DISPATCH(pKernelChannel, userdAddrLo, userdAddrHi) #define kchannelCtrlCmdResetIsolatedChannel(pKernelChannel, pResetParams) kchannelCtrlCmdResetIsolatedChannel_DISPATCH(pKernelChannel, pResetParams) +#define kchannelCtrlCmdInternalResetIsolatedChannel(pKernelChannel, pResetParams) kchannelCtrlCmdInternalResetIsolatedChannel_DISPATCH(pKernelChannel, pResetParams) #define kchannelCtrlCmdGetClassEngineid(pKernelChannel, pParams) kchannelCtrlCmdGetClassEngineid_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlCmdResetChannel(pKernelChannel, pResetChannelParams) kchannelCtrlCmdResetChannel_DISPATCH(pKernelChannel, pResetChannelParams) #define kchannelCtrlCmdGetDeferRCState(pKernelChannel, pStateParams) kchannelCtrlCmdGetDeferRCState_DISPATCH(pKernelChannel, pStateParams) @@ -421,6 +432,8 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelCtrlSetTpcPartitionMode(pKernelChannel, pParams) kchannelCtrlSetTpcPartitionMode_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlGetMMUDebugMode(pKernelChannel, pParams) kchannelCtrlGetMMUDebugMode_DISPATCH(pKernelChannel, pParams) #define kchannelCtrlProgramVidmemPromote(pKernelChannel, pParams) kchannelCtrlProgramVidmemPromote_DISPATCH(pKernelChannel, pParams) +#define kchannelRetrieveKmb(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) kchannelRetrieveKmb_DISPATCH(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) +#define kchannelRetrieveKmb_HAL(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) kchannelRetrieveKmb_DISPATCH(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) #define kchannelShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kchannelShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define kchannelGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kchannelGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) #define kchannelMapTo(pResource, pParams) kchannelMapTo_DISPATCH(pResource, pParams) @@ -432,7 +445,6 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelInternalControlForward(pGpuResource, command, pParams, size) kchannelInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kchannelUnmapFrom(pResource, pParams) kchannelUnmapFrom_DISPATCH(pResource, pParams) #define kchannelControl_Epilogue(pResource, pCallContext, pParams) kchannelControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kchannelControlLookup(pResource, pParams, ppEntry) kchannelControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kchannelGetInternalObjectHandle(pGpuResource) kchannelGetInternalObjectHandle_DISPATCH(pGpuResource) #define kchannelControl(pGpuResource, pCallContext, pParams) kchannelControl_DISPATCH(pGpuResource, pCallContext, pParams) #define kchannelGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kchannelGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) @@ -440,6 +452,7 @@ NV_STATUS __nvoc_objCreate_KernelChannel(KernelChannel**, Dynamic*, NvU32, CALL_ #define kchannelUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kchannelUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define kchannelControlSerialization_Prologue(pResource, pCallContext, pParams) kchannelControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kchannelCanCopy(pResource) kchannelCanCopy_DISPATCH(pResource) +#define kchannelIsPartialUnmapSupported(pResource) kchannelIsPartialUnmapSupported_DISPATCH(pResource) #define kchannelPreDestruct(pResource) kchannelPreDestruct_DISPATCH(pResource) #define kchannelIsDuplicate(pResource, hMemory, pDuplicate) kchannelIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kchannelControlSerialization_Epilogue(pResource, pCallContext, pParams) kchannelControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -515,22 +528,22 @@ static inline NV_STATUS kchannelGetChannelPhysicalState(struct OBJGPU *pGpu, str #define kchannelGetChannelPhysicalState_HAL(pGpu, pKernelChannel, pChannelStateParams) kchannelGetChannelPhysicalState(pGpu, pKernelChannel, pChannelStateParams) -static inline NvU32 kchannelEmbedRunlistIDForSMC_13cd8d(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { +static inline NvU32 kchannelEmbedRunlistID_13cd8d(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { NV_ASSERT_PRECOMP(0); return 0; } #ifdef __nvoc_kernel_channel_h_disabled -static inline NvU32 kchannelEmbedRunlistIDForSMC(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { +static inline NvU32 kchannelEmbedRunlistID(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel) { NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); return 0; } #else //__nvoc_kernel_channel_h_disabled -#define kchannelEmbedRunlistIDForSMC(pGpu, pKernelChannel) kchannelEmbedRunlistIDForSMC_13cd8d(pGpu, pKernelChannel) +#define kchannelEmbedRunlistID(pGpu, pKernelChannel) kchannelEmbedRunlistID_13cd8d(pGpu, pKernelChannel) #endif //__nvoc_kernel_channel_h_disabled -#define kchannelEmbedRunlistIDForSMC_HAL(pGpu, pKernelChannel) kchannelEmbedRunlistIDForSMC(pGpu, pKernelChannel) +#define kchannelEmbedRunlistID_HAL(pGpu, pKernelChannel) kchannelEmbedRunlistID(pGpu, pKernelChannel) NV_STATUS kchannelAllocHwID_GM107(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvHandle hClient, NvU32 Flags, NvU32 verifFlags2, NvU32 ChID); @@ -735,20 +748,6 @@ static inline NV_STATUS kchannelRotateSecureChannelIv(struct KernelChannel *pKer #define kchannelRotateSecureChannelIv_HAL(pKernelChannel, rotateOperation, encryptIv, decryptIv) kchannelRotateSecureChannelIv(pKernelChannel, rotateOperation, encryptIv, decryptIv) -NV_STATUS kchannelRetrieveKmb_KERNEL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); - - -#ifdef __nvoc_kernel_channel_h_disabled -static inline NV_STATUS kchannelRetrieveKmb(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { - NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_channel_h_disabled -#define kchannelRetrieveKmb(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) kchannelRetrieveKmb_KERNEL(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) -#endif //__nvoc_kernel_channel_h_disabled - -#define kchannelRetrieveKmb_HAL(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) kchannelRetrieveKmb(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle) - NV_STATUS kchannelMap_IMPL(struct KernelChannel *pKernelChannel, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping); static inline NV_STATUS kchannelMap_DISPATCH(struct KernelChannel *pKernelChannel, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -803,6 +802,12 @@ static inline NV_STATUS kchannelCtrlCmdResetIsolatedChannel_DISPATCH(struct Kern return pKernelChannel->__kchannelCtrlCmdResetIsolatedChannel__(pKernelChannel, pResetParams); } +NV_STATUS kchannelCtrlCmdInternalResetIsolatedChannel_IMPL(struct KernelChannel *pKernelChannel, NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS *pResetParams); + +static inline NV_STATUS kchannelCtrlCmdInternalResetIsolatedChannel_DISPATCH(struct KernelChannel *pKernelChannel, NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS *pResetParams) { + return pKernelChannel->__kchannelCtrlCmdInternalResetIsolatedChannel__(pKernelChannel, pResetParams); +} + NV_STATUS kchannelCtrlCmdGetClassEngineid_IMPL(struct KernelChannel *pKernelChannel, NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS *pParams); static inline NV_STATUS kchannelCtrlCmdGetClassEngineid_DISPATCH(struct KernelChannel *pKernelChannel, NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS *pParams) { @@ -1103,12 +1108,20 @@ static inline NV_STATUS kchannelCtrlCmdStopChannel_DISPATCH(struct KernelChannel return pKernelChannel->__kchannelCtrlCmdStopChannel__(pKernelChannel, pStopChannelParams); } +static inline NV_STATUS kchannelCtrlCmdGetKmb_46f6a7(struct KernelChannel *pKernelChannel, NVC56F_CTRL_CMD_GET_KMB_PARAMS *pGetKmbParams) { + return NV_ERR_NOT_SUPPORTED; +} + NV_STATUS kchannelCtrlCmdGetKmb_KERNEL(struct KernelChannel *pKernelChannel, NVC56F_CTRL_CMD_GET_KMB_PARAMS *pGetKmbParams); static inline NV_STATUS kchannelCtrlCmdGetKmb_DISPATCH(struct KernelChannel *pKernelChannel, NVC56F_CTRL_CMD_GET_KMB_PARAMS *pGetKmbParams) { return pKernelChannel->__kchannelCtrlCmdGetKmb__(pKernelChannel, pGetKmbParams); } +static inline NV_STATUS kchannelCtrlRotateSecureChannelIv_46f6a7(struct KernelChannel *pKernelChannel, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams) { + return NV_ERR_NOT_SUPPORTED; +} + NV_STATUS kchannelCtrlRotateSecureChannelIv_KERNEL(struct KernelChannel *pKernelChannel, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams); static inline NV_STATUS kchannelCtrlRotateSecureChannelIv_DISPATCH(struct KernelChannel *pKernelChannel, NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS *pRotateIvParams) { @@ -1147,6 +1160,16 @@ static inline NV_STATUS kchannelCtrlProgramVidmemPromote_DISPATCH(struct KernelC return pKernelChannel->__kchannelCtrlProgramVidmemPromote__(pKernelChannel, pParams); } +static inline NV_STATUS kchannelRetrieveKmb_56cd7a(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return NV_OK; +} + +NV_STATUS kchannelRetrieveKmb_KERNEL(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); + +static inline NV_STATUS kchannelRetrieveKmb_DISPATCH(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle) { + return pKernelChannel->__kchannelRetrieveKmb__(pGpu, pKernelChannel, rotateOperation, includeSecrets, keyMaterialBundle); +} + static inline NvBool kchannelShareCallback_DISPATCH(struct KernelChannel *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__kchannelShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -1191,10 +1214,6 @@ static inline void kchannelControl_Epilogue_DISPATCH(struct KernelChannel *pReso pResource->__kchannelControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS kchannelControlLookup_DISPATCH(struct KernelChannel *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kchannelControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle kchannelGetInternalObjectHandle_DISPATCH(struct KernelChannel *pGpuResource) { return pGpuResource->__kchannelGetInternalObjectHandle__(pGpuResource); } @@ -1223,6 +1242,10 @@ static inline NvBool kchannelCanCopy_DISPATCH(struct KernelChannel *pResource) { return pResource->__kchannelCanCopy__(pResource); } +static inline NvBool kchannelIsPartialUnmapSupported_DISPATCH(struct KernelChannel *pResource) { + return pResource->__kchannelIsPartialUnmapSupported__(pResource); +} + static inline void kchannelPreDestruct_DISPATCH(struct KernelChannel *pResource) { pResource->__kchannelPreDestruct__(pResource); } @@ -1454,6 +1477,26 @@ static inline void kchannelUnmapUserD(struct OBJGPU *pGpu, struct KernelChannel #define kchannelUnmapUserD(pGpu, arg0, arg1, arg2, arg3) kchannelUnmapUserD_IMPL(pGpu, arg0, arg1, arg2, arg3) #endif //__nvoc_kernel_channel_h_disabled +void kchannelFillMmuExceptionInfo_IMPL(struct KernelChannel *pKernelChannel, FIFO_MMU_EXCEPTION_DATA *arg0); + +#ifdef __nvoc_kernel_channel_h_disabled +static inline void kchannelFillMmuExceptionInfo(struct KernelChannel *pKernelChannel, FIFO_MMU_EXCEPTION_DATA *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); +} +#else //__nvoc_kernel_channel_h_disabled +#define kchannelFillMmuExceptionInfo(pKernelChannel, arg0) kchannelFillMmuExceptionInfo_IMPL(pKernelChannel, arg0) +#endif //__nvoc_kernel_channel_h_disabled + +void kchannelFreeMmuExceptionInfo_IMPL(struct KernelChannel *pKernelChannel); + +#ifdef __nvoc_kernel_channel_h_disabled +static inline void kchannelFreeMmuExceptionInfo(struct KernelChannel *pKernelChannel) { + NV_ASSERT_FAILED_PRECOMP("KernelChannel was disabled!"); +} +#else //__nvoc_kernel_channel_h_disabled +#define kchannelFreeMmuExceptionInfo(pKernelChannel) kchannelFreeMmuExceptionInfo_IMPL(pKernelChannel) +#endif //__nvoc_kernel_channel_h_disabled + NV_STATUS kchannelGetFromDualHandle_IMPL(struct RsClient *arg0, NvHandle arg1, struct KernelChannel **arg2); #define kchannelGetFromDualHandle(arg0, arg1, arg2) kchannelGetFromDualHandle_IMPL(arg0, arg1, arg2) @@ -1474,16 +1517,17 @@ static inline NvU32 kchannelGetGfid(struct KernelChannel *pKernelChannel) { #undef PRIVATE_FIELD #ifndef NVOC_KERNEL_CHANNEL_H_PRIVATE_ACCESS_ALLOWED +#undef kchannelRetrieveKmb +NV_STATUS NVOC_PRIVATE_FUNCTION(kchannelRetrieveKmb)(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); + +#undef kchannelRetrieveKmb_HAL +NV_STATUS NVOC_PRIVATE_FUNCTION(kchannelRetrieveKmb_HAL)(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); + #ifndef __nvoc_kernel_channel_h_disabled #undef kchannelRotateSecureChannelIv NV_STATUS NVOC_PRIVATE_FUNCTION(kchannelRotateSecureChannelIv)(struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvU32 *encryptIv, NvU32 *decryptIv); #endif //__nvoc_kernel_channel_h_disabled -#ifndef __nvoc_kernel_channel_h_disabled -#undef kchannelRetrieveKmb -NV_STATUS NVOC_PRIVATE_FUNCTION(kchannelRetrieveKmb)(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, ROTATE_IV_TYPE rotateOperation, NvBool includeSecrets, CC_KMB *keyMaterialBundle); -#endif //__nvoc_kernel_channel_h_disabled - #endif // NVOC_KERNEL_CHANNEL_H_PRIVATE_ACCESS_ALLOWED @@ -1536,13 +1580,19 @@ ChannelDescendant *kchannelGetNextChildOverGroup(KernelChannelChildIterOverGroup NV_STATUS kchannelFindChildByHandle(struct KernelChannel *pKernelChannel, NvHandle hResource, ChannelDescendant **ppObject); // Bitmap for KernelChannel->swState -#define KERNEL_CHANNEL_SW_STATE_CPU_MAP NVBIT(0) //UserD is mapped -#define KERNEL_CHANNEL_SW_STATE_RUNLIST_SET NVBIT(1) // RunlistId is set +#define KERNEL_CHANNEL_SW_STATE_CPU_MAP NVBIT(0) //UserD is mapped +#define KERNEL_CHANNEL_SW_STATE_RUNLIST_SET NVBIT(1) // RunlistId is set +#define KERNEL_CHANNEL_SW_STATE_DISABLED_FOR_KEY_ROTATION NVBIT(2) // disabled for key rotation +#define KERNEL_CHANNEL_SW_STATE_ENABLE_AFTER_KEY_ROTATION NVBIT(3) // RM should enable after key rotation NvBool kchannelIsCpuMapped(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel); void kchannelSetCpuMapped(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvBool bCpuMapped); NvBool kchannelIsRunlistSet(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel); void kchannelSetRunlistSet(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvBool bRunlistSet); +NvBool kchannelIsDisabledForKeyRotation(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel); +void kchannelDisableForKeyRotation(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvBool bDisable); +NvBool kchannelIsEnableAfterKeyRotation(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel); +void kchannelEnableAfterKeyRotation(struct OBJGPU *pGpu, struct KernelChannel *pKernelChannel, NvBool bEnable); #endif // KERNEL_CHANNEL_H diff --git a/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h b/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h index 38d48b9059..e8c0de645f 100644 --- a/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h +++ b/src/nvidia/generated/g_kernel_crashcat_engine_nvoc.h @@ -52,11 +52,16 @@ typedef struct KernelCrashCatEngineConfig /*! * Base implementation of CrashCatEngine in RM. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CRASHCAT_ENGINE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelCrashCatEngine { const struct NVOC_RTTI *__nvoc_rtti; struct CrashCatEngine __nvoc_base_CrashCatEngine; diff --git a/src/nvidia/generated/g_kernel_ctxshare_nvoc.c b/src/nvidia/generated/g_kernel_ctxshare_nvoc.c index f6e477dba5..8ca00663bd 100644 --- a/src/nvidia/generated/g_kernel_ctxshare_nvoc.c +++ b/src/nvidia/generated/g_kernel_ctxshare_nvoc.c @@ -129,23 +129,31 @@ void __nvoc_init_KernelCtxShare(KernelCtxShare *pThis, RmHalspecOwner *pRmhalspe __nvoc_init_funcTable_KernelCtxShare(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelCtxShare(KernelCtxShare **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelCtxShare(KernelCtxShare **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelCtxShare *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCtxShare), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelCtxShare)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCtxShare); pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); @@ -163,16 +171,25 @@ NV_STATUS __nvoc_objCreate_KernelCtxShare(KernelCtxShare **ppThis, Dynamic *pPar status = __nvoc_ctor_KernelCtxShare(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelCtxShare_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelCtxShare_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelCtxShare)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -320,10 +337,6 @@ static void __nvoc_thunk_RmResource_kctxshareapiControl_Epilogue(struct KernelCt rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kctxshareapiControlLookup(struct KernelCtxShareApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle(struct KernelCtxShareApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelCtxShareApi_GpuResource.offset)); } @@ -352,6 +365,10 @@ static NV_STATUS __nvoc_thunk_RmResource_kctxshareapiControlSerialization_Prolog return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_kctxshareapiIsPartialUnmapSupported(struct KernelCtxShareApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_kctxshareapiPreDestruct(struct KernelCtxShareApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelCtxShareApi_RsResource.offset)); } @@ -503,8 +520,6 @@ static void __nvoc_init_funcTable_KernelCtxShareApi_1(KernelCtxShareApi *pThis) pThis->__kctxshareapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kctxshareapiControl_Epilogue; - pThis->__kctxshareapiControlLookup__ = &__nvoc_thunk_RsResource_kctxshareapiControlLookup; - pThis->__kctxshareapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kctxshareapiGetInternalObjectHandle; pThis->__kctxshareapiControl__ = &__nvoc_thunk_GpuResource_kctxshareapiControl; @@ -519,6 +534,8 @@ static void __nvoc_init_funcTable_KernelCtxShareApi_1(KernelCtxShareApi *pThis) pThis->__kctxshareapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kctxshareapiControlSerialization_Prologue; + pThis->__kctxshareapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_kctxshareapiIsPartialUnmapSupported; + pThis->__kctxshareapiPreDestruct__ = &__nvoc_thunk_RsResource_kctxshareapiPreDestruct; pThis->__kctxshareapiIsDuplicate__ = &__nvoc_thunk_RsResource_kctxshareapiIsDuplicate; @@ -546,21 +563,26 @@ void __nvoc_init_KernelCtxShareApi(KernelCtxShareApi *pThis) { __nvoc_init_funcTable_KernelCtxShareApi(pThis); } -NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelCtxShareApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelCtxShareApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelCtxShareApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelCtxShareApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -575,16 +597,25 @@ NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi **ppThis, Dynamic status = __nvoc_ctor_KernelCtxShareApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelCtxShareApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelCtxShareApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelCtxShareApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_ctxshare_nvoc.h b/src/nvidia/generated/g_kernel_ctxshare_nvoc.h index c2376a3b4c..cabbf50bf8 100644 --- a/src/nvidia/generated/g_kernel_ctxshare_nvoc.h +++ b/src/nvidia/generated/g_kernel_ctxshare_nvoc.h @@ -79,11 +79,16 @@ typedef struct KernelCtxShareApi KernelCtxShareApi; * Instances of this class are ref-counted and will be kept alive until * all subcontext copies have been freed by the resource server. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CTXSHARE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelCtxShare { const struct NVOC_RTTI *__nvoc_rtti; struct RsShared __nvoc_base_RsShared; @@ -124,13 +129,13 @@ NV_STATUS __nvoc_objCreate_KernelCtxShare(KernelCtxShare**, Dynamic*, NvU32); #define __objCreate_KernelCtxShare(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_KernelCtxShare((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) -static inline NV_STATUS kctxshareInit_56cd7a(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct OBJVASPACE *pVAS, struct KernelChannelGroupApi *pKernelChannelGroupApi, NvU64 offset, PEMEMBLOCK pBlock) { +static inline NV_STATUS kctxshareInit_56cd7a(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct OBJVASPACE *pVAS, struct KernelChannelGroupApi *pKernelChannelGroupApi, NvU64 offset, struct EMEMBLOCK *pBlock) { return NV_OK; } #ifdef __nvoc_kernel_ctxshare_h_disabled -static inline NV_STATUS kctxshareInit(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct OBJVASPACE *pVAS, struct KernelChannelGroupApi *pKernelChannelGroupApi, NvU64 offset, PEMEMBLOCK pBlock) { +static inline NV_STATUS kctxshareInit(struct KernelCtxShare *pKernelCtxShare, struct KernelCtxShareApi *pKernelCtxShareApi, struct OBJGPU *pGpu, struct OBJVASPACE *pVAS, struct KernelChannelGroupApi *pKernelChannelGroupApi, NvU64 offset, struct EMEMBLOCK *pBlock) { NV_ASSERT_FAILED_PRECOMP("KernelCtxShare was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -187,11 +192,16 @@ void kctxshareDestruct_IMPL(struct KernelCtxShare *pKernelCtxShare); #undef PRIVATE_FIELD + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_CTXSHARE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelCtxShareApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -216,7 +226,6 @@ struct KernelCtxShareApi { NV_STATUS (*__kctxshareapiInternalControlForward__)(struct KernelCtxShareApi *, NvU32, void *, NvU32); NV_STATUS (*__kctxshareapiUnmapFrom__)(struct KernelCtxShareApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kctxshareapiControl_Epilogue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kctxshareapiControlLookup__)(struct KernelCtxShareApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__kctxshareapiGetInternalObjectHandle__)(struct KernelCtxShareApi *); NV_STATUS (*__kctxshareapiControl__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kctxshareapiUnmap__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -224,6 +233,7 @@ struct KernelCtxShareApi { NV_STATUS (*__kctxshareapiGetMemoryMappingDescriptor__)(struct KernelCtxShareApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kctxshareapiControlFilter__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kctxshareapiControlSerialization_Prologue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__kctxshareapiIsPartialUnmapSupported__)(struct KernelCtxShareApi *); void (*__kctxshareapiPreDestruct__)(struct KernelCtxShareApi *); NV_STATUS (*__kctxshareapiIsDuplicate__)(struct KernelCtxShareApi *, NvHandle, NvBool *); void (*__kctxshareapiControlSerialization_Epilogue__)(struct KernelCtxShareApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -276,7 +286,6 @@ NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi**, Dynamic*, NvU3 #define kctxshareapiInternalControlForward(pGpuResource, command, pParams, size) kctxshareapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kctxshareapiUnmapFrom(pResource, pParams) kctxshareapiUnmapFrom_DISPATCH(pResource, pParams) #define kctxshareapiControl_Epilogue(pResource, pCallContext, pParams) kctxshareapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kctxshareapiControlLookup(pResource, pParams, ppEntry) kctxshareapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kctxshareapiGetInternalObjectHandle(pGpuResource) kctxshareapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define kctxshareapiControl(pGpuResource, pCallContext, pParams) kctxshareapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define kctxshareapiUnmap(pGpuResource, pCallContext, pCpuMapping) kctxshareapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -284,6 +293,7 @@ NV_STATUS __nvoc_objCreate_KernelCtxShareApi(KernelCtxShareApi**, Dynamic*, NvU3 #define kctxshareapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kctxshareapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define kctxshareapiControlFilter(pResource, pCallContext, pParams) kctxshareapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kctxshareapiControlSerialization_Prologue(pResource, pCallContext, pParams) kctxshareapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kctxshareapiIsPartialUnmapSupported(pResource) kctxshareapiIsPartialUnmapSupported_DISPATCH(pResource) #define kctxshareapiPreDestruct(pResource) kctxshareapiPreDestruct_DISPATCH(pResource) #define kctxshareapiIsDuplicate(pResource, hMemory, pDuplicate) kctxshareapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kctxshareapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kctxshareapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -357,10 +367,6 @@ static inline void kctxshareapiControl_Epilogue_DISPATCH(struct KernelCtxShareAp pResource->__kctxshareapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS kctxshareapiControlLookup_DISPATCH(struct KernelCtxShareApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kctxshareapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle kctxshareapiGetInternalObjectHandle_DISPATCH(struct KernelCtxShareApi *pGpuResource) { return pGpuResource->__kctxshareapiGetInternalObjectHandle__(pGpuResource); } @@ -389,6 +395,10 @@ static inline NV_STATUS kctxshareapiControlSerialization_Prologue_DISPATCH(struc return pResource->__kctxshareapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool kctxshareapiIsPartialUnmapSupported_DISPATCH(struct KernelCtxShareApi *pResource) { + return pResource->__kctxshareapiIsPartialUnmapSupported__(pResource); +} + static inline void kctxshareapiPreDestruct_DISPATCH(struct KernelCtxShareApi *pResource) { pResource->__kctxshareapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.c b/src/nvidia/generated/g_kernel_falcon_nvoc.c index 3632f028fe..cbe9db5e3f 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.c +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.c @@ -181,102 +181,266 @@ static void __nvoc_init_funcTable_KernelFalcon_1(KernelFalcon *pThis, RmHalspecO PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); // Hal function -- kflcnRegRead - pThis->__kflcnRegRead__ = &kflcnRegRead_TU102; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnRegRead__ = &kflcnRegRead_474d46; + } + else + { + pThis->__kflcnRegRead__ = &kflcnRegRead_TU102; + } // Hal function -- kflcnRegWrite - pThis->__kflcnRegWrite__ = &kflcnRegWrite_TU102; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnRegWrite__ = &kflcnRegWrite_f2d351; + } + else + { + pThis->__kflcnRegWrite__ = &kflcnRegWrite_TU102; + } + + // Hal function -- kflcnRiscvRegRead + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnRiscvRegRead__ = &kflcnRiscvRegRead_474d46; + } + else + { + pThis->__kflcnRiscvRegRead__ = &kflcnRiscvRegRead_TU102; + } + + // Hal function -- kflcnRiscvRegWrite + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnRiscvRegWrite__ = &kflcnRiscvRegWrite_f2d351; + } + else + { + pThis->__kflcnRiscvRegWrite__ = &kflcnRiscvRegWrite_TU102; + } + + // Hal function -- kflcnIsRiscvCpuEnabled + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnIsRiscvCpuEnabled__ = &kflcnIsRiscvCpuEnabled_108313; + } + else + { + pThis->__kflcnIsRiscvCpuEnabled__ = &kflcnIsRiscvCpuEnabled_TU102; + } // Hal function -- kflcnIsRiscvActive - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_TU102; + pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_108313; } else { - pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_GA10X; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_TU102; + } + else + { + pThis->__kflcnIsRiscvActive__ = &kflcnIsRiscvActive_GA10X; + } } // Hal function -- kflcnRiscvProgramBcr - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_f2d351; } else { - pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_GA102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_f2d351; + } + else + { + pThis->__kflcnRiscvProgramBcr__ = &kflcnRiscvProgramBcr_GA102; + } } // Hal function -- kflcnSwitchToFalcon - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_b3696a; + pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_f2d351; } else { - pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_GA10X; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_b3696a; + } + else + { + pThis->__kflcnSwitchToFalcon__ = &kflcnSwitchToFalcon_GA10X; + } } pThis->__kflcnResetHw__ = NULL; + // Hal function -- kflcnReset + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnReset__ = &kflcnReset_f2d351; + } + else + { + pThis->__kflcnReset__ = &kflcnReset_TU102; + } + + // Hal function -- kflcnResetIntoRiscv + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnResetIntoRiscv__ = &kflcnResetIntoRiscv_f2d351; + } + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnResetIntoRiscv__ = &kflcnResetIntoRiscv_TU102; + } + else + { + pThis->__kflcnResetIntoRiscv__ = &kflcnResetIntoRiscv_GA102; + } + } + + // Hal function -- kflcnStartCpu + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnStartCpu__ = &kflcnStartCpu_f2d351; + } + else + { + pThis->__kflcnStartCpu__ = &kflcnStartCpu_TU102; + } + + // Hal function -- kflcnDisableCtxReq + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnDisableCtxReq__ = &kflcnDisableCtxReq_f2d351; + } + else + { + pThis->__kflcnDisableCtxReq__ = &kflcnDisableCtxReq_TU102; + } + // Hal function -- kflcnPreResetWait - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_GA10X; + pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_5baef9; } - // default else { - pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_56cd7a; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_GA10X; + } + // default + else + { + pThis->__kflcnPreResetWait__ = &kflcnPreResetWait_56cd7a; + } } // Hal function -- kflcnWaitForResetToFinish - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_5baef9; + } + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_TU102; + } + else + { + pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_GA102; + } + } + + // Hal function -- kflcnWaitForHalt + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_TU102; + pThis->__kflcnWaitForHalt__ = &kflcnWaitForHalt_5baef9; } else { - pThis->__kflcnWaitForResetToFinish__ = &kflcnWaitForResetToFinish_GA102; + pThis->__kflcnWaitForHalt__ = &kflcnWaitForHalt_TU102; } // Hal function -- kflcnReadIntrStatus - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_TU102; + pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_474d46; } else { - pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_GA102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_TU102; + } + else + { + pThis->__kflcnReadIntrStatus__ = &kflcnReadIntrStatus_GA102; + } } // Hal function -- kflcnIntrRetrigger - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_b3696a; + pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_f2d351; } else { - pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_GA100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_b3696a; + } + else + { + pThis->__kflcnIntrRetrigger__ = &kflcnIntrRetrigger_GA100; + } } // Hal function -- kflcnMaskImemAddr - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_TU102; + pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_474d46; } else { - pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_GA100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_TU102; + } + else + { + pThis->__kflcnMaskImemAddr__ = &kflcnMaskImemAddr_GA100; + } } // Hal function -- kflcnMaskDmemAddr - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_TU102; + pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_474d46; } else { - pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_GA100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_TU102; + } + else + { + pThis->__kflcnMaskDmemAddr__ = &kflcnMaskDmemAddr_GA100; + } } pThis->__nvoc_base_KernelCrashCatEngine.__kcrashcatEngineRegRead__ = &__nvoc_thunk_KernelFalcon_kcrashcatEngineRegRead; @@ -413,7 +577,7 @@ static NV_STATUS __nvoc_thunk_GenericKernelFalcon_kflcnResetHw(struct OBJGPU *pG return gkflcnResetHw(pGpu, (struct GenericKernelFalcon *)(((unsigned char *)pGenKernFlcn) - __nvoc_rtti_GenericKernelFalcon_KernelFalcon.offset)); } -static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[168]) { +static void __nvoc_thunk_GenericKernelFalcon_intrservRegisterIntrService(struct OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[171]) { gkflcnRegisterIntrService(arg0, (struct GenericKernelFalcon *)(((unsigned char *)arg1) - __nvoc_rtti_GenericKernelFalcon_IntrService.offset), arg2); } @@ -608,23 +772,31 @@ void __nvoc_init_GenericKernelFalcon(GenericKernelFalcon *pThis, RmHalspecOwner __nvoc_init_funcTable_GenericKernelFalcon(pThis); } -NV_STATUS __nvoc_objCreate_GenericKernelFalcon(GenericKernelFalcon **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KernelFalconEngineConfig * arg_pFalconConfig) { +NV_STATUS __nvoc_objCreate_GenericKernelFalcon(GenericKernelFalcon **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KernelFalconEngineConfig * arg_pFalconConfig) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; GenericKernelFalcon *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(GenericKernelFalcon), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(GenericKernelFalcon)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_GenericKernelFalcon); pThis->__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_Object); @@ -642,16 +814,25 @@ NV_STATUS __nvoc_objCreate_GenericKernelFalcon(GenericKernelFalcon **ppThis, Dyn status = __nvoc_ctor_GenericKernelFalcon(pThis, pRmhalspecowner, arg_pGpu, arg_pFalconConfig); if (status != NV_OK) goto __nvoc_objCreate_GenericKernelFalcon_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_GenericKernelFalcon_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(GenericKernelFalcon)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_falcon_nvoc.h b/src/nvidia/generated/g_kernel_falcon_nvoc.h index e167c6bc0d..d13fad51e9 100644 --- a/src/nvidia/generated/g_kernel_falcon_nvoc.h +++ b/src/nvidia/generated/g_kernel_falcon_nvoc.h @@ -75,11 +75,16 @@ typedef struct KernelFalconEngineConfig { /*! * Base class for booting Falcon cores (including RISC-V) */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_FALCON_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelFalcon { const struct NVOC_RTTI *__nvoc_rtti; struct KernelCrashCatEngine __nvoc_base_KernelCrashCatEngine; @@ -88,12 +93,20 @@ struct KernelFalcon { struct KernelFalcon *__nvoc_pbase_KernelFalcon; NvU32 (*__kflcnRegRead__)(struct OBJGPU *, struct KernelFalcon *, NvU32); void (*__kflcnRegWrite__)(struct OBJGPU *, struct KernelFalcon *, NvU32, NvU32); + NvU32 (*__kflcnRiscvRegRead__)(struct OBJGPU *, struct KernelFalcon *, NvU32); + void (*__kflcnRiscvRegWrite__)(struct OBJGPU *, struct KernelFalcon *, NvU32, NvU32); + NvBool (*__kflcnIsRiscvCpuEnabled__)(struct OBJGPU *, struct KernelFalcon *); NvBool (*__kflcnIsRiscvActive__)(struct OBJGPU *, struct KernelFalcon *); void (*__kflcnRiscvProgramBcr__)(struct OBJGPU *, struct KernelFalcon *, NvBool); void (*__kflcnSwitchToFalcon__)(struct OBJGPU *, struct KernelFalcon *); NV_STATUS (*__kflcnResetHw__)(struct OBJGPU *, struct KernelFalcon *); + void (*__kflcnReset__)(struct OBJGPU *, struct KernelFalcon *); + void (*__kflcnResetIntoRiscv__)(struct OBJGPU *, struct KernelFalcon *); + void (*__kflcnStartCpu__)(struct OBJGPU *, struct KernelFalcon *); + void (*__kflcnDisableCtxReq__)(struct OBJGPU *, struct KernelFalcon *); NV_STATUS (*__kflcnPreResetWait__)(struct OBJGPU *, struct KernelFalcon *); NV_STATUS (*__kflcnWaitForResetToFinish__)(struct OBJGPU *, struct KernelFalcon *); + NV_STATUS (*__kflcnWaitForHalt__)(struct OBJGPU *, struct KernelFalcon *, NvU32, NvU32); NvU32 (*__kflcnReadIntrStatus__)(struct OBJGPU *, struct KernelFalcon *); void (*__kflcnIntrRetrigger__)(struct OBJGPU *, struct KernelFalcon *); NvU32 (*__kflcnMaskImemAddr__)(struct OBJGPU *, struct KernelFalcon *, NvU32); @@ -154,6 +167,12 @@ NV_STATUS __nvoc_objCreate_KernelFalcon(KernelFalcon**, Dynamic*, NvU32); #define kflcnRegRead_HAL(pGpu, pKernelFlcn, offset) kflcnRegRead_DISPATCH(pGpu, pKernelFlcn, offset) #define kflcnRegWrite(pGpu, pKernelFlcn, offset, data) kflcnRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) #define kflcnRegWrite_HAL(pGpu, pKernelFlcn, offset, data) kflcnRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) +#define kflcnRiscvRegRead(pGpu, pKernelFlcn, offset) kflcnRiscvRegRead_DISPATCH(pGpu, pKernelFlcn, offset) +#define kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, offset) kflcnRiscvRegRead_DISPATCH(pGpu, pKernelFlcn, offset) +#define kflcnRiscvRegWrite(pGpu, pKernelFlcn, offset, data) kflcnRiscvRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) +#define kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, offset, data) kflcnRiscvRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) +#define kflcnIsRiscvCpuEnabled(pGpu, pKernelFlcn) kflcnIsRiscvCpuEnabled_DISPATCH(pGpu, pKernelFlcn) +#define kflcnIsRiscvCpuEnabled_HAL(pGpu, pKernelFlcn) kflcnIsRiscvCpuEnabled_DISPATCH(pGpu, pKernelFlcn) #define kflcnIsRiscvActive(pGpu, pKernelFlcn) kflcnIsRiscvActive_DISPATCH(pGpu, pKernelFlcn) #define kflcnIsRiscvActive_HAL(pGpu, pKernelFlcn) kflcnIsRiscvActive_DISPATCH(pGpu, pKernelFlcn) #define kflcnRiscvProgramBcr(pGpu, pKernelFlcn, bBRFetch) kflcnRiscvProgramBcr_DISPATCH(pGpu, pKernelFlcn, bBRFetch) @@ -161,10 +180,20 @@ NV_STATUS __nvoc_objCreate_KernelFalcon(KernelFalcon**, Dynamic*, NvU32); #define kflcnSwitchToFalcon(pGpu, pKernelFlcn) kflcnSwitchToFalcon_DISPATCH(pGpu, pKernelFlcn) #define kflcnSwitchToFalcon_HAL(pGpu, pKernelFlcn) kflcnSwitchToFalcon_DISPATCH(pGpu, pKernelFlcn) #define kflcnResetHw(pGpu, pKernelFlcn) kflcnResetHw_DISPATCH(pGpu, pKernelFlcn) +#define kflcnReset(pGpu, pKernelFlcn) kflcnReset_DISPATCH(pGpu, pKernelFlcn) +#define kflcnReset_HAL(pGpu, pKernelFlcn) kflcnReset_DISPATCH(pGpu, pKernelFlcn) +#define kflcnResetIntoRiscv(pGpu, pKernelFlcn) kflcnResetIntoRiscv_DISPATCH(pGpu, pKernelFlcn) +#define kflcnResetIntoRiscv_HAL(pGpu, pKernelFlcn) kflcnResetIntoRiscv_DISPATCH(pGpu, pKernelFlcn) +#define kflcnStartCpu(pGpu, pKernelFlcn) kflcnStartCpu_DISPATCH(pGpu, pKernelFlcn) +#define kflcnStartCpu_HAL(pGpu, pKernelFlcn) kflcnStartCpu_DISPATCH(pGpu, pKernelFlcn) +#define kflcnDisableCtxReq(pGpu, pKernelFlcn) kflcnDisableCtxReq_DISPATCH(pGpu, pKernelFlcn) +#define kflcnDisableCtxReq_HAL(pGpu, pKernelFlcn) kflcnDisableCtxReq_DISPATCH(pGpu, pKernelFlcn) #define kflcnPreResetWait(pGpu, pKernelFlcn) kflcnPreResetWait_DISPATCH(pGpu, pKernelFlcn) #define kflcnPreResetWait_HAL(pGpu, pKernelFlcn) kflcnPreResetWait_DISPATCH(pGpu, pKernelFlcn) #define kflcnWaitForResetToFinish(pGpu, pKernelFlcn) kflcnWaitForResetToFinish_DISPATCH(pGpu, pKernelFlcn) #define kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn) kflcnWaitForResetToFinish_DISPATCH(pGpu, pKernelFlcn) +#define kflcnWaitForHalt(pGpu, pKernelFlcn, timeoutUs, flags) kflcnWaitForHalt_DISPATCH(pGpu, pKernelFlcn, timeoutUs, flags) +#define kflcnWaitForHalt_HAL(pGpu, pKernelFlcn, timeoutUs, flags) kflcnWaitForHalt_DISPATCH(pGpu, pKernelFlcn, timeoutUs, flags) #define kflcnReadIntrStatus(pGpu, pKerneFlcn) kflcnReadIntrStatus_DISPATCH(pGpu, pKerneFlcn) #define kflcnReadIntrStatus_HAL(pGpu, pKerneFlcn) kflcnReadIntrStatus_DISPATCH(pGpu, pKerneFlcn) #define kflcnIntrRetrigger(pGpu, pKernelFlcn) kflcnIntrRetrigger_DISPATCH(pGpu, pKernelFlcn) @@ -185,142 +214,64 @@ NV_STATUS __nvoc_objCreate_KernelFalcon(KernelFalcon**, Dynamic*, NvU32); #define kflcnMapBufferDescriptor(arg0, pBufDesc) kflcnMapBufferDescriptor_DISPATCH(arg0, pBufDesc) #define kflcnUnmapBufferDescriptor(arg0, pBufDesc) kflcnUnmapBufferDescriptor_DISPATCH(arg0, pBufDesc) #define kflcnReadDmem(arg0, offset, size, pBuf) kflcnReadDmem_DISPATCH(arg0, offset, size, pBuf) -NvU32 kflcnRiscvRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); - +NvU32 kflcnRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); -#ifdef __nvoc_kernel_falcon_h_disabled -static inline NvU32 kflcnRiscvRegRead(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); - return 0; +static inline NvU32 kflcnRegRead_474d46(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); } -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnRiscvRegRead(pGpu, pKernelFlcn, offset) kflcnRiscvRegRead_TU102(pGpu, pKernelFlcn, offset) -#endif //__nvoc_kernel_falcon_h_disabled -#define kflcnRiscvRegRead_HAL(pGpu, pKernelFlcn, offset) kflcnRiscvRegRead(pGpu, pKernelFlcn, offset) - -void kflcnRiscvRegWrite_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data); - - -#ifdef __nvoc_kernel_falcon_h_disabled -static inline void kflcnRiscvRegWrite(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); +static inline NvU32 kflcnRegRead_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { + return pKernelFlcn->__kflcnRegRead__(pGpu, pKernelFlcn, offset); } -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnRiscvRegWrite(pGpu, pKernelFlcn, offset, data) kflcnRiscvRegWrite_TU102(pGpu, pKernelFlcn, offset, data) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnRiscvRegWrite_HAL(pGpu, pKernelFlcn, offset, data) kflcnRiscvRegWrite(pGpu, pKernelFlcn, offset, data) - -NvBool kflcnIsRiscvCpuEnabled_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); +void kflcnRegWrite_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data); -#ifdef __nvoc_kernel_falcon_h_disabled -static inline NvBool kflcnIsRiscvCpuEnabled(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); - return NV_FALSE; +static inline void kflcnRegWrite_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { + NV_ASSERT_PRECOMP(0); } -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnIsRiscvCpuEnabled(pGpu, pKernelFlcn) kflcnIsRiscvCpuEnabled_TU102(pGpu, pKernelFlcn) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnIsRiscvCpuEnabled_HAL(pGpu, pKernelFlcn) kflcnIsRiscvCpuEnabled(pGpu, pKernelFlcn) - -void kflcnReset_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); - -#ifdef __nvoc_kernel_falcon_h_disabled -static inline void kflcnReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); +static inline void kflcnRegWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { + pKernelFlcn->__kflcnRegWrite__(pGpu, pKernelFlcn, offset, data); } -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnReset(pGpu, pKernelFlcn) kflcnReset_TU102(pGpu, pKernelFlcn) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnReset_HAL(pGpu, pKernelFlcn) kflcnReset(pGpu, pKernelFlcn) - -void kflcnSecureReset_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); +NvU32 kflcnRiscvRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); -#ifdef __nvoc_kernel_falcon_h_disabled -static inline void kflcnSecureReset(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); +static inline NvU32 kflcnRiscvRegRead_474d46(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); } -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnSecureReset(pGpu, pKernelFlcn) kflcnSecureReset_TU102(pGpu, pKernelFlcn) -#endif //__nvoc_kernel_falcon_h_disabled -#define kflcnSecureReset_HAL(pGpu, pKernelFlcn) kflcnSecureReset(pGpu, pKernelFlcn) - -void kflcnEnable_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvBool bEnable); - - -#ifdef __nvoc_kernel_falcon_h_disabled -static inline void kflcnEnable(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvBool bEnable) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); +static inline NvU32 kflcnRiscvRegRead_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { + return pKernelFlcn->__kflcnRiscvRegRead__(pGpu, pKernelFlcn, offset); } -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnEnable(pGpu, pKernelFlcn, bEnable) kflcnEnable_TU102(pGpu, pKernelFlcn, bEnable) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnEnable_HAL(pGpu, pKernelFlcn, bEnable) kflcnEnable(pGpu, pKernelFlcn, bEnable) - -void kflcnStartCpu_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); +void kflcnRiscvRegWrite_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data); -#ifdef __nvoc_kernel_falcon_h_disabled -static inline void kflcnStartCpu(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); +static inline void kflcnRiscvRegWrite_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { + NV_ASSERT_PRECOMP(0); } -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnStartCpu(pGpu, pKernelFlcn) kflcnStartCpu_TU102(pGpu, pKernelFlcn) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnStartCpu_HAL(pGpu, pKernelFlcn) kflcnStartCpu(pGpu, pKernelFlcn) - -void kflcnDisableCtxReq_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); - -#ifdef __nvoc_kernel_falcon_h_disabled -static inline void kflcnDisableCtxReq(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); +static inline void kflcnRiscvRegWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { + pKernelFlcn->__kflcnRiscvRegWrite__(pGpu, pKernelFlcn, offset, data); } -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnDisableCtxReq(pGpu, pKernelFlcn) kflcnDisableCtxReq_TU102(pGpu, pKernelFlcn) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnDisableCtxReq_HAL(pGpu, pKernelFlcn) kflcnDisableCtxReq(pGpu, pKernelFlcn) - -NV_STATUS kflcnWaitForHalt_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 timeoutUs, NvU32 flags); +NvBool kflcnIsRiscvCpuEnabled_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); -#ifdef __nvoc_kernel_falcon_h_disabled -static inline NV_STATUS kflcnWaitForHalt(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 timeoutUs, NvU32 flags) { - NV_ASSERT_FAILED_PRECOMP("KernelFalcon was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_falcon_h_disabled -#define kflcnWaitForHalt(pGpu, pKernelFlcn, timeoutUs, flags) kflcnWaitForHalt_TU102(pGpu, pKernelFlcn, timeoutUs, flags) -#endif //__nvoc_kernel_falcon_h_disabled - -#define kflcnWaitForHalt_HAL(pGpu, pKernelFlcn, timeoutUs, flags) kflcnWaitForHalt(pGpu, pKernelFlcn, timeoutUs, flags) - -NvU32 kflcnRegRead_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset); - -static inline NvU32 kflcnRegRead_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset) { - return pKernelFlcn->__kflcnRegRead__(pGpu, pKernelFlcn, offset); +static inline NvBool kflcnIsRiscvCpuEnabled_108313(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); } -void kflcnRegWrite_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data); - -static inline void kflcnRegWrite_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 offset, NvU32 data) { - pKernelFlcn->__kflcnRegWrite__(pGpu, pKernelFlcn, offset, data); +static inline NvBool kflcnIsRiscvCpuEnabled_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + return pKernelFlcn->__kflcnIsRiscvCpuEnabled__(pGpu, pKernelFlcn); } NvBool kflcnIsRiscvActive_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); NvBool kflcnIsRiscvActive_GA10X(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); +static inline NvBool kflcnIsRiscvActive_108313(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + static inline NvBool kflcnIsRiscvActive_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { return pKernelFlcn->__kflcnIsRiscvActive__(pGpu, pKernelFlcn); } @@ -341,6 +292,10 @@ static inline void kflcnSwitchToFalcon_b3696a(struct OBJGPU *pGpu, struct Kernel return; } +static inline void kflcnSwitchToFalcon_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_PRECOMP(0); +} + static inline void kflcnSwitchToFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { pKernelFlcn->__kflcnSwitchToFalcon__(pGpu, pKernelFlcn); } @@ -349,12 +304,58 @@ static inline NV_STATUS kflcnResetHw_DISPATCH(struct OBJGPU *pGpu, struct Kernel return pKernelFlcn->__kflcnResetHw__(pGpu, pKernelFlcn); } +void kflcnReset_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + +static inline void kflcnReset_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kflcnReset_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + pKernelFlcn->__kflcnReset__(pGpu, pKernelFlcn); +} + +void kflcnResetIntoRiscv_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + +void kflcnResetIntoRiscv_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + +static inline void kflcnResetIntoRiscv_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kflcnResetIntoRiscv_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + pKernelFlcn->__kflcnResetIntoRiscv__(pGpu, pKernelFlcn); +} + +void kflcnStartCpu_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + +static inline void kflcnStartCpu_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kflcnStartCpu_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + pKernelFlcn->__kflcnStartCpu__(pGpu, pKernelFlcn); +} + +void kflcnDisableCtxReq_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); + +static inline void kflcnDisableCtxReq_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kflcnDisableCtxReq_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + pKernelFlcn->__kflcnDisableCtxReq__(pGpu, pKernelFlcn); +} + NV_STATUS kflcnPreResetWait_GA10X(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); static inline NV_STATUS kflcnPreResetWait_56cd7a(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { return NV_OK; } +static inline NV_STATUS kflcnPreResetWait_5baef9(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS kflcnPreResetWait_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { return pKernelFlcn->__kflcnPreResetWait__(pGpu, pKernelFlcn); } @@ -363,14 +364,32 @@ NV_STATUS kflcnWaitForResetToFinish_GA102(struct OBJGPU *pGpu, struct KernelFalc NV_STATUS kflcnWaitForResetToFinish_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn); +static inline NV_STATUS kflcnWaitForResetToFinish_5baef9(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS kflcnWaitForResetToFinish_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { return pKernelFlcn->__kflcnWaitForResetToFinish__(pGpu, pKernelFlcn); } +NV_STATUS kflcnWaitForHalt_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 timeoutUs, NvU32 flags); + +static inline NV_STATUS kflcnWaitForHalt_5baef9(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 timeoutUs, NvU32 flags) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kflcnWaitForHalt_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 timeoutUs, NvU32 flags) { + return pKernelFlcn->__kflcnWaitForHalt__(pGpu, pKernelFlcn, timeoutUs, flags); +} + NvU32 kflcnReadIntrStatus_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn); NvU32 kflcnReadIntrStatus_GA102(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn); +static inline NvU32 kflcnReadIntrStatus_474d46(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + static inline NvU32 kflcnReadIntrStatus_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKerneFlcn) { return pKerneFlcn->__kflcnReadIntrStatus__(pGpu, pKerneFlcn); } @@ -381,6 +400,10 @@ static inline void kflcnIntrRetrigger_b3696a(struct OBJGPU *pGpu, struct KernelF return; } +static inline void kflcnIntrRetrigger_f2d351(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { + NV_ASSERT_PRECOMP(0); +} + static inline void kflcnIntrRetrigger_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn) { pKernelFlcn->__kflcnIntrRetrigger__(pGpu, pKernelFlcn); } @@ -389,6 +412,10 @@ NvU32 kflcnMaskImemAddr_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelF NvU32 kflcnMaskImemAddr_GA100(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr); +static inline NvU32 kflcnMaskImemAddr_474d46(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + static inline NvU32 kflcnMaskImemAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr) { return pKernelFlcn->__kflcnMaskImemAddr__(pGpu, pKernelFlcn, addr); } @@ -397,6 +424,10 @@ NvU32 kflcnMaskDmemAddr_TU102(struct OBJGPU *pGpu, struct KernelFalcon *pKernelF NvU32 kflcnMaskDmemAddr_GA100(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr); +static inline NvU32 kflcnMaskDmemAddr_474d46(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + static inline NvU32 kflcnMaskDmemAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelFalcon *pKernelFlcn, NvU32 addr) { return pKernelFlcn->__kflcnMaskDmemAddr__(pGpu, pKernelFlcn, addr); } @@ -488,11 +519,16 @@ struct KernelFalcon *kflcnGetKernelFalconForEngine_IMPL(struct OBJGPU *pGpu, ENG // Basic implementation of KernelFalcon that can be instantiated. + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_FALCON_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct GenericKernelFalcon { const struct NVOC_RTTI *__nvoc_rtti; struct KernelFalcon __nvoc_base_KernelFalcon; @@ -580,9 +616,9 @@ static inline NV_STATUS gkflcnResetHw_DISPATCH(struct OBJGPU *pGpu, struct Gener return pGenKernFlcn->__gkflcnResetHw__(pGpu, pGenKernFlcn); } -void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[168]); +void gkflcnRegisterIntrService_IMPL(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[171]); -static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[168]) { +static inline void gkflcnRegisterIntrService_DISPATCH(struct OBJGPU *arg0, struct GenericKernelFalcon *arg1, IntrServiceRecord arg2[171]) { arg1->__gkflcnRegisterIntrService__(arg0, arg1, arg2); } diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.c b/src/nvidia/generated/g_kernel_fifo_nvoc.c index 4a8ae2bd56..4df672d0b6 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.c +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.c @@ -70,6 +70,14 @@ static NV_STATUS __nvoc_thunk_KernelFifo_engstateConstructEngine(struct OBJGPU * return kfifoConstructEngine(pGpu, (struct KernelFifo *)(((unsigned char *)pKernelFifo) - __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), engDesc); } +static NV_STATUS __nvoc_thunk_KernelFifo_engstateStateLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelFifo, NvU32 flags) { + return kfifoStateLoad(pGpu, (struct KernelFifo *)(((unsigned char *)pKernelFifo) - __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), flags); +} + +static NV_STATUS __nvoc_thunk_KernelFifo_engstateStateUnload(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelFifo, NvU32 flags) { + return kfifoStateUnload(pGpu, (struct KernelFifo *)(((unsigned char *)pKernelFifo) - __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), flags); +} + static NV_STATUS __nvoc_thunk_KernelFifo_engstateStateInitLocked(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelFifo) { return kfifoStateInitLocked(pGpu, (struct KernelFifo *)(((unsigned char *)pKernelFifo) - __nvoc_rtti_KernelFifo_OBJENGSTATE.offset)); } @@ -86,14 +94,6 @@ static NV_STATUS __nvoc_thunk_KernelFifo_engstateStatePreUnload(struct OBJGPU *p return kfifoStatePreUnload(pGpu, (struct KernelFifo *)(((unsigned char *)pKernelFifo) - __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), flags); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoStateLoad(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { - return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), arg0); -} - -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoStateUnload(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { - return engstateStateUnload(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kfifoStatePreLoad(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelFifo_OBJENGSTATE.offset), arg0); } @@ -249,6 +249,28 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoConstructEngine__ = &kfifoConstructEngine_IMPL; + // Hal function -- kfifoStateLoad + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kfifoStateLoad__ = &kfifoStateLoad_IMPL; + } + // default + else + { + pThis->__kfifoStateLoad__ = &kfifoStateLoad_56cd7a; + } + + // Hal function -- kfifoStateUnload + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kfifoStateUnload__ = &kfifoStateUnload_IMPL; + } + // default + else + { + pThis->__kfifoStateUnload__ = &kfifoStateUnload_56cd7a; + } + pThis->__kfifoStateInitLocked__ = &kfifoStateInitLocked_IMPL; pThis->__kfifoStateDestroy__ = &kfifoStateDestroy_IMPL; @@ -345,6 +367,16 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoRunlistGetBaseShift__ = &kfifoRunlistGetBaseShift_GA102; } + // Hal function -- kfifoGetUserdBar1MapStartOffset + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kfifoGetUserdBar1MapStartOffset__ = &kfifoGetUserdBar1MapStartOffset_VF; + } + else + { + pThis->__kfifoGetUserdBar1MapStartOffset__ = &kfifoGetUserdBar1MapStartOffset_4a4dee; + } + // Hal function -- kfifoGetMaxCeChannelGroups if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -355,8 +387,139 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__kfifoGetMaxCeChannelGroups__ = &kfifoGetMaxCeChannelGroups_GA100; } + // Hal function -- kfifoGetVChIdForSChId + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kfifoGetVChIdForSChId__ = &kfifoGetVChIdForSChId_c04480; + } + else + { + pThis->__kfifoGetVChIdForSChId__ = &kfifoGetVChIdForSChId_FWCLIENT; + } + + // Hal function -- kfifoProgramChIdTable + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kfifoProgramChIdTable__ = &kfifoProgramChIdTable_c04480; + } + else + { + pThis->__kfifoProgramChIdTable__ = &kfifoProgramChIdTable_56cd7a; + } + + // Hal function -- kfifoRecoverAllChannels + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kfifoRecoverAllChannels__ = &kfifoRecoverAllChannels_56cd7a; + } + else + { + pThis->__kfifoRecoverAllChannels__ = &kfifoRecoverAllChannels_92bfc3; + } + + // Hal function -- kfifoGetEnginePbdmaFaultIds + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kfifoGetEnginePbdmaFaultIds__ = &kfifoGetEnginePbdmaFaultIds_5baef9; + } + else + { + pThis->__kfifoGetEnginePbdmaFaultIds__ = &kfifoGetEnginePbdmaFaultIds_GA100; + } + + // Hal function -- kfifoGetNumPBDMAs + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kfifoGetNumPBDMAs__ = &kfifoGetNumPBDMAs_GM200; + } + else + { + pThis->__kfifoGetNumPBDMAs__ = &kfifoGetNumPBDMAs_GA100; + } + + // Hal function -- kfifoPrintPbdmaId + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kfifoPrintPbdmaId__ = &kfifoPrintPbdmaId_TU102; + } + else + { + pThis->__kfifoPrintPbdmaId__ = &kfifoPrintPbdmaId_GA100; + } + + // Hal function -- kfifoPrintInternalEngine + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfifoPrintInternalEngine__ = &kfifoPrintInternalEngine_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kfifoPrintInternalEngine__ = &kfifoPrintInternalEngine_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kfifoPrintInternalEngine__ = &kfifoPrintInternalEngine_AD102; + } + else + { + pThis->__kfifoPrintInternalEngine__ = &kfifoPrintInternalEngine_GA100; + } + + // Hal function -- kfifoPrintInternalEngineCheck + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GH100 */ + { + pThis->__kfifoPrintInternalEngineCheck__ = &kfifoPrintInternalEngineCheck_fa6e19; + } + else + { + pThis->__kfifoPrintInternalEngineCheck__ = &kfifoPrintInternalEngineCheck_GA100; + } + + // Hal function -- kfifoGetClientIdStringCommon + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfifoGetClientIdStringCommon__ = &kfifoGetClientIdStringCommon_GH100; + } + // default + else + { + pThis->__kfifoGetClientIdStringCommon__ = &kfifoGetClientIdStringCommon_95626c; + } + + // Hal function -- kfifoGetClientIdString + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kfifoGetClientIdString__ = &kfifoGetClientIdString_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kfifoGetClientIdString__ = &kfifoGetClientIdString_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kfifoGetClientIdString__ = &kfifoGetClientIdString_AD102; + } + else + { + pThis->__kfifoGetClientIdString__ = &kfifoGetClientIdString_GA100; + } + + // Hal function -- kfifoGetClientIdStringCheck + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kfifoGetClientIdStringCheck__ = &kfifoGetClientIdStringCheck_da47da; + } + else + { + pThis->__kfifoGetClientIdStringCheck__ = &kfifoGetClientIdStringCheck_GA100; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelFifo_engstateConstructEngine; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelFifo_engstateStateLoad; + + pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelFifo_engstateStateUnload; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelFifo_engstateStateInitLocked; pThis->__nvoc_base_OBJENGSTATE.__engstateStateDestroy__ = &__nvoc_thunk_KernelFifo_engstateStateDestroy; @@ -365,10 +528,6 @@ static void __nvoc_init_funcTable_KernelFifo_1(KernelFifo *pThis, RmHalspecOwner pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreUnload__ = &__nvoc_thunk_KernelFifo_engstateStatePreUnload; - pThis->__kfifoStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kfifoStateLoad; - - pThis->__kfifoStateUnload__ = &__nvoc_thunk_OBJENGSTATE_kfifoStateUnload; - pThis->__kfifoStatePreLoad__ = &__nvoc_thunk_OBJENGSTATE_kfifoStatePreLoad; pThis->__kfifoStatePostUnload__ = &__nvoc_thunk_OBJENGSTATE_kfifoStatePostUnload; @@ -397,23 +556,31 @@ void __nvoc_init_KernelFifo(KernelFifo *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_KernelFifo(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelFifo *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelFifo), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelFifo)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelFifo); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -431,16 +598,25 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_KernelFifo(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelFifo_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelFifo_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelFifo)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.h b/src/nvidia/generated/g_kernel_fifo_nvoc.h index 004b72ca42..b2394cbec1 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.h +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.h @@ -379,11 +379,16 @@ MAKE_LIST(FifoSchedulingHandlerEntryList, FifoSchedulingHandlerEntry); // // The actual GPU object definition // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_FIFO_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelFifo { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -391,6 +396,8 @@ struct KernelFifo { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelFifo *__nvoc_pbase_KernelFifo; NV_STATUS (*__kfifoConstructEngine__)(struct OBJGPU *, struct KernelFifo *, ENGDESCRIPTOR); + NV_STATUS (*__kfifoStateLoad__)(struct OBJGPU *, struct KernelFifo *, NvU32); + NV_STATUS (*__kfifoStateUnload__)(struct OBJGPU *, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStateInitLocked__)(struct OBJGPU *, struct KernelFifo *); void (*__kfifoStateDestroy__)(struct OBJGPU *, struct KernelFifo *); NV_STATUS (*__kfifoStatePostLoad__)(struct OBJGPU *, struct KernelFifo *, NvU32); @@ -403,9 +410,19 @@ struct KernelFifo { NV_STATUS (*__kfifoGenerateWorkSubmitToken__)(struct OBJGPU *, struct KernelFifo *, struct KernelChannel *, NvU32 *, NvBool); NV_STATUS (*__kfifoUpdateUsermodeDoorbell__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32); NvU32 (*__kfifoRunlistGetBaseShift__)(struct KernelFifo *); + NvU64 (*__kfifoGetUserdBar1MapStartOffset__)(struct OBJGPU *, struct KernelFifo *); NvU32 (*__kfifoGetMaxCeChannelGroups__)(struct OBJGPU *, struct KernelFifo *); - NV_STATUS (*__kfifoStateLoad__)(POBJGPU, struct KernelFifo *, NvU32); - NV_STATUS (*__kfifoStateUnload__)(POBJGPU, struct KernelFifo *, NvU32); + NV_STATUS (*__kfifoGetVChIdForSChId__)(struct OBJGPU *, struct KernelFifo *, NvU32, NvU32, NvU32, NvU32 *); + NV_STATUS (*__kfifoProgramChIdTable__)(struct OBJGPU *, struct KernelFifo *, CHID_MGR *, NvU32, NvU32, NvU32, struct Device *, NvU32, FIFO_ENGINE_LIST *); + NV_STATUS (*__kfifoRecoverAllChannels__)(struct OBJGPU *, struct KernelFifo *, NvU32); + NV_STATUS (*__kfifoGetEnginePbdmaFaultIds__)(struct OBJGPU *, struct KernelFifo *, ENGINE_INFO_TYPE, NvU32, NvU32 **, NvU32 *); + NvU32 (*__kfifoGetNumPBDMAs__)(struct OBJGPU *, struct KernelFifo *); + const char *(*__kfifoPrintPbdmaId__)(struct OBJGPU *, struct KernelFifo *, NvU32); + const char *(*__kfifoPrintInternalEngine__)(struct OBJGPU *, struct KernelFifo *, NvU32); + const char *(*__kfifoPrintInternalEngineCheck__)(struct OBJGPU *, struct KernelFifo *, NvU32); + const char *(*__kfifoGetClientIdStringCommon__)(struct OBJGPU *, struct KernelFifo *, FIFO_MMU_EXCEPTION_DATA *); + const char *(*__kfifoGetClientIdString__)(struct OBJGPU *, struct KernelFifo *, FIFO_MMU_EXCEPTION_DATA *); + const char *(*__kfifoGetClientIdStringCheck__)(struct OBJGPU *, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStatePreLoad__)(POBJGPU, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStatePostUnload__)(POBJGPU, struct KernelFifo *, NvU32); NV_STATUS (*__kfifoStateInitUnlocked__)(POBJGPU, struct KernelFifo *); @@ -448,7 +465,7 @@ struct KernelFifo { MEMORY_DESCRIPTOR *pBar1VF; MEMORY_DESCRIPTOR *pBar1PrivVF; MEMORY_DESCRIPTOR *pRegVF; - CTX_BUF_POOL_INFO *pRunlistBufPool[63]; + CTX_BUF_POOL_INFO *pRunlistBufPool[64]; MEMORY_DESCRIPTOR ***pppRunlistBufMemDesc; }; @@ -483,6 +500,10 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo**, Dynamic*, NvU32); __nvoc_objCreate_KernelFifo((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define kfifoConstructEngine(pGpu, pKernelFifo, engDesc) kfifoConstructEngine_DISPATCH(pGpu, pKernelFifo, engDesc) +#define kfifoStateLoad(pGpu, pKernelFifo, flags) kfifoStateLoad_DISPATCH(pGpu, pKernelFifo, flags) +#define kfifoStateLoad_HAL(pGpu, pKernelFifo, flags) kfifoStateLoad_DISPATCH(pGpu, pKernelFifo, flags) +#define kfifoStateUnload(pGpu, pKernelFifo, flags) kfifoStateUnload_DISPATCH(pGpu, pKernelFifo, flags) +#define kfifoStateUnload_HAL(pGpu, pKernelFifo, flags) kfifoStateUnload_DISPATCH(pGpu, pKernelFifo, flags) #define kfifoStateInitLocked(pGpu, pKernelFifo) kfifoStateInitLocked_DISPATCH(pGpu, pKernelFifo) #define kfifoStateDestroy(pGpu, pKernelFifo) kfifoStateDestroy_DISPATCH(pGpu, pKernelFifo) #define kfifoStatePostLoad(pGpu, pKernelFifo, flags) kfifoStatePostLoad_DISPATCH(pGpu, pKernelFifo, flags) @@ -505,10 +526,32 @@ NV_STATUS __nvoc_objCreate_KernelFifo(KernelFifo**, Dynamic*, NvU32); #define kfifoUpdateUsermodeDoorbell_HAL(arg0, arg1, workSubmitToken, runlisId) kfifoUpdateUsermodeDoorbell_DISPATCH(arg0, arg1, workSubmitToken, runlisId) #define kfifoRunlistGetBaseShift(pKernelFifo) kfifoRunlistGetBaseShift_DISPATCH(pKernelFifo) #define kfifoRunlistGetBaseShift_HAL(pKernelFifo) kfifoRunlistGetBaseShift_DISPATCH(pKernelFifo) +#define kfifoGetUserdBar1MapStartOffset(pGpu, pKernelFifo) kfifoGetUserdBar1MapStartOffset_DISPATCH(pGpu, pKernelFifo) +#define kfifoGetUserdBar1MapStartOffset_HAL(pGpu, pKernelFifo) kfifoGetUserdBar1MapStartOffset_DISPATCH(pGpu, pKernelFifo) #define kfifoGetMaxCeChannelGroups(pGpu, pKernelFifo) kfifoGetMaxCeChannelGroups_DISPATCH(pGpu, pKernelFifo) #define kfifoGetMaxCeChannelGroups_HAL(pGpu, pKernelFifo) kfifoGetMaxCeChannelGroups_DISPATCH(pGpu, pKernelFifo) -#define kfifoStateLoad(pGpu, pEngstate, arg0) kfifoStateLoad_DISPATCH(pGpu, pEngstate, arg0) -#define kfifoStateUnload(pGpu, pEngstate, arg0) kfifoStateUnload_DISPATCH(pGpu, pEngstate, arg0) +#define kfifoGetVChIdForSChId(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) kfifoGetVChIdForSChId_DISPATCH(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) +#define kfifoGetVChIdForSChId_HAL(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) kfifoGetVChIdForSChId_DISPATCH(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) +#define kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable_DISPATCH(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) +#define kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable_DISPATCH(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) +#define kfifoRecoverAllChannels(pGpu, pKernelFifo, gfid) kfifoRecoverAllChannels_DISPATCH(pGpu, pKernelFifo, gfid) +#define kfifoRecoverAllChannels_HAL(pGpu, pKernelFifo, gfid) kfifoRecoverAllChannels_DISPATCH(pGpu, pKernelFifo, gfid) +#define kfifoGetEnginePbdmaFaultIds(pGpu, pKernelFifo, arg0, arg1, arg2, arg3) kfifoGetEnginePbdmaFaultIds_DISPATCH(pGpu, pKernelFifo, arg0, arg1, arg2, arg3) +#define kfifoGetEnginePbdmaFaultIds_HAL(pGpu, pKernelFifo, arg0, arg1, arg2, arg3) kfifoGetEnginePbdmaFaultIds_DISPATCH(pGpu, pKernelFifo, arg0, arg1, arg2, arg3) +#define kfifoGetNumPBDMAs(pGpu, pKernelFifo) kfifoGetNumPBDMAs_DISPATCH(pGpu, pKernelFifo) +#define kfifoGetNumPBDMAs_HAL(pGpu, pKernelFifo) kfifoGetNumPBDMAs_DISPATCH(pGpu, pKernelFifo) +#define kfifoPrintPbdmaId(pGpu, pKernelFifo, pbdmaId) kfifoPrintPbdmaId_DISPATCH(pGpu, pKernelFifo, pbdmaId) +#define kfifoPrintPbdmaId_HAL(pGpu, pKernelFifo, pbdmaId) kfifoPrintPbdmaId_DISPATCH(pGpu, pKernelFifo, pbdmaId) +#define kfifoPrintInternalEngine(pGpu, pKernelFifo, arg0) kfifoPrintInternalEngine_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoPrintInternalEngine_HAL(pGpu, pKernelFifo, arg0) kfifoPrintInternalEngine_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoPrintInternalEngineCheck(pGpu, pKernelFifo, arg0) kfifoPrintInternalEngineCheck_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoPrintInternalEngineCheck_HAL(pGpu, pKernelFifo, arg0) kfifoPrintInternalEngineCheck_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetClientIdStringCommon(pGpu, pKernelFifo, arg0) kfifoGetClientIdStringCommon_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetClientIdStringCommon_HAL(pGpu, pKernelFifo, arg0) kfifoGetClientIdStringCommon_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetClientIdString(pGpu, pKernelFifo, arg0) kfifoGetClientIdString_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetClientIdString_HAL(pGpu, pKernelFifo, arg0) kfifoGetClientIdString_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetClientIdStringCheck(pGpu, pKernelFifo, arg0) kfifoGetClientIdStringCheck_DISPATCH(pGpu, pKernelFifo, arg0) +#define kfifoGetClientIdStringCheck_HAL(pGpu, pKernelFifo, arg0) kfifoGetClientIdStringCheck_DISPATCH(pGpu, pKernelFifo, arg0) #define kfifoStatePreLoad(pGpu, pEngstate, arg0) kfifoStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kfifoStatePostUnload(pGpu, pEngstate, arg0) kfifoStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kfifoStateInitUnlocked(pGpu, pEngstate) kfifoStateInitUnlocked_DISPATCH(pGpu, pEngstate) @@ -1092,22 +1135,6 @@ static inline void kfifoFreePreAllocUserD(struct OBJGPU *pGpu, struct KernelFifo #define kfifoFreePreAllocUserD_HAL(pGpu, pKernelFifo) kfifoFreePreAllocUserD(pGpu, pKernelFifo) -static inline NvU64 kfifoGetUserdBar1MapStartOffset_4a4dee(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { - return 0; -} - - -#ifdef __nvoc_kernel_fifo_h_disabled -static inline NvU64 kfifoGetUserdBar1MapStartOffset(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { - NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); - return 0; -} -#else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetUserdBar1MapStartOffset(pGpu, pKernelFifo) kfifoGetUserdBar1MapStartOffset_4a4dee(pGpu, pKernelFifo) -#endif //__nvoc_kernel_fifo_h_disabled - -#define kfifoGetUserdBar1MapStartOffset_HAL(pGpu, pKernelFifo) kfifoGetUserdBar1MapStartOffset(pGpu, pKernelFifo) - NV_STATUS kfifoGetUserdBar1MapInfo_GM107(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU64 *bar1Offset, NvU32 *bar1MapSize); @@ -1177,36 +1204,6 @@ static inline NV_STATUS kfifoCheckEngine(struct OBJGPU *pGpu, struct KernelFifo #define kfifoCheckEngine_HAL(pGpu, pKernelFifo, engDesc, pPresent) kfifoCheckEngine(pGpu, pKernelFifo, engDesc, pPresent) -NV_STATUS kfifoGetVChIdForSChId_FWCLIENT(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 chId, NvU32 gfid, NvU32 engineId, NvU32 *pVChid); - - -#ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoGetVChIdForSChId(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 chId, NvU32 gfid, NvU32 engineId, NvU32 *pVChid) { - NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_fifo_h_disabled -#define kfifoGetVChIdForSChId(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) kfifoGetVChIdForSChId_FWCLIENT(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) -#endif //__nvoc_kernel_fifo_h_disabled - -#define kfifoGetVChIdForSChId_HAL(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) kfifoGetVChIdForSChId(pGpu, pKernelFifo, chId, gfid, engineId, pVChid) - -static inline NV_STATUS kfifoProgramChIdTable_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { - return NV_OK; -} - - -#ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoProgramChIdTable(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { - NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_fifo_h_disabled -#define kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable_56cd7a(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) -#endif //__nvoc_kernel_fifo_h_disabled - -#define kfifoProgramChIdTable_HAL(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoProgramChIdTable(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList) - static inline NV_STATUS kfifoRestoreSchedPolicy_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { return NV_OK; } @@ -1278,12 +1275,46 @@ static inline void kfifoSetupUserD(struct OBJGPU *pGpu, struct KernelFifo *pKern #define kfifoSetupUserD_HAL(pGpu, pKernelFifo, pMemDesc) kfifoSetupUserD(pGpu, pKernelFifo, pMemDesc) +const char *kfifoGetFaultAccessTypeString_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0); + + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline const char *kfifoGetFaultAccessTypeString(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NULL; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoGetFaultAccessTypeString(pGpu, pKernelFifo, arg0) kfifoGetFaultAccessTypeString_GV100(pGpu, pKernelFifo, arg0) +#endif //__nvoc_kernel_fifo_h_disabled + +#define kfifoGetFaultAccessTypeString_HAL(pGpu, pKernelFifo, arg0) kfifoGetFaultAccessTypeString(pGpu, pKernelFifo, arg0) + NV_STATUS kfifoConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGDESCRIPTOR engDesc); static inline NV_STATUS kfifoConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGDESCRIPTOR engDesc) { return pKernelFifo->__kfifoConstructEngine__(pGpu, pKernelFifo, engDesc); } +NV_STATUS kfifoStateLoad_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags); + +static inline NV_STATUS kfifoStateLoad_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags) { + return NV_OK; +} + +static inline NV_STATUS kfifoStateLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags) { + return pKernelFifo->__kfifoStateLoad__(pGpu, pKernelFifo, flags); +} + +NV_STATUS kfifoStateUnload_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags); + +static inline NV_STATUS kfifoStateUnload_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags) { + return NV_OK; +} + +static inline NV_STATUS kfifoStateUnload_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 flags) { + return pKernelFifo->__kfifoStateUnload__(pGpu, pKernelFifo, flags); +} + NV_STATUS kfifoStateInitLocked_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); static inline NV_STATUS kfifoStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { @@ -1378,6 +1409,16 @@ static inline NvU32 kfifoRunlistGetBaseShift_DISPATCH(struct KernelFifo *pKernel return pKernelFifo->__kfifoRunlistGetBaseShift__(pKernelFifo); } +NvU64 kfifoGetUserdBar1MapStartOffset_VF(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + +static inline NvU64 kfifoGetUserdBar1MapStartOffset_4a4dee(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + return 0; +} + +static inline NvU64 kfifoGetUserdBar1MapStartOffset_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + return pKernelFifo->__kfifoGetUserdBar1MapStartOffset__(pGpu, pKernelFifo); +} + NvU32 kfifoGetMaxCeChannelGroups_GV100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); NvU32 kfifoGetMaxCeChannelGroups_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); @@ -1386,12 +1427,119 @@ static inline NvU32 kfifoGetMaxCeChannelGroups_DISPATCH(struct OBJGPU *pGpu, str return pKernelFifo->__kfifoGetMaxCeChannelGroups__(pGpu, pKernelFifo); } -static inline NV_STATUS kfifoStateLoad_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { - return pEngstate->__kfifoStateLoad__(pGpu, pEngstate, arg0); +static inline NV_STATUS kfifoGetVChIdForSChId_c04480(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 chId, NvU32 gfid, NvU32 engineId, NvU32 *pVChid) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -static inline NV_STATUS kfifoStateUnload_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { - return pEngstate->__kfifoStateUnload__(pGpu, pEngstate, arg0); +NV_STATUS kfifoGetVChIdForSChId_FWCLIENT(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 chId, NvU32 gfid, NvU32 engineId, NvU32 *pVChid); + +static inline NV_STATUS kfifoGetVChIdForSChId_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 chId, NvU32 gfid, NvU32 engineId, NvU32 *pVChid) { + return pKernelFifo->__kfifoGetVChIdForSChId__(pGpu, pKernelFifo, chId, gfid, engineId, pVChid); +} + +static inline NV_STATUS kfifoProgramChIdTable_c04480(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kfifoProgramChIdTable_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { + return NV_OK; +} + +static inline NV_STATUS kfifoProgramChIdTable_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 offset, NvU32 numChannels, NvU32 gfid, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { + return pKernelFifo->__kfifoProgramChIdTable__(pGpu, pKernelFifo, pChidMgr, offset, numChannels, gfid, pMigDevice, engineFifoListNumEntries, pEngineFifoList); +} + +static inline NV_STATUS kfifoRecoverAllChannels_56cd7a(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 gfid) { + return NV_OK; +} + +static inline NV_STATUS kfifoRecoverAllChannels_92bfc3(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 gfid) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS kfifoRecoverAllChannels_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 gfid) { + return pKernelFifo->__kfifoRecoverAllChannels__(pGpu, pKernelFifo, gfid); +} + +NV_STATUS kfifoGetEnginePbdmaFaultIds_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE arg0, NvU32 arg1, NvU32 **arg2, NvU32 *arg3); + +static inline NV_STATUS kfifoGetEnginePbdmaFaultIds_5baef9(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE arg0, NvU32 arg1, NvU32 **arg2, NvU32 *arg3) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kfifoGetEnginePbdmaFaultIds_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, ENGINE_INFO_TYPE arg0, NvU32 arg1, NvU32 **arg2, NvU32 *arg3) { + return pKernelFifo->__kfifoGetEnginePbdmaFaultIds__(pGpu, pKernelFifo, arg0, arg1, arg2, arg3); +} + +NvU32 kfifoGetNumPBDMAs_GM200(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + +NvU32 kfifoGetNumPBDMAs_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo); + +static inline NvU32 kfifoGetNumPBDMAs_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo) { + return pKernelFifo->__kfifoGetNumPBDMAs__(pGpu, pKernelFifo); +} + +const char *kfifoPrintPbdmaId_TU102(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 pbdmaId); + +const char *kfifoPrintPbdmaId_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 pbdmaId); + +static inline const char *kfifoPrintPbdmaId_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 pbdmaId) { + return pKernelFifo->__kfifoPrintPbdmaId__(pGpu, pKernelFifo, pbdmaId); +} + +const char *kfifoPrintInternalEngine_TU102(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0); + +const char *kfifoPrintInternalEngine_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0); + +const char *kfifoPrintInternalEngine_AD102(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0); + +const char *kfifoPrintInternalEngine_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0); + +static inline const char *kfifoPrintInternalEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0) { + return pKernelFifo->__kfifoPrintInternalEngine__(pGpu, pKernelFifo, arg0); +} + +const char *kfifoPrintInternalEngineCheck_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0); + +static inline const char *kfifoPrintInternalEngineCheck_fa6e19(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0) { + return ((void *)0); +} + +static inline const char *kfifoPrintInternalEngineCheck_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0) { + return pKernelFifo->__kfifoPrintInternalEngineCheck__(pGpu, pKernelFifo, arg0); +} + +const char *kfifoGetClientIdStringCommon_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_MMU_EXCEPTION_DATA *arg0); + +static inline const char *kfifoGetClientIdStringCommon_95626c(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_MMU_EXCEPTION_DATA *arg0) { + NV_ASSERT_OR_RETURN_PRECOMP(0, "UNKNOWN"); +} + +static inline const char *kfifoGetClientIdStringCommon_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_MMU_EXCEPTION_DATA *arg0) { + return pKernelFifo->__kfifoGetClientIdStringCommon__(pGpu, pKernelFifo, arg0); +} + +const char *kfifoGetClientIdString_TU102(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_MMU_EXCEPTION_DATA *arg0); + +const char *kfifoGetClientIdString_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_MMU_EXCEPTION_DATA *arg0); + +const char *kfifoGetClientIdString_AD102(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_MMU_EXCEPTION_DATA *arg0); + +const char *kfifoGetClientIdString_GH100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_MMU_EXCEPTION_DATA *arg0); + +static inline const char *kfifoGetClientIdString_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, FIFO_MMU_EXCEPTION_DATA *arg0) { + return pKernelFifo->__kfifoGetClientIdString__(pGpu, pKernelFifo, arg0); +} + +const char *kfifoGetClientIdStringCheck_GA100(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0); + +static inline const char *kfifoGetClientIdStringCheck_da47da(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0) { + return "UNKNOWN"; +} + +static inline const char *kfifoGetClientIdStringCheck_DISPATCH(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0) { + return pKernelFifo->__kfifoGetClientIdStringCheck__(pGpu, pKernelFifo, arg0); } static inline NV_STATUS kfifoStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelFifo *pEngstate, NvU32 arg0) { @@ -1556,15 +1704,15 @@ static inline NV_STATUS kfifoChidMgrFreeChid(struct OBJGPU *pGpu, struct KernelF #define kfifoChidMgrFreeChid(pGpu, pKernelFifo, pChidMgr, ChID) kfifoChidMgrFreeChid_IMPL(pGpu, pKernelFifo, pChidMgr, ChID) #endif //__nvoc_kernel_fifo_h_disabled -NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); +NV_STATUS kfifoChidMgrReserveSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU64 offset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); #ifdef __nvoc_kernel_fifo_h_disabled -static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { +static inline NV_STATUS kfifoChidMgrReserveSystemChids(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 numChannels, NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, NvU64 offset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList) { NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_fifo_h_disabled -#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) +#define kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, offset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) kfifoChidMgrReserveSystemChids_IMPL(pGpu, pKernelFifo, pChidMgr, numChannels, flags, gfid, pChidOffset, offset, pChannelCount, pMigDevice, engineFifoListNumEntries, pEngineFifoList) #endif //__nvoc_kernel_fifo_h_disabled NV_STATUS kfifoChidMgrFreeSystemChids_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, CHID_MGR *pChidMgr, NvU32 gfid, NvU32 *pChidOffset, NvU32 *pChannelCount, struct Device *pMigDevice, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *pEngineFifoList); @@ -1940,6 +2088,39 @@ static inline NvU32 kfifoGetChannelClassId(struct OBJGPU *pGpu, struct KernelFif #define kfifoGetChannelClassId(pGpu, pKernelFifo) kfifoGetChannelClassId_IMPL(pGpu, pKernelFifo) #endif //__nvoc_kernel_fifo_h_disabled +NvBool kfifoIsMmuFaultEngineIdPbdma_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0); + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NvBool kfifoIsMmuFaultEngineIdPbdma(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoIsMmuFaultEngineIdPbdma(pGpu, pKernelFifo, arg0) kfifoIsMmuFaultEngineIdPbdma_IMPL(pGpu, pKernelFifo, arg0) +#endif //__nvoc_kernel_fifo_h_disabled + +NV_STATUS kfifoGetPbdmaIdFromMmuFaultId_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0, NvU32 *arg1); + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoGetPbdmaIdFromMmuFaultId(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0, NvU32 *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoGetPbdmaIdFromMmuFaultId(pGpu, pKernelFifo, arg0, arg1) kfifoGetPbdmaIdFromMmuFaultId_IMPL(pGpu, pKernelFifo, arg0, arg1) +#endif //__nvoc_kernel_fifo_h_disabled + +NV_STATUS kfifoGetEngineTypeFromPbdmaFaultId_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0, RM_ENGINE_TYPE *arg1); + +#ifdef __nvoc_kernel_fifo_h_disabled +static inline NV_STATUS kfifoGetEngineTypeFromPbdmaFaultId(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, NvU32 arg0, RM_ENGINE_TYPE *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelFifo was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_fifo_h_disabled +#define kfifoGetEngineTypeFromPbdmaFaultId(pGpu, pKernelFifo, arg0, arg1) kfifoGetEngineTypeFromPbdmaFaultId_IMPL(pGpu, pKernelFifo, arg0, arg1) +#endif //__nvoc_kernel_fifo_h_disabled + NV_STATUS kfifoChannelGroupSetTimeslice_IMPL(struct OBJGPU *pGpu, struct KernelFifo *pKernelFifo, struct KernelChannelGroup *pKernelChannelGroup, NvU64 timesliceUs, NvBool bSkipSubmit); #ifdef __nvoc_kernel_fifo_h_disabled diff --git a/src/nvidia/generated/g_kernel_graphics_context_nvoc.c b/src/nvidia/generated/g_kernel_graphics_context_nvoc.c index 1a8c9950a4..9012d3cc9d 100644 --- a/src/nvidia/generated/g_kernel_graphics_context_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_context_nvoc.c @@ -145,10 +145,6 @@ static void __nvoc_thunk_RmResource_kgrctxControl_Epilogue(struct KernelGraphics rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kgrctxControlLookup(struct KernelGraphicsContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_GpuResource_kgrctxControl(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelGraphicsContext_GpuResource.offset), pCallContext, pParams); } @@ -173,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RmResource_kgrctxControlSerialization_Prologue(str return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_kgrctxIsPartialUnmapSupported(struct KernelGraphicsContext *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_kgrctxPreDestruct(struct KernelGraphicsContext *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsContext_RsResource.offset)); } @@ -323,6 +323,26 @@ static void __nvoc_init_funcTable_KernelGraphicsContext_1(KernelGraphicsContext pThis->__kgrctxGetInternalObjectHandle__ = &kgrctxGetInternalObjectHandle_IMPL; + // Hal function -- kgrctxShouldPreAllocPmBuffer + if (((( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ && (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ )) + { + pThis->__kgrctxShouldPreAllocPmBuffer__ = &kgrctxShouldPreAllocPmBuffer_VF; + } + else + { + pThis->__kgrctxShouldPreAllocPmBuffer__ = &kgrctxShouldPreAllocPmBuffer_PF; + } + + // Hal function -- kgrctxGetRegisterAccessMapId + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgrctxGetRegisterAccessMapId__ = &kgrctxGetRegisterAccessMapId_aa21e9; + } + else + { + pThis->__kgrctxGetRegisterAccessMapId__ = &kgrctxGetRegisterAccessMapId_PF; + } + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__kgrctxCtrlGetTpcPartitionMode__ = &kgrctxCtrlGetTpcPartitionMode_IMPL; #endif @@ -365,8 +385,6 @@ static void __nvoc_init_funcTable_KernelGraphicsContext_1(KernelGraphicsContext pThis->__kgrctxControl_Epilogue__ = &__nvoc_thunk_RmResource_kgrctxControl_Epilogue; - pThis->__kgrctxControlLookup__ = &__nvoc_thunk_RsResource_kgrctxControlLookup; - pThis->__kgrctxControl__ = &__nvoc_thunk_GpuResource_kgrctxControl; pThis->__kgrctxUnmap__ = &__nvoc_thunk_GpuResource_kgrctxUnmap; @@ -379,6 +397,8 @@ static void __nvoc_init_funcTable_KernelGraphicsContext_1(KernelGraphicsContext pThis->__kgrctxControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kgrctxControlSerialization_Prologue; + pThis->__kgrctxIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_kgrctxIsPartialUnmapSupported; + pThis->__kgrctxPreDestruct__ = &__nvoc_thunk_RsResource_kgrctxPreDestruct; pThis->__kgrctxIsDuplicate__ = &__nvoc_thunk_RsResource_kgrctxIsDuplicate; @@ -406,23 +426,31 @@ void __nvoc_init_KernelGraphicsContext(KernelGraphicsContext *pThis, RmHalspecOw __nvoc_init_funcTable_KernelGraphicsContext(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelGraphicsContext *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsContext), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelGraphicsContext)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsContext); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -440,16 +468,25 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext **ppThis, status = __nvoc_ctor_KernelGraphicsContext(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsContext_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelGraphicsContext_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelGraphicsContext)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -577,21 +614,26 @@ void __nvoc_init_KernelGraphicsContextShared(KernelGraphicsContextShared *pThis) __nvoc_init_funcTable_KernelGraphicsContextShared(pThis); } -NV_STATUS __nvoc_objCreate_KernelGraphicsContextShared(KernelGraphicsContextShared **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelGraphicsContextShared(KernelGraphicsContextShared **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelGraphicsContextShared *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsContextShared), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelGraphicsContextShared)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsContextShared); pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -606,16 +648,25 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContextShared(KernelGraphicsContextShar status = __nvoc_ctor_KernelGraphicsContextShared(pThis); if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsContextShared_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelGraphicsContextShared_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelGraphicsContextShared)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h index bdc0136527..2e21723ac7 100644 --- a/src/nvidia/generated/g_kernel_graphics_context_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_context_nvoc.h @@ -103,6 +103,16 @@ typedef enum GR_OBJECT_TYPE_INVALID, } GR_OBJECT_TYPE; +/* Structure used when allocating/deallocating GFxP buffers for vGPU */ +typedef struct VGPU_GFXP_BUFFERS +{ + NvBool bIsBufferAllocated; + NvU32 refCountChannel; /* count of channels using these buffers */ + NvHandle hMemory[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; + NvHandle hDma[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; + NvU64 dmaOffset[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; +} VGPU_GFXP_BUFFERS; + typedef struct { MEMORY_DESCRIPTOR *memDesc[GR_GLOBALCTX_BUFFER_COUNT]; @@ -158,11 +168,16 @@ typedef struct KernelGraphicsObject KernelGraphicsObject; * this object, and any interfaces which do not manage the underlying HW can be managed * by this object. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelGraphicsContext { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -174,6 +189,8 @@ struct KernelGraphicsContext { struct KernelGraphicsContext *__nvoc_pbase_KernelGraphicsContext; NvBool (*__kgrctxCanCopy__)(struct KernelGraphicsContext *); NvHandle (*__kgrctxGetInternalObjectHandle__)(struct KernelGraphicsContext *); + NvBool (*__kgrctxShouldPreAllocPmBuffer__)(struct OBJGPU *, struct KernelGraphicsContext *, struct KernelChannel *); + GR_GLOBALCTX_BUFFER (*__kgrctxGetRegisterAccessMapId__)(struct OBJGPU *, struct KernelGraphicsContext *, struct KernelChannel *); NV_STATUS (*__kgrctxCtrlGetTpcPartitionMode__)(struct KernelGraphicsContext *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); NV_STATUS (*__kgrctxCtrlSetTpcPartitionMode__)(struct KernelGraphicsContext *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); NV_STATUS (*__kgrctxCtrlGetMMUDebugMode__)(struct KernelGraphicsContext *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); @@ -189,19 +206,64 @@ struct KernelGraphicsContext { NV_STATUS (*__kgrctxInternalControlForward__)(struct KernelGraphicsContext *, NvU32, void *, NvU32); NV_STATUS (*__kgrctxUnmapFrom__)(struct KernelGraphicsContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kgrctxControl_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kgrctxControlLookup__)(struct KernelGraphicsContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kgrctxControl__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxUnmap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__kgrctxGetMemInterMapParams__)(struct KernelGraphicsContext *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__kgrctxGetMemoryMappingDescriptor__)(struct KernelGraphicsContext *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__kgrctxControlFilter__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxControlSerialization_Prologue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__kgrctxIsPartialUnmapSupported__)(struct KernelGraphicsContext *); void (*__kgrctxPreDestruct__)(struct KernelGraphicsContext *); NV_STATUS (*__kgrctxIsDuplicate__)(struct KernelGraphicsContext *, NvHandle, NvBool *); void (*__kgrctxControlSerialization_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kgrctxMap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__kgrctxAccessCallback__)(struct KernelGraphicsContext *, struct RsClient *, void *, RsAccessRight); struct KernelGraphicsContextShared *PRIVATE_FIELD(pShared); + VGPU_GFXP_BUFFERS *PRIVATE_FIELD(pVgpuGfxpBuffers); +}; + +struct KernelGraphicsContext_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct KernelGraphicsContext *__nvoc_pbase_KernelGraphicsContext; + NvBool (*__kgrctxCanCopy__)(struct KernelGraphicsContext *); + NvHandle (*__kgrctxGetInternalObjectHandle__)(struct KernelGraphicsContext *); + NvBool (*__kgrctxShouldPreAllocPmBuffer__)(struct OBJGPU *, struct KernelGraphicsContext *, struct KernelChannel *); + GR_GLOBALCTX_BUFFER (*__kgrctxGetRegisterAccessMapId__)(struct OBJGPU *, struct KernelGraphicsContext *, struct KernelChannel *); + NV_STATUS (*__kgrctxCtrlGetTpcPartitionMode__)(struct KernelGraphicsContext *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); + NV_STATUS (*__kgrctxCtrlSetTpcPartitionMode__)(struct KernelGraphicsContext *, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *); + NV_STATUS (*__kgrctxCtrlGetMMUDebugMode__)(struct KernelGraphicsContext *, NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *); + NV_STATUS (*__kgrctxCtrlProgramVidmemPromote__)(struct KernelGraphicsContext *, NV0090_CTRL_PROGRAM_VIDMEM_PROMOTE_PARAMS *); + NvBool (*__kgrctxShareCallback__)(struct KernelGraphicsContext *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__kgrctxCheckMemInterUnmap__)(struct KernelGraphicsContext *, NvBool); + NV_STATUS (*__kgrctxMapTo__)(struct KernelGraphicsContext *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__kgrctxGetMapAddrSpace__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__kgrctxGetRefCount__)(struct KernelGraphicsContext *); + void (*__kgrctxAddAdditionalDependants__)(struct RsClient *, struct KernelGraphicsContext *, RsResourceRef *); + NV_STATUS (*__kgrctxControl_Prologue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxGetRegBaseOffsetAndSize__)(struct KernelGraphicsContext *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__kgrctxInternalControlForward__)(struct KernelGraphicsContext *, NvU32, void *, NvU32); + NV_STATUS (*__kgrctxUnmapFrom__)(struct KernelGraphicsContext *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__kgrctxControl_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxControl__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxUnmap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__kgrctxGetMemInterMapParams__)(struct KernelGraphicsContext *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__kgrctxGetMemoryMappingDescriptor__)(struct KernelGraphicsContext *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__kgrctxControlFilter__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxControlSerialization_Prologue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__kgrctxIsPartialUnmapSupported__)(struct KernelGraphicsContext *); + void (*__kgrctxPreDestruct__)(struct KernelGraphicsContext *); + NV_STATUS (*__kgrctxIsDuplicate__)(struct KernelGraphicsContext *, NvHandle, NvBool *); + void (*__kgrctxControlSerialization_Epilogue__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__kgrctxMap__)(struct KernelGraphicsContext *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__kgrctxAccessCallback__)(struct KernelGraphicsContext *, struct RsClient *, void *, RsAccessRight); + struct KernelGraphicsContextShared *pShared; + VGPU_GFXP_BUFFERS *pVgpuGfxpBuffers; }; #ifndef __NVOC_CLASS_KernelGraphicsContext_TYPEDEF__ @@ -234,6 +296,10 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext**, Dynami #define kgrctxCanCopy(arg0) kgrctxCanCopy_DISPATCH(arg0) #define kgrctxGetInternalObjectHandle(arg0) kgrctxGetInternalObjectHandle_DISPATCH(arg0) +#define kgrctxShouldPreAllocPmBuffer(pGpu, pKernelGraphicsContext, pKernelChannel) kgrctxShouldPreAllocPmBuffer_DISPATCH(pGpu, pKernelGraphicsContext, pKernelChannel) +#define kgrctxShouldPreAllocPmBuffer_HAL(pGpu, pKernelGraphicsContext, pKernelChannel) kgrctxShouldPreAllocPmBuffer_DISPATCH(pGpu, pKernelGraphicsContext, pKernelChannel) +#define kgrctxGetRegisterAccessMapId(arg0, arg1, arg2) kgrctxGetRegisterAccessMapId_DISPATCH(arg0, arg1, arg2) +#define kgrctxGetRegisterAccessMapId_HAL(arg0, arg1, arg2) kgrctxGetRegisterAccessMapId_DISPATCH(arg0, arg1, arg2) #define kgrctxCtrlGetTpcPartitionMode(pKernelGraphicsContext, pParams) kgrctxCtrlGetTpcPartitionMode_DISPATCH(pKernelGraphicsContext, pParams) #define kgrctxCtrlSetTpcPartitionMode(pKernelGraphicsContext, pParams) kgrctxCtrlSetTpcPartitionMode_DISPATCH(pKernelGraphicsContext, pParams) #define kgrctxCtrlGetMMUDebugMode(pKernelGraphicsContext, pParams) kgrctxCtrlGetMMUDebugMode_DISPATCH(pKernelGraphicsContext, pParams) @@ -249,13 +315,13 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsContext(KernelGraphicsContext**, Dynami #define kgrctxInternalControlForward(pGpuResource, command, pParams, size) kgrctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kgrctxUnmapFrom(pResource, pParams) kgrctxUnmapFrom_DISPATCH(pResource, pParams) #define kgrctxControl_Epilogue(pResource, pCallContext, pParams) kgrctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kgrctxControlLookup(pResource, pParams, ppEntry) kgrctxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kgrctxControl(pGpuResource, pCallContext, pParams) kgrctxControl_DISPATCH(pGpuResource, pCallContext, pParams) #define kgrctxUnmap(pGpuResource, pCallContext, pCpuMapping) kgrctxUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define kgrctxGetMemInterMapParams(pRmResource, pParams) kgrctxGetMemInterMapParams_DISPATCH(pRmResource, pParams) #define kgrctxGetMemoryMappingDescriptor(pRmResource, ppMemDesc) kgrctxGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define kgrctxControlFilter(pResource, pCallContext, pParams) kgrctxControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kgrctxControlSerialization_Prologue(pResource, pCallContext, pParams) kgrctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kgrctxIsPartialUnmapSupported(pResource) kgrctxIsPartialUnmapSupported_DISPATCH(pResource) #define kgrctxPreDestruct(pResource) kgrctxPreDestruct_DISPATCH(pResource) #define kgrctxIsDuplicate(pResource, hMemory, pDuplicate) kgrctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kgrctxControlSerialization_Epilogue(pResource, pCallContext, pParams) kgrctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -289,20 +355,6 @@ static inline NvBool kgrctxShouldCleanup(struct OBJGPU *pGpu, struct KernelGraph #define kgrctxShouldCleanup_HAL(pGpu, pKernelGraphicsContext) kgrctxShouldCleanup(pGpu, pKernelGraphicsContext) -NvBool kgrctxShouldPreAllocPmBuffer_PF(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext, struct KernelChannel *pKernelChannel); - - -#ifdef __nvoc_kernel_graphics_context_h_disabled -static inline NvBool kgrctxShouldPreAllocPmBuffer(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext, struct KernelChannel *pKernelChannel) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_graphics_context_h_disabled -#define kgrctxShouldPreAllocPmBuffer(pGpu, pKernelGraphicsContext, pKernelChannel) kgrctxShouldPreAllocPmBuffer_PF(pGpu, pKernelGraphicsContext, pKernelChannel) -#endif //__nvoc_kernel_graphics_context_h_disabled - -#define kgrctxShouldPreAllocPmBuffer_HAL(pGpu, pKernelGraphicsContext, pKernelChannel) kgrctxShouldPreAllocPmBuffer(pGpu, pKernelGraphicsContext, pKernelChannel) - void kgrctxUnmapBuffers_KERNEL(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, KernelGraphicsContextUnicast *arg2, struct KernelChannel *arg3); @@ -356,22 +408,6 @@ static inline void kgrctxDecObjectCount(struct OBJGPU *arg0, struct KernelGraphi #define kgrctxDecObjectCount_HAL(arg0, arg1, classNum) kgrctxDecObjectCount(arg0, arg1, classNum) -GR_GLOBALCTX_BUFFER kgrctxGetRegisterAccessMapId_PF(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2); - - -#ifdef __nvoc_kernel_graphics_context_h_disabled -static inline GR_GLOBALCTX_BUFFER kgrctxGetRegisterAccessMapId(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphicsContext was disabled!"); - GR_GLOBALCTX_BUFFER ret; - portMemSet(&ret, 0, sizeof(GR_GLOBALCTX_BUFFER)); - return ret; -} -#else //__nvoc_kernel_graphics_context_h_disabled -#define kgrctxGetRegisterAccessMapId(arg0, arg1, arg2) kgrctxGetRegisterAccessMapId_PF(arg0, arg1, arg2) -#endif //__nvoc_kernel_graphics_context_h_disabled - -#define kgrctxGetRegisterAccessMapId_HAL(arg0, arg1, arg2) kgrctxGetRegisterAccessMapId(arg0, arg1, arg2) - static inline NvBool kgrctxCanCopy_0c883b(struct KernelGraphicsContext *arg0) { return ((NvBool)(0 == 0)); } @@ -386,6 +422,24 @@ static inline NvHandle kgrctxGetInternalObjectHandle_DISPATCH(struct KernelGraph return arg0->__kgrctxGetInternalObjectHandle__(arg0); } +NvBool kgrctxShouldPreAllocPmBuffer_VF(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext, struct KernelChannel *pKernelChannel); + +NvBool kgrctxShouldPreAllocPmBuffer_PF(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext, struct KernelChannel *pKernelChannel); + +static inline NvBool kgrctxShouldPreAllocPmBuffer_DISPATCH(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext, struct KernelChannel *pKernelChannel) { + return pKernelGraphicsContext->__kgrctxShouldPreAllocPmBuffer__(pGpu, pKernelGraphicsContext, pKernelChannel); +} + +static inline GR_GLOBALCTX_BUFFER kgrctxGetRegisterAccessMapId_aa21e9(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2) { + return GR_GLOBALCTX_BUFFER_PRIV_ACCESS_MAP; +} + +GR_GLOBALCTX_BUFFER kgrctxGetRegisterAccessMapId_PF(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2); + +static inline GR_GLOBALCTX_BUFFER kgrctxGetRegisterAccessMapId_DISPATCH(struct OBJGPU *arg0, struct KernelGraphicsContext *arg1, struct KernelChannel *arg2) { + return arg1->__kgrctxGetRegisterAccessMapId__(arg0, arg1, arg2); +} + NV_STATUS kgrctxCtrlGetTpcPartitionMode_IMPL(struct KernelGraphicsContext *pKernelGraphicsContext, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *pParams); static inline NV_STATUS kgrctxCtrlGetTpcPartitionMode_DISPATCH(struct KernelGraphicsContext *pKernelGraphicsContext, NV0090_CTRL_TPC_PARTITION_MODE_PARAMS *pParams) { @@ -454,10 +508,6 @@ static inline void kgrctxControl_Epilogue_DISPATCH(struct KernelGraphicsContext pResource->__kgrctxControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS kgrctxControlLookup_DISPATCH(struct KernelGraphicsContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kgrctxControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS kgrctxControl_DISPATCH(struct KernelGraphicsContext *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__kgrctxControl__(pGpuResource, pCallContext, pParams); } @@ -482,6 +532,10 @@ static inline NV_STATUS kgrctxControlSerialization_Prologue_DISPATCH(struct Kern return pResource->__kgrctxControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool kgrctxIsPartialUnmapSupported_DISPATCH(struct KernelGraphicsContext *pResource) { + return pResource->__kgrctxIsPartialUnmapSupported__(pResource); +} + static inline void kgrctxPreDestruct_DISPATCH(struct KernelGraphicsContext *pResource) { pResource->__kgrctxPreDestruct__(pResource); } @@ -502,6 +556,21 @@ static inline NvBool kgrctxAccessCallback_DISPATCH(struct KernelGraphicsContext return pResource->__kgrctxAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } +static inline struct KernelGraphicsContextShared *kgrctxGetShared(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext) { + struct KernelGraphicsContext_PRIVATE *pKernelGraphicsContext_PRIVATE = (struct KernelGraphicsContext_PRIVATE *)pKernelGraphicsContext; + return pKernelGraphicsContext_PRIVATE->pShared; +} + +static inline VGPU_GFXP_BUFFERS *kgrctxGetVgpuGfxpBuffers(struct OBJGPU *pGpu, struct KernelGraphicsContext *pKernelGraphicsContext) { + struct KernelGraphicsContext_PRIVATE *pKernelGraphicsContext_PRIVATE = (struct KernelGraphicsContext_PRIVATE *)pKernelGraphicsContext; + return pKernelGraphicsContext_PRIVATE->pVgpuGfxpBuffers; +} + +static inline void kgrctxSetVgpuGfxpBuffers(struct KernelGraphicsContext *pKernelGraphicsContext, VGPU_GFXP_BUFFERS *pBuffers) { + struct KernelGraphicsContext_PRIVATE *pKernelGraphicsContext_PRIVATE = (struct KernelGraphicsContext_PRIVATE *)pKernelGraphicsContext; + pKernelGraphicsContext_PRIVATE->pVgpuGfxpBuffers = pBuffers; +} + NV_STATUS kgrctxFromKernelChannel_IMPL(struct KernelChannel *arg0, struct KernelGraphicsContext **arg1); #define kgrctxFromKernelChannel(arg0, arg1) kgrctxFromKernelChannel_IMPL(arg0, arg1) @@ -978,11 +1047,16 @@ static inline void kgrctxFreeAssociatedCtxBuffers(struct OBJGPU *arg0, struct Ke * This refcounted class encapsulates the context data that is shared when a * context is duped. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelGraphicsContextUnicast { NvU32 channelObjects; NvU32 objectCounts[4]; @@ -1000,6 +1074,7 @@ struct KernelGraphicsContextUnicast { NV_CONTEXT_BUFFER betaCBCtxswBuffer; NV_CONTEXT_BUFFER pagepoolCtxswBuffer; NV_CONTEXT_BUFFER rtvCbCtxswBuffer; + NV_CONTEXT_BUFFER setupCtxswBuffer; NvBool bVprChannel; NvBool bSupportsPerSubctxHeader; struct MMU_FAULT_INFO { diff --git a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c index 655bfe2eb9..329e1ec70a 100644 --- a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.c @@ -221,23 +221,31 @@ void __nvoc_init_KernelGraphicsManager(KernelGraphicsManager *pThis, RmHalspecOw __nvoc_init_funcTable_KernelGraphicsManager(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelGraphicsManager *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsManager), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelGraphicsManager)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsManager); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -255,16 +263,25 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsManager(KernelGraphicsManager **ppThis, status = __nvoc_ctor_KernelGraphicsManager(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsManager_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelGraphicsManager_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelGraphicsManager)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h index ecbd867018..a38ee1c787 100644 --- a/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_manager_nvoc.h @@ -54,16 +54,23 @@ typedef struct GRMGR_LEGACY_KGRAPHICS_STATIC_INFO NvBool bInitialized; } GRMGR_LEGACY_KGRAPHICS_STATIC_INFO; +typedef struct KGRMGR_FECS_GLOBAL_TRACE_INFO KGRMGR_FECS_GLOBAL_TRACE_INFO; +typedef struct KGRMGR_FECS_VGPU_GLOBAL_TRACE_INFO KGRMGR_FECS_VGPU_GLOBAL_TRACE_INFO; /*! * KernelGraphicsManager provides means to access KernelGraphics engine with specified index. * It also houses information at a higher level or that is common between KernelGraphics engines. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelGraphicsManager { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -86,9 +93,10 @@ struct KernelGraphicsManager { NV_STATUS (*__kgrmgrStatePostLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NvBool (*__kgrmgrIsPresent__)(POBJGPU, struct KernelGraphicsManager *); GRMGR_LEGACY_KGRAPHICS_STATIC_INFO PRIVATE_FIELD(legacyKgraphicsStaticInfo); - NvU32 PRIVATE_FIELD(fecsCallbackScheduled); NvU64 PRIVATE_FIELD(veidInUseMask); NvU64 PRIVATE_FIELD(grIdxVeidMask)[8]; + KGRMGR_FECS_GLOBAL_TRACE_INFO *PRIVATE_FIELD(pFecsGlobalTraceInfo); + KGRMGR_FECS_VGPU_GLOBAL_TRACE_INFO *PRIVATE_FIELD(pFecsVgpuGlobalTraceInfo); CTX_BUF_INFO PRIVATE_FIELD(globalCtxBufInfo)[10]; }; @@ -114,9 +122,10 @@ struct KernelGraphicsManager_PRIVATE { NV_STATUS (*__kgrmgrStatePostLoad__)(POBJGPU, struct KernelGraphicsManager *, NvU32); NvBool (*__kgrmgrIsPresent__)(POBJGPU, struct KernelGraphicsManager *); GRMGR_LEGACY_KGRAPHICS_STATIC_INFO legacyKgraphicsStaticInfo; - NvU32 fecsCallbackScheduled; NvU64 veidInUseMask; NvU64 grIdxVeidMask[8]; + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo; + KGRMGR_FECS_VGPU_GLOBAL_TRACE_INFO *pFecsVgpuGlobalTraceInfo; CTX_BUF_INFO globalCtxBufInfo[10]; }; @@ -259,6 +268,16 @@ static inline void kgrmgrSetVeidInUseMask(OBJGPU *pGpu, struct KernelGraphicsMan pKernelGraphicsManager_PRIVATE->veidInUseMask = mask; } +static inline KGRMGR_FECS_GLOBAL_TRACE_INFO *kgrmgrGetFecsGlobalTraceInfo(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager) { + struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; + return pKernelGraphicsManager_PRIVATE->pFecsGlobalTraceInfo; +} + +static inline KGRMGR_FECS_VGPU_GLOBAL_TRACE_INFO *kgrmgrGetFecsVgpuGlobalTraceInfo(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager) { + struct KernelGraphicsManager_PRIVATE *pKernelGraphicsManager_PRIVATE = (struct KernelGraphicsManager_PRIVATE *)pKernelGraphicsManager; + return pKernelGraphicsManager_PRIVATE->pFecsVgpuGlobalTraceInfo; +} + void kgrmgrGetGrObjectType_IMPL(NvU32 classNum, NvU32 *pObjectType); #define kgrmgrGetGrObjectType(classNum, pObjectType) kgrmgrGetGrObjectType_IMPL(classNum, pObjectType) @@ -472,27 +491,6 @@ static inline NV_STATUS kgrmgrCheckVeidsRequest(OBJGPU *arg0, struct KernelGraph #define kgrmgrCheckVeidsRequest(arg0, arg1, pInUseMask, veidCount, pSpanStart, arg2) kgrmgrCheckVeidsRequest_IMPL(arg0, arg1, pInUseMask, veidCount, pSpanStart, arg2) #endif //__nvoc_kernel_graphics_manager_h_disabled -NvBool kgrmgrSignalFecsCallbackScheduled_IMPL(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); - -#ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline NvBool kgrmgrSignalFecsCallbackScheduled(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_graphics_manager_h_disabled -#define kgrmgrSignalFecsCallbackScheduled(pGpu, pKernelGraphicsManager) kgrmgrSignalFecsCallbackScheduled_IMPL(pGpu, pKernelGraphicsManager) -#endif //__nvoc_kernel_graphics_manager_h_disabled - -void kgrmgrClearFecsCallbackScheduled_IMPL(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager); - -#ifdef __nvoc_kernel_graphics_manager_h_disabled -static inline void kgrmgrClearFecsCallbackScheduled(OBJGPU *pGpu, struct KernelGraphicsManager *pKernelGraphicsManager) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphicsManager was disabled!"); -} -#else //__nvoc_kernel_graphics_manager_h_disabled -#define kgrmgrClearFecsCallbackScheduled(pGpu, pKernelGraphicsManager) kgrmgrClearFecsCallbackScheduled_IMPL(pGpu, pKernelGraphicsManager) -#endif //__nvoc_kernel_graphics_manager_h_disabled - #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.c b/src/nvidia/generated/g_kernel_graphics_nvoc.c index 09e399826c..a9ac946df4 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.c @@ -107,7 +107,7 @@ static NV_STATUS __nvoc_thunk_KernelGraphics_engstateStatePostLoad(OBJGPU *arg0, return kgraphicsStatePostLoad(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_OBJENGSTATE.offset), flags); } -static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[168]) { +static void __nvoc_thunk_KernelGraphics_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *arg1, IntrServiceRecord arg2[171]) { kgraphicsRegisterIntrService(arg0, (struct KernelGraphics *)(((unsigned char *)arg1) - __nvoc_rtti_KernelGraphics_IntrService.offset), arg2); } @@ -181,7 +181,7 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner } // Hal field -- bDeferContextInit - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000003UL) )) /* RmVariantHal: VF | PF_KERNEL_ONLY */ { pThis->bDeferContextInit = ((NvBool)(0 != 0)); } @@ -211,7 +211,11 @@ void __nvoc_init_dataField_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner } // Hal field -- bFecsRecordUcodeSeqnoSupported - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->bFecsRecordUcodeSeqnoSupported = ((NvBool)(0 != 0)); + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -276,12 +280,33 @@ static void __nvoc_init_funcTable_KernelGraphics_1(KernelGraphics *pThis, RmHals pThis->__kgraphicsServiceNotificationInterrupt__ = &kgraphicsServiceNotificationInterrupt_IMPL; + // Hal function -- kgraphicsLoadStaticInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgraphicsLoadStaticInfo__ = &kgraphicsLoadStaticInfo_VGPUSTUB; + } + else + { + pThis->__kgraphicsLoadStaticInfo__ = &kgraphicsLoadStaticInfo_KERNEL; + } + // Hal function -- kgraphicsClearInterrupt pThis->__kgraphicsClearInterrupt__ = &kgraphicsClearInterrupt_GP100; // Hal function -- kgraphicsServiceInterrupt pThis->__kgraphicsServiceInterrupt__ = &kgraphicsServiceInterrupt_GP100; + // Hal function -- kgraphicsIsUnrestrictedAccessMapSupported + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgraphicsIsUnrestrictedAccessMapSupported__ = &kgraphicsIsUnrestrictedAccessMapSupported_491d52; + } + // default + else + { + pThis->__kgraphicsIsUnrestrictedAccessMapSupported__ = &kgraphicsIsUnrestrictedAccessMapSupported_PF; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGraphics_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelGraphics_engstateStateInitLocked; @@ -335,23 +360,31 @@ void __nvoc_init_KernelGraphics(KernelGraphics *pThis, RmHalspecOwner *pRmhalspe __nvoc_init_funcTable_KernelGraphics(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelGraphics(KernelGraphics **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelGraphics(KernelGraphics **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelGraphics *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphics), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelGraphics)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphics); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -369,16 +402,25 @@ NV_STATUS __nvoc_objCreate_KernelGraphics(KernelGraphics **ppThis, Dynamic *pPar status = __nvoc_ctor_KernelGraphics(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelGraphics_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelGraphics_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelGraphics)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_graphics_nvoc.h b/src/nvidia/generated/g_kernel_graphics_nvoc.h index 43f32d5853..acacbdfde5 100644 --- a/src/nvidia/generated/g_kernel_graphics_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_nvoc.h @@ -145,11 +145,16 @@ typedef struct KGRAPHICS_FECS_TRACE_INFO KGRAPHICS_FECS_TRACE_INFO; * interfaces which do not manage the underlying Graphics hardware can be * managed by this object. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelGraphics { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -168,8 +173,10 @@ struct KernelGraphics { NV_STATUS (*__kgraphicsStatePostLoad__)(OBJGPU *, struct KernelGraphics *, NvU32); void (*__kgraphicsRegisterIntrService__)(OBJGPU *, struct KernelGraphics *, IntrServiceRecord *); NV_STATUS (*__kgraphicsServiceNotificationInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceNotificationInterruptArguments *); + NV_STATUS (*__kgraphicsLoadStaticInfo__)(OBJGPU *, struct KernelGraphics *, NvU32); NvBool (*__kgraphicsClearInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceClearInterruptArguments *); NvU32 (*__kgraphicsServiceInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceInterruptArguments *); + NvBool (*__kgraphicsIsUnrestrictedAccessMapSupported__)(OBJGPU *, struct KernelGraphics *); NV_STATUS (*__kgraphicsStatePreLoad__)(POBJGPU, struct KernelGraphics *, NvU32); NV_STATUS (*__kgraphicsStatePostUnload__)(POBJGPU, struct KernelGraphics *, NvU32); NV_STATUS (*__kgraphicsStateInitUnlocked__)(POBJGPU, struct KernelGraphics *); @@ -188,12 +195,11 @@ struct KernelGraphics { NvU32 PRIVATE_FIELD(instance); KGRAPHICS_PRIVATE_DATA *PRIVATE_FIELD(pPrivate); NvBool PRIVATE_FIELD(bCollectingDeferredStaticData); - NvBool PRIVATE_FIELD(bBug4162646War); KGRAPHICS_FECS_TRACE_INFO *PRIVATE_FIELD(pFecsTraceInfo); struct KGRAPHICS_GLOBAL_CTX_BUFFERS_INFO PRIVATE_FIELD(globalCtxBuffersInfo); struct CTX_BUF_POOL_INFO *PRIVATE_FIELD(pCtxBufPool); - CTX_BUF_INFO PRIVATE_FIELD(maxCtxBufSize)[9]; - GR_BUFFER_ATTR PRIVATE_FIELD(ctxAttr)[9]; + CTX_BUF_INFO PRIVATE_FIELD(maxCtxBufSize)[10]; + GR_BUFFER_ATTR PRIVATE_FIELD(ctxAttr)[10]; }; struct KernelGraphics_PRIVATE { @@ -214,8 +220,10 @@ struct KernelGraphics_PRIVATE { NV_STATUS (*__kgraphicsStatePostLoad__)(OBJGPU *, struct KernelGraphics *, NvU32); void (*__kgraphicsRegisterIntrService__)(OBJGPU *, struct KernelGraphics *, IntrServiceRecord *); NV_STATUS (*__kgraphicsServiceNotificationInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceNotificationInterruptArguments *); + NV_STATUS (*__kgraphicsLoadStaticInfo__)(OBJGPU *, struct KernelGraphics *, NvU32); NvBool (*__kgraphicsClearInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceClearInterruptArguments *); NvU32 (*__kgraphicsServiceInterrupt__)(OBJGPU *, struct KernelGraphics *, IntrServiceServiceInterruptArguments *); + NvBool (*__kgraphicsIsUnrestrictedAccessMapSupported__)(OBJGPU *, struct KernelGraphics *); NV_STATUS (*__kgraphicsStatePreLoad__)(POBJGPU, struct KernelGraphics *, NvU32); NV_STATUS (*__kgraphicsStatePostUnload__)(POBJGPU, struct KernelGraphics *, NvU32); NV_STATUS (*__kgraphicsStateInitUnlocked__)(POBJGPU, struct KernelGraphics *); @@ -234,12 +242,11 @@ struct KernelGraphics_PRIVATE { NvU32 instance; KGRAPHICS_PRIVATE_DATA *pPrivate; NvBool bCollectingDeferredStaticData; - NvBool bBug4162646War; KGRAPHICS_FECS_TRACE_INFO *pFecsTraceInfo; struct KGRAPHICS_GLOBAL_CTX_BUFFERS_INFO globalCtxBuffersInfo; struct CTX_BUF_POOL_INFO *pCtxBufPool; - CTX_BUF_INFO maxCtxBufSize[9]; - GR_BUFFER_ATTR ctxAttr[9]; + CTX_BUF_INFO maxCtxBufSize[10]; + GR_BUFFER_ATTR ctxAttr[10]; }; #ifndef __NVOC_CLASS_KernelGraphics_TYPEDEF__ @@ -282,10 +289,14 @@ NV_STATUS __nvoc_objCreate_KernelGraphics(KernelGraphics**, Dynamic*, NvU32); #define kgraphicsStatePostLoad(arg0, arg1, flags) kgraphicsStatePostLoad_DISPATCH(arg0, arg1, flags) #define kgraphicsRegisterIntrService(arg0, arg1, arg2) kgraphicsRegisterIntrService_DISPATCH(arg0, arg1, arg2) #define kgraphicsServiceNotificationInterrupt(arg0, arg1, arg2) kgraphicsServiceNotificationInterrupt_DISPATCH(arg0, arg1, arg2) +#define kgraphicsLoadStaticInfo(arg0, arg1, swizzId) kgraphicsLoadStaticInfo_DISPATCH(arg0, arg1, swizzId) +#define kgraphicsLoadStaticInfo_HAL(arg0, arg1, swizzId) kgraphicsLoadStaticInfo_DISPATCH(arg0, arg1, swizzId) #define kgraphicsClearInterrupt(arg0, arg1, arg2) kgraphicsClearInterrupt_DISPATCH(arg0, arg1, arg2) #define kgraphicsClearInterrupt_HAL(arg0, arg1, arg2) kgraphicsClearInterrupt_DISPATCH(arg0, arg1, arg2) #define kgraphicsServiceInterrupt(arg0, arg1, arg2) kgraphicsServiceInterrupt_DISPATCH(arg0, arg1, arg2) #define kgraphicsServiceInterrupt_HAL(arg0, arg1, arg2) kgraphicsServiceInterrupt_DISPATCH(arg0, arg1, arg2) +#define kgraphicsIsUnrestrictedAccessMapSupported(arg0, arg1) kgraphicsIsUnrestrictedAccessMapSupported_DISPATCH(arg0, arg1) +#define kgraphicsIsUnrestrictedAccessMapSupported_HAL(arg0, arg1) kgraphicsIsUnrestrictedAccessMapSupported_DISPATCH(arg0, arg1) #define kgraphicsStatePreLoad(pGpu, pEngstate, arg0) kgraphicsStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgraphicsStatePostUnload(pGpu, pEngstate, arg0) kgraphicsStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define kgraphicsStateInitUnlocked(pGpu, pEngstate) kgraphicsStateInitUnlocked_DISPATCH(pGpu, pEngstate) @@ -350,20 +361,6 @@ static inline NV_STATUS kgraphicsAllocGlobalCtxBuffers(OBJGPU *arg0, struct Kern #define kgraphicsAllocGlobalCtxBuffers_HAL(arg0, arg1, gfid) kgraphicsAllocGlobalCtxBuffers(arg0, arg1, gfid) -NV_STATUS kgraphicsLoadStaticInfo_KERNEL(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 swizzId); - - -#ifdef __nvoc_kernel_graphics_h_disabled -static inline NV_STATUS kgraphicsLoadStaticInfo(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 swizzId) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_graphics_h_disabled -#define kgraphicsLoadStaticInfo(arg0, arg1, swizzId) kgraphicsLoadStaticInfo_KERNEL(arg0, arg1, swizzId) -#endif //__nvoc_kernel_graphics_h_disabled - -#define kgraphicsLoadStaticInfo_HAL(arg0, arg1, swizzId) kgraphicsLoadStaticInfo(arg0, arg1, swizzId) - static inline void kgraphicsNonstallIntrCheckAndClear_b3696a(OBJGPU *arg0, struct KernelGraphics *arg1, struct THREAD_STATE_NODE *arg2) { return; } @@ -392,20 +389,6 @@ static inline void kgraphicsInitFecsRegistryOverrides(OBJGPU *arg0, struct Kerne #define kgraphicsInitFecsRegistryOverrides_HAL(arg0, arg1) kgraphicsInitFecsRegistryOverrides(arg0, arg1) -NvBool kgraphicsIsUnrestrictedAccessMapSupported_PF(OBJGPU *arg0, struct KernelGraphics *arg1); - - -#ifdef __nvoc_kernel_graphics_h_disabled -static inline NvBool kgraphicsIsUnrestrictedAccessMapSupported(OBJGPU *arg0, struct KernelGraphics *arg1) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphics was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_graphics_h_disabled -#define kgraphicsIsUnrestrictedAccessMapSupported(arg0, arg1) kgraphicsIsUnrestrictedAccessMapSupported_PF(arg0, arg1) -#endif //__nvoc_kernel_graphics_h_disabled - -#define kgraphicsIsUnrestrictedAccessMapSupported_HAL(arg0, arg1) kgraphicsIsUnrestrictedAccessMapSupported(arg0, arg1) - NV_STATUS kgraphicsConstructEngine_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, ENGDESCRIPTOR arg2); static inline NV_STATUS kgraphicsConstructEngine_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, ENGDESCRIPTOR arg2) { @@ -454,9 +437,9 @@ static inline NV_STATUS kgraphicsStatePostLoad_DISPATCH(OBJGPU *arg0, struct Ker return arg1->__kgraphicsStatePostLoad__(arg0, arg1, flags); } -void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[168]); +void kgraphicsRegisterIntrService_IMPL(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[171]); -static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[168]) { +static inline void kgraphicsRegisterIntrService_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceRecord arg2[171]) { arg1->__kgraphicsRegisterIntrService__(arg0, arg1, arg2); } @@ -466,6 +449,14 @@ static inline NV_STATUS kgraphicsServiceNotificationInterrupt_DISPATCH(OBJGPU *a return arg1->__kgraphicsServiceNotificationInterrupt__(arg0, arg1, arg2); } +NV_STATUS kgraphicsLoadStaticInfo_VGPUSTUB(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 swizzId); + +NV_STATUS kgraphicsLoadStaticInfo_KERNEL(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 swizzId); + +static inline NV_STATUS kgraphicsLoadStaticInfo_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, NvU32 swizzId) { + return arg1->__kgraphicsLoadStaticInfo__(arg0, arg1, swizzId); +} + NvBool kgraphicsClearInterrupt_GP100(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceClearInterruptArguments *arg2); static inline NvBool kgraphicsClearInterrupt_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1, IntrServiceClearInterruptArguments *arg2) { @@ -478,6 +469,16 @@ static inline NvU32 kgraphicsServiceInterrupt_DISPATCH(OBJGPU *arg0, struct Kern return arg1->__kgraphicsServiceInterrupt__(arg0, arg1, arg2); } +static inline NvBool kgraphicsIsUnrestrictedAccessMapSupported_491d52(OBJGPU *arg0, struct KernelGraphics *arg1) { + return ((NvBool)(0 != 0)); +} + +NvBool kgraphicsIsUnrestrictedAccessMapSupported_PF(OBJGPU *arg0, struct KernelGraphics *arg1); + +static inline NvBool kgraphicsIsUnrestrictedAccessMapSupported_DISPATCH(OBJGPU *arg0, struct KernelGraphics *arg1) { + return arg1->__kgraphicsIsUnrestrictedAccessMapSupported__(arg0, arg1); +} + static inline NV_STATUS kgraphicsStatePreLoad_DISPATCH(POBJGPU pGpu, struct KernelGraphics *pEngstate, NvU32 arg0) { return pEngstate->__kgraphicsStatePreLoad__(pGpu, pEngstate, arg0); } diff --git a/src/nvidia/generated/g_kernel_graphics_object_nvoc.c b/src/nvidia/generated/g_kernel_graphics_object_nvoc.c index 45474cd4a4..27fe68ac4c 100644 --- a/src/nvidia/generated/g_kernel_graphics_object_nvoc.c +++ b/src/nvidia/generated/g_kernel_graphics_object_nvoc.c @@ -176,10 +176,6 @@ static void __nvoc_thunk_RmResource_kgrobjControl_Epilogue(struct KernelGraphics rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kgrobjControlLookup(struct KernelGraphicsObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_ChannelDescendant_kgrobjGetSwMethods(struct KernelGraphicsObject *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_KernelGraphicsObject_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_kgrobjCanCopy(struct KernelGraphicsObject return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_kgrobjIsPartialUnmapSupported(struct KernelGraphicsObject *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_kgrobjPreDestruct(struct KernelGraphicsObject *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelGraphicsObject_RsResource.offset)); } @@ -307,6 +307,16 @@ static void __nvoc_init_funcTable_KernelGraphicsObject_1(KernelGraphicsObject *p pThis->__kgrobjGetMemInterMapParams__ = &kgrobjGetMemInterMapParams_IMPL; + // Hal function -- kgrobjGetPromoteIds + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgrobjGetPromoteIds__ = &kgrobjGetPromoteIds_VF; + } + else + { + pThis->__kgrobjGetPromoteIds__ = &kgrobjGetPromoteIds_FWCLIENT; + } + pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__rmresGetMemInterMapParams__ = &__nvoc_thunk_KernelGraphicsObject_rmresGetMemInterMapParams; pThis->__kgrobjCheckMemInterUnmap__ = &__nvoc_thunk_ChannelDescendant_kgrobjCheckMemInterUnmap; @@ -335,8 +345,6 @@ static void __nvoc_init_funcTable_KernelGraphicsObject_1(KernelGraphicsObject *p pThis->__kgrobjControl_Epilogue__ = &__nvoc_thunk_RmResource_kgrobjControl_Epilogue; - pThis->__kgrobjControlLookup__ = &__nvoc_thunk_RsResource_kgrobjControlLookup; - pThis->__kgrobjGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_kgrobjGetSwMethods; pThis->__kgrobjGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kgrobjGetInternalObjectHandle; @@ -357,6 +365,8 @@ static void __nvoc_init_funcTable_KernelGraphicsObject_1(KernelGraphicsObject *p pThis->__kgrobjCanCopy__ = &__nvoc_thunk_RsResource_kgrobjCanCopy; + pThis->__kgrobjIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_kgrobjIsPartialUnmapSupported; + pThis->__kgrobjPreDestruct__ = &__nvoc_thunk_RsResource_kgrobjPreDestruct; pThis->__kgrobjIsDuplicate__ = &__nvoc_thunk_RsResource_kgrobjIsDuplicate; @@ -391,23 +401,31 @@ void __nvoc_init_KernelGraphicsObject(KernelGraphicsObject *pThis, RmHalspecOwne __nvoc_init_funcTable_KernelGraphicsObject(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelGraphicsObject *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGraphicsObject), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelGraphicsObject)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGraphicsObject); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -425,16 +443,25 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject **ppThis, D status = __nvoc_ctor_KernelGraphicsObject(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelGraphicsObject_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelGraphicsObject_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelGraphicsObject)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h index 0a4cba287f..11a6bfcb7b 100644 --- a/src/nvidia/generated/g_kernel_graphics_object_nvoc.h +++ b/src/nvidia/generated/g_kernel_graphics_object_nvoc.h @@ -45,11 +45,16 @@ extern "C" { * RM internal class representing 3D and compute graphics classes, e.g.: _A, * _COMPUTE_A, etc */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelGraphicsObject { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -63,6 +68,7 @@ struct KernelGraphicsObject { struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct KernelGraphicsObject *__nvoc_pbase_KernelGraphicsObject; NV_STATUS (*__kgrobjGetMemInterMapParams__)(struct KernelGraphicsObject *, RMRES_MEM_INTER_MAP_PARAMS *); + void (*__kgrobjGetPromoteIds__)(struct OBJGPU *, struct KernelGraphicsObject *, NvU32, NvU32 *, NvU32 *, NvBool *); NV_STATUS (*__kgrobjCheckMemInterUnmap__)(struct KernelGraphicsObject *, NvBool); NvBool (*__kgrobjShareCallback__)(struct KernelGraphicsObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NvBool (*__kgrobjAccessCallback__)(struct KernelGraphicsObject *, struct RsClient *, void *, RsAccessRight); @@ -76,7 +82,6 @@ struct KernelGraphicsObject { NV_STATUS (*__kgrobjInternalControlForward__)(struct KernelGraphicsObject *, NvU32, void *, NvU32); NV_STATUS (*__kgrobjUnmapFrom__)(struct KernelGraphicsObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kgrobjControl_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kgrobjControlLookup__)(struct KernelGraphicsObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kgrobjGetSwMethods__)(struct KernelGraphicsObject *, const METHOD **, NvU32 *); NvHandle (*__kgrobjGetInternalObjectHandle__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjControl__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -87,6 +92,7 @@ struct KernelGraphicsObject { NV_STATUS (*__kgrobjUnregisterEvent__)(struct KernelGraphicsObject *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__kgrobjControlSerialization_Prologue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kgrobjCanCopy__)(struct KernelGraphicsObject *); + NvBool (*__kgrobjIsPartialUnmapSupported__)(struct KernelGraphicsObject *); void (*__kgrobjPreDestruct__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjIsDuplicate__)(struct KernelGraphicsObject *, NvHandle, NvBool *); void (*__kgrobjControlSerialization_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -111,6 +117,7 @@ struct KernelGraphicsObject_PRIVATE { struct ChannelDescendant *__nvoc_pbase_ChannelDescendant; struct KernelGraphicsObject *__nvoc_pbase_KernelGraphicsObject; NV_STATUS (*__kgrobjGetMemInterMapParams__)(struct KernelGraphicsObject *, RMRES_MEM_INTER_MAP_PARAMS *); + void (*__kgrobjGetPromoteIds__)(struct OBJGPU *, struct KernelGraphicsObject *, NvU32, NvU32 *, NvU32 *, NvBool *); NV_STATUS (*__kgrobjCheckMemInterUnmap__)(struct KernelGraphicsObject *, NvBool); NvBool (*__kgrobjShareCallback__)(struct KernelGraphicsObject *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NvBool (*__kgrobjAccessCallback__)(struct KernelGraphicsObject *, struct RsClient *, void *, RsAccessRight); @@ -124,7 +131,6 @@ struct KernelGraphicsObject_PRIVATE { NV_STATUS (*__kgrobjInternalControlForward__)(struct KernelGraphicsObject *, NvU32, void *, NvU32); NV_STATUS (*__kgrobjUnmapFrom__)(struct KernelGraphicsObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kgrobjControl_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kgrobjControlLookup__)(struct KernelGraphicsObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__kgrobjGetSwMethods__)(struct KernelGraphicsObject *, const METHOD **, NvU32 *); NvHandle (*__kgrobjGetInternalObjectHandle__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjControl__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -135,6 +141,7 @@ struct KernelGraphicsObject_PRIVATE { NV_STATUS (*__kgrobjUnregisterEvent__)(struct KernelGraphicsObject *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__kgrobjControlSerialization_Prologue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__kgrobjCanCopy__)(struct KernelGraphicsObject *); + NvBool (*__kgrobjIsPartialUnmapSupported__)(struct KernelGraphicsObject *); void (*__kgrobjPreDestruct__)(struct KernelGraphicsObject *); NV_STATUS (*__kgrobjIsDuplicate__)(struct KernelGraphicsObject *, NvHandle, NvBool *); void (*__kgrobjControlSerialization_Epilogue__)(struct KernelGraphicsObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -175,6 +182,8 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject**, Dynamic* __nvoc_objCreate_KernelGraphicsObject((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) #define kgrobjGetMemInterMapParams(arg0, arg1) kgrobjGetMemInterMapParams_DISPATCH(arg0, arg1) +#define kgrobjGetPromoteIds(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote) kgrobjGetPromoteIds_DISPATCH(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote) +#define kgrobjGetPromoteIds_HAL(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote) kgrobjGetPromoteIds_DISPATCH(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote) #define kgrobjCheckMemInterUnmap(pChannelDescendant, bSubdeviceHandleProvided) kgrobjCheckMemInterUnmap_DISPATCH(pChannelDescendant, bSubdeviceHandleProvided) #define kgrobjShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kgrobjShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define kgrobjAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) kgrobjAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) @@ -188,7 +197,6 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject**, Dynamic* #define kgrobjInternalControlForward(pGpuResource, command, pParams, size) kgrobjInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kgrobjUnmapFrom(pResource, pParams) kgrobjUnmapFrom_DISPATCH(pResource, pParams) #define kgrobjControl_Epilogue(pResource, pCallContext, pParams) kgrobjControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kgrobjControlLookup(pResource, pParams, ppEntry) kgrobjControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kgrobjGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) kgrobjGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) #define kgrobjGetInternalObjectHandle(pGpuResource) kgrobjGetInternalObjectHandle_DISPATCH(pGpuResource) #define kgrobjControl(pGpuResource, pCallContext, pParams) kgrobjControl_DISPATCH(pGpuResource, pCallContext, pParams) @@ -199,6 +207,7 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject**, Dynamic* #define kgrobjUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kgrobjUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define kgrobjControlSerialization_Prologue(pResource, pCallContext, pParams) kgrobjControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define kgrobjCanCopy(pResource) kgrobjCanCopy_DISPATCH(pResource) +#define kgrobjIsPartialUnmapSupported(pResource) kgrobjIsPartialUnmapSupported_DISPATCH(pResource) #define kgrobjPreDestruct(pResource) kgrobjPreDestruct_DISPATCH(pResource) #define kgrobjIsDuplicate(pResource, hMemory, pDuplicate) kgrobjIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kgrobjControlSerialization_Epilogue(pResource, pCallContext, pParams) kgrobjControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -206,19 +215,6 @@ NV_STATUS __nvoc_objCreate_KernelGraphicsObject(KernelGraphicsObject**, Dynamic* #define kgrobjGetNotificationShare(pNotifier) kgrobjGetNotificationShare_DISPATCH(pNotifier) #define kgrobjMap(pGpuResource, pCallContext, pParams, pCpuMapping) kgrobjMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define kgrobjGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kgrobjGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) -void kgrobjGetPromoteIds_FWCLIENT(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, NvU32 maxPromoteIds, NvU32 *pPromoteIds, NvU32 *pNumEntries, NvBool *pbPromote); - - -#ifdef __nvoc_kernel_graphics_object_h_disabled -static inline void kgrobjGetPromoteIds(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, NvU32 maxPromoteIds, NvU32 *pPromoteIds, NvU32 *pNumEntries, NvBool *pbPromote) { - NV_ASSERT_FAILED_PRECOMP("KernelGraphicsObject was disabled!"); -} -#else //__nvoc_kernel_graphics_object_h_disabled -#define kgrobjGetPromoteIds(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote) kgrobjGetPromoteIds_FWCLIENT(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote) -#endif //__nvoc_kernel_graphics_object_h_disabled - -#define kgrobjGetPromoteIds_HAL(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote) kgrobjGetPromoteIds(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote) - NvBool kgrobjShouldCleanup_KERNEL(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1); @@ -266,6 +262,14 @@ static inline NV_STATUS kgrobjGetMemInterMapParams_DISPATCH(struct KernelGraphic return arg0->__kgrobjGetMemInterMapParams__(arg0, arg1); } +void kgrobjGetPromoteIds_VF(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, NvU32 maxPromoteIds, NvU32 *pPromoteIds, NvU32 *pNumEntries, NvBool *pbPromote); + +void kgrobjGetPromoteIds_FWCLIENT(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, NvU32 maxPromoteIds, NvU32 *pPromoteIds, NvU32 *pNumEntries, NvBool *pbPromote); + +static inline void kgrobjGetPromoteIds_DISPATCH(struct OBJGPU *arg0, struct KernelGraphicsObject *arg1, NvU32 maxPromoteIds, NvU32 *pPromoteIds, NvU32 *pNumEntries, NvBool *pbPromote) { + arg1->__kgrobjGetPromoteIds__(arg0, arg1, maxPromoteIds, pPromoteIds, pNumEntries, pbPromote); +} + static inline NV_STATUS kgrobjCheckMemInterUnmap_DISPATCH(struct KernelGraphicsObject *pChannelDescendant, NvBool bSubdeviceHandleProvided) { return pChannelDescendant->__kgrobjCheckMemInterUnmap__(pChannelDescendant, bSubdeviceHandleProvided); } @@ -318,10 +322,6 @@ static inline void kgrobjControl_Epilogue_DISPATCH(struct KernelGraphicsObject * pResource->__kgrobjControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS kgrobjControlLookup_DISPATCH(struct KernelGraphicsObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kgrobjControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS kgrobjGetSwMethods_DISPATCH(struct KernelGraphicsObject *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__kgrobjGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -362,6 +362,10 @@ static inline NvBool kgrobjCanCopy_DISPATCH(struct KernelGraphicsObject *pResour return pResource->__kgrobjCanCopy__(pResource); } +static inline NvBool kgrobjIsPartialUnmapSupported_DISPATCH(struct KernelGraphicsObject *pResource) { + return pResource->__kgrobjIsPartialUnmapSupported__(pResource); +} + static inline void kgrobjPreDestruct_DISPATCH(struct KernelGraphicsObject *pResource) { pResource->__kgrobjPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index b5721a4048..47d024d609 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -106,7 +106,7 @@ static NV_STATUS __nvoc_thunk_KernelGsp_engstateConstructEngine(struct OBJGPU *p return kgspConstructEngine(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[168]) { +static void __nvoc_thunk_KernelGsp_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelGsp, IntrServiceRecord pRecords[171]) { kgspRegisterIntrService(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_IntrService.offset), pRecords); } @@ -118,6 +118,10 @@ static NV_STATUS __nvoc_thunk_KernelGsp_kflcnResetHw(struct OBJGPU *pGpu, struct return kgspResetHw(pGpu, (struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelFalcon.offset)); } +static void __nvoc_thunk_KernelGsp_kcrashcatEngineReadEmem(struct KernelCrashCatEngine *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf) { + kgspReadEmem((struct KernelGsp *)(((unsigned char *)pKernelGsp) - __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, size, pBuf); +} + static NvBool __nvoc_thunk_KernelCrashCatEngine_kgspConfigured(struct KernelGsp *arg0) { return kcrashcatEngineConfigured((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset)); } @@ -166,10 +170,6 @@ static NvBool __nvoc_thunk_OBJENGSTATE_kgspIsPresent(POBJGPU pGpu, struct Kernel return engstateIsPresent(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset)); } -static void __nvoc_thunk_KernelCrashCatEngine_kgspReadEmem(struct KernelGsp *arg0, NvU64 offset, NvU64 size, void *pBuf) { - kcrashcatEngineReadEmem((struct KernelCrashCatEngine *)(((unsigned char *)arg0) + __nvoc_rtti_KernelGsp_KernelCrashCatEngine.offset), offset, size, pBuf); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kgspStateLoad(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return engstateStateLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelGsp_OBJENGSTATE.offset), arg0); } @@ -303,7 +303,7 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe } // Hal field -- bBootGspRmWithBoostClocks - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->bBootGspRmWithBoostClocks = ((NvBool)(0 == 0)); } @@ -312,6 +312,21 @@ void __nvoc_init_dataField_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspe { pThis->bBootGspRmWithBoostClocks = ((NvBool)(0 != 0)); } + + // Hal field -- ememPort + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->ememPort = 6; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->ememPort = 2; + } + // default + else + { + pThis->ememPort = 0; + } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -357,434 +372,849 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__kgspServiceInterrupt__ = &kgspServiceInterrupt_IMPL; // Hal function -- kgspConfigureFalcon - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; + pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_f2d351; } else { - pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_TU102; + } + else + { + pThis->__kgspConfigureFalcon__ = &kgspConfigureFalcon_GA102; + } } // Hal function -- kgspIsDebugModeEnabled - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; + pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_108313; } else { - pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_TU102; + } + else + { + pThis->__kgspIsDebugModeEnabled__ = &kgspIsDebugModeEnabled_GA100; + } } // Hal function -- kgspAllocBootArgs - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_5baef9; } else { - pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_GH100; + } + else + { + pThis->__kgspAllocBootArgs__ = &kgspAllocBootArgs_TU102; + } } // Hal function -- kgspFreeBootArgs - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_f2d351; } else { - pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_GH100; + } + else + { + pThis->__kgspFreeBootArgs__ = &kgspFreeBootArgs_TU102; + } } - // Hal function -- kgspBootstrapRiscvOSEarly - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // Hal function -- kgspProgramLibosBootArgsAddr + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GH100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_TU102; + pThis->__kgspProgramLibosBootArgsAddr__ = &kgspProgramLibosBootArgsAddr_f2d351; } else { - pThis->__kgspBootstrapRiscvOSEarly__ = &kgspBootstrapRiscvOSEarly_GA102; + pThis->__kgspProgramLibosBootArgsAddr__ = &kgspProgramLibosBootArgsAddr_TU102; } - // Hal function -- kgspGetGspRmBootUcodeStorage - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // Hal function -- kgspSetCmdQueueHead + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GH100; + pThis->__kgspSetCmdQueueHead__ = &kgspSetCmdQueueHead_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + else { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; + pThis->__kgspSetCmdQueueHead__ = &kgspSetCmdQueueHead_TU102; + } + + // Hal function -- kgspPrepareForBootstrap + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgspPrepareForBootstrap__ = &kgspPrepareForBootstrap_5baef9; } else { - pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspPrepareForBootstrap__ = &kgspPrepareForBootstrap_GH100; + } + else + { + pThis->__kgspPrepareForBootstrap__ = &kgspPrepareForBootstrap_TU102; + } } - // Hal function -- kgspGetBinArchiveGspRmBoot - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + // Hal function -- kgspBootstrap + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA100; + pThis->__kgspBootstrap__ = &kgspBootstrap_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspBootstrap__ = &kgspBootstrap_GH100; + } + else + { + pThis->__kgspBootstrap__ = &kgspBootstrap_TU102; + } + } + + // Hal function -- kgspGetGspRmBootUcodeStorage + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_f2d351; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + else { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_TU102; + } + else + { + pThis->__kgspGetGspRmBootUcodeStorage__ = &kgspGetGspRmBootUcodeStorage_GA102; + } } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + + // Hal function -- kgspGetBinArchiveGspRmBoot + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_80f438; } else { - pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_GA102; + } + else + { + pThis->__kgspGetBinArchiveGspRmBoot__ = &kgspGetBinArchiveGspRmBoot_AD102; + } } // Hal function -- kgspGetBinArchiveConcatenatedFMCDesc - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_GH100; + pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_80f438; } else { - pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_80f438; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_GH100; + } + else + { + pThis->__kgspGetBinArchiveConcatenatedFMCDesc__ = &kgspGetBinArchiveConcatenatedFMCDesc_80f438; + } } // Hal function -- kgspGetBinArchiveConcatenatedFMC - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_GH100; + pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_80f438; } else { - pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_80f438; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_GH100; + } + else + { + pThis->__kgspGetBinArchiveConcatenatedFMC__ = &kgspGetBinArchiveConcatenatedFMC_80f438; + } } // Hal function -- kgspGetBinArchiveGspRmFmcGfwDebugSigned - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; } - // default else { - pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmFmcGfwDebugSigned__ = &kgspGetBinArchiveGspRmFmcGfwDebugSigned_80f438; + } } // Hal function -- kgspGetBinArchiveGspRmFmcGfwProdSigned - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; } - // default else { - pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmFmcGfwProdSigned_80f438; + } } // Hal function -- kgspGetBinArchiveGspRmCcFmcGfwProdSigned - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100; + pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_80f438; } - // default else { - pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_80f438; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_GH100; + } + // default + else + { + pThis->__kgspGetBinArchiveGspRmCcFmcGfwProdSigned__ = &kgspGetBinArchiveGspRmCcFmcGfwProdSigned_80f438; + } } // Hal function -- kgspCalculateFbLayout - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_5baef9; } else { - pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_GH100; + } + else + { + pThis->__kgspCalculateFbLayout__ = &kgspCalculateFbLayout_TU102; + } } // Hal function -- kgspGetNonWprHeapSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_5baef9; } else { - pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_d505ea; + } + else + { + pThis->__kgspGetNonWprHeapSize__ = &kgspGetNonWprHeapSize_ed6b8b; + } } // Hal function -- kgspExecuteSequencerCommand - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; + pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_5baef9; } else { - pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_TU102; + } + else + { + pThis->__kgspExecuteSequencerCommand__ = &kgspExecuteSequencerCommand_GA102; + } } // Hal function -- kgspReadUcodeFuseVersion - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; + pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_474d46; } else { - pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_b2b553; + } + else + { + pThis->__kgspReadUcodeFuseVersion__ = &kgspReadUcodeFuseVersion_GA100; + } } // Hal function -- kgspResetHw - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspResetHw__ = &kgspResetHw_GH100; + pThis->__kgspResetHw__ = &kgspResetHw_5baef9; } else { - pThis->__kgspResetHw__ = &kgspResetHw_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspResetHw__ = &kgspResetHw_GH100; + } + else + { + pThis->__kgspResetHw__ = &kgspResetHw_TU102; + } + } + + // Hal function -- kgspHealthCheck + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgspHealthCheck__ = &kgspHealthCheck_108313; + } + else + { + pThis->__kgspHealthCheck__ = &kgspHealthCheck_TU102; + } + + // Hal function -- kgspService + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgspService__ = &kgspService_474d46; + } + else + { + pThis->__kgspService__ = &kgspService_TU102; } // Hal function -- kgspIsWpr2Up - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_GH100; + pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_108313; } else { - pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_GH100; + } + else + { + pThis->__kgspIsWpr2Up__ = &kgspIsWpr2Up_TU102; + } } // Hal function -- kgspGetFrtsSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; + pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_474d46; } else { - pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_4a4dee; + } + else + { + pThis->__kgspGetFrtsSize__ = &kgspGetFrtsSize_TU102; + } } // Hal function -- kgspGetPrescrubbedTopFbSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_604eb7; + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_474d46; } else { - pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_604eb7; + } + else + { + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623; + } } // Hal function -- kgspExtractVbiosFromRom - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_5baef9; } else { - pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_395e98; + } + else + { + pThis->__kgspExtractVbiosFromRom__ = &kgspExtractVbiosFromRom_TU102; + } } - // Hal function -- kgspExecuteFwsecFrts - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + // Hal function -- kgspPrepareForFwsecFrts + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_5baef9; + pThis->__kgspPrepareForFwsecFrts__ = &kgspPrepareForFwsecFrts_5baef9; } else { - pThis->__kgspExecuteFwsecFrts__ = &kgspExecuteFwsecFrts_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kgspPrepareForFwsecFrts__ = &kgspPrepareForFwsecFrts_5baef9; + } + else + { + pThis->__kgspPrepareForFwsecFrts__ = &kgspPrepareForFwsecFrts_TU102; + } } - // Hal function -- kgspExecuteFwsecSb - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // Hal function -- kgspPrepareForFwsecSb + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_ac1694; + pThis->__kgspPrepareForFwsecSb__ = &kgspPrepareForFwsecSb_5baef9; } else { - pThis->__kgspExecuteFwsecSb__ = &kgspExecuteFwsecSb_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspPrepareForFwsecSb__ = &kgspPrepareForFwsecSb_395e98; + } + else + { + pThis->__kgspPrepareForFwsecSb__ = &kgspPrepareForFwsecSb_TU102; + } } - // Hal function -- kgspExecuteScrubberIfNeeded - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + // Hal function -- kgspExecuteFwsec + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102; + pThis->__kgspExecuteFwsec__ = &kgspExecuteFwsec_5baef9; } else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExecuteFwsec__ = &kgspExecuteFwsec_5baef9; + } + else + { + pThis->__kgspExecuteFwsec__ = &kgspExecuteFwsec_TU102; + } + } + + // Hal function -- kgspExecuteScrubberIfNeeded + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9; } + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102; + } + else + { + pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9; + } + } // Hal function -- kgspExecuteBooterLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; } else { - pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_5baef9; + } + else + { + pThis->__kgspExecuteBooterLoad__ = &kgspExecuteBooterLoad_TU102; + } } // Hal function -- kgspExecuteBooterUnloadIfNeeded - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; } else { - pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_5baef9; + } + else + { + pThis->__kgspExecuteBooterUnloadIfNeeded__ = &kgspExecuteBooterUnloadIfNeeded_TU102; + } } // Hal function -- kgspExecuteHsFalcon - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ - { - pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; - } else { - pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_5baef9; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_TU102; + } + else + { + pThis->__kgspExecuteHsFalcon__ = &kgspExecuteHsFalcon_GA102; + } } - // Hal function -- kgspWaitForGfwBootOk - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + // Hal function -- kgspWaitForProcessorSuspend + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; + pThis->__kgspWaitForProcessorSuspend__ = &kgspWaitForProcessorSuspend_5baef9; } else { - pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; + pThis->__kgspWaitForProcessorSuspend__ = &kgspWaitForProcessorSuspend_TU102; } - // Hal function -- kgspGetBinArchiveBooterLoadUcode - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + // Hal function -- kgspSavePowerMgmtState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA100; + pThis->__kgspSavePowerMgmtState__ = &kgspSavePowerMgmtState_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; + pThis->__kgspSavePowerMgmtState__ = &kgspSavePowerMgmtState_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ + + // Hal function -- kgspRestorePowerMgmtState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU116; + pThis->__kgspRestorePowerMgmtState__ = &kgspRestorePowerMgmtState_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + else { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU102; + pThis->__kgspRestorePowerMgmtState__ = &kgspRestorePowerMgmtState_TU102; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + + // Hal function -- kgspFreeSuspendResumeData + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; + pThis->__kgspFreeSuspendResumeData__ = &kgspFreeSuspendResumeData_f2d351; } else { - pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; + pThis->__kgspFreeSuspendResumeData__ = &kgspFreeSuspendResumeData_TU102; } - // Hal function -- kgspGetBinArchiveBooterUnloadUcode - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + // Hal function -- kgspWaitForGfwBootOk + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA100; + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_5baef9; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + else { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_GH100; + } + else + { + pThis->__kgspWaitForGfwBootOk__ = &kgspWaitForGfwBootOk_TU102; + } } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ + + // Hal function -- kgspGetBinArchiveBooterLoadUcode + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU116; + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + else { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_80f438; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU116; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_GA102; + } + else + { + pThis->__kgspGetBinArchiveBooterLoadUcode__ = &kgspGetBinArchiveBooterLoadUcode_AD102; + } } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + + // Hal function -- kgspGetBinArchiveBooterUnloadUcode + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; } else { - pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_80f438; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU116; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_TU102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_GA102; + } + else + { + pThis->__kgspGetBinArchiveBooterUnloadUcode__ = &kgspGetBinArchiveBooterUnloadUcode_AD102; + } } // Hal function -- kgspGetMinWprHeapSizeMB - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_7185bf; + pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_b2b553; } else { - pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_cc88c3; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_7185bf; + } + else + { + pThis->__kgspGetMinWprHeapSizeMB__ = &kgspGetMinWprHeapSizeMB_cc88c3; + } } // Hal function -- kgspGetMaxWprHeapSizeMB - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_ad4e6a; + pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_b2b553; } else { - pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_55728f; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_ad4e6a; + } + else + { + pThis->__kgspGetMaxWprHeapSizeMB__ = &kgspGetMaxWprHeapSizeMB_55728f; + } } // Hal function -- kgspGetFwHeapParamOsCarveoutSize - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_397f70; + pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_b2b553; } else { - pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_4b5307; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_397f70; + } + else + { + pThis->__kgspGetFwHeapParamOsCarveoutSize__ = &kgspGetFwHeapParamOsCarveoutSize_4b5307; + } } // Hal function -- kgspInitVgpuPartitionLogging - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; } else { - pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; + } + else + { + pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; + } } // Hal function -- kgspFreeVgpuPartitionLogging - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; } else { - pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 */ + { + pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; + } + else + { + pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; + } } // Hal function -- kgspGetSignatureSectionNamePrefix - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_GH100; + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_80f438; } - // default else { - pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_789efb; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_GH100; + } + // default + else + { + pThis->__kgspGetSignatureSectionNamePrefix__ = &kgspGetSignatureSectionNamePrefix_789efb; + } } // Hal function -- kgspSetupGspFmcArgs - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; } - // default else { - pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_GH100; + } + // default + else + { + pThis->__kgspSetupGspFmcArgs__ = &kgspSetupGspFmcArgs_5baef9; + } + } + + // Hal function -- kgspReadEmem + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgspReadEmem__ = &kgspReadEmem_366c4c; + } + else + { + pThis->__kgspReadEmem__ = &kgspReadEmem_TU102; + } + + // Hal function -- kgspIssueNotifyOp + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgspIssueNotifyOp__ = &kgspIssueNotifyOp_5baef9; + } + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspIssueNotifyOp__ = &kgspIssueNotifyOp_GH100; + } + // default + else + { + pThis->__kgspIssueNotifyOp__ = &kgspIssueNotifyOp_5baef9; + } + } + + // Hal function -- kgspCheckGspRmCcCleanup + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kgspCheckGspRmCcCleanup__ = &kgspCheckGspRmCcCleanup_5baef9; + } + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kgspCheckGspRmCcCleanup__ = &kgspCheckGspRmCcCleanup_GH100; + } + // default + else + { + pThis->__kgspCheckGspRmCcCleanup__ = &kgspCheckGspRmCcCleanup_5baef9; + } } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelGsp_engstateConstructEngine; @@ -795,6 +1225,8 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelGsp_kflcnResetHw; + pThis->__nvoc_base_KernelFalcon.__nvoc_base_KernelCrashCatEngine.__kcrashcatEngineReadEmem__ = &__nvoc_thunk_KernelGsp_kcrashcatEngineReadEmem; + pThis->__kgspConfigured__ = &__nvoc_thunk_KernelCrashCatEngine_kgspConfigured; pThis->__kgspPriRead__ = &__nvoc_thunk_KernelCrashCatEngine_kgspPriRead; @@ -819,8 +1251,6 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * pThis->__kgspIsPresent__ = &__nvoc_thunk_OBJENGSTATE_kgspIsPresent; - pThis->__kgspReadEmem__ = &__nvoc_thunk_KernelCrashCatEngine_kgspReadEmem; - pThis->__kgspStateLoad__ = &__nvoc_thunk_OBJENGSTATE_kgspStateLoad; pThis->__kgspGetScratchOffsets__ = &__nvoc_thunk_KernelCrashCatEngine_kgspGetScratchOffsets; @@ -877,23 +1307,31 @@ void __nvoc_init_KernelGsp(KernelGsp *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelGsp(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelGsp *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelGsp), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelGsp)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelGsp); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -911,16 +1349,25 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_KernelGsp(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelGsp_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelGsp_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelGsp)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index a7e37cbbcd..03fd3bbf86 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -162,6 +162,16 @@ typedef enum KernelGspFlcnUcodeBootType KGSP_FLCN_UCODE_BOOT_FROM_HS } KernelGspFlcnUcodeBootType; +/*! + * RPC processing trigger + */ +typedef enum KernelGspRpcEventHandlerContext +{ + KGSP_RPC_EVENT_HANDLER_CONTEXT_POLL, // called after issuing an RPC + KGSP_RPC_EVENT_HANDLER_CONTEXT_POLL_BOOTUP, // called from kgspWaitForRmInitDone + KGSP_RPC_EVENT_HANDLER_CONTEXT_INTERRUPT // called in bottom-half interrupt path +} KernelGspRpcEventHandlerContext; + /*! * Tagged union of falcon ucode variants used by early FRTS and GSP-RM boot. */ @@ -176,6 +186,16 @@ typedef struct KernelGspFlcnUcode }; } KernelGspFlcnUcode; +/*! + * Structure for used for executing a FWSEC command + */ +typedef struct KernelGspPreparedFwsecCmd +{ + KernelGspFlcnUcode *pFwsecUcode; + NvU32 cmd; + NvU64 frtsOffset; +} KernelGspPreparedFwsecCmd; + /*! * GSP-RM source when running in Emulated/Simulated RISCV environment is * extremely slow, so we need a factor (X) to scale timeouts by. @@ -211,6 +231,36 @@ typedef struct GSP_FIRMWARE #define GSP_SIGNATURE_SECTION_NAME_PREFIX ".fwsignature_" #define GSP_CC_SIGNATURE_SECTION_NAME_PREFIX ".fwsignature_cc_" +/*! + * GSP Notify op infra. Used by UVM in HCC mode. + */ +#define GSP_NOTIFY_OP_RESERVED_OPCODE 0 +// Request fault buffer flush. +#define GSP_NOTIFY_OP_FLUSH_REPLAYABLE_FAULT_BUFFER_OPCODE 1 +// Fault on prefetch toggle. +#define GSP_NOTIFY_OP_TOGGLE_FAULT_ON_PREFETCH_OPCODE 2 +#define GSP_NOTIFY_OP_TOGGLE_FAULT_ON_PREFETCH_VALID_ARGC 1 +#define GSP_NOTIFY_OP_TOGGLE_FAULT_ON_PREFETCH_EN_ARGIDX 0 +// Always keep this as the last defined value +#define GSP_NOTIFY_OP_OPCODE_MAX 3 +#define GSP_NOTIFY_OP_NO_ARGUMENTS 0 +#define GSP_NOTIFY_OP_MAX_ARGUMENT_COUNT 1 +typedef struct NotifyOpSharedSurface +{ + NvU32 inUse; // 0 - signals free, 1 - signals busy + // An atomic swap is issued in a loop over this field from the + // KernelRM side to synchronize access to the shared notify op resource. + // Once the operation finishes the exiting thread flips the value back to 0. + NvU32 seqNum; // Read by KernelRM; Written by GSP. Provides synchronization so the + // requester knows when the operation is finished by GSP. + NvU32 opCode; // Written by KernelRM; Read by GSP. Specifies the operation to be performed. + NvU32 status; // Read by KernelRM; Written by GSP. Specifies the status of the operation. + // Becomes valid for the current operation after seqNum is incremented. + NvU32 argc; // Written by KernelRM; Read by GSP. Specifies the number of arguments. + NvU32 args[GSP_NOTIFY_OP_MAX_ARGUMENT_COUNT]; // Written by KernelRM; Read by GSP. Contains a list of NvU32 args used + // by the operation. +} NotifyOpSharedSurface; + /*! * Index into libosLogDecode array. */ @@ -237,11 +287,16 @@ typedef struct /*! * KernelGsp object definition */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_GSP_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MESSAGE_QUEUE_COLLECTION; @@ -264,7 +319,10 @@ struct KernelGsp { NvBool (*__kgspIsDebugModeEnabled__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspAllocBootArgs__)(struct OBJGPU *, struct KernelGsp *); void (*__kgspFreeBootArgs__)(struct OBJGPU *, struct KernelGsp *); - NV_STATUS (*__kgspBootstrapRiscvOSEarly__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); + void (*__kgspProgramLibosBootArgsAddr__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspSetCmdQueueHead__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32); + NV_STATUS (*__kgspPrepareForBootstrap__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); + NV_STATUS (*__kgspBootstrap__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); void (*__kgspGetGspRmBootUcodeStorage__)(struct OBJGPU *, struct KernelGsp *, BINDATA_STORAGE **, BINDATA_STORAGE **); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveGspRmBoot__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveConcatenatedFMCDesc__)(struct KernelGsp *); @@ -277,16 +335,23 @@ struct KernelGsp { NV_STATUS (*__kgspExecuteSequencerCommand__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32 *, NvU32); NvU32 (*__kgspReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelGsp *, NvU32); NV_STATUS (*__kgspResetHw__)(struct OBJGPU *, struct KernelGsp *); + NvBool (*__kgspHealthCheck__)(struct OBJGPU *, struct KernelGsp *); + NvU32 (*__kgspService__)(struct OBJGPU *, struct KernelGsp *); NvBool (*__kgspIsWpr2Up__)(struct OBJGPU *, struct KernelGsp *); NvU32 (*__kgspGetFrtsSize__)(struct OBJGPU *, struct KernelGsp *); NvU64 (*__kgspGetPrescrubbedTopFbSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExtractVbiosFromRom__)(struct OBJGPU *, struct KernelGsp *, KernelGspVbiosImg **); - NV_STATUS (*__kgspExecuteFwsecFrts__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, const NvU64); - NV_STATUS (*__kgspExecuteFwsecSb__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *); + NV_STATUS (*__kgspPrepareForFwsecFrts__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, const NvU64, KernelGspPreparedFwsecCmd *); + NV_STATUS (*__kgspPrepareForFwsecSb__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, KernelGspPreparedFwsecCmd *); + NV_STATUS (*__kgspExecuteFwsec__)(struct OBJGPU *, struct KernelGsp *, KernelGspPreparedFwsecCmd *); NV_STATUS (*__kgspExecuteScrubberIfNeeded__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteBooterLoad__)(struct OBJGPU *, struct KernelGsp *, const NvU64); NV_STATUS (*__kgspExecuteBooterUnloadIfNeeded__)(struct OBJGPU *, struct KernelGsp *, const NvU64); NV_STATUS (*__kgspExecuteHsFalcon__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, struct KernelFalcon *, NvU32 *, NvU32 *); + NV_STATUS (*__kgspWaitForProcessorSuspend__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspSavePowerMgmtState__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspRestorePowerMgmtState__)(struct OBJGPU *, struct KernelGsp *); + void (*__kgspFreeSuspendResumeData__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspWaitForGfwBootOk__)(struct OBJGPU *, struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *); @@ -297,6 +362,9 @@ struct KernelGsp { NV_STATUS (*__kgspFreeVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32); const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspSetupGspFmcArgs__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); + void (*__kgspReadEmem__)(struct KernelGsp *, NvU64, NvU64, void *); + NV_STATUS (*__kgspIssueNotifyOp__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32 *, NvU32); + NV_STATUS (*__kgspCheckGspRmCcCleanup__)(struct OBJGPU *, struct KernelGsp *); NvBool (*__kgspConfigured__)(struct KernelGsp *); NvU32 (*__kgspPriRead__)(struct KernelGsp *, NvU32); void (*__kgspRegWrite__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU32); @@ -309,7 +377,6 @@ struct KernelGsp { void (*__kgspSyncBufferDescriptor__)(struct KernelGsp *, CrashCatBufferDescriptor *, NvU32, NvU32); NvU32 (*__kgspRegRead__)(struct OBJGPU *, struct KernelGsp *, NvU32); NvBool (*__kgspIsPresent__)(POBJGPU, struct KernelGsp *); - void (*__kgspReadEmem__)(struct KernelGsp *, NvU64, NvU64, void *); NV_STATUS (*__kgspStateLoad__)(POBJGPU, struct KernelGsp *, NvU32); const NvU32 *(*__kgspGetScratchOffsets__)(struct KernelGsp *, NV_CRASHCAT_SCRATCH_GROUP_ID); void (*__kgspUnload__)(struct KernelGsp *); @@ -338,6 +405,7 @@ struct KernelGsp { MEMORY_DESCRIPTOR *pWprMetaDescriptor; GspFwWprMeta *pWprMeta; NvP64 pWprMetaMappingPriv; + KernelGspPreparedFwsecCmd *pPreparedFwsecCmd; MEMORY_DESCRIPTOR *pSRMetaDescriptor; MEMORY_DESCRIPTOR *pSRRadix3Descriptor; MEMORY_DESCRIPTOR *pGspFmcArgumentsDescriptor; @@ -373,6 +441,9 @@ struct KernelGsp { MEMORY_DESCRIPTOR *pMemDesc_simAccessBuf; SimAccessBuffer *pSimAccessBuf; NvP64 pSimAccessBufPriv; + MEMORY_DESCRIPTOR *pNotifyOpSurfMemDesc; + NotifyOpSharedSurface *pNotifyOpSurf; + NvP64 pNotifyOpSurfPriv; MEMORY_DESCRIPTOR *pProfilerSamplesMD; void *pProfilerSamplesMDPriv; void *pProfilerSamples; @@ -382,6 +453,7 @@ struct KernelGsp { NvBool bScrubberUcodeSupported; NvU32 fwHeapParamBaseSize; NvBool bBootGspRmWithBoostClocks; + NvU8 ememPort; }; #ifndef __NVOC_CLASS_KernelGsp_TYPEDEF__ @@ -425,8 +497,14 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspAllocBootArgs_HAL(pGpu, pKernelGsp) kgspAllocBootArgs_DISPATCH(pGpu, pKernelGsp) #define kgspFreeBootArgs(pGpu, pKernelGsp) kgspFreeBootArgs_DISPATCH(pGpu, pKernelGsp) #define kgspFreeBootArgs_HAL(pGpu, pKernelGsp) kgspFreeBootArgs_DISPATCH(pGpu, pKernelGsp) -#define kgspBootstrapRiscvOSEarly(pGpu, pKernelGsp, pGspFw) kgspBootstrapRiscvOSEarly_DISPATCH(pGpu, pKernelGsp, pGspFw) -#define kgspBootstrapRiscvOSEarly_HAL(pGpu, pKernelGsp, pGspFw) kgspBootstrapRiscvOSEarly_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspProgramLibosBootArgsAddr(pGpu, pKernelGsp) kgspProgramLibosBootArgsAddr_DISPATCH(pGpu, pKernelGsp) +#define kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp) kgspProgramLibosBootArgsAddr_DISPATCH(pGpu, pKernelGsp) +#define kgspSetCmdQueueHead(pGpu, pKernelGsp, queueIdx, value) kgspSetCmdQueueHead_DISPATCH(pGpu, pKernelGsp, queueIdx, value) +#define kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, queueIdx, value) kgspSetCmdQueueHead_DISPATCH(pGpu, pKernelGsp, queueIdx, value) +#define kgspPrepareForBootstrap(pGpu, pKernelGsp, pGspFw) kgspPrepareForBootstrap_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspPrepareForBootstrap_HAL(pGpu, pKernelGsp, pGspFw) kgspPrepareForBootstrap_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspBootstrap(pGpu, pKernelGsp, pGspFw) kgspBootstrap_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspBootstrap_HAL(pGpu, pKernelGsp, pGspFw) kgspBootstrap_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspGetGspRmBootUcodeStorage(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) kgspGetGspRmBootUcodeStorage_DISPATCH(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) #define kgspGetGspRmBootUcodeStorage_HAL(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) kgspGetGspRmBootUcodeStorage_DISPATCH(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc) #define kgspGetBinArchiveGspRmBoot(pKernelGsp) kgspGetBinArchiveGspRmBoot_DISPATCH(pKernelGsp) @@ -451,6 +529,10 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspReadUcodeFuseVersion_HAL(pGpu, pKernelGsp, ucodeId) kgspReadUcodeFuseVersion_DISPATCH(pGpu, pKernelGsp, ucodeId) #define kgspResetHw(pGpu, pKernelGsp) kgspResetHw_DISPATCH(pGpu, pKernelGsp) #define kgspResetHw_HAL(pGpu, pKernelGsp) kgspResetHw_DISPATCH(pGpu, pKernelGsp) +#define kgspHealthCheck(pGpu, pKernelGsp) kgspHealthCheck_DISPATCH(pGpu, pKernelGsp) +#define kgspHealthCheck_HAL(pGpu, pKernelGsp) kgspHealthCheck_DISPATCH(pGpu, pKernelGsp) +#define kgspService(pGpu, pKernelGsp) kgspService_DISPATCH(pGpu, pKernelGsp) +#define kgspService_HAL(pGpu, pKernelGsp) kgspService_DISPATCH(pGpu, pKernelGsp) #define kgspIsWpr2Up(pGpu, pKernelGsp) kgspIsWpr2Up_DISPATCH(pGpu, pKernelGsp) #define kgspIsWpr2Up_HAL(pGpu, pKernelGsp) kgspIsWpr2Up_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) @@ -459,10 +541,12 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetPrescrubbedTopFbSize_HAL(pGpu, pKernelGsp) kgspGetPrescrubbedTopFbSize_DISPATCH(pGpu, pKernelGsp) #define kgspExtractVbiosFromRom(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_DISPATCH(pGpu, pKernelGsp, ppVbiosImg) #define kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_DISPATCH(pGpu, pKernelGsp, ppVbiosImg) -#define kgspExecuteFwsecFrts(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) kgspExecuteFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) -#define kgspExecuteFwsecFrts_HAL(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) kgspExecuteFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) -#define kgspExecuteFwsecSb(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode) -#define kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode) +#define kgspPrepareForFwsecFrts(pGpu, pKernelGsp, pFwsecUcode, frtsOffset, preparedCmd) kgspPrepareForFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset, preparedCmd) +#define kgspPrepareForFwsecFrts_HAL(pGpu, pKernelGsp, pFwsecUcode, frtsOffset, preparedCmd) kgspPrepareForFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset, preparedCmd) +#define kgspPrepareForFwsecSb(pGpu, pKernelGsp, pFwsecUcode, preparedCmd) kgspPrepareForFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, preparedCmd) +#define kgspPrepareForFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode, preparedCmd) kgspPrepareForFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, preparedCmd) +#define kgspExecuteFwsec(pGpu, pKernelGsp, preparedCmd) kgspExecuteFwsec_DISPATCH(pGpu, pKernelGsp, preparedCmd) +#define kgspExecuteFwsec_HAL(pGpu, pKernelGsp, preparedCmd) kgspExecuteFwsec_DISPATCH(pGpu, pKernelGsp, preparedCmd) #define kgspExecuteScrubberIfNeeded(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp) #define kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp) #define kgspExecuteBooterLoad(pGpu, pKernelGsp, sysmemAddrOfData) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfData) @@ -471,6 +555,14 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp, sysmemAddrOfSuspendResumeData) #define kgspExecuteHsFalcon(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) #define kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) +#define kgspWaitForProcessorSuspend(pGpu, pKernelGsp) kgspWaitForProcessorSuspend_DISPATCH(pGpu, pKernelGsp) +#define kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp) kgspWaitForProcessorSuspend_DISPATCH(pGpu, pKernelGsp) +#define kgspSavePowerMgmtState(pGpu, pKernelGsp) kgspSavePowerMgmtState_DISPATCH(pGpu, pKernelGsp) +#define kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp) kgspSavePowerMgmtState_DISPATCH(pGpu, pKernelGsp) +#define kgspRestorePowerMgmtState(pGpu, pKernelGsp) kgspRestorePowerMgmtState_DISPATCH(pGpu, pKernelGsp) +#define kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp) kgspRestorePowerMgmtState_DISPATCH(pGpu, pKernelGsp) +#define kgspFreeSuspendResumeData(pGpu, pKernelGsp) kgspFreeSuspendResumeData_DISPATCH(pGpu, pKernelGsp) +#define kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp) kgspFreeSuspendResumeData_DISPATCH(pGpu, pKernelGsp) #define kgspWaitForGfwBootOk(pGpu, pKernelGsp) kgspWaitForGfwBootOk_DISPATCH(pGpu, pKernelGsp) #define kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp) kgspWaitForGfwBootOk_DISPATCH(pGpu, pKernelGsp) #define kgspGetBinArchiveBooterLoadUcode(pKernelGsp) kgspGetBinArchiveBooterLoadUcode_DISPATCH(pKernelGsp) @@ -491,6 +583,12 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetSignatureSectionNamePrefix_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp) #define kgspSetupGspFmcArgs(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) #define kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) +#define kgspReadEmem(pKernelGsp, offset, size, pBuf) kgspReadEmem_DISPATCH(pKernelGsp, offset, size, pBuf) +#define kgspReadEmem_HAL(pKernelGsp, offset, size, pBuf) kgspReadEmem_DISPATCH(pKernelGsp, offset, size, pBuf) +#define kgspIssueNotifyOp(pGpu, pKernelGsp, opCode, pArgs, argc) kgspIssueNotifyOp_DISPATCH(pGpu, pKernelGsp, opCode, pArgs, argc) +#define kgspIssueNotifyOp_HAL(pGpu, pKernelGsp, opCode, pArgs, argc) kgspIssueNotifyOp_DISPATCH(pGpu, pKernelGsp, opCode, pArgs, argc) +#define kgspCheckGspRmCcCleanup(pGpu, pKernelGsp) kgspCheckGspRmCcCleanup_DISPATCH(pGpu, pKernelGsp) +#define kgspCheckGspRmCcCleanup_HAL(pGpu, pKernelGsp) kgspCheckGspRmCcCleanup_DISPATCH(pGpu, pKernelGsp) #define kgspConfigured(arg0) kgspConfigured_DISPATCH(arg0) #define kgspPriRead(arg0, offset) kgspPriRead_DISPATCH(arg0, offset) #define kgspRegWrite(pGpu, pKernelFlcn, offset, data) kgspRegWrite_DISPATCH(pGpu, pKernelFlcn, offset, data) @@ -503,7 +601,6 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspSyncBufferDescriptor(arg0, pBufDesc, offset, size) kgspSyncBufferDescriptor_DISPATCH(arg0, pBufDesc, offset, size) #define kgspRegRead(pGpu, pKernelFlcn, offset) kgspRegRead_DISPATCH(pGpu, pKernelFlcn, offset) #define kgspIsPresent(pGpu, pEngstate) kgspIsPresent_DISPATCH(pGpu, pEngstate) -#define kgspReadEmem(arg0, offset, size, pBuf) kgspReadEmem_DISPATCH(arg0, offset, size, pBuf) #define kgspStateLoad(pGpu, pEngstate, arg0) kgspStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgspGetScratchOffsets(arg0, scratchGroupId) kgspGetScratchOffsets_DISPATCH(arg0, scratchGroupId) #define kgspUnload(arg0) kgspUnload_DISPATCH(arg0) @@ -521,125 +618,15 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspStatePostLoad(pGpu, pEngstate, arg0) kgspStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kgspUnmapBufferDescriptor(arg0, pBufDesc) kgspUnmapBufferDescriptor_DISPATCH(arg0, pBufDesc) #define kgspReadDmem(arg0, offset, size, pBuf) kgspReadDmem_DISPATCH(arg0, offset, size, pBuf) -void kgspProgramLibosBootArgsAddr_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline void kgspProgramLibosBootArgsAddr(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspProgramLibosBootArgsAddr(pGpu, pKernelGsp) kgspProgramLibosBootArgsAddr_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp) kgspProgramLibosBootArgsAddr(pGpu, pKernelGsp) - -NV_STATUS kgspSetCmdQueueHead_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 queueIdx, NvU32 value); - - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspSetCmdQueueHead(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 queueIdx, NvU32 value) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspSetCmdQueueHead(pGpu, pKernelGsp, queueIdx, value) kgspSetCmdQueueHead_TU102(pGpu, pKernelGsp, queueIdx, value) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, queueIdx, value) kgspSetCmdQueueHead(pGpu, pKernelGsp, queueIdx, value) - -NvBool kgspHealthCheck_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NvBool kgspHealthCheck(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_FALSE; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspHealthCheck(pGpu, pKernelGsp) kgspHealthCheck_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspHealthCheck_HAL(pGpu, pKernelGsp) kgspHealthCheck(pGpu, pKernelGsp) - -NvU32 kgspService_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NvU32 kgspService(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return 0; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspService(pGpu, pKernelGsp) kgspService_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspService_HAL(pGpu, pKernelGsp) kgspService(pGpu, pKernelGsp) - -NV_STATUS kgspWaitForProcessorSuspend_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspWaitForProcessorSuspend(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspWaitForProcessorSuspend(pGpu, pKernelGsp) kgspWaitForProcessorSuspend_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp) kgspWaitForProcessorSuspend(pGpu, pKernelGsp) - -NV_STATUS kgspSavePowerMgmtState_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspSavePowerMgmtState(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspSavePowerMgmtState(pGpu, pKernelGsp) kgspSavePowerMgmtState_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp) kgspSavePowerMgmtState(pGpu, pKernelGsp) - -NV_STATUS kgspRestorePowerMgmtState_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspRestorePowerMgmtState(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspRestorePowerMgmtState(pGpu, pKernelGsp) kgspRestorePowerMgmtState_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp) kgspRestorePowerMgmtState(pGpu, pKernelGsp) - -void kgspFreeSuspendResumeData_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline void kgspFreeSuspendResumeData(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspFreeSuspendResumeData(pGpu, pKernelGsp) kgspFreeSuspendResumeData_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp) kgspFreeSuspendResumeData(pGpu, pKernelGsp) - NV_STATUS kgspConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, ENGDESCRIPTOR arg0); static inline NV_STATUS kgspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, ENGDESCRIPTOR arg0) { return pKernelGsp->__kgspConstructEngine__(pGpu, pKernelGsp, arg0); } -void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[168]); +void kgspRegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[171]); -static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[168]) { +static inline void kgspRegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, IntrServiceRecord pRecords[171]) { pKernelGsp->__kgspRegisterIntrService__(pGpu, pKernelGsp, pRecords); } @@ -653,6 +640,10 @@ void kgspConfigureFalcon_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp void kgspConfigureFalcon_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +static inline void kgspConfigureFalcon_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_PRECOMP(0); +} + static inline void kgspConfigureFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { pKernelGsp->__kgspConfigureFalcon__(pGpu, pKernelGsp); } @@ -661,6 +652,10 @@ NvBool kgspIsDebugModeEnabled_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKern NvBool kgspIsDebugModeEnabled_GA100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +static inline NvBool kgspIsDebugModeEnabled_108313(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + static inline NvBool kgspIsDebugModeEnabled_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspIsDebugModeEnabled__(pGpu, pKernelGsp); } @@ -669,6 +664,10 @@ NV_STATUS kgspAllocBootArgs_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernel NV_STATUS kgspAllocBootArgs_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +static inline NV_STATUS kgspAllocBootArgs_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS kgspAllocBootArgs_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspAllocBootArgs__(pGpu, pKernelGsp); } @@ -677,18 +676,56 @@ void kgspFreeBootArgs_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); void kgspFreeBootArgs_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +static inline void kgspFreeBootArgs_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_PRECOMP(0); +} + static inline void kgspFreeBootArgs_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { pKernelGsp->__kgspFreeBootArgs__(pGpu, pKernelGsp); } -NV_STATUS kgspBootstrapRiscvOSEarly_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); +void kgspProgramLibosBootArgsAddr_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); -NV_STATUS kgspBootstrapRiscvOSEarly_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); +static inline void kgspProgramLibosBootArgsAddr_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kgspProgramLibosBootArgsAddr_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + pKernelGsp->__kgspProgramLibosBootArgsAddr__(pGpu, pKernelGsp); +} + +NV_STATUS kgspSetCmdQueueHead_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 queueIdx, NvU32 value); -NV_STATUS kgspBootstrapRiscvOSEarly_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); +static inline NV_STATUS kgspSetCmdQueueHead_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 queueIdx, NvU32 value) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} -static inline NV_STATUS kgspBootstrapRiscvOSEarly_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { - return pKernelGsp->__kgspBootstrapRiscvOSEarly__(pGpu, pKernelGsp, pGspFw); +static inline NV_STATUS kgspSetCmdQueueHead_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 queueIdx, NvU32 value) { + return pKernelGsp->__kgspSetCmdQueueHead__(pGpu, pKernelGsp, queueIdx, value); +} + +NV_STATUS kgspPrepareForBootstrap_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + +NV_STATUS kgspPrepareForBootstrap_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + +static inline NV_STATUS kgspPrepareForBootstrap_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspPrepareForBootstrap_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + return pKernelGsp->__kgspPrepareForBootstrap__(pGpu, pKernelGsp, pGspFw); +} + +NV_STATUS kgspBootstrap_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + +NV_STATUS kgspBootstrap_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); + +static inline NV_STATUS kgspBootstrap_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspBootstrap_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + return pKernelGsp->__kgspBootstrap__(pGpu, pKernelGsp, pGspFw); } void kgspGetGspRmBootUcodeStorage_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, BINDATA_STORAGE **ppBinStorageImage, BINDATA_STORAGE **ppBinStorageDesc); @@ -697,6 +734,10 @@ void kgspGetGspRmBootUcodeStorage_GA102(struct OBJGPU *pGpu, struct KernelGsp *p void kgspGetGspRmBootUcodeStorage_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, BINDATA_STORAGE **ppBinStorageImage, BINDATA_STORAGE **ppBinStorageDesc); +static inline void kgspGetGspRmBootUcodeStorage_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, BINDATA_STORAGE **ppBinStorageImage, BINDATA_STORAGE **ppBinStorageDesc) { + NV_ASSERT_PRECOMP(0); +} + static inline void kgspGetGspRmBootUcodeStorage_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, BINDATA_STORAGE **ppBinStorageImage, BINDATA_STORAGE **ppBinStorageDesc) { pKernelGsp->__kgspGetGspRmBootUcodeStorage__(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc); } @@ -711,6 +752,10 @@ const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_GH100(struct KernelGsp *pKerne const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_AD102(struct KernelGsp *pKernelGsp); +static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_80f438(struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + static inline const BINDATA_ARCHIVE *kgspGetBinArchiveGspRmBoot_DISPATCH(struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetBinArchiveGspRmBoot__(pKernelGsp); } @@ -769,6 +814,10 @@ NV_STATUS kgspCalculateFbLayout_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKe NV_STATUS kgspCalculateFbLayout_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw); +static inline NV_STATUS kgspCalculateFbLayout_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS kgspCalculateFbLayout_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw) { return pKernelGsp->__kgspCalculateFbLayout__(pGpu, pKernelGsp, pGspFw); } @@ -781,6 +830,10 @@ static inline NvU32 kgspGetNonWprHeapSize_d505ea(struct OBJGPU *pGpu, struct Ker return 2097152; } +static inline NvU32 kgspGetNonWprHeapSize_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NvU32 kgspGetNonWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetNonWprHeapSize__(pGpu, pKernelGsp); } @@ -789,6 +842,10 @@ NV_STATUS kgspExecuteSequencerCommand_TU102(struct OBJGPU *pGpu, struct KernelGs NV_STATUS kgspExecuteSequencerCommand_GA102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pPayLoad, NvU32 payloadSize); +static inline NV_STATUS kgspExecuteSequencerCommand_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pPayLoad, NvU32 payloadSize) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS kgspExecuteSequencerCommand_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pPayLoad, NvU32 payloadSize) { return pKernelGsp->__kgspExecuteSequencerCommand__(pGpu, pKernelGsp, opCode, pPayLoad, payloadSize); } @@ -799,6 +856,10 @@ static inline NvU32 kgspReadUcodeFuseVersion_b2b553(struct OBJGPU *pGpu, struct NvU32 kgspReadUcodeFuseVersion_GA100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 ucodeId); +static inline NvU32 kgspReadUcodeFuseVersion_474d46(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 ucodeId) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + static inline NvU32 kgspReadUcodeFuseVersion_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 ucodeId) { return pKernelGsp->__kgspReadUcodeFuseVersion__(pGpu, pKernelGsp, ucodeId); } @@ -807,14 +868,42 @@ NV_STATUS kgspResetHw_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); NV_STATUS kgspResetHw_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +static inline NV_STATUS kgspResetHw_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS kgspResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspResetHw__(pGpu, pKernelGsp); } +NvBool kgspHealthCheck_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NvBool kgspHealthCheck_108313(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + +static inline NvBool kgspHealthCheck_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspHealthCheck__(pGpu, pKernelGsp); +} + +NvU32 kgspService_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NvU32 kgspService_474d46(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + +static inline NvU32 kgspService_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspService__(pGpu, pKernelGsp); +} + NvBool kgspIsWpr2Up_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); NvBool kgspIsWpr2Up_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +static inline NvBool kgspIsWpr2Up_108313(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + static inline NvBool kgspIsWpr2Up_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspIsWpr2Up__(pGpu, pKernelGsp); } @@ -825,6 +914,10 @@ static inline NvU32 kgspGetFrtsSize_4a4dee(struct OBJGPU *pGpu, struct KernelGsp return 0; } +static inline NvU32 kgspGetFrtsSize_474d46(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + static inline NvU32 kgspGetFrtsSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetFrtsSize__(pGpu, pKernelGsp); } @@ -837,6 +930,10 @@ static inline NvU64 kgspGetPrescrubbedTopFbSize_604eb7(struct OBJGPU *pGpu, stru return (+18446744073709551615ULL); } +static inline NvU64 kgspGetPrescrubbedTopFbSize_474d46(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + static inline NvU64 kgspGetPrescrubbedTopFbSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetPrescrubbedTopFbSize__(pGpu, pKernelGsp); } @@ -847,28 +944,46 @@ static inline NV_STATUS kgspExtractVbiosFromRom_395e98(struct OBJGPU *pGpu, stru return NV_ERR_NOT_SUPPORTED; } +static inline NV_STATUS kgspExtractVbiosFromRom_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS kgspExtractVbiosFromRom_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { return pKernelGsp->__kgspExtractVbiosFromRom__(pGpu, pKernelGsp, ppVbiosImg); } -NV_STATUS kgspExecuteFwsecFrts_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU64 frtsOffset); +NV_STATUS kgspPrepareForFwsecFrts_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU64 frtsOffset, KernelGspPreparedFwsecCmd *preparedCmd); -static inline NV_STATUS kgspExecuteFwsecFrts_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU64 frtsOffset) { +static inline NV_STATUS kgspPrepareForFwsecFrts_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU64 frtsOffset, KernelGspPreparedFwsecCmd *preparedCmd) { NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); } -static inline NV_STATUS kgspExecuteFwsecFrts_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU64 frtsOffset) { - return pKernelGsp->__kgspExecuteFwsecFrts__(pGpu, pKernelGsp, pFwsecUcode, frtsOffset); +static inline NV_STATUS kgspPrepareForFwsecFrts_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU64 frtsOffset, KernelGspPreparedFwsecCmd *preparedCmd) { + return pKernelGsp->__kgspPrepareForFwsecFrts__(pGpu, pKernelGsp, pFwsecUcode, frtsOffset, preparedCmd); } -NV_STATUS kgspExecuteFwsecSb_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode); +NV_STATUS kgspPrepareForFwsecSb_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, KernelGspPreparedFwsecCmd *preparedCmd); -static inline NV_STATUS kgspExecuteFwsecSb_ac1694(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { - return NV_OK; +static inline NV_STATUS kgspPrepareForFwsecSb_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, KernelGspPreparedFwsecCmd *preparedCmd) { + return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS kgspExecuteFwsecSb_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { - return pKernelGsp->__kgspExecuteFwsecSb__(pGpu, pKernelGsp, pFwsecUcode); +static inline NV_STATUS kgspPrepareForFwsecSb_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, KernelGspPreparedFwsecCmd *preparedCmd) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspPrepareForFwsecSb_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, KernelGspPreparedFwsecCmd *preparedCmd) { + return pKernelGsp->__kgspPrepareForFwsecSb__(pGpu, pKernelGsp, pFwsecUcode, preparedCmd); +} + +NV_STATUS kgspExecuteFwsec_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspPreparedFwsecCmd *preparedCmd); + +static inline NV_STATUS kgspExecuteFwsec_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspPreparedFwsecCmd *preparedCmd) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspExecuteFwsec_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspPreparedFwsecCmd *preparedCmd) { + return pKernelGsp->__kgspExecuteFwsec__(pGpu, pKernelGsp, preparedCmd); } NV_STATUS kgspExecuteScrubberIfNeeded_AD102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); @@ -913,10 +1028,54 @@ static inline NV_STATUS kgspExecuteHsFalcon_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspExecuteHsFalcon__(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1); } +NV_STATUS kgspWaitForProcessorSuspend_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NV_STATUS kgspWaitForProcessorSuspend_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspWaitForProcessorSuspend_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspWaitForProcessorSuspend__(pGpu, pKernelGsp); +} + +NV_STATUS kgspSavePowerMgmtState_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NV_STATUS kgspSavePowerMgmtState_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspSavePowerMgmtState_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspSavePowerMgmtState__(pGpu, pKernelGsp); +} + +NV_STATUS kgspRestorePowerMgmtState_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NV_STATUS kgspRestorePowerMgmtState_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspRestorePowerMgmtState_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspRestorePowerMgmtState__(pGpu, pKernelGsp); +} + +void kgspFreeSuspendResumeData_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline void kgspFreeSuspendResumeData_f2d351(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_PRECOMP(0); +} + +static inline void kgspFreeSuspendResumeData_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + pKernelGsp->__kgspFreeSuspendResumeData__(pGpu, pKernelGsp); +} + NV_STATUS kgspWaitForGfwBootOk_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); NV_STATUS kgspWaitForGfwBootOk_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); +static inline NV_STATUS kgspWaitForGfwBootOk_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS kgspWaitForGfwBootOk_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspWaitForGfwBootOk__(pGpu, pKernelGsp); } @@ -965,6 +1124,10 @@ static inline NvU64 kgspGetMinWprHeapSizeMB_cc88c3(struct OBJGPU *pGpu, struct K return pGpu->bVgpuGspPluginOffloadEnabled ? (565U) : (86U); } +static inline NvU64 kgspGetMinWprHeapSizeMB_b2b553(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return 0; +} + static inline NvU64 kgspGetMinWprHeapSizeMB_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetMinWprHeapSizeMB__(pGpu, pKernelGsp); } @@ -977,6 +1140,10 @@ static inline NvU64 kgspGetMaxWprHeapSizeMB_55728f(struct OBJGPU *pGpu, struct K return pGpu->bVgpuGspPluginOffloadEnabled ? (1040U) : (278U); } +static inline NvU64 kgspGetMaxWprHeapSizeMB_b2b553(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return 0; +} + static inline NvU64 kgspGetMaxWprHeapSizeMB_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetMaxWprHeapSizeMB__(pGpu, pKernelGsp); } @@ -989,6 +1156,10 @@ static inline NvU32 kgspGetFwHeapParamOsCarveoutSize_4b5307(struct OBJGPU *pGpu, return pGpu->bVgpuGspPluginOffloadEnabled ? (36 << 20) : (22 << 20); } +static inline NvU32 kgspGetFwHeapParamOsCarveoutSize_b2b553(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return 0; +} + static inline NvU32 kgspGetFwHeapParamOsCarveoutSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetFwHeapParamOsCarveoutSize__(pGpu, pKernelGsp); } @@ -1019,6 +1190,10 @@ static inline const char *kgspGetSignatureSectionNamePrefix_789efb(struct OBJGPU return ".fwsignature_"; } +static inline const char *kgspGetSignatureSectionNamePrefix_80f438(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + static inline const char *kgspGetSignatureSectionNamePrefix_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetSignatureSectionNamePrefix__(pGpu, pKernelGsp); } @@ -1033,6 +1208,36 @@ static inline NV_STATUS kgspSetupGspFmcArgs_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspSetupGspFmcArgs__(pGpu, pKernelGsp, pGspFw); } +void kgspReadEmem_TU102(struct KernelGsp *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf); + +static inline void kgspReadEmem_366c4c(struct KernelGsp *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf) { + NV_ASSERT(0); +} + +static inline void kgspReadEmem_DISPATCH(struct KernelGsp *pKernelGsp, NvU64 offset, NvU64 size, void *pBuf) { + pKernelGsp->__kgspReadEmem__(pKernelGsp, offset, size, pBuf); +} + +NV_STATUS kgspIssueNotifyOp_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pArgs, NvU32 argc); + +static inline NV_STATUS kgspIssueNotifyOp_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pArgs, NvU32 argc) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspIssueNotifyOp_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 opCode, NvU32 *pArgs, NvU32 argc) { + return pKernelGsp->__kgspIssueNotifyOp__(pGpu, pKernelGsp, opCode, pArgs, argc); +} + +NV_STATUS kgspCheckGspRmCcCleanup_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NV_STATUS kgspCheckGspRmCcCleanup_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspCheckGspRmCcCleanup_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspCheckGspRmCcCleanup__(pGpu, pKernelGsp); +} + static inline NvBool kgspConfigured_DISPATCH(struct KernelGsp *arg0) { return arg0->__kgspConfigured__(arg0); } @@ -1081,10 +1286,6 @@ static inline NvBool kgspIsPresent_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEng return pEngstate->__kgspIsPresent__(pGpu, pEngstate); } -static inline void kgspReadEmem_DISPATCH(struct KernelGsp *arg0, NvU64 offset, NvU64 size, void *pBuf) { - arg0->__kgspReadEmem__(arg0, offset, size, pBuf); -} - static inline NV_STATUS kgspStateLoad_DISPATCH(POBJGPU pGpu, struct KernelGsp *pEngstate, NvU32 arg0) { return pEngstate->__kgspStateLoad__(pGpu, pEngstate, arg0); } @@ -1231,6 +1432,17 @@ static inline void kgspSetupLibosInitArgs(struct OBJGPU *pGpu, struct KernelGsp #define kgspSetupLibosInitArgs(pGpu, pKernelGsp) kgspSetupLibosInitArgs_IMPL(pGpu, pKernelGsp) #endif //__nvoc_kernel_gsp_h_disabled +NV_STATUS kgspQueueAsyncInitRpcs_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspQueueAsyncInitRpcs(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspQueueAsyncInitRpcs(pGpu, pKernelGsp) kgspQueueAsyncInitRpcs_IMPL(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + void kgspRpcRecvEvents_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -1354,6 +1566,8 @@ void kgspFreeVbiosImg(KernelGspVbiosImg *pVbiosImg); /* Free a KernelGspFlcnUcode structure */ void kgspFreeFlcnUcode(KernelGspFlcnUcode *pFlcnUcode); +void kgspLogRpcDebugInfo(struct OBJGPU *pGpu, OBJRPC *pRpc, NvU32 errorNum, NvBool bPollingForRpcResponse); + #endif // KERNEL_GSP_H #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kernel_head_nvoc.c b/src/nvidia/generated/g_kernel_head_nvoc.c index 873e0791b7..24db371d00 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.c +++ b/src/nvidia/generated/g_kernel_head_nvoc.c @@ -222,23 +222,31 @@ void __nvoc_init_KernelHead(KernelHead *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_KernelHead(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelHead(KernelHead **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelHead(KernelHead **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelHead *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHead), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelHead)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHead); pThis->__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_Object); @@ -256,16 +264,25 @@ NV_STATUS __nvoc_objCreate_KernelHead(KernelHead **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_KernelHead(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelHead_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelHead_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelHead)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_head_nvoc.h b/src/nvidia/generated/g_kernel_head_nvoc.h index 793157a1cd..94a51ad051 100644 --- a/src/nvidia/generated/g_kernel_head_nvoc.h +++ b/src/nvidia/generated/g_kernel_head_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,11 +47,16 @@ extern "C" { /* ------------------------ Types definitions ------------------------------ */ /* ------------------------ Macros & Defines ------------------------------- */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_HEAD_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct __nvoc_inner_struc_KernelHead_1__ { struct { NvU32 Total; @@ -61,7 +66,9 @@ struct __nvoc_inner_struc_KernelHead_1__ { struct { VBLANKCALLBACK *pListLL; VBLANKCALLBACK *pListNL; + VBLANKCALLBACK CheckVblankCount; } Callback; + NvU32 VblankCountTimeout; NvU32 IntrState; }; @@ -329,6 +336,16 @@ static inline void kheadDeleteVblankCallback(struct OBJGPU *pGpu, struct KernelH #define kheadDeleteVblankCallback(pGpu, pKernelHead, arg0) kheadDeleteVblankCallback_IMPL(pGpu, pKernelHead, arg0) #endif //__nvoc_kernel_head_h_disabled +void kheadPauseVblankCbNotifications_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, VBLANKCALLBACK *arg0); + +#ifdef __nvoc_kernel_head_h_disabled +static inline void kheadPauseVblankCbNotifications(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, VBLANKCALLBACK *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelHead was disabled!"); +} +#else //__nvoc_kernel_head_h_disabled +#define kheadPauseVblankCbNotifications(pGpu, pKernelHead, arg0) kheadPauseVblankCbNotifications_IMPL(pGpu, pKernelHead, arg0) +#endif //__nvoc_kernel_head_h_disabled + NvU32 kheadCheckVblankCallbacksQueued_IMPL(struct OBJGPU *pGpu, struct KernelHead *pKernelHead, NvU32 arg0, NvU32 *arg1); #ifdef __nvoc_kernel_head_h_disabled diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c index 0f9481e31e..254ef3d6db 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.c @@ -119,21 +119,26 @@ void __nvoc_init_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr *pThis) { __nvoc_init_funcTable_KernelHostVgpuDeviceShr(pThis); } -NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelHostVgpuDeviceShr *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHostVgpuDeviceShr), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceShr)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHostVgpuDeviceShr); pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -148,16 +153,25 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceShr(KernelHostVgpuDeviceShr **ppT status = __nvoc_ctor_KernelHostVgpuDeviceShr(pThis); if (status != NV_OK) goto __nvoc_objCreate_KernelHostVgpuDeviceShr_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelHostVgpuDeviceShr_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceShr)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -331,10 +345,6 @@ static void __nvoc_thunk_RmResource_kernelhostvgpudeviceapiControl_Epilogue(stru rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_kernelhostvgpudeviceapiControlLookup(struct KernelHostVgpuDeviceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetInternalObjectHandle(struct KernelHostVgpuDeviceApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_GpuResource.offset)); } @@ -367,6 +377,10 @@ static NV_STATUS __nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerializa return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_kernelhostvgpudeviceapiIsPartialUnmapSupported(struct KernelHostVgpuDeviceApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_kernelhostvgpudeviceapiPreDestruct(struct KernelHostVgpuDeviceApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelHostVgpuDeviceApi_RsResource.offset)); } @@ -534,6 +548,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelHo /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition" +#endif + }, + { /* [9] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) kernelhostvgpudeviceapiCtrlCmdFreeStates_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa084010cu, + /*paramSize=*/ sizeof(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_KernelHostVgpuDeviceApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "kernelhostvgpudeviceapiCtrlCmdFreeStates" #endif }, @@ -541,7 +570,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelHo const struct NVOC_EXPORT_INFO __nvoc_export_info_KernelHostVgpuDeviceApi = { - /*numEntries=*/ 9, + /*numEntries=*/ 10, /*pExportEntries=*/ __nvoc_exported_method_def_KernelHostVgpuDeviceApi }; @@ -623,6 +652,10 @@ static void __nvoc_init_funcTable_KernelHostVgpuDeviceApi_1(KernelHostVgpuDevice pThis->__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__ = &kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__kernelhostvgpudeviceapiCtrlCmdFreeStates__ = &kernelhostvgpudeviceapiCtrlCmdFreeStates_IMPL; +#endif + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_KernelHostVgpuDeviceApi_resCanCopy; pThis->__kernelhostvgpudeviceapiShareCallback__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiShareCallback; @@ -651,8 +684,6 @@ static void __nvoc_init_funcTable_KernelHostVgpuDeviceApi_1(KernelHostVgpuDevice pThis->__kernelhostvgpudeviceapiControl_Epilogue__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiControl_Epilogue; - pThis->__kernelhostvgpudeviceapiControlLookup__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiControlLookup; - pThis->__kernelhostvgpudeviceapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiGetInternalObjectHandle; pThis->__kernelhostvgpudeviceapiControl__ = &__nvoc_thunk_GpuResource_kernelhostvgpudeviceapiControl; @@ -669,6 +700,8 @@ static void __nvoc_init_funcTable_KernelHostVgpuDeviceApi_1(KernelHostVgpuDevice pThis->__kernelhostvgpudeviceapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_kernelhostvgpudeviceapiControlSerialization_Prologue; + pThis->__kernelhostvgpudeviceapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiIsPartialUnmapSupported; + pThis->__kernelhostvgpudeviceapiPreDestruct__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiPreDestruct; pThis->__kernelhostvgpudeviceapiIsDuplicate__ = &__nvoc_thunk_RsResource_kernelhostvgpudeviceapiIsDuplicate; @@ -704,21 +737,26 @@ void __nvoc_init_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi *pThis) { __nvoc_init_funcTable_KernelHostVgpuDeviceApi(pThis); } -NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelHostVgpuDeviceApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelHostVgpuDeviceApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelHostVgpuDeviceApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -733,16 +771,25 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi **ppT status = __nvoc_ctor_KernelHostVgpuDeviceApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelHostVgpuDeviceApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelHostVgpuDeviceApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelHostVgpuDeviceApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h index d7870212d5..f5547b82b7 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h @@ -41,11 +41,16 @@ extern "C" { #include "class/cla084.h" + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_HOSTVGPUDEVICEAPI_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelHostVgpuDeviceShr { const struct NVOC_RTTI *__nvoc_rtti; struct RsShared __nvoc_base_RsShared; @@ -94,11 +99,16 @@ void kernelhostvgpudeviceshrDestruct_IMPL(struct KernelHostVgpuDeviceShr *pKerne void destroyKernelHostVgpuDeviceShare(struct OBJGPU *pGpu, struct KernelHostVgpuDeviceShr* pShare); + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_HOSTVGPUDEVICEAPI_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelHostVgpuDeviceApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -121,6 +131,7 @@ struct KernelHostVgpuDeviceApi { NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdEventSetNotification__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *); NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__)(struct KernelHostVgpuDeviceApi *); + NV_STATUS (*__kernelhostvgpudeviceapiCtrlCmdFreeStates__)(struct KernelHostVgpuDeviceApi *, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS *); NvBool (*__kernelhostvgpudeviceapiShareCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__kernelhostvgpudeviceapiCheckMemInterUnmap__)(struct KernelHostVgpuDeviceApi *, NvBool); NV_STATUS (*__kernelhostvgpudeviceapiGetOrAllocNotifShare__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, struct NotifShare **); @@ -134,7 +145,6 @@ struct KernelHostVgpuDeviceApi { NV_STATUS (*__kernelhostvgpudeviceapiInternalControlForward__)(struct KernelHostVgpuDeviceApi *, NvU32, void *, NvU32); NV_STATUS (*__kernelhostvgpudeviceapiUnmapFrom__)(struct KernelHostVgpuDeviceApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__kernelhostvgpudeviceapiControl_Epilogue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__kernelhostvgpudeviceapiControlLookup__)(struct KernelHostVgpuDeviceApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__kernelhostvgpudeviceapiGetInternalObjectHandle__)(struct KernelHostVgpuDeviceApi *); NV_STATUS (*__kernelhostvgpudeviceapiControl__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kernelhostvgpudeviceapiUnmap__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -143,6 +153,7 @@ struct KernelHostVgpuDeviceApi { NV_STATUS (*__kernelhostvgpudeviceapiControlFilter__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__kernelhostvgpudeviceapiUnregisterEvent__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__kernelhostvgpudeviceapiControlSerialization_Prologue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__kernelhostvgpudeviceapiIsPartialUnmapSupported__)(struct KernelHostVgpuDeviceApi *); void (*__kernelhostvgpudeviceapiPreDestruct__)(struct KernelHostVgpuDeviceApi *); NV_STATUS (*__kernelhostvgpudeviceapiIsDuplicate__)(struct KernelHostVgpuDeviceApi *, NvHandle, NvBool *); void (*__kernelhostvgpudeviceapiControlSerialization_Epilogue__)(struct KernelHostVgpuDeviceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -192,6 +203,7 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi**, Dy #define kernelhostvgpudeviceapiCtrlCmdEventSetNotification(pKernelHostVgpuDeviceApi, pSetEventParams) kernelhostvgpudeviceapiCtrlCmdEventSetNotification_DISPATCH(pKernelHostVgpuDeviceApi, pSetEventParams) #define kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition(pKernelHostVgpuDeviceApi) kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_DISPATCH(pKernelHostVgpuDeviceApi) +#define kernelhostvgpudeviceapiCtrlCmdFreeStates(pKernelHostVgpuDeviceApi, pParams) kernelhostvgpudeviceapiCtrlCmdFreeStates_DISPATCH(pKernelHostVgpuDeviceApi, pParams) #define kernelhostvgpudeviceapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) kernelhostvgpudeviceapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define kernelhostvgpudeviceapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) kernelhostvgpudeviceapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define kernelhostvgpudeviceapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) kernelhostvgpudeviceapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) @@ -205,7 +217,6 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi**, Dy #define kernelhostvgpudeviceapiInternalControlForward(pGpuResource, command, pParams, size) kernelhostvgpudeviceapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define kernelhostvgpudeviceapiUnmapFrom(pResource, pParams) kernelhostvgpudeviceapiUnmapFrom_DISPATCH(pResource, pParams) #define kernelhostvgpudeviceapiControl_Epilogue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define kernelhostvgpudeviceapiControlLookup(pResource, pParams, ppEntry) kernelhostvgpudeviceapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define kernelhostvgpudeviceapiGetInternalObjectHandle(pGpuResource) kernelhostvgpudeviceapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define kernelhostvgpudeviceapiControl(pGpuResource, pCallContext, pParams) kernelhostvgpudeviceapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define kernelhostvgpudeviceapiUnmap(pGpuResource, pCallContext, pCpuMapping) kernelhostvgpudeviceapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -214,6 +225,7 @@ NV_STATUS __nvoc_objCreate_KernelHostVgpuDeviceApi(KernelHostVgpuDeviceApi**, Dy #define kernelhostvgpudeviceapiControlFilter(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define kernelhostvgpudeviceapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) kernelhostvgpudeviceapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define kernelhostvgpudeviceapiControlSerialization_Prologue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define kernelhostvgpudeviceapiIsPartialUnmapSupported(pResource) kernelhostvgpudeviceapiIsPartialUnmapSupported_DISPATCH(pResource) #define kernelhostvgpudeviceapiPreDestruct(pResource) kernelhostvgpudeviceapiPreDestruct_DISPATCH(pResource) #define kernelhostvgpudeviceapiIsDuplicate(pResource, hMemory, pDuplicate) kernelhostvgpudeviceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define kernelhostvgpudeviceapiControlSerialization_Epilogue(pResource, pCallContext, pParams) kernelhostvgpudeviceapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -281,6 +293,12 @@ static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartitio return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition__(pKernelHostVgpuDeviceApi); } +NV_STATUS kernelhostvgpudeviceapiCtrlCmdFreeStates_IMPL(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS *pParams); + +static inline NV_STATUS kernelhostvgpudeviceapiCtrlCmdFreeStates_DISPATCH(struct KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS *pParams) { + return pKernelHostVgpuDeviceApi->__kernelhostvgpudeviceapiCtrlCmdFreeStates__(pKernelHostVgpuDeviceApi, pParams); +} + static inline NvBool kernelhostvgpudeviceapiShareCallback_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__kernelhostvgpudeviceapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -333,10 +351,6 @@ static inline void kernelhostvgpudeviceapiControl_Epilogue_DISPATCH(struct Kerne pResource->__kernelhostvgpudeviceapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS kernelhostvgpudeviceapiControlLookup_DISPATCH(struct KernelHostVgpuDeviceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__kernelhostvgpudeviceapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle kernelhostvgpudeviceapiGetInternalObjectHandle_DISPATCH(struct KernelHostVgpuDeviceApi *pGpuResource) { return pGpuResource->__kernelhostvgpudeviceapiGetInternalObjectHandle__(pGpuResource); } @@ -369,6 +383,10 @@ static inline NV_STATUS kernelhostvgpudeviceapiControlSerialization_Prologue_DIS return pResource->__kernelhostvgpudeviceapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool kernelhostvgpudeviceapiIsPartialUnmapSupported_DISPATCH(struct KernelHostVgpuDeviceApi *pResource) { + return pResource->__kernelhostvgpudeviceapiIsPartialUnmapSupported__(pResource); +} + static inline void kernelhostvgpudeviceapiPreDestruct_DISPATCH(struct KernelHostVgpuDeviceApi *pResource) { pResource->__kernelhostvgpudeviceapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c index 4f2704ad00..0366dc0c72 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.c +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.c @@ -147,7 +147,7 @@ void __nvoc_init_dataField_KernelIoctrl(KernelIoctrl *pThis, RmHalspecOwner *pRm PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx); // NVOC Property Hal field -- PDB_PROP_KIOCTRL_IS_MISSING - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000003UL) )) /* RmVariantHal: VF | PF_KERNEL_ONLY */ { pThis->setProperty(pThis, PDB_PROP_KIOCTRL_IS_MISSING, ((NvBool)(0 != 0))); } @@ -254,23 +254,31 @@ void __nvoc_init_KernelIoctrl(KernelIoctrl *pThis, RmHalspecOwner *pRmhalspecown __nvoc_init_funcTable_KernelIoctrl(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelIoctrl(KernelIoctrl **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelIoctrl(KernelIoctrl **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelIoctrl *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelIoctrl), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelIoctrl)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelIoctrl); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -288,16 +296,25 @@ NV_STATUS __nvoc_objCreate_KernelIoctrl(KernelIoctrl **ppThis, Dynamic *pParent, status = __nvoc_ctor_KernelIoctrl(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelIoctrl_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelIoctrl_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelIoctrl)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h index c929e1ae41..f96acda7f4 100644 --- a/src/nvidia/generated/g_kernel_ioctrl_nvoc.h +++ b/src/nvidia/generated/g_kernel_ioctrl_nvoc.h @@ -51,11 +51,20 @@ extern "C" { * any interfaces which do not manage the underlying Ioctrl hardware * can be managed by this object. */ + + // Link Conversion Macros +#define KIOCTRL_LINK_GLOBAL_TO_LOCAL_MASK(mask) (mask >> pKernelIoctrl->localGlobalLinkOffset) + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelIoctrl { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -90,6 +99,40 @@ struct KernelIoctrl { NvU8 PRIVATE_FIELD(numDevices); }; +struct KernelIoctrl_PRIVATE { + const struct NVOC_RTTI *__nvoc_rtti; + struct OBJENGSTATE __nvoc_base_OBJENGSTATE; + struct Object *__nvoc_pbase_Object; + struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; + struct KernelIoctrl *__nvoc_pbase_KernelIoctrl; + NV_STATUS (*__kioctrlConstructEngine__)(struct OBJGPU *, struct KernelIoctrl *, NvU32); + NvBool (*__kioctrlGetMinionEnableDefault__)(struct OBJGPU *, struct KernelIoctrl *); + NV_STATUS (*__kioctrlMinionConstruct__)(struct OBJGPU *, struct KernelIoctrl *); + NV_STATUS (*__kioctrlStateLoad__)(POBJGPU, struct KernelIoctrl *, NvU32); + NV_STATUS (*__kioctrlStateUnload__)(POBJGPU, struct KernelIoctrl *, NvU32); + NV_STATUS (*__kioctrlStateInitLocked__)(POBJGPU, struct KernelIoctrl *); + NV_STATUS (*__kioctrlStatePreLoad__)(POBJGPU, struct KernelIoctrl *, NvU32); + NV_STATUS (*__kioctrlStatePostUnload__)(POBJGPU, struct KernelIoctrl *, NvU32); + void (*__kioctrlStateDestroy__)(POBJGPU, struct KernelIoctrl *); + NV_STATUS (*__kioctrlStatePreUnload__)(POBJGPU, struct KernelIoctrl *, NvU32); + NV_STATUS (*__kioctrlStateInitUnlocked__)(POBJGPU, struct KernelIoctrl *); + void (*__kioctrlInitMissing__)(POBJGPU, struct KernelIoctrl *); + NV_STATUS (*__kioctrlStatePreInitLocked__)(POBJGPU, struct KernelIoctrl *); + NV_STATUS (*__kioctrlStatePreInitUnlocked__)(POBJGPU, struct KernelIoctrl *); + NV_STATUS (*__kioctrlStatePostLoad__)(POBJGPU, struct KernelIoctrl *, NvU32); + NvBool (*__kioctrlIsPresent__)(POBJGPU, struct KernelIoctrl *); + NvBool PDB_PROP_KIOCTRL_MINION_AVAILABLE; + NvBool PDB_PROP_KIOCTRL_MINION_FORCE_BOOT; + NvBool PDB_PROP_KIOCTRL_MINION_CACHE_SEEDS; + NvU32 PublicId; + NvU32 localDiscoveredLinks; + NvU32 localGlobalLinkOffset; + NvU32 ipVerIoctrl; + NvU32 ipVerMinion; + NvU32 ioctrlDiscoverySize; + NvU8 numDevices; +}; + #ifndef __NVOC_CLASS_KernelIoctrl_TYPEDEF__ #define __NVOC_CLASS_KernelIoctrl_TYPEDEF__ typedef struct KernelIoctrl KernelIoctrl; @@ -222,6 +265,21 @@ static inline NvBool kioctrlIsPresent_DISPATCH(POBJGPU pGpu, struct KernelIoctrl return pEngstate->__kioctrlIsPresent__(pGpu, pEngstate); } +static inline NvU32 kioctrlGetLocalDiscoveredLinks(struct OBJGPU *pGpu, struct KernelIoctrl *pKernelIoctrl) { + struct KernelIoctrl_PRIVATE *pKernelIoctrl_PRIVATE = (struct KernelIoctrl_PRIVATE *)pKernelIoctrl; + return pKernelIoctrl_PRIVATE->localDiscoveredLinks; +} + +static inline NvU32 kioctrlGetGlobalToLocalMask(struct OBJGPU *pGpu, struct KernelIoctrl *pKernelIoctrl, NvU32 mask) { + struct KernelIoctrl_PRIVATE *pKernelIoctrl_PRIVATE = (struct KernelIoctrl_PRIVATE *)pKernelIoctrl; + return (mask >> pKernelIoctrl_PRIVATE->localGlobalLinkOffset); +} + +static inline NvU32 kioctrlGetPublicId(struct OBJGPU *pGpu, struct KernelIoctrl *pKernelIoctrl) { + struct KernelIoctrl_PRIVATE *pKernelIoctrl_PRIVATE = (struct KernelIoctrl_PRIVATE *)pKernelIoctrl; + return pKernelIoctrl_PRIVATE->PublicId; +} + void kioctrlDestructEngine_IMPL(struct KernelIoctrl *arg0); #ifdef __nvoc_kernel_ioctrl_h_disabled @@ -235,9 +293,6 @@ static inline void kioctrlDestructEngine(struct KernelIoctrl *arg0) { #undef PRIVATE_FIELD -// Link Conversion Macros -#define KIOCTRL_LINK_GLOBAL_TO_LOCAL_MASK(mask) (mask >> pKernelIoctrl->localGlobalLinkOffset) - #endif // _KERNEL_IOCTRL_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.c b/src/nvidia/generated/g_kernel_mc_nvoc.c index fd663fc2be..ef747d01f3 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.c +++ b/src/nvidia/generated/g_kernel_mc_nvoc.c @@ -170,7 +170,11 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR pThis->__kmcStateLoad__ = &kmcStateLoad_IMPL; // Hal function -- kmcWritePmcEnableReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kmcWritePmcEnableReg__ = &kmcWritePmcEnableReg_GK104; } @@ -180,7 +184,11 @@ static void __nvoc_init_funcTable_KernelMc_1(KernelMc *pThis, RmHalspecOwner *pR } // Hal function -- kmcReadPmcEnableReg - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GH100; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { pThis->__kmcReadPmcEnableReg__ = &kmcReadPmcEnableReg_GK104; } @@ -231,23 +239,31 @@ void __nvoc_init_KernelMc(KernelMc *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelMc(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelMc(KernelMc **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelMc(KernelMc **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelMc *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMc), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelMc)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMc); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -265,16 +281,25 @@ NV_STATUS __nvoc_objCreate_KernelMc(KernelMc **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_KernelMc(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelMc_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelMc_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelMc)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_mc_nvoc.h b/src/nvidia/generated/g_kernel_mc_nvoc.h index 65e041526a..8defb4fb3e 100644 --- a/src/nvidia/generated/g_kernel_mc_nvoc.h +++ b/src/nvidia/generated/g_kernel_mc_nvoc.h @@ -51,11 +51,16 @@ typedef struct LATENCY_TIMER_CONTROL NvU32 LatencyTimerValue; // Requested value for PCI latency timer. } LATENCY_TIMER_CONTROL; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_MC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelMc { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -173,6 +178,8 @@ NV_STATUS kmcWritePmcEnableReg_GK104(struct OBJGPU *pGpu, struct KernelMc *pKern NV_STATUS kmcWritePmcEnableReg_GA100(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0, NvBool arg1, NvBool arg2); +NV_STATUS kmcWritePmcEnableReg_GH100(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0, NvBool arg1, NvBool arg2); + static inline NV_STATUS kmcWritePmcEnableReg_DISPATCH(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 arg0, NvBool arg1, NvBool arg2) { return pKernelMc->__kmcWritePmcEnableReg__(pGpu, pKernelMc, arg0, arg1, arg2); } @@ -181,6 +188,8 @@ NvU32 kmcReadPmcEnableReg_GK104(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvU32 kmcReadPmcEnableReg_GA100(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvBool arg0); +NvU32 kmcReadPmcEnableReg_GH100(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvBool arg0); + static inline NvU32 kmcReadPmcEnableReg_DISPATCH(struct OBJGPU *pGpu, struct KernelMc *pKernelMc, NvBool arg0) { return pKernelMc->__kmcReadPmcEnableReg__(pGpu, pKernelMc, arg0); } diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c index ec0e95cf9f..ff71fb9ef7 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.c +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.c @@ -180,6 +180,76 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm pThis->__kmigmgrStateUnload__ = &kmigmgrStateUnload_IMPL; + // Hal function -- kmigmgrLoadStaticInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrLoadStaticInfo__ = &kmigmgrLoadStaticInfo_VF; + } + else + { + pThis->__kmigmgrLoadStaticInfo__ = &kmigmgrLoadStaticInfo_KERNEL; + } + + // Hal function -- kmigmgrSetStaticInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrSetStaticInfo__ = &kmigmgrSetStaticInfo_VF; + } + else + { + pThis->__kmigmgrSetStaticInfo__ = &kmigmgrSetStaticInfo_46f6a7; + } + + // Hal function -- kmigmgrClearStaticInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrClearStaticInfo__ = &kmigmgrClearStaticInfo_VF; + } + else + { + pThis->__kmigmgrClearStaticInfo__ = &kmigmgrClearStaticInfo_b3696a; + } + + // Hal function -- kmigmgrSaveToPersistenceFromVgpuStaticInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrSaveToPersistenceFromVgpuStaticInfo__ = &kmigmgrSaveToPersistenceFromVgpuStaticInfo_VF; + } + else + { + pThis->__kmigmgrSaveToPersistenceFromVgpuStaticInfo__ = &kmigmgrSaveToPersistenceFromVgpuStaticInfo_46f6a7; + } + + // Hal function -- kmigmgrDeleteGPUInstanceRunlists + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrDeleteGPUInstanceRunlists__ = &kmigmgrDeleteGPUInstanceRunlists_56cd7a; + } + else + { + pThis->__kmigmgrDeleteGPUInstanceRunlists__ = &kmigmgrDeleteGPUInstanceRunlists_FWCLIENT; + } + + // Hal function -- kmigmgrCreateGPUInstanceRunlists + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrCreateGPUInstanceRunlists__ = &kmigmgrCreateGPUInstanceRunlists_56cd7a; + } + else + { + pThis->__kmigmgrCreateGPUInstanceRunlists__ = &kmigmgrCreateGPUInstanceRunlists_FWCLIENT; + } + + // Hal function -- kmigmgrRestoreFromPersistence + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrRestoreFromPersistence__ = &kmigmgrRestoreFromPersistence_VF; + } + else + { + pThis->__kmigmgrRestoreFromPersistence__ = &kmigmgrRestoreFromPersistence_PF; + } + // Hal function -- kmigmgrCreateGPUInstanceCheck if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { @@ -191,14 +261,21 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm } // Hal function -- kmigmgrIsDevinitMIGBitSet - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_GA100; + pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_VF; } - // default else { - pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_491d52; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ + { + pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_GA100; + } + // default + else + { + pThis->__kmigmgrIsDevinitMIGBitSet__ = &kmigmgrIsDevinitMIGBitSet_491d52; + } } // Hal function -- kmigmgrIsGPUInstanceCombinationValid @@ -231,6 +308,38 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm pThis->__kmigmgrIsGPUInstanceFlagValid__ = &kmigmgrIsGPUInstanceFlagValid_491d52; } + // Hal function -- kmigmgrGenerateComputeInstanceUuid + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrGenerateComputeInstanceUuid__ = &kmigmgrGenerateComputeInstanceUuid_VF; + } + // default + else + { + pThis->__kmigmgrGenerateComputeInstanceUuid__ = &kmigmgrGenerateComputeInstanceUuid_5baef9; + } + + // Hal function -- kmigmgrGenerateGPUInstanceUuid + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrGenerateGPUInstanceUuid__ = &kmigmgrGenerateGPUInstanceUuid_VF; + } + // default + else + { + pThis->__kmigmgrGenerateGPUInstanceUuid__ = &kmigmgrGenerateGPUInstanceUuid_5baef9; + } + + // Hal function -- kmigmgrCreateComputeInstances + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrCreateComputeInstances__ = &kmigmgrCreateComputeInstances_VF; + } + else + { + pThis->__kmigmgrCreateComputeInstances__ = &kmigmgrCreateComputeInstances_FWCLIENT; + } + // Hal function -- kmigmgrIsMemoryPartitioningRequested if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { @@ -252,13 +361,60 @@ static void __nvoc_init_funcTable_KernelMIGManager_1(KernelMIGManager *pThis, Rm } // Hal function -- kmigmgrMemSizeFlagToSwizzIdRange + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; + } + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_GA100; + } + else + { + pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; + } + } + + // Hal function -- kmigmgrSwizzIdToSpan if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ { - pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_GA100; + pThis->__kmigmgrSwizzIdToSpan__ = &kmigmgrSwizzIdToSpan_GA100; } else { - pThis->__kmigmgrMemSizeFlagToSwizzIdRange__ = &kmigmgrMemSizeFlagToSwizzIdRange_d64cd6; + pThis->__kmigmgrSwizzIdToSpan__ = &kmigmgrSwizzIdToSpan_d64cd6; + } + + // Hal function -- kmigmgrSetMIGState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrSetMIGState__ = &kmigmgrSetMIGState_VF; + } + else + { + pThis->__kmigmgrSetMIGState__ = &kmigmgrSetMIGState_FWCLIENT; + } + + // Hal function -- kmigmgrIsCTSAlignmentRequired + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrIsCTSAlignmentRequired__ = &kmigmgrIsCTSAlignmentRequired_VF; + } + else + { + pThis->__kmigmgrIsCTSAlignmentRequired__ = &kmigmgrIsCTSAlignmentRequired_PF; + } + + // Hal function -- kmigmgrRestoreFromBootConfig + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kmigmgrRestoreFromBootConfig__ = &kmigmgrRestoreFromBootConfig_56cd7a; + } + else + { + pThis->__kmigmgrRestoreFromBootConfig__ = &kmigmgrRestoreFromBootConfig_PF; } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMIGManager_engstateConstructEngine; @@ -303,23 +459,31 @@ void __nvoc_init_KernelMIGManager(KernelMIGManager *pThis, RmHalspecOwner *pRmha __nvoc_init_funcTable_KernelMIGManager(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelMIGManager *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelMIGManager), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelMIGManager)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelMIGManager); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -337,16 +501,25 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager **ppThis, Dynamic * status = __nvoc_ctor_KernelMIGManager(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelMIGManager_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelMIGManager_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelMIGManager)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h index a0be1efc3f..22c2a4c926 100644 --- a/src/nvidia/generated/g_kernel_mig_manager_nvoc.h +++ b/src/nvidia/generated/g_kernel_mig_manager_nvoc.h @@ -389,6 +389,11 @@ typedef struct KERNEL_MIG_GPU_INSTANCE * Mask tracking which compute spans are currently in-use */ NvU32 spanInUseMask; + + /*! + * GPU Instance UUID + */ + NvUuid uuid; } KERNEL_MIG_GPU_INSTANCE; /*! @@ -440,8 +445,8 @@ typedef struct KERNEL_MIG_MANAGER_STATIC_INFO /*! @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES */ NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS *pProfiles; - /*! Mask of partitionable engines which are present on this GPU. */ - NvU32 partitionableEngineMask[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]; + /*! Partitionable engines which are present on this GPU. */ + ENGTYPE_BIT_VECTOR partitionableEngines; /*! Per swizzId FB memory page ranges */ NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS *pSwizzIdFbMemPageRanges; @@ -457,11 +462,16 @@ typedef struct KERNEL_MIG_MANAGER_STATIC_INFO * KernelMIGManager provides kernel side services for managing MIG instances. * It also maintains state relating to GPU partitioning and related state. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelMIGManager { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -471,13 +481,27 @@ struct KernelMIGManager { NV_STATUS (*__kmigmgrConstructEngine__)(OBJGPU *, struct KernelMIGManager *, ENGDESCRIPTOR); NV_STATUS (*__kmigmgrStateInitLocked__)(OBJGPU *, struct KernelMIGManager *); NV_STATUS (*__kmigmgrStateUnload__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrLoadStaticInfo__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrSetStaticInfo__)(OBJGPU *, struct KernelMIGManager *); + void (*__kmigmgrClearStaticInfo__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrSaveToPersistenceFromVgpuStaticInfo__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrDeleteGPUInstanceRunlists__)(OBJGPU *, struct KernelMIGManager *, KERNEL_MIG_GPU_INSTANCE *); + NV_STATUS (*__kmigmgrCreateGPUInstanceRunlists__)(OBJGPU *, struct KernelMIGManager *, KERNEL_MIG_GPU_INSTANCE *); + NV_STATUS (*__kmigmgrRestoreFromPersistence__)(OBJGPU *, struct KernelMIGManager *); NV_STATUS (*__kmigmgrCreateGPUInstanceCheck__)(OBJGPU *, struct KernelMIGManager *, NvBool); NvBool (*__kmigmgrIsDevinitMIGBitSet__)(OBJGPU *, struct KernelMIGManager *); NvBool (*__kmigmgrIsGPUInstanceCombinationValid__)(OBJGPU *, struct KernelMIGManager *, NvU32); NvBool (*__kmigmgrIsGPUInstanceFlagValid__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrGenerateComputeInstanceUuid__)(OBJGPU *, struct KernelMIGManager *, NvU32, NvU32, NvUuid *); + NV_STATUS (*__kmigmgrGenerateGPUInstanceUuid__)(OBJGPU *, struct KernelMIGManager *, NvU32, NvUuid *); + NV_STATUS (*__kmigmgrCreateComputeInstances__)(OBJGPU *, struct KernelMIGManager *, KERNEL_MIG_GPU_INSTANCE *, NvBool, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS, NvU32 *, NvBool); NvBool (*__kmigmgrIsMemoryPartitioningRequested__)(OBJGPU *, struct KernelMIGManager *, NvU32); NvBool (*__kmigmgrIsMemoryPartitioningNeeded__)(OBJGPU *, struct KernelMIGManager *, NvU32); struct NV_RANGE (*__kmigmgrMemSizeFlagToSwizzIdRange__)(OBJGPU *, struct KernelMIGManager *, NvU32); + struct NV_RANGE (*__kmigmgrSwizzIdToSpan__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrSetMIGState__)(OBJGPU *, struct KernelMIGManager *, NvBool, NvBool, NvBool); + NvBool (*__kmigmgrIsCTSAlignmentRequired__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrRestoreFromBootConfig__)(OBJGPU *, struct KernelMIGManager *); NV_STATUS (*__kmigmgrStateLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NV_STATUS (*__kmigmgrStatePreLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NV_STATUS (*__kmigmgrStatePostUnload__)(POBJGPU, struct KernelMIGManager *, NvU32); @@ -501,6 +525,9 @@ struct KernelMIGManager { NvBool PRIVATE_FIELD(bMIGAutoOnlineEnabled); NvBool PRIVATE_FIELD(bBootConfigSupported); NvBool PRIVATE_FIELD(bAutoUpdateBootConfig); + NvBool PRIVATE_FIELD(bGlobalBootConfigUsed); + NvU64 PRIVATE_FIELD(validGlobalCTSIdMask); + NvU64 PRIVATE_FIELD(validGlobalGfxCTSIdMask); }; struct KernelMIGManager_PRIVATE { @@ -512,13 +539,27 @@ struct KernelMIGManager_PRIVATE { NV_STATUS (*__kmigmgrConstructEngine__)(OBJGPU *, struct KernelMIGManager *, ENGDESCRIPTOR); NV_STATUS (*__kmigmgrStateInitLocked__)(OBJGPU *, struct KernelMIGManager *); NV_STATUS (*__kmigmgrStateUnload__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrLoadStaticInfo__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrSetStaticInfo__)(OBJGPU *, struct KernelMIGManager *); + void (*__kmigmgrClearStaticInfo__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrSaveToPersistenceFromVgpuStaticInfo__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrDeleteGPUInstanceRunlists__)(OBJGPU *, struct KernelMIGManager *, KERNEL_MIG_GPU_INSTANCE *); + NV_STATUS (*__kmigmgrCreateGPUInstanceRunlists__)(OBJGPU *, struct KernelMIGManager *, KERNEL_MIG_GPU_INSTANCE *); + NV_STATUS (*__kmigmgrRestoreFromPersistence__)(OBJGPU *, struct KernelMIGManager *); NV_STATUS (*__kmigmgrCreateGPUInstanceCheck__)(OBJGPU *, struct KernelMIGManager *, NvBool); NvBool (*__kmigmgrIsDevinitMIGBitSet__)(OBJGPU *, struct KernelMIGManager *); NvBool (*__kmigmgrIsGPUInstanceCombinationValid__)(OBJGPU *, struct KernelMIGManager *, NvU32); NvBool (*__kmigmgrIsGPUInstanceFlagValid__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrGenerateComputeInstanceUuid__)(OBJGPU *, struct KernelMIGManager *, NvU32, NvU32, NvUuid *); + NV_STATUS (*__kmigmgrGenerateGPUInstanceUuid__)(OBJGPU *, struct KernelMIGManager *, NvU32, NvUuid *); + NV_STATUS (*__kmigmgrCreateComputeInstances__)(OBJGPU *, struct KernelMIGManager *, KERNEL_MIG_GPU_INSTANCE *, NvBool, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS, NvU32 *, NvBool); NvBool (*__kmigmgrIsMemoryPartitioningRequested__)(OBJGPU *, struct KernelMIGManager *, NvU32); NvBool (*__kmigmgrIsMemoryPartitioningNeeded__)(OBJGPU *, struct KernelMIGManager *, NvU32); struct NV_RANGE (*__kmigmgrMemSizeFlagToSwizzIdRange__)(OBJGPU *, struct KernelMIGManager *, NvU32); + struct NV_RANGE (*__kmigmgrSwizzIdToSpan__)(OBJGPU *, struct KernelMIGManager *, NvU32); + NV_STATUS (*__kmigmgrSetMIGState__)(OBJGPU *, struct KernelMIGManager *, NvBool, NvBool, NvBool); + NvBool (*__kmigmgrIsCTSAlignmentRequired__)(OBJGPU *, struct KernelMIGManager *); + NV_STATUS (*__kmigmgrRestoreFromBootConfig__)(OBJGPU *, struct KernelMIGManager *); NV_STATUS (*__kmigmgrStateLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NV_STATUS (*__kmigmgrStatePreLoad__)(POBJGPU, struct KernelMIGManager *, NvU32); NV_STATUS (*__kmigmgrStatePostUnload__)(POBJGPU, struct KernelMIGManager *, NvU32); @@ -542,6 +583,9 @@ struct KernelMIGManager_PRIVATE { NvBool bMIGAutoOnlineEnabled; NvBool bBootConfigSupported; NvBool bAutoUpdateBootConfig; + NvBool bGlobalBootConfigUsed; + NvU64 validGlobalCTSIdMask; + NvU64 validGlobalGfxCTSIdMask; }; #ifndef __NVOC_CLASS_KernelMIGManager_TYPEDEF__ @@ -577,6 +621,20 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager**, Dynamic*, NvU32) #define kmigmgrConstructEngine(arg0, arg1, arg2) kmigmgrConstructEngine_DISPATCH(arg0, arg1, arg2) #define kmigmgrStateInitLocked(arg0, arg1) kmigmgrStateInitLocked_DISPATCH(arg0, arg1) #define kmigmgrStateUnload(arg0, arg1, flags) kmigmgrStateUnload_DISPATCH(arg0, arg1, flags) +#define kmigmgrLoadStaticInfo(arg0, arg1) kmigmgrLoadStaticInfo_DISPATCH(arg0, arg1) +#define kmigmgrLoadStaticInfo_HAL(arg0, arg1) kmigmgrLoadStaticInfo_DISPATCH(arg0, arg1) +#define kmigmgrSetStaticInfo(arg0, arg1) kmigmgrSetStaticInfo_DISPATCH(arg0, arg1) +#define kmigmgrSetStaticInfo_HAL(arg0, arg1) kmigmgrSetStaticInfo_DISPATCH(arg0, arg1) +#define kmigmgrClearStaticInfo(arg0, arg1) kmigmgrClearStaticInfo_DISPATCH(arg0, arg1) +#define kmigmgrClearStaticInfo_HAL(arg0, arg1) kmigmgrClearStaticInfo_DISPATCH(arg0, arg1) +#define kmigmgrSaveToPersistenceFromVgpuStaticInfo(arg0, arg1) kmigmgrSaveToPersistenceFromVgpuStaticInfo_DISPATCH(arg0, arg1) +#define kmigmgrSaveToPersistenceFromVgpuStaticInfo_HAL(arg0, arg1) kmigmgrSaveToPersistenceFromVgpuStaticInfo_DISPATCH(arg0, arg1) +#define kmigmgrDeleteGPUInstanceRunlists(arg0, arg1, arg2) kmigmgrDeleteGPUInstanceRunlists_DISPATCH(arg0, arg1, arg2) +#define kmigmgrDeleteGPUInstanceRunlists_HAL(arg0, arg1, arg2) kmigmgrDeleteGPUInstanceRunlists_DISPATCH(arg0, arg1, arg2) +#define kmigmgrCreateGPUInstanceRunlists(arg0, arg1, arg2) kmigmgrCreateGPUInstanceRunlists_DISPATCH(arg0, arg1, arg2) +#define kmigmgrCreateGPUInstanceRunlists_HAL(arg0, arg1, arg2) kmigmgrCreateGPUInstanceRunlists_DISPATCH(arg0, arg1, arg2) +#define kmigmgrRestoreFromPersistence(arg0, arg1) kmigmgrRestoreFromPersistence_DISPATCH(arg0, arg1) +#define kmigmgrRestoreFromPersistence_HAL(arg0, arg1) kmigmgrRestoreFromPersistence_DISPATCH(arg0, arg1) #define kmigmgrCreateGPUInstanceCheck(arg0, arg1, bMemoryPartitioningNeeded) kmigmgrCreateGPUInstanceCheck_DISPATCH(arg0, arg1, bMemoryPartitioningNeeded) #define kmigmgrCreateGPUInstanceCheck_HAL(arg0, arg1, bMemoryPartitioningNeeded) kmigmgrCreateGPUInstanceCheck_DISPATCH(arg0, arg1, bMemoryPartitioningNeeded) #define kmigmgrIsDevinitMIGBitSet(arg0, arg1) kmigmgrIsDevinitMIGBitSet_DISPATCH(arg0, arg1) @@ -585,12 +643,26 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager**, Dynamic*, NvU32) #define kmigmgrIsGPUInstanceCombinationValid_HAL(arg0, arg1, gpuInstanceFlag) kmigmgrIsGPUInstanceCombinationValid_DISPATCH(arg0, arg1, gpuInstanceFlag) #define kmigmgrIsGPUInstanceFlagValid(arg0, arg1, gpuInstanceFlag) kmigmgrIsGPUInstanceFlagValid_DISPATCH(arg0, arg1, gpuInstanceFlag) #define kmigmgrIsGPUInstanceFlagValid_HAL(arg0, arg1, gpuInstanceFlag) kmigmgrIsGPUInstanceFlagValid_DISPATCH(arg0, arg1, gpuInstanceFlag) +#define kmigmgrGenerateComputeInstanceUuid(arg0, arg1, swizzId, globalGrIdx, arg2) kmigmgrGenerateComputeInstanceUuid_DISPATCH(arg0, arg1, swizzId, globalGrIdx, arg2) +#define kmigmgrGenerateComputeInstanceUuid_HAL(arg0, arg1, swizzId, globalGrIdx, arg2) kmigmgrGenerateComputeInstanceUuid_DISPATCH(arg0, arg1, swizzId, globalGrIdx, arg2) +#define kmigmgrGenerateGPUInstanceUuid(arg0, arg1, swizzId, arg2) kmigmgrGenerateGPUInstanceUuid_DISPATCH(arg0, arg1, swizzId, arg2) +#define kmigmgrGenerateGPUInstanceUuid_HAL(arg0, arg1, swizzId, arg2) kmigmgrGenerateGPUInstanceUuid_DISPATCH(arg0, arg1, swizzId, arg2) +#define kmigmgrCreateComputeInstances(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap) kmigmgrCreateComputeInstances_DISPATCH(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap) +#define kmigmgrCreateComputeInstances_HAL(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap) kmigmgrCreateComputeInstances_DISPATCH(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap) #define kmigmgrIsMemoryPartitioningRequested(arg0, arg1, partitionFlags) kmigmgrIsMemoryPartitioningRequested_DISPATCH(arg0, arg1, partitionFlags) #define kmigmgrIsMemoryPartitioningRequested_HAL(arg0, arg1, partitionFlags) kmigmgrIsMemoryPartitioningRequested_DISPATCH(arg0, arg1, partitionFlags) #define kmigmgrIsMemoryPartitioningNeeded(arg0, arg1, swizzId) kmigmgrIsMemoryPartitioningNeeded_DISPATCH(arg0, arg1, swizzId) #define kmigmgrIsMemoryPartitioningNeeded_HAL(arg0, arg1, swizzId) kmigmgrIsMemoryPartitioningNeeded_DISPATCH(arg0, arg1, swizzId) #define kmigmgrMemSizeFlagToSwizzIdRange(arg0, arg1, memSizeFlag) kmigmgrMemSizeFlagToSwizzIdRange_DISPATCH(arg0, arg1, memSizeFlag) #define kmigmgrMemSizeFlagToSwizzIdRange_HAL(arg0, arg1, memSizeFlag) kmigmgrMemSizeFlagToSwizzIdRange_DISPATCH(arg0, arg1, memSizeFlag) +#define kmigmgrSwizzIdToSpan(arg0, arg1, swizzId) kmigmgrSwizzIdToSpan_DISPATCH(arg0, arg1, swizzId) +#define kmigmgrSwizzIdToSpan_HAL(arg0, arg1, swizzId) kmigmgrSwizzIdToSpan_DISPATCH(arg0, arg1, swizzId) +#define kmigmgrSetMIGState(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) kmigmgrSetMIGState_DISPATCH(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) +#define kmigmgrSetMIGState_HAL(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) kmigmgrSetMIGState_DISPATCH(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) +#define kmigmgrIsCTSAlignmentRequired(arg0, arg1) kmigmgrIsCTSAlignmentRequired_DISPATCH(arg0, arg1) +#define kmigmgrIsCTSAlignmentRequired_HAL(arg0, arg1) kmigmgrIsCTSAlignmentRequired_DISPATCH(arg0, arg1) +#define kmigmgrRestoreFromBootConfig(pGpu, pKernelMIGManager) kmigmgrRestoreFromBootConfig_DISPATCH(pGpu, pKernelMIGManager) +#define kmigmgrRestoreFromBootConfig_HAL(pGpu, pKernelMIGManager) kmigmgrRestoreFromBootConfig_DISPATCH(pGpu, pKernelMIGManager) #define kmigmgrStateLoad(pGpu, pEngstate, arg0) kmigmgrStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmigmgrStatePreLoad(pGpu, pEngstate, arg0) kmigmgrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmigmgrStatePostUnload(pGpu, pEngstate, arg0) kmigmgrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -602,224 +674,115 @@ NV_STATUS __nvoc_objCreate_KernelMIGManager(KernelMIGManager**, Dynamic*, NvU32) #define kmigmgrStatePreInitUnlocked(pGpu, pEngstate) kmigmgrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate) #define kmigmgrStatePostLoad(pGpu, pEngstate, arg0) kmigmgrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kmigmgrIsPresent(pGpu, pEngstate) kmigmgrIsPresent_DISPATCH(pGpu, pEngstate) -NV_STATUS kmigmgrLoadStaticInfo_KERNEL(OBJGPU *arg0, struct KernelMIGManager *arg1); +void kmigmgrDetectReducedConfig_KERNEL(OBJGPU *arg0, struct KernelMIGManager *arg1); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrLoadStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { +static inline void kmigmgrDetectReducedConfig(OBJGPU *arg0, struct KernelMIGManager *arg1) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrLoadStaticInfo(arg0, arg1) kmigmgrLoadStaticInfo_KERNEL(arg0, arg1) +#define kmigmgrDetectReducedConfig(arg0, arg1) kmigmgrDetectReducedConfig_KERNEL(arg0, arg1) #endif //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrLoadStaticInfo_HAL(arg0, arg1) kmigmgrLoadStaticInfo(arg0, arg1) +#define kmigmgrDetectReducedConfig_HAL(arg0, arg1) kmigmgrDetectReducedConfig(arg0, arg1) -static inline NV_STATUS kmigmgrSetStaticInfo_46f6a7(OBJGPU *arg0, struct KernelMIGManager *arg1) { - return NV_ERR_NOT_SUPPORTED; -} +NV_STATUS kmigmgrGetComputeProfileFromGpcCount_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrSetStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { +static inline NV_STATUS kmigmgrGetComputeProfileFromGpcCount(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrSetStaticInfo(arg0, arg1) kmigmgrSetStaticInfo_46f6a7(arg0, arg1) +#define kmigmgrGetComputeProfileFromGpcCount(arg0, arg1, gpcCount, pProfile) kmigmgrGetComputeProfileFromGpcCount_IMPL(arg0, arg1, gpcCount, pProfile) #endif //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrSetStaticInfo_HAL(arg0, arg1) kmigmgrSetStaticInfo(arg0, arg1) - -static inline void kmigmgrClearStaticInfo_b3696a(OBJGPU *arg0, struct KernelMIGManager *arg1) { - return; -} +#define kmigmgrGetComputeProfileFromGpcCount_HAL(arg0, arg1, gpcCount, pProfile) kmigmgrGetComputeProfileFromGpcCount(arg0, arg1, gpcCount, pProfile) +NV_STATUS kmigmgrConstructEngine_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, ENGDESCRIPTOR arg2); -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline void kmigmgrClearStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); +static inline NV_STATUS kmigmgrConstructEngine_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, ENGDESCRIPTOR arg2) { + return arg1->__kmigmgrConstructEngine__(arg0, arg1, arg2); } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrClearStaticInfo(arg0, arg1) kmigmgrClearStaticInfo_b3696a(arg0, arg1) -#endif //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrClearStaticInfo_HAL(arg0, arg1) kmigmgrClearStaticInfo(arg0, arg1) +NV_STATUS kmigmgrStateInitLocked_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); -static inline NV_STATUS kmigmgrSaveToPersistenceFromVgpuStaticInfo_46f6a7(OBJGPU *arg0, struct KernelMIGManager *arg1) { - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kmigmgrStateInitLocked_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1) { + return arg1->__kmigmgrStateInitLocked__(arg0, arg1); } +NV_STATUS kmigmgrStateUnload_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 flags); -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrSaveToPersistenceFromVgpuStaticInfo(OBJGPU *arg0, struct KernelMIGManager *arg1) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kmigmgrStateUnload_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 flags) { + return arg1->__kmigmgrStateUnload__(arg0, arg1, flags); } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrSaveToPersistenceFromVgpuStaticInfo(arg0, arg1) kmigmgrSaveToPersistenceFromVgpuStaticInfo_46f6a7(arg0, arg1) -#endif //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrSaveToPersistenceFromVgpuStaticInfo_HAL(arg0, arg1) kmigmgrSaveToPersistenceFromVgpuStaticInfo(arg0, arg1) - -NV_STATUS kmigmgrDeleteGPUInstanceRunlists_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); +NV_STATUS kmigmgrLoadStaticInfo_VF(OBJGPU *arg0, struct KernelMIGManager *arg1); +NV_STATUS kmigmgrLoadStaticInfo_KERNEL(OBJGPU *arg0, struct KernelMIGManager *arg1); -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrDeleteGPUInstanceRunlists(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kmigmgrLoadStaticInfo_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1) { + return arg1->__kmigmgrLoadStaticInfo__(arg0, arg1); } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrDeleteGPUInstanceRunlists(arg0, arg1, arg2) kmigmgrDeleteGPUInstanceRunlists_FWCLIENT(arg0, arg1, arg2) -#endif //__nvoc_kernel_mig_manager_h_disabled - -#define kmigmgrDeleteGPUInstanceRunlists_HAL(arg0, arg1, arg2) kmigmgrDeleteGPUInstanceRunlists(arg0, arg1, arg2) - -NV_STATUS kmigmgrCreateGPUInstanceRunlists_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); +NV_STATUS kmigmgrSetStaticInfo_VF(OBJGPU *arg0, struct KernelMIGManager *arg1); -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrCreateGPUInstanceRunlists(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrCreateGPUInstanceRunlists(arg0, arg1, arg2) kmigmgrCreateGPUInstanceRunlists_FWCLIENT(arg0, arg1, arg2) -#endif //__nvoc_kernel_mig_manager_h_disabled - -#define kmigmgrCreateGPUInstanceRunlists_HAL(arg0, arg1, arg2) kmigmgrCreateGPUInstanceRunlists(arg0, arg1, arg2) - -NV_STATUS kmigmgrRestoreFromPersistence_PF(OBJGPU *arg0, struct KernelMIGManager *arg1); - - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrRestoreFromPersistence(OBJGPU *arg0, struct KernelMIGManager *arg1) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); +static inline NV_STATUS kmigmgrSetStaticInfo_46f6a7(OBJGPU *arg0, struct KernelMIGManager *arg1) { return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrRestoreFromPersistence(arg0, arg1) kmigmgrRestoreFromPersistence_PF(arg0, arg1) -#endif //__nvoc_kernel_mig_manager_h_disabled - -#define kmigmgrRestoreFromPersistence_HAL(arg0, arg1) kmigmgrRestoreFromPersistence(arg0, arg1) - -void kmigmgrDetectReducedConfig_KERNEL(OBJGPU *arg0, struct KernelMIGManager *arg1); - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline void kmigmgrDetectReducedConfig(OBJGPU *arg0, struct KernelMIGManager *arg1) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); +static inline NV_STATUS kmigmgrSetStaticInfo_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1) { + return arg1->__kmigmgrSetStaticInfo__(arg0, arg1); } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrDetectReducedConfig(arg0, arg1) kmigmgrDetectReducedConfig_KERNEL(arg0, arg1) -#endif //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrDetectReducedConfig_HAL(arg0, arg1) kmigmgrDetectReducedConfig(arg0, arg1) +void kmigmgrClearStaticInfo_VF(OBJGPU *arg0, struct KernelMIGManager *arg1); -static inline NV_STATUS kmigmgrGenerateComputeInstanceUuid_5baef9(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU32 globalGrIdx, NvUuid *pUuid) { - NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +static inline void kmigmgrClearStaticInfo_b3696a(OBJGPU *arg0, struct KernelMIGManager *arg1) { + return; } - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGenerateComputeInstanceUuid(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU32 globalGrIdx, NvUuid *pUuid) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline void kmigmgrClearStaticInfo_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1) { + arg1->__kmigmgrClearStaticInfo__(arg0, arg1); } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGenerateComputeInstanceUuid(arg0, arg1, swizzId, globalGrIdx, pUuid) kmigmgrGenerateComputeInstanceUuid_5baef9(arg0, arg1, swizzId, globalGrIdx, pUuid) -#endif //__nvoc_kernel_mig_manager_h_disabled - -#define kmigmgrGenerateComputeInstanceUuid_HAL(arg0, arg1, swizzId, globalGrIdx, pUuid) kmigmgrGenerateComputeInstanceUuid(arg0, arg1, swizzId, globalGrIdx, pUuid) - -NV_STATUS kmigmgrCreateComputeInstances_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvBool bQuery, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS arg3, NvU32 *pCIIds, NvBool bCreateCap); +NV_STATUS kmigmgrSaveToPersistenceFromVgpuStaticInfo_VF(OBJGPU *arg0, struct KernelMIGManager *arg1); -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrCreateComputeInstances(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvBool bQuery, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS arg3, NvU32 *pCIIds, NvBool bCreateCap) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); +static inline NV_STATUS kmigmgrSaveToPersistenceFromVgpuStaticInfo_46f6a7(OBJGPU *arg0, struct KernelMIGManager *arg1) { return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrCreateComputeInstances(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap) kmigmgrCreateComputeInstances_FWCLIENT(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap) -#endif //__nvoc_kernel_mig_manager_h_disabled - -#define kmigmgrCreateComputeInstances_HAL(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap) kmigmgrCreateComputeInstances(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap) -NV_STATUS kmigmgrSetMIGState_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bMemoryPartitioningNeeded, NvBool bEnable, NvBool bUnload); - - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrSetMIGState(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bMemoryPartitioningNeeded, NvBool bEnable, NvBool bUnload) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kmigmgrSaveToPersistenceFromVgpuStaticInfo_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1) { + return arg1->__kmigmgrSaveToPersistenceFromVgpuStaticInfo__(arg0, arg1); } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrSetMIGState(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) kmigmgrSetMIGState_FWCLIENT(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) -#endif //__nvoc_kernel_mig_manager_h_disabled - -#define kmigmgrSetMIGState_HAL(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) kmigmgrSetMIGState(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload) - -NV_STATUS kmigmgrGetComputeProfileFromGpcCount_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrGetComputeProfileFromGpcCount(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 gpcCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kmigmgrDeleteGPUInstanceRunlists_56cd7a(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { + return NV_OK; } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrGetComputeProfileFromGpcCount(arg0, arg1, gpcCount, pProfile) kmigmgrGetComputeProfileFromGpcCount_IMPL(arg0, arg1, gpcCount, pProfile) -#endif //__nvoc_kernel_mig_manager_h_disabled - -#define kmigmgrGetComputeProfileFromGpcCount_HAL(arg0, arg1, gpcCount, pProfile) kmigmgrGetComputeProfileFromGpcCount(arg0, arg1, gpcCount, pProfile) - -NvBool kmigmgrIsCTSAlignmentRequired_PF(OBJGPU *arg0, struct KernelMIGManager *arg1); +NV_STATUS kmigmgrDeleteGPUInstanceRunlists_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NvBool kmigmgrIsCTSAlignmentRequired(OBJGPU *arg0, struct KernelMIGManager *arg1) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_FALSE; +static inline NV_STATUS kmigmgrDeleteGPUInstanceRunlists_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { + return arg1->__kmigmgrDeleteGPUInstanceRunlists__(arg0, arg1, arg2); } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrIsCTSAlignmentRequired(arg0, arg1) kmigmgrIsCTSAlignmentRequired_PF(arg0, arg1) -#endif //__nvoc_kernel_mig_manager_h_disabled - -#define kmigmgrIsCTSAlignmentRequired_HAL(arg0, arg1) kmigmgrIsCTSAlignmentRequired(arg0, arg1) -NV_STATUS kmigmgrRestoreFromBootConfig_PF(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager); - - -#ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrRestoreFromBootConfig(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { - NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS kmigmgrCreateGPUInstanceRunlists_56cd7a(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { + return NV_OK; } -#else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrRestoreFromBootConfig(pGpu, pKernelMIGManager) kmigmgrRestoreFromBootConfig_PF(pGpu, pKernelMIGManager) -#endif //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrRestoreFromBootConfig_HAL(pGpu, pKernelMIGManager) kmigmgrRestoreFromBootConfig(pGpu, pKernelMIGManager) - -NV_STATUS kmigmgrConstructEngine_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, ENGDESCRIPTOR arg2); +NV_STATUS kmigmgrCreateGPUInstanceRunlists_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2); -static inline NV_STATUS kmigmgrConstructEngine_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, ENGDESCRIPTOR arg2) { - return arg1->__kmigmgrConstructEngine__(arg0, arg1, arg2); +static inline NV_STATUS kmigmgrCreateGPUInstanceRunlists_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2) { + return arg1->__kmigmgrCreateGPUInstanceRunlists__(arg0, arg1, arg2); } -NV_STATUS kmigmgrStateInitLocked_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1); +NV_STATUS kmigmgrRestoreFromPersistence_VF(OBJGPU *arg0, struct KernelMIGManager *arg1); -static inline NV_STATUS kmigmgrStateInitLocked_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1) { - return arg1->__kmigmgrStateInitLocked__(arg0, arg1); -} - -NV_STATUS kmigmgrStateUnload_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 flags); +NV_STATUS kmigmgrRestoreFromPersistence_PF(OBJGPU *arg0, struct KernelMIGManager *arg1); -static inline NV_STATUS kmigmgrStateUnload_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 flags) { - return arg1->__kmigmgrStateUnload__(arg0, arg1, flags); +static inline NV_STATUS kmigmgrRestoreFromPersistence_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1) { + return arg1->__kmigmgrRestoreFromPersistence__(arg0, arg1); } NV_STATUS kmigmgrCreateGPUInstanceCheck_GA100(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bMemoryPartitioningNeeded); @@ -832,6 +795,8 @@ static inline NV_STATUS kmigmgrCreateGPUInstanceCheck_DISPATCH(OBJGPU *arg0, str return arg1->__kmigmgrCreateGPUInstanceCheck__(arg0, arg1, bMemoryPartitioningNeeded); } +NvBool kmigmgrIsDevinitMIGBitSet_VF(OBJGPU *arg0, struct KernelMIGManager *arg1); + NvBool kmigmgrIsDevinitMIGBitSet_GA100(OBJGPU *arg0, struct KernelMIGManager *arg1); static inline NvBool kmigmgrIsDevinitMIGBitSet_491d52(OBJGPU *arg0, struct KernelMIGManager *arg1) { @@ -866,6 +831,34 @@ static inline NvBool kmigmgrIsGPUInstanceFlagValid_DISPATCH(OBJGPU *arg0, struct return arg1->__kmigmgrIsGPUInstanceFlagValid__(arg0, arg1, gpuInstanceFlag); } +NV_STATUS kmigmgrGenerateComputeInstanceUuid_VF(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU32 globalGrIdx, NvUuid *arg2); + +static inline NV_STATUS kmigmgrGenerateComputeInstanceUuid_5baef9(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU32 globalGrIdx, NvUuid *arg2) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kmigmgrGenerateComputeInstanceUuid_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU32 globalGrIdx, NvUuid *arg2) { + return arg1->__kmigmgrGenerateComputeInstanceUuid__(arg0, arg1, swizzId, globalGrIdx, arg2); +} + +NV_STATUS kmigmgrGenerateGPUInstanceUuid_VF(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvUuid *arg2); + +static inline NV_STATUS kmigmgrGenerateGPUInstanceUuid_5baef9(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvUuid *arg2) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kmigmgrGenerateGPUInstanceUuid_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvUuid *arg2) { + return arg1->__kmigmgrGenerateGPUInstanceUuid__(arg0, arg1, swizzId, arg2); +} + +NV_STATUS kmigmgrCreateComputeInstances_VF(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvBool bQuery, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS arg3, NvU32 *pCIIds, NvBool bCreateCap); + +NV_STATUS kmigmgrCreateComputeInstances_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvBool bQuery, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS arg3, NvU32 *pCIIds, NvBool bCreateCap); + +static inline NV_STATUS kmigmgrCreateComputeInstances_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvBool bQuery, KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS arg3, NvU32 *pCIIds, NvBool bCreateCap) { + return arg1->__kmigmgrCreateComputeInstances__(arg0, arg1, arg2, bQuery, arg3, pCIIds, bCreateCap); +} + NvBool kmigmgrIsMemoryPartitioningRequested_GA100(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 partitionFlags); static inline NvBool kmigmgrIsMemoryPartitioningRequested_491d52(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 partitionFlags) { @@ -896,6 +889,42 @@ static inline struct NV_RANGE kmigmgrMemSizeFlagToSwizzIdRange_DISPATCH(OBJGPU * return arg1->__kmigmgrMemSizeFlagToSwizzIdRange__(arg0, arg1, memSizeFlag); } +struct NV_RANGE kmigmgrSwizzIdToSpan_GA100(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId); + +static inline struct NV_RANGE kmigmgrSwizzIdToSpan_d64cd6(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId) { + return NV_RANGE_EMPTY; +} + +static inline struct NV_RANGE kmigmgrSwizzIdToSpan_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId) { + return arg1->__kmigmgrSwizzIdToSpan__(arg0, arg1, swizzId); +} + +NV_STATUS kmigmgrSetMIGState_VF(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bMemoryPartitioningNeeded, NvBool bEnable, NvBool bUnload); + +NV_STATUS kmigmgrSetMIGState_FWCLIENT(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bMemoryPartitioningNeeded, NvBool bEnable, NvBool bUnload); + +static inline NV_STATUS kmigmgrSetMIGState_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1, NvBool bMemoryPartitioningNeeded, NvBool bEnable, NvBool bUnload) { + return arg1->__kmigmgrSetMIGState__(arg0, arg1, bMemoryPartitioningNeeded, bEnable, bUnload); +} + +NvBool kmigmgrIsCTSAlignmentRequired_VF(OBJGPU *arg0, struct KernelMIGManager *arg1); + +NvBool kmigmgrIsCTSAlignmentRequired_PF(OBJGPU *arg0, struct KernelMIGManager *arg1); + +static inline NvBool kmigmgrIsCTSAlignmentRequired_DISPATCH(OBJGPU *arg0, struct KernelMIGManager *arg1) { + return arg1->__kmigmgrIsCTSAlignmentRequired__(arg0, arg1); +} + +NV_STATUS kmigmgrRestoreFromBootConfig_PF(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager); + +static inline NV_STATUS kmigmgrRestoreFromBootConfig_56cd7a(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { + return NV_OK; +} + +static inline NV_STATUS kmigmgrRestoreFromBootConfig_DISPATCH(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { + return pKernelMIGManager->__kmigmgrRestoreFromBootConfig__(pGpu, pKernelMIGManager); +} + static inline NV_STATUS kmigmgrStateLoad_DISPATCH(POBJGPU pGpu, struct KernelMIGManager *pEngstate, NvU32 arg0) { return pEngstate->__kmigmgrStateLoad__(pGpu, pEngstate, arg0); } @@ -968,6 +997,26 @@ static inline void kmigmgrSetIsA100ReducedConfig(OBJGPU *pGpu, struct KernelMIGM pKernelMIGManager_PRIVATE->bIsA100ReducedConfig = bA100ReducedConfig; } +static inline NvU64 kmigmgrGetValidGlobalCTSIdMask(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + return pKernelMIGManager_PRIVATE->validGlobalCTSIdMask; +} + +static inline void kmigmgrSetValidGlobalCTSIdMask(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, NvU64 validGlobalCTSIdMask) { + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + pKernelMIGManager_PRIVATE->validGlobalCTSIdMask = validGlobalCTSIdMask; +} + +static inline NvU64 kmigmgrGetValidGlobalGfxCTSIdMask(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager) { + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + return pKernelMIGManager_PRIVATE->validGlobalGfxCTSIdMask; +} + +static inline void kmigmgrSetValidGlobalGfxCTSIdMask(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, NvU64 validGlobalGfxCTSIdMask) { + struct KernelMIGManager_PRIVATE *pKernelMIGManager_PRIVATE = (struct KernelMIGManager_PRIVATE *)pKernelMIGManager; + pKernelMIGManager_PRIVATE->validGlobalGfxCTSIdMask = validGlobalGfxCTSIdMask; +} + NV_STATUS kmigmgrIncRefCount_IMPL(struct RsShared *arg0); #define kmigmgrIncRefCount(arg0) kmigmgrIncRefCount_IMPL(arg0) @@ -1249,15 +1298,26 @@ static inline NvBool kmigmgrIsEngineInInstance(OBJGPU *arg0, struct KernelMIGMan #define kmigmgrIsEngineInInstance(arg0, arg1, globalRmEngType, arg2) kmigmgrIsEngineInInstance_IMPL(arg0, arg1, globalRmEngType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrCreateGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pSwizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, NvBool bValid, NvBool bCreateCap); +NvBool kmigmgrIsLocalEngineInInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE localRmEngType, struct MIG_INSTANCE_REF arg2); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrCreateGPUInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pSwizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, NvBool bValid, NvBool bCreateCap) { +static inline NvBool kmigmgrIsLocalEngineInInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, RM_ENGINE_TYPE localRmEngType, struct MIG_INSTANCE_REF arg2) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrIsLocalEngineInInstance(arg0, arg1, localRmEngType, arg2) kmigmgrIsLocalEngineInInstance_IMPL(arg0, arg1, localRmEngType, arg2) +#endif //__nvoc_kernel_mig_manager_h_disabled + +NV_STATUS kmigmgrCreateGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU8 *pUuid, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, NvBool bValid, NvBool bCreateCap); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrCreateGPUInstance(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU8 *pUuid, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2, NvBool bValid, NvBool bCreateCap) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrCreateGPUInstance(arg0, arg1, pSwizzId, arg2, bValid, bCreateCap) kmigmgrCreateGPUInstance_IMPL(arg0, arg1, pSwizzId, arg2, bValid, bCreateCap) +#define kmigmgrCreateGPUInstance(arg0, arg1, swizzId, pUuid, arg2, bValid, bCreateCap) kmigmgrCreateGPUInstance_IMPL(arg0, arg1, swizzId, pUuid, arg2, bValid, bCreateCap) #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrInvalidateGPUInstance_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvBool bUnload); @@ -1493,15 +1553,15 @@ static inline void kmigmgrPrintGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGMan #define kmigmgrPrintGPUInstanceInfo(arg0, arg1, arg2) kmigmgrPrintGPUInstanceInfo_IMPL(arg0, arg1, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled -NV_STATUS kmigmgrSetGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2); +NV_STATUS kmigmgrSetGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU8 *pUuid, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2); #ifdef __nvoc_kernel_mig_manager_h_disabled -static inline NV_STATUS kmigmgrSetGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2) { +static inline NV_STATUS kmigmgrSetGPUInstanceInfo(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, NvU8 *pUuid, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS arg2) { NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_kernel_mig_manager_h_disabled -#define kmigmgrSetGPUInstanceInfo(arg0, arg1, swizzId, arg2) kmigmgrSetGPUInstanceInfo_IMPL(arg0, arg1, swizzId, arg2) +#define kmigmgrSetGPUInstanceInfo(arg0, arg1, swizzId, pUuid, arg2) kmigmgrSetGPUInstanceInfo_IMPL(arg0, arg1, swizzId, pUuid, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled NV_STATUS kmigmgrGetGPUInstanceInfo_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 swizzId, KERNEL_MIG_GPU_INSTANCE **arg2); @@ -1603,6 +1663,17 @@ static inline NV_STATUS kmigmgrGetMIGReferenceFromEngineType(OBJGPU *arg0, struc #define kmigmgrGetMIGReferenceFromEngineType(arg0, arg1, rmEngineType, arg2) kmigmgrGetMIGReferenceFromEngineType_IMPL(arg0, arg1, rmEngineType, arg2) #endif //__nvoc_kernel_mig_manager_h_disabled +NV_STATUS kmigmgrGetSmallestGpuInstanceSize_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pComputeSizeFlag); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetSmallestGpuInstanceSize(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pComputeSizeFlag) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetSmallestGpuInstanceSize(arg0, arg1, pComputeSizeFlag) kmigmgrGetSmallestGpuInstanceSize_IMPL(arg0, arg1, pComputeSizeFlag) +#endif //__nvoc_kernel_mig_manager_h_disabled + NV_STATUS kmigmgrGetGPUInstanceScrubberCe_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, Device *pDevice, NvU32 *ceInst); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1736,6 +1807,17 @@ static inline NV_STATUS kmigmgrGetComputeProfileFromSize(OBJGPU *arg0, struct Ke #define kmigmgrGetComputeProfileFromSize(arg0, arg1, computeSize, pProfile) kmigmgrGetComputeProfileFromSize_IMPL(arg0, arg1, computeSize, pProfile) #endif //__nvoc_kernel_mig_manager_h_disabled +NV_STATUS kmigmgrGetComputeProfileForRequest_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvU32 smCountRequest, NvU32 gpcCountRequest, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NV_STATUS kmigmgrGetComputeProfileForRequest(OBJGPU *arg0, struct KernelMIGManager *arg1, KERNEL_MIG_GPU_INSTANCE *arg2, NvU32 smCountRequest, NvU32 gpcCountRequest, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrGetComputeProfileForRequest(arg0, arg1, arg2, smCountRequest, gpcCountRequest, pProfile) kmigmgrGetComputeProfileForRequest_IMPL(arg0, arg1, arg2, smCountRequest, gpcCountRequest, pProfile) +#endif //__nvoc_kernel_mig_manager_h_disabled + NV_STATUS kmigmgrGetComputeProfileFromSmCount_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 smCount, NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1772,6 +1854,19 @@ static inline NV_STATUS kmigmgrGetInvalidCTSIdMask(OBJGPU *arg0, struct KernelMI struct NV_RANGE kmigmgrComputeProfileSizeToCTSIdRange_IMPL(NvU32 computeSize); #define kmigmgrComputeProfileSizeToCTSIdRange(computeSize) kmigmgrComputeProfileSizeToCTSIdRange_IMPL(computeSize) +struct NV_RANGE kmigmgrCtsIdToSpan_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline struct NV_RANGE kmigmgrCtsIdToSpan(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 ctsId) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + struct NV_RANGE ret; + portMemSet(&ret, 0, sizeof(struct NV_RANGE)); + return ret; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrCtsIdToSpan(arg0, arg1, ctsId) kmigmgrCtsIdToSpan_IMPL(arg0, arg1, ctsId) +#endif //__nvoc_kernel_mig_manager_h_disabled + NV_STATUS kmigmgrGetFreeCTSId_IMPL(OBJGPU *arg0, struct KernelMIGManager *arg1, NvU32 *pCtsId, NvU64 globalValidCtsMask, NvU64 globalValidGfxCtsMask, NvU64 ctsIdsInUseMask, NvU32 profileSize, NvBool bRestrictWithGfx, NvBool bGfxRequested); #ifdef __nvoc_kernel_mig_manager_h_disabled @@ -1855,6 +1950,17 @@ static inline NV_STATUS kmigmgrUpdateCiConfigForVgpu(OBJGPU *pGpu, struct Kernel #define kmigmgrUpdateCiConfigForVgpu(pGpu, pKernelMIGManager, execPartCount, pExecPartId, gfid, bDelete) kmigmgrUpdateCiConfigForVgpu_IMPL(pGpu, pKernelMIGManager, execPartCount, pExecPartId, gfid, bDelete) #endif //__nvoc_kernel_mig_manager_h_disabled +NvBool kmigmgrIsPartitionVeidAllocationContiguous_IMPL(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, KERNEL_MIG_GPU_INSTANCE *arg0); + +#ifdef __nvoc_kernel_mig_manager_h_disabled +static inline NvBool kmigmgrIsPartitionVeidAllocationContiguous(OBJGPU *pGpu, struct KernelMIGManager *pKernelMIGManager, KERNEL_MIG_GPU_INSTANCE *arg0) { + NV_ASSERT_FAILED_PRECOMP("KernelMIGManager was disabled!"); + return NV_FALSE; +} +#else //__nvoc_kernel_mig_manager_h_disabled +#define kmigmgrIsPartitionVeidAllocationContiguous(pGpu, pKernelMIGManager, arg0) kmigmgrIsPartitionVeidAllocationContiguous_IMPL(pGpu, pKernelMIGManager, arg0) +#endif //__nvoc_kernel_mig_manager_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c index 009a98b9d0..c561b1c998 100644 --- a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.c @@ -172,10 +172,6 @@ static void __nvoc_thunk_RmResource_nvdecctxControl_Epilogue(struct NvdecContext rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_nvdecctxControlLookup(struct NvdecContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_ChannelDescendant_nvdecctxGetSwMethods(struct NvdecContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_NvdecContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_nvdecctxCanCopy(struct NvdecContext *pReso return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_nvdecctxIsPartialUnmapSupported(struct NvdecContext *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_nvdecctxPreDestruct(struct NvdecContext *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvdecContext_RsResource.offset)); } @@ -323,8 +323,6 @@ static void __nvoc_init_funcTable_NvdecContext_1(NvdecContext *pThis, RmHalspecO pThis->__nvdecctxControl_Epilogue__ = &__nvoc_thunk_RmResource_nvdecctxControl_Epilogue; - pThis->__nvdecctxControlLookup__ = &__nvoc_thunk_RsResource_nvdecctxControlLookup; - pThis->__nvdecctxGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_nvdecctxGetSwMethods; pThis->__nvdecctxGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_nvdecctxGetInternalObjectHandle; @@ -347,6 +345,8 @@ static void __nvoc_init_funcTable_NvdecContext_1(NvdecContext *pThis, RmHalspecO pThis->__nvdecctxCanCopy__ = &__nvoc_thunk_RsResource_nvdecctxCanCopy; + pThis->__nvdecctxIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_nvdecctxIsPartialUnmapSupported; + pThis->__nvdecctxPreDestruct__ = &__nvoc_thunk_RsResource_nvdecctxPreDestruct; pThis->__nvdecctxIsDuplicate__ = &__nvoc_thunk_RsResource_nvdecctxIsDuplicate; @@ -381,23 +381,31 @@ void __nvoc_init_NvdecContext(NvdecContext *pThis, RmHalspecOwner *pRmhalspecown __nvoc_init_funcTable_NvdecContext(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; NvdecContext *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvdecContext), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(NvdecContext)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvdecContext); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -415,16 +423,25 @@ NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext **ppThis, Dynamic *pParent, status = __nvoc_ctor_NvdecContext(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_NvdecContext_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_NvdecContext_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(NvdecContext)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h index 88b1b07585..500cba7607 100644 --- a/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvdec_ctx_nvoc.h @@ -41,11 +41,16 @@ ENGDESCRIPTOR nvdecGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClas /*! * RM internal class representing NVXXXX_VIDEO_DECODER */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_NVDEC_CTX_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct NvdecContext { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -71,7 +76,6 @@ struct NvdecContext { NV_STATUS (*__nvdecctxInternalControlForward__)(struct NvdecContext *, NvU32, void *, NvU32); NV_STATUS (*__nvdecctxUnmapFrom__)(struct NvdecContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nvdecctxControl_Epilogue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__nvdecctxControlLookup__)(struct NvdecContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__nvdecctxGetSwMethods__)(struct NvdecContext *, const METHOD **, NvU32 *); NvHandle (*__nvdecctxGetInternalObjectHandle__)(struct NvdecContext *); NV_STATUS (*__nvdecctxControl__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -83,6 +87,7 @@ struct NvdecContext { NV_STATUS (*__nvdecctxUnregisterEvent__)(struct NvdecContext *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__nvdecctxControlSerialization_Prologue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvdecctxCanCopy__)(struct NvdecContext *); + NvBool (*__nvdecctxIsPartialUnmapSupported__)(struct NvdecContext *); void (*__nvdecctxPreDestruct__)(struct NvdecContext *); NV_STATUS (*__nvdecctxIsDuplicate__)(struct NvdecContext *, NvHandle, NvBool *); void (*__nvdecctxControlSerialization_Epilogue__)(struct NvdecContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -133,7 +138,6 @@ NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext**, Dynamic*, NvU32, struct #define nvdecctxInternalControlForward(pGpuResource, command, pParams, size) nvdecctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define nvdecctxUnmapFrom(pResource, pParams) nvdecctxUnmapFrom_DISPATCH(pResource, pParams) #define nvdecctxControl_Epilogue(pResource, pCallContext, pParams) nvdecctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define nvdecctxControlLookup(pResource, pParams, ppEntry) nvdecctxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define nvdecctxGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) nvdecctxGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) #define nvdecctxGetInternalObjectHandle(pGpuResource) nvdecctxGetInternalObjectHandle_DISPATCH(pGpuResource) #define nvdecctxControl(pGpuResource, pCallContext, pParams) nvdecctxControl_DISPATCH(pGpuResource, pCallContext, pParams) @@ -145,6 +149,7 @@ NV_STATUS __nvoc_objCreate_NvdecContext(NvdecContext**, Dynamic*, NvU32, struct #define nvdecctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvdecctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define nvdecctxControlSerialization_Prologue(pResource, pCallContext, pParams) nvdecctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvdecctxCanCopy(pResource) nvdecctxCanCopy_DISPATCH(pResource) +#define nvdecctxIsPartialUnmapSupported(pResource) nvdecctxIsPartialUnmapSupported_DISPATCH(pResource) #define nvdecctxPreDestruct(pResource) nvdecctxPreDestruct_DISPATCH(pResource) #define nvdecctxIsDuplicate(pResource, hMemory, pDuplicate) nvdecctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define nvdecctxControlSerialization_Epilogue(pResource, pCallContext, pParams) nvdecctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -231,10 +236,6 @@ static inline void nvdecctxControl_Epilogue_DISPATCH(struct NvdecContext *pResou pResource->__nvdecctxControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS nvdecctxControlLookup_DISPATCH(struct NvdecContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__nvdecctxControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS nvdecctxGetSwMethods_DISPATCH(struct NvdecContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__nvdecctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -279,6 +280,10 @@ static inline NvBool nvdecctxCanCopy_DISPATCH(struct NvdecContext *pResource) { return pResource->__nvdecctxCanCopy__(pResource); } +static inline NvBool nvdecctxIsPartialUnmapSupported_DISPATCH(struct NvdecContext *pResource) { + return pResource->__nvdecctxIsPartialUnmapSupported__(pResource); +} + static inline void nvdecctxPreDestruct_DISPATCH(struct NvdecContext *pResource) { pResource->__nvdecctxPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c index dfd990269a..70b0ecc5d4 100644 --- a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.c @@ -172,10 +172,6 @@ static void __nvoc_thunk_RmResource_msencctxControl_Epilogue(struct MsencContext rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_msencctxControlLookup(struct MsencContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_ChannelDescendant_msencctxGetSwMethods(struct MsencContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_MsencContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_msencctxCanCopy(struct MsencContext *pReso return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_msencctxIsPartialUnmapSupported(struct MsencContext *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_msencctxPreDestruct(struct MsencContext *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MsencContext_RsResource.offset)); } @@ -323,8 +323,6 @@ static void __nvoc_init_funcTable_MsencContext_1(MsencContext *pThis, RmHalspecO pThis->__msencctxControl_Epilogue__ = &__nvoc_thunk_RmResource_msencctxControl_Epilogue; - pThis->__msencctxControlLookup__ = &__nvoc_thunk_RsResource_msencctxControlLookup; - pThis->__msencctxGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_msencctxGetSwMethods; pThis->__msencctxGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_msencctxGetInternalObjectHandle; @@ -347,6 +345,8 @@ static void __nvoc_init_funcTable_MsencContext_1(MsencContext *pThis, RmHalspecO pThis->__msencctxCanCopy__ = &__nvoc_thunk_RsResource_msencctxCanCopy; + pThis->__msencctxIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_msencctxIsPartialUnmapSupported; + pThis->__msencctxPreDestruct__ = &__nvoc_thunk_RsResource_msencctxPreDestruct; pThis->__msencctxIsDuplicate__ = &__nvoc_thunk_RsResource_msencctxIsDuplicate; @@ -381,23 +381,31 @@ void __nvoc_init_MsencContext(MsencContext *pThis, RmHalspecOwner *pRmhalspecown __nvoc_init_funcTable_MsencContext(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_MsencContext(MsencContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MsencContext(MsencContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MsencContext *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MsencContext), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MsencContext)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MsencContext); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -415,16 +423,25 @@ NV_STATUS __nvoc_objCreate_MsencContext(MsencContext **ppThis, Dynamic *pParent, status = __nvoc_ctor_MsencContext(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MsencContext_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MsencContext_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MsencContext)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h index 1a6aaaf64c..e802a7d1a7 100644 --- a/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvenc_ctx_nvoc.h @@ -41,11 +41,16 @@ ENGDESCRIPTOR msencGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClas /*! * RM internal class representing NVXXXX_VIDEO_ENCODER */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_NVENC_CTX_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MsencContext { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -71,7 +76,6 @@ struct MsencContext { NV_STATUS (*__msencctxInternalControlForward__)(struct MsencContext *, NvU32, void *, NvU32); NV_STATUS (*__msencctxUnmapFrom__)(struct MsencContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__msencctxControl_Epilogue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__msencctxControlLookup__)(struct MsencContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__msencctxGetSwMethods__)(struct MsencContext *, const METHOD **, NvU32 *); NvHandle (*__msencctxGetInternalObjectHandle__)(struct MsencContext *); NV_STATUS (*__msencctxControl__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -83,6 +87,7 @@ struct MsencContext { NV_STATUS (*__msencctxUnregisterEvent__)(struct MsencContext *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__msencctxControlSerialization_Prologue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__msencctxCanCopy__)(struct MsencContext *); + NvBool (*__msencctxIsPartialUnmapSupported__)(struct MsencContext *); void (*__msencctxPreDestruct__)(struct MsencContext *); NV_STATUS (*__msencctxIsDuplicate__)(struct MsencContext *, NvHandle, NvBool *); void (*__msencctxControlSerialization_Epilogue__)(struct MsencContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -133,7 +138,6 @@ NV_STATUS __nvoc_objCreate_MsencContext(MsencContext**, Dynamic*, NvU32, struct #define msencctxInternalControlForward(pGpuResource, command, pParams, size) msencctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define msencctxUnmapFrom(pResource, pParams) msencctxUnmapFrom_DISPATCH(pResource, pParams) #define msencctxControl_Epilogue(pResource, pCallContext, pParams) msencctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define msencctxControlLookup(pResource, pParams, ppEntry) msencctxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define msencctxGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) msencctxGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) #define msencctxGetInternalObjectHandle(pGpuResource) msencctxGetInternalObjectHandle_DISPATCH(pGpuResource) #define msencctxControl(pGpuResource, pCallContext, pParams) msencctxControl_DISPATCH(pGpuResource, pCallContext, pParams) @@ -145,6 +149,7 @@ NV_STATUS __nvoc_objCreate_MsencContext(MsencContext**, Dynamic*, NvU32, struct #define msencctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) msencctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define msencctxControlSerialization_Prologue(pResource, pCallContext, pParams) msencctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define msencctxCanCopy(pResource) msencctxCanCopy_DISPATCH(pResource) +#define msencctxIsPartialUnmapSupported(pResource) msencctxIsPartialUnmapSupported_DISPATCH(pResource) #define msencctxPreDestruct(pResource) msencctxPreDestruct_DISPATCH(pResource) #define msencctxIsDuplicate(pResource, hMemory, pDuplicate) msencctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define msencctxControlSerialization_Epilogue(pResource, pCallContext, pParams) msencctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -231,10 +236,6 @@ static inline void msencctxControl_Epilogue_DISPATCH(struct MsencContext *pResou pResource->__msencctxControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS msencctxControlLookup_DISPATCH(struct MsencContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__msencctxControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS msencctxGetSwMethods_DISPATCH(struct MsencContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__msencctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -279,6 +280,10 @@ static inline NvBool msencctxCanCopy_DISPATCH(struct MsencContext *pResource) { return pResource->__msencctxCanCopy__(pResource); } +static inline NvBool msencctxIsPartialUnmapSupported_DISPATCH(struct MsencContext *pResource) { + return pResource->__msencctxIsPartialUnmapSupported__(pResource); +} + static inline void msencctxPreDestruct_DISPATCH(struct MsencContext *pResource) { pResource->__msencctxPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c index f64b22d81d..b62aa9b06e 100644 --- a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.c @@ -172,10 +172,6 @@ static void __nvoc_thunk_RmResource_nvjpgctxControl_Epilogue(struct NvjpgContext rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_nvjpgctxControlLookup(struct NvjpgContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_ChannelDescendant_nvjpgctxGetSwMethods(struct NvjpgContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_NvjpgContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_nvjpgctxCanCopy(struct NvjpgContext *pReso return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_nvjpgctxIsPartialUnmapSupported(struct NvjpgContext *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_nvjpgctxPreDestruct(struct NvjpgContext *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvjpgContext_RsResource.offset)); } @@ -323,8 +323,6 @@ static void __nvoc_init_funcTable_NvjpgContext_1(NvjpgContext *pThis, RmHalspecO pThis->__nvjpgctxControl_Epilogue__ = &__nvoc_thunk_RmResource_nvjpgctxControl_Epilogue; - pThis->__nvjpgctxControlLookup__ = &__nvoc_thunk_RsResource_nvjpgctxControlLookup; - pThis->__nvjpgctxGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_nvjpgctxGetSwMethods; pThis->__nvjpgctxGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_nvjpgctxGetInternalObjectHandle; @@ -347,6 +345,8 @@ static void __nvoc_init_funcTable_NvjpgContext_1(NvjpgContext *pThis, RmHalspecO pThis->__nvjpgctxCanCopy__ = &__nvoc_thunk_RsResource_nvjpgctxCanCopy; + pThis->__nvjpgctxIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_nvjpgctxIsPartialUnmapSupported; + pThis->__nvjpgctxPreDestruct__ = &__nvoc_thunk_RsResource_nvjpgctxPreDestruct; pThis->__nvjpgctxIsDuplicate__ = &__nvoc_thunk_RsResource_nvjpgctxIsDuplicate; @@ -381,23 +381,31 @@ void __nvoc_init_NvjpgContext(NvjpgContext *pThis, RmHalspecOwner *pRmhalspecown __nvoc_init_funcTable_NvjpgContext(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; NvjpgContext *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvjpgContext), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(NvjpgContext)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvjpgContext); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -415,16 +423,25 @@ NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext **ppThis, Dynamic *pParent, status = __nvoc_ctor_NvjpgContext(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_NvjpgContext_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_NvjpgContext_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(NvjpgContext)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h index a7580f04bf..ba40b0272f 100644 --- a/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvjpg_ctx_nvoc.h @@ -41,11 +41,16 @@ ENGDESCRIPTOR nvjpgGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClas /*! * RM internal class representing NVXXXX_VIDEO_NVJPG */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_NVJPG_CTX_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct NvjpgContext { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -71,7 +76,6 @@ struct NvjpgContext { NV_STATUS (*__nvjpgctxInternalControlForward__)(struct NvjpgContext *, NvU32, void *, NvU32); NV_STATUS (*__nvjpgctxUnmapFrom__)(struct NvjpgContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nvjpgctxControl_Epilogue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__nvjpgctxControlLookup__)(struct NvjpgContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__nvjpgctxGetSwMethods__)(struct NvjpgContext *, const METHOD **, NvU32 *); NvHandle (*__nvjpgctxGetInternalObjectHandle__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxControl__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -83,6 +87,7 @@ struct NvjpgContext { NV_STATUS (*__nvjpgctxUnregisterEvent__)(struct NvjpgContext *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__nvjpgctxControlSerialization_Prologue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nvjpgctxCanCopy__)(struct NvjpgContext *); + NvBool (*__nvjpgctxIsPartialUnmapSupported__)(struct NvjpgContext *); void (*__nvjpgctxPreDestruct__)(struct NvjpgContext *); NV_STATUS (*__nvjpgctxIsDuplicate__)(struct NvjpgContext *, NvHandle, NvBool *); void (*__nvjpgctxControlSerialization_Epilogue__)(struct NvjpgContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -133,7 +138,6 @@ NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext**, Dynamic*, NvU32, struct #define nvjpgctxInternalControlForward(pGpuResource, command, pParams, size) nvjpgctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define nvjpgctxUnmapFrom(pResource, pParams) nvjpgctxUnmapFrom_DISPATCH(pResource, pParams) #define nvjpgctxControl_Epilogue(pResource, pCallContext, pParams) nvjpgctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define nvjpgctxControlLookup(pResource, pParams, ppEntry) nvjpgctxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define nvjpgctxGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) nvjpgctxGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) #define nvjpgctxGetInternalObjectHandle(pGpuResource) nvjpgctxGetInternalObjectHandle_DISPATCH(pGpuResource) #define nvjpgctxControl(pGpuResource, pCallContext, pParams) nvjpgctxControl_DISPATCH(pGpuResource, pCallContext, pParams) @@ -145,6 +149,7 @@ NV_STATUS __nvoc_objCreate_NvjpgContext(NvjpgContext**, Dynamic*, NvU32, struct #define nvjpgctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) nvjpgctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define nvjpgctxControlSerialization_Prologue(pResource, pCallContext, pParams) nvjpgctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nvjpgctxCanCopy(pResource) nvjpgctxCanCopy_DISPATCH(pResource) +#define nvjpgctxIsPartialUnmapSupported(pResource) nvjpgctxIsPartialUnmapSupported_DISPATCH(pResource) #define nvjpgctxPreDestruct(pResource) nvjpgctxPreDestruct_DISPATCH(pResource) #define nvjpgctxIsDuplicate(pResource, hMemory, pDuplicate) nvjpgctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define nvjpgctxControlSerialization_Epilogue(pResource, pCallContext, pParams) nvjpgctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -231,10 +236,6 @@ static inline void nvjpgctxControl_Epilogue_DISPATCH(struct NvjpgContext *pResou pResource->__nvjpgctxControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS nvjpgctxControlLookup_DISPATCH(struct NvjpgContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__nvjpgctxControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS nvjpgctxGetSwMethods_DISPATCH(struct NvjpgContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__nvjpgctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -279,6 +280,10 @@ static inline NvBool nvjpgctxCanCopy_DISPATCH(struct NvjpgContext *pResource) { return pResource->__nvjpgctxCanCopy__(pResource); } +static inline NvBool nvjpgctxIsPartialUnmapSupported_DISPATCH(struct NvjpgContext *pResource) { + return pResource->__nvjpgctxIsPartialUnmapSupported__(pResource); +} + static inline void nvjpgctxPreDestruct_DISPATCH(struct NvjpgContext *pResource) { pResource->__nvjpgctxPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.c b/src/nvidia/generated/g_kernel_nvlink_nvoc.c index 11f4c03c67..cf7e4eca37 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.c @@ -621,23 +621,31 @@ void __nvoc_init_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRmhalspecown __nvoc_init_funcTable_KernelNvlink(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelNvlink *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelNvlink), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelNvlink)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelNvlink); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -655,16 +663,25 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink **ppThis, Dynamic *pParent, status = __nvoc_ctor_KernelNvlink(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelNvlink_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelNvlink_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelNvlink)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.h b/src/nvidia/generated/g_kernel_nvlink_nvoc.h index 95d6e6df65..39236b0470 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.h @@ -192,7 +192,7 @@ typedef struct _def_knvlink_link typedef struct NVLINK_INBAND_CALLBACK { NvU32 messageType; - NV_STATUS (*pCallback)(NvU32 gpuInstance, + NV_STATUS (*pCallback)(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); NvU32 wqItemFlags; } NVLINK_INBAND_MSG_CALLBACK; @@ -210,11 +210,16 @@ MAKE_LIST(FaultUpList, NVLINK_ID); * any interfaces which do not manage the underlying Nvlink hardware * can be managed by this object. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelNvlink { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -306,7 +311,6 @@ struct KernelNvlink { NvU32 PRIVATE_FIELD(sysmemLinkMask); NvU32 PRIVATE_FIELD(peerLinkMasks)[32]; NvU32 PRIVATE_FIELD(forcedSysmemDeviceType); - NVLINK_INBAND_MSG_CALLBACK PRIVATE_FIELD(inbandCallback)[6]; nvlink_device *PRIVATE_FIELD(pNvlinkDev); NvU32 PRIVATE_FIELD(deviceLockRefcount); char *PRIVATE_FIELD(driverName); @@ -419,7 +423,6 @@ struct KernelNvlink_PRIVATE { NvU32 sysmemLinkMask; NvU32 peerLinkMasks[32]; NvU32 forcedSysmemDeviceType; - NVLINK_INBAND_MSG_CALLBACK inbandCallback[6]; nvlink_device *pNvlinkDev; NvU32 deviceLockRefcount; char *driverName; @@ -844,34 +847,6 @@ static inline NV_STATUS knvlinkCoreUpdateDeviceUUID(struct OBJGPU *pGpu, struct #define knvlinkCoreUpdateDeviceUUID_HAL(pGpu, pKernelNvlink) knvlinkCoreUpdateDeviceUUID(pGpu, pKernelNvlink) -NV_STATUS knvlinkRegisterInbandCallback_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NVLINK_INBAND_MSG_CALLBACK *params); - - -#ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkRegisterInbandCallback(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NVLINK_INBAND_MSG_CALLBACK *params) { - NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_nvlink_h_disabled -#define knvlinkRegisterInbandCallback(pGpu, pKernelNvlink, params) knvlinkRegisterInbandCallback_IMPL(pGpu, pKernelNvlink, params) -#endif //__nvoc_kernel_nvlink_h_disabled - -#define knvlinkRegisterInbandCallback_HAL(pGpu, pKernelNvlink, params) knvlinkRegisterInbandCallback(pGpu, pKernelNvlink, params) - -NV_STATUS knvlinkUnregisterInbandCallback_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU16 msgType); - - -#ifdef __nvoc_kernel_nvlink_h_disabled -static inline NV_STATUS knvlinkUnregisterInbandCallback(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU16 msgType) { - NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_nvlink_h_disabled -#define knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, msgType) knvlinkUnregisterInbandCallback_IMPL(pGpu, pKernelNvlink, msgType) -#endif //__nvoc_kernel_nvlink_h_disabled - -#define knvlinkUnregisterInbandCallback_HAL(pGpu, pKernelNvlink, msgType) knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, msgType) - NV_STATUS knvlinkCoreGetRemoteDeviceInfo_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink); @@ -1152,6 +1127,20 @@ static inline NV_STATUS knvlinkInbandMsgCallbackDispatcher(struct OBJGPU *pGpu, #define knvlinkInbandMsgCallbackDispatcher_HAL(pGpu, pKernelNvLink, dataSize, pMessage) knvlinkInbandMsgCallbackDispatcher(pGpu, pKernelNvLink, dataSize, pMessage) +NV_STATUS knvlinkFatalErrorRecovery_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvLink); + + +#ifdef __nvoc_kernel_nvlink_h_disabled +static inline NV_STATUS knvlinkFatalErrorRecovery(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvLink) { + NV_ASSERT_FAILED_PRECOMP("KernelNvlink was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_nvlink_h_disabled +#define knvlinkFatalErrorRecovery(pGpu, pKernelNvLink) knvlinkFatalErrorRecovery_IMPL(pGpu, pKernelNvLink) +#endif //__nvoc_kernel_nvlink_h_disabled + +#define knvlinkFatalErrorRecovery_HAL(pGpu, pKernelNvLink) knvlinkFatalErrorRecovery(pGpu, pKernelNvLink) + NV_STATUS knvlinkSendInbandData_IMPL(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *pParams); @@ -1809,6 +1798,11 @@ static inline NvU32 knvlinkGetIPVersion(struct OBJGPU *pGpu, struct KernelNvlink return pKernelNvlink_PRIVATE->ipVerNvlink; } +static inline NvU32 knvlinkGetMinionControl(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink) { + struct KernelNvlink_PRIVATE *pKernelNvlink_PRIVATE = (struct KernelNvlink_PRIVATE *)pKernelNvlink; + return pKernelNvlink_PRIVATE->minionControl; +} + void knvlinkDestruct_IMPL(struct KernelNvlink *arg0); #define __nvoc_knvlinkDestruct(arg0) knvlinkDestruct_IMPL(arg0) @@ -1879,6 +1873,8 @@ void knvlinkCoreTrainingCompleteCallback (nvlink_link *link); void knvlinkCoreGetUphyLoadCallback (nvlink_link *link, NvBool *bUnlocked); NvlStatus knvlinkCoreAliTrainingCallback (nvlink_link *link); +NvlStatus knvlinkCoreGetCciLinkModeCallback (nvlink_link *link, NvU64 *mode); + #endif // NVLINK Utility Functions diff --git a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c index 43658fe221..f333488859 100644 --- a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c +++ b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.c @@ -172,10 +172,6 @@ static void __nvoc_thunk_RmResource_ofactxControl_Epilogue(struct OfaContext *pR rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_ofactxControlLookup(struct OfaContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_ChannelDescendant_ofactxGetSwMethods(struct OfaContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_OfaContext_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_ofactxCanCopy(struct OfaContext *pResource return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_ofactxIsPartialUnmapSupported(struct OfaContext *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_ofactxPreDestruct(struct OfaContext *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OfaContext_RsResource.offset)); } @@ -323,8 +323,6 @@ static void __nvoc_init_funcTable_OfaContext_1(OfaContext *pThis, RmHalspecOwner pThis->__ofactxControl_Epilogue__ = &__nvoc_thunk_RmResource_ofactxControl_Epilogue; - pThis->__ofactxControlLookup__ = &__nvoc_thunk_RsResource_ofactxControlLookup; - pThis->__ofactxGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_ofactxGetSwMethods; pThis->__ofactxGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_ofactxGetInternalObjectHandle; @@ -347,6 +345,8 @@ static void __nvoc_init_funcTable_OfaContext_1(OfaContext *pThis, RmHalspecOwner pThis->__ofactxCanCopy__ = &__nvoc_thunk_RsResource_ofactxCanCopy; + pThis->__ofactxIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_ofactxIsPartialUnmapSupported; + pThis->__ofactxPreDestruct__ = &__nvoc_thunk_RsResource_ofactxPreDestruct; pThis->__ofactxIsDuplicate__ = &__nvoc_thunk_RsResource_ofactxIsDuplicate; @@ -381,23 +381,31 @@ void __nvoc_init_OfaContext(OfaContext *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_OfaContext(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_OfaContext(OfaContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_OfaContext(OfaContext **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OfaContext *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OfaContext), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OfaContext)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OfaContext); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -415,16 +423,25 @@ NV_STATUS __nvoc_objCreate_OfaContext(OfaContext **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_OfaContext(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_OfaContext_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OfaContext_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OfaContext)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h index 0a8bec05dc..191ca5f54e 100644 --- a/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h +++ b/src/nvidia/generated/g_kernel_ofa_ctx_nvoc.h @@ -41,11 +41,16 @@ ENGDESCRIPTOR ofaGetEngineDescFromAllocParams(OBJGPU *pGpu, NvU32 externalClassI /*! * RM internal class representing NVXXXX_VIDEO_OFA */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_OFA_CTX_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OfaContext { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -71,7 +76,6 @@ struct OfaContext { NV_STATUS (*__ofactxInternalControlForward__)(struct OfaContext *, NvU32, void *, NvU32); NV_STATUS (*__ofactxUnmapFrom__)(struct OfaContext *, RS_RES_UNMAP_FROM_PARAMS *); void (*__ofactxControl_Epilogue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__ofactxControlLookup__)(struct OfaContext *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__ofactxGetSwMethods__)(struct OfaContext *, const METHOD **, NvU32 *); NvHandle (*__ofactxGetInternalObjectHandle__)(struct OfaContext *); NV_STATUS (*__ofactxControl__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -83,6 +87,7 @@ struct OfaContext { NV_STATUS (*__ofactxUnregisterEvent__)(struct OfaContext *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__ofactxControlSerialization_Prologue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ofactxCanCopy__)(struct OfaContext *); + NvBool (*__ofactxIsPartialUnmapSupported__)(struct OfaContext *); void (*__ofactxPreDestruct__)(struct OfaContext *); NV_STATUS (*__ofactxIsDuplicate__)(struct OfaContext *, NvHandle, NvBool *); void (*__ofactxControlSerialization_Epilogue__)(struct OfaContext *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -133,7 +138,6 @@ NV_STATUS __nvoc_objCreate_OfaContext(OfaContext**, Dynamic*, NvU32, struct CALL #define ofactxInternalControlForward(pGpuResource, command, pParams, size) ofactxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define ofactxUnmapFrom(pResource, pParams) ofactxUnmapFrom_DISPATCH(pResource, pParams) #define ofactxControl_Epilogue(pResource, pCallContext, pParams) ofactxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define ofactxControlLookup(pResource, pParams, ppEntry) ofactxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define ofactxGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) ofactxGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) #define ofactxGetInternalObjectHandle(pGpuResource) ofactxGetInternalObjectHandle_DISPATCH(pGpuResource) #define ofactxControl(pGpuResource, pCallContext, pParams) ofactxControl_DISPATCH(pGpuResource, pCallContext, pParams) @@ -145,6 +149,7 @@ NV_STATUS __nvoc_objCreate_OfaContext(OfaContext**, Dynamic*, NvU32, struct CALL #define ofactxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ofactxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define ofactxControlSerialization_Prologue(pResource, pCallContext, pParams) ofactxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ofactxCanCopy(pResource) ofactxCanCopy_DISPATCH(pResource) +#define ofactxIsPartialUnmapSupported(pResource) ofactxIsPartialUnmapSupported_DISPATCH(pResource) #define ofactxPreDestruct(pResource) ofactxPreDestruct_DISPATCH(pResource) #define ofactxIsDuplicate(pResource, hMemory, pDuplicate) ofactxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define ofactxControlSerialization_Epilogue(pResource, pCallContext, pParams) ofactxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -231,10 +236,6 @@ static inline void ofactxControl_Epilogue_DISPATCH(struct OfaContext *pResource, pResource->__ofactxControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS ofactxControlLookup_DISPATCH(struct OfaContext *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__ofactxControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS ofactxGetSwMethods_DISPATCH(struct OfaContext *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__ofactxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -279,6 +280,10 @@ static inline NvBool ofactxCanCopy_DISPATCH(struct OfaContext *pResource) { return pResource->__ofactxCanCopy__(pResource); } +static inline NvBool ofactxIsPartialUnmapSupported_DISPATCH(struct OfaContext *pResource) { + return pResource->__ofactxIsPartialUnmapSupported__(pResource); +} + static inline void ofactxPreDestruct_DISPATCH(struct OfaContext *pResource) { pResource->__ofactxPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_rc_nvoc.c b/src/nvidia/generated/g_kernel_rc_nvoc.c index fed668f80a..c548e93cd7 100644 --- a/src/nvidia/generated/g_kernel_rc_nvoc.c +++ b/src/nvidia/generated/g_kernel_rc_nvoc.c @@ -175,6 +175,16 @@ static void __nvoc_init_funcTable_KernelRc_1(KernelRc *pThis, RmHalspecOwner *pR pThis->__krcConstructEngine__ = &krcConstructEngine_IMPL; + // Hal function -- krcWatchdogRecovery + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__krcWatchdogRecovery__ = &krcWatchdogRecovery_f2d351; + } + else + { + pThis->__krcWatchdogRecovery__ = &krcWatchdogRecovery_KERNEL; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelRc_engstateConstructEngine; pThis->__krcStateLoad__ = &__nvoc_thunk_OBJENGSTATE_krcStateLoad; @@ -217,23 +227,31 @@ void __nvoc_init_KernelRc(KernelRc *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_KernelRc(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelRc(KernelRc **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelRc(KernelRc **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelRc *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelRc), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelRc)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelRc); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -251,16 +269,25 @@ NV_STATUS __nvoc_objCreate_KernelRc(KernelRc **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_KernelRc(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelRc_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelRc_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelRc)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_rc_nvoc.h b/src/nvidia/generated/g_kernel_rc_nvoc.h index 8b639f6890..94528eb3ad 100644 --- a/src/nvidia/generated/g_kernel_rc_nvoc.h +++ b/src/nvidia/generated/g_kernel_rc_nvoc.h @@ -67,11 +67,16 @@ typedef enum { /*! * Kernel interface for RC (Robust Channels) and Watchdog */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_RC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelRc { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -79,6 +84,7 @@ struct KernelRc { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct KernelRc *__nvoc_pbase_KernelRc; NV_STATUS (*__krcConstructEngine__)(struct OBJGPU *, struct KernelRc *, ENGDESCRIPTOR); + void (*__krcWatchdogRecovery__)(struct OBJGPU *, struct KernelRc *); NV_STATUS (*__krcStateLoad__)(POBJGPU, struct KernelRc *, NvU32); NV_STATUS (*__krcStateUnload__)(POBJGPU, struct KernelRc *, NvU32); NV_STATUS (*__krcStateInitLocked__)(POBJGPU, struct KernelRc *); @@ -134,6 +140,8 @@ NV_STATUS __nvoc_objCreate_KernelRc(KernelRc**, Dynamic*, NvU32); __nvoc_objCreate_KernelRc((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) #define krcConstructEngine(pGpu, pKernelRc, engDescriptor) krcConstructEngine_DISPATCH(pGpu, pKernelRc, engDescriptor) +#define krcWatchdogRecovery(pGpu, pKernelRc) krcWatchdogRecovery_DISPATCH(pGpu, pKernelRc) +#define krcWatchdogRecovery_HAL(pGpu, pKernelRc) krcWatchdogRecovery_DISPATCH(pGpu, pKernelRc) #define krcStateLoad(pGpu, pEngstate, arg0) krcStateLoad_DISPATCH(pGpu, pEngstate, arg0) #define krcStateUnload(pGpu, pEngstate, arg0) krcStateUnload_DISPATCH(pGpu, pEngstate, arg0) #define krcStateInitLocked(pGpu, pEngstate) krcStateInitLocked_DISPATCH(pGpu, pEngstate) @@ -298,19 +306,6 @@ static inline void krcWatchdog(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) #define krcWatchdog_HAL(pGpu, pKernelRc) krcWatchdog(pGpu, pKernelRc) -void krcWatchdogRecovery_KERNEL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); - - -#ifdef __nvoc_kernel_rc_h_disabled -static inline void krcWatchdogRecovery(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { - NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); -} -#else //__nvoc_kernel_rc_h_disabled -#define krcWatchdogRecovery(pGpu, pKernelRc) krcWatchdogRecovery_KERNEL(pGpu, pKernelRc) -#endif //__nvoc_kernel_rc_h_disabled - -#define krcWatchdogRecovery_HAL(pGpu, pKernelRc) krcWatchdogRecovery(pGpu, pKernelRc) - static inline void krcWatchdogCallbackPerf_b3696a(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { return; } @@ -332,6 +327,16 @@ static inline NV_STATUS krcConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct return pKernelRc->__krcConstructEngine__(pGpu, pKernelRc, engDescriptor); } +static inline void krcWatchdogRecovery_f2d351(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { + NV_ASSERT_PRECOMP(0); +} + +void krcWatchdogRecovery_KERNEL(struct OBJGPU *pGpu, struct KernelRc *pKernelRc); + +static inline void krcWatchdogRecovery_DISPATCH(struct OBJGPU *pGpu, struct KernelRc *pKernelRc) { + pKernelRc->__krcWatchdogRecovery__(pGpu, pKernelRc); +} + static inline NV_STATUS krcStateLoad_DISPATCH(POBJGPU pGpu, struct KernelRc *pEngstate, NvU32 arg0) { return pEngstate->__krcStateLoad__(pGpu, pEngstate, arg0); } @@ -542,6 +547,17 @@ static inline void krcWatchdogCallbackVblankRecovery(struct OBJGPU *pGpu, struct #define krcWatchdogCallbackVblankRecovery(pGpu, pKernelRc) krcWatchdogCallbackVblankRecovery_IMPL(pGpu, pKernelRc) #endif //__nvoc_kernel_rc_h_disabled +NV_STATUS krcWatchdogGetClientHandle_IMPL(struct KernelRc *arg0, NvHandle *arg1); + +#ifdef __nvoc_kernel_rc_h_disabled +static inline NV_STATUS krcWatchdogGetClientHandle(struct KernelRc *arg0, NvHandle *arg1) { + NV_ASSERT_FAILED_PRECOMP("KernelRc was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_rc_h_disabled +#define krcWatchdogGetClientHandle(arg0, arg1) krcWatchdogGetClientHandle_IMPL(arg0, arg1) +#endif //__nvoc_kernel_rc_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c index 56df886b48..bf303c3052 100644 --- a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c +++ b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.c @@ -105,21 +105,26 @@ void __nvoc_init_KernelSchedMgr(KernelSchedMgr *pThis) { __nvoc_init_funcTable_KernelSchedMgr(pThis); } -NV_STATUS __nvoc_objCreate_KernelSchedMgr(KernelSchedMgr **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelSchedMgr(KernelSchedMgr **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelSchedMgr *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSchedMgr), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelSchedMgr)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSchedMgr); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -134,16 +139,25 @@ NV_STATUS __nvoc_objCreate_KernelSchedMgr(KernelSchedMgr **ppThis, Dynamic *pPar status = __nvoc_ctor_KernelSchedMgr(pThis); if (status != NV_OK) goto __nvoc_objCreate_KernelSchedMgr_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelSchedMgr_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelSchedMgr)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h index 5a540007b2..877b3f24ed 100644 --- a/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h +++ b/src/nvidia/generated/g_kernel_sched_mgr_nvoc.h @@ -48,17 +48,28 @@ extern "C" { /* ------------------------------- Datatypes --------------------------------*/ -#define SCHED_POLICY_DEFAULT 0 -typedef NvU32 SCHED_POLICY; +enum __SCHED_POLICY +{ + SCHED_POLICY_DEFAULT = 0, + SCHED_POLICY_BEST_EFFORT = 1, + SCHED_POLICY_VGPU_EQUAL_SHARE = 2, + SCHED_POLICY_VGPU_FIXED_SHARE = 3, +}; +typedef enum __SCHED_POLICY SCHED_POLICY; /*! * Class of scheduling manager for all the runlists. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_SCHED_MGR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelSchedMgr { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -105,7 +116,7 @@ static inline NvU32 kschedmgrGetSchedPolicy(struct KernelSchedMgr *pKernelSchedM } static inline NvBool kschedmgrIsPvmrlEnabled(struct KernelSchedMgr *pKernelSchedMgr) { - return ((NvBool)(0 != 0)); + return (pKernelSchedMgr->bIsSchedSwEnabled && ((pKernelSchedMgr->configSchedPolicy == SCHED_POLICY_VGPU_EQUAL_SHARE) || (pKernelSchedMgr->configSchedPolicy == SCHED_POLICY_VGPU_FIXED_SHARE))); } void kschedmgrConstructPolicy_IMPL(struct KernelSchedMgr *pKernelSchedMgr, struct OBJGPU *pGpu); diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.c b/src/nvidia/generated/g_kernel_sec2_nvoc.c index de33cd529e..30c4148152 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.c +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.c @@ -106,7 +106,7 @@ static NV_STATUS __nvoc_thunk_KernelSec2_engstateConstructEngine(struct OBJGPU * return ksec2ConstructEngine(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_OBJENGSTATE.offset), arg0); } -static void __nvoc_thunk_KernelSec2_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelSec2, IntrServiceRecord pRecords[168]) { +static void __nvoc_thunk_KernelSec2_intrservRegisterIntrService(struct OBJGPU *pGpu, struct IntrService *pKernelSec2, IntrServiceRecord pRecords[171]) { ksec2RegisterIntrService(pGpu, (struct KernelSec2 *)(((unsigned char *)pKernelSec2) - __nvoc_rtti_KernelSec2_IntrService.offset), pRecords); } @@ -328,57 +328,99 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner } // Hal function -- ksec2ResetHw - pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__ksec2ResetHw__ = &ksec2ResetHw_5baef9; + } + else + { + pThis->__ksec2ResetHw__ = &ksec2ResetHw_TU102; + } // Hal function -- ksec2StateLoad - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__ksec2StateLoad__ = &ksec2StateLoad_GH100; + pThis->__ksec2StateLoad__ = &ksec2StateLoad_56cd7a; } - // default else { - pThis->__ksec2StateLoad__ = &ksec2StateLoad_56cd7a; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__ksec2StateLoad__ = &ksec2StateLoad_GH100; + } + // default + else + { + pThis->__ksec2StateLoad__ = &ksec2StateLoad_56cd7a; + } } // Hal function -- ksec2ReadUcodeFuseVersion - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_b2b553; + pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_474d46; } else { - pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_GA100; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_b2b553; + } + else + { + pThis->__ksec2ReadUcodeFuseVersion__ = &ksec2ReadUcodeFuseVersion_GA100; + } } // Hal function -- ksec2GetBinArchiveBlUcode - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_80f438; } else { - pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_80f438; + } + else + { + pThis->__ksec2GetBinArchiveBlUcode__ = &ksec2GetBinArchiveBlUcode_TU102; + } } // Hal function -- ksec2GetGenericBlUcode - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_5baef9; } else { - pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_TU102; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ + { + pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_5baef9; + } + else + { + pThis->__ksec2GetGenericBlUcode__ = &ksec2GetGenericBlUcode_TU102; + } } // Hal function -- ksec2GetBinArchiveSecurescrubUcode - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_AD10X; + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438; } else { - pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438; + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_AD10X; + } + else + { + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438; + } } pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelSec2_engstateConstructEngine; @@ -471,23 +513,31 @@ void __nvoc_init_KernelSec2(KernelSec2 *pThis, RmHalspecOwner *pRmhalspecowner) __nvoc_init_funcTable_KernelSec2(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2 **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2 **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelSec2 *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSec2), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelSec2)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSec2); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -505,16 +555,25 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2 **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_KernelSec2(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_KernelSec2_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelSec2_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelSec2)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.h b/src/nvidia/generated/g_kernel_sec2_nvoc.h index 49917cc068..5d9da952e6 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.h +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.h @@ -44,11 +44,16 @@ extern "C" { struct _def_rm_flcn_bl_desc; typedef struct _def_rm_flcn_bl_desc RM_FLCN_BL_DESC; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_SEC2_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelSec2 { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -64,7 +69,7 @@ struct KernelSec2 { NV_STATUS (*__ksec2ConstructEngine__)(struct OBJGPU *, struct KernelSec2 *, ENGDESCRIPTOR); void (*__ksec2RegisterIntrService__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceRecord *); NV_STATUS (*__ksec2ServiceNotificationInterrupt__)(struct OBJGPU *, struct KernelSec2 *, IntrServiceServiceNotificationInterruptArguments *); - void (*__ksec2ConfigureFalcon__)(struct OBJGPU *, struct KernelSec2 *); + NV_STATUS (*__ksec2ConfigureFalcon__)(struct OBJGPU *, struct KernelSec2 *); NV_STATUS (*__ksec2ResetHw__)(struct OBJGPU *, struct KernelSec2 *); NV_STATUS (*__ksec2StateLoad__)(struct OBJGPU *, struct KernelSec2 *, NvU32); NvU32 (*__ksec2ReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelSec2 *, NvU32); @@ -189,9 +194,9 @@ static inline NV_STATUS ksec2ConstructEngine_DISPATCH(struct OBJGPU *pGpu, struc return pKernelSec2->__ksec2ConstructEngine__(pGpu, pKernelSec2, arg0); } -void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[168]); +void ksec2RegisterIntrService_IMPL(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[171]); -static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[168]) { +static inline void ksec2RegisterIntrService_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, IntrServiceRecord pRecords[171]) { pKernelSec2->__ksec2RegisterIntrService__(pGpu, pKernelSec2, pRecords); } @@ -201,18 +206,22 @@ static inline NV_STATUS ksec2ServiceNotificationInterrupt_DISPATCH(struct OBJGPU return arg1->__ksec2ServiceNotificationInterrupt__(arg0, arg1, arg2); } -void ksec2ConfigureFalcon_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); +NV_STATUS ksec2ConfigureFalcon_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); -void ksec2ConfigureFalcon_GA100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); +NV_STATUS ksec2ConfigureFalcon_GA100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); -void ksec2ConfigureFalcon_GA102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); +NV_STATUS ksec2ConfigureFalcon_GA102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); -static inline void ksec2ConfigureFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { - pKernelSec2->__ksec2ConfigureFalcon__(pGpu, pKernelSec2); +static inline NV_STATUS ksec2ConfigureFalcon_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { + return pKernelSec2->__ksec2ConfigureFalcon__(pGpu, pKernelSec2); } NV_STATUS ksec2ResetHw_TU102(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); +static inline NV_STATUS ksec2ResetHw_5baef9(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + static inline NV_STATUS ksec2ResetHw_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { return pKernelSec2->__ksec2ResetHw__(pGpu, pKernelSec2); } @@ -233,6 +242,10 @@ static inline NvU32 ksec2ReadUcodeFuseVersion_b2b553(struct OBJGPU *pGpu, struct NvU32 ksec2ReadUcodeFuseVersion_GA100(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId); +static inline NvU32 ksec2ReadUcodeFuseVersion_474d46(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) { + NV_ASSERT_OR_RETURN_PRECOMP(0, 0); +} + static inline NvU32 ksec2ReadUcodeFuseVersion_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2, NvU32 ucodeId) { return pKernelSec2->__ksec2ReadUcodeFuseVersion__(pGpu, pKernelSec2, ucodeId); } diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c index 94962f24f8..f2f78a8950 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.c @@ -139,21 +139,26 @@ void __nvoc_init_RmDebuggerSession(RmDebuggerSession *pThis) { __nvoc_init_funcTable_RmDebuggerSession(pThis); } -NV_STATUS __nvoc_objCreate_RmDebuggerSession(RmDebuggerSession **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_RmDebuggerSession(RmDebuggerSession **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RmDebuggerSession *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmDebuggerSession), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RmDebuggerSession)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmDebuggerSession); pThis->__nvoc_base_RsSession.__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -168,16 +173,25 @@ NV_STATUS __nvoc_objCreate_RmDebuggerSession(RmDebuggerSession **ppThis, Dynamic status = __nvoc_ctor_RmDebuggerSession(pThis); if (status != NV_OK) goto __nvoc_objCreate_RmDebuggerSession_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RmDebuggerSession_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsSession.__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RmDebuggerSession)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -351,10 +365,6 @@ static void __nvoc_thunk_RmResource_ksmdbgssnControl_Epilogue(struct KernelSMDeb rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_ksmdbgssnControlLookup(struct KernelSMDebuggerSession *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_GpuResource_ksmdbgssnControl(struct KernelSMDebuggerSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_KernelSMDebuggerSession_GpuResource.offset), pCallContext, pParams); } @@ -387,6 +397,10 @@ static NvBool __nvoc_thunk_RsResource_ksmdbgssnCanCopy(struct KernelSMDebuggerSe return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_ksmdbgssnIsPartialUnmapSupported(struct KernelSMDebuggerSession *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_ksmdbgssnPreDestruct(struct KernelSMDebuggerSession *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_KernelSMDebuggerSession_RsResource.offset)); } @@ -422,12 +436,12 @@ static NvBool __nvoc_thunk_RmResource_ksmdbgssnAccessCallback(struct KernelSMDeb static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSMDebuggerSession[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdSMDebugModeEnable_fcf1ac, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) - /*flags=*/ 0x2200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0x83de0301u, /*paramSize=*/ 0, @@ -437,12 +451,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdSMDebugModeDisable_fcf1ac, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) - /*flags=*/ 0x2200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0x83de0302u, /*paramSize=*/ 0, @@ -512,12 +526,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM #endif }, { /* [6] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdDebugReadAllSmErrorStates_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x83de030cu, /*paramSize=*/ sizeof(NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS), @@ -542,12 +556,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelSM #endif }, { /* [8] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) ksmdbgssnCtrlCmdDebugClearAllSmErrorStates_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x83de0310u, /*paramSize=*/ sizeof(NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS), @@ -909,11 +923,11 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnGetInternalObjectHandle__ = &ksmdbgssnGetInternalObjectHandle_IMPL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__ksmdbgssnCtrlCmdSMDebugModeEnable__ = &ksmdbgssnCtrlCmdSMDebugModeEnable_fcf1ac; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__ksmdbgssnCtrlCmdSMDebugModeDisable__ = &ksmdbgssnCtrlCmdSMDebugModeDisable_fcf1ac; #endif @@ -941,7 +955,7 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnCtrlCmdDebugReadSingleSmErrorState__ = &ksmdbgssnCtrlCmdDebugReadSingleSmErrorState_fcf1ac; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) pThis->__ksmdbgssnCtrlCmdDebugReadAllSmErrorStates__ = &ksmdbgssnCtrlCmdDebugReadAllSmErrorStates_IMPL; #endif @@ -949,7 +963,7 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnCtrlCmdDebugClearSingleSmErrorState__ = &ksmdbgssnCtrlCmdDebugClearSingleSmErrorState_fcf1ac; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) pThis->__ksmdbgssnCtrlCmdDebugClearAllSmErrorStates__ = &ksmdbgssnCtrlCmdDebugClearAllSmErrorStates_IMPL; #endif @@ -1053,8 +1067,6 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnControl_Epilogue__ = &__nvoc_thunk_RmResource_ksmdbgssnControl_Epilogue; - pThis->__ksmdbgssnControlLookup__ = &__nvoc_thunk_RsResource_ksmdbgssnControlLookup; - pThis->__ksmdbgssnControl__ = &__nvoc_thunk_GpuResource_ksmdbgssnControl; pThis->__ksmdbgssnUnmap__ = &__nvoc_thunk_GpuResource_ksmdbgssnUnmap; @@ -1071,6 +1083,8 @@ static void __nvoc_init_funcTable_KernelSMDebuggerSession_1(KernelSMDebuggerSess pThis->__ksmdbgssnCanCopy__ = &__nvoc_thunk_RsResource_ksmdbgssnCanCopy; + pThis->__ksmdbgssnIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_ksmdbgssnIsPartialUnmapSupported; + pThis->__ksmdbgssnPreDestruct__ = &__nvoc_thunk_RsResource_ksmdbgssnPreDestruct; pThis->__ksmdbgssnIsDuplicate__ = &__nvoc_thunk_RsResource_ksmdbgssnIsDuplicate; @@ -1106,21 +1120,26 @@ void __nvoc_init_KernelSMDebuggerSession(KernelSMDebuggerSession *pThis) { __nvoc_init_funcTable_KernelSMDebuggerSession(pThis); } -NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelSMDebuggerSession *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelSMDebuggerSession), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelSMDebuggerSession)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelSMDebuggerSession); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -1135,16 +1154,25 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession **ppT status = __nvoc_ctor_KernelSMDebuggerSession(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_KernelSMDebuggerSession_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelSMDebuggerSession_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelSMDebuggerSession)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h index 945f5f29e4..f689d5eef3 100644 --- a/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h +++ b/src/nvidia/generated/g_kernel_sm_debugger_session_nvoc.h @@ -78,11 +78,16 @@ typedef struct KernelGraphicsObject KernelGraphicsObject; // invalidating the debugger object when underlying objects that it // relies on are freed before it. // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_SM_DEBUGGER_SESSION_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RmDebuggerSession { const struct NVOC_RTTI *__nvoc_rtti; struct RsSession __nvoc_base_RsSession; @@ -139,11 +144,16 @@ static inline void dbgSessionRemoveDependency_DISPATCH(struct RmDebuggerSession #undef PRIVATE_FIELD + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_SM_DEBUGGER_SESSION_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelSMDebuggerSession { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -199,7 +209,6 @@ struct KernelSMDebuggerSession { NV_STATUS (*__ksmdbgssnGetRegBaseOffsetAndSize__)(struct KernelSMDebuggerSession *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__ksmdbgssnUnmapFrom__)(struct KernelSMDebuggerSession *, RS_RES_UNMAP_FROM_PARAMS *); void (*__ksmdbgssnControl_Epilogue__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__ksmdbgssnControlLookup__)(struct KernelSMDebuggerSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__ksmdbgssnControl__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__ksmdbgssnUnmap__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__ksmdbgssnGetMemInterMapParams__)(struct KernelSMDebuggerSession *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -208,6 +217,7 @@ struct KernelSMDebuggerSession { NV_STATUS (*__ksmdbgssnUnregisterEvent__)(struct KernelSMDebuggerSession *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__ksmdbgssnControlSerialization_Prologue__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__ksmdbgssnCanCopy__)(struct KernelSMDebuggerSession *); + NvBool (*__ksmdbgssnIsPartialUnmapSupported__)(struct KernelSMDebuggerSession *); void (*__ksmdbgssnPreDestruct__)(struct KernelSMDebuggerSession *); NV_STATUS (*__ksmdbgssnIsDuplicate__)(struct KernelSMDebuggerSession *, NvHandle, NvBool *); void (*__ksmdbgssnControlSerialization_Epilogue__)(struct KernelSMDebuggerSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -300,7 +310,6 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession**, Dy #define ksmdbgssnGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) ksmdbgssnGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define ksmdbgssnUnmapFrom(pResource, pParams) ksmdbgssnUnmapFrom_DISPATCH(pResource, pParams) #define ksmdbgssnControl_Epilogue(pResource, pCallContext, pParams) ksmdbgssnControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define ksmdbgssnControlLookup(pResource, pParams, ppEntry) ksmdbgssnControlLookup_DISPATCH(pResource, pParams, ppEntry) #define ksmdbgssnControl(pGpuResource, pCallContext, pParams) ksmdbgssnControl_DISPATCH(pGpuResource, pCallContext, pParams) #define ksmdbgssnUnmap(pGpuResource, pCallContext, pCpuMapping) ksmdbgssnUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define ksmdbgssnGetMemInterMapParams(pRmResource, pParams) ksmdbgssnGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -309,6 +318,7 @@ NV_STATUS __nvoc_objCreate_KernelSMDebuggerSession(KernelSMDebuggerSession**, Dy #define ksmdbgssnUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) ksmdbgssnUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define ksmdbgssnControlSerialization_Prologue(pResource, pCallContext, pParams) ksmdbgssnControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define ksmdbgssnCanCopy(pResource) ksmdbgssnCanCopy_DISPATCH(pResource) +#define ksmdbgssnIsPartialUnmapSupported(pResource) ksmdbgssnIsPartialUnmapSupported_DISPATCH(pResource) #define ksmdbgssnPreDestruct(pResource) ksmdbgssnPreDestruct_DISPATCH(pResource) #define ksmdbgssnIsDuplicate(pResource, hMemory, pDuplicate) ksmdbgssnIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define ksmdbgssnControlSerialization_Epilogue(pResource, pCallContext, pParams) ksmdbgssnControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -586,10 +596,6 @@ static inline void ksmdbgssnControl_Epilogue_DISPATCH(struct KernelSMDebuggerSes pResource->__ksmdbgssnControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS ksmdbgssnControlLookup_DISPATCH(struct KernelSMDebuggerSession *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__ksmdbgssnControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS ksmdbgssnControl_DISPATCH(struct KernelSMDebuggerSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pGpuResource->__ksmdbgssnControl__(pGpuResource, pCallContext, pParams); } @@ -622,6 +628,10 @@ static inline NvBool ksmdbgssnCanCopy_DISPATCH(struct KernelSMDebuggerSession *p return pResource->__ksmdbgssnCanCopy__(pResource); } +static inline NvBool ksmdbgssnIsPartialUnmapSupported_DISPATCH(struct KernelSMDebuggerSession *pResource) { + return pResource->__ksmdbgssnIsPartialUnmapSupported__(pResource); +} + static inline void ksmdbgssnPreDestruct_DISPATCH(struct KernelSMDebuggerSession *pResource) { pResource->__ksmdbgssnPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c index 4b4c050d9d..3b07b67485 100644 --- a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c +++ b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_KernelVgpuMgr(KernelVgpuMgr *pThis) { __nvoc_init_funcTable_KernelVgpuMgr(pThis); } -NV_STATUS __nvoc_objCreate_KernelVgpuMgr(KernelVgpuMgr **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_KernelVgpuMgr(KernelVgpuMgr **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelVgpuMgr *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelVgpuMgr), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelVgpuMgr)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelVgpuMgr); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_KernelVgpuMgr(KernelVgpuMgr **ppThis, Dynamic *pParen status = __nvoc_ctor_KernelVgpuMgr(pThis); if (status != NV_OK) goto __nvoc_objCreate_KernelVgpuMgr_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelVgpuMgr_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelVgpuMgr)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h index 2e45ea3c13..a0faed9b6e 100644 --- a/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h @@ -47,6 +47,7 @@ extern "C" { #include "nvoc/prelude.h" #include "kernel/gpu/fifo/kernel_fifo.h" #include "virtualization/common_vgpu_mgr.h" +#include "gpu_mgr/gpu_mgr.h" struct PhysMemSubAlloc; @@ -119,6 +120,7 @@ typedef struct KERNEL_HOST_VGPU_DEVICE struct KERNEL_VGPU_GUEST *vgpuGuest; NvU32 gfid; NvU32 swizzId; + NvU16 placementId; NvU32 numPluginChannels; NvU32 chidOffset[RM_ENGINE_TYPE_LAST]; NvU32 channelCount[RM_ENGINE_TYPE_LAST]; /*Number of channels available to the VF*/ @@ -153,6 +155,10 @@ typedef struct KERNEL_VGPU_GUEST MAKE_LIST(KERNEL_VGPU_GUEST_LIST, KERNEL_VGPU_GUEST); +#define NV_VGPU_MAX_FB_SIZE_GB 512 + +MAKE_BITVECTOR(PLACEMENT_REGION_BIT_VECTOR, NV_VGPU_MAX_FB_SIZE_GB); + /* pGPU information */ typedef struct { @@ -166,11 +172,19 @@ typedef struct NvBool isAttached; // Per VF per engine ChidOffset. Used for reserving guest channels per engine NvU32 chidOffset[VGPU_MAX_GFID][RM_ENGINE_TYPE_LAST]; + NvU16 creatablePlacementIds[MAX_VGPU_TYPES_PER_PGPU][MAX_VGPU_DEVICES_PER_PGPU]; + NvU32 supportedVmmuOffsets[MAX_VGPU_TYPES_PER_PGPU][MAX_VGPU_DEVICES_PER_PGPU]; + NvU64 gspHeapOffsets[MAX_VGPU_TYPES_PER_PGPU][MAX_VGPU_DEVICES_PER_PGPU]; + NvU32 guestVmmuCount[MAX_VGPU_TYPES_PER_PGPU]; + NvU16 placementRegionSize; + PLACEMENT_REGION_BIT_VECTOR usedPlacementRegionMap; VGPU_CONFIG_EVENT_INFO_NODE_LIST listVgpuConfigEventsHead; NvBool sriovEnabled; + NvBool heterogeneousTimesliceSizesSupported; NvU32 numCreatedVgpu; // Used only on KVM vgpu_vf_pci_info vfPciInfo[MAX_VF_COUNT_PER_GPU]; // Used only on KVM NvU64 createdVfMask; // Used only on KVM + NvBool miniQuarterEnabled; // Used only on ESXi /*! * SwizzId Map. HW currently uses only 14 swizzIds. Every bit position @@ -200,11 +214,16 @@ typedef struct REQUEST_VGPU_INFO_NODE MAKE_LIST(REQUEST_VGPU_INFO_NODE_LIST, REQUEST_VGPU_INFO_NODE); + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_VGPU_MGR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelVgpuMgr { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -263,6 +282,14 @@ kvgpumgrGetPgpuIndex(struct KernelVgpuMgr *pKernelVgpuMgr, NvU32 gpuPciId, NvU32 NV_STATUS kvgpumgrGetVgpuTypeInfo(NvU32 vgpuTypeId, VGPU_TYPE **vgpuType); +NV_STATUS +kvgpumgrSetSupportedPlacementIds(struct OBJGPU *pGpu); + +NV_STATUS +kvgpumgrUpdateHeterogeneousInfo(struct OBJGPU *pGpu, NvU32 vgpuTypeId, NvU16 *placementId, + NvU64 *guestFbLength, NvU64 *guestFbOffset, + NvU64 *gspHeapOffset); + NV_STATUS kvgpumgrPgpuAddVgpuType(struct OBJGPU *pGpu, NvBool discardVgpuTypes, NVA081_CTRL_VGPU_INFO *pVgpuInfo); @@ -290,6 +317,7 @@ kvgpumgrGuestRegister(struct OBJGPU *pGpu, NvU32 swizzId, NvU32 vgpuDeviceInstanceId, NvBool bDisableDefaultSmcExecPartRestore, + NvU16 placementId, KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice); NV_STATUS @@ -299,7 +327,7 @@ NV_STATUS kvgpumgrGetMaxInstanceOfVgpu(NvU32 vgpuTypeId, NvU32 *maxInstanceVgpu); NV_STATUS -kvgpumgrCheckVgpuTypeCreatable(KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, VGPU_TYPE *vgpuTypeInfo); +kvgpumgrCheckVgpuTypeCreatable(struct OBJGPU *pGpu, KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, VGPU_TYPE *vgpuTypeInfo); NV_STATUS kvgpumgrEnumerateVgpuPerPgpu(struct OBJGPU *pGpu, NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams); @@ -313,6 +341,10 @@ kvgpumgrGetSwizzId(struct OBJGPU *pGpu, NvU32 partitionFlag, NvU32 *swizzId); +NV_STATUS +kvgpumgrHeterogeneousGetChidOffset(NvU32 vgpuTypeId, NvU16 placementId, + NvU32 numChannels, NvU64 *pChidOffset); + NV_STATUS kvgpumgrValidateSwizzId(struct OBJGPU *pGpu, NvU32 vgpuTypeId, @@ -346,6 +378,9 @@ kvgpumgrGetHostVgpuDeviceFromVgpuUuid(NvU32 gpuPciId, NvU8 *vgpuUuid, NV_STATUS kvgpumgrGetCreatableVgpuTypes(struct OBJGPU *pGpu, struct KernelVgpuMgr *pKernelVgpuMgr, NvU32 pgpuIndex, NvU32* numVgpuTypes, NvU32* vgpuTypes); +NvU64 +kvgpumgrGetEccAndPrReservedFb(struct OBJGPU *pGpu); + NvU32 kvgpumgrGetPgpuDevIdEncoding(struct OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize); diff --git a/src/nvidia/generated/g_kernel_video_engine_nvoc.c b/src/nvidia/generated/g_kernel_video_engine_nvoc.c index d55131c540..c6ee00787d 100644 --- a/src/nvidia/generated/g_kernel_video_engine_nvoc.c +++ b/src/nvidia/generated/g_kernel_video_engine_nvoc.c @@ -104,6 +104,26 @@ static void __nvoc_init_funcTable_KernelVideoEngine_1(KernelVideoEngine *pThis, PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + + // Hal function -- kvidengInitLogging + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kvidengInitLogging__ = &kvidengInitLogging_46f6a7; + } + else + { + pThis->__kvidengInitLogging__ = &kvidengInitLogging_KERNEL; + } + + // Hal function -- kvidengFreeLogging + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__kvidengFreeLogging__ = &kvidengFreeLogging_b3696a; + } + else + { + pThis->__kvidengFreeLogging__ = &kvidengFreeLogging_KERNEL; + } } void __nvoc_init_funcTable_KernelVideoEngine(KernelVideoEngine *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -118,23 +138,31 @@ void __nvoc_init_KernelVideoEngine(KernelVideoEngine *pThis, RmHalspecOwner *pRm __nvoc_init_funcTable_KernelVideoEngine(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_KernelVideoEngine(KernelVideoEngine **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, ENGDESCRIPTOR arg_physEngDesc) { +NV_STATUS __nvoc_objCreate_KernelVideoEngine(KernelVideoEngine **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, ENGDESCRIPTOR arg_physEngDesc) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; KernelVideoEngine *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(KernelVideoEngine), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(KernelVideoEngine)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_KernelVideoEngine); pThis->__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_Object); @@ -152,16 +180,25 @@ NV_STATUS __nvoc_objCreate_KernelVideoEngine(KernelVideoEngine **ppThis, Dynamic status = __nvoc_ctor_KernelVideoEngine(pThis, pRmhalspecowner, arg_pGpu, arg_physEngDesc); if (status != NV_OK) goto __nvoc_objCreate_KernelVideoEngine_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_KernelVideoEngine_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(KernelVideoEngine)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_kernel_video_engine_nvoc.h b/src/nvidia/generated/g_kernel_video_engine_nvoc.h index 1fe9fcb2ed..172e565bc7 100644 --- a/src/nvidia/generated/g_kernel_video_engine_nvoc.h +++ b/src/nvidia/generated/g_kernel_video_engine_nvoc.h @@ -71,19 +71,31 @@ typedef struct */ PORT_CRYPTO_PRNG *pVideoLogPrng; #endif + + /*! + * Variable holding the regeky value + */ + NvU32 eventTraceRegkeyData; } VIDEO_TRACE_INFO; // Basic implementation of KernelVideoEngine that can be instantiated. + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_KERNEL_VIDEO_ENGINE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct KernelVideoEngine { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct KernelVideoEngine *__nvoc_pbase_KernelVideoEngine; + NV_STATUS (*__kvidengInitLogging__)(struct OBJGPU *, struct KernelVideoEngine *); + void (*__kvidengFreeLogging__)(struct OBJGPU *, struct KernelVideoEngine *); ENGDESCRIPTOR physEngDesc; VIDEO_TRACE_INFO videoTraceInfo; NvBool bVideoTraceEnabled; @@ -117,6 +129,10 @@ NV_STATUS __nvoc_objCreate_KernelVideoEngine(KernelVideoEngine**, Dynamic*, NvU3 #define __objCreate_KernelVideoEngine(ppNewObj, pParent, createFlags, arg_pGpu, arg_physEngDesc) \ __nvoc_objCreate_KernelVideoEngine((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pGpu, arg_physEngDesc) +#define kvidengInitLogging(pGpu, pKernelVideoEngine) kvidengInitLogging_DISPATCH(pGpu, pKernelVideoEngine) +#define kvidengInitLogging_HAL(pGpu, pKernelVideoEngine) kvidengInitLogging_DISPATCH(pGpu, pKernelVideoEngine) +#define kvidengFreeLogging(pGpu, pKernelVideoEngine) kvidengFreeLogging_DISPATCH(pGpu, pKernelVideoEngine) +#define kvidengFreeLogging_HAL(pGpu, pKernelVideoEngine) kvidengFreeLogging_DISPATCH(pGpu, pKernelVideoEngine) NvBool kvidengIsVideoTraceLogSupported_IMPL(struct OBJGPU *pGpu); @@ -125,30 +141,23 @@ NvBool kvidengIsVideoTraceLogSupported_IMPL(struct OBJGPU *pGpu); NV_STATUS kvidengInitLogging_KERNEL(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine); - -#ifdef __nvoc_kernel_video_engine_h_disabled -static inline NV_STATUS kvidengInitLogging(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine) { - NV_ASSERT_FAILED_PRECOMP("KernelVideoEngine was disabled!"); +static inline NV_STATUS kvidengInitLogging_46f6a7(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine) { return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_kernel_video_engine_h_disabled -#define kvidengInitLogging(pGpu, pKernelVideoEngine) kvidengInitLogging_KERNEL(pGpu, pKernelVideoEngine) -#endif //__nvoc_kernel_video_engine_h_disabled -#define kvidengInitLogging_HAL(pGpu, pKernelVideoEngine) kvidengInitLogging(pGpu, pKernelVideoEngine) +static inline NV_STATUS kvidengInitLogging_DISPATCH(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine) { + return pKernelVideoEngine->__kvidengInitLogging__(pGpu, pKernelVideoEngine); +} void kvidengFreeLogging_KERNEL(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine); - -#ifdef __nvoc_kernel_video_engine_h_disabled -static inline void kvidengFreeLogging(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine) { - NV_ASSERT_FAILED_PRECOMP("KernelVideoEngine was disabled!"); +static inline void kvidengFreeLogging_b3696a(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine) { + return; } -#else //__nvoc_kernel_video_engine_h_disabled -#define kvidengFreeLogging(pGpu, pKernelVideoEngine) kvidengFreeLogging_KERNEL(pGpu, pKernelVideoEngine) -#endif //__nvoc_kernel_video_engine_h_disabled -#define kvidengFreeLogging_HAL(pGpu, pKernelVideoEngine) kvidengFreeLogging(pGpu, pKernelVideoEngine) +static inline void kvidengFreeLogging_DISPATCH(struct OBJGPU *pGpu, struct KernelVideoEngine *pKernelVideoEngine) { + pKernelVideoEngine->__kvidengFreeLogging__(pGpu, pKernelVideoEngine); +} NV_STATUS kvidengRingbufferMakeSpace_IMPL(struct OBJGPU *pGpu, NvU32 oldReadPtr, NvU32 size, VIDEO_TRACE_RING_BUFFER *pTraceBuffer); diff --git a/src/nvidia/generated/g_mem_desc_nvoc.h b/src/nvidia/generated/g_mem_desc_nvoc.h index 1259d2adb4..88fe2ce502 100644 --- a/src/nvidia/generated/g_mem_desc_nvoc.h +++ b/src/nvidia/generated/g_mem_desc_nvoc.h @@ -81,6 +81,8 @@ typedef struct COMPR_INFO COMPR_INFO; // // Address space identifiers. +// Note: This should match the NV2080_CTRL_GR_CTX_BUFFER_INFO_APERTURE_* defines +// in ctrl2080gr.h // typedef NvU32 NV_ADDRESS_SPACE; #define ADDR_UNKNOWN 0 // Address space is unknown @@ -355,12 +357,12 @@ typedef enum NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_141 = 174U, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_142 = 175U, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_143 = 176U, + NV_FB_ALLOC_RM_INTERNAL_OWNER_GSP_NOTIFY_OP_SURFACE = 177U, // // Unused tags from here, for any new use-case it's required // to replace the below tags with known verbose strings // - NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_144 = 177U, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_145 = 178U, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_146 = 179U, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_147 = 180U, @@ -1417,6 +1419,7 @@ void memdescSetName(OBJGPU*, MEMORY_DESCRIPTOR *pMemDesc, const char *name, cons // #define MEMDESC_FLAGS_RESTORE_PTE_KIND_ON_FREE NVBIT64(49) + #endif // _MEMDESC_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_mem_export_nvoc.c b/src/nvidia/generated/g_mem_export_nvoc.c new file mode 100644 index 0000000000..170454fe8c --- /dev/null +++ b/src/nvidia/generated/g_mem_export_nvoc.c @@ -0,0 +1,405 @@ +#define NVOC_MEM_EXPORT_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_mem_export_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xe7ac53 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryExport; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +void __nvoc_init_MemoryExport(MemoryExport*); +void __nvoc_init_funcTable_MemoryExport(MemoryExport*); +NV_STATUS __nvoc_ctor_MemoryExport(MemoryExport*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_MemoryExport(MemoryExport*); +void __nvoc_dtor_MemoryExport(MemoryExport*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryExport; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryExport_MemoryExport = { + /*pClassDef=*/ &__nvoc_class_def_MemoryExport, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_MemoryExport, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryExport_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryExport, __nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryExport_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryExport, __nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryExport_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryExport, __nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryExport_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryExport, __nvoc_base_RmResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_MemoryExport = { + /*numRelatives=*/ 5, + /*relatives=*/ { + &__nvoc_rtti_MemoryExport_MemoryExport, + &__nvoc_rtti_MemoryExport_RmResource, + &__nvoc_rtti_MemoryExport_RmResourceCommon, + &__nvoc_rtti_MemoryExport_RsResource, + &__nvoc_rtti_MemoryExport_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryExport = +{ + /*classInfo=*/ { + /*size=*/ sizeof(MemoryExport), + /*classId=*/ classId(MemoryExport), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "MemoryExport", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_MemoryExport, + /*pCastInfo=*/ &__nvoc_castinfo_MemoryExport, + /*pExportInfo=*/ &__nvoc_export_info_MemoryExport +}; + +static NvBool __nvoc_thunk_MemoryExport_resCanCopy(struct RsResource *pMemoryExport) { + return memoryexportCanCopy((struct MemoryExport *)(((unsigned char *)pMemoryExport) - __nvoc_rtti_MemoryExport_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_MemoryExport_resControl(struct RsResource *pMemoryExport, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memoryexportControl((struct MemoryExport *)(((unsigned char *)pMemoryExport) - __nvoc_rtti_MemoryExport_RsResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RmResource_memoryexportShareCallback(struct MemoryExport *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryexportCheckMemInterUnmap(struct MemoryExport *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryExport_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryexportGetMemInterMapParams(struct MemoryExport *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryExport_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryexportGetMemoryMappingDescriptor(struct MemoryExport *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryExport_RmResource.offset), ppMemDesc); +} + +static NvU32 __nvoc_thunk_RsResource_memoryexportGetRefCount(struct MemoryExport *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryexportControlFilter(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_memoryexportAddAdditionalDependants(struct RsClient *pClient, struct MemoryExport *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryexportControlSerialization_Prologue(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryexportControl_Prologue(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryexportUnmap(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset), pCallContext, pCpuMapping); +} + +static NvBool __nvoc_thunk_RsResource_memoryexportIsPartialUnmapSupported(struct MemoryExport *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_memoryexportPreDestruct(struct MemoryExport *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryexportMapTo(struct MemoryExport *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryexportIsDuplicate(struct MemoryExport *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_memoryexportControlSerialization_Epilogue(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmResource_memoryexportControl_Epilogue(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryexportUnmapFrom(struct MemoryExport *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryexportMap(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RsResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_memoryexportAccessCallback(struct MemoryExport *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryExport_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryExport[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryexportCtrlExportMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xe00101u, + /*paramSize=*/ sizeof(NV00E0_CTRL_EXPORT_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryExport.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryexportCtrlExportMem" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryexportCtrlImportMem_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xe00102u, + /*paramSize=*/ sizeof(NV00E0_CTRL_IMPORT_MEM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryExport.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryexportCtrlImportMem" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryexportCtrlGetInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xe00103u, + /*paramSize=*/ sizeof(NV00E0_CTRL_GET_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryExport.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryexportCtrlGetInfo" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryExport = +{ + /*numEntries=*/ 3, + /*pExportEntries=*/ __nvoc_exported_method_def_MemoryExport +}; + +void __nvoc_dtor_RmResource(RmResource*); +void __nvoc_dtor_MemoryExport(MemoryExport *pThis) { + __nvoc_memoryexportDestruct(pThis); + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_MemoryExport(MemoryExport *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RmResource(RmResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_MemoryExport(MemoryExport *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_RmResource(&pThis->__nvoc_base_RmResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryExport_fail_RmResource; + __nvoc_init_dataField_MemoryExport(pThis); + + status = __nvoc_memoryexportConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryExport_fail__init; + goto __nvoc_ctor_MemoryExport_exit; // Success + +__nvoc_ctor_MemoryExport_fail__init: + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); +__nvoc_ctor_MemoryExport_fail_RmResource: +__nvoc_ctor_MemoryExport_exit: + + return status; +} + +static void __nvoc_init_funcTable_MemoryExport_1(MemoryExport *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__memoryexportCanCopy__ = &memoryexportCanCopy_IMPL; + + pThis->__memoryexportControl__ = &memoryexportControl_IMPL; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__memoryexportCtrlExportMem__ = &memoryexportCtrlExportMem_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__memoryexportCtrlImportMem__ = &memoryexportCtrlImportMem_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__memoryexportCtrlGetInfo__ = &memoryexportCtrlGetInfo_IMPL; +#endif + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryExport_resCanCopy; + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resControl__ = &__nvoc_thunk_MemoryExport_resControl; + + pThis->__memoryexportShareCallback__ = &__nvoc_thunk_RmResource_memoryexportShareCallback; + + pThis->__memoryexportCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_memoryexportCheckMemInterUnmap; + + pThis->__memoryexportGetMemInterMapParams__ = &__nvoc_thunk_RmResource_memoryexportGetMemInterMapParams; + + pThis->__memoryexportGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_memoryexportGetMemoryMappingDescriptor; + + pThis->__memoryexportGetRefCount__ = &__nvoc_thunk_RsResource_memoryexportGetRefCount; + + pThis->__memoryexportControlFilter__ = &__nvoc_thunk_RsResource_memoryexportControlFilter; + + pThis->__memoryexportAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memoryexportAddAdditionalDependants; + + pThis->__memoryexportControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memoryexportControlSerialization_Prologue; + + pThis->__memoryexportControl_Prologue__ = &__nvoc_thunk_RmResource_memoryexportControl_Prologue; + + pThis->__memoryexportUnmap__ = &__nvoc_thunk_RsResource_memoryexportUnmap; + + pThis->__memoryexportIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_memoryexportIsPartialUnmapSupported; + + pThis->__memoryexportPreDestruct__ = &__nvoc_thunk_RsResource_memoryexportPreDestruct; + + pThis->__memoryexportMapTo__ = &__nvoc_thunk_RsResource_memoryexportMapTo; + + pThis->__memoryexportIsDuplicate__ = &__nvoc_thunk_RsResource_memoryexportIsDuplicate; + + pThis->__memoryexportControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memoryexportControlSerialization_Epilogue; + + pThis->__memoryexportControl_Epilogue__ = &__nvoc_thunk_RmResource_memoryexportControl_Epilogue; + + pThis->__memoryexportUnmapFrom__ = &__nvoc_thunk_RsResource_memoryexportUnmapFrom; + + pThis->__memoryexportMap__ = &__nvoc_thunk_RsResource_memoryexportMap; + + pThis->__memoryexportAccessCallback__ = &__nvoc_thunk_RmResource_memoryexportAccessCallback; +} + +void __nvoc_init_funcTable_MemoryExport(MemoryExport *pThis) { + __nvoc_init_funcTable_MemoryExport_1(pThis); +} + +void __nvoc_init_RmResource(RmResource*); +void __nvoc_init_MemoryExport(MemoryExport *pThis) { + pThis->__nvoc_pbase_MemoryExport = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_RmResource; + __nvoc_init_RmResource(&pThis->__nvoc_base_RmResource); + __nvoc_init_funcTable_MemoryExport(pThis); +} + +NV_STATUS __nvoc_objCreate_MemoryExport(MemoryExport **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ + NV_STATUS status; + Object *pParentObj = NULL; + MemoryExport *pThis; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryExport), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(MemoryExport)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryExport); + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + // Link the child into the parent if there is one unless flagged not to do so. + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_MemoryExport(pThis); + status = __nvoc_ctor_MemoryExport(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_MemoryExport_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_MemoryExport_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryExport)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_MemoryExport(MemoryExport **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_MemoryExport(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_mem_export_nvoc.h b/src/nvidia/generated/g_mem_export_nvoc.h new file mode 100644 index 0000000000..1076fb4b20 --- /dev/null +++ b/src/nvidia/generated/g_mem_export_nvoc.h @@ -0,0 +1,277 @@ +#ifndef _G_MEM_EXPORT_NVOC_H_ +#define _G_MEM_EXPORT_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions for exporting memory + * + *****************************************************************************/ + +#include "g_mem_export_nvoc.h" + +#ifndef _MEMORYEXPORT_H_ +#define _MEMORYEXPORT_H_ + +#include "core/core.h" +#include "rmapi/resource.h" + +#include "class/cl00e0.h" +#include "ctrl/ctrl00e0.h" + +// **************************************************************************** +// Type Definitions +// **************************************************************************** + +typedef struct mem_export_info MEM_EXPORT_INFO; + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_MEM_EXPORT_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif + +struct MemoryExport { + const struct NVOC_RTTI *__nvoc_rtti; + struct RmResource __nvoc_base_RmResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct MemoryExport *__nvoc_pbase_MemoryExport; + NvBool (*__memoryexportCanCopy__)(struct MemoryExport *); + NV_STATUS (*__memoryexportControl__)(struct MemoryExport *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryexportCtrlExportMem__)(struct MemoryExport *, NV00E0_CTRL_EXPORT_MEM_PARAMS *); + NV_STATUS (*__memoryexportCtrlImportMem__)(struct MemoryExport *, NV00E0_CTRL_IMPORT_MEM_PARAMS *); + NV_STATUS (*__memoryexportCtrlGetInfo__)(struct MemoryExport *, NV00E0_CTRL_GET_INFO_PARAMS *); + NvBool (*__memoryexportShareCallback__)(struct MemoryExport *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memoryexportCheckMemInterUnmap__)(struct MemoryExport *, NvBool); + NV_STATUS (*__memoryexportGetMemInterMapParams__)(struct MemoryExport *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memoryexportGetMemoryMappingDescriptor__)(struct MemoryExport *, struct MEMORY_DESCRIPTOR **); + NvU32 (*__memoryexportGetRefCount__)(struct MemoryExport *); + NV_STATUS (*__memoryexportControlFilter__)(struct MemoryExport *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__memoryexportAddAdditionalDependants__)(struct RsClient *, struct MemoryExport *, RsResourceRef *); + NV_STATUS (*__memoryexportControlSerialization_Prologue__)(struct MemoryExport *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryexportControl_Prologue__)(struct MemoryExport *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryexportUnmap__)(struct MemoryExport *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__memoryexportIsPartialUnmapSupported__)(struct MemoryExport *); + void (*__memoryexportPreDestruct__)(struct MemoryExport *); + NV_STATUS (*__memoryexportMapTo__)(struct MemoryExport *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memoryexportIsDuplicate__)(struct MemoryExport *, NvHandle, NvBool *); + void (*__memoryexportControlSerialization_Epilogue__)(struct MemoryExport *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__memoryexportControl_Epilogue__)(struct MemoryExport *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryexportUnmapFrom__)(struct MemoryExport *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__memoryexportMap__)(struct MemoryExport *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__memoryexportAccessCallback__)(struct MemoryExport *, struct RsClient *, void *, RsAccessRight); + MEM_EXPORT_INFO *PRIVATE_FIELD(pExportInfo); +}; + +#ifndef __NVOC_CLASS_MemoryExport_TYPEDEF__ +#define __NVOC_CLASS_MemoryExport_TYPEDEF__ +typedef struct MemoryExport MemoryExport; +#endif /* __NVOC_CLASS_MemoryExport_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryExport +#define __nvoc_class_id_MemoryExport 0xe7ac53 +#endif /* __nvoc_class_id_MemoryExport */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryExport; + +#define __staticCast_MemoryExport(pThis) \ + ((pThis)->__nvoc_pbase_MemoryExport) + +#ifdef __nvoc_mem_export_h_disabled +#define __dynamicCast_MemoryExport(pThis) ((MemoryExport*)NULL) +#else //__nvoc_mem_export_h_disabled +#define __dynamicCast_MemoryExport(pThis) \ + ((MemoryExport*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(MemoryExport))) +#endif //__nvoc_mem_export_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_MemoryExport(MemoryExport**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_MemoryExport(MemoryExport**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_MemoryExport(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_MemoryExport((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define memoryexportCanCopy(pMemoryExport) memoryexportCanCopy_DISPATCH(pMemoryExport) +#define memoryexportControl(pMemoryExport, pCallContext, pParams) memoryexportControl_DISPATCH(pMemoryExport, pCallContext, pParams) +#define memoryexportCtrlExportMem(pMemoryExport, pParams) memoryexportCtrlExportMem_DISPATCH(pMemoryExport, pParams) +#define memoryexportCtrlImportMem(pMemoryExport, pParams) memoryexportCtrlImportMem_DISPATCH(pMemoryExport, pParams) +#define memoryexportCtrlGetInfo(pMemoryExport, pParams) memoryexportCtrlGetInfo_DISPATCH(pMemoryExport, pParams) +#define memoryexportShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memoryexportShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memoryexportCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) memoryexportCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define memoryexportGetMemInterMapParams(pRmResource, pParams) memoryexportGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define memoryexportGetMemoryMappingDescriptor(pRmResource, ppMemDesc) memoryexportGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define memoryexportGetRefCount(pResource) memoryexportGetRefCount_DISPATCH(pResource) +#define memoryexportControlFilter(pResource, pCallContext, pParams) memoryexportControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memoryexportAddAdditionalDependants(pClient, pResource, pReference) memoryexportAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memoryexportControlSerialization_Prologue(pResource, pCallContext, pParams) memoryexportControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryexportControl_Prologue(pResource, pCallContext, pParams) memoryexportControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryexportUnmap(pResource, pCallContext, pCpuMapping) memoryexportUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define memoryexportIsPartialUnmapSupported(pResource) memoryexportIsPartialUnmapSupported_DISPATCH(pResource) +#define memoryexportPreDestruct(pResource) memoryexportPreDestruct_DISPATCH(pResource) +#define memoryexportMapTo(pResource, pParams) memoryexportMapTo_DISPATCH(pResource, pParams) +#define memoryexportIsDuplicate(pResource, hMemory, pDuplicate) memoryexportIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define memoryexportControlSerialization_Epilogue(pResource, pCallContext, pParams) memoryexportControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memoryexportControl_Epilogue(pResource, pCallContext, pParams) memoryexportControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memoryexportUnmapFrom(pResource, pParams) memoryexportUnmapFrom_DISPATCH(pResource, pParams) +#define memoryexportMap(pResource, pCallContext, pParams, pCpuMapping) memoryexportMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) +#define memoryexportAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memoryexportAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NvBool memoryexportCanCopy_IMPL(struct MemoryExport *pMemoryExport); + +static inline NvBool memoryexportCanCopy_DISPATCH(struct MemoryExport *pMemoryExport) { + return pMemoryExport->__memoryexportCanCopy__(pMemoryExport); +} + +NV_STATUS memoryexportControl_IMPL(struct MemoryExport *pMemoryExport, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS memoryexportControl_DISPATCH(struct MemoryExport *pMemoryExport, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemoryExport->__memoryexportControl__(pMemoryExport, pCallContext, pParams); +} + +NV_STATUS memoryexportCtrlExportMem_IMPL(struct MemoryExport *pMemoryExport, NV00E0_CTRL_EXPORT_MEM_PARAMS *pParams); + +static inline NV_STATUS memoryexportCtrlExportMem_DISPATCH(struct MemoryExport *pMemoryExport, NV00E0_CTRL_EXPORT_MEM_PARAMS *pParams) { + return pMemoryExport->__memoryexportCtrlExportMem__(pMemoryExport, pParams); +} + +NV_STATUS memoryexportCtrlImportMem_IMPL(struct MemoryExport *pMemoryExport, NV00E0_CTRL_IMPORT_MEM_PARAMS *pParams); + +static inline NV_STATUS memoryexportCtrlImportMem_DISPATCH(struct MemoryExport *pMemoryExport, NV00E0_CTRL_IMPORT_MEM_PARAMS *pParams) { + return pMemoryExport->__memoryexportCtrlImportMem__(pMemoryExport, pParams); +} + +NV_STATUS memoryexportCtrlGetInfo_IMPL(struct MemoryExport *pMemoryExport, NV00E0_CTRL_GET_INFO_PARAMS *pParams); + +static inline NV_STATUS memoryexportCtrlGetInfo_DISPATCH(struct MemoryExport *pMemoryExport, NV00E0_CTRL_GET_INFO_PARAMS *pParams) { + return pMemoryExport->__memoryexportCtrlGetInfo__(pMemoryExport, pParams); +} + +static inline NvBool memoryexportShareCallback_DISPATCH(struct MemoryExport *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memoryexportShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memoryexportCheckMemInterUnmap_DISPATCH(struct MemoryExport *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__memoryexportCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS memoryexportGetMemInterMapParams_DISPATCH(struct MemoryExport *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__memoryexportGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS memoryexportGetMemoryMappingDescriptor_DISPATCH(struct MemoryExport *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__memoryexportGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NvU32 memoryexportGetRefCount_DISPATCH(struct MemoryExport *pResource) { + return pResource->__memoryexportGetRefCount__(pResource); +} + +static inline NV_STATUS memoryexportControlFilter_DISPATCH(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryexportControlFilter__(pResource, pCallContext, pParams); +} + +static inline void memoryexportAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryExport *pResource, RsResourceRef *pReference) { + pResource->__memoryexportAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS memoryexportControlSerialization_Prologue_DISPATCH(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryexportControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryexportControl_Prologue_DISPATCH(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryexportControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryexportUnmap_DISPATCH(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__memoryexportUnmap__(pResource, pCallContext, pCpuMapping); +} + +static inline NvBool memoryexportIsPartialUnmapSupported_DISPATCH(struct MemoryExport *pResource) { + return pResource->__memoryexportIsPartialUnmapSupported__(pResource); +} + +static inline void memoryexportPreDestruct_DISPATCH(struct MemoryExport *pResource) { + pResource->__memoryexportPreDestruct__(pResource); +} + +static inline NV_STATUS memoryexportMapTo_DISPATCH(struct MemoryExport *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memoryexportMapTo__(pResource, pParams); +} + +static inline NV_STATUS memoryexportIsDuplicate_DISPATCH(struct MemoryExport *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__memoryexportIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void memoryexportControlSerialization_Epilogue_DISPATCH(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryexportControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline void memoryexportControl_Epilogue_DISPATCH(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryexportControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryexportUnmapFrom_DISPATCH(struct MemoryExport *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memoryexportUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS memoryexportMap_DISPATCH(struct MemoryExport *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pResource->__memoryexportMap__(pResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool memoryexportAccessCallback_DISPATCH(struct MemoryExport *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__memoryexportAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS memoryexportConstruct_IMPL(struct MemoryExport *arg_pMemoryExport, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_memoryexportConstruct(arg_pMemoryExport, arg_pCallContext, arg_pParams) memoryexportConstruct_IMPL(arg_pMemoryExport, arg_pCallContext, arg_pParams) +void memoryexportDestruct_IMPL(struct MemoryExport *pMemoryExport); + +#define __nvoc_memoryexportDestruct(pMemoryExport) memoryexportDestruct_IMPL(pMemoryExport) +#undef PRIVATE_FIELD + + +void memoryexportClearCache(NvU16 nodeId); +NvU16 memoryExportGetNodeId(NV_EXPORT_MEM_PACKET *pExportPacket); + +#endif /* _MEMORYEXPORT_H_ */ + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_MEM_EXPORT_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_fabric_import_ref_nvoc.c b/src/nvidia/generated/g_mem_fabric_import_ref_nvoc.c new file mode 100644 index 0000000000..f9363de7b4 --- /dev/null +++ b/src/nvidia/generated/g_mem_fabric_import_ref_nvoc.c @@ -0,0 +1,365 @@ +#define NVOC_MEM_FABRIC_IMPORT_REF_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_mem_fabric_import_ref_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x189bad = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryFabricImportedRef; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +void __nvoc_init_MemoryFabricImportedRef(MemoryFabricImportedRef*); +void __nvoc_init_funcTable_MemoryFabricImportedRef(MemoryFabricImportedRef*); +NV_STATUS __nvoc_ctor_MemoryFabricImportedRef(MemoryFabricImportedRef*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_MemoryFabricImportedRef(MemoryFabricImportedRef*); +void __nvoc_dtor_MemoryFabricImportedRef(MemoryFabricImportedRef*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryFabricImportedRef; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportedRef_MemoryFabricImportedRef = { + /*pClassDef=*/ &__nvoc_class_def_MemoryFabricImportedRef, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_MemoryFabricImportedRef, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportedRef_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportedRef, __nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportedRef_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportedRef, __nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportedRef_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportedRef, __nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportedRef_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportedRef, __nvoc_base_RmResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_MemoryFabricImportedRef = { + /*numRelatives=*/ 5, + /*relatives=*/ { + &__nvoc_rtti_MemoryFabricImportedRef_MemoryFabricImportedRef, + &__nvoc_rtti_MemoryFabricImportedRef_RmResource, + &__nvoc_rtti_MemoryFabricImportedRef_RmResourceCommon, + &__nvoc_rtti_MemoryFabricImportedRef_RsResource, + &__nvoc_rtti_MemoryFabricImportedRef_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryFabricImportedRef = +{ + /*classInfo=*/ { + /*size=*/ sizeof(MemoryFabricImportedRef), + /*classId=*/ classId(MemoryFabricImportedRef), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "MemoryFabricImportedRef", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_MemoryFabricImportedRef, + /*pCastInfo=*/ &__nvoc_castinfo_MemoryFabricImportedRef, + /*pExportInfo=*/ &__nvoc_export_info_MemoryFabricImportedRef +}; + +static NvBool __nvoc_thunk_MemoryFabricImportedRef_resCanCopy(struct RsResource *pMemoryFabricImportedRef) { + return memoryfabricimportedrefCanCopy((struct MemoryFabricImportedRef *)(((unsigned char *)pMemoryFabricImportedRef) - __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset)); +} + +static NvBool __nvoc_thunk_RmResource_memoryfabricimportedrefShareCallback(struct MemoryFabricImportedRef *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricimportedrefCheckMemInterUnmap(struct MemoryFabricImportedRef *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportedrefControl(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControl((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricimportedrefGetMemInterMapParams(struct MemoryFabricImportedRef *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricimportedrefGetMemoryMappingDescriptor(struct MemoryFabricImportedRef *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), ppMemDesc); +} + +static NvU32 __nvoc_thunk_RsResource_memoryfabricimportedrefGetRefCount(struct MemoryFabricImportedRef *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportedrefControlFilter(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RsResource_memoryfabricimportedrefAddAdditionalDependants(struct RsClient *pClient, struct MemoryFabricImportedRef *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricimportedrefControlSerialization_Prologue(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricimportedrefControl_Prologue(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportedrefUnmap(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset), pCallContext, pCpuMapping); +} + +static NvBool __nvoc_thunk_RsResource_memoryfabricimportedrefIsPartialUnmapSupported(struct MemoryFabricImportedRef *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_memoryfabricimportedrefPreDestruct(struct MemoryFabricImportedRef *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportedrefMapTo(struct MemoryFabricImportedRef *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportedrefIsDuplicate(struct MemoryFabricImportedRef *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_memoryfabricimportedrefControlSerialization_Epilogue(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), pCallContext, pParams); +} + +static void __nvoc_thunk_RmResource_memoryfabricimportedrefControl_Epilogue(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportedrefUnmapFrom(struct MemoryFabricImportedRef *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportedrefMap(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RsResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_memoryfabricimportedrefAccessCallback(struct MemoryFabricImportedRef *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportedRef_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFabricImportedRef[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricimportedrefCtrlValidate_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfb0101u, + /*paramSize=*/ sizeof(NV00FB_CTRL_VALIDATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabricImportedRef.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricimportedrefCtrlValidate" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryFabricImportedRef = +{ + /*numEntries=*/ 1, + /*pExportEntries=*/ __nvoc_exported_method_def_MemoryFabricImportedRef +}; + +void __nvoc_dtor_RmResource(RmResource*); +void __nvoc_dtor_MemoryFabricImportedRef(MemoryFabricImportedRef *pThis) { + __nvoc_memoryfabricimportedrefDestruct(pThis); + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_MemoryFabricImportedRef(MemoryFabricImportedRef *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_RmResource(RmResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_MemoryFabricImportedRef(MemoryFabricImportedRef *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_RmResource(&pThis->__nvoc_base_RmResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryFabricImportedRef_fail_RmResource; + __nvoc_init_dataField_MemoryFabricImportedRef(pThis); + + status = __nvoc_memoryfabricimportedrefConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryFabricImportedRef_fail__init; + goto __nvoc_ctor_MemoryFabricImportedRef_exit; // Success + +__nvoc_ctor_MemoryFabricImportedRef_fail__init: + __nvoc_dtor_RmResource(&pThis->__nvoc_base_RmResource); +__nvoc_ctor_MemoryFabricImportedRef_fail_RmResource: +__nvoc_ctor_MemoryFabricImportedRef_exit: + + return status; +} + +static void __nvoc_init_funcTable_MemoryFabricImportedRef_1(MemoryFabricImportedRef *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__memoryfabricimportedrefCanCopy__ = &memoryfabricimportedrefCanCopy_IMPL; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__memoryfabricimportedrefCtrlValidate__ = &memoryfabricimportedrefCtrlValidate_IMPL; +#endif + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryFabricImportedRef_resCanCopy; + + pThis->__memoryfabricimportedrefShareCallback__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefShareCallback; + + pThis->__memoryfabricimportedrefCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefCheckMemInterUnmap; + + pThis->__memoryfabricimportedrefControl__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefControl; + + pThis->__memoryfabricimportedrefGetMemInterMapParams__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefGetMemInterMapParams; + + pThis->__memoryfabricimportedrefGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefGetMemoryMappingDescriptor; + + pThis->__memoryfabricimportedrefGetRefCount__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefGetRefCount; + + pThis->__memoryfabricimportedrefControlFilter__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefControlFilter; + + pThis->__memoryfabricimportedrefAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefAddAdditionalDependants; + + pThis->__memoryfabricimportedrefControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefControlSerialization_Prologue; + + pThis->__memoryfabricimportedrefControl_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefControl_Prologue; + + pThis->__memoryfabricimportedrefUnmap__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefUnmap; + + pThis->__memoryfabricimportedrefIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefIsPartialUnmapSupported; + + pThis->__memoryfabricimportedrefPreDestruct__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefPreDestruct; + + pThis->__memoryfabricimportedrefMapTo__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefMapTo; + + pThis->__memoryfabricimportedrefIsDuplicate__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefIsDuplicate; + + pThis->__memoryfabricimportedrefControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefControlSerialization_Epilogue; + + pThis->__memoryfabricimportedrefControl_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefControl_Epilogue; + + pThis->__memoryfabricimportedrefUnmapFrom__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefUnmapFrom; + + pThis->__memoryfabricimportedrefMap__ = &__nvoc_thunk_RsResource_memoryfabricimportedrefMap; + + pThis->__memoryfabricimportedrefAccessCallback__ = &__nvoc_thunk_RmResource_memoryfabricimportedrefAccessCallback; +} + +void __nvoc_init_funcTable_MemoryFabricImportedRef(MemoryFabricImportedRef *pThis) { + __nvoc_init_funcTable_MemoryFabricImportedRef_1(pThis); +} + +void __nvoc_init_RmResource(RmResource*); +void __nvoc_init_MemoryFabricImportedRef(MemoryFabricImportedRef *pThis) { + pThis->__nvoc_pbase_MemoryFabricImportedRef = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_RmResource; + __nvoc_init_RmResource(&pThis->__nvoc_base_RmResource); + __nvoc_init_funcTable_MemoryFabricImportedRef(pThis); +} + +NV_STATUS __nvoc_objCreate_MemoryFabricImportedRef(MemoryFabricImportedRef **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ + NV_STATUS status; + Object *pParentObj = NULL; + MemoryFabricImportedRef *pThis; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryFabricImportedRef), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(MemoryFabricImportedRef)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryFabricImportedRef); + + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + // Link the child into the parent if there is one unless flagged not to do so. + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_MemoryFabricImportedRef(pThis); + status = __nvoc_ctor_MemoryFabricImportedRef(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_MemoryFabricImportedRef_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_MemoryFabricImportedRef_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryFabricImportedRef)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_MemoryFabricImportedRef(MemoryFabricImportedRef **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_MemoryFabricImportedRef(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_mem_fabric_import_ref_nvoc.h b/src/nvidia/generated/g_mem_fabric_import_ref_nvoc.h new file mode 100644 index 0000000000..7ca817ab1d --- /dev/null +++ b/src/nvidia/generated/g_mem_fabric_import_ref_nvoc.h @@ -0,0 +1,257 @@ +#ifndef _G_MEM_FABRIC_IMPORT_REF_NVOC_H_ +#define _G_MEM_FABRIC_IMPORT_REF_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions managing the ref-counted imported + * fabric memory + * + *****************************************************************************/ + +#include "g_mem_fabric_import_ref_nvoc.h" + +#ifndef _MEMORYFABRICIMPORTREF_H_ +#define _MEMORYFABRICIMPORTREF_H_ + +#include "core/core.h" +#include "rmapi/resource.h" +#include "mem_mgr/mem_fabric_import_v2.h" + +#include "ctrl/ctrl00fb.h" + +// **************************************************************************** +// Type Definitions +// **************************************************************************** + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_MEM_FABRIC_IMPORT_REF_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif + +struct MemoryFabricImportedRef { + const struct NVOC_RTTI *__nvoc_rtti; + struct RmResource __nvoc_base_RmResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct MemoryFabricImportedRef *__nvoc_pbase_MemoryFabricImportedRef; + NvBool (*__memoryfabricimportedrefCanCopy__)(struct MemoryFabricImportedRef *); + NV_STATUS (*__memoryfabricimportedrefCtrlValidate__)(struct MemoryFabricImportedRef *, NV00FB_CTRL_VALIDATE_PARAMS *); + NvBool (*__memoryfabricimportedrefShareCallback__)(struct MemoryFabricImportedRef *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memoryfabricimportedrefCheckMemInterUnmap__)(struct MemoryFabricImportedRef *, NvBool); + NV_STATUS (*__memoryfabricimportedrefControl__)(struct MemoryFabricImportedRef *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportedrefGetMemInterMapParams__)(struct MemoryFabricImportedRef *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memoryfabricimportedrefGetMemoryMappingDescriptor__)(struct MemoryFabricImportedRef *, struct MEMORY_DESCRIPTOR **); + NvU32 (*__memoryfabricimportedrefGetRefCount__)(struct MemoryFabricImportedRef *); + NV_STATUS (*__memoryfabricimportedrefControlFilter__)(struct MemoryFabricImportedRef *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__memoryfabricimportedrefAddAdditionalDependants__)(struct RsClient *, struct MemoryFabricImportedRef *, RsResourceRef *); + NV_STATUS (*__memoryfabricimportedrefControlSerialization_Prologue__)(struct MemoryFabricImportedRef *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportedrefControl_Prologue__)(struct MemoryFabricImportedRef *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportedrefUnmap__)(struct MemoryFabricImportedRef *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__memoryfabricimportedrefIsPartialUnmapSupported__)(struct MemoryFabricImportedRef *); + void (*__memoryfabricimportedrefPreDestruct__)(struct MemoryFabricImportedRef *); + NV_STATUS (*__memoryfabricimportedrefMapTo__)(struct MemoryFabricImportedRef *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__memoryfabricimportedrefIsDuplicate__)(struct MemoryFabricImportedRef *, NvHandle, NvBool *); + void (*__memoryfabricimportedrefControlSerialization_Epilogue__)(struct MemoryFabricImportedRef *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + void (*__memoryfabricimportedrefControl_Epilogue__)(struct MemoryFabricImportedRef *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportedrefUnmapFrom__)(struct MemoryFabricImportedRef *, RS_RES_UNMAP_FROM_PARAMS *); + NV_STATUS (*__memoryfabricimportedrefMap__)(struct MemoryFabricImportedRef *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__memoryfabricimportedrefAccessCallback__)(struct MemoryFabricImportedRef *, struct RsClient *, void *, RsAccessRight); + NvU64 PRIVATE_FIELD(numUpdatedPfns); + MEMORY_DESCRIPTOR *PRIVATE_FIELD(pTempMemDesc); + MEM_FABRIC_IMPORT_DESCRIPTOR *PRIVATE_FIELD(pFabricImportDesc); +}; + +#ifndef __NVOC_CLASS_MemoryFabricImportedRef_TYPEDEF__ +#define __NVOC_CLASS_MemoryFabricImportedRef_TYPEDEF__ +typedef struct MemoryFabricImportedRef MemoryFabricImportedRef; +#endif /* __NVOC_CLASS_MemoryFabricImportedRef_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryFabricImportedRef +#define __nvoc_class_id_MemoryFabricImportedRef 0x189bad +#endif /* __nvoc_class_id_MemoryFabricImportedRef */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryFabricImportedRef; + +#define __staticCast_MemoryFabricImportedRef(pThis) \ + ((pThis)->__nvoc_pbase_MemoryFabricImportedRef) + +#ifdef __nvoc_mem_fabric_import_ref_h_disabled +#define __dynamicCast_MemoryFabricImportedRef(pThis) ((MemoryFabricImportedRef*)NULL) +#else //__nvoc_mem_fabric_import_ref_h_disabled +#define __dynamicCast_MemoryFabricImportedRef(pThis) \ + ((MemoryFabricImportedRef*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(MemoryFabricImportedRef))) +#endif //__nvoc_mem_fabric_import_ref_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_MemoryFabricImportedRef(MemoryFabricImportedRef**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_MemoryFabricImportedRef(MemoryFabricImportedRef**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_MemoryFabricImportedRef(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_MemoryFabricImportedRef((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define memoryfabricimportedrefCanCopy(pMemoryFabricImportedRef) memoryfabricimportedrefCanCopy_DISPATCH(pMemoryFabricImportedRef) +#define memoryfabricimportedrefCtrlValidate(pMemoryFabricImportedRef, pParams) memoryfabricimportedrefCtrlValidate_DISPATCH(pMemoryFabricImportedRef, pParams) +#define memoryfabricimportedrefShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memoryfabricimportedrefShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memoryfabricimportedrefCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) memoryfabricimportedrefCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define memoryfabricimportedrefControl(pResource, pCallContext, pParams) memoryfabricimportedrefControl_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportedrefGetMemInterMapParams(pRmResource, pParams) memoryfabricimportedrefGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define memoryfabricimportedrefGetMemoryMappingDescriptor(pRmResource, ppMemDesc) memoryfabricimportedrefGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define memoryfabricimportedrefGetRefCount(pResource) memoryfabricimportedrefGetRefCount_DISPATCH(pResource) +#define memoryfabricimportedrefControlFilter(pResource, pCallContext, pParams) memoryfabricimportedrefControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportedrefAddAdditionalDependants(pClient, pResource, pReference) memoryfabricimportedrefAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memoryfabricimportedrefControlSerialization_Prologue(pResource, pCallContext, pParams) memoryfabricimportedrefControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportedrefControl_Prologue(pResource, pCallContext, pParams) memoryfabricimportedrefControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportedrefUnmap(pResource, pCallContext, pCpuMapping) memoryfabricimportedrefUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define memoryfabricimportedrefIsPartialUnmapSupported(pResource) memoryfabricimportedrefIsPartialUnmapSupported_DISPATCH(pResource) +#define memoryfabricimportedrefPreDestruct(pResource) memoryfabricimportedrefPreDestruct_DISPATCH(pResource) +#define memoryfabricimportedrefMapTo(pResource, pParams) memoryfabricimportedrefMapTo_DISPATCH(pResource, pParams) +#define memoryfabricimportedrefIsDuplicate(pResource, hMemory, pDuplicate) memoryfabricimportedrefIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define memoryfabricimportedrefControlSerialization_Epilogue(pResource, pCallContext, pParams) memoryfabricimportedrefControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportedrefControl_Epilogue(pResource, pCallContext, pParams) memoryfabricimportedrefControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportedrefUnmapFrom(pResource, pParams) memoryfabricimportedrefUnmapFrom_DISPATCH(pResource, pParams) +#define memoryfabricimportedrefMap(pResource, pCallContext, pParams, pCpuMapping) memoryfabricimportedrefMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) +#define memoryfabricimportedrefAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memoryfabricimportedrefAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NvBool memoryfabricimportedrefCanCopy_IMPL(struct MemoryFabricImportedRef *pMemoryFabricImportedRef); + +static inline NvBool memoryfabricimportedrefCanCopy_DISPATCH(struct MemoryFabricImportedRef *pMemoryFabricImportedRef) { + return pMemoryFabricImportedRef->__memoryfabricimportedrefCanCopy__(pMemoryFabricImportedRef); +} + +NV_STATUS memoryfabricimportedrefCtrlValidate_IMPL(struct MemoryFabricImportedRef *pMemoryFabricImportedRef, NV00FB_CTRL_VALIDATE_PARAMS *pParams); + +static inline NV_STATUS memoryfabricimportedrefCtrlValidate_DISPATCH(struct MemoryFabricImportedRef *pMemoryFabricImportedRef, NV00FB_CTRL_VALIDATE_PARAMS *pParams) { + return pMemoryFabricImportedRef->__memoryfabricimportedrefCtrlValidate__(pMemoryFabricImportedRef, pParams); +} + +static inline NvBool memoryfabricimportedrefShareCallback_DISPATCH(struct MemoryFabricImportedRef *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memoryfabricimportedrefShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memoryfabricimportedrefCheckMemInterUnmap_DISPATCH(struct MemoryFabricImportedRef *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__memoryfabricimportedrefCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS memoryfabricimportedrefControl_DISPATCH(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricimportedrefControl__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricimportedrefGetMemInterMapParams_DISPATCH(struct MemoryFabricImportedRef *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__memoryfabricimportedrefGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS memoryfabricimportedrefGetMemoryMappingDescriptor_DISPATCH(struct MemoryFabricImportedRef *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__memoryfabricimportedrefGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NvU32 memoryfabricimportedrefGetRefCount_DISPATCH(struct MemoryFabricImportedRef *pResource) { + return pResource->__memoryfabricimportedrefGetRefCount__(pResource); +} + +static inline NV_STATUS memoryfabricimportedrefControlFilter_DISPATCH(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricimportedrefControlFilter__(pResource, pCallContext, pParams); +} + +static inline void memoryfabricimportedrefAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryFabricImportedRef *pResource, RsResourceRef *pReference) { + pResource->__memoryfabricimportedrefAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS memoryfabricimportedrefControlSerialization_Prologue_DISPATCH(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricimportedrefControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricimportedrefControl_Prologue_DISPATCH(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricimportedrefControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricimportedrefUnmap_DISPATCH(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pResource->__memoryfabricimportedrefUnmap__(pResource, pCallContext, pCpuMapping); +} + +static inline NvBool memoryfabricimportedrefIsPartialUnmapSupported_DISPATCH(struct MemoryFabricImportedRef *pResource) { + return pResource->__memoryfabricimportedrefIsPartialUnmapSupported__(pResource); +} + +static inline void memoryfabricimportedrefPreDestruct_DISPATCH(struct MemoryFabricImportedRef *pResource) { + pResource->__memoryfabricimportedrefPreDestruct__(pResource); +} + +static inline NV_STATUS memoryfabricimportedrefMapTo_DISPATCH(struct MemoryFabricImportedRef *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memoryfabricimportedrefMapTo__(pResource, pParams); +} + +static inline NV_STATUS memoryfabricimportedrefIsDuplicate_DISPATCH(struct MemoryFabricImportedRef *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__memoryfabricimportedrefIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void memoryfabricimportedrefControlSerialization_Epilogue_DISPATCH(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryfabricimportedrefControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline void memoryfabricimportedrefControl_Epilogue_DISPATCH(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryfabricimportedrefControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricimportedrefUnmapFrom_DISPATCH(struct MemoryFabricImportedRef *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memoryfabricimportedrefUnmapFrom__(pResource, pParams); +} + +static inline NV_STATUS memoryfabricimportedrefMap_DISPATCH(struct MemoryFabricImportedRef *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pResource->__memoryfabricimportedrefMap__(pResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool memoryfabricimportedrefAccessCallback_DISPATCH(struct MemoryFabricImportedRef *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__memoryfabricimportedrefAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS memoryfabricimportedrefConstruct_IMPL(struct MemoryFabricImportedRef *arg_pMemoryFabricImportedRef, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_memoryfabricimportedrefConstruct(arg_pMemoryFabricImportedRef, arg_pCallContext, arg_pParams) memoryfabricimportedrefConstruct_IMPL(arg_pMemoryFabricImportedRef, arg_pCallContext, arg_pParams) +void memoryfabricimportedrefDestruct_IMPL(struct MemoryFabricImportedRef *pMemoryFabricImportedRef); + +#define __nvoc_memoryfabricimportedrefDestruct(pMemoryFabricImportedRef) memoryfabricimportedrefDestruct_IMPL(pMemoryFabricImportedRef) +#undef PRIVATE_FIELD + + +#endif /* _MEMORYFABRICIMPORTREF_H_ */ + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_MEM_FABRIC_IMPORT_REF_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_fabric_import_v2_nvoc.c b/src/nvidia/generated/g_mem_fabric_import_v2_nvoc.c new file mode 100644 index 0000000000..fca3741736 --- /dev/null +++ b/src/nvidia/generated/g_mem_fabric_import_v2_nvoc.c @@ -0,0 +1,417 @@ +#define NVOC_MEM_FABRIC_IMPORT_V2_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_mem_fabric_import_v2_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xf96871 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryFabricImportV2; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Memory; + +void __nvoc_init_MemoryFabricImportV2(MemoryFabricImportV2*); +void __nvoc_init_funcTable_MemoryFabricImportV2(MemoryFabricImportV2*); +NV_STATUS __nvoc_ctor_MemoryFabricImportV2(MemoryFabricImportV2*, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_MemoryFabricImportV2(MemoryFabricImportV2*); +void __nvoc_dtor_MemoryFabricImportV2(MemoryFabricImportV2*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryFabricImportV2; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportV2_MemoryFabricImportV2 = { + /*pClassDef=*/ &__nvoc_class_def_MemoryFabricImportV2, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_MemoryFabricImportV2, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportV2_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportV2, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportV2_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportV2, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportV2_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportV2, __nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportV2_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportV2, __nvoc_base_Memory.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_MemoryFabricImportV2_Memory = { + /*pClassDef=*/ &__nvoc_class_def_Memory, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(MemoryFabricImportV2, __nvoc_base_Memory), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_MemoryFabricImportV2 = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_MemoryFabricImportV2_MemoryFabricImportV2, + &__nvoc_rtti_MemoryFabricImportV2_Memory, + &__nvoc_rtti_MemoryFabricImportV2_RmResource, + &__nvoc_rtti_MemoryFabricImportV2_RmResourceCommon, + &__nvoc_rtti_MemoryFabricImportV2_RsResource, + &__nvoc_rtti_MemoryFabricImportV2_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryFabricImportV2 = +{ + /*classInfo=*/ { + /*size=*/ sizeof(MemoryFabricImportV2), + /*classId=*/ classId(MemoryFabricImportV2), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "MemoryFabricImportV2", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_MemoryFabricImportV2, + /*pCastInfo=*/ &__nvoc_castinfo_MemoryFabricImportV2, + /*pExportInfo=*/ &__nvoc_export_info_MemoryFabricImportV2 +}; + +static NvBool __nvoc_thunk_MemoryFabricImportV2_resCanCopy(struct RsResource *pMemoryFabricImportV2) { + return memoryfabricimportv2CanCopy((struct MemoryFabricImportV2 *)(((unsigned char *)pMemoryFabricImportV2) - __nvoc_rtti_MemoryFabricImportV2_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_MemoryFabricImportV2_memIsReady(struct Memory *pMemoryFabricImportV2, NvBool bCopyConstructorContext) { + return memoryfabricimportv2IsReady((struct MemoryFabricImportV2 *)(((unsigned char *)pMemoryFabricImportV2) - __nvoc_rtti_MemoryFabricImportV2_Memory.offset), bCopyConstructorContext); +} + +static NV_STATUS __nvoc_thunk_MemoryFabricImportV2_memControl(struct Memory *pMemoryFabricImportV2, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return memoryfabricimportv2Control((struct MemoryFabricImportV2 *)(((unsigned char *)pMemoryFabricImportV2) - __nvoc_rtti_MemoryFabricImportV2_Memory.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_MemoryFabricImportV2_memGetMapAddrSpace(struct Memory *pMemoryFabricImportV2, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return memoryfabricimportv2GetMapAddrSpace((struct MemoryFabricImportV2 *)(((unsigned char *)pMemoryFabricImportV2) - __nvoc_rtti_MemoryFabricImportV2_Memory.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvBool __nvoc_thunk_MemoryFabricImportV2_memIsGpuMapAllowed(struct Memory *pMemoryFabricImportV2, struct OBJGPU *pGpu) { + return memoryfabricimportv2IsGpuMapAllowed((struct MemoryFabricImportV2 *)(((unsigned char *)pMemoryFabricImportV2) - __nvoc_rtti_MemoryFabricImportV2_Memory.offset), pGpu); +} + +static NvBool __nvoc_thunk_MemoryFabricImportV2_memIsExportAllowed(struct Memory *pMemoryFabricImportV2) { + return memoryfabricimportv2IsExportAllowed((struct MemoryFabricImportV2 *)(((unsigned char *)pMemoryFabricImportV2) - __nvoc_rtti_MemoryFabricImportV2_Memory.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricimportv2CheckMemInterUnmap(struct MemoryFabricImportV2 *pMemory, NvBool bSubdeviceHandleProvided) { + return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabricImportV2_Memory.offset), bSubdeviceHandleProvided); +} + +static NvBool __nvoc_thunk_RmResource_memoryfabricimportv2ShareCallback(struct MemoryFabricImportV2 *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return rmresShareCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RmResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportv2MapTo(struct MemoryFabricImportV2 *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RsResource.offset), pParams); +} + +static NvU32 __nvoc_thunk_RsResource_memoryfabricimportv2GetRefCount(struct MemoryFabricImportV2 *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_memoryfabricimportv2AddAdditionalDependants(struct RsClient *pClient, struct MemoryFabricImportV2 *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricimportv2Control_Prologue(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportv2UnmapFrom(struct MemoryFabricImportV2 *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_memoryfabricimportv2Control_Epilogue(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricimportv2Unmap(struct MemoryFabricImportV2 *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabricImportV2_Memory.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricimportv2GetMemInterMapParams(struct MemoryFabricImportV2 *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return memGetMemInterMapParams((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabricImportV2_Memory.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricimportv2GetMemoryMappingDescriptor(struct MemoryFabricImportV2 *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return memGetMemoryMappingDescriptor((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabricImportV2_Memory.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_memoryfabricimportv2ControlFilter(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_memoryfabricimportv2ControlSerialization_Prologue(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_memoryfabricimportv2IsPartialUnmapSupported(struct MemoryFabricImportV2 *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricimportv2CheckCopyPermissions(struct MemoryFabricImportV2 *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabricImportV2_Memory.offset), pDstGpu, pDstDevice); +} + +static void __nvoc_thunk_RsResource_memoryfabricimportv2PreDestruct(struct MemoryFabricImportV2 *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricimportv2IsDuplicate(struct MemoryFabricImportV2 *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return memIsDuplicate((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabricImportV2_Memory.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_memoryfabricimportv2ControlSerialization_Epilogue(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_Memory_memoryfabricimportv2Map(struct MemoryFabricImportV2 *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return memMap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabricImportV2_Memory.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_memoryfabricimportv2AccessCallback(struct MemoryFabricImportV2 *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabricImportV2_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryFabricImportV2[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memoryfabricimportv2CtrlGetInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xf90101u, + /*paramSize=*/ sizeof(NV00F9_CTRL_GET_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryFabricImportV2.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memoryfabricimportv2CtrlGetInfo" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryFabricImportV2 = +{ + /*numEntries=*/ 1, + /*pExportEntries=*/ __nvoc_exported_method_def_MemoryFabricImportV2 +}; + +void __nvoc_dtor_Memory(Memory*); +void __nvoc_dtor_MemoryFabricImportV2(MemoryFabricImportV2 *pThis) { + __nvoc_memoryfabricimportv2Destruct(pThis); + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_MemoryFabricImportV2(MemoryFabricImportV2 *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_Memory(Memory* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_MemoryFabricImportV2(MemoryFabricImportV2 *pThis, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_Memory(&pThis->__nvoc_base_Memory, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryFabricImportV2_fail_Memory; + __nvoc_init_dataField_MemoryFabricImportV2(pThis); + + status = __nvoc_memoryfabricimportv2Construct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_MemoryFabricImportV2_fail__init; + goto __nvoc_ctor_MemoryFabricImportV2_exit; // Success + +__nvoc_ctor_MemoryFabricImportV2_fail__init: + __nvoc_dtor_Memory(&pThis->__nvoc_base_Memory); +__nvoc_ctor_MemoryFabricImportV2_fail_Memory: +__nvoc_ctor_MemoryFabricImportV2_exit: + + return status; +} + +static void __nvoc_init_funcTable_MemoryFabricImportV2_1(MemoryFabricImportV2 *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + + pThis->__memoryfabricimportv2CanCopy__ = &memoryfabricimportv2CanCopy_IMPL; + + pThis->__memoryfabricimportv2IsReady__ = &memoryfabricimportv2IsReady_IMPL; + + pThis->__memoryfabricimportv2CopyConstruct__ = &memoryfabricimportv2CopyConstruct_IMPL; + + pThis->__memoryfabricimportv2Control__ = &memoryfabricimportv2Control_IMPL; + + pThis->__memoryfabricimportv2GetMapAddrSpace__ = &memoryfabricimportv2GetMapAddrSpace_IMPL; + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__memoryfabricimportv2CtrlGetInfo__ = &memoryfabricimportv2CtrlGetInfo_IMPL; +#endif + + pThis->__memoryfabricimportv2IsGpuMapAllowed__ = &memoryfabricimportv2IsGpuMapAllowed_IMPL; + + pThis->__memoryfabricimportv2IsExportAllowed__ = &memoryfabricimportv2IsExportAllowed_IMPL; + + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryFabricImportV2_resCanCopy; + + pThis->__nvoc_base_Memory.__memIsReady__ = &__nvoc_thunk_MemoryFabricImportV2_memIsReady; + + pThis->__nvoc_base_Memory.__memControl__ = &__nvoc_thunk_MemoryFabricImportV2_memControl; + + pThis->__nvoc_base_Memory.__memGetMapAddrSpace__ = &__nvoc_thunk_MemoryFabricImportV2_memGetMapAddrSpace; + + pThis->__nvoc_base_Memory.__memIsGpuMapAllowed__ = &__nvoc_thunk_MemoryFabricImportV2_memIsGpuMapAllowed; + + pThis->__nvoc_base_Memory.__memIsExportAllowed__ = &__nvoc_thunk_MemoryFabricImportV2_memIsExportAllowed; + + pThis->__memoryfabricimportv2CheckMemInterUnmap__ = &__nvoc_thunk_Memory_memoryfabricimportv2CheckMemInterUnmap; + + pThis->__memoryfabricimportv2ShareCallback__ = &__nvoc_thunk_RmResource_memoryfabricimportv2ShareCallback; + + pThis->__memoryfabricimportv2MapTo__ = &__nvoc_thunk_RsResource_memoryfabricimportv2MapTo; + + pThis->__memoryfabricimportv2GetRefCount__ = &__nvoc_thunk_RsResource_memoryfabricimportv2GetRefCount; + + pThis->__memoryfabricimportv2AddAdditionalDependants__ = &__nvoc_thunk_RsResource_memoryfabricimportv2AddAdditionalDependants; + + pThis->__memoryfabricimportv2Control_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricimportv2Control_Prologue; + + pThis->__memoryfabricimportv2UnmapFrom__ = &__nvoc_thunk_RsResource_memoryfabricimportv2UnmapFrom; + + pThis->__memoryfabricimportv2Control_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricimportv2Control_Epilogue; + + pThis->__memoryfabricimportv2Unmap__ = &__nvoc_thunk_Memory_memoryfabricimportv2Unmap; + + pThis->__memoryfabricimportv2GetMemInterMapParams__ = &__nvoc_thunk_Memory_memoryfabricimportv2GetMemInterMapParams; + + pThis->__memoryfabricimportv2GetMemoryMappingDescriptor__ = &__nvoc_thunk_Memory_memoryfabricimportv2GetMemoryMappingDescriptor; + + pThis->__memoryfabricimportv2ControlFilter__ = &__nvoc_thunk_RsResource_memoryfabricimportv2ControlFilter; + + pThis->__memoryfabricimportv2ControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricimportv2ControlSerialization_Prologue; + + pThis->__memoryfabricimportv2IsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_memoryfabricimportv2IsPartialUnmapSupported; + + pThis->__memoryfabricimportv2CheckCopyPermissions__ = &__nvoc_thunk_Memory_memoryfabricimportv2CheckCopyPermissions; + + pThis->__memoryfabricimportv2PreDestruct__ = &__nvoc_thunk_RsResource_memoryfabricimportv2PreDestruct; + + pThis->__memoryfabricimportv2IsDuplicate__ = &__nvoc_thunk_Memory_memoryfabricimportv2IsDuplicate; + + pThis->__memoryfabricimportv2ControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricimportv2ControlSerialization_Epilogue; + + pThis->__memoryfabricimportv2Map__ = &__nvoc_thunk_Memory_memoryfabricimportv2Map; + + pThis->__memoryfabricimportv2AccessCallback__ = &__nvoc_thunk_RmResource_memoryfabricimportv2AccessCallback; +} + +void __nvoc_init_funcTable_MemoryFabricImportV2(MemoryFabricImportV2 *pThis) { + __nvoc_init_funcTable_MemoryFabricImportV2_1(pThis); +} + +void __nvoc_init_Memory(Memory*); +void __nvoc_init_MemoryFabricImportV2(MemoryFabricImportV2 *pThis) { + pThis->__nvoc_pbase_MemoryFabricImportV2 = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_Memory.__nvoc_base_RmResource; + pThis->__nvoc_pbase_Memory = &pThis->__nvoc_base_Memory; + __nvoc_init_Memory(&pThis->__nvoc_base_Memory); + __nvoc_init_funcTable_MemoryFabricImportV2(pThis); +} + +NV_STATUS __nvoc_objCreate_MemoryFabricImportV2(MemoryFabricImportV2 **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ + NV_STATUS status; + Object *pParentObj = NULL; + MemoryFabricImportV2 *pThis; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryFabricImportV2), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(MemoryFabricImportV2)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryFabricImportV2); + + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + // Link the child into the parent if there is one unless flagged not to do so. + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_MemoryFabricImportV2(pThis); + status = __nvoc_ctor_MemoryFabricImportV2(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_MemoryFabricImportV2_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_MemoryFabricImportV2_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(MemoryFabricImportV2)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_MemoryFabricImportV2(MemoryFabricImportV2 **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_MemoryFabricImportV2(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_mem_fabric_import_v2_nvoc.h b/src/nvidia/generated/g_mem_fabric_import_v2_nvoc.h new file mode 100644 index 0000000000..d28f9ba9f6 --- /dev/null +++ b/src/nvidia/generated/g_mem_fabric_import_v2_nvoc.h @@ -0,0 +1,347 @@ +#ifndef _G_MEM_FABRIC_IMPORT_V2_NVOC_H_ +#define _G_MEM_FABRIC_IMPORT_V2_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions for import fabric memory + * + *****************************************************************************/ + +#include "g_mem_fabric_import_v2_nvoc.h" + +#ifndef _MEMORYFABRICIMPORTV2_H_ +#define _MEMORYFABRICIMPORTV2_H_ + +#include "core/core.h" +#include "rmapi/resource.h" +#include "mem_mgr/mem.h" +#include "containers/list.h" +#include "nvCpuUuid.h" + +#include "ctrl/ctrl00f9.h" + +// **************************************************************************** +// Type Definitions +// **************************************************************************** + +typedef struct mem_fabric_import_descriptor MEM_FABRIC_IMPORT_DESCRIPTOR; + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_MEM_FABRIC_IMPORT_V2_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif + +struct MemoryFabricImportV2 { + const struct NVOC_RTTI *__nvoc_rtti; + struct Memory __nvoc_base_Memory; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct Memory *__nvoc_pbase_Memory; + struct MemoryFabricImportV2 *__nvoc_pbase_MemoryFabricImportV2; + NvBool (*__memoryfabricimportv2CanCopy__)(struct MemoryFabricImportV2 *); + NV_STATUS (*__memoryfabricimportv2IsReady__)(struct MemoryFabricImportV2 *, NvBool); + NV_STATUS (*__memoryfabricimportv2CopyConstruct__)(struct MemoryFabricImportV2 *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportv2Control__)(struct MemoryFabricImportV2 *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportv2GetMapAddrSpace__)(struct MemoryFabricImportV2 *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NV_STATUS (*__memoryfabricimportv2CtrlGetInfo__)(struct MemoryFabricImportV2 *, NV00F9_CTRL_GET_INFO_PARAMS *); + NvBool (*__memoryfabricimportv2IsGpuMapAllowed__)(struct MemoryFabricImportV2 *, struct OBJGPU *); + NvBool (*__memoryfabricimportv2IsExportAllowed__)(struct MemoryFabricImportV2 *); + NV_STATUS (*__memoryfabricimportv2CheckMemInterUnmap__)(struct MemoryFabricImportV2 *, NvBool); + NvBool (*__memoryfabricimportv2ShareCallback__)(struct MemoryFabricImportV2 *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__memoryfabricimportv2MapTo__)(struct MemoryFabricImportV2 *, RS_RES_MAP_TO_PARAMS *); + NvU32 (*__memoryfabricimportv2GetRefCount__)(struct MemoryFabricImportV2 *); + void (*__memoryfabricimportv2AddAdditionalDependants__)(struct RsClient *, struct MemoryFabricImportV2 *, RsResourceRef *); + NV_STATUS (*__memoryfabricimportv2Control_Prologue__)(struct MemoryFabricImportV2 *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportv2UnmapFrom__)(struct MemoryFabricImportV2 *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__memoryfabricimportv2Control_Epilogue__)(struct MemoryFabricImportV2 *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportv2Unmap__)(struct MemoryFabricImportV2 *, CALL_CONTEXT *, RsCpuMapping *); + NV_STATUS (*__memoryfabricimportv2GetMemInterMapParams__)(struct MemoryFabricImportV2 *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__memoryfabricimportv2GetMemoryMappingDescriptor__)(struct MemoryFabricImportV2 *, MEMORY_DESCRIPTOR **); + NV_STATUS (*__memoryfabricimportv2ControlFilter__)(struct MemoryFabricImportV2 *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportv2ControlSerialization_Prologue__)(struct MemoryFabricImportV2 *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memoryfabricimportv2IsPartialUnmapSupported__)(struct MemoryFabricImportV2 *); + NV_STATUS (*__memoryfabricimportv2CheckCopyPermissions__)(struct MemoryFabricImportV2 *, struct OBJGPU *, struct Device *); + void (*__memoryfabricimportv2PreDestruct__)(struct MemoryFabricImportV2 *); + NV_STATUS (*__memoryfabricimportv2IsDuplicate__)(struct MemoryFabricImportV2 *, NvHandle, NvBool *); + void (*__memoryfabricimportv2ControlSerialization_Epilogue__)(struct MemoryFabricImportV2 *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__memoryfabricimportv2Map__)(struct MemoryFabricImportV2 *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); + NvBool (*__memoryfabricimportv2AccessCallback__)(struct MemoryFabricImportV2 *, struct RsClient *, void *, RsAccessRight); + NvU16 expNodeId; + MEM_FABRIC_IMPORT_DESCRIPTOR *PRIVATE_FIELD(pFabricImportDesc); +}; + +#ifndef __NVOC_CLASS_MemoryFabricImportV2_TYPEDEF__ +#define __NVOC_CLASS_MemoryFabricImportV2_TYPEDEF__ +typedef struct MemoryFabricImportV2 MemoryFabricImportV2; +#endif /* __NVOC_CLASS_MemoryFabricImportV2_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryFabricImportV2 +#define __nvoc_class_id_MemoryFabricImportV2 0xf96871 +#endif /* __nvoc_class_id_MemoryFabricImportV2 */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_MemoryFabricImportV2; + +#define __staticCast_MemoryFabricImportV2(pThis) \ + ((pThis)->__nvoc_pbase_MemoryFabricImportV2) + +#ifdef __nvoc_mem_fabric_import_v2_h_disabled +#define __dynamicCast_MemoryFabricImportV2(pThis) ((MemoryFabricImportV2*)NULL) +#else //__nvoc_mem_fabric_import_v2_h_disabled +#define __dynamicCast_MemoryFabricImportV2(pThis) \ + ((MemoryFabricImportV2*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(MemoryFabricImportV2))) +#endif //__nvoc_mem_fabric_import_v2_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_MemoryFabricImportV2(MemoryFabricImportV2**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_MemoryFabricImportV2(MemoryFabricImportV2**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_MemoryFabricImportV2(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_MemoryFabricImportV2((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define memoryfabricimportv2CanCopy(pMemoryFabricImportV2) memoryfabricimportv2CanCopy_DISPATCH(pMemoryFabricImportV2) +#define memoryfabricimportv2IsReady(pMemoryFabricImportV2, bCopyConstructorContext) memoryfabricimportv2IsReady_DISPATCH(pMemoryFabricImportV2, bCopyConstructorContext) +#define memoryfabricimportv2CopyConstruct(pMemoryFabricImportV2, pCallContext, pParams) memoryfabricimportv2CopyConstruct_DISPATCH(pMemoryFabricImportV2, pCallContext, pParams) +#define memoryfabricimportv2Control(pMemoryFabricImportV2, pCallContext, pParams) memoryfabricimportv2Control_DISPATCH(pMemoryFabricImportV2, pCallContext, pParams) +#define memoryfabricimportv2GetMapAddrSpace(pMemoryFabricImportV2, pCallContext, mapFlags, pAddrSpace) memoryfabricimportv2GetMapAddrSpace_DISPATCH(pMemoryFabricImportV2, pCallContext, mapFlags, pAddrSpace) +#define memoryfabricimportv2CtrlGetInfo(pMemoryFabricImportV2, pParams) memoryfabricimportv2CtrlGetInfo_DISPATCH(pMemoryFabricImportV2, pParams) +#define memoryfabricimportv2IsGpuMapAllowed(pMemoryFabricImportV2, pGpu) memoryfabricimportv2IsGpuMapAllowed_DISPATCH(pMemoryFabricImportV2, pGpu) +#define memoryfabricimportv2IsExportAllowed(pMemoryFabricImportV2) memoryfabricimportv2IsExportAllowed_DISPATCH(pMemoryFabricImportV2) +#define memoryfabricimportv2CheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memoryfabricimportv2CheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) +#define memoryfabricimportv2ShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memoryfabricimportv2ShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) +#define memoryfabricimportv2MapTo(pResource, pParams) memoryfabricimportv2MapTo_DISPATCH(pResource, pParams) +#define memoryfabricimportv2GetRefCount(pResource) memoryfabricimportv2GetRefCount_DISPATCH(pResource) +#define memoryfabricimportv2AddAdditionalDependants(pClient, pResource, pReference) memoryfabricimportv2AddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define memoryfabricimportv2Control_Prologue(pResource, pCallContext, pParams) memoryfabricimportv2Control_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportv2UnmapFrom(pResource, pParams) memoryfabricimportv2UnmapFrom_DISPATCH(pResource, pParams) +#define memoryfabricimportv2Control_Epilogue(pResource, pCallContext, pParams) memoryfabricimportv2Control_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportv2Unmap(pMemory, pCallContext, pCpuMapping) memoryfabricimportv2Unmap_DISPATCH(pMemory, pCallContext, pCpuMapping) +#define memoryfabricimportv2GetMemInterMapParams(pMemory, pParams) memoryfabricimportv2GetMemInterMapParams_DISPATCH(pMemory, pParams) +#define memoryfabricimportv2GetMemoryMappingDescriptor(pMemory, ppMemDesc) memoryfabricimportv2GetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) +#define memoryfabricimportv2ControlFilter(pResource, pCallContext, pParams) memoryfabricimportv2ControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportv2ControlSerialization_Prologue(pResource, pCallContext, pParams) memoryfabricimportv2ControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportv2IsPartialUnmapSupported(pResource) memoryfabricimportv2IsPartialUnmapSupported_DISPATCH(pResource) +#define memoryfabricimportv2CheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memoryfabricimportv2CheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) +#define memoryfabricimportv2PreDestruct(pResource) memoryfabricimportv2PreDestruct_DISPATCH(pResource) +#define memoryfabricimportv2IsDuplicate(pMemory, hMemory, pDuplicate) memoryfabricimportv2IsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) +#define memoryfabricimportv2ControlSerialization_Epilogue(pResource, pCallContext, pParams) memoryfabricimportv2ControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricimportv2Map(pMemory, pCallContext, pParams, pCpuMapping) memoryfabricimportv2Map_DISPATCH(pMemory, pCallContext, pParams, pCpuMapping) +#define memoryfabricimportv2AccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memoryfabricimportv2AccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NvBool memoryfabricimportv2CanCopy_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2); + +static inline NvBool memoryfabricimportv2CanCopy_DISPATCH(struct MemoryFabricImportV2 *pMemoryFabricImportV2) { + return pMemoryFabricImportV2->__memoryfabricimportv2CanCopy__(pMemoryFabricImportV2); +} + +NV_STATUS memoryfabricimportv2IsReady_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2, NvBool bCopyConstructorContext); + +static inline NV_STATUS memoryfabricimportv2IsReady_DISPATCH(struct MemoryFabricImportV2 *pMemoryFabricImportV2, NvBool bCopyConstructorContext) { + return pMemoryFabricImportV2->__memoryfabricimportv2IsReady__(pMemoryFabricImportV2, bCopyConstructorContext); +} + +NV_STATUS memoryfabricimportv2CopyConstruct_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS memoryfabricimportv2CopyConstruct_DISPATCH(struct MemoryFabricImportV2 *pMemoryFabricImportV2, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return pMemoryFabricImportV2->__memoryfabricimportv2CopyConstruct__(pMemoryFabricImportV2, pCallContext, pParams); +} + +NV_STATUS memoryfabricimportv2Control_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); + +static inline NV_STATUS memoryfabricimportv2Control_DISPATCH(struct MemoryFabricImportV2 *pMemoryFabricImportV2, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pMemoryFabricImportV2->__memoryfabricimportv2Control__(pMemoryFabricImportV2, pCallContext, pParams); +} + +NV_STATUS memoryfabricimportv2GetMapAddrSpace_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace); + +static inline NV_STATUS memoryfabricimportv2GetMapAddrSpace_DISPATCH(struct MemoryFabricImportV2 *pMemoryFabricImportV2, CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pMemoryFabricImportV2->__memoryfabricimportv2GetMapAddrSpace__(pMemoryFabricImportV2, pCallContext, mapFlags, pAddrSpace); +} + +NV_STATUS memoryfabricimportv2CtrlGetInfo_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2, NV00F9_CTRL_GET_INFO_PARAMS *pParams); + +static inline NV_STATUS memoryfabricimportv2CtrlGetInfo_DISPATCH(struct MemoryFabricImportV2 *pMemoryFabricImportV2, NV00F9_CTRL_GET_INFO_PARAMS *pParams) { + return pMemoryFabricImportV2->__memoryfabricimportv2CtrlGetInfo__(pMemoryFabricImportV2, pParams); +} + +NvBool memoryfabricimportv2IsGpuMapAllowed_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2, struct OBJGPU *pGpu); + +static inline NvBool memoryfabricimportv2IsGpuMapAllowed_DISPATCH(struct MemoryFabricImportV2 *pMemoryFabricImportV2, struct OBJGPU *pGpu) { + return pMemoryFabricImportV2->__memoryfabricimportv2IsGpuMapAllowed__(pMemoryFabricImportV2, pGpu); +} + +NvBool memoryfabricimportv2IsExportAllowed_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2); + +static inline NvBool memoryfabricimportv2IsExportAllowed_DISPATCH(struct MemoryFabricImportV2 *pMemoryFabricImportV2) { + return pMemoryFabricImportV2->__memoryfabricimportv2IsExportAllowed__(pMemoryFabricImportV2); +} + +static inline NV_STATUS memoryfabricimportv2CheckMemInterUnmap_DISPATCH(struct MemoryFabricImportV2 *pMemory, NvBool bSubdeviceHandleProvided) { + return pMemory->__memoryfabricimportv2CheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); +} + +static inline NvBool memoryfabricimportv2ShareCallback_DISPATCH(struct MemoryFabricImportV2 *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pResource->__memoryfabricimportv2ShareCallback__(pResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS memoryfabricimportv2MapTo_DISPATCH(struct MemoryFabricImportV2 *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__memoryfabricimportv2MapTo__(pResource, pParams); +} + +static inline NvU32 memoryfabricimportv2GetRefCount_DISPATCH(struct MemoryFabricImportV2 *pResource) { + return pResource->__memoryfabricimportv2GetRefCount__(pResource); +} + +static inline void memoryfabricimportv2AddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct MemoryFabricImportV2 *pResource, RsResourceRef *pReference) { + pResource->__memoryfabricimportv2AddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS memoryfabricimportv2Control_Prologue_DISPATCH(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricimportv2Control_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricimportv2UnmapFrom_DISPATCH(struct MemoryFabricImportV2 *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memoryfabricimportv2UnmapFrom__(pResource, pParams); +} + +static inline void memoryfabricimportv2Control_Epilogue_DISPATCH(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryfabricimportv2Control_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricimportv2Unmap_DISPATCH(struct MemoryFabricImportV2 *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { + return pMemory->__memoryfabricimportv2Unmap__(pMemory, pCallContext, pCpuMapping); +} + +static inline NV_STATUS memoryfabricimportv2GetMemInterMapParams_DISPATCH(struct MemoryFabricImportV2 *pMemory, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pMemory->__memoryfabricimportv2GetMemInterMapParams__(pMemory, pParams); +} + +static inline NV_STATUS memoryfabricimportv2GetMemoryMappingDescriptor_DISPATCH(struct MemoryFabricImportV2 *pMemory, MEMORY_DESCRIPTOR **ppMemDesc) { + return pMemory->__memoryfabricimportv2GetMemoryMappingDescriptor__(pMemory, ppMemDesc); +} + +static inline NV_STATUS memoryfabricimportv2ControlFilter_DISPATCH(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricimportv2ControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricimportv2ControlSerialization_Prologue_DISPATCH(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__memoryfabricimportv2ControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool memoryfabricimportv2IsPartialUnmapSupported_DISPATCH(struct MemoryFabricImportV2 *pResource) { + return pResource->__memoryfabricimportv2IsPartialUnmapSupported__(pResource); +} + +static inline NV_STATUS memoryfabricimportv2CheckCopyPermissions_DISPATCH(struct MemoryFabricImportV2 *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { + return pMemory->__memoryfabricimportv2CheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); +} + +static inline void memoryfabricimportv2PreDestruct_DISPATCH(struct MemoryFabricImportV2 *pResource) { + pResource->__memoryfabricimportv2PreDestruct__(pResource); +} + +static inline NV_STATUS memoryfabricimportv2IsDuplicate_DISPATCH(struct MemoryFabricImportV2 *pMemory, NvHandle hMemory, NvBool *pDuplicate) { + return pMemory->__memoryfabricimportv2IsDuplicate__(pMemory, hMemory, pDuplicate); +} + +static inline void memoryfabricimportv2ControlSerialization_Epilogue_DISPATCH(struct MemoryFabricImportV2 *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__memoryfabricimportv2ControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS memoryfabricimportv2Map_DISPATCH(struct MemoryFabricImportV2 *pMemory, CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { + return pMemory->__memoryfabricimportv2Map__(pMemory, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool memoryfabricimportv2AccessCallback_DISPATCH(struct MemoryFabricImportV2 *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__memoryfabricimportv2AccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS memoryfabricimportv2Construct_IMPL(struct MemoryFabricImportV2 *arg_pMemoryFabricImportV2, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_memoryfabricimportv2Construct(arg_pMemoryFabricImportV2, arg_pCallContext, arg_pParams) memoryfabricimportv2Construct_IMPL(arg_pMemoryFabricImportV2, arg_pCallContext, arg_pParams) +void memoryfabricimportv2Destruct_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2); + +#define __nvoc_memoryfabricimportv2Destruct(pMemoryFabricImportV2) memoryfabricimportv2Destruct_IMPL(pMemoryFabricImportV2) +void memoryfabricimportv2RemoveFromCache_IMPL(struct MemoryFabricImportV2 *pMemoryFabricImportV2); + +#ifdef __nvoc_mem_fabric_import_v2_h_disabled +static inline void memoryfabricimportv2RemoveFromCache(struct MemoryFabricImportV2 *pMemoryFabricImportV2) { + NV_ASSERT_FAILED_PRECOMP("MemoryFabricImportV2 was disabled!"); +} +#else //__nvoc_mem_fabric_import_v2_h_disabled +#define memoryfabricimportv2RemoveFromCache(pMemoryFabricImportV2) memoryfabricimportv2RemoveFromCache_IMPL(pMemoryFabricImportV2) +#endif //__nvoc_mem_fabric_import_v2_h_disabled + +#undef PRIVATE_FIELD + + +typedef struct +{ + NV_PHYSICAL_MEMORY_ATTRS physAttrs; + NvU32 memFlags; + NvU32 cliqueId; +} FABRIC_IMPORT_MEMDESC_DATA; + +// +// Gets (ref-counts) an import descriptor on which importDescriptorAttachMemDesc() +// is never called. +// +// importDescriptorPutNonBlocking() must be called to drop the ref-count. +// +MEM_FABRIC_IMPORT_DESCRIPTOR* importDescriptorGetUnused(const NvUuid *pExportUuid, + NvU16 index, NvU64 id); + +// +// importDescriptorPutNonBlocking() doesn't generate an unimport event, which +// further blocks the thread on the fabric manager to complete the unimport request. +// +// This function must be used by the code paths executed by the fabric manager, so +// that we don't block the fabric manager thread. +// +void importDescriptorPutNonBlocking(MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc); + +// Installs a memdesc to an import descriptor. A NULL memdesc is acceptable. +NV_STATUS importDescriptorInstallMemDesc(MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc, + MEMORY_DESCRIPTOR *pMemDesc); + +#endif /* _MEMORYFABRICIMPORTV2_H_ */ + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_MEM_FABRIC_IMPORT_V2_NVOC_H_ diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.c b/src/nvidia/generated/g_mem_fabric_nvoc.c index c00913898c..9c40e26e12 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_fabric_nvoc.c @@ -145,10 +145,6 @@ static void __nvoc_thunk_RmResource_memoryfabricControl_Epilogue(struct MemoryFa rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memoryfabricControlLookup(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_memoryfabricUnmap(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), pCallContext, pCpuMapping); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_memoryfabricControlSerialization_Prolog return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_memoryfabricIsPartialUnmapSupported(struct MemoryFabric *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryFabric_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_memoryfabricIsReady(struct MemoryFabric *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryFabric_Memory.offset), bCopyConstructorContext); } @@ -410,8 +410,6 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memoryfabricControl_Epilogue; - pThis->__memoryfabricControlLookup__ = &__nvoc_thunk_RsResource_memoryfabricControlLookup; - pThis->__memoryfabricUnmap__ = &__nvoc_thunk_Memory_memoryfabricUnmap; pThis->__memoryfabricGetMemInterMapParams__ = &__nvoc_thunk_Memory_memoryfabricGetMemInterMapParams; @@ -422,6 +420,8 @@ static void __nvoc_init_funcTable_MemoryFabric_1(MemoryFabric *pThis) { pThis->__memoryfabricControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memoryfabricControlSerialization_Prologue; + pThis->__memoryfabricIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_memoryfabricIsPartialUnmapSupported; + pThis->__memoryfabricIsReady__ = &__nvoc_thunk_Memory_memoryfabricIsReady; pThis->__memoryfabricCheckCopyPermissions__ = &__nvoc_thunk_Memory_memoryfabricCheckCopyPermissions; @@ -453,21 +453,26 @@ void __nvoc_init_MemoryFabric(MemoryFabric *pThis) { __nvoc_init_funcTable_MemoryFabric(pThis); } -NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MemoryFabric *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryFabric), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MemoryFabric)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryFabric); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -482,16 +487,25 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric **ppThis, Dynamic *pParent, status = __nvoc_ctor_MemoryFabric(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MemoryFabric_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MemoryFabric_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MemoryFabric)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mem_fabric_nvoc.h b/src/nvidia/generated/g_mem_fabric_nvoc.h index 52a5e4a895..5a98afa2c7 100644 --- a/src/nvidia/generated/g_mem_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_fabric_nvoc.h @@ -52,11 +52,16 @@ extern "C" { // Type Definitions // **************************************************************************** + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MEM_FABRIC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MemoryFabric { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -87,12 +92,12 @@ struct MemoryFabric { NvBool (*__memoryfabricIsGpuMapAllowed__)(struct MemoryFabric *, struct OBJGPU *); NV_STATUS (*__memoryfabricUnmapFrom__)(struct MemoryFabric *, RS_RES_UNMAP_FROM_PARAMS *); void (*__memoryfabricControl_Epilogue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memoryfabricControlLookup__)(struct MemoryFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__memoryfabricUnmap__)(struct MemoryFabric *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__memoryfabricGetMemInterMapParams__)(struct MemoryFabric *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memoryfabricGetMemoryMappingDescriptor__)(struct MemoryFabric *, MEMORY_DESCRIPTOR **); NV_STATUS (*__memoryfabricControlFilter__)(struct MemoryFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memoryfabricControlSerialization_Prologue__)(struct MemoryFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memoryfabricIsPartialUnmapSupported__)(struct MemoryFabric *); NV_STATUS (*__memoryfabricIsReady__)(struct MemoryFabric *, NvBool); NV_STATUS (*__memoryfabricCheckCopyPermissions__)(struct MemoryFabric *, struct OBJGPU *, struct Device *); void (*__memoryfabricPreDestruct__)(struct MemoryFabric *); @@ -151,12 +156,12 @@ NV_STATUS __nvoc_objCreate_MemoryFabric(MemoryFabric**, Dynamic*, NvU32, CALL_CO #define memoryfabricIsGpuMapAllowed(pMemory, pGpu) memoryfabricIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define memoryfabricUnmapFrom(pResource, pParams) memoryfabricUnmapFrom_DISPATCH(pResource, pParams) #define memoryfabricControl_Epilogue(pResource, pCallContext, pParams) memoryfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memoryfabricControlLookup(pResource, pParams, ppEntry) memoryfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memoryfabricUnmap(pMemory, pCallContext, pCpuMapping) memoryfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define memoryfabricGetMemInterMapParams(pMemory, pParams) memoryfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memoryfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memoryfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define memoryfabricControlFilter(pResource, pCallContext, pParams) memoryfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memoryfabricControlSerialization_Prologue(pResource, pCallContext, pParams) memoryfabricControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memoryfabricIsPartialUnmapSupported(pResource) memoryfabricIsPartialUnmapSupported_DISPATCH(pResource) #define memoryfabricIsReady(pMemory, bCopyConstructorContext) memoryfabricIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define memoryfabricCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memoryfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memoryfabricPreDestruct(pResource) memoryfabricPreDestruct_DISPATCH(pResource) @@ -268,10 +273,6 @@ static inline void memoryfabricControl_Epilogue_DISPATCH(struct MemoryFabric *pR pResource->__memoryfabricControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memoryfabricControlLookup_DISPATCH(struct MemoryFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memoryfabricControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS memoryfabricUnmap_DISPATCH(struct MemoryFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pMemory->__memoryfabricUnmap__(pMemory, pCallContext, pCpuMapping); } @@ -292,6 +293,10 @@ static inline NV_STATUS memoryfabricControlSerialization_Prologue_DISPATCH(struc return pResource->__memoryfabricControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool memoryfabricIsPartialUnmapSupported_DISPATCH(struct MemoryFabric *pResource) { + return pResource->__memoryfabricIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS memoryfabricIsReady_DISPATCH(struct MemoryFabric *pMemory, NvBool bCopyConstructorContext) { return pMemory->__memoryfabricIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_mem_list_nvoc.c b/src/nvidia/generated/g_mem_list_nvoc.c index 5f0f55766d..bc8e50f32e 100644 --- a/src/nvidia/generated/g_mem_list_nvoc.c +++ b/src/nvidia/generated/g_mem_list_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_memlistControl_Epilogue(struct MemoryList *p rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memlistControlLookup(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_memlistControl(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_memlistControlSerialization_Prologue(st return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_memlistIsPartialUnmapSupported(struct MemoryList *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryList_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_memlistIsReady(struct MemoryList *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryList_Memory.offset), bCopyConstructorContext); } @@ -261,8 +261,6 @@ static void __nvoc_init_funcTable_MemoryList_1(MemoryList *pThis) { pThis->__memlistControl_Epilogue__ = &__nvoc_thunk_RmResource_memlistControl_Epilogue; - pThis->__memlistControlLookup__ = &__nvoc_thunk_RsResource_memlistControlLookup; - pThis->__memlistControl__ = &__nvoc_thunk_Memory_memlistControl; pThis->__memlistUnmap__ = &__nvoc_thunk_Memory_memlistUnmap; @@ -275,6 +273,8 @@ static void __nvoc_init_funcTable_MemoryList_1(MemoryList *pThis) { pThis->__memlistControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memlistControlSerialization_Prologue; + pThis->__memlistIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_memlistIsPartialUnmapSupported; + pThis->__memlistIsReady__ = &__nvoc_thunk_Memory_memlistIsReady; pThis->__memlistCheckCopyPermissions__ = &__nvoc_thunk_Memory_memlistCheckCopyPermissions; @@ -306,21 +306,26 @@ void __nvoc_init_MemoryList(MemoryList *pThis) { __nvoc_init_funcTable_MemoryList(pThis); } -NV_STATUS __nvoc_objCreate_MemoryList(MemoryList **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MemoryList(MemoryList **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MemoryList *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryList), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MemoryList)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryList); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -335,16 +340,25 @@ NV_STATUS __nvoc_objCreate_MemoryList(MemoryList **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_MemoryList(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MemoryList_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MemoryList_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MemoryList)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mem_list_nvoc.h b/src/nvidia/generated/g_mem_list_nvoc.h index 551ed16cfc..290a17fd33 100644 --- a/src/nvidia/generated/g_mem_list_nvoc.h +++ b/src/nvidia/generated/g_mem_list_nvoc.h @@ -40,11 +40,16 @@ extern "C" { * These classes are used by the vGPU support to create memory objects for memory * assigned to a guest VM. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MEM_LIST_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MemoryList { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -66,13 +71,13 @@ struct MemoryList { NvBool (*__memlistIsGpuMapAllowed__)(struct MemoryList *, struct OBJGPU *); NV_STATUS (*__memlistUnmapFrom__)(struct MemoryList *, RS_RES_UNMAP_FROM_PARAMS *); void (*__memlistControl_Epilogue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memlistControlLookup__)(struct MemoryList *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__memlistControl__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistUnmap__)(struct MemoryList *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__memlistGetMemInterMapParams__)(struct MemoryList *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memlistGetMemoryMappingDescriptor__)(struct MemoryList *, MEMORY_DESCRIPTOR **); NV_STATUS (*__memlistControlFilter__)(struct MemoryList *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memlistControlSerialization_Prologue__)(struct MemoryList *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memlistIsPartialUnmapSupported__)(struct MemoryList *); NV_STATUS (*__memlistIsReady__)(struct MemoryList *, NvBool); NV_STATUS (*__memlistCheckCopyPermissions__)(struct MemoryList *, struct OBJGPU *, struct Device *); void (*__memlistPreDestruct__)(struct MemoryList *); @@ -122,13 +127,13 @@ NV_STATUS __nvoc_objCreate_MemoryList(MemoryList**, Dynamic*, NvU32, CALL_CONTEX #define memlistIsGpuMapAllowed(pMemory, pGpu) memlistIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define memlistUnmapFrom(pResource, pParams) memlistUnmapFrom_DISPATCH(pResource, pParams) #define memlistControl_Epilogue(pResource, pCallContext, pParams) memlistControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memlistControlLookup(pResource, pParams, ppEntry) memlistControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memlistControl(pMemory, pCallContext, pParams) memlistControl_DISPATCH(pMemory, pCallContext, pParams) #define memlistUnmap(pMemory, pCallContext, pCpuMapping) memlistUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define memlistGetMemInterMapParams(pMemory, pParams) memlistGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memlistGetMemoryMappingDescriptor(pMemory, ppMemDesc) memlistGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define memlistControlFilter(pResource, pCallContext, pParams) memlistControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memlistControlSerialization_Prologue(pResource, pCallContext, pParams) memlistControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memlistIsPartialUnmapSupported(pResource) memlistIsPartialUnmapSupported_DISPATCH(pResource) #define memlistIsReady(pMemory, bCopyConstructorContext) memlistIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define memlistCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memlistCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memlistPreDestruct(pResource) memlistPreDestruct_DISPATCH(pResource) @@ -186,10 +191,6 @@ static inline void memlistControl_Epilogue_DISPATCH(struct MemoryList *pResource pResource->__memlistControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memlistControlLookup_DISPATCH(struct MemoryList *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memlistControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS memlistControl_DISPATCH(struct MemoryList *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__memlistControl__(pMemory, pCallContext, pParams); } @@ -214,6 +215,10 @@ static inline NV_STATUS memlistControlSerialization_Prologue_DISPATCH(struct Mem return pResource->__memlistControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool memlistIsPartialUnmapSupported_DISPATCH(struct MemoryList *pResource) { + return pResource->__memlistIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS memlistIsReady_DISPATCH(struct MemoryList *pMemory, NvBool bCopyConstructorContext) { return pMemory->__memlistIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_mem_mapper_nvoc.c b/src/nvidia/generated/g_mem_mapper_nvoc.c index 791d408b3c..575a46f55a 100644 --- a/src/nvidia/generated/g_mem_mapper_nvoc.c +++ b/src/nvidia/generated/g_mem_mapper_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_memmapperControl_Epilogue(struct MemoryMappe rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memmapperControlLookup(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle(struct MemoryMapper *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MemoryMapper_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_memmapperCanCopy(struct MemoryMapper *pRes return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_memmapperIsPartialUnmapSupported(struct MemoryMapper *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_memmapperPreDestruct(struct MemoryMapper *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMapper_RsResource.offset)); } @@ -203,15 +203,15 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMa #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) memmapperCtrlCmdSubmitPagingOperations_IMPL, + /*pFunc=*/ (void (*)(void)) memmapperCtrlCmdSubmitOperations_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, /*accessRight=*/0x0u, - /*methodId=*/ 0xfe0002u, - /*paramSize=*/ sizeof(NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS), + /*methodId=*/ 0xfe0101u, + /*paramSize=*/ sizeof(NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_MemoryMapper.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "memmapperCtrlCmdSubmitPagingOperations" + /*func=*/ "memmapperCtrlCmdSubmitOperations" #endif }, @@ -225,6 +225,7 @@ const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryMapper = void __nvoc_dtor_GpuResource(GpuResource*); void __nvoc_dtor_MemoryMapper(MemoryMapper *pThis) { + __nvoc_memmapperDestruct(pThis); __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); PORT_UNREFERENCED_VARIABLE(pThis); } @@ -256,7 +257,7 @@ static void __nvoc_init_funcTable_MemoryMapper_1(MemoryMapper *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__memmapperCtrlCmdSubmitPagingOperations__ = &memmapperCtrlCmdSubmitPagingOperations_IMPL; + pThis->__memmapperCtrlCmdSubmitOperations__ = &memmapperCtrlCmdSubmitOperations_IMPL; #endif pThis->__memmapperShareCallback__ = &__nvoc_thunk_GpuResource_memmapperShareCallback; @@ -281,8 +282,6 @@ static void __nvoc_init_funcTable_MemoryMapper_1(MemoryMapper *pThis) { pThis->__memmapperControl_Epilogue__ = &__nvoc_thunk_RmResource_memmapperControl_Epilogue; - pThis->__memmapperControlLookup__ = &__nvoc_thunk_RsResource_memmapperControlLookup; - pThis->__memmapperGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_memmapperGetInternalObjectHandle; pThis->__memmapperControl__ = &__nvoc_thunk_GpuResource_memmapperControl; @@ -299,6 +298,8 @@ static void __nvoc_init_funcTable_MemoryMapper_1(MemoryMapper *pThis) { pThis->__memmapperCanCopy__ = &__nvoc_thunk_RsResource_memmapperCanCopy; + pThis->__memmapperIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_memmapperIsPartialUnmapSupported; + pThis->__memmapperPreDestruct__ = &__nvoc_thunk_RsResource_memmapperPreDestruct; pThis->__memmapperIsDuplicate__ = &__nvoc_thunk_RsResource_memmapperIsDuplicate; @@ -326,21 +327,26 @@ void __nvoc_init_MemoryMapper(MemoryMapper *pThis) { __nvoc_init_funcTable_MemoryMapper(pThis); } -NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MemoryMapper *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryMapper), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MemoryMapper)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryMapper); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -355,16 +361,25 @@ NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper **ppThis, Dynamic *pParent, status = __nvoc_ctor_MemoryMapper(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MemoryMapper_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MemoryMapper_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MemoryMapper)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mem_mapper_nvoc.h b/src/nvidia/generated/g_mem_mapper_nvoc.h index fb685ab021..72c712595e 100644 --- a/src/nvidia/generated/g_mem_mapper_nvoc.h +++ b/src/nvidia/generated/g_mem_mapper_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -41,6 +41,7 @@ extern "C" { #include "class/cl00fe.h" #include "ctrl/ctrl00fe.h" +#include "ctrl/ctrl2080/ctrl2080fb.h" struct Subdevice; @@ -66,15 +67,52 @@ typedef struct OBJGPU OBJGPU; #endif /* __nvoc_class_id_OBJGPU */ +struct SemaphoreSurface; + +#ifndef __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +#define __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ +typedef struct SemaphoreSurface SemaphoreSurface; +#endif /* __NVOC_CLASS_SemaphoreSurface_TYPEDEF__ */ + +#ifndef __nvoc_class_id_SemaphoreSurface +#define __nvoc_class_id_SemaphoreSurface 0xeabc69 +#endif /* __nvoc_class_id_SemaphoreSurface */ + + +struct MemoryMapper; + +#ifndef __NVOC_CLASS_MemoryMapper_TYPEDEF__ +#define __NVOC_CLASS_MemoryMapper_TYPEDEF__ +typedef struct MemoryMapper MemoryMapper; +#endif /* __NVOC_CLASS_MemoryMapper_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryMapper +#define __nvoc_class_id_MemoryMapper 0xb8e4a2 +#endif /* __nvoc_class_id_MemoryMapper */ + + + +// MemoryMapper can't wait for workers to finish in destructor due to locking constraints +// Instead set pMemoryMapper to NULL and leave the params structure until all workers are done +typedef struct +{ + struct MemoryMapper *pMemoryMapper; + NvU32 numRefs; +} MemoryMapperWorkerParams; /*! * MemoryMapper provides paging operations channel interface to userspace clients. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MEM_MAPPER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MemoryMapper { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -84,7 +122,7 @@ struct MemoryMapper { struct RmResource *__nvoc_pbase_RmResource; struct GpuResource *__nvoc_pbase_GpuResource; struct MemoryMapper *__nvoc_pbase_MemoryMapper; - NV_STATUS (*__memmapperCtrlCmdSubmitPagingOperations__)(struct MemoryMapper *, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *); + NV_STATUS (*__memmapperCtrlCmdSubmitOperations__)(struct MemoryMapper *, NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS *); NvBool (*__memmapperShareCallback__)(struct MemoryMapper *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memmapperCheckMemInterUnmap__)(struct MemoryMapper *, NvBool); NV_STATUS (*__memmapperMapTo__)(struct MemoryMapper *, RS_RES_MAP_TO_PARAMS *); @@ -96,7 +134,6 @@ struct MemoryMapper { NV_STATUS (*__memmapperInternalControlForward__)(struct MemoryMapper *, NvU32, void *, NvU32); NV_STATUS (*__memmapperUnmapFrom__)(struct MemoryMapper *, RS_RES_UNMAP_FROM_PARAMS *); void (*__memmapperControl_Epilogue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memmapperControlLookup__)(struct MemoryMapper *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__memmapperGetInternalObjectHandle__)(struct MemoryMapper *); NV_STATUS (*__memmapperControl__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memmapperUnmap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -105,12 +142,22 @@ struct MemoryMapper { NV_STATUS (*__memmapperControlFilter__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memmapperControlSerialization_Prologue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memmapperCanCopy__)(struct MemoryMapper *); + NvBool (*__memmapperIsPartialUnmapSupported__)(struct MemoryMapper *); void (*__memmapperPreDestruct__)(struct MemoryMapper *); NV_STATUS (*__memmapperIsDuplicate__)(struct MemoryMapper *, NvHandle, NvBool *); void (*__memmapperControlSerialization_Epilogue__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memmapperMap__)(struct MemoryMapper *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); NvBool (*__memmapperAccessCallback__)(struct MemoryMapper *, struct RsClient *, void *, RsAccessRight); - struct Subdevice *pSubDevice; + struct Subdevice *pSubdevice; + NV00FE_CTRL_OPERATION *pOperationQueue; + NvU32 operationQueuePut; + NvU32 operationQueueGet; + NvU32 operationQueueLen; + NvHandle hInternalSemaphoreSurface; + NVOS10_EVENT_KERNEL_CALLBACK_EX semaphoreCallback; + MemoryMapperWorkerParams *pWorkerParams; + struct SemaphoreSurface *pSemSurf; + NvBool bError; }; #ifndef __NVOC_CLASS_MemoryMapper_TYPEDEF__ @@ -141,7 +188,7 @@ NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper**, Dynamic*, NvU32, struct #define __objCreate_MemoryMapper(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_MemoryMapper((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) -#define memmapperCtrlCmdSubmitPagingOperations(pMemoryMapper, pParams) memmapperCtrlCmdSubmitPagingOperations_DISPATCH(pMemoryMapper, pParams) +#define memmapperCtrlCmdSubmitOperations(pMemoryMapper, pParams) memmapperCtrlCmdSubmitOperations_DISPATCH(pMemoryMapper, pParams) #define memmapperShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) memmapperShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define memmapperCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) memmapperCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define memmapperMapTo(pResource, pParams) memmapperMapTo_DISPATCH(pResource, pParams) @@ -153,7 +200,6 @@ NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper**, Dynamic*, NvU32, struct #define memmapperInternalControlForward(pGpuResource, command, pParams, size) memmapperInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define memmapperUnmapFrom(pResource, pParams) memmapperUnmapFrom_DISPATCH(pResource, pParams) #define memmapperControl_Epilogue(pResource, pCallContext, pParams) memmapperControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memmapperControlLookup(pResource, pParams, ppEntry) memmapperControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memmapperGetInternalObjectHandle(pGpuResource) memmapperGetInternalObjectHandle_DISPATCH(pGpuResource) #define memmapperControl(pGpuResource, pCallContext, pParams) memmapperControl_DISPATCH(pGpuResource, pCallContext, pParams) #define memmapperUnmap(pGpuResource, pCallContext, pCpuMapping) memmapperUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -162,15 +208,16 @@ NV_STATUS __nvoc_objCreate_MemoryMapper(MemoryMapper**, Dynamic*, NvU32, struct #define memmapperControlFilter(pResource, pCallContext, pParams) memmapperControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memmapperControlSerialization_Prologue(pResource, pCallContext, pParams) memmapperControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memmapperCanCopy(pResource) memmapperCanCopy_DISPATCH(pResource) +#define memmapperIsPartialUnmapSupported(pResource) memmapperIsPartialUnmapSupported_DISPATCH(pResource) #define memmapperPreDestruct(pResource) memmapperPreDestruct_DISPATCH(pResource) #define memmapperIsDuplicate(pResource, hMemory, pDuplicate) memmapperIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define memmapperControlSerialization_Epilogue(pResource, pCallContext, pParams) memmapperControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memmapperMap(pGpuResource, pCallContext, pParams, pCpuMapping) memmapperMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define memmapperAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memmapperAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS memmapperCtrlCmdSubmitPagingOperations_IMPL(struct MemoryMapper *pMemoryMapper, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *pParams); +NV_STATUS memmapperCtrlCmdSubmitOperations_IMPL(struct MemoryMapper *pMemoryMapper, NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS *pParams); -static inline NV_STATUS memmapperCtrlCmdSubmitPagingOperations_DISPATCH(struct MemoryMapper *pMemoryMapper, NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *pParams) { - return pMemoryMapper->__memmapperCtrlCmdSubmitPagingOperations__(pMemoryMapper, pParams); +static inline NV_STATUS memmapperCtrlCmdSubmitOperations_DISPATCH(struct MemoryMapper *pMemoryMapper, NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS *pParams) { + return pMemoryMapper->__memmapperCtrlCmdSubmitOperations__(pMemoryMapper, pParams); } static inline NvBool memmapperShareCallback_DISPATCH(struct MemoryMapper *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -217,10 +264,6 @@ static inline void memmapperControl_Epilogue_DISPATCH(struct MemoryMapper *pReso pResource->__memmapperControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memmapperControlLookup_DISPATCH(struct MemoryMapper *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memmapperControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle memmapperGetInternalObjectHandle_DISPATCH(struct MemoryMapper *pGpuResource) { return pGpuResource->__memmapperGetInternalObjectHandle__(pGpuResource); } @@ -253,6 +296,10 @@ static inline NvBool memmapperCanCopy_DISPATCH(struct MemoryMapper *pResource) { return pResource->__memmapperCanCopy__(pResource); } +static inline NvBool memmapperIsPartialUnmapSupported_DISPATCH(struct MemoryMapper *pResource) { + return pResource->__memmapperIsPartialUnmapSupported__(pResource); +} + static inline void memmapperPreDestruct_DISPATCH(struct MemoryMapper *pResource) { pResource->__memmapperPreDestruct__(pResource); } @@ -276,6 +323,9 @@ static inline NvBool memmapperAccessCallback_DISPATCH(struct MemoryMapper *pReso NV_STATUS memmapperConstruct_IMPL(struct MemoryMapper *arg_pMemoryMapper, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); #define __nvoc_memmapperConstruct(arg_pMemoryMapper, arg_pCallContext, arg_pParams) memmapperConstruct_IMPL(arg_pMemoryMapper, arg_pCallContext, arg_pParams) +void memmapperDestruct_IMPL(struct MemoryMapper *pMemoryMapper); + +#define __nvoc_memmapperDestruct(pMemoryMapper) memmapperDestruct_IMPL(pMemoryMapper) #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.c b/src/nvidia/generated/g_mem_mgr_nvoc.c index d106e2cef3..ffaa81da17 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.c +++ b/src/nvidia/generated/g_mem_mgr_nvoc.c @@ -283,12 +283,6 @@ void __nvoc_init_dataField_MemoryManager(MemoryManager *pThis, RmHalspecOwner *p { pThis->bGenericKindSupport = ((NvBool)(0 == 0)); } - - // Hal field -- bLocalizedMemPoolEnabled - // default - { - pThis->bLocalizedMemPoolEnabled = ((NvBool)(0 != 0)); - } } NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* ); @@ -333,6 +327,16 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrStateDestroy__ = &memmgrStateDestroy_IMPL; + // Hal function -- memmgrAllocateConsoleRegion + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_56cd7a; + } + else + { + pThis->__memmgrAllocateConsoleRegion__ = &memmgrAllocateConsoleRegion_IMPL; + } + // Hal function -- memmgrMemUtilsSec2CtxInit if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -378,6 +382,16 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrGetMaxContextSize__ = &memmgrGetMaxContextSize_GA100; } + // Hal function -- memmgrGetFbTaxSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrGetFbTaxSize__ = &memmgrGetFbTaxSize_VGPUSTUB; + } + else + { + pThis->__memmgrGetFbTaxSize__ = &memmgrGetFbTaxSize_4a4dee; + } + // Hal function -- memmgrScrubRegistryOverrides if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -428,15 +442,15 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrGetFlaKind__ = &memmgrGetFlaKind_GA100; } - // Hal function -- memmgrIsApertureSupportedByFla + // Hal function -- memmgrIsMemDescSupportedByFla if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x11f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 | GH100 */ { - pThis->__memmgrIsApertureSupportedByFla__ = &memmgrIsApertureSupportedByFla_GA100; + pThis->__memmgrIsMemDescSupportedByFla__ = &memmgrIsMemDescSupportedByFla_GA100; } // default else { - pThis->__memmgrIsApertureSupportedByFla__ = &memmgrIsApertureSupportedByFla_46f6a7; + pThis->__memmgrIsMemDescSupportedByFla__ = &memmgrIsMemDescSupportedByFla_46f6a7; } // Hal function -- memmgrDetermineComptag @@ -449,6 +463,36 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrDetermineComptag__ = &memmgrDetermineComptag_13cd8d; } + // Hal function -- memmgrGetGrHeapReservationSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrGetGrHeapReservationSize__ = &memmgrGetGrHeapReservationSize_VGPUSTUB; + } + else + { + pThis->__memmgrGetGrHeapReservationSize__ = &memmgrGetGrHeapReservationSize_4a4dee; + } + + // Hal function -- memmgrGetRunlistEntriesReservedFbSpace + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrGetRunlistEntriesReservedFbSpace__ = &memmgrGetRunlistEntriesReservedFbSpace_4a4dee; + } + else + { + pThis->__memmgrGetRunlistEntriesReservedFbSpace__ = &memmgrGetRunlistEntriesReservedFbSpace_GM107; + } + + // Hal function -- memmgrGetUserdReservedFbSpace + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrGetUserdReservedFbSpace__ = &memmgrGetUserdReservedFbSpace_4a4dee; + } + else + { + pThis->__memmgrGetUserdReservedFbSpace__ = &memmgrGetUserdReservedFbSpace_GM107; + } + // Hal function -- memmgrCheckReservedMemorySize if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -490,6 +534,16 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrInsertUnprotectedRegionAtBottomOfFb__ = &memmgrInsertUnprotectedRegionAtBottomOfFb_56cd7a; } + // Hal function -- memmgrInitBaseFbRegions + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrInitBaseFbRegions__ = &memmgrInitBaseFbRegions_VGPUSTUB; + } + else + { + pThis->__memmgrInitBaseFbRegions__ = &memmgrInitBaseFbRegions_FWCLIENT; + } + // Hal function -- memmgrGetDisablePlcKind if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -514,6 +568,27 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrEnableDynamicPageOfflining__ = &memmgrEnableDynamicPageOfflining_GA102; } + // Hal function -- memmgrSetPartitionableMem + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrSetPartitionableMem__ = &memmgrSetPartitionableMem_56cd7a; + } + else + { + // default + pThis->__memmgrSetPartitionableMem__ = &memmgrSetPartitionableMem_IMPL; + } + + // Hal function -- memmgrAllocMIGGPUInstanceMemory + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrAllocMIGGPUInstanceMemory__ = &memmgrAllocMIGGPUInstanceMemory_VF; + } + else + { + pThis->__memmgrAllocMIGGPUInstanceMemory__ = &memmgrAllocMIGGPUInstanceMemory_PF; + } + // Hal function -- memmgrGetBlackListPages if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ { @@ -524,6 +599,27 @@ static void __nvoc_init_funcTable_MemoryManager_1(MemoryManager *pThis, RmHalspe pThis->__memmgrGetBlackListPages__ = &memmgrGetBlackListPages_GA100; } + // Hal function -- memmgrDiscoverMIGPartitionableMemoryRange + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__memmgrDiscoverMIGPartitionableMemoryRange__ = &memmgrDiscoverMIGPartitionableMemoryRange_VF; + } + else + { + pThis->__memmgrDiscoverMIGPartitionableMemoryRange__ = &memmgrDiscoverMIGPartitionableMemoryRange_46f6a7; + } + + // Hal function -- memmgrValidateFBEndReservation + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__memmgrValidateFBEndReservation__ = &memmgrValidateFBEndReservation_PF; + } + // default + else + { + pThis->__memmgrValidateFBEndReservation__ = &memmgrValidateFBEndReservation_56cd7a; + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_MemoryManager_engstateConstructEngine; pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_thunk_MemoryManager_engstateStatePreInitLocked; @@ -566,23 +662,31 @@ void __nvoc_init_MemoryManager(MemoryManager *pThis, RmHalspecOwner *pRmhalspeco __nvoc_init_funcTable_MemoryManager(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MemoryManager *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryManager), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MemoryManager)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryManager); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -600,16 +704,25 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager **ppThis, Dynamic *pParen status = __nvoc_ctor_MemoryManager(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_MemoryManager_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MemoryManager_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MemoryManager)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mem_mgr_nvoc.h b/src/nvidia/generated/g_mem_mgr_nvoc.h index 9a44e84f6e..e038a66e12 100644 --- a/src/nvidia/generated/g_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_mem_mgr_nvoc.h @@ -35,7 +35,6 @@ extern "C" { #define MEM_MGR_H #include "core/core.h" -#include "core/info_block.h" #include "gpu/eng_state.h" #include "gpu/mem_mgr/fbsr.h" @@ -98,6 +97,8 @@ typedef enum #define TRANSFER_FLAGS_MAP_PROTECT_READABLE NVBIT32(8) // Transfer is only reading data #define TRANSFER_FLAGS_MAP_PROTECT_WRITEABLE NVBIT32(9) // Transfer is only writing data +#define TRANSFER_FLAGS_PREFER_PROCESSOR NVBIT32(10) // Use BAR1/2 if possible + typedef struct { NvU32 bar1Size; @@ -428,11 +429,16 @@ typedef struct _def_fb_mem_node #define MEM_MGR_STUB_ORIN(...) + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MEM_MGR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RM_POOL_ALLOC_MEM_RESERVE_INFO; struct __nvoc_inner_struc_MemoryManager_1__ { @@ -481,24 +487,34 @@ struct MemoryManager { NV_STATUS (*__memmgrStatePreUnload__)(OBJGPU *, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStateUnload__)(OBJGPU *, struct MemoryManager *, NvU32); void (*__memmgrStateDestroy__)(OBJGPU *, struct MemoryManager *); + NV_STATUS (*__memmgrAllocateConsoleRegion__)(OBJGPU *, struct MemoryManager *, FB_REGION_DESCRIPTOR *); NV_STATUS (*__memmgrMemUtilsSec2CtxInit__)(OBJGPU *, struct MemoryManager *, OBJCHANNEL *); NvBool (*__memmgrMemUtilsCheckMemoryFastScrubEnable__)(OBJGPU *, struct MemoryManager *, NvU32, NvBool, RmPhysAddr, NvU32, NV_ADDRESS_SPACE); NV_STATUS (*__memmgrAllocDetermineAlignment__)(OBJGPU *, struct MemoryManager *, NvU64 *, NvU64 *, NvU64, NvU32, NvU32, NvU32, NvU64); NvU64 (*__memmgrGetMaxContextSize__)(OBJGPU *, struct MemoryManager *); + NvU64 (*__memmgrGetFbTaxSize__)(OBJGPU *, struct MemoryManager *); void (*__memmgrScrubRegistryOverrides__)(OBJGPU *, struct MemoryManager *); NvU32 (*__memmgrGetPteKindBl__)(OBJGPU *, struct MemoryManager *); NvU32 (*__memmgrGetPteKindPitch__)(OBJGPU *, struct MemoryManager *); NvU32 (*__memmgrChooseKindCompressC__)(OBJGPU *, struct MemoryManager *, FB_ALLOC_PAGE_FORMAT *); NV_STATUS (*__memmgrGetFlaKind__)(OBJGPU *, struct MemoryManager *, NvU32 *); - NvBool (*__memmgrIsApertureSupportedByFla__)(OBJGPU *, struct MemoryManager *, NV_ADDRESS_SPACE); + NvBool (*__memmgrIsMemDescSupportedByFla__)(OBJGPU *, struct MemoryManager *, MEMORY_DESCRIPTOR *); NvU32 (*__memmgrDetermineComptag__)(OBJGPU *, struct MemoryManager *, RmPhysAddr); + NvU32 (*__memmgrGetGrHeapReservationSize__)(OBJGPU *, struct MemoryManager *); + NvU32 (*__memmgrGetRunlistEntriesReservedFbSpace__)(OBJGPU *, struct MemoryManager *); + NvU32 (*__memmgrGetUserdReservedFbSpace__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrCheckReservedMemorySize__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrReadMmuLock__)(OBJGPU *, struct MemoryManager *, NvBool *, NvU64 *, NvU64 *); NV_STATUS (*__memmgrBlockMemLockedMemory__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrInsertUnprotectedRegionAtBottomOfFb__)(OBJGPU *, struct MemoryManager *, NvU64 *); + NV_STATUS (*__memmgrInitBaseFbRegions__)(OBJGPU *, struct MemoryManager *); void (*__memmgrGetDisablePlcKind__)(struct MemoryManager *, NvU32 *); void (*__memmgrEnableDynamicPageOfflining__)(OBJGPU *, struct MemoryManager *); + NV_STATUS (*__memmgrSetPartitionableMem__)(OBJGPU *, struct MemoryManager *); + NV_STATUS (*__memmgrAllocMIGGPUInstanceMemory__)(OBJGPU *, struct MemoryManager *, NvU32, NvHandle *, struct NV_RANGE *, struct Heap **); NV_STATUS (*__memmgrGetBlackListPages__)(OBJGPU *, struct MemoryManager *, BLACKLIST_ADDRESS *, NvU32 *); + NV_STATUS (*__memmgrDiscoverMIGPartitionableMemoryRange__)(OBJGPU *, struct MemoryManager *, struct NV_RANGE *); + NV_STATUS (*__memmgrValidateFBEndReservation__)(OBJGPU *, struct MemoryManager *); NV_STATUS (*__memmgrStatePreLoad__)(POBJGPU, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStatePostUnload__)(POBJGPU, struct MemoryManager *, NvU32); NV_STATUS (*__memmgrStateInitUnlocked__)(POBJGPU, struct MemoryManager *); @@ -511,7 +527,6 @@ struct MemoryManager { NvBool bPmaEnabled; NvBool bPmaInitialized; NvBool bPmaForcePersistence; - NvBool bPmaAddrTree; NvBool bClientPageTablesPmaManaged; NvBool bScanoutSysmem; NvBool bMixedDensityFbp; @@ -547,6 +562,7 @@ struct MemoryManager { NvBool bFastScrubberEnabled; NvBool bDisableAsyncScrubforMods; NvBool bUseVasForCeMemoryOps; + NvBool bCePhysicalVidmemAccessNotSupported; NvBool bRmExecutingEccScrub; NvBool bBug1441072EccScrubWar; NvU64 heapStartOffset; @@ -558,7 +574,6 @@ struct MemoryManager { OBJSCRUB eccScrubberState; struct __nvoc_inner_struc_MemoryManager_1__ Ram; NvU32 PteKindOverride; - NvU64 scratchDwordOffset; NvU32 zbcSurfaces; NvU64 overrideInitHeapMin; NvU64 overrideHeapMax; @@ -576,11 +591,11 @@ struct MemoryManager { NvHandle hClient; NvHandle hDevice; NvHandle hSubdevice; + NvBool bReservedMemAtBottom; NvHandle hThirdPartyP2P; NvBool bMonitoredFenceSupported; NvBool b64BitSemaphoresSupported; NvBool bGenericKindSupport; - NvBool bLocalizedMemPoolEnabled; }; #ifndef __NVOC_CLASS_MemoryManager_TYPEDEF__ @@ -621,6 +636,8 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrStatePreUnload(pGpu, pMemoryManager, arg0) memmgrStatePreUnload_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStateUnload(pGpu, pMemoryManager, arg0) memmgrStateUnload_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrStateDestroy(pGpu, pMemoryManager) memmgrStateDestroy_DISPATCH(pGpu, pMemoryManager) +#define memmgrAllocateConsoleRegion(pGpu, pMemoryManager, arg0) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrAllocateConsoleRegion_HAL(pGpu, pMemoryManager, arg0) memmgrAllocateConsoleRegion_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrMemUtilsSec2CtxInit(pGpu, pMemoryManager, arg0) memmgrMemUtilsSec2CtxInit_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrMemUtilsSec2CtxInit_HAL(pGpu, pMemoryManager, arg0) memmgrMemUtilsSec2CtxInit_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrMemUtilsCheckMemoryFastScrubEnable(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsCheckMemoryFastScrubEnable_DISPATCH(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) @@ -629,6 +646,8 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrAllocDetermineAlignment_HAL(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment) memmgrAllocDetermineAlignment_DISPATCH(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment) #define memmgrGetMaxContextSize(pGpu, pMemoryManager) memmgrGetMaxContextSize_DISPATCH(pGpu, pMemoryManager) #define memmgrGetMaxContextSize_HAL(pGpu, pMemoryManager) memmgrGetMaxContextSize_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetFbTaxSize(pGpu, pMemoryManager) memmgrGetFbTaxSize_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetFbTaxSize_HAL(pGpu, pMemoryManager) memmgrGetFbTaxSize_DISPATCH(pGpu, pMemoryManager) #define memmgrScrubRegistryOverrides(pGpu, pMemoryManager) memmgrScrubRegistryOverrides_DISPATCH(pGpu, pMemoryManager) #define memmgrScrubRegistryOverrides_HAL(pGpu, pMemoryManager) memmgrScrubRegistryOverrides_DISPATCH(pGpu, pMemoryManager) #define memmgrGetPteKindBl(pGpu, pMemoryManager) memmgrGetPteKindBl_DISPATCH(pGpu, pMemoryManager) @@ -639,10 +658,16 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrChooseKindCompressC_HAL(pGpu, pMemoryManager, arg0) memmgrChooseKindCompressC_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrGetFlaKind(pGpu, pMemoryManager, arg0) memmgrGetFlaKind_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrGetFlaKind_HAL(pGpu, pMemoryManager, arg0) memmgrGetFlaKind_DISPATCH(pGpu, pMemoryManager, arg0) -#define memmgrIsApertureSupportedByFla(pGpu, pMemoryManager, arg0) memmgrIsApertureSupportedByFla_DISPATCH(pGpu, pMemoryManager, arg0) -#define memmgrIsApertureSupportedByFla_HAL(pGpu, pMemoryManager, arg0) memmgrIsApertureSupportedByFla_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrIsMemDescSupportedByFla(pGpu, pMemoryManager, pMemDesc) memmgrIsMemDescSupportedByFla_DISPATCH(pGpu, pMemoryManager, pMemDesc) +#define memmgrIsMemDescSupportedByFla_HAL(pGpu, pMemoryManager, pMemDesc) memmgrIsMemDescSupportedByFla_DISPATCH(pGpu, pMemoryManager, pMemDesc) #define memmgrDetermineComptag(pGpu, pMemoryManager, arg0) memmgrDetermineComptag_DISPATCH(pGpu, pMemoryManager, arg0) #define memmgrDetermineComptag_HAL(pGpu, pMemoryManager, arg0) memmgrDetermineComptag_DISPATCH(pGpu, pMemoryManager, arg0) +#define memmgrGetGrHeapReservationSize(pGpu, pMemoryManager) memmgrGetGrHeapReservationSize_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetGrHeapReservationSize_HAL(pGpu, pMemoryManager) memmgrGetGrHeapReservationSize_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetRunlistEntriesReservedFbSpace(pGpu, pMemoryManager) memmgrGetRunlistEntriesReservedFbSpace_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetRunlistEntriesReservedFbSpace_HAL(pGpu, pMemoryManager) memmgrGetRunlistEntriesReservedFbSpace_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetUserdReservedFbSpace(pGpu, pMemoryManager) memmgrGetUserdReservedFbSpace_DISPATCH(pGpu, pMemoryManager) +#define memmgrGetUserdReservedFbSpace_HAL(pGpu, pMemoryManager) memmgrGetUserdReservedFbSpace_DISPATCH(pGpu, pMemoryManager) #define memmgrCheckReservedMemorySize(pGpu, pMemoryManager) memmgrCheckReservedMemorySize_DISPATCH(pGpu, pMemoryManager) #define memmgrCheckReservedMemorySize_HAL(pGpu, pMemoryManager) memmgrCheckReservedMemorySize_DISPATCH(pGpu, pMemoryManager) #define memmgrReadMmuLock(pGpu, pMemoryManager, pbIsValid, pMmuLockLo, pMmuLockHi) memmgrReadMmuLock_DISPATCH(pGpu, pMemoryManager, pbIsValid, pMmuLockLo, pMmuLockHi) @@ -651,12 +676,22 @@ NV_STATUS __nvoc_objCreate_MemoryManager(MemoryManager**, Dynamic*, NvU32); #define memmgrBlockMemLockedMemory_HAL(pGpu, pMemoryManager) memmgrBlockMemLockedMemory_DISPATCH(pGpu, pMemoryManager) #define memmgrInsertUnprotectedRegionAtBottomOfFb(pGpu, pMemoryManager, pSize) memmgrInsertUnprotectedRegionAtBottomOfFb_DISPATCH(pGpu, pMemoryManager, pSize) #define memmgrInsertUnprotectedRegionAtBottomOfFb_HAL(pGpu, pMemoryManager, pSize) memmgrInsertUnprotectedRegionAtBottomOfFb_DISPATCH(pGpu, pMemoryManager, pSize) +#define memmgrInitBaseFbRegions(pGpu, pMemoryManager) memmgrInitBaseFbRegions_DISPATCH(pGpu, pMemoryManager) +#define memmgrInitBaseFbRegions_HAL(pGpu, pMemoryManager) memmgrInitBaseFbRegions_DISPATCH(pGpu, pMemoryManager) #define memmgrGetDisablePlcKind(pMemoryManager, pteKind) memmgrGetDisablePlcKind_DISPATCH(pMemoryManager, pteKind) #define memmgrGetDisablePlcKind_HAL(pMemoryManager, pteKind) memmgrGetDisablePlcKind_DISPATCH(pMemoryManager, pteKind) #define memmgrEnableDynamicPageOfflining(pGpu, pMemoryManager) memmgrEnableDynamicPageOfflining_DISPATCH(pGpu, pMemoryManager) #define memmgrEnableDynamicPageOfflining_HAL(pGpu, pMemoryManager) memmgrEnableDynamicPageOfflining_DISPATCH(pGpu, pMemoryManager) +#define memmgrSetPartitionableMem(pGpu, pMemoryManager) memmgrSetPartitionableMem_DISPATCH(pGpu, pMemoryManager) +#define memmgrSetPartitionableMem_HAL(pGpu, pMemoryManager) memmgrSetPartitionableMem_DISPATCH(pGpu, pMemoryManager) +#define memmgrAllocMIGGPUInstanceMemory(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap) memmgrAllocMIGGPUInstanceMemory_DISPATCH(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap) +#define memmgrAllocMIGGPUInstanceMemory_HAL(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap) memmgrAllocMIGGPUInstanceMemory_DISPATCH(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap) #define memmgrGetBlackListPages(pGpu, pMemoryManager, pBlAddrs, pCount) memmgrGetBlackListPages_DISPATCH(pGpu, pMemoryManager, pBlAddrs, pCount) #define memmgrGetBlackListPages_HAL(pGpu, pMemoryManager, pBlAddrs, pCount) memmgrGetBlackListPages_DISPATCH(pGpu, pMemoryManager, pBlAddrs, pCount) +#define memmgrDiscoverMIGPartitionableMemoryRange(pGpu, pMemoryManager, pMemoryRange) memmgrDiscoverMIGPartitionableMemoryRange_DISPATCH(pGpu, pMemoryManager, pMemoryRange) +#define memmgrDiscoverMIGPartitionableMemoryRange_HAL(pGpu, pMemoryManager, pMemoryRange) memmgrDiscoverMIGPartitionableMemoryRange_DISPATCH(pGpu, pMemoryManager, pMemoryRange) +#define memmgrValidateFBEndReservation(pGpu, pMemoryManager) memmgrValidateFBEndReservation_DISPATCH(pGpu, pMemoryManager) +#define memmgrValidateFBEndReservation_HAL(pGpu, pMemoryManager) memmgrValidateFBEndReservation_DISPATCH(pGpu, pMemoryManager) #define memmgrStatePreLoad(pGpu, pEngstate, arg0) memmgrStatePreLoad_DISPATCH(pGpu, pEngstate, arg0) #define memmgrStatePostUnload(pGpu, pEngstate, arg0) memmgrStatePostUnload_DISPATCH(pGpu, pEngstate, arg0) #define memmgrStateInitUnlocked(pGpu, pEngstate) memmgrStateInitUnlocked_DISPATCH(pGpu, pEngstate) @@ -721,20 +756,6 @@ static inline NV_STATUS memmgrReserveConsoleRegion(OBJGPU *pGpu, struct MemoryMa #define memmgrReserveConsoleRegion_HAL(pGpu, pMemoryManager, arg0) memmgrReserveConsoleRegion(pGpu, pMemoryManager, arg0) -NV_STATUS memmgrAllocateConsoleRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg0); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrAllocateConsoleRegion(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg0) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrAllocateConsoleRegion(pGpu, pMemoryManager, arg0) memmgrAllocateConsoleRegion_IMPL(pGpu, pMemoryManager, arg0) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrAllocateConsoleRegion_HAL(pGpu, pMemoryManager, arg0) memmgrAllocateConsoleRegion(pGpu, pMemoryManager, arg0) - NV_STATUS memmgrGetKindComprForGpu_KERNEL(struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *arg0, OBJGPU *pGpu, NvU64 offset, NvU32 *kind, COMPR_INFO *pComprInfo); @@ -888,7 +909,10 @@ static inline void memmgrScrubMemory(OBJGPU *pGpu, struct MemoryManager *pMemory #define memmgrScrubMemory_HAL(pGpu, pMemoryManager, arg0, arg1) memmgrScrubMemory(pGpu, pMemoryManager, arg0, arg1) -NV_STATUS memmgrMemUtilsMemSetBlocking_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2); +static inline NV_STATUS memmgrMemUtilsMemSetBlocking_92bfc3(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} #ifdef __nvoc_mem_mgr_h_disabled @@ -897,12 +921,15 @@ static inline NV_STATUS memmgrMemUtilsMemSetBlocking(OBJGPU *pGpu, struct Memory return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrMemUtilsMemSetBlocking(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrMemUtilsMemSetBlocking_GM107(pGpu, pMemoryManager, arg0, arg1, arg2) +#define memmgrMemUtilsMemSetBlocking(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrMemUtilsMemSetBlocking_92bfc3(pGpu, pMemoryManager, arg0, arg1, arg2) #endif //__nvoc_mem_mgr_h_disabled #define memmgrMemUtilsMemSetBlocking_HAL(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrMemUtilsMemSetBlocking(pGpu, pMemoryManager, arg0, arg1, arg2) -NV_STATUS memmgrMemUtilsMemSet_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2, NvU32 arg3, NvU32 *arg4); +static inline NV_STATUS memmgrMemUtilsMemSet_92bfc3(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0, RmPhysAddr arg1, NvU64 arg2, NvU32 arg3, NvU32 *arg4) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} #ifdef __nvoc_mem_mgr_h_disabled @@ -911,12 +938,15 @@ static inline NV_STATUS memmgrMemUtilsMemSet(OBJGPU *pGpu, struct MemoryManager return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrMemUtilsMemSet(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsMemSet_GM107(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) +#define memmgrMemUtilsMemSet(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsMemSet_92bfc3(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) #endif //__nvoc_mem_mgr_h_disabled #define memmgrMemUtilsMemSet_HAL(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) memmgrMemUtilsMemSet(pGpu, pMemoryManager, arg0, arg1, arg2, arg3, arg4) -NV_STATUS memmgrMemUtilsAllocateEccScrubber_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); +static inline NV_STATUS memmgrMemUtilsAllocateEccScrubber_92bfc3(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} #ifdef __nvoc_mem_mgr_h_disabled @@ -925,12 +955,15 @@ static inline NV_STATUS memmgrMemUtilsAllocateEccScrubber(OBJGPU *pGpu, struct M return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrMemUtilsAllocateEccScrubber(pGpu, pMemoryManager, arg0) memmgrMemUtilsAllocateEccScrubber_GM107(pGpu, pMemoryManager, arg0) +#define memmgrMemUtilsAllocateEccScrubber(pGpu, pMemoryManager, arg0) memmgrMemUtilsAllocateEccScrubber_92bfc3(pGpu, pMemoryManager, arg0) #endif //__nvoc_mem_mgr_h_disabled #define memmgrMemUtilsAllocateEccScrubber_HAL(pGpu, pMemoryManager, arg0) memmgrMemUtilsAllocateEccScrubber(pGpu, pMemoryManager, arg0) -NV_STATUS memmgrMemUtilsAllocateEccAllocScrubber_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); +static inline NV_STATUS memmgrMemUtilsAllocateEccAllocScrubber_92bfc3(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} #ifdef __nvoc_mem_mgr_h_disabled @@ -939,7 +972,7 @@ static inline NV_STATUS memmgrMemUtilsAllocateEccAllocScrubber(OBJGPU *pGpu, str return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrMemUtilsAllocateEccAllocScrubber(pGpu, pMemoryManager, arg0) memmgrMemUtilsAllocateEccAllocScrubber_GM107(pGpu, pMemoryManager, arg0) +#define memmgrMemUtilsAllocateEccAllocScrubber(pGpu, pMemoryManager, arg0) memmgrMemUtilsAllocateEccAllocScrubber_92bfc3(pGpu, pMemoryManager, arg0) #endif //__nvoc_mem_mgr_h_disabled #define memmgrMemUtilsAllocateEccAllocScrubber_HAL(pGpu, pMemoryManager, arg0) memmgrMemUtilsAllocateEccAllocScrubber(pGpu, pMemoryManager, arg0) @@ -1144,22 +1177,6 @@ static inline NV_STATUS memmgrGetBAR1InfoForDevice(OBJGPU *pGpu, struct MemoryMa #define memmgrGetBAR1InfoForDevice_HAL(pGpu, pMemoryManager, pDevice, bar1Info) memmgrGetBAR1InfoForDevice(pGpu, pMemoryManager, pDevice, bar1Info) -static inline NvU64 memmgrGetFbTaxSize_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - return 0; -} - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NvU64 memmgrGetFbTaxSize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return 0; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrGetFbTaxSize(pGpu, pMemoryManager) memmgrGetFbTaxSize_4a4dee(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrGetFbTaxSize_HAL(pGpu, pMemoryManager) memmgrGetFbTaxSize(pGpu, pMemoryManager) - NvU64 memmgrGetVgpuHostRmReservedFb_KERNEL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 vgpuTypeId); NvU64 memmgrGetVgpuHostRmReservedFb_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 vgpuTypeId); @@ -1560,7 +1577,9 @@ static inline void memmgrSetCtagOffsetInParams(OBJGPU *pGpu, struct MemoryManage #define memmgrSetCtagOffsetInParams_HAL(pGpu, pMemoryManager, arg0, arg1) memmgrSetCtagOffsetInParams(pGpu, pMemoryManager, arg0, arg1) -void memmgrChannelPushSemaphoreMethodsBlock_GP100(struct MemoryManager *pMemoryManager, NvU32 arg0, NvU64 arg1, NvU32 arg2, NvU32 **arg3); +static inline void memmgrChannelPushSemaphoreMethodsBlock_f2d351(struct MemoryManager *pMemoryManager, NvU32 arg0, NvU64 arg1, NvU32 arg2, NvU32 **arg3) { + NV_ASSERT_PRECOMP(0); +} #ifdef __nvoc_mem_mgr_h_disabled @@ -1568,12 +1587,14 @@ static inline void memmgrChannelPushSemaphoreMethodsBlock(struct MemoryManager * NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); } #else //__nvoc_mem_mgr_h_disabled -#define memmgrChannelPushSemaphoreMethodsBlock(pMemoryManager, arg0, arg1, arg2, arg3) memmgrChannelPushSemaphoreMethodsBlock_GP100(pMemoryManager, arg0, arg1, arg2, arg3) +#define memmgrChannelPushSemaphoreMethodsBlock(pMemoryManager, arg0, arg1, arg2, arg3) memmgrChannelPushSemaphoreMethodsBlock_f2d351(pMemoryManager, arg0, arg1, arg2, arg3) #endif //__nvoc_mem_mgr_h_disabled #define memmgrChannelPushSemaphoreMethodsBlock_HAL(pMemoryManager, arg0, arg1, arg2, arg3) memmgrChannelPushSemaphoreMethodsBlock(pMemoryManager, arg0, arg1, arg2, arg3) -void memmgrChannelPushAddressMethodsBlock_GP100(struct MemoryManager *pMemoryManager, NvBool arg0, NvU32 arg1, RmPhysAddr arg2, NvU32 **arg3); +static inline void memmgrChannelPushAddressMethodsBlock_f2d351(struct MemoryManager *pMemoryManager, NvBool arg0, NvU32 arg1, RmPhysAddr arg2, NvU32 **arg3) { + NV_ASSERT_PRECOMP(0); +} #ifdef __nvoc_mem_mgr_h_disabled @@ -1581,7 +1602,7 @@ static inline void memmgrChannelPushAddressMethodsBlock(struct MemoryManager *pM NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); } #else //__nvoc_mem_mgr_h_disabled -#define memmgrChannelPushAddressMethodsBlock(pMemoryManager, arg0, arg1, arg2, arg3) memmgrChannelPushAddressMethodsBlock_GP100(pMemoryManager, arg0, arg1, arg2, arg3) +#define memmgrChannelPushAddressMethodsBlock(pMemoryManager, arg0, arg1, arg2, arg3) memmgrChannelPushAddressMethodsBlock_f2d351(pMemoryManager, arg0, arg1, arg2, arg3) #endif //__nvoc_mem_mgr_h_disabled #define memmgrChannelPushAddressMethodsBlock_HAL(pMemoryManager, arg0, arg1, arg2, arg3) memmgrChannelPushAddressMethodsBlock(pMemoryManager, arg0, arg1, arg2, arg3) @@ -1627,8 +1648,6 @@ static inline void memmgrCalcReservedFbSpaceForUVM(OBJGPU *pGpu, struct MemoryMa #define memmgrCalcReservedFbSpaceForUVM_HAL(pGpu, pMemoryManager, arg0) memmgrCalcReservedFbSpaceForUVM(pGpu, pMemoryManager, arg0) -void memmgrCalcReservedFbSpaceHal_FWCLIENT(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0, NvU64 *arg1, NvU64 *arg2); - void memmgrCalcReservedFbSpaceHal_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 *arg0, NvU64 *arg1, NvU64 *arg2); @@ -1637,57 +1656,11 @@ static inline void memmgrCalcReservedFbSpaceHal(OBJGPU *pGpu, struct MemoryManag NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); } #else //__nvoc_mem_mgr_h_disabled -#define memmgrCalcReservedFbSpaceHal(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrCalcReservedFbSpaceHal_FWCLIENT(pGpu, pMemoryManager, arg0, arg1, arg2) +#define memmgrCalcReservedFbSpaceHal(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrCalcReservedFbSpaceHal_GM107(pGpu, pMemoryManager, arg0, arg1, arg2) #endif //__nvoc_mem_mgr_h_disabled #define memmgrCalcReservedFbSpaceHal_HAL(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrCalcReservedFbSpaceHal(pGpu, pMemoryManager, arg0, arg1, arg2) -static inline NvU32 memmgrGetGrHeapReservationSize_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - return 0; -} - -NvU32 memmgrGetGrHeapReservationSize_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NvU32 memmgrGetGrHeapReservationSize(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return 0; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrGetGrHeapReservationSize(pGpu, pMemoryManager) memmgrGetGrHeapReservationSize_4a4dee(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrGetGrHeapReservationSize_HAL(pGpu, pMemoryManager) memmgrGetGrHeapReservationSize(pGpu, pMemoryManager) - -NvU32 memmgrGetRunlistEntriesReservedFbSpace_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NvU32 memmgrGetRunlistEntriesReservedFbSpace(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return 0; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrGetRunlistEntriesReservedFbSpace(pGpu, pMemoryManager) memmgrGetRunlistEntriesReservedFbSpace_GM107(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrGetRunlistEntriesReservedFbSpace_HAL(pGpu, pMemoryManager) memmgrGetRunlistEntriesReservedFbSpace(pGpu, pMemoryManager) - -NvU32 memmgrGetUserdReservedFbSpace_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NvU32 memmgrGetUserdReservedFbSpace(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return 0; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrGetUserdReservedFbSpace(pGpu, pMemoryManager) memmgrGetUserdReservedFbSpace_GM107(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrGetUserdReservedFbSpace_HAL(pGpu, pMemoryManager) memmgrGetUserdReservedFbSpace(pGpu, pMemoryManager) - NV_STATUS memmgrInitReservedMemory_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU64 arg0); @@ -1702,8 +1675,6 @@ static inline NV_STATUS memmgrInitReservedMemory(OBJGPU *pGpu, struct MemoryMana #define memmgrInitReservedMemory_HAL(pGpu, pMemoryManager, arg0) memmgrInitReservedMemory(pGpu, pMemoryManager, arg0) -NV_STATUS memmgrPreInitReservedMemory_FWCLIENT(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - NV_STATUS memmgrPreInitReservedMemory_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); @@ -1713,27 +1684,11 @@ static inline NV_STATUS memmgrPreInitReservedMemory(OBJGPU *pGpu, struct MemoryM return NV_ERR_NOT_SUPPORTED; } #else //__nvoc_mem_mgr_h_disabled -#define memmgrPreInitReservedMemory(pGpu, pMemoryManager) memmgrPreInitReservedMemory_FWCLIENT(pGpu, pMemoryManager) +#define memmgrPreInitReservedMemory(pGpu, pMemoryManager) memmgrPreInitReservedMemory_GM107(pGpu, pMemoryManager) #endif //__nvoc_mem_mgr_h_disabled #define memmgrPreInitReservedMemory_HAL(pGpu, pMemoryManager) memmgrPreInitReservedMemory(pGpu, pMemoryManager) -NV_STATUS memmgrInitBaseFbRegions_FWCLIENT(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - -NV_STATUS memmgrInitBaseFbRegions_GP102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrInitBaseFbRegions(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrInitBaseFbRegions(pGpu, pMemoryManager) memmgrInitBaseFbRegions_FWCLIENT(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrInitBaseFbRegions_HAL(pGpu, pMemoryManager) memmgrInitBaseFbRegions(pGpu, pMemoryManager) - NV_STATUS memmgrSetMemDescPageSize_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, PMEMORY_DESCRIPTOR arg0, ADDRESS_TRANSLATION arg1, RM_ATTR_PAGE_SIZE arg2); @@ -1748,34 +1703,6 @@ static inline NV_STATUS memmgrSetMemDescPageSize(OBJGPU *pGpu, struct MemoryMana #define memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, arg0, arg1, arg2) memmgrSetMemDescPageSize(pGpu, pMemoryManager, arg0, arg1, arg2) -NV_STATUS memmgrSetPartitionableMem_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrSetPartitionableMem(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrSetPartitionableMem(pGpu, pMemoryManager) memmgrSetPartitionableMem_IMPL(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrSetPartitionableMem_HAL(pGpu, pMemoryManager) memmgrSetPartitionableMem(pGpu, pMemoryManager) - -NV_STATUS memmgrAllocMIGGPUInstanceMemory_PF(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle *phMemory, struct NV_RANGE *pAddrRange, struct Heap **ppMemoryPartitionHeap); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrAllocMIGGPUInstanceMemory(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle *phMemory, struct NV_RANGE *pAddrRange, struct Heap **ppMemoryPartitionHeap) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrAllocMIGGPUInstanceMemory(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap) memmgrAllocMIGGPUInstanceMemory_PF(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrAllocMIGGPUInstanceMemory_HAL(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap) memmgrAllocMIGGPUInstanceMemory(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap) - NV_STATUS memmgrGetBlackListPagesForHeap_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct Heap *pHeap); @@ -1790,22 +1717,6 @@ static inline NV_STATUS memmgrGetBlackListPagesForHeap(OBJGPU *pGpu, struct Memo #define memmgrGetBlackListPagesForHeap_HAL(pGpu, pMemoryManager, pHeap) memmgrGetBlackListPagesForHeap(pGpu, pMemoryManager, pHeap) -static inline NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct NV_RANGE *pMemoryRange) { - return NV_ERR_NOT_SUPPORTED; -} - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct NV_RANGE *pMemoryRange) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrDiscoverMIGPartitionableMemoryRange(pGpu, pMemoryManager, pMemoryRange) memmgrDiscoverMIGPartitionableMemoryRange_46f6a7(pGpu, pMemoryManager, pMemoryRange) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrDiscoverMIGPartitionableMemoryRange_HAL(pGpu, pMemoryManager, pMemoryRange) memmgrDiscoverMIGPartitionableMemoryRange(pGpu, pMemoryManager, pMemoryRange) - NvU32 memmgrGetFBEndReserveSizeEstimate_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); @@ -1820,20 +1731,6 @@ static inline NvU32 memmgrGetFBEndReserveSizeEstimate(OBJGPU *pGpu, struct Memor #define memmgrGetFBEndReserveSizeEstimate_HAL(pGpu, pMemoryManager) memmgrGetFBEndReserveSizeEstimate(pGpu, pMemoryManager) -NV_STATUS memmgrValidateFBEndReservation_PF(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); - - -#ifdef __nvoc_mem_mgr_h_disabled -static inline NV_STATUS memmgrValidateFBEndReservation(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { - NV_ASSERT_FAILED_PRECOMP("MemoryManager was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_mem_mgr_h_disabled -#define memmgrValidateFBEndReservation(pGpu, pMemoryManager) memmgrValidateFBEndReservation_PF(pGpu, pMemoryManager) -#endif //__nvoc_mem_mgr_h_disabled - -#define memmgrValidateFBEndReservation_HAL(pGpu, pMemoryManager) memmgrValidateFBEndReservation(pGpu, pMemoryManager) - static inline NV_STATUS memmgrReserveMemoryForPmu_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { return NV_OK; } @@ -1959,6 +1856,16 @@ static inline void memmgrStateDestroy_DISPATCH(OBJGPU *pGpu, struct MemoryManage pMemoryManager->__memmgrStateDestroy__(pGpu, pMemoryManager); } +static inline NV_STATUS memmgrAllocateConsoleRegion_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg0) { + return NV_OK; +} + +NV_STATUS memmgrAllocateConsoleRegion_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg0); + +static inline NV_STATUS memmgrAllocateConsoleRegion_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, FB_REGION_DESCRIPTOR *arg0) { + return pMemoryManager->__memmgrAllocateConsoleRegion__(pGpu, pMemoryManager, arg0); +} + NV_STATUS memmgrMemUtilsSec2CtxInit_GH100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0); static inline NV_STATUS memmgrMemUtilsSec2CtxInit_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, OBJCHANNEL *arg0) { @@ -1997,6 +1904,16 @@ static inline NvU64 memmgrGetMaxContextSize_DISPATCH(OBJGPU *pGpu, struct Memory return pMemoryManager->__memmgrGetMaxContextSize__(pGpu, pMemoryManager); } +NvU64 memmgrGetFbTaxSize_VGPUSTUB(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NvU64 memmgrGetFbTaxSize_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return 0; +} + +static inline NvU64 memmgrGetFbTaxSize_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrGetFbTaxSize__(pGpu, pMemoryManager); +} + void memmgrScrubRegistryOverrides_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); void memmgrScrubRegistryOverrides_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); @@ -2045,14 +1962,14 @@ static inline NV_STATUS memmgrGetFlaKind_DISPATCH(OBJGPU *pGpu, struct MemoryMan return pMemoryManager->__memmgrGetFlaKind__(pGpu, pMemoryManager, arg0); } -NvBool memmgrIsApertureSupportedByFla_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0); +NvBool memmgrIsMemDescSupportedByFla_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc); -static inline NvBool memmgrIsApertureSupportedByFla_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0) { +static inline NvBool memmgrIsMemDescSupportedByFla_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc) { return NV_ERR_NOT_SUPPORTED; } -static inline NvBool memmgrIsApertureSupportedByFla_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NV_ADDRESS_SPACE arg0) { - return pMemoryManager->__memmgrIsApertureSupportedByFla__(pGpu, pMemoryManager, arg0); +static inline NvBool memmgrIsMemDescSupportedByFla_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, MEMORY_DESCRIPTOR *pMemDesc) { + return pMemoryManager->__memmgrIsMemDescSupportedByFla__(pGpu, pMemoryManager, pMemDesc); } NvU32 memmgrDetermineComptag_TU102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, RmPhysAddr arg0); @@ -2066,6 +1983,38 @@ static inline NvU32 memmgrDetermineComptag_DISPATCH(OBJGPU *pGpu, struct MemoryM return pMemoryManager->__memmgrDetermineComptag__(pGpu, pMemoryManager, arg0); } +NvU32 memmgrGetGrHeapReservationSize_VGPUSTUB(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NvU32 memmgrGetGrHeapReservationSize_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return 0; +} + +NvU32 memmgrGetGrHeapReservationSize_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NvU32 memmgrGetGrHeapReservationSize_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrGetGrHeapReservationSize__(pGpu, pMemoryManager); +} + +static inline NvU32 memmgrGetRunlistEntriesReservedFbSpace_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return 0; +} + +NvU32 memmgrGetRunlistEntriesReservedFbSpace_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NvU32 memmgrGetRunlistEntriesReservedFbSpace_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrGetRunlistEntriesReservedFbSpace__(pGpu, pMemoryManager); +} + +static inline NvU32 memmgrGetUserdReservedFbSpace_4a4dee(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return 0; +} + +NvU32 memmgrGetUserdReservedFbSpace_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NvU32 memmgrGetUserdReservedFbSpace_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrGetUserdReservedFbSpace__(pGpu, pMemoryManager); +} + NV_STATUS memmgrCheckReservedMemorySize_GK104(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); static inline NV_STATUS memmgrCheckReservedMemorySize_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { @@ -2107,6 +2056,16 @@ static inline NV_STATUS memmgrInsertUnprotectedRegionAtBottomOfFb_DISPATCH(OBJGP return pMemoryManager->__memmgrInsertUnprotectedRegionAtBottomOfFb__(pGpu, pMemoryManager, pSize); } +NV_STATUS memmgrInitBaseFbRegions_FWCLIENT(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +NV_STATUS memmgrInitBaseFbRegions_VGPUSTUB(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +NV_STATUS memmgrInitBaseFbRegions_GP102(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NV_STATUS memmgrInitBaseFbRegions_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrInitBaseFbRegions__(pGpu, pMemoryManager); +} + void memmgrGetDisablePlcKind_GA100(struct MemoryManager *pMemoryManager, NvU32 *pteKind); static inline void memmgrGetDisablePlcKind_b3696a(struct MemoryManager *pMemoryManager, NvU32 *pteKind) { @@ -2129,6 +2088,24 @@ static inline void memmgrEnableDynamicPageOfflining_DISPATCH(OBJGPU *pGpu, struc pMemoryManager->__memmgrEnableDynamicPageOfflining__(pGpu, pMemoryManager); } +static inline NV_STATUS memmgrSetPartitionableMem_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return NV_OK; +} + +NV_STATUS memmgrSetPartitionableMem_IMPL(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NV_STATUS memmgrSetPartitionableMem_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrSetPartitionableMem__(pGpu, pMemoryManager); +} + +NV_STATUS memmgrAllocMIGGPUInstanceMemory_VF(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle *phMemory, struct NV_RANGE *pAddrRange, struct Heap **ppMemoryPartitionHeap); + +NV_STATUS memmgrAllocMIGGPUInstanceMemory_PF(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle *phMemory, struct NV_RANGE *pAddrRange, struct Heap **ppMemoryPartitionHeap); + +static inline NV_STATUS memmgrAllocMIGGPUInstanceMemory_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, NvU32 swizzId, NvHandle *phMemory, struct NV_RANGE *pAddrRange, struct Heap **ppMemoryPartitionHeap) { + return pMemoryManager->__memmgrAllocMIGGPUInstanceMemory__(pGpu, pMemoryManager, swizzId, phMemory, pAddrRange, ppMemoryPartitionHeap); +} + NV_STATUS memmgrGetBlackListPages_GM107(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, BLACKLIST_ADDRESS *pBlAddrs, NvU32 *pCount); NV_STATUS memmgrGetBlackListPages_GA100(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, BLACKLIST_ADDRESS *pBlAddrs, NvU32 *pCount); @@ -2137,6 +2114,26 @@ static inline NV_STATUS memmgrGetBlackListPages_DISPATCH(OBJGPU *pGpu, struct Me return pMemoryManager->__memmgrGetBlackListPages__(pGpu, pMemoryManager, pBlAddrs, pCount); } +NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange_VF(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct NV_RANGE *pMemoryRange); + +static inline NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange_46f6a7(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct NV_RANGE *pMemoryRange) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS memmgrDiscoverMIGPartitionableMemoryRange_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager, struct NV_RANGE *pMemoryRange) { + return pMemoryManager->__memmgrDiscoverMIGPartitionableMemoryRange__(pGpu, pMemoryManager, pMemoryRange); +} + +NV_STATUS memmgrValidateFBEndReservation_PF(OBJGPU *pGpu, struct MemoryManager *pMemoryManager); + +static inline NV_STATUS memmgrValidateFBEndReservation_56cd7a(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return NV_OK; +} + +static inline NV_STATUS memmgrValidateFBEndReservation_DISPATCH(OBJGPU *pGpu, struct MemoryManager *pMemoryManager) { + return pMemoryManager->__memmgrValidateFBEndReservation__(pGpu, pMemoryManager); +} + static inline NV_STATUS memmgrStatePreLoad_DISPATCH(POBJGPU pGpu, struct MemoryManager *pEngstate, NvU32 arg0) { return pEngstate->__memmgrStatePreLoad__(pGpu, pEngstate, arg0); } @@ -2173,6 +2170,10 @@ static inline NvU32 memmgrLocalEgmPeerId(struct MemoryManager *pMemoryManager) { return pMemoryManager->localEgmPeerId; } +static inline NvU64 memmgrLocalEgmBaseAddress(struct MemoryManager *pMemoryManager) { + return pMemoryManager->localEgmBasePhysAddr; +} + static inline NvBool memmgrIsScrubOnFreeEnabled(struct MemoryManager *pMemoryManager) { return pMemoryManager->bScrubOnFreeEnabled; } @@ -2229,10 +2230,6 @@ static inline void memmgrSetClientPageTablesPmaManaged(struct MemoryManager *pMe pMemoryManager->bClientPageTablesPmaManaged = val; } -static inline NvBool memmgrIsPmaAddrTree(struct MemoryManager *pMemoryManager) { - return pMemoryManager->bPmaAddrTree; -} - static inline NvU64 memmgrGetRsvdMemoryBase(struct MemoryManager *pMemoryManager) { return pMemoryManager->rsvdMemoryBase; } diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c index fbe6a12320..2701ec436a 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.c @@ -149,10 +149,6 @@ static void __nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue(struct rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memorymulticastfabricControlLookup(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricUnmap(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return memUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pCallContext, pCpuMapping); } @@ -173,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RmResource_memorymulticastfabricControlSerializati return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_memorymulticastfabricIsPartialUnmapSupported(struct MemoryMulticastFabric *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MemoryMulticastFabric_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { return memCheckCopyPermissions((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_MemoryMulticastFabric_Memory.offset), pDstGpu, pDstDevice); } @@ -204,12 +204,12 @@ static NvBool __nvoc_thunk_RmResource_memorymulticastfabricAccessCallback(struct static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMulticastFabric[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0xfd0101u, /*paramSize=*/ sizeof(NV00FD_CTRL_GET_INFO_PARAMS), @@ -219,12 +219,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMu #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlAttachMem_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0xfd0102u, /*paramSize=*/ sizeof(NV00FD_CTRL_ATTACH_MEM_PARAMS), @@ -234,12 +234,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMu #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlRegisterEvent_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) - /*flags=*/ 0x811u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, /*accessRight=*/0x0u, /*methodId=*/ 0xfd0103u, /*paramSize=*/ sizeof(NV00FD_CTRL_REGISTER_EVENT_PARAMS), @@ -249,12 +249,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMu #endif }, { /* [3] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlAttachGpu_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0xfd0104u, /*paramSize=*/ sizeof(NV00FD_CTRL_ATTACH_GPU_PARAMS), @@ -264,18 +264,48 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMu #endif }, { /* [4] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlDetachMem_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) - /*flags=*/ 0x810u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, /*accessRight=*/0x0u, /*methodId=*/ 0xfd0105u, /*paramSize=*/ sizeof(NV00FD_CTRL_DETACH_MEM_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "memorymulticastfabricCtrlDetachMem" +#endif + }, + { /* [5] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlAttachRemoteGpu_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + /*flags=*/ 0x811u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0106u, + /*paramSize=*/ sizeof(NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlAttachRemoteGpu" +#endif + }, + { /* [6] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) memorymulticastfabricCtrlSetFailure_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + /*flags=*/ 0x813u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xfd0107u, + /*paramSize=*/ sizeof(NV00FD_CTRL_SET_FAILURE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_MemoryMulticastFabric.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "memorymulticastfabricCtrlSetFailure" #endif }, @@ -283,7 +313,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_MemoryMu const struct NVOC_EXPORT_INFO __nvoc_export_info_MemoryMulticastFabric = { - /*numEntries=*/ 5, + /*numEntries=*/ 7, /*pExportEntries=*/ __nvoc_exported_method_def_MemoryMulticastFabric }; @@ -334,26 +364,34 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricGetMapAddrSpace__ = &memorymulticastfabricGetMapAddrSpace_IMPL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__memorymulticastfabricCtrlGetInfo__ = &memorymulticastfabricCtrlGetInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__memorymulticastfabricCtrlAttachMem__ = &memorymulticastfabricCtrlAttachMem_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__memorymulticastfabricCtrlDetachMem__ = &memorymulticastfabricCtrlDetachMem_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) pThis->__memorymulticastfabricCtrlAttachGpu__ = &memorymulticastfabricCtrlAttachGpu_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) pThis->__memorymulticastfabricCtrlRegisterEvent__ = &memorymulticastfabricCtrlRegisterEvent_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) + pThis->__memorymulticastfabricCtrlAttachRemoteGpu__ = &memorymulticastfabricCtrlAttachRemoteGpu_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x813u) + pThis->__memorymulticastfabricCtrlSetFailure__ = &memorymulticastfabricCtrlSetFailure_IMPL; +#endif + pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resCanCopy__ = &__nvoc_thunk_MemoryMulticastFabric_resCanCopy; pThis->__nvoc_base_Memory.__memIsReady__ = &__nvoc_thunk_MemoryMulticastFabric_memIsReady; @@ -382,8 +420,6 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricControl_Epilogue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControl_Epilogue; - pThis->__memorymulticastfabricControlLookup__ = &__nvoc_thunk_RsResource_memorymulticastfabricControlLookup; - pThis->__memorymulticastfabricUnmap__ = &__nvoc_thunk_Memory_memorymulticastfabricUnmap; pThis->__memorymulticastfabricGetMemInterMapParams__ = &__nvoc_thunk_Memory_memorymulticastfabricGetMemInterMapParams; @@ -394,6 +430,8 @@ static void __nvoc_init_funcTable_MemoryMulticastFabric_1(MemoryMulticastFabric pThis->__memorymulticastfabricControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memorymulticastfabricControlSerialization_Prologue; + pThis->__memorymulticastfabricIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_memorymulticastfabricIsPartialUnmapSupported; + pThis->__memorymulticastfabricCheckCopyPermissions__ = &__nvoc_thunk_Memory_memorymulticastfabricCheckCopyPermissions; pThis->__memorymulticastfabricPreDestruct__ = &__nvoc_thunk_RsResource_memorymulticastfabricPreDestruct; @@ -423,21 +461,26 @@ void __nvoc_init_MemoryMulticastFabric(MemoryMulticastFabric *pThis) { __nvoc_init_funcTable_MemoryMulticastFabric(pThis); } -NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MemoryMulticastFabric *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MemoryMulticastFabric), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MemoryMulticastFabric)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MemoryMulticastFabric); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -452,16 +495,25 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric **ppThis, status = __nvoc_ctor_MemoryMulticastFabric(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MemoryMulticastFabric_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MemoryMulticastFabric_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MemoryMulticastFabric)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h index 3b7c7c3aef..885ac0610a 100644 --- a/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h +++ b/src/nvidia/generated/g_mem_multicast_fabric_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2022-23 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -56,11 +56,16 @@ extern "C" { typedef struct mem_multicast_fabric_descriptor MEM_MULTICAST_FABRIC_DESCRIPTOR; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MEM_MULTICAST_FABRIC_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MemoryMulticastFabric { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -82,6 +87,8 @@ struct MemoryMulticastFabric { NV_STATUS (*__memorymulticastfabricCtrlDetachMem__)(struct MemoryMulticastFabric *, NV00FD_CTRL_DETACH_MEM_PARAMS *); NV_STATUS (*__memorymulticastfabricCtrlAttachGpu__)(struct MemoryMulticastFabric *, NV00FD_CTRL_ATTACH_GPU_PARAMS *); NV_STATUS (*__memorymulticastfabricCtrlRegisterEvent__)(struct MemoryMulticastFabric *, NV00FD_CTRL_REGISTER_EVENT_PARAMS *); + NV_STATUS (*__memorymulticastfabricCtrlAttachRemoteGpu__)(struct MemoryMulticastFabric *, NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS *); + NV_STATUS (*__memorymulticastfabricCtrlSetFailure__)(struct MemoryMulticastFabric *, NV00FD_CTRL_SET_FAILURE_PARAMS *); NV_STATUS (*__memorymulticastfabricCheckMemInterUnmap__)(struct MemoryMulticastFabric *, NvBool); NvBool (*__memorymulticastfabricShareCallback__)(struct MemoryMulticastFabric *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__memorymulticastfabricMapTo__)(struct MemoryMulticastFabric *, RS_RES_MAP_TO_PARAMS *); @@ -90,18 +97,20 @@ struct MemoryMulticastFabric { NV_STATUS (*__memorymulticastfabricControl_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricUnmapFrom__)(struct MemoryMulticastFabric *, RS_RES_UNMAP_FROM_PARAMS *); void (*__memorymulticastfabricControl_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memorymulticastfabricControlLookup__)(struct MemoryMulticastFabric *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__memorymulticastfabricUnmap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__memorymulticastfabricGetMemInterMapParams__)(struct MemoryMulticastFabric *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__memorymulticastfabricGetMemoryMappingDescriptor__)(struct MemoryMulticastFabric *, MEMORY_DESCRIPTOR **); NV_STATUS (*__memorymulticastfabricControlFilter__)(struct MemoryMulticastFabric *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricControlSerialization_Prologue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__memorymulticastfabricIsPartialUnmapSupported__)(struct MemoryMulticastFabric *); NV_STATUS (*__memorymulticastfabricCheckCopyPermissions__)(struct MemoryMulticastFabric *, struct OBJGPU *, struct Device *); void (*__memorymulticastfabricPreDestruct__)(struct MemoryMulticastFabric *); NV_STATUS (*__memorymulticastfabricIsDuplicate__)(struct MemoryMulticastFabric *, NvHandle, NvBool *); void (*__memorymulticastfabricControlSerialization_Epilogue__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memorymulticastfabricMap__)(struct MemoryMulticastFabric *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__memorymulticastfabricAccessCallback__)(struct MemoryMulticastFabric *, struct RsClient *, void *, RsAccessRight); + NvU16 expNodeId; + NvBool bImported; MEM_MULTICAST_FABRIC_DESCRIPTOR *PRIVATE_FIELD(pMulticastFabricDesc); }; @@ -145,6 +154,8 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric**, Dynami #define memorymulticastfabricCtrlDetachMem(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlDetachMem_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCtrlAttachGpu(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlAttachGpu_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCtrlRegisterEvent(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlRegisterEvent_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCtrlAttachRemoteGpu(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlAttachRemoteGpu_DISPATCH(pMemoryMulticastFabric, pParams) +#define memorymulticastfabricCtrlSetFailure(pMemoryMulticastFabric, pParams) memorymulticastfabricCtrlSetFailure_DISPATCH(pMemoryMulticastFabric, pParams) #define memorymulticastfabricCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) memorymulticastfabricCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define memorymulticastfabricShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) memorymulticastfabricShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define memorymulticastfabricMapTo(pResource, pParams) memorymulticastfabricMapTo_DISPATCH(pResource, pParams) @@ -153,12 +164,12 @@ NV_STATUS __nvoc_objCreate_MemoryMulticastFabric(MemoryMulticastFabric**, Dynami #define memorymulticastfabricControl_Prologue(pResource, pCallContext, pParams) memorymulticastfabricControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memorymulticastfabricUnmapFrom(pResource, pParams) memorymulticastfabricUnmapFrom_DISPATCH(pResource, pParams) #define memorymulticastfabricControl_Epilogue(pResource, pCallContext, pParams) memorymulticastfabricControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memorymulticastfabricControlLookup(pResource, pParams, ppEntry) memorymulticastfabricControlLookup_DISPATCH(pResource, pParams, ppEntry) #define memorymulticastfabricUnmap(pMemory, pCallContext, pCpuMapping) memorymulticastfabricUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define memorymulticastfabricGetMemInterMapParams(pMemory, pParams) memorymulticastfabricGetMemInterMapParams_DISPATCH(pMemory, pParams) #define memorymulticastfabricGetMemoryMappingDescriptor(pMemory, ppMemDesc) memorymulticastfabricGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define memorymulticastfabricControlFilter(pResource, pCallContext, pParams) memorymulticastfabricControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memorymulticastfabricControlSerialization_Prologue(pResource, pCallContext, pParams) memorymulticastfabricControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define memorymulticastfabricIsPartialUnmapSupported(pResource) memorymulticastfabricIsPartialUnmapSupported_DISPATCH(pResource) #define memorymulticastfabricCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) memorymulticastfabricCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define memorymulticastfabricPreDestruct(pResource) memorymulticastfabricPreDestruct_DISPATCH(pResource) #define memorymulticastfabricIsDuplicate(pMemory, hMemory, pDuplicate) memorymulticastfabricIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) @@ -237,6 +248,18 @@ static inline NV_STATUS memorymulticastfabricCtrlRegisterEvent_DISPATCH(struct M return pMemoryMulticastFabric->__memorymulticastfabricCtrlRegisterEvent__(pMemoryMulticastFabric, pParams); } +NV_STATUS memorymulticastfabricCtrlAttachRemoteGpu_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlAttachRemoteGpu_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlAttachRemoteGpu__(pMemoryMulticastFabric, pParams); +} + +NV_STATUS memorymulticastfabricCtrlSetFailure_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_SET_FAILURE_PARAMS *pParams); + +static inline NV_STATUS memorymulticastfabricCtrlSetFailure_DISPATCH(struct MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_SET_FAILURE_PARAMS *pParams) { + return pMemoryMulticastFabric->__memorymulticastfabricCtrlSetFailure__(pMemoryMulticastFabric, pParams); +} + static inline NV_STATUS memorymulticastfabricCheckMemInterUnmap_DISPATCH(struct MemoryMulticastFabric *pMemory, NvBool bSubdeviceHandleProvided) { return pMemory->__memorymulticastfabricCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } @@ -269,10 +292,6 @@ static inline void memorymulticastfabricControl_Epilogue_DISPATCH(struct MemoryM pResource->__memorymulticastfabricControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memorymulticastfabricControlLookup_DISPATCH(struct MemoryMulticastFabric *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memorymulticastfabricControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS memorymulticastfabricUnmap_DISPATCH(struct MemoryMulticastFabric *pMemory, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping) { return pMemory->__memorymulticastfabricUnmap__(pMemory, pCallContext, pCpuMapping); } @@ -293,6 +312,10 @@ static inline NV_STATUS memorymulticastfabricControlSerialization_Prologue_DISPA return pResource->__memorymulticastfabricControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool memorymulticastfabricIsPartialUnmapSupported_DISPATCH(struct MemoryMulticastFabric *pResource) { + return pResource->__memorymulticastfabricIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS memorymulticastfabricCheckCopyPermissions_DISPATCH(struct MemoryMulticastFabric *pMemory, struct OBJGPU *pDstGpu, struct Device *pDstDevice) { return pMemory->__memorymulticastfabricCheckCopyPermissions__(pMemory, pDstGpu, pDstDevice); } @@ -323,10 +346,20 @@ NV_STATUS memorymulticastfabricConstruct_IMPL(struct MemoryMulticastFabric *arg_ void memorymulticastfabricDestruct_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric); #define __nvoc_memorymulticastfabricDestruct(pMemoryMulticastFabric) memorymulticastfabricDestruct_IMPL(pMemoryMulticastFabric) +void memorymulticastfabricRemoveFromCache_IMPL(struct MemoryMulticastFabric *pMemoryMulticastFabric); + +#ifdef __nvoc_mem_multicast_fabric_h_disabled +static inline void memorymulticastfabricRemoveFromCache(struct MemoryMulticastFabric *pMemoryMulticastFabric) { + NV_ASSERT_FAILED_PRECOMP("MemoryMulticastFabric was disabled!"); +} +#else //__nvoc_mem_multicast_fabric_h_disabled +#define memorymulticastfabricRemoveFromCache(pMemoryMulticastFabric) memorymulticastfabricRemoveFromCache_IMPL(pMemoryMulticastFabric) +#endif //__nvoc_mem_multicast_fabric_h_disabled + #undef PRIVATE_FIELD -NV_STATUS memorymulticastfabricTeamSetupResponseCallback(NvU32 gpuInstance, +NV_STATUS memorymulticastfabricTeamSetupResponseCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage); #endif // _MEMORYMULTICASTFABRIC_H_ diff --git a/src/nvidia/generated/g_mem_nvoc.c b/src/nvidia/generated/g_mem_nvoc.c index 08ed1d4c42..385c1175a8 100644 --- a/src/nvidia/generated/g_mem_nvoc.c +++ b/src/nvidia/generated/g_mem_nvoc.c @@ -128,10 +128,6 @@ static void __nvoc_thunk_RsResource_memAddAdditionalDependants(struct RsClient * resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_memUnmapFrom(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_memControlSerialization_Prologue(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RmResource.offset), pCallContext, pParams); } @@ -144,6 +140,10 @@ static NvBool __nvoc_thunk_RsResource_memCanCopy(struct Memory *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_memIsPartialUnmapSupported(struct Memory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_memPreDestruct(struct Memory *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset)); } @@ -160,8 +160,8 @@ static void __nvoc_thunk_RmResource_memControl_Epilogue(struct Memory *pResource rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_memControlLookup(struct Memory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_memUnmapFrom(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Memory_RsResource.offset), pParams); } static NvBool __nvoc_thunk_RmResource_memAccessCallback(struct Memory *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { @@ -205,12 +205,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Memory[] #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - /*flags=*/ 0x10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) + /*flags=*/ 0x2010u, /*accessRight=*/0x0u, /*methodId=*/ 0x410112u, /*paramSize=*/ sizeof(NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS), @@ -345,7 +345,7 @@ static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { pThis->__memIsExportAllowed__ = &memIsExportAllowed_0c883b; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) pThis->__memCtrlCmdGetSurfaceCompressionCoverageLvm__ = &memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL; #endif @@ -395,14 +395,14 @@ static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { pThis->__memAddAdditionalDependants__ = &__nvoc_thunk_RsResource_memAddAdditionalDependants; - pThis->__memUnmapFrom__ = &__nvoc_thunk_RsResource_memUnmapFrom; - pThis->__memControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_memControlSerialization_Prologue; pThis->__memControl_Prologue__ = &__nvoc_thunk_RmResource_memControl_Prologue; pThis->__memCanCopy__ = &__nvoc_thunk_RsResource_memCanCopy; + pThis->__memIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_memIsPartialUnmapSupported; + pThis->__memPreDestruct__ = &__nvoc_thunk_RsResource_memPreDestruct; pThis->__memMapTo__ = &__nvoc_thunk_RsResource_memMapTo; @@ -411,7 +411,7 @@ static void __nvoc_init_funcTable_Memory_1(Memory *pThis) { pThis->__memControl_Epilogue__ = &__nvoc_thunk_RmResource_memControl_Epilogue; - pThis->__memControlLookup__ = &__nvoc_thunk_RsResource_memControlLookup; + pThis->__memUnmapFrom__ = &__nvoc_thunk_RsResource_memUnmapFrom; pThis->__memAccessCallback__ = &__nvoc_thunk_RmResource_memAccessCallback; } @@ -431,21 +431,26 @@ void __nvoc_init_Memory(Memory *pThis) { __nvoc_init_funcTable_Memory(pThis); } -NV_STATUS __nvoc_objCreate_Memory(Memory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_Memory(Memory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Memory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Memory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Memory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Memory); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -460,16 +465,25 @@ NV_STATUS __nvoc_objCreate_Memory(Memory **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_Memory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_Memory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Memory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Memory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mem_nvoc.h b/src/nvidia/generated/g_mem_nvoc.h index b06237c474..38a61e34ab 100644 --- a/src/nvidia/generated/g_mem_nvoc.h +++ b/src/nvidia/generated/g_mem_nvoc.h @@ -135,11 +135,16 @@ typedef struct * @note Memory cannot be a GpuResource because NoDeviceMemory * subclass is not allocated under a device. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Memory { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -171,15 +176,15 @@ struct Memory { NvU32 (*__memGetRefCount__)(struct Memory *); NV_STATUS (*__memControlFilter__)(struct Memory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__memAddAdditionalDependants__)(struct RsClient *, struct Memory *, RsResourceRef *); - NV_STATUS (*__memUnmapFrom__)(struct Memory *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__memControlSerialization_Prologue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__memControl_Prologue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__memCanCopy__)(struct Memory *); + NvBool (*__memIsPartialUnmapSupported__)(struct Memory *); void (*__memPreDestruct__)(struct Memory *); NV_STATUS (*__memMapTo__)(struct Memory *, RS_RES_MAP_TO_PARAMS *); void (*__memControlSerialization_Epilogue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__memControl_Epilogue__)(struct Memory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__memControlLookup__)(struct Memory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__memUnmapFrom__)(struct Memory *, RS_RES_UNMAP_FROM_PARAMS *); NvBool (*__memAccessCallback__)(struct Memory *, struct RsClient *, void *, RsAccessRight); NvBool bConstructed; struct Device *pDevice; @@ -261,15 +266,15 @@ NV_STATUS __nvoc_objCreate_Memory(Memory**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define memGetRefCount(pResource) memGetRefCount_DISPATCH(pResource) #define memControlFilter(pResource, pCallContext, pParams) memControlFilter_DISPATCH(pResource, pCallContext, pParams) #define memAddAdditionalDependants(pClient, pResource, pReference) memAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define memUnmapFrom(pResource, pParams) memUnmapFrom_DISPATCH(pResource, pParams) #define memControlSerialization_Prologue(pResource, pCallContext, pParams) memControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memControl_Prologue(pResource, pCallContext, pParams) memControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define memCanCopy(pResource) memCanCopy_DISPATCH(pResource) +#define memIsPartialUnmapSupported(pResource) memIsPartialUnmapSupported_DISPATCH(pResource) #define memPreDestruct(pResource) memPreDestruct_DISPATCH(pResource) #define memMapTo(pResource, pParams) memMapTo_DISPATCH(pResource, pParams) #define memControlSerialization_Epilogue(pResource, pCallContext, pParams) memControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define memControl_Epilogue(pResource, pCallContext, pParams) memControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define memControlLookup(pResource, pParams, ppEntry) memControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define memUnmapFrom(pResource, pParams) memUnmapFrom_DISPATCH(pResource, pParams) #define memAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) memAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) NV_STATUS memIsDuplicate_IMPL(struct Memory *pMemory, NvHandle hMemory, NvBool *pDuplicate); @@ -409,10 +414,6 @@ static inline void memAddAdditionalDependants_DISPATCH(struct RsClient *pClient, pResource->__memAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS memUnmapFrom_DISPATCH(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__memUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS memControlSerialization_Prologue_DISPATCH(struct Memory *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__memControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -425,6 +426,10 @@ static inline NvBool memCanCopy_DISPATCH(struct Memory *pResource) { return pResource->__memCanCopy__(pResource); } +static inline NvBool memIsPartialUnmapSupported_DISPATCH(struct Memory *pResource) { + return pResource->__memIsPartialUnmapSupported__(pResource); +} + static inline void memPreDestruct_DISPATCH(struct Memory *pResource) { pResource->__memPreDestruct__(pResource); } @@ -441,8 +446,8 @@ static inline void memControl_Epilogue_DISPATCH(struct Memory *pResource, CALL_C pResource->__memControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS memControlLookup_DISPATCH(struct Memory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__memControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS memUnmapFrom_DISPATCH(struct Memory *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__memUnmapFrom__(pResource, pParams); } static inline NvBool memAccessCallback_DISPATCH(struct Memory *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { diff --git a/src/nvidia/generated/g_mig_config_session_nvoc.c b/src/nvidia/generated/g_mig_config_session_nvoc.c index 116872ad81..e9766c1b0f 100644 --- a/src/nvidia/generated/g_mig_config_session_nvoc.c +++ b/src/nvidia/generated/g_mig_config_session_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_migconfigsessionAddAdditionalDependants(stru resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmapFrom(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_migconfigsessionControlSerialization_Prologue(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmap(struct MIGConfigS return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_migconfigsessionIsPartialUnmapSupported(struct MIGConfigSession *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_migconfigsessionPreDestruct(struct MIGConfigSession *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_migconfigsessionControl_Epilogue(struct MIGC rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionControlLookup(struct MIGConfigSession *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionUnmapFrom(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGConfigSession_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_migconfigsessionMap(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -223,8 +223,6 @@ static void __nvoc_init_funcTable_MIGConfigSession_1(MIGConfigSession *pThis) { pThis->__migconfigsessionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_migconfigsessionAddAdditionalDependants; - pThis->__migconfigsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migconfigsessionUnmapFrom; - pThis->__migconfigsessionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_migconfigsessionControlSerialization_Prologue; pThis->__migconfigsessionControl_Prologue__ = &__nvoc_thunk_RmResource_migconfigsessionControl_Prologue; @@ -233,6 +231,8 @@ static void __nvoc_init_funcTable_MIGConfigSession_1(MIGConfigSession *pThis) { pThis->__migconfigsessionUnmap__ = &__nvoc_thunk_RsResource_migconfigsessionUnmap; + pThis->__migconfigsessionIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_migconfigsessionIsPartialUnmapSupported; + pThis->__migconfigsessionPreDestruct__ = &__nvoc_thunk_RsResource_migconfigsessionPreDestruct; pThis->__migconfigsessionMapTo__ = &__nvoc_thunk_RsResource_migconfigsessionMapTo; @@ -243,7 +243,7 @@ static void __nvoc_init_funcTable_MIGConfigSession_1(MIGConfigSession *pThis) { pThis->__migconfigsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_migconfigsessionControl_Epilogue; - pThis->__migconfigsessionControlLookup__ = &__nvoc_thunk_RsResource_migconfigsessionControlLookup; + pThis->__migconfigsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migconfigsessionUnmapFrom; pThis->__migconfigsessionMap__ = &__nvoc_thunk_RsResource_migconfigsessionMap; @@ -265,21 +265,26 @@ void __nvoc_init_MIGConfigSession(MIGConfigSession *pThis) { __nvoc_init_funcTable_MIGConfigSession(pThis); } -NV_STATUS __nvoc_objCreate_MIGConfigSession(MIGConfigSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MIGConfigSession(MIGConfigSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MIGConfigSession *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MIGConfigSession), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MIGConfigSession)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MIGConfigSession); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -294,16 +299,25 @@ NV_STATUS __nvoc_objCreate_MIGConfigSession(MIGConfigSession **ppThis, Dynamic * status = __nvoc_ctor_MIGConfigSession(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MIGConfigSession_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MIGConfigSession_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MIGConfigSession)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mig_config_session_nvoc.h b/src/nvidia/generated/g_mig_config_session_nvoc.h index 6bf2b9eaad..f261f0d0ba 100644 --- a/src/nvidia/generated/g_mig_config_session_nvoc.h +++ b/src/nvidia/generated/g_mig_config_session_nvoc.h @@ -52,11 +52,16 @@ extern "C" { // Type Definitions // **************************************************************************** + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MIG_CONFIG_SESSION_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MIGConfigSession { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -73,17 +78,17 @@ struct MIGConfigSession { NvU32 (*__migconfigsessionGetRefCount__)(struct MIGConfigSession *); NV_STATUS (*__migconfigsessionControlFilter__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migconfigsessionAddAdditionalDependants__)(struct RsClient *, struct MIGConfigSession *, RsResourceRef *); - NV_STATUS (*__migconfigsessionUnmapFrom__)(struct MIGConfigSession *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__migconfigsessionControlSerialization_Prologue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migconfigsessionControl_Prologue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__migconfigsessionCanCopy__)(struct MIGConfigSession *); NV_STATUS (*__migconfigsessionUnmap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__migconfigsessionIsPartialUnmapSupported__)(struct MIGConfigSession *); void (*__migconfigsessionPreDestruct__)(struct MIGConfigSession *); NV_STATUS (*__migconfigsessionMapTo__)(struct MIGConfigSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__migconfigsessionIsDuplicate__)(struct MIGConfigSession *, NvHandle, NvBool *); void (*__migconfigsessionControlSerialization_Epilogue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migconfigsessionControl_Epilogue__)(struct MIGConfigSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__migconfigsessionControlLookup__)(struct MIGConfigSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__migconfigsessionUnmapFrom__)(struct MIGConfigSession *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__migconfigsessionMap__)(struct MIGConfigSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__migconfigsessionAccessCallback__)(struct MIGConfigSession *, struct RsClient *, void *, RsAccessRight); NvU64 PRIVATE_FIELD(dupedCapDescriptor); @@ -125,17 +130,17 @@ NV_STATUS __nvoc_objCreate_MIGConfigSession(MIGConfigSession**, Dynamic*, NvU32, #define migconfigsessionGetRefCount(pResource) migconfigsessionGetRefCount_DISPATCH(pResource) #define migconfigsessionControlFilter(pResource, pCallContext, pParams) migconfigsessionControlFilter_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionAddAdditionalDependants(pClient, pResource, pReference) migconfigsessionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define migconfigsessionUnmapFrom(pResource, pParams) migconfigsessionUnmapFrom_DISPATCH(pResource, pParams) #define migconfigsessionControlSerialization_Prologue(pResource, pCallContext, pParams) migconfigsessionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControl_Prologue(pResource, pCallContext, pParams) migconfigsessionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionCanCopy(pResource) migconfigsessionCanCopy_DISPATCH(pResource) #define migconfigsessionUnmap(pResource, pCallContext, pCpuMapping) migconfigsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define migconfigsessionIsPartialUnmapSupported(pResource) migconfigsessionIsPartialUnmapSupported_DISPATCH(pResource) #define migconfigsessionPreDestruct(pResource) migconfigsessionPreDestruct_DISPATCH(pResource) #define migconfigsessionMapTo(pResource, pParams) migconfigsessionMapTo_DISPATCH(pResource, pParams) #define migconfigsessionIsDuplicate(pResource, hMemory, pDuplicate) migconfigsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define migconfigsessionControlSerialization_Epilogue(pResource, pCallContext, pParams) migconfigsessionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migconfigsessionControl_Epilogue(pResource, pCallContext, pParams) migconfigsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define migconfigsessionControlLookup(pResource, pParams, ppEntry) migconfigsessionControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define migconfigsessionUnmapFrom(pResource, pParams) migconfigsessionUnmapFrom_DISPATCH(pResource, pParams) #define migconfigsessionMap(pResource, pCallContext, pParams, pCpuMapping) migconfigsessionMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define migconfigsessionAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) migconfigsessionAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool migconfigsessionShareCallback_DISPATCH(struct MIGConfigSession *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -170,10 +175,6 @@ static inline void migconfigsessionAddAdditionalDependants_DISPATCH(struct RsCli pResource->__migconfigsessionAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS migconfigsessionUnmapFrom_DISPATCH(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__migconfigsessionUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS migconfigsessionControlSerialization_Prologue_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__migconfigsessionControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -190,6 +191,10 @@ static inline NV_STATUS migconfigsessionUnmap_DISPATCH(struct MIGConfigSession * return pResource->__migconfigsessionUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool migconfigsessionIsPartialUnmapSupported_DISPATCH(struct MIGConfigSession *pResource) { + return pResource->__migconfigsessionIsPartialUnmapSupported__(pResource); +} + static inline void migconfigsessionPreDestruct_DISPATCH(struct MIGConfigSession *pResource) { pResource->__migconfigsessionPreDestruct__(pResource); } @@ -210,8 +215,8 @@ static inline void migconfigsessionControl_Epilogue_DISPATCH(struct MIGConfigSes pResource->__migconfigsessionControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS migconfigsessionControlLookup_DISPATCH(struct MIGConfigSession *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__migconfigsessionControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS migconfigsessionUnmapFrom_DISPATCH(struct MIGConfigSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__migconfigsessionUnmapFrom__(pResource, pParams); } static inline NV_STATUS migconfigsessionMap_DISPATCH(struct MIGConfigSession *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_mig_monitor_session_nvoc.c b/src/nvidia/generated/g_mig_monitor_session_nvoc.c index 7d3cbdfa46..77c7796369 100644 --- a/src/nvidia/generated/g_mig_monitor_session_nvoc.c +++ b/src/nvidia/generated/g_mig_monitor_session_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_migmonitorsessionAddAdditionalDependants(str resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmapFrom(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Prologue(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmap(struct MIGMonito return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_migmonitorsessionIsPartialUnmapSupported(struct MIGMonitorSession *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_migmonitorsessionPreDestruct(struct MIGMonitorSession *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_migmonitorsessionControl_Epilogue(struct MIG rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionControlLookup(struct MIGMonitorSession *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionUnmapFrom(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MIGMonitorSession_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_migmonitorsessionMap(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -223,8 +223,6 @@ static void __nvoc_init_funcTable_MIGMonitorSession_1(MIGMonitorSession *pThis) pThis->__migmonitorsessionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_migmonitorsessionAddAdditionalDependants; - pThis->__migmonitorsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmapFrom; - pThis->__migmonitorsessionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_migmonitorsessionControlSerialization_Prologue; pThis->__migmonitorsessionControl_Prologue__ = &__nvoc_thunk_RmResource_migmonitorsessionControl_Prologue; @@ -233,6 +231,8 @@ static void __nvoc_init_funcTable_MIGMonitorSession_1(MIGMonitorSession *pThis) pThis->__migmonitorsessionUnmap__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmap; + pThis->__migmonitorsessionIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_migmonitorsessionIsPartialUnmapSupported; + pThis->__migmonitorsessionPreDestruct__ = &__nvoc_thunk_RsResource_migmonitorsessionPreDestruct; pThis->__migmonitorsessionMapTo__ = &__nvoc_thunk_RsResource_migmonitorsessionMapTo; @@ -243,7 +243,7 @@ static void __nvoc_init_funcTable_MIGMonitorSession_1(MIGMonitorSession *pThis) pThis->__migmonitorsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_migmonitorsessionControl_Epilogue; - pThis->__migmonitorsessionControlLookup__ = &__nvoc_thunk_RsResource_migmonitorsessionControlLookup; + pThis->__migmonitorsessionUnmapFrom__ = &__nvoc_thunk_RsResource_migmonitorsessionUnmapFrom; pThis->__migmonitorsessionMap__ = &__nvoc_thunk_RsResource_migmonitorsessionMap; @@ -265,21 +265,26 @@ void __nvoc_init_MIGMonitorSession(MIGMonitorSession *pThis) { __nvoc_init_funcTable_MIGMonitorSession(pThis); } -NV_STATUS __nvoc_objCreate_MIGMonitorSession(MIGMonitorSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MIGMonitorSession(MIGMonitorSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MIGMonitorSession *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MIGMonitorSession), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MIGMonitorSession)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MIGMonitorSession); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -294,16 +299,25 @@ NV_STATUS __nvoc_objCreate_MIGMonitorSession(MIGMonitorSession **ppThis, Dynamic status = __nvoc_ctor_MIGMonitorSession(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MIGMonitorSession_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MIGMonitorSession_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MIGMonitorSession)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mig_monitor_session_nvoc.h b/src/nvidia/generated/g_mig_monitor_session_nvoc.h index c0d72295fc..f44a1f28ca 100644 --- a/src/nvidia/generated/g_mig_monitor_session_nvoc.h +++ b/src/nvidia/generated/g_mig_monitor_session_nvoc.h @@ -53,11 +53,16 @@ extern "C" { // Type Definitions // **************************************************************************** + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MIG_MONITOR_SESSION_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MIGMonitorSession { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -74,17 +79,17 @@ struct MIGMonitorSession { NvU32 (*__migmonitorsessionGetRefCount__)(struct MIGMonitorSession *); NV_STATUS (*__migmonitorsessionControlFilter__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migmonitorsessionAddAdditionalDependants__)(struct RsClient *, struct MIGMonitorSession *, RsResourceRef *); - NV_STATUS (*__migmonitorsessionUnmapFrom__)(struct MIGMonitorSession *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__migmonitorsessionControlSerialization_Prologue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__migmonitorsessionControl_Prologue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__migmonitorsessionCanCopy__)(struct MIGMonitorSession *); NV_STATUS (*__migmonitorsessionUnmap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__migmonitorsessionIsPartialUnmapSupported__)(struct MIGMonitorSession *); void (*__migmonitorsessionPreDestruct__)(struct MIGMonitorSession *); NV_STATUS (*__migmonitorsessionMapTo__)(struct MIGMonitorSession *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__migmonitorsessionIsDuplicate__)(struct MIGMonitorSession *, NvHandle, NvBool *); void (*__migmonitorsessionControlSerialization_Epilogue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__migmonitorsessionControl_Epilogue__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__migmonitorsessionControlLookup__)(struct MIGMonitorSession *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__migmonitorsessionUnmapFrom__)(struct MIGMonitorSession *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__migmonitorsessionMap__)(struct MIGMonitorSession *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__migmonitorsessionAccessCallback__)(struct MIGMonitorSession *, struct RsClient *, void *, RsAccessRight); NvU64 PRIVATE_FIELD(dupedCapDescriptor); @@ -126,17 +131,17 @@ NV_STATUS __nvoc_objCreate_MIGMonitorSession(MIGMonitorSession**, Dynamic*, NvU3 #define migmonitorsessionGetRefCount(pResource) migmonitorsessionGetRefCount_DISPATCH(pResource) #define migmonitorsessionControlFilter(pResource, pCallContext, pParams) migmonitorsessionControlFilter_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionAddAdditionalDependants(pClient, pResource, pReference) migmonitorsessionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define migmonitorsessionUnmapFrom(pResource, pParams) migmonitorsessionUnmapFrom_DISPATCH(pResource, pParams) #define migmonitorsessionControlSerialization_Prologue(pResource, pCallContext, pParams) migmonitorsessionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControl_Prologue(pResource, pCallContext, pParams) migmonitorsessionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionCanCopy(pResource) migmonitorsessionCanCopy_DISPATCH(pResource) #define migmonitorsessionUnmap(pResource, pCallContext, pCpuMapping) migmonitorsessionUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define migmonitorsessionIsPartialUnmapSupported(pResource) migmonitorsessionIsPartialUnmapSupported_DISPATCH(pResource) #define migmonitorsessionPreDestruct(pResource) migmonitorsessionPreDestruct_DISPATCH(pResource) #define migmonitorsessionMapTo(pResource, pParams) migmonitorsessionMapTo_DISPATCH(pResource, pParams) #define migmonitorsessionIsDuplicate(pResource, hMemory, pDuplicate) migmonitorsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define migmonitorsessionControlSerialization_Epilogue(pResource, pCallContext, pParams) migmonitorsessionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define migmonitorsessionControl_Epilogue(pResource, pCallContext, pParams) migmonitorsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define migmonitorsessionControlLookup(pResource, pParams, ppEntry) migmonitorsessionControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define migmonitorsessionUnmapFrom(pResource, pParams) migmonitorsessionUnmapFrom_DISPATCH(pResource, pParams) #define migmonitorsessionMap(pResource, pCallContext, pParams, pCpuMapping) migmonitorsessionMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define migmonitorsessionAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) migmonitorsessionAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool migmonitorsessionShareCallback_DISPATCH(struct MIGMonitorSession *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -171,10 +176,6 @@ static inline void migmonitorsessionAddAdditionalDependants_DISPATCH(struct RsCl pResource->__migmonitorsessionAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS migmonitorsessionUnmapFrom_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__migmonitorsessionUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS migmonitorsessionControlSerialization_Prologue_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__migmonitorsessionControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -191,6 +192,10 @@ static inline NV_STATUS migmonitorsessionUnmap_DISPATCH(struct MIGMonitorSession return pResource->__migmonitorsessionUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool migmonitorsessionIsPartialUnmapSupported_DISPATCH(struct MIGMonitorSession *pResource) { + return pResource->__migmonitorsessionIsPartialUnmapSupported__(pResource); +} + static inline void migmonitorsessionPreDestruct_DISPATCH(struct MIGMonitorSession *pResource) { pResource->__migmonitorsessionPreDestruct__(pResource); } @@ -211,8 +216,8 @@ static inline void migmonitorsessionControl_Epilogue_DISPATCH(struct MIGMonitorS pResource->__migmonitorsessionControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS migmonitorsessionControlLookup_DISPATCH(struct MIGMonitorSession *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__migmonitorsessionControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS migmonitorsessionUnmapFrom_DISPATCH(struct MIGMonitorSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__migmonitorsessionUnmapFrom__(pResource, pParams); } static inline NV_STATUS migmonitorsessionMap_DISPATCH(struct MIGMonitorSession *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c index cc77cfe6eb..c39de54948 100644 --- a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c +++ b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.c @@ -171,10 +171,6 @@ static void __nvoc_thunk_RmResource_faultbufControl_Epilogue(struct MmuFaultBuff rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_faultbufControlLookup(struct MmuFaultBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_faultbufGetInternalObjectHandle(struct MmuFaultBuffer *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_MmuFaultBuffer_GpuResource.offset)); } @@ -207,6 +203,10 @@ static NvBool __nvoc_thunk_RsResource_faultbufCanCopy(struct MmuFaultBuffer *pRe return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_faultbufIsPartialUnmapSupported(struct MmuFaultBuffer *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_faultbufPreDestruct(struct MmuFaultBuffer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MmuFaultBuffer_RsResource.offset)); } @@ -436,8 +436,6 @@ static void __nvoc_init_funcTable_MmuFaultBuffer_1(MmuFaultBuffer *pThis) { pThis->__faultbufControl_Epilogue__ = &__nvoc_thunk_RmResource_faultbufControl_Epilogue; - pThis->__faultbufControlLookup__ = &__nvoc_thunk_RsResource_faultbufControlLookup; - pThis->__faultbufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_faultbufGetInternalObjectHandle; pThis->__faultbufControl__ = &__nvoc_thunk_GpuResource_faultbufControl; @@ -454,6 +452,8 @@ static void __nvoc_init_funcTable_MmuFaultBuffer_1(MmuFaultBuffer *pThis) { pThis->__faultbufCanCopy__ = &__nvoc_thunk_RsResource_faultbufCanCopy; + pThis->__faultbufIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_faultbufIsPartialUnmapSupported; + pThis->__faultbufPreDestruct__ = &__nvoc_thunk_RsResource_faultbufPreDestruct; pThis->__faultbufIsDuplicate__ = &__nvoc_thunk_RsResource_faultbufIsDuplicate; @@ -487,21 +487,26 @@ void __nvoc_init_MmuFaultBuffer(MmuFaultBuffer *pThis) { __nvoc_init_funcTable_MmuFaultBuffer(pThis); } -NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MmuFaultBuffer *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MmuFaultBuffer), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MmuFaultBuffer)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MmuFaultBuffer); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -516,16 +521,25 @@ NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer **ppThis, Dynamic *pPar status = __nvoc_ctor_MmuFaultBuffer(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MmuFaultBuffer_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MmuFaultBuffer_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MmuFaultBuffer)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h index 55b5f6cccd..c944fe0204 100644 --- a/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h +++ b/src/nvidia/generated/g_mmu_fault_buffer_nvoc.h @@ -43,11 +43,16 @@ extern "C" { /*! * RM internal class representing XXX_FAULT_BUFFER */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MMU_FAULT_BUFFER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MmuFaultBuffer { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -81,7 +86,6 @@ struct MmuFaultBuffer { NV_STATUS (*__faultbufInternalControlForward__)(struct MmuFaultBuffer *, NvU32, void *, NvU32); NV_STATUS (*__faultbufUnmapFrom__)(struct MmuFaultBuffer *, RS_RES_UNMAP_FROM_PARAMS *); void (*__faultbufControl_Epilogue__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__faultbufControlLookup__)(struct MmuFaultBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__faultbufGetInternalObjectHandle__)(struct MmuFaultBuffer *); NV_STATUS (*__faultbufControl__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__faultbufGetMemInterMapParams__)(struct MmuFaultBuffer *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -90,6 +94,7 @@ struct MmuFaultBuffer { NV_STATUS (*__faultbufUnregisterEvent__)(struct MmuFaultBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__faultbufControlSerialization_Prologue__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__faultbufCanCopy__)(struct MmuFaultBuffer *); + NvBool (*__faultbufIsPartialUnmapSupported__)(struct MmuFaultBuffer *); void (*__faultbufPreDestruct__)(struct MmuFaultBuffer *); NV_STATUS (*__faultbufIsDuplicate__)(struct MmuFaultBuffer *, NvHandle, NvBool *); void (*__faultbufControlSerialization_Epilogue__)(struct MmuFaultBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -147,7 +152,6 @@ NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer**, Dynamic*, NvU32, str #define faultbufInternalControlForward(pGpuResource, command, pParams, size) faultbufInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define faultbufUnmapFrom(pResource, pParams) faultbufUnmapFrom_DISPATCH(pResource, pParams) #define faultbufControl_Epilogue(pResource, pCallContext, pParams) faultbufControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define faultbufControlLookup(pResource, pParams, ppEntry) faultbufControlLookup_DISPATCH(pResource, pParams, ppEntry) #define faultbufGetInternalObjectHandle(pGpuResource) faultbufGetInternalObjectHandle_DISPATCH(pGpuResource) #define faultbufControl(pGpuResource, pCallContext, pParams) faultbufControl_DISPATCH(pGpuResource, pCallContext, pParams) #define faultbufGetMemInterMapParams(pRmResource, pParams) faultbufGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -156,6 +160,7 @@ NV_STATUS __nvoc_objCreate_MmuFaultBuffer(MmuFaultBuffer**, Dynamic*, NvU32, str #define faultbufUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) faultbufUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define faultbufControlSerialization_Prologue(pResource, pCallContext, pParams) faultbufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define faultbufCanCopy(pResource) faultbufCanCopy_DISPATCH(pResource) +#define faultbufIsPartialUnmapSupported(pResource) faultbufIsPartialUnmapSupported_DISPATCH(pResource) #define faultbufPreDestruct(pResource) faultbufPreDestruct_DISPATCH(pResource) #define faultbufIsDuplicate(pResource, hMemory, pDuplicate) faultbufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define faultbufControlSerialization_Epilogue(pResource, pCallContext, pParams) faultbufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -264,10 +269,6 @@ static inline void faultbufControl_Epilogue_DISPATCH(struct MmuFaultBuffer *pRes pResource->__faultbufControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS faultbufControlLookup_DISPATCH(struct MmuFaultBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__faultbufControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle faultbufGetInternalObjectHandle_DISPATCH(struct MmuFaultBuffer *pGpuResource) { return pGpuResource->__faultbufGetInternalObjectHandle__(pGpuResource); } @@ -300,6 +301,10 @@ static inline NvBool faultbufCanCopy_DISPATCH(struct MmuFaultBuffer *pResource) return pResource->__faultbufCanCopy__(pResource); } +static inline NvBool faultbufIsPartialUnmapSupported_DISPATCH(struct MmuFaultBuffer *pResource) { + return pResource->__faultbufIsPartialUnmapSupported__(pResource); +} + static inline void faultbufPreDestruct_DISPATCH(struct MmuFaultBuffer *pResource) { pResource->__faultbufPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_mps_api_nvoc.c b/src/nvidia/generated/g_mps_api_nvoc.c index 4ee6ee656d..2a8b80336a 100644 --- a/src/nvidia/generated/g_mps_api_nvoc.c +++ b/src/nvidia/generated/g_mps_api_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_mpsApiAddAdditionalDependants(struct RsClien resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmapFrom(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_mpsApiControlSerialization_Prologue(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmap(struct MpsApi *pResource, s return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_mpsApiIsPartialUnmapSupported(struct MpsApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_mpsApiPreDestruct(struct MpsApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_mpsApiControl_Epilogue(struct MpsApi *pResou rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_mpsApiControlLookup(struct MpsApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_mpsApiUnmapFrom(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_MpsApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_mpsApiMap(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -223,8 +223,6 @@ static void __nvoc_init_funcTable_MpsApi_1(MpsApi *pThis) { pThis->__mpsApiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_mpsApiAddAdditionalDependants; - pThis->__mpsApiUnmapFrom__ = &__nvoc_thunk_RsResource_mpsApiUnmapFrom; - pThis->__mpsApiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_mpsApiControlSerialization_Prologue; pThis->__mpsApiControl_Prologue__ = &__nvoc_thunk_RmResource_mpsApiControl_Prologue; @@ -233,6 +231,8 @@ static void __nvoc_init_funcTable_MpsApi_1(MpsApi *pThis) { pThis->__mpsApiUnmap__ = &__nvoc_thunk_RsResource_mpsApiUnmap; + pThis->__mpsApiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_mpsApiIsPartialUnmapSupported; + pThis->__mpsApiPreDestruct__ = &__nvoc_thunk_RsResource_mpsApiPreDestruct; pThis->__mpsApiMapTo__ = &__nvoc_thunk_RsResource_mpsApiMapTo; @@ -243,7 +243,7 @@ static void __nvoc_init_funcTable_MpsApi_1(MpsApi *pThis) { pThis->__mpsApiControl_Epilogue__ = &__nvoc_thunk_RmResource_mpsApiControl_Epilogue; - pThis->__mpsApiControlLookup__ = &__nvoc_thunk_RsResource_mpsApiControlLookup; + pThis->__mpsApiUnmapFrom__ = &__nvoc_thunk_RsResource_mpsApiUnmapFrom; pThis->__mpsApiMap__ = &__nvoc_thunk_RsResource_mpsApiMap; @@ -265,21 +265,26 @@ void __nvoc_init_MpsApi(MpsApi *pThis) { __nvoc_init_funcTable_MpsApi(pThis); } -NV_STATUS __nvoc_objCreate_MpsApi(MpsApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_MpsApi(MpsApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; MpsApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(MpsApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(MpsApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_MpsApi); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -294,16 +299,25 @@ NV_STATUS __nvoc_objCreate_MpsApi(MpsApi **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_MpsApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_MpsApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_MpsApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(MpsApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_mps_api_nvoc.h b/src/nvidia/generated/g_mps_api_nvoc.h index 5e7199eecd..0029b9a105 100644 --- a/src/nvidia/generated/g_mps_api_nvoc.h +++ b/src/nvidia/generated/g_mps_api_nvoc.h @@ -57,11 +57,16 @@ extern "C" { // // A client which has allocated MpsApi object is identified as MPS process. // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_MPS_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct MpsApi { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -78,17 +83,17 @@ struct MpsApi { NvU32 (*__mpsApiGetRefCount__)(struct MpsApi *); NV_STATUS (*__mpsApiControlFilter__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__mpsApiAddAdditionalDependants__)(struct RsClient *, struct MpsApi *, RsResourceRef *); - NV_STATUS (*__mpsApiUnmapFrom__)(struct MpsApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__mpsApiControlSerialization_Prologue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__mpsApiControl_Prologue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__mpsApiCanCopy__)(struct MpsApi *); NV_STATUS (*__mpsApiUnmap__)(struct MpsApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__mpsApiIsPartialUnmapSupported__)(struct MpsApi *); void (*__mpsApiPreDestruct__)(struct MpsApi *); NV_STATUS (*__mpsApiMapTo__)(struct MpsApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__mpsApiIsDuplicate__)(struct MpsApi *, NvHandle, NvBool *); void (*__mpsApiControlSerialization_Epilogue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__mpsApiControl_Epilogue__)(struct MpsApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__mpsApiControlLookup__)(struct MpsApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__mpsApiUnmapFrom__)(struct MpsApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__mpsApiMap__)(struct MpsApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__mpsApiAccessCallback__)(struct MpsApi *, struct RsClient *, void *, RsAccessRight); }; @@ -129,17 +134,17 @@ NV_STATUS __nvoc_objCreate_MpsApi(MpsApi**, Dynamic*, NvU32, CALL_CONTEXT * arg_ #define mpsApiGetRefCount(pResource) mpsApiGetRefCount_DISPATCH(pResource) #define mpsApiControlFilter(pResource, pCallContext, pParams) mpsApiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define mpsApiAddAdditionalDependants(pClient, pResource, pReference) mpsApiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define mpsApiUnmapFrom(pResource, pParams) mpsApiUnmapFrom_DISPATCH(pResource, pParams) #define mpsApiControlSerialization_Prologue(pResource, pCallContext, pParams) mpsApiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControl_Prologue(pResource, pCallContext, pParams) mpsApiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiCanCopy(pResource) mpsApiCanCopy_DISPATCH(pResource) #define mpsApiUnmap(pResource, pCallContext, pCpuMapping) mpsApiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define mpsApiIsPartialUnmapSupported(pResource) mpsApiIsPartialUnmapSupported_DISPATCH(pResource) #define mpsApiPreDestruct(pResource) mpsApiPreDestruct_DISPATCH(pResource) #define mpsApiMapTo(pResource, pParams) mpsApiMapTo_DISPATCH(pResource, pParams) #define mpsApiIsDuplicate(pResource, hMemory, pDuplicate) mpsApiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define mpsApiControlSerialization_Epilogue(pResource, pCallContext, pParams) mpsApiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define mpsApiControl_Epilogue(pResource, pCallContext, pParams) mpsApiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define mpsApiControlLookup(pResource, pParams, ppEntry) mpsApiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define mpsApiUnmapFrom(pResource, pParams) mpsApiUnmapFrom_DISPATCH(pResource, pParams) #define mpsApiMap(pResource, pCallContext, pParams, pCpuMapping) mpsApiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define mpsApiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) mpsApiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool mpsApiShareCallback_DISPATCH(struct MpsApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -174,10 +179,6 @@ static inline void mpsApiAddAdditionalDependants_DISPATCH(struct RsClient *pClie pResource->__mpsApiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS mpsApiUnmapFrom_DISPATCH(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__mpsApiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS mpsApiControlSerialization_Prologue_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__mpsApiControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -194,6 +195,10 @@ static inline NV_STATUS mpsApiUnmap_DISPATCH(struct MpsApi *pResource, struct CA return pResource->__mpsApiUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool mpsApiIsPartialUnmapSupported_DISPATCH(struct MpsApi *pResource) { + return pResource->__mpsApiIsPartialUnmapSupported__(pResource); +} + static inline void mpsApiPreDestruct_DISPATCH(struct MpsApi *pResource) { pResource->__mpsApiPreDestruct__(pResource); } @@ -214,8 +219,8 @@ static inline void mpsApiControl_Epilogue_DISPATCH(struct MpsApi *pResource, str pResource->__mpsApiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS mpsApiControlLookup_DISPATCH(struct MpsApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__mpsApiControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS mpsApiUnmapFrom_DISPATCH(struct MpsApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__mpsApiUnmapFrom__(pResource, pParams); } static inline NV_STATUS mpsApiMap_DISPATCH(struct MpsApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.c b/src/nvidia/generated/g_no_device_mem_nvoc.c index bd66952fbc..b53bcd0162 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.c +++ b/src/nvidia/generated/g_no_device_mem_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_nodevicememControl_Epilogue(struct NoDeviceM rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_nodevicememControlLookup(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_nodevicememControl(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NvBool __nvoc_thunk_RsResource_nodevicememCanCopy(struct NoDeviceMemory * return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_nodevicememIsPartialUnmapSupported(struct NoDeviceMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NoDeviceMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_nodevicememIsReady(struct NoDeviceMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_NoDeviceMemory_Memory.offset), bCopyConstructorContext); } @@ -260,8 +260,6 @@ static void __nvoc_init_funcTable_NoDeviceMemory_1(NoDeviceMemory *pThis) { pThis->__nodevicememControl_Epilogue__ = &__nvoc_thunk_RmResource_nodevicememControl_Epilogue; - pThis->__nodevicememControlLookup__ = &__nvoc_thunk_RsResource_nodevicememControlLookup; - pThis->__nodevicememControl__ = &__nvoc_thunk_Memory_nodevicememControl; pThis->__nodevicememUnmap__ = &__nvoc_thunk_Memory_nodevicememUnmap; @@ -276,6 +274,8 @@ static void __nvoc_init_funcTable_NoDeviceMemory_1(NoDeviceMemory *pThis) { pThis->__nodevicememCanCopy__ = &__nvoc_thunk_RsResource_nodevicememCanCopy; + pThis->__nodevicememIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_nodevicememIsPartialUnmapSupported; + pThis->__nodevicememIsReady__ = &__nvoc_thunk_Memory_nodevicememIsReady; pThis->__nodevicememCheckCopyPermissions__ = &__nvoc_thunk_Memory_nodevicememCheckCopyPermissions; @@ -307,21 +307,26 @@ void __nvoc_init_NoDeviceMemory(NoDeviceMemory *pThis) { __nvoc_init_funcTable_NoDeviceMemory(pThis); } -NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; NoDeviceMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NoDeviceMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(NoDeviceMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NoDeviceMemory); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -336,16 +341,25 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory **ppThis, Dynamic *pPar status = __nvoc_ctor_NoDeviceMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_NoDeviceMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_NoDeviceMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(NoDeviceMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_no_device_mem_nvoc.h b/src/nvidia/generated/g_no_device_mem_nvoc.h index 25d3465693..4c3326046d 100644 --- a/src/nvidia/generated/g_no_device_mem_nvoc.h +++ b/src/nvidia/generated/g_no_device_mem_nvoc.h @@ -41,11 +41,16 @@ extern "C" { * client instead of a device. This object can be used for memory allocations * that should survive device teardown. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_NO_DEVICE_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct NoDeviceMemory { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -66,7 +71,6 @@ struct NoDeviceMemory { NvBool (*__nodevicememIsGpuMapAllowed__)(struct NoDeviceMemory *, struct OBJGPU *); NV_STATUS (*__nodevicememUnmapFrom__)(struct NoDeviceMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__nodevicememControl_Epilogue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__nodevicememControlLookup__)(struct NoDeviceMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__nodevicememControl__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nodevicememUnmap__)(struct NoDeviceMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__nodevicememGetMemInterMapParams__)(struct NoDeviceMemory *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -74,6 +78,7 @@ struct NoDeviceMemory { NV_STATUS (*__nodevicememControlFilter__)(struct NoDeviceMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__nodevicememControlSerialization_Prologue__)(struct NoDeviceMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__nodevicememCanCopy__)(struct NoDeviceMemory *); + NvBool (*__nodevicememIsPartialUnmapSupported__)(struct NoDeviceMemory *); NV_STATUS (*__nodevicememIsReady__)(struct NoDeviceMemory *, NvBool); NV_STATUS (*__nodevicememCheckCopyPermissions__)(struct NoDeviceMemory *, struct OBJGPU *, struct Device *); void (*__nodevicememPreDestruct__)(struct NoDeviceMemory *); @@ -122,7 +127,6 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory**, Dynamic*, NvU32, CAL #define nodevicememIsGpuMapAllowed(pMemory, pGpu) nodevicememIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define nodevicememUnmapFrom(pResource, pParams) nodevicememUnmapFrom_DISPATCH(pResource, pParams) #define nodevicememControl_Epilogue(pResource, pCallContext, pParams) nodevicememControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define nodevicememControlLookup(pResource, pParams, ppEntry) nodevicememControlLookup_DISPATCH(pResource, pParams, ppEntry) #define nodevicememControl(pMemory, pCallContext, pParams) nodevicememControl_DISPATCH(pMemory, pCallContext, pParams) #define nodevicememUnmap(pMemory, pCallContext, pCpuMapping) nodevicememUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define nodevicememGetMemInterMapParams(pMemory, pParams) nodevicememGetMemInterMapParams_DISPATCH(pMemory, pParams) @@ -130,6 +134,7 @@ NV_STATUS __nvoc_objCreate_NoDeviceMemory(NoDeviceMemory**, Dynamic*, NvU32, CAL #define nodevicememControlFilter(pResource, pCallContext, pParams) nodevicememControlFilter_DISPATCH(pResource, pCallContext, pParams) #define nodevicememControlSerialization_Prologue(pResource, pCallContext, pParams) nodevicememControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define nodevicememCanCopy(pResource) nodevicememCanCopy_DISPATCH(pResource) +#define nodevicememIsPartialUnmapSupported(pResource) nodevicememIsPartialUnmapSupported_DISPATCH(pResource) #define nodevicememIsReady(pMemory, bCopyConstructorContext) nodevicememIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define nodevicememCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) nodevicememCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define nodevicememPreDestruct(pResource) nodevicememPreDestruct_DISPATCH(pResource) @@ -183,10 +188,6 @@ static inline void nodevicememControl_Epilogue_DISPATCH(struct NoDeviceMemory *p pResource->__nodevicememControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS nodevicememControlLookup_DISPATCH(struct NoDeviceMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__nodevicememControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS nodevicememControl_DISPATCH(struct NoDeviceMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__nodevicememControl__(pMemory, pCallContext, pParams); } @@ -215,6 +216,10 @@ static inline NvBool nodevicememCanCopy_DISPATCH(struct NoDeviceMemory *pResourc return pResource->__nodevicememCanCopy__(pResource); } +static inline NvBool nodevicememIsPartialUnmapSupported_DISPATCH(struct NoDeviceMemory *pResource) { + return pResource->__nodevicememIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS nodevicememIsReady_DISPATCH(struct NoDeviceMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__nodevicememIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_nv_debug_dump_nvoc.c b/src/nvidia/generated/g_nv_debug_dump_nvoc.c index 069c772dc5..c303a76d7b 100644 --- a/src/nvidia/generated/g_nv_debug_dump_nvoc.c +++ b/src/nvidia/generated/g_nv_debug_dump_nvoc.c @@ -202,21 +202,26 @@ void __nvoc_init_NvDebugDump(NvDebugDump *pThis) { __nvoc_init_funcTable_NvDebugDump(pThis); } -NV_STATUS __nvoc_objCreate_NvDebugDump(NvDebugDump **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_NvDebugDump(NvDebugDump **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; NvDebugDump *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvDebugDump), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(NvDebugDump)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvDebugDump); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -231,16 +236,25 @@ NV_STATUS __nvoc_objCreate_NvDebugDump(NvDebugDump **ppThis, Dynamic *pParent, N status = __nvoc_ctor_NvDebugDump(pThis); if (status != NV_OK) goto __nvoc_objCreate_NvDebugDump_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_NvDebugDump_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(NvDebugDump)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_nv_debug_dump_nvoc.h b/src/nvidia/generated/g_nv_debug_dump_nvoc.h index 29fcc5a790..f9afe0c632 100644 --- a/src/nvidia/generated/g_nv_debug_dump_nvoc.h +++ b/src/nvidia/generated/g_nv_debug_dump_nvoc.h @@ -35,7 +35,6 @@ extern "C" { #include "gpu/eng_state.h" #include "gpu/mem_mgr/mem_desc.h" -#include "core/info_block.h" #include "nvdump.h" @@ -152,11 +151,16 @@ typedef struct _def_nvd_engine_callback { struct _def_nvd_engine_callback *pNext; // Next Engine } NVD_ENGINE_CALLBACK; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_NV_DEBUG_DUMP_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct NvDebugDump { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index 9f9b234d83..dae72b8f53 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -57,7 +57,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1349, 0x36d1, 0x17aa, "NVIDIA GeForce 930A" }, { 0x1349, 0x36d8, 0x17aa, "NVIDIA GeForce 930A" }, { 0x134B, 0x0000, 0x0000, "NVIDIA GeForce 940MX" }, - { 0x134B, 0x0008, 0x1414, "NVIDIA GeForce GPU" }, { 0x134D, 0x0000, 0x0000, "NVIDIA GeForce 940MX" }, { 0x134E, 0x0000, 0x0000, "NVIDIA GeForce 930MX" }, { 0x134F, 0x0000, 0x0000, "NVIDIA GeForce 920MX" }, @@ -833,6 +832,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20F6, 0x180a, 0x103c, "NVIDIA A800 40GB Active" }, { 0x20F6, 0x180a, 0x10de, "NVIDIA A800 40GB Active" }, { 0x20F6, 0x180a, 0x17aa, "NVIDIA A800 40GB Active" }, + { 0x20FD, 0x17f8, 0x10de, "NVIDIA AX800" }, { 0x2182, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660 Ti" }, { 0x2184, 0x0000, 0x0000, "NVIDIA GeForce GTX 1660" }, { 0x2187, 0x0000, 0x0000, "NVIDIA GeForce GTX 1650 SUPER" }, @@ -987,6 +987,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25FA, 0x0000, 0x0000, "NVIDIA RTX A2000 Embedded GPU" }, { 0x25FB, 0x0000, 0x0000, "NVIDIA RTX A500 Embedded GPU" }, { 0x2684, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090" }, + { 0x2685, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 D" }, { 0x26B1, 0x16a1, 0x1028, "NVIDIA RTX 6000 Ada Generation" }, { 0x26B1, 0x16a1, 0x103c, "NVIDIA RTX 6000 Ada Generation" }, { 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" }, @@ -995,16 +996,22 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B2, 0x17fa, 0x103c, "NVIDIA RTX 5000 Ada Generation" }, { 0x26B2, 0x17fa, 0x10de, "NVIDIA RTX 5000 Ada Generation" }, { 0x26B2, 0x17fa, 0x17aa, "NVIDIA RTX 5000 Ada Generation" }, + { 0x26B3, 0x1934, 0x103c, "NVIDIA RTX 5880 Ada Generation" }, + { 0x26B3, 0x1934, 0x10de, "NVIDIA RTX 5880 Ada Generation" }, + { 0x26B3, 0x1934, 0x17aa, "NVIDIA RTX 5880 Ada Generation" }, { 0x26B5, 0x169d, 0x10de, "NVIDIA L40" }, { 0x26B5, 0x17da, 0x10de, "NVIDIA L40" }, { 0x26B9, 0x1851, 0x10de, "NVIDIA L40S" }, { 0x26B9, 0x18cf, 0x10de, "NVIDIA L40S" }, + { 0x26BA, 0x1957, 0x10de, "NVIDIA L20" }, { 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" }, + { 0x2705, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti SUPER" }, { 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" }, { 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" }, { 0x2757, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" }, { 0x2770, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Embedded GPU" }, { 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" }, + { 0x2783, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 SUPER" }, { 0x2786, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070" }, { 0x27A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" }, { 0x27B0, 0x16fa, 0x1028, "NVIDIA RTX 4000 SFF Ada Generation" }, @@ -1019,6 +1026,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x27B2, 0x181b, 0x103c, "NVIDIA RTX 4000 Ada Generation" }, { 0x27B2, 0x181b, 0x10de, "NVIDIA RTX 4000 Ada Generation" }, { 0x27B2, 0x181b, 0x17aa, "NVIDIA RTX 4000 Ada Generation" }, + { 0x27B6, 0x1933, 0x10de, "NVIDIA L2" }, { 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" }, { 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" }, { 0x27BA, 0x0000, 0x0000, "NVIDIA RTX 4000 Ada Generation Laptop GPU" }, @@ -1513,17 +1521,6 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B7, 0x1590, 0x10DE, "NVIDIA A30-24C" }, { 0x20B7, 0x1610, 0x10DE, "NVIDIA A30-1-6CME" }, { 0x20B7, 0x183c, 0x10DE, "NVIDIA A30-2-12CME" }, - { 0x20BF, 0x4450, 0x10DE, "GRID A100B-4C" }, - { 0x20BF, 0x4451, 0x10DE, "GRID A100B-5C" }, - { 0x20BF, 0x4452, 0x10DE, "GRID A100B-8C" }, - { 0x20BF, 0x4453, 0x10DE, "GRID A100B-10C" }, - { 0x20BF, 0x4454, 0x10DE, "GRID A100B-20C" }, - { 0x20BF, 0x4455, 0x10DE, "GRID A100B-40C" }, - { 0x20BF, 0x5560, 0x10DE, "GRID A100B-1-5C" }, - { 0x20BF, 0x5561, 0x10DE, "GRID A100B-2-10C" }, - { 0x20BF, 0x5562, 0x10DE, "GRID A100B-3-20C" }, - { 0x20BF, 0x5563, 0x10DE, "GRID A100B-4-20C" }, - { 0x20BF, 0x5564, 0x10DE, "GRID A100B-7-40C" }, { 0x20F1, 0x1493, 0x10DE, "GRID A100-1-5C" }, { 0x20F1, 0x1494, 0x10DE, "GRID A100-2-10C" }, { 0x20F1, 0x1495, 0x10DE, "GRID A100-3-20C" }, @@ -1565,6 +1562,19 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20F5, 0x17ca, 0x10DE, "GRID A800D-40C" }, { 0x20F5, 0x17cb, 0x10DE, "GRID A800D-80C" }, { 0x20F5, 0x183f, 0x10DE, "GRID A800D-1-20C" }, + { 0x20F6, 0x17cc, 0x10DE, "GRID A800-1-5CME" }, + { 0x20F6, 0x17cd, 0x10DE, "GRID A800-1-5C" }, + { 0x20F6, 0x17ce, 0x10DE, "GRID A800-2-10C" }, + { 0x20F6, 0x17cf, 0x10DE, "GRID A800-3-20C" }, + { 0x20F6, 0x17d0, 0x10DE, "GRID A800-4-20C" }, + { 0x20F6, 0x17d1, 0x10DE, "GRID A800-7-40C" }, + { 0x20F6, 0x17d2, 0x10DE, "GRID A800-4C" }, + { 0x20F6, 0x17d3, 0x10DE, "GRID A800-5C" }, + { 0x20F6, 0x17d4, 0x10DE, "GRID A800-8C" }, + { 0x20F6, 0x17d5, 0x10DE, "GRID A800-10C" }, + { 0x20F6, 0x17d6, 0x10DE, "GRID A800-20C" }, + { 0x20F6, 0x17d7, 0x10DE, "GRID A800-40C" }, + { 0x20F6, 0x1843, 0x10DE, "GRID A800-1-10C" }, { 0x2230, 0x14fa, 0x10DE, "NVIDIA RTXA6000-1B" }, { 0x2230, 0x14fb, 0x10DE, "NVIDIA RTXA6000-2B" }, { 0x2230, 0x14fc, 0x10DE, "NVIDIA RTXA6000-1Q" }, @@ -1803,6 +1813,21 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2322, 0x17ee, 0x10DE, "NVIDIA H800-40C" }, { 0x2322, 0x17ef, 0x10DE, "NVIDIA H800-80C" }, { 0x2322, 0x1845, 0x10DE, "NVIDIA H800-1-20C" }, + { 0x2324, 0x18d5, 0x10DE, "NVIDIA H800XM-1-10CME" }, + { 0x2324, 0x18d6, 0x10DE, "NVIDIA H800XM-1-10C" }, + { 0x2324, 0x18d7, 0x10DE, "NVIDIA H800XM-1-20C" }, + { 0x2324, 0x18d8, 0x10DE, "NVIDIA H800XM-2-20C" }, + { 0x2324, 0x18d9, 0x10DE, "NVIDIA H800XM-3-40C" }, + { 0x2324, 0x18da, 0x10DE, "NVIDIA H800XM-4-40C" }, + { 0x2324, 0x18db, 0x10DE, "NVIDIA H800XM-7-80C" }, + { 0x2324, 0x18dc, 0x10DE, "NVIDIA H800XM-4C" }, + { 0x2324, 0x18dd, 0x10DE, "NVIDIA H800XM-5C" }, + { 0x2324, 0x18de, 0x10DE, "NVIDIA H800XM-8C" }, + { 0x2324, 0x18df, 0x10DE, "NVIDIA H800XM-10C" }, + { 0x2324, 0x18e0, 0x10DE, "NVIDIA H800XM-16C" }, + { 0x2324, 0x18e1, 0x10DE, "NVIDIA H800XM-20C" }, + { 0x2324, 0x18e2, 0x10DE, "NVIDIA H800XM-40C" }, + { 0x2324, 0x18e3, 0x10DE, "NVIDIA H800XM-80C" }, { 0x2330, 0x187a, 0x10DE, "NVIDIA H100XM-1-10CME" }, { 0x2330, 0x187b, 0x10DE, "NVIDIA H100XM-1-10C" }, { 0x2330, 0x187c, 0x10DE, "NVIDIA H100XM-1-20C" }, @@ -1833,6 +1858,32 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2331, 0x1798, 0x10DE, "NVIDIA H100-5C" }, { 0x2331, 0x17f0, 0x10DE, "NVIDIA H100-1-10CME" }, { 0x2331, 0x1844, 0x10DE, "NVIDIA H100-1-20C" }, + { 0x2337, 0x18f2, 0x10DE, "NVIDIA H100XS-1-8CME" }, + { 0x2337, 0x18f3, 0x10DE, "NVIDIA H100XS-1-8C" }, + { 0x2337, 0x18f4, 0x10DE, "NVIDIA H100XS-1-16C" }, + { 0x2337, 0x18f5, 0x10DE, "NVIDIA H100XS-2-16C" }, + { 0x2337, 0x18f6, 0x10DE, "NVIDIA H100XS-3-32C" }, + { 0x2337, 0x18f7, 0x10DE, "NVIDIA H100XS-4-32C" }, + { 0x2337, 0x18f8, 0x10DE, "NVIDIA H100XS-7-64C" }, + { 0x2337, 0x18f9, 0x10DE, "NVIDIA H100XS-4C" }, + { 0x2337, 0x18fa, 0x10DE, "NVIDIA H100XS-8C" }, + { 0x2337, 0x18fb, 0x10DE, "NVIDIA H100XS-16C" }, + { 0x2337, 0x18fc, 0x10DE, "NVIDIA H100XS-32C" }, + { 0x2337, 0x18fd, 0x10DE, "NVIDIA H100XS-64C" }, + { 0x2339, 0x18e4, 0x10DE, "NVIDIA H100XL-1-12CME" }, + { 0x2339, 0x18e5, 0x10DE, "NVIDIA H100XL-1-12C" }, + { 0x2339, 0x18e6, 0x10DE, "NVIDIA H100XL-1-24C" }, + { 0x2339, 0x18e7, 0x10DE, "NVIDIA H100XL-2-24C" }, + { 0x2339, 0x18e8, 0x10DE, "NVIDIA H100XL-3-47C" }, + { 0x2339, 0x18e9, 0x10DE, "NVIDIA H100XL-4-47C" }, + { 0x2339, 0x18ea, 0x10DE, "NVIDIA H100XL-7-94C" }, + { 0x2339, 0x18eb, 0x10DE, "NVIDIA H100XL-4C" }, + { 0x2339, 0x18ec, 0x10DE, "NVIDIA H100XL-6C" }, + { 0x2339, 0x18ed, 0x10DE, "NVIDIA H100XL-11C" }, + { 0x2339, 0x18ee, 0x10DE, "NVIDIA H100XL-15C" }, + { 0x2339, 0x18ef, 0x10DE, "NVIDIA H100XL-23C" }, + { 0x2339, 0x18f0, 0x10DE, "NVIDIA H100XL-47C" }, + { 0x2339, 0x18f1, 0x10DE, "NVIDIA H100XL-94C" }, { 0x233A, 0x1861, 0x10DE, "NVIDIA H800L-1-12CME" }, { 0x233A, 0x1862, 0x10DE, "NVIDIA H800L-1-12C" }, { 0x233A, 0x1863, 0x10DE, "NVIDIA H800L-1-24C" }, @@ -1847,6 +1898,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x233A, 0x186c, 0x10DE, "NVIDIA H800L-23C" }, { 0x233A, 0x186d, 0x10DE, "NVIDIA H800L-47C" }, { 0x233A, 0x186e, 0x10DE, "NVIDIA H800L-94C" }, + { 0x2342, 0x18c2, 0x10DE, "NVIDIA H100GL-1-12CME" }, + { 0x2342, 0x18c3, 0x10DE, "NVIDIA H100GL-1-12C" }, + { 0x2342, 0x18c4, 0x10DE, "NVIDIA H100GL-1-24C" }, + { 0x2342, 0x18c5, 0x10DE, "NVIDIA H100GL-2-24C" }, + { 0x2342, 0x18c6, 0x10DE, "NVIDIA H100GL-3-48C" }, + { 0x2342, 0x18c7, 0x10DE, "NVIDIA H100GL-4-48C" }, + { 0x2342, 0x18c8, 0x10DE, "NVIDIA H100GL-7-96C" }, + { 0x2342, 0x18c9, 0x10DE, "NVIDIA H100GL-96C" }, { 0x25B6, 0x159d, 0x10DE, "NVIDIA A16-1B" }, { 0x25B6, 0x159e, 0x10DE, "NVIDIA A16-2B" }, { 0x25B6, 0x159f, 0x10DE, "NVIDIA A16-1Q" }, @@ -2039,8 +2098,8 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x26B9, 0x189c, 0x10DE, "NVIDIA L40S-16A" }, { 0x26B9, 0x189d, 0x10DE, "NVIDIA L40S-24A" }, { 0x26B9, 0x189e, 0x10DE, "NVIDIA L40S-48A" }, - { 0x26B9, 0x189f, 0x10DE, "GeForce RTX 3050" }, - { 0x26B9, 0x18a0, 0x10DE, "GeForce RTX 3060" }, + { 0x26B9, 0x189f, 0x10DE, "NVIDIA GeForce RTX 3050" }, + { 0x26B9, 0x18a0, 0x10DE, "NVIDIA GeForce RTX 3060" }, { 0x26B9, 0x18a1, 0x10DE, "NVIDIA L40S-1" }, { 0x26B9, 0x18a2, 0x10DE, "NVIDIA L40S-2" }, { 0x26B9, 0x18a3, 0x10DE, "NVIDIA L40S-3" }, diff --git a/src/nvidia/generated/g_nvencsession_nvoc.c b/src/nvidia/generated/g_nvencsession_nvoc.c new file mode 100644 index 0000000000..b307b47374 --- /dev/null +++ b/src/nvidia/generated/g_nvencsession_nvoc.c @@ -0,0 +1,416 @@ +#define NVOC_NVENCSESSION_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_nvencsession_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x3434af = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_NvencSession; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_NvencSession(NvencSession*); +void __nvoc_init_funcTable_NvencSession(NvencSession*); +NV_STATUS __nvoc_ctor_NvencSession(NvencSession*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_NvencSession(NvencSession*); +void __nvoc_dtor_NvencSession(NvencSession*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_NvencSession; + +static const struct NVOC_RTTI __nvoc_rtti_NvencSession_NvencSession = { + /*pClassDef=*/ &__nvoc_class_def_NvencSession, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_NvencSession, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvencSession_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvencSession, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvencSession_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvencSession, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvencSession_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvencSession, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvencSession_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvencSession, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvencSession_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvencSession, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_NvencSession = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_NvencSession_NvencSession, + &__nvoc_rtti_NvencSession_GpuResource, + &__nvoc_rtti_NvencSession_RmResource, + &__nvoc_rtti_NvencSession_RmResourceCommon, + &__nvoc_rtti_NvencSession_RsResource, + &__nvoc_rtti_NvencSession_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_NvencSession = +{ + /*classInfo=*/ { + /*size=*/ sizeof(NvencSession), + /*classId=*/ classId(NvencSession), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "NvencSession", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_NvencSession, + /*pCastInfo=*/ &__nvoc_castinfo_NvencSession, + /*pExportInfo=*/ &__nvoc_export_info_NvencSession +}; + +static NvBool __nvoc_thunk_GpuResource_nvencsessionShareCallback(struct NvencSession *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvencSession_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvencsessionCheckMemInterUnmap(struct NvencSession *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvencSession_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvencsessionMapTo(struct NvencSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvencsessionGetMapAddrSpace(struct NvencSession *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvencSession_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_nvencsessionGetRefCount(struct NvencSession *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_nvencsessionAddAdditionalDependants(struct RsClient *pClient, struct NvencSession *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvencsessionControl_Prologue(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvencsessionGetRegBaseOffsetAndSize(struct NvencSession *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvencSession_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvencsessionInternalControlForward(struct NvencSession *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvencSession_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvencsessionUnmapFrom(struct NvencSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_nvencsessionControl_Epilogue(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RmResource.offset), pCallContext, pParams); +} + +static NvHandle __nvoc_thunk_GpuResource_nvencsessionGetInternalObjectHandle(struct NvencSession *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvencSession_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvencsessionControl(struct NvencSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvencSession_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvencsessionUnmap(struct NvencSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvencSession_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvencsessionGetMemInterMapParams(struct NvencSession *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvencSession_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvencsessionGetMemoryMappingDescriptor(struct NvencSession *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvencSession_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvencsessionControlFilter(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvencsessionControlSerialization_Prologue(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_nvencsessionCanCopy(struct NvencSession *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset)); +} + +static NvBool __nvoc_thunk_RsResource_nvencsessionIsPartialUnmapSupported(struct NvencSession *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_nvencsessionPreDestruct(struct NvencSession *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvencsessionIsDuplicate(struct NvencSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_nvencsessionControlSerialization_Epilogue(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvencsessionMap(struct NvencSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvencSession_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_nvencsessionAccessCallback(struct NvencSession *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvencSession_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_NvencSession[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) nvencsessionCtrlCmdNvencSwSessionUpdateInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0bc0101u, + /*paramSize=*/ sizeof(NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_NvencSession.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "nvencsessionCtrlCmdNvencSwSessionUpdateInfo" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0bc0102u, + /*paramSize=*/ sizeof(NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_NvencSession.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_NvencSession = +{ + /*numEntries=*/ 2, + /*pExportEntries=*/ __nvoc_exported_method_def_NvencSession +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_NvencSession(NvencSession *pThis) { + __nvoc_nvencsessionDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_NvencSession(NvencSession *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_NvencSession(NvencSession *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_NvencSession_fail_GpuResource; + __nvoc_init_dataField_NvencSession(pThis); + + status = __nvoc_nvencsessionConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_NvencSession_fail__init; + goto __nvoc_ctor_NvencSession_exit; // Success + +__nvoc_ctor_NvencSession_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_NvencSession_fail_GpuResource: +__nvoc_ctor_NvencSession_exit: + + return status; +} + +static void __nvoc_init_funcTable_NvencSession_1(NvencSession *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__ = &nvencsessionCtrlCmdNvencSwSessionUpdateInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__ = &nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_IMPL; +#endif + + pThis->__nvencsessionShareCallback__ = &__nvoc_thunk_GpuResource_nvencsessionShareCallback; + + pThis->__nvencsessionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_nvencsessionCheckMemInterUnmap; + + pThis->__nvencsessionMapTo__ = &__nvoc_thunk_RsResource_nvencsessionMapTo; + + pThis->__nvencsessionGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_nvencsessionGetMapAddrSpace; + + pThis->__nvencsessionGetRefCount__ = &__nvoc_thunk_RsResource_nvencsessionGetRefCount; + + pThis->__nvencsessionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nvencsessionAddAdditionalDependants; + + pThis->__nvencsessionControl_Prologue__ = &__nvoc_thunk_RmResource_nvencsessionControl_Prologue; + + pThis->__nvencsessionGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_nvencsessionGetRegBaseOffsetAndSize; + + pThis->__nvencsessionInternalControlForward__ = &__nvoc_thunk_GpuResource_nvencsessionInternalControlForward; + + pThis->__nvencsessionUnmapFrom__ = &__nvoc_thunk_RsResource_nvencsessionUnmapFrom; + + pThis->__nvencsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_nvencsessionControl_Epilogue; + + pThis->__nvencsessionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_nvencsessionGetInternalObjectHandle; + + pThis->__nvencsessionControl__ = &__nvoc_thunk_GpuResource_nvencsessionControl; + + pThis->__nvencsessionUnmap__ = &__nvoc_thunk_GpuResource_nvencsessionUnmap; + + pThis->__nvencsessionGetMemInterMapParams__ = &__nvoc_thunk_RmResource_nvencsessionGetMemInterMapParams; + + pThis->__nvencsessionGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_nvencsessionGetMemoryMappingDescriptor; + + pThis->__nvencsessionControlFilter__ = &__nvoc_thunk_RsResource_nvencsessionControlFilter; + + pThis->__nvencsessionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nvencsessionControlSerialization_Prologue; + + pThis->__nvencsessionCanCopy__ = &__nvoc_thunk_RsResource_nvencsessionCanCopy; + + pThis->__nvencsessionIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_nvencsessionIsPartialUnmapSupported; + + pThis->__nvencsessionPreDestruct__ = &__nvoc_thunk_RsResource_nvencsessionPreDestruct; + + pThis->__nvencsessionIsDuplicate__ = &__nvoc_thunk_RsResource_nvencsessionIsDuplicate; + + pThis->__nvencsessionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nvencsessionControlSerialization_Epilogue; + + pThis->__nvencsessionMap__ = &__nvoc_thunk_GpuResource_nvencsessionMap; + + pThis->__nvencsessionAccessCallback__ = &__nvoc_thunk_RmResource_nvencsessionAccessCallback; +} + +void __nvoc_init_funcTable_NvencSession(NvencSession *pThis) { + __nvoc_init_funcTable_NvencSession_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_NvencSession(NvencSession *pThis) { + pThis->__nvoc_pbase_NvencSession = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_NvencSession(pThis); +} + +NV_STATUS __nvoc_objCreate_NvencSession(NvencSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ + NV_STATUS status; + Object *pParentObj = NULL; + NvencSession *pThis; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvencSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(NvencSession)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvencSession); + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + // Link the child into the parent if there is one unless flagged not to do so. + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_NvencSession(pThis); + status = __nvoc_ctor_NvencSession(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_NvencSession_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_NvencSession_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvencSession)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_NvencSession(NvencSession **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_NvencSession(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_nvencsession_nvoc.h b/src/nvidia/generated/g_nvencsession_nvoc.h new file mode 100644 index 0000000000..7daa8c2681 --- /dev/null +++ b/src/nvidia/generated/g_nvencsession_nvoc.h @@ -0,0 +1,316 @@ +#ifndef _G_NVENCSESSION_NVOC_H_ +#define _G_NVENCSESSION_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_nvencsession_nvoc.h" + +#ifndef _NVENCSESSION_H_ +#define _NVENCSESSION_H_ + +#include "core/core.h" +#include "rmapi/client.h" +#include "gpu/gpu_resource.h" +#include "class/cla0bc.h" +#include "ctrl/ctrla0bc.h" + +struct Memory; + +#ifndef __NVOC_CLASS_Memory_TYPEDEF__ +#define __NVOC_CLASS_Memory_TYPEDEF__ +typedef struct Memory Memory; +#endif /* __NVOC_CLASS_Memory_TYPEDEF__ */ + +#ifndef __nvoc_class_id_Memory +#define __nvoc_class_id_Memory 0x4789f2 +#endif /* __nvoc_class_id_Memory */ + + + +typedef struct NvencSession NvencSession; +typedef struct NVENC_SESSION_LIST_ITEM +{ + NvHandle hClient; + NvencSession *sessionPtr; +} NVENC_SESSION_LIST_ITEM, *PNVENC_SESSION_LIST_ITEM; +MAKE_LIST(NVENC_SESSION_LIST, NVENC_SESSION_LIST_ITEM); + +typedef struct NVENC_SESSION_ENTRY +{ + NvU32 processId; + NvU32 subProcessId; + NvU32 sessionId; + NvU32 codecType; + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeFps; + NvU32 averageEncodeLatency; // average over last 60 samples if FPS exceeds 60 +} NVENC_SESSION_ENTRY, *PNVENC_SESSION_ENTRY; + + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_NVENCSESSION_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif + +struct NvencSession { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct NvencSession *__nvoc_pbase_NvencSession; + NV_STATUS (*__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__)(struct NvencSession *, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *); + NV_STATUS (*__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__)(struct NvencSession *, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS *); + NvBool (*__nvencsessionShareCallback__)(struct NvencSession *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__nvencsessionCheckMemInterUnmap__)(struct NvencSession *, NvBool); + NV_STATUS (*__nvencsessionMapTo__)(struct NvencSession *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__nvencsessionGetMapAddrSpace__)(struct NvencSession *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__nvencsessionGetRefCount__)(struct NvencSession *); + void (*__nvencsessionAddAdditionalDependants__)(struct RsClient *, struct NvencSession *, RsResourceRef *); + NV_STATUS (*__nvencsessionControl_Prologue__)(struct NvencSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvencsessionGetRegBaseOffsetAndSize__)(struct NvencSession *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__nvencsessionInternalControlForward__)(struct NvencSession *, NvU32, void *, NvU32); + NV_STATUS (*__nvencsessionUnmapFrom__)(struct NvencSession *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__nvencsessionControl_Epilogue__)(struct NvencSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvHandle (*__nvencsessionGetInternalObjectHandle__)(struct NvencSession *); + NV_STATUS (*__nvencsessionControl__)(struct NvencSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvencsessionUnmap__)(struct NvencSession *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__nvencsessionGetMemInterMapParams__)(struct NvencSession *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__nvencsessionGetMemoryMappingDescriptor__)(struct NvencSession *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__nvencsessionControlFilter__)(struct NvencSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvencsessionControlSerialization_Prologue__)(struct NvencSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__nvencsessionCanCopy__)(struct NvencSession *); + NvBool (*__nvencsessionIsPartialUnmapSupported__)(struct NvencSession *); + void (*__nvencsessionPreDestruct__)(struct NvencSession *); + NV_STATUS (*__nvencsessionIsDuplicate__)(struct NvencSession *, NvHandle, NvBool *); + void (*__nvencsessionControlSerialization_Epilogue__)(struct NvencSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvencsessionMap__)(struct NvencSession *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__nvencsessionAccessCallback__)(struct NvencSession *, struct RsClient *, void *, RsAccessRight); + NvHandle handle; + NVENC_SESSION_ENTRY nvencSessionEntry; + NvU32 version; + struct Memory *pMemory; + NvP64 pSessionStatsBuffer; + NvP64 pPriv; + NvU32 lastProcessedIndex; + NvU32 lastProcessedFrameId; + NvU64 lastProcessedFrameTS; +}; + +#ifndef __NVOC_CLASS_NvencSession_TYPEDEF__ +#define __NVOC_CLASS_NvencSession_TYPEDEF__ +typedef struct NvencSession NvencSession; +#endif /* __NVOC_CLASS_NvencSession_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NvencSession +#define __nvoc_class_id_NvencSession 0x3434af +#endif /* __nvoc_class_id_NvencSession */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_NvencSession; + +#define __staticCast_NvencSession(pThis) \ + ((pThis)->__nvoc_pbase_NvencSession) + +#ifdef __nvoc_nvencsession_h_disabled +#define __dynamicCast_NvencSession(pThis) ((NvencSession*)NULL) +#else //__nvoc_nvencsession_h_disabled +#define __dynamicCast_NvencSession(pThis) \ + ((NvencSession*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(NvencSession))) +#endif //__nvoc_nvencsession_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_NvencSession(NvencSession**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_NvencSession(NvencSession**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_NvencSession(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_NvencSession((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define nvencsessionCtrlCmdNvencSwSessionUpdateInfo(pNvencSession, pParams) nvencsessionCtrlCmdNvencSwSessionUpdateInfo_DISPATCH(pNvencSession, pParams) +#define nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2(pNvencSession, pParams) nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_DISPATCH(pNvencSession, pParams) +#define nvencsessionShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) nvencsessionShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define nvencsessionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) nvencsessionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define nvencsessionMapTo(pResource, pParams) nvencsessionMapTo_DISPATCH(pResource, pParams) +#define nvencsessionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) nvencsessionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define nvencsessionGetRefCount(pResource) nvencsessionGetRefCount_DISPATCH(pResource) +#define nvencsessionAddAdditionalDependants(pClient, pResource, pReference) nvencsessionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define nvencsessionControl_Prologue(pResource, pCallContext, pParams) nvencsessionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define nvencsessionGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) nvencsessionGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define nvencsessionInternalControlForward(pGpuResource, command, pParams, size) nvencsessionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define nvencsessionUnmapFrom(pResource, pParams) nvencsessionUnmapFrom_DISPATCH(pResource, pParams) +#define nvencsessionControl_Epilogue(pResource, pCallContext, pParams) nvencsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define nvencsessionGetInternalObjectHandle(pGpuResource) nvencsessionGetInternalObjectHandle_DISPATCH(pGpuResource) +#define nvencsessionControl(pGpuResource, pCallContext, pParams) nvencsessionControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define nvencsessionUnmap(pGpuResource, pCallContext, pCpuMapping) nvencsessionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define nvencsessionGetMemInterMapParams(pRmResource, pParams) nvencsessionGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define nvencsessionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) nvencsessionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define nvencsessionControlFilter(pResource, pCallContext, pParams) nvencsessionControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define nvencsessionControlSerialization_Prologue(pResource, pCallContext, pParams) nvencsessionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define nvencsessionCanCopy(pResource) nvencsessionCanCopy_DISPATCH(pResource) +#define nvencsessionIsPartialUnmapSupported(pResource) nvencsessionIsPartialUnmapSupported_DISPATCH(pResource) +#define nvencsessionPreDestruct(pResource) nvencsessionPreDestruct_DISPATCH(pResource) +#define nvencsessionIsDuplicate(pResource, hMemory, pDuplicate) nvencsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define nvencsessionControlSerialization_Epilogue(pResource, pCallContext, pParams) nvencsessionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define nvencsessionMap(pGpuResource, pCallContext, pParams, pCpuMapping) nvencsessionMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define nvencsessionAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) nvencsessionAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS nvencsessionCtrlCmdNvencSwSessionUpdateInfo_IMPL(struct NvencSession *pNvencSession, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams); + +static inline NV_STATUS nvencsessionCtrlCmdNvencSwSessionUpdateInfo_DISPATCH(struct NvencSession *pNvencSession, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams) { + return pNvencSession->__nvencsessionCtrlCmdNvencSwSessionUpdateInfo__(pNvencSession, pParams); +} + +NV_STATUS nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_IMPL(struct NvencSession *pNvencSession, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS *pParams); + +static inline NV_STATUS nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_DISPATCH(struct NvencSession *pNvencSession, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS *pParams) { + return pNvencSession->__nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2__(pNvencSession, pParams); +} + +static inline NvBool nvencsessionShareCallback_DISPATCH(struct NvencSession *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__nvencsessionShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS nvencsessionCheckMemInterUnmap_DISPATCH(struct NvencSession *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__nvencsessionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS nvencsessionMapTo_DISPATCH(struct NvencSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__nvencsessionMapTo__(pResource, pParams); +} + +static inline NV_STATUS nvencsessionGetMapAddrSpace_DISPATCH(struct NvencSession *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__nvencsessionGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 nvencsessionGetRefCount_DISPATCH(struct NvencSession *pResource) { + return pResource->__nvencsessionGetRefCount__(pResource); +} + +static inline void nvencsessionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NvencSession *pResource, RsResourceRef *pReference) { + pResource->__nvencsessionAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS nvencsessionControl_Prologue_DISPATCH(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvencsessionControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS nvencsessionGetRegBaseOffsetAndSize_DISPATCH(struct NvencSession *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__nvencsessionGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS nvencsessionInternalControlForward_DISPATCH(struct NvencSession *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__nvencsessionInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS nvencsessionUnmapFrom_DISPATCH(struct NvencSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__nvencsessionUnmapFrom__(pResource, pParams); +} + +static inline void nvencsessionControl_Epilogue_DISPATCH(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvencsessionControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NvHandle nvencsessionGetInternalObjectHandle_DISPATCH(struct NvencSession *pGpuResource) { + return pGpuResource->__nvencsessionGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS nvencsessionControl_DISPATCH(struct NvencSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__nvencsessionControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS nvencsessionUnmap_DISPATCH(struct NvencSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__nvencsessionUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS nvencsessionGetMemInterMapParams_DISPATCH(struct NvencSession *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__nvencsessionGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS nvencsessionGetMemoryMappingDescriptor_DISPATCH(struct NvencSession *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__nvencsessionGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS nvencsessionControlFilter_DISPATCH(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvencsessionControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS nvencsessionControlSerialization_Prologue_DISPATCH(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvencsessionControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool nvencsessionCanCopy_DISPATCH(struct NvencSession *pResource) { + return pResource->__nvencsessionCanCopy__(pResource); +} + +static inline NvBool nvencsessionIsPartialUnmapSupported_DISPATCH(struct NvencSession *pResource) { + return pResource->__nvencsessionIsPartialUnmapSupported__(pResource); +} + +static inline void nvencsessionPreDestruct_DISPATCH(struct NvencSession *pResource) { + pResource->__nvencsessionPreDestruct__(pResource); +} + +static inline NV_STATUS nvencsessionIsDuplicate_DISPATCH(struct NvencSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__nvencsessionIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void nvencsessionControlSerialization_Epilogue_DISPATCH(struct NvencSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvencsessionControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS nvencsessionMap_DISPATCH(struct NvencSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__nvencsessionMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool nvencsessionAccessCallback_DISPATCH(struct NvencSession *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__nvencsessionAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS nvencsessionConstruct_IMPL(struct NvencSession *arg_pNvencSession, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_nvencsessionConstruct(arg_pNvencSession, arg_pCallContext, arg_pParams) nvencsessionConstruct_IMPL(arg_pNvencSession, arg_pCallContext, arg_pParams) +void nvencsessionDestruct_IMPL(struct NvencSession *pNvencSession); + +#define __nvoc_nvencsessionDestruct(pNvencSession) nvencsessionDestruct_IMPL(pNvencSession) +#undef PRIVATE_FIELD + + +#endif // _NVENCSESSION_H_ + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_NVENCSESSION_NVOC_H_ diff --git a/src/nvidia/generated/g_nvfbc_session_nvoc.c b/src/nvidia/generated/g_nvfbc_session_nvoc.c new file mode 100644 index 0000000000..7e557b6a58 --- /dev/null +++ b/src/nvidia/generated/g_nvfbc_session_nvoc.c @@ -0,0 +1,397 @@ +#define NVOC_NVFBC_SESSION_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_nvfbc_session_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0xcbde75 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_NvfbcSession; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_NvfbcSession(NvfbcSession*); +void __nvoc_init_funcTable_NvfbcSession(NvfbcSession*); +NV_STATUS __nvoc_ctor_NvfbcSession(NvfbcSession*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_NvfbcSession(NvfbcSession*); +void __nvoc_dtor_NvfbcSession(NvfbcSession*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_NvfbcSession; + +static const struct NVOC_RTTI __nvoc_rtti_NvfbcSession_NvfbcSession = { + /*pClassDef=*/ &__nvoc_class_def_NvfbcSession, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_NvfbcSession, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvfbcSession_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvfbcSession, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvfbcSession_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvfbcSession, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvfbcSession_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvfbcSession, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvfbcSession_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvfbcSession, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_NvfbcSession_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(NvfbcSession, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_NvfbcSession = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_NvfbcSession_NvfbcSession, + &__nvoc_rtti_NvfbcSession_GpuResource, + &__nvoc_rtti_NvfbcSession_RmResource, + &__nvoc_rtti_NvfbcSession_RmResourceCommon, + &__nvoc_rtti_NvfbcSession_RsResource, + &__nvoc_rtti_NvfbcSession_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_NvfbcSession = +{ + /*classInfo=*/ { + /*size=*/ sizeof(NvfbcSession), + /*classId=*/ classId(NvfbcSession), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "NvfbcSession", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_NvfbcSession, + /*pCastInfo=*/ &__nvoc_castinfo_NvfbcSession, + /*pExportInfo=*/ &__nvoc_export_info_NvfbcSession +}; + +static NvBool __nvoc_thunk_GpuResource_nvfbcsessionShareCallback(struct NvfbcSession *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvfbcSession_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvfbcsessionCheckMemInterUnmap(struct NvfbcSession *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvfbcSession_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvfbcsessionMapTo(struct NvfbcSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvfbcsessionGetMapAddrSpace(struct NvfbcSession *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvfbcSession_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_nvfbcsessionGetRefCount(struct NvfbcSession *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_nvfbcsessionAddAdditionalDependants(struct RsClient *pClient, struct NvfbcSession *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvfbcsessionControl_Prologue(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvfbcsessionGetRegBaseOffsetAndSize(struct NvfbcSession *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvfbcSession_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvfbcsessionInternalControlForward(struct NvfbcSession *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvfbcSession_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvfbcsessionUnmapFrom(struct NvfbcSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_nvfbcsessionControl_Epilogue(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RmResource.offset), pCallContext, pParams); +} + +static NvHandle __nvoc_thunk_GpuResource_nvfbcsessionGetInternalObjectHandle(struct NvfbcSession *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvfbcSession_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvfbcsessionControl(struct NvfbcSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvfbcSession_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvfbcsessionUnmap(struct NvfbcSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvfbcSession_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvfbcsessionGetMemInterMapParams(struct NvfbcSession *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvfbcSession_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvfbcsessionGetMemoryMappingDescriptor(struct NvfbcSession *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_NvfbcSession_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvfbcsessionControlFilter(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_nvfbcsessionControlSerialization_Prologue(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_nvfbcsessionCanCopy(struct NvfbcSession *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset)); +} + +static NvBool __nvoc_thunk_RsResource_nvfbcsessionIsPartialUnmapSupported(struct NvfbcSession *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_nvfbcsessionPreDestruct(struct NvfbcSession *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_nvfbcsessionIsDuplicate(struct NvfbcSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_nvfbcsessionControlSerialization_Epilogue(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_nvfbcsessionMap(struct NvfbcSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_NvfbcSession_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_nvfbcsessionAccessCallback(struct NvfbcSession *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_NvfbcSession_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_NvfbcSession[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0bd0101u, + /*paramSize=*/ sizeof(NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_NvfbcSession.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_NvfbcSession = +{ + /*numEntries=*/ 1, + /*pExportEntries=*/ __nvoc_exported_method_def_NvfbcSession +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_NvfbcSession(NvfbcSession *pThis) { + __nvoc_nvfbcsessionDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_NvfbcSession(NvfbcSession *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_NvfbcSession(NvfbcSession *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_NvfbcSession_fail_GpuResource; + __nvoc_init_dataField_NvfbcSession(pThis); + + status = __nvoc_nvfbcsessionConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_NvfbcSession_fail__init; + goto __nvoc_ctor_NvfbcSession_exit; // Success + +__nvoc_ctor_NvfbcSession_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_NvfbcSession_fail_GpuResource: +__nvoc_ctor_NvfbcSession_exit: + + return status; +} + +static void __nvoc_init_funcTable_NvfbcSession_1(NvfbcSession *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo__ = &nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo_IMPL; +#endif + + pThis->__nvfbcsessionShareCallback__ = &__nvoc_thunk_GpuResource_nvfbcsessionShareCallback; + + pThis->__nvfbcsessionCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_nvfbcsessionCheckMemInterUnmap; + + pThis->__nvfbcsessionMapTo__ = &__nvoc_thunk_RsResource_nvfbcsessionMapTo; + + pThis->__nvfbcsessionGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_nvfbcsessionGetMapAddrSpace; + + pThis->__nvfbcsessionGetRefCount__ = &__nvoc_thunk_RsResource_nvfbcsessionGetRefCount; + + pThis->__nvfbcsessionAddAdditionalDependants__ = &__nvoc_thunk_RsResource_nvfbcsessionAddAdditionalDependants; + + pThis->__nvfbcsessionControl_Prologue__ = &__nvoc_thunk_RmResource_nvfbcsessionControl_Prologue; + + pThis->__nvfbcsessionGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_nvfbcsessionGetRegBaseOffsetAndSize; + + pThis->__nvfbcsessionInternalControlForward__ = &__nvoc_thunk_GpuResource_nvfbcsessionInternalControlForward; + + pThis->__nvfbcsessionUnmapFrom__ = &__nvoc_thunk_RsResource_nvfbcsessionUnmapFrom; + + pThis->__nvfbcsessionControl_Epilogue__ = &__nvoc_thunk_RmResource_nvfbcsessionControl_Epilogue; + + pThis->__nvfbcsessionGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_nvfbcsessionGetInternalObjectHandle; + + pThis->__nvfbcsessionControl__ = &__nvoc_thunk_GpuResource_nvfbcsessionControl; + + pThis->__nvfbcsessionUnmap__ = &__nvoc_thunk_GpuResource_nvfbcsessionUnmap; + + pThis->__nvfbcsessionGetMemInterMapParams__ = &__nvoc_thunk_RmResource_nvfbcsessionGetMemInterMapParams; + + pThis->__nvfbcsessionGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_nvfbcsessionGetMemoryMappingDescriptor; + + pThis->__nvfbcsessionControlFilter__ = &__nvoc_thunk_RsResource_nvfbcsessionControlFilter; + + pThis->__nvfbcsessionControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_nvfbcsessionControlSerialization_Prologue; + + pThis->__nvfbcsessionCanCopy__ = &__nvoc_thunk_RsResource_nvfbcsessionCanCopy; + + pThis->__nvfbcsessionIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_nvfbcsessionIsPartialUnmapSupported; + + pThis->__nvfbcsessionPreDestruct__ = &__nvoc_thunk_RsResource_nvfbcsessionPreDestruct; + + pThis->__nvfbcsessionIsDuplicate__ = &__nvoc_thunk_RsResource_nvfbcsessionIsDuplicate; + + pThis->__nvfbcsessionControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_nvfbcsessionControlSerialization_Epilogue; + + pThis->__nvfbcsessionMap__ = &__nvoc_thunk_GpuResource_nvfbcsessionMap; + + pThis->__nvfbcsessionAccessCallback__ = &__nvoc_thunk_RmResource_nvfbcsessionAccessCallback; +} + +void __nvoc_init_funcTable_NvfbcSession(NvfbcSession *pThis) { + __nvoc_init_funcTable_NvfbcSession_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_NvfbcSession(NvfbcSession *pThis) { + pThis->__nvoc_pbase_NvfbcSession = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_NvfbcSession(pThis); +} + +NV_STATUS __nvoc_objCreate_NvfbcSession(NvfbcSession **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ + NV_STATUS status; + Object *pParentObj = NULL; + NvfbcSession *pThis; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(NvfbcSession), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(NvfbcSession)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_NvfbcSession); + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + // Link the child into the parent if there is one unless flagged not to do so. + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_NvfbcSession(pThis); + status = __nvoc_ctor_NvfbcSession(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_NvfbcSession_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_NvfbcSession_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(NvfbcSession)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_NvfbcSession(NvfbcSession **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_NvfbcSession(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_nvfbc_session_nvoc.h b/src/nvidia/generated/g_nvfbc_session_nvoc.h new file mode 100644 index 0000000000..7a790b5c13 --- /dev/null +++ b/src/nvidia/generated/g_nvfbc_session_nvoc.h @@ -0,0 +1,302 @@ +#ifndef _G_NVFBC_SESSION_NVOC_H_ +#define _G_NVFBC_SESSION_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_nvfbc_session_nvoc.h" + +#ifndef _NVFBCSESSION_H_ +#define _NVFBCSESSION_H_ + +#include "core/core.h" + +#include "rmapi/client.h" +#include "gpu/gpu_resource.h" +#include "class/cla0bd.h" +#include "ctrl/ctrla0bd.h" + +#include "rmapi/control.h" + +#define SESSION_UPDATE_TIMESTAMP_UNINITIALIZED 0 + +typedef struct NvfbcSession NvfbcSession; +typedef struct NVFBC_SESSION_LIST_ITEM +{ + NvHandle hClient; + NvfbcSession *sessionPtr; +} NVFBC_SESSION_LIST_ITEM, *PNVFBC_SESSION_LIST_ITEM; + +MAKE_LIST(NVFBC_SESSION_LIST, NVFBC_SESSION_LIST_ITEM); + +typedef struct NVFBC_SESSION_ENTRY +{ + NvU32 processId; + NvU32 vgpuInstanceId; + NvU32 sessionId; + NvU32 displayOrdinal; + NvU32 sessionType; + NvU32 sessionFlags; + NvU32 hMaxResolution; + NvU32 vMaxResolution; + NvU32 hResolution; + NvU32 vResolution; + NvU32 totalGrabCalls; + NvU32 averageFPS; + NvU32 averageLatency; // average over last 60 samples if FPS exceeds 60 + NvU64 lastUpdateTimeStamp; // timestamp of last session update call +} NVFBC_SESSION_ENTRY, *PNVFBC_SESSION_ENTRY; + + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_NVFBC_SESSION_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif + +struct NvfbcSession { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct NvfbcSession *__nvoc_pbase_NvfbcSession; + NV_STATUS (*__nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo__)(struct NvfbcSession *, NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS *); + NvBool (*__nvfbcsessionShareCallback__)(struct NvfbcSession *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__nvfbcsessionCheckMemInterUnmap__)(struct NvfbcSession *, NvBool); + NV_STATUS (*__nvfbcsessionMapTo__)(struct NvfbcSession *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__nvfbcsessionGetMapAddrSpace__)(struct NvfbcSession *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__nvfbcsessionGetRefCount__)(struct NvfbcSession *); + void (*__nvfbcsessionAddAdditionalDependants__)(struct RsClient *, struct NvfbcSession *, RsResourceRef *); + NV_STATUS (*__nvfbcsessionControl_Prologue__)(struct NvfbcSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvfbcsessionGetRegBaseOffsetAndSize__)(struct NvfbcSession *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__nvfbcsessionInternalControlForward__)(struct NvfbcSession *, NvU32, void *, NvU32); + NV_STATUS (*__nvfbcsessionUnmapFrom__)(struct NvfbcSession *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__nvfbcsessionControl_Epilogue__)(struct NvfbcSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvHandle (*__nvfbcsessionGetInternalObjectHandle__)(struct NvfbcSession *); + NV_STATUS (*__nvfbcsessionControl__)(struct NvfbcSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvfbcsessionUnmap__)(struct NvfbcSession *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__nvfbcsessionGetMemInterMapParams__)(struct NvfbcSession *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__nvfbcsessionGetMemoryMappingDescriptor__)(struct NvfbcSession *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__nvfbcsessionControlFilter__)(struct NvfbcSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvfbcsessionControlSerialization_Prologue__)(struct NvfbcSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__nvfbcsessionCanCopy__)(struct NvfbcSession *); + NvBool (*__nvfbcsessionIsPartialUnmapSupported__)(struct NvfbcSession *); + void (*__nvfbcsessionPreDestruct__)(struct NvfbcSession *); + NV_STATUS (*__nvfbcsessionIsDuplicate__)(struct NvfbcSession *, NvHandle, NvBool *); + void (*__nvfbcsessionControlSerialization_Epilogue__)(struct NvfbcSession *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__nvfbcsessionMap__)(struct NvfbcSession *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__nvfbcsessionAccessCallback__)(struct NvfbcSession *, struct RsClient *, void *, RsAccessRight); + NVFBC_SESSION_ENTRY nvfbcSessionEntry; +}; + +#ifndef __NVOC_CLASS_NvfbcSession_TYPEDEF__ +#define __NVOC_CLASS_NvfbcSession_TYPEDEF__ +typedef struct NvfbcSession NvfbcSession; +#endif /* __NVOC_CLASS_NvfbcSession_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NvfbcSession +#define __nvoc_class_id_NvfbcSession 0xcbde75 +#endif /* __nvoc_class_id_NvfbcSession */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_NvfbcSession; + +#define __staticCast_NvfbcSession(pThis) \ + ((pThis)->__nvoc_pbase_NvfbcSession) + +#ifdef __nvoc_nvfbc_session_h_disabled +#define __dynamicCast_NvfbcSession(pThis) ((NvfbcSession*)NULL) +#else //__nvoc_nvfbc_session_h_disabled +#define __dynamicCast_NvfbcSession(pThis) \ + ((NvfbcSession*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(NvfbcSession))) +#endif //__nvoc_nvfbc_session_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_NvfbcSession(NvfbcSession**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_NvfbcSession(NvfbcSession**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_NvfbcSession(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_NvfbcSession((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo(pNvfbcSession, pParams) nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo_DISPATCH(pNvfbcSession, pParams) +#define nvfbcsessionShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) nvfbcsessionShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define nvfbcsessionCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) nvfbcsessionCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define nvfbcsessionMapTo(pResource, pParams) nvfbcsessionMapTo_DISPATCH(pResource, pParams) +#define nvfbcsessionGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) nvfbcsessionGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define nvfbcsessionGetRefCount(pResource) nvfbcsessionGetRefCount_DISPATCH(pResource) +#define nvfbcsessionAddAdditionalDependants(pClient, pResource, pReference) nvfbcsessionAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define nvfbcsessionControl_Prologue(pResource, pCallContext, pParams) nvfbcsessionControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define nvfbcsessionGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) nvfbcsessionGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define nvfbcsessionInternalControlForward(pGpuResource, command, pParams, size) nvfbcsessionInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define nvfbcsessionUnmapFrom(pResource, pParams) nvfbcsessionUnmapFrom_DISPATCH(pResource, pParams) +#define nvfbcsessionControl_Epilogue(pResource, pCallContext, pParams) nvfbcsessionControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define nvfbcsessionGetInternalObjectHandle(pGpuResource) nvfbcsessionGetInternalObjectHandle_DISPATCH(pGpuResource) +#define nvfbcsessionControl(pGpuResource, pCallContext, pParams) nvfbcsessionControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define nvfbcsessionUnmap(pGpuResource, pCallContext, pCpuMapping) nvfbcsessionUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define nvfbcsessionGetMemInterMapParams(pRmResource, pParams) nvfbcsessionGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define nvfbcsessionGetMemoryMappingDescriptor(pRmResource, ppMemDesc) nvfbcsessionGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define nvfbcsessionControlFilter(pResource, pCallContext, pParams) nvfbcsessionControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define nvfbcsessionControlSerialization_Prologue(pResource, pCallContext, pParams) nvfbcsessionControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define nvfbcsessionCanCopy(pResource) nvfbcsessionCanCopy_DISPATCH(pResource) +#define nvfbcsessionIsPartialUnmapSupported(pResource) nvfbcsessionIsPartialUnmapSupported_DISPATCH(pResource) +#define nvfbcsessionPreDestruct(pResource) nvfbcsessionPreDestruct_DISPATCH(pResource) +#define nvfbcsessionIsDuplicate(pResource, hMemory, pDuplicate) nvfbcsessionIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define nvfbcsessionControlSerialization_Epilogue(pResource, pCallContext, pParams) nvfbcsessionControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define nvfbcsessionMap(pGpuResource, pCallContext, pParams, pCpuMapping) nvfbcsessionMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define nvfbcsessionAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) nvfbcsessionAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo_IMPL(struct NvfbcSession *pNvfbcSession, NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS *pParams); + +static inline NV_STATUS nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo_DISPATCH(struct NvfbcSession *pNvfbcSession, NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS *pParams) { + return pNvfbcSession->__nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo__(pNvfbcSession, pParams); +} + +static inline NvBool nvfbcsessionShareCallback_DISPATCH(struct NvfbcSession *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__nvfbcsessionShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS nvfbcsessionCheckMemInterUnmap_DISPATCH(struct NvfbcSession *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__nvfbcsessionCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS nvfbcsessionMapTo_DISPATCH(struct NvfbcSession *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__nvfbcsessionMapTo__(pResource, pParams); +} + +static inline NV_STATUS nvfbcsessionGetMapAddrSpace_DISPATCH(struct NvfbcSession *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__nvfbcsessionGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 nvfbcsessionGetRefCount_DISPATCH(struct NvfbcSession *pResource) { + return pResource->__nvfbcsessionGetRefCount__(pResource); +} + +static inline void nvfbcsessionAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct NvfbcSession *pResource, RsResourceRef *pReference) { + pResource->__nvfbcsessionAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS nvfbcsessionControl_Prologue_DISPATCH(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvfbcsessionControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS nvfbcsessionGetRegBaseOffsetAndSize_DISPATCH(struct NvfbcSession *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__nvfbcsessionGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS nvfbcsessionInternalControlForward_DISPATCH(struct NvfbcSession *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__nvfbcsessionInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS nvfbcsessionUnmapFrom_DISPATCH(struct NvfbcSession *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__nvfbcsessionUnmapFrom__(pResource, pParams); +} + +static inline void nvfbcsessionControl_Epilogue_DISPATCH(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvfbcsessionControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NvHandle nvfbcsessionGetInternalObjectHandle_DISPATCH(struct NvfbcSession *pGpuResource) { + return pGpuResource->__nvfbcsessionGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS nvfbcsessionControl_DISPATCH(struct NvfbcSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__nvfbcsessionControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS nvfbcsessionUnmap_DISPATCH(struct NvfbcSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__nvfbcsessionUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS nvfbcsessionGetMemInterMapParams_DISPATCH(struct NvfbcSession *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__nvfbcsessionGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS nvfbcsessionGetMemoryMappingDescriptor_DISPATCH(struct NvfbcSession *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__nvfbcsessionGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS nvfbcsessionControlFilter_DISPATCH(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvfbcsessionControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS nvfbcsessionControlSerialization_Prologue_DISPATCH(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__nvfbcsessionControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool nvfbcsessionCanCopy_DISPATCH(struct NvfbcSession *pResource) { + return pResource->__nvfbcsessionCanCopy__(pResource); +} + +static inline NvBool nvfbcsessionIsPartialUnmapSupported_DISPATCH(struct NvfbcSession *pResource) { + return pResource->__nvfbcsessionIsPartialUnmapSupported__(pResource); +} + +static inline void nvfbcsessionPreDestruct_DISPATCH(struct NvfbcSession *pResource) { + pResource->__nvfbcsessionPreDestruct__(pResource); +} + +static inline NV_STATUS nvfbcsessionIsDuplicate_DISPATCH(struct NvfbcSession *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__nvfbcsessionIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void nvfbcsessionControlSerialization_Epilogue_DISPATCH(struct NvfbcSession *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__nvfbcsessionControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS nvfbcsessionMap_DISPATCH(struct NvfbcSession *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__nvfbcsessionMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool nvfbcsessionAccessCallback_DISPATCH(struct NvfbcSession *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__nvfbcsessionAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS nvfbcsessionConstruct_IMPL(struct NvfbcSession *arg_pNvfbcSession, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_nvfbcsessionConstruct(arg_pNvfbcSession, arg_pCallContext, arg_pParams) nvfbcsessionConstruct_IMPL(arg_pNvfbcSession, arg_pCallContext, arg_pParams) +void nvfbcsessionDestruct_IMPL(struct NvfbcSession *pNvfbcSession); + +#define __nvoc_nvfbcsessionDestruct(pNvfbcSession) nvfbcsessionDestruct_IMPL(pNvfbcSession) +#undef PRIVATE_FIELD + + +NV_STATUS nvA0BDCtrlCmdNvFBCSwSessionUpdateInfo(RmCtrlParams *pRmCtrlParams); +NvBool nvfbcIsSessionDataStale(NvU64 lastUpdateTimeStamp); + +#endif // _NVFBCSESSION_H_ + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_NVFBC_SESSION_NVOC_H_ diff --git a/src/nvidia/generated/g_object_nvoc.c b/src/nvidia/generated/g_object_nvoc.c index c4c08b8542..404d278a2d 100644 --- a/src/nvidia/generated/g_object_nvoc.c +++ b/src/nvidia/generated/g_object_nvoc.c @@ -85,21 +85,26 @@ void __nvoc_init_Object(Object *pThis) { __nvoc_init_funcTable_Object(pThis); } -NV_STATUS __nvoc_objCreate_Object(Object **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_Object(Object **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Object *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Object), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Object)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Object); pThis->createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -114,16 +119,25 @@ NV_STATUS __nvoc_objCreate_Object(Object **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_Object(pThis); if (status != NV_OK) goto __nvoc_objCreate_Object_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Object_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, pThis); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Object)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_object_nvoc.h b/src/nvidia/generated/g_object_nvoc.h index 8da263c56e..ff1237acf6 100644 --- a/src/nvidia/generated/g_object_nvoc.h +++ b/src/nvidia/generated/g_object_nvoc.h @@ -68,11 +68,16 @@ struct NVOC_CHILD_TREE }; //! The base class of all instantiable NVOC objects. + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_OBJECT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Object { const struct NVOC_RTTI *__nvoc_rtti; struct Object *__nvoc_pbase_Object; diff --git a/src/nvidia/generated/g_objgpumon_nvoc.c b/src/nvidia/generated/g_objgpumon_nvoc.c index 9c39327829..5777352e8b 100644 --- a/src/nvidia/generated/g_objgpumon_nvoc.c +++ b/src/nvidia/generated/g_objgpumon_nvoc.c @@ -207,23 +207,31 @@ void __nvoc_init_OBJGPUMON(OBJGPUMON *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_OBJGPUMON(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJGPUMON *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJGPUMON), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJGPUMON)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJGPUMON); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -241,16 +249,25 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_OBJGPUMON(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_OBJGPUMON_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJGPUMON_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJGPUMON)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_objgpumon_nvoc.h b/src/nvidia/generated/g_objgpumon_nvoc.h index 3c1e1b2f5c..ffaf59531d 100644 --- a/src/nvidia/generated/g_objgpumon_nvoc.h +++ b/src/nvidia/generated/g_objgpumon_nvoc.h @@ -31,8 +31,8 @@ extern "C" { #include "g_objgpumon_nvoc.h" -#ifndef _OBJGPUMON_H_ -#define _OBJGPUMON_H_ +#ifndef OBJGPUMON_H +#define OBJGPUMON_H /****************** Resource Manager Defines and Structures *****************\ * * @@ -46,13 +46,17 @@ extern "C" { #include "ctrl/ctrl2080/ctrl2080perf.h" -typedef struct OBJGPUMON *POBJGPUMON; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_OBJGPUMON_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJGPUMON { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -202,7 +206,7 @@ static inline NV_STATUS gpumonGetPerfmonUtilSamples(struct OBJGPU *pGpu, struct #undef PRIVATE_FIELD -#endif //_OBJGPUMON_H_ +#endif //OBJGPUMON_H #ifdef __cplusplus } // extern "C" diff --git a/src/nvidia/generated/g_objsweng_nvoc.c b/src/nvidia/generated/g_objsweng_nvoc.c index e63e88e7ed..833f274e77 100644 --- a/src/nvidia/generated/g_objsweng_nvoc.c +++ b/src/nvidia/generated/g_objsweng_nvoc.c @@ -199,21 +199,26 @@ void __nvoc_init_OBJSWENG(OBJSWENG *pThis) { __nvoc_init_funcTable_OBJSWENG(pThis); } -NV_STATUS __nvoc_objCreate_OBJSWENG(OBJSWENG **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJSWENG(OBJSWENG **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJSWENG *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJSWENG), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJSWENG)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJSWENG); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -228,16 +233,25 @@ NV_STATUS __nvoc_objCreate_OBJSWENG(OBJSWENG **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_OBJSWENG(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJSWENG_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJSWENG_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJSWENG)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_objsweng_nvoc.h b/src/nvidia/generated/g_objsweng_nvoc.h index b4d62d1707..f29eff5859 100644 --- a/src/nvidia/generated/g_objsweng_nvoc.h +++ b/src/nvidia/generated/g_objsweng_nvoc.h @@ -47,11 +47,16 @@ extern "C" { typedef struct OBJSWENG *POBJSWENG; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_OBJSWENG_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJSWENG { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; diff --git a/src/nvidia/generated/g_objtmr_nvoc.c b/src/nvidia/generated/g_objtmr_nvoc.c index b34b186efb..0339183ce5 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.c +++ b/src/nvidia/generated/g_objtmr_nvoc.c @@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTMR = /*pExportInfo=*/ &__nvoc_export_info_OBJTMR }; -static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[168]) { +static void __nvoc_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[171]) { tmrRegisterIntrService(pGpu, (struct OBJTMR *)(((unsigned char *)pTmr) - __nvoc_rtti_OBJTMR_IntrService.offset), pRecords); } @@ -196,6 +196,13 @@ void __nvoc_init_dataField_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner { pThis->setProperty(pThis, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS, ((NvBool)(0 == 0))); } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + // default + { + pThis->setProperty(pThis, PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS, ((NvBool)(0 != 0))); + } + } pThis->setProperty(pThis, PDB_PROP_TMR_USE_PTIMER_FOR_OSTIMER_CALLBACKS, (0)); pThis->setProperty(pThis, PDB_PROP_TMR_USE_POLLING_FOR_CALLBACKS, (0)); @@ -242,12 +249,36 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal function -- tmrDelay + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__tmrDelay__ = &tmrDelay_PTIMER; + } + else + { + pThis->__tmrDelay__ = &tmrDelay_OSTIMER; + } + pThis->__tmrRegisterIntrService__ = &tmrRegisterIntrService_IMPL; pThis->__tmrClearInterrupt__ = &tmrClearInterrupt_IMPL; // Hal function -- tmrServiceInterrupt - pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_56cd7a; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_TU102; + } + else + { + pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_GA100; + } + } + else + { + pThis->__tmrServiceInterrupt__ = &tmrServiceInterrupt_56cd7a; + } pThis->__tmrConstructEngine__ = &tmrConstructEngine_IMPL; @@ -262,13 +293,40 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal pThis->__tmrStateDestroy__ = &tmrStateDestroy_IMPL; // Hal function -- tmrSetCurrentTime - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_56cd7a; + } + else + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GH100; + } + else + { + pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GV100; + } + } + + // Hal function -- tmrGetTimeLo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__tmrGetTimeLo__ = &tmrGetTimeLo_GM107; + } + else + { + pThis->__tmrGetTimeLo__ = &tmrGetTimeLo_cf0499; + } + + // Hal function -- tmrGetTime + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ { - pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GH100; + pThis->__tmrGetTime__ = &tmrGetTime_GM107; } else { - pThis->__tmrSetCurrentTime__ = &tmrSetCurrentTime_GV100; + pThis->__tmrGetTime__ = &tmrGetTime_fa6bbe; } // Hal function -- tmrGetTimeEx @@ -374,23 +432,31 @@ void __nvoc_init_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_OBJTMR(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJTMR *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJTMR), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJTMR)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJTMR); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -408,16 +474,25 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_OBJTMR(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_OBJTMR_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJTMR_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJTMR)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_objtmr_nvoc.h b/src/nvidia/generated/g_objtmr_nvoc.h index 2d572db9b9..9ecddd2204 100644 --- a/src/nvidia/generated/g_objtmr_nvoc.h +++ b/src/nvidia/generated/g_objtmr_nvoc.h @@ -40,7 +40,6 @@ extern "C" { /* ------------------------ Includes --------------------------------------- */ #include "core/core.h" -#include "core/info_block.h" #include "gpu/eng_state.h" #include "gpu/gpu.h" #include "tmr.h" @@ -85,11 +84,6 @@ extern "C" { /* ------------------------ Function Redefinitions ------------------------- */ #define tmrEventScheduleRelSec(pTmr, pEvent, RelTimeSec) tmrEventScheduleRel(pTmr, pEvent, (NvU64)(RelTimeSec) * 1000000000 ) -#define tmrGetInfoBlock(pTmr, pListHead, dataId) getInfoPtr(pListHead, dataId) -#define tmrAddInfoBlock(pTmr, ppListHead, dataId, size) addInfoPtr(ppListHead, dataId, size) -#define tmrDeleteInfoBlock(pTmr, ppListHead, dataId) deleteInfoPtr(ppListHead, dataId) -#define tmrTestInfoBlock(pTmr, pListHead, dataId) testInfoPtr(pListHead, dataId) - /* ------------------------ Datatypes -------------------------------------- */ TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR); @@ -185,11 +179,16 @@ typedef struct TMR_EVENT_GENERAL_PARAMS { /*! * Timer object itself */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_OBJTMR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJTMR { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -198,6 +197,7 @@ struct OBJTMR { struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; struct IntrService *__nvoc_pbase_IntrService; struct OBJTMR *__nvoc_pbase_OBJTMR; + NV_STATUS (*__tmrDelay__)(struct OBJTMR *, NvU32); void (*__tmrRegisterIntrService__)(OBJGPU *, struct OBJTMR *, IntrServiceRecord *); NvBool (*__tmrClearInterrupt__)(OBJGPU *, struct OBJTMR *, IntrServiceClearInterruptArguments *); NvU32 (*__tmrServiceInterrupt__)(OBJGPU *, struct OBJTMR *, IntrServiceServiceInterruptArguments *); @@ -208,6 +208,8 @@ struct OBJTMR { NV_STATUS (*__tmrStateUnload__)(OBJGPU *, struct OBJTMR *, NvU32); void (*__tmrStateDestroy__)(OBJGPU *, struct OBJTMR *); NV_STATUS (*__tmrSetCurrentTime__)(OBJGPU *, struct OBJTMR *); + NvU32 (*__tmrGetTimeLo__)(OBJGPU *, struct OBJTMR *); + NvU64 (*__tmrGetTime__)(OBJGPU *, struct OBJTMR *); NvU64 (*__tmrGetTimeEx__)(OBJGPU *, struct OBJTMR *, struct THREAD_STATE_NODE *); NV_STATUS (*__tmrSetCountdownIntrDisable__)(OBJGPU *, struct OBJTMR *); NV_STATUS (*__tmrSetCountdown__)(OBJGPU *, struct OBJTMR *, NvU32, NvU32, struct THREAD_STATE_NODE *); @@ -243,7 +245,6 @@ struct OBJTMR { volatile NvS32 tmrChangePending; NvBool bInitialized; NvBool bAlarmIntrEnabled; - PENG_INFO_LINK_NODE infoList; struct OBJREFCNT *pGrTickFreqRefcnt; NvU64 sysTimerOffsetNs; }; @@ -290,6 +291,8 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR**, Dynamic*, NvU32); #define __objCreate_OBJTMR(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_OBJTMR((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) +#define tmrDelay(pTmr, arg0) tmrDelay_DISPATCH(pTmr, arg0) +#define tmrDelay_HAL(pTmr, arg0) tmrDelay_DISPATCH(pTmr, arg0) #define tmrRegisterIntrService(pGpu, pTmr, pRecords) tmrRegisterIntrService_DISPATCH(pGpu, pTmr, pRecords) #define tmrClearInterrupt(pGpu, pTmr, pParams) tmrClearInterrupt_DISPATCH(pGpu, pTmr, pParams) #define tmrServiceInterrupt(pGpu, pTmr, pParams) tmrServiceInterrupt_DISPATCH(pGpu, pTmr, pParams) @@ -302,6 +305,10 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR**, Dynamic*, NvU32); #define tmrStateDestroy(pGpu, pTmr) tmrStateDestroy_DISPATCH(pGpu, pTmr) #define tmrSetCurrentTime(pGpu, pTmr) tmrSetCurrentTime_DISPATCH(pGpu, pTmr) #define tmrSetCurrentTime_HAL(pGpu, pTmr) tmrSetCurrentTime_DISPATCH(pGpu, pTmr) +#define tmrGetTimeLo(pGpu, pTmr) tmrGetTimeLo_DISPATCH(pGpu, pTmr) +#define tmrGetTimeLo_HAL(pGpu, pTmr) tmrGetTimeLo_DISPATCH(pGpu, pTmr) +#define tmrGetTime(pGpu, pTmr) tmrGetTime_DISPATCH(pGpu, pTmr) +#define tmrGetTime_HAL(pGpu, pTmr) tmrGetTime_DISPATCH(pGpu, pTmr) #define tmrGetTimeEx(pGpu, pTmr, arg0) tmrGetTimeEx_DISPATCH(pGpu, pTmr, arg0) #define tmrGetTimeEx_HAL(pGpu, pTmr, arg0) tmrGetTimeEx_DISPATCH(pGpu, pTmr, arg0) #define tmrSetCountdownIntrDisable(pGpu, pTmr) tmrSetCountdownIntrDisable_DISPATCH(pGpu, pTmr) @@ -349,22 +356,6 @@ static inline NV_STATUS tmrGetCurrentTimeEx(struct OBJTMR *pTmr, NvU64 *pTime, s #define tmrGetCurrentTimeEx_HAL(pTmr, pTime, arg0) tmrGetCurrentTimeEx(pTmr, pTime, arg0) -NV_STATUS tmrDelay_OSTIMER(struct OBJTMR *pTmr, NvU32 arg0); - -NV_STATUS tmrDelay_PTIMER(struct OBJTMR *pTmr, NvU32 arg0); - - -#ifdef __nvoc_objtmr_h_disabled -static inline NV_STATUS tmrDelay(struct OBJTMR *pTmr, NvU32 arg0) { - NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_objtmr_h_disabled -#define tmrDelay(pTmr, arg0) tmrDelay_OSTIMER(pTmr, arg0) -#endif //__nvoc_objtmr_h_disabled - -#define tmrDelay_HAL(pTmr, arg0) tmrDelay(pTmr, arg0) - static inline NV_STATUS tmrSetAlarmIntrDisable_56cd7a(OBJGPU *pGpu, struct OBJTMR *pTmr) { return NV_OK; } @@ -458,42 +449,6 @@ static inline NV_STATUS tmrGetIntrStatus(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU3 #define tmrGetIntrStatus_HAL(pGpu, pTmr, pStatus, arg0) tmrGetIntrStatus(pGpu, pTmr, pStatus, arg0) -static inline NvU32 tmrGetTimeLo_cf0499(OBJGPU *pGpu, struct OBJTMR *pTmr) { - return ((NvU32)(((NvU64)(osGetTimestamp())) & 4294967295U)); -} - -NvU32 tmrGetTimeLo_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); - - -#ifdef __nvoc_objtmr_h_disabled -static inline NvU32 tmrGetTimeLo(OBJGPU *pGpu, struct OBJTMR *pTmr) { - NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); - return 0; -} -#else //__nvoc_objtmr_h_disabled -#define tmrGetTimeLo(pGpu, pTmr) tmrGetTimeLo_cf0499(pGpu, pTmr) -#endif //__nvoc_objtmr_h_disabled - -#define tmrGetTimeLo_HAL(pGpu, pTmr) tmrGetTimeLo(pGpu, pTmr) - -static inline NvU64 tmrGetTime_fa6bbe(OBJGPU *pGpu, struct OBJTMR *pTmr) { - return osGetTimestamp(); -} - -NvU64 tmrGetTime_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); - - -#ifdef __nvoc_objtmr_h_disabled -static inline NvU64 tmrGetTime(OBJGPU *pGpu, struct OBJTMR *pTmr) { - NV_ASSERT_FAILED_PRECOMP("OBJTMR was disabled!"); - return 0; -} -#else //__nvoc_objtmr_h_disabled -#define tmrGetTime(pGpu, pTmr) tmrGetTime_fa6bbe(pGpu, pTmr) -#endif //__nvoc_objtmr_h_disabled - -#define tmrGetTime_HAL(pGpu, pTmr) tmrGetTime(pGpu, pTmr) - NvU32 tmrReadTimeLoReg_TU102(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); @@ -743,9 +698,17 @@ static inline NV_STATUS tmrEventDestroyOSTimer(struct OBJTMR *pTmr, PTMR_EVENT p #define tmrEventDestroyOSTimer_HAL(pTmr, pEvent) tmrEventDestroyOSTimer(pTmr, pEvent) -void tmrRegisterIntrService_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[168]); +NV_STATUS tmrDelay_OSTIMER(struct OBJTMR *pTmr, NvU32 arg0); -static inline void tmrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[168]) { +NV_STATUS tmrDelay_PTIMER(struct OBJTMR *pTmr, NvU32 arg0); + +static inline NV_STATUS tmrDelay_DISPATCH(struct OBJTMR *pTmr, NvU32 arg0) { + return pTmr->__tmrDelay__(pTmr, arg0); +} + +void tmrRegisterIntrService_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[171]); + +static inline void tmrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr, IntrServiceRecord pRecords[171]) { pTmr->__tmrRegisterIntrService__(pGpu, pTmr, pRecords); } @@ -803,6 +766,10 @@ static inline void tmrStateDestroy_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { pTmr->__tmrStateDestroy__(pGpu, pTmr); } +static inline NV_STATUS tmrSetCurrentTime_56cd7a(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return NV_OK; +} + NV_STATUS tmrSetCurrentTime_GV100(OBJGPU *pGpu, struct OBJTMR *pTmr); NV_STATUS tmrSetCurrentTime_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr); @@ -811,6 +778,26 @@ static inline NV_STATUS tmrSetCurrentTime_DISPATCH(OBJGPU *pGpu, struct OBJTMR * return pTmr->__tmrSetCurrentTime__(pGpu, pTmr); } +static inline NvU32 tmrGetTimeLo_cf0499(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return ((NvU32)(((NvU64)(osGetTimestamp())) & 4294967295U)); +} + +NvU32 tmrGetTimeLo_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); + +static inline NvU32 tmrGetTimeLo_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return pTmr->__tmrGetTimeLo__(pGpu, pTmr); +} + +static inline NvU64 tmrGetTime_fa6bbe(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return osGetTimestamp(); +} + +NvU64 tmrGetTime_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr); + +static inline NvU64 tmrGetTime_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) { + return pTmr->__tmrGetTime__(pGpu, pTmr); +} + NvU64 tmrGetTimeEx_GM107(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); NvU64 tmrGetTimeEx_GH100(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0); @@ -903,7 +890,7 @@ static inline void tmrServiceSwrlCallbacks(OBJGPU *pGpu, struct OBJTMR *pTmr, st return; } -static inline NvBool tmrServiceSwrlWrapper(OBJGPU *pGpu, struct OBJTMR *pTmr, MC_ENGINE_BITVECTOR *arg0, struct THREAD_STATE_NODE *arg1) { +static inline NvBool tmrServiceSwrlWrapper(OBJGPU *pGpu, struct OBJTMR *pTmr, struct THREAD_STATE_NODE *arg0) { return ((NvBool)(0 != 0)); } diff --git a/src/nvidia/generated/g_odb.h b/src/nvidia/generated/g_odb.h index e1b30513b3..cb6add47e0 100644 --- a/src/nvidia/generated/g_odb.h +++ b/src/nvidia/generated/g_odb.h @@ -59,7 +59,7 @@ typedef struct OBJDISP *POBJDISP; // #define __dynamicCast_OBJGPIO(pObj) NULL #define __dynamicCast_OBJRPC(pObj) ((POBJRPC)__nvoc_dynamicCast(staticCast((pObj), Dynamic), classInfo(OBJRPC))) -#define __dynamicCast_OBJRPCSTRUCTURECOPY(pObj) NULL +#define __dynamicCast_OBJRPCSTRUCTURECOPY(pObj) ((POBJRPCSTRUCTURECOPY)__nvoc_dynamicCast(staticCast((pObj), Dynamic), classInfo(OBJRPCSTRUCTURECOPY))) diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.c b/src/nvidia/generated/g_os_desc_mem_nvoc.c index b160419bb1..b8d7897ce0 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.c +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_osdescControl_Epilogue(struct OsDescMemory * rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_osdescControlLookup(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_osdescControl(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_osdescControlSerialization_Prologue(str return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_osdescIsPartialUnmapSupported(struct OsDescMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_OsDescMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_osdescIsReady(struct OsDescMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_OsDescMemory_Memory.offset), bCopyConstructorContext); } @@ -261,8 +261,6 @@ static void __nvoc_init_funcTable_OsDescMemory_1(OsDescMemory *pThis) { pThis->__osdescControl_Epilogue__ = &__nvoc_thunk_RmResource_osdescControl_Epilogue; - pThis->__osdescControlLookup__ = &__nvoc_thunk_RsResource_osdescControlLookup; - pThis->__osdescControl__ = &__nvoc_thunk_Memory_osdescControl; pThis->__osdescUnmap__ = &__nvoc_thunk_Memory_osdescUnmap; @@ -275,6 +273,8 @@ static void __nvoc_init_funcTable_OsDescMemory_1(OsDescMemory *pThis) { pThis->__osdescControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_osdescControlSerialization_Prologue; + pThis->__osdescIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_osdescIsPartialUnmapSupported; + pThis->__osdescIsReady__ = &__nvoc_thunk_Memory_osdescIsReady; pThis->__osdescCheckCopyPermissions__ = &__nvoc_thunk_Memory_osdescCheckCopyPermissions; @@ -306,21 +306,26 @@ void __nvoc_init_OsDescMemory(OsDescMemory *pThis) { __nvoc_init_funcTable_OsDescMemory(pThis); } -NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OsDescMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OsDescMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OsDescMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OsDescMemory); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -335,16 +340,25 @@ NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory **ppThis, Dynamic *pParent, status = __nvoc_ctor_OsDescMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_OsDescMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OsDescMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OsDescMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_os_desc_mem_nvoc.h b/src/nvidia/generated/g_os_desc_mem_nvoc.h index 4f31ee5aad..835838addc 100644 --- a/src/nvidia/generated/g_os_desc_mem_nvoc.h +++ b/src/nvidia/generated/g_os_desc_mem_nvoc.h @@ -39,11 +39,16 @@ extern "C" { /*! * Bind memory allocated through os descriptor */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_OS_DESC_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OsDescMemory { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -65,13 +70,13 @@ struct OsDescMemory { NvBool (*__osdescIsGpuMapAllowed__)(struct OsDescMemory *, struct OBJGPU *); NV_STATUS (*__osdescUnmapFrom__)(struct OsDescMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__osdescControl_Epilogue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__osdescControlLookup__)(struct OsDescMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__osdescControl__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescUnmap__)(struct OsDescMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__osdescGetMemInterMapParams__)(struct OsDescMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__osdescGetMemoryMappingDescriptor__)(struct OsDescMemory *, MEMORY_DESCRIPTOR **); NV_STATUS (*__osdescControlFilter__)(struct OsDescMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__osdescControlSerialization_Prologue__)(struct OsDescMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__osdescIsPartialUnmapSupported__)(struct OsDescMemory *); NV_STATUS (*__osdescIsReady__)(struct OsDescMemory *, NvBool); NV_STATUS (*__osdescCheckCopyPermissions__)(struct OsDescMemory *, struct OBJGPU *, struct Device *); void (*__osdescPreDestruct__)(struct OsDescMemory *); @@ -121,13 +126,13 @@ NV_STATUS __nvoc_objCreate_OsDescMemory(OsDescMemory**, Dynamic*, NvU32, CALL_CO #define osdescIsGpuMapAllowed(pMemory, pGpu) osdescIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define osdescUnmapFrom(pResource, pParams) osdescUnmapFrom_DISPATCH(pResource, pParams) #define osdescControl_Epilogue(pResource, pCallContext, pParams) osdescControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define osdescControlLookup(pResource, pParams, ppEntry) osdescControlLookup_DISPATCH(pResource, pParams, ppEntry) #define osdescControl(pMemory, pCallContext, pParams) osdescControl_DISPATCH(pMemory, pCallContext, pParams) #define osdescUnmap(pMemory, pCallContext, pCpuMapping) osdescUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define osdescGetMemInterMapParams(pMemory, pParams) osdescGetMemInterMapParams_DISPATCH(pMemory, pParams) #define osdescGetMemoryMappingDescriptor(pMemory, ppMemDesc) osdescGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define osdescControlFilter(pResource, pCallContext, pParams) osdescControlFilter_DISPATCH(pResource, pCallContext, pParams) #define osdescControlSerialization_Prologue(pResource, pCallContext, pParams) osdescControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define osdescIsPartialUnmapSupported(pResource) osdescIsPartialUnmapSupported_DISPATCH(pResource) #define osdescIsReady(pMemory, bCopyConstructorContext) osdescIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define osdescCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) osdescCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define osdescPreDestruct(pResource) osdescPreDestruct_DISPATCH(pResource) @@ -185,10 +190,6 @@ static inline void osdescControl_Epilogue_DISPATCH(struct OsDescMemory *pResourc pResource->__osdescControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS osdescControlLookup_DISPATCH(struct OsDescMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__osdescControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS osdescControl_DISPATCH(struct OsDescMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__osdescControl__(pMemory, pCallContext, pParams); } @@ -213,6 +214,10 @@ static inline NV_STATUS osdescControlSerialization_Prologue_DISPATCH(struct OsDe return pResource->__osdescControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool osdescIsPartialUnmapSupported_DISPATCH(struct OsDescMemory *pResource) { + return pResource->__osdescIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS osdescIsReady_DISPATCH(struct OsDescMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__osdescIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_os_nvoc.c b/src/nvidia/generated/g_os_nvoc.c index d2eb133b19..37f1294a05 100644 --- a/src/nvidia/generated/g_os_nvoc.c +++ b/src/nvidia/generated/g_os_nvoc.c @@ -104,21 +104,26 @@ void __nvoc_init_OBJOS(OBJOS *pThis) { __nvoc_init_funcTable_OBJOS(pThis); } -NV_STATUS __nvoc_objCreate_OBJOS(OBJOS **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJOS(OBJOS **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJOS *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJOS), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJOS)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJOS); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -133,16 +138,25 @@ NV_STATUS __nvoc_objCreate_OBJOS(OBJOS **ppThis, Dynamic *pParent, NvU32 createF status = __nvoc_ctor_OBJOS(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJOS_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJOS_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJOS)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_os_nvoc.h b/src/nvidia/generated/g_os_nvoc.h index c0edaa2818..9d69aa1919 100644 --- a/src/nvidia/generated/g_os_nvoc.h +++ b/src/nvidia/generated/g_os_nvoc.h @@ -451,10 +451,6 @@ NV_STATUS osCallACPI_NVHG_ROM(OBJGPU *, NvU32 *, NvU32 *); NV_STATUS osCallACPI_NVHG_DCS(OBJGPU *, NvU32, NvU32 *); NV_STATUS osCallACPI_DOD(OBJGPU *, NvU32 *, NvU32 *); -// Tegra ACPI calls -NV_STATUS osCallACPI_ON(OBJGPU *, NvU32); -NV_STATUS osCallACPI_OFF(OBJGPU *, NvU32); - // Optimus WMI ACPI calls NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *); @@ -625,11 +621,16 @@ NvBool osCheckCallback_v2(OBJGPU *); typedef NV_STATUS OSReadPFPciConfigInVF(NvU32, NvU32*); // Actual definition of the OBJOS structure + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_OS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJOS { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -657,7 +658,6 @@ struct OBJOS { OSPexRecoveryCallback *osPexRecoveryCallback; OSInternalReserveAllocCallback *osInternalReserveAllocCallback; OSInternalReserveFreeCallback *osInternalReserveFreeCallback; - NvU32 SystemMemorySize; OSPageArrayGetPhysAddr *osPageArrayGetPhysAddr; NvU32 dynamicPowerSupportGpuMask; NvBool bIsSimMods; @@ -824,6 +824,7 @@ NV_STATUS osGetAtsTargetAddressRange(OBJGPU *pGpu, NvU32 peerIndex); NV_STATUS osGetFbNumaInfo(OBJGPU *pGpu, NvU64 *pAddrPhys, + NvU64 *pAddrRsvdPhys, NvS32 *pNodeId); NV_STATUS osGetEgmInfo(OBJGPU *pGpu, NvU64 *pPhysAddr, @@ -849,7 +850,8 @@ NV_STATUS osVgpuInjectInterrupt(void *pArg1); NV_STATUS osVgpuRegisterMdev(OS_GPU_INFO *pArg1); NV_STATUS osIsVgpuVfioPresent(void); NV_STATUS osIsVfioPciCorePresent(void); -NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1); +NV_STATUS rm_is_vgpu_supported_device(OS_GPU_INFO *pNv, NvU32 pmc_boot_1, + NvU32 pmc_boot_42); NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection); NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection); @@ -985,19 +987,6 @@ void* osMapKernelSpace(RmPhysAddr Start, void osUnmapKernelSpace(void *addr, NvU64 size); - -void *osMapIOSpace(RmPhysAddr start, - NvU64 size_bytes, - void ** priv, - NvU32 user, - NvU32 mode, - NvU32 Protect); - -void osUnmapIOSpace(void *pAddress, - NvU64 Size, - void *pData, - NvU32 User); - NvBool osTestPcieExtendedConfigAccess(void *handle, NvU32 offset); NvU32 osGetCpuFrequency(void); @@ -1059,12 +1048,6 @@ NV_STATUS osGetValidWindowHeadMask(OS_GPU_INFO *pArg1, NV_STATUS osSchedule(void); -NV_STATUS osDmaMapPages(OS_GPU_INFO *pArg1, - MEMORY_DESCRIPTOR *pMemDesc); - -NV_STATUS osDmaUnmapPages(OS_GPU_INFO *pArg1, - MEMORY_DESCRIPTOR *pMemDesc); - void osDmaSetAddressSize(OS_GPU_INFO *pArg1, NvU32 bits); @@ -1153,6 +1136,12 @@ NV_STATUS osSetTegraBrightnessLevel(OS_GPU_INFO *pArg1, NvBool osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo); +void osTegraGetDispSMMUStreamIds( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *dispIsoStreamId, + NvU32 *dispNisoStreamId +); + NvBool osIsVga(OS_GPU_INFO *pArg1, NvBool bIsGpuPrimaryDevice); @@ -1240,6 +1229,8 @@ NV_STATUS osSanityTestIsr(OBJGPU *pGpu); void osAllocatedRmClient(void* pOSInfo); +NvBool osTegraSocIsSimNetlistNet07(OS_GPU_INFO *pArg1); + NV_STATUS osConfigurePcieReqAtomics(OS_GPU_INFO *pOsGpuInfo, NvU32 *pMask); NvBool osDmabufIsSupported(void); @@ -1285,9 +1276,10 @@ NV_STATUS osOfflinePageAtAddress(NvU64 address); // Os 1Hz timer callback functions NV_STATUS osInit1HzCallbacks(OBJTMR *pTmr); NV_STATUS osDestroy1HzCallbacks(OBJTMR *pTmr); -NV_STATUS osSchedule1SecondCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData, NvU32 flags); -void osRemove1SecondRepeatingCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData); +NV_STATUS osSchedule1HzCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData, NvU32 flags); +void osRemove1HzCallback(OBJGPU *pGpu, OS1HZPROC callback, void *pData); NvBool osRun1HzCallbacksNow(OBJGPU *pGpu); + NV_STATUS osDoFunctionLevelReset(OBJGPU *pGpu); void vgpuDevWriteReg032( diff --git a/src/nvidia/generated/g_p2p_api_nvoc.c b/src/nvidia/generated/g_p2p_api_nvoc.c index 4f196762d6..f9af609cd4 100644 --- a/src/nvidia/generated/g_p2p_api_nvoc.c +++ b/src/nvidia/generated/g_p2p_api_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_p2papiAddAdditionalDependants(struct RsClien resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmapFrom(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_p2papiControlSerialization_Prologue(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmap(struct P2PApi *pResource, s return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_p2papiIsPartialUnmapSupported(struct P2PApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_p2papiPreDestruct(struct P2PApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_p2papiControl_Epilogue(struct P2PApi *pResou rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_p2papiControlLookup(struct P2PApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_p2papiUnmapFrom(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_P2PApi_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_p2papiMap(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -223,8 +223,6 @@ static void __nvoc_init_funcTable_P2PApi_1(P2PApi *pThis) { pThis->__p2papiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_p2papiAddAdditionalDependants; - pThis->__p2papiUnmapFrom__ = &__nvoc_thunk_RsResource_p2papiUnmapFrom; - pThis->__p2papiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_p2papiControlSerialization_Prologue; pThis->__p2papiControl_Prologue__ = &__nvoc_thunk_RmResource_p2papiControl_Prologue; @@ -233,6 +231,8 @@ static void __nvoc_init_funcTable_P2PApi_1(P2PApi *pThis) { pThis->__p2papiUnmap__ = &__nvoc_thunk_RsResource_p2papiUnmap; + pThis->__p2papiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_p2papiIsPartialUnmapSupported; + pThis->__p2papiPreDestruct__ = &__nvoc_thunk_RsResource_p2papiPreDestruct; pThis->__p2papiMapTo__ = &__nvoc_thunk_RsResource_p2papiMapTo; @@ -243,7 +243,7 @@ static void __nvoc_init_funcTable_P2PApi_1(P2PApi *pThis) { pThis->__p2papiControl_Epilogue__ = &__nvoc_thunk_RmResource_p2papiControl_Epilogue; - pThis->__p2papiControlLookup__ = &__nvoc_thunk_RsResource_p2papiControlLookup; + pThis->__p2papiUnmapFrom__ = &__nvoc_thunk_RsResource_p2papiUnmapFrom; pThis->__p2papiMap__ = &__nvoc_thunk_RsResource_p2papiMap; @@ -265,21 +265,26 @@ void __nvoc_init_P2PApi(P2PApi *pThis) { __nvoc_init_funcTable_P2PApi(pThis); } -NV_STATUS __nvoc_objCreate_P2PApi(P2PApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_P2PApi(P2PApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; P2PApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(P2PApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(P2PApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_P2PApi); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -294,16 +299,25 @@ NV_STATUS __nvoc_objCreate_P2PApi(P2PApi **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_P2PApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_P2PApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_P2PApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(P2PApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_p2p_api_nvoc.h b/src/nvidia/generated/g_p2p_api_nvoc.h index ede81ca2bd..fc987c734b 100644 --- a/src/nvidia/generated/g_p2p_api_nvoc.h +++ b/src/nvidia/generated/g_p2p_api_nvoc.h @@ -56,11 +56,16 @@ extern "C" { #define NV_P2PAPI_ATTRIBUTES_REMOTE_EGM_NO 0x0 #define NV_P2PAPI_ATTRIBUTES_REMOTE_EGM_YES 0x1 + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_P2P_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct P2PApi { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -77,17 +82,17 @@ struct P2PApi { NvU32 (*__p2papiGetRefCount__)(struct P2PApi *); NV_STATUS (*__p2papiControlFilter__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__p2papiAddAdditionalDependants__)(struct RsClient *, struct P2PApi *, RsResourceRef *); - NV_STATUS (*__p2papiUnmapFrom__)(struct P2PApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__p2papiControlSerialization_Prologue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__p2papiControl_Prologue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__p2papiCanCopy__)(struct P2PApi *); NV_STATUS (*__p2papiUnmap__)(struct P2PApi *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__p2papiIsPartialUnmapSupported__)(struct P2PApi *); void (*__p2papiPreDestruct__)(struct P2PApi *); NV_STATUS (*__p2papiMapTo__)(struct P2PApi *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__p2papiIsDuplicate__)(struct P2PApi *, NvHandle, NvBool *); void (*__p2papiControlSerialization_Epilogue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__p2papiControl_Epilogue__)(struct P2PApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__p2papiControlLookup__)(struct P2PApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__p2papiUnmapFrom__)(struct P2PApi *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__p2papiMap__)(struct P2PApi *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__p2papiAccessCallback__)(struct P2PApi *, struct RsClient *, void *, RsAccessRight); struct OBJGPU *peer1; @@ -137,17 +142,17 @@ NV_STATUS __nvoc_objCreate_P2PApi(P2PApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define p2papiGetRefCount(pResource) p2papiGetRefCount_DISPATCH(pResource) #define p2papiControlFilter(pResource, pCallContext, pParams) p2papiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define p2papiAddAdditionalDependants(pClient, pResource, pReference) p2papiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define p2papiUnmapFrom(pResource, pParams) p2papiUnmapFrom_DISPATCH(pResource, pParams) #define p2papiControlSerialization_Prologue(pResource, pCallContext, pParams) p2papiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControl_Prologue(pResource, pCallContext, pParams) p2papiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define p2papiCanCopy(pResource) p2papiCanCopy_DISPATCH(pResource) #define p2papiUnmap(pResource, pCallContext, pCpuMapping) p2papiUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define p2papiIsPartialUnmapSupported(pResource) p2papiIsPartialUnmapSupported_DISPATCH(pResource) #define p2papiPreDestruct(pResource) p2papiPreDestruct_DISPATCH(pResource) #define p2papiMapTo(pResource, pParams) p2papiMapTo_DISPATCH(pResource, pParams) #define p2papiIsDuplicate(pResource, hMemory, pDuplicate) p2papiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define p2papiControlSerialization_Epilogue(pResource, pCallContext, pParams) p2papiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define p2papiControl_Epilogue(pResource, pCallContext, pParams) p2papiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define p2papiControlLookup(pResource, pParams, ppEntry) p2papiControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define p2papiUnmapFrom(pResource, pParams) p2papiUnmapFrom_DISPATCH(pResource, pParams) #define p2papiMap(pResource, pCallContext, pParams, pCpuMapping) p2papiMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define p2papiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) p2papiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool p2papiShareCallback_DISPATCH(struct P2PApi *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -182,10 +187,6 @@ static inline void p2papiAddAdditionalDependants_DISPATCH(struct RsClient *pClie pResource->__p2papiAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS p2papiUnmapFrom_DISPATCH(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__p2papiUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS p2papiControlSerialization_Prologue_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__p2papiControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -202,6 +203,10 @@ static inline NV_STATUS p2papiUnmap_DISPATCH(struct P2PApi *pResource, struct CA return pResource->__p2papiUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool p2papiIsPartialUnmapSupported_DISPATCH(struct P2PApi *pResource) { + return pResource->__p2papiIsPartialUnmapSupported__(pResource); +} + static inline void p2papiPreDestruct_DISPATCH(struct P2PApi *pResource) { pResource->__p2papiPreDestruct__(pResource); } @@ -222,8 +227,8 @@ static inline void p2papiControl_Epilogue_DISPATCH(struct P2PApi *pResource, str pResource->__p2papiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS p2papiControlLookup_DISPATCH(struct P2PApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__p2papiControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS p2papiUnmapFrom_DISPATCH(struct P2PApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__p2papiUnmapFrom__(pResource, pParams); } static inline NV_STATUS p2papiMap_DISPATCH(struct P2PApi *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_phys_mem_nvoc.c b/src/nvidia/generated/g_phys_mem_nvoc.c index 78880540f0..533b51d415 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.c +++ b/src/nvidia/generated/g_phys_mem_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_physmemControl_Epilogue(struct PhysicalMemor rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_physmemControlLookup(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_physmemControl(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_physmemControlSerialization_Prologue(st return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_physmemIsPartialUnmapSupported(struct PhysicalMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_PhysicalMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_physmemIsReady(struct PhysicalMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_PhysicalMemory_Memory.offset), bCopyConstructorContext); } @@ -261,8 +261,6 @@ static void __nvoc_init_funcTable_PhysicalMemory_1(PhysicalMemory *pThis) { pThis->__physmemControl_Epilogue__ = &__nvoc_thunk_RmResource_physmemControl_Epilogue; - pThis->__physmemControlLookup__ = &__nvoc_thunk_RsResource_physmemControlLookup; - pThis->__physmemControl__ = &__nvoc_thunk_Memory_physmemControl; pThis->__physmemUnmap__ = &__nvoc_thunk_Memory_physmemUnmap; @@ -275,6 +273,8 @@ static void __nvoc_init_funcTable_PhysicalMemory_1(PhysicalMemory *pThis) { pThis->__physmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_physmemControlSerialization_Prologue; + pThis->__physmemIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_physmemIsPartialUnmapSupported; + pThis->__physmemIsReady__ = &__nvoc_thunk_Memory_physmemIsReady; pThis->__physmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_physmemCheckCopyPermissions; @@ -306,21 +306,26 @@ void __nvoc_init_PhysicalMemory(PhysicalMemory *pThis) { __nvoc_init_funcTable_PhysicalMemory(pThis); } -NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; PhysicalMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PhysicalMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(PhysicalMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PhysicalMemory); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -335,16 +340,25 @@ NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory **ppThis, Dynamic *pPar status = __nvoc_ctor_PhysicalMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_PhysicalMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_PhysicalMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(PhysicalMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_phys_mem_nvoc.h b/src/nvidia/generated/g_phys_mem_nvoc.h index b1d2f903cc..caec4c32aa 100644 --- a/src/nvidia/generated/g_phys_mem_nvoc.h +++ b/src/nvidia/generated/g_phys_mem_nvoc.h @@ -41,11 +41,16 @@ extern "C" { * * Linear view for all video memory (similar to /dev/mem). */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_PHYS_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct PhysicalMemory { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -67,13 +72,13 @@ struct PhysicalMemory { NvBool (*__physmemIsGpuMapAllowed__)(struct PhysicalMemory *, struct OBJGPU *); NV_STATUS (*__physmemUnmapFrom__)(struct PhysicalMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__physmemControl_Epilogue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__physmemControlLookup__)(struct PhysicalMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__physmemControl__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemUnmap__)(struct PhysicalMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__physmemGetMemInterMapParams__)(struct PhysicalMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__physmemGetMemoryMappingDescriptor__)(struct PhysicalMemory *, MEMORY_DESCRIPTOR **); NV_STATUS (*__physmemControlFilter__)(struct PhysicalMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__physmemControlSerialization_Prologue__)(struct PhysicalMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__physmemIsPartialUnmapSupported__)(struct PhysicalMemory *); NV_STATUS (*__physmemIsReady__)(struct PhysicalMemory *, NvBool); NV_STATUS (*__physmemCheckCopyPermissions__)(struct PhysicalMemory *, struct OBJGPU *, struct Device *); void (*__physmemPreDestruct__)(struct PhysicalMemory *); @@ -123,13 +128,13 @@ NV_STATUS __nvoc_objCreate_PhysicalMemory(PhysicalMemory**, Dynamic*, NvU32, CAL #define physmemIsGpuMapAllowed(pMemory, pGpu) physmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define physmemUnmapFrom(pResource, pParams) physmemUnmapFrom_DISPATCH(pResource, pParams) #define physmemControl_Epilogue(pResource, pCallContext, pParams) physmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define physmemControlLookup(pResource, pParams, ppEntry) physmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define physmemControl(pMemory, pCallContext, pParams) physmemControl_DISPATCH(pMemory, pCallContext, pParams) #define physmemUnmap(pMemory, pCallContext, pCpuMapping) physmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define physmemGetMemInterMapParams(pMemory, pParams) physmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define physmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) physmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define physmemControlFilter(pResource, pCallContext, pParams) physmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define physmemControlSerialization_Prologue(pResource, pCallContext, pParams) physmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define physmemIsPartialUnmapSupported(pResource) physmemIsPartialUnmapSupported_DISPATCH(pResource) #define physmemIsReady(pMemory, bCopyConstructorContext) physmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define physmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) physmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define physmemPreDestruct(pResource) physmemPreDestruct_DISPATCH(pResource) @@ -187,10 +192,6 @@ static inline void physmemControl_Epilogue_DISPATCH(struct PhysicalMemory *pReso pResource->__physmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS physmemControlLookup_DISPATCH(struct PhysicalMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__physmemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS physmemControl_DISPATCH(struct PhysicalMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__physmemControl__(pMemory, pCallContext, pParams); } @@ -215,6 +216,10 @@ static inline NV_STATUS physmemControlSerialization_Prologue_DISPATCH(struct Phy return pResource->__physmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool physmemIsPartialUnmapSupported_DISPATCH(struct PhysicalMemory *pResource) { + return pResource->__physmemIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS physmemIsReady_DISPATCH(struct PhysicalMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__physmemIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_platform_nvoc.c b/src/nvidia/generated/g_platform_nvoc.c index c3409d2248..bcdb2faab1 100644 --- a/src/nvidia/generated/g_platform_nvoc.c +++ b/src/nvidia/generated/g_platform_nvoc.c @@ -110,21 +110,26 @@ void __nvoc_init_OBJPFM(OBJPFM *pThis) { __nvoc_init_funcTable_OBJPFM(pThis); } -NV_STATUS __nvoc_objCreate_OBJPFM(OBJPFM **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJPFM(OBJPFM **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJPFM *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJPFM), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJPFM)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJPFM); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -139,16 +144,25 @@ NV_STATUS __nvoc_objCreate_OBJPFM(OBJPFM **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_OBJPFM(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJPFM_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJPFM_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJPFM)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_platform_nvoc.h b/src/nvidia/generated/g_platform_nvoc.h index 2e8560ce2c..00e369dc98 100644 --- a/src/nvidia/generated/g_platform_nvoc.h +++ b/src/nvidia/generated/g_platform_nvoc.h @@ -82,11 +82,16 @@ typedef struct * Defines and structures used for the Platform object. * \***************************************************************************/ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_PLATFORM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJPFM { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_platform_request_handler_nvoc.c b/src/nvidia/generated/g_platform_request_handler_nvoc.c index a3244305d8..c0b3e3b469 100644 --- a/src/nvidia/generated/g_platform_request_handler_nvoc.c +++ b/src/nvidia/generated/g_platform_request_handler_nvoc.c @@ -108,21 +108,26 @@ void __nvoc_init_PlatformRequestHandler(PlatformRequestHandler *pThis) { __nvoc_init_funcTable_PlatformRequestHandler(pThis); } -NV_STATUS __nvoc_objCreate_PlatformRequestHandler(PlatformRequestHandler **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_PlatformRequestHandler(PlatformRequestHandler **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; PlatformRequestHandler *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PlatformRequestHandler), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(PlatformRequestHandler)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PlatformRequestHandler); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -137,16 +142,25 @@ NV_STATUS __nvoc_objCreate_PlatformRequestHandler(PlatformRequestHandler **ppThi status = __nvoc_ctor_PlatformRequestHandler(pThis); if (status != NV_OK) goto __nvoc_objCreate_PlatformRequestHandler_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_PlatformRequestHandler_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(PlatformRequestHandler)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_platform_request_handler_nvoc.h b/src/nvidia/generated/g_platform_request_handler_nvoc.h index 778740a443..d2c529191f 100644 --- a/src/nvidia/generated/g_platform_request_handler_nvoc.h +++ b/src/nvidia/generated/g_platform_request_handler_nvoc.h @@ -268,11 +268,16 @@ typedef struct NvU32 queuedCounterMask; } PFM_REQ_HNDLR_SYS_CONTROL_DATA; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_PLATFORM_REQUEST_HANDLER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct PlatformRequestHandler { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_prereq_tracker_nvoc.c b/src/nvidia/generated/g_prereq_tracker_nvoc.c index aa4435b193..0e46fa086c 100644 --- a/src/nvidia/generated/g_prereq_tracker_nvoc.c +++ b/src/nvidia/generated/g_prereq_tracker_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_PrereqTracker(PrereqTracker *pThis) { __nvoc_init_funcTable_PrereqTracker(pThis); } -NV_STATUS __nvoc_objCreate_PrereqTracker(PrereqTracker **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pParent) { +NV_STATUS __nvoc_objCreate_PrereqTracker(PrereqTracker **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pParent) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; PrereqTracker *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(PrereqTracker), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(PrereqTracker)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_PrereqTracker); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_PrereqTracker(PrereqTracker **ppThis, Dynamic *pParen status = __nvoc_ctor_PrereqTracker(pThis, arg_pParent); if (status != NV_OK) goto __nvoc_objCreate_PrereqTracker_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_PrereqTracker_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(PrereqTracker)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_prereq_tracker_nvoc.h b/src/nvidia/generated/g_prereq_tracker_nvoc.h index f7a410072e..8f92fa8d0f 100644 --- a/src/nvidia/generated/g_prereq_tracker_nvoc.h +++ b/src/nvidia/generated/g_prereq_tracker_nvoc.h @@ -155,11 +155,16 @@ MAKE_LIST(PrereqList, PREREQ_ENTRY); /*! * Holds common prerequisite tracking information. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_PREREQ_TRACKER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct PrereqTracker { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_profiler_v1_nvoc.c b/src/nvidia/generated/g_profiler_v1_nvoc.c index 93c18a0d0a..34dccfd662 100644 --- a/src/nvidia/generated/g_profiler_v1_nvoc.c +++ b/src/nvidia/generated/g_profiler_v1_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_profilerControl_Epilogue(struct Profiler *pR rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerControlLookup(struct Profiler *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_profilerGetInternalObjectHandle(struct Profiler *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Profiler_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_profilerCanCopy(struct Profiler *pResource return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_profilerIsPartialUnmapSupported(struct Profiler *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_profilerPreDestruct(struct Profiler *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Profiler_RsResource.offset)); } @@ -372,8 +372,6 @@ static void __nvoc_init_funcTable_Profiler_1(Profiler *pThis, RmHalspecOwner *pR pThis->__profilerControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerControl_Epilogue; - pThis->__profilerControlLookup__ = &__nvoc_thunk_RsResource_profilerControlLookup; - pThis->__profilerGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerGetInternalObjectHandle; pThis->__profilerUnmap__ = &__nvoc_thunk_GpuResource_profilerUnmap; @@ -388,6 +386,8 @@ static void __nvoc_init_funcTable_Profiler_1(Profiler *pThis, RmHalspecOwner *pR pThis->__profilerCanCopy__ = &__nvoc_thunk_RsResource_profilerCanCopy; + pThis->__profilerIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_profilerIsPartialUnmapSupported; + pThis->__profilerPreDestruct__ = &__nvoc_thunk_RsResource_profilerPreDestruct; pThis->__profilerIsDuplicate__ = &__nvoc_thunk_RsResource_profilerIsDuplicate; @@ -415,23 +415,31 @@ void __nvoc_init_Profiler(Profiler *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_Profiler(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_Profiler(Profiler **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_Profiler(Profiler **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Profiler *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Profiler), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Profiler)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Profiler); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -449,16 +457,25 @@ NV_STATUS __nvoc_objCreate_Profiler(Profiler **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_Profiler(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_Profiler_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Profiler_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Profiler)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_profiler_v1_nvoc.h b/src/nvidia/generated/g_profiler_v1_nvoc.h index 730b990e7c..a576198bc3 100644 --- a/src/nvidia/generated/g_profiler_v1_nvoc.h +++ b/src/nvidia/generated/g_profiler_v1_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,11 +42,16 @@ extern "C" { #include "gpu/gpu_halspec.h" #include "nvoc/utility.h" + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_PROFILER_V1_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Profiler { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -73,7 +78,6 @@ struct Profiler { NV_STATUS (*__profilerInternalControlForward__)(struct Profiler *, NvU32, void *, NvU32); NV_STATUS (*__profilerUnmapFrom__)(struct Profiler *, RS_RES_UNMAP_FROM_PARAMS *); void (*__profilerControl_Epilogue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerControlLookup__)(struct Profiler *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__profilerGetInternalObjectHandle__)(struct Profiler *); NV_STATUS (*__profilerUnmap__)(struct Profiler *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__profilerGetMemInterMapParams__)(struct Profiler *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -81,6 +85,7 @@ struct Profiler { NV_STATUS (*__profilerControlFilter__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerControlSerialization_Prologue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__profilerCanCopy__)(struct Profiler *); + NvBool (*__profilerIsPartialUnmapSupported__)(struct Profiler *); void (*__profilerPreDestruct__)(struct Profiler *); NV_STATUS (*__profilerIsDuplicate__)(struct Profiler *, NvHandle, NvBool *); void (*__profilerControlSerialization_Epilogue__)(struct Profiler *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -133,7 +138,6 @@ NV_STATUS __nvoc_objCreate_Profiler(Profiler**, Dynamic*, NvU32, struct CALL_CON #define profilerInternalControlForward(pGpuResource, command, pParams, size) profilerInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerUnmapFrom(pResource, pParams) profilerUnmapFrom_DISPATCH(pResource, pParams) #define profilerControl_Epilogue(pResource, pCallContext, pParams) profilerControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define profilerControlLookup(pResource, pParams, ppEntry) profilerControlLookup_DISPATCH(pResource, pParams, ppEntry) #define profilerGetInternalObjectHandle(pGpuResource) profilerGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerUnmap(pGpuResource, pCallContext, pCpuMapping) profilerUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define profilerGetMemInterMapParams(pRmResource, pParams) profilerGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -141,6 +145,7 @@ NV_STATUS __nvoc_objCreate_Profiler(Profiler**, Dynamic*, NvU32, struct CALL_CON #define profilerControlFilter(pResource, pCallContext, pParams) profilerControlFilter_DISPATCH(pResource, pCallContext, pParams) #define profilerControlSerialization_Prologue(pResource, pCallContext, pParams) profilerControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerCanCopy(pResource) profilerCanCopy_DISPATCH(pResource) +#define profilerIsPartialUnmapSupported(pResource) profilerIsPartialUnmapSupported_DISPATCH(pResource) #define profilerPreDestruct(pResource) profilerPreDestruct_DISPATCH(pResource) #define profilerIsDuplicate(pResource, hMemory, pDuplicate) profilerIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -278,10 +283,6 @@ static inline void profilerControl_Epilogue_DISPATCH(struct Profiler *pResource, pResource->__profilerControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS profilerControlLookup_DISPATCH(struct Profiler *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__profilerControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle profilerGetInternalObjectHandle_DISPATCH(struct Profiler *pGpuResource) { return pGpuResource->__profilerGetInternalObjectHandle__(pGpuResource); } @@ -310,6 +311,10 @@ static inline NvBool profilerCanCopy_DISPATCH(struct Profiler *pResource) { return pResource->__profilerCanCopy__(pResource); } +static inline NvBool profilerIsPartialUnmapSupported_DISPATCH(struct Profiler *pResource) { + return pResource->__profilerIsPartialUnmapSupported__(pResource); +} + static inline void profilerPreDestruct_DISPATCH(struct Profiler *pResource) { pResource->__profilerPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.c b/src/nvidia/generated/g_profiler_v2_nvoc.c index 703b7ae3a0..1df91c0915 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.c +++ b/src/nvidia/generated/g_profiler_v2_nvoc.c @@ -25,7 +25,7 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; void __nvoc_init_ProfilerBase(ProfilerBase*, RmHalspecOwner* ); void __nvoc_init_funcTable_ProfilerBase(ProfilerBase*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_ProfilerBase(ProfilerBase*, RmHalspecOwner* , struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +NV_STATUS __nvoc_ctor_ProfilerBase(ProfilerBase*, RmHalspecOwner* , CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); void __nvoc_init_dataField_ProfilerBase(ProfilerBase*, RmHalspecOwner* ); void __nvoc_dtor_ProfilerBase(ProfilerBase*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ProfilerBase; @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_profilerBaseControl_Epilogue(struct Profiler rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerBaseControlLookup(struct ProfilerBase *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle(struct ProfilerBase *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerBase_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_profilerBaseCanCopy(struct ProfilerBase *p return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_profilerBaseIsPartialUnmapSupported(struct ProfilerBase *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_profilerBasePreDestruct(struct ProfilerBase *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerBase_RsResource.offset)); } @@ -230,12 +230,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReservePmAreaSmpc_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0103u, /*paramSize=*/ sizeof(NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS), @@ -320,12 +320,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [8] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdPmaStreamUpdateGetPut_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdPmaStreamUpdateGetPut_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0109u, /*paramSize=*/ sizeof(NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS), @@ -485,12 +485,42 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler #endif }, { /* [19] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalQuiescePmaChannel_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0201u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalQuiescePmaChannel" +#endif + }, + { /* [20] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400010u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalSriovPromotePmaStream_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400010u) + /*flags=*/ 0x400010u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xb0cc0202u, + /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_ProfilerBase.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "profilerBaseCtrlCmdInternalSriovPromotePmaStream" +#endif + }, + { /* [21] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalPermissionsInit_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - /*flags=*/ 0x610u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0203u, /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS), @@ -499,13 +529,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalPermissionsInit" #endif }, - { /* [20] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + { /* [22] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400610u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalAllocPmaStream_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - /*flags=*/ 0x610u, + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400610u) + /*flags=*/ 0x400610u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0204u, /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS), @@ -514,13 +544,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalAllocPmaStream" #endif }, - { /* [21] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + { /* [23] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400610u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalFreePmaStream_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - /*flags=*/ 0x610u, + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalFreePmaStream_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400610u) + /*flags=*/ 0x400610u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0206u, /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS), @@ -529,13 +559,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalFreePmaStream" #endif }, - { /* [22] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + { /* [24] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400610u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdInternalGetMaxPmas_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - /*flags=*/ 0x610u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400610u) + /*flags=*/ 0x400610u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0207u, /*paramSize=*/ sizeof(NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS), @@ -544,7 +574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalGetMaxPmas" #endif }, - { /* [23] */ + { /* [25] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -559,7 +589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalBindPmResources" #endif }, - { /* [24] */ + { /* [26] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -574,7 +604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalUnbindPmResources" #endif }, - { /* [25] */ + { /* [27] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -589,13 +619,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdInternalReserveHwpmLegacy" #endif }, - { /* [26] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [28] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdRequestCgControls_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdRequestCgControls_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0301u, /*paramSize=*/ sizeof(NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS), @@ -604,13 +634,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler /*func=*/ "profilerBaseCtrlCmdRequestCgControls" #endif }, - { /* [27] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [29] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReleaseCgControls_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) profilerBaseCtrlCmdReleaseCgControls_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0xb0cc0302u, /*paramSize=*/ sizeof(NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS), @@ -624,7 +654,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Profiler const struct NVOC_EXPORT_INFO __nvoc_export_info_ProfilerBase = { - /*numEntries=*/ 28, + /*numEntries=*/ 30, /*pExportEntries=*/ __nvoc_exported_method_def_ProfilerBase }; @@ -644,8 +674,8 @@ void __nvoc_init_dataField_ProfilerBase(ProfilerBase *pThis, RmHalspecOwner *pRm PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); } -NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); -NV_STATUS __nvoc_ctor_ProfilerBase(ProfilerBase *pThis, RmHalspecOwner *pRmhalspecowner, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_ProfilerBase(ProfilerBase *pThis, RmHalspecOwner *pRmhalspecowner, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_ProfilerBase_fail_GpuResource; @@ -671,6 +701,26 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal function -- profilerBaseConstructState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerBaseConstructState__ = &profilerBaseConstructState_IMPL; + } + else + { + pThis->__profilerBaseConstructState__ = &profilerBaseConstructState_56cd7a; + } + + // Hal function -- profilerBaseDestructState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerBaseDestructState__ = &profilerBaseDestructState_VF; + } + else + { + pThis->__profilerBaseDestructState__ = &profilerBaseDestructState_b3696a; + } + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) pThis->__profilerBaseCtrlCmdReserveHwpmLegacy__ = &profilerBaseCtrlCmdReserveHwpmLegacy_IMPL; #endif @@ -683,7 +733,7 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdReleaseHwpmLegacy__ = &profilerBaseCtrlCmdReleaseHwpmLegacy_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__profilerBaseCtrlCmdReservePmAreaSmpc__ = &profilerBaseCtrlCmdReservePmAreaSmpc_IMPL; #endif @@ -699,11 +749,17 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdFreePmaStream__ = &profilerBaseCtrlCmdFreePmaStream_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - pThis->__profilerBaseCtrlCmdInternalFreePmaStream__ = &profilerBaseCtrlCmdInternalFreePmaStream_IMPL; -#endif + // Hal function -- profilerBaseCtrlCmdInternalFreePmaStream + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerBaseCtrlCmdInternalFreePmaStream__ = &profilerBaseCtrlCmdInternalFreePmaStream_VF; + } + else + { + pThis->__profilerBaseCtrlCmdInternalFreePmaStream__ = &profilerBaseCtrlCmdInternalFreePmaStream_56cd7a; + } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400610u) pThis->__profilerBaseCtrlCmdInternalGetMaxPmas__ = &profilerBaseCtrlCmdInternalGetMaxPmas_IMPL; #endif @@ -723,19 +779,45 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdInternalUnbindPmResources__ = &profilerBaseCtrlCmdInternalUnbindPmResources_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__profilerBaseCtrlCmdPmaStreamUpdateGetPut__ = &profilerBaseCtrlCmdPmaStreamUpdateGetPut_IMPL; -#endif + // Hal function -- profilerBaseCtrlCmdPmaStreamUpdateGetPut + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerBaseCtrlCmdPmaStreamUpdateGetPut__ = &profilerBaseCtrlCmdPmaStreamUpdateGetPut_VF; + } + else + { + pThis->__profilerBaseCtrlCmdPmaStreamUpdateGetPut__ = &profilerBaseCtrlCmdPmaStreamUpdateGetPut_56cd7a; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__profilerBaseCtrlCmdExecRegops__ = &profilerBaseCtrlCmdExecRegops_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) - pThis->__profilerBaseCtrlCmdInternalAllocPmaStream__ = &profilerBaseCtrlCmdInternalAllocPmaStream_IMPL; + // Hal function -- profilerBaseCtrlCmdInternalAllocPmaStream + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerBaseCtrlCmdInternalAllocPmaStream__ = &profilerBaseCtrlCmdInternalAllocPmaStream_VF; + } + else + { + pThis->__profilerBaseCtrlCmdInternalAllocPmaStream__ = &profilerBaseCtrlCmdInternalAllocPmaStream_56cd7a; + } + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__profilerBaseCtrlCmdInternalQuiescePmaChannel__ = &profilerBaseCtrlCmdInternalQuiescePmaChannel_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) + // Hal function -- profilerBaseCtrlCmdInternalSriovPromotePmaStream + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerBaseCtrlCmdInternalSriovPromotePmaStream__ = &profilerBaseCtrlCmdInternalSriovPromotePmaStream_VF; + } + else + { + pThis->__profilerBaseCtrlCmdInternalSriovPromotePmaStream__ = &profilerBaseCtrlCmdInternalSriovPromotePmaStream_108313; + } + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__profilerBaseCtrlCmdInternalPermissionsInit__ = &profilerBaseCtrlCmdInternalPermissionsInit_IMPL; #endif @@ -767,13 +849,25 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCtrlCmdReleaseHes__ = &profilerBaseCtrlCmdReleaseHes_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__profilerBaseCtrlCmdRequestCgControls__ = &profilerBaseCtrlCmdRequestCgControls_IMPL; -#endif + // Hal function -- profilerBaseCtrlCmdRequestCgControls + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerBaseCtrlCmdRequestCgControls__ = &profilerBaseCtrlCmdRequestCgControls_VF; + } + else + { + pThis->__profilerBaseCtrlCmdRequestCgControls__ = &profilerBaseCtrlCmdRequestCgControls_92bfc3; + } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__profilerBaseCtrlCmdReleaseCgControls__ = &profilerBaseCtrlCmdReleaseCgControls_IMPL; -#endif + // Hal function -- profilerBaseCtrlCmdReleaseCgControls + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerBaseCtrlCmdReleaseCgControls__ = &profilerBaseCtrlCmdReleaseCgControls_56cd7a; + } + else + { + pThis->__profilerBaseCtrlCmdReleaseCgControls__ = &profilerBaseCtrlCmdReleaseCgControls_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__profilerBaseCtrlCmdDisableDynamicMMABoost__ = &profilerBaseCtrlCmdDisableDynamicMMABoost_IMPL; @@ -805,8 +899,6 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerBaseControl_Epilogue; - pThis->__profilerBaseControlLookup__ = &__nvoc_thunk_RsResource_profilerBaseControlLookup; - pThis->__profilerBaseGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerBaseGetInternalObjectHandle; pThis->__profilerBaseControl__ = &__nvoc_thunk_GpuResource_profilerBaseControl; @@ -823,6 +915,8 @@ static void __nvoc_init_funcTable_ProfilerBase_1(ProfilerBase *pThis, RmHalspecO pThis->__profilerBaseCanCopy__ = &__nvoc_thunk_RsResource_profilerBaseCanCopy; + pThis->__profilerBaseIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_profilerBaseIsPartialUnmapSupported; + pThis->__profilerBasePreDestruct__ = &__nvoc_thunk_RsResource_profilerBasePreDestruct; pThis->__profilerBaseIsDuplicate__ = &__nvoc_thunk_RsResource_profilerBaseIsDuplicate; @@ -850,23 +944,31 @@ void __nvoc_init_ProfilerBase(ProfilerBase *pThis, RmHalspecOwner *pRmhalspecown __nvoc_init_funcTable_ProfilerBase(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ProfilerBase *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ProfilerBase), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ProfilerBase)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ProfilerBase); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -884,16 +986,25 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase **ppThis, Dynamic *pParent, status = __nvoc_ctor_ProfilerBase(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ProfilerBase_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ProfilerBase_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ProfilerBase)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -901,7 +1012,7 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase **ppThis, Dynamic *pParent, NV_STATUS __nvoc_objCreateDynamic_ProfilerBase(ProfilerBase **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { NV_STATUS status; - struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); status = __nvoc_objCreate_ProfilerBase(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); @@ -929,7 +1040,7 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_ProfilerBase; void __nvoc_init_ProfilerDev(ProfilerDev*, RmHalspecOwner* ); void __nvoc_init_funcTable_ProfilerDev(ProfilerDev*, RmHalspecOwner* ); -NV_STATUS __nvoc_ctor_ProfilerDev(ProfilerDev*, RmHalspecOwner* , struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +NV_STATUS __nvoc_ctor_ProfilerDev(ProfilerDev*, RmHalspecOwner* , CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); void __nvoc_init_dataField_ProfilerDev(ProfilerDev*, RmHalspecOwner* ); void __nvoc_dtor_ProfilerDev(ProfilerDev*); extern const struct NVOC_EXPORT_INFO __nvoc_export_info_ProfilerDev; @@ -1048,10 +1159,6 @@ static void __nvoc_thunk_RmResource_profilerDevControl_Epilogue(struct ProfilerD rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_profilerDevControlLookup(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle(struct ProfilerDev *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ProfilerDev_GpuResource.offset)); } @@ -1084,6 +1191,10 @@ static NvBool __nvoc_thunk_RsResource_profilerDevCanCopy(struct ProfilerDev *pRe return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_profilerDevIsPartialUnmapSupported(struct ProfilerDev *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_profilerDevPreDestruct(struct ProfilerDev *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ProfilerDev_RsResource.offset)); } @@ -1126,8 +1237,8 @@ void __nvoc_init_dataField_ProfilerDev(ProfilerDev *pThis, RmHalspecOwner *pRmha PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); } -NV_STATUS __nvoc_ctor_ProfilerBase(ProfilerBase* , RmHalspecOwner* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); -NV_STATUS __nvoc_ctor_ProfilerDev(ProfilerDev *pThis, RmHalspecOwner *pRmhalspecowner, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_ctor_ProfilerBase(ProfilerBase* , RmHalspecOwner* , CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_ProfilerDev(ProfilerDev *pThis, RmHalspecOwner *pRmhalspecowner, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { NV_STATUS status = NV_OK; status = __nvoc_ctor_ProfilerBase(&pThis->__nvoc_base_ProfilerBase, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_ctor_ProfilerDev_fail_ProfilerBase; @@ -1153,6 +1264,56 @@ static void __nvoc_init_funcTable_ProfilerDev_1(ProfilerDev *pThis, RmHalspecOwn PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); + // Hal function -- profilerDevConstructState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerDevConstructState__ = &profilerDevConstructState_VF; + } + else + { + pThis->__profilerDevConstructState__ = &profilerDevConstructState_IMPL; + } + + // Hal function -- profilerDevConstructStatePrologue + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerDevConstructStatePrologue__ = &profilerDevConstructStatePrologue_92bfc3; + } + else + { + pThis->__profilerDevConstructStatePrologue__ = &profilerDevConstructStatePrologue_FWCLIENT; + } + + // Hal function -- profilerDevConstructStateInterlude + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerDevConstructStateInterlude__ = &profilerDevConstructStateInterlude_92bfc3; + } + else + { + pThis->__profilerDevConstructStateInterlude__ = &profilerDevConstructStateInterlude_IMPL; + } + + // Hal function -- profilerDevConstructStateEpilogue + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerDevConstructStateEpilogue__ = &profilerDevConstructStateEpilogue_92bfc3; + } + else + { + pThis->__profilerDevConstructStateEpilogue__ = &profilerDevConstructStateEpilogue_56cd7a; + } + + // Hal function -- profilerDevDestructState + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__profilerDevDestructState__ = &profilerDevDestructState_b3696a; + } + else + { + pThis->__profilerDevDestructState__ = &profilerDevDestructState_FWCLIENT; + } + pThis->__profilerDevShareCallback__ = &__nvoc_thunk_GpuResource_profilerDevShareCallback; pThis->__profilerDevCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_profilerDevCheckMemInterUnmap; @@ -1175,8 +1336,6 @@ static void __nvoc_init_funcTable_ProfilerDev_1(ProfilerDev *pThis, RmHalspecOwn pThis->__profilerDevControl_Epilogue__ = &__nvoc_thunk_RmResource_profilerDevControl_Epilogue; - pThis->__profilerDevControlLookup__ = &__nvoc_thunk_RsResource_profilerDevControlLookup; - pThis->__profilerDevGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_profilerDevGetInternalObjectHandle; pThis->__profilerDevControl__ = &__nvoc_thunk_GpuResource_profilerDevControl; @@ -1193,6 +1352,8 @@ static void __nvoc_init_funcTable_ProfilerDev_1(ProfilerDev *pThis, RmHalspecOwn pThis->__profilerDevCanCopy__ = &__nvoc_thunk_RsResource_profilerDevCanCopy; + pThis->__profilerDevIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_profilerDevIsPartialUnmapSupported; + pThis->__profilerDevPreDestruct__ = &__nvoc_thunk_RsResource_profilerDevPreDestruct; pThis->__profilerDevIsDuplicate__ = &__nvoc_thunk_RsResource_profilerDevIsDuplicate; @@ -1221,23 +1382,31 @@ void __nvoc_init_ProfilerDev(ProfilerDev *pThis, RmHalspecOwner *pRmhalspecowner __nvoc_init_funcTable_ProfilerDev(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ProfilerDev *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ProfilerDev), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ProfilerDev)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ProfilerDev); pThis->__nvoc_base_ProfilerBase.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ProfilerBase.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -1255,16 +1424,25 @@ NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev **ppThis, Dynamic *pParent, N status = __nvoc_ctor_ProfilerDev(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ProfilerDev_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ProfilerDev_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ProfilerBase.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ProfilerDev)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -1272,7 +1450,7 @@ NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev **ppThis, Dynamic *pParent, N NV_STATUS __nvoc_objCreateDynamic_ProfilerDev(ProfilerDev **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { NV_STATUS status; - struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + CALL_CONTEXT * arg_pCallContext = va_arg(args, CALL_CONTEXT *); struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); status = __nvoc_objCreate_ProfilerDev(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); diff --git a/src/nvidia/generated/g_profiler_v2_nvoc.h b/src/nvidia/generated/g_profiler_v2_nvoc.h index d40973c23c..6811876b64 100644 --- a/src/nvidia/generated/g_profiler_v2_nvoc.h +++ b/src/nvidia/generated/g_profiler_v2_nvoc.h @@ -42,6 +42,7 @@ extern "C" { #include "ctrl/ctrlb0cc.h" #include "gpu/gpu_halspec.h" #include "nvoc/utility.h" +#include "gpu/hwpm/kern_hwpm_common_defs.h" #include "class/clb2cc.h" // MAXWELL_PROFILER_DEVICE @@ -52,11 +53,16 @@ typedef struct NvBool bDevProfilingPermitted; } PROFILER_CLIENT_PERMISSIONS; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_PROFILER_V2_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ProfilerBase { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -66,6 +72,8 @@ struct ProfilerBase { struct RmResource *__nvoc_pbase_RmResource; struct GpuResource *__nvoc_pbase_GpuResource; struct ProfilerBase *__nvoc_pbase_ProfilerBase; + NV_STATUS (*__profilerBaseConstructState__)(struct ProfilerBase *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + void (*__profilerBaseDestructState__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdReserveHwpmLegacy__)(struct ProfilerBase *, NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdInternalReserveHwpmLegacy__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_RESERVE_HWPM_LEGACY_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReleaseHwpmLegacy__)(struct ProfilerBase *); @@ -82,6 +90,8 @@ struct ProfilerBase { NV_STATUS (*__profilerBaseCtrlCmdPmaStreamUpdateGetPut__)(struct ProfilerBase *, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdExecRegops__)(struct ProfilerBase *, NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdInternalAllocPmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdInternalQuiescePmaChannel__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *); + NV_STATUS (*__profilerBaseCtrlCmdInternalSriovPromotePmaStream__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdInternalPermissionsInit__)(struct ProfilerBase *, NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS *); NV_STATUS (*__profilerBaseCtrlCmdReservePmAreaPcSampler__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseCtrlCmdReleasePmAreaPcSampler__)(struct ProfilerBase *); @@ -105,7 +115,6 @@ struct ProfilerBase { NV_STATUS (*__profilerBaseInternalControlForward__)(struct ProfilerBase *, NvU32, void *, NvU32); NV_STATUS (*__profilerBaseUnmapFrom__)(struct ProfilerBase *, RS_RES_UNMAP_FROM_PARAMS *); void (*__profilerBaseControl_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerBaseControlLookup__)(struct ProfilerBase *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__profilerBaseGetInternalObjectHandle__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseControl__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerBaseUnmap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -114,6 +123,7 @@ struct ProfilerBase { NV_STATUS (*__profilerBaseControlFilter__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerBaseControlSerialization_Prologue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__profilerBaseCanCopy__)(struct ProfilerBase *); + NvBool (*__profilerBaseIsPartialUnmapSupported__)(struct ProfilerBase *); void (*__profilerBasePreDestruct__)(struct ProfilerBase *); NV_STATUS (*__profilerBaseIsDuplicate__)(struct ProfilerBase *, NvHandle, NvBool *); void (*__profilerBaseControlSerialization_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -126,6 +136,10 @@ struct ProfilerBase { struct RsResourceRef **ppStreamBuffers; struct RsResourceRef *pBoundCntBuf; struct RsResourceRef *pBoundPmaBuf; + NvU64 profilerId; + HWPM_PMA_STREAM *pPmaStreamList; + NvBool *pBindPointAllocated; + NvBool bMmaBoostDisabled; }; #ifndef __NVOC_CLASS_ProfilerBase_TYPEDEF__ @@ -152,10 +166,14 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_ProfilerBase; NV_STATUS __nvoc_objCreateDynamic_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, va_list); -NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); #define __objCreate_ProfilerBase(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_ProfilerBase((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) +#define profilerBaseConstructState(pProf, pCallContext, pParams) profilerBaseConstructState_DISPATCH(pProf, pCallContext, pParams) +#define profilerBaseConstructState_HAL(pProf, pCallContext, pParams) profilerBaseConstructState_DISPATCH(pProf, pCallContext, pParams) +#define profilerBaseDestructState(pProf) profilerBaseDestructState_DISPATCH(pProf) +#define profilerBaseDestructState_HAL(pProf) profilerBaseDestructState_DISPATCH(pProf) #define profilerBaseCtrlCmdReserveHwpmLegacy(pProfiler, pParams) profilerBaseCtrlCmdReserveHwpmLegacy_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdInternalReserveHwpmLegacy(pProfiler, pParams) profilerBaseCtrlCmdInternalReserveHwpmLegacy_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReleaseHwpmLegacy(pProfiler) profilerBaseCtrlCmdReleaseHwpmLegacy_DISPATCH(pProfiler) @@ -164,14 +182,20 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseCtrlCmdAllocPmaStream(pProfiler, pParams) profilerBaseCtrlCmdAllocPmaStream_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdFreePmaStream(pProfiler, pParams) profilerBaseCtrlCmdFreePmaStream_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdInternalFreePmaStream(pProfiler, pParams) profilerBaseCtrlCmdInternalFreePmaStream_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdInternalFreePmaStream_HAL(pProfiler, pParams) profilerBaseCtrlCmdInternalFreePmaStream_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdInternalGetMaxPmas(pProfiler, pParams) profilerBaseCtrlCmdInternalGetMaxPmas_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdBindPmResources(pProfiler) profilerBaseCtrlCmdBindPmResources_DISPATCH(pProfiler) #define profilerBaseCtrlCmdUnbindPmResources(pProfiler) profilerBaseCtrlCmdUnbindPmResources_DISPATCH(pProfiler) #define profilerBaseCtrlCmdInternalBindPmResources(pProfiler) profilerBaseCtrlCmdInternalBindPmResources_DISPATCH(pProfiler) #define profilerBaseCtrlCmdInternalUnbindPmResources(pProfiler) profilerBaseCtrlCmdInternalUnbindPmResources_DISPATCH(pProfiler) #define profilerBaseCtrlCmdPmaStreamUpdateGetPut(pProfiler, pParams) profilerBaseCtrlCmdPmaStreamUpdateGetPut_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdPmaStreamUpdateGetPut_HAL(pProfiler, pParams) profilerBaseCtrlCmdPmaStreamUpdateGetPut_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdExecRegops(pProfiler, pParams) profilerBaseCtrlCmdExecRegops_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdInternalAllocPmaStream(pProfiler, pParams) profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdInternalAllocPmaStream_HAL(pProfiler, pParams) profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdInternalQuiescePmaChannel(pProfiler, pParams) profilerBaseCtrlCmdInternalQuiescePmaChannel_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdInternalSriovPromotePmaStream(pProfiler, pParams) profilerBaseCtrlCmdInternalSriovPromotePmaStream_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdInternalSriovPromotePmaStream_HAL(pProfiler, pParams) profilerBaseCtrlCmdInternalSriovPromotePmaStream_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdInternalPermissionsInit(pProfiler, pParams) profilerBaseCtrlCmdInternalPermissionsInit_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReservePmAreaPcSampler(pProfiler) profilerBaseCtrlCmdReservePmAreaPcSampler_DISPATCH(pProfiler) #define profilerBaseCtrlCmdReleasePmAreaPcSampler(pProfiler) profilerBaseCtrlCmdReleasePmAreaPcSampler_DISPATCH(pProfiler) @@ -181,7 +205,9 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseCtrlCmdReserveHes(pProfiler, pParams) profilerBaseCtrlCmdReserveHes_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReleaseHes(pProfiler, pParams) profilerBaseCtrlCmdReleaseHes_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdRequestCgControls(pProfiler, pParams) profilerBaseCtrlCmdRequestCgControls_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdRequestCgControls_HAL(pProfiler, pParams) profilerBaseCtrlCmdRequestCgControls_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdReleaseCgControls(pProfiler, pParams) profilerBaseCtrlCmdReleaseCgControls_DISPATCH(pProfiler, pParams) +#define profilerBaseCtrlCmdReleaseCgControls_HAL(pProfiler, pParams) profilerBaseCtrlCmdReleaseCgControls_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdDisableDynamicMMABoost(pProfiler, pParams) profilerBaseCtrlCmdDisableDynamicMMABoost_DISPATCH(pProfiler, pParams) #define profilerBaseCtrlCmdGetDynamicMMABoostStatus(pProfiler, pParams) profilerBaseCtrlCmdGetDynamicMMABoostStatus_DISPATCH(pProfiler, pParams) #define profilerBaseShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerBaseShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) @@ -195,7 +221,6 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseInternalControlForward(pGpuResource, command, pParams, size) profilerBaseInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerBaseUnmapFrom(pResource, pParams) profilerBaseUnmapFrom_DISPATCH(pResource, pParams) #define profilerBaseControl_Epilogue(pResource, pCallContext, pParams) profilerBaseControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define profilerBaseControlLookup(pResource, pParams, ppEntry) profilerBaseControlLookup_DISPATCH(pResource, pParams, ppEntry) #define profilerBaseGetInternalObjectHandle(pGpuResource) profilerBaseGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerBaseControl(pGpuResource, pCallContext, pParams) profilerBaseControl_DISPATCH(pGpuResource, pCallContext, pParams) #define profilerBaseUnmap(pGpuResource, pCallContext, pCpuMapping) profilerBaseUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -204,41 +229,31 @@ NV_STATUS __nvoc_objCreate_ProfilerBase(ProfilerBase**, Dynamic*, NvU32, struct #define profilerBaseControlFilter(pResource, pCallContext, pParams) profilerBaseControlFilter_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseControlSerialization_Prologue(pResource, pCallContext, pParams) profilerBaseControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseCanCopy(pResource) profilerBaseCanCopy_DISPATCH(pResource) +#define profilerBaseIsPartialUnmapSupported(pResource) profilerBaseIsPartialUnmapSupported_DISPATCH(pResource) #define profilerBasePreDestruct(pResource) profilerBasePreDestruct_DISPATCH(pResource) #define profilerBaseIsDuplicate(pResource, hMemory, pDuplicate) profilerBaseIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerBaseControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerBaseControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerBaseMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerBaseMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerBaseAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerBaseAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -static inline NV_STATUS profilerBaseConstructState_56cd7a(struct ProfilerBase *pProf, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { +static inline NV_STATUS profilerBaseConstructState_56cd7a(struct ProfilerBase *pProf, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { return NV_OK; } +NV_STATUS profilerBaseConstructState_IMPL(struct ProfilerBase *pProf, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); -#ifdef __nvoc_profiler_v2_h_disabled -static inline NV_STATUS profilerBaseConstructState(struct ProfilerBase *pProf, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - NV_ASSERT_FAILED_PRECOMP("ProfilerBase was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS profilerBaseConstructState_DISPATCH(struct ProfilerBase *pProf, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return pProf->__profilerBaseConstructState__(pProf, pCallContext, pParams); } -#else //__nvoc_profiler_v2_h_disabled -#define profilerBaseConstructState(pProf, pCallContext, pParams) profilerBaseConstructState_56cd7a(pProf, pCallContext, pParams) -#endif //__nvoc_profiler_v2_h_disabled -#define profilerBaseConstructState_HAL(pProf, pCallContext, pParams) profilerBaseConstructState(pProf, pCallContext, pParams) +void profilerBaseDestructState_VF(struct ProfilerBase *pProf); static inline void profilerBaseDestructState_b3696a(struct ProfilerBase *pProf) { return; } - -#ifdef __nvoc_profiler_v2_h_disabled -static inline void profilerBaseDestructState(struct ProfilerBase *pProf) { - NV_ASSERT_FAILED_PRECOMP("ProfilerBase was disabled!"); +static inline void profilerBaseDestructState_DISPATCH(struct ProfilerBase *pProf) { + pProf->__profilerBaseDestructState__(pProf); } -#else //__nvoc_profiler_v2_h_disabled -#define profilerBaseDestructState(pProf) profilerBaseDestructState_b3696a(pProf) -#endif //__nvoc_profiler_v2_h_disabled - -#define profilerBaseDestructState_HAL(pProf) profilerBaseDestructState(pProf) NV_STATUS profilerBaseCtrlCmdReserveHwpmLegacy_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *pParams); @@ -282,7 +297,11 @@ static inline NV_STATUS profilerBaseCtrlCmdFreePmaStream_DISPATCH(struct Profile return pProfiler->__profilerBaseCtrlCmdFreePmaStream__(pProfiler, pParams); } -NV_STATUS profilerBaseCtrlCmdInternalFreePmaStream_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS *pParams); +NV_STATUS profilerBaseCtrlCmdInternalFreePmaStream_VF(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdInternalFreePmaStream_56cd7a(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS *pParams) { + return NV_OK; +} static inline NV_STATUS profilerBaseCtrlCmdInternalFreePmaStream_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS *pParams) { return pProfiler->__profilerBaseCtrlCmdInternalFreePmaStream__(pProfiler, pParams); @@ -318,7 +337,11 @@ static inline NV_STATUS profilerBaseCtrlCmdInternalUnbindPmResources_DISPATCH(st return pProfiler->__profilerBaseCtrlCmdInternalUnbindPmResources__(pProfiler); } -NV_STATUS profilerBaseCtrlCmdPmaStreamUpdateGetPut_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams); +NV_STATUS profilerBaseCtrlCmdPmaStreamUpdateGetPut_VF(struct ProfilerBase *pProfiler, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdPmaStreamUpdateGetPut_56cd7a(struct ProfilerBase *pProfiler, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams) { + return NV_OK; +} static inline NV_STATUS profilerBaseCtrlCmdPmaStreamUpdateGetPut_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams) { return pProfiler->__profilerBaseCtrlCmdPmaStreamUpdateGetPut__(pProfiler, pParams); @@ -330,12 +353,32 @@ static inline NV_STATUS profilerBaseCtrlCmdExecRegops_DISPATCH(struct ProfilerBa return pProfiler->__profilerBaseCtrlCmdExecRegops__(pProfiler, pParams); } -NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams); +NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_VF(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_56cd7a(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams) { + return NV_OK; +} static inline NV_STATUS profilerBaseCtrlCmdInternalAllocPmaStream_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams) { return pProfiler->__profilerBaseCtrlCmdInternalAllocPmaStream__(pProfiler, pParams); } +NV_STATUS profilerBaseCtrlCmdInternalQuiescePmaChannel_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdInternalQuiescePmaChannel_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdInternalQuiescePmaChannel__(pProfiler, pParams); +} + +static inline NV_STATUS profilerBaseCtrlCmdInternalSriovPromotePmaStream_108313(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((NvBool)(0 != 0))); +} + +NV_STATUS profilerBaseCtrlCmdInternalSriovPromotePmaStream_VF(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdInternalSriovPromotePmaStream_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams) { + return pProfiler->__profilerBaseCtrlCmdInternalSriovPromotePmaStream__(pProfiler, pParams); +} + NV_STATUS profilerBaseCtrlCmdInternalPermissionsInit_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS *pParams); static inline NV_STATUS profilerBaseCtrlCmdInternalPermissionsInit_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_INTERNAL_PERMISSIONS_INIT_PARAMS *pParams) { @@ -384,13 +427,25 @@ static inline NV_STATUS profilerBaseCtrlCmdReleaseHes_DISPATCH(struct ProfilerBa return pProfiler->__profilerBaseCtrlCmdReleaseHes__(pProfiler, pParams); } -NV_STATUS profilerBaseCtrlCmdRequestCgControls_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams); +NV_STATUS profilerBaseCtrlCmdRequestCgControls_VF(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams); + +static inline NV_STATUS profilerBaseCtrlCmdRequestCgControls_92bfc3(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS profilerBaseCtrlCmdRequestCgControls_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams) { return pProfiler->__profilerBaseCtrlCmdRequestCgControls__(pProfiler, pParams); } -NV_STATUS profilerBaseCtrlCmdReleaseCgControls_IMPL(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *pParams); +static inline NV_STATUS profilerBaseCtrlCmdReleaseCgControls_56cd7a(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *pParams) { + return NV_OK; +} + +static inline NV_STATUS profilerBaseCtrlCmdReleaseCgControls_92bfc3(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS profilerBaseCtrlCmdReleaseCgControls_DISPATCH(struct ProfilerBase *pProfiler, NVB0CC_CTRL_POWER_RELEASE_FEATURES_PARAMS *pParams) { return pProfiler->__profilerBaseCtrlCmdReleaseCgControls__(pProfiler, pParams); @@ -452,10 +507,6 @@ static inline void profilerBaseControl_Epilogue_DISPATCH(struct ProfilerBase *pR pResource->__profilerBaseControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS profilerBaseControlLookup_DISPATCH(struct ProfilerBase *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__profilerBaseControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle profilerBaseGetInternalObjectHandle_DISPATCH(struct ProfilerBase *pGpuResource) { return pGpuResource->__profilerBaseGetInternalObjectHandle__(pGpuResource); } @@ -488,6 +539,10 @@ static inline NvBool profilerBaseCanCopy_DISPATCH(struct ProfilerBase *pResource return pResource->__profilerBaseCanCopy__(pResource); } +static inline NvBool profilerBaseIsPartialUnmapSupported_DISPATCH(struct ProfilerBase *pResource) { + return pResource->__profilerBaseIsPartialUnmapSupported__(pResource); +} + static inline void profilerBasePreDestruct_DISPATCH(struct ProfilerBase *pResource) { pResource->__profilerBasePreDestruct__(pResource); } @@ -508,20 +563,35 @@ static inline NvBool profilerBaseAccessCallback_DISPATCH(struct ProfilerBase *pR return pResource->__profilerBaseAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -NV_STATUS profilerBaseConstruct_IMPL(struct ProfilerBase *arg_pProf, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); +NV_STATUS profilerBaseConstruct_IMPL(struct ProfilerBase *arg_pProf, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); #define __nvoc_profilerBaseConstruct(arg_pProf, arg_pCallContext, arg_pParams) profilerBaseConstruct_IMPL(arg_pProf, arg_pCallContext, arg_pParams) void profilerBaseDestruct_IMPL(struct ProfilerBase *pProf); #define __nvoc_profilerBaseDestruct(pProf) profilerBaseDestruct_IMPL(pProf) +NV_STATUS profilerBaseQuiesceStreamout_IMPL(struct ProfilerBase *pProf, OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 pmaChIdx); + +#ifdef __nvoc_profiler_v2_h_disabled +static inline NV_STATUS profilerBaseQuiesceStreamout(struct ProfilerBase *pProf, OBJGPU *pGpu, struct KernelHwpm *pKernelHwpm, NvU32 pmaChIdx) { + NV_ASSERT_FAILED_PRECOMP("ProfilerBase was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_profiler_v2_h_disabled +#define profilerBaseQuiesceStreamout(pProf, pGpu, pKernelHwpm, pmaChIdx) profilerBaseQuiesceStreamout_IMPL(pProf, pGpu, pKernelHwpm, pmaChIdx) +#endif //__nvoc_profiler_v2_h_disabled + #undef PRIVATE_FIELD +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_PROFILER_V2_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ProfilerDev { const struct NVOC_RTTI *__nvoc_rtti; struct ProfilerBase __nvoc_base_ProfilerBase; @@ -532,6 +602,11 @@ struct ProfilerDev { struct GpuResource *__nvoc_pbase_GpuResource; struct ProfilerBase *__nvoc_pbase_ProfilerBase; struct ProfilerDev *__nvoc_pbase_ProfilerDev; + NV_STATUS (*__profilerDevConstructState__)(struct ProfilerDev *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *, PROFILER_CLIENT_PERMISSIONS); + NV_STATUS (*__profilerDevConstructStatePrologue__)(struct ProfilerDev *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + NV_STATUS (*__profilerDevConstructStateInterlude__)(struct ProfilerDev *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *, PROFILER_CLIENT_PERMISSIONS); + NV_STATUS (*__profilerDevConstructStateEpilogue__)(struct ProfilerDev *, CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + void (*__profilerDevDestructState__)(struct ProfilerDev *); NvBool (*__profilerDevShareCallback__)(struct ProfilerDev *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__profilerDevCheckMemInterUnmap__)(struct ProfilerDev *, NvBool); NV_STATUS (*__profilerDevMapTo__)(struct ProfilerDev *, RS_RES_MAP_TO_PARAMS *); @@ -543,7 +618,6 @@ struct ProfilerDev { NV_STATUS (*__profilerDevInternalControlForward__)(struct ProfilerDev *, NvU32, void *, NvU32); NV_STATUS (*__profilerDevUnmapFrom__)(struct ProfilerDev *, RS_RES_UNMAP_FROM_PARAMS *); void (*__profilerDevControl_Epilogue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__profilerDevControlLookup__)(struct ProfilerDev *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__profilerDevGetInternalObjectHandle__)(struct ProfilerDev *); NV_STATUS (*__profilerDevControl__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerDevUnmap__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -552,6 +626,7 @@ struct ProfilerDev { NV_STATUS (*__profilerDevControlFilter__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__profilerDevControlSerialization_Prologue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__profilerDevCanCopy__)(struct ProfilerDev *); + NvBool (*__profilerDevIsPartialUnmapSupported__)(struct ProfilerDev *); void (*__profilerDevPreDestruct__)(struct ProfilerDev *); NV_STATUS (*__profilerDevIsDuplicate__)(struct ProfilerDev *, NvHandle, NvBool *); void (*__profilerDevControlSerialization_Epilogue__)(struct ProfilerDev *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -583,10 +658,20 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_ProfilerDev; NV_STATUS __nvoc_objCreateDynamic_ProfilerDev(ProfilerDev**, Dynamic*, NvU32, va_list); -NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev**, Dynamic*, NvU32, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); #define __objCreate_ProfilerDev(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ __nvoc_objCreate_ProfilerDev((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) +#define profilerDevConstructState(pResource, pCallContext, pParams, clientPermissions) profilerDevConstructState_DISPATCH(pResource, pCallContext, pParams, clientPermissions) +#define profilerDevConstructState_HAL(pResource, pCallContext, pParams, clientPermissions) profilerDevConstructState_DISPATCH(pResource, pCallContext, pParams, clientPermissions) +#define profilerDevConstructStatePrologue(pResource, pCallContext, pParams) profilerDevConstructStatePrologue_DISPATCH(pResource, pCallContext, pParams) +#define profilerDevConstructStatePrologue_HAL(pResource, pCallContext, pParams) profilerDevConstructStatePrologue_DISPATCH(pResource, pCallContext, pParams) +#define profilerDevConstructStateInterlude(pResource, pCallContext, pParams, clientPermissions) profilerDevConstructStateInterlude_DISPATCH(pResource, pCallContext, pParams, clientPermissions) +#define profilerDevConstructStateInterlude_HAL(pResource, pCallContext, pParams, clientPermissions) profilerDevConstructStateInterlude_DISPATCH(pResource, pCallContext, pParams, clientPermissions) +#define profilerDevConstructStateEpilogue(pResource, pCallContext, pParams) profilerDevConstructStateEpilogue_DISPATCH(pResource, pCallContext, pParams) +#define profilerDevConstructStateEpilogue_HAL(pResource, pCallContext, pParams) profilerDevConstructStateEpilogue_DISPATCH(pResource, pCallContext, pParams) +#define profilerDevDestructState(pResource) profilerDevDestructState_DISPATCH(pResource) +#define profilerDevDestructState_HAL(pResource) profilerDevDestructState_DISPATCH(pResource) #define profilerDevShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) profilerDevShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define profilerDevCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) profilerDevCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define profilerDevMapTo(pResource, pParams) profilerDevMapTo_DISPATCH(pResource, pParams) @@ -598,7 +683,6 @@ NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev**, Dynamic*, NvU32, struct CA #define profilerDevInternalControlForward(pGpuResource, command, pParams, size) profilerDevInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define profilerDevUnmapFrom(pResource, pParams) profilerDevUnmapFrom_DISPATCH(pResource, pParams) #define profilerDevControl_Epilogue(pResource, pCallContext, pParams) profilerDevControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define profilerDevControlLookup(pResource, pParams, ppEntry) profilerDevControlLookup_DISPATCH(pResource, pParams, ppEntry) #define profilerDevGetInternalObjectHandle(pGpuResource) profilerDevGetInternalObjectHandle_DISPATCH(pGpuResource) #define profilerDevControl(pGpuResource, pCallContext, pParams) profilerDevControl_DISPATCH(pGpuResource, pCallContext, pParams) #define profilerDevUnmap(pGpuResource, pCallContext, pCpuMapping) profilerDevUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -607,95 +691,78 @@ NV_STATUS __nvoc_objCreate_ProfilerDev(ProfilerDev**, Dynamic*, NvU32, struct CA #define profilerDevControlFilter(pResource, pCallContext, pParams) profilerDevControlFilter_DISPATCH(pResource, pCallContext, pParams) #define profilerDevControlSerialization_Prologue(pResource, pCallContext, pParams) profilerDevControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define profilerDevCanCopy(pResource) profilerDevCanCopy_DISPATCH(pResource) +#define profilerDevIsPartialUnmapSupported(pResource) profilerDevIsPartialUnmapSupported_DISPATCH(pResource) #define profilerDevPreDestruct(pResource) profilerDevPreDestruct_DISPATCH(pResource) #define profilerDevIsDuplicate(pResource, hMemory, pDuplicate) profilerDevIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define profilerDevControlSerialization_Epilogue(pResource, pCallContext, pParams) profilerDevControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define profilerDevMap(pGpuResource, pCallContext, pParams, pCpuMapping) profilerDevMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) #define profilerDevAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) profilerDevAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) -NV_STATUS profilerDevConstructState_IMPL(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); +NvBool profilerDevQueryCapabilities_IMPL(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS *pClientPermissions); #ifdef __nvoc_profiler_v2_h_disabled -static inline NV_STATUS profilerDevConstructState(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions) { +static inline NvBool profilerDevQueryCapabilities(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS *pClientPermissions) { NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); - return NV_ERR_NOT_SUPPORTED; + return NV_FALSE; } #else //__nvoc_profiler_v2_h_disabled -#define profilerDevConstructState(pResource, pCallContext, pParams, clientPermissions) profilerDevConstructState_IMPL(pResource, pCallContext, pParams, clientPermissions) +#define profilerDevQueryCapabilities(pResource, pCallContext, pParams, pClientPermissions) profilerDevQueryCapabilities_IMPL(pResource, pCallContext, pParams, pClientPermissions) #endif //__nvoc_profiler_v2_h_disabled -#define profilerDevConstructState_HAL(pResource, pCallContext, pParams, clientPermissions) profilerDevConstructState(pResource, pCallContext, pParams, clientPermissions) +#define profilerDevQueryCapabilities_HAL(pResource, pCallContext, pParams, pClientPermissions) profilerDevQueryCapabilities(pResource, pCallContext, pParams, pClientPermissions) -NV_STATUS profilerDevConstructStatePrologue_FWCLIENT(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); +NV_STATUS profilerDevConstructState_VF(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); +NV_STATUS profilerDevConstructState_IMPL(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); -#ifdef __nvoc_profiler_v2_h_disabled -static inline NV_STATUS profilerDevConstructStatePrologue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); - return NV_ERR_NOT_SUPPORTED; +static inline NV_STATUS profilerDevConstructState_DISPATCH(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions) { + return pResource->__profilerDevConstructState__(pResource, pCallContext, pParams, clientPermissions); } -#else //__nvoc_profiler_v2_h_disabled -#define profilerDevConstructStatePrologue(pResource, pCallContext, pParams) profilerDevConstructStatePrologue_FWCLIENT(pResource, pCallContext, pParams) -#endif //__nvoc_profiler_v2_h_disabled -#define profilerDevConstructStatePrologue_HAL(pResource, pCallContext, pParams) profilerDevConstructStatePrologue(pResource, pCallContext, pParams) +NV_STATUS profilerDevConstructStatePrologue_FWCLIENT(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams); -NV_STATUS profilerDevConstructStateInterlude_IMPL(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); - - -#ifdef __nvoc_profiler_v2_h_disabled -static inline NV_STATUS profilerDevConstructStateInterlude(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions) { - NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); +static inline NV_STATUS profilerDevConstructStatePrologue_92bfc3(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + NV_ASSERT_PRECOMP(0); return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_profiler_v2_h_disabled -#define profilerDevConstructStateInterlude(pResource, pCallContext, pParams, clientPermissions) profilerDevConstructStateInterlude_IMPL(pResource, pCallContext, pParams, clientPermissions) -#endif //__nvoc_profiler_v2_h_disabled -#define profilerDevConstructStateInterlude_HAL(pResource, pCallContext, pParams, clientPermissions) profilerDevConstructStateInterlude(pResource, pCallContext, pParams, clientPermissions) - -static inline NV_STATUS profilerDevConstructStateEpilogue_56cd7a(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - return NV_OK; +static inline NV_STATUS profilerDevConstructStatePrologue_DISPATCH(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return pResource->__profilerDevConstructStatePrologue__(pResource, pCallContext, pParams); } +NV_STATUS profilerDevConstructStateInterlude_IMPL(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions); -#ifdef __nvoc_profiler_v2_h_disabled -static inline NV_STATUS profilerDevConstructStateEpilogue(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { - NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); +static inline NV_STATUS profilerDevConstructStateInterlude_92bfc3(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions) { + NV_ASSERT_PRECOMP(0); return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_profiler_v2_h_disabled -#define profilerDevConstructStateEpilogue(pResource, pCallContext, pParams) profilerDevConstructStateEpilogue_56cd7a(pResource, pCallContext, pParams) -#endif //__nvoc_profiler_v2_h_disabled -#define profilerDevConstructStateEpilogue_HAL(pResource, pCallContext, pParams) profilerDevConstructStateEpilogue(pResource, pCallContext, pParams) - -NvBool profilerDevQueryCapabilities_IMPL(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS *pClientPermissions); +static inline NV_STATUS profilerDevConstructStateInterlude_DISPATCH(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS clientPermissions) { + return pResource->__profilerDevConstructStateInterlude__(pResource, pCallContext, pParams, clientPermissions); +} +static inline NV_STATUS profilerDevConstructStateEpilogue_56cd7a(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return NV_OK; +} -#ifdef __nvoc_profiler_v2_h_disabled -static inline NvBool profilerDevQueryCapabilities(struct ProfilerDev *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams, PROFILER_CLIENT_PERMISSIONS *pClientPermissions) { - NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); - return NV_FALSE; +static inline NV_STATUS profilerDevConstructStateEpilogue_92bfc3(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; } -#else //__nvoc_profiler_v2_h_disabled -#define profilerDevQueryCapabilities(pResource, pCallContext, pParams, pClientPermissions) profilerDevQueryCapabilities_IMPL(pResource, pCallContext, pParams, pClientPermissions) -#endif //__nvoc_profiler_v2_h_disabled -#define profilerDevQueryCapabilities_HAL(pResource, pCallContext, pParams, pClientPermissions) profilerDevQueryCapabilities(pResource, pCallContext, pParams, pClientPermissions) +static inline NV_STATUS profilerDevConstructStateEpilogue_DISPATCH(struct ProfilerDev *pResource, CALL_CONTEXT *pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *pParams) { + return pResource->__profilerDevConstructStateEpilogue__(pResource, pCallContext, pParams); +} void profilerDevDestructState_FWCLIENT(struct ProfilerDev *pResource); - -#ifdef __nvoc_profiler_v2_h_disabled -static inline void profilerDevDestructState(struct ProfilerDev *pResource) { - NV_ASSERT_FAILED_PRECOMP("ProfilerDev was disabled!"); +static inline void profilerDevDestructState_b3696a(struct ProfilerDev *pResource) { + return; } -#else //__nvoc_profiler_v2_h_disabled -#define profilerDevDestructState(pResource) profilerDevDestructState_FWCLIENT(pResource) -#endif //__nvoc_profiler_v2_h_disabled -#define profilerDevDestructState_HAL(pResource) profilerDevDestructState(pResource) +static inline void profilerDevDestructState_DISPATCH(struct ProfilerDev *pResource) { + pResource->__profilerDevDestructState__(pResource); +} static inline NvBool profilerDevShareCallback_DISPATCH(struct ProfilerDev *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__profilerDevShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); @@ -741,10 +808,6 @@ static inline void profilerDevControl_Epilogue_DISPATCH(struct ProfilerDev *pRes pResource->__profilerDevControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS profilerDevControlLookup_DISPATCH(struct ProfilerDev *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__profilerDevControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle profilerDevGetInternalObjectHandle_DISPATCH(struct ProfilerDev *pGpuResource) { return pGpuResource->__profilerDevGetInternalObjectHandle__(pGpuResource); } @@ -777,6 +840,10 @@ static inline NvBool profilerDevCanCopy_DISPATCH(struct ProfilerDev *pResource) return pResource->__profilerDevCanCopy__(pResource); } +static inline NvBool profilerDevIsPartialUnmapSupported_DISPATCH(struct ProfilerDev *pResource) { + return pResource->__profilerDevIsPartialUnmapSupported__(pResource); +} + static inline void profilerDevPreDestruct_DISPATCH(struct ProfilerDev *pResource) { pResource->__profilerDevPreDestruct__(pResource); } @@ -797,7 +864,7 @@ static inline NvBool profilerDevAccessCallback_DISPATCH(struct ProfilerDev *pRes return pResource->__profilerDevAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); } -NV_STATUS profilerDevConstruct_IMPL(struct ProfilerDev *arg_pResource, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); +NV_STATUS profilerDevConstruct_IMPL(struct ProfilerDev *arg_pResource, CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); #define __nvoc_profilerDevConstruct(arg_pResource, arg_pCallContext, arg_pParams) profilerDevConstruct_IMPL(arg_pResource, arg_pCallContext, arg_pParams) void profilerDevDestruct_IMPL(struct ProfilerDev *pResource); diff --git a/src/nvidia/generated/g_ref_count_nvoc.c b/src/nvidia/generated/g_ref_count_nvoc.c index a16c1ecb0b..30cc51dd7e 100644 --- a/src/nvidia/generated/g_ref_count_nvoc.c +++ b/src/nvidia/generated/g_ref_count_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_OBJREFCNT(OBJREFCNT *pThis) { __nvoc_init_funcTable_OBJREFCNT(pThis); } -NV_STATUS __nvoc_objCreate_OBJREFCNT(OBJREFCNT **ppThis, Dynamic *pParent, NvU32 createFlags, Dynamic * arg_pParent, NvU32 arg_tag, RefcntStateChangeCallback * arg_pStateChangeCallback, RefcntResetCallback * arg_pResetCallback) { +NV_STATUS __nvoc_objCreate_OBJREFCNT(OBJREFCNT **ppThis, Dynamic *pParent, NvU32 createFlags, Dynamic * arg_pParent, NvU32 arg_tag, RefcntStateChangeCallback * arg_pStateChangeCallback, RefcntResetCallback * arg_pResetCallback) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJREFCNT *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJREFCNT), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJREFCNT)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJREFCNT); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_OBJREFCNT(OBJREFCNT **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_OBJREFCNT(pThis, arg_pParent, arg_tag, arg_pStateChangeCallback, arg_pResetCallback); if (status != NV_OK) goto __nvoc_objCreate_OBJREFCNT_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJREFCNT_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJREFCNT)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_ref_count_nvoc.h b/src/nvidia/generated/g_ref_count_nvoc.h index ea72aec267..9129813d75 100644 --- a/src/nvidia/generated/g_ref_count_nvoc.h +++ b/src/nvidia/generated/g_ref_count_nvoc.h @@ -83,16 +83,21 @@ typedef struct OBJREFCNT OBJREFCNT; // kind of class still requires a non-trivial amount of boilerplate to wire // up). // -typedef NV_STATUS RefcntStateChangeCallback(POBJREFCNT, Dynamic *, +typedef NV_STATUS RefcntStateChangeCallback(struct OBJREFCNT *, Dynamic *, REFCNT_STATE, REFCNT_STATE); -typedef void RefcntResetCallback(POBJREFCNT, Dynamic *, NvU64); +typedef void RefcntResetCallback(struct OBJREFCNT *, Dynamic *, NvU64); + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_REF_COUNT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJREFCNT { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -138,16 +143,16 @@ NV_STATUS __nvoc_objCreate_OBJREFCNT(OBJREFCNT**, Dynamic*, NvU32, Dynamic * arg #define __objCreate_OBJREFCNT(ppNewObj, pParent, createFlags, arg_pParent, arg_tag, arg_pStateChangeCallback, arg_pResetCallback) \ __nvoc_objCreate_OBJREFCNT((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pParent, arg_tag, arg_pStateChangeCallback, arg_pResetCallback) -NV_STATUS refcntConstruct_IMPL(POBJREFCNT arg_pRefcnt, Dynamic *arg_pParent, NvU32 arg_tag, RefcntStateChangeCallback *arg_pStateChangeCallback, RefcntResetCallback *arg_pResetCallback); +NV_STATUS refcntConstruct_IMPL(struct OBJREFCNT *arg_pRefcnt, Dynamic *arg_pParent, NvU32 arg_tag, RefcntStateChangeCallback *arg_pStateChangeCallback, RefcntResetCallback *arg_pResetCallback); #define __nvoc_refcntConstruct(arg_pRefcnt, arg_pParent, arg_tag, arg_pStateChangeCallback, arg_pResetCallback) refcntConstruct_IMPL(arg_pRefcnt, arg_pParent, arg_tag, arg_pStateChangeCallback, arg_pResetCallback) -void refcntDestruct_IMPL(POBJREFCNT pRefcnt); +void refcntDestruct_IMPL(struct OBJREFCNT *pRefcnt); #define __nvoc_refcntDestruct(pRefcnt) refcntDestruct_IMPL(pRefcnt) -NV_STATUS refcntRequestReference_IMPL(POBJREFCNT pRefcnt, NvU64 arg0, NvU32 arg1, NvBool arg2); +NV_STATUS refcntRequestReference_IMPL(struct OBJREFCNT *pRefcnt, NvU64 arg0, NvU32 arg1, NvBool arg2); #ifdef __nvoc_ref_count_h_disabled -static inline NV_STATUS refcntRequestReference(POBJREFCNT pRefcnt, NvU64 arg0, NvU32 arg1, NvBool arg2) { +static inline NV_STATUS refcntRequestReference(struct OBJREFCNT *pRefcnt, NvU64 arg0, NvU32 arg1, NvBool arg2) { NV_ASSERT_FAILED_PRECOMP("OBJREFCNT was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -155,10 +160,10 @@ static inline NV_STATUS refcntRequestReference(POBJREFCNT pRefcnt, NvU64 arg0, N #define refcntRequestReference(pRefcnt, arg0, arg1, arg2) refcntRequestReference_IMPL(pRefcnt, arg0, arg1, arg2) #endif //__nvoc_ref_count_h_disabled -NV_STATUS refcntReleaseReferences_IMPL(POBJREFCNT pRefcnt, NvU64 arg0, NvBool arg1); +NV_STATUS refcntReleaseReferences_IMPL(struct OBJREFCNT *pRefcnt, NvU64 arg0, NvBool arg1); #ifdef __nvoc_ref_count_h_disabled -static inline NV_STATUS refcntReleaseReferences(POBJREFCNT pRefcnt, NvU64 arg0, NvBool arg1) { +static inline NV_STATUS refcntReleaseReferences(struct OBJREFCNT *pRefcnt, NvU64 arg0, NvBool arg1) { NV_ASSERT_FAILED_PRECOMP("OBJREFCNT was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -166,10 +171,10 @@ static inline NV_STATUS refcntReleaseReferences(POBJREFCNT pRefcnt, NvU64 arg0, #define refcntReleaseReferences(pRefcnt, arg0, arg1) refcntReleaseReferences_IMPL(pRefcnt, arg0, arg1) #endif //__nvoc_ref_count_h_disabled -NV_STATUS refcntReset_IMPL(POBJREFCNT pRefcnt, NvBool arg0); +NV_STATUS refcntReset_IMPL(struct OBJREFCNT *pRefcnt, NvBool arg0); #ifdef __nvoc_ref_count_h_disabled -static inline NV_STATUS refcntReset(POBJREFCNT pRefcnt, NvBool arg0) { +static inline NV_STATUS refcntReset(struct OBJREFCNT *pRefcnt, NvBool arg0) { NV_ASSERT_FAILED_PRECOMP("OBJREFCNT was disabled!"); return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/generated/g_reg_mem_nvoc.c b/src/nvidia/generated/g_reg_mem_nvoc.c index 5e04684376..0586209000 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.c +++ b/src/nvidia/generated/g_reg_mem_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_regmemControl_Epilogue(struct RegisterMemory rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_regmemControlLookup(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_regmemControl(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_regmemControlSerialization_Prologue(str return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_regmemIsPartialUnmapSupported(struct RegisterMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RegisterMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_regmemIsReady(struct RegisterMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_RegisterMemory_Memory.offset), bCopyConstructorContext); } @@ -261,8 +261,6 @@ static void __nvoc_init_funcTable_RegisterMemory_1(RegisterMemory *pThis) { pThis->__regmemControl_Epilogue__ = &__nvoc_thunk_RmResource_regmemControl_Epilogue; - pThis->__regmemControlLookup__ = &__nvoc_thunk_RsResource_regmemControlLookup; - pThis->__regmemControl__ = &__nvoc_thunk_Memory_regmemControl; pThis->__regmemUnmap__ = &__nvoc_thunk_Memory_regmemUnmap; @@ -275,6 +273,8 @@ static void __nvoc_init_funcTable_RegisterMemory_1(RegisterMemory *pThis) { pThis->__regmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_regmemControlSerialization_Prologue; + pThis->__regmemIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_regmemIsPartialUnmapSupported; + pThis->__regmemIsReady__ = &__nvoc_thunk_Memory_regmemIsReady; pThis->__regmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_regmemCheckCopyPermissions; @@ -306,21 +306,26 @@ void __nvoc_init_RegisterMemory(RegisterMemory *pThis) { __nvoc_init_funcTable_RegisterMemory(pThis); } -NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RegisterMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RegisterMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RegisterMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RegisterMemory); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -335,16 +340,25 @@ NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory **ppThis, Dynamic *pPar status = __nvoc_ctor_RegisterMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_RegisterMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RegisterMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RegisterMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_reg_mem_nvoc.h b/src/nvidia/generated/g_reg_mem_nvoc.h index 80c8c65221..2fe0cf0d11 100644 --- a/src/nvidia/generated/g_reg_mem_nvoc.h +++ b/src/nvidia/generated/g_reg_mem_nvoc.h @@ -41,11 +41,16 @@ extern "C" { * * For security and maintenance reasons we want to phase this class out. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_REG_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RegisterMemory { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -67,13 +72,13 @@ struct RegisterMemory { NvBool (*__regmemIsGpuMapAllowed__)(struct RegisterMemory *, struct OBJGPU *); NV_STATUS (*__regmemUnmapFrom__)(struct RegisterMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__regmemControl_Epilogue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__regmemControlLookup__)(struct RegisterMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__regmemControl__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemUnmap__)(struct RegisterMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__regmemGetMemInterMapParams__)(struct RegisterMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__regmemGetMemoryMappingDescriptor__)(struct RegisterMemory *, MEMORY_DESCRIPTOR **); NV_STATUS (*__regmemControlFilter__)(struct RegisterMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__regmemControlSerialization_Prologue__)(struct RegisterMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__regmemIsPartialUnmapSupported__)(struct RegisterMemory *); NV_STATUS (*__regmemIsReady__)(struct RegisterMemory *, NvBool); NV_STATUS (*__regmemCheckCopyPermissions__)(struct RegisterMemory *, struct OBJGPU *, struct Device *); void (*__regmemPreDestruct__)(struct RegisterMemory *); @@ -123,13 +128,13 @@ NV_STATUS __nvoc_objCreate_RegisterMemory(RegisterMemory**, Dynamic*, NvU32, CAL #define regmemIsGpuMapAllowed(pMemory, pGpu) regmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define regmemUnmapFrom(pResource, pParams) regmemUnmapFrom_DISPATCH(pResource, pParams) #define regmemControl_Epilogue(pResource, pCallContext, pParams) regmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define regmemControlLookup(pResource, pParams, ppEntry) regmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define regmemControl(pMemory, pCallContext, pParams) regmemControl_DISPATCH(pMemory, pCallContext, pParams) #define regmemUnmap(pMemory, pCallContext, pCpuMapping) regmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define regmemGetMemInterMapParams(pMemory, pParams) regmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define regmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) regmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define regmemControlFilter(pResource, pCallContext, pParams) regmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define regmemControlSerialization_Prologue(pResource, pCallContext, pParams) regmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define regmemIsPartialUnmapSupported(pResource) regmemIsPartialUnmapSupported_DISPATCH(pResource) #define regmemIsReady(pMemory, bCopyConstructorContext) regmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define regmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) regmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define regmemPreDestruct(pResource) regmemPreDestruct_DISPATCH(pResource) @@ -187,10 +192,6 @@ static inline void regmemControl_Epilogue_DISPATCH(struct RegisterMemory *pResou pResource->__regmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS regmemControlLookup_DISPATCH(struct RegisterMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__regmemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS regmemControl_DISPATCH(struct RegisterMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__regmemControl__(pMemory, pCallContext, pParams); } @@ -215,6 +216,10 @@ static inline NV_STATUS regmemControlSerialization_Prologue_DISPATCH(struct Regi return pResource->__regmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool regmemIsPartialUnmapSupported_DISPATCH(struct RegisterMemory *pResource) { + return pResource->__regmemIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS regmemIsReady_DISPATCH(struct RegisterMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__regmemIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h index a9a0a1ee80..7450a2ee3b 100644 --- a/src/nvidia/generated/g_resource_fwd_decls_nvoc.h +++ b/src/nvidia/generated/g_resource_fwd_decls_nvoc.h @@ -272,11 +272,16 @@ typedef struct KernelSMDebuggerSession KernelSMDebuggerSession; // NVOC only expand macros inside a class. Use the stub class + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RESOURCE_FWD_DECLS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RmClientResource; #ifndef __NVOC_CLASS_RmClientResource_TYPEDEF__ @@ -288,6 +293,17 @@ typedef struct RmClientResource RmClientResource; #define __nvoc_class_id_RmClientResource 0x37a701 #endif /* __nvoc_class_id_RmClientResource */ +struct ImexSessionApi; + +#ifndef __NVOC_CLASS_ImexSessionApi_TYPEDEF__ +#define __NVOC_CLASS_ImexSessionApi_TYPEDEF__ +typedef struct ImexSessionApi ImexSessionApi; +#endif /* __NVOC_CLASS_ImexSessionApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_ImexSessionApi +#define __nvoc_class_id_ImexSessionApi 0xb4748b +#endif /* __nvoc_class_id_ImexSessionApi */ + struct GpuManagementApi; #ifndef __NVOC_CLASS_GpuManagementApi_TYPEDEF__ @@ -398,6 +414,17 @@ typedef struct PerfBuffer PerfBuffer; #define __nvoc_class_id_PerfBuffer 0x4bc43b #endif /* __nvoc_class_id_PerfBuffer */ +struct VgpuApi; + +#ifndef __NVOC_CLASS_VgpuApi_TYPEDEF__ +#define __NVOC_CLASS_VgpuApi_TYPEDEF__ +typedef struct VgpuApi VgpuApi; +#endif /* __NVOC_CLASS_VgpuApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VgpuApi +#define __nvoc_class_id_VgpuApi 0x7774f5 +#endif /* __nvoc_class_id_VgpuApi */ + struct Hdacodec; #ifndef __NVOC_CLASS_Hdacodec_TYPEDEF__ @@ -651,6 +678,28 @@ typedef struct FlaMemory FlaMemory; #define __nvoc_class_id_FlaMemory 0xe61ee1 #endif /* __nvoc_class_id_FlaMemory */ +struct MemoryExport; + +#ifndef __NVOC_CLASS_MemoryExport_TYPEDEF__ +#define __NVOC_CLASS_MemoryExport_TYPEDEF__ +typedef struct MemoryExport MemoryExport; +#endif /* __NVOC_CLASS_MemoryExport_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryExport +#define __nvoc_class_id_MemoryExport 0xe7ac53 +#endif /* __nvoc_class_id_MemoryExport */ + +struct MemoryFabricImportV2; + +#ifndef __NVOC_CLASS_MemoryFabricImportV2_TYPEDEF__ +#define __NVOC_CLASS_MemoryFabricImportV2_TYPEDEF__ +typedef struct MemoryFabricImportV2 MemoryFabricImportV2; +#endif /* __NVOC_CLASS_MemoryFabricImportV2_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryFabricImportV2 +#define __nvoc_class_id_MemoryFabricImportV2 0xf96871 +#endif /* __nvoc_class_id_MemoryFabricImportV2 */ + struct MemoryFabric; #ifndef __NVOC_CLASS_MemoryFabric_TYPEDEF__ @@ -662,6 +711,17 @@ typedef struct MemoryFabric MemoryFabric; #define __nvoc_class_id_MemoryFabric 0x127499 #endif /* __nvoc_class_id_MemoryFabric */ +struct MemoryFabricImportedRef; + +#ifndef __NVOC_CLASS_MemoryFabricImportedRef_TYPEDEF__ +#define __NVOC_CLASS_MemoryFabricImportedRef_TYPEDEF__ +typedef struct MemoryFabricImportedRef MemoryFabricImportedRef; +#endif /* __NVOC_CLASS_MemoryFabricImportedRef_TYPEDEF__ */ + +#ifndef __nvoc_class_id_MemoryFabricImportedRef +#define __nvoc_class_id_MemoryFabricImportedRef 0x189bad +#endif /* __nvoc_class_id_MemoryFabricImportedRef */ + struct VaSpaceApi; #ifndef __NVOC_CLASS_VaSpaceApi_TYPEDEF__ @@ -684,6 +744,28 @@ typedef struct MemoryMulticastFabric MemoryMulticastFabric; #define __nvoc_class_id_MemoryMulticastFabric 0x130210 #endif /* __nvoc_class_id_MemoryMulticastFabric */ +struct NvencSession; + +#ifndef __NVOC_CLASS_NvencSession_TYPEDEF__ +#define __NVOC_CLASS_NvencSession_TYPEDEF__ +typedef struct NvencSession NvencSession; +#endif /* __NVOC_CLASS_NvencSession_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NvencSession +#define __nvoc_class_id_NvencSession 0x3434af +#endif /* __nvoc_class_id_NvencSession */ + +struct NvfbcSession; + +#ifndef __NVOC_CLASS_NvfbcSession_TYPEDEF__ +#define __NVOC_CLASS_NvfbcSession_TYPEDEF__ +typedef struct NvfbcSession NvfbcSession; +#endif /* __NVOC_CLASS_NvfbcSession_TYPEDEF__ */ + +#ifndef __nvoc_class_id_NvfbcSession +#define __nvoc_class_id_NvfbcSession 0xcbde75 +#endif /* __nvoc_class_id_NvfbcSession */ + struct VgpuConfigApi; #ifndef __NVOC_CLASS_VgpuConfigApi_TYPEDEF__ @@ -1133,6 +1215,7 @@ struct NVOCFwdDeclHack { struct RmClientResource *PRIVATE_FIELD(RmClientResource_NV01_ROOT_CLIENT); struct MpsApi *PRIVATE_FIELD(MpsApi_MPS_COMPUTE); struct FmSessionApi *PRIVATE_FIELD(FmSessionApi_FABRIC_MANAGER_SESSION); + struct ImexSessionApi *PRIVATE_FIELD(ImexSessionApi_NV_IMEX_SESSION); struct GpuManagementApi *PRIVATE_FIELD(GpuManagementApi_NV0020_GPU_MANAGEMENT); struct EventBuffer *PRIVATE_FIELD(EventBuffer_NV_EVENT_BUFFER); struct SemaphoreSurface *PRIVATE_FIELD(SemaphoreSurface_NV_SEMAPHORE_SURFACE); @@ -1144,6 +1227,7 @@ struct NVOCFwdDeclHack { struct Profiler *PRIVATE_FIELD(Profiler_GF100_PROFILER); struct ProfilerDev *PRIVATE_FIELD(ProfilerDev_MAXWELL_PROFILER_DEVICE); struct PerfBuffer *PRIVATE_FIELD(PerfBuffer_G84_PERFBUFFER); + struct VgpuApi *PRIVATE_FIELD(VgpuApi_KEPLER_DEVICE_VGPU); struct Hdacodec *PRIVATE_FIELD(Hdacodec_GF100_HDACODEC); struct KernelChannel *PRIVATE_FIELD(KernelChannel_GF100_CHANNEL_GPFIFO); struct KernelChannel *PRIVATE_FIELD(KernelChannel_KEPLER_CHANNEL_GPFIFO_A); @@ -1177,9 +1261,14 @@ struct NVOCFwdDeclHack { struct MemoryList *PRIVATE_FIELD(MemoryList_NV01_MEMORY_LIST_FBMEM); struct MemoryList *PRIVATE_FIELD(MemoryList_NV01_MEMORY_LIST_OBJECT); struct FlaMemory *PRIVATE_FIELD(FlaMemory_NV01_MEMORY_FLA); + struct MemoryExport *PRIVATE_FIELD(MemoryExport_NV_MEMORY_EXPORT); + struct MemoryFabricImportV2 *PRIVATE_FIELD(MemoryFabricImportV2_NV_MEMORY_FABRIC_IMPORT_V2); struct MemoryFabric *PRIVATE_FIELD(MemoryFabric_NV_MEMORY_FABRIC); + struct MemoryFabricImportedRef *PRIVATE_FIELD(MemoryFabricImportedRef_NV_MEMORY_FABRIC_IMPORTED_REF); struct VaSpaceApi *PRIVATE_FIELD(VaSpaceApi_FERMI_VASPACE_A); struct MemoryMulticastFabric *PRIVATE_FIELD(MemoryMulticastFabric_NV_MEMORY_MULTICAST_FABRIC); + struct NvencSession *PRIVATE_FIELD(NvencSession_NVENC_SW_SESSION); + struct NvfbcSession *PRIVATE_FIELD(NvfbcSession_NVFBC_SW_SESSION); struct VgpuConfigApi *PRIVATE_FIELD(VgpuConfigApi_NVA081_VGPU_CONFIG); struct KernelHostVgpuDeviceApi *PRIVATE_FIELD(KernelHostVgpuDeviceApi_NVA084_KERNEL_HOST_VGPU_DEVICE); struct ThirdPartyP2P *PRIVATE_FIELD(ThirdPartyP2P_NV50_THIRD_PARTY_P2P); diff --git a/src/nvidia/generated/g_resource_nvoc.c b/src/nvidia/generated/g_resource_nvoc.c index 4ff85e6886..d0c2544674 100644 --- a/src/nvidia/generated/g_resource_nvoc.c +++ b/src/nvidia/generated/g_resource_nvoc.c @@ -210,6 +210,10 @@ static NvBool __nvoc_thunk_RsResource_rmresCanCopy(struct RmResource *pResource) return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_rmresIsPartialUnmapSupported(struct RmResource *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_rmresPreDestruct(struct RmResource *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset)); } @@ -222,10 +226,6 @@ static NV_STATUS __nvoc_thunk_RsResource_rmresIsDuplicate(struct RmResource *pRe return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset), hMemory, pDuplicate); } -static NV_STATUS __nvoc_thunk_RsResource_rmresControlLookup(struct RmResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_rmresMap(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RmResource_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -319,14 +319,14 @@ static void __nvoc_init_funcTable_RmResource_1(RmResource *pThis) { pThis->__rmresCanCopy__ = &__nvoc_thunk_RsResource_rmresCanCopy; + pThis->__rmresIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_rmresIsPartialUnmapSupported; + pThis->__rmresPreDestruct__ = &__nvoc_thunk_RsResource_rmresPreDestruct; pThis->__rmresUnmapFrom__ = &__nvoc_thunk_RsResource_rmresUnmapFrom; pThis->__rmresIsDuplicate__ = &__nvoc_thunk_RsResource_rmresIsDuplicate; - pThis->__rmresControlLookup__ = &__nvoc_thunk_RsResource_rmresControlLookup; - pThis->__rmresMap__ = &__nvoc_thunk_RsResource_rmresMap; } @@ -346,21 +346,26 @@ void __nvoc_init_RmResource(RmResource *pThis) { __nvoc_init_funcTable_RmResource(pThis); } -NV_STATUS __nvoc_objCreate_RmResource(RmResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_RmResource(RmResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RmResource *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RmResource), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RmResource)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RmResource); pThis->__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -375,16 +380,25 @@ NV_STATUS __nvoc_objCreate_RmResource(RmResource **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_RmResource(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_RmResource_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RmResource_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RmResource)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_resource_nvoc.h b/src/nvidia/generated/g_resource_nvoc.h index afb12d1fe4..cdd0a3c536 100644 --- a/src/nvidia/generated/g_resource_nvoc.h +++ b/src/nvidia/generated/g_resource_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -53,7 +53,6 @@ struct RMRES_MEM_INTER_MAP_PARAMS OBJGPU *pSrcGpu; struct MEMORY_DESCRIPTOR *pSrcMemDesc; NvHandle hMemoryDevice; - NvBool bDmaMapNeeded; // This flag will be set when this is FLA mapping NvBool bFlaMapping; }; @@ -73,7 +72,6 @@ struct RS_RES_MAP_TO_PARAMS NvU32 flags; ///< [in] NvU64 *pDmaOffset; ///< [inout] NvBool bSubdeviceHandleProvided; ///< [in] - NvBool bDmaMapNeeded; ///< [in] NvBool bFlaMapping; ///< [in] }; @@ -85,6 +83,7 @@ struct RS_RES_UNMAP_FROM_PARAMS NvU32 gpuMask; ///< [in] NvU32 flags; ///< [in] NvU64 dmaOffset; ///< [in] + NvU64 size; ///< [in] struct MEMORY_DESCRIPTOR *pMemDesc; ///< [in] NvBool bSubdeviceHandleProvided; ///< [in] }; @@ -98,7 +97,6 @@ struct RS_INTER_MAP_PRIVATE NvHandle hMemoryDevice; NvU32 gpuMask; NvBool bSubdeviceHandleProvided; - NvBool bDmaMapNeeded; NvBool bFlaMapping; }; @@ -127,11 +125,16 @@ typedef struct RMRES_MEM_INTER_MAP_PARAMS RMRES_MEM_INTER_MAP_PARAMS; /*! * All RsResource subclasses in RM must inherit from this class */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RESOURCE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RmResourceCommon { const struct NVOC_RTTI *__nvoc_rtti; struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; @@ -175,11 +178,16 @@ NV_STATUS rmrescmnConstruct_IMPL(struct RmResourceCommon *arg_pResourceCommmon); * Utility base class for all RsResource subclasses in by RM. Doesn't have to be * used but if it isn't used RmResourceCommon must be inherited manually */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RESOURCE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RmResource { const struct NVOC_RTTI *__nvoc_rtti; struct RsResource __nvoc_base_RsResource; @@ -204,10 +212,10 @@ struct RmResource { NV_STATUS (*__rmresControlFilter__)(struct RmResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__rmresAddAdditionalDependants__)(struct RsClient *, struct RmResource *, RsResourceRef *); NvBool (*__rmresCanCopy__)(struct RmResource *); + NvBool (*__rmresIsPartialUnmapSupported__)(struct RmResource *); void (*__rmresPreDestruct__)(struct RmResource *); NV_STATUS (*__rmresUnmapFrom__)(struct RmResource *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__rmresIsDuplicate__)(struct RmResource *, NvHandle, NvBool *); - NV_STATUS (*__rmresControlLookup__)(struct RmResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__rmresMap__)(struct RmResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvU32 rpcGpuInstance; NvBool bRpcFree; @@ -257,10 +265,10 @@ NV_STATUS __nvoc_objCreate_RmResource(RmResource**, Dynamic*, NvU32, struct CALL #define rmresControlFilter(pResource, pCallContext, pParams) rmresControlFilter_DISPATCH(pResource, pCallContext, pParams) #define rmresAddAdditionalDependants(pClient, pResource, pReference) rmresAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) #define rmresCanCopy(pResource) rmresCanCopy_DISPATCH(pResource) +#define rmresIsPartialUnmapSupported(pResource) rmresIsPartialUnmapSupported_DISPATCH(pResource) #define rmresPreDestruct(pResource) rmresPreDestruct_DISPATCH(pResource) #define rmresUnmapFrom(pResource, pParams) rmresUnmapFrom_DISPATCH(pResource, pParams) #define rmresIsDuplicate(pResource, hMemory, pDuplicate) rmresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) -#define rmresControlLookup(pResource, pParams, ppEntry) rmresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define rmresMap(pResource, pCallContext, pParams, pCpuMapping) rmresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) NvBool rmresAccessCallback_IMPL(struct RmResource *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight); @@ -344,6 +352,10 @@ static inline NvBool rmresCanCopy_DISPATCH(struct RmResource *pResource) { return pResource->__rmresCanCopy__(pResource); } +static inline NvBool rmresIsPartialUnmapSupported_DISPATCH(struct RmResource *pResource) { + return pResource->__rmresIsPartialUnmapSupported__(pResource); +} + static inline void rmresPreDestruct_DISPATCH(struct RmResource *pResource) { pResource->__rmresPreDestruct__(pResource); } @@ -356,10 +368,6 @@ static inline NV_STATUS rmresIsDuplicate_DISPATCH(struct RmResource *pResource, return pResource->__rmresIsDuplicate__(pResource, hMemory, pDuplicate); } -static inline NV_STATUS rmresControlLookup_DISPATCH(struct RmResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__rmresControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS rmresMap_DISPATCH(struct RmResource *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__rmresMap__(pResource, pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_rg_line_callback_nvoc.c b/src/nvidia/generated/g_rg_line_callback_nvoc.c index 8bad33a200..7bc34f1be4 100644 --- a/src/nvidia/generated/g_rg_line_callback_nvoc.c +++ b/src/nvidia/generated/g_rg_line_callback_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_rglcbControl_Epilogue(struct RgLineCallback rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_rglcbControlLookup(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle(struct RgLineCallback *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_RgLineCallback_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_rglcbCanCopy(struct RgLineCallback *pResou return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_rglcbIsPartialUnmapSupported(struct RgLineCallback *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_rglcbPreDestruct(struct RgLineCallback *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RgLineCallback_RsResource.offset)); } @@ -254,8 +254,6 @@ static void __nvoc_init_funcTable_RgLineCallback_1(RgLineCallback *pThis) { pThis->__rglcbControl_Epilogue__ = &__nvoc_thunk_RmResource_rglcbControl_Epilogue; - pThis->__rglcbControlLookup__ = &__nvoc_thunk_RsResource_rglcbControlLookup; - pThis->__rglcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_rglcbGetInternalObjectHandle; pThis->__rglcbControl__ = &__nvoc_thunk_GpuResource_rglcbControl; @@ -272,6 +270,8 @@ static void __nvoc_init_funcTable_RgLineCallback_1(RgLineCallback *pThis) { pThis->__rglcbCanCopy__ = &__nvoc_thunk_RsResource_rglcbCanCopy; + pThis->__rglcbIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_rglcbIsPartialUnmapSupported; + pThis->__rglcbPreDestruct__ = &__nvoc_thunk_RsResource_rglcbPreDestruct; pThis->__rglcbIsDuplicate__ = &__nvoc_thunk_RsResource_rglcbIsDuplicate; @@ -299,21 +299,26 @@ void __nvoc_init_RgLineCallback(RgLineCallback *pThis) { __nvoc_init_funcTable_RgLineCallback(pThis); } -NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RgLineCallback *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RgLineCallback), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RgLineCallback)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RgLineCallback); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -328,16 +333,25 @@ NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback **ppThis, Dynamic *pPar status = __nvoc_ctor_RgLineCallback(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_RgLineCallback_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RgLineCallback_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RgLineCallback)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_rg_line_callback_nvoc.h b/src/nvidia/generated/g_rg_line_callback_nvoc.h index 9166b6dac7..ea5d613f75 100644 --- a/src/nvidia/generated/g_rg_line_callback_nvoc.h +++ b/src/nvidia/generated/g_rg_line_callback_nvoc.h @@ -53,11 +53,16 @@ typedef struct DispCommon DispCommon; /*! * RM internal class representing NV0092_RG_LINE_CALLBACK */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RG_LINE_CALLBACK_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RgLineCallback { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -78,7 +83,6 @@ struct RgLineCallback { NV_STATUS (*__rglcbInternalControlForward__)(struct RgLineCallback *, NvU32, void *, NvU32); NV_STATUS (*__rglcbUnmapFrom__)(struct RgLineCallback *, RS_RES_UNMAP_FROM_PARAMS *); void (*__rglcbControl_Epilogue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__rglcbControlLookup__)(struct RgLineCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__rglcbGetInternalObjectHandle__)(struct RgLineCallback *); NV_STATUS (*__rglcbControl__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rglcbUnmap__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -87,6 +91,7 @@ struct RgLineCallback { NV_STATUS (*__rglcbControlFilter__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__rglcbControlSerialization_Prologue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__rglcbCanCopy__)(struct RgLineCallback *); + NvBool (*__rglcbIsPartialUnmapSupported__)(struct RgLineCallback *); void (*__rglcbPreDestruct__)(struct RgLineCallback *); NV_STATUS (*__rglcbIsDuplicate__)(struct RgLineCallback *, NvHandle, NvBool *); void (*__rglcbControlSerialization_Epilogue__)(struct RgLineCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -140,7 +145,6 @@ NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback**, Dynamic*, NvU32, str #define rglcbInternalControlForward(pGpuResource, command, pParams, size) rglcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define rglcbUnmapFrom(pResource, pParams) rglcbUnmapFrom_DISPATCH(pResource, pParams) #define rglcbControl_Epilogue(pResource, pCallContext, pParams) rglcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define rglcbControlLookup(pResource, pParams, ppEntry) rglcbControlLookup_DISPATCH(pResource, pParams, ppEntry) #define rglcbGetInternalObjectHandle(pGpuResource) rglcbGetInternalObjectHandle_DISPATCH(pGpuResource) #define rglcbControl(pGpuResource, pCallContext, pParams) rglcbControl_DISPATCH(pGpuResource, pCallContext, pParams) #define rglcbUnmap(pGpuResource, pCallContext, pCpuMapping) rglcbUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -149,6 +153,7 @@ NV_STATUS __nvoc_objCreate_RgLineCallback(RgLineCallback**, Dynamic*, NvU32, str #define rglcbControlFilter(pResource, pCallContext, pParams) rglcbControlFilter_DISPATCH(pResource, pCallContext, pParams) #define rglcbControlSerialization_Prologue(pResource, pCallContext, pParams) rglcbControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define rglcbCanCopy(pResource) rglcbCanCopy_DISPATCH(pResource) +#define rglcbIsPartialUnmapSupported(pResource) rglcbIsPartialUnmapSupported_DISPATCH(pResource) #define rglcbPreDestruct(pResource) rglcbPreDestruct_DISPATCH(pResource) #define rglcbIsDuplicate(pResource, hMemory, pDuplicate) rglcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define rglcbControlSerialization_Epilogue(pResource, pCallContext, pParams) rglcbControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -198,10 +203,6 @@ static inline void rglcbControl_Epilogue_DISPATCH(struct RgLineCallback *pResour pResource->__rglcbControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS rglcbControlLookup_DISPATCH(struct RgLineCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__rglcbControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle rglcbGetInternalObjectHandle_DISPATCH(struct RgLineCallback *pGpuResource) { return pGpuResource->__rglcbGetInternalObjectHandle__(pGpuResource); } @@ -234,6 +235,10 @@ static inline NvBool rglcbCanCopy_DISPATCH(struct RgLineCallback *pResource) { return pResource->__rglcbCanCopy__(pResource); } +static inline NvBool rglcbIsPartialUnmapSupported_DISPATCH(struct RgLineCallback *pResource) { + return pResource->__rglcbIsPartialUnmapSupported__(pResource); +} + static inline void rglcbPreDestruct_DISPATCH(struct RgLineCallback *pResource) { pResource->__rglcbPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_rpc-message-header.h b/src/nvidia/generated/g_rpc-message-header.h index db5bd9d620..4146226289 100644 --- a/src/nvidia/generated/g_rpc-message-header.h +++ b/src/nvidia/generated/g_rpc-message-header.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/generated/g_rpc-structures.h b/src/nvidia/generated/g_rpc-structures.h index 0c26e51a3e..9efd9f1c18 100644 --- a/src/nvidia/generated/g_rpc-structures.h +++ b/src/nvidia/generated/g_rpc-structures.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,6 +48,25 @@ typedef struct rpc_set_guest_system_info_v03_00 typedef rpc_set_guest_system_info_v03_00 rpc_set_guest_system_info_v; +typedef struct rpc_set_guest_system_info_ext_v15_02 +{ + char guestDriverBranch[0x100]; + NvU32 domain; + NvU16 bus; + NvU16 device; +} rpc_set_guest_system_info_ext_v15_02; + +typedef rpc_set_guest_system_info_ext_v15_02 rpc_set_guest_system_info_ext_v; + +typedef struct rpc_alloc_root_v07_00 +{ + NvHandle hClient; + NvU32 processID; + char processName[0x64]; +} rpc_alloc_root_v07_00; + +typedef rpc_alloc_root_v07_00 rpc_alloc_root_v; + typedef struct rpc_alloc_memory_v13_01 { NvHandle hClient; @@ -64,6 +83,31 @@ typedef struct rpc_alloc_memory_v13_01 typedef rpc_alloc_memory_v13_01 rpc_alloc_memory_v; +typedef struct rpc_alloc_channel_dma_v1F_04 +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hChannel; + NvU32 hClass; + NvU32 flags; + NV_CHANNEL_ALLOC_PARAMS_v1F_04 params; + NvU32 chid; +} rpc_alloc_channel_dma_v1F_04; + +typedef rpc_alloc_channel_dma_v1F_04 rpc_alloc_channel_dma_v; + +typedef struct rpc_alloc_object_v25_08 +{ + NvHandle hClient; + NvHandle hParent; + NvHandle hObject; + NvU32 hClass; + NvU32 param_len; + alloc_object_params_v25_08 params; +} rpc_alloc_object_v25_08; + +typedef rpc_alloc_object_v25_08 rpc_alloc_object_v; + typedef struct rpc_free_v03_00 { NVOS00_PARAMETERS_v03_00 params; @@ -71,6 +115,15 @@ typedef struct rpc_free_v03_00 typedef rpc_free_v03_00 rpc_free_v; +typedef struct rpc_log_v03_00 +{ + NvU32 level; + NvU32 log_len; + char log_msg[]; +} rpc_log_v03_00; + +typedef rpc_log_v03_00 rpc_log_v; + typedef struct rpc_map_memory_dma_v03_00 { NVOS46_PARAMETERS_v03_00 params; @@ -85,6 +138,14 @@ typedef struct rpc_unmap_memory_dma_v03_00 typedef rpc_unmap_memory_dma_v03_00 rpc_unmap_memory_dma_v; +typedef struct rpc_alloc_subdevice_v08_01 +{ + NvU32 subDeviceInst; + NVOS21_PARAMETERS_v03_00 params; +} rpc_alloc_subdevice_v08_01; + +typedef rpc_alloc_subdevice_v08_01 rpc_alloc_subdevice_v; + typedef struct rpc_dup_object_v03_00 { NVOS55_PARAMETERS_v03_00 params; @@ -102,6 +163,117 @@ typedef struct rpc_idle_channels_v03_00 typedef rpc_idle_channels_v03_00 rpc_idle_channels_v; +typedef struct rpc_alloc_event_v03_00 +{ + NvHandle hClient; + NvHandle hParentClient; + NvHandle hChannel; + NvHandle hObject; + NvHandle hEvent; + NvU32 hClass; + NvU32 notifyIndex; +} rpc_alloc_event_v03_00; + +typedef rpc_alloc_event_v03_00 rpc_alloc_event_v; + +typedef struct rpc_rm_api_control_v25_0D +{ + NVOS54_PARAMETERS_v03_00 params; + NvP64 rm_api_params NV_ALIGN_BYTES(8); +} rpc_rm_api_control_v25_0D; + +typedef struct rpc_rm_api_control_v25_0F +{ + NVOS54_PARAMETERS_v03_00 params; + NvP64 rm_api_params NV_ALIGN_BYTES(8); +} rpc_rm_api_control_v25_0F; + +typedef struct rpc_rm_api_control_v25_10 +{ + NVOS54_PARAMETERS_v03_00 params; + NvP64 rm_api_params NV_ALIGN_BYTES(8); +} rpc_rm_api_control_v25_10; + +typedef struct rpc_rm_api_control_v25_14 +{ + NVOS54_PARAMETERS_v03_00 params; + NvP64 rm_api_params NV_ALIGN_BYTES(8); +} rpc_rm_api_control_v25_14; + +typedef struct rpc_rm_api_control_v25_15 +{ + NVOS54_PARAMETERS_v03_00 params; + NvP64 rm_api_params NV_ALIGN_BYTES(8); +} rpc_rm_api_control_v25_15; + +typedef struct rpc_rm_api_control_v25_16 +{ + NVOS54_PARAMETERS_v03_00 params; + NvP64 rm_api_params NV_ALIGN_BYTES(8); +} rpc_rm_api_control_v25_16; + +typedef struct rpc_rm_api_control_v25_17 +{ + NVOS54_PARAMETERS_v03_00 params; + NvP64 rm_api_params NV_ALIGN_BYTES(8); +} rpc_rm_api_control_v25_17; + +typedef struct rpc_rm_api_control_v25_18 +{ + NVOS54_PARAMETERS_v03_00 params; + NvP64 rm_api_params NV_ALIGN_BYTES(8); +} rpc_rm_api_control_v25_18; + +typedef rpc_rm_api_control_v25_18 rpc_rm_api_control_v; + +typedef struct rpc_alloc_share_device_v03_00 +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 hClass; + NV_DEVICE_ALLOCATION_PARAMETERS_v03_00 params; +} rpc_alloc_share_device_v03_00; + +typedef rpc_alloc_share_device_v03_00 rpc_alloc_share_device_v; + +typedef struct rpc_get_engine_utilization_v1F_0E +{ + NvHandle hClient; + NvHandle hObject; + NvU32 cmd; + vgpuGetEngineUtilization_data_v1F_0E params; +} rpc_get_engine_utilization_v1F_0E; + +typedef rpc_get_engine_utilization_v1F_0E rpc_get_engine_utilization_v; + +typedef struct rpc_perf_get_level_info_v03_00 +{ + NvHandle hClient; + NvHandle hObject; + NvU32 level; + NvU32 flags; + NvU32 perfGetClkInfoListSize; + NvU32 param_size; + NvU32 params[]; +} rpc_perf_get_level_info_v03_00; + +typedef rpc_perf_get_level_info_v03_00 rpc_perf_get_level_info_v; + +typedef struct rpc_set_surface_properties_v07_07 +{ + NvHandle hClient; + NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07 params; +} rpc_set_surface_properties_v07_07; + +typedef rpc_set_surface_properties_v07_07 rpc_set_surface_properties_v; + +typedef struct rpc_cleanup_surface_v03_00 +{ + NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00 params; +} rpc_cleanup_surface_v03_00; + +typedef rpc_cleanup_surface_v03_00 rpc_cleanup_surface_v; + typedef struct rpc_unloading_guest_driver_v1F_07 { NvBool bInPMTransition; @@ -120,12 +292,23 @@ typedef struct rpc_gpu_exec_reg_ops_v12_01 typedef rpc_gpu_exec_reg_ops_v12_01 rpc_gpu_exec_reg_ops_v; -typedef struct rpc_set_page_directory_v03_00 +typedef struct rpc_get_static_data_v25_0E { - NvHandle hClient; - NvHandle hDevice; - NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00 params; -} rpc_set_page_directory_v03_00; + NvU32 offset; + NvU32 size; + NvU8 payload[]; +} rpc_get_static_data_v25_0E; + +typedef rpc_get_static_data_v25_0E rpc_get_static_data_v; + +typedef struct rpc_get_consolidated_gr_static_info_v1B_04 +{ + NvU32 offset; + NvU32 size; + NvU8 payload[]; +} rpc_get_consolidated_gr_static_info_v1B_04; + +typedef rpc_get_consolidated_gr_static_info_v1B_04 rpc_get_consolidated_gr_static_info_v; typedef struct rpc_set_page_directory_v1E_05 { @@ -137,13 +320,6 @@ typedef struct rpc_set_page_directory_v1E_05 typedef rpc_set_page_directory_v1E_05 rpc_set_page_directory_v; -typedef struct rpc_unset_page_directory_v03_00 -{ - NvHandle hClient; - NvHandle hDevice; - NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00 params; -} rpc_unset_page_directory_v03_00; - typedef struct rpc_unset_page_directory_v1E_05 { NvHandle hClient; @@ -167,6 +343,15 @@ typedef struct rpc_update_bar_pde_v15_00 typedef rpc_update_bar_pde_v15_00 rpc_update_bar_pde_v; +typedef struct rpc_get_encoder_capacity_v07_00 +{ + NvHandle hClient; + NvHandle hObject; + NvU32 encoderCapacity; +} rpc_get_encoder_capacity_v07_00; + +typedef rpc_get_encoder_capacity_v07_00 rpc_get_encoder_capacity_v; + typedef struct rpc_vgpu_pf_reg_read32_v15_00 { NvU64 address NV_ALIGN_BYTES(8); @@ -176,554 +361,6236 @@ typedef struct rpc_vgpu_pf_reg_read32_v15_00 typedef rpc_vgpu_pf_reg_read32_v15_00 rpc_vgpu_pf_reg_read32_v; -typedef struct rpc_ctrl_subdevice_get_p2p_caps_v21_02 +typedef struct rpc_ctrl_nvenc_sw_session_update_info_v1A_09 { - NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 ctrlParams; -} rpc_ctrl_subdevice_get_p2p_caps_v21_02; + NvHandle hClient; + NvHandle hObject; + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 nvencSessionUpdate; +} rpc_ctrl_nvenc_sw_session_update_info_v1A_09; -typedef rpc_ctrl_subdevice_get_p2p_caps_v21_02 rpc_ctrl_subdevice_get_p2p_caps_v; +typedef rpc_ctrl_nvenc_sw_session_update_info_v1A_09 rpc_ctrl_nvenc_sw_session_update_info_v; -typedef struct rpc_ctrl_bus_set_p2p_mapping_v21_03 +typedef struct rpc_ctrl_reset_channel_v1A_09 { NvHandle hClient; NvHandle hObject; - NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 params; -} rpc_ctrl_bus_set_p2p_mapping_v21_03; + NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 resetChannel; +} rpc_ctrl_reset_channel_v1A_09; -typedef rpc_ctrl_bus_set_p2p_mapping_v21_03 rpc_ctrl_bus_set_p2p_mapping_v; +typedef rpc_ctrl_reset_channel_v1A_09 rpc_ctrl_reset_channel_v; -typedef struct rpc_ctrl_bus_unset_p2p_mapping_v21_03 +typedef struct rpc_ctrl_reset_isolated_channel_v1A_09 { NvHandle hClient; NvHandle hObject; - NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 params; -} rpc_ctrl_bus_unset_p2p_mapping_v21_03; + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 resetIsolatedChannel; +} rpc_ctrl_reset_isolated_channel_v1A_09; -typedef rpc_ctrl_bus_unset_p2p_mapping_v21_03 rpc_ctrl_bus_unset_p2p_mapping_v; +typedef rpc_ctrl_reset_isolated_channel_v1A_09 rpc_ctrl_reset_isolated_channel_v; -typedef struct rpc_rmfs_init_v15_00 +typedef struct rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 { - NvU64 statusQueuePhysAddr NV_ALIGN_BYTES(8); -} rpc_rmfs_init_v15_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 handleVfPriFault; +} rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09; -typedef rpc_rmfs_init_v15_00 rpc_rmfs_init_v; +typedef rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 rpc_ctrl_gpu_handle_vf_pri_fault_v; -typedef struct rpc_rmfs_test_v15_00 +typedef struct rpc_ctrl_perf_boost_v1A_09 { - NvU32 numReps; - NvU32 flags; - NvU32 testData1; - NvU32 testData2; -} rpc_rmfs_test_v15_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 perfBoost; +} rpc_ctrl_perf_boost_v1A_09; -typedef rpc_rmfs_test_v15_00 rpc_rmfs_test_v; +typedef rpc_ctrl_perf_boost_v1A_09 rpc_ctrl_perf_boost_v; -typedef struct rpc_gsp_set_system_info_v17_00 +typedef struct rpc_ctrl_get_zbc_clear_table_v1A_09 { - NvU32 data; -} rpc_gsp_set_system_info_v17_00; + NvHandle hClient; + NvHandle hObject; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 getZbcClearTable; +} rpc_ctrl_get_zbc_clear_table_v1A_09; -typedef rpc_gsp_set_system_info_v17_00 rpc_gsp_set_system_info_v; +typedef rpc_ctrl_get_zbc_clear_table_v1A_09 rpc_ctrl_get_zbc_clear_table_v; -typedef struct rpc_gsp_rm_alloc_v03_00 +typedef struct rpc_ctrl_set_zbc_color_clear_v1A_09 { NvHandle hClient; - NvHandle hParent; NvHandle hObject; - NvU32 hClass; - NvU32 status; - NvU32 paramsSize; - NvU32 flags; - NvU8 reserved[4]; - NvU8 params[]; -} rpc_gsp_rm_alloc_v03_00; + NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 setZbcColorClr; +} rpc_ctrl_set_zbc_color_clear_v1A_09; -typedef rpc_gsp_rm_alloc_v03_00 rpc_gsp_rm_alloc_v; +typedef rpc_ctrl_set_zbc_color_clear_v1A_09 rpc_ctrl_set_zbc_color_clear_v; -typedef struct rpc_gsp_rm_control_v03_00 +typedef struct rpc_ctrl_set_zbc_depth_clear_v1A_09 { NvHandle hClient; NvHandle hObject; - NvU32 cmd; - NvU32 status; - NvU32 paramsSize; - NvU32 flags; - NvU8 params[]; -} rpc_gsp_rm_control_v03_00; + NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 setZbcDepthClr; +} rpc_ctrl_set_zbc_depth_clear_v1A_09; -typedef rpc_gsp_rm_control_v03_00 rpc_gsp_rm_control_v; +typedef rpc_ctrl_set_zbc_depth_clear_v1A_09 rpc_ctrl_set_zbc_depth_clear_v; -typedef struct rpc_dump_protobuf_component_v18_12 +typedef struct rpc_ctrl_gpfifo_schedule_v1A_0A { - NvU16 component; - NvU8 nvDumpType; - NvBool countOnly; - NvU32 bugCheckCode; - NvU32 internalCode; - NvU32 bufferSize; - NvU8 blob[]; -} rpc_dump_protobuf_component_v18_12; + NvHandle hClient; + NvHandle hObject; + NvU32 cmd; + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 gpfifoSchedule; +} rpc_ctrl_gpfifo_schedule_v1A_0A; -typedef rpc_dump_protobuf_component_v18_12 rpc_dump_protobuf_component_v; +typedef rpc_ctrl_gpfifo_schedule_v1A_0A rpc_ctrl_gpfifo_schedule_v; -typedef struct rpc_run_cpu_sequencer_v17_00 +typedef struct rpc_ctrl_set_timeslice_v1A_0A { - NvU32 bufferSizeDWord; - NvU32 cmdIndex; - NvU32 regSaveArea[8]; - NvU32 commandBuffer[]; -} rpc_run_cpu_sequencer_v17_00; + NvHandle hClient; + NvHandle hObject; + NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 setTimeSlice; +} rpc_ctrl_set_timeslice_v1A_0A; -typedef rpc_run_cpu_sequencer_v17_00 rpc_run_cpu_sequencer_v; +typedef rpc_ctrl_set_timeslice_v1A_0A rpc_ctrl_set_timeslice_v; -typedef struct rpc_post_event_v17_00 +typedef struct rpc_ctrl_fifo_disable_channels_v1A_0A { NvHandle hClient; - NvHandle hEvent; - NvU32 notifyIndex; - NvU32 data; - NvU16 info16; - NvU32 status; - NvU32 eventDataSize; - NvBool bNotifyList; - NvU8 eventData[]; -} rpc_post_event_v17_00; + NvHandle hObject; + NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 fifoDisableChannels; +} rpc_ctrl_fifo_disable_channels_v1A_0A; -typedef rpc_post_event_v17_00 rpc_post_event_v; +typedef rpc_ctrl_fifo_disable_channels_v1A_0A rpc_ctrl_fifo_disable_channels_v; -typedef struct rpc_rc_triggered_v17_02 +typedef struct rpc_ctrl_preempt_v1A_0A { - NvU32 nv2080EngineType; - NvU32 chid; - NvU32 exceptType; - NvU32 scope; - NvU16 partitionAttributionId; -} rpc_rc_triggered_v17_02; + NvHandle hClient; + NvHandle hObject; + NVA06C_CTRL_PREEMPT_PARAMS_v09_0A cmdPreempt; +} rpc_ctrl_preempt_v1A_0A; -typedef rpc_rc_triggered_v17_02 rpc_rc_triggered_v; +typedef rpc_ctrl_preempt_v1A_0A rpc_ctrl_preempt_v; -typedef struct rpc_os_error_log_v17_00 +typedef struct rpc_ctrl_set_tsg_interleave_level_v1A_0A { - NvU32 exceptType; - NvU32 runlistId; - NvU32 chid; - char errString[0x100]; -} rpc_os_error_log_v17_00; + NvHandle hClient; + NvHandle hObject; + NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 interleaveLevelTSG; +} rpc_ctrl_set_tsg_interleave_level_v1A_0A; -typedef rpc_os_error_log_v17_00 rpc_os_error_log_v; +typedef rpc_ctrl_set_tsg_interleave_level_v1A_0A rpc_ctrl_set_tsg_interleave_level_v; -typedef struct rpc_rg_line_intr_v17_00 +typedef struct rpc_ctrl_set_channel_interleave_level_v1A_0A { - NvU32 head; - NvU32 rgIntr; -} rpc_rg_line_intr_v17_00; + NvHandle hClient; + NvHandle hObject; + NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 interleaveLevelChannel; +} rpc_ctrl_set_channel_interleave_level_v1A_0A; -typedef rpc_rg_line_intr_v17_00 rpc_rg_line_intr_v; +typedef rpc_ctrl_set_channel_interleave_level_v1A_0A rpc_ctrl_set_channel_interleave_level_v; -typedef struct rpc_display_modeset_v01_00 +typedef struct rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E { - NvBool bModesetStart; - NvU32 minRequiredIsoBandwidthKBPS; - NvU32 minRequiredFloorBandwidthKBPS; -} rpc_display_modeset_v01_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 ctrlParams; +} rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E; -typedef rpc_display_modeset_v01_00 rpc_display_modeset_v; +typedef rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E rpc_ctrl_gr_ctxsw_preemption_bind_v; -typedef struct rpc_gpuacct_perfmon_util_samples_v17_00 +typedef struct rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E { - NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00 params; -} rpc_gpuacct_perfmon_util_samples_v17_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 ctrlParams; +} rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E; -typedef rpc_gpuacct_perfmon_util_samples_v17_00 rpc_gpuacct_perfmon_util_samples_v; +typedef rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E rpc_ctrl_gr_set_ctxsw_preemption_mode_v; -typedef struct rpc_vgpu_gsp_plugin_triggered_v17_00 +typedef struct rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E { - NvU32 gfid; - NvU32 notifyIndex; -} rpc_vgpu_gsp_plugin_triggered_v17_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 ctrlParams; +} rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E; -typedef rpc_vgpu_gsp_plugin_triggered_v17_00 rpc_vgpu_gsp_plugin_triggered_v; +typedef rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E rpc_ctrl_gr_ctxsw_zcull_bind_v; -typedef struct rpc_vgpu_config_event_v17_00 +typedef struct rpc_ctrl_gpu_initialize_ctx_v1A_0E { - NvU32 notifyIndex; -} rpc_vgpu_config_event_v17_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 ctrlParams; +} rpc_ctrl_gpu_initialize_ctx_v1A_0E; -typedef rpc_vgpu_config_event_v17_00 rpc_vgpu_config_event_v; +typedef rpc_ctrl_gpu_initialize_ctx_v1A_0E rpc_ctrl_gpu_initialize_ctx_v; -typedef struct rpc_dce_rm_init_v01_00 +typedef struct rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 { - NvBool bInit; -} rpc_dce_rm_init_v01_00; + NvHandle hClient; + NvHandle hObject; + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 ctrlParams; +} rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04; -typedef rpc_dce_rm_init_v01_00 rpc_dce_rm_init_v; +typedef rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 rpc_ctrl_vaspace_copy_server_reserved_pdes_v; -typedef struct rpc_sim_read_v1E_01 +typedef struct rpc_ctrl_mc_service_interrupts_v1A_0E { - char path[0x100]; - NvU32 index; - NvU32 count; -} rpc_sim_read_v1E_01; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 ctrlParams; +} rpc_ctrl_mc_service_interrupts_v1A_0E; -typedef rpc_sim_read_v1E_01 rpc_sim_read_v; +typedef rpc_ctrl_mc_service_interrupts_v1A_0E rpc_ctrl_mc_service_interrupts_v; -typedef struct rpc_sim_write_v1E_01 +typedef struct rpc_ctrl_get_p2p_caps_v2_v1F_0D { - char path[0x100]; - NvU32 index; - NvU32 count; - NvU32 data; -} rpc_sim_write_v1E_01; - -typedef rpc_sim_write_v1E_01 rpc_sim_write_v; + NvU8 iter; + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D]; + NvU32 busPeerIds[VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC]; +} rpc_ctrl_get_p2p_caps_v2_v1F_0D; + +typedef rpc_ctrl_get_p2p_caps_v2_v1F_0D rpc_ctrl_get_p2p_caps_v2_v; -typedef struct rpc_ucode_libos_print_v1E_08 +typedef struct rpc_ctrl_subdevice_get_p2p_caps_v21_02 { - NvU32 ucodeEngDesc; - NvU32 libosPrintBufSize; - NvU8 libosPrintBuf[]; -} rpc_ucode_libos_print_v1E_08; + NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 ctrlParams; +} rpc_ctrl_subdevice_get_p2p_caps_v21_02; -typedef rpc_ucode_libos_print_v1E_08 rpc_ucode_libos_print_v; +typedef rpc_ctrl_subdevice_get_p2p_caps_v21_02 rpc_ctrl_subdevice_get_p2p_caps_v; -typedef struct rpc_init_done_v17_00 +typedef struct rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C { - NvU32 not_used; -} rpc_init_done_v17_00; + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 ctrlParams; +} rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C; -typedef rpc_init_done_v17_00 rpc_init_done_v; +typedef rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C rpc_ctrl_dbg_clear_all_sm_error_states_v; -typedef struct rpc_semaphore_schedule_callback_v17_00 +typedef struct rpc_ctrl_dbg_read_all_sm_error_states_v21_06 { - NvU64 GPUVA NV_ALIGN_BYTES(8); - NvU32 hVASpace; - NvU32 ReleaseValue; - NvU32 Flags; - NvU32 completionStatus; NvHandle hClient; - NvHandle hEvent; -} rpc_semaphore_schedule_callback_v17_00; + NvHandle hObject; + NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 ctrlParams; +} rpc_ctrl_dbg_read_all_sm_error_states_v21_06; -typedef rpc_semaphore_schedule_callback_v17_00 rpc_semaphore_schedule_callback_v; +typedef rpc_ctrl_dbg_read_all_sm_error_states_v21_06 rpc_ctrl_dbg_read_all_sm_error_states_v; -typedef struct rpc_timed_semaphore_release_v01_00 +typedef struct rpc_ctrl_dbg_set_exception_mask_v1A_0C { - NvU64 semaphoreVA NV_ALIGN_BYTES(8); - NvU64 notifierVA NV_ALIGN_BYTES(8); - NvU32 hVASpace; - NvU32 releaseValue; - NvU32 completionStatus; NvHandle hClient; - NvHandle hDevice; -} rpc_timed_semaphore_release_v01_00; + NvHandle hObject; + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 ctrlParams; +} rpc_ctrl_dbg_set_exception_mask_v1A_0C; -typedef rpc_timed_semaphore_release_v01_00 rpc_timed_semaphore_release_v; +typedef rpc_ctrl_dbg_set_exception_mask_v1A_0C rpc_ctrl_dbg_set_exception_mask_v; -typedef struct rpc_perf_gpu_boost_sync_limits_callback_v17_00 +typedef struct rpc_ctrl_gpu_promote_ctx_v1A_20 { - NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 params; -} rpc_perf_gpu_boost_sync_limits_callback_v17_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 promoteCtx; +} rpc_ctrl_gpu_promote_ctx_v1A_20; -typedef rpc_perf_gpu_boost_sync_limits_callback_v17_00 rpc_perf_gpu_boost_sync_limits_callback_v; +typedef rpc_ctrl_gpu_promote_ctx_v1A_20 rpc_ctrl_gpu_promote_ctx_v; -typedef struct rpc_perf_bridgeless_info_update_v17_00 +typedef struct rpc_ctrl_dbg_suspend_context_v1A_10 { - NvU64 bBridgeless NV_ALIGN_BYTES(8); -} rpc_perf_bridgeless_info_update_v17_00; + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 ctrlParams; +} rpc_ctrl_dbg_suspend_context_v1A_10; -typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v; +typedef rpc_ctrl_dbg_suspend_context_v1A_10 rpc_ctrl_dbg_suspend_context_v; -typedef struct rpc_nvlink_fault_up_v17_00 +typedef struct rpc_ctrl_dbg_resume_context_v1A_10 { - NvU32 linkId; -} rpc_nvlink_fault_up_v17_00; + NvHandle hClient; + NvHandle hObject; +} rpc_ctrl_dbg_resume_context_v1A_10; -typedef rpc_nvlink_fault_up_v17_00 rpc_nvlink_fault_up_v; +typedef rpc_ctrl_dbg_resume_context_v1A_10 rpc_ctrl_dbg_resume_context_v; -typedef struct rpc_nvlink_inband_received_data_256_v17_00 +typedef struct rpc_ctrl_dbg_exec_reg_ops_v1A_10 { - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 params; -} rpc_nvlink_inband_received_data_256_v17_00; + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 ctrlParams; +} rpc_ctrl_dbg_exec_reg_ops_v1A_10; -typedef rpc_nvlink_inband_received_data_256_v17_00 rpc_nvlink_inband_received_data_256_v; +typedef rpc_ctrl_dbg_exec_reg_ops_v1A_10 rpc_ctrl_dbg_exec_reg_ops_v; -typedef struct rpc_nvlink_inband_received_data_512_v17_00 +typedef struct rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 { - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 params; -} rpc_nvlink_inband_received_data_512_v17_00; + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 ctrlParams; +} rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10; -typedef rpc_nvlink_inband_received_data_512_v17_00 rpc_nvlink_inband_received_data_512_v; +typedef rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 rpc_ctrl_dbg_set_mode_mmu_debug_v; -typedef struct rpc_nvlink_inband_received_data_1024_v17_00 +typedef struct rpc_ctrl_dbg_read_single_sm_error_state_v21_06 { - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 params; -} rpc_nvlink_inband_received_data_1024_v17_00; + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 ctrlParams; +} rpc_ctrl_dbg_read_single_sm_error_state_v21_06; -typedef rpc_nvlink_inband_received_data_1024_v17_00 rpc_nvlink_inband_received_data_1024_v; +typedef rpc_ctrl_dbg_read_single_sm_error_state_v21_06 rpc_ctrl_dbg_read_single_sm_error_state_v; -typedef struct rpc_nvlink_inband_received_data_2048_v17_00 +typedef struct rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 { - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 params; -} rpc_nvlink_inband_received_data_2048_v17_00; + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 ctrlParams; +} rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10; -typedef rpc_nvlink_inband_received_data_2048_v17_00 rpc_nvlink_inband_received_data_2048_v; +typedef rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 rpc_ctrl_dbg_clear_single_sm_error_state_v; -typedef struct rpc_nvlink_inband_received_data_4096_v17_00 +typedef struct rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 { - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 params; -} rpc_nvlink_inband_received_data_4096_v17_00; + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 ctrlParams; +} rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10; -typedef rpc_nvlink_inband_received_data_4096_v17_00 rpc_nvlink_inband_received_data_4096_v; +typedef rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 rpc_ctrl_dbg_set_mode_errbar_debug_v; -typedef struct rpc_nvlink_is_gpu_degraded_v17_00 +typedef struct rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 { - NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 params; -} rpc_nvlink_is_gpu_degraded_v17_00; + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 ctrlParams; +} rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10; -typedef rpc_nvlink_is_gpu_degraded_v17_00 rpc_nvlink_is_gpu_degraded_v; +typedef rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 rpc_ctrl_dbg_set_next_stop_trigger_type_v; -typedef struct rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 +typedef struct rpc_ctrl_dma_set_default_vaspace_v1A_0E { - NvU32 sysmemPfnBitmapRing; - NvU32 sysmemPfnBitmapRingHi; - NvU32 sysmemPfnBitmap; -} rpc_set_sysmem_dirty_page_tracking_buffer_v20_00; + NvHandle hClient; + NvHandle hObject; + NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 ctrlParams; +} rpc_ctrl_dma_set_default_vaspace_v1A_0E; -typedef rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 rpc_set_sysmem_dirty_page_tracking_buffer_v; +typedef rpc_ctrl_dma_set_default_vaspace_v1A_0E rpc_ctrl_dma_set_default_vaspace_v; -typedef struct rpc_extdev_intr_service_v17_00 +typedef struct rpc_ctrl_get_ce_pce_mask_v1A_0E { - NvU8 lossRegStatus; - NvU8 gainRegStatus; - NvU8 miscRegStatus; - NvBool rmStatus; -} rpc_extdev_intr_service_v17_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 ctrlParams; +} rpc_ctrl_get_ce_pce_mask_v1A_0E; -typedef rpc_extdev_intr_service_v17_00 rpc_extdev_intr_service_v; +typedef rpc_ctrl_get_ce_pce_mask_v1A_0E rpc_ctrl_get_ce_pce_mask_v; -typedef struct rpc_pfm_req_hndlr_state_sync_callback_v21_04 +typedef struct rpc_ctrl_get_zbc_clear_table_entry_v1A_0E { - NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 params; -} rpc_pfm_req_hndlr_state_sync_callback_v21_04; + NvHandle hClient; + NvHandle hObject; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 ctrlParams; +} rpc_ctrl_get_zbc_clear_table_entry_v1A_0E; -typedef rpc_pfm_req_hndlr_state_sync_callback_v21_04 rpc_pfm_req_hndlr_state_sync_callback_v; +typedef rpc_ctrl_get_zbc_clear_table_entry_v1A_0E rpc_ctrl_get_zbc_clear_table_entry_v; -typedef struct rpc_vgpu_gsp_mig_ci_config_v21_03 +typedef struct rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E { - NvU32 execPartCount; - NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; - NvU32 gfid; - NvBool bDelete; -} rpc_vgpu_gsp_mig_ci_config_v21_03; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00 ctrlParams; +} rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E; -typedef rpc_vgpu_gsp_mig_ci_config_v21_03 rpc_vgpu_gsp_mig_ci_config_v; +typedef rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E rpc_ctrl_get_nvlink_peer_id_mask_v; -typedef struct rpc_gsp_lockdown_notice_v17_00 +typedef struct rpc_ctrl_get_nvlink_status_v23_04 { - NvBool bLockdownEngaging; -} rpc_gsp_lockdown_notice_v17_00; + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 ctrlParams; +} rpc_ctrl_get_nvlink_status_v23_04; -typedef rpc_gsp_lockdown_notice_v17_00 rpc_gsp_lockdown_notice_v; +typedef rpc_ctrl_get_nvlink_status_v23_04 rpc_ctrl_get_nvlink_status_v; +typedef struct rpc_ctrl_get_p2p_caps_v1F_0D +{ + NvHandle hClient; + NvHandle hObject; + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D ctrlParams; +} rpc_ctrl_get_p2p_caps_v1F_0D; -#endif +typedef rpc_ctrl_get_p2p_caps_v1F_0D rpc_ctrl_get_p2p_caps_v; -#ifdef RPC_DEBUG_PRINT_STRUCTURES -// These are printable definitions of above structures. These will be used for RPC logging in the vmioplugin. -#define SDK_DEBUG_PRINT_STRUCTURES -#include "g_sdk-structures.h" -#undef SDK_DEBUG_PRINT_STRUCTURES +typedef struct rpc_ctrl_get_p2p_caps_matrix_v1A_0E +{ + NvHandle hClient; + NvHandle hObject; + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A ctrlParams; +} rpc_ctrl_get_p2p_caps_matrix_v1A_0E; -#ifndef SKIP_PRINT_rpc_nop_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nop_v03_00[] = { - { - .vtype = vt_end - } -}; +typedef rpc_ctrl_get_p2p_caps_matrix_v1A_0E rpc_ctrl_get_p2p_caps_matrix_v; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nop_v03_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_nop", - #endif - .fdesc = vmiopd_fdesc_t_rpc_nop_v03_00 -}; -#endif +typedef struct rpc_ctrl_reserve_pm_area_smpc_v1A_0F +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F params; +} rpc_ctrl_reserve_pm_area_smpc_v1A_0F; -#ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMajorNum), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "vgxVersionMajorNum" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMinorNum), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "vgxVersionMinorNum" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersionBufferLength), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "guestDriverVersionBufferLength" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersionBufferLength), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "guestVersionBufferLength" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitleBufferLength), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "guestTitleBufferLength" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestClNum), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "guestClNum" - #endif - }, - { - .vtype = vtype_char_array, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersion), - .array_length = 0x100, - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "guestDriverVersion" - #endif - }, - { - .vtype = vtype_char_array, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersion), - .array_length = 0x100, - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "guestVersion" - #endif - }, - { - .vtype = vtype_char_array, - .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitle), - .array_length = 0x100, - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "guestTitle" - #endif - }, - { - .vtype = vt_end - } -}; +typedef rpc_ctrl_reserve_pm_area_smpc_v1A_0F rpc_ctrl_reserve_pm_area_smpc_v; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_set_guest_system_info", - #endif - .header_length = sizeof(rpc_set_guest_system_info_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00 -}; -#endif +typedef struct rpc_ctrl_reserve_hwpm_legacy_v1A_0F +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F params; +} rpc_ctrl_reserve_hwpm_legacy_v1A_0F; -#ifndef SKIP_PRINT_rpc_alloc_memory_v13_01 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_memory_v13_01[] = { - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClient), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hDevice), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hDevice" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hMemory), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hMemory" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClass), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClass" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, flags), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "flags" - #endif - }, - { +typedef rpc_ctrl_reserve_hwpm_legacy_v1A_0F rpc_ctrl_reserve_hwpm_legacy_v; + +typedef struct rpc_ctrl_b0cc_exec_reg_ops_v1A_0F +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F params; +} rpc_ctrl_b0cc_exec_reg_ops_v1A_0F; + +typedef rpc_ctrl_b0cc_exec_reg_ops_v1A_0F rpc_ctrl_b0cc_exec_reg_ops_v; + +typedef struct rpc_ctrl_bind_pm_resources_v1A_0F +{ + NvHandle hClient; + NvHandle hObject; +} rpc_ctrl_bind_pm_resources_v1A_0F; + +typedef rpc_ctrl_bind_pm_resources_v1A_0F rpc_ctrl_bind_pm_resources_v; + +typedef struct rpc_ctrl_alloc_pma_stream_v1A_14 +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 params; +} rpc_ctrl_alloc_pma_stream_v1A_14; + +typedef rpc_ctrl_alloc_pma_stream_v1A_14 rpc_ctrl_alloc_pma_stream_v; + +typedef struct rpc_ctrl_pma_stream_update_get_put_v1A_14 +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 params; +} rpc_ctrl_pma_stream_update_get_put_v1A_14; + +typedef rpc_ctrl_pma_stream_update_get_put_v1A_14 rpc_ctrl_pma_stream_update_get_put_v; + +typedef struct rpc_ctrl_fb_get_info_v2_v25_0A +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A ctrlParams; +} rpc_ctrl_fb_get_info_v2_v25_0A; + +typedef rpc_ctrl_fb_get_info_v2_v25_0A rpc_ctrl_fb_get_info_v2_v; + +typedef struct rpc_ctrl_fifo_set_channel_properties_v1A_16 +{ + NvHandle hClient; + NvHandle hObject; + NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 ctrlParams; +} rpc_ctrl_fifo_set_channel_properties_v1A_16; + +typedef rpc_ctrl_fifo_set_channel_properties_v1A_16 rpc_ctrl_fifo_set_channel_properties_v; + +typedef struct rpc_ctrl_gpu_evict_ctx_v1A_1C +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 params; +} rpc_ctrl_gpu_evict_ctx_v1A_1C; + +typedef rpc_ctrl_gpu_evict_ctx_v1A_1C rpc_ctrl_gpu_evict_ctx_v; + +typedef struct rpc_ctrl_fb_get_fs_info_v24_00 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 params; +} rpc_ctrl_fb_get_fs_info_v24_00; + +typedef rpc_ctrl_fb_get_fs_info_v24_00 rpc_ctrl_fb_get_fs_info_v; + +typedef struct rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D params; +} rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D; + +typedef rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D rpc_ctrl_grmgr_get_gr_fs_info_v; + +typedef struct rpc_ctrl_stop_channel_v1A_1E +{ + NvHandle hClient; + NvHandle hObject; + NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E params; +} rpc_ctrl_stop_channel_v1A_1E; + +typedef rpc_ctrl_stop_channel_v1A_1E rpc_ctrl_stop_channel_v; + +typedef struct rpc_ctrl_gr_pc_sampling_mode_v1A_1F +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F params; +} rpc_ctrl_gr_pc_sampling_mode_v1A_1F; + +typedef rpc_ctrl_gr_pc_sampling_mode_v1A_1F rpc_ctrl_gr_pc_sampling_mode_v; + +typedef struct rpc_ctrl_perf_rated_tdp_get_status_v1A_1F +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F params; +} rpc_ctrl_perf_rated_tdp_get_status_v1A_1F; + +typedef rpc_ctrl_perf_rated_tdp_get_status_v1A_1F rpc_ctrl_perf_rated_tdp_get_status_v; + +typedef struct rpc_ctrl_perf_rated_tdp_set_control_v1A_1F +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F params; +} rpc_ctrl_perf_rated_tdp_set_control_v1A_1F; + +typedef rpc_ctrl_perf_rated_tdp_set_control_v1A_1F rpc_ctrl_perf_rated_tdp_set_control_v; + +typedef struct rpc_ctrl_timer_set_gr_tick_freq_v1A_1F +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F params; +} rpc_ctrl_timer_set_gr_tick_freq_v1A_1F; + +typedef rpc_ctrl_timer_set_gr_tick_freq_v1A_1F rpc_ctrl_timer_set_gr_tick_freq_v; + +typedef struct rpc_ctrl_free_pma_stream_v1A_1F +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F params; +} rpc_ctrl_free_pma_stream_v1A_1F; + +typedef rpc_ctrl_free_pma_stream_v1A_1F rpc_ctrl_free_pma_stream_v; + +typedef struct rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 params; +} rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23; + +typedef rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v; + +typedef struct rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 +{ + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 params; +} rpc_ctrl_dbg_set_single_sm_single_step_v1C_02; + +typedef rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 rpc_ctrl_dbg_set_single_sm_single_step_v; + +typedef struct rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 +{ + NvHandle hClient; + NvHandle hObject; + NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 params; +} rpc_ctrl_gr_get_tpc_partition_mode_v1C_04; + +typedef rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 rpc_ctrl_gr_get_tpc_partition_mode_v; + +typedef struct rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 +{ + NvHandle hClient; + NvHandle hObject; + NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 params; +} rpc_ctrl_gr_set_tpc_partition_mode_v1C_04; + +typedef rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 rpc_ctrl_gr_set_tpc_partition_mode_v; + +typedef struct rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 +{ + NvHandle hClient; + NvHandle hObject; + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 params; +} rpc_ctrl_internal_promote_fault_method_buffers_v1E_07; + +typedef rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 rpc_ctrl_internal_promote_fault_method_buffers_v; + +typedef struct rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 params; +} rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05; + +typedef rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 rpc_ctrl_internal_memsys_set_zbc_referenced_v; + +typedef struct rpc_ctrl_fabric_memory_describe_v1E_0C +{ + NvHandle hClient; + NvHandle hObject; + NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C params; +} rpc_ctrl_fabric_memory_describe_v1E_0C; + +typedef rpc_ctrl_fabric_memory_describe_v1E_0C rpc_ctrl_fabric_memory_describe_v; + +typedef struct rpc_ctrl_fabric_mem_stats_v1E_0C +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C params; +} rpc_ctrl_fabric_mem_stats_v1E_0C; + +typedef rpc_ctrl_fabric_mem_stats_v1E_0C rpc_ctrl_fabric_mem_stats_v; + +typedef struct rpc_ctrl_bus_set_p2p_mapping_v21_03 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 params; +} rpc_ctrl_bus_set_p2p_mapping_v21_03; + +typedef rpc_ctrl_bus_set_p2p_mapping_v21_03 rpc_ctrl_bus_set_p2p_mapping_v; + +typedef struct rpc_ctrl_bus_unset_p2p_mapping_v21_03 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 params; +} rpc_ctrl_bus_unset_p2p_mapping_v21_03; + +typedef rpc_ctrl_bus_unset_p2p_mapping_v21_03 rpc_ctrl_bus_unset_p2p_mapping_v; + +typedef struct rpc_ctrl_gpu_get_info_v2_v25_11 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 params; +} rpc_ctrl_gpu_get_info_v2_v25_11; + +typedef rpc_ctrl_gpu_get_info_v2_v25_11 rpc_ctrl_gpu_get_info_v2_v; + +typedef struct rpc_ctrl_internal_quiesce_pma_channel_v1C_08 +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 params; +} rpc_ctrl_internal_quiesce_pma_channel_v1C_08; + +typedef rpc_ctrl_internal_quiesce_pma_channel_v1C_08 rpc_ctrl_internal_quiesce_pma_channel_v; + +typedef struct rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C params; +} rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C; + +typedef rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C rpc_ctrl_internal_sriov_promote_pma_stream_v; + +typedef struct rpc_ctrl_exec_partitions_create_v24_05 +{ + NvHandle hClient; + NvHandle hObject; + NvU32 status; + NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 execPartitionsCreate; +} rpc_ctrl_exec_partitions_create_v24_05; + +typedef rpc_ctrl_exec_partitions_create_v24_05 rpc_ctrl_exec_partitions_create_v; + +typedef struct rpc_ctrl_fla_setup_instance_mem_block_v21_05 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 params; +} rpc_ctrl_fla_setup_instance_mem_block_v21_05; + +typedef rpc_ctrl_fla_setup_instance_mem_block_v21_05 rpc_ctrl_fla_setup_instance_mem_block_v; + +typedef struct rpc_ctrl_get_total_hs_credits_v21_08 +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 params; +} rpc_ctrl_get_total_hs_credits_v21_08; + +typedef rpc_ctrl_get_total_hs_credits_v21_08 rpc_ctrl_get_total_hs_credits_v; + +typedef struct rpc_ctrl_get_hs_credits_v21_08 +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 params; +} rpc_ctrl_get_hs_credits_v21_08; + +typedef rpc_ctrl_get_hs_credits_v21_08 rpc_ctrl_get_hs_credits_v; + +typedef struct rpc_ctrl_set_hs_credits_v21_08 +{ + NvHandle hClient; + NvHandle hObject; + NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 params; +} rpc_ctrl_set_hs_credits_v21_08; + +typedef rpc_ctrl_set_hs_credits_v21_08 rpc_ctrl_set_hs_credits_v; + +typedef struct rpc_ctrl_pm_area_pc_sampler_v21_0B +{ + NvHandle hClient; + NvHandle hObject; + NvU32 cmd; +} rpc_ctrl_pm_area_pc_sampler_v21_0B; + +typedef rpc_ctrl_pm_area_pc_sampler_v21_0B rpc_ctrl_pm_area_pc_sampler_v; + +typedef struct rpc_ctrl_exec_partitions_delete_v1F_0A +{ + NvHandle hClient; + NvHandle hObject; + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 execPartitionsDelete; +} rpc_ctrl_exec_partitions_delete_v1F_0A; + +typedef rpc_ctrl_exec_partitions_delete_v1F_0A rpc_ctrl_exec_partitions_delete_v; + +typedef struct rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A +{ + NvHandle hClient; + NvHandle hObject; + NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 workSubmitToken; +} rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A; + +typedef rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A rpc_ctrl_gpfifo_get_work_submit_token_v; + +typedef struct rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A +{ + NvHandle hClient; + NvHandle hObject; + NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 setWorkSubmitTokenIndex; +} rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A; + +typedef rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v; + +typedef struct rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D +{ + NvHandle hClient; + NvHandle hObject; + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B vfErrContIntrMask; +} rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D; + +typedef rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v; + +typedef struct rpc_save_hibernation_data_v1E_0E +{ + NvU32 remainedBytes; + NvU8 payload[]; +} rpc_save_hibernation_data_v1E_0E; + +typedef rpc_save_hibernation_data_v1E_0E rpc_save_hibernation_data_v; + +typedef struct rpc_restore_hibernation_data_v1E_0E +{ + NvU32 remainedBytes; + NvU8 payload[]; +} rpc_restore_hibernation_data_v1E_0E; + +typedef rpc_restore_hibernation_data_v1E_0E rpc_restore_hibernation_data_v; + +typedef struct rpc_ctrl_get_mmu_debug_mode_v1E_06 +{ + NvHandle hClient; + NvHandle hObject; + NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 params; +} rpc_ctrl_get_mmu_debug_mode_v1E_06; + +typedef rpc_ctrl_get_mmu_debug_mode_v1E_06 rpc_ctrl_get_mmu_debug_mode_v; + +typedef struct rpc_disable_channels_v1E_0B +{ + NvU32 bDisable; +} rpc_disable_channels_v1E_0B; + +typedef rpc_disable_channels_v1E_0B rpc_disable_channels_v; + +typedef struct rpc_ctrl_gpu_migratable_ops_v21_07 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 ctrlParams; +} rpc_ctrl_gpu_migratable_ops_v21_07; + +typedef rpc_ctrl_gpu_migratable_ops_v21_07 rpc_ctrl_gpu_migratable_ops_v; + +typedef struct rpc_invalidate_tlb_v23_03 +{ + NvU64 pdbAddress NV_ALIGN_BYTES(8); + NvU32 regVal; +} rpc_invalidate_tlb_v23_03; + +typedef rpc_invalidate_tlb_v23_03 rpc_invalidate_tlb_v; + +typedef struct rpc_get_brand_caps_v25_12 +{ + NvU32 brands; +} rpc_get_brand_caps_v25_12; + +typedef rpc_get_brand_caps_v25_12 rpc_get_brand_caps_v; + +typedef struct rpc_gsp_set_system_info_v17_00 +{ + NvU32 data; +} rpc_gsp_set_system_info_v17_00; + +typedef rpc_gsp_set_system_info_v17_00 rpc_gsp_set_system_info_v; + +typedef struct rpc_gsp_rm_alloc_v03_00 +{ + NvHandle hClient; + NvHandle hParent; + NvHandle hObject; + NvU32 hClass; + NvU32 status; + NvU32 paramsSize; + NvU32 flags; + NvU8 reserved[4]; + NvU8 params[]; +} rpc_gsp_rm_alloc_v03_00; + +typedef rpc_gsp_rm_alloc_v03_00 rpc_gsp_rm_alloc_v; + +typedef struct rpc_gsp_rm_control_v03_00 +{ + NvHandle hClient; + NvHandle hObject; + NvU32 cmd; + NvU32 status; + NvU32 paramsSize; + NvU32 flags; + NvU8 params[]; +} rpc_gsp_rm_control_v03_00; + +typedef rpc_gsp_rm_control_v03_00 rpc_gsp_rm_control_v; + +typedef struct rpc_dump_protobuf_component_v18_12 +{ + NvU16 component; + NvU8 nvDumpType; + NvBool countOnly; + NvU32 bugCheckCode; + NvU32 internalCode; + NvU32 bufferSize; + NvU8 blob[]; +} rpc_dump_protobuf_component_v18_12; + +typedef rpc_dump_protobuf_component_v18_12 rpc_dump_protobuf_component_v; + +typedef struct rpc_run_cpu_sequencer_v17_00 +{ + NvU32 bufferSizeDWord; + NvU32 cmdIndex; + NvU32 regSaveArea[8]; + NvU32 commandBuffer[]; +} rpc_run_cpu_sequencer_v17_00; + +typedef rpc_run_cpu_sequencer_v17_00 rpc_run_cpu_sequencer_v; + +typedef struct rpc_post_event_v17_00 +{ + NvHandle hClient; + NvHandle hEvent; + NvU32 notifyIndex; + NvU32 data; + NvU16 info16; + NvU32 status; + NvU32 eventDataSize; + NvBool bNotifyList; + NvU8 eventData[]; +} rpc_post_event_v17_00; + +typedef rpc_post_event_v17_00 rpc_post_event_v; + +typedef struct rpc_rc_triggered_v17_02 +{ + NvU32 nv2080EngineType; + NvU32 chid; + NvU32 exceptType; + NvU32 scope; + NvU16 partitionAttributionId; + NvU32 rcJournalBufferSize; + NvU8 rcJournalBuffer[]; +} rpc_rc_triggered_v17_02; + +typedef rpc_rc_triggered_v17_02 rpc_rc_triggered_v; + +typedef struct rpc_os_error_log_v17_00 +{ + NvU32 exceptType; + NvU32 runlistId; + NvU32 chid; + char errString[0x100]; +} rpc_os_error_log_v17_00; + +typedef rpc_os_error_log_v17_00 rpc_os_error_log_v; + +typedef struct rpc_rg_line_intr_v17_00 +{ + NvU32 head; + NvU32 rgIntr; +} rpc_rg_line_intr_v17_00; + +typedef rpc_rg_line_intr_v17_00 rpc_rg_line_intr_v; + +typedef struct rpc_display_modeset_v01_00 +{ + NvBool bModesetStart; + NvU32 minRequiredIsoBandwidthKBPS; + NvU32 minRequiredFloorBandwidthKBPS; +} rpc_display_modeset_v01_00; + +typedef rpc_display_modeset_v01_00 rpc_display_modeset_v; + +typedef struct rpc_gpuacct_perfmon_util_samples_v1F_0E +{ + NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E params; +} rpc_gpuacct_perfmon_util_samples_v1F_0E; + +typedef rpc_gpuacct_perfmon_util_samples_v1F_0E rpc_gpuacct_perfmon_util_samples_v; + +typedef struct rpc_vgpu_gsp_plugin_triggered_v17_00 +{ + NvU32 gfid; + NvU32 notifyIndex; +} rpc_vgpu_gsp_plugin_triggered_v17_00; + +typedef rpc_vgpu_gsp_plugin_triggered_v17_00 rpc_vgpu_gsp_plugin_triggered_v; + +typedef struct rpc_vgpu_config_event_v17_00 +{ + NvU32 notifyIndex; +} rpc_vgpu_config_event_v17_00; + +typedef rpc_vgpu_config_event_v17_00 rpc_vgpu_config_event_v; + +typedef struct rpc_dce_rm_init_v01_00 +{ + NvBool bInit; +} rpc_dce_rm_init_v01_00; + +typedef rpc_dce_rm_init_v01_00 rpc_dce_rm_init_v; + +typedef struct rpc_sim_read_v1E_01 +{ + char path[0x100]; + NvU32 index; + NvU32 count; +} rpc_sim_read_v1E_01; + +typedef rpc_sim_read_v1E_01 rpc_sim_read_v; + +typedef struct rpc_sim_write_v1E_01 +{ + char path[0x100]; + NvU32 index; + NvU32 count; + NvU32 data; +} rpc_sim_write_v1E_01; + +typedef rpc_sim_write_v1E_01 rpc_sim_write_v; + +typedef struct rpc_ucode_libos_print_v1E_08 +{ + NvU32 ucodeEngDesc; + NvU32 libosPrintBufSize; + NvU8 libosPrintBuf[]; +} rpc_ucode_libos_print_v1E_08; + +typedef rpc_ucode_libos_print_v1E_08 rpc_ucode_libos_print_v; + +typedef struct rpc_init_done_v17_00 +{ + NvU32 not_used; +} rpc_init_done_v17_00; + +typedef rpc_init_done_v17_00 rpc_init_done_v; + +typedef struct rpc_semaphore_schedule_callback_v17_00 +{ + NvU64 GPUVA NV_ALIGN_BYTES(8); + NvU32 hVASpace; + NvU32 ReleaseValue; + NvU32 Flags; + NvU32 completionStatus; + NvHandle hClient; + NvHandle hEvent; +} rpc_semaphore_schedule_callback_v17_00; + +typedef rpc_semaphore_schedule_callback_v17_00 rpc_semaphore_schedule_callback_v; + +typedef struct rpc_timed_semaphore_release_v01_00 +{ + NvU64 semaphoreVA NV_ALIGN_BYTES(8); + NvU64 notifierVA NV_ALIGN_BYTES(8); + NvU32 hVASpace; + NvU32 releaseValue; + NvU32 completionStatus; + NvHandle hClient; + NvHandle hDevice; +} rpc_timed_semaphore_release_v01_00; + +typedef rpc_timed_semaphore_release_v01_00 rpc_timed_semaphore_release_v; + +typedef struct rpc_perf_gpu_boost_sync_limits_callback_v17_00 +{ + NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 params; +} rpc_perf_gpu_boost_sync_limits_callback_v17_00; + +typedef rpc_perf_gpu_boost_sync_limits_callback_v17_00 rpc_perf_gpu_boost_sync_limits_callback_v; + +typedef struct rpc_perf_bridgeless_info_update_v17_00 +{ + NvU64 bBridgeless NV_ALIGN_BYTES(8); +} rpc_perf_bridgeless_info_update_v17_00; + +typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v; + +typedef struct rpc_nvlink_fault_up_v17_00 +{ + NvU32 linkId; +} rpc_nvlink_fault_up_v17_00; + +typedef rpc_nvlink_fault_up_v17_00 rpc_nvlink_fault_up_v; + +typedef struct rpc_nvlink_inband_received_data_256_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_256_v17_00; + +typedef rpc_nvlink_inband_received_data_256_v17_00 rpc_nvlink_inband_received_data_256_v; + +typedef struct rpc_nvlink_inband_received_data_512_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_512_v17_00; + +typedef rpc_nvlink_inband_received_data_512_v17_00 rpc_nvlink_inband_received_data_512_v; + +typedef struct rpc_nvlink_inband_received_data_1024_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_1024_v17_00; + +typedef rpc_nvlink_inband_received_data_1024_v17_00 rpc_nvlink_inband_received_data_1024_v; + +typedef struct rpc_nvlink_inband_received_data_2048_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_2048_v17_00; + +typedef rpc_nvlink_inband_received_data_2048_v17_00 rpc_nvlink_inband_received_data_2048_v; + +typedef struct rpc_nvlink_inband_received_data_4096_v17_00 +{ + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 params; +} rpc_nvlink_inband_received_data_4096_v17_00; + +typedef rpc_nvlink_inband_received_data_4096_v17_00 rpc_nvlink_inband_received_data_4096_v; + +typedef struct rpc_nvlink_is_gpu_degraded_v17_00 +{ + NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 params; +} rpc_nvlink_is_gpu_degraded_v17_00; + +typedef rpc_nvlink_is_gpu_degraded_v17_00 rpc_nvlink_is_gpu_degraded_v; + +typedef struct rpc_update_gsp_trace_v01_00 +{ + NvU32 records; + NvU32 data; +} rpc_update_gsp_trace_v01_00; + +typedef rpc_update_gsp_trace_v01_00 rpc_update_gsp_trace_v; + +typedef struct rpc_gsp_post_nocat_record_v01_00 +{ + NvU32 data; +} rpc_gsp_post_nocat_record_v01_00; + +typedef rpc_gsp_post_nocat_record_v01_00 rpc_gsp_post_nocat_record_v; + +typedef struct rpc_extdev_intr_service_v17_00 +{ + NvU8 lossRegStatus; + NvU8 gainRegStatus; + NvU8 miscRegStatus; + NvBool rmStatus; +} rpc_extdev_intr_service_v17_00; + +typedef rpc_extdev_intr_service_v17_00 rpc_extdev_intr_service_v; + +typedef struct rpc_pfm_req_hndlr_state_sync_callback_v21_04 +{ + NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 params; +} rpc_pfm_req_hndlr_state_sync_callback_v21_04; + +typedef rpc_pfm_req_hndlr_state_sync_callback_v21_04 rpc_pfm_req_hndlr_state_sync_callback_v; + +typedef struct rpc_vgpu_gsp_mig_ci_config_v21_03 +{ + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NvU32 gfid; + NvBool bDelete; +} rpc_vgpu_gsp_mig_ci_config_v21_03; + +typedef rpc_vgpu_gsp_mig_ci_config_v21_03 rpc_vgpu_gsp_mig_ci_config_v; + +typedef struct rpc_gsp_lockdown_notice_v17_00 +{ + NvBool bLockdownEngaging; +} rpc_gsp_lockdown_notice_v17_00; + +typedef rpc_gsp_lockdown_notice_v17_00 rpc_gsp_lockdown_notice_v; + +typedef struct rpc_ctrl_gpu_query_ecc_status_v24_06 +{ + NvHandle hClient; + NvHandle hObject; + NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06 params; +} rpc_ctrl_gpu_query_ecc_status_v24_06; + +typedef rpc_ctrl_gpu_query_ecc_status_v24_06 rpc_ctrl_gpu_query_ecc_status_v; + +typedef struct rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 +{ + NvHandle hClient; + NvHandle hObject; + NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 ctrlParams; +} rpc_ctrl_dbg_get_mode_mmu_debug_v25_04; + +typedef rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 rpc_ctrl_dbg_get_mode_mmu_debug_v; + +typedef struct rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 +{ + NvU8 bwMode; +} rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09; + +typedef rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v; + +typedef struct rpc_ctrl_nvlink_get_inband_received_data_v25_0C +{ + NvU16 message_type; + NvBool more; + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C payload; +} rpc_ctrl_nvlink_get_inband_received_data_v25_0C; + +typedef rpc_ctrl_nvlink_get_inband_received_data_v25_0C rpc_ctrl_nvlink_get_inband_received_data_v; + + +#endif + +#ifdef RPC_DEBUG_PRINT_STRUCTURES +// These are printable definitions of above structures. These will be used for RPC logging in the vmioplugin. +#define SDK_DEBUG_PRINT_STRUCTURES +#include "g_sdk-structures.h" +#undef SDK_DEBUG_PRINT_STRUCTURES + +#ifndef SKIP_PRINT_rpc_nop_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nop_v03_00[] = { + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nop_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_nop", + #endif + .fdesc = vmiopd_fdesc_t_rpc_nop_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMajorNum), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "vgxVersionMajorNum" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMinorNum), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "vgxVersionMinorNum" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersionBufferLength), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "guestDriverVersionBufferLength" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersionBufferLength), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "guestVersionBufferLength" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitleBufferLength), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "guestTitleBufferLength" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestClNum), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "guestClNum" + #endif + }, + { + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersion), + .array_length = 0x100, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "guestDriverVersion" + #endif + }, + { + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersion), + .array_length = 0x100, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "guestVersion" + #endif + }, + { + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitle), + .array_length = 0x100, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "guestTitle" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_set_guest_system_info", + #endif + .header_length = sizeof(rpc_set_guest_system_info_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_set_guest_system_info_ext_v15_02 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_ext_v15_02[] = { + { + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v15_02, guestDriverBranch), + .array_length = 0x100, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "guestDriverBranch" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v15_02, domain), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "domain" + #endif + }, + { + .vtype = vtype_NvU16, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v15_02, bus), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bus" + #endif + }, + { + .vtype = vtype_NvU16, + .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v15_02, device), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "device" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_ext_v15_02 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_set_guest_system_info_ext", + #endif + .header_length = sizeof(rpc_set_guest_system_info_ext_v15_02), + .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_ext_v15_02 +}; +#endif + +#ifndef SKIP_PRINT_rpc_alloc_root_v07_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_root_v07_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_root_v07_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_root_v07_00, processID), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "processID" + #endif + }, + { + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_alloc_root_v07_00, processName), + .array_length = 0x64, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "processName" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_root_v07_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_alloc_root", + #endif + .header_length = sizeof(rpc_alloc_root_v07_00), + .fdesc = vmiopd_fdesc_t_rpc_alloc_root_v07_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_alloc_memory_v13_01 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_memory_v13_01[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hDevice), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hDevice" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hMemory), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hMemory" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClass), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClass" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, flags), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "flags" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteAdjust), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "pteAdjust" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, format), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "format" + #endif + }, + { + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, length), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "length" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pageCount), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "pageCount" + #endif + }, + { + .vtype = vtype_struct_pte_desc, + .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteDesc), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "pteDesc" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_memory_v13_01 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_alloc_memory", + #endif + .header_length = sizeof(rpc_alloc_memory_v13_01), + .fdesc = vmiopd_fdesc_t_rpc_alloc_memory_v13_01 +}; +#endif + +#ifndef SKIP_PRINT_rpc_alloc_channel_dma_v1F_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_channel_dma_v1F_04[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, hDevice), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hDevice" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, hChannel), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hChannel" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, hClass), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClass" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, flags), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "flags" + #endif + }, + { + .vtype = vtype_NV_CHANNEL_ALLOC_PARAMS_v1F_04, + .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, chid), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "chid" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_channel_dma_v1F_04 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_alloc_channel_dma", + #endif + .header_length = sizeof(rpc_alloc_channel_dma_v1F_04), + .fdesc = vmiopd_fdesc_t_rpc_alloc_channel_dma_v1F_04 +}; +#endif + +#ifndef SKIP_PRINT_rpc_alloc_object_v25_08 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_object_v25_08[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, hParent), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hParent" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, hClass), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClass" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, param_len), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "param_len" + #endif + }, + { + .vtype = vtype_alloc_object_params_v25_08, + .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, params), + .union_member_index_fn = get_union_member_index_rpc_alloc_object_v25_08_params, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_object_v25_08 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_alloc_object", + #endif + .header_length = sizeof(rpc_alloc_object_v25_08), + .fdesc = vmiopd_fdesc_t_rpc_alloc_object_v25_08 +}; +#endif + +#ifndef SKIP_PRINT_rpc_free_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_free_v03_00[] = { + { + .vtype = vtype_NVOS00_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_free_v03_00, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_free_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_free", + #endif + .header_length = sizeof(rpc_free_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_free_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_log_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_log_v03_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_log_v03_00, level), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "level" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_log_v03_00, log_len), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "log_len" + #endif + }, + { + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_log_v03_00, log_msg), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "log_msg" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_log_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_log", + #endif + .header_length = sizeof(rpc_log_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_log_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_map_memory_dma_v03_00[] = { + { + .vtype = vtype_NVOS46_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_map_memory_dma_v03_00, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_map_memory_dma_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_map_memory_dma", + #endif + .header_length = sizeof(rpc_map_memory_dma_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_map_memory_dma_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00[] = { + { + .vtype = vtype_NVOS47_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_unmap_memory_dma_v03_00, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_unmap_memory_dma", + #endif + .header_length = sizeof(rpc_unmap_memory_dma_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_alloc_subdevice_v08_01 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_subdevice_v08_01[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_subdevice_v08_01, subDeviceInst), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "subDeviceInst" + #endif + }, + { + .vtype = vtype_NVOS21_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_alloc_subdevice_v08_01, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_subdevice_v08_01 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_alloc_subdevice", + #endif + .header_length = sizeof(rpc_alloc_subdevice_v08_01), + .fdesc = vmiopd_fdesc_t_rpc_alloc_subdevice_v08_01 +}; +#endif + +#ifndef SKIP_PRINT_rpc_dup_object_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dup_object_v03_00[] = { + { + .vtype = vtype_NVOS55_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_dup_object_v03_00, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dup_object_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_dup_object", + #endif + .header_length = sizeof(rpc_dup_object_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_dup_object_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_idle_channels_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_idle_channels_v03_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, flags), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "flags" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, timeout), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "timeout" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "nchannels" + #endif + }, + { + .vtype = vtype_idle_channel_list_v03_00_array, + .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, channel_list), + .array_length = 0, + .array_length_fn = get_array_length_rpc_idle_channels_v03_00_channel_list, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "channel_list" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_idle_channels_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_idle_channels", + #endif + .header_length = sizeof(rpc_idle_channels_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_idle_channels_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_alloc_event_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_event_v03_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hParentClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hParentClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hChannel), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hChannel" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hEvent), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hEvent" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hClass), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClass" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, notifyIndex), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "notifyIndex" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_event_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_alloc_event", + #endif + .header_length = sizeof(rpc_alloc_event_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_alloc_event_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_0F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_0F[] = { + { + .vtype = vtype_NVOS54_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_0F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvP64, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_0F, rm_api_params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rm_api_params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_0F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_rm_api_control", + #endif + .header_length = sizeof(rpc_rm_api_control_v25_0F), + .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_0F +}; +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_16 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_16[] = { + { + .vtype = vtype_NVOS54_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_16, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvP64, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_16, rm_api_params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rm_api_params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_16 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_rm_api_control", + #endif + .header_length = sizeof(rpc_rm_api_control_v25_16), + .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_16 +}; +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_10 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_10[] = { + { + .vtype = vtype_NVOS54_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_10, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvP64, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_10, rm_api_params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rm_api_params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_10 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_rm_api_control", + #endif + .header_length = sizeof(rpc_rm_api_control_v25_10), + .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_10 +}; +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_15 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_15[] = { + { + .vtype = vtype_NVOS54_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_15, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvP64, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_15, rm_api_params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rm_api_params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_15 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_rm_api_control", + #endif + .header_length = sizeof(rpc_rm_api_control_v25_15), + .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_15 +}; +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_0D +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_0D[] = { + { + .vtype = vtype_NVOS54_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_0D, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvP64, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_0D, rm_api_params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rm_api_params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_0D = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_rm_api_control", + #endif + .header_length = sizeof(rpc_rm_api_control_v25_0D), + .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_0D +}; +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_17 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_17[] = { + { + .vtype = vtype_NVOS54_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_17, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvP64, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_17, rm_api_params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rm_api_params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_17 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_rm_api_control", + #endif + .header_length = sizeof(rpc_rm_api_control_v25_17), + .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_17 +}; +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_18 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_18[] = { + { + .vtype = vtype_NVOS54_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_18, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvP64, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_18, rm_api_params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rm_api_params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_18 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_rm_api_control", + #endif + .header_length = sizeof(rpc_rm_api_control_v25_18), + .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_18 +}; +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_14 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_14[] = { + { + .vtype = vtype_NVOS54_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_14, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vtype_NvP64, + .offset = NV_OFFSETOF(rpc_rm_api_control_v25_14, rm_api_params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rm_api_params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_14 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_rm_api_control", + #endif + .header_length = sizeof(rpc_rm_api_control_v25_14), + .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_14 +}; +#endif + +#ifndef SKIP_PRINT_rpc_alloc_share_device_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_share_device_v03_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_share_device_v03_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_alloc_share_device_v03_00, hDevice), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hDevice" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_alloc_share_device_v03_00, hClass), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClass" + #endif + }, + { + .vtype = vtype_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00, + .offset = NV_OFFSETOF(rpc_alloc_share_device_v03_00, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_share_device_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_alloc_share_device", + #endif + .header_length = sizeof(rpc_alloc_share_device_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_alloc_share_device_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_get_engine_utilization_v1F_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_engine_utilization_v1F_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, cmd), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "cmd" + #endif + }, + { + .vtype = vtype_vgpuGetEngineUtilization_data_v1F_0E, + .offset = NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, params), + .union_member_index_fn = get_union_member_index_rpc_get_engine_utilization_v1F_0E_params, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_engine_utilization_v1F_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_get_engine_utilization", + #endif + .header_length = sizeof(rpc_get_engine_utilization_v1F_0E), + .fdesc = vmiopd_fdesc_t_rpc_get_engine_utilization_v1F_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_perf_get_level_info_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_get_level_info_v03_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, level), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "level" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, flags), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "flags" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, perfGetClkInfoListSize), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "perfGetClkInfoListSize" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, param_size), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "param_size" + #endif + }, + { + .vtype = vtype_NvU32_array, + .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, params), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_get_level_info_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_perf_get_level_info", + #endif + .header_length = sizeof(rpc_perf_get_level_info_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_perf_get_level_info_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_set_surface_properties_v07_07 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_surface_properties_v07_07[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_set_surface_properties_v07_07, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07, + .offset = NV_OFFSETOF(rpc_set_surface_properties_v07_07, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_surface_properties_v07_07 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_set_surface_properties", + #endif + .header_length = sizeof(rpc_set_surface_properties_v07_07), + .fdesc = vmiopd_fdesc_t_rpc_set_surface_properties_v07_07 +}; +#endif + +#ifndef SKIP_PRINT_rpc_cleanup_surface_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_cleanup_surface_v03_00[] = { + { + .vtype = vtype_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_cleanup_surface_v03_00, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_cleanup_surface_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_cleanup_surface", + #endif + .header_length = sizeof(rpc_cleanup_surface_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_cleanup_surface_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = { + { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bInPMTransition), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bInPMTransition" + #endif + }, + { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bGc6Entering), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bGc6Entering" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, newLevel), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "newLevel" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_unloading_guest_driver", + #endif + .header_length = sizeof(rpc_unloading_guest_driver_v1F_07), + .fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07 +}; +#endif + +#ifndef SKIP_PRINT_rpc_switch_to_vga_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_switch_to_vga_v03_00[] = { + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_switch_to_vga_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_switch_to_vga", + #endif + .fdesc = vmiopd_fdesc_t_rpc_switch_to_vga_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_gpu_exec_reg_ops_v12_01, + .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_gpu_exec_reg_ops", + #endif + .header_length = sizeof(rpc_gpu_exec_reg_ops_v12_01), + .fdesc = vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01 +}; +#endif + +#ifndef SKIP_PRINT_rpc_get_static_data_v25_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_static_data_v25_0E[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_get_static_data_v25_0E, offset), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "offset" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_get_static_data_v25_0E, size), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "size" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_get_static_data_v25_0E, payload), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "payload" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_static_data_v25_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_get_static_data", + #endif + .header_length = sizeof(rpc_get_static_data_v25_0E), + .fdesc = vmiopd_fdesc_t_rpc_get_static_data_v25_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_get_consolidated_gr_static_info_v1B_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_consolidated_gr_static_info_v1B_04[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_get_consolidated_gr_static_info_v1B_04, offset), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "offset" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_get_consolidated_gr_static_info_v1B_04, size), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "size" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_get_consolidated_gr_static_info_v1B_04, payload), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "payload" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_consolidated_gr_static_info_v1B_04 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_get_consolidated_gr_static_info", + #endif + .header_length = sizeof(rpc_get_consolidated_gr_static_info_v1B_04), + .fdesc = vmiopd_fdesc_t_rpc_get_consolidated_gr_static_info_v1B_04 +}; +#endif + +#ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v1E_05[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hDevice), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hDevice" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, pasid), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "pasid" + #endif + }, + { + .vtype = vtype_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05, + .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v1E_05 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_set_page_directory", + #endif + .header_length = sizeof(rpc_set_page_directory_v1E_05), + .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v1E_05 +}; +#endif + +#ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hDevice), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hDevice" + #endif + }, + { + .vtype = vtype_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05, + .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_unset_page_directory", + #endif + .header_length = sizeof(rpc_unset_page_directory_v1E_05), + .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05 +}; +#endif + +#ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_get_gsp_static_info_v14_00, data), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "data" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_get_gsp_static_info", + #endif + .header_length = sizeof(rpc_get_gsp_static_info_v14_00), + .fdesc = vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_update_bar_pde_v15_00[] = { + { + .vtype = vtype_UpdateBarPde_v15_00, + .offset = NV_OFFSETOF(rpc_update_bar_pde_v15_00, info), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "info" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_update_bar_pde_v15_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_update_bar_pde", + #endif + .header_length = sizeof(rpc_update_bar_pde_v15_00), + .fdesc = vmiopd_fdesc_t_rpc_update_bar_pde_v15_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_get_encoder_capacity_v07_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_encoder_capacity_v07_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_get_encoder_capacity_v07_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_get_encoder_capacity_v07_00, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_get_encoder_capacity_v07_00, encoderCapacity), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "encoderCapacity" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_encoder_capacity_v07_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_get_encoder_capacity", + #endif + .header_length = sizeof(rpc_get_encoder_capacity_v07_00), + .fdesc = vmiopd_fdesc_t_rpc_get_encoder_capacity_v07_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00[] = { + { + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, address), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "address" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, value), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "value" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, grEngId), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "grEngId" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_vgpu_pf_reg_read32", + #endif + .header_length = sizeof(rpc_vgpu_pf_reg_read32_v15_00), + .fdesc = vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_nvenc_sw_session_update_info_v1A_09[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_nvenc_sw_session_update_info_v1A_09, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_nvenc_sw_session_update_info_v1A_09, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01, + .offset = NV_OFFSETOF(rpc_ctrl_nvenc_sw_session_update_info_v1A_09, nvencSessionUpdate), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "nvencSessionUpdate" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_nvenc_sw_session_update_info", + #endif + .header_length = sizeof(rpc_ctrl_nvenc_sw_session_update_info_v1A_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_reset_channel_v1A_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_reset_channel_v1A_09[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_reset_channel_v1A_09, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_reset_channel_v1A_09, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01, + .offset = NV_OFFSETOF(rpc_ctrl_reset_channel_v1A_09, resetChannel), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "resetChannel" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_reset_channel_v1A_09 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_reset_channel", + #endif + .header_length = sizeof(rpc_ctrl_reset_channel_v1A_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_reset_channel_v1A_09 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_reset_isolated_channel_v1A_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_reset_isolated_channel_v1A_09[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_reset_isolated_channel_v1A_09, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_reset_isolated_channel_v1A_09, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_reset_isolated_channel_v1A_09, resetIsolatedChannel), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "resetIsolatedChannel" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_reset_isolated_channel_v1A_09 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_reset_isolated_channel", + #endif + .header_length = sizeof(rpc_ctrl_reset_isolated_channel_v1A_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_reset_isolated_channel_v1A_09 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09, handleVfPriFault), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "handleVfPriFault" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpu_handle_vf_pri_fault", + #endif + .header_length = sizeof(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_perf_boost_v1A_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_perf_boost_v1A_09[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_perf_boost_v1A_09, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_perf_boost_v1A_09, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_perf_boost_v1A_09, perfBoost), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "perfBoost" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_perf_boost_v1A_09 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_perf_boost", + #endif + .header_length = sizeof(rpc_ctrl_perf_boost_v1A_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_perf_boost_v1A_09 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_zbc_clear_table_v1A_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_zbc_clear_table_v1A_09[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_v1A_09, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_v1A_09, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00, + .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_v1A_09, getZbcClearTable), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "getZbcClearTable" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_zbc_clear_table_v1A_09 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_zbc_clear_table", + #endif + .header_length = sizeof(rpc_ctrl_get_zbc_clear_table_v1A_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_zbc_clear_table_v1A_09 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_set_zbc_color_clear_v1A_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_zbc_color_clear_v1A_09[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_color_clear_v1A_09, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_color_clear_v1A_09, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_color_clear_v1A_09, setZbcColorClr), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "setZbcColorClr" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_zbc_color_clear_v1A_09 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_set_zbc_color_clear", + #endif + .header_length = sizeof(rpc_ctrl_set_zbc_color_clear_v1A_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_zbc_color_clear_v1A_09 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_set_zbc_depth_clear_v1A_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_zbc_depth_clear_v1A_09[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_depth_clear_v1A_09, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_depth_clear_v1A_09, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_depth_clear_v1A_09, setZbcDepthClr), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "setZbcDepthClr" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_zbc_depth_clear_v1A_09 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_set_zbc_depth_clear", + #endif + .header_length = sizeof(rpc_ctrl_set_zbc_depth_clear_v1A_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_zbc_depth_clear_v1A_09 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpfifo_schedule_v1A_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpfifo_schedule_v1A_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_schedule_v1A_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_schedule_v1A_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_schedule_v1A_0A, cmd), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "cmd" + #endif + }, + { + .vtype = vtype_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_schedule_v1A_0A, gpfifoSchedule), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "gpfifoSchedule" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpfifo_schedule_v1A_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpfifo_schedule", + #endif + .header_length = sizeof(rpc_ctrl_gpfifo_schedule_v1A_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpfifo_schedule_v1A_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_set_timeslice_v1A_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_timeslice_v1A_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_timeslice_v1A_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_timeslice_v1A_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00, + .offset = NV_OFFSETOF(rpc_ctrl_set_timeslice_v1A_0A, setTimeSlice), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "setTimeSlice" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_timeslice_v1A_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_set_timeslice", + #endif + .header_length = sizeof(rpc_ctrl_set_timeslice_v1A_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_timeslice_v1A_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fifo_disable_channels_v1A_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fifo_disable_channels_v1A_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_disable_channels_v1A_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_disable_channels_v1A_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_disable_channels_v1A_0A, fifoDisableChannels), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "fifoDisableChannels" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fifo_disable_channels_v1A_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_fifo_disable_channels", + #endif + .header_length = sizeof(rpc_ctrl_fifo_disable_channels_v1A_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_fifo_disable_channels_v1A_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_preempt_v1A_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_preempt_v1A_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_preempt_v1A_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_preempt_v1A_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A, + .offset = NV_OFFSETOF(rpc_ctrl_preempt_v1A_0A, cmdPreempt), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "cmdPreempt" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_preempt_v1A_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_preempt", + #endif + .header_length = sizeof(rpc_ctrl_preempt_v1A_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_preempt_v1A_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_set_tsg_interleave_level_v1A_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_tsg_interleave_level_v1A_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_tsg_interleave_level_v1A_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_tsg_interleave_level_v1A_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02, + .offset = NV_OFFSETOF(rpc_ctrl_set_tsg_interleave_level_v1A_0A, interleaveLevelTSG), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "interleaveLevelTSG" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_tsg_interleave_level_v1A_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_set_tsg_interleave_level", + #endif + .header_length = sizeof(rpc_ctrl_set_tsg_interleave_level_v1A_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_tsg_interleave_level_v1A_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_set_channel_interleave_level_v1A_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_channel_interleave_level_v1A_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_channel_interleave_level_v1A_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_channel_interleave_level_v1A_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02, + .offset = NV_OFFSETOF(rpc_ctrl_set_channel_interleave_level_v1A_0A, interleaveLevelChannel), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "interleaveLevelChannel" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_channel_interleave_level_v1A_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_set_channel_interleave_level", + #endif + .header_length = sizeof(rpc_ctrl_set_channel_interleave_level_v1A_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_channel_interleave_level_v1A_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01, + .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gr_ctxsw_preemption_bind", + #endif + .header_length = sizeof(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01, + .offset = NV_OFFSETOF(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gr_set_ctxsw_preemption_mode", + #endif + .header_length = sizeof(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gr_ctxsw_zcull_bind", + #endif + .header_length = sizeof(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpu_initialize_ctx_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_initialize_ctx_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_initialize_ctx_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_initialize_ctx_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_initialize_ctx_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_initialize_ctx_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpu_initialize_ctx", + #endif + .header_length = sizeof(rpc_ctrl_gpu_initialize_ctx_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_initialize_ctx_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04, + .offset = NV_OFFSETOF(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_vaspace_copy_server_reserved_pdes", + #endif + .header_length = sizeof(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_mc_service_interrupts_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_mc_service_interrupts_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_mc_service_interrupts_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_mc_service_interrupts_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01, + .offset = NV_OFFSETOF(rpc_ctrl_mc_service_interrupts_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_mc_service_interrupts_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_mc_service_interrupts", + #endif + .header_length = sizeof(rpc_ctrl_mc_service_interrupts_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_mc_service_interrupts_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_v2_v1F_0D +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_v2_v1F_0D[] = { + { + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, iter), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "iter" + #endif + }, + { + .vtype = vtype_NvU32_array, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, gpuIds), + .array_length = NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "gpuIds" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, gpuCount), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "gpuCount" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, p2pCaps), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "p2pCaps" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, p2pOptimalReadCEs), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "p2pOptimalReadCEs" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, p2pOptimalWriteCEs), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "p2pOptimalWriteCEs" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, p2pCapsStatus), + .array_length = NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "p2pCapsStatus" + #endif + }, + { + .vtype = vtype_NvU32_array, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, busPeerIds), + .array_length = VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "busPeerIds" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_v2_v1F_0D = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_p2p_caps_v2", + #endif + .header_length = sizeof(rpc_ctrl_get_p2p_caps_v2_v1F_0D), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_v2_v1F_0D +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02[] = { + { + .vtype = vtype_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02, + .offset = NV_OFFSETOF(rpc_ctrl_subdevice_get_p2p_caps_v21_02, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_subdevice_get_p2p_caps", + #endif + .header_length = sizeof(rpc_ctrl_subdevice_get_p2p_caps_v21_02), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_clear_all_sm_error_states", + #endif + .header_length = sizeof(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_read_all_sm_error_states_v21_06[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_all_sm_error_states_v21_06, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_all_sm_error_states_v21_06, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_all_sm_error_states_v21_06, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_read_all_sm_error_states", + #endif + .header_length = sizeof(rpc_ctrl_dbg_read_all_sm_error_states_v21_06), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_exception_mask_v1A_0C +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_exception_mask_v1A_0C[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_exception_mask_v1A_0C, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_exception_mask_v1A_0C, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_exception_mask_v1A_0C, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_exception_mask_v1A_0C = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_set_exception_mask", + #endif + .header_length = sizeof(rpc_ctrl_dbg_set_exception_mask_v1A_0C), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_exception_mask_v1A_0C +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpu_promote_ctx_v1A_20 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_promote_ctx_v1A_20[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_promote_ctx_v1A_20, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_promote_ctx_v1A_20, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_promote_ctx_v1A_20, promoteCtx), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "promoteCtx" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_promote_ctx_v1A_20 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpu_promote_ctx", + #endif + .header_length = sizeof(rpc_ctrl_gpu_promote_ctx_v1A_20), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_promote_ctx_v1A_20 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_suspend_context_v1A_10 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_suspend_context_v1A_10[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_suspend_context_v1A_10, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_suspend_context_v1A_10, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_suspend_context_v1A_10, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_suspend_context_v1A_10 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_suspend_context", + #endif + .header_length = sizeof(rpc_ctrl_dbg_suspend_context_v1A_10), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_suspend_context_v1A_10 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_resume_context_v1A_10 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_resume_context_v1A_10[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_resume_context_v1A_10, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_resume_context_v1A_10, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_resume_context_v1A_10 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_resume_context", + #endif + .header_length = sizeof(rpc_ctrl_dbg_resume_context_v1A_10), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_resume_context_v1A_10 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_exec_reg_ops_v1A_10 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_exec_reg_ops_v1A_10[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_exec_reg_ops_v1A_10, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_exec_reg_ops_v1A_10, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_exec_reg_ops_v1A_10, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_exec_reg_ops_v1A_10 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_exec_reg_ops", + #endif + .header_length = sizeof(rpc_ctrl_dbg_exec_reg_ops_v1A_10), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_exec_reg_ops_v1A_10 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_set_mode_mmu_debug", + #endif + .header_length = sizeof(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_read_single_sm_error_state_v21_06[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_single_sm_error_state_v21_06, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_single_sm_error_state_v21_06, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_single_sm_error_state_v21_06, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_read_single_sm_error_state", + #endif + .header_length = sizeof(rpc_ctrl_dbg_read_single_sm_error_state_v21_06), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_clear_single_sm_error_state", + #endif + .header_length = sizeof(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_set_mode_errbar_debug", + #endif + .header_length = sizeof(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_set_next_stop_trigger_type", + #endif + .header_length = sizeof(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dma_set_default_vaspace_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dma_set_default_vaspace_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dma_set_default_vaspace_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dma_set_default_vaspace_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_dma_set_default_vaspace_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dma_set_default_vaspace_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dma_set_default_vaspace", + #endif + .header_length = sizeof(rpc_ctrl_dma_set_default_vaspace_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dma_set_default_vaspace_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_ce_pce_mask_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_ce_pce_mask_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_ce_pce_mask_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_ce_pce_mask_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07, + .offset = NV_OFFSETOF(rpc_ctrl_get_ce_pce_mask_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_ce_pce_mask_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_ce_pce_mask", + #endif + .header_length = sizeof(rpc_ctrl_get_ce_pce_mask_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_ce_pce_mask_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07, + .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_zbc_clear_table_entry", + #endif + .header_length = sizeof(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00, + .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_nvlink_peer_id_mask", + #endif + .header_length = sizeof(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_nvlink_status_v23_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_nvlink_status_v23_04[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_status_v23_04, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_status_v23_04, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04, + .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_status_v23_04, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_nvlink_status_v23_04 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_nvlink_status", + #endif + .header_length = sizeof(rpc_ctrl_get_nvlink_status_v23_04), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_nvlink_status_v23_04 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_v1F_0D +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_v1F_0D[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v1F_0D, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v1F_0D, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v1F_0D, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_v1F_0D = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_p2p_caps", + #endif + .header_length = sizeof(rpc_ctrl_get_p2p_caps_v1F_0D), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_v1F_0D +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_matrix_v1A_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_matrix_v1A_0E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_matrix_v1A_0E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_matrix_v1A_0E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A, + .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_matrix_v1A_0E, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_matrix_v1A_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_p2p_caps_matrix", + #endif + .header_length = sizeof(rpc_ctrl_get_p2p_caps_matrix_v1A_0E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_matrix_v1A_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_reserve_pm_area_smpc_v1A_0F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_reserve_pm_area_smpc_v1A_0F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_reserve_pm_area_smpc_v1A_0F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_reserve_pm_area_smpc_v1A_0F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F, + .offset = NV_OFFSETOF(rpc_ctrl_reserve_pm_area_smpc_v1A_0F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_reserve_pm_area_smpc_v1A_0F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_reserve_pm_area_smpc", + #endif + .header_length = sizeof(rpc_ctrl_reserve_pm_area_smpc_v1A_0F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_reserve_pm_area_smpc_v1A_0F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_reserve_hwpm_legacy_v1A_0F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_reserve_hwpm_legacy_v1A_0F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_reserve_hwpm_legacy_v1A_0F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_reserve_hwpm_legacy_v1A_0F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F, + .offset = NV_OFFSETOF(rpc_ctrl_reserve_hwpm_legacy_v1A_0F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_reserve_hwpm_legacy_v1A_0F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_reserve_hwpm_legacy", + #endif + .header_length = sizeof(rpc_ctrl_reserve_hwpm_legacy_v1A_0F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_reserve_hwpm_legacy_v1A_0F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F, + .offset = NV_OFFSETOF(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_b0cc_exec_reg_ops", + #endif + .header_length = sizeof(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_bind_pm_resources_v1A_0F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bind_pm_resources_v1A_0F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bind_pm_resources_v1A_0F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bind_pm_resources_v1A_0F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bind_pm_resources_v1A_0F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_bind_pm_resources", + #endif + .header_length = sizeof(rpc_ctrl_bind_pm_resources_v1A_0F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_bind_pm_resources_v1A_0F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_alloc_pma_stream_v1A_14 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_alloc_pma_stream_v1A_14[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_alloc_pma_stream_v1A_14, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_alloc_pma_stream_v1A_14, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14, + .offset = NV_OFFSETOF(rpc_ctrl_alloc_pma_stream_v1A_14, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_alloc_pma_stream_v1A_14 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_alloc_pma_stream", + #endif + .header_length = sizeof(rpc_ctrl_alloc_pma_stream_v1A_14), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_alloc_pma_stream_v1A_14 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_pma_stream_update_get_put_v1A_14 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_pma_stream_update_get_put_v1A_14[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_pma_stream_update_get_put_v1A_14, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_pma_stream_update_get_put_v1A_14, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14, + .offset = NV_OFFSETOF(rpc_ctrl_pma_stream_update_get_put_v1A_14, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_pma_stream_update_get_put_v1A_14 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_pma_stream_update_get_put", + #endif + .header_length = sizeof(rpc_ctrl_pma_stream_update_get_put_v1A_14), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_pma_stream_update_get_put_v1A_14 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fb_get_info_v2_v25_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fb_get_info_v2_v25_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fb_get_info_v2_v25_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fb_get_info_v2_v25_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A, + .offset = NV_OFFSETOF(rpc_ctrl_fb_get_info_v2_v25_0A, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fb_get_info_v2_v25_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_fb_get_info_v2", + #endif + .header_length = sizeof(rpc_ctrl_fb_get_info_v2_v25_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_fb_get_info_v2_v25_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fifo_set_channel_properties_v1A_16 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fifo_set_channel_properties_v1A_16[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_set_channel_properties_v1A_16, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_set_channel_properties_v1A_16, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_set_channel_properties_v1A_16, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fifo_set_channel_properties_v1A_16 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_fifo_set_channel_properties", + #endif + .header_length = sizeof(rpc_ctrl_fifo_set_channel_properties_v1A_16), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_fifo_set_channel_properties_v1A_16 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpu_evict_ctx_v1A_1C +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_evict_ctx_v1A_1C[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_evict_ctx_v1A_1C, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_evict_ctx_v1A_1C, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_evict_ctx_v1A_1C, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_evict_ctx_v1A_1C = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpu_evict_ctx", + #endif + .header_length = sizeof(rpc_ctrl_gpu_evict_ctx_v1A_1C), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_evict_ctx_v1A_1C +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fb_get_fs_info_v24_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fb_get_fs_info_v24_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fb_get_fs_info_v24_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fb_get_fs_info_v24_00, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00, + .offset = NV_OFFSETOF(rpc_ctrl_fb_get_fs_info_v24_00, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fb_get_fs_info_v24_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_fb_get_fs_info", + #endif + .header_length = sizeof(rpc_ctrl_fb_get_fs_info_v24_00), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_fb_get_fs_info_v24_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D, + .offset = NV_OFFSETOF(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_grmgr_get_gr_fs_info", + #endif + .header_length = sizeof(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_stop_channel_v1A_1E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_stop_channel_v1A_1E[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_stop_channel_v1A_1E, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_stop_channel_v1A_1E, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E, + .offset = NV_OFFSETOF(rpc_ctrl_stop_channel_v1A_1E, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_stop_channel_v1A_1E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_stop_channel", + #endif + .header_length = sizeof(rpc_ctrl_stop_channel_v1A_1E), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_stop_channel_v1A_1E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gr_pc_sampling_mode_v1A_1F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_pc_sampling_mode_v1A_1F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_pc_sampling_mode_v1A_1F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_pc_sampling_mode_v1A_1F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F, + .offset = NV_OFFSETOF(rpc_ctrl_gr_pc_sampling_mode_v1A_1F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_pc_sampling_mode_v1A_1F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gr_pc_sampling_mode", + #endif + .header_length = sizeof(rpc_ctrl_gr_pc_sampling_mode_v1A_1F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_pc_sampling_mode_v1A_1F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F, + .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_perf_rated_tdp_get_status", + #endif + .header_length = sizeof(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F, + .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_perf_rated_tdp_set_control", + #endif + .header_length = sizeof(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F, + .offset = NV_OFFSETOF(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_timer_set_gr_tick_freq", + #endif + .header_length = sizeof(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_free_pma_stream_v1A_1F +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_free_pma_stream_v1A_1F[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_free_pma_stream_v1A_1F, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_free_pma_stream_v1A_1F, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F, + .offset = NV_OFFSETOF(rpc_ctrl_free_pma_stream_v1A_1F, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_free_pma_stream_v1A_1F = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_free_pma_stream", + #endif + .header_length = sizeof(rpc_ctrl_free_pma_stream_v1A_1F), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_free_pma_stream_v1A_1F +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23, + .offset = NV_OFFSETOF(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb", + #endif + .header_length = sizeof(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_set_single_sm_single_step", + #endif + .header_length = sizeof(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04, + .offset = NV_OFFSETOF(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gr_get_tpc_partition_mode", + #endif + .header_length = sizeof(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04, + .offset = NV_OFFSETOF(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gr_set_tpc_partition_mode", + #endif + .header_length = sizeof(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07, + .offset = NV_OFFSETOF(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_internal_promote_fault_method_buffers", + #endif + .header_length = sizeof(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05, + .offset = NV_OFFSETOF(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_internal_memsys_set_zbc_referenced", + #endif + .header_length = sizeof(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fabric_memory_describe_v1E_0C +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fabric_memory_describe_v1E_0C[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fabric_memory_describe_v1E_0C, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fabric_memory_describe_v1E_0C, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C, + .offset = NV_OFFSETOF(rpc_ctrl_fabric_memory_describe_v1E_0C, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fabric_memory_describe_v1E_0C = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_fabric_memory_describe", + #endif + .header_length = sizeof(rpc_ctrl_fabric_memory_describe_v1E_0C), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_fabric_memory_describe_v1E_0C +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fabric_mem_stats_v1E_0C +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fabric_mem_stats_v1E_0C[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fabric_mem_stats_v1E_0C, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fabric_mem_stats_v1E_0C, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C, + .offset = NV_OFFSETOF(rpc_ctrl_fabric_mem_stats_v1E_0C, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fabric_mem_stats_v1E_0C = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_fabric_mem_stats", + #endif + .header_length = sizeof(rpc_ctrl_fabric_mem_stats_v1E_0C), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_fabric_mem_stats_v1E_0C +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_bus_set_p2p_mapping_v21_03 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03, + .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_bus_set_p2p_mapping", + #endif + .header_length = sizeof(rpc_ctrl_bus_set_p2p_mapping_v21_03), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_bus_unset_p2p_mapping_v21_03 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03, + .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_bus_unset_p2p_mapping", + #endif + .header_length = sizeof(rpc_ctrl_bus_unset_p2p_mapping_v21_03), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpu_get_info_v2_v25_11 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_get_info_v2_v25_11[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_get_info_v2_v25_11, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_get_info_v2_v25_11, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_get_info_v2_v25_11, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_get_info_v2_v25_11 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpu_get_info_v2", + #endif + .header_length = sizeof(rpc_ctrl_gpu_get_info_v2_v25_11), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_get_info_v2_v25_11 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_internal_quiesce_pma_channel_v1C_08[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_internal_quiesce_pma_channel_v1C_08, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_internal_quiesce_pma_channel_v1C_08, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08, + .offset = NV_OFFSETOF(rpc_ctrl_internal_quiesce_pma_channel_v1C_08, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_internal_quiesce_pma_channel", + #endif + .header_length = sizeof(rpc_ctrl_internal_quiesce_pma_channel_v1C_08), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C, + .offset = NV_OFFSETOF(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_internal_sriov_promote_pma_stream", + #endif + .header_length = sizeof(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_exec_partitions_create_v24_05 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_exec_partitions_create_v24_05[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_create_v24_05, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_create_v24_05, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_create_v24_05, status), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "status" + #endif + }, + { + .vtype = vtype_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05, + .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_create_v24_05, execPartitionsCreate), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "execPartitionsCreate" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_exec_partitions_create_v24_05 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_exec_partitions_create", + #endif + .header_length = sizeof(rpc_ctrl_exec_partitions_create_v24_05), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_exec_partitions_create_v24_05 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fla_setup_instance_mem_block_v21_05 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fla_setup_instance_mem_block_v21_05[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fla_setup_instance_mem_block_v21_05, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_fla_setup_instance_mem_block_v21_05, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04, + .offset = NV_OFFSETOF(rpc_ctrl_fla_setup_instance_mem_block_v21_05, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fla_setup_instance_mem_block_v21_05 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_fla_setup_instance_mem_block", + #endif + .header_length = sizeof(rpc_ctrl_fla_setup_instance_mem_block_v21_05), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_fla_setup_instance_mem_block_v21_05 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_total_hs_credits_v21_08 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_total_hs_credits_v21_08[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_total_hs_credits_v21_08, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_total_hs_credits_v21_08, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08, + .offset = NV_OFFSETOF(rpc_ctrl_get_total_hs_credits_v21_08, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_total_hs_credits_v21_08 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_total_hs_credits", + #endif + .header_length = sizeof(rpc_ctrl_get_total_hs_credits_v21_08), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_total_hs_credits_v21_08 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_hs_credits_v21_08 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_hs_credits_v21_08[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_hs_credits_v21_08, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_hs_credits_v21_08, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08, + .offset = NV_OFFSETOF(rpc_ctrl_get_hs_credits_v21_08, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_hs_credits_v21_08 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_hs_credits", + #endif + .header_length = sizeof(rpc_ctrl_get_hs_credits_v21_08), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_hs_credits_v21_08 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_set_hs_credits_v21_08 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_hs_credits_v21_08[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_hs_credits_v21_08, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_set_hs_credits_v21_08, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08, + .offset = NV_OFFSETOF(rpc_ctrl_set_hs_credits_v21_08, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_hs_credits_v21_08 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_set_hs_credits", + #endif + .header_length = sizeof(rpc_ctrl_set_hs_credits_v21_08), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_hs_credits_v21_08 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_pm_area_pc_sampler_v21_0B +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_pm_area_pc_sampler_v21_0B[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_pm_area_pc_sampler_v21_0B, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_pm_area_pc_sampler_v21_0B, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ctrl_pm_area_pc_sampler_v21_0B, cmd), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "cmd" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_pm_area_pc_sampler_v21_0B = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_pm_area_pc_sampler", + #endif + .header_length = sizeof(rpc_ctrl_pm_area_pc_sampler_v21_0B), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_pm_area_pc_sampler_v21_0B +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_exec_partitions_delete_v1F_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_exec_partitions_delete_v1F_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_delete_v1F_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_delete_v1F_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05, + .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_delete_v1F_0A, execPartitionsDelete), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "execPartitionsDelete" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_exec_partitions_delete_v1F_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_exec_partitions_delete", + #endif + .header_length = sizeof(rpc_ctrl_exec_partitions_delete_v1F_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_exec_partitions_delete_v1F_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A, workSubmitToken), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "workSubmitToken" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpfifo_get_work_submit_token", + #endif + .header_length = sizeof(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04, + .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A, setWorkSubmitTokenIndex), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "setWorkSubmitTokenIndex" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpfifo_set_work_submit_token_notif_index", + #endif + .header_length = sizeof(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B, + .offset = NV_OFFSETOF(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D, vfErrContIntrMask), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "vfErrContIntrMask" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_master_get_virtual_function_error_cont_intr_mask", + #endif + .header_length = sizeof(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D +}; +#endif + +#ifndef SKIP_PRINT_rpc_save_hibernation_data_v1E_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_save_hibernation_data_v1E_0E[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_save_hibernation_data_v1E_0E, remainedBytes), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "remainedBytes" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_save_hibernation_data_v1E_0E, payload), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "payload" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_save_hibernation_data_v1E_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_save_hibernation_data", + #endif + .header_length = sizeof(rpc_save_hibernation_data_v1E_0E), + .fdesc = vmiopd_fdesc_t_rpc_save_hibernation_data_v1E_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_restore_hibernation_data_v1E_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_restore_hibernation_data_v1E_0E[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_restore_hibernation_data_v1E_0E, remainedBytes), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "remainedBytes" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_restore_hibernation_data_v1E_0E, payload), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "payload" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_restore_hibernation_data_v1E_0E = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_restore_hibernation_data", + #endif + .header_length = sizeof(rpc_restore_hibernation_data_v1E_0E), + .fdesc = vmiopd_fdesc_t_rpc_restore_hibernation_data_v1E_0E +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_mmu_debug_mode_v1E_06 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_mmu_debug_mode_v1E_06[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_mmu_debug_mode_v1E_06, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_get_mmu_debug_mode_v1E_06, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06, + .offset = NV_OFFSETOF(rpc_ctrl_get_mmu_debug_mode_v1E_06, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_mmu_debug_mode_v1E_06 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_get_mmu_debug_mode", + #endif + .header_length = sizeof(rpc_ctrl_get_mmu_debug_mode_v1E_06), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_mmu_debug_mode_v1E_06 +}; +#endif + +#ifndef SKIP_PRINT_rpc_disable_channels_v1E_0B +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_disable_channels_v1E_0B[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_disable_channels_v1E_0B, bDisable), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bDisable" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_disable_channels_v1E_0B = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_disable_channels", + #endif + .header_length = sizeof(rpc_disable_channels_v1E_0B), + .fdesc = vmiopd_fdesc_t_rpc_disable_channels_v1E_0B +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpu_migratable_ops_v21_07 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_migratable_ops_v21_07[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_migratable_ops_v21_07, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_migratable_ops_v21_07, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_migratable_ops_v21_07, ctrlParams), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "ctrlParams" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_migratable_ops_v21_07 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_gpu_migratable_ops", + #endif + .header_length = sizeof(rpc_ctrl_gpu_migratable_ops_v21_07), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_migratable_ops_v21_07 +}; +#endif + +#ifndef SKIP_PRINT_rpc_invalidate_tlb_v23_03 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_invalidate_tlb_v23_03[] = { + { + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_invalidate_tlb_v23_03, pdbAddress), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "pdbAddress" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_invalidate_tlb_v23_03, regVal), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "regVal" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_invalidate_tlb_v23_03 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_invalidate_tlb", + #endif + .header_length = sizeof(rpc_invalidate_tlb_v23_03), + .fdesc = vmiopd_fdesc_t_rpc_invalidate_tlb_v23_03 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ecc_notifier_write_ack_v23_05 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ecc_notifier_write_ack_v23_05[] = { + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ecc_notifier_write_ack_v23_05 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ecc_notifier_write_ack", + #endif + .fdesc = vmiopd_fdesc_t_rpc_ecc_notifier_write_ack_v23_05 +}; +#endif + +#ifndef SKIP_PRINT_rpc_get_brand_caps_v25_12 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_brand_caps_v25_12[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_get_brand_caps_v25_12, brands), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "brands" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_brand_caps_v25_12 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_get_brand_caps", + #endif + .header_length = sizeof(rpc_get_brand_caps_v25_12), + .fdesc = vmiopd_fdesc_t_rpc_get_brand_caps_v25_12 +}; +#endif + +#ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_set_system_info_v17_00, data), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "data" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_gsp_set_system_info", + #endif + .header_length = sizeof(rpc_gsp_set_system_info_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_set_registry_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_registry_v17_00[] = { + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_registry_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_set_registry", + #endif + .fdesc = vmiopd_fdesc_t_rpc_set_registry_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_gsp_rm_alloc_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hParent), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hParent" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClass), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClass" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, status), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "status" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, paramsSize), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "paramsSize" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, flags), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "flags" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, reserved), + .array_length = 4, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "reserved" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, params), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_gsp_rm_alloc", + #endif + .header_length = sizeof(rpc_gsp_rm_alloc_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_gsp_rm_control_v03_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hObject), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hObject" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, cmd), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "cmd" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, status), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "status" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, paramsSize), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "paramsSize" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, flags), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "flags" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, params), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_gsp_rm_control", + #endif + .header_length = sizeof(rpc_gsp_rm_control_v03_00), + .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_dump_protobuf_component_v18_12 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12[] = { + { + .vtype = vtype_NvU16, + .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, component), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "component" + #endif + }, + { + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, nvDumpType), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "nvDumpType" + #endif + }, + { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, countOnly), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "countOnly" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bugCheckCode), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bugCheckCode" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, internalCode), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "internalCode" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bufferSize), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bufferSize" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, blob), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "blob" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_dump_protobuf_component", + #endif + .header_length = sizeof(rpc_dump_protobuf_component_v18_12), + .fdesc = vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12 +}; +#endif + +#ifndef SKIP_PRINT_rpc_run_cpu_sequencer_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, bufferSizeDWord), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bufferSizeDWord" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, cmdIndex), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "cmdIndex" + #endif + }, + { + .vtype = vtype_NvU32_array, + .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, regSaveArea), + .array_length = 8, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "regSaveArea" + #endif + }, + { + .vtype = vtype_NvU32_array, + .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, commandBuffer), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "commandBuffer" + #endif + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_run_cpu_sequencer", + #endif + .header_length = sizeof(rpc_run_cpu_sequencer_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_post_event_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_post_event_v17_00[] = { + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_post_event_v17_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, + { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_post_event_v17_00, hEvent), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hEvent" + #endif + }, + { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteAdjust), + .offset = NV_OFFSETOF(rpc_post_event_v17_00, notifyIndex), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "pteAdjust" + .name = "notifyIndex" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, format), + .offset = NV_OFFSETOF(rpc_post_event_v17_00, data), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "format" + .name = "data" #endif }, { - .vtype = vtype_NvU64, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, length), + .vtype = vtype_NvU16, + .offset = NV_OFFSETOF(rpc_post_event_v17_00, info16), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "length" + .name = "info16" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pageCount), + .offset = NV_OFFSETOF(rpc_post_event_v17_00, status), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "pageCount" + .name = "status" #endif }, { - .vtype = vtype_struct_pte_desc, - .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteDesc), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_post_event_v17_00, eventDataSize), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "pteDesc" + .name = "eventDataSize" #endif }, { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_memory_v13_01 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_alloc_memory", - #endif - .header_length = sizeof(rpc_alloc_memory_v13_01), - .fdesc = vmiopd_fdesc_t_rpc_alloc_memory_v13_01 -}; -#endif - -#ifndef SKIP_PRINT_rpc_free_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_free_v03_00[] = { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_post_event_v17_00, bNotifyList), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bNotifyList" + #endif + }, { - .vtype = vtype_NVOS00_PARAMETERS_v03_00, - .offset = NV_OFFSETOF(rpc_free_v03_00, params), + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_post_event_v17_00, eventData), + .array_length = 0, #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "eventData" #endif }, { @@ -731,68 +6598,65 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_free_v03_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_free_v03_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_post_event_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_free", + .name = "rpc_post_event", #endif - .header_length = sizeof(rpc_free_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_free_v03_00 + .header_length = sizeof(rpc_post_event_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_post_event_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_map_memory_dma_v03_00[] = { +#ifndef SKIP_PRINT_rpc_rc_triggered_v17_02 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rc_triggered_v17_02[] = { { - .vtype = vtype_NVOS46_PARAMETERS_v03_00, - .offset = NV_OFFSETOF(rpc_map_memory_dma_v03_00, params), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, nv2080EngineType), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "nv2080EngineType" #endif }, { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_map_memory_dma_v03_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_map_memory_dma", - #endif - .header_length = sizeof(rpc_map_memory_dma_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_map_memory_dma_v03_00 -}; -#endif - -#ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00[] = { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, chid), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "chid" + #endif + }, { - .vtype = vtype_NVOS47_PARAMETERS_v03_00, - .offset = NV_OFFSETOF(rpc_unmap_memory_dma_v03_00, params), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, exceptType), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "exceptType" #endif }, { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_unmap_memory_dma", - #endif - .header_length = sizeof(rpc_unmap_memory_dma_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00 -}; -#endif - -#ifndef SKIP_PRINT_rpc_dup_object_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dup_object_v03_00[] = { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, scope), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "scope" + #endif + }, { - .vtype = vtype_NVOS55_PARAMETERS_v03_00, - .offset = NV_OFFSETOF(rpc_dup_object_v03_00, params), + .vtype = vtype_NvU16, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, partitionAttributionId), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "partitionAttributionId" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, rcJournalBufferSize), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rcJournalBufferSize" + #endif + }, + { + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, rcJournalBuffer), + .array_length = 0, + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rcJournalBuffer" #endif }, { @@ -800,45 +6664,44 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dup_object_v03_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dup_object_v03_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rc_triggered_v17_02 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_dup_object", + .name = "rpc_rc_triggered", #endif - .header_length = sizeof(rpc_dup_object_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_dup_object_v03_00 + .header_length = sizeof(rpc_rc_triggered_v17_02), + .fdesc = vmiopd_fdesc_t_rpc_rc_triggered_v17_02 }; #endif -#ifndef SKIP_PRINT_rpc_idle_channels_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_idle_channels_v03_00[] = { +#ifndef SKIP_PRINT_rpc_os_error_log_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_os_error_log_v17_00[] = { { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, flags), + .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, exceptType), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "flags" + .name = "exceptType" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, timeout), + .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, runlistId), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "timeout" + .name = "runlistId" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels), + .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, chid), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "nchannels" + .name = "chid" #endif }, { - .vtype = vtype_idle_channel_list_v03_00_array, - .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, channel_list), - .array_length = 0, - .array_length_fn = get_array_length_rpc_idle_channels_v03_00_channel_list, + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, errString), + .array_length = 0x100, #if (defined(DEBUG) || defined(DEVELOP)) - .name = "channel_list" + .name = "errString" #endif }, { @@ -846,51 +6709,66 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_idle_channels_v03_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_idle_channels_v03_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_os_error_log_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_idle_channels", + .name = "rpc_os_error_log", #endif - .header_length = sizeof(rpc_idle_channels_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_idle_channels_v03_00 + .header_length = sizeof(rpc_os_error_log_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_os_error_log_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v03_00[] = { +#ifndef SKIP_PRINT_rpc_rg_line_intr_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rg_line_intr_v17_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, head), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "head" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, rgIntr), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rgIntr" + #endif + }, { .vtype = vt_end } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v03_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rg_line_intr_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_unloading_guest_driver", + .name = "rpc_rg_line_intr", #endif - .fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v03_00 + .header_length = sizeof(rpc_rg_line_intr_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_rg_line_intr_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = { +#ifndef SKIP_PRINT_rpc_display_modeset_v01_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_display_modeset_v01_00[] = { { .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bInPMTransition), + .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, bModesetStart), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bInPMTransition" + .name = "bModesetStart" #endif }, { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bGc6Entering), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredIsoBandwidthKBPS), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bGc6Entering" + .name = "minRequiredIsoBandwidthKBPS" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, newLevel), + .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredFloorBandwidthKBPS), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "newLevel" + .name = "minRequiredFloorBandwidthKBPS" #endif }, { @@ -898,34 +6776,20 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_display_modeset_v01_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_unloading_guest_driver", + .name = "rpc_display_modeset", #endif - .header_length = sizeof(rpc_unloading_guest_driver_v1F_07), - .fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07 + .header_length = sizeof(rpc_display_modeset_v01_00), + .fdesc = vmiopd_fdesc_t_rpc_display_modeset_v01_00 }; #endif -#ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01[] = { - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hClient), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hObject), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hObject" - #endif - }, +#ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v1F_0E +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v1F_0E[] = { { - .vtype = vtype_gpu_exec_reg_ops_v12_01, - .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, params), + .vtype = vtype_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E, + .offset = NV_OFFSETOF(rpc_gpuacct_perfmon_util_samples_v1F_0E, params), #if (defined(DEBUG) || defined(DEVELOP)) .name = "params" #endif @@ -935,43 +6799,75 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v1F_0E = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_gpu_exec_reg_ops", + .name = "rpc_gpuacct_perfmon_util_samples", #endif - .header_length = sizeof(rpc_gpu_exec_reg_ops_v12_01), - .fdesc = vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01 + .header_length = sizeof(rpc_gpuacct_perfmon_util_samples_v1F_0E), + .fdesc = vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v1F_0E }; #endif -#ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v1E_05[] = { +#ifndef SKIP_PRINT_rpc_vgpu_gsp_plugin_triggered_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00[] = { { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hClient), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, gfid), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" + .name = "gfid" #endif }, { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hDevice), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, notifyIndex), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hDevice" + .name = "notifyIndex" #endif }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_vgpu_gsp_plugin_triggered", + #endif + .header_length = sizeof(rpc_vgpu_gsp_plugin_triggered_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_vgpu_config_event_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00[] = { { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, pasid), + .offset = NV_OFFSETOF(rpc_vgpu_config_event_v17_00, notifyIndex), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "pasid" + .name = "notifyIndex" #endif }, { - .vtype = vtype_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05, - .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, params), + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_vgpu_config_event", + #endif + .header_length = sizeof(rpc_vgpu_config_event_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_dce_rm_init_v01_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dce_rm_init_v01_00[] = { + { + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_dce_rm_init_v01_00, bInit), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "bInit" #endif }, { @@ -979,36 +6875,37 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v1E_05[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v1E_05 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dce_rm_init_v01_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_set_page_directory", + .name = "rpc_dce_rm_init", #endif - .header_length = sizeof(rpc_set_page_directory_v1E_05), - .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v1E_05 + .header_length = sizeof(rpc_dce_rm_init_v01_00), + .fdesc = vmiopd_fdesc_t_rpc_dce_rm_init_v01_00 }; #endif -#ifndef SKIP_PRINT_rpc_set_page_directory_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v03_00[] = { +#ifndef SKIP_PRINT_rpc_sim_read_v1E_01 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_read_v1E_01[] = { { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, hClient), + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, path), + .array_length = 0x100, #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" + .name = "path" #endif }, { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, hDevice), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, index), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hDevice" + .name = "index" #endif }, { - .vtype = vtype_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00, - .offset = NV_OFFSETOF(rpc_set_page_directory_v03_00, params), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, count), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "count" #endif }, { @@ -1016,36 +6913,44 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v03_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v03_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_read_v1E_01 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_set_page_directory", + .name = "rpc_sim_read", #endif - .header_length = sizeof(rpc_set_page_directory_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v03_00 + .header_length = sizeof(rpc_sim_read_v1E_01), + .fdesc = vmiopd_fdesc_t_rpc_sim_read_v1E_01 }; #endif -#ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05[] = { +#ifndef SKIP_PRINT_rpc_sim_write_v1E_01 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_write_v1E_01[] = { { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hClient), + .vtype = vtype_char_array, + .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, path), + .array_length = 0x100, #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" + .name = "path" #endif }, { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hDevice), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, index), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hDevice" + .name = "index" #endif }, { - .vtype = vtype_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05, - .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, params), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, count), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "count" + #endif + }, + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, data), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "data" #endif }, { @@ -1053,36 +6958,37 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_write_v1E_01 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_unset_page_directory", + .name = "rpc_sim_write", #endif - .header_length = sizeof(rpc_unset_page_directory_v1E_05), - .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05 + .header_length = sizeof(rpc_sim_write_v1E_01), + .fdesc = vmiopd_fdesc_t_rpc_sim_write_v1E_01 }; #endif -#ifndef SKIP_PRINT_rpc_unset_page_directory_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v03_00[] = { +#ifndef SKIP_PRINT_rpc_ucode_libos_print_v1E_08 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08[] = { { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, hClient), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, ucodeEngDesc), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" + .name = "ucodeEngDesc" #endif }, { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, hDevice), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBufSize), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hDevice" + .name = "libosPrintBufSize" #endif }, { - .vtype = vtype_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00, - .offset = NV_OFFSETOF(rpc_unset_page_directory_v03_00, params), + .vtype = vtype_NvU8_array, + .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBuf), + .array_length = 0, #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "libosPrintBuf" #endif }, { @@ -1090,22 +6996,22 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v03_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v03_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_unset_page_directory", + .name = "rpc_ucode_libos_print", #endif - .header_length = sizeof(rpc_unset_page_directory_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v03_00 + .header_length = sizeof(rpc_ucode_libos_print_v1E_08), + .fdesc = vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08 }; #endif -#ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00[] = { +#ifndef SKIP_PRINT_rpc_init_done_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_init_done_v17_00[] = { { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_get_gsp_static_info_v14_00, data), + .offset = NV_OFFSETOF(rpc_init_done_v17_00, not_used), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "data" + .name = "not_used" #endif }, { @@ -1113,82 +7019,64 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_init_done_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_get_gsp_static_info", + .name = "rpc_init_done", #endif - .header_length = sizeof(rpc_get_gsp_static_info_v14_00), - .fdesc = vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00 + .header_length = sizeof(rpc_init_done_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_init_done_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_update_bar_pde_v15_00[] = { +#ifndef SKIP_PRINT_rpc_semaphore_schedule_callback_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00[] = { { - .vtype = vtype_UpdateBarPde_v15_00, - .offset = NV_OFFSETOF(rpc_update_bar_pde_v15_00, info), + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, GPUVA), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "info" + .name = "GPUVA" #endif }, { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_update_bar_pde_v15_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_update_bar_pde", - #endif - .header_length = sizeof(rpc_update_bar_pde_v15_00), - .fdesc = vmiopd_fdesc_t_rpc_update_bar_pde_v15_00 -}; -#endif - -#ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00[] = { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hVASpace), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hVASpace" + #endif + }, { - .vtype = vtype_NvU64, - .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, address), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, ReleaseValue), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "address" + .name = "ReleaseValue" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, value), + .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, Flags), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "value" + .name = "Flags" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, grEngId), + .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, completionStatus), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "grEngId" + .name = "completionStatus" #endif }, { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_vgpu_pf_reg_read32", - #endif - .header_length = sizeof(rpc_vgpu_pf_reg_read32_v15_00), - .fdesc = vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00 -}; -#endif - -#ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02[] = { + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hClient), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "hClient" + #endif + }, { - .vtype = vtype_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02, - .offset = NV_OFFSETOF(rpc_ctrl_subdevice_get_p2p_caps_v21_02, ctrlParams), + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hEvent), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "ctrlParams" + .name = "hEvent" #endif }, { @@ -1196,73 +7084,64 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02[] = } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_ctrl_subdevice_get_p2p_caps", + .name = "rpc_semaphore_schedule_callback", #endif - .header_length = sizeof(rpc_ctrl_subdevice_get_p2p_caps_v21_02), - .fdesc = vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 + .header_length = sizeof(rpc_semaphore_schedule_callback_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_ctrl_bus_set_p2p_mapping_v21_03 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03[] = { +#ifndef SKIP_PRINT_rpc_timed_semaphore_release_v01_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00[] = { { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hClient), + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, semaphoreVA), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" + .name = "semaphoreVA" #endif }, { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hObject), + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, notifierVA), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hObject" + .name = "notifierVA" #endif }, { - .vtype = vtype_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03, - .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, params), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hVASpace), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "hVASpace" #endif }, { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_ctrl_bus_set_p2p_mapping", - #endif - .header_length = sizeof(rpc_ctrl_bus_set_p2p_mapping_v21_03), - .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 -}; -#endif - -#ifndef SKIP_PRINT_rpc_ctrl_bus_unset_p2p_mapping_v21_03 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03[] = { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, releaseValue), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "releaseValue" + #endif + }, { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hClient), + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, completionStatus), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" + .name = "completionStatus" #endif }, { .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hObject), + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hClient), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hObject" + .name = "hClient" #endif }, { - .vtype = vtype_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03, - .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, params), + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hDevice), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" + .name = "hDevice" #endif }, { @@ -1270,22 +7149,22 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_ctrl_bus_unset_p2p_mapping", + .name = "rpc_timed_semaphore_release", #endif - .header_length = sizeof(rpc_ctrl_bus_unset_p2p_mapping_v21_03), - .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 + .header_length = sizeof(rpc_timed_semaphore_release_v01_00), + .fdesc = vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00 }; #endif -#ifndef SKIP_PRINT_rpc_rmfs_init_v15_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_init_v15_00[] = { +#ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00[] = { { - .vtype = vtype_NvU64, - .offset = NV_OFFSETOF(rpc_rmfs_init_v15_00, statusQueuePhysAddr), + .vtype = vtype_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_perf_gpu_boost_sync_limits_callback_v17_00, params), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "statusQueuePhysAddr" + .name = "params" #endif }, { @@ -1293,73 +7172,45 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_init_v15_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_init_v15_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_rmfs_init", + .name = "rpc_perf_gpu_boost_sync_limits_callback", #endif - .header_length = sizeof(rpc_rmfs_init_v15_00), - .fdesc = vmiopd_fdesc_t_rpc_rmfs_init_v15_00 + .header_length = sizeof(rpc_perf_gpu_boost_sync_limits_callback_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_rmfs_close_queue_v15_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_close_queue_v15_00[] = { +#ifndef SKIP_PRINT_rpc_perf_bridgeless_info_update_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00[] = { { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_close_queue_v15_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_rmfs_close_queue", - #endif - .fdesc = vmiopd_fdesc_t_rpc_rmfs_close_queue_v15_00 -}; -#endif - -#ifndef SKIP_PRINT_rpc_rmfs_cleanup_v15_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_cleanup_v15_00[] = { + .vtype = vtype_NvU64, + .offset = NV_OFFSETOF(rpc_perf_bridgeless_info_update_v17_00, bBridgeless), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "bBridgeless" + #endif + }, { .vtype = vt_end } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_cleanup_v15_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_rmfs_cleanup", + .name = "rpc_perf_bridgeless_info_update", #endif - .fdesc = vmiopd_fdesc_t_rpc_rmfs_cleanup_v15_00 + .header_length = sizeof(rpc_perf_bridgeless_info_update_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_rmfs_test_v15_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_test_v15_00[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, numReps), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "numReps" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, flags), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "flags" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, testData1), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "testData1" - #endif - }, +#ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00[] = { { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rmfs_test_v15_00, testData2), + .offset = NV_OFFSETOF(rpc_nvlink_fault_up_v17_00, linkId), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "testData2" + .name = "linkId" #endif }, { @@ -1367,37 +7218,22 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rmfs_test_v15_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rmfs_test_v15_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_rmfs_test", - #endif - .header_length = sizeof(rpc_rmfs_test_v15_00), - .fdesc = vmiopd_fdesc_t_rpc_rmfs_test_v15_00 -}; -#endif - -#ifndef SKIP_PRINT_rpc_ecc_notifier_write_ack_v23_05 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ecc_notifier_write_ack_v23_05[] = { - { - .vtype = vt_end - } -}; - -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ecc_notifier_write_ack_v23_05 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_ecc_notifier_write_ack", + .name = "rpc_nvlink_fault_up", #endif - .fdesc = vmiopd_fdesc_t_rpc_ecc_notifier_write_ack_v23_05 + .header_length = sizeof(rpc_nvlink_fault_up_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00[] = { +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00[] = { { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_set_system_info_v17_00, data), + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_256_v17_00, params), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "data" + .name = "params" #endif }, { @@ -1405,93 +7241,43 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_gsp_set_system_info", + .name = "rpc_nvlink_inband_received_data_256", #endif - .header_length = sizeof(rpc_gsp_set_system_info_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00 + .header_length = sizeof(rpc_nvlink_inband_received_data_256_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_set_registry_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_registry_v17_00[] = { +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_512_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00[] = { + { + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_512_v17_00, params), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "params" + #endif + }, { .vtype = vt_end } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_registry_v17_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_set_registry", + .name = "rpc_nvlink_inband_received_data_512", #endif - .fdesc = vmiopd_fdesc_t_rpc_set_registry_v17_00 + .header_length = sizeof(rpc_nvlink_inband_received_data_512_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_gsp_rm_alloc_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00[] = { - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClient), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hParent), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hParent" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hObject), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hObject" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClass), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClass" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, status), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "status" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, paramsSize), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "paramsSize" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, flags), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "flags" - #endif - }, - { - .vtype = vtype_NvU8_array, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, reserved), - .array_length = 4, - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "reserved" - #endif - }, +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_1024_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00[] = { { - .vtype = vtype_NvU8_array, - .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, params), - .array_length = 0, + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_1024_v17_00, params), #if (defined(DEBUG) || defined(DEVELOP)) .name = "params" #endif @@ -1501,63 +7287,43 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_gsp_rm_alloc", + .name = "rpc_nvlink_inband_received_data_1024", #endif - .header_length = sizeof(rpc_gsp_rm_alloc_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00 + .header_length = sizeof(rpc_nvlink_inband_received_data_1024_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_gsp_rm_control_v03_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = { - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hClient), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hObject), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hObject" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, cmd), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "cmd" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, status), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "status" - #endif - }, +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_2048_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00[] = { { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, paramsSize), + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_2048_v17_00, params), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "paramsSize" + .name = "params" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, flags), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "flags" - #endif - }, + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_nvlink_inband_received_data_2048", + #endif + .header_length = sizeof(rpc_nvlink_inband_received_data_2048_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_4096_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00[] = { { - .vtype = vtype_NvU8_array, - .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, params), - .array_length = 0, + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_4096_v17_00, params), #if (defined(DEBUG) || defined(DEVELOP)) .name = "params" #endif @@ -1567,65 +7333,75 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_gsp_rm_control", + .name = "rpc_nvlink_inband_received_data_4096", #endif - .header_length = sizeof(rpc_gsp_rm_control_v03_00), - .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00 + .header_length = sizeof(rpc_nvlink_inband_received_data_4096_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_dump_protobuf_component_v18_12 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12[] = { - { - .vtype = vtype_NvU16, - .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, component), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "component" - #endif - }, +#ifndef SKIP_PRINT_rpc_nvlink_is_gpu_degraded_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00[] = { { - .vtype = vtype_NvU8, - .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, nvDumpType), + .vtype = vtype_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00, + .offset = NV_OFFSETOF(rpc_nvlink_is_gpu_degraded_v17_00, params), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "nvDumpType" + .name = "params" #endif }, { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, countOnly), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "countOnly" - #endif - }, + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_nvlink_is_gpu_degraded", + #endif + .header_length = sizeof(rpc_nvlink_is_gpu_degraded_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_update_gsp_trace_v01_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_update_gsp_trace_v01_00[] = { { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bugCheckCode), + .offset = NV_OFFSETOF(rpc_update_gsp_trace_v01_00, records), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bugCheckCode" + .name = "records" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, internalCode), + .offset = NV_OFFSETOF(rpc_update_gsp_trace_v01_00, data), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "internalCode" + .name = "data" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bufferSize), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bufferSize" - #endif - }, + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_update_gsp_trace_v01_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_update_gsp_trace", + #endif + .header_length = sizeof(rpc_update_gsp_trace_v01_00), + .fdesc = vmiopd_fdesc_t_rpc_update_gsp_trace_v01_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_gsp_post_nocat_record_v01_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_post_nocat_record_v01_00[] = { { - .vtype = vtype_NvU8_array, - .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, blob), - .array_length = 0, + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_gsp_post_nocat_record_v01_00, data), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "blob" + .name = "data" #endif }, { @@ -1633,45 +7409,43 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_post_nocat_record_v01_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_dump_protobuf_component", + .name = "rpc_gsp_post_nocat_record", #endif - .header_length = sizeof(rpc_dump_protobuf_component_v18_12), - .fdesc = vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12 + .header_length = sizeof(rpc_gsp_post_nocat_record_v01_00), + .fdesc = vmiopd_fdesc_t_rpc_gsp_post_nocat_record_v01_00 }; #endif -#ifndef SKIP_PRINT_rpc_run_cpu_sequencer_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00[] = { +#ifndef SKIP_PRINT_rpc_extdev_intr_service_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00[] = { { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, bufferSizeDWord), + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, lossRegStatus), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bufferSizeDWord" + .name = "lossRegStatus" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, cmdIndex), + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, gainRegStatus), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "cmdIndex" + .name = "gainRegStatus" #endif }, { - .vtype = vtype_NvU32_array, - .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, regSaveArea), - .array_length = 8, + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, miscRegStatus), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "regSaveArea" + .name = "miscRegStatus" #endif }, { - .vtype = vtype_NvU32_array, - .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, commandBuffer), - .array_length = 0, + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, rmStatus), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "commandBuffer" + .name = "rmStatus" #endif }, { @@ -1679,79 +7453,67 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_run_cpu_sequencer", + .name = "rpc_extdev_intr_service", #endif - .header_length = sizeof(rpc_run_cpu_sequencer_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00 + .header_length = sizeof(rpc_extdev_intr_service_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00 }; #endif -#ifndef SKIP_PRINT_rpc_post_event_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_post_event_v17_00[] = { - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, hClient), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" - #endif - }, +#ifndef SKIP_PRINT_rpc_pfm_req_hndlr_state_sync_callback_v21_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04[] = { { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, hEvent), + .vtype = vtype_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04, + .offset = NV_OFFSETOF(rpc_pfm_req_hndlr_state_sync_callback_v21_04, params), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hEvent" + .name = "params" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, notifyIndex), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "notifyIndex" - #endif - }, + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_pfm_req_hndlr_state_sync_callback", + #endif + .header_length = sizeof(rpc_pfm_req_hndlr_state_sync_callback_v21_04), + .fdesc = vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 +}; +#endif + +#ifndef SKIP_PRINT_rpc_vgpu_gsp_mig_ci_config_v21_03 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03[] = { { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, data), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "data" - #endif - }, - { - .vtype = vtype_NvU16, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, info16), + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartCount), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "info16" + .name = "execPartCount" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, status), + .vtype = vtype_NvU32_array, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartId), + .array_length = NVC637_CTRL_MAX_EXEC_PARTITIONS, #if (defined(DEBUG) || defined(DEVELOP)) - .name = "status" + .name = "execPartId" #endif }, { .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, eventDataSize), + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, gfid), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "eventDataSize" + .name = "gfid" #endif }, { .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, bNotifyList), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bNotifyList" - #endif - }, - { - .vtype = vtype_NvU8_array, - .offset = NV_OFFSETOF(rpc_post_event_v17_00, eventData), - .array_length = 0, + .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, bDelete), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "eventData" + .name = "bDelete" #endif }, { @@ -1759,50 +7521,59 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_post_event_v17_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_post_event_v17_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_post_event", + .name = "rpc_vgpu_gsp_mig_ci_config", #endif - .header_length = sizeof(rpc_post_event_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_post_event_v17_00 + .header_length = sizeof(rpc_vgpu_gsp_mig_ci_config_v21_03), + .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 }; #endif -#ifndef SKIP_PRINT_rpc_rc_triggered_v17_02 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rc_triggered_v17_02[] = { +#ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00[] = { { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, nv2080EngineType), + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_gsp_lockdown_notice_v17_00, bLockdownEngaging), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "nv2080EngineType" + .name = "bLockdownEngaging" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, chid), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "chid" - #endif - }, + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_lockdown_notice_v17_00 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_gsp_lockdown_notice", + #endif + .header_length = sizeof(rpc_gsp_lockdown_notice_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpu_query_ecc_status_v24_06 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_query_ecc_status_v24_06[] = { { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, exceptType), + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_query_ecc_status_v24_06, hClient), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "exceptType" + .name = "hClient" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, scope), + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_query_ecc_status_v24_06, hObject), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "scope" + .name = "hObject" #endif }, { - .vtype = vtype_NvU16, - .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, partitionAttributionId), + .vtype = vtype_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06, + .offset = NV_OFFSETOF(rpc_ctrl_gpu_query_ecc_status_v24_06, params), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "partitionAttributionId" + .name = "params" #endif }, { @@ -1810,44 +7581,59 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rc_triggered_v17_02[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rc_triggered_v17_02 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_query_ecc_status_v24_06 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_rc_triggered", + .name = "rpc_ctrl_gpu_query_ecc_status", #endif - .header_length = sizeof(rpc_rc_triggered_v17_02), - .fdesc = vmiopd_fdesc_t_rpc_rc_triggered_v17_02 + .header_length = sizeof(rpc_ctrl_gpu_query_ecc_status_v24_06), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_query_ecc_status_v24_06 }; #endif -#ifndef SKIP_PRINT_rpc_os_error_log_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_os_error_log_v17_00[] = { +#ifndef SKIP_PRINT_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04[] = { { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, exceptType), + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04, hClient), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "exceptType" + .name = "hClient" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, runlistId), + .vtype = vtype_NvHandle, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04, hObject), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "runlistId" + .name = "hObject" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, chid), + .vtype = vtype_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04, + .offset = NV_OFFSETOF(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04, ctrlParams), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "chid" + .name = "ctrlParams" #endif }, { - .vtype = vtype_char_array, - .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, errString), - .array_length = 0x100, + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_dbg_get_mode_mmu_debug", + #endif + .header_length = sizeof(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 +}; +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09[] = { + { + .vtype = vtype_NvU8, + .offset = NV_OFFSETOF(rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09, bwMode), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "errString" + .name = "bwMode" #endif }, { @@ -1855,29 +7641,36 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_os_error_log_v17_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_os_error_log_v17_00 = { +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 = { #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_os_error_log", + .name = "rpc_ctrl_cmd_internal_gpu_start_fabric_probe", #endif - .header_length = sizeof(rpc_os_error_log_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_os_error_log_v17_00 + .header_length = sizeof(rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 }; #endif -#ifndef SKIP_PRINT_rpc_rg_line_intr_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rg_line_intr_v17_00[] = { +#ifndef SKIP_PRINT_rpc_ctrl_nvlink_get_inband_received_data_v25_0C +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_nvlink_get_inband_received_data_v25_0C[] = { { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, head), + .vtype = vtype_NvU16, + .offset = NV_OFFSETOF(rpc_ctrl_nvlink_get_inband_received_data_v25_0C, message_type), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "head" + .name = "message_type" #endif }, { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, rgIntr), + .vtype = vtype_NvBool, + .offset = NV_OFFSETOF(rpc_ctrl_nvlink_get_inband_received_data_v25_0C, more), #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rgIntr" + .name = "more" + #endif + }, + { + .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C, + .offset = NV_OFFSETOF(rpc_ctrl_nvlink_get_inband_received_data_v25_0C, payload), + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "payload" #endif }, { @@ -1885,941 +7678,754 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rg_line_intr_v17_00[] = { } }; -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rg_line_intr_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_rg_line_intr", - #endif - .header_length = sizeof(rpc_rg_line_intr_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_rg_line_intr_v17_00 -}; +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_nvlink_get_inband_received_data_v25_0C = { + #if (defined(DEBUG) || defined(DEVELOP)) + .name = "rpc_ctrl_nvlink_get_inband_received_data", + #endif + .header_length = sizeof(rpc_ctrl_nvlink_get_inband_received_data_v25_0C), + .fdesc = vmiopd_fdesc_t_rpc_ctrl_nvlink_get_inband_received_data_v25_0C +}; +#endif + +#endif + +#ifdef RPC_DEBUG_PRINT_FUNCTIONS +// These are definitions for versioned functions. These will be used for RPC logging in the vmioplugin. +#define SDK_DEBUG_PRINT_FUNCTIONS +#include "g_sdk-structures.h" +#undef SDK_DEBUG_PRINT_FUNCTIONS +#ifndef SKIP_PRINT_rpc_nop_v03_00 +vmiopd_mdesc_t *rpcdebugNop_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_nop_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00 +vmiopd_mdesc_t *rpcdebugSetGuestSystemInfo_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_set_guest_system_info_ext_v15_02 +vmiopd_mdesc_t *rpcdebugSetGuestSystemInfoExt_v15_02(void) +{ + return &vmiopd_mdesc_t_rpc_set_guest_system_info_ext_v15_02; +} +#endif + +#ifndef SKIP_PRINT_rpc_alloc_root_v07_00 +vmiopd_mdesc_t *rpcdebugAllocRoot_v07_00(void) +{ + return &vmiopd_mdesc_t_rpc_alloc_root_v07_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_alloc_memory_v13_01 +vmiopd_mdesc_t *rpcdebugAllocMemory_v13_01(void) +{ + return &vmiopd_mdesc_t_rpc_alloc_memory_v13_01; +} +#endif + +#ifndef SKIP_PRINT_rpc_alloc_channel_dma_v1F_04 +vmiopd_mdesc_t *rpcdebugAllocChannelDma_v1F_04(void) +{ + return &vmiopd_mdesc_t_rpc_alloc_channel_dma_v1F_04; +} +#endif + +#ifndef SKIP_PRINT_rpc_alloc_object_v25_08 +vmiopd_mdesc_t *rpcdebugAllocObject_v25_08(void) +{ + return &vmiopd_mdesc_t_rpc_alloc_object_v25_08; +} +#endif + +#ifndef SKIP_PRINT_rpc_free_v03_00 +vmiopd_mdesc_t *rpcdebugFree_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_free_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_log_v03_00 +vmiopd_mdesc_t *rpcdebugLog_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_log_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00 +vmiopd_mdesc_t *rpcdebugMapMemoryDma_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_map_memory_dma_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00 +vmiopd_mdesc_t *rpcdebugUnmapMemoryDma_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_alloc_subdevice_v08_01 +vmiopd_mdesc_t *rpcdebugAllocSubdevice_v08_01(void) +{ + return &vmiopd_mdesc_t_rpc_alloc_subdevice_v08_01; +} +#endif + +#ifndef SKIP_PRINT_rpc_dup_object_v03_00 +vmiopd_mdesc_t *rpcdebugDupObject_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_dup_object_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_idle_channels_v03_00 +vmiopd_mdesc_t *rpcdebugIdleChannels_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_idle_channels_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_alloc_event_v03_00 +vmiopd_mdesc_t *rpcdebugAllocEvent_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_alloc_event_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_0F +vmiopd_mdesc_t *rpcdebugRmApiControl_v25_0F(void) +{ + return &vmiopd_mdesc_t_rpc_rm_api_control_v25_0F; +} +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_16 +vmiopd_mdesc_t *rpcdebugRmApiControl_v25_16(void) +{ + return &vmiopd_mdesc_t_rpc_rm_api_control_v25_16; +} +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_10 +vmiopd_mdesc_t *rpcdebugRmApiControl_v25_10(void) +{ + return &vmiopd_mdesc_t_rpc_rm_api_control_v25_10; +} +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_15 +vmiopd_mdesc_t *rpcdebugRmApiControl_v25_15(void) +{ + return &vmiopd_mdesc_t_rpc_rm_api_control_v25_15; +} +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_0D +vmiopd_mdesc_t *rpcdebugRmApiControl_v25_0D(void) +{ + return &vmiopd_mdesc_t_rpc_rm_api_control_v25_0D; +} +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_17 +vmiopd_mdesc_t *rpcdebugRmApiControl_v25_17(void) +{ + return &vmiopd_mdesc_t_rpc_rm_api_control_v25_17; +} +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_18 +vmiopd_mdesc_t *rpcdebugRmApiControl_v25_18(void) +{ + return &vmiopd_mdesc_t_rpc_rm_api_control_v25_18; +} +#endif + +#ifndef SKIP_PRINT_rpc_rm_api_control_v25_14 +vmiopd_mdesc_t *rpcdebugRmApiControl_v25_14(void) +{ + return &vmiopd_mdesc_t_rpc_rm_api_control_v25_14; +} +#endif + +#ifndef SKIP_PRINT_rpc_alloc_share_device_v03_00 +vmiopd_mdesc_t *rpcdebugAllocShareDevice_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_alloc_share_device_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_get_engine_utilization_v1F_0E +vmiopd_mdesc_t *rpcdebugGetEngineUtilization_v1F_0E(void) +{ + return &vmiopd_mdesc_t_rpc_get_engine_utilization_v1F_0E; +} +#endif + +#ifndef SKIP_PRINT_rpc_perf_get_level_info_v03_00 +vmiopd_mdesc_t *rpcdebugPerfGetLevelInfo_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_perf_get_level_info_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_set_surface_properties_v07_07 +vmiopd_mdesc_t *rpcdebugSetSurfaceProperties_v07_07(void) +{ + return &vmiopd_mdesc_t_rpc_set_surface_properties_v07_07; +} +#endif + +#ifndef SKIP_PRINT_rpc_cleanup_surface_v03_00 +vmiopd_mdesc_t *rpcdebugCleanupSurface_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_cleanup_surface_v03_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07 +vmiopd_mdesc_t *rpcdebugUnloadingGuestDriver_v1F_07(void) +{ + return &vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07; +} +#endif + +#ifndef SKIP_PRINT_rpc_switch_to_vga_v03_00 +vmiopd_mdesc_t *rpcdebugSwitchToVga_v03_00(void) +{ + return &vmiopd_mdesc_t_rpc_switch_to_vga_v03_00; +} #endif -#ifndef SKIP_PRINT_rpc_display_modeset_v01_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_display_modeset_v01_00[] = { - { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, bModesetStart), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bModesetStart" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredIsoBandwidthKBPS), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "minRequiredIsoBandwidthKBPS" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredFloorBandwidthKBPS), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "minRequiredFloorBandwidthKBPS" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01 +vmiopd_mdesc_t *rpcdebugGpuExecRegOps_v12_01(void) +{ + return &vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_display_modeset_v01_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_display_modeset", - #endif - .header_length = sizeof(rpc_display_modeset_v01_00), - .fdesc = vmiopd_fdesc_t_rpc_display_modeset_v01_00 -}; +#ifndef SKIP_PRINT_rpc_get_static_data_v25_0E +vmiopd_mdesc_t *rpcdebugGetStaticData_v25_0E(void) +{ + return &vmiopd_mdesc_t_rpc_get_static_data_v25_0E; +} #endif -#ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00[] = { - { - .vtype = vtype_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00, - .offset = NV_OFFSETOF(rpc_gpuacct_perfmon_util_samples_v17_00, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_get_consolidated_gr_static_info_v1B_04 +vmiopd_mdesc_t *rpcdebugGetConsolidatedGrStaticInfo_v1B_04(void) +{ + return &vmiopd_mdesc_t_rpc_get_consolidated_gr_static_info_v1B_04; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_gpuacct_perfmon_util_samples", - #endif - .header_length = sizeof(rpc_gpuacct_perfmon_util_samples_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00 -}; +#ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05 +vmiopd_mdesc_t *rpcdebugSetPageDirectory_v1E_05(void) +{ + return &vmiopd_mdesc_t_rpc_set_page_directory_v1E_05; +} #endif -#ifndef SKIP_PRINT_rpc_vgpu_gsp_plugin_triggered_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, gfid), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "gfid" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, notifyIndex), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "notifyIndex" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05 +vmiopd_mdesc_t *rpcdebugUnsetPageDirectory_v1E_05(void) +{ + return &vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_vgpu_gsp_plugin_triggered", - #endif - .header_length = sizeof(rpc_vgpu_gsp_plugin_triggered_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 -}; +#ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00 +vmiopd_mdesc_t *rpcdebugGetGspStaticInfo_v14_00(void) +{ + return &vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00; +} #endif -#ifndef SKIP_PRINT_rpc_vgpu_config_event_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_vgpu_config_event_v17_00, notifyIndex), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "notifyIndex" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00 +vmiopd_mdesc_t *rpcdebugUpdateBarPde_v15_00(void) +{ + return &vmiopd_mdesc_t_rpc_update_bar_pde_v15_00; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_vgpu_config_event", - #endif - .header_length = sizeof(rpc_vgpu_config_event_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00 -}; +#ifndef SKIP_PRINT_rpc_get_encoder_capacity_v07_00 +vmiopd_mdesc_t *rpcdebugGetEncoderCapacity_v07_00(void) +{ + return &vmiopd_mdesc_t_rpc_get_encoder_capacity_v07_00; +} #endif -#ifndef SKIP_PRINT_rpc_dce_rm_init_v01_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dce_rm_init_v01_00[] = { - { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_dce_rm_init_v01_00, bInit), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bInit" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00 +vmiopd_mdesc_t *rpcdebugVgpuPfRegRead32_v15_00(void) +{ + return &vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dce_rm_init_v01_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_dce_rm_init", - #endif - .header_length = sizeof(rpc_dce_rm_init_v01_00), - .fdesc = vmiopd_fdesc_t_rpc_dce_rm_init_v01_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 +vmiopd_mdesc_t *rpcdebugCtrlNvencSwSessionUpdateInfo_v1A_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_nvenc_sw_session_update_info_v1A_09; +} #endif -#ifndef SKIP_PRINT_rpc_sim_read_v1E_01 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_read_v1E_01[] = { - { - .vtype = vtype_char_array, - .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, path), - .array_length = 0x100, - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "path" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, index), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "index" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, count), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "count" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_reset_channel_v1A_09 +vmiopd_mdesc_t *rpcdebugCtrlResetChannel_v1A_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_reset_channel_v1A_09; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_read_v1E_01 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_sim_read", - #endif - .header_length = sizeof(rpc_sim_read_v1E_01), - .fdesc = vmiopd_fdesc_t_rpc_sim_read_v1E_01 -}; +#ifndef SKIP_PRINT_rpc_ctrl_reset_isolated_channel_v1A_09 +vmiopd_mdesc_t *rpcdebugCtrlResetIsolatedChannel_v1A_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_reset_isolated_channel_v1A_09; +} #endif -#ifndef SKIP_PRINT_rpc_sim_write_v1E_01 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_write_v1E_01[] = { - { - .vtype = vtype_char_array, - .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, path), - .array_length = 0x100, - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "path" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, index), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "index" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, count), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "count" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, data), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "data" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 +vmiopd_mdesc_t *rpcdebugCtrlGpuHandleVfPriFault_v1A_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_perf_boost_v1A_09 +vmiopd_mdesc_t *rpcdebugCtrlPerfBoost_v1A_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_perf_boost_v1A_09; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_zbc_clear_table_v1A_09 +vmiopd_mdesc_t *rpcdebugCtrlGetZbcClearTable_v1A_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_zbc_clear_table_v1A_09; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_write_v1E_01 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_sim_write", - #endif - .header_length = sizeof(rpc_sim_write_v1E_01), - .fdesc = vmiopd_fdesc_t_rpc_sim_write_v1E_01 -}; +#ifndef SKIP_PRINT_rpc_ctrl_set_zbc_color_clear_v1A_09 +vmiopd_mdesc_t *rpcdebugCtrlSetZbcColorClear_v1A_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_set_zbc_color_clear_v1A_09; +} #endif -#ifndef SKIP_PRINT_rpc_ucode_libos_print_v1E_08 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, ucodeEngDesc), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "ucodeEngDesc" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBufSize), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "libosPrintBufSize" - #endif - }, - { - .vtype = vtype_NvU8_array, - .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBuf), - .array_length = 0, - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "libosPrintBuf" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_set_zbc_depth_clear_v1A_09 +vmiopd_mdesc_t *rpcdebugCtrlSetZbcDepthClear_v1A_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_set_zbc_depth_clear_v1A_09; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_ucode_libos_print", - #endif - .header_length = sizeof(rpc_ucode_libos_print_v1E_08), - .fdesc = vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08 -}; +#ifndef SKIP_PRINT_rpc_ctrl_gpfifo_schedule_v1A_0A +vmiopd_mdesc_t *rpcdebugCtrlGpfifoSchedule_v1A_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gpfifo_schedule_v1A_0A; +} #endif -#ifndef SKIP_PRINT_rpc_init_done_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_init_done_v17_00[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_init_done_v17_00, not_used), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "not_used" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_set_timeslice_v1A_0A +vmiopd_mdesc_t *rpcdebugCtrlSetTimeslice_v1A_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_set_timeslice_v1A_0A; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_init_done_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_init_done", - #endif - .header_length = sizeof(rpc_init_done_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_init_done_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_fifo_disable_channels_v1A_0A +vmiopd_mdesc_t *rpcdebugCtrlFifoDisableChannels_v1A_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_fifo_disable_channels_v1A_0A; +} #endif -#ifndef SKIP_PRINT_rpc_semaphore_schedule_callback_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00[] = { - { - .vtype = vtype_NvU64, - .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, GPUVA), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "GPUVA" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hVASpace), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hVASpace" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, ReleaseValue), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "ReleaseValue" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, Flags), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "Flags" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, completionStatus), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "completionStatus" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hClient), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hEvent), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hEvent" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_preempt_v1A_0A +vmiopd_mdesc_t *rpcdebugCtrlPreempt_v1A_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_preempt_v1A_0A; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_semaphore_schedule_callback", - #endif - .header_length = sizeof(rpc_semaphore_schedule_callback_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_set_tsg_interleave_level_v1A_0A +vmiopd_mdesc_t *rpcdebugCtrlSetTsgInterleaveLevel_v1A_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_set_tsg_interleave_level_v1A_0A; +} #endif -#ifndef SKIP_PRINT_rpc_timed_semaphore_release_v01_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00[] = { - { - .vtype = vtype_NvU64, - .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, semaphoreVA), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "semaphoreVA" - #endif - }, - { - .vtype = vtype_NvU64, - .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, notifierVA), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "notifierVA" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hVASpace), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hVASpace" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, releaseValue), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "releaseValue" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, completionStatus), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "completionStatus" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hClient), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hClient" - #endif - }, - { - .vtype = vtype_NvHandle, - .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hDevice), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "hDevice" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_set_channel_interleave_level_v1A_0A +vmiopd_mdesc_t *rpcdebugCtrlSetChannelInterleaveLevel_v1A_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_set_channel_interleave_level_v1A_0A; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_timed_semaphore_release", - #endif - .header_length = sizeof(rpc_timed_semaphore_release_v01_00), - .fdesc = vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlGrCtxswPreemptionBind_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E; +} #endif -#ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00[] = { - { - .vtype = vtype_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00, - .offset = NV_OFFSETOF(rpc_perf_gpu_boost_sync_limits_callback_v17_00, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlGrSetCtxswPreemptionMode_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_perf_gpu_boost_sync_limits_callback", - #endif - .header_length = sizeof(rpc_perf_gpu_boost_sync_limits_callback_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlGrCtxswZcullBind_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E; +} #endif -#ifndef SKIP_PRINT_rpc_perf_bridgeless_info_update_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00[] = { - { - .vtype = vtype_NvU64, - .offset = NV_OFFSETOF(rpc_perf_bridgeless_info_update_v17_00, bBridgeless), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bBridgeless" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_gpu_initialize_ctx_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlGpuInitializeCtx_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gpu_initialize_ctx_v1A_0E; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 +vmiopd_mdesc_t *rpcdebugCtrlVaspaceCopyServerReservedPdes_v1E_04(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_mc_service_interrupts_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlMcServiceInterrupts_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_mc_service_interrupts_v1A_0E; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_perf_bridgeless_info_update", - #endif - .header_length = sizeof(rpc_perf_bridgeless_info_update_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_v2_v1F_0D +vmiopd_mdesc_t *rpcdebugCtrlGetP2pCapsV2_v1F_0D(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_v2_v1F_0D; +} #endif -#ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_nvlink_fault_up_v17_00, linkId), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "linkId" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02 +vmiopd_mdesc_t *rpcdebugCtrlSubdeviceGetP2pCaps_v21_02(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_nvlink_fault_up", - #endif - .header_length = sizeof(rpc_nvlink_fault_up_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C +vmiopd_mdesc_t *rpcdebugCtrlDbgClearAllSmErrorStates_v1A_0C(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C; +} #endif -#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00[] = { - { - .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00, - .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_256_v17_00, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 +vmiopd_mdesc_t *rpcdebugCtrlDbgReadAllSmErrorStates_v21_06(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_read_all_sm_error_states_v21_06; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_nvlink_inband_received_data_256", - #endif - .header_length = sizeof(rpc_nvlink_inband_received_data_256_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_exception_mask_v1A_0C +vmiopd_mdesc_t *rpcdebugCtrlDbgSetExceptionMask_v1A_0C(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_exception_mask_v1A_0C; +} #endif -#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_512_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00[] = { - { - .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00, - .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_512_v17_00, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_gpu_promote_ctx_v1A_20 +vmiopd_mdesc_t *rpcdebugCtrlGpuPromoteCtx_v1A_20(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gpu_promote_ctx_v1A_20; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_nvlink_inband_received_data_512", - #endif - .header_length = sizeof(rpc_nvlink_inband_received_data_512_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_suspend_context_v1A_10 +vmiopd_mdesc_t *rpcdebugCtrlDbgSuspendContext_v1A_10(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_suspend_context_v1A_10; +} #endif -#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_1024_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00[] = { - { - .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00, - .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_1024_v17_00, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_resume_context_v1A_10 +vmiopd_mdesc_t *rpcdebugCtrlDbgResumeContext_v1A_10(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_resume_context_v1A_10; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_nvlink_inband_received_data_1024", - #endif - .header_length = sizeof(rpc_nvlink_inband_received_data_1024_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_exec_reg_ops_v1A_10 +vmiopd_mdesc_t *rpcdebugCtrlDbgExecRegOps_v1A_10(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_exec_reg_ops_v1A_10; +} #endif -#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_2048_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00[] = { - { - .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00, - .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_2048_v17_00, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 +vmiopd_mdesc_t *rpcdebugCtrlDbgSetModeMmuDebug_v1A_10(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_nvlink_inband_received_data_2048", - #endif - .header_length = sizeof(rpc_nvlink_inband_received_data_2048_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 +vmiopd_mdesc_t *rpcdebugCtrlDbgReadSingleSmErrorState_v21_06(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_read_single_sm_error_state_v21_06; +} #endif -#ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_4096_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00[] = { - { - .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00, - .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_4096_v17_00, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 +vmiopd_mdesc_t *rpcdebugCtrlDbgClearSingleSmErrorState_v1A_10(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_nvlink_inband_received_data_4096", - #endif - .header_length = sizeof(rpc_nvlink_inband_received_data_4096_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 +vmiopd_mdesc_t *rpcdebugCtrlDbgSetModeErrbarDebug_v1A_10(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10; +} #endif -#ifndef SKIP_PRINT_rpc_nvlink_is_gpu_degraded_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00[] = { - { - .vtype = vtype_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00, - .offset = NV_OFFSETOF(rpc_nvlink_is_gpu_degraded_v17_00, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 +vmiopd_mdesc_t *rpcdebugCtrlDbgSetNextStopTriggerType_v1A_10(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_nvlink_is_gpu_degraded", - #endif - .header_length = sizeof(rpc_nvlink_is_gpu_degraded_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_dma_set_default_vaspace_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlDmaSetDefaultVaspace_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dma_set_default_vaspace_v1A_0E; +} #endif -#ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmapRing), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "sysmemPfnBitmapRing" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmapRingHi), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "sysmemPfnBitmapRingHi" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00, sysmemPfnBitmap), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "sysmemPfnBitmap" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_get_ce_pce_mask_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlGetCePceMask_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_ce_pce_mask_v1A_0E; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_set_sysmem_dirty_page_tracking_buffer", - #endif - .header_length = sizeof(rpc_set_sysmem_dirty_page_tracking_buffer_v20_00), - .fdesc = vmiopd_fdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlGetZbcClearTableEntry_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E; +} #endif -#ifndef SKIP_PRINT_rpc_extdev_intr_service_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00[] = { - { - .vtype = vtype_NvU8, - .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, lossRegStatus), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "lossRegStatus" - #endif - }, - { - .vtype = vtype_NvU8, - .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, gainRegStatus), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "gainRegStatus" - #endif - }, - { - .vtype = vtype_NvU8, - .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, miscRegStatus), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "miscRegStatus" - #endif - }, - { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, rmStatus), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rmStatus" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlGetNvlinkPeerIdMask_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_nvlink_status_v23_04 +vmiopd_mdesc_t *rpcdebugCtrlGetNvlinkStatus_v23_04(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_nvlink_status_v23_04; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_extdev_intr_service", - #endif - .header_length = sizeof(rpc_extdev_intr_service_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_v1F_0D +vmiopd_mdesc_t *rpcdebugCtrlGetP2pCaps_v1F_0D(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_v1F_0D; +} #endif -#ifndef SKIP_PRINT_rpc_pfm_req_hndlr_state_sync_callback_v21_04 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04[] = { - { - .vtype = vtype_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04, - .offset = NV_OFFSETOF(rpc_pfm_req_hndlr_state_sync_callback_v21_04, params), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "params" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_matrix_v1A_0E +vmiopd_mdesc_t *rpcdebugCtrlGetP2pCapsMatrix_v1A_0E(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_matrix_v1A_0E; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_pfm_req_hndlr_state_sync_callback", - #endif - .header_length = sizeof(rpc_pfm_req_hndlr_state_sync_callback_v21_04), - .fdesc = vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 -}; +#ifndef SKIP_PRINT_rpc_ctrl_reserve_pm_area_smpc_v1A_0F +vmiopd_mdesc_t *rpcdebugCtrlReservePmAreaSmpc_v1A_0F(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_reserve_pm_area_smpc_v1A_0F; +} #endif -#ifndef SKIP_PRINT_rpc_vgpu_gsp_mig_ci_config_v21_03 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03[] = { - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartCount), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "execPartCount" - #endif - }, - { - .vtype = vtype_NvU32_array, - .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartId), - .array_length = NVC637_CTRL_MAX_EXEC_PARTITIONS, - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "execPartId" - #endif - }, - { - .vtype = vtype_NvU32, - .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, gfid), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "gfid" - #endif - }, - { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, bDelete), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bDelete" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_reserve_hwpm_legacy_v1A_0F +vmiopd_mdesc_t *rpcdebugCtrlReserveHwpmLegacy_v1A_0F(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_reserve_hwpm_legacy_v1A_0F; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_vgpu_gsp_mig_ci_config", - #endif - .header_length = sizeof(rpc_vgpu_gsp_mig_ci_config_v21_03), - .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 -}; +#ifndef SKIP_PRINT_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F +vmiopd_mdesc_t *rpcdebugCtrlB0ccExecRegOps_v1A_0F(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F; +} #endif -#ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00 -static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00[] = { - { - .vtype = vtype_NvBool, - .offset = NV_OFFSETOF(rpc_gsp_lockdown_notice_v17_00, bLockdownEngaging), - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "bLockdownEngaging" - #endif - }, - { - .vtype = vt_end - } -}; +#ifndef SKIP_PRINT_rpc_ctrl_bind_pm_resources_v1A_0F +vmiopd_mdesc_t *rpcdebugCtrlBindPmResources_v1A_0F(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_bind_pm_resources_v1A_0F; +} +#endif -static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_lockdown_notice_v17_00 = { - #if (defined(DEBUG) || defined(DEVELOP)) - .name = "rpc_gsp_lockdown_notice", - #endif - .header_length = sizeof(rpc_gsp_lockdown_notice_v17_00), - .fdesc = vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00 -}; +#ifndef SKIP_PRINT_rpc_ctrl_alloc_pma_stream_v1A_14 +vmiopd_mdesc_t *rpcdebugCtrlAllocPmaStream_v1A_14(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_alloc_pma_stream_v1A_14; +} #endif +#ifndef SKIP_PRINT_rpc_ctrl_pma_stream_update_get_put_v1A_14 +vmiopd_mdesc_t *rpcdebugCtrlPmaStreamUpdateGetPut_v1A_14(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_pma_stream_update_get_put_v1A_14; +} #endif -#ifdef RPC_DEBUG_PRINT_FUNCTIONS -// These are definitions for versioned functions. These will be used for RPC logging in the vmioplugin. -#define SDK_DEBUG_PRINT_FUNCTIONS -#include "g_sdk-structures.h" -#undef SDK_DEBUG_PRINT_FUNCTIONS -#ifndef SKIP_PRINT_rpc_nop_v03_00 -vmiopd_mdesc_t *rpcdebugNop_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_fb_get_info_v2_v25_0A +vmiopd_mdesc_t *rpcdebugCtrlFbGetInfoV2_v25_0A(void) { - return &vmiopd_mdesc_t_rpc_nop_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_fb_get_info_v2_v25_0A; } #endif -#ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00 -vmiopd_mdesc_t *rpcdebugSetGuestSystemInfo_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_fifo_set_channel_properties_v1A_16 +vmiopd_mdesc_t *rpcdebugCtrlFifoSetChannelProperties_v1A_16(void) { - return &vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_fifo_set_channel_properties_v1A_16; } #endif -#ifndef SKIP_PRINT_rpc_alloc_memory_v13_01 -vmiopd_mdesc_t *rpcdebugAllocMemory_v13_01(void) +#ifndef SKIP_PRINT_rpc_ctrl_gpu_evict_ctx_v1A_1C +vmiopd_mdesc_t *rpcdebugCtrlGpuEvictCtx_v1A_1C(void) { - return &vmiopd_mdesc_t_rpc_alloc_memory_v13_01; + return &vmiopd_mdesc_t_rpc_ctrl_gpu_evict_ctx_v1A_1C; } #endif -#ifndef SKIP_PRINT_rpc_free_v03_00 -vmiopd_mdesc_t *rpcdebugFree_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_fb_get_fs_info_v24_00 +vmiopd_mdesc_t *rpcdebugCtrlFbGetFsInfo_v24_00(void) { - return &vmiopd_mdesc_t_rpc_free_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_fb_get_fs_info_v24_00; } #endif -#ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00 -vmiopd_mdesc_t *rpcdebugMapMemoryDma_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D +vmiopd_mdesc_t *rpcdebugCtrlGrmgrGetGrFsInfo_v1A_1D(void) { - return &vmiopd_mdesc_t_rpc_map_memory_dma_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D; } #endif -#ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00 -vmiopd_mdesc_t *rpcdebugUnmapMemoryDma_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_stop_channel_v1A_1E +vmiopd_mdesc_t *rpcdebugCtrlStopChannel_v1A_1E(void) { - return &vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_stop_channel_v1A_1E; } #endif -#ifndef SKIP_PRINT_rpc_dup_object_v03_00 -vmiopd_mdesc_t *rpcdebugDupObject_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_gr_pc_sampling_mode_v1A_1F +vmiopd_mdesc_t *rpcdebugCtrlGrPcSamplingMode_v1A_1F(void) { - return &vmiopd_mdesc_t_rpc_dup_object_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_gr_pc_sampling_mode_v1A_1F; } #endif -#ifndef SKIP_PRINT_rpc_idle_channels_v03_00 -vmiopd_mdesc_t *rpcdebugIdleChannels_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F +vmiopd_mdesc_t *rpcdebugCtrlPerfRatedTdpGetStatus_v1A_1F(void) { - return &vmiopd_mdesc_t_rpc_idle_channels_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F; } #endif -#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v03_00 -vmiopd_mdesc_t *rpcdebugUnloadingGuestDriver_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F +vmiopd_mdesc_t *rpcdebugCtrlPerfRatedTdpSetControl_v1A_1F(void) { - return &vmiopd_mdesc_t_rpc_unloading_guest_driver_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F; } #endif -#ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07 -vmiopd_mdesc_t *rpcdebugUnloadingGuestDriver_v1F_07(void) +#ifndef SKIP_PRINT_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F +vmiopd_mdesc_t *rpcdebugCtrlTimerSetGrTickFreq_v1A_1F(void) { - return &vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07; + return &vmiopd_mdesc_t_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F; } #endif -#ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01 -vmiopd_mdesc_t *rpcdebugGpuExecRegOps_v12_01(void) +#ifndef SKIP_PRINT_rpc_ctrl_free_pma_stream_v1A_1F +vmiopd_mdesc_t *rpcdebugCtrlFreePmaStream_v1A_1F(void) { - return &vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01; + return &vmiopd_mdesc_t_rpc_ctrl_free_pma_stream_v1A_1F; } #endif -#ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05 -vmiopd_mdesc_t *rpcdebugSetPageDirectory_v1E_05(void) +#ifndef SKIP_PRINT_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 +vmiopd_mdesc_t *rpcdebugCtrlFifoSetupVfZombieSubctxPdb_v1A_23(void) { - return &vmiopd_mdesc_t_rpc_set_page_directory_v1E_05; + return &vmiopd_mdesc_t_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23; } #endif -#ifndef SKIP_PRINT_rpc_set_page_directory_v03_00 -vmiopd_mdesc_t *rpcdebugSetPageDirectory_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 +vmiopd_mdesc_t *rpcdebugCtrlDbgSetSingleSmSingleStep_v1C_02(void) { - return &vmiopd_mdesc_t_rpc_set_page_directory_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02; } #endif -#ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05 -vmiopd_mdesc_t *rpcdebugUnsetPageDirectory_v1E_05(void) +#ifndef SKIP_PRINT_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 +vmiopd_mdesc_t *rpcdebugCtrlGrGetTpcPartitionMode_v1C_04(void) { - return &vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05; + return &vmiopd_mdesc_t_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04; } #endif -#ifndef SKIP_PRINT_rpc_unset_page_directory_v03_00 -vmiopd_mdesc_t *rpcdebugUnsetPageDirectory_v03_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 +vmiopd_mdesc_t *rpcdebugCtrlGrSetTpcPartitionMode_v1C_04(void) { - return &vmiopd_mdesc_t_rpc_unset_page_directory_v03_00; + return &vmiopd_mdesc_t_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04; } #endif -#ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00 -vmiopd_mdesc_t *rpcdebugGetGspStaticInfo_v14_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 +vmiopd_mdesc_t *rpcdebugCtrlInternalPromoteFaultMethodBuffers_v1E_07(void) { - return &vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00; + return &vmiopd_mdesc_t_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07; } #endif -#ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00 -vmiopd_mdesc_t *rpcdebugUpdateBarPde_v15_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 +vmiopd_mdesc_t *rpcdebugCtrlInternalMemsysSetZbcReferenced_v1F_05(void) { - return &vmiopd_mdesc_t_rpc_update_bar_pde_v15_00; + return &vmiopd_mdesc_t_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05; } #endif -#ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00 -vmiopd_mdesc_t *rpcdebugVgpuPfRegRead32_v15_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_fabric_memory_describe_v1E_0C +vmiopd_mdesc_t *rpcdebugCtrlFabricMemoryDescribe_v1E_0C(void) { - return &vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00; + return &vmiopd_mdesc_t_rpc_ctrl_fabric_memory_describe_v1E_0C; } #endif -#ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02 -vmiopd_mdesc_t *rpcdebugCtrlSubdeviceGetP2pCaps_v21_02(void) +#ifndef SKIP_PRINT_rpc_ctrl_fabric_mem_stats_v1E_0C +vmiopd_mdesc_t *rpcdebugCtrlFabricMemStats_v1E_0C(void) { - return &vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02; + return &vmiopd_mdesc_t_rpc_ctrl_fabric_mem_stats_v1E_0C; } #endif @@ -2837,31 +8443,136 @@ vmiopd_mdesc_t *rpcdebugCtrlBusUnsetP2pMapping_v21_03(void) } #endif -#ifndef SKIP_PRINT_rpc_rmfs_init_v15_00 -vmiopd_mdesc_t *rpcdebugRmfsInit_v15_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_gpu_get_info_v2_v25_11 +vmiopd_mdesc_t *rpcdebugCtrlGpuGetInfoV2_v25_11(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gpu_get_info_v2_v25_11; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 +vmiopd_mdesc_t *rpcdebugCtrlInternalQuiescePmaChannel_v1C_08(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_internal_quiesce_pma_channel_v1C_08; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C +vmiopd_mdesc_t *rpcdebugCtrlInternalSriovPromotePmaStream_v1C_0C(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_exec_partitions_create_v24_05 +vmiopd_mdesc_t *rpcdebugCtrlExecPartitionsCreate_v24_05(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_exec_partitions_create_v24_05; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_fla_setup_instance_mem_block_v21_05 +vmiopd_mdesc_t *rpcdebugCtrlFlaSetupInstanceMemBlock_v21_05(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_fla_setup_instance_mem_block_v21_05; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_total_hs_credits_v21_08 +vmiopd_mdesc_t *rpcdebugCtrlGetTotalHsCredits_v21_08(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_total_hs_credits_v21_08; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_hs_credits_v21_08 +vmiopd_mdesc_t *rpcdebugCtrlGetHsCredits_v21_08(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_get_hs_credits_v21_08; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_set_hs_credits_v21_08 +vmiopd_mdesc_t *rpcdebugCtrlSetHsCredits_v21_08(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_set_hs_credits_v21_08; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_pm_area_pc_sampler_v21_0B +vmiopd_mdesc_t *rpcdebugCtrlPmAreaPcSampler_v21_0B(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_pm_area_pc_sampler_v21_0B; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_exec_partitions_delete_v1F_0A +vmiopd_mdesc_t *rpcdebugCtrlExecPartitionsDelete_v1F_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_exec_partitions_delete_v1F_0A; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A +vmiopd_mdesc_t *rpcdebugCtrlGpfifoGetWorkSubmitToken_v1F_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A +vmiopd_mdesc_t *rpcdebugCtrlGpfifoSetWorkSubmitTokenNotifIndex_v1F_0A(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D +vmiopd_mdesc_t *rpcdebugCtrlMasterGetVirtualFunctionErrorContIntrMask_v1F_0D(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D; +} +#endif + +#ifndef SKIP_PRINT_rpc_save_hibernation_data_v1E_0E +vmiopd_mdesc_t *rpcdebugSaveHibernationData_v1E_0E(void) +{ + return &vmiopd_mdesc_t_rpc_save_hibernation_data_v1E_0E; +} +#endif + +#ifndef SKIP_PRINT_rpc_restore_hibernation_data_v1E_0E +vmiopd_mdesc_t *rpcdebugRestoreHibernationData_v1E_0E(void) +{ + return &vmiopd_mdesc_t_rpc_restore_hibernation_data_v1E_0E; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_get_mmu_debug_mode_v1E_06 +vmiopd_mdesc_t *rpcdebugCtrlGetMmuDebugMode_v1E_06(void) { - return &vmiopd_mdesc_t_rpc_rmfs_init_v15_00; + return &vmiopd_mdesc_t_rpc_ctrl_get_mmu_debug_mode_v1E_06; } #endif -#ifndef SKIP_PRINT_rpc_rmfs_close_queue_v15_00 -vmiopd_mdesc_t *rpcdebugRmfsCloseQueue_v15_00(void) +#ifndef SKIP_PRINT_rpc_disable_channels_v1E_0B +vmiopd_mdesc_t *rpcdebugDisableChannels_v1E_0B(void) { - return &vmiopd_mdesc_t_rpc_rmfs_close_queue_v15_00; + return &vmiopd_mdesc_t_rpc_disable_channels_v1E_0B; } #endif -#ifndef SKIP_PRINT_rpc_rmfs_cleanup_v15_00 -vmiopd_mdesc_t *rpcdebugRmfsCleanup_v15_00(void) +#ifndef SKIP_PRINT_rpc_ctrl_gpu_migratable_ops_v21_07 +vmiopd_mdesc_t *rpcdebugCtrlGpuMigratableOps_v21_07(void) { - return &vmiopd_mdesc_t_rpc_rmfs_cleanup_v15_00; + return &vmiopd_mdesc_t_rpc_ctrl_gpu_migratable_ops_v21_07; } #endif -#ifndef SKIP_PRINT_rpc_rmfs_test_v15_00 -vmiopd_mdesc_t *rpcdebugRmfsTest_v15_00(void) +#ifndef SKIP_PRINT_rpc_invalidate_tlb_v23_03 +vmiopd_mdesc_t *rpcdebugInvalidateTlb_v23_03(void) { - return &vmiopd_mdesc_t_rpc_rmfs_test_v15_00; + return &vmiopd_mdesc_t_rpc_invalidate_tlb_v23_03; } #endif @@ -2872,6 +8583,13 @@ vmiopd_mdesc_t *rpcdebugEccNotifierWriteAck_v23_05(void) } #endif +#ifndef SKIP_PRINT_rpc_get_brand_caps_v25_12 +vmiopd_mdesc_t *rpcdebugGetBrandCaps_v25_12(void) +{ + return &vmiopd_mdesc_t_rpc_get_brand_caps_v25_12; +} +#endif + #ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00 vmiopd_mdesc_t *rpcdebugGspSetSystemInfo_v17_00(void) { @@ -2949,10 +8667,10 @@ vmiopd_mdesc_t *rpcdebugDisplayModeset_v01_00(void) } #endif -#ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v17_00 -vmiopd_mdesc_t *rpcdebugGpuacctPerfmonUtilSamples_v17_00(void) +#ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v1F_0E +vmiopd_mdesc_t *rpcdebugGpuacctPerfmonUtilSamples_v1F_0E(void) { - return &vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v17_00; + return &vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v1F_0E; } #endif @@ -3082,10 +8800,17 @@ vmiopd_mdesc_t *rpcdebugNvlinkIsGpuDegraded_v17_00(void) } #endif -#ifndef SKIP_PRINT_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 -vmiopd_mdesc_t *rpcdebugSetSysmemDirtyPageTrackingBuffer_v20_00(void) +#ifndef SKIP_PRINT_rpc_update_gsp_trace_v01_00 +vmiopd_mdesc_t *rpcdebugUpdateGspTrace_v01_00(void) +{ + return &vmiopd_mdesc_t_rpc_update_gsp_trace_v01_00; +} +#endif + +#ifndef SKIP_PRINT_rpc_gsp_post_nocat_record_v01_00 +vmiopd_mdesc_t *rpcdebugGspPostNocatRecord_v01_00(void) { - return &vmiopd_mdesc_t_rpc_set_sysmem_dirty_page_tracking_buffer_v20_00; + return &vmiopd_mdesc_t_rpc_gsp_post_nocat_record_v01_00; } #endif @@ -3117,6 +8842,34 @@ vmiopd_mdesc_t *rpcdebugGspLockdownNotice_v17_00(void) } #endif +#ifndef SKIP_PRINT_rpc_ctrl_gpu_query_ecc_status_v24_06 +vmiopd_mdesc_t *rpcdebugCtrlGpuQueryEccStatus_v24_06(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_gpu_query_ecc_status_v24_06; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 +vmiopd_mdesc_t *rpcdebugCtrlDbgGetModeMmuDebug_v25_04(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 +vmiopd_mdesc_t *rpcdebugCtrlCmdInternalGpuStartFabricProbe_v25_09(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09; +} +#endif + +#ifndef SKIP_PRINT_rpc_ctrl_nvlink_get_inband_received_data_v25_0C +vmiopd_mdesc_t *rpcdebugCtrlNvlinkGetInbandReceivedData_v25_0C(void) +{ + return &vmiopd_mdesc_t_rpc_ctrl_nvlink_get_inband_received_data_v25_0C; +} +#endif + #endif @@ -3125,44 +8878,247 @@ vmiopd_mdesc_t *rpcdebugGspLockdownNotice_v17_00(void) typedef union rpc_generic_union { rpc_set_guest_system_info_v03_00 set_guest_system_info_v03_00; rpc_set_guest_system_info_v set_guest_system_info_v; + rpc_set_guest_system_info_ext_v15_02 set_guest_system_info_ext_v15_02; + rpc_set_guest_system_info_ext_v set_guest_system_info_ext_v; + rpc_alloc_root_v07_00 alloc_root_v07_00; + rpc_alloc_root_v alloc_root_v; rpc_alloc_memory_v13_01 alloc_memory_v13_01; rpc_alloc_memory_v alloc_memory_v; + rpc_alloc_channel_dma_v1F_04 alloc_channel_dma_v1F_04; + rpc_alloc_channel_dma_v alloc_channel_dma_v; + rpc_alloc_object_v25_08 alloc_object_v25_08; + rpc_alloc_object_v alloc_object_v; rpc_free_v03_00 free_v03_00; rpc_free_v free_v; + rpc_log_v03_00 log_v03_00; + rpc_log_v log_v; rpc_map_memory_dma_v03_00 map_memory_dma_v03_00; rpc_map_memory_dma_v map_memory_dma_v; rpc_unmap_memory_dma_v03_00 unmap_memory_dma_v03_00; rpc_unmap_memory_dma_v unmap_memory_dma_v; + rpc_alloc_subdevice_v08_01 alloc_subdevice_v08_01; + rpc_alloc_subdevice_v alloc_subdevice_v; rpc_dup_object_v03_00 dup_object_v03_00; rpc_dup_object_v dup_object_v; rpc_idle_channels_v03_00 idle_channels_v03_00; rpc_idle_channels_v idle_channels_v; + rpc_alloc_event_v03_00 alloc_event_v03_00; + rpc_alloc_event_v alloc_event_v; + rpc_rm_api_control_v25_0F rm_api_control_v25_0F; + rpc_rm_api_control_v25_16 rm_api_control_v25_16; + rpc_rm_api_control_v25_10 rm_api_control_v25_10; + rpc_rm_api_control_v25_15 rm_api_control_v25_15; + rpc_rm_api_control_v25_0D rm_api_control_v25_0D; + rpc_rm_api_control_v25_17 rm_api_control_v25_17; + rpc_rm_api_control_v25_18 rm_api_control_v25_18; + rpc_rm_api_control_v25_14 rm_api_control_v25_14; + rpc_rm_api_control_v rm_api_control_v; + rpc_alloc_share_device_v03_00 alloc_share_device_v03_00; + rpc_alloc_share_device_v alloc_share_device_v; + rpc_get_engine_utilization_v1F_0E get_engine_utilization_v1F_0E; + rpc_get_engine_utilization_v get_engine_utilization_v; + rpc_perf_get_level_info_v03_00 perf_get_level_info_v03_00; + rpc_perf_get_level_info_v perf_get_level_info_v; + rpc_set_surface_properties_v07_07 set_surface_properties_v07_07; + rpc_set_surface_properties_v set_surface_properties_v; + rpc_cleanup_surface_v03_00 cleanup_surface_v03_00; + rpc_cleanup_surface_v cleanup_surface_v; rpc_unloading_guest_driver_v1F_07 unloading_guest_driver_v1F_07; rpc_unloading_guest_driver_v unloading_guest_driver_v; rpc_gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v12_01; rpc_gpu_exec_reg_ops_v gpu_exec_reg_ops_v; + rpc_get_static_data_v25_0E get_static_data_v25_0E; + rpc_get_static_data_v get_static_data_v; + rpc_get_consolidated_gr_static_info_v1B_04 get_consolidated_gr_static_info_v1B_04; + rpc_get_consolidated_gr_static_info_v get_consolidated_gr_static_info_v; rpc_set_page_directory_v1E_05 set_page_directory_v1E_05; - rpc_set_page_directory_v03_00 set_page_directory_v03_00; rpc_set_page_directory_v set_page_directory_v; rpc_unset_page_directory_v1E_05 unset_page_directory_v1E_05; - rpc_unset_page_directory_v03_00 unset_page_directory_v03_00; rpc_unset_page_directory_v unset_page_directory_v; rpc_get_gsp_static_info_v14_00 get_gsp_static_info_v14_00; rpc_get_gsp_static_info_v get_gsp_static_info_v; rpc_update_bar_pde_v15_00 update_bar_pde_v15_00; rpc_update_bar_pde_v update_bar_pde_v; + rpc_get_encoder_capacity_v07_00 get_encoder_capacity_v07_00; + rpc_get_encoder_capacity_v get_encoder_capacity_v; rpc_vgpu_pf_reg_read32_v15_00 vgpu_pf_reg_read32_v15_00; rpc_vgpu_pf_reg_read32_v vgpu_pf_reg_read32_v; + rpc_ctrl_nvenc_sw_session_update_info_v1A_09 ctrl_nvenc_sw_session_update_info_v1A_09; + rpc_ctrl_nvenc_sw_session_update_info_v ctrl_nvenc_sw_session_update_info_v; + rpc_ctrl_reset_channel_v1A_09 ctrl_reset_channel_v1A_09; + rpc_ctrl_reset_channel_v ctrl_reset_channel_v; + rpc_ctrl_reset_isolated_channel_v1A_09 ctrl_reset_isolated_channel_v1A_09; + rpc_ctrl_reset_isolated_channel_v ctrl_reset_isolated_channel_v; + rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 ctrl_gpu_handle_vf_pri_fault_v1A_09; + rpc_ctrl_gpu_handle_vf_pri_fault_v ctrl_gpu_handle_vf_pri_fault_v; + rpc_ctrl_perf_boost_v1A_09 ctrl_perf_boost_v1A_09; + rpc_ctrl_perf_boost_v ctrl_perf_boost_v; + rpc_ctrl_get_zbc_clear_table_v1A_09 ctrl_get_zbc_clear_table_v1A_09; + rpc_ctrl_get_zbc_clear_table_v ctrl_get_zbc_clear_table_v; + rpc_ctrl_set_zbc_color_clear_v1A_09 ctrl_set_zbc_color_clear_v1A_09; + rpc_ctrl_set_zbc_color_clear_v ctrl_set_zbc_color_clear_v; + rpc_ctrl_set_zbc_depth_clear_v1A_09 ctrl_set_zbc_depth_clear_v1A_09; + rpc_ctrl_set_zbc_depth_clear_v ctrl_set_zbc_depth_clear_v; + rpc_ctrl_gpfifo_schedule_v1A_0A ctrl_gpfifo_schedule_v1A_0A; + rpc_ctrl_gpfifo_schedule_v ctrl_gpfifo_schedule_v; + rpc_ctrl_set_timeslice_v1A_0A ctrl_set_timeslice_v1A_0A; + rpc_ctrl_set_timeslice_v ctrl_set_timeslice_v; + rpc_ctrl_fifo_disable_channels_v1A_0A ctrl_fifo_disable_channels_v1A_0A; + rpc_ctrl_fifo_disable_channels_v ctrl_fifo_disable_channels_v; + rpc_ctrl_preempt_v1A_0A ctrl_preempt_v1A_0A; + rpc_ctrl_preempt_v ctrl_preempt_v; + rpc_ctrl_set_tsg_interleave_level_v1A_0A ctrl_set_tsg_interleave_level_v1A_0A; + rpc_ctrl_set_tsg_interleave_level_v ctrl_set_tsg_interleave_level_v; + rpc_ctrl_set_channel_interleave_level_v1A_0A ctrl_set_channel_interleave_level_v1A_0A; + rpc_ctrl_set_channel_interleave_level_v ctrl_set_channel_interleave_level_v; + rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E ctrl_gr_ctxsw_preemption_bind_v1A_0E; + rpc_ctrl_gr_ctxsw_preemption_bind_v ctrl_gr_ctxsw_preemption_bind_v; + rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E ctrl_gr_set_ctxsw_preemption_mode_v1A_0E; + rpc_ctrl_gr_set_ctxsw_preemption_mode_v ctrl_gr_set_ctxsw_preemption_mode_v; + rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E ctrl_gr_ctxsw_zcull_bind_v1A_0E; + rpc_ctrl_gr_ctxsw_zcull_bind_v ctrl_gr_ctxsw_zcull_bind_v; + rpc_ctrl_gpu_initialize_ctx_v1A_0E ctrl_gpu_initialize_ctx_v1A_0E; + rpc_ctrl_gpu_initialize_ctx_v ctrl_gpu_initialize_ctx_v; + rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 ctrl_vaspace_copy_server_reserved_pdes_v1E_04; + rpc_ctrl_vaspace_copy_server_reserved_pdes_v ctrl_vaspace_copy_server_reserved_pdes_v; + rpc_ctrl_mc_service_interrupts_v1A_0E ctrl_mc_service_interrupts_v1A_0E; + rpc_ctrl_mc_service_interrupts_v ctrl_mc_service_interrupts_v; + rpc_ctrl_get_p2p_caps_v2_v1F_0D ctrl_get_p2p_caps_v2_v1F_0D; + rpc_ctrl_get_p2p_caps_v2_v ctrl_get_p2p_caps_v2_v; rpc_ctrl_subdevice_get_p2p_caps_v21_02 ctrl_subdevice_get_p2p_caps_v21_02; rpc_ctrl_subdevice_get_p2p_caps_v ctrl_subdevice_get_p2p_caps_v; + rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C ctrl_dbg_clear_all_sm_error_states_v1A_0C; + rpc_ctrl_dbg_clear_all_sm_error_states_v ctrl_dbg_clear_all_sm_error_states_v; + rpc_ctrl_dbg_read_all_sm_error_states_v21_06 ctrl_dbg_read_all_sm_error_states_v21_06; + rpc_ctrl_dbg_read_all_sm_error_states_v ctrl_dbg_read_all_sm_error_states_v; + rpc_ctrl_dbg_set_exception_mask_v1A_0C ctrl_dbg_set_exception_mask_v1A_0C; + rpc_ctrl_dbg_set_exception_mask_v ctrl_dbg_set_exception_mask_v; + rpc_ctrl_gpu_promote_ctx_v1A_20 ctrl_gpu_promote_ctx_v1A_20; + rpc_ctrl_gpu_promote_ctx_v ctrl_gpu_promote_ctx_v; + rpc_ctrl_dbg_suspend_context_v1A_10 ctrl_dbg_suspend_context_v1A_10; + rpc_ctrl_dbg_suspend_context_v ctrl_dbg_suspend_context_v; + rpc_ctrl_dbg_resume_context_v1A_10 ctrl_dbg_resume_context_v1A_10; + rpc_ctrl_dbg_resume_context_v ctrl_dbg_resume_context_v; + rpc_ctrl_dbg_exec_reg_ops_v1A_10 ctrl_dbg_exec_reg_ops_v1A_10; + rpc_ctrl_dbg_exec_reg_ops_v ctrl_dbg_exec_reg_ops_v; + rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 ctrl_dbg_set_mode_mmu_debug_v1A_10; + rpc_ctrl_dbg_set_mode_mmu_debug_v ctrl_dbg_set_mode_mmu_debug_v; + rpc_ctrl_dbg_read_single_sm_error_state_v21_06 ctrl_dbg_read_single_sm_error_state_v21_06; + rpc_ctrl_dbg_read_single_sm_error_state_v ctrl_dbg_read_single_sm_error_state_v; + rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 ctrl_dbg_clear_single_sm_error_state_v1A_10; + rpc_ctrl_dbg_clear_single_sm_error_state_v ctrl_dbg_clear_single_sm_error_state_v; + rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 ctrl_dbg_set_mode_errbar_debug_v1A_10; + rpc_ctrl_dbg_set_mode_errbar_debug_v ctrl_dbg_set_mode_errbar_debug_v; + rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 ctrl_dbg_set_next_stop_trigger_type_v1A_10; + rpc_ctrl_dbg_set_next_stop_trigger_type_v ctrl_dbg_set_next_stop_trigger_type_v; + rpc_ctrl_dma_set_default_vaspace_v1A_0E ctrl_dma_set_default_vaspace_v1A_0E; + rpc_ctrl_dma_set_default_vaspace_v ctrl_dma_set_default_vaspace_v; + rpc_ctrl_get_ce_pce_mask_v1A_0E ctrl_get_ce_pce_mask_v1A_0E; + rpc_ctrl_get_ce_pce_mask_v ctrl_get_ce_pce_mask_v; + rpc_ctrl_get_zbc_clear_table_entry_v1A_0E ctrl_get_zbc_clear_table_entry_v1A_0E; + rpc_ctrl_get_zbc_clear_table_entry_v ctrl_get_zbc_clear_table_entry_v; + rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E ctrl_get_nvlink_peer_id_mask_v1A_0E; + rpc_ctrl_get_nvlink_peer_id_mask_v ctrl_get_nvlink_peer_id_mask_v; + rpc_ctrl_get_nvlink_status_v23_04 ctrl_get_nvlink_status_v23_04; + rpc_ctrl_get_nvlink_status_v ctrl_get_nvlink_status_v; + rpc_ctrl_get_p2p_caps_v1F_0D ctrl_get_p2p_caps_v1F_0D; + rpc_ctrl_get_p2p_caps_v ctrl_get_p2p_caps_v; + rpc_ctrl_get_p2p_caps_matrix_v1A_0E ctrl_get_p2p_caps_matrix_v1A_0E; + rpc_ctrl_get_p2p_caps_matrix_v ctrl_get_p2p_caps_matrix_v; + rpc_ctrl_reserve_pm_area_smpc_v1A_0F ctrl_reserve_pm_area_smpc_v1A_0F; + rpc_ctrl_reserve_pm_area_smpc_v ctrl_reserve_pm_area_smpc_v; + rpc_ctrl_reserve_hwpm_legacy_v1A_0F ctrl_reserve_hwpm_legacy_v1A_0F; + rpc_ctrl_reserve_hwpm_legacy_v ctrl_reserve_hwpm_legacy_v; + rpc_ctrl_b0cc_exec_reg_ops_v1A_0F ctrl_b0cc_exec_reg_ops_v1A_0F; + rpc_ctrl_b0cc_exec_reg_ops_v ctrl_b0cc_exec_reg_ops_v; + rpc_ctrl_bind_pm_resources_v1A_0F ctrl_bind_pm_resources_v1A_0F; + rpc_ctrl_bind_pm_resources_v ctrl_bind_pm_resources_v; + rpc_ctrl_alloc_pma_stream_v1A_14 ctrl_alloc_pma_stream_v1A_14; + rpc_ctrl_alloc_pma_stream_v ctrl_alloc_pma_stream_v; + rpc_ctrl_pma_stream_update_get_put_v1A_14 ctrl_pma_stream_update_get_put_v1A_14; + rpc_ctrl_pma_stream_update_get_put_v ctrl_pma_stream_update_get_put_v; + rpc_ctrl_fb_get_info_v2_v25_0A ctrl_fb_get_info_v2_v25_0A; + rpc_ctrl_fb_get_info_v2_v ctrl_fb_get_info_v2_v; + rpc_ctrl_fifo_set_channel_properties_v1A_16 ctrl_fifo_set_channel_properties_v1A_16; + rpc_ctrl_fifo_set_channel_properties_v ctrl_fifo_set_channel_properties_v; + rpc_ctrl_gpu_evict_ctx_v1A_1C ctrl_gpu_evict_ctx_v1A_1C; + rpc_ctrl_gpu_evict_ctx_v ctrl_gpu_evict_ctx_v; + rpc_ctrl_fb_get_fs_info_v24_00 ctrl_fb_get_fs_info_v24_00; + rpc_ctrl_fb_get_fs_info_v ctrl_fb_get_fs_info_v; + rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D ctrl_grmgr_get_gr_fs_info_v1A_1D; + rpc_ctrl_grmgr_get_gr_fs_info_v ctrl_grmgr_get_gr_fs_info_v; + rpc_ctrl_stop_channel_v1A_1E ctrl_stop_channel_v1A_1E; + rpc_ctrl_stop_channel_v ctrl_stop_channel_v; + rpc_ctrl_gr_pc_sampling_mode_v1A_1F ctrl_gr_pc_sampling_mode_v1A_1F; + rpc_ctrl_gr_pc_sampling_mode_v ctrl_gr_pc_sampling_mode_v; + rpc_ctrl_perf_rated_tdp_get_status_v1A_1F ctrl_perf_rated_tdp_get_status_v1A_1F; + rpc_ctrl_perf_rated_tdp_get_status_v ctrl_perf_rated_tdp_get_status_v; + rpc_ctrl_perf_rated_tdp_set_control_v1A_1F ctrl_perf_rated_tdp_set_control_v1A_1F; + rpc_ctrl_perf_rated_tdp_set_control_v ctrl_perf_rated_tdp_set_control_v; + rpc_ctrl_timer_set_gr_tick_freq_v1A_1F ctrl_timer_set_gr_tick_freq_v1A_1F; + rpc_ctrl_timer_set_gr_tick_freq_v ctrl_timer_set_gr_tick_freq_v; + rpc_ctrl_free_pma_stream_v1A_1F ctrl_free_pma_stream_v1A_1F; + rpc_ctrl_free_pma_stream_v ctrl_free_pma_stream_v; + rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23; + rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v ctrl_fifo_setup_vf_zombie_subctx_pdb_v; + rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 ctrl_dbg_set_single_sm_single_step_v1C_02; + rpc_ctrl_dbg_set_single_sm_single_step_v ctrl_dbg_set_single_sm_single_step_v; + rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 ctrl_gr_get_tpc_partition_mode_v1C_04; + rpc_ctrl_gr_get_tpc_partition_mode_v ctrl_gr_get_tpc_partition_mode_v; + rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 ctrl_gr_set_tpc_partition_mode_v1C_04; + rpc_ctrl_gr_set_tpc_partition_mode_v ctrl_gr_set_tpc_partition_mode_v; + rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 ctrl_internal_promote_fault_method_buffers_v1E_07; + rpc_ctrl_internal_promote_fault_method_buffers_v ctrl_internal_promote_fault_method_buffers_v; + rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 ctrl_internal_memsys_set_zbc_referenced_v1F_05; + rpc_ctrl_internal_memsys_set_zbc_referenced_v ctrl_internal_memsys_set_zbc_referenced_v; + rpc_ctrl_fabric_memory_describe_v1E_0C ctrl_fabric_memory_describe_v1E_0C; + rpc_ctrl_fabric_memory_describe_v ctrl_fabric_memory_describe_v; + rpc_ctrl_fabric_mem_stats_v1E_0C ctrl_fabric_mem_stats_v1E_0C; + rpc_ctrl_fabric_mem_stats_v ctrl_fabric_mem_stats_v; rpc_ctrl_bus_set_p2p_mapping_v21_03 ctrl_bus_set_p2p_mapping_v21_03; rpc_ctrl_bus_set_p2p_mapping_v ctrl_bus_set_p2p_mapping_v; rpc_ctrl_bus_unset_p2p_mapping_v21_03 ctrl_bus_unset_p2p_mapping_v21_03; rpc_ctrl_bus_unset_p2p_mapping_v ctrl_bus_unset_p2p_mapping_v; - rpc_rmfs_init_v15_00 rmfs_init_v15_00; - rpc_rmfs_init_v rmfs_init_v; - rpc_rmfs_test_v15_00 rmfs_test_v15_00; - rpc_rmfs_test_v rmfs_test_v; + rpc_ctrl_gpu_get_info_v2_v25_11 ctrl_gpu_get_info_v2_v25_11; + rpc_ctrl_gpu_get_info_v2_v ctrl_gpu_get_info_v2_v; + rpc_ctrl_internal_quiesce_pma_channel_v1C_08 ctrl_internal_quiesce_pma_channel_v1C_08; + rpc_ctrl_internal_quiesce_pma_channel_v ctrl_internal_quiesce_pma_channel_v; + rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C ctrl_internal_sriov_promote_pma_stream_v1C_0C; + rpc_ctrl_internal_sriov_promote_pma_stream_v ctrl_internal_sriov_promote_pma_stream_v; + rpc_ctrl_exec_partitions_create_v24_05 ctrl_exec_partitions_create_v24_05; + rpc_ctrl_exec_partitions_create_v ctrl_exec_partitions_create_v; + rpc_ctrl_fla_setup_instance_mem_block_v21_05 ctrl_fla_setup_instance_mem_block_v21_05; + rpc_ctrl_fla_setup_instance_mem_block_v ctrl_fla_setup_instance_mem_block_v; + rpc_ctrl_get_total_hs_credits_v21_08 ctrl_get_total_hs_credits_v21_08; + rpc_ctrl_get_total_hs_credits_v ctrl_get_total_hs_credits_v; + rpc_ctrl_get_hs_credits_v21_08 ctrl_get_hs_credits_v21_08; + rpc_ctrl_get_hs_credits_v ctrl_get_hs_credits_v; + rpc_ctrl_set_hs_credits_v21_08 ctrl_set_hs_credits_v21_08; + rpc_ctrl_set_hs_credits_v ctrl_set_hs_credits_v; + rpc_ctrl_pm_area_pc_sampler_v21_0B ctrl_pm_area_pc_sampler_v21_0B; + rpc_ctrl_pm_area_pc_sampler_v ctrl_pm_area_pc_sampler_v; + rpc_ctrl_exec_partitions_delete_v1F_0A ctrl_exec_partitions_delete_v1F_0A; + rpc_ctrl_exec_partitions_delete_v ctrl_exec_partitions_delete_v; + rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A ctrl_gpfifo_get_work_submit_token_v1F_0A; + rpc_ctrl_gpfifo_get_work_submit_token_v ctrl_gpfifo_get_work_submit_token_v; + rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A; + rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v ctrl_gpfifo_set_work_submit_token_notif_index_v; + rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D; + rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v ctrl_master_get_virtual_function_error_cont_intr_mask_v; + rpc_save_hibernation_data_v1E_0E save_hibernation_data_v1E_0E; + rpc_save_hibernation_data_v save_hibernation_data_v; + rpc_restore_hibernation_data_v1E_0E restore_hibernation_data_v1E_0E; + rpc_restore_hibernation_data_v restore_hibernation_data_v; + rpc_ctrl_get_mmu_debug_mode_v1E_06 ctrl_get_mmu_debug_mode_v1E_06; + rpc_ctrl_get_mmu_debug_mode_v ctrl_get_mmu_debug_mode_v; + rpc_disable_channels_v1E_0B disable_channels_v1E_0B; + rpc_disable_channels_v disable_channels_v; + rpc_ctrl_gpu_migratable_ops_v21_07 ctrl_gpu_migratable_ops_v21_07; + rpc_ctrl_gpu_migratable_ops_v ctrl_gpu_migratable_ops_v; + rpc_invalidate_tlb_v23_03 invalidate_tlb_v23_03; + rpc_invalidate_tlb_v invalidate_tlb_v; + rpc_get_brand_caps_v25_12 get_brand_caps_v25_12; + rpc_get_brand_caps_v get_brand_caps_v; rpc_gsp_set_system_info_v17_00 gsp_set_system_info_v17_00; rpc_gsp_set_system_info_v gsp_set_system_info_v; rpc_gsp_rm_alloc_v03_00 gsp_rm_alloc_v03_00; @@ -3183,7 +9139,7 @@ typedef union rpc_generic_union { rpc_rg_line_intr_v rg_line_intr_v; rpc_display_modeset_v01_00 display_modeset_v01_00; rpc_display_modeset_v display_modeset_v; - rpc_gpuacct_perfmon_util_samples_v17_00 gpuacct_perfmon_util_samples_v17_00; + rpc_gpuacct_perfmon_util_samples_v1F_0E gpuacct_perfmon_util_samples_v1F_0E; rpc_gpuacct_perfmon_util_samples_v gpuacct_perfmon_util_samples_v; rpc_vgpu_gsp_plugin_triggered_v17_00 vgpu_gsp_plugin_triggered_v17_00; rpc_vgpu_gsp_plugin_triggered_v vgpu_gsp_plugin_triggered_v; @@ -3221,8 +9177,10 @@ typedef union rpc_generic_union { rpc_nvlink_inband_received_data_4096_v nvlink_inband_received_data_4096_v; rpc_nvlink_is_gpu_degraded_v17_00 nvlink_is_gpu_degraded_v17_00; rpc_nvlink_is_gpu_degraded_v nvlink_is_gpu_degraded_v; - rpc_set_sysmem_dirty_page_tracking_buffer_v20_00 set_sysmem_dirty_page_tracking_buffer_v20_00; - rpc_set_sysmem_dirty_page_tracking_buffer_v set_sysmem_dirty_page_tracking_buffer_v; + rpc_update_gsp_trace_v01_00 update_gsp_trace_v01_00; + rpc_update_gsp_trace_v update_gsp_trace_v; + rpc_gsp_post_nocat_record_v01_00 gsp_post_nocat_record_v01_00; + rpc_gsp_post_nocat_record_v gsp_post_nocat_record_v; rpc_extdev_intr_service_v17_00 extdev_intr_service_v17_00; rpc_extdev_intr_service_v extdev_intr_service_v; rpc_pfm_req_hndlr_state_sync_callback_v21_04 pfm_req_hndlr_state_sync_callback_v21_04; @@ -3231,6 +9189,14 @@ typedef union rpc_generic_union { rpc_vgpu_gsp_mig_ci_config_v vgpu_gsp_mig_ci_config_v; rpc_gsp_lockdown_notice_v17_00 gsp_lockdown_notice_v17_00; rpc_gsp_lockdown_notice_v gsp_lockdown_notice_v; + rpc_ctrl_gpu_query_ecc_status_v24_06 ctrl_gpu_query_ecc_status_v24_06; + rpc_ctrl_gpu_query_ecc_status_v ctrl_gpu_query_ecc_status_v; + rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 ctrl_dbg_get_mode_mmu_debug_v25_04; + rpc_ctrl_dbg_get_mode_mmu_debug_v ctrl_dbg_get_mode_mmu_debug_v; + rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 ctrl_cmd_internal_gpu_start_fabric_probe_v25_09; + rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v ctrl_cmd_internal_gpu_start_fabric_probe_v; + rpc_ctrl_nvlink_get_inband_received_data_v25_0C ctrl_nvlink_get_inband_received_data_v25_0C; + rpc_ctrl_nvlink_get_inband_received_data_v ctrl_nvlink_get_inband_received_data_v; } rpc_generic_union; #endif @@ -3239,6 +9205,24 @@ typedef union rpc_generic_union { #define SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD #include "g_sdk-structures.h" #undef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD +static NV_STATUS get_union_member_index_rpc_alloc_object_v25_08_params(void *msg, NvS32 bytes_remaining, uint32_t* index) +{ + rpc_alloc_object_v25_08 *param = msg; + + if ((NvS32)(NV_OFFSETOF(rpc_alloc_object_v25_08, hClass) + sizeof(param->hClass)) > bytes_remaining) + return NV_ERR_BUFFER_TOO_SMALL; + *index = _get_union_member_index_alloc_object_params_v25_08(param->hClass); + return NV_OK; +} +static NV_STATUS get_union_member_index_rpc_get_engine_utilization_v1F_0E_params(void *msg, NvS32 bytes_remaining, uint32_t* index) +{ + rpc_get_engine_utilization_v1F_0E *param = msg; + + if ((NvS32)(NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, cmd) + sizeof(param->cmd)) > bytes_remaining) + return NV_ERR_BUFFER_TOO_SMALL; + *index = _get_union_member_index_vgpuGetEngineUtilization_data_v1F_0E(param->cmd); + return NV_OK; +} #endif @@ -3262,6 +9246,6 @@ static NV_STATUS get_array_length_rpc_idle_channels_v03_00_channel_list(void *ms #endif #ifdef AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION -#define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR 0x18 -#define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR 0x00 +#define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR 0x25 +#define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR 0x0E #endif diff --git a/src/nvidia/generated/g_rpc_hal.h b/src/nvidia/generated/g_rpc_hal.h index 37f00fe50d..79acc10df3 100644 --- a/src/nvidia/generated/g_rpc_hal.h +++ b/src/nvidia/generated/g_rpc_hal.h @@ -64,33 +64,153 @@ typedef struct RPC_OBJ_IFACES { // Typedefs for RPC HAL interfaces. // +typedef NV_STATUS RpcCtrlFifoSetupVfZombieSubctxPdb(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcVgpuPfRegRead32(POBJGPU, POBJRPC, NvU64, NvU32*, NvU32); +typedef NV_STATUS RpcCtrlBusUnsetP2pMapping(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcDumpProtobufComponent(POBJGPU, POBJRPC, PRB_ENCODER *pPrbEnc, NVD_STATE *pNvDumpState, NVDUMP_COMPONENT component); typedef NV_STATUS RpcEccNotifierWriteAck(POBJGPU, POBJRPC); typedef NV_STATUS RpcAllocMemory(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvU32, NvU32, MEMORY_DESCRIPTOR*); +typedef NV_STATUS RpcCtrlDbgReadSingleSmErrorState(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcDisableChannels(POBJGPU, POBJRPC, NvU32); typedef NV_STATUS RpcGpuExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS*, NV2080_CTRL_GPU_REG_OP*); -typedef NV_STATUS RpcRmfsInit(POBJGPU, POBJRPC, PMEMORY_DESCRIPTOR); +typedef NV_STATUS RpcCtrlGpuPromoteCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgSetNextStopTriggerType(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcAllocShareDevice(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, + NvHandle, NvHandle, NvU32, NvU32, NvU64, NvU32); +typedef NV_STATUS RpcCtrlPreempt(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGpuInitializeCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlReservePmAreaSmpc(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGpuMigratableOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgSetModeErrbarDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlPmaStreamUpdateGetPut(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlFabricMemoryDescribe(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcAllocChannelDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, + NvU32, NV_CHANNEL_ALLOC_PARAMS*, NvU32*); +typedef NV_STATUS RpcCtrlSetZbcDepthClear(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlResetIsolatedChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDmaSetDefaultVaspace(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcAllocSubdevice(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvU32, NvU32); +typedef NV_STATUS RpcFree(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle); +typedef NV_STATUS RpcDmaControl(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32); +typedef NV_STATUS RpcCtrlDbgClearSingleSmErrorState(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcUnsetPageDirectory(POBJGPU, POBJRPC, NvHandle, NvHandle, NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS*); typedef NV_STATUS RpcGetGspStaticInfo(POBJGPU, POBJRPC); +typedef NV_STATUS RpcSaveHibernationData(POBJGPU, POBJRPC); +typedef NV_STATUS RpcDupObject(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, + NvHandle, NvHandle, NvU32); typedef NV_STATUS RpcGspSetSystemInfo(POBJGPU, POBJRPC); -typedef NV_STATUS RpcRmfsCleanup(POBJGPU, POBJRPC); +typedef NV_STATUS RpcCtrlPmAreaPcSampler(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*); +typedef NV_STATUS RpcCtrlDbgSetExceptionMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlVaspaceCopyServerReservedPdes(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGrCtxswPreemptionBind(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlAllocPmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlReserveHwpmLegacy(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlInternalQuiescePmaChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlPerfRatedTdpGetStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlBusSetP2pMapping(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGpuGetInfoV2(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGetHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGrSetCtxswPreemptionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlB0ccExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGrmgrGetGrFsInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGetZbcClearTable(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCleanupSurface(POBJGPU, POBJRPC, + NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS*); +typedef NV_STATUS RpcCtrlSetTimeslice(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGpuQueryEccStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgGetModeMmuDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgClearAllSmErrorStates(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcVgpuGspRingDoorbell(POBJGPU, NvU32); +typedef NV_STATUS RpcCtrlGrSetTpcPartitionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGetTotalHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlInternalPromoteFaultMethodBuffers(OBJGPU *, OBJRPC *, NvHandle, NvHandle, void *); +typedef NV_STATUS RpcCtrlFbGetInfoV2(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcVgpuGspWriteScratchRegister(POBJGPU, NvU64); typedef NV_STATUS RpcSetPageDirectory(POBJGPU, POBJRPC, NvHandle, NvHandle, NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS*); +typedef NV_STATUS RpcCtrlGetP2pCapsV2(POBJGPU, POBJRPC, void*); +typedef NV_STATUS RpcCtrlNvlinkGetInbandReceivedData(POBJGPU, POBJRPC, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS*, NvU16, NvBool*); +typedef NV_STATUS RpcCtrlGetCePceMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGetNvlinkPeerIdMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGpuEvictCtx(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGetMmuDebugMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcInvalidateTlb(POBJGPU, POBJRPC, NvU64, NvU32); +typedef NV_STATUS RpcCtrlDbgSetSingleSmSingleStep(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcUnloadingGuestDriver(POBJGPU, POBJRPC, NvBool, NvBool, NvU32); +typedef NV_STATUS RpcGetEngineUtilizationWrapper(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32); +typedef NV_STATUS RpcGetConsolidatedGrStaticInfo(POBJGPU, POBJRPC); +typedef NV_STATUS RpcSwitchToVga(POBJGPU, POBJRPC); +typedef NV_STATUS RpcCtrlResetChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGpfifoSchedule(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*); typedef NV_STATUS RpcSetRegistry(POBJGPU, POBJRPC); -typedef NV_STATUS RpcRmfsCloseQueue(POBJGPU, POBJRPC); -typedef NV_STATUS RpcGetStaticInfo(POBJGPU, POBJRPC); +typedef NV_STATUS RpcCtrlGetNvlinkStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcGetStaticData(POBJGPU, POBJRPC); +typedef NV_STATUS RpcCtrlGrGetTpcPartitionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlStopChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcSetSurfaceProperties(POBJGPU, POBJRPC, NvHandle, + NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES*, + NvBool); +typedef NV_STATUS RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlTimerSetGrTickFreq(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcAllocEvent(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, + NvHandle, NvHandle, NvU32, NvU32); +typedef NV_STATUS RpcCtrlGrPcSamplingMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlMcServiceInterrupts(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgReadAllSmErrorStates(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlSetZbcColorClear(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcGetEncoderCapacity(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32*); +typedef NV_STATUS RpcCtrlGetP2pCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcPerfGetLevelInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, + NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS*, + NV2080_CTRL_PERF_GET_CLK_INFO*); +typedef NV_STATUS RpcAllocObject(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvU32, void*); +typedef NV_STATUS RpcCtrlGpuHandleVfPriFault(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcRmApiControl(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32); +typedef NV_STATUS RpcCtrlFabricMemStats(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGrCtxswZcullBind(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlInternalMemsysSetZbcReferenced(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlPerfRatedTdpSetControl(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlExecPartitionsCreate(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGpfifoGetWorkSubmitToken(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcIdleChannels(OBJGPU *, OBJRPC *, NvHandle *phclients, NvHandle *phdevices, NvHandle *phchannels, NvU32 nentries, NvU32 flags, NvU32 timeout); +typedef NV_STATUS RpcCtrlCmdInternalGpuStartFabricProbe(POBJGPU, POBJRPC, NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS*); +typedef NV_STATUS RpcGetBrandCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*, NvU32); +typedef NV_STATUS RpcRestoreHibernationData(POBJGPU, POBJRPC); +typedef NV_STATUS RpcCtrlFlaSetupInstanceMemBlock(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlInternalSriovPromotePmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlFbGetFsInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlSetChannelInterleaveLevel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgResumeContext(POBJGPU, POBJRPC, NvHandle, NvHandle); +typedef NV_STATUS RpcAllocRoot(POBJGPU, POBJRPC, NvHandle); +typedef NV_STATUS RpcCtrlFifoDisableChannels(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlSetHsCredits(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcGetEngineUtilization(POBJGPU, POBJRPC, NvHandle, + NvHandle, NvU32, void*, NvU32); +typedef NV_STATUS RpcCtrlGetZbcClearTableEntry(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlNvencSwSessionUpdateInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgSuspendContext(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlGetP2pCapsMatrix(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlFreePmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlSetTsgInterleaveLevel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlMasterGetVirtualFunctionErrorContIntrMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcLog(POBJGPU, POBJRPC, const char*, NvU32); +typedef NV_STATUS RpcCtrlExecPartitionsDelete(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlPerfBoost(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlDbgSetModeMmuDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlFifoSetChannelProperties(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); +typedef NV_STATUS RpcCtrlSubdeviceGetP2pCaps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*); typedef NV_STATUS RpcUpdateBarPde(POBJGPU, POBJRPC, NV_RPC_UPDATE_PDE_BAR_TYPE, NvU64, NvU64); +typedef NV_STATUS RpcCtrlBindPmResources(POBJGPU, POBJRPC, NvHandle, NvHandle); typedef NV_STATUS RpcMapMemoryDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvHandle, NvU64, NvU64, NvU32, NvU64*); typedef NV_STATUS RpcUnmapMemoryDma(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle, NvHandle, NvU32, NvU64); -typedef NV_STATUS RpcRmfsTest(POBJGPU, POBJRPC, NvU32, NvU32, NvU32, NvU32); +typedef NV_STATUS RpcSetGuestSystemInfoExt(POBJGPU, POBJRPC); typedef NV_STATUS Rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *); @@ -99,26 +219,136 @@ typedef NV_STATUS Rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO * // typedef struct RPC_HAL_IFACES { + RpcCtrlFifoSetupVfZombieSubctxPdb *rpcCtrlFifoSetupVfZombieSubctxPdb; /* CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB */ RpcVgpuPfRegRead32 *rpcVgpuPfRegRead32; /* Read reg value from plugin */ + RpcCtrlBusUnsetP2pMapping *rpcCtrlBusUnsetP2pMapping; /* CTRL_BUS_UNSET_P2P_MAPPING */ RpcDumpProtobufComponent *rpcDumpProtobufComponent; /* Dump a GSP component into the protobuf. */ RpcEccNotifierWriteAck *rpcEccNotifierWriteAck; /* ECC_NOTIFIER_WRITE_ACK */ RpcAllocMemory *rpcAllocMemory; /* ALLOC_MEMORY */ + RpcCtrlDbgReadSingleSmErrorState *rpcCtrlDbgReadSingleSmErrorState; /* CTRL_DBG_READ_SINGLE_SM_ERROR_STATE */ + RpcDisableChannels *rpcDisableChannels; /* Disable channels */ RpcGpuExecRegOps *rpcGpuExecRegOps; /* GPU_EXEC_REG_OPS */ - RpcRmfsInit *rpcRmfsInit; /* Resman File Streaming Init */ + RpcCtrlGpuPromoteCtx *rpcCtrlGpuPromoteCtx; /* GPU_PROMOTE_CTX */ + RpcCtrlDbgSetNextStopTriggerType *rpcCtrlDbgSetNextStopTriggerType; /* CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE */ + RpcAllocShareDevice *rpcAllocShareDevice; /* ALLOC_SHARE_DEVICE */ + RpcCtrlPreempt *rpcCtrlPreempt; /* CTRL_PREEMPT */ + RpcCtrlGpuInitializeCtx *rpcCtrlGpuInitializeCtx; /* CTRL_GPU_INITIALIZE_CTX */ + RpcCtrlReservePmAreaSmpc *rpcCtrlReservePmAreaSmpc; /* CTRL_RESERVE_PM_AREA_SMPC */ + RpcCtrlGpuMigratableOps *rpcCtrlGpuMigratableOps; /* NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS */ + RpcCtrlDbgSetModeErrbarDebug *rpcCtrlDbgSetModeErrbarDebug; /* CTRL_DBG_SET_MODE_ERRBAR_DEBUG */ + RpcCtrlPmaStreamUpdateGetPut *rpcCtrlPmaStreamUpdateGetPut; /* CTRL_HWPM_STREAMOUT_UPDATE_GET_PUT */ + RpcCtrlFabricMemoryDescribe *rpcCtrlFabricMemoryDescribe; /* CTRL_FABRIC_MEMORY_DESCRIBE */ + RpcAllocChannelDma *rpcAllocChannelDma; /* ALLOC_CHANNEL_DMA */ + RpcCtrlSetZbcDepthClear *rpcCtrlSetZbcDepthClear; /* CTRL_SET_ZBC_DEPTH_CLEAR */ + RpcCtrlResetIsolatedChannel *rpcCtrlResetIsolatedChannel; /* CTRL_RESET_ISOLATED_CHANNEL */ + RpcCtrlDmaSetDefaultVaspace *rpcCtrlDmaSetDefaultVaspace; /* CTRL_DMA_SET_DEFAULT_VASPACE */ + RpcAllocSubdevice *rpcAllocSubdevice; /* ALLOC_SUBDEVICE */ + RpcFree *rpcFree; /* FREE */ + RpcDmaControl *rpcDmaControl; /* DMA_CONTROL */ + RpcCtrlDbgClearSingleSmErrorState *rpcCtrlDbgClearSingleSmErrorState; /* CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE */ RpcUnsetPageDirectory *rpcUnsetPageDirectory; /* UNSET_PAGE_DIRECTORY */ RpcGetGspStaticInfo *rpcGetGspStaticInfo; /* Get static info from GSP RM. */ + RpcSaveHibernationData *rpcSaveHibernationData; /* SAVE_HIBERNATION_DATA */ + RpcDupObject *rpcDupObject; /* DUP_OBJECT */ RpcGspSetSystemInfo *rpcGspSetSystemInfo; /* Tells GSP-RM about the overall system environment */ - RpcRmfsCleanup *rpcRmfsCleanup; /* Resman File Cleanup */ + RpcCtrlPmAreaPcSampler *rpcCtrlPmAreaPcSampler; /* CTRL_PM_AREA_PC_SAMPLER */ + RpcCtrlDbgSetExceptionMask *rpcCtrlDbgSetExceptionMask; /* CTRL_DBG_SET_EXCEPTION_MASK */ + RpcCtrlVaspaceCopyServerReservedPdes *rpcCtrlVaspaceCopyServerReservedPdes; /* CTRL_VASPACE_COPY_SERVER_RESERVED_PDES */ + RpcCtrlGrCtxswPreemptionBind *rpcCtrlGrCtxswPreemptionBind; /* CTRL_GR_CTXSW_PREEMPTION_BIND */ + RpcCtrlAllocPmaStream *rpcCtrlAllocPmaStream; /* CTRL_ALLOC_PMA_STREAM */ + RpcCtrlReserveHwpmLegacy *rpcCtrlReserveHwpmLegacy; /* CTRL_RESERVE_HWPM_LEGACY */ + RpcCtrlInternalQuiescePmaChannel *rpcCtrlInternalQuiescePmaChannel; /* CTRL_INTERNAL_QUIESCE_PMA_CHANNEL */ + RpcCtrlPerfRatedTdpGetStatus *rpcCtrlPerfRatedTdpGetStatus; /* CTRL_PERF_RATED_TDP_GET_STATUS */ + RpcCtrlBusSetP2pMapping *rpcCtrlBusSetP2pMapping; /* CTRL_BUS_SET_P2P_MAPPING */ + RpcCtrlGpuGetInfoV2 *rpcCtrlGpuGetInfoV2; /* CTRL_GPU_GET_INFO_V2 */ + RpcCtrlGetHsCredits *rpcCtrlGetHsCredits; /* CTRL_GET_HS_CREDITS */ + RpcCtrlGrSetCtxswPreemptionMode *rpcCtrlGrSetCtxswPreemptionMode; /* CTRL_GR_SET_CTXSW_PREEMPTION_MODE */ + RpcCtrlB0ccExecRegOps *rpcCtrlB0ccExecRegOps; /* CTRL_B0CC_EXEC_REG_OPS */ + RpcCtrlGrmgrGetGrFsInfo *rpcCtrlGrmgrGetGrFsInfo; /* CTRL_GRMGR_GET_GR_FS_INFO */ + RpcCtrlGetZbcClearTable *rpcCtrlGetZbcClearTable; /* CTRL_GET_ZBC_CLEAR_TABLE */ + RpcCleanupSurface *rpcCleanupSurface; /* CLEANUP_SURFACE */ + RpcCtrlSetTimeslice *rpcCtrlSetTimeslice; /* CTRL_SET_TIMESLICE */ + RpcCtrlGpuQueryEccStatus *rpcCtrlGpuQueryEccStatus; /* CTRL_GPU_QUERY_ECC_STATUS */ + RpcCtrlDbgGetModeMmuDebug *rpcCtrlDbgGetModeMmuDebug; /* CTRL_DBG_GET_MODE_MMU_DEBUG */ + RpcCtrlDbgClearAllSmErrorStates *rpcCtrlDbgClearAllSmErrorStates; /* CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES */ + RpcVgpuGspRingDoorbell *rpcVgpuGspRingDoorbell; /* Ring the doorbell register */ + RpcCtrlGrSetTpcPartitionMode *rpcCtrlGrSetTpcPartitionMode; /* CTRL_GR_SET_TPC_PARTITION_MODE */ + RpcCtrlGetTotalHsCredits *rpcCtrlGetTotalHsCredits; /* CTRL_GET_TOTAL_HS_CREDITS */ + RpcCtrlInternalPromoteFaultMethodBuffers *rpcCtrlInternalPromoteFaultMethodBuffers; /* CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS */ + RpcCtrlFbGetInfoV2 *rpcCtrlFbGetInfoV2; /* CTRL_FB_GET_INFO_V2 */ + RpcVgpuGspWriteScratchRegister *rpcVgpuGspWriteScratchRegister; /* Write the vGPU GSP scratch register */ RpcSetPageDirectory *rpcSetPageDirectory; /* SET_PAGE_DIRECTORY */ + RpcCtrlGetP2pCapsV2 *rpcCtrlGetP2pCapsV2; /* CTRL_GET_P2P_CAPS_V2 */ + RpcCtrlNvlinkGetInbandReceivedData *rpcCtrlNvlinkGetInbandReceivedData; /* CTRL_NVLINK_GET_INBAND_RECEIVED_DATA */ + RpcCtrlGetCePceMask *rpcCtrlGetCePceMask; /* CTRL_GET_CE_PCE_MASK */ + RpcCtrlGetNvlinkPeerIdMask *rpcCtrlGetNvlinkPeerIdMask; /* CTRL_GET_NVLINK_PEER_ID_MASK */ + RpcCtrlGpuEvictCtx *rpcCtrlGpuEvictCtx; /* CTRL_GPU_EVICT_CTX */ + RpcCtrlGetMmuDebugMode *rpcCtrlGetMmuDebugMode; /* CTRL_GET_MMU_DEBUG_MODE */ + RpcInvalidateTlb *rpcInvalidateTlb; /* INVALIDATE_TLB */ + RpcCtrlDbgSetSingleSmSingleStep *rpcCtrlDbgSetSingleSmSingleStep; /* CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP */ RpcUnloadingGuestDriver *rpcUnloadingGuestDriver; /* UNLOADING_GUEST_DRIVER */ + RpcGetEngineUtilizationWrapper *rpcGetEngineUtilizationWrapper; /* Get engine utilization wrapper */ + RpcGetConsolidatedGrStaticInfo *rpcGetConsolidatedGrStaticInfo; /* GET_CONSOLIDATED_GR_STATIC_INFO */ + RpcSwitchToVga *rpcSwitchToVga; /* SWITCH_TO_VGA */ + RpcCtrlResetChannel *rpcCtrlResetChannel; /* CTRL_RESET_CHANNEL */ + RpcCtrlGpfifoSchedule *rpcCtrlGpfifoSchedule; /* CTRL_GPFIFO_SCHEDULE */ RpcSetRegistry *rpcSetRegistry; /* GSP Init Set registry values */ - RpcRmfsCloseQueue *rpcRmfsCloseQueue; /* Resman File Streaming Close Queue */ - RpcGetStaticInfo *rpcGetStaticInfo; /* GET_STATIC_INFO */ + RpcCtrlGetNvlinkStatus *rpcCtrlGetNvlinkStatus; /* CTRL_NVLINK_GET_NVLINK_STATUS */ + RpcGetStaticData *rpcGetStaticData; /* GET_STATIC_DATA published for OpenRM */ + RpcCtrlGrGetTpcPartitionMode *rpcCtrlGrGetTpcPartitionMode; /* CTRL_GR_GET_TPC_PARTITION_MODE */ + RpcCtrlStopChannel *rpcCtrlStopChannel; /* CTRL_STOP_CHANNEL */ + RpcSetSurfaceProperties *rpcSetSurfaceProperties; /* SET_SURFACE_PROPERTIES */ + RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex *rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex; /* CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX */ + RpcCtrlTimerSetGrTickFreq *rpcCtrlTimerSetGrTickFreq; /* CTRL_TIMER_SET_GR_TICK_FREQ */ + RpcAllocEvent *rpcAllocEvent; /* ALLOC_EVENT */ + RpcCtrlGrPcSamplingMode *rpcCtrlGrPcSamplingMode; /* CTRL_GR_PC_SAMPLING_MODE */ + RpcCtrlMcServiceInterrupts *rpcCtrlMcServiceInterrupts; /* CTRL_MC_SERVICE_INTERRUPTS */ + RpcCtrlDbgReadAllSmErrorStates *rpcCtrlDbgReadAllSmErrorStates; /* CTRL_DBG_READ_ALL_SM_ERROR_STATES */ + RpcCtrlSetZbcColorClear *rpcCtrlSetZbcColorClear; /* CTRL_SET_ZBC_COLOR_CLEAR */ + RpcGetEncoderCapacity *rpcGetEncoderCapacity; /* Get encoder capacity */ + RpcCtrlGetP2pCaps *rpcCtrlGetP2pCaps; /* CTRL_GET_P2P_CAPS */ + RpcPerfGetLevelInfo *rpcPerfGetLevelInfo; /* PERF_GET_LEVEL_INFO */ + RpcAllocObject *rpcAllocObject; /* ALLOC_OBJECT */ + RpcCtrlGpuHandleVfPriFault *rpcCtrlGpuHandleVfPriFault; /* CTRL_GPU_HANDLE_VF_PRI_FAULT */ + RpcRmApiControl *rpcRmApiControl; /* RM_API_CONTROL */ + RpcCtrlFabricMemStats *rpcCtrlFabricMemStats; /* CTRL_FABRIC_MEM_STATS */ + RpcCtrlGrCtxswZcullBind *rpcCtrlGrCtxswZcullBind; /* CTRL_GR_CTXSW_ZCULL_BIND */ + RpcCtrlInternalMemsysSetZbcReferenced *rpcCtrlInternalMemsysSetZbcReferenced; /* CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED */ + RpcCtrlPerfRatedTdpSetControl *rpcCtrlPerfRatedTdpSetControl; /* CTRL_PERF_RATED_TDP_SET_CONTROL */ + RpcCtrlExecPartitionsCreate *rpcCtrlExecPartitionsCreate; /* CTRL_EXEC_PARTITIONS_CREATE */ + RpcCtrlGpfifoGetWorkSubmitToken *rpcCtrlGpfifoGetWorkSubmitToken; /* CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN */ RpcIdleChannels *rpcIdleChannels; /* IDLE_CHANNELS */ + RpcCtrlCmdInternalGpuStartFabricProbe *rpcCtrlCmdInternalGpuStartFabricProbe; /* CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS */ + RpcGetBrandCaps *rpcGetBrandCaps; /* GET_BRAND_CAPS */ + RpcRestoreHibernationData *rpcRestoreHibernationData; /* RESTORE_HIBERNATION_DATA */ + RpcCtrlFlaSetupInstanceMemBlock *rpcCtrlFlaSetupInstanceMemBlock; /* NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK */ + RpcCtrlInternalSriovPromotePmaStream *rpcCtrlInternalSriovPromotePmaStream; /* CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM */ + RpcCtrlFbGetFsInfo *rpcCtrlFbGetFsInfo; /* CTRL_FB_GET_FS_INFO */ + RpcCtrlSetChannelInterleaveLevel *rpcCtrlSetChannelInterleaveLevel; /* CTRL_SET_CHANNEL_INTERLEAVE_LEVEL */ + RpcCtrlDbgResumeContext *rpcCtrlDbgResumeContext; /* CTRL_DBG_RESUME_CONTEXT */ + RpcAllocRoot *rpcAllocRoot; /* ALLOC_ROOT */ + RpcCtrlFifoDisableChannels *rpcCtrlFifoDisableChannels; /* CTRL_FIFO_DISABLE_CHANNELS */ + RpcCtrlSetHsCredits *rpcCtrlSetHsCredits; /* CTRL_SET_HS_CREDITS */ + RpcGetEngineUtilization *rpcGetEngineUtilization; /* GET_ENGINE_UTILIZATION */ + RpcCtrlGetZbcClearTableEntry *rpcCtrlGetZbcClearTableEntry; /* CTRL_GET_ZBC_CLEAR_TABLE_ENTRY */ + RpcCtrlNvencSwSessionUpdateInfo *rpcCtrlNvencSwSessionUpdateInfo; /* CTRL_NVENC_SW_SESSION_UPDATE_INFO */ + RpcCtrlDbgSuspendContext *rpcCtrlDbgSuspendContext; /* CTRL_DBG_SUSPEND_CONTEXT */ + RpcCtrlGetP2pCapsMatrix *rpcCtrlGetP2pCapsMatrix; /* CTRL_GET_P2P_CAPS_MATRIX */ + RpcCtrlDbgExecRegOps *rpcCtrlDbgExecRegOps; /* CTRL_DBG_EXEC_REG_OPS */ + RpcCtrlFreePmaStream *rpcCtrlFreePmaStream; /* CTRL_FREE_PMA_STREAM */ + RpcCtrlSetTsgInterleaveLevel *rpcCtrlSetTsgInterleaveLevel; /* CTRL_SET_TSG_INTERLEAVE_LEVEL */ + RpcCtrlMasterGetVirtualFunctionErrorContIntrMask *rpcCtrlMasterGetVirtualFunctionErrorContIntrMask; /* CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK */ + RpcLog *rpcLog; /* LOG */ + RpcCtrlExecPartitionsDelete *rpcCtrlExecPartitionsDelete; /* CTRL_EXEC_PARTITIONS_DELETE */ + RpcCtrlPerfBoost *rpcCtrlPerfBoost; /* CTRL_PERF_BOOST */ + RpcCtrlDbgSetModeMmuDebug *rpcCtrlDbgSetModeMmuDebug; /* CTRL_DBG_SET_MODE_MMU_DEBUG */ + RpcCtrlFifoSetChannelProperties *rpcCtrlFifoSetChannelProperties; /* CTRL_FIFO_SET_CHANNEL_PROPERTIES */ + RpcCtrlSubdeviceGetP2pCaps *rpcCtrlSubdeviceGetP2pCaps; /* CTRL_SUBDEVICE_GET_P2P_CAPS */ RpcUpdateBarPde *rpcUpdateBarPde; /* Update the value of BAR1/BAR2 PDE */ + RpcCtrlBindPmResources *rpcCtrlBindPmResources; /* CTRL_BIND_PM_RESOURCES */ RpcMapMemoryDma *rpcMapMemoryDma; /* MAP_MEMORY_DMA */ RpcUnmapMemoryDma *rpcUnmapMemoryDma; /* UNMAP_MEMORY_DMA */ - RpcRmfsTest *rpcRmfsTest; /* Resman File Streaming Test */ + RpcSetGuestSystemInfoExt *rpcSetGuestSystemInfoExt; /* SET_GUEST_SYSTEM_INFO_EXT */ Rpc_iGrp_ipVersions_getInfo *rpc_iGrp_ipVersions_getInfo; /* Return lookup table of hal interface ptrs based on IP_VERSION */ } RPC_HAL_IFACES; @@ -128,46 +358,266 @@ typedef struct RPC_HAL_IFACES { // eg: #define rpcReadFoo_HAL(_pGpu, _pRpc) _pRpc->hal.rpcReadFoo(_pGpu, _pRpc) // +#define rpcCtrlFifoSetupVfZombieSubctxPdb_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFifoSetupVfZombieSubctxPdb(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcVgpuPfRegRead32_HAL(_pGpu, _pRpc, _arg0, _pArg1, _arg2) \ (_pRpc)->_hal.rpcVgpuPfRegRead32(_pGpu, _pRpc, _arg0, _pArg1, _arg2) +#define rpcCtrlBusUnsetP2pMapping_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlBusUnsetP2pMapping(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcDumpProtobufComponent_HAL(_pGpu, _pRpc, _pPrbEnc, _pNvDumpState, _component) \ (_pRpc)->_hal.rpcDumpProtobufComponent(_pGpu, _pRpc, _pPrbEnc, _pNvDumpState, _component) #define rpcEccNotifierWriteAck_HAL(_pGpu, _pRpc) \ (_pRpc)->_hal.rpcEccNotifierWriteAck(_pGpu, _pRpc) #define rpcAllocMemory_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _pArg5) \ (_pRpc)->_hal.rpcAllocMemory(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _pArg5) +#define rpcCtrlDbgReadSingleSmErrorState_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgReadSingleSmErrorState(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcDisableChannels_HAL(_pGpu, _pRpc, _arg0) \ + (_pRpc)->_hal.rpcDisableChannels(_pGpu, _pRpc, _arg0) #define rpcGpuExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) \ (_pRpc)->_hal.rpcGpuExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) -#define rpcRmfsInit_HAL(_pGpu, _pRpc, _arg0) \ - (_pRpc)->_hal.rpcRmfsInit(_pGpu, _pRpc, _arg0) +#define rpcCtrlGpuPromoteCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpuPromoteCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgSetNextStopTriggerType_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgSetNextStopTriggerType(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcAllocShareDevice_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _arg7, _arg8) \ + (_pRpc)->_hal.rpcAllocShareDevice(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _arg7, _arg8) +#define rpcCtrlPreempt_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlPreempt(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGpuInitializeCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpuInitializeCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlReservePmAreaSmpc_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlReservePmAreaSmpc(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGpuMigratableOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpuMigratableOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgSetModeErrbarDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgSetModeErrbarDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlPmaStreamUpdateGetPut_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlPmaStreamUpdateGetPut(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlFabricMemoryDescribe_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFabricMemoryDescribe(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcAllocChannelDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4, _pArg5) \ + (_pRpc)->_hal.rpcAllocChannelDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4, _pArg5) +#define rpcCtrlSetZbcDepthClear_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlSetZbcDepthClear(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlResetIsolatedChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlResetIsolatedChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDmaSetDefaultVaspace_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDmaSetDefaultVaspace(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcAllocSubdevice_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4) \ + (_pRpc)->_hal.rpcAllocSubdevice(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4) +#define rpcFree_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \ + (_pRpc)->_hal.rpcFree(_pGpu, _pRpc, _arg0, _arg1, _arg2) +#define rpcDmaControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ + (_pRpc)->_hal.rpcDmaControl(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) +#define rpcCtrlDbgClearSingleSmErrorState_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgClearSingleSmErrorState(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcUnsetPageDirectory_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ (_pRpc)->_hal.rpcUnsetPageDirectory(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcGetGspStaticInfo_HAL(_pGpu, _pRpc) \ (_pRpc)->_hal.rpcGetGspStaticInfo(_pGpu, _pRpc) +#define rpcSaveHibernationData_HAL(_pGpu, _pRpc) \ + (_pRpc)->_hal.rpcSaveHibernationData(_pGpu, _pRpc) +#define rpcDupObject_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) \ + (_pRpc)->_hal.rpcDupObject(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) #define rpcGspSetSystemInfo_HAL(_pGpu, _pRpc) \ (_pRpc)->_hal.rpcGspSetSystemInfo(_pGpu, _pRpc) -#define rpcRmfsCleanup_HAL(_pGpu, _pRpc) \ - (_pRpc)->_hal.rpcRmfsCleanup(_pGpu, _pRpc) +#define rpcCtrlPmAreaPcSampler_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) \ + (_pRpc)->_hal.rpcCtrlPmAreaPcSampler(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) +#define rpcCtrlDbgSetExceptionMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgSetExceptionMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlVaspaceCopyServerReservedPdes_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlVaspaceCopyServerReservedPdes(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGrCtxswPreemptionBind_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGrCtxswPreemptionBind(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlAllocPmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlAllocPmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlReserveHwpmLegacy_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlReserveHwpmLegacy(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlInternalQuiescePmaChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlInternalQuiescePmaChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlPerfRatedTdpGetStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlPerfRatedTdpGetStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlBusSetP2pMapping_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlBusSetP2pMapping(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGpuGetInfoV2_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpuGetInfoV2(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGetHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGrSetCtxswPreemptionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGrSetCtxswPreemptionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlB0ccExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlB0ccExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGrmgrGetGrFsInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGrmgrGetGrFsInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGetZbcClearTable_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetZbcClearTable(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCleanupSurface_HAL(_pGpu, _pRpc, _pArg0) \ + (_pRpc)->_hal.rpcCleanupSurface(_pGpu, _pRpc, _pArg0) +#define rpcCtrlSetTimeslice_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlSetTimeslice(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGpuQueryEccStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpuQueryEccStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgGetModeMmuDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgGetModeMmuDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgClearAllSmErrorStates_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgClearAllSmErrorStates(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcVgpuGspRingDoorbell_HAL(_pRpc, _pGpu, _arg0) \ + (_pRpc)->_hal.rpcVgpuGspRingDoorbell(_pGpu, _arg0) +#define rpcCtrlGrSetTpcPartitionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGrSetTpcPartitionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGetTotalHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetTotalHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlInternalPromoteFaultMethodBuffers_HAL(_pArg0, _pRpc, _arg1, _arg2, _pArg3) \ + (_pRpc)->_hal.rpcCtrlInternalPromoteFaultMethodBuffers(_pArg0, _pRpc, _arg1, _arg2, _pArg3) +#define rpcCtrlFbGetInfoV2_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFbGetInfoV2(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcVgpuGspWriteScratchRegister_HAL(_pRpc, _pGpu, _arg0) \ + (_pRpc)->_hal.rpcVgpuGspWriteScratchRegister(_pGpu, _arg0) #define rpcSetPageDirectory_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ (_pRpc)->_hal.rpcSetPageDirectory(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGetP2pCapsV2_HAL(_pGpu, _pRpc, _pArg0) \ + (_pRpc)->_hal.rpcCtrlGetP2pCapsV2(_pGpu, _pRpc, _pArg0) +#define rpcCtrlNvlinkGetInbandReceivedData_HAL(_pGpu, _pRpc, _pArg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlNvlinkGetInbandReceivedData(_pGpu, _pRpc, _pArg0, _arg1, _pArg2) +#define rpcCtrlGetCePceMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetCePceMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGetNvlinkPeerIdMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetNvlinkPeerIdMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGpuEvictCtx_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpuEvictCtx(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGetMmuDebugMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetMmuDebugMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcInvalidateTlb_HAL(_pGpu, _pRpc, _arg0, _arg1) \ + (_pRpc)->_hal.rpcInvalidateTlb(_pGpu, _pRpc, _arg0, _arg1) +#define rpcCtrlDbgSetSingleSmSingleStep_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgSetSingleSmSingleStep(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcUnloadingGuestDriver_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \ (_pRpc)->_hal.rpcUnloadingGuestDriver(_pGpu, _pRpc, _arg0, _arg1, _arg2) +#define rpcGetEngineUtilizationWrapper_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ + (_pRpc)->_hal.rpcGetEngineUtilizationWrapper(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) +#define rpcGetConsolidatedGrStaticInfo_HAL(_pGpu, _pRpc) \ + (_pRpc)->_hal.rpcGetConsolidatedGrStaticInfo(_pGpu, _pRpc) +#define rpcSwitchToVga_HAL(_pGpu, _pRpc) \ + (_pRpc)->_hal.rpcSwitchToVga(_pGpu, _pRpc) +#define rpcCtrlResetChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlResetChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGpfifoSchedule_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) \ + (_pRpc)->_hal.rpcCtrlGpfifoSchedule(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) #define rpcSetRegistry_HAL(_pGpu, _pRpc) \ (_pRpc)->_hal.rpcSetRegistry(_pGpu, _pRpc) -#define rpcRmfsCloseQueue_HAL(_pGpu, _pRpc) \ - (_pRpc)->_hal.rpcRmfsCloseQueue(_pGpu, _pRpc) -#define rpcGetStaticInfo_HAL(_pGpu, _pRpc) \ - (_pRpc)->_hal.rpcGetStaticInfo(_pGpu, _pRpc) +#define rpcCtrlGetNvlinkStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetNvlinkStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcGetStaticData_HAL(_pGpu, _pRpc) \ + (_pRpc)->_hal.rpcGetStaticData(_pGpu, _pRpc) +#define rpcCtrlGrGetTpcPartitionMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGrGetTpcPartitionMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlStopChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlStopChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcSetSurfaceProperties_HAL(_pGpu, _pRpc, _arg0, _pArg1, _arg2) \ + (_pRpc)->_hal.rpcSetSurfaceProperties(_pGpu, _pRpc, _arg0, _pArg1, _arg2) +#define rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlTimerSetGrTickFreq_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlTimerSetGrTickFreq(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcAllocEvent_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6) \ + (_pRpc)->_hal.rpcAllocEvent(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6) +#define rpcCtrlGrPcSamplingMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGrPcSamplingMode(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlMcServiceInterrupts_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlMcServiceInterrupts(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgReadAllSmErrorStates_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgReadAllSmErrorStates(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlSetZbcColorClear_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlSetZbcColorClear(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcGetEncoderCapacity_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcGetEncoderCapacity(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGetP2pCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetP2pCaps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcPerfGetLevelInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) \ + (_pRpc)->_hal.rpcPerfGetLevelInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2, _pArg3) +#define rpcAllocObject_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4) \ + (_pRpc)->_hal.rpcAllocObject(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _pArg4) +#define rpcCtrlGpuHandleVfPriFault_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpuHandleVfPriFault(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcRmApiControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ + (_pRpc)->_hal.rpcRmApiControl(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) +#define rpcCtrlFabricMemStats_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFabricMemStats(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGrCtxswZcullBind_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGrCtxswZcullBind(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlInternalMemsysSetZbcReferenced_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlInternalMemsysSetZbcReferenced(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlPerfRatedTdpSetControl_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlPerfRatedTdpSetControl(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlExecPartitionsCreate_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlExecPartitionsCreate(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGpfifoGetWorkSubmitToken_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGpfifoGetWorkSubmitToken(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcIdleChannels_HAL(_pArg0, _pRpc, _pPhclients, _pPhdevices, _pPhchannels, _nentries, _flags, _timeout) \ (_pRpc)->_hal.rpcIdleChannels(_pArg0, _pRpc, _pPhclients, _pPhdevices, _pPhchannels, _nentries, _flags, _timeout) +#define rpcCtrlCmdInternalGpuStartFabricProbe_HAL(_pGpu, _pRpc, _pArg0) \ + (_pRpc)->_hal.rpcCtrlCmdInternalGpuStartFabricProbe(_pGpu, _pRpc, _pArg0) +#define rpcGetBrandCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ + (_pRpc)->_hal.rpcGetBrandCaps(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) +#define rpcRestoreHibernationData_HAL(_pGpu, _pRpc) \ + (_pRpc)->_hal.rpcRestoreHibernationData(_pGpu, _pRpc) +#define rpcCtrlFlaSetupInstanceMemBlock_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFlaSetupInstanceMemBlock(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlInternalSriovPromotePmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlInternalSriovPromotePmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlFbGetFsInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFbGetFsInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlSetChannelInterleaveLevel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlSetChannelInterleaveLevel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgResumeContext_HAL(_pGpu, _pRpc, _arg0, _arg1) \ + (_pRpc)->_hal.rpcCtrlDbgResumeContext(_pGpu, _pRpc, _arg0, _arg1) +#define rpcAllocRoot_HAL(_pGpu, _pRpc, _arg0) \ + (_pRpc)->_hal.rpcAllocRoot(_pGpu, _pRpc, _arg0) +#define rpcCtrlFifoDisableChannels_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFifoDisableChannels(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlSetHsCredits_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlSetHsCredits(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcGetEngineUtilization_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) \ + (_pRpc)->_hal.rpcGetEngineUtilization(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3, _arg4) +#define rpcCtrlGetZbcClearTableEntry_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetZbcClearTableEntry(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlNvencSwSessionUpdateInfo_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlNvencSwSessionUpdateInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgSuspendContext_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgSuspendContext(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlGetP2pCapsMatrix_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlGetP2pCapsMatrix(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgExecRegOps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgExecRegOps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlFreePmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFreePmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlSetTsgInterleaveLevel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlSetTsgInterleaveLevel(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlMasterGetVirtualFunctionErrorContIntrMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcLog_HAL(_pGpu, _pRpc, _pChar, _arg0) \ + (_pRpc)->_hal.rpcLog(_pGpu, _pRpc, _pChar, _arg0) +#define rpcCtrlExecPartitionsDelete_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlExecPartitionsDelete(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlPerfBoost_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlPerfBoost(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlDbgSetModeMmuDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlDbgSetModeMmuDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlFifoSetChannelProperties_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlFifoSetChannelProperties(_pGpu, _pRpc, _arg0, _arg1, _pArg2) +#define rpcCtrlSubdeviceGetP2pCaps_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \ + (_pRpc)->_hal.rpcCtrlSubdeviceGetP2pCaps(_pGpu, _pRpc, _arg0, _arg1, _pArg2) #define rpcUpdateBarPde_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2) \ (_pRpc)->_hal.rpcUpdateBarPde(_pGpu, _pRpc, _arg0, _arg1, _arg2) +#define rpcCtrlBindPmResources_HAL(_pGpu, _pRpc, _arg0, _arg1) \ + (_pRpc)->_hal.rpcCtrlBindPmResources(_pGpu, _pRpc, _arg0, _arg1) #define rpcMapMemoryDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _pArg7) \ (_pRpc)->_hal.rpcMapMemoryDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6, _pArg7) #define rpcUnmapMemoryDma_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) \ (_pRpc)->_hal.rpcUnmapMemoryDma(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) -#define rpcRmfsTest_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3) \ - (_pRpc)->_hal.rpcRmfsTest(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3) +#define rpcSetGuestSystemInfoExt_HAL(_pGpu, _pRpc) \ + (_pRpc)->_hal.rpcSetGuestSystemInfoExt(_pGpu, _pRpc) #define rpc_iGrp_ipVersions_getInfo_HAL(_pRpc, _pArg0) \ (_pRpc)->_hal.rpc_iGrp_ipVersions_getInfo(_pArg0) diff --git a/src/nvidia/generated/g_rpc_iom.c b/src/nvidia/generated/g_rpc_iom.c index c66f6c48c9..c9221a8ae1 100644 --- a/src/nvidia/generated/g_rpc_iom.c +++ b/src/nvidia/generated/g_rpc_iom.c @@ -37,8 +37,8 @@ void rpcObjIfacesSetup(OBJRPC *pRpc) pRpcMethods->__rpcDestroy__ = rpcDestroy_IMPL; pRpcMethods->__rpcSendMessage__ = rpcSendMessage_IMPL; pRpcMethods->__rpcRecvPoll__ = rpcRecvPoll_IMPL; - // pRpcMethods->__rpcSendMessageUvm__ = rpcSendMessageUvm_IMPL; # ONLY_IF => VIRTUALIZATION - // pRpcMethods->__rpcRecvPollUvm__ = rpcRecvPollUvm_IMPL; # ONLY_IF => VIRTUALIZATION + // pRpcMethods->__rpcSendMessageUvm__ = rpcSendMessageUvm_IMPL; # ONLY_IF => VIRTUALIZATION_LEGACY + // pRpcMethods->__rpcRecvPollUvm__ = rpcRecvPollUvm_IMPL; # ONLY_IF => VIRTUALIZATION_LEGACY } static void diff --git a/src/nvidia/generated/g_rpc_private.h b/src/nvidia/generated/g_rpc_private.h index 9e48b38161..75d993b06f 100644 --- a/src/nvidia/generated/g_rpc_private.h +++ b/src/nvidia/generated/g_rpc_private.h @@ -13,10 +13,18 @@ #include "g_rpc_hal.h" + // RPC:CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB +RpcCtrlFifoSetupVfZombieSubctxPdb rpcCtrlFifoSetupVfZombieSubctxPdb_v1A_23; +RpcCtrlFifoSetupVfZombieSubctxPdb rpcCtrlFifoSetupVfZombieSubctxPdb_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:VGPU_PF_REG_READ32 RpcVgpuPfRegRead32 rpcVgpuPfRegRead32_v15_00; RpcVgpuPfRegRead32 rpcVgpuPfRegRead32_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_BUS_UNSET_P2P_MAPPING +RpcCtrlBusUnsetP2pMapping rpcCtrlBusUnsetP2pMapping_v21_03; +RpcCtrlBusUnsetP2pMapping rpcCtrlBusUnsetP2pMapping_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:DUMP_PROTOBUF_COMPONENT RpcDumpProtobufComponent rpcDumpProtobufComponent_v18_12; RpcDumpProtobufComponent rpcDumpProtobufComponent_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X @@ -29,957 +37,531 @@ RpcEccNotifierWriteAck rpcEccNotifierWriteAck_STUB; // TU10X, GA100 RpcAllocMemory rpcAllocMemory_v13_01; RpcAllocMemory rpcAllocMemory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_DBG_READ_SINGLE_SM_ERROR_STATE +RpcCtrlDbgReadSingleSmErrorState rpcCtrlDbgReadSingleSmErrorState_v21_06; +RpcCtrlDbgReadSingleSmErrorState rpcCtrlDbgReadSingleSmErrorState_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:DISABLE_CHANNELS +RpcDisableChannels rpcDisableChannels_v1E_0B; +RpcDisableChannels rpcDisableChannels_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:GPU_EXEC_REG_OPS RpcGpuExecRegOps rpcGpuExecRegOps_v12_01; RpcGpuExecRegOps rpcGpuExecRegOps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // RPC:RMFS_INIT -RpcRmfsInit rpcRmfsInit_v15_00; -RpcRmfsInit rpcRmfsInit_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - - // RPC:UNSET_PAGE_DIRECTORY -RpcUnsetPageDirectory rpcUnsetPageDirectory_v03_00; -RpcUnsetPageDirectory rpcUnsetPageDirectory_v1E_05; -RpcUnsetPageDirectory rpcUnsetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - - // RPC:GET_GSP_STATIC_INFO -RpcGetGspStaticInfo rpcGetGspStaticInfo_v14_00; -RpcGetGspStaticInfo rpcGetGspStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - - // RPC:GSP_SET_SYSTEM_INFO -RpcGspSetSystemInfo rpcGspSetSystemInfo_v17_00; -RpcGspSetSystemInfo rpcGspSetSystemInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - - // RPC:RMFS_CLEANUP -RpcRmfsCleanup rpcRmfsCleanup_v15_00; -RpcRmfsCleanup rpcRmfsCleanup_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - - // RPC:SET_PAGE_DIRECTORY -RpcSetPageDirectory rpcSetPageDirectory_v03_00; -RpcSetPageDirectory rpcSetPageDirectory_v1E_05; -RpcSetPageDirectory rpcSetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - - // RPC:UNLOADING_GUEST_DRIVER -RpcUnloadingGuestDriver rpcUnloadingGuestDriver_v03_00; -RpcUnloadingGuestDriver rpcUnloadingGuestDriver_v1F_07; -RpcUnloadingGuestDriver rpcUnloadingGuestDriver_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_GPU_PROMOTE_CTX +RpcCtrlGpuPromoteCtx rpcCtrlGpuPromoteCtx_v1A_20; +RpcCtrlGpuPromoteCtx rpcCtrlGpuPromoteCtx_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // RPC:SET_REGISTRY -RpcSetRegistry rpcSetRegistry_v17_00; -RpcSetRegistry rpcSetRegistry_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE +RpcCtrlDbgSetNextStopTriggerType rpcCtrlDbgSetNextStopTriggerType_v1A_10; +RpcCtrlDbgSetNextStopTriggerType rpcCtrlDbgSetNextStopTriggerType_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // RPC:RMFS_CLOSE_QUEUE -RpcRmfsCloseQueue rpcRmfsCloseQueue_v15_00; -RpcRmfsCloseQueue rpcRmfsCloseQueue_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - - // RPC:GET_STATIC_INFO -RpcGetStaticInfo rpcGetStaticInfo_v17_05; -RpcGetStaticInfo rpcGetStaticInfo_v18_03; -RpcGetStaticInfo rpcGetStaticInfo_v18_04; -RpcGetStaticInfo rpcGetStaticInfo_v18_0E; -RpcGetStaticInfo rpcGetStaticInfo_v18_10; -RpcGetStaticInfo rpcGetStaticInfo_v18_11; -RpcGetStaticInfo rpcGetStaticInfo_v18_13; -RpcGetStaticInfo rpcGetStaticInfo_v18_16; -RpcGetStaticInfo rpcGetStaticInfo_v19_00; -RpcGetStaticInfo rpcGetStaticInfo_v1A_00; -RpcGetStaticInfo rpcGetStaticInfo_v1A_05; -RpcGetStaticInfo rpcGetStaticInfo_v20_01; -RpcGetStaticInfo rpcGetStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:ALLOC_SHARE_DEVICE +RpcAllocShareDevice rpcAllocShareDevice_v03_00; +RpcAllocShareDevice rpcAllocShareDevice_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // RPC:IDLE_CHANNELS -RpcIdleChannels rpcIdleChannels_v03_00; -RpcIdleChannels rpcIdleChannels_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_PREEMPT +RpcCtrlPreempt rpcCtrlPreempt_v1A_0A; +RpcCtrlPreempt rpcCtrlPreempt_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // RPC:UPDATE_BAR_PDE -RpcUpdateBarPde rpcUpdateBarPde_v15_00; -RpcUpdateBarPde rpcUpdateBarPde_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_GPU_INITIALIZE_CTX +RpcCtrlGpuInitializeCtx rpcCtrlGpuInitializeCtx_v1A_0E; +RpcCtrlGpuInitializeCtx rpcCtrlGpuInitializeCtx_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // RPC:MAP_MEMORY_DMA -RpcMapMemoryDma rpcMapMemoryDma_v03_00; -RpcMapMemoryDma rpcMapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_RESERVE_PM_AREA_SMPC +RpcCtrlReservePmAreaSmpc rpcCtrlReservePmAreaSmpc_v1A_0F; +RpcCtrlReservePmAreaSmpc rpcCtrlReservePmAreaSmpc_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // RPC:UNMAP_MEMORY_DMA -RpcUnmapMemoryDma rpcUnmapMemoryDma_v03_00; -RpcUnmapMemoryDma rpcUnmapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_GPU_MIGRATABLE_OPS +RpcCtrlGpuMigratableOps rpcCtrlGpuMigratableOps_v21_07; +RpcCtrlGpuMigratableOps rpcCtrlGpuMigratableOps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // RPC:RMFS_TEST -RpcRmfsTest rpcRmfsTest_v15_00; -RpcRmfsTest rpcRmfsTest_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_DBG_SET_MODE_ERRBAR_DEBUG +RpcCtrlDbgSetModeErrbarDebug rpcCtrlDbgSetModeErrbarDebug_v1A_10; +RpcCtrlDbgSetModeErrbarDebug rpcCtrlDbgSetModeErrbarDebug_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_PMA_STREAM_UPDATE_GET_PUT +RpcCtrlPmaStreamUpdateGetPut rpcCtrlPmaStreamUpdateGetPut_v1A_14; +RpcCtrlPmaStreamUpdateGetPut rpcCtrlPmaStreamUpdateGetPut_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_FABRIC_MEMORY_DESCRIBE +RpcCtrlFabricMemoryDescribe rpcCtrlFabricMemoryDescribe_v1E_0C; +RpcCtrlFabricMemoryDescribe rpcCtrlFabricMemoryDescribe_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:ALLOC_CHANNEL_DMA +RpcAllocChannelDma rpcAllocChannelDma_v1F_04; +RpcAllocChannelDma rpcAllocChannelDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_SET_ZBC_DEPTH_CLEAR +RpcCtrlSetZbcDepthClear rpcCtrlSetZbcDepthClear_v1A_09; +RpcCtrlSetZbcDepthClear rpcCtrlSetZbcDepthClear_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_RESET_ISOLATED_CHANNEL +RpcCtrlResetIsolatedChannel rpcCtrlResetIsolatedChannel_v1A_09; +RpcCtrlResetIsolatedChannel rpcCtrlResetIsolatedChannel_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// -// RPC's object-level *non-static* interface functions (static ones are below) -// -RpcConstruct rpcConstruct_IMPL; -RpcDestroy rpcDestroy_IMPL; -RpcSendMessage rpcSendMessage_IMPL; -RpcRecvPoll rpcRecvPoll_IMPL; + // RPC:CTRL_DMA_SET_DEFAULT_VASPACE +RpcCtrlDmaSetDefaultVaspace rpcCtrlDmaSetDefaultVaspace_v1A_0E; +RpcCtrlDmaSetDefaultVaspace rpcCtrlDmaSetDefaultVaspace_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:ALLOC_SUBDEVICE +RpcAllocSubdevice rpcAllocSubdevice_v08_01; +RpcAllocSubdevice rpcAllocSubdevice_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:FREE +RpcFree rpcFree_v03_00; +RpcFree rpcFree_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#if defined(RMCFG_ENGINE_SETUP) // for use by hal init only + // RPC:DMA_CONTROL +RpcDmaControl rpcDmaControl_v24_05; +RpcDmaControl rpcDmaControl_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE +RpcCtrlDbgClearSingleSmErrorState rpcCtrlDbgClearSingleSmErrorState_v1A_10; +RpcCtrlDbgClearSingleSmErrorState rpcCtrlDbgClearSingleSmErrorState_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:UNSET_PAGE_DIRECTORY +RpcUnsetPageDirectory rpcUnsetPageDirectory_v1E_05; +RpcUnsetPageDirectory rpcUnsetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:GET_GSP_STATIC_INFO +RpcGetGspStaticInfo rpcGetGspStaticInfo_v14_00; +RpcGetGspStaticInfo rpcGetGspStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:SAVE_HIBERNATION_DATA +RpcSaveHibernationData rpcSaveHibernationData_v1E_0E; +RpcSaveHibernationData rpcSaveHibernationData_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v03_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:DUP_OBJECT +RpcDupObject rpcDupObject_v03_00; +RpcDupObject rpcDupObject_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:GSP_SET_SYSTEM_INFO +RpcGspSetSystemInfo rpcGspSetSystemInfo_v17_00; +RpcGspSetSystemInfo rpcGspSetSystemInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CTRL_PM_AREA_PC_SAMPLER +RpcCtrlPmAreaPcSampler rpcCtrlPmAreaPcSampler_v21_0B; +RpcCtrlPmAreaPcSampler rpcCtrlPmAreaPcSampler_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_DBG_SET_EXCEPTION_MASK +RpcCtrlDbgSetExceptionMask rpcCtrlDbgSetExceptionMask_v1A_0C; +RpcCtrlDbgSetExceptionMask rpcCtrlDbgSetExceptionMask_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_VASPACE_COPY_SERVER_RESERVED_PDES +RpcCtrlVaspaceCopyServerReservedPdes rpcCtrlVaspaceCopyServerReservedPdes_v1E_04; +RpcCtrlVaspaceCopyServerReservedPdes rpcCtrlVaspaceCopyServerReservedPdes_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v04_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_GR_CTXSW_PREEMPTION_BIND +RpcCtrlGrCtxswPreemptionBind rpcCtrlGrCtxswPreemptionBind_v1A_0E; +RpcCtrlGrCtxswPreemptionBind rpcCtrlGrCtxswPreemptionBind_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_ALLOC_PMA_STREAM +RpcCtrlAllocPmaStream rpcCtrlAllocPmaStream_v1A_14; +RpcCtrlAllocPmaStream rpcCtrlAllocPmaStream_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CTRL_RESERVE_HWPM_LEGACY +RpcCtrlReserveHwpmLegacy rpcCtrlReserveHwpmLegacy_v1A_0F; +RpcCtrlReserveHwpmLegacy rpcCtrlReserveHwpmLegacy_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_INTERNAL_QUIESCE_PMA_CHANNEL +RpcCtrlInternalQuiescePmaChannel rpcCtrlInternalQuiescePmaChannel_v1C_08; +RpcCtrlInternalQuiescePmaChannel rpcCtrlInternalQuiescePmaChannel_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_PERF_RATED_TDP_GET_STATUS +RpcCtrlPerfRatedTdpGetStatus rpcCtrlPerfRatedTdpGetStatus_v1A_1F; +RpcCtrlPerfRatedTdpGetStatus rpcCtrlPerfRatedTdpGetStatus_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v05_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_BUS_SET_P2P_MAPPING +RpcCtrlBusSetP2pMapping rpcCtrlBusSetP2pMapping_v21_03; +RpcCtrlBusSetP2pMapping rpcCtrlBusSetP2pMapping_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_GPU_GET_INFO_V2 +RpcCtrlGpuGetInfoV2 rpcCtrlGpuGetInfoV2_v25_11; +RpcCtrlGpuGetInfoV2 rpcCtrlGpuGetInfoV2_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CTRL_GET_HS_CREDITS +RpcCtrlGetHsCredits rpcCtrlGetHsCredits_v21_08; +RpcCtrlGetHsCredits rpcCtrlGetHsCredits_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_GR_SET_CTXSW_PREEMPTION_MODE +RpcCtrlGrSetCtxswPreemptionMode rpcCtrlGrSetCtxswPreemptionMode_v1A_0E; +RpcCtrlGrSetCtxswPreemptionMode rpcCtrlGrSetCtxswPreemptionMode_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_B0CC_EXEC_REG_OPS +RpcCtrlB0ccExecRegOps rpcCtrlB0ccExecRegOps_v1A_0F; +RpcCtrlB0ccExecRegOps rpcCtrlB0ccExecRegOps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v06_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_GRMGR_GET_GR_FS_INFO +RpcCtrlGrmgrGetGrFsInfo rpcCtrlGrmgrGetGrFsInfo_v1A_1D; +RpcCtrlGrmgrGetGrFsInfo rpcCtrlGrmgrGetGrFsInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_GET_ZBC_CLEAR_TABLE +RpcCtrlGetZbcClearTable rpcCtrlGetZbcClearTable_v1A_09; +RpcCtrlGetZbcClearTable rpcCtrlGetZbcClearTable_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CLEANUP_SURFACE +RpcCleanupSurface rpcCleanupSurface_v03_00; +RpcCleanupSurface rpcCleanupSurface_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_SET_TIMESLICE +RpcCtrlSetTimeslice rpcCtrlSetTimeslice_v1A_0A; +RpcCtrlSetTimeslice rpcCtrlSetTimeslice_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_GPU_QUERY_ECC_STATUS +RpcCtrlGpuQueryEccStatus rpcCtrlGpuQueryEccStatus_v24_06; +RpcCtrlGpuQueryEccStatus rpcCtrlGpuQueryEccStatus_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v07_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_DBG_GET_MODE_MMU_DEBUG +RpcCtrlDbgGetModeMmuDebug rpcCtrlDbgGetModeMmuDebug_v25_04; +RpcCtrlDbgGetModeMmuDebug rpcCtrlDbgGetModeMmuDebug_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES +RpcCtrlDbgClearAllSmErrorStates rpcCtrlDbgClearAllSmErrorStates_v1A_0C; +RpcCtrlDbgClearAllSmErrorStates rpcCtrlDbgClearAllSmErrorStates_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:VGPU_GSP_RING_DOORBELL +RpcVgpuGspRingDoorbell rpcVgpuGspRingDoorbell_GA102; // GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +RpcVgpuGspRingDoorbell rpcVgpuGspRingDoorbell_STUB; // TU10X, GA100 + // RPC:CTRL_GR_SET_TPC_PARTITION_MODE +RpcCtrlGrSetTpcPartitionMode rpcCtrlGrSetTpcPartitionMode_v1C_04; +RpcCtrlGrSetTpcPartitionMode rpcCtrlGrSetTpcPartitionMode_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_GET_TOTAL_HS_CREDITS +RpcCtrlGetTotalHsCredits rpcCtrlGetTotalHsCredits_v21_08; +RpcCtrlGetTotalHsCredits rpcCtrlGetTotalHsCredits_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v07_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS +RpcCtrlInternalPromoteFaultMethodBuffers rpcCtrlInternalPromoteFaultMethodBuffers_v1E_07; +RpcCtrlInternalPromoteFaultMethodBuffers rpcCtrlInternalPromoteFaultMethodBuffers_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_FB_GET_INFO_V2 +RpcCtrlFbGetInfoV2 rpcCtrlFbGetInfoV2_v25_0A; +RpcCtrlFbGetInfoV2 rpcCtrlFbGetInfoV2_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:VGPU_GSP_WRITE_SCRATCH_REGISTER +RpcVgpuGspWriteScratchRegister rpcVgpuGspWriteScratchRegister_GA102; // GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X +RpcVgpuGspWriteScratchRegister rpcVgpuGspWriteScratchRegister_STUB; // TU10X, GA100 + // RPC:SET_PAGE_DIRECTORY +RpcSetPageDirectory rpcSetPageDirectory_v1E_05; +RpcSetPageDirectory rpcSetPageDirectory_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_GET_P2P_CAPS_V2 +RpcCtrlGetP2pCapsV2 rpcCtrlGetP2pCapsV2_v1F_0D; +RpcCtrlGetP2pCapsV2 rpcCtrlGetP2pCapsV2_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v08_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_NVLINK_GET_INBAND_RECEIVED_DATA +RpcCtrlNvlinkGetInbandReceivedData rpcCtrlNvlinkGetInbandReceivedData_v25_0C; +RpcCtrlNvlinkGetInbandReceivedData rpcCtrlNvlinkGetInbandReceivedData_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_GET_CE_PCE_MASK +RpcCtrlGetCePceMask rpcCtrlGetCePceMask_v1A_0E; +RpcCtrlGetCePceMask rpcCtrlGetCePceMask_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CTRL_GET_NVLINK_PEER_ID_MASK +RpcCtrlGetNvlinkPeerIdMask rpcCtrlGetNvlinkPeerIdMask_v1A_0E; +RpcCtrlGetNvlinkPeerIdMask rpcCtrlGetNvlinkPeerIdMask_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_GPU_EVICT_CTX +RpcCtrlGpuEvictCtx rpcCtrlGpuEvictCtx_v1A_1C; +RpcCtrlGpuEvictCtx rpcCtrlGpuEvictCtx_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_GET_MMU_DEBUG_MODE +RpcCtrlGetMmuDebugMode rpcCtrlGetMmuDebugMode_v1E_06; +RpcCtrlGetMmuDebugMode rpcCtrlGetMmuDebugMode_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v09_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:INVALIDATE_TLB +RpcInvalidateTlb rpcInvalidateTlb_v23_03; +RpcInvalidateTlb rpcInvalidateTlb_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP +RpcCtrlDbgSetSingleSmSingleStep rpcCtrlDbgSetSingleSmSingleStep_v1C_02; +RpcCtrlDbgSetSingleSmSingleStep rpcCtrlDbgSetSingleSmSingleStep_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:UNLOADING_GUEST_DRIVER +RpcUnloadingGuestDriver rpcUnloadingGuestDriver_v1F_07; +RpcUnloadingGuestDriver rpcUnloadingGuestDriver_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:GET_ENGINE_UTILIZATION_WRAPPER +RpcGetEngineUtilizationWrapper rpcGetEngineUtilizationWrapper_GM204; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:GET_CONSOLIDATED_GR_STATIC_INFO +RpcGetConsolidatedGrStaticInfo rpcGetConsolidatedGrStaticInfo_v1B_04; +RpcGetConsolidatedGrStaticInfo rpcGetConsolidatedGrStaticInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v09_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:SWITCH_TO_VGA +RpcSwitchToVga rpcSwitchToVga_v03_00; +RpcSwitchToVga rpcSwitchToVga_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_RESET_CHANNEL +RpcCtrlResetChannel rpcCtrlResetChannel_v1A_09; +RpcCtrlResetChannel rpcCtrlResetChannel_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CTRL_GPFIFO_SCHEDULE +RpcCtrlGpfifoSchedule rpcCtrlGpfifoSchedule_v1A_0A; +RpcCtrlGpfifoSchedule rpcCtrlGpfifoSchedule_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:SET_REGISTRY +RpcSetRegistry rpcSetRegistry_v17_00; +RpcSetRegistry rpcSetRegistry_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_GET_NVLINK_STATUS +RpcCtrlGetNvlinkStatus rpcCtrlGetNvlinkStatus_v23_04; +RpcCtrlGetNvlinkStatus rpcCtrlGetNvlinkStatus_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:GET_STATIC_DATA +RpcGetStaticData rpcGetStaticData_v25_0E; +RpcGetStaticData rpcGetStaticData_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_GR_GET_TPC_PARTITION_MODE +RpcCtrlGrGetTpcPartitionMode rpcCtrlGrGetTpcPartitionMode_v1C_04; +RpcCtrlGrGetTpcPartitionMode rpcCtrlGrGetTpcPartitionMode_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_STOP_CHANNEL +RpcCtrlStopChannel rpcCtrlStopChannel_v1A_1E; +RpcCtrlStopChannel rpcCtrlStopChannel_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:SET_SURFACE_PROPERTIES +RpcSetSurfaceProperties rpcSetSurfaceProperties_v07_07; +RpcSetSurfaceProperties rpcSetSurfaceProperties_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX +RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_v1F_0A; +RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_TIMER_SET_GR_TICK_FREQ +RpcCtrlTimerSetGrTickFreq rpcCtrlTimerSetGrTickFreq_v1A_1F; +RpcCtrlTimerSetGrTickFreq rpcCtrlTimerSetGrTickFreq_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:ALLOC_EVENT +RpcAllocEvent rpcAllocEvent_v03_00; +RpcAllocEvent rpcAllocEvent_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_GR_PC_SAMPLING_MODE +RpcCtrlGrPcSamplingMode rpcCtrlGrPcSamplingMode_v1A_1F; +RpcCtrlGrPcSamplingMode rpcCtrlGrPcSamplingMode_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_MC_SERVICE_INTERRUPTS +RpcCtrlMcServiceInterrupts rpcCtrlMcServiceInterrupts_v1A_0E; +RpcCtrlMcServiceInterrupts rpcCtrlMcServiceInterrupts_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_DBG_READ_ALL_SM_ERROR_STATES +RpcCtrlDbgReadAllSmErrorStates rpcCtrlDbgReadAllSmErrorStates_v21_06; +RpcCtrlDbgReadAllSmErrorStates rpcCtrlDbgReadAllSmErrorStates_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_SET_ZBC_COLOR_CLEAR +RpcCtrlSetZbcColorClear rpcCtrlSetZbcColorClear_v1A_09; +RpcCtrlSetZbcColorClear rpcCtrlSetZbcColorClear_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:GET_ENCODER_CAPACITY +RpcGetEncoderCapacity rpcGetEncoderCapacity_v07_00; +RpcGetEncoderCapacity rpcGetEncoderCapacity_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_GET_P2P_CAPS +RpcCtrlGetP2pCaps rpcCtrlGetP2pCaps_v1F_0D; +RpcCtrlGetP2pCaps rpcCtrlGetP2pCaps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:PERF_GET_LEVEL_INFO +RpcPerfGetLevelInfo rpcPerfGetLevelInfo_v03_00; +RpcPerfGetLevelInfo rpcPerfGetLevelInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:ALLOC_OBJECT +RpcAllocObject rpcAllocObject_v25_08; +RpcAllocObject rpcAllocObject_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_GPU_HANDLE_VF_PRI_FAULT +RpcCtrlGpuHandleVfPriFault rpcCtrlGpuHandleVfPriFault_v1A_09; +RpcCtrlGpuHandleVfPriFault rpcCtrlGpuHandleVfPriFault_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:RM_API_CONTROL +RpcRmApiControl rpcRmApiControl_v25_0D; +RpcRmApiControl rpcRmApiControl_v25_0F; +RpcRmApiControl rpcRmApiControl_v25_10; +RpcRmApiControl rpcRmApiControl_v25_14; +RpcRmApiControl rpcRmApiControl_v25_15; +RpcRmApiControl rpcRmApiControl_v25_16; +RpcRmApiControl rpcRmApiControl_v25_17; +RpcRmApiControl rpcRmApiControl_v25_18; +RpcRmApiControl rpcRmApiControl_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_FABRIC_MEM_STATS +RpcCtrlFabricMemStats rpcCtrlFabricMemStats_v1E_0C; +RpcCtrlFabricMemStats rpcCtrlFabricMemStats_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_GR_CTXSW_ZCULL_BIND +RpcCtrlGrCtxswZcullBind rpcCtrlGrCtxswZcullBind_v1A_0E; +RpcCtrlGrCtxswZcullBind rpcCtrlGrCtxswZcullBind_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED +RpcCtrlInternalMemsysSetZbcReferenced rpcCtrlInternalMemsysSetZbcReferenced_v1F_05; +RpcCtrlInternalMemsysSetZbcReferenced rpcCtrlInternalMemsysSetZbcReferenced_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_PERF_RATED_TDP_SET_CONTROL +RpcCtrlPerfRatedTdpSetControl rpcCtrlPerfRatedTdpSetControl_v1A_1F; +RpcCtrlPerfRatedTdpSetControl rpcCtrlPerfRatedTdpSetControl_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_EXEC_PARTITIONS_CREATE +RpcCtrlExecPartitionsCreate rpcCtrlExecPartitionsCreate_v24_05; +RpcCtrlExecPartitionsCreate rpcCtrlExecPartitionsCreate_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPC:CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN +RpcCtrlGpfifoGetWorkSubmitToken rpcCtrlGpfifoGetWorkSubmitToken_v1F_0A; +RpcCtrlGpfifoGetWorkSubmitToken rpcCtrlGpfifoGetWorkSubmitToken_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v09_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:IDLE_CHANNELS +RpcIdleChannels rpcIdleChannels_v03_00; +RpcIdleChannels rpcIdleChannels_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE +RpcCtrlCmdInternalGpuStartFabricProbe rpcCtrlCmdInternalGpuStartFabricProbe_v25_09; +RpcCtrlCmdInternalGpuStartFabricProbe rpcCtrlCmdInternalGpuStartFabricProbe_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:GET_BRAND_CAPS +RpcGetBrandCaps rpcGetBrandCaps_v25_12; +RpcGetBrandCaps rpcGetBrandCaps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:RESTORE_HIBERNATION_DATA +RpcRestoreHibernationData rpcRestoreHibernationData_v1E_0E; +RpcRestoreHibernationData rpcRestoreHibernationData_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK +RpcCtrlFlaSetupInstanceMemBlock rpcCtrlFlaSetupInstanceMemBlock_v21_05; +RpcCtrlFlaSetupInstanceMemBlock rpcCtrlFlaSetupInstanceMemBlock_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v12_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM +RpcCtrlInternalSriovPromotePmaStream rpcCtrlInternalSriovPromotePmaStream_v1C_0C; +RpcCtrlInternalSriovPromotePmaStream rpcCtrlInternalSriovPromotePmaStream_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_FB_GET_FS_INFO +RpcCtrlFbGetFsInfo rpcCtrlFbGetFsInfo_v24_00; +RpcCtrlFbGetFsInfo rpcCtrlFbGetFsInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CTRL_SET_CHANNEL_INTERLEAVE_LEVEL +RpcCtrlSetChannelInterleaveLevel rpcCtrlSetChannelInterleaveLevel_v1A_0A; +RpcCtrlSetChannelInterleaveLevel rpcCtrlSetChannelInterleaveLevel_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_DBG_RESUME_CONTEXT +RpcCtrlDbgResumeContext rpcCtrlDbgResumeContext_v1A_10; +RpcCtrlDbgResumeContext rpcCtrlDbgResumeContext_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:ALLOC_ROOT +RpcAllocRoot rpcAllocRoot_v07_00; +RpcAllocRoot rpcAllocRoot_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v13_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_FIFO_DISABLE_CHANNELS +RpcCtrlFifoDisableChannels rpcCtrlFifoDisableChannels_v1A_0A; +RpcCtrlFifoDisableChannels rpcCtrlFifoDisableChannels_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_SET_HS_CREDITS +RpcCtrlSetHsCredits rpcCtrlSetHsCredits_v21_08; +RpcCtrlSetHsCredits rpcCtrlSetHsCredits_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:GET_ENGINE_UTILIZATION +RpcGetEngineUtilization rpcGetEngineUtilization_v1F_0E; +RpcGetEngineUtilization rpcGetEngineUtilization_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_GET_ZBC_CLEAR_TABLE_ENTRY +RpcCtrlGetZbcClearTableEntry rpcCtrlGetZbcClearTableEntry_v1A_0E; +RpcCtrlGetZbcClearTableEntry rpcCtrlGetZbcClearTableEntry_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_NVENC_SW_SESSION_UPDATE_INFO +RpcCtrlNvencSwSessionUpdateInfo rpcCtrlNvencSwSessionUpdateInfo_v1A_09; +RpcCtrlNvencSwSessionUpdateInfo rpcCtrlNvencSwSessionUpdateInfo_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v14_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_DBG_SUSPEND_CONTEXT +RpcCtrlDbgSuspendContext rpcCtrlDbgSuspendContext_v1A_10; +RpcCtrlDbgSuspendContext rpcCtrlDbgSuspendContext_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_GET_P2P_CAPS_MATRIX +RpcCtrlGetP2pCapsMatrix rpcCtrlGetP2pCapsMatrix_v1A_0E; +RpcCtrlGetP2pCapsMatrix rpcCtrlGetP2pCapsMatrix_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CTRL_DBG_EXEC_REG_OPS +RpcCtrlDbgExecRegOps rpcCtrlDbgExecRegOps_v1A_10; +RpcCtrlDbgExecRegOps rpcCtrlDbgExecRegOps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_FREE_PMA_STREAM +RpcCtrlFreePmaStream rpcCtrlFreePmaStream_v1A_1F; +RpcCtrlFreePmaStream rpcCtrlFreePmaStream_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_SET_TSG_INTERLEAVE_LEVEL +RpcCtrlSetTsgInterleaveLevel rpcCtrlSetTsgInterleaveLevel_v1A_0A; +RpcCtrlSetTsgInterleaveLevel rpcCtrlSetTsgInterleaveLevel_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v14_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK +RpcCtrlMasterGetVirtualFunctionErrorContIntrMask rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_v1F_0D; +RpcCtrlMasterGetVirtualFunctionErrorContIntrMask rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:LOG +RpcLog rpcLog_v03_00; +RpcLog rpcLog_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:CTRL_EXEC_PARTITIONS_DELETE +RpcCtrlExecPartitionsDelete rpcCtrlExecPartitionsDelete_v1F_0A; +RpcCtrlExecPartitionsDelete rpcCtrlExecPartitionsDelete_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_PERF_BOOST +RpcCtrlPerfBoost rpcCtrlPerfBoost_v1A_09; +RpcCtrlPerfBoost rpcCtrlPerfBoost_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:CTRL_DBG_SET_MODE_MMU_DEBUG +RpcCtrlDbgSetModeMmuDebug rpcCtrlDbgSetModeMmuDebug_v1A_10; +RpcCtrlDbgSetModeMmuDebug rpcCtrlDbgSetModeMmuDebug_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v14_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:CTRL_FIFO_SET_CHANNEL_PROPERTIES +RpcCtrlFifoSetChannelProperties rpcCtrlFifoSetChannelProperties_v1A_16; +RpcCtrlFifoSetChannelProperties rpcCtrlFifoSetChannelProperties_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:CTRL_SUBDEVICE_GET_P2P_CAPS +RpcCtrlSubdeviceGetP2pCaps rpcCtrlSubdeviceGetP2pCaps_v21_02; +RpcCtrlSubdeviceGetP2pCaps rpcCtrlSubdeviceGetP2pCaps_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; + // RPC:UPDATE_BAR_PDE +RpcUpdateBarPde rpcUpdateBarPde_v15_00; +RpcUpdateBarPde rpcUpdateBarPde_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + // RPC:CTRL_BIND_PM_RESOURCES +RpcCtrlBindPmResources rpcCtrlBindPmResources_v1A_0F; +RpcCtrlBindPmResources rpcCtrlBindPmResources_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -#endif // -} + // RPC:MAP_MEMORY_DMA +RpcMapMemoryDma rpcMapMemoryDma_v03_00; +RpcMapMemoryDma rpcMapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v15_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v15_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v17_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v17_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v17_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_10(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_11(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_12(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_13(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_14(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_15(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v18_16(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v19_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v19_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; - - -#endif // -} - -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 + // RPC:UNMAP_MEMORY_DMA +RpcUnmapMemoryDma rpcUnmapMemoryDma_v03_00; +RpcUnmapMemoryDma rpcUnmapMemoryDma_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; + // RPC:SET_GUEST_SYSTEM_INFO_EXT +RpcSetGuestSystemInfoExt rpcSetGuestSystemInfoExt_v15_02; +RpcSetGuestSystemInfoExt rpcSetGuestSystemInfoExt_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; -#endif // -} -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; +// +// RPC's object-level *non-static* interface functions (static ones are below) +// +RpcConstruct rpcConstruct_IMPL; +RpcDestroy rpcDestroy_IMPL; +RpcSendMessage rpcSendMessage_IMPL; +RpcRecvPoll rpcRecvPoll_IMPL; -#endif // -} -// No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) -{ -#if 0 +#if defined(RMCFG_ENGINE_SETUP) // for use by hal init only - POBJGPU pGpu = pInfo->pGpu; - OBJRPC *pRpc = (OBJRPC *) pInfo->pDynamic; - RPC_HAL_IFACES *pRpcHal = &pRpc->_hal; - // avoid possible unused warnings - pGpu += 0; - pRpcHal += 0; -#endif // -} // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v03_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -996,7 +578,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_05(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v04_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1013,7 +595,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_06(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v05_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1030,7 +612,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_07(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v06_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1047,7 +629,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_08(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v07_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1064,7 +646,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_09(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v07_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1081,7 +663,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v08_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1098,7 +680,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v09_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1115,7 +697,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v09_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1132,7 +714,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v12_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1149,7 +731,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v13_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1166,7 +748,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_10(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v14_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1183,7 +765,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_10(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_12(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v14_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1200,7 +782,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_12(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_13(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v14_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1217,7 +799,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_13(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_14(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v15_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1234,7 +816,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_14(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_15(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v15_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1251,7 +833,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_15(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_16(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v17_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1268,7 +850,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_16(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_17(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v18_12(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1285,7 +867,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_17(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_18(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1302,7 +884,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_18(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_1A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1319,7 +901,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_1A(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_1B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1336,7 +918,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_1B(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_1C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1353,7 +935,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_1C(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_1D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1370,7 +952,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_1D(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_1E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1387,7 +969,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_1E(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_1F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1404,7 +986,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_1F(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_20(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_10(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1421,7 +1003,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_20(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_21(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_14(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1438,7 +1020,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_21(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_22(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_16(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1455,7 +1037,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_22(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_23(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_1A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1472,7 +1054,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_23(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1A_24(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_1C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1489,7 +1071,7 @@ static void rpc_iGrp_ipVersions_Install_v1A_24(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1B_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_1D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1506,7 +1088,7 @@ static void rpc_iGrp_ipVersions_Install_v1B_02(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1B_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_1E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1523,7 +1105,7 @@ static void rpc_iGrp_ipVersions_Install_v1B_04(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_1F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1540,7 +1122,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_02(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_20(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1557,7 +1139,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_04(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1A_23(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1574,7 +1156,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_05(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1B_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1591,7 +1173,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_07(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1C_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1608,7 +1190,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_08(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1C_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1625,7 +1207,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_09(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1C_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1642,7 +1224,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1C_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1659,7 +1241,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1C_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1C_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1676,7 +1258,7 @@ static void rpc_iGrp_ipVersions_Install_v1C_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1D_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1C_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1693,7 +1275,7 @@ static void rpc_iGrp_ipVersions_Install_v1D_02(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1D_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1C_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1710,7 +1292,7 @@ static void rpc_iGrp_ipVersions_Install_v1D_05(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1D_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1D_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1727,7 +1309,7 @@ static void rpc_iGrp_ipVersions_Install_v1D_06(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1E_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1D_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1812,7 +1394,7 @@ static void rpc_iGrp_ipVersions_Install_v1E_07(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1E_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1E_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1829,7 +1411,7 @@ static void rpc_iGrp_ipVersions_Install_v1E_08(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1E_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1E_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1846,7 +1428,7 @@ static void rpc_iGrp_ipVersions_Install_v1E_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1E_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1E_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1863,7 +1445,7 @@ static void rpc_iGrp_ipVersions_Install_v1E_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1E_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1E_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1880,7 +1462,7 @@ static void rpc_iGrp_ipVersions_Install_v1E_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1E_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1F_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1897,7 +1479,7 @@ static void rpc_iGrp_ipVersions_Install_v1E_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1E_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1F_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1914,7 +1496,7 @@ static void rpc_iGrp_ipVersions_Install_v1E_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1F_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1931,7 +1513,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_00(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1F_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1948,7 +1530,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_03(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1F_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1965,7 +1547,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_04(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1F_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1982,7 +1564,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_05(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1F_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -1999,7 +1581,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_07(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v1F_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2016,7 +1598,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_08(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v20_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2033,7 +1615,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v21_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2050,7 +1632,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v21_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2067,7 +1649,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v21_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2084,7 +1666,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v21_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2101,7 +1683,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v1F_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v21_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2118,7 +1700,7 @@ static void rpc_iGrp_ipVersions_Install_v1F_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v20_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v21_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2135,7 +1717,7 @@ static void rpc_iGrp_ipVersions_Install_v20_00(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v20_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v21_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2152,7 +1734,7 @@ static void rpc_iGrp_ipVersions_Install_v20_01(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v20_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v23_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2169,7 +1751,7 @@ static void rpc_iGrp_ipVersions_Install_v20_02(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v20_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v23_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2186,7 +1768,7 @@ static void rpc_iGrp_ipVersions_Install_v20_03(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v23_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2203,7 +1785,7 @@ static void rpc_iGrp_ipVersions_Install_v21_02(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v24_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2220,7 +1802,7 @@ static void rpc_iGrp_ipVersions_Install_v21_03(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v24_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2237,7 +1819,7 @@ static void rpc_iGrp_ipVersions_Install_v21_04(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v24_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2254,7 +1836,7 @@ static void rpc_iGrp_ipVersions_Install_v21_05(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2271,7 +1853,7 @@ static void rpc_iGrp_ipVersions_Install_v21_06(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2288,7 +1870,7 @@ static void rpc_iGrp_ipVersions_Install_v21_07(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2305,7 +1887,7 @@ static void rpc_iGrp_ipVersions_Install_v21_08(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2322,7 +1904,7 @@ static void rpc_iGrp_ipVersions_Install_v21_09(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2339,7 +1921,7 @@ static void rpc_iGrp_ipVersions_Install_v21_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v21_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2356,7 +1938,7 @@ static void rpc_iGrp_ipVersions_Install_v21_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v22_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2373,7 +1955,7 @@ static void rpc_iGrp_ipVersions_Install_v22_01(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v23_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_0F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2390,7 +1972,7 @@ static void rpc_iGrp_ipVersions_Install_v23_02(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v23_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_10(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2407,7 +1989,7 @@ static void rpc_iGrp_ipVersions_Install_v23_03(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v23_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_11(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2424,7 +2006,7 @@ static void rpc_iGrp_ipVersions_Install_v23_04(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v23_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_12(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2441,7 +2023,7 @@ static void rpc_iGrp_ipVersions_Install_v23_05(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v24_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_14(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2458,7 +2040,7 @@ static void rpc_iGrp_ipVersions_Install_v24_00(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v24_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_15(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2475,7 +2057,7 @@ static void rpc_iGrp_ipVersions_Install_v24_01(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v24_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_16(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2492,7 +2074,7 @@ static void rpc_iGrp_ipVersions_Install_v24_05(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v24_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_17(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2509,7 +2091,7 @@ static void rpc_iGrp_ipVersions_Install_v24_06(IGRP_IP_VERSIONS_TABLE_INFO *pInf } // No enabled chips use this variant provider -static void rpc_iGrp_ipVersions_Install_v24_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +static void rpc_iGrp_ipVersions_Install_v25_18(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) { #if 0 @@ -2541,100 +2123,407 @@ static NV_STATUS rpc_iGrp_ipVersions_Wrapup(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) pRpcHal += 0; // fixup per-interface overrides? + if (IsIPVersionInRange(pRpc, 0x1A230000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFifoSetupVfZombieSubctxPdb = rpcCtrlFifoSetupVfZombieSubctxPdb_v1A_23; if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF)) pRpcHal->rpcVgpuPfRegRead32 = rpcVgpuPfRegRead32_v15_00; + if (IsIPVersionInRange(pRpc, 0x21030000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlBusUnsetP2pMapping = rpcCtrlBusUnsetP2pMapping_v21_03; if (IsIPVersionInRange(pRpc, 0x18120000, 0xFFFFFFFF)) pRpcHal->rpcDumpProtobufComponent = rpcDumpProtobufComponent_v18_12; if (IsIPVersionInRange(pRpc, 0x23050000, 0xFFFFFFFF)) pRpcHal->rpcEccNotifierWriteAck = rpcEccNotifierWriteAck_v23_05; if (IsIPVersionInRange(pRpc, 0x13010000, 0xFFFFFFFF)) pRpcHal->rpcAllocMemory = rpcAllocMemory_v13_01; + if (IsIPVersionInRange(pRpc, 0x21060000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgReadSingleSmErrorState = rpcCtrlDbgReadSingleSmErrorState_v21_06; + if (IsIPVersionInRange(pRpc, 0x1E0B0000, 0xFFFFFFFF)) + pRpcHal->rpcDisableChannels = rpcDisableChannels_v1E_0B; if (IsIPVersionInRange(pRpc, 0x12010000, 0xFFFFFFFF)) pRpcHal->rpcGpuExecRegOps = rpcGpuExecRegOps_v12_01; - if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF)) - pRpcHal->rpcRmfsInit = rpcRmfsInit_v15_00; - if (IsIPVersionInRange(pRpc, 0x03000000, 0x1E04FFFF)) - pRpcHal->rpcUnsetPageDirectory = rpcUnsetPageDirectory_v03_00; + if (IsIPVersionInRange(pRpc, 0x1A200000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpuPromoteCtx = rpcCtrlGpuPromoteCtx_v1A_20; + if (IsIPVersionInRange(pRpc, 0x1A100000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgSetNextStopTriggerType = rpcCtrlDbgSetNextStopTriggerType_v1A_10; + if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) + pRpcHal->rpcAllocShareDevice = rpcAllocShareDevice_v03_00; + if (IsIPVersionInRange(pRpc, 0x1A0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlPreempt = rpcCtrlPreempt_v1A_0A; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpuInitializeCtx = rpcCtrlGpuInitializeCtx_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x1A0F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlReservePmAreaSmpc = rpcCtrlReservePmAreaSmpc_v1A_0F; + if (IsIPVersionInRange(pRpc, 0x21070000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpuMigratableOps = rpcCtrlGpuMigratableOps_v21_07; + if (IsIPVersionInRange(pRpc, 0x1A100000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgSetModeErrbarDebug = rpcCtrlDbgSetModeErrbarDebug_v1A_10; + if (IsIPVersionInRange(pRpc, 0x1A140000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlPmaStreamUpdateGetPut = rpcCtrlPmaStreamUpdateGetPut_v1A_14; + if (IsIPVersionInRange(pRpc, 0x1E0C0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFabricMemoryDescribe = rpcCtrlFabricMemoryDescribe_v1E_0C; + if (IsIPVersionInRange(pRpc, 0x1F040000, 0xFFFFFFFF)) + pRpcHal->rpcAllocChannelDma = rpcAllocChannelDma_v1F_04; + if (IsIPVersionInRange(pRpc, 0x1A090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlSetZbcDepthClear = rpcCtrlSetZbcDepthClear_v1A_09; + if (IsIPVersionInRange(pRpc, 0x1A090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlResetIsolatedChannel = rpcCtrlResetIsolatedChannel_v1A_09; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDmaSetDefaultVaspace = rpcCtrlDmaSetDefaultVaspace_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x08010000, 0xFFFFFFFF)) + pRpcHal->rpcAllocSubdevice = rpcAllocSubdevice_v08_01; + if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) + pRpcHal->rpcFree = rpcFree_v03_00; + if (IsIPVersionInRange(pRpc, 0x24050000, 0xFFFFFFFF)) + pRpcHal->rpcDmaControl = rpcDmaControl_v24_05; + if (IsIPVersionInRange(pRpc, 0x1A100000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgClearSingleSmErrorState = rpcCtrlDbgClearSingleSmErrorState_v1A_10; if (IsIPVersionInRange(pRpc, 0x1E050000, 0xFFFFFFFF)) pRpcHal->rpcUnsetPageDirectory = rpcUnsetPageDirectory_v1E_05; if (IsIPVersionInRange(pRpc, 0x14000000, 0xFFFFFFFF)) pRpcHal->rpcGetGspStaticInfo = rpcGetGspStaticInfo_v14_00; + if (IsIPVersionInRange(pRpc, 0x1E0E0000, 0xFFFFFFFF)) + pRpcHal->rpcSaveHibernationData = rpcSaveHibernationData_v1E_0E; + if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) + pRpcHal->rpcDupObject = rpcDupObject_v03_00; if (IsIPVersionInRange(pRpc, 0x17000000, 0xFFFFFFFF)) pRpcHal->rpcGspSetSystemInfo = rpcGspSetSystemInfo_v17_00; - if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF)) - pRpcHal->rpcRmfsCleanup = rpcRmfsCleanup_v15_00; - if (IsIPVersionInRange(pRpc, 0x03000000, 0x1E04FFFF)) - pRpcHal->rpcSetPageDirectory = rpcSetPageDirectory_v03_00; + if (IsIPVersionInRange(pRpc, 0x210B0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlPmAreaPcSampler = rpcCtrlPmAreaPcSampler_v21_0B; + if (IsIPVersionInRange(pRpc, 0x1A0C0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgSetExceptionMask = rpcCtrlDbgSetExceptionMask_v1A_0C; + if (IsIPVersionInRange(pRpc, 0x1E040000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlVaspaceCopyServerReservedPdes = rpcCtrlVaspaceCopyServerReservedPdes_v1E_04; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGrCtxswPreemptionBind = rpcCtrlGrCtxswPreemptionBind_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x1A140000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlAllocPmaStream = rpcCtrlAllocPmaStream_v1A_14; + if (IsIPVersionInRange(pRpc, 0x1A0F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlReserveHwpmLegacy = rpcCtrlReserveHwpmLegacy_v1A_0F; + if (IsIPVersionInRange(pRpc, 0x1C080000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlInternalQuiescePmaChannel = rpcCtrlInternalQuiescePmaChannel_v1C_08; + if (IsIPVersionInRange(pRpc, 0x1A1F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlPerfRatedTdpGetStatus = rpcCtrlPerfRatedTdpGetStatus_v1A_1F; + if (IsIPVersionInRange(pRpc, 0x21030000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlBusSetP2pMapping = rpcCtrlBusSetP2pMapping_v21_03; + if (IsIPVersionInRange(pRpc, 0x25110000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpuGetInfoV2 = rpcCtrlGpuGetInfoV2_v25_11; + if (IsIPVersionInRange(pRpc, 0x21080000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetHsCredits = rpcCtrlGetHsCredits_v21_08; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGrSetCtxswPreemptionMode = rpcCtrlGrSetCtxswPreemptionMode_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x1A0F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlB0ccExecRegOps = rpcCtrlB0ccExecRegOps_v1A_0F; + if (IsIPVersionInRange(pRpc, 0x1A1D0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGrmgrGetGrFsInfo = rpcCtrlGrmgrGetGrFsInfo_v1A_1D; + if (IsIPVersionInRange(pRpc, 0x1A090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetZbcClearTable = rpcCtrlGetZbcClearTable_v1A_09; + if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) + pRpcHal->rpcCleanupSurface = rpcCleanupSurface_v03_00; + if (IsIPVersionInRange(pRpc, 0x1A0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlSetTimeslice = rpcCtrlSetTimeslice_v1A_0A; + if (IsIPVersionInRange(pRpc, 0x24060000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpuQueryEccStatus = rpcCtrlGpuQueryEccStatus_v24_06; + if (IsIPVersionInRange(pRpc, 0x25040000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgGetModeMmuDebug = rpcCtrlDbgGetModeMmuDebug_v25_04; + if (IsIPVersionInRange(pRpc, 0x1A0C0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgClearAllSmErrorStates = rpcCtrlDbgClearAllSmErrorStates_v1A_0C; + if (IsIPVersionInRange(pRpc, 0x1C040000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGrSetTpcPartitionMode = rpcCtrlGrSetTpcPartitionMode_v1C_04; + if (IsIPVersionInRange(pRpc, 0x21080000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetTotalHsCredits = rpcCtrlGetTotalHsCredits_v21_08; + if (IsIPVersionInRange(pRpc, 0x1E070000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlInternalPromoteFaultMethodBuffers = rpcCtrlInternalPromoteFaultMethodBuffers_v1E_07; + if (IsIPVersionInRange(pRpc, 0x250A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFbGetInfoV2 = rpcCtrlFbGetInfoV2_v25_0A; if (IsIPVersionInRange(pRpc, 0x1E050000, 0xFFFFFFFF)) pRpcHal->rpcSetPageDirectory = rpcSetPageDirectory_v1E_05; - if (IsIPVersionInRange(pRpc, 0x03000000, 0x1F06FFFF)) - pRpcHal->rpcUnloadingGuestDriver = rpcUnloadingGuestDriver_v03_00; + if (IsIPVersionInRange(pRpc, 0x1F0D0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetP2pCapsV2 = rpcCtrlGetP2pCapsV2_v1F_0D; + if (IsIPVersionInRange(pRpc, 0x250C0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlNvlinkGetInbandReceivedData = rpcCtrlNvlinkGetInbandReceivedData_v25_0C; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetCePceMask = rpcCtrlGetCePceMask_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetNvlinkPeerIdMask = rpcCtrlGetNvlinkPeerIdMask_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x1A1C0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpuEvictCtx = rpcCtrlGpuEvictCtx_v1A_1C; + if (IsIPVersionInRange(pRpc, 0x1E060000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetMmuDebugMode = rpcCtrlGetMmuDebugMode_v1E_06; + if (IsIPVersionInRange(pRpc, 0x23030000, 0xFFFFFFFF)) + pRpcHal->rpcInvalidateTlb = rpcInvalidateTlb_v23_03; + if (IsIPVersionInRange(pRpc, 0x1C020000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgSetSingleSmSingleStep = rpcCtrlDbgSetSingleSmSingleStep_v1C_02; if (IsIPVersionInRange(pRpc, 0x1F070000, 0xFFFFFFFF)) pRpcHal->rpcUnloadingGuestDriver = rpcUnloadingGuestDriver_v1F_07; + if (IsIPVersionInRange(pRpc, 0x1B040000, 0xFFFFFFFF)) + pRpcHal->rpcGetConsolidatedGrStaticInfo = rpcGetConsolidatedGrStaticInfo_v1B_04; + if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) + pRpcHal->rpcSwitchToVga = rpcSwitchToVga_v03_00; + if (IsIPVersionInRange(pRpc, 0x1A090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlResetChannel = rpcCtrlResetChannel_v1A_09; + if (IsIPVersionInRange(pRpc, 0x1A0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpfifoSchedule = rpcCtrlGpfifoSchedule_v1A_0A; if (IsIPVersionInRange(pRpc, 0x17000000, 0xFFFFFFFF)) pRpcHal->rpcSetRegistry = rpcSetRegistry_v17_00; - if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF)) - pRpcHal->rpcRmfsCloseQueue = rpcRmfsCloseQueue_v15_00; - if (IsIPVersionInRange(pRpc, 0x17050000, 0x1802FFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v17_05; - if (IsIPVersionInRange(pRpc, 0x18030000, 0x1803FFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_03; - if (IsIPVersionInRange(pRpc, 0x18040000, 0x180DFFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_04; - if (IsIPVersionInRange(pRpc, 0x180E0000, 0x180FFFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_0E; - if (IsIPVersionInRange(pRpc, 0x18100000, 0x1810FFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_10; - if (IsIPVersionInRange(pRpc, 0x18110000, 0x1812FFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_11; - if (IsIPVersionInRange(pRpc, 0x18130000, 0x1815FFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_13; - if (IsIPVersionInRange(pRpc, 0x18160000, 0x18FFFFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v18_16; - if (IsIPVersionInRange(pRpc, 0x19000000, 0x19FFFFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v19_00; - if (IsIPVersionInRange(pRpc, 0x1A000000, 0x1A04FFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v1A_00; - if (IsIPVersionInRange(pRpc, 0x1A050000, 0x2000FFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v1A_05; - if (IsIPVersionInRange(pRpc, 0x20010000, 0xFFFFFFFF)) - pRpcHal->rpcGetStaticInfo = rpcGetStaticInfo_v20_01; + if (IsIPVersionInRange(pRpc, 0x23040000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetNvlinkStatus = rpcCtrlGetNvlinkStatus_v23_04; + if (IsIPVersionInRange(pRpc, 0x250E0000, 0xFFFFFFFF)) + pRpcHal->rpcGetStaticData = rpcGetStaticData_v25_0E; + if (IsIPVersionInRange(pRpc, 0x1C040000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGrGetTpcPartitionMode = rpcCtrlGrGetTpcPartitionMode_v1C_04; + if (IsIPVersionInRange(pRpc, 0x1A1E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlStopChannel = rpcCtrlStopChannel_v1A_1E; + if (IsIPVersionInRange(pRpc, 0x07070000, 0xFFFFFFFF)) + pRpcHal->rpcSetSurfaceProperties = rpcSetSurfaceProperties_v07_07; + if (IsIPVersionInRange(pRpc, 0x1F0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex = rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_v1F_0A; + if (IsIPVersionInRange(pRpc, 0x1A1F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlTimerSetGrTickFreq = rpcCtrlTimerSetGrTickFreq_v1A_1F; + if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) + pRpcHal->rpcAllocEvent = rpcAllocEvent_v03_00; + if (IsIPVersionInRange(pRpc, 0x1A1F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGrPcSamplingMode = rpcCtrlGrPcSamplingMode_v1A_1F; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlMcServiceInterrupts = rpcCtrlMcServiceInterrupts_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x21060000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgReadAllSmErrorStates = rpcCtrlDbgReadAllSmErrorStates_v21_06; + if (IsIPVersionInRange(pRpc, 0x1A090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlSetZbcColorClear = rpcCtrlSetZbcColorClear_v1A_09; + if (IsIPVersionInRange(pRpc, 0x07000000, 0xFFFFFFFF)) + pRpcHal->rpcGetEncoderCapacity = rpcGetEncoderCapacity_v07_00; + if (IsIPVersionInRange(pRpc, 0x1F0D0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetP2pCaps = rpcCtrlGetP2pCaps_v1F_0D; + if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) + pRpcHal->rpcPerfGetLevelInfo = rpcPerfGetLevelInfo_v03_00; + if (IsIPVersionInRange(pRpc, 0x25080000, 0xFFFFFFFF)) + pRpcHal->rpcAllocObject = rpcAllocObject_v25_08; + if (IsIPVersionInRange(pRpc, 0x1A090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpuHandleVfPriFault = rpcCtrlGpuHandleVfPriFault_v1A_09; + if (IsIPVersionInRange(pRpc, 0x250D0000, 0x250EFFFF)) + pRpcHal->rpcRmApiControl = rpcRmApiControl_v25_0D; + if (IsIPVersionInRange(pRpc, 0x250F0000, 0x250FFFFF)) + pRpcHal->rpcRmApiControl = rpcRmApiControl_v25_0F; + if (IsIPVersionInRange(pRpc, 0x25100000, 0x2513FFFF)) + pRpcHal->rpcRmApiControl = rpcRmApiControl_v25_10; + if (IsIPVersionInRange(pRpc, 0x25140000, 0x2514FFFF)) + pRpcHal->rpcRmApiControl = rpcRmApiControl_v25_14; + if (IsIPVersionInRange(pRpc, 0x25150000, 0x2515FFFF)) + pRpcHal->rpcRmApiControl = rpcRmApiControl_v25_15; + if (IsIPVersionInRange(pRpc, 0x25160000, 0x2516FFFF)) + pRpcHal->rpcRmApiControl = rpcRmApiControl_v25_16; + if (IsIPVersionInRange(pRpc, 0x25170000, 0x2517FFFF)) + pRpcHal->rpcRmApiControl = rpcRmApiControl_v25_17; + if (IsIPVersionInRange(pRpc, 0x25180000, 0xFFFFFFFF)) + pRpcHal->rpcRmApiControl = rpcRmApiControl_v25_18; + if (IsIPVersionInRange(pRpc, 0x1E0C0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFabricMemStats = rpcCtrlFabricMemStats_v1E_0C; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGrCtxswZcullBind = rpcCtrlGrCtxswZcullBind_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x1F050000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlInternalMemsysSetZbcReferenced = rpcCtrlInternalMemsysSetZbcReferenced_v1F_05; + if (IsIPVersionInRange(pRpc, 0x1A1F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlPerfRatedTdpSetControl = rpcCtrlPerfRatedTdpSetControl_v1A_1F; + if (IsIPVersionInRange(pRpc, 0x24050000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlExecPartitionsCreate = rpcCtrlExecPartitionsCreate_v24_05; + if (IsIPVersionInRange(pRpc, 0x1F0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGpfifoGetWorkSubmitToken = rpcCtrlGpfifoGetWorkSubmitToken_v1F_0A; if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) pRpcHal->rpcIdleChannels = rpcIdleChannels_v03_00; + if (IsIPVersionInRange(pRpc, 0x25090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlCmdInternalGpuStartFabricProbe = rpcCtrlCmdInternalGpuStartFabricProbe_v25_09; + if (IsIPVersionInRange(pRpc, 0x25120000, 0xFFFFFFFF)) + pRpcHal->rpcGetBrandCaps = rpcGetBrandCaps_v25_12; + if (IsIPVersionInRange(pRpc, 0x1E0E0000, 0xFFFFFFFF)) + pRpcHal->rpcRestoreHibernationData = rpcRestoreHibernationData_v1E_0E; + if (IsIPVersionInRange(pRpc, 0x21050000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFlaSetupInstanceMemBlock = rpcCtrlFlaSetupInstanceMemBlock_v21_05; + if (IsIPVersionInRange(pRpc, 0x1C0C0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlInternalSriovPromotePmaStream = rpcCtrlInternalSriovPromotePmaStream_v1C_0C; + if (IsIPVersionInRange(pRpc, 0x24000000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFbGetFsInfo = rpcCtrlFbGetFsInfo_v24_00; + if (IsIPVersionInRange(pRpc, 0x1A0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlSetChannelInterleaveLevel = rpcCtrlSetChannelInterleaveLevel_v1A_0A; + if (IsIPVersionInRange(pRpc, 0x1A100000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgResumeContext = rpcCtrlDbgResumeContext_v1A_10; + if (IsIPVersionInRange(pRpc, 0x07000000, 0xFFFFFFFF)) + pRpcHal->rpcAllocRoot = rpcAllocRoot_v07_00; + if (IsIPVersionInRange(pRpc, 0x1A0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFifoDisableChannels = rpcCtrlFifoDisableChannels_v1A_0A; + if (IsIPVersionInRange(pRpc, 0x21080000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlSetHsCredits = rpcCtrlSetHsCredits_v21_08; + if (IsIPVersionInRange(pRpc, 0x1F0E0000, 0xFFFFFFFF)) + pRpcHal->rpcGetEngineUtilization = rpcGetEngineUtilization_v1F_0E; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetZbcClearTableEntry = rpcCtrlGetZbcClearTableEntry_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x1A090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlNvencSwSessionUpdateInfo = rpcCtrlNvencSwSessionUpdateInfo_v1A_09; + if (IsIPVersionInRange(pRpc, 0x1A100000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgSuspendContext = rpcCtrlDbgSuspendContext_v1A_10; + if (IsIPVersionInRange(pRpc, 0x1A0E0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlGetP2pCapsMatrix = rpcCtrlGetP2pCapsMatrix_v1A_0E; + if (IsIPVersionInRange(pRpc, 0x1A100000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgExecRegOps = rpcCtrlDbgExecRegOps_v1A_10; + if (IsIPVersionInRange(pRpc, 0x1A1F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFreePmaStream = rpcCtrlFreePmaStream_v1A_1F; + if (IsIPVersionInRange(pRpc, 0x1A0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlSetTsgInterleaveLevel = rpcCtrlSetTsgInterleaveLevel_v1A_0A; + if (IsIPVersionInRange(pRpc, 0x1F0D0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlMasterGetVirtualFunctionErrorContIntrMask = rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_v1F_0D; + if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) + pRpcHal->rpcLog = rpcLog_v03_00; + if (IsIPVersionInRange(pRpc, 0x1F0A0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlExecPartitionsDelete = rpcCtrlExecPartitionsDelete_v1F_0A; + if (IsIPVersionInRange(pRpc, 0x1A090000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlPerfBoost = rpcCtrlPerfBoost_v1A_09; + if (IsIPVersionInRange(pRpc, 0x1A100000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlDbgSetModeMmuDebug = rpcCtrlDbgSetModeMmuDebug_v1A_10; + if (IsIPVersionInRange(pRpc, 0x1A160000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlFifoSetChannelProperties = rpcCtrlFifoSetChannelProperties_v1A_16; + if (IsIPVersionInRange(pRpc, 0x21020000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlSubdeviceGetP2pCaps = rpcCtrlSubdeviceGetP2pCaps_v21_02; if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF)) pRpcHal->rpcUpdateBarPde = rpcUpdateBarPde_v15_00; + if (IsIPVersionInRange(pRpc, 0x1A0F0000, 0xFFFFFFFF)) + pRpcHal->rpcCtrlBindPmResources = rpcCtrlBindPmResources_v1A_0F; if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) pRpcHal->rpcMapMemoryDma = rpcMapMemoryDma_v03_00; if (IsIPVersionInRange(pRpc, 0x03000000, 0xFFFFFFFF)) pRpcHal->rpcUnmapMemoryDma = rpcUnmapMemoryDma_v03_00; - if (IsIPVersionInRange(pRpc, 0x15000000, 0xFFFFFFFF)) - pRpcHal->rpcRmfsTest = rpcRmfsTest_v15_00; + if (IsIPVersionInRange(pRpc, 0x15020000, 0xFFFFFFFF)) + pRpcHal->rpcSetGuestSystemInfoExt = rpcSetGuestSystemInfoExt_v15_02; // Verify each 'dynamically set' interface was actually set #define _RPC_HAL_VERIFY_INTERFACE(_pHalFn) \ NV_ASSERT_OR_RETURN_PRECOMP(_pHalFn != (void *) iGrp_ipVersions_UNASSIGNED, NV_ERR_NOT_SUPPORTED) + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFifoSetupVfZombieSubctxPdb); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcVgpuPfRegRead32); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlBusUnsetP2pMapping); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcDumpProtobufComponent); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcEccNotifierWriteAck); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocMemory); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgReadSingleSmErrorState); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcDisableChannels); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGpuExecRegOps); - _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsInit); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpuPromoteCtx); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgSetNextStopTriggerType); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocShareDevice); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlPreempt); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpuInitializeCtx); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlReservePmAreaSmpc); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpuMigratableOps); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgSetModeErrbarDebug); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlPmaStreamUpdateGetPut); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFabricMemoryDescribe); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocChannelDma); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlSetZbcDepthClear); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlResetIsolatedChannel); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDmaSetDefaultVaspace); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocSubdevice); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcFree); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcDmaControl); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgClearSingleSmErrorState); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcUnsetPageDirectory); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetGspStaticInfo); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcSaveHibernationData); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcDupObject); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGspSetSystemInfo); - _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsCleanup); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlPmAreaPcSampler); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgSetExceptionMask); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlVaspaceCopyServerReservedPdes); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGrCtxswPreemptionBind); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlAllocPmaStream); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlReserveHwpmLegacy); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlInternalQuiescePmaChannel); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlPerfRatedTdpGetStatus); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlBusSetP2pMapping); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpuGetInfoV2); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetHsCredits); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGrSetCtxswPreemptionMode); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlB0ccExecRegOps); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGrmgrGetGrFsInfo); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetZbcClearTable); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCleanupSurface); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlSetTimeslice); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpuQueryEccStatus); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgGetModeMmuDebug); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgClearAllSmErrorStates); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGrSetTpcPartitionMode); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetTotalHsCredits); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlInternalPromoteFaultMethodBuffers); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFbGetInfoV2); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcSetPageDirectory); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetP2pCapsV2); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlNvlinkGetInbandReceivedData); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetCePceMask); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetNvlinkPeerIdMask); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpuEvictCtx); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetMmuDebugMode); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcInvalidateTlb); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgSetSingleSmSingleStep); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcUnloadingGuestDriver); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetConsolidatedGrStaticInfo); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcSwitchToVga); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlResetChannel); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpfifoSchedule); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcSetRegistry); - _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsCloseQueue); - _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetStaticInfo); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetNvlinkStatus); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetStaticData); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGrGetTpcPartitionMode); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlStopChannel); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcSetSurfaceProperties); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlTimerSetGrTickFreq); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocEvent); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGrPcSamplingMode); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlMcServiceInterrupts); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgReadAllSmErrorStates); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlSetZbcColorClear); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetEncoderCapacity); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetP2pCaps); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcPerfGetLevelInfo); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocObject); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpuHandleVfPriFault); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmApiControl); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFabricMemStats); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGrCtxswZcullBind); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlInternalMemsysSetZbcReferenced); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlPerfRatedTdpSetControl); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlExecPartitionsCreate); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGpfifoGetWorkSubmitToken); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcIdleChannels); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlCmdInternalGpuStartFabricProbe); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetBrandCaps); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRestoreHibernationData); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFlaSetupInstanceMemBlock); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlInternalSriovPromotePmaStream); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFbGetFsInfo); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlSetChannelInterleaveLevel); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgResumeContext); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcAllocRoot); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFifoDisableChannels); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlSetHsCredits); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcGetEngineUtilization); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetZbcClearTableEntry); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlNvencSwSessionUpdateInfo); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgSuspendContext); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlGetP2pCapsMatrix); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgExecRegOps); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFreePmaStream); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlSetTsgInterleaveLevel); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlMasterGetVirtualFunctionErrorContIntrMask); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcLog); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlExecPartitionsDelete); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlPerfBoost); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlDbgSetModeMmuDebug); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlFifoSetChannelProperties); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlSubdeviceGetP2pCaps); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcUpdateBarPde); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcCtrlBindPmResources); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcMapMemoryDma); _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcUnmapMemoryDma); - _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcRmfsTest); + _RPC_HAL_VERIFY_INTERFACE(pRpcHal->rpcSetGuestSystemInfoExt); #undef _RPC_HAL_VERIFY_INTERFACE @@ -2671,9 +2560,6 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v09_0B[] = { { 0x090B0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v09_0C[] = { - { 0x090C0000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v12_01[] = { { 0x12010000, 0xFFFFFFFF, }, // }; @@ -2698,111 +2584,12 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v17_00[] = { { 0x17000000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v17_04[] = { - { 0x17040000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v17_05[] = { - { 0x17050000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_00[] = { - { 0x18000000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_01[] = { - { 0x18010000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_02[] = { - { 0x18020000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_03[] = { - { 0x18030000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_04[] = { - { 0x18040000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_05[] = { - { 0x18050000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_06[] = { - { 0x18060000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_07[] = { - { 0x18070000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_08[] = { - { 0x18080000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_09[] = { - { 0x18090000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_0A[] = { - { 0x180A0000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_0B[] = { - { 0x180B0000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_0C[] = { - { 0x180C0000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_0D[] = { - { 0x180D0000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_0E[] = { - { 0x180E0000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_0F[] = { - { 0x180F0000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_10[] = { - { 0x18100000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_11[] = { - { 0x18110000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_12[] = { { 0x18120000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_13[] = { - { 0x18130000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_14[] = { - { 0x18140000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_15[] = { - { 0x18150000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v18_16[] = { - { 0x18160000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v19_00[] = { - { 0x19000000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v19_01[] = { - { 0x19010000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_00[] = { - { 0x1A000000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_01[] = { - { 0x1A010000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_02[] = { - { 0x1A020000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_03[] = { - { 0x1A030000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_04[] = { - { 0x1A040000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_05[] = { { 0x1A050000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_06[] = { - { 0x1A060000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_07[] = { - { 0x1A070000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_08[] = { { 0x1A080000, 0xFFFFFFFF, }, // }; @@ -2812,15 +2599,9 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_0A[] = { { 0x1A0A0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_0B[] = { - { 0x1A0B0000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_0C[] = { { 0x1A0C0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_0D[] = { - { 0x1A0D0000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_0E[] = { { 0x1A0E0000, 0xFFFFFFFF, }, // }; @@ -2830,33 +2611,15 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_10[] = { { 0x1A100000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_12[] = { - { 0x1A120000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_13[] = { - { 0x1A130000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_14[] = { { 0x1A140000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_15[] = { - { 0x1A150000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_16[] = { { 0x1A160000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_17[] = { - { 0x1A170000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_18[] = { - { 0x1A180000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_1A[] = { { 0x1A1A0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_1B[] = { - { 0x1A1B0000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_1C[] = { { 0x1A1C0000, 0xFFFFFFFF, }, // }; @@ -2872,21 +2635,9 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_20[] = { { 0x1A200000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_21[] = { - { 0x1A210000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_22[] = { - { 0x1A220000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_23[] = { { 0x1A230000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1A_24[] = { - { 0x1A240000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1B_02[] = { - { 0x1B020000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1B_04[] = { { 0x1B040000, 0xFFFFFFFF, }, // }; @@ -2899,15 +2650,9 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1C_05[] = { { 0x1C050000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1C_07[] = { - { 0x1C070000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1C_08[] = { { 0x1C080000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1C_09[] = { - { 0x1C090000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1C_0A[] = { { 0x1C0A0000, 0xFFFFFFFF, }, // }; @@ -2917,18 +2662,12 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1C_0C[] = { { 0x1C0C0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1D_02[] = { - { 0x1D020000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1D_05[] = { { 0x1D050000, 0xFFFFFFFF, }, // }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1D_06[] = { { 0x1D060000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1E_01[] = { - { 0x1E010000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1E_04[] = { { 0x1E040000, 0xFFFFFFFF, }, // }; @@ -2941,9 +2680,6 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1E_07[] = { { 0x1E070000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1E_08[] = { - { 0x1E080000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1E_0A[] = { { 0x1E0A0000, 0xFFFFFFFF, }, // }; @@ -2953,18 +2689,9 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1E_0C[] = { { 0x1E0C0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1E_0D[] = { - { 0x1E0D0000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1E_0E[] = { { 0x1E0E0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_00[] = { - { 0x1F000000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_03[] = { - { 0x1F030000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_04[] = { { 0x1F040000, 0xFFFFFFFF, }, // }; @@ -2974,9 +2701,6 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_07[] = { { 0x1F070000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_08[] = { - { 0x1F080000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_0A[] = { { 0x1F0A0000, 0xFFFFFFFF, }, // }; @@ -2992,30 +2716,15 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_0E[] = { { 0x1F0E0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v1F_0F[] = { - { 0x1F0F0000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_00[] = { { 0x20000000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_01[] = { - { 0x20010000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_02[] = { - { 0x20020000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v20_03[] = { - { 0x20030000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_02[] = { { 0x21020000, 0xFFFFFFFF, }, // }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_03[] = { { 0x21030000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_04[] = { - { 0x21040000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_05[] = { { 0x21050000, 0xFFFFFFFF, }, // }; @@ -3028,21 +2737,9 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_08[] = { { 0x21080000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_09[] = { - { 0x21090000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_0A[] = { - { 0x210A0000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v21_0B[] = { { 0x210B0000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v22_01[] = { - { 0x22010000, 0xFFFFFFFF, }, // - }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_02[] = { - { 0x23020000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v23_03[] = { { 0x23030000, 0xFFFFFFFF, }, // }; @@ -3055,17 +2752,59 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_00[] = { { 0x24000000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_01[] = { - { 0x24010000, 0xFFFFFFFF, }, // - }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_05[] = { { 0x24050000, 0xFFFFFFFF, }, // }; static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_06[] = { { 0x24060000, 0xFFFFFFFF, }, // }; - static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v24_0A[] = { - { 0x240A0000, 0xFFFFFFFF, }, // + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_04[] = { + { 0x25040000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_08[] = { + { 0x25080000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_09[] = { + { 0x25090000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_0A[] = { + { 0x250A0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_0C[] = { + { 0x250C0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_0D[] = { + { 0x250D0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_0E[] = { + { 0x250E0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_0F[] = { + { 0x250F0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_10[] = { + { 0x25100000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_11[] = { + { 0x25110000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_12[] = { + { 0x25120000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_14[] = { + { 0x25140000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_15[] = { + { 0x25150000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_16[] = { + { 0x25160000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_17[] = { + { 0x25170000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPC_IGRP_IP_VERSIONS_RANGES_v25_18[] = { + { 0x25180000, 0xFFFFFFFF, }, // }; #define _RPC_HAL_IGRP_ENTRY_INIT(v) \ @@ -3081,7 +2820,6 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) _RPC_HAL_IGRP_ENTRY_INIT(v08_01), // _RPC_HAL_IGRP_ENTRY_INIT(v09_08), // _RPC_HAL_IGRP_ENTRY_INIT(v09_0B), // - _RPC_HAL_IGRP_ENTRY_INIT(v09_0C), // _RPC_HAL_IGRP_ENTRY_INIT(v12_01), // _RPC_HAL_IGRP_ENTRY_INIT(v13_01), // _RPC_HAL_IGRP_ENTRY_INIT(v14_00), // @@ -3090,129 +2828,80 @@ static NV_STATUS rpc_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) _RPC_HAL_IGRP_ENTRY_INIT(v15_00), // _RPC_HAL_IGRP_ENTRY_INIT(v15_02), // _RPC_HAL_IGRP_ENTRY_INIT(v17_00), // - _RPC_HAL_IGRP_ENTRY_INIT(v17_04), // - _RPC_HAL_IGRP_ENTRY_INIT(v17_05), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_00), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_01), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_02), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_03), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_04), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_05), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_06), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_07), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_08), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_09), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_0A), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_0B), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_0C), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_0D), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_0E), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_0F), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_10), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_11), // _RPC_HAL_IGRP_ENTRY_INIT(v18_12), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_13), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_14), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_15), // - _RPC_HAL_IGRP_ENTRY_INIT(v18_16), // - _RPC_HAL_IGRP_ENTRY_INIT(v19_00), // - _RPC_HAL_IGRP_ENTRY_INIT(v19_01), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_00), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_01), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_02), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_03), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_04), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_05), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_06), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_07), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_08), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_09), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_0A), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_0B), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_0C), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_0D), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_0E), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_0F), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_10), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_12), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_13), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_14), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_15), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_16), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_17), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_18), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_1A), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_1B), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_1C), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_1D), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_1E), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_1F), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_20), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_21), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_22), // _RPC_HAL_IGRP_ENTRY_INIT(v1A_23), // - _RPC_HAL_IGRP_ENTRY_INIT(v1A_24), // - _RPC_HAL_IGRP_ENTRY_INIT(v1B_02), // _RPC_HAL_IGRP_ENTRY_INIT(v1B_04), // _RPC_HAL_IGRP_ENTRY_INIT(v1C_02), // _RPC_HAL_IGRP_ENTRY_INIT(v1C_04), // _RPC_HAL_IGRP_ENTRY_INIT(v1C_05), // - _RPC_HAL_IGRP_ENTRY_INIT(v1C_07), // _RPC_HAL_IGRP_ENTRY_INIT(v1C_08), // - _RPC_HAL_IGRP_ENTRY_INIT(v1C_09), // _RPC_HAL_IGRP_ENTRY_INIT(v1C_0A), // _RPC_HAL_IGRP_ENTRY_INIT(v1C_0B), // _RPC_HAL_IGRP_ENTRY_INIT(v1C_0C), // - _RPC_HAL_IGRP_ENTRY_INIT(v1D_02), // _RPC_HAL_IGRP_ENTRY_INIT(v1D_05), // _RPC_HAL_IGRP_ENTRY_INIT(v1D_06), // - _RPC_HAL_IGRP_ENTRY_INIT(v1E_01), // _RPC_HAL_IGRP_ENTRY_INIT(v1E_04), // _RPC_HAL_IGRP_ENTRY_INIT(v1E_05), // _RPC_HAL_IGRP_ENTRY_INIT(v1E_06), // _RPC_HAL_IGRP_ENTRY_INIT(v1E_07), // - _RPC_HAL_IGRP_ENTRY_INIT(v1E_08), // _RPC_HAL_IGRP_ENTRY_INIT(v1E_0A), // _RPC_HAL_IGRP_ENTRY_INIT(v1E_0B), // _RPC_HAL_IGRP_ENTRY_INIT(v1E_0C), // - _RPC_HAL_IGRP_ENTRY_INIT(v1E_0D), // _RPC_HAL_IGRP_ENTRY_INIT(v1E_0E), // - _RPC_HAL_IGRP_ENTRY_INIT(v1F_00), // - _RPC_HAL_IGRP_ENTRY_INIT(v1F_03), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_04), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_05), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_07), // - _RPC_HAL_IGRP_ENTRY_INIT(v1F_08), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_0A), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_0B), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_0C), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_0D), // _RPC_HAL_IGRP_ENTRY_INIT(v1F_0E), // - _RPC_HAL_IGRP_ENTRY_INIT(v1F_0F), // _RPC_HAL_IGRP_ENTRY_INIT(v20_00), // - _RPC_HAL_IGRP_ENTRY_INIT(v20_01), // - _RPC_HAL_IGRP_ENTRY_INIT(v20_02), // - _RPC_HAL_IGRP_ENTRY_INIT(v20_03), // _RPC_HAL_IGRP_ENTRY_INIT(v21_02), // _RPC_HAL_IGRP_ENTRY_INIT(v21_03), // - _RPC_HAL_IGRP_ENTRY_INIT(v21_04), // _RPC_HAL_IGRP_ENTRY_INIT(v21_05), // _RPC_HAL_IGRP_ENTRY_INIT(v21_06), // _RPC_HAL_IGRP_ENTRY_INIT(v21_07), // _RPC_HAL_IGRP_ENTRY_INIT(v21_08), // - _RPC_HAL_IGRP_ENTRY_INIT(v21_09), // - _RPC_HAL_IGRP_ENTRY_INIT(v21_0A), // _RPC_HAL_IGRP_ENTRY_INIT(v21_0B), // - _RPC_HAL_IGRP_ENTRY_INIT(v22_01), // - _RPC_HAL_IGRP_ENTRY_INIT(v23_02), // _RPC_HAL_IGRP_ENTRY_INIT(v23_03), // _RPC_HAL_IGRP_ENTRY_INIT(v23_04), // _RPC_HAL_IGRP_ENTRY_INIT(v23_05), // _RPC_HAL_IGRP_ENTRY_INIT(v24_00), // - _RPC_HAL_IGRP_ENTRY_INIT(v24_01), // _RPC_HAL_IGRP_ENTRY_INIT(v24_05), // _RPC_HAL_IGRP_ENTRY_INIT(v24_06), // - _RPC_HAL_IGRP_ENTRY_INIT(v24_0A), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_04), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_08), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_09), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_0A), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_0C), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_0D), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_0E), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_0F), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_10), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_11), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_12), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_14), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_15), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_16), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_17), // + _RPC_HAL_IGRP_ENTRY_INIT(v25_18), // }; #undef _RPC_HAL_IGRP_ENTRY_INIT @@ -3237,26 +2926,136 @@ static void rpcHalIfacesSetup_TU102(RPC_HAL_IFACES *pRpcHal) // TU102's RPC hal interface function pointer block static const RPC_HAL_IFACES rpcHalIfacesInitStruct_TU102 = { + rpcCtrlFifoSetupVfZombieSubctxPdb_STUB, // rpcCtrlFifoSetupVfZombieSubctxPdb rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 + rpcCtrlBusUnsetP2pMapping_STUB, // rpcCtrlBusUnsetP2pMapping rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent rpcEccNotifierWriteAck_STUB, // rpcEccNotifierWriteAck rpcAllocMemory_STUB, // rpcAllocMemory + rpcCtrlDbgReadSingleSmErrorState_STUB, // rpcCtrlDbgReadSingleSmErrorState + rpcDisableChannels_STUB, // rpcDisableChannels rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps - rpcRmfsInit_STUB, // rpcRmfsInit + rpcCtrlGpuPromoteCtx_STUB, // rpcCtrlGpuPromoteCtx + rpcCtrlDbgSetNextStopTriggerType_STUB, // rpcCtrlDbgSetNextStopTriggerType + rpcAllocShareDevice_STUB, // rpcAllocShareDevice + rpcCtrlPreempt_STUB, // rpcCtrlPreempt + rpcCtrlGpuInitializeCtx_STUB, // rpcCtrlGpuInitializeCtx + rpcCtrlReservePmAreaSmpc_STUB, // rpcCtrlReservePmAreaSmpc + rpcCtrlGpuMigratableOps_STUB, // rpcCtrlGpuMigratableOps + rpcCtrlDbgSetModeErrbarDebug_STUB, // rpcCtrlDbgSetModeErrbarDebug + rpcCtrlPmaStreamUpdateGetPut_STUB, // rpcCtrlPmaStreamUpdateGetPut + rpcCtrlFabricMemoryDescribe_STUB, // rpcCtrlFabricMemoryDescribe + rpcAllocChannelDma_STUB, // rpcAllocChannelDma + rpcCtrlSetZbcDepthClear_STUB, // rpcCtrlSetZbcDepthClear + rpcCtrlResetIsolatedChannel_STUB, // rpcCtrlResetIsolatedChannel + rpcCtrlDmaSetDefaultVaspace_STUB, // rpcCtrlDmaSetDefaultVaspace + rpcAllocSubdevice_STUB, // rpcAllocSubdevice + rpcFree_STUB, // rpcFree + rpcDmaControl_STUB, // rpcDmaControl + rpcCtrlDbgClearSingleSmErrorState_STUB, // rpcCtrlDbgClearSingleSmErrorState rpcUnsetPageDirectory_STUB, // rpcUnsetPageDirectory rpcGetGspStaticInfo_STUB, // rpcGetGspStaticInfo + rpcSaveHibernationData_STUB, // rpcSaveHibernationData + rpcDupObject_STUB, // rpcDupObject rpcGspSetSystemInfo_STUB, // rpcGspSetSystemInfo - rpcRmfsCleanup_STUB, // rpcRmfsCleanup + rpcCtrlPmAreaPcSampler_STUB, // rpcCtrlPmAreaPcSampler + rpcCtrlDbgSetExceptionMask_STUB, // rpcCtrlDbgSetExceptionMask + rpcCtrlVaspaceCopyServerReservedPdes_STUB, // rpcCtrlVaspaceCopyServerReservedPdes + rpcCtrlGrCtxswPreemptionBind_STUB, // rpcCtrlGrCtxswPreemptionBind + rpcCtrlAllocPmaStream_STUB, // rpcCtrlAllocPmaStream + rpcCtrlReserveHwpmLegacy_STUB, // rpcCtrlReserveHwpmLegacy + rpcCtrlInternalQuiescePmaChannel_STUB, // rpcCtrlInternalQuiescePmaChannel + rpcCtrlPerfRatedTdpGetStatus_STUB, // rpcCtrlPerfRatedTdpGetStatus + rpcCtrlBusSetP2pMapping_STUB, // rpcCtrlBusSetP2pMapping + rpcCtrlGpuGetInfoV2_STUB, // rpcCtrlGpuGetInfoV2 + rpcCtrlGetHsCredits_STUB, // rpcCtrlGetHsCredits + rpcCtrlGrSetCtxswPreemptionMode_STUB, // rpcCtrlGrSetCtxswPreemptionMode + rpcCtrlB0ccExecRegOps_STUB, // rpcCtrlB0ccExecRegOps + rpcCtrlGrmgrGetGrFsInfo_STUB, // rpcCtrlGrmgrGetGrFsInfo + rpcCtrlGetZbcClearTable_STUB, // rpcCtrlGetZbcClearTable + rpcCleanupSurface_STUB, // rpcCleanupSurface + rpcCtrlSetTimeslice_STUB, // rpcCtrlSetTimeslice + rpcCtrlGpuQueryEccStatus_STUB, // rpcCtrlGpuQueryEccStatus + rpcCtrlDbgGetModeMmuDebug_STUB, // rpcCtrlDbgGetModeMmuDebug + rpcCtrlDbgClearAllSmErrorStates_STUB, // rpcCtrlDbgClearAllSmErrorStates + rpcVgpuGspRingDoorbell_STUB, // rpcVgpuGspRingDoorbell + rpcCtrlGrSetTpcPartitionMode_STUB, // rpcCtrlGrSetTpcPartitionMode + rpcCtrlGetTotalHsCredits_STUB, // rpcCtrlGetTotalHsCredits + rpcCtrlInternalPromoteFaultMethodBuffers_STUB, // rpcCtrlInternalPromoteFaultMethodBuffers + rpcCtrlFbGetInfoV2_STUB, // rpcCtrlFbGetInfoV2 + rpcVgpuGspWriteScratchRegister_STUB, // rpcVgpuGspWriteScratchRegister rpcSetPageDirectory_STUB, // rpcSetPageDirectory + rpcCtrlGetP2pCapsV2_STUB, // rpcCtrlGetP2pCapsV2 + rpcCtrlNvlinkGetInbandReceivedData_STUB, // rpcCtrlNvlinkGetInbandReceivedData + rpcCtrlGetCePceMask_STUB, // rpcCtrlGetCePceMask + rpcCtrlGetNvlinkPeerIdMask_STUB, // rpcCtrlGetNvlinkPeerIdMask + rpcCtrlGpuEvictCtx_STUB, // rpcCtrlGpuEvictCtx + rpcCtrlGetMmuDebugMode_STUB, // rpcCtrlGetMmuDebugMode + rpcInvalidateTlb_STUB, // rpcInvalidateTlb + rpcCtrlDbgSetSingleSmSingleStep_STUB, // rpcCtrlDbgSetSingleSmSingleStep rpcUnloadingGuestDriver_STUB, // rpcUnloadingGuestDriver + rpcGetEngineUtilizationWrapper_GM204, // rpcGetEngineUtilizationWrapper + rpcGetConsolidatedGrStaticInfo_STUB, // rpcGetConsolidatedGrStaticInfo + rpcSwitchToVga_STUB, // rpcSwitchToVga + rpcCtrlResetChannel_STUB, // rpcCtrlResetChannel + rpcCtrlGpfifoSchedule_STUB, // rpcCtrlGpfifoSchedule rpcSetRegistry_STUB, // rpcSetRegistry - rpcRmfsCloseQueue_STUB, // rpcRmfsCloseQueue - rpcGetStaticInfo_STUB, // rpcGetStaticInfo + rpcCtrlGetNvlinkStatus_STUB, // rpcCtrlGetNvlinkStatus + rpcGetStaticData_STUB, // rpcGetStaticData + rpcCtrlGrGetTpcPartitionMode_STUB, // rpcCtrlGrGetTpcPartitionMode + rpcCtrlStopChannel_STUB, // rpcCtrlStopChannel + rpcSetSurfaceProperties_STUB, // rpcSetSurfaceProperties + rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_STUB, // rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex + rpcCtrlTimerSetGrTickFreq_STUB, // rpcCtrlTimerSetGrTickFreq + rpcAllocEvent_STUB, // rpcAllocEvent + rpcCtrlGrPcSamplingMode_STUB, // rpcCtrlGrPcSamplingMode + rpcCtrlMcServiceInterrupts_STUB, // rpcCtrlMcServiceInterrupts + rpcCtrlDbgReadAllSmErrorStates_STUB, // rpcCtrlDbgReadAllSmErrorStates + rpcCtrlSetZbcColorClear_STUB, // rpcCtrlSetZbcColorClear + rpcGetEncoderCapacity_STUB, // rpcGetEncoderCapacity + rpcCtrlGetP2pCaps_STUB, // rpcCtrlGetP2pCaps + rpcPerfGetLevelInfo_STUB, // rpcPerfGetLevelInfo + rpcAllocObject_STUB, // rpcAllocObject + rpcCtrlGpuHandleVfPriFault_STUB, // rpcCtrlGpuHandleVfPriFault + rpcRmApiControl_STUB, // rpcRmApiControl + rpcCtrlFabricMemStats_STUB, // rpcCtrlFabricMemStats + rpcCtrlGrCtxswZcullBind_STUB, // rpcCtrlGrCtxswZcullBind + rpcCtrlInternalMemsysSetZbcReferenced_STUB, // rpcCtrlInternalMemsysSetZbcReferenced + rpcCtrlPerfRatedTdpSetControl_STUB, // rpcCtrlPerfRatedTdpSetControl + rpcCtrlExecPartitionsCreate_STUB, // rpcCtrlExecPartitionsCreate + rpcCtrlGpfifoGetWorkSubmitToken_STUB, // rpcCtrlGpfifoGetWorkSubmitToken rpcIdleChannels_STUB, // rpcIdleChannels + rpcCtrlCmdInternalGpuStartFabricProbe_STUB, // rpcCtrlCmdInternalGpuStartFabricProbe + rpcGetBrandCaps_STUB, // rpcGetBrandCaps + rpcRestoreHibernationData_STUB, // rpcRestoreHibernationData + rpcCtrlFlaSetupInstanceMemBlock_STUB, // rpcCtrlFlaSetupInstanceMemBlock + rpcCtrlInternalSriovPromotePmaStream_STUB, // rpcCtrlInternalSriovPromotePmaStream + rpcCtrlFbGetFsInfo_STUB, // rpcCtrlFbGetFsInfo + rpcCtrlSetChannelInterleaveLevel_STUB, // rpcCtrlSetChannelInterleaveLevel + rpcCtrlDbgResumeContext_STUB, // rpcCtrlDbgResumeContext + rpcAllocRoot_STUB, // rpcAllocRoot + rpcCtrlFifoDisableChannels_STUB, // rpcCtrlFifoDisableChannels + rpcCtrlSetHsCredits_STUB, // rpcCtrlSetHsCredits + rpcGetEngineUtilization_STUB, // rpcGetEngineUtilization + rpcCtrlGetZbcClearTableEntry_STUB, // rpcCtrlGetZbcClearTableEntry + rpcCtrlNvencSwSessionUpdateInfo_STUB, // rpcCtrlNvencSwSessionUpdateInfo + rpcCtrlDbgSuspendContext_STUB, // rpcCtrlDbgSuspendContext + rpcCtrlGetP2pCapsMatrix_STUB, // rpcCtrlGetP2pCapsMatrix + rpcCtrlDbgExecRegOps_STUB, // rpcCtrlDbgExecRegOps + rpcCtrlFreePmaStream_STUB, // rpcCtrlFreePmaStream + rpcCtrlSetTsgInterleaveLevel_STUB, // rpcCtrlSetTsgInterleaveLevel + rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_STUB, // rpcCtrlMasterGetVirtualFunctionErrorContIntrMask + rpcLog_STUB, // rpcLog + rpcCtrlExecPartitionsDelete_STUB, // rpcCtrlExecPartitionsDelete + rpcCtrlPerfBoost_STUB, // rpcCtrlPerfBoost + rpcCtrlDbgSetModeMmuDebug_STUB, // rpcCtrlDbgSetModeMmuDebug + rpcCtrlFifoSetChannelProperties_STUB, // rpcCtrlFifoSetChannelProperties + rpcCtrlSubdeviceGetP2pCaps_STUB, // rpcCtrlSubdeviceGetP2pCaps rpcUpdateBarPde_STUB, // rpcUpdateBarPde + rpcCtrlBindPmResources_STUB, // rpcCtrlBindPmResources rpcMapMemoryDma_STUB, // rpcMapMemoryDma rpcUnmapMemoryDma_STUB, // rpcUnmapMemoryDma - rpcRmfsTest_STUB, // rpcRmfsTest + rpcSetGuestSystemInfoExt_STUB, // rpcSetGuestSystemInfoExt rpc_iGrp_ipVersions_getInfo, // rpc_iGrp_ipVersions_getInfo }; // rpcHalIfacesInitStruct_TU102 @@ -3311,26 +3110,136 @@ static void rpcHalIfacesSetup_GA100(RPC_HAL_IFACES *pRpcHal) // GA100's RPC hal interface function pointer block static const RPC_HAL_IFACES rpcHalIfacesInitStruct_GA100 = { + rpcCtrlFifoSetupVfZombieSubctxPdb_STUB, // rpcCtrlFifoSetupVfZombieSubctxPdb rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 + rpcCtrlBusUnsetP2pMapping_STUB, // rpcCtrlBusUnsetP2pMapping rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent rpcEccNotifierWriteAck_STUB, // rpcEccNotifierWriteAck rpcAllocMemory_STUB, // rpcAllocMemory + rpcCtrlDbgReadSingleSmErrorState_STUB, // rpcCtrlDbgReadSingleSmErrorState + rpcDisableChannels_STUB, // rpcDisableChannels rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps - rpcRmfsInit_STUB, // rpcRmfsInit + rpcCtrlGpuPromoteCtx_STUB, // rpcCtrlGpuPromoteCtx + rpcCtrlDbgSetNextStopTriggerType_STUB, // rpcCtrlDbgSetNextStopTriggerType + rpcAllocShareDevice_STUB, // rpcAllocShareDevice + rpcCtrlPreempt_STUB, // rpcCtrlPreempt + rpcCtrlGpuInitializeCtx_STUB, // rpcCtrlGpuInitializeCtx + rpcCtrlReservePmAreaSmpc_STUB, // rpcCtrlReservePmAreaSmpc + rpcCtrlGpuMigratableOps_STUB, // rpcCtrlGpuMigratableOps + rpcCtrlDbgSetModeErrbarDebug_STUB, // rpcCtrlDbgSetModeErrbarDebug + rpcCtrlPmaStreamUpdateGetPut_STUB, // rpcCtrlPmaStreamUpdateGetPut + rpcCtrlFabricMemoryDescribe_STUB, // rpcCtrlFabricMemoryDescribe + rpcAllocChannelDma_STUB, // rpcAllocChannelDma + rpcCtrlSetZbcDepthClear_STUB, // rpcCtrlSetZbcDepthClear + rpcCtrlResetIsolatedChannel_STUB, // rpcCtrlResetIsolatedChannel + rpcCtrlDmaSetDefaultVaspace_STUB, // rpcCtrlDmaSetDefaultVaspace + rpcAllocSubdevice_STUB, // rpcAllocSubdevice + rpcFree_STUB, // rpcFree + rpcDmaControl_STUB, // rpcDmaControl + rpcCtrlDbgClearSingleSmErrorState_STUB, // rpcCtrlDbgClearSingleSmErrorState rpcUnsetPageDirectory_STUB, // rpcUnsetPageDirectory rpcGetGspStaticInfo_STUB, // rpcGetGspStaticInfo + rpcSaveHibernationData_STUB, // rpcSaveHibernationData + rpcDupObject_STUB, // rpcDupObject rpcGspSetSystemInfo_STUB, // rpcGspSetSystemInfo - rpcRmfsCleanup_STUB, // rpcRmfsCleanup + rpcCtrlPmAreaPcSampler_STUB, // rpcCtrlPmAreaPcSampler + rpcCtrlDbgSetExceptionMask_STUB, // rpcCtrlDbgSetExceptionMask + rpcCtrlVaspaceCopyServerReservedPdes_STUB, // rpcCtrlVaspaceCopyServerReservedPdes + rpcCtrlGrCtxswPreemptionBind_STUB, // rpcCtrlGrCtxswPreemptionBind + rpcCtrlAllocPmaStream_STUB, // rpcCtrlAllocPmaStream + rpcCtrlReserveHwpmLegacy_STUB, // rpcCtrlReserveHwpmLegacy + rpcCtrlInternalQuiescePmaChannel_STUB, // rpcCtrlInternalQuiescePmaChannel + rpcCtrlPerfRatedTdpGetStatus_STUB, // rpcCtrlPerfRatedTdpGetStatus + rpcCtrlBusSetP2pMapping_STUB, // rpcCtrlBusSetP2pMapping + rpcCtrlGpuGetInfoV2_STUB, // rpcCtrlGpuGetInfoV2 + rpcCtrlGetHsCredits_STUB, // rpcCtrlGetHsCredits + rpcCtrlGrSetCtxswPreemptionMode_STUB, // rpcCtrlGrSetCtxswPreemptionMode + rpcCtrlB0ccExecRegOps_STUB, // rpcCtrlB0ccExecRegOps + rpcCtrlGrmgrGetGrFsInfo_STUB, // rpcCtrlGrmgrGetGrFsInfo + rpcCtrlGetZbcClearTable_STUB, // rpcCtrlGetZbcClearTable + rpcCleanupSurface_STUB, // rpcCleanupSurface + rpcCtrlSetTimeslice_STUB, // rpcCtrlSetTimeslice + rpcCtrlGpuQueryEccStatus_STUB, // rpcCtrlGpuQueryEccStatus + rpcCtrlDbgGetModeMmuDebug_STUB, // rpcCtrlDbgGetModeMmuDebug + rpcCtrlDbgClearAllSmErrorStates_STUB, // rpcCtrlDbgClearAllSmErrorStates + rpcVgpuGspRingDoorbell_STUB, // rpcVgpuGspRingDoorbell + rpcCtrlGrSetTpcPartitionMode_STUB, // rpcCtrlGrSetTpcPartitionMode + rpcCtrlGetTotalHsCredits_STUB, // rpcCtrlGetTotalHsCredits + rpcCtrlInternalPromoteFaultMethodBuffers_STUB, // rpcCtrlInternalPromoteFaultMethodBuffers + rpcCtrlFbGetInfoV2_STUB, // rpcCtrlFbGetInfoV2 + rpcVgpuGspWriteScratchRegister_STUB, // rpcVgpuGspWriteScratchRegister rpcSetPageDirectory_STUB, // rpcSetPageDirectory + rpcCtrlGetP2pCapsV2_STUB, // rpcCtrlGetP2pCapsV2 + rpcCtrlNvlinkGetInbandReceivedData_STUB, // rpcCtrlNvlinkGetInbandReceivedData + rpcCtrlGetCePceMask_STUB, // rpcCtrlGetCePceMask + rpcCtrlGetNvlinkPeerIdMask_STUB, // rpcCtrlGetNvlinkPeerIdMask + rpcCtrlGpuEvictCtx_STUB, // rpcCtrlGpuEvictCtx + rpcCtrlGetMmuDebugMode_STUB, // rpcCtrlGetMmuDebugMode + rpcInvalidateTlb_STUB, // rpcInvalidateTlb + rpcCtrlDbgSetSingleSmSingleStep_STUB, // rpcCtrlDbgSetSingleSmSingleStep rpcUnloadingGuestDriver_STUB, // rpcUnloadingGuestDriver + rpcGetEngineUtilizationWrapper_GM204, // rpcGetEngineUtilizationWrapper + rpcGetConsolidatedGrStaticInfo_STUB, // rpcGetConsolidatedGrStaticInfo + rpcSwitchToVga_STUB, // rpcSwitchToVga + rpcCtrlResetChannel_STUB, // rpcCtrlResetChannel + rpcCtrlGpfifoSchedule_STUB, // rpcCtrlGpfifoSchedule rpcSetRegistry_STUB, // rpcSetRegistry - rpcRmfsCloseQueue_STUB, // rpcRmfsCloseQueue - rpcGetStaticInfo_STUB, // rpcGetStaticInfo + rpcCtrlGetNvlinkStatus_STUB, // rpcCtrlGetNvlinkStatus + rpcGetStaticData_STUB, // rpcGetStaticData + rpcCtrlGrGetTpcPartitionMode_STUB, // rpcCtrlGrGetTpcPartitionMode + rpcCtrlStopChannel_STUB, // rpcCtrlStopChannel + rpcSetSurfaceProperties_STUB, // rpcSetSurfaceProperties + rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_STUB, // rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex + rpcCtrlTimerSetGrTickFreq_STUB, // rpcCtrlTimerSetGrTickFreq + rpcAllocEvent_STUB, // rpcAllocEvent + rpcCtrlGrPcSamplingMode_STUB, // rpcCtrlGrPcSamplingMode + rpcCtrlMcServiceInterrupts_STUB, // rpcCtrlMcServiceInterrupts + rpcCtrlDbgReadAllSmErrorStates_STUB, // rpcCtrlDbgReadAllSmErrorStates + rpcCtrlSetZbcColorClear_STUB, // rpcCtrlSetZbcColorClear + rpcGetEncoderCapacity_STUB, // rpcGetEncoderCapacity + rpcCtrlGetP2pCaps_STUB, // rpcCtrlGetP2pCaps + rpcPerfGetLevelInfo_STUB, // rpcPerfGetLevelInfo + rpcAllocObject_STUB, // rpcAllocObject + rpcCtrlGpuHandleVfPriFault_STUB, // rpcCtrlGpuHandleVfPriFault + rpcRmApiControl_STUB, // rpcRmApiControl + rpcCtrlFabricMemStats_STUB, // rpcCtrlFabricMemStats + rpcCtrlGrCtxswZcullBind_STUB, // rpcCtrlGrCtxswZcullBind + rpcCtrlInternalMemsysSetZbcReferenced_STUB, // rpcCtrlInternalMemsysSetZbcReferenced + rpcCtrlPerfRatedTdpSetControl_STUB, // rpcCtrlPerfRatedTdpSetControl + rpcCtrlExecPartitionsCreate_STUB, // rpcCtrlExecPartitionsCreate + rpcCtrlGpfifoGetWorkSubmitToken_STUB, // rpcCtrlGpfifoGetWorkSubmitToken rpcIdleChannels_STUB, // rpcIdleChannels + rpcCtrlCmdInternalGpuStartFabricProbe_STUB, // rpcCtrlCmdInternalGpuStartFabricProbe + rpcGetBrandCaps_STUB, // rpcGetBrandCaps + rpcRestoreHibernationData_STUB, // rpcRestoreHibernationData + rpcCtrlFlaSetupInstanceMemBlock_STUB, // rpcCtrlFlaSetupInstanceMemBlock + rpcCtrlInternalSriovPromotePmaStream_STUB, // rpcCtrlInternalSriovPromotePmaStream + rpcCtrlFbGetFsInfo_STUB, // rpcCtrlFbGetFsInfo + rpcCtrlSetChannelInterleaveLevel_STUB, // rpcCtrlSetChannelInterleaveLevel + rpcCtrlDbgResumeContext_STUB, // rpcCtrlDbgResumeContext + rpcAllocRoot_STUB, // rpcAllocRoot + rpcCtrlFifoDisableChannels_STUB, // rpcCtrlFifoDisableChannels + rpcCtrlSetHsCredits_STUB, // rpcCtrlSetHsCredits + rpcGetEngineUtilization_STUB, // rpcGetEngineUtilization + rpcCtrlGetZbcClearTableEntry_STUB, // rpcCtrlGetZbcClearTableEntry + rpcCtrlNvencSwSessionUpdateInfo_STUB, // rpcCtrlNvencSwSessionUpdateInfo + rpcCtrlDbgSuspendContext_STUB, // rpcCtrlDbgSuspendContext + rpcCtrlGetP2pCapsMatrix_STUB, // rpcCtrlGetP2pCapsMatrix + rpcCtrlDbgExecRegOps_STUB, // rpcCtrlDbgExecRegOps + rpcCtrlFreePmaStream_STUB, // rpcCtrlFreePmaStream + rpcCtrlSetTsgInterleaveLevel_STUB, // rpcCtrlSetTsgInterleaveLevel + rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_STUB, // rpcCtrlMasterGetVirtualFunctionErrorContIntrMask + rpcLog_STUB, // rpcLog + rpcCtrlExecPartitionsDelete_STUB, // rpcCtrlExecPartitionsDelete + rpcCtrlPerfBoost_STUB, // rpcCtrlPerfBoost + rpcCtrlDbgSetModeMmuDebug_STUB, // rpcCtrlDbgSetModeMmuDebug + rpcCtrlFifoSetChannelProperties_STUB, // rpcCtrlFifoSetChannelProperties + rpcCtrlSubdeviceGetP2pCaps_STUB, // rpcCtrlSubdeviceGetP2pCaps rpcUpdateBarPde_STUB, // rpcUpdateBarPde + rpcCtrlBindPmResources_STUB, // rpcCtrlBindPmResources rpcMapMemoryDma_STUB, // rpcMapMemoryDma rpcUnmapMemoryDma_STUB, // rpcUnmapMemoryDma - rpcRmfsTest_STUB, // rpcRmfsTest + rpcSetGuestSystemInfoExt_STUB, // rpcSetGuestSystemInfoExt rpc_iGrp_ipVersions_getInfo, // rpc_iGrp_ipVersions_getInfo }; // rpcHalIfacesInitStruct_GA100 @@ -3347,6 +3256,8 @@ static void rpcHalIfacesSetup_GA102(RPC_HAL_IFACES *pRpcHal) { rpcHalIfacesSetup_GA100(pRpcHal); // GA102 interfaces almost identical to GA100 + pRpcHal->rpcVgpuGspRingDoorbell = rpcVgpuGspRingDoorbell_GA102; + pRpcHal->rpcVgpuGspWriteScratchRegister = rpcVgpuGspWriteScratchRegister_GA102; } #endif // GA10X or GA102 @@ -3395,26 +3306,136 @@ static void rpcHalIfacesSetup_AD102(RPC_HAL_IFACES *pRpcHal) // AD102's RPC hal interface function pointer block static const RPC_HAL_IFACES rpcHalIfacesInitStruct_AD102 = { + rpcCtrlFifoSetupVfZombieSubctxPdb_STUB, // rpcCtrlFifoSetupVfZombieSubctxPdb rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 + rpcCtrlBusUnsetP2pMapping_STUB, // rpcCtrlBusUnsetP2pMapping rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent rpcEccNotifierWriteAck_STUB, // rpcEccNotifierWriteAck rpcAllocMemory_STUB, // rpcAllocMemory + rpcCtrlDbgReadSingleSmErrorState_STUB, // rpcCtrlDbgReadSingleSmErrorState + rpcDisableChannels_STUB, // rpcDisableChannels rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps - rpcRmfsInit_STUB, // rpcRmfsInit + rpcCtrlGpuPromoteCtx_STUB, // rpcCtrlGpuPromoteCtx + rpcCtrlDbgSetNextStopTriggerType_STUB, // rpcCtrlDbgSetNextStopTriggerType + rpcAllocShareDevice_STUB, // rpcAllocShareDevice + rpcCtrlPreempt_STUB, // rpcCtrlPreempt + rpcCtrlGpuInitializeCtx_STUB, // rpcCtrlGpuInitializeCtx + rpcCtrlReservePmAreaSmpc_STUB, // rpcCtrlReservePmAreaSmpc + rpcCtrlGpuMigratableOps_STUB, // rpcCtrlGpuMigratableOps + rpcCtrlDbgSetModeErrbarDebug_STUB, // rpcCtrlDbgSetModeErrbarDebug + rpcCtrlPmaStreamUpdateGetPut_STUB, // rpcCtrlPmaStreamUpdateGetPut + rpcCtrlFabricMemoryDescribe_STUB, // rpcCtrlFabricMemoryDescribe + rpcAllocChannelDma_STUB, // rpcAllocChannelDma + rpcCtrlSetZbcDepthClear_STUB, // rpcCtrlSetZbcDepthClear + rpcCtrlResetIsolatedChannel_STUB, // rpcCtrlResetIsolatedChannel + rpcCtrlDmaSetDefaultVaspace_STUB, // rpcCtrlDmaSetDefaultVaspace + rpcAllocSubdevice_STUB, // rpcAllocSubdevice + rpcFree_STUB, // rpcFree + rpcDmaControl_STUB, // rpcDmaControl + rpcCtrlDbgClearSingleSmErrorState_STUB, // rpcCtrlDbgClearSingleSmErrorState rpcUnsetPageDirectory_STUB, // rpcUnsetPageDirectory rpcGetGspStaticInfo_STUB, // rpcGetGspStaticInfo + rpcSaveHibernationData_STUB, // rpcSaveHibernationData + rpcDupObject_STUB, // rpcDupObject rpcGspSetSystemInfo_STUB, // rpcGspSetSystemInfo - rpcRmfsCleanup_STUB, // rpcRmfsCleanup + rpcCtrlPmAreaPcSampler_STUB, // rpcCtrlPmAreaPcSampler + rpcCtrlDbgSetExceptionMask_STUB, // rpcCtrlDbgSetExceptionMask + rpcCtrlVaspaceCopyServerReservedPdes_STUB, // rpcCtrlVaspaceCopyServerReservedPdes + rpcCtrlGrCtxswPreemptionBind_STUB, // rpcCtrlGrCtxswPreemptionBind + rpcCtrlAllocPmaStream_STUB, // rpcCtrlAllocPmaStream + rpcCtrlReserveHwpmLegacy_STUB, // rpcCtrlReserveHwpmLegacy + rpcCtrlInternalQuiescePmaChannel_STUB, // rpcCtrlInternalQuiescePmaChannel + rpcCtrlPerfRatedTdpGetStatus_STUB, // rpcCtrlPerfRatedTdpGetStatus + rpcCtrlBusSetP2pMapping_STUB, // rpcCtrlBusSetP2pMapping + rpcCtrlGpuGetInfoV2_STUB, // rpcCtrlGpuGetInfoV2 + rpcCtrlGetHsCredits_STUB, // rpcCtrlGetHsCredits + rpcCtrlGrSetCtxswPreemptionMode_STUB, // rpcCtrlGrSetCtxswPreemptionMode + rpcCtrlB0ccExecRegOps_STUB, // rpcCtrlB0ccExecRegOps + rpcCtrlGrmgrGetGrFsInfo_STUB, // rpcCtrlGrmgrGetGrFsInfo + rpcCtrlGetZbcClearTable_STUB, // rpcCtrlGetZbcClearTable + rpcCleanupSurface_STUB, // rpcCleanupSurface + rpcCtrlSetTimeslice_STUB, // rpcCtrlSetTimeslice + rpcCtrlGpuQueryEccStatus_STUB, // rpcCtrlGpuQueryEccStatus + rpcCtrlDbgGetModeMmuDebug_STUB, // rpcCtrlDbgGetModeMmuDebug + rpcCtrlDbgClearAllSmErrorStates_STUB, // rpcCtrlDbgClearAllSmErrorStates + rpcVgpuGspRingDoorbell_GA102, // rpcVgpuGspRingDoorbell + rpcCtrlGrSetTpcPartitionMode_STUB, // rpcCtrlGrSetTpcPartitionMode + rpcCtrlGetTotalHsCredits_STUB, // rpcCtrlGetTotalHsCredits + rpcCtrlInternalPromoteFaultMethodBuffers_STUB, // rpcCtrlInternalPromoteFaultMethodBuffers + rpcCtrlFbGetInfoV2_STUB, // rpcCtrlFbGetInfoV2 + rpcVgpuGspWriteScratchRegister_GA102, // rpcVgpuGspWriteScratchRegister rpcSetPageDirectory_STUB, // rpcSetPageDirectory + rpcCtrlGetP2pCapsV2_STUB, // rpcCtrlGetP2pCapsV2 + rpcCtrlNvlinkGetInbandReceivedData_STUB, // rpcCtrlNvlinkGetInbandReceivedData + rpcCtrlGetCePceMask_STUB, // rpcCtrlGetCePceMask + rpcCtrlGetNvlinkPeerIdMask_STUB, // rpcCtrlGetNvlinkPeerIdMask + rpcCtrlGpuEvictCtx_STUB, // rpcCtrlGpuEvictCtx + rpcCtrlGetMmuDebugMode_STUB, // rpcCtrlGetMmuDebugMode + rpcInvalidateTlb_STUB, // rpcInvalidateTlb + rpcCtrlDbgSetSingleSmSingleStep_STUB, // rpcCtrlDbgSetSingleSmSingleStep rpcUnloadingGuestDriver_STUB, // rpcUnloadingGuestDriver + rpcGetEngineUtilizationWrapper_GM204, // rpcGetEngineUtilizationWrapper + rpcGetConsolidatedGrStaticInfo_STUB, // rpcGetConsolidatedGrStaticInfo + rpcSwitchToVga_STUB, // rpcSwitchToVga + rpcCtrlResetChannel_STUB, // rpcCtrlResetChannel + rpcCtrlGpfifoSchedule_STUB, // rpcCtrlGpfifoSchedule rpcSetRegistry_STUB, // rpcSetRegistry - rpcRmfsCloseQueue_STUB, // rpcRmfsCloseQueue - rpcGetStaticInfo_STUB, // rpcGetStaticInfo + rpcCtrlGetNvlinkStatus_STUB, // rpcCtrlGetNvlinkStatus + rpcGetStaticData_STUB, // rpcGetStaticData + rpcCtrlGrGetTpcPartitionMode_STUB, // rpcCtrlGrGetTpcPartitionMode + rpcCtrlStopChannel_STUB, // rpcCtrlStopChannel + rpcSetSurfaceProperties_STUB, // rpcSetSurfaceProperties + rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_STUB, // rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex + rpcCtrlTimerSetGrTickFreq_STUB, // rpcCtrlTimerSetGrTickFreq + rpcAllocEvent_STUB, // rpcAllocEvent + rpcCtrlGrPcSamplingMode_STUB, // rpcCtrlGrPcSamplingMode + rpcCtrlMcServiceInterrupts_STUB, // rpcCtrlMcServiceInterrupts + rpcCtrlDbgReadAllSmErrorStates_STUB, // rpcCtrlDbgReadAllSmErrorStates + rpcCtrlSetZbcColorClear_STUB, // rpcCtrlSetZbcColorClear + rpcGetEncoderCapacity_STUB, // rpcGetEncoderCapacity + rpcCtrlGetP2pCaps_STUB, // rpcCtrlGetP2pCaps + rpcPerfGetLevelInfo_STUB, // rpcPerfGetLevelInfo + rpcAllocObject_STUB, // rpcAllocObject + rpcCtrlGpuHandleVfPriFault_STUB, // rpcCtrlGpuHandleVfPriFault + rpcRmApiControl_STUB, // rpcRmApiControl + rpcCtrlFabricMemStats_STUB, // rpcCtrlFabricMemStats + rpcCtrlGrCtxswZcullBind_STUB, // rpcCtrlGrCtxswZcullBind + rpcCtrlInternalMemsysSetZbcReferenced_STUB, // rpcCtrlInternalMemsysSetZbcReferenced + rpcCtrlPerfRatedTdpSetControl_STUB, // rpcCtrlPerfRatedTdpSetControl + rpcCtrlExecPartitionsCreate_STUB, // rpcCtrlExecPartitionsCreate + rpcCtrlGpfifoGetWorkSubmitToken_STUB, // rpcCtrlGpfifoGetWorkSubmitToken rpcIdleChannels_STUB, // rpcIdleChannels + rpcCtrlCmdInternalGpuStartFabricProbe_STUB, // rpcCtrlCmdInternalGpuStartFabricProbe + rpcGetBrandCaps_STUB, // rpcGetBrandCaps + rpcRestoreHibernationData_STUB, // rpcRestoreHibernationData + rpcCtrlFlaSetupInstanceMemBlock_STUB, // rpcCtrlFlaSetupInstanceMemBlock + rpcCtrlInternalSriovPromotePmaStream_STUB, // rpcCtrlInternalSriovPromotePmaStream + rpcCtrlFbGetFsInfo_STUB, // rpcCtrlFbGetFsInfo + rpcCtrlSetChannelInterleaveLevel_STUB, // rpcCtrlSetChannelInterleaveLevel + rpcCtrlDbgResumeContext_STUB, // rpcCtrlDbgResumeContext + rpcAllocRoot_STUB, // rpcAllocRoot + rpcCtrlFifoDisableChannels_STUB, // rpcCtrlFifoDisableChannels + rpcCtrlSetHsCredits_STUB, // rpcCtrlSetHsCredits + rpcGetEngineUtilization_STUB, // rpcGetEngineUtilization + rpcCtrlGetZbcClearTableEntry_STUB, // rpcCtrlGetZbcClearTableEntry + rpcCtrlNvencSwSessionUpdateInfo_STUB, // rpcCtrlNvencSwSessionUpdateInfo + rpcCtrlDbgSuspendContext_STUB, // rpcCtrlDbgSuspendContext + rpcCtrlGetP2pCapsMatrix_STUB, // rpcCtrlGetP2pCapsMatrix + rpcCtrlDbgExecRegOps_STUB, // rpcCtrlDbgExecRegOps + rpcCtrlFreePmaStream_STUB, // rpcCtrlFreePmaStream + rpcCtrlSetTsgInterleaveLevel_STUB, // rpcCtrlSetTsgInterleaveLevel + rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_STUB, // rpcCtrlMasterGetVirtualFunctionErrorContIntrMask + rpcLog_STUB, // rpcLog + rpcCtrlExecPartitionsDelete_STUB, // rpcCtrlExecPartitionsDelete + rpcCtrlPerfBoost_STUB, // rpcCtrlPerfBoost + rpcCtrlDbgSetModeMmuDebug_STUB, // rpcCtrlDbgSetModeMmuDebug + rpcCtrlFifoSetChannelProperties_STUB, // rpcCtrlFifoSetChannelProperties + rpcCtrlSubdeviceGetP2pCaps_STUB, // rpcCtrlSubdeviceGetP2pCaps rpcUpdateBarPde_STUB, // rpcUpdateBarPde + rpcCtrlBindPmResources_STUB, // rpcCtrlBindPmResources rpcMapMemoryDma_STUB, // rpcMapMemoryDma rpcUnmapMemoryDma_STUB, // rpcUnmapMemoryDma - rpcRmfsTest_STUB, // rpcRmfsTest + rpcSetGuestSystemInfoExt_STUB, // rpcSetGuestSystemInfoExt rpc_iGrp_ipVersions_getInfo, // rpc_iGrp_ipVersions_getInfo }; // rpcHalIfacesInitStruct_AD102 @@ -3469,26 +3490,136 @@ static void rpcHalIfacesSetup_GH100(RPC_HAL_IFACES *pRpcHal) // GH100's RPC hal interface function pointer block static const RPC_HAL_IFACES rpcHalIfacesInitStruct_GH100 = { + rpcCtrlFifoSetupVfZombieSubctxPdb_STUB, // rpcCtrlFifoSetupVfZombieSubctxPdb rpcVgpuPfRegRead32_STUB, // rpcVgpuPfRegRead32 + rpcCtrlBusUnsetP2pMapping_STUB, // rpcCtrlBusUnsetP2pMapping rpcDumpProtobufComponent_STUB, // rpcDumpProtobufComponent rpcEccNotifierWriteAck_STUB, // rpcEccNotifierWriteAck rpcAllocMemory_STUB, // rpcAllocMemory + rpcCtrlDbgReadSingleSmErrorState_STUB, // rpcCtrlDbgReadSingleSmErrorState + rpcDisableChannels_STUB, // rpcDisableChannels rpcGpuExecRegOps_STUB, // rpcGpuExecRegOps - rpcRmfsInit_STUB, // rpcRmfsInit + rpcCtrlGpuPromoteCtx_STUB, // rpcCtrlGpuPromoteCtx + rpcCtrlDbgSetNextStopTriggerType_STUB, // rpcCtrlDbgSetNextStopTriggerType + rpcAllocShareDevice_STUB, // rpcAllocShareDevice + rpcCtrlPreempt_STUB, // rpcCtrlPreempt + rpcCtrlGpuInitializeCtx_STUB, // rpcCtrlGpuInitializeCtx + rpcCtrlReservePmAreaSmpc_STUB, // rpcCtrlReservePmAreaSmpc + rpcCtrlGpuMigratableOps_STUB, // rpcCtrlGpuMigratableOps + rpcCtrlDbgSetModeErrbarDebug_STUB, // rpcCtrlDbgSetModeErrbarDebug + rpcCtrlPmaStreamUpdateGetPut_STUB, // rpcCtrlPmaStreamUpdateGetPut + rpcCtrlFabricMemoryDescribe_STUB, // rpcCtrlFabricMemoryDescribe + rpcAllocChannelDma_STUB, // rpcAllocChannelDma + rpcCtrlSetZbcDepthClear_STUB, // rpcCtrlSetZbcDepthClear + rpcCtrlResetIsolatedChannel_STUB, // rpcCtrlResetIsolatedChannel + rpcCtrlDmaSetDefaultVaspace_STUB, // rpcCtrlDmaSetDefaultVaspace + rpcAllocSubdevice_STUB, // rpcAllocSubdevice + rpcFree_STUB, // rpcFree + rpcDmaControl_STUB, // rpcDmaControl + rpcCtrlDbgClearSingleSmErrorState_STUB, // rpcCtrlDbgClearSingleSmErrorState rpcUnsetPageDirectory_STUB, // rpcUnsetPageDirectory rpcGetGspStaticInfo_STUB, // rpcGetGspStaticInfo + rpcSaveHibernationData_STUB, // rpcSaveHibernationData + rpcDupObject_STUB, // rpcDupObject rpcGspSetSystemInfo_STUB, // rpcGspSetSystemInfo - rpcRmfsCleanup_STUB, // rpcRmfsCleanup + rpcCtrlPmAreaPcSampler_STUB, // rpcCtrlPmAreaPcSampler + rpcCtrlDbgSetExceptionMask_STUB, // rpcCtrlDbgSetExceptionMask + rpcCtrlVaspaceCopyServerReservedPdes_STUB, // rpcCtrlVaspaceCopyServerReservedPdes + rpcCtrlGrCtxswPreemptionBind_STUB, // rpcCtrlGrCtxswPreemptionBind + rpcCtrlAllocPmaStream_STUB, // rpcCtrlAllocPmaStream + rpcCtrlReserveHwpmLegacy_STUB, // rpcCtrlReserveHwpmLegacy + rpcCtrlInternalQuiescePmaChannel_STUB, // rpcCtrlInternalQuiescePmaChannel + rpcCtrlPerfRatedTdpGetStatus_STUB, // rpcCtrlPerfRatedTdpGetStatus + rpcCtrlBusSetP2pMapping_STUB, // rpcCtrlBusSetP2pMapping + rpcCtrlGpuGetInfoV2_STUB, // rpcCtrlGpuGetInfoV2 + rpcCtrlGetHsCredits_STUB, // rpcCtrlGetHsCredits + rpcCtrlGrSetCtxswPreemptionMode_STUB, // rpcCtrlGrSetCtxswPreemptionMode + rpcCtrlB0ccExecRegOps_STUB, // rpcCtrlB0ccExecRegOps + rpcCtrlGrmgrGetGrFsInfo_STUB, // rpcCtrlGrmgrGetGrFsInfo + rpcCtrlGetZbcClearTable_STUB, // rpcCtrlGetZbcClearTable + rpcCleanupSurface_STUB, // rpcCleanupSurface + rpcCtrlSetTimeslice_STUB, // rpcCtrlSetTimeslice + rpcCtrlGpuQueryEccStatus_STUB, // rpcCtrlGpuQueryEccStatus + rpcCtrlDbgGetModeMmuDebug_STUB, // rpcCtrlDbgGetModeMmuDebug + rpcCtrlDbgClearAllSmErrorStates_STUB, // rpcCtrlDbgClearAllSmErrorStates + rpcVgpuGspRingDoorbell_GA102, // rpcVgpuGspRingDoorbell + rpcCtrlGrSetTpcPartitionMode_STUB, // rpcCtrlGrSetTpcPartitionMode + rpcCtrlGetTotalHsCredits_STUB, // rpcCtrlGetTotalHsCredits + rpcCtrlInternalPromoteFaultMethodBuffers_STUB, // rpcCtrlInternalPromoteFaultMethodBuffers + rpcCtrlFbGetInfoV2_STUB, // rpcCtrlFbGetInfoV2 + rpcVgpuGspWriteScratchRegister_GA102, // rpcVgpuGspWriteScratchRegister rpcSetPageDirectory_STUB, // rpcSetPageDirectory + rpcCtrlGetP2pCapsV2_STUB, // rpcCtrlGetP2pCapsV2 + rpcCtrlNvlinkGetInbandReceivedData_STUB, // rpcCtrlNvlinkGetInbandReceivedData + rpcCtrlGetCePceMask_STUB, // rpcCtrlGetCePceMask + rpcCtrlGetNvlinkPeerIdMask_STUB, // rpcCtrlGetNvlinkPeerIdMask + rpcCtrlGpuEvictCtx_STUB, // rpcCtrlGpuEvictCtx + rpcCtrlGetMmuDebugMode_STUB, // rpcCtrlGetMmuDebugMode + rpcInvalidateTlb_STUB, // rpcInvalidateTlb + rpcCtrlDbgSetSingleSmSingleStep_STUB, // rpcCtrlDbgSetSingleSmSingleStep rpcUnloadingGuestDriver_STUB, // rpcUnloadingGuestDriver + rpcGetEngineUtilizationWrapper_GM204, // rpcGetEngineUtilizationWrapper + rpcGetConsolidatedGrStaticInfo_STUB, // rpcGetConsolidatedGrStaticInfo + rpcSwitchToVga_STUB, // rpcSwitchToVga + rpcCtrlResetChannel_STUB, // rpcCtrlResetChannel + rpcCtrlGpfifoSchedule_STUB, // rpcCtrlGpfifoSchedule rpcSetRegistry_STUB, // rpcSetRegistry - rpcRmfsCloseQueue_STUB, // rpcRmfsCloseQueue - rpcGetStaticInfo_STUB, // rpcGetStaticInfo + rpcCtrlGetNvlinkStatus_STUB, // rpcCtrlGetNvlinkStatus + rpcGetStaticData_STUB, // rpcGetStaticData + rpcCtrlGrGetTpcPartitionMode_STUB, // rpcCtrlGrGetTpcPartitionMode + rpcCtrlStopChannel_STUB, // rpcCtrlStopChannel + rpcSetSurfaceProperties_STUB, // rpcSetSurfaceProperties + rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_STUB, // rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex + rpcCtrlTimerSetGrTickFreq_STUB, // rpcCtrlTimerSetGrTickFreq + rpcAllocEvent_STUB, // rpcAllocEvent + rpcCtrlGrPcSamplingMode_STUB, // rpcCtrlGrPcSamplingMode + rpcCtrlMcServiceInterrupts_STUB, // rpcCtrlMcServiceInterrupts + rpcCtrlDbgReadAllSmErrorStates_STUB, // rpcCtrlDbgReadAllSmErrorStates + rpcCtrlSetZbcColorClear_STUB, // rpcCtrlSetZbcColorClear + rpcGetEncoderCapacity_STUB, // rpcGetEncoderCapacity + rpcCtrlGetP2pCaps_STUB, // rpcCtrlGetP2pCaps + rpcPerfGetLevelInfo_STUB, // rpcPerfGetLevelInfo + rpcAllocObject_STUB, // rpcAllocObject + rpcCtrlGpuHandleVfPriFault_STUB, // rpcCtrlGpuHandleVfPriFault + rpcRmApiControl_STUB, // rpcRmApiControl + rpcCtrlFabricMemStats_STUB, // rpcCtrlFabricMemStats + rpcCtrlGrCtxswZcullBind_STUB, // rpcCtrlGrCtxswZcullBind + rpcCtrlInternalMemsysSetZbcReferenced_STUB, // rpcCtrlInternalMemsysSetZbcReferenced + rpcCtrlPerfRatedTdpSetControl_STUB, // rpcCtrlPerfRatedTdpSetControl + rpcCtrlExecPartitionsCreate_STUB, // rpcCtrlExecPartitionsCreate + rpcCtrlGpfifoGetWorkSubmitToken_STUB, // rpcCtrlGpfifoGetWorkSubmitToken rpcIdleChannels_STUB, // rpcIdleChannels + rpcCtrlCmdInternalGpuStartFabricProbe_STUB, // rpcCtrlCmdInternalGpuStartFabricProbe + rpcGetBrandCaps_STUB, // rpcGetBrandCaps + rpcRestoreHibernationData_STUB, // rpcRestoreHibernationData + rpcCtrlFlaSetupInstanceMemBlock_STUB, // rpcCtrlFlaSetupInstanceMemBlock + rpcCtrlInternalSriovPromotePmaStream_STUB, // rpcCtrlInternalSriovPromotePmaStream + rpcCtrlFbGetFsInfo_STUB, // rpcCtrlFbGetFsInfo + rpcCtrlSetChannelInterleaveLevel_STUB, // rpcCtrlSetChannelInterleaveLevel + rpcCtrlDbgResumeContext_STUB, // rpcCtrlDbgResumeContext + rpcAllocRoot_STUB, // rpcAllocRoot + rpcCtrlFifoDisableChannels_STUB, // rpcCtrlFifoDisableChannels + rpcCtrlSetHsCredits_STUB, // rpcCtrlSetHsCredits + rpcGetEngineUtilization_STUB, // rpcGetEngineUtilization + rpcCtrlGetZbcClearTableEntry_STUB, // rpcCtrlGetZbcClearTableEntry + rpcCtrlNvencSwSessionUpdateInfo_STUB, // rpcCtrlNvencSwSessionUpdateInfo + rpcCtrlDbgSuspendContext_STUB, // rpcCtrlDbgSuspendContext + rpcCtrlGetP2pCapsMatrix_STUB, // rpcCtrlGetP2pCapsMatrix + rpcCtrlDbgExecRegOps_STUB, // rpcCtrlDbgExecRegOps + rpcCtrlFreePmaStream_STUB, // rpcCtrlFreePmaStream + rpcCtrlSetTsgInterleaveLevel_STUB, // rpcCtrlSetTsgInterleaveLevel + rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_STUB, // rpcCtrlMasterGetVirtualFunctionErrorContIntrMask + rpcLog_STUB, // rpcLog + rpcCtrlExecPartitionsDelete_STUB, // rpcCtrlExecPartitionsDelete + rpcCtrlPerfBoost_STUB, // rpcCtrlPerfBoost + rpcCtrlDbgSetModeMmuDebug_STUB, // rpcCtrlDbgSetModeMmuDebug + rpcCtrlFifoSetChannelProperties_STUB, // rpcCtrlFifoSetChannelProperties + rpcCtrlSubdeviceGetP2pCaps_STUB, // rpcCtrlSubdeviceGetP2pCaps rpcUpdateBarPde_STUB, // rpcUpdateBarPde + rpcCtrlBindPmResources_STUB, // rpcCtrlBindPmResources rpcMapMemoryDma_STUB, // rpcMapMemoryDma rpcUnmapMemoryDma_STUB, // rpcUnmapMemoryDma - rpcRmfsTest_STUB, // rpcRmfsTest + rpcSetGuestSystemInfoExt_STUB, // rpcSetGuestSystemInfoExt rpc_iGrp_ipVersions_getInfo, // rpc_iGrp_ipVersions_getInfo }; // rpcHalIfacesInitStruct_GH100 diff --git a/src/nvidia/generated/g_rpcstructurecopy_hal.h b/src/nvidia/generated/g_rpcstructurecopy_hal.h new file mode 100644 index 0000000000..695d113e57 --- /dev/null +++ b/src/nvidia/generated/g_rpcstructurecopy_hal.h @@ -0,0 +1,277 @@ +// This file is automatically generated by rmconfig - DO NOT EDIT! +// +// Provides access to RPCSTRUCTURECOPY Hal interfaces. +// +// Profile: shipping-gpus-openrm +// Haldef: rpcstructurecopy.def +// Template: templates/gt_eng_hal.h +// + +#ifndef _G_RPCSTRUCTURECOPYHAL_H_ +#define _G_RPCSTRUCTURECOPYHAL_H_ + +// +// Typedefs for RPCSTRUCTURECOPY public object interfaces. +// + + + +// +// "struct" to list RPCSTRUCTURECOPY's public interfaces, eg: pRpcstructurecopy->rpcstructurecopyInit(pGpu, pRpcstructurecopy) +// + + + +// +// macro defines to directly access RPCSTRUCTURECOPY's OBJ interfaces, +// eg: #define rpcstructurecopyReadFoo(_pGpu, _pRpcstructurecopy) _pRpcstructurecopy->obj._rpcstructurecopyReadFoo(_pGpu, _pRpcstructurecopy) +// + + + +// +// macro defines to access RPCSTRUCTURECOPY's function pointers, +// eg: #define rpcstructurecopyReadFoo_FNPTR(_pRpcstructurecopy) _pRpcstructurecopy->obj.__rpcstructurecopyReadFoo__ +// or #define rpcstructurecopyReadFoo_FNPTR(_pRpcstructurecopy) _pRpcstructurecopy->__rpcstructurecopyReadFoo__ +// + + + +// +// Typedefs for RPCSTRUCTURECOPY HAL interfaces. +// + +typedef NV_STATUS Deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS(NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_P2P_CAPABILITY_PARAMS(VGPU_P2P_CAPABILITY_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS(NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP(VGPU_FB_GET_LTC_INFO_FOR_FBP* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_STATIC_DATA(VGPU_STATIC_DATA* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE(VGPU_FIFO_GET_DEVICE_INFO_TABLE* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_BSP_GET_CAPS(VGPU_BSP_GET_CAPS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_GPU_PARTITION_INFO(GPU_PARTITION_INFO* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_STATIC_PROPERTIES(VGPU_STATIC_PROPERTIES* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS(NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS(NV2080_CTRL_FLA_GET_RANGE_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_CE_GET_CAPS_V2(VGPU_CE_GET_CAPS_V2* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_VGPU_GET_LATENCY_BUFFER_SIZE(VGPU_GET_LATENCY_BUFFER_SIZE* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS(NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS* data, NvU8* stream, NvU32 streamSize, NvU32 *offset); +typedef NV_STATUS Rpcstructurecopy_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *); + + +// +// struct to access RPCSTRUCTURECOPY's hal interfaces, eg: pRpcstructurecopy->hal.rpcstructurecopyReadFoo(pGpu, pRpcstructurecopy) +// + +typedef struct RPCSTRUCTURECOPY_HAL_IFACES { + Deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS */ + Deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS; /* HAL function to deserialize NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS */ + Deserialize_VGPU_P2P_CAPABILITY_PARAMS *deserialize_VGPU_P2P_CAPABILITY_PARAMS; /* HAL function to deserialize VGPU_P2P_CAPABILITY_PARAMS */ + Deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS */ + Deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS; /* HAL function to deserialize NVA080_CTRL_VGPU_GET_CONFIG_PARAMS */ + Deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS *deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS; /* HAL function to deserialize NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS */ + Deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS */ + Deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS *deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_GPU_GET_GID_INFO_PARAMS */ + Deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS; /* HAL function to deserialize NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS */ + Deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS; /* HAL function to deserialize NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS */ + Deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES *deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES; /* HAL function to deserialize VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS */ + Deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP *deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP; /* HAL function to deserialize VGPU_FB_GET_LTC_INFO_FOR_FBP */ + Deserialize_VGPU_STATIC_DATA *deserialize_VGPU_STATIC_DATA; /* HAL function to deserialize VGPU_STATIC_DATA */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS */ + Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS; /* HAL function to deserialize NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS */ + Deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS; /* HAL function to deserialize NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS */ + Deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS */ + Deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE *deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE; /* HAL function to deserialize VGPU_FIFO_GET_DEVICE_INFO_TABLE */ + Deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS; /* HAL function to deserialize NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS */ + Deserialize_VGPU_BSP_GET_CAPS *deserialize_VGPU_BSP_GET_CAPS; /* HAL function to deserialize VGPU_BSP_GET_CAPS */ + Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS; /* HAL function to deserialize NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS */ + Deserialize_GPU_PARTITION_INFO *deserialize_GPU_PARTITION_INFO; /* HAL function to deserialize GPU_PARTITION_INFO */ + Deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS; /* HAL function to deserialize NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS */ + Deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS; /* HAL function to deserialize NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS */ + Deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS; /* HAL function to deserialize NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS */ + Deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS; /* HAL function to deserialize NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS */ + Deserialize_VGPU_STATIC_PROPERTIES *deserialize_VGPU_STATIC_PROPERTIES; /* HAL function to deserialize VGPU_STATIC_PROPERTIES */ + Deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS; /* HAL function to deserialize NV2080_CTRL_BUS_GET_INFO_V2_PARAMS */ + Deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS */ + Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS; /* HAL function to deserialize NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS */ + Deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS *deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS; /* HAL function to deserialize NV2080_CTRL_FLA_GET_RANGE_PARAMS */ + Deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS; /* HAL function to deserialize NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS */ + Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS; /* HAL function to deserialize NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS */ + Deserialize_VGPU_CE_GET_CAPS_V2 *deserialize_VGPU_CE_GET_CAPS_V2; /* HAL function to deserialize VGPU_CE_GET_CAPS_V2 */ + Deserialize_VGPU_GET_LATENCY_BUFFER_SIZE *deserialize_VGPU_GET_LATENCY_BUFFER_SIZE; /* HAL function to deserialize VGPU_GET_LATENCY_BUFFER_SIZE */ + Deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS; /* HAL function to deserialize NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS */ + Rpcstructurecopy_iGrp_ipVersions_getInfo *rpcstructurecopy_iGrp_ipVersions_getInfo; /* Return lookup table of hal interface ptrs based on IP_VERSION */ +} RPCSTRUCTURECOPY_HAL_IFACES; + + +// +// macro defines to directly access RPCSTRUCTURECOPY's hal interfaces, +// eg: #define rpcstructurecopyReadFoo_HAL(_pGpu, _pRpcstructurecopy) _pRpcstructurecopy->hal.rpcstructurecopyReadFoo(_pGpu, _pRpcstructurecopy) +// + +#define deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_P2P_CAPABILITY_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_P2P_CAPABILITY_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_STATIC_DATA_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_STATIC_DATA(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_BSP_GET_CAPS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_BSP_GET_CAPS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_GPU_PARTITION_INFO_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_GPU_PARTITION_INFO(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_STATIC_PROPERTIES_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_STATIC_PROPERTIES(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_CE_GET_CAPS_V2_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_CE_GET_CAPS_V2(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_VGPU_GET_LATENCY_BUFFER_SIZE(_pData, _pStream, _streamSize, _pOffset) +#define deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_HAL(_pRpcstructurecopy, _pData, _pStream, _streamSize, _pOffset) \ + (_pRpcstructurecopy)->_hal.deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS(_pData, _pStream, _streamSize, _pOffset) +#define rpcstructurecopy_iGrp_ipVersions_getInfo_HAL(_pRpcstructurecopy, _pArg0) \ + (_pRpcstructurecopy)->_hal.rpcstructurecopy_iGrp_ipVersions_getInfo(_pArg0) + +// +// hal function pointer defines requested by the :GEN_FNPTR_DEFINE flag +// + +#define rpcstructurecopy_iGrp_ipVersions_getInfo_HAL_FNPTR(_pObj) (_pObj)->_hal.rpcstructurecopy_iGrp_ipVersions_getInfo + +// Are there any optimized hal interfaces? +#define RPCSTRUCTURECOPY_DIRECT_HAL_CALLS 0 + +// Are there any non-optimized hal interfaces? +#define RPCSTRUCTURECOPY_INDIRECT_HAL_CALLS 1 + + +// +// Inline stub function definitions. +// + + + +// +// RPCSTRUCTURECOPY PDB properties +// + + + +#endif // _G_RPCSTRUCTURECOPYHAL_H_ diff --git a/src/nvidia/generated/g_rpcstructurecopy_iom.c b/src/nvidia/generated/g_rpcstructurecopy_iom.c new file mode 100644 index 0000000000..1044ea514d --- /dev/null +++ b/src/nvidia/generated/g_rpcstructurecopy_iom.c @@ -0,0 +1,128 @@ +// This file is automatically generated by rmconfig - DO NOT EDIT! +// +// Profile: shipping-gpus-openrm +// Template: templates/gt_eng_iom.c +// +#include "nvstatus.h" +#include "nvport/inline/util_valist.h" +#include "nvport/nvport.h" +#include "core/core.h" +#include "nvoc/rtti.h" +#include "os/os.h" +#include "gpu/gpu.h" + +#include "objrpcstructurecopy.h" + +#include "g_rpcstructurecopy_private.h" + +// +// RPCSTRUCTURECOPY's object-level _STUB, _MISSING, _VGPUSTUB interface routines +// (if any) +// + + + + + + + + +// +// Initialize RPCSTRUCTURECOPY's object-level interfaces +// +static void +rpcstructurecopySetPropertiesSpecial +( + POBJRPCSTRUCTURECOPY pRpcstructurecopy +) +{ + +} + + + + + +// +// RPCSTRUCTURECOPY's run-time type information +// + +extern const struct NVOC_CLASS_DEF __iom_class_def_OBJRPCSTRUCTURECOPY; + +void __iom_dtor_OBJRPCSTRUCTURECOPY(POBJRPCSTRUCTURECOPY); + +const struct NVOC_RTTI __iom_rtti_OBJRPCSTRUCTURECOPY_OBJRPCSTRUCTURECOPY = +{ + &__iom_class_def_OBJRPCSTRUCTURECOPY, + (NVOC_DYNAMIC_DTOR)&__iom_dtor_OBJRPCSTRUCTURECOPY, + 0, +}; + +static const struct NVOC_CASTINFO __iom_castinfo_OBJRPCSTRUCTURECOPY = +{ + 1, + { + &__iom_rtti_OBJRPCSTRUCTURECOPY_OBJRPCSTRUCTURECOPY + } +}; + +extern const NVOC_RTTI_PROVIDER __iom_rtti_provider; +const struct NVOC_CLASS_DEF __iom_class_def_OBJRPCSTRUCTURECOPY = +{ + { + sizeof(OBJRPCSTRUCTURECOPY), + classId(OBJRPCSTRUCTURECOPY), + &__iom_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + "OBJRPCSTRUCTURECOPY", +#endif + }, + NULL, + &__iom_castinfo_OBJRPCSTRUCTURECOPY, +}; + + + + +// +// RPCSTRUCTURECOPY's object infrastructure boilerplate +// + +// initializers, constructors, and destructors for RPCSTRUCTURECOPY's base classes + +NV_STATUS __iom_ctor_OBJRPCSTRUCTURECOPY(POBJRPCSTRUCTURECOPY pRpcstructurecopy) +{ + RMCFG_MODULE_ENABLED_OR_ASSERT_AND_BAIL(RPCSTRUCTURECOPY); + return NV_OK; +} + +NV_STATUS __iom_vctor_OBJRPCSTRUCTURECOPY(Dynamic *pDynamic, va_list args) +{ + NV_STATUS status; + POBJRPCSTRUCTURECOPY pThis = dynamicCast(pDynamic, OBJRPCSTRUCTURECOPY); + if (pThis != NULL) + { + status = __iom_ctor_OBJRPCSTRUCTURECOPY(pThis); + } + else + { + status = NV_ERR_INVALID_OBJECT; + } + return status; +} + +void __iom_dtor_OBJRPCSTRUCTURECOPY(POBJRPCSTRUCTURECOPY pRpcstructurecopy) +{ +} + +// RPCSTRUCTURECOPY's object initializer function to set up vtables and RTTI +void __iom_init_OBJRPCSTRUCTURECOPY(POBJRPCSTRUCTURECOPY pRpcstructurecopy) +{ + rpcstructurecopySetPropertiesSpecial(pRpcstructurecopy); +} + + +// +// RPCSTRUCTURECOPY's object creation routine +// + diff --git a/src/nvidia/generated/g_rpcstructurecopy_odb.h b/src/nvidia/generated/g_rpcstructurecopy_odb.h new file mode 100644 index 0000000000..0b57129b36 --- /dev/null +++ b/src/nvidia/generated/g_rpcstructurecopy_odb.h @@ -0,0 +1,30 @@ +// This file is automatically generated by rmconfig - DO NOT EDIT! +// +// Provides RPCSTRUCTURECOPY object boilerplate and RTTI. +// +// Profile: shipping-gpus-openrm +// Haldef: rpcstructurecopy.def +// Template: templates/gt_eng_odb.h +// + +#ifndef _G_RPCSTRUCTURECOPY_ODB_H_ +#define _G_RPCSTRUCTURECOPY_ODB_H_ + +#include "core/core.h" +#include "g_rpcstructurecopy_hal.h" + + +#define __RPCSTRUCTURECOPY_OBJECT_BASE_DEFINITION \ + const struct NVOC_RTTI *__nvoc_rtti; \ + RPCSTRUCTURECOPY_HAL_IFACES _hal + + +extern const struct NVOC_CLASS_DEF __iom_class_def_OBJRPCSTRUCTURECOPY; +#define __nvoc_class_def_OBJRPCSTRUCTURECOPY __iom_class_def_OBJRPCSTRUCTURECOPY + +#ifndef __nvoc_class_id_OBJRPCSTRUCTURECOPY +#define __nvoc_class_id_OBJRPCSTRUCTURECOPY 0xd4dff8 +#endif /* __nvoc_class_id_OBJRPCSTRUCTURECOPY */ + + +#endif // _G_RPCSTRUCTURECOPY_ODB_H_ diff --git a/src/nvidia/generated/g_rpcstructurecopy_private.h b/src/nvidia/generated/g_rpcstructurecopy_private.h new file mode 100644 index 0000000000..869273b411 --- /dev/null +++ b/src/nvidia/generated/g_rpcstructurecopy_private.h @@ -0,0 +1,1583 @@ +// This file is automatically generated by rmconfig - DO NOT EDIT! +// +// Private HAL support for RPCSTRUCTURECOPY. +// +// Profile: shipping-gpus-openrm +// Haldef: rpcstructurecopy.def +// Template: templates/gt_eng_private.h +// + +#ifndef _G_RPCSTRUCTURECOPY_PRIVATE_H_ +#define _G_RPCSTRUCTURECOPY_PRIVATE_H_ + +#include "g_rpcstructurecopy_hal.h" + + + // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS +Deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00; +Deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06; +Deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS +Deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04; +Deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_P2P_CAPABILITY_PARAMS +Deserialize_VGPU_P2P_CAPABILITY_PARAMS deserialize_VGPU_P2P_CAPABILITY_PARAMS_v25_03; +Deserialize_VGPU_P2P_CAPABILITY_PARAMS deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS +Deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01; +Deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NVA080_CTRL_VGPU_GET_CONFIG_PARAMS +Deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C; +Deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS +Deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03; +Deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05; +Deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS +Deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E; +Deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_GPU_GET_GID_INFO_PARAMS +Deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00; +Deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS +Deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B; +Deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13; +Deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS +Deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05; +Deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES +Deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07; +Deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_FB_GET_LTC_INFO_FOR_FBP +Deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D; +Deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_STATIC_DATA +Deserialize_VGPU_STATIC_DATA deserialize_VGPU_STATIC_DATA_v25_0E; +Deserialize_VGPU_STATIC_DATA deserialize_VGPU_STATIC_DATA_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS +Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B; +Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS +Deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00; +Deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS +Deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01; +Deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_FIFO_GET_DEVICE_INFO_TABLE +Deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07; +Deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS +Deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A; +Deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_BSP_GET_CAPS +Deserialize_VGPU_BSP_GET_CAPS deserialize_VGPU_BSP_GET_CAPS_v25_00; +Deserialize_VGPU_BSP_GET_CAPS deserialize_VGPU_BSP_GET_CAPS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS +Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08; +Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:GPU_PARTITION_INFO +Deserialize_GPU_PARTITION_INFO deserialize_GPU_PARTITION_INFO_v24_05; +Deserialize_GPU_PARTITION_INFO deserialize_GPU_PARTITION_INFO_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS +Deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09; +Deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS +Deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00; +Deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS +Deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07; +Deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS +Deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02; +Deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_STATIC_PROPERTIES +Deserialize_VGPU_STATIC_PROPERTIES deserialize_VGPU_STATIC_PROPERTIES_v1B_01; +Deserialize_VGPU_STATIC_PROPERTIES deserialize_VGPU_STATIC_PROPERTIES_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_BUS_GET_INFO_V2_PARAMS +Deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09; +Deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS +Deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01; +Deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07; +Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_FLA_GET_RANGE_PARAMS +Deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18; +Deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS +Deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F; +Deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS +Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06; +Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_CE_GET_CAPS_V2 +Deserialize_VGPU_CE_GET_CAPS_V2 deserialize_VGPU_CE_GET_CAPS_V2_v24_09; +Deserialize_VGPU_CE_GET_CAPS_V2 deserialize_VGPU_CE_GET_CAPS_V2_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:VGPU_GET_LATENCY_BUFFER_SIZE +Deserialize_VGPU_GET_LATENCY_BUFFER_SIZE deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09; +Deserialize_VGPU_GET_LATENCY_BUFFER_SIZE deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + // RPCSTRUCTURECOPY:NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS +Deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00; +Deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB; // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X + + + + + + +// +// RPCSTRUCTURECOPY's object-level *non-static* interface functions (static ones are below) +// + + + +#if defined(RMCFG_ENGINE_SETUP) // for use by hal init only + + + + + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v03_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v12_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v15_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v15_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v16_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v18_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1A_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1A_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1A_18(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1A_1F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1B_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1B_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1C_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1C_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1D_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1D_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1E_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1E_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1F_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v1F_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v20_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v21_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v21_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v22_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v24_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v24_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v24_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v24_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + +// No enabled chips use this variant provider +static void rpcstructurecopy_iGrp_ipVersions_Install_v25_13(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ +#if 0 + + POBJGPU pGpu = pInfo->pGpu; + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pGpu += 0; + pRpcstructurecopyHal += 0; + + +#endif // +} + + + + +// the "_UNASSIGNED" function for all IP_VERSIONS dynamic interfaces +NV_STATUS iGrp_ipVersions_UNASSIGNED(void); + + +static NV_STATUS rpcstructurecopy_iGrp_ipVersions_Wrapup(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ + OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic; + RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal; + + // avoid possible unused warnings + pRpcstructurecopyHal += 0; + + // fixup per-interface overrides? + if (IsIPVersionInRange(pRpcstructurecopy, 0x03000000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS = deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00; + if (IsIPVersionInRange(pRpcstructurecopy, 0x25060000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS = deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06; + if (IsIPVersionInRange(pRpcstructurecopy, 0x20040000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS = deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04; + if (IsIPVersionInRange(pRpcstructurecopy, 0x25030000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_P2P_CAPABILITY_PARAMS = deserialize_VGPU_P2P_CAPABILITY_PARAMS_v25_03; + if (IsIPVersionInRange(pRpcstructurecopy, 0x22010000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS = deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01; + if (IsIPVersionInRange(pRpcstructurecopy, 0x210C0000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS = deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C; + if (IsIPVersionInRange(pRpcstructurecopy, 0x15030000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS = deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1F010000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01; + if (IsIPVersionInRange(pRpcstructurecopy, 0x25050000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS = deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05; + if (IsIPVersionInRange(pRpcstructurecopy, 0x250E0000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS = deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E; + if (IsIPVersionInRange(pRpcstructurecopy, 0x03000000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS = deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00; + if (IsIPVersionInRange(pRpcstructurecopy, 0x180B0000, 0x2512FFFF)) + pRpcstructurecopyHal->deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS = deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B; + if (IsIPVersionInRange(pRpcstructurecopy, 0x25130000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS = deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13; + if (IsIPVersionInRange(pRpcstructurecopy, 0x24050000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS = deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05; + if (IsIPVersionInRange(pRpcstructurecopy, 0x24070000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1A070000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES = deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1B050000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1A0D0000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP = deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D; + if (IsIPVersionInRange(pRpcstructurecopy, 0x250E0000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_STATIC_DATA = deserialize_VGPU_STATIC_DATA_v25_0E; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1E020000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02; + if (IsIPVersionInRange(pRpcstructurecopy, 0x250B0000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS = deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1D040000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1C060000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06; + if (IsIPVersionInRange(pRpcstructurecopy, 0x03000000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS = deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00; + if (IsIPVersionInRange(pRpcstructurecopy, 0x12010000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS = deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1D030000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1B050000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1A070000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE = deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07; + if (IsIPVersionInRange(pRpcstructurecopy, 0x210A0000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS = deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A; + if (IsIPVersionInRange(pRpcstructurecopy, 0x25000000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_BSP_GET_CAPS = deserialize_VGPU_BSP_GET_CAPS_v25_00; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1F080000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS = deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08; + if (IsIPVersionInRange(pRpcstructurecopy, 0x24050000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_GPU_PARTITION_INFO = deserialize_GPU_PARTITION_INFO_v24_05; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1E090000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS = deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09; + if (IsIPVersionInRange(pRpcstructurecopy, 0x16000000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS = deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1B050000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1A070000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS = deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1B050000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05; + if (IsIPVersionInRange(pRpcstructurecopy, 0x15020000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS = deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1B010000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_STATIC_PROPERTIES = deserialize_VGPU_STATIC_PROPERTIES_v1B_01; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1C090000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS = deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09; + if (IsIPVersionInRange(pRpcstructurecopy, 0x25010000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS = deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01; + if (IsIPVersionInRange(pRpcstructurecopy, 0x25070000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1A180000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS = deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1A1F0000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F; + if (IsIPVersionInRange(pRpcstructurecopy, 0x24060000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06; + if (IsIPVersionInRange(pRpcstructurecopy, 0x24090000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_CE_GET_CAPS_V2 = deserialize_VGPU_CE_GET_CAPS_V2_v24_09; + if (IsIPVersionInRange(pRpcstructurecopy, 0x1C090000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_VGPU_GET_LATENCY_BUFFER_SIZE = deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09; + if (IsIPVersionInRange(pRpcstructurecopy, 0x25000000, 0xFFFFFFFF)) + pRpcstructurecopyHal->deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS = deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00; + + // Verify each 'dynamically set' interface was actually set + +#define _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(_pHalFn) \ + NV_ASSERT_OR_RETURN_PRECOMP(_pHalFn != (void *) iGrp_ipVersions_UNASSIGNED, NV_ERR_NOT_SUPPORTED) + + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_P2P_CAPABILITY_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_STATIC_DATA); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_BSP_GET_CAPS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_GPU_PARTITION_INFO); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_STATIC_PROPERTIES); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_CE_GET_CAPS_V2); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_GET_LATENCY_BUFFER_SIZE); + _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS); + +#undef _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE + + return NV_OK; +} + + +static NV_STATUS rpcstructurecopy_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo) +{ + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v03_00[] = { + { 0x03000000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v12_01[] = { + { 0x12010000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v15_02[] = { + { 0x15020000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v15_03[] = { + { 0x15030000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v16_00[] = { + { 0x16000000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v18_0B[] = { + { 0x180B0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1A_07[] = { + { 0x1A070000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1A_0D[] = { + { 0x1A0D0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1A_18[] = { + { 0x1A180000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1A_1F[] = { + { 0x1A1F0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1B_01[] = { + { 0x1B010000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1B_05[] = { + { 0x1B050000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1C_06[] = { + { 0x1C060000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1C_09[] = { + { 0x1C090000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1D_03[] = { + { 0x1D030000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1D_04[] = { + { 0x1D040000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1E_02[] = { + { 0x1E020000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1E_09[] = { + { 0x1E090000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1F_01[] = { + { 0x1F010000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1F_08[] = { + { 0x1F080000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v20_04[] = { + { 0x20040000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v21_0A[] = { + { 0x210A0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v21_0C[] = { + { 0x210C0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v22_01[] = { + { 0x22010000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v24_05[] = { + { 0x24050000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v24_06[] = { + { 0x24060000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v24_07[] = { + { 0x24070000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v24_09[] = { + { 0x24090000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_00[] = { + { 0x25000000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_01[] = { + { 0x25010000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_03[] = { + { 0x25030000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_05[] = { + { 0x25050000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_06[] = { + { 0x25060000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_07[] = { + { 0x25070000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_0B[] = { + { 0x250B0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_0E[] = { + { 0x250E0000, 0xFFFFFFFF, }, // + }; + static const IGRP_IP_VERSION_RANGE RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_13[] = { + { 0x25130000, 0xFFFFFFFF, }, // + }; + +#define _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v) \ + { RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_##v, NV_ARRAY_ELEMENTS(RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_##v), rpcstructurecopy_iGrp_ipVersions_Install_##v, } + + static const IGRP_IP_VERSIONS_ENTRY rpcstructurecopy_iGrp_ipVersions_table[] = { + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v03_00), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v12_01), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v15_02), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v15_03), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v16_00), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v18_0B), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1A_07), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1A_0D), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1A_18), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1A_1F), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1B_01), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1B_05), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1C_06), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1C_09), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1D_03), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1D_04), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1E_02), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1E_09), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1F_01), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1F_08), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v20_04), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v21_0A), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v21_0C), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v22_01), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v24_05), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v24_06), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v24_07), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v24_09), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_00), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_01), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_03), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_05), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_06), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_07), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_0B), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_0E), // + _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_13), // + }; + +#undef _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT + + pInfo->pTable = rpcstructurecopy_iGrp_ipVersions_table; + pInfo->numEntries = NV_ARRAY_ELEMENTS(rpcstructurecopy_iGrp_ipVersions_table); + pInfo->ifacesWrapupFn = rpcstructurecopy_iGrp_ipVersions_Wrapup; + + return NV_OK; +} + + +// +// Setup RPCSTRUCTURECOPY's hal interface function pointers +// + +#if defined(RMCFG_HAL_SETUP_TU102) + +static void rpcstructurecopyHalIfacesSetup_TU102(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + + // TU102's RPCSTRUCTURECOPY hal interface function pointer block + static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_TU102 = + { + deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS + deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS + deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB, // deserialize_VGPU_P2P_CAPABILITY_PARAMS + deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS + deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB, // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS + deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB, // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS + deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS + deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS + deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS + deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB, // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS + deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB, // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS + deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB, // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS + deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB, // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP + deserialize_VGPU_STATIC_DATA_STUB, // deserialize_VGPU_STATIC_DATA + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS + deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS + deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB, // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS + deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS + deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB, // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE + deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS + deserialize_VGPU_BSP_GET_CAPS_STUB, // deserialize_VGPU_BSP_GET_CAPS + deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS + deserialize_GPU_PARTITION_INFO_STUB, // deserialize_GPU_PARTITION_INFO + deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB, // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS + deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB, // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS + deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB, // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS + deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS + deserialize_VGPU_STATIC_PROPERTIES_STUB, // deserialize_VGPU_STATIC_PROPERTIES + deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB, // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS + deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS + deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB, // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS + deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB, // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS + deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS + deserialize_VGPU_CE_GET_CAPS_V2_STUB, // deserialize_VGPU_CE_GET_CAPS_V2 + deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB, // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE + deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB, // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS + rpcstructurecopy_iGrp_ipVersions_getInfo, // rpcstructurecopy_iGrp_ipVersions_getInfo + + }; // rpcstructurecopyHalIfacesInitStruct_TU102 + + // init TU102's RPCSTRUCTURECOPY function ptrs using the init struct above + *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_TU102; +} + +#endif // TU10X or TU102 + +#if defined(RMCFG_HAL_SETUP_TU104) + +static void rpcstructurecopyHalIfacesSetup_TU104(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_TU102(pRpcstructurecopyHal); // TU104 interfaces identical to TU102 +} + +#endif // TU10X or TU104 + +#if defined(RMCFG_HAL_SETUP_TU106) + +static void rpcstructurecopyHalIfacesSetup_TU106(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_TU102(pRpcstructurecopyHal); // TU106 interfaces identical to TU102 +} + +#endif // TU10X or TU106 + +#if defined(RMCFG_HAL_SETUP_TU116) + +static void rpcstructurecopyHalIfacesSetup_TU116(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_TU102(pRpcstructurecopyHal); // TU116 interfaces identical to TU102 +} + +#endif // TU10X or TU116 + +#if defined(RMCFG_HAL_SETUP_TU117) + +static void rpcstructurecopyHalIfacesSetup_TU117(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_TU102(pRpcstructurecopyHal); // TU117 interfaces identical to TU102 +} + +#endif // TU10X or TU117 + +#if defined(RMCFG_HAL_SETUP_GA100) + +static void rpcstructurecopyHalIfacesSetup_GA100(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + + // GA100's RPCSTRUCTURECOPY hal interface function pointer block + static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_GA100 = + { + deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS + deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS + deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB, // deserialize_VGPU_P2P_CAPABILITY_PARAMS + deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS + deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB, // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS + deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB, // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS + deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS + deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS + deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS + deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB, // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS + deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB, // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS + deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB, // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS + deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB, // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP + deserialize_VGPU_STATIC_DATA_STUB, // deserialize_VGPU_STATIC_DATA + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS + deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS + deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB, // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS + deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS + deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB, // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE + deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS + deserialize_VGPU_BSP_GET_CAPS_STUB, // deserialize_VGPU_BSP_GET_CAPS + deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS + deserialize_GPU_PARTITION_INFO_STUB, // deserialize_GPU_PARTITION_INFO + deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB, // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS + deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB, // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS + deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB, // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS + deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS + deserialize_VGPU_STATIC_PROPERTIES_STUB, // deserialize_VGPU_STATIC_PROPERTIES + deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB, // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS + deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS + deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB, // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS + deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB, // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS + deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS + deserialize_VGPU_CE_GET_CAPS_V2_STUB, // deserialize_VGPU_CE_GET_CAPS_V2 + deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB, // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE + deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB, // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS + rpcstructurecopy_iGrp_ipVersions_getInfo, // rpcstructurecopy_iGrp_ipVersions_getInfo + + }; // rpcstructurecopyHalIfacesInitStruct_GA100 + + // init GA100's RPCSTRUCTURECOPY function ptrs using the init struct above + *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_GA100; +} + +#endif // GA10X or GA100 + +#if defined(RMCFG_HAL_SETUP_GA102) + +static void rpcstructurecopyHalIfacesSetup_GA102(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal); // GA102 interfaces identical to GA100 +} + +#endif // GA10X or GA102 + +#if defined(RMCFG_HAL_SETUP_GA103) + +static void rpcstructurecopyHalIfacesSetup_GA103(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal); // GA103 interfaces identical to GA100 +} + +#endif // GA10X or GA103 + +#if defined(RMCFG_HAL_SETUP_GA104) + +static void rpcstructurecopyHalIfacesSetup_GA104(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal); // GA104 interfaces identical to GA100 +} + +#endif // GA10X or GA104 + +#if defined(RMCFG_HAL_SETUP_GA106) + +static void rpcstructurecopyHalIfacesSetup_GA106(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal); // GA106 interfaces identical to GA100 +} + +#endif // GA10X or GA106 + +#if defined(RMCFG_HAL_SETUP_GA107) + +static void rpcstructurecopyHalIfacesSetup_GA107(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal); // GA107 interfaces identical to GA100 +} + +#endif // GA10X or GA107 + +#if defined(RMCFG_HAL_SETUP_AD102) + +static void rpcstructurecopyHalIfacesSetup_AD102(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + + // AD102's RPCSTRUCTURECOPY hal interface function pointer block + static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_AD102 = + { + deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS + deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS + deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB, // deserialize_VGPU_P2P_CAPABILITY_PARAMS + deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS + deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB, // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS + deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB, // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS + deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS + deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS + deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS + deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB, // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS + deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB, // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS + deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB, // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS + deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB, // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP + deserialize_VGPU_STATIC_DATA_STUB, // deserialize_VGPU_STATIC_DATA + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS + deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS + deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB, // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS + deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS + deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB, // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE + deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS + deserialize_VGPU_BSP_GET_CAPS_STUB, // deserialize_VGPU_BSP_GET_CAPS + deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS + deserialize_GPU_PARTITION_INFO_STUB, // deserialize_GPU_PARTITION_INFO + deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB, // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS + deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB, // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS + deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB, // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS + deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS + deserialize_VGPU_STATIC_PROPERTIES_STUB, // deserialize_VGPU_STATIC_PROPERTIES + deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB, // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS + deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS + deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB, // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS + deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB, // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS + deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS + deserialize_VGPU_CE_GET_CAPS_V2_STUB, // deserialize_VGPU_CE_GET_CAPS_V2 + deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB, // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE + deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB, // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS + rpcstructurecopy_iGrp_ipVersions_getInfo, // rpcstructurecopy_iGrp_ipVersions_getInfo + + }; // rpcstructurecopyHalIfacesInitStruct_AD102 + + // init AD102's RPCSTRUCTURECOPY function ptrs using the init struct above + *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_AD102; +} + +#endif // AD10X or AD102 + +#if defined(RMCFG_HAL_SETUP_AD103) + +static void rpcstructurecopyHalIfacesSetup_AD103(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_AD102(pRpcstructurecopyHal); // AD103 interfaces identical to AD102 +} + +#endif // AD10X or AD103 + +#if defined(RMCFG_HAL_SETUP_AD104) + +static void rpcstructurecopyHalIfacesSetup_AD104(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_AD102(pRpcstructurecopyHal); // AD104 interfaces identical to AD102 +} + +#endif // AD10X or AD104 + +#if defined(RMCFG_HAL_SETUP_AD106) + +static void rpcstructurecopyHalIfacesSetup_AD106(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_AD102(pRpcstructurecopyHal); // AD106 interfaces identical to AD102 +} + +#endif // AD10X or AD106 + +#if defined(RMCFG_HAL_SETUP_AD107) + +static void rpcstructurecopyHalIfacesSetup_AD107(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + rpcstructurecopyHalIfacesSetup_AD102(pRpcstructurecopyHal); // AD107 interfaces identical to AD102 +} + +#endif // AD10X or AD107 + +#if defined(RMCFG_HAL_SETUP_GH100) + +static void rpcstructurecopyHalIfacesSetup_GH100(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal) +{ + + // GH100's RPCSTRUCTURECOPY hal interface function pointer block + static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_GH100 = + { + deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS + deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS + deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB, // deserialize_VGPU_P2P_CAPABILITY_PARAMS + deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS + deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB, // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS + deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB, // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS + deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS + deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS + deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS + deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB, // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS + deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB, // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS + deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB, // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS + deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB, // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP + deserialize_VGPU_STATIC_DATA_STUB, // deserialize_VGPU_STATIC_DATA + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS + deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS + deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB, // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS + deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS + deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB, // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE + deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS + deserialize_VGPU_BSP_GET_CAPS_STUB, // deserialize_VGPU_BSP_GET_CAPS + deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS + deserialize_GPU_PARTITION_INFO_STUB, // deserialize_GPU_PARTITION_INFO + deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB, // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS + deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB, // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS + deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB, // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS + deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB, // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS + deserialize_VGPU_STATIC_PROPERTIES_STUB, // deserialize_VGPU_STATIC_PROPERTIES + deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB, // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS + deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS + deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB, // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS + deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB, // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS + deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB, // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS + deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB, // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS + deserialize_VGPU_CE_GET_CAPS_V2_STUB, // deserialize_VGPU_CE_GET_CAPS_V2 + deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB, // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE + deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB, // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS + rpcstructurecopy_iGrp_ipVersions_getInfo, // rpcstructurecopy_iGrp_ipVersions_getInfo + + }; // rpcstructurecopyHalIfacesInitStruct_GH100 + + // init GH100's RPCSTRUCTURECOPY function ptrs using the init struct above + *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_GH100; +} + +#endif // GH10X or GH100 + + + + + +#endif // RMCFG_ENGINE_SETUP + + + +// Were any _MOCK interfaces generated into g_rpcstructurecopy_private.h ? +#define RPCSTRUCTURECOPY_MOCK_FUNCTIONS_GENERATED 0 + + +#endif // _G_RPCSTRUCTURECOPY_PRIVATE_H_ diff --git a/src/nvidia/generated/g_rs_client_nvoc.c b/src/nvidia/generated/g_rs_client_nvoc.c index bb29043f76..1b49304ea6 100644 --- a/src/nvidia/generated/g_rs_client_nvoc.c +++ b/src/nvidia/generated/g_rs_client_nvoc.c @@ -131,21 +131,26 @@ void __nvoc_init_RsClient(RsClient *pThis) { __nvoc_init_funcTable_RsClient(pThis); } -NV_STATUS __nvoc_objCreate_RsClient(RsClient **ppThis, Dynamic *pParent, NvU32 createFlags, struct PORT_MEM_ALLOCATOR * arg_pAllocator, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_RsClient(RsClient **ppThis, Dynamic *pParent, NvU32 createFlags, struct PORT_MEM_ALLOCATOR * arg_pAllocator, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RsClient *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsClient), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RsClient)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsClient); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -160,16 +165,25 @@ NV_STATUS __nvoc_objCreate_RsClient(RsClient **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_RsClient(pThis, arg_pAllocator, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_RsClient_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RsClient_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RsClient)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -284,6 +298,10 @@ static NV_STATUS __nvoc_thunk_RsResource_clientresControl_Prologue(struct RsClie return resControl_Prologue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_clientresIsPartialUnmapSupported(struct RsClientResource *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_clientresPreDestruct(struct RsClientResource *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset)); } @@ -304,10 +322,6 @@ static void __nvoc_thunk_RsResource_clientresControl_Epilogue(struct RsClientRes resControl_Epilogue((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_clientresControlLookup(struct RsClientResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_RsResource_clientresMap(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return resMap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_RsClientResource_RsResource.offset), pCallContext, pParams, pCpuMapping); } @@ -375,6 +389,8 @@ static void __nvoc_init_funcTable_RsClientResource_1(RsClientResource *pThis) { pThis->__clientresControl_Prologue__ = &__nvoc_thunk_RsResource_clientresControl_Prologue; + pThis->__clientresIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_clientresIsPartialUnmapSupported; + pThis->__clientresPreDestruct__ = &__nvoc_thunk_RsResource_clientresPreDestruct; pThis->__clientresUnmapFrom__ = &__nvoc_thunk_RsResource_clientresUnmapFrom; @@ -385,8 +401,6 @@ static void __nvoc_init_funcTable_RsClientResource_1(RsClientResource *pThis) { pThis->__clientresControl_Epilogue__ = &__nvoc_thunk_RsResource_clientresControl_Epilogue; - pThis->__clientresControlLookup__ = &__nvoc_thunk_RsResource_clientresControlLookup; - pThis->__clientresMap__ = &__nvoc_thunk_RsResource_clientresMap; pThis->__clientresAccessCallback__ = &__nvoc_thunk_RsResource_clientresAccessCallback; @@ -405,21 +419,26 @@ void __nvoc_init_RsClientResource(RsClientResource *pThis) { __nvoc_init_funcTable_RsClientResource(pThis); } -NV_STATUS __nvoc_objCreate_RsClientResource(RsClientResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_RsClientResource(RsClientResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RsClientResource *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsClientResource), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RsClientResource)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsClientResource); pThis->__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -434,16 +453,25 @@ NV_STATUS __nvoc_objCreate_RsClientResource(RsClientResource **ppThis, Dynamic * status = __nvoc_ctor_RsClientResource(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_RsClientResource_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RsClientResource_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RsClientResource)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_rs_client_nvoc.h b/src/nvidia/generated/g_rs_client_nvoc.h index 03743bd467..24e70e649c 100644 --- a/src/nvidia/generated/g_rs_client_nvoc.h +++ b/src/nvidia/generated/g_rs_client_nvoc.h @@ -69,11 +69,16 @@ MAKE_LIST(AccessBackRefList, AccessBackRef); /** * Information about a client */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RS_CLIENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RsClient { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -86,7 +91,7 @@ struct RsClient { NV_STATUS (*__clientDestructResourceRef__)(struct RsClient *, RsServer *, struct RsResourceRef *); NV_STATUS (*__clientUnmapMemory__)(struct RsClient *, struct RsResourceRef *, struct RS_LOCK_INFO *, struct RsCpuMapping **, API_SECURITY_INFO *); NV_STATUS (*__clientInterMap__)(struct RsClient *, struct RsResourceRef *, struct RsResourceRef *, struct RS_INTER_MAP_PARAMS *); - void (*__clientInterUnmap__)(struct RsClient *, struct RsResourceRef *, struct RS_INTER_UNMAP_PARAMS *); + NV_STATUS (*__clientInterUnmap__)(struct RsClient *, struct RsResourceRef *, struct RS_INTER_UNMAP_PARAMS *); NV_STATUS (*__clientValidateNewResourceHandle__)(struct RsClient *, NvHandle, NvBool); NV_STATUS (*__clientPostProcessPendingFreeList__)(struct RsClient *, struct RsResourceRef **); NV_STATUS (*__clientShareResource__)(struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *, struct CALL_CONTEXT *); @@ -188,10 +193,10 @@ static inline NV_STATUS clientInterMap_DISPATCH(struct RsClient *pClient, struct return pClient->__clientInterMap__(pClient, pMapperRef, pMappableRef, pParams); } -void clientInterUnmap_IMPL(struct RsClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams); +NV_STATUS clientInterUnmap_IMPL(struct RsClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams); -static inline void clientInterUnmap_DISPATCH(struct RsClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams) { - pClient->__clientInterUnmap__(pClient, pMapperRef, pParams); +static inline NV_STATUS clientInterUnmap_DISPATCH(struct RsClient *pClient, struct RsResourceRef *pMapperRef, struct RS_INTER_UNMAP_PARAMS *pParams) { + return pClient->__clientInterUnmap__(pClient, pMapperRef, pParams); } NV_STATUS clientValidateNewResourceHandle_IMPL(struct RsClient *pClient, NvHandle hResource, NvBool bRestrict); @@ -461,11 +466,16 @@ NV_STATUS clientUnmapResourceRefMappings(struct RsClient *pClient, CALL_CONTEXT * proxy resource. * */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RS_CLIENT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RsClientResource { const struct NVOC_RTTI *__nvoc_rtti; struct RsResource __nvoc_base_RsResource; @@ -482,12 +492,12 @@ struct RsClientResource { NV_STATUS (*__clientresControlSerialization_Prologue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__clientresCanCopy__)(struct RsClientResource *); NV_STATUS (*__clientresControl_Prologue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__clientresIsPartialUnmapSupported__)(struct RsClientResource *); void (*__clientresPreDestruct__)(struct RsClientResource *); NV_STATUS (*__clientresUnmapFrom__)(struct RsClientResource *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__clientresIsDuplicate__)(struct RsClientResource *, NvHandle, NvBool *); void (*__clientresControlSerialization_Epilogue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__clientresControl_Epilogue__)(struct RsClientResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__clientresControlLookup__)(struct RsClientResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__clientresMap__)(struct RsClientResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__clientresAccessCallback__)(struct RsClientResource *, struct RsClient *, void *, RsAccessRight); struct RsClient *pClient; @@ -531,12 +541,12 @@ NV_STATUS __nvoc_objCreate_RsClientResource(RsClientResource**, Dynamic*, NvU32, #define clientresControlSerialization_Prologue(pResource, pCallContext, pParams) clientresControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define clientresCanCopy(pResource) clientresCanCopy_DISPATCH(pResource) #define clientresControl_Prologue(pResource, pCallContext, pParams) clientresControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define clientresIsPartialUnmapSupported(pResource) clientresIsPartialUnmapSupported_DISPATCH(pResource) #define clientresPreDestruct(pResource) clientresPreDestruct_DISPATCH(pResource) #define clientresUnmapFrom(pResource, pParams) clientresUnmapFrom_DISPATCH(pResource, pParams) #define clientresIsDuplicate(pResource, hMemory, pDuplicate) clientresIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define clientresControlSerialization_Epilogue(pResource, pCallContext, pParams) clientresControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define clientresControl_Epilogue(pResource, pCallContext, pParams) clientresControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define clientresControlLookup(pResource, pParams, ppEntry) clientresControlLookup_DISPATCH(pResource, pParams, ppEntry) #define clientresMap(pResource, pCallContext, pParams, pCpuMapping) clientresMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define clientresAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) clientresAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool clientresShareCallback_DISPATCH(struct RsClientResource *pResource, struct RsClient *pInvokingClient, RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -579,6 +589,10 @@ static inline NV_STATUS clientresControl_Prologue_DISPATCH(struct RsClientResour return pResource->__clientresControl_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool clientresIsPartialUnmapSupported_DISPATCH(struct RsClientResource *pResource) { + return pResource->__clientresIsPartialUnmapSupported__(pResource); +} + static inline void clientresPreDestruct_DISPATCH(struct RsClientResource *pResource) { pResource->__clientresPreDestruct__(pResource); } @@ -599,10 +613,6 @@ static inline void clientresControl_Epilogue_DISPATCH(struct RsClientResource *p pResource->__clientresControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS clientresControlLookup_DISPATCH(struct RsClientResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__clientresControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS clientresMap_DISPATCH(struct RsClientResource *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { return pResource->__clientresMap__(pResource, pCallContext, pParams, pCpuMapping); } diff --git a/src/nvidia/generated/g_rs_resource_nvoc.c b/src/nvidia/generated/g_rs_resource_nvoc.c index a5865a3a32..4e39eb81ff 100644 --- a/src/nvidia/generated/g_rs_resource_nvoc.c +++ b/src/nvidia/generated/g_rs_resource_nvoc.c @@ -102,8 +102,6 @@ static void __nvoc_init_funcTable_RsResource_1(RsResource *pThis) { pThis->__resPreDestruct__ = &resPreDestruct_IMPL; - pThis->__resControlLookup__ = &resControlLookup_IMPL; - pThis->__resControl__ = &resControl_IMPL; pThis->__resControlFilter__ = &resControlFilter_IMPL; @@ -120,6 +118,8 @@ static void __nvoc_init_funcTable_RsResource_1(RsResource *pThis) { pThis->__resUnmap__ = &resUnmap_IMPL; + pThis->__resIsPartialUnmapSupported__ = &resIsPartialUnmapSupported_bf6dfa; + pThis->__resMapTo__ = &resMapTo_IMPL; pThis->__resUnmapFrom__ = &resUnmapFrom_IMPL; @@ -145,21 +145,26 @@ void __nvoc_init_RsResource(RsResource *pThis) { __nvoc_init_funcTable_RsResource(pThis); } -NV_STATUS __nvoc_objCreate_RsResource(RsResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_RsResource(RsResource **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RsResource *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsResource), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RsResource)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsResource); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -174,16 +179,25 @@ NV_STATUS __nvoc_objCreate_RsResource(RsResource **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_RsResource(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_RsResource_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RsResource_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RsResource)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_rs_resource_nvoc.h b/src/nvidia/generated/g_rs_resource_nvoc.h index c6d1be018d..19acdc00fc 100644 --- a/src/nvidia/generated/g_rs_resource_nvoc.h +++ b/src/nvidia/generated/g_rs_resource_nvoc.h @@ -235,11 +235,16 @@ struct RS_RES_DTOR_PARAMS * Base class for all resources. Mostly a pure virtual interface which * should be overridden to implement resource specific behavior. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RS_RESOURCE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RsResource { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -248,7 +253,6 @@ struct RsResource { NvBool (*__resCanCopy__)(struct RsResource *); NV_STATUS (*__resIsDuplicate__)(struct RsResource *, NvHandle, NvBool *); void (*__resPreDestruct__)(struct RsResource *); - NV_STATUS (*__resControlLookup__)(struct RsResource *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__resControl__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resControlFilter__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resControlSerialization_Prologue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -257,6 +261,7 @@ struct RsResource { void (*__resControl_Epilogue__)(struct RsResource *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__resMap__)(struct RsResource *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NV_STATUS (*__resUnmap__)(struct RsResource *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__resIsPartialUnmapSupported__)(struct RsResource *); NV_STATUS (*__resMapTo__)(struct RsResource *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__resUnmapFrom__)(struct RsResource *, RS_RES_UNMAP_FROM_PARAMS *); NvU32 (*__resGetRefCount__)(struct RsResource *); @@ -299,7 +304,6 @@ NV_STATUS __nvoc_objCreate_RsResource(RsResource**, Dynamic*, NvU32, struct CALL #define resCanCopy(pResource) resCanCopy_DISPATCH(pResource) #define resIsDuplicate(pResource, hMemory, pDuplicate) resIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define resPreDestruct(pResource) resPreDestruct_DISPATCH(pResource) -#define resControlLookup(pResource, pParams, ppEntry) resControlLookup_DISPATCH(pResource, pParams, ppEntry) #define resControl(pResource, pCallContext, pParams) resControl_DISPATCH(pResource, pCallContext, pParams) #define resControlFilter(pResource, pCallContext, pParams) resControlFilter_DISPATCH(pResource, pCallContext, pParams) #define resControlSerialization_Prologue(pResource, pCallContext, pParams) resControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) @@ -308,6 +312,7 @@ NV_STATUS __nvoc_objCreate_RsResource(RsResource**, Dynamic*, NvU32, struct CALL #define resControl_Epilogue(pResource, pCallContext, pParams) resControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define resMap(pResource, pCallContext, pParams, pCpuMapping) resMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define resUnmap(pResource, pCallContext, pCpuMapping) resUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define resIsPartialUnmapSupported(pResource) resIsPartialUnmapSupported_DISPATCH(pResource) #define resMapTo(pResource, pParams) resMapTo_DISPATCH(pResource, pParams) #define resUnmapFrom(pResource, pParams) resUnmapFrom_DISPATCH(pResource, pParams) #define resGetRefCount(pResource) resGetRefCount_DISPATCH(pResource) @@ -332,12 +337,6 @@ static inline void resPreDestruct_DISPATCH(struct RsResource *pResource) { pResource->__resPreDestruct__(pResource); } -NV_STATUS resControlLookup_IMPL(struct RsResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry); - -static inline NV_STATUS resControlLookup_DISPATCH(struct RsResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__resControlLookup__(pResource, pParams, ppEntry); -} - NV_STATUS resControl_IMPL(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams); static inline NV_STATUS resControl_DISPATCH(struct RsResource *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { @@ -386,6 +385,14 @@ static inline NV_STATUS resUnmap_DISPATCH(struct RsResource *pResource, struct C return pResource->__resUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool resIsPartialUnmapSupported_bf6dfa(struct RsResource *pResource) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool resIsPartialUnmapSupported_DISPATCH(struct RsResource *pResource) { + return pResource->__resIsPartialUnmapSupported__(pResource); +} + NV_STATUS resMapTo_IMPL(struct RsResource *pResource, RS_RES_MAP_TO_PARAMS *pParams); static inline NV_STATUS resMapTo_DISPATCH(struct RsResource *pResource, RS_RES_MAP_TO_PARAMS *pParams) { @@ -450,6 +457,17 @@ static inline NV_STATUS resGetFreeParams(struct RsResource *pResource, struct CA #define resGetFreeParams(pResource, ppCallContext, ppParams) resGetFreeParams_IMPL(pResource, ppCallContext, ppParams) #endif //__nvoc_rs_resource_h_disabled +NV_STATUS resControlLookup_IMPL(struct RsResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry); + +#ifdef __nvoc_rs_resource_h_disabled +static inline NV_STATUS resControlLookup(struct RsResource *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { + NV_ASSERT_FAILED_PRECOMP("RsResource was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_rs_resource_h_disabled +#define resControlLookup(pResource, pParams, ppEntry) resControlLookup_IMPL(pResource, pParams, ppEntry) +#endif //__nvoc_rs_resource_h_disabled + #undef PRIVATE_FIELD @@ -572,13 +590,14 @@ struct RS_INTER_UNMAP_PARAMS { NvHandle hClient; NvHandle hMapper; - NvHandle hMappable; NvHandle hDevice; NvU32 flags; NvU64 dmaOffset; ///< [in] RS-TODO rename this - void *pMemDesc; ///< MEMORY_DESCRIPTOR * + NvU64 size; // Internal use only + NvHandle hMappable; + void *pMemDesc; ///< MEMORY_DESCRIPTOR * RS_LOCK_INFO *pLockInfo; ///< [inout] Locking flags and state API_SECURITY_INFO *pSecInfo; ///< [in] Security Info @@ -596,6 +615,7 @@ struct RsInterMapping RsResourceRef *pContextRef; ///< A resource used to provide additional context for the mapping (e.g. hDevice) NvU32 flags; ///< Flags passed when mapping, same flags also passed when unmapping NvU64 dmaOffset; + NvU64 size; void *pMemDesc; }; MAKE_LIST(RsInterMappingList, RsInterMapping); @@ -853,7 +873,6 @@ void refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRe * @param[inout] ppMapping Writes the resulting inter-mapping, if successfully created (Add) or found (Find) * @param[in] pMapping The inter-mapping to remove (Remove) */ -NV_STATUS refFindInterMapping(RsResourceRef *pMapperRef, RsResourceRef *pMappableRef, RsResourceRef *pContextRef, NvU64 dmaOffset, RsInterMapping **ppMapping); NV_STATUS refAddInterMapping(RsResourceRef *pMapperRef, RsResourceRef *pMappableRef, RsResourceRef *pContextRef, RsInterMapping **ppMapping); void refRemoveInterMapping(RsResourceRef *pMapperRef, RsInterMapping *pMapping); diff --git a/src/nvidia/generated/g_rs_server_nvoc.c b/src/nvidia/generated/g_rs_server_nvoc.c index b6306ee351..8e5f578ea2 100644 --- a/src/nvidia/generated/g_rs_server_nvoc.c +++ b/src/nvidia/generated/g_rs_server_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_RsShared(RsShared *pThis) { __nvoc_init_funcTable_RsShared(pThis); } -NV_STATUS __nvoc_objCreate_RsShared(RsShared **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_RsShared(RsShared **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RsShared *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsShared), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RsShared)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsShared); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_RsShared(RsShared **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_RsShared(pThis); if (status != NV_OK) goto __nvoc_objCreate_RsShared_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RsShared_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RsShared)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -277,21 +291,26 @@ void __nvoc_init_RsSession(RsSession *pThis) { __nvoc_init_funcTable_RsSession(pThis); } -NV_STATUS __nvoc_objCreate_RsSession(RsSession **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_RsSession(RsSession **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; RsSession *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(RsSession), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(RsSession)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_RsSession); pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -306,16 +325,25 @@ NV_STATUS __nvoc_objCreate_RsSession(RsSession **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_RsSession(pThis); if (status != NV_OK) goto __nvoc_objCreate_RsSession_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_RsSession_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(RsSession)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_rs_server_nvoc.h b/src/nvidia/generated/g_rs_server_nvoc.h index d39ef2f343..bf7ad94e62 100644 --- a/src/nvidia/generated/g_rs_server_nvoc.h +++ b/src/nvidia/generated/g_rs_server_nvoc.h @@ -67,11 +67,16 @@ struct CLIENT_ENTRY * Base-class for objects that are shared among multiple * RsResources (including RsResources from other clients) */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RS_SERVER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RsShared { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -125,11 +130,16 @@ MAKE_INTRUSIVE_MAP(RsSharedMap, RsShared, node); * that occur on objects which reference an RsSession will * need to acquire pLock first. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_RS_SERVER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct RsSession { const struct NVOC_RTTI *__nvoc_rtti; struct RsShared __nvoc_base_RsShared; @@ -663,10 +673,24 @@ extern NV_STATUS serverAllocApiCopyOut(RsServer *pServer, NV_STATUS status, API_ * Obtain a second client handle to lock if required for the allocation. * @param[in] externalClassId External class ID of resource * @param[in] pAllocParams Class-specific allocation parameters + * @param[out] phSecondClient Second client handle to lock on success + * + * @return NV_OK on success + NV_ERR_INVALID_STATE if allocation is incorrectly configured with RS_FLAGS_DUAL_CLIENT_LOCK without having updated this function. + */ +extern NV_STATUS serverAllocLookupSecondClient(NvU32 externalClassId, void *pAllocParams, NvHandle *phSecondClient); + +/** + * Obtain a second client handle to lock if required for the control (DISCOURAGED). + * @param[in] cmd Control call ID + * @param[in] pControlParams Control-specific parameters + * @param[in] pCookie Control call cookie to check flags for + * @param[out] phSecondClient Second client handle to lock on success * - * @return Second client to lock, if any + * @return NV_OK on success + NV_ERR_INVALID_STATE if allocation is incorrectly configured with RMCTRL_FLAGS_DUAL_CLIENT_LOCK without having updated this function. */ -extern NvHandle serverAllocLookupSecondClient(NvU32 externalClassId, void *pAllocParams); +extern NV_STATUS serverControlLookupSecondClient(NvU32 cmd, void *pControlParams, RS_CONTROL_COOKIE *pCookie, NvHandle *phSecondClient); /** * Acquires a top-level lock. User-implemented. diff --git a/src/nvidia/generated/g_sdk-structures.h b/src/nvidia/generated/g_sdk-structures.h index 7bf71603af..4fcff2a447 100644 --- a/src/nvidia/generated/g_sdk-structures.h +++ b/src/nvidia/generated/g_sdk-structures.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,16 +32,6 @@ // These are copy of sdk structures, that will be used for the communication between the vmioplugin & guest RM. // #if condition can be removed when this file is included in OpenRM-Orin build. #include "vgpu/sdk-structures.h" -typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00 -{ - NvU64 physAddress NV_ALIGN_BYTES(8); - NvU32 numEntries; - NvU32 flags; - NvHandle hVASpace; - NvU32 chId; - NvU32 subDeviceId; -} NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00; - typedef struct NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 { NvU64 physAddress NV_ALIGN_BYTES(8); @@ -76,6 +66,176 @@ typedef struct NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00 typedef NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v03_00 NV0080_CTRL_DMA_UPDATE_PDE_2_PARAMS_v; +typedef struct NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 +{ + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; + NvHandle hVirtMemory; + NvU64 physAddress NV_ALIGN_BYTES(8); + NvU32 physAttr; + NvHandle hDmaHandle; + NvU32 index; + NvU64 size NV_ALIGN_BYTES(8); +} NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00; + +typedef NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 +{ + NvU64 gpuPhysAddr NV_ALIGN_BYTES(8); + NvU64 gpuVirtAddr NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU32 physAttr; + NvU16 bufferId; + NvU8 bInitialize; + NvU8 bNonmapped; +} NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20; + +typedef NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v; + +typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 +{ + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; + NvHandle hVirtMemory; + NvU64 virtAddress NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU32 entryCount; + NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY_v1A_20 promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES]; +} NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20; + +typedef NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 +{ + NvU32 engineType; + NvHandle hClient; + NvU32 ChID; + NvHandle hChanClient; + NvHandle hObject; +} NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00; + +typedef NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v; + +typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00 +{ + NvHandle hClient; + NvHandle hDevice; + NvU32 engine; + NvHandle hVASpace; +} NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00; + +typedef NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00 NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v; + +typedef union NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00 +{ + NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 InitCtx; + NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 EvictCtx; + NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00 InvalidateTlb; +} NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00; + +typedef NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00 NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v; + +typedef struct NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00 +{ + NvHandle hApiHandle; + NvU32 cmd; + NvU32 flags; + NvHandle hClientVA; + NvHandle hDeviceVA; + NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00 api_bundle; +} NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00; + +typedef NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00 NV5080_CTRL_DEFERRED_API_V2_PARAMS_v; + +typedef struct NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00 +{ + NvU32 headIndex; + NvU32 blankingEnabled; +} NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00; + +typedef NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00 NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v; + +typedef struct NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07 +{ + NvU32 headIndex; + NvU32 isPrimary; + NvU32 offset; + NvU32 surfaceType; + NvU32 surfaceBlockHeight; + NvU32 surfacePitch; + NvU32 surfaceFormat; + NvU32 surfaceWidth; + NvU32 surfaceHeight; + NvU32 rectX; + NvU32 rectY; + NvU32 rectWidth; + NvU32 rectHeight; + NvU32 surfaceSize; + NvU32 surfaceKind; + NvU32 hHwResDevice; + NvU32 hHwResHandle; + NvU32 effectiveFbPageSize; +} NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07; + +typedef NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07 NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v; + +typedef struct NV_MEMORY_DESC_PARAMS_v18_01 +{ + NvU64 base NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV_MEMORY_DESC_PARAMS_v18_01; + +typedef NV_MEMORY_DESC_PARAMS_v18_01 NV_MEMORY_DESC_PARAMS_v; + +typedef struct NV_CHANNEL_ALLOC_PARAMS_v1F_04 +{ + NvHandle hObjectError; + NvHandle hObjectBuffer; + NvU64 gpFifoOffset NV_ALIGN_BYTES(8); + NvU32 gpFifoEntries; + NvU32 flags; + NvHandle hContextShare; + NvHandle hVASpace; + NvHandle hUserdMemory[1]; + NvU64 userdOffset[1] NV_ALIGN_BYTES(8); + NvU32 engineType; + NvHandle hObjectEccError; + NV_MEMORY_DESC_PARAMS_v18_01 instanceMem; + NV_MEMORY_DESC_PARAMS_v18_01 ramfcMem; + NV_MEMORY_DESC_PARAMS_v18_01 userdMem; + NV_MEMORY_DESC_PARAMS_v18_01 mthdbufMem; + NvHandle hPhysChannelGroup; + NvHandle subDeviceId; + NvU32 internalFlags; + NV_MEMORY_DESC_PARAMS_v18_01 errorNotifierMem; + NV_MEMORY_DESC_PARAMS_v18_01 eccErrorNotifierMem; +} NV_CHANNEL_ALLOC_PARAMS_v1F_04; + +typedef NV_CHANNEL_ALLOC_PARAMS_v1F_04 NV_CHANNEL_ALLOC_PARAMS_v; + +typedef struct NV_DEVICE_ALLOCATION_PARAMETERS_v03_00 +{ + NvP64 szName NV_ALIGN_BYTES(8); + NvHandle hClientShare; + NvHandle hTargetClient; + NvHandle hTargetDevice; + NvV32 flags; + NvU64 vaSpaceSize NV_ALIGN_BYTES(8); + NvV32 vaMode; + NvU64 vaBase NV_ALIGN_BYTES(8); +} NV_DEVICE_ALLOCATION_PARAMETERS_v03_00; + +typedef NV_DEVICE_ALLOCATION_PARAMETERS_v03_00 NV_DEVICE_ALLOCATION_PARAMETERS_v; + typedef struct NVOS00_PARAMETERS_v03_00 { NvHandle hRoot; @@ -86,6 +246,61 @@ typedef struct NVOS00_PARAMETERS_v03_00 typedef NVOS00_PARAMETERS_v03_00 NVOS00_PARAMETERS_v; +typedef struct NVOS21_PARAMETERS_v03_00 +{ + NvHandle hRoot; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvP64 pAllocParms NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS21_PARAMETERS_v03_00; + +typedef NVOS21_PARAMETERS_v03_00 NVOS21_PARAMETERS_v; + +typedef struct NVOS33_PARAMETERS_v09_0B +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 length NV_ALIGN_BYTES(8); + NvP64 pLinearAddress NV_ALIGN_BYTES(8); + NvU32 status; + NvU32 flags; + NvU64 bar1_offset NV_ALIGN_BYTES(8); +} NVOS33_PARAMETERS_v09_0B; + +typedef NVOS33_PARAMETERS_v09_0B NVOS33_PARAMETERS_v; + +typedef struct NVOS34_PARAMETERS_v03_00 +{ + NvHandle hClient; + NvHandle hDevice; + NvHandle hMemory; + NvP64 pLinearAddress NV_ALIGN_BYTES(8); + NvU32 status; + NvU32 flags; +} NVOS34_PARAMETERS_v03_00; + +typedef NVOS34_PARAMETERS_v03_00 NVOS34_PARAMETERS_v; + +typedef struct NVOS39_PARAMETERS_v03_00 +{ + NvHandle hClient; + NvHandle hObjectParent; + NvHandle hObjectNew; + NvV32 hClass; + NvV32 flags; + NvU32 selector; + NvHandle hMemory; + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvV32 status; +} NVOS39_PARAMETERS_v03_00; + +typedef NVOS39_PARAMETERS_v03_00 NVOS39_PARAMETERS_v; + typedef struct NVOS46_PARAMETERS_v03_00 { NvHandle hClient; @@ -114,6 +329,18 @@ typedef struct NVOS47_PARAMETERS_v03_00 typedef NVOS47_PARAMETERS_v03_00 NVOS47_PARAMETERS_v; +typedef struct NVOS54_PARAMETERS_v03_00 +{ + NvHandle hClient; + NvHandle hObject; + NvRmctrlCmd cmd; + NvP64 params NV_ALIGN_BYTES(8); + NvU32 paramsSize; + NvV32 status; +} NVOS54_PARAMETERS_v03_00; + +typedef NVOS54_PARAMETERS_v03_00 NVOS54_PARAMETERS_v; + typedef struct NVOS55_PARAMETERS_v03_00 { NvHandle hClient; @@ -135,15 +362,6 @@ typedef struct NV2080_CTRL_GR_ROUTE_INFO_v12_01 typedef NV2080_CTRL_GR_ROUTE_INFO_v12_01 NV2080_CTRL_GR_ROUTE_INFO_v; -typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00 -{ - NvHandle hClientTarget; - NvHandle hChannelTarget; - NvU32 reserved00[3]; - NvU32 regOpCount; - NvP64 regOps NV_ALIGN_BYTES(8); -} NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00; - typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 { NvHandle hClientTarget; @@ -173,11 +391,171 @@ typedef struct NV2080_CTRL_GPU_REG_OP_v03_00 typedef NV2080_CTRL_GPU_REG_OP_v03_00 NV2080_CTRL_GPU_REG_OP_v; -typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 +typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C { - NvU32 util; - NvU32 procId; -} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01; + NvU32 frameRateLimiter; + NvU32 swVSyncEnabled; + NvU32 cudaEnabled; + NvU32 pluginPteBlitEnabled; + NvU32 disableWddm1xPreemption; + NvU32 debugBufferSize; + NvP64 debugBuffer NV_ALIGN_BYTES(8); + NvU64 guestFbOffset NV_ALIGN_BYTES(8); + NvU64 mappableCpuHostAperture NV_ALIGN_BYTES(8); + NvU32 linuxInterruptOptimization; + NvU32 vgpuDeviceCapsBits; + NvU32 maxPixels; + NvU32 uvmEnabledFeatures; + NvBool enableKmdSysmemScratch; +} NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C; + +typedef NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v; + +typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00 +{ + char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE]; + NvU32 iHostChangelistNumber; + NvU32 iPluginChangelistNumber; +} NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00; + +typedef NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00 NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00 +{ + NvU32 index; + NvU32 flags; + NvU32 length; + NvU8 data[NV2080_GPU_MAX_GID_LENGTH]; +} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00; + +typedef NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00 NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_v03_00 +{ + NvU32 gpcMask; +} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_v03_00; + +typedef NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_v03_00 NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_v03_00 +{ + NvU32 gpcId; + NvU32 tpcMask; +} NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_v03_00; + +typedef NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_v03_00 NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_v03_00 +{ + NvU32 gpcId; + NvU32 zcullMask; +} NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_v03_00; + +typedef NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_v03_00 NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00 +{ + NvU32 nvlinkPeerIdMask[NV2080_CTRL_BUS_MAX_NUM_GPUS]; +} NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00; + +typedef NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00 NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v03_00 +{ + NvU32 BoardID; + char chipSKU[4]; + char chipSKUMod[2]; + char project[5]; + char projectSKU[5]; + char CDP[6]; + char projectSKUMod[2]; + NvU32 businessCycle; +} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v03_00; + +typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E +{ + NvU32 BoardID; + char chipSKU[9]; + char chipSKUMod[5]; + NvU32 skuConfigVersion; + char project[5]; + char projectSKU[5]; + char CDP[6]; + char projectSKUMod[2]; + NvU32 businessCycle; +} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E; + +typedef NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_PARTITION_SPAN_v18_03 +{ + NvU64 lo NV_ALIGN_BYTES(8); + NvU64 hi NV_ALIGN_BYTES(8); +} NV2080_CTRL_GPU_PARTITION_SPAN_v18_03; + +typedef NV2080_CTRL_GPU_PARTITION_SPAN_v18_03 NV2080_CTRL_GPU_PARTITION_SPAN_v; + +typedef struct GPU_PARTITION_INFO_v24_05 +{ + NvU32 swizzId; + NvU32 grEngCount; + NvU32 veidCount; + NvU32 ceCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 nvDecCount; + NvU32 nvEncCount; + NvU32 nvJpgCount; + NvU32 partitionFlag; + NvU32 smCount; + NvU32 nvOfaCount; + NvU64 memSize NV_ALIGN_BYTES(8); + NvBool bValid; + NV2080_CTRL_GPU_PARTITION_SPAN_v18_03 span; + NvU64 validCTSIdMask NV_ALIGN_BYTES(8); +} GPU_PARTITION_INFO_v24_05; + +typedef GPU_PARTITION_INFO_v24_05 GPU_PARTITION_INFO_v; + +typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v03_00 +{ + NvU64 base NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvU64 reserved NV_ALIGN_BYTES(8); + NvU32 performance; + NvBool supportCompressed; + NvBool supportISO; + NvBool bProtected; + NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG_v03_00 blackList; +} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v03_00; + +typedef NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v03_00 NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v; + +typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00 +{ + NvU32 numFBRegions; + NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO_v03_00 fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES]; +} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00; + +typedef NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00 NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 +{ + NV2080_CTRL_CMD_PERF_VID_ENG engineType; + NvU32 clkPercentBusy; + NvU32 samplingPeriodUs; +} NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00; + +typedef NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v; typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 { @@ -188,24 +566,6 @@ typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 typedef NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v; -typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v06_01 -{ - NvU64 timeStamp NV_ALIGN_BYTES(8); - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 fb; - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 gr; - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 nvenc; - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v06_01 nvdec; -} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v06_01; - -typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00 -{ - NvU64 timeStamp NV_ALIGN_BYTES(8); - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 fb; - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 gr; - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvenc; - NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE_v17_00 nvdec; -} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00; - typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E { NvU64 timeStamp NV_ALIGN_BYTES(8); @@ -217,15 +577,6 @@ typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E typedef NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v; -typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00 -{ - NvU8 type; - NvU32 bufSize; - NvU32 count; - NvU32 tracker; - NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v17_00 samples[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL]; -} NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00; - typedef struct NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E { NvU8 type; @@ -246,6 +597,90 @@ typedef struct NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 typedef NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v; +typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C +{ + NvU32 gpuId; + NvU32 vmPid; + NvU32 state; +} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C; + +typedef NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v; + +typedef struct NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C +{ + NvU32 gpuId; + NvU32 vmPid; + NvU32 newState; +} NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C; + +typedef NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v; + +typedef struct NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C +{ + NvU32 gpuId; + NvU32 vmPid; + NvU32 passIndex; + NvU32 pidCount; + NvU32 pidTable[NV0000_GPUACCT_RPC_PID_MAX_QUERY_COUNT]; +} NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C; + +typedef NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v; + +typedef struct NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C +{ + NvU32 gpuId; + NvU32 pid; + NvU32 subPid; + NvU32 gpuUtil; + NvU32 fbUtil; + NvU64 maxFbUsage NV_ALIGN_BYTES(8); + NvU64 startTime NV_ALIGN_BYTES(8); + NvU64 endTime NV_ALIGN_BYTES(8); +} NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C; + +typedef NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v; + +typedef struct NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C +{ + NvU32 gpuId; + NvU32 vmPid; +} NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C; + +typedef NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v; + +typedef union vgpuGetEngineUtilization_data_v1F_0E +{ + NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 vidPerfmonSample; + NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C getAccountingState; + NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C setAccountingState; + NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v09_0C getAccountingPidList; + NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C procAccountingInfo; + NV0000_CTRL_GPUACCT_CLEAR_ACCOUNTING_DATA_PARAMS_v09_0C clearAccountingInfo; + NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E gpumonPerfmonsampleV2[NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E]; +} vgpuGetEngineUtilization_data_v1F_0E; + +typedef vgpuGetEngineUtilization_data_v1F_0E vgpuGetEngineUtilization_data_v; + +typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_v01_00 +{ + NvU32 totalVFs; + NvU32 firstVfOffset; + NvU32 vfFeatureMask; + NvU64 FirstVFBar0Address NV_ALIGN_BYTES(8); + NvU64 FirstVFBar1Address NV_ALIGN_BYTES(8); + NvU64 FirstVFBar2Address NV_ALIGN_BYTES(8); + NvU64 bar0Size NV_ALIGN_BYTES(8); + NvU64 bar1Size NV_ALIGN_BYTES(8); + NvU64 bar2Size NV_ALIGN_BYTES(8); + NvBool b64bitBar0; + NvBool b64bitBar1; + NvBool b64bitBar2; + NvBool bSriovEnabled; + NvBool bSriovHeavyEnabled; +} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_v01_00; + +typedef NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_v01_00 NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS_v; + typedef struct UpdateBarPde_v15_00 { NV_RPC_UPDATE_PDE_BAR_TYPE barType; @@ -303,137 +738,2499 @@ typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 typedef NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v; -typedef struct gpu_exec_reg_ops_v03_00 +typedef struct NV_DEVICE_NAME_v13_06 { - NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v03_00 reg_op_params; - NV2080_CTRL_GPU_REG_OP_v03_00 operations[]; -} gpu_exec_reg_ops_v03_00; + NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; +} NV_DEVICE_NAME_v13_06; -typedef struct gpu_exec_reg_ops_v12_01 +typedef NV_DEVICE_NAME_v13_06 NV_DEVICE_NAME_v; + +typedef struct NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00 { - NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 reg_op_params; - NV2080_CTRL_GPU_REG_OP_v03_00 operations[]; -} gpu_exec_reg_ops_v12_01; + NvU8 capsTbl[NV0080_CTRL_MSENC_CAPS_TBL_SIZE_V25_00]; + NvU32 instanceId; +} NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00; -typedef gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v; +typedef NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00 NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v; -typedef struct idle_channel_list_v03_00 +typedef struct NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01 { - NvU32 phClient; - NvU32 phDevice; - NvU32 phChannel; -} idle_channel_list_v03_00; + NvU32 engDesc; + NvU32 ctxAttr; + NvU32 ctxBufferSize; + NvU32 addrSpaceList; + NvU32 registerBase; +} NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01; -typedef idle_channel_list_v03_00 idle_channel_list_v; +typedef NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01 NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v; -typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00 +typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01 { - NvHandle hVASpace; - NvU32 subDeviceId; -} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00; + NvU32 numConstructedFalcons; + NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01 constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS_V25_01]; +} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01; -typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 +typedef NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01 NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v; + +typedef struct VGPU_STATIC_PROPERTIES_v1B_01 { - NvHandle hVASpace; - NvU32 subDeviceId; -} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05; + NvU32 encSessionStatsReportingState; + NvBool bProfilingTracingEnabled; + NvBool bDebuggingEnabled; + NvU32 channelCount; + NvBool bPblObjNotPresent; +} VGPU_STATIC_PROPERTIES_v1B_01; -typedef NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v; +typedef VGPU_STATIC_PROPERTIES_v1B_01 VGPU_STATIC_PROPERTIES_v; -typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F +typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE_v20_04 { - NvU32 regOpCount; - NVB0CC_REGOPS_MODE mode; - NvBool bPassed; - NvBool bDirect; - NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NVB0CC_REGOPS_MAX_COUNT]; -} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F; + NvU8 computeSize; + NvU32 gfxGpcCount; + NvU32 gpcCount; + NvU32 veidCount; + NvU32 smCount; +} NV2080_CTRL_GPU_COMPUTE_PROFILE_v20_04; -typedef NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v; +typedef NV2080_CTRL_GPU_COMPUTE_PROFILE_v20_04 NV2080_CTRL_GPU_COMPUTE_PROFILE_v; -typedef struct ATOMIC_OP_v1F_08 +typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04 { - NvBool bSupported; - NvU32 attributes; -} ATOMIC_OP_v1F_08; + NvU32 profileCount; + NV2080_CTRL_GPU_COMPUTE_PROFILE_v20_04 profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE_v20_04]; +} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04; -typedef ATOMIC_OP_v1F_08 ATOMIC_OP_v; +typedef NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04 NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v; -typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 +typedef struct alloc_object_NV50_TESLA_v03_00 { - NvU32 gpuId; - NvU8 gpuUuid[VM_UUID_SIZE_v21_02]; - NvU32 p2pCaps; - NvU32 p2pOptimalReadCEs; - NvU32 p2pOptimalWriteCEs; - NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D]; - NvU32 busPeerId; -} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02; + NvU32 version; + NvU32 flags; + NvU32 size; + NvU32 caps; +} alloc_object_NV50_TESLA_v03_00; -typedef NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v; +typedef alloc_object_NV50_TESLA_v03_00 alloc_object_NV50_TESLA_v; -typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 +typedef struct alloc_object_GT212_DMA_COPY_v03_00 { - NvBool bAllCaps; - NvBool bUseUuid; - NvU32 peerGpuCount; - NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02]; -} NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02; + NvU32 version; + NvU32 engineInstance; +} alloc_object_GT212_DMA_COPY_v03_00; -typedef NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v; +typedef alloc_object_GT212_DMA_COPY_v03_00 alloc_object_GT212_DMA_COPY_v; -typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 +typedef struct alloc_object_GF100_DISP_SW_v03_00 { - NvU32 connectionType; - NvU32 peerId; - NvU32 bSpaAccessOnly; - NvBool bUseUuid; - NvU32 remoteGpuId; - NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02]; -} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03; + NvU32 _reserved1; + NvU64 _reserved2 NV_ALIGN_BYTES(8); + NvU32 logicalHeadId; + NvU32 displayMask; + NvU32 caps; +} alloc_object_GF100_DISP_SW_v03_00; -typedef NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v; +typedef alloc_object_GF100_DISP_SW_v03_00 alloc_object_GF100_DISP_SW_v; -typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 +typedef struct alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 { - NvU32 connectionType; - NvU32 peerId; - NvBool bUseUuid; - NvU32 remoteGpuId; - NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02]; -} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03; + NvU32 hObjectError; + NvU32 hVASpace; + NvU32 engineType; +} alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08; -typedef NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v; +typedef alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 alloc_object_KEPLER_CHANNEL_GROUP_A_v; -typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 +typedef struct alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 { - NvU8 chipletType; - NvU8 chipletIndex; - NvU16 numCredits; -} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08; + NvU32 hVASpace; + NvU32 flags; + NvU32 subctxId; +} alloc_object_FERMI_CONTEXT_SHARE_A_v04_00; -typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v; +typedef alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 alloc_object_FERMI_CONTEXT_SHARE_A_v; -typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 +typedef struct alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 { - NvU8 status; - NvU8 entryIndex; -} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08; + NvU32 size; + NvU32 prohibitMultipleInstances; + NvU32 engineInstance; +} alloc_object_NVD0B7_VIDEO_ENCODER_v03_00; -typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v; +typedef alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 alloc_object_NVD0B7_VIDEO_ENCODER_v; -typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 +typedef struct alloc_object_FERMI_VASPACE_A_v03_00 { - NvU32 numCredits; -} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08; + NvU32 index; + NvU32 flags; + NvU64 vaSize NV_ALIGN_BYTES(8); + NvU32 bigPageSize; + NvU64 vaBase NV_ALIGN_BYTES(8); +} alloc_object_FERMI_VASPACE_A_v03_00; -typedef NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v; +typedef alloc_object_FERMI_VASPACE_A_v03_00 alloc_object_FERMI_VASPACE_A_v; -typedef struct NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 +typedef struct alloc_object_NVB0B0_VIDEO_DECODER_v03_00 { - NvU8 pmaChannelIdx; - NvU8 numEntries; - NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 statusInfo; + NvU32 size; + NvU32 prohibitMultipleInstances; +} alloc_object_NVB0B0_VIDEO_DECODER_v03_00; + +typedef alloc_object_NVB0B0_VIDEO_DECODER_v03_00 alloc_object_NVB0B0_VIDEO_DECODER_v; + +typedef struct alloc_object_NVC4B0_VIDEO_DECODER_v12_02 +{ + NvU32 size; + NvU32 prohibitMultipleInstances; + NvU32 engineInstance; +} alloc_object_NVC4B0_VIDEO_DECODER_v12_02; + +typedef alloc_object_NVC4B0_VIDEO_DECODER_v12_02 alloc_object_NVC4B0_VIDEO_DECODER_v; + +typedef struct alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 +{ + NvHandle hDebuggerClient; + NvHandle hAppClient; + NvHandle hClass3dObject; +} alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00; + +typedef alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 alloc_object_NV83DE_ALLOC_PARAMETERS_v; + +typedef struct alloc_object_NVENC_SW_SESSION_v06_01 +{ + NvU32 codecType; + NvU32 hResolution; + NvU32 vResolution; +} alloc_object_NVENC_SW_SESSION_v06_01; + +typedef alloc_object_NVENC_SW_SESSION_v06_01 alloc_object_NVENC_SW_SESSION_v; + +typedef struct alloc_object_NVFBC_SW_SESSION_v12_04 +{ + NvU32 displayOrdinal; + NvU32 sessionType; + NvU32 sessionFlags; + NvU32 hMaxResolution; + NvU32 vMaxResolution; +} alloc_object_NVFBC_SW_SESSION_v12_04; + +typedef alloc_object_NVFBC_SW_SESSION_v12_04 alloc_object_NVFBC_SW_SESSION_v; + +typedef struct alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 +{ + NvU32 size; + NvU32 prohibitMultipleInstances; + NvU32 engineInstance; +} alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02; + +typedef alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v; + +typedef struct alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 +{ + NvHandle hSubDevice; + NvHandle hPeerSubDevice; + NvU32 subDevicePeerIdMask; + NvU32 peerSubDevicePeerIdMask; + NvU64 mailboxBar1Addr NV_ALIGN_BYTES(8); + NvU32 mailboxTotalSize; + NvU32 flags; +} alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02; + +typedef alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 alloc_object_NV503B_ALLOC_PARAMETERS_v; + +typedef struct alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 +{ + NvU32 flags; + NvU64 p2pToken NV_ALIGN_BYTES(8); +} alloc_object_NV503C_ALLOC_PARAMETERS_v18_15; + +typedef alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 alloc_object_NV503C_ALLOC_PARAMETERS_v; + +typedef struct alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 +{ + NvU32 swizzId; +} alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00; + +typedef alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 alloc_object_NVC637_ALLOCATION_PARAMETERS_v; + +typedef struct alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 +{ + NvU32 execPartitionId; +} alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06; + +typedef alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 alloc_object_NVC638_ALLOCATION_PARAMETERS_v; + +typedef struct alloc_object_NV_FLA_MEMORY_ALLOCATION_PARAMS_v17_04 +{ + NvU32 type; + NvU32 flags; + NvU32 attr; + NvU32 attr2; + NvU64 base NV_ALIGN_BYTES(8); + NvU64 align NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvU32 flagsOs02; + NvHandle hExportSubdevice; + NvHandle hExportHandle; + NvHandle hExportClient; +} alloc_object_NV_FLA_MEMORY_ALLOCATION_PARAMS_v17_04; + +typedef alloc_object_NV_FLA_MEMORY_ALLOCATION_PARAMS_v17_04 alloc_object_NV_FLA_MEMORY_ALLOCATION_PARAMS_v; + +typedef struct alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 +{ + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvHandle hVASpace; +} alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03; + +typedef alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v; + +typedef struct alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 +{ + NvU32 numHeads; + NvU32 numSors; + NvU32 numDsis; +} alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01; + +typedef alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 alloc_object_NVC670_ALLOCATION_PARAMETERS_v; + +typedef struct alloc_object_NVC9FA_VIDEO_OFA_v1F_00 +{ + NvU32 size; + NvU32 prohibitMultipleInstances; +} alloc_object_NVC9FA_VIDEO_OFA_v1F_00; + +typedef alloc_object_NVC9FA_VIDEO_OFA_v1F_00 alloc_object_NVC9FA_VIDEO_OFA_v; + +typedef struct alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 +{ + NvHandle hClientTarget; + NvHandle hContextTarget; +} alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03; + +typedef alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 alloc_object_NVB2CC_ALLOC_PARAMETERS_v; + +typedef struct NV_GR_ALLOCATION_PARAMETERS_v1A_17 +{ + NvU32 version; + NvU32 flags; + NvU32 size; + NvU32 caps; +} NV_GR_ALLOCATION_PARAMETERS_v1A_17; + +typedef NV_GR_ALLOCATION_PARAMETERS_v1A_17 NV_GR_ALLOCATION_PARAMETERS_v; + +typedef struct alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B +{ + NvHandle hClient; + NvHandle hChannel; +} alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B; + +typedef alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v; + +typedef struct NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C +{ + NvU64 offset NV_ALIGN_BYTES(8); + NvHandle hVidMem; + NvU32 flags; +} NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C; + +typedef NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v; + +typedef struct alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C +{ + NvU64 alignment NV_ALIGN_BYTES(8); + NvU64 allocSize NV_ALIGN_BYTES(8); + NvU32 pageSize; + NvU32 allocFlags; + NV00F8_ALLOCATION_PARAMETERS_MAP_STRUCT_v1E_0C map; +} alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C; + +typedef alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C alloc_object_NV00F8_ALLOCATION_PARAMETERS_v; + +typedef struct alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 +{ + NvU32 reserved; +} alloc_object_NV2081_ALLOC_PARAMETERS_v25_08; + +typedef alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 alloc_object_NV2081_ALLOC_PARAMETERS_v; + +typedef union alloc_object_params_v25_08 +{ + alloc_object_NV50_TESLA_v03_00 param_NV50_TESLA; + alloc_object_GT212_DMA_COPY_v03_00 param_GT212_DMA_COPY; + alloc_object_GF100_DISP_SW_v03_00 param_GF100_DISP_SW; + alloc_object_KEPLER_CHANNEL_GROUP_A_v12_08 param_KEPLER_CHANNEL_GROUP_A; + alloc_object_FERMI_CONTEXT_SHARE_A_v04_00 param_FERMI_CONTEXT_SHARE_A; + alloc_object_NVD0B7_VIDEO_ENCODER_v03_00 param_NVD0B7_VIDEO_ENCODER; + alloc_object_FERMI_VASPACE_A_v03_00 param_FERMI_VASPACE_A; + alloc_object_NVB0B0_VIDEO_DECODER_v03_00 param_NVB0B0_VIDEO_DECODER; + alloc_object_NV83DE_ALLOC_PARAMETERS_v03_00 param_NV83DE_ALLOC_PARAMETERS; + alloc_object_NVENC_SW_SESSION_v06_01 param_NVENC_SW_SESSION; + alloc_object_NVC4B0_VIDEO_DECODER_v12_02 param_NVC4B0_VIDEO_DECODER; + alloc_object_NVFBC_SW_SESSION_v12_04 param_NVFBC_SW_SESSION; + alloc_object_NV_NVJPG_ALLOCATION_PARAMETERS_v20_02 param_NV_NVJPG_ALLOCATION_PARAMETERS; + alloc_object_NV503B_ALLOC_PARAMETERS_v1D_02 param_NV503B_ALLOC_PARAMETERS; + alloc_object_NVC637_ALLOCATION_PARAMETERS_v13_00 param_NVC637_ALLOCATION_PARAMETERS; + alloc_object_NV_FLA_MEMORY_ALLOCATION_PARAMS_v17_04 param_NV_FLA_MEMORY_ALLOCATION_PARAMS; + alloc_object_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS_v13_03 param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS; + alloc_object_NVC638_ALLOCATION_PARAMETERS_v18_06 param_NVC638_ALLOCATION_PARAMETERS; + alloc_object_NV503C_ALLOC_PARAMETERS_v18_15 param_NV503C_ALLOC_PARAMETERS; + alloc_object_NVC670_ALLOCATION_PARAMETERS_v1A_01 param_NVC670_ALLOCATION_PARAMETERS; + alloc_object_NVB2CC_ALLOC_PARAMETERS_v1A_03 param_NVB2CC_ALLOC_PARAMETERS; + NV_GR_ALLOCATION_PARAMETERS_v1A_17 param_NV_GR_ALLOCATION_PARAMETERS; + alloc_object_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS_v1A_1B param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS; + alloc_object_NV00F8_ALLOCATION_PARAMETERS_v1E_0C param_NV00F8_ALLOCATION_PARAMETERS; + alloc_object_NVC9FA_VIDEO_OFA_v1F_00 param_NVC9FA_VIDEO_OFA; + alloc_object_NV2081_ALLOC_PARAMETERS_v25_08 param_NV2081_ALLOC_PARAMETERS; +} alloc_object_params_v25_08; + +typedef alloc_object_params_v25_08 alloc_object_params_v; + +typedef struct gpu_exec_reg_ops_v12_01 +{ + NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_v12_01 reg_op_params; + NV2080_CTRL_GPU_REG_OP_v03_00 operations[]; +} gpu_exec_reg_ops_v12_01; + +typedef gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v; + +typedef struct idle_channel_list_v03_00 +{ + NvU32 phClient; + NvU32 phDevice; + NvU32 phChannel; +} idle_channel_list_v03_00; + +typedef idle_channel_list_v03_00 idle_channel_list_v; + +typedef struct NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v03_00 +{ + NvU64 ptePhysAddr NV_ALIGN_BYTES(8); + NvU32 pteCacheAttrib; + NvU32 pteEntrySize; + NvU32 pageSize; + NvU32 pteAddrSpace; + NvU32 pdeVASpaceSize; + NvU32 pdeFlags; +} NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v03_00; + +typedef NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v03_00 NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v; + +typedef struct NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_v03_00 +{ + NvU64 gpuAddr NV_ALIGN_BYTES(8); + NvU64 pdeVirtAddr NV_ALIGN_BYTES(8); + NvU32 pdeEntrySize; + NvU32 pdeAddrSpace; + NvU32 pdeSize; + NvU32 subDeviceId; + NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCK_v03_00 pteBlocks[NV0080_CTRL_DMA_PDE_INFO_PTE_BLOCKS]; + NvU64 pdbAddr NV_ALIGN_BYTES(8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_v03_00; + +typedef NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_v03_00 NV0080_CTRL_DMA_GET_PDE_INFO_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00 +{ + NvHandle hVASpace; + NvU32 flags; +} NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00; + +typedef NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v03_00 NV0080_CTRL_DMA_INVALIDATE_TLB_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 +{ + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00; + +typedef NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_v03_00 +{ + NvU64 vaSpaceSize NV_ALIGN_BYTES(8); + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_v03_00; + +typedef NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_v03_00 NV0080_CTRL_DMA_SET_VA_SPACE_SIZE_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 +{ + NvHandle hVASpace; + NvU32 subDeviceId; +} NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05; + +typedef NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v; + +typedef struct NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v03_00 +{ + NvU32 engineId; + NvU32 alignment; + NvU32 size; +} NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v03_00; + +typedef NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v03_00 NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v; + +typedef struct NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00 +{ + NvU32 engineID; + NvU32 gpEntries; + NvU32 pbEntries; +} NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00; + +typedef NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00 NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v; + +typedef struct VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09 +{ + NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS_v03_00 fifoLatencyBufferSize[NV2080_ENGINE_TYPE_LAST_v1C_09]; +} VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09; + +typedef VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09 VGPU_GET_LATENCY_BUFFER_SIZE_v; + +typedef struct NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 +{ + NvHandle hChannel; + NvU32 property; + NvU64 value NV_ALIGN_BYTES(8); +} NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00; + +typedef NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v; + +typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 +{ + NvU32 flags; + NvHandle hClient; + NvHandle hChannel; + NvU64 vMemPtrs[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END] NV_ALIGN_BYTES(8); + NvU32 gfxpPreemptMode; + NvU32 cilpPreemptMode; + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; +} NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01; + +typedef NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v; + +typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 +{ + NvHandle hClient; + NvHandle hChannel; + NvU64 vMemPtr NV_ALIGN_BYTES(8); + NvU32 zcullMode; +} NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00; + +typedef NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v; + +typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_v12_01 +{ + NvHandle hChannel; + NvHandle hShareClient; + NvHandle hShareChannel; + NvU32 zcullMode; + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; +} NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_v12_01; + +typedef NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_v12_01 NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_v; + +typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01 +{ + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; +} NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01; + +typedef NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01 NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 +{ + NvU32 flags; + NvU32 duration; +} NV2080_CTRL_PERF_BOOST_PARAMS_v03_00; + +typedef NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 NV2080_CTRL_PERF_BOOST_PARAMS_v; + +typedef struct NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_v03_00 +{ + NvU32 currPstate; +} NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_v03_00; + +typedef NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_v03_00 NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_INFO_v25_11 +{ + NvU32 index; + NvU32 data; +} NV2080_CTRL_GPU_INFO_v25_11; + +typedef NV2080_CTRL_GPU_INFO_v25_11 NV2080_CTRL_GPU_INFO_v; + +typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 +{ + NvU32 gpuInfoListSize; + NV2080_CTRL_GPU_INFO_v25_11 gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11]; +} NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11; + +typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v; + +typedef struct NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 +{ + NvU32 exceptType; + NvU32 engineID; +} NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00; + +typedef NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 +{ + NvHandle hTargetChannel; + NvU32 numSMsToClear; +} NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00; + +typedef NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v; + +typedef struct NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 +{ + NvU32 hwwGlobalEsr; + NvU32 hwwWarpEsr; + NvU32 hwwWarpEsrPc; + NvU32 hwwGlobalEsrReportMask; + NvU32 hwwWarpEsrReportMask; + NvU64 hwwEsrAddr NV_ALIGN_BYTES(8); + NvU64 hwwWarpEsrPc64 NV_ALIGN_BYTES(8); + NvU32 hwwCgaEsr; + NvU32 hwwCgaEsrReportMask; +} NV83DE_SM_ERROR_STATE_REGISTERS_v21_06; + +typedef NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 NV83DE_SM_ERROR_STATE_REGISTERS_v; + +typedef struct NV83DE_MMU_FAULT_INFO_v16_03 +{ + NvBool valid; + NvU32 faultInfo; +} NV83DE_MMU_FAULT_INFO_v16_03; + +typedef NV83DE_MMU_FAULT_INFO_v16_03 NV83DE_MMU_FAULT_INFO_v; + +typedef struct NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 +{ + NvHandle hTargetChannel; + NvU32 numSMsToRead; + NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 smErrorStateArray[VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06]; + NvU32 mmuFaultInfo; + NV83DE_MMU_FAULT_INFO_v16_03 mmuFault; + NvU32 startingSM; +} NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06; + +typedef NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 +{ + NvU32 exceptionMask; +} NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00; + +typedef NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v; + +typedef struct NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 +{ + NvU32 engineID; + NvU32 subdeviceInstance; + NvU32 resetReason; +} NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01; + +typedef NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v; + +typedef struct NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_v03_00 +{ + NvHandle hObject; + NvU32 classEngineID; + NvU32 classID; + NvU32 engineID; +} NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_v03_00; + +typedef NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_v03_00 NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS_v; + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00 +{ + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 depth; + NvU32 stencil; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00; + +typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v; + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 +{ + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_value_v04_00 value; + NvU32 indexSize; + NvU32 indexUsed; + NvU32 format; + NvU32 valType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00; + +typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v; + +typedef struct NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 +{ + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 format; +} NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00; + +typedef NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v; + +typedef struct NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 +{ + NvU32 depth; + NvU32 format; +} NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00; + +typedef NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v; + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07 +{ + NvU32 colorFB[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 colorDS[NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE]; + NvU32 depth; + NvU32 stencil; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07; + +typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v; + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 +{ + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_value_v1A_07 value; + NvU32 format; + NvU32 index; + NvBool bIndexValid; + NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE tableType; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07; + +typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v; + +typedef struct NVA06F_CTRL_BIND_PARAMS_v03_00 +{ + NvU32 engineType; +} NVA06F_CTRL_BIND_PARAMS_v03_00; + +typedef NVA06F_CTRL_BIND_PARAMS_v03_00 NVA06F_CTRL_BIND_PARAMS_v; + +typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 +{ + NvBool bEnable; +} NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00; + +typedef NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v; + +typedef struct MMU_FMT_LEVEL_v09_02 +{ + NvU8 virtAddrBitLo; + NvU8 virtAddrBitHi; + NvU8 entrySize ; + NvBool bPageTable; + NvU8 numSubLevels; +} MMU_FMT_LEVEL_v09_02; + +typedef MMU_FMT_LEVEL_v09_02 MMU_FMT_LEVEL_v; + +typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v09_02 +{ + NvU64 physAddress NV_ALIGN_BYTES(8); + NvU32 aperture; + NvU64 size NV_ALIGN_BYTES(8); + MMU_FMT_LEVEL_v09_02 levelFmt; + MMU_FMT_LEVEL_v09_02 sublevelFmt[MMU_FMT_MAX_SUB_LEVELS_v09_02]; +} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v09_02; + +typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v09_02 NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v; + +typedef struct NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_v1A_12 +{ + NvHandle hSubDevice; + NvU32 subDeviceId; + NvU64 virtAddress NV_ALIGN_BYTES(8); + NvU64 pageSize NV_ALIGN_BYTES(8); + NvU32 numLevels; + NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_levels_v09_02 levels[GMMU_FMT_MAX_LEVELS_v1A_12]; +} NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_v1A_12; + +typedef NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_v1A_12 NV90F1_CTRL_VASPACE_GET_PAGE_LEVEL_INFO_PARAMS_v; + +typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 +{ + NvU64 physAddress NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU32 aperture; + NvU8 pageShift; +} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04; + +typedef NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v; + +typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 +{ + NvHandle hSubDevice; + NvU32 subDeviceId; + NvU64 pageSize NV_ALIGN_BYTES(8); + NvU64 virtAddrLo NV_ALIGN_BYTES(8); + NvU64 virtAddrHi NV_ALIGN_BYTES(8); + NvU32 numLevelsToCopy; + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_levels_v1E_04 levels[GMMU_FMT_MAX_LEVELS_v1A_12]; +} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04; + +typedef NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v; + +typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 +{ + NvU32 flags; + NvHandle hChannel; + NvU32 gfxpPreemptMode; + NvU32 cilpPreemptMode; + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; +} NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01; + +typedef NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v; + +typedef struct NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 +{ + NvU64 timesliceUs NV_ALIGN_BYTES(8); +} NVA06C_CTRL_TIMESLICE_PARAMS_v06_00; + +typedef NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 NVA06C_CTRL_TIMESLICE_PARAMS_v; + +typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 +{ + NvBool bDisable; + NvU32 numChannels; + NvBool bOnlyDisableScheduling; + NvBool bRewindGpPut; + NvP64 pRunlistPreemptEvent NV_ALIGN_BYTES(8); + NvHandle hClientList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; + NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES]; +} NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00; + +typedef NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v; + +typedef struct NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_v06_00 +{ + NvHandle hSubDevice; + NvU32 subDeviceId; + NvU64 pageSize NV_ALIGN_BYTES(8); + NvU64 virtAddrLo NV_ALIGN_BYTES(8); + NvU64 virtAddrHi NV_ALIGN_BYTES(8); +} NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_v06_00; + +typedef NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_v06_00 NV90F1_CTRL_VASPACE_RESERVE_ENTRIES_PARAMS_v; + +typedef struct NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_v06_00 +{ + NvHandle hSubDevice; + NvU32 subDeviceId; + NvU64 pageSize NV_ALIGN_BYTES(8); + NvU64 virtAddrLo NV_ALIGN_BYTES(8); + NvU64 virtAddrHi NV_ALIGN_BYTES(8); +} NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_v06_00; + +typedef NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_v06_00 NV90F1_CTRL_VASPACE_RELEASE_ENTRIES_PARAMS_v; + +typedef struct NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 +{ + NvU32 hResolution; + NvU32 vResolution; + NvU32 averageEncodeLatency; + NvU32 averageEncodeFps; + NvU32 timestampBufferSize; + NvP64 timestampBuffer NV_ALIGN_BYTES(8); +} NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01; + +typedef NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v; + +typedef struct NVA0BD_CTRL_NVFBC_TIMESTAMP_v12_04 +{ + NvU64 startTime NV_ALIGN_BYTES(8); + NvU64 endTime NV_ALIGN_BYTES(8); +} NVA0BD_CTRL_NVFBC_TIMESTAMP_v12_04; + +typedef NVA0BD_CTRL_NVFBC_TIMESTAMP_v12_04 NVA0BD_CTRL_NVFBC_TIMESTAMP_v; + +typedef struct NVA082_CTRL_HOST_VGPU_DEVICE_SET_VGPU_FB_USAGE_PARAMS_v07_02 +{ + NvU64 fbUsed NV_ALIGN_BYTES(8); +} NVA082_CTRL_HOST_VGPU_DEVICE_SET_VGPU_FB_USAGE_PARAMS_v07_02; + +typedef NVA082_CTRL_HOST_VGPU_DEVICE_SET_VGPU_FB_USAGE_PARAMS_v07_02 NVA082_CTRL_HOST_VGPU_DEVICE_SET_VGPU_FB_USAGE_PARAMS_v; + +typedef struct NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 +{ + NvU32 workSubmitToken; +} NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00; + +typedef NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00 +{ + NvU32 pageSize; + NvU64 pteEntrySize NV_ALIGN_BYTES(8); + NvU32 comptagLine; + NvU32 kind; + NvU32 pteFlags; +} NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00; + +typedef NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00 NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v; + +typedef struct NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_v09_00 +{ + NvU64 gpuAddr NV_ALIGN_BYTES(8); + NvU32 subDeviceId; + NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00 pteBlocks[NV0080_CTRL_DMA_SET_PTE_INFO_PTE_BLOCKS]; + NvHandle hVASpace; +} NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_v09_00; + +typedef NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_v09_00 NV0080_CTRL_DMA_SET_PTE_INFO_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_v09_00 +{ + NvU64 gpuAddr NV_ALIGN_BYTES(8); + NvU32 subDeviceId; + NvU8 skipVASpaceInit; + NV0080_CTRL_DMA_PTE_INFO_PTE_BLOCK_v09_00 pteBlocks[NV0080_CTRL_DMA_GET_PTE_INFO_PTE_BLOCKS]; + NvHandle hVASpace; +} NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_v09_00; + +typedef NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_v09_00 NV0080_CTRL_DMA_GET_PTE_INFO_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_GET_CAPS_PARAMS_v09_00 +{ + NvU32 capsTblSize; + NvU8 capsTbl[NV0080_CTRL_DMA_CAPS_TBL_SIZE]; +} NV0080_CTRL_DMA_GET_CAPS_PARAMS_v09_00; + +typedef NV0080_CTRL_DMA_GET_CAPS_PARAMS_v09_00 NV0080_CTRL_DMA_GET_CAPS_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_FLUSH_PARAMS_v09_00 +{ + NvU32 targetUnit; +} NV0080_CTRL_DMA_FLUSH_PARAMS_v09_00; + +typedef NV0080_CTRL_DMA_FLUSH_PARAMS_v09_00 NV0080_CTRL_DMA_FLUSH_PARAMS_v; + +typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00 +{ + NvU32 pageTableSize; + NvU32 pageTableCoverage; +} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00; + +typedef NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00 NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v; + +typedef struct NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_v13_02 +{ + NvU32 vaBitCount; + NvU32 pdeCoverageBitCount; + NvU32 num4KPageTableFormats; + NvU32 bigPageSize; + NvU32 compressionPageSize; + NvU32 dualPageTableSupported; + NvU32 idealVRAMPageSize; + NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00 pageTableBigFormat; + NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PAGE_TABLE_FORMAT_v09_00 pageTable4KFormat[NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_MAX_NUM_PAGE_TABLE_FORMATS]; + NvHandle hVASpace; + NvU64 vaRangeLo NV_ALIGN_BYTES(8); + NvU32 vaSpaceId; + NvU64 supportedPageSizeMask NV_ALIGN_BYTES(8); +} NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_v13_02; + +typedef NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_v13_02 NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS_v; + +typedef struct NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_v09_03 +{ + NvU64 bar2Addr[NVC36F_CTRL_CMD_GPFIFO_FAULT_METHOD_BUFFER_MAX_RUNQUEUES] NV_ALIGN_BYTES(8); +} NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_v09_03; + +typedef NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_v09_03 NVC36F_CTRL_GPFIFO_UPDATE_FAULT_METHOD_BUFFER_PARAMS_v; + +typedef struct NV2080_CTRL_FIFO_MEM_INFO_v09_01 +{ + NvU32 aperture; + NvU64 base NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); +} NV2080_CTRL_FIFO_MEM_INFO_v09_01; + +typedef NV2080_CTRL_FIFO_MEM_INFO_v09_01 NV2080_CTRL_FIFO_MEM_INFO_v; + +typedef struct NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v09_01 +{ + NV2080_CTRL_FIFO_MEM_INFO_v09_01 inst; + NV2080_CTRL_FIFO_MEM_INFO_v09_01 ramfc; +} NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v09_01; + +typedef NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v09_01 NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v; + +typedef struct NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_v09_01 +{ + NvHandle hChannel; + NV2080_CTRL_FIFO_CHANNEL_MEM_INFO_v09_01 chMemInfo; +} NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_v09_01; + +typedef NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_v09_01 NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS_v; + +typedef struct NVA06C_CTRL_PREEMPT_PARAMS_v09_0A +{ + NvBool bWait; + NvBool bManualTimeout; + NvU32 timeoutUs; +} NVA06C_CTRL_PREEMPT_PARAMS_v09_0A; + +typedef NVA06C_CTRL_PREEMPT_PARAMS_v09_0A NVA06C_CTRL_PREEMPT_PARAMS_v; + +typedef struct NV0080_CTRL_BSP_GET_CAPS_PARAMS_v09_10 +{ + NvU32 capsTblSize; + NvU32 instanceId; + NvU8 capsTblData[NV0080_CTRL_BSP_CAPS_TBL_SIZE_V09_10]; +} NV0080_CTRL_BSP_GET_CAPS_PARAMS_v09_10; + +typedef NV0080_CTRL_BSP_GET_CAPS_PARAMS_v09_10 NV0080_CTRL_BSP_GET_CAPS_PARAMS_v; + +typedef struct VGPU_BSP_GET_CAPS_v25_00 +{ + NV0080_CTRL_BSP_GET_CAPS_PARAMS_v09_10 bspCaps[MAX_NVDEC_ENGINES_V25_00]; +} VGPU_BSP_GET_CAPS_v25_00; + +typedef VGPU_BSP_GET_CAPS_v25_00 VGPU_BSP_GET_CAPS_v; + +typedef struct NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_v09_03 +{ + NvU32 engineID; +} NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_v09_03; + +typedef NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_v09_03 NV0080_CTRL_FIFO_STOP_RUNLIST_PARAMS_v; + +typedef struct NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_v09_03 +{ + NvU32 engineID; +} NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_v09_03; + +typedef NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_v09_03 NV0080_CTRL_FIFO_START_RUNLIST_PARAMS_v; + +typedef struct NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_v09_03 +{ + NvU64 virtualAddress NV_ALIGN_BYTES(8); + NvU64 beginAddress NV_ALIGN_BYTES(8); + NvU64 endAddress NV_ALIGN_BYTES(8); + NvU64 alignedAddress NV_ALIGN_BYTES(8); + NvU32 pageSize; + NvHandle hVASpace; +} NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_v09_03; + +typedef NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_v09_03 NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS_v; + +typedef struct NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_v10_01 +{ + NvHandle hSubDevice; + NvU32 lineMin; + NvU32 lineMax; + NvU32 format; +} NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_v10_01; + +typedef NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_v10_01 NV0041_CTRL_GET_SURFACE_COMPRESSION_COVERAGE_PARAMS_v; + +typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY_v19_01 +{ + NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES]; + NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; + NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA]; + NvU32 numPbdmas; + char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN]; +} NV2080_CTRL_FIFO_DEVICE_ENTRY_v19_01; + +typedef NV2080_CTRL_FIFO_DEVICE_ENTRY_v19_01 NV2080_CTRL_FIFO_DEVICE_ENTRY_v; + +typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v19_01 +{ + NvU32 baseIndex; + NV2080_CTRL_FIFO_DEVICE_ENTRY_v19_01 entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES]; + NvU32 numEntries; + NvBool bMore; +} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v19_01; + +typedef NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v19_01 NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v; + +typedef struct VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07 +{ + NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_v19_01 fifoDeviceInfoTable[MAX_ITERATIONS_DEVICE_INFO_TABLE]; +} VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07; + +typedef VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07 VGPU_FIFO_GET_DEVICE_INFO_TABLE_v; + +typedef struct NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 +{ + NvU32 waitForEvent; + NvHandle hResidentChannel; +} NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06; + +typedef NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 +{ + NvBool bNonTransactional; + NvU32 regOpCount; + NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS]; +} NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06; + +typedef NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 +{ + NvHandle hClientTarget; + NvHandle hChannelTarget; + NvU32 bNonTransactional; + NvU32 regOpCount; + NvU32 smIds[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07]; + NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07]; + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; +} NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07; + +typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 +{ + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06; + +typedef NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 +{ + NvHandle hTargetChannel; + NvU32 smID; + NV83DE_SM_ERROR_STATE_REGISTERS_v21_06 smErrorState; +} NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06; + +typedef NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 +{ + NvHandle hTargetChannel; + NvU32 smID; +} NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06; + +typedef NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 +{ + NvU32 action; +} NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06; + +typedef NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 +{ + NvU32 stopTriggerType; +} NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06; + +typedef NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v; + +typedef struct ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v16_00 +{ + NvU32 nv2080EngineType; + NvU32 notificationIntrVector; +} ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v16_00; + +typedef ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v16_00 ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v; + +typedef struct NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00 +{ + NvU32 numEntries; + ENGINE_NOTIFICATION_INTR_VECTOR_ENTRY_v16_00 entries[NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES]; +} NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00; + +typedef NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00 NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v; + +typedef struct STATIC_INTR_ENTRY_v1E_09 +{ + NvU32 nv2080IntrType; + NvU32 pmcIntrMask; + NvU32 intrVectorStall; + NvU32 intrVectorNonStall; +} STATIC_INTR_ENTRY_v1E_09; + +typedef STATIC_INTR_ENTRY_v1E_09 STATIC_INTR_ENTRY_v; + +typedef struct NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09 +{ + NvU32 numEntries; + STATIC_INTR_ENTRY_v1E_09 entries[NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09]; +} NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09; + +typedef NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09 NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v; + +typedef struct NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v12_09 +{ + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; + NvU32 engineId; + NvU32 alignment; + NvU32 size; + NvBool bInfoPopulated; +} NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v12_09; + +typedef NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v12_09 NV2080_CTRL_GR_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS_v; + +typedef struct NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 +{ + NvU64 imbPhysAddr NV_ALIGN_BYTES(8); + NvU32 addrSpace; + NvU32 flaAction; +} NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04; + +typedef NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v; + +typedef struct NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_v18_08 +{ + NvU32 engineType; + NvU32 vChid; + NvU32 faultType; +} NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_v18_08; + +typedef NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_v18_08 NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 +{ + NvU64 count NV_ALIGN_BYTES(8); +} NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01; + +typedef NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v; + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 +{ + NvBool enabled; + NvBool scrubComplete; + NvBool supported; + NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 dbe; + NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 dbeNonResettable; + NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 sbe; + NV2080_CTRL_GPU_QUERY_ECC_EXCEPTION_STATUS_v15_01 sbeNonResettable; +} NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01; + +typedef NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v; + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06 +{ + NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 units[NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06]; + NvBool bFatalPoisonError; + NvU32 flags; +} NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06; + +typedef NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06 NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06 +{ + NV2080_CTRL_GPU_QUERY_ECC_UNIT_STATUS_v15_01 units[NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06]; + NvBool bFatalPoisonError; + NvU32 flags; +} NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06; + +typedef NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06 NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v; + +typedef struct NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 +{ + NvU32 engines; +} NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01; + +typedef NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v; + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02 +{ + NvU32 capsTbl; + NvU8 lowestNvlinkVersion; + NvU8 highestNvlinkVersion; + NvU8 lowestNciVersion; + NvU8 highestNciVersion; + NvU32 discoveredLinkMask; + NvU32 enabledLinkMask; +} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02; + +typedef NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v; + +typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 +{ + NvU32 deviceIdFlags; + NvU32 domain; + NvU16 bus; + NvU16 device; + NvU16 function; + NvU32 pciDeviceId; + NvU64 deviceType NV_ALIGN_BYTES(8); + NvU8 deviceUUID[16]; +} NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02; + +typedef NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 NV2080_CTRL_NVLINK_DEVICE_INFO_v; + +typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D +{ + NvU32 capsTbl; + NvU8 phyType; + NvU8 subLinkWidth; + NvU32 linkState; + NvU8 rxSublinkStatus; + NvU8 txSublinkStatus; + NvU8 nvlinkVersion; + NvU8 nciVersion; + NvU8 phyVersion; + NvU32 nvlinkLinkClockKHz; + NvU32 nvlinkLineRateMbps; + NvBool connected; + NvU8 remoteDeviceLinkNumber; + NvU8 localDeviceLinkNumber; + NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 remoteDeviceInfo; + NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 localDeviceInfo; +} NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D; + +typedef NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v; + +typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 +{ + NvU32 enabledLinkMask; + NV2080_CTRL_NVLINK_LINK_STATUS_INFO_v18_0D linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS_v23_04]; +} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04; + +typedef NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v; + +typedef struct NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18 +{ + NvU64 base NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); +} NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18; + +typedef NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18 NV2080_CTRL_FLA_GET_RANGE_PARAMS_v; + +typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v15_02 +{ + NvU32 ceEngineType; + NvU8 capsTbl[NV2080_CTRL_CE_CAPS_TBL_SIZE]; +} NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v15_02; + +typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v15_02 NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v; + +typedef struct VGPU_CE_GET_CAPS_V2_v24_09 +{ + NV2080_CTRL_CE_GET_CAPS_V2_PARAMS_v15_02 ceCaps[NV2080_ENGINE_TYPE_COPY_SIZE_v24_09]; +} VGPU_CE_GET_CAPS_V2_v24_09; + +typedef VGPU_CE_GET_CAPS_V2_v24_09 VGPU_CE_GET_CAPS_V2_v; + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D +{ + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D; + +typedef NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v; + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_v1F_0D +{ + NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS]; + NvU32 gpuCount; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D]; + NvU32 busPeerIds[VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_v1F_0D; + +typedef NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_v1F_0D NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_v; + +typedef struct NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03 +{ + NvU8 fbpIndex; + NvU32 ltcMask; + NvU32 ltcCount; +} NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03; + +typedef NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03 NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v; + +typedef struct NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v15_04 +{ + NvU64 pageAddress NV_ALIGN_BYTES(8); + NvU32 source; + NvU32 status; + NvU32 timestamp; +} NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v15_04; + +typedef NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v15_04 NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v; + +typedef struct NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04 +{ + NV2080_CTRL_FB_OFFLINED_ADDRESS_INFO_v15_04 blackList[NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES]; + NvU32 pageSize; + NvU32 validEntries; + NvBool bRetirementPending; + NvU8 retirementPending; +} NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04; + +typedef NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04 NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_v16_01 +{ + NvU32 statuses; + NvU8 flags; +} NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_v16_01; + +typedef NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_v16_01 NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS_v; + +typedef struct NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 +{ + NvU32 index; +} NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04; + +typedef NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v; + +typedef struct NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 +{ + NvU32 tsgInterleaveLevel; +} NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02; + +typedef NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v; + +typedef struct NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 +{ + NvU32 channelInterleaveLevel; +} NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02; + +typedef NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v; + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 +{ + NvU32 gpcCount; + NvU32 gfxGpcCount; + NvU32 veidCount; + NvU32 ceCount; + NvU32 nvEncCount; + NvU32 nvDecCount; + NvU32 nvJpgCount; + NvU32 ofaCount; + NvU32 sharedEngFlag; + NvU32 smCount; + NvU32 spanStart; + NvU32 computeSize; +} NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05; + +typedef NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 NVC637_CTRL_EXEC_PARTITIONS_INFO_v; + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 +{ + NvBool bQuery; + NvU32 execPartCount; + NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05]; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05]; +} NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05; + +typedef NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v; + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 +{ + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05]; +} NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05; + +typedef NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v; + +typedef struct NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05 +{ + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05]; + NVC637_CTRL_EXEC_PARTITIONS_INFO_v24_05 execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05]; +} NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05; + +typedef NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05 NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v; + +typedef struct NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07 +{ + NvU32 indexStart; + NvU32 indexEnd; +} NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07; + +typedef NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v; + +typedef struct VGPU_STATIC_DATA_v25_0E +{ + NvU64 fbTaxLength NV_ALIGN_BYTES(8); + NvU64 fbLength NV_ALIGN_BYTES(8); + NvU32 fbBusWidth; + NvU32 fbioMask; + NvU32 fbpMask; + NvU32 ltcMask; + NvU32 ltsCount; + NvU32 subProcessIsolation; + NvU64 engineList NV_ALIGN_BYTES(8); + NvU32 sizeL2Cache; + NvBool poisonFuseEnabled; + NvBool guestManagedHwAlloc; + NV_DEVICE_NAME_v13_06 gpuName; + NvBool bSplitVasBetweenServerClientRm; + NvU64 maxSupportedPageSize NV_ALIGN_BYTES(8); + NvBool bFlaSupported; + NvBool bPerRunlistChannelRamEnabled; + NvBool bAtsSupported; + NvBool bPerSubCtxheaderSupported; + NvBool bC2CLinkUp; + NvBool bLocalEgmEnabled; + NvU32 localEgmPeerId; + NvBool bSelfHostedMode; + NvU32 ceFaultMethodBufferDepth; + NvU32 pcieGpuLinkCaps; + NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE_v25_0E]; + NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E]; + NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E]; + NvU32 grBufferSize[RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E]; + NvU8 jpegCaps[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE_V18_0C]; +} VGPU_STATIC_DATA_v25_0E; + +typedef VGPU_STATIC_DATA_v25_0E VGPU_STATIC_DATA_v; + +typedef struct NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 +{ + NvU32 faultType; +} NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09; + +typedef NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v; + +typedef struct rpc_fb_region_descriptor_v17_00 +{ + NvU64 base NV_ALIGN_BYTES(8); + NvU64 limit NV_ALIGN_BYTES(8); + NvBool bRsvdRegion; +} rpc_fb_region_descriptor_v17_00; + +typedef rpc_fb_region_descriptor_v17_00 rpc_fb_region_descriptor_v; + +typedef struct NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A +{ + NvU32 array[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; +} NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A; + +typedef NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v; + +typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A +{ + NvU32 grpACount; + NvU32 grpBCount; + NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; + NV0000_CTRL_P2P_CAPS_MATRIX_ROW_v18_0A b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS]; +} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A; + +typedef NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v; + +typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B +{ + NvU32 eccMask; + NvU32 nvlinkMask ; +} NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B; + +typedef struct NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13 +{ + NvU32 eccMask; + NvU32 nvlinkMask ; +} NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13; + +typedef NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FLA_RANGE_PARAMS_v18_11 +{ + NvU64 base NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU32 mode; + NvU32 hVASpace; +} NV2080_CTRL_FLA_RANGE_PARAMS_v18_11; + +typedef NV2080_CTRL_FLA_RANGE_PARAMS_v18_11 NV2080_CTRL_FLA_RANGE_PARAMS_v; + +typedef struct NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v18_14 +{ + NvU64 pageNumber NV_ALIGN_BYTES(8); + NvU8 source; +} NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v18_14; + +typedef NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v18_14 NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v; + +typedef struct NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v18_14 +{ + NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO_v18_14 blackList[NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES]; + NvU32 validEntries; + NvU32 baseIndex; + NvBool bMore; +} NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v18_14; + +typedef NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v18_14 NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v; + +typedef struct NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_v18_15 +{ + NvHandle hVASpace; + NvU64 vaSpaceToken NV_ALIGN_BYTES(8); +} NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_v18_15; + +typedef NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_v18_15 NV503C_CTRL_REGISTER_VA_SPACE_PARAMS_v; + +typedef struct NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_v18_15 +{ + NvHandle hVASpace; +} NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_v18_15; + +typedef NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_v18_15 NV503C_CTRL_UNREGISTER_VA_SPACE_PARAMS_v; + +typedef struct NV503C_CTRL_REGISTER_VIDMEM_PARAMS_v18_15 +{ + NvHandle hMemory; + NvU64 address NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU64 offset NV_ALIGN_BYTES(8); +} NV503C_CTRL_REGISTER_VIDMEM_PARAMS_v18_15; + +typedef NV503C_CTRL_REGISTER_VIDMEM_PARAMS_v18_15 NV503C_CTRL_REGISTER_VIDMEM_PARAMS_v; + +typedef struct NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_v18_15 +{ + NvHandle hMemory; +} NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_v18_15; + +typedef NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_v18_15 NV503C_CTRL_UNREGISTER_VIDMEM_PARAMS_v; + +typedef struct NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 +{ + NvU32 ceEngineType; + NvU32 pceMask; +} NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07; + +typedef NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_v1A_07 +{ + NvHandle hChannel; + NvU64 totalBufferSize NV_ALIGN_BYTES(8); +} NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_v1A_07; + +typedef NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_v1A_07 NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS_v; + +typedef struct NV2080_CTRL_GR_CTX_BUFFER_INFO_v1A_1A +{ + NvU64 alignment NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvP64 bufferHandle NV_ALIGN_BYTES(8); + NvU64 pageCount NV_ALIGN_BYTES(8); + NvU64 physAddr NV_ALIGN_BYTES(8); + NvU32 bufferType; + NvU32 aperture; + NvU32 kind; + NvU32 pageSize; + NvBool bIsContigous; + NvBool bGlobalBuffer; + NvBool bLocalBuffer; + NvBool bDeviceDescendant; + NvU8 uuid[16]; +} NV2080_CTRL_GR_CTX_BUFFER_INFO_v1A_1A; + +typedef NV2080_CTRL_GR_CTX_BUFFER_INFO_v1A_1A NV2080_CTRL_GR_CTX_BUFFER_INFO_v; + +typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A +{ + NvHandle hUserClient; + NvHandle hChannel; + NvU32 bufferCount; + NV2080_CTRL_GR_CTX_BUFFER_INFO_v1A_1A ctxBufferInfo[GR_MAX_RPC_CTX_BUFFER_COUNT]; +} NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A; + +typedef NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v; + +typedef struct VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07 +{ + NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS_v18_14 fbDynamicBlacklistedPages[MAX_ITERATIONS_DYNAMIC_BLACKLIST]; +} VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07; + +typedef VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07 VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v; + +typedef struct VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D +{ + NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03 fbLtcInfoForFbp[MAX_FBPS]; +} VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D; + +typedef VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D VGPU_FB_GET_LTC_INFO_FOR_FBP_v; + +typedef struct NV2080_CTRL_BUS_INFO_v1A_0F +{ + NvU32 index; + NvU32 data; +} NV2080_CTRL_BUS_INFO_v1A_0F; + +typedef NV2080_CTRL_BUS_INFO_v1A_0F NV2080_CTRL_BUS_INFO_v; + +typedef struct NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09 +{ + NvU32 busInfoListSize; + NV2080_CTRL_BUS_INFO_v1A_0F busInfoList[NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09]; +} NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09; + +typedef NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09 NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_GR_INFO_v1B_04 +{ + NvU32 index; + NvU32 data; +} NV2080_CTRL_INTERNAL_GR_INFO_v1B_04; + +typedef NV2080_CTRL_INTERNAL_GR_INFO_v1B_04 NV2080_CTRL_INTERNAL_GR_INFO_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v24_07 +{ + NV2080_CTRL_INTERNAL_GR_INFO_v1B_04 infoList[NV0080_CTRL_GR_INFO_MAX_SIZE_24_07]; +} NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v24_07; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v24_07 NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_INFO_v24_07 engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07 NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v; + +typedef struct GLOBAL_SM_ID_v1F_01 +{ + NvU16 gpcId; + NvU16 localTpcId; + NvU16 localSmId; + NvU16 globalTpcId; + NvU16 virtualGpcId; + NvU16 migratableTpcId; +} GLOBAL_SM_ID_v1F_01; + +typedef GLOBAL_SM_ID_v1F_01 GLOBAL_SM_ID_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v1F_01 +{ + GLOBAL_SM_ID_v1F_01 globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03]; + NvU16 numSm; + NvU16 numTpc; +} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v1F_01; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v1F_01 NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER_v1F_01 globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01 NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v1B_05 +{ + NvU32 ropUnitCount; + NvU32 ropOperationsFactor; + NvU32 ropOperationsCount; +} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v1B_05; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO_v1B_05 engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v1C_06 +{ + NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03]; +} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v1C_06; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v1C_06 NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS_v1C_06 enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v1B_05 +{ + NvU32 size; + NvU32 alignment; +} NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v1B_05; + +typedef NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v1B_05 NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v25_07 +{ + NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO_v1B_05 engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07]; +} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v25_07; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v25_07 NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO_v25_07 engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07 NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v1B_05 +{ + NvU8 imla0; + NvU8 fmla16; + NvU8 dp; + NvU8 fmla32; + NvU8 ffma; + NvU8 imla1; + NvU8 imla2; + NvU8 imla3; + NvU8 imla4; +} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v1B_05; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_v1B_05 smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v1D_03 +{ + NvU32 gpcMask; + NvU32 tpcMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03]; + NvU32 tpcCount[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03]; + NvU32 physGpcMask; + NvU32 mmuPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03]; + NvU32 tpcToPesMap[NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03]; + NvU32 numPesPerGpc[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03]; + NvU32 zcullMask[NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03]; +} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v1D_03; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v1D_03 NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS_v1D_03 floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v1B_05 +{ + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; +} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v1B_05; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO_v1B_05 engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v1B_05 +{ + NvU32 fecsRecordSize; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v1B_05; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_v1B_05 fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v1D_04 +{ + NvU32 fecsRecordSize; + NvU32 timestampHiTagMask; + NvU8 timestampHiTagShift; + NvU64 timestampVMask NV_ALIGN_BYTES(8); + NvU8 numLowerBitsZeroShift; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v1D_04; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v1D_04 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_v1D_04 fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04 NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v1E_02 +{ + NvBool bPerSubCtxheaderSupported; +} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v1E_02; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v1E_02 NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v; + +typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02 +{ + NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES_v1E_02 pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04]; +} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02; + +typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02 NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v; + +typedef struct NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F +{ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F; + +typedef NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v; + +typedef struct NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F +{ + NvBool ctxsw; +} NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F; + +typedef NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v; + +typedef struct NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F +{ + NvU32 regOpCount; + NVB0CC_REGOPS_MODE mode; + NvBool bPassed; + NvBool bDirect; + NV2080_CTRL_GPU_REG_OP_v03_00 regOps[NVB0CC_REGOPS_MAX_COUNT]; +} NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F; + +typedef NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v; + +typedef struct NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 +{ + NvHandle hMemPmaBuffer; + NvU64 pmaBufferOffset NV_ALIGN_BYTES(8); + NvU64 pmaBufferSize NV_ALIGN_BYTES(8); + NvHandle hMemPmaBytesAvailable; + NvU64 pmaBytesAvailableOffset NV_ALIGN_BYTES(8); + NvBool ctxsw; + NvU32 pmaChannelIdx; + NvU64 pmaBufferVA NV_ALIGN_BYTES(8); +} NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14; + +typedef NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v; + +typedef struct NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 +{ + NvU64 bytesConsumed NV_ALIGN_BYTES(8); + NvBool bUpdateAvailableBytes; + NvBool bWait; + NvU64 bytesAvailable NV_ALIGN_BYTES(8); + NvBool bReturnPut; + NvU64 putPtr NV_ALIGN_BYTES(8); + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14; + +typedef NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v; + +typedef struct NV2080_CTRL_FB_INFO_v1A_15 +{ + NvU32 index; + NvU32 data; +} NV2080_CTRL_FB_INFO_v1A_15; + +typedef NV2080_CTRL_FB_INFO_v1A_15 NV2080_CTRL_FB_INFO_v; + +typedef struct NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A +{ + NvU32 fbInfoListSize; + NV2080_CTRL_FB_INFO_v1A_15 fbInfoList[NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A]; +} NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A; + +typedef NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v; + +typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_v1A_1A +{ + NvHandle hUserClient; + NvHandle hChannel; + NvU32 bufferType; + NvU32 firstPage; + NvU32 numPages; + NvU64 physAddrs[NV2080_CTRL_KGR_MAX_BUFFER_PTES] NV_ALIGN_BYTES(8); + NvBool bNoMorePages; +} NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_v1A_1A; + +typedef NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_v1A_1A NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D +{ + NvU8 data[NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D]; +} NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D +{ + NvU32 swizzId; + NvU64 fbpEnMask NV_ALIGN_BYTES(8); +} NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 ltcEnMask; +} NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 ltsEnMask; +} NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 fbpaEnMask; +} NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 ropEnMask; +} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 swizzId; + NvU32 ltcEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 swizzId; + NvU32 ltsEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 swizzId; + NvU32 fbpaEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 swizzId; + NvU32 ropEnMask; +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 swizzId; + NvU64 fbpaSubpEnMask NV_ALIGN_BYTES(8); +} NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 fbpaSubpEnMask; +} NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D +{ + NvU32 fbpIndex; + NvU32 fbpLogicalIndex; +} NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v; + +typedef union NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D +{ + NV2080_CTRL_FB_FS_INFO_INVALID_QUERY_PARAMS_v1A_1D inv; + NV2080_CTRL_FB_FS_INFO_FBP_MASK_PARAMS_v1A_1D fbp; + NV2080_CTRL_FB_FS_INFO_LTC_MASK_PARAMS_v1A_1D ltc; + NV2080_CTRL_FB_FS_INFO_LTS_MASK_PARAMS_v1A_1D lts; + NV2080_CTRL_FB_FS_INFO_FBPA_MASK_PARAMS_v1A_1D fbpa; + NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS_v1A_1D rop; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK_PARAMS_v1A_1D dmLtc; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK_PARAMS_v1A_1D dmLts; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK_PARAMS_v1A_1D dmFbpa; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK_PARAMS_v1A_1D dmRop; + NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK_PARAMS_v1A_1D dmFbpaSubp; + NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK_PARAMS_v1A_1D fbpaSubp; + NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP_PARAMS_v1A_1D fbpLogicalMap; +} NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v; + +typedef struct NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D +{ + NvU16 queryType; + NvU8 reserved[2]; + NvU32 status; + NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D queryParams; +} NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D; + +typedef NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D NV2080_CTRL_FB_FS_INFO_QUERY_v; + +typedef struct NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 +{ + NvU16 numQueries; + NvU8 reserved[6]; + NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D queries[NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00]; +} NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00; + +typedef NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D +{ + NvU32 gpcCount; +} NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D +{ + NvU32 gpcId; + NvU32 chipletGpcMap; +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D +{ + NvU32 gpcId; + NvU32 tpcMask; +} NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D +{ + NvU32 gpcId; + NvU32 ppcMask; +} NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D +{ + NvU32 swizzId; + NvU32 gpcId; + NvU32 chipletGpcMap; +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D +{ + NvU32 chipletSyspipeMask; +} NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D +{ + NvU16 swizzId; + NvU16 physSyspipeIdCount; + NvU8 physSyspipeId[NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D]; +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D +{ + NvU32 swizzId; + NvU32 grIdx; + NvU32 gpcEnMask; +} NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D +{ + NvU32 syspipeId; +} NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D +{ + NvU32 gpcId; + NvU32 ropMask; +} NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v; + +typedef union NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D +{ + NV2080_CTRL_GRMGR_GR_FS_INFO_GPC_COUNT_PARAMS_v1A_1D gpcCountData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_GPC_MAP_PARAMS_v1A_1D chipletGpcMapData; + NV2080_CTRL_GRMGR_GR_FS_INFO_TPC_MASK_PARAMS_v1A_1D tpcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PPC_MASK_PARAMS_v1A_1D ppcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_GPC_MAP_PARAMS_v1A_1D partitionGpcMapData; + NV2080_CTRL_GRMGR_GR_FS_INFO_CHIPLET_SYSPIPE_MASK_PARAMS_v1A_1D syspipeMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_CHIPLET_SYSPIPE_IDS_PARAMS_v1A_1D partitionChipletSyspipeData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PROFILER_MON_GPC_MASK_PARAMS_v1A_1D dmGpcMaskData; + NV2080_CTRL_GRMGR_GR_FS_INFO_PARTITION_SYSPIPE_ID_PARAMS_v1A_1D partitionSyspipeIdData; + NV2080_CTRL_GRMGR_GR_FS_INFO_ROP_MASK_PARAMS_v1A_1D ropMaskData; +} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v; + +typedef struct NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D +{ + NvU16 queryType; + NvU8 reserved[2]; + NvU32 status; + NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D queryData; +} NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v; + +typedef struct NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D +{ + NvU16 numQueries; + NvU8 reserved[6]; + NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D queries[NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D]; +} NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D; + +typedef NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v; + +typedef struct NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E +{ + NvBool bImmediate; +} NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E; + +typedef NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E NVA06F_CTRL_STOP_CHANNEL_PARAMS_v; + +typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F +{ + NvHandle hChannel; + NvU32 samplingMode; + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; +} NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F; + +typedef NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v; + +typedef struct NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F +{ + NvBool bSetMaxFreq; +} NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F; + +typedef NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v; + +typedef struct PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F +{ + NvU32 clientActiveMask; + NvU8 bRegkeyLimitRatedTdp; +} PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F; + +typedef PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v; + +typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F +{ + PERF_RATED_TDP_RM_INTERNAL_STATE_STRUCT_v1A_1F rm; + NV2080_CTRL_PERF_RATED_TDP_ACTION output; + NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F]; +} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F; + +typedef NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v; + +typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F +{ + NV2080_CTRL_PERF_RATED_TDP_CLIENT client; + NV2080_CTRL_PERF_RATED_TDP_ACTION input; +} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F; + +typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v; + +typedef struct NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F +{ + NvU32 pmaChannelIdx; +} NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F; + +typedef NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v; + +typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F +{ + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; + NvU8 imla0; + NvU8 fmla16; + NvU8 dp; + NvU8 fmla32; + NvU8 ffma; + NvU8 imla1; + NvU8 imla2; + NvU8 imla3; + NvU8 imla4; +} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F; + +typedef NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v; + +typedef struct NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 +{ + NvU64 base NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU32 addressSpace; + NvU32 cacheAttrib; +} NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23; + +typedef NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 +{ + NvU32 smID; + NvBool bSingleStep; +} NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02; + +typedef NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v; + +typedef struct NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 +{ + NvHandle hChannelGroup; + NV0080_CTRL_GR_TPC_PARTITION_MODE mode; + NvBool bEnableAllTpcs; + NV2080_CTRL_GR_ROUTE_INFO_v12_01 grRouteInfo; +} NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04; + +typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v; + +typedef struct NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 +{ + NvU32 pmaChannelIdx; + NvBool bMembytesPollingRequired; +} NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08; + +typedef NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v; + +typedef struct NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C +{ + NvU32 pmaChannelIdx; + NvU64 pmaBufferVA NV_ALIGN_BYTES(8); + NvU64 pmaBufferSize NV_ALIGN_BYTES(8); + NvU64 membytesVA NV_ALIGN_BYTES(8); + NvU64 hwpmIBPA NV_ALIGN_BYTES(8); + NvU8 hwpmIBAperture; +} NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C; + +typedef NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v; + +typedef struct NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 +{ + NvBool bMode; +} NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06; + +typedef NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 +{ + NvU64 base NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvU64 alignment NV_ALIGN_BYTES(8); + NvU32 addressSpace; + NvU32 cpuCacheAttrib; +} NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07; + +typedef NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 NV2080_CTRL_INTERNAL_MEMDESC_INFO_v; + +typedef struct NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 +{ + NV2080_CTRL_INTERNAL_MEMDESC_INFO_v1E_07 methodBufferMemdesc[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07]; + NvU64 bar2Addr[NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07] NV_ALIGN_BYTES(8); + NvU32 numValidEntries; +} NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07; + +typedef NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v; + +typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A +{ + NvHandle hChannel; + NvU64 totalBufferSize NV_ALIGN_BYTES(8); +} NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A; + +typedef NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v; + +typedef struct NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A +{ + NvHandle hUserClient; + NvHandle hChannel; + NvU64 alignment NV_ALIGN_BYTES(8); + NvU64 size NV_ALIGN_BYTES(8); + NvP64 bufferHandle NV_ALIGN_BYTES(8); + NvU64 pageCount NV_ALIGN_BYTES(8); + NvU64 physAddr NV_ALIGN_BYTES(8); + NvU32 aperture; + NvU32 kind; + NvU32 pageSize; + NvBool bIsContigous; + NvBool bDeviceDescendant; + NvU8 uuid[16]; +} NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A; + +typedef NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v; + +typedef struct NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 +{ + NvBool bZbcSurfacesExist; +} NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05; + +typedef NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v; + +typedef struct NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C +{ + NvU64 offset NV_ALIGN_BYTES(8); + NvU64 totalPfns NV_ALIGN_BYTES(8); + NvU32 pfnArray[NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE]; + NvU32 numPfns; +} NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C; + +typedef NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C NV00F8_CTRL_DESCRIBE_PARAMS_v; + +typedef struct NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C +{ + NvU64 totalSize NV_ALIGN_BYTES(8); + NvU64 freeSize NV_ALIGN_BYTES(8); +} NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C; + +typedef NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v; + +typedef struct ATOMIC_OP_v1F_08 +{ + NvBool bSupported; + NvU32 attributes; +} ATOMIC_OP_v1F_08; + +typedef ATOMIC_OP_v1F_08 ATOMIC_OP_v; + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08 +{ + ATOMIC_OP_v1F_08 atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08]; +} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08; + +typedef NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08 NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v; + +typedef struct NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 +{ + NvU32 gpuId; + NvU8 gpuUuid[VM_UUID_SIZE_v21_02]; + NvU32 p2pCaps; + NvU32 p2pOptimalReadCEs; + NvU32 p2pOptimalWriteCEs; + NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D]; + NvU32 busPeerId; +} NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02; + +typedef NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v; + +typedef struct NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 +{ + NvBool bAllCaps; + NvBool bUseUuid; + NvU32 peerGpuCount; + NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO_v21_02 peerGpuCaps[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02]; +} NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02; + +typedef NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v; + +typedef struct NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 +{ + NvU32 connectionType; + NvU32 peerId; + NvU32 bSpaAccessOnly; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02]; +} NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03; + +typedef NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v; + +typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 +{ + NvU32 connectionType; + NvU32 peerId; + NvBool bUseUuid; + NvU32 remoteGpuId; + NvU8 remoteGpuUuid[VM_UUID_SIZE_v21_02]; +} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03; + +typedef NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 +{ + NvU8 chipletType; + NvU8 chipletIndex; + NvU16 numCredits; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08; + +typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v; + +typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 +{ + NvU8 status; + NvU8 entryIndex; +} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08; + +typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v; + +typedef struct NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 +{ + NvU32 numCredits; +} NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08; + +typedef NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v; + +typedef struct NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 +{ + NvU8 pmaChannelIdx; + NvU8 numEntries; + NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS_v21_08 statusInfo; NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 creditInfo[NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08]; } NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08; @@ -506,10 +3303,398 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v; +typedef struct VGPU_P2P_CAPABILITY_PARAMS_v25_03 +{ + NvBool bGpuSupportsFabricProbe; +} VGPU_P2P_CAPABILITY_PARAMS_v25_03; + +typedef VGPU_P2P_CAPABILITY_PARAMS_v25_03 VGPU_P2P_CAPABILITY_PARAMS_v; + +typedef struct NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 +{ + NvU32 value; +} NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04; + +typedef NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05 +{ + NvU32 faultId; + NvU32 instanceId; + NvU32 typeEnum; + NvU32 resetId; + NvU32 devicePriBase; + NvU32 isEngine; + NvU32 rlEngId; + NvU32 runlistPriBase; + NvU32 groupId; +} NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05; + +typedef NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05 NV2080_CTRL_INTERNAL_DEVICE_INFO_v; + +typedef struct NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05 +{ + NvU32 numEntries; + NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05 deviceInfoTable[NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES_V25_05]; +} NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05; + +typedef NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05 NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v; + +typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06 +{ + NvBool bOneToOneComptagLineAllocation; + NvBool bUseOneToFourComptagLineAllocation; + NvBool bUseRawModeComptaglineAllocation; + NvBool bDisableCompbitBacking; + NvBool bDisablePostL2Compression; + NvBool bEnabledEccFBPA; + NvBool bL2PreFill; + NvU64 l2CacheSize NV_ALIGN_BYTES(8); + NvBool bFbpaPresent; + NvU32 comprPageSize; + NvU32 comprPageShift; + NvU32 ramType; + NvU32 ltcCount; + NvU32 ltsPerLtcCount; +} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06; + +typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06 NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v; + +typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B +{ + NvU32 atomicsCaps; +} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B; + +typedef NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v; + +typedef struct NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C +{ + NvU32 dataSize; + NvU8 data[512]; +} NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C; + +typedef NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v; + #endif #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS +// Union member index functions for NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle +uint32_t _get_union_member_index_NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00(NvU32 cmd) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_GPU_INITIALIZE_CTX: + return 0; // "InitCtx" + + case NV2080_CTRL_CMD_GPU_PROMOTE_CTX: + return 1; // "PromoteCtx" + + case NV2080_CTRL_CMD_GPU_EVICT_CTX: + return 2; // "EvictCtx" + + case NV2080_CTRL_CMD_DMA_INVALIDATE_TLB: + return 3; // "InvalidateTlb" + + default: + return UNION_UNKNOWN_FIELD_PRINT; + } +} + + + + +// Union member index functions for vgpuGetEngineUtilization_data +uint32_t _get_union_member_index_vgpuGetEngineUtilization_data_v1F_0E(NvU32 cmd) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_PERF_GET_PERFMON_SAMPLE: + return 0; // "perfmonSample" + + case NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE: + return 1; // "vidPerfmonSample" + + case NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE: + return 3; // "getAccountingState" + + case NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE: + return 4; // "setAccountingState" + + case NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS: + return 5; // "getAccountingPidList" + + case NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO: + return 6; // "procAccountingInfo" + + case NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA: + return 7; // "clearAccountingInfo" + + case NV2080_CTRL_CMD_PERF_GET_PERFMON_SAMPLE_V3: + return 8; // "perfmonSampleV3" + + case NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2: + return 9; // "gpumonPerfmonsampleV2" + + default: + return UNION_UNKNOWN_FIELD_PRINT; + } +} + + + + +// Union member index functions for alloc_object_params +uint32_t _get_union_member_index_alloc_object_params_v25_08(NvU32 cmd) +{ + switch (cmd) + { + case G82_TESLA: + case GT200_TESLA: + case GT214_TESLA: + case NV50_TESLA: + case FERMI_A: + case KEPLER_A: + case KEPLER_B: + case MAXWELL_A: + case MAXWELL_B: + case PASCAL_A: + case PASCAL_B: + case VOLTA_A: + case TURING_A: + case AMPERE_A: + return 0; // "param_NV50_TESLA" + + case KEPLER_DMA_COPY_A: + case MAXWELL_DMA_COPY_A: + case PASCAL_DMA_COPY_A: + case VOLTA_DMA_COPY_A: + case TURING_DMA_COPY_A: + case AMPERE_DMA_COPY_A: + return 1; // "param_GT212_DMA_COPY" + + case GF100_MSPPP: + return 2; // "param_G98_MSPPP" + + case GF100_DISP_SW: + return 3; // "param_GF100_DISP_SW" + + case KEPLER_CHANNEL_GROUP_A: + return 4; // "param_KEPLER_CHANNEL_GROUP_A" + + case FERMI_CONTEXT_SHARE_A: + return 5; // "param_FERMI_CONTEXT_SHARE_A" + + case NVD0B7_VIDEO_ENCODER: + case NVC1B7_VIDEO_ENCODER: + case NVC2B7_VIDEO_ENCODER: + case NVC3B7_VIDEO_ENCODER: + case NVC4B7_VIDEO_ENCODER: + case NVC7B7_VIDEO_ENCODER: + case NVC9B7_VIDEO_ENCODER: + return 6; // "param_NVD0B7_VIDEO_ENCODER" + + case FERMI_VASPACE_A: + return 7; // "param_FERMI_VASPACE_A" + + case NVA0B0_VIDEO_DECODER: + case NVB0B0_VIDEO_DECODER: + case NVC1B0_VIDEO_DECODER: + case NVC2B0_VIDEO_DECODER: + case NVC3B0_VIDEO_DECODER: + case NV95B1_VIDEO_MSVLD: + return 8; // "param_NVB0B0_VIDEO_DECODER" + + case NV95B2_VIDEO_MSPDEC: + return 9; // "param_NV95B2_VIDEO_MSPDEC" + + case GT200_DEBUGGER: + return 10; // "param_NV83DE_ALLOC_PARAMETERS" + + case NVENC_SW_SESSION: + return 11; // "param_NVENC_SW_SESSION" + + case NVC4B0_VIDEO_DECODER: + case NVC6B0_VIDEO_DECODER: + case NVC7B0_VIDEO_DECODER: + case NVB8B0_VIDEO_DECODER: + case NVC9B0_VIDEO_DECODER: + case NVCDB0_VIDEO_DECODER: + return 12; // "param_NVC4B0_VIDEO_DECODER" + + case NVFBC_SW_SESSION: + return 13; // "param_NVFBC_SW_SESSION" + + case NVC4D1_VIDEO_NVJPG: + case NVB8D1_VIDEO_NVJPG: + case NVC9D1_VIDEO_NVJPG: + case NVCDD1_VIDEO_NVJPG: + return 14; // "param_NV_NVJPG_ALLOCATION_PARAMETERS" + + case NV50_P2P: + return 15; // "param_NV503B_ALLOC_PARAMETERS" + + case AMPERE_SMC_PARTITION_REF: + return 16; // "param_NVC637_ALLOCATION_PARAMETERS" + + case NV01_MEMORY_FLA: + return 17; // "param_NV_FLA_MEMORY_ALLOCATION_PARAMS" + + case NV01_MEMORY_VIRTUAL: + return 18; // "param_NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS" + + case AMPERE_SMC_EXEC_PARTITION_REF: + return 19; // "param_NVC638_ALLOCATION_PARAMETERS" + + case NV50_THIRD_PARTY_P2P: + return 20; // "param_NV503C_ALLOC_PARAMETERS" + + case NVC670_DISPLAY: + return 21; // "param_NVC670_ALLOCATION_PARAMETERS" + + case NVC67B_WINDOW_IMM_CHANNEL_DMA: + case NVC67D_CORE_CHANNEL_DMA: + case NVC67E_WINDOW_CHANNEL_DMA: + return 22; // "param_NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS" + + case MAXWELL_PROFILER_CONTEXT: + return 23; // "param_NVB1CC_ALLOC_PARAMETERS" + + case MAXWELL_PROFILER_DEVICE: + return 24; // "param_NVB2CC_ALLOC_PARAMETERS" + + case MAXWELL_COMPUTE_A: + case PASCAL_COMPUTE_A: + case VOLTA_COMPUTE_A: + case TURING_COMPUTE_A: + case AMPERE_COMPUTE_A: + case HOPPER_COMPUTE_A: + case MAXWELL_COMPUTE_B: + case PASCAL_COMPUTE_B: + case VOLTA_COMPUTE_B: + case AMPERE_COMPUTE_B: + return 25; // "param_NV_GR_ALLOCATION_PARAMETERS" + + case UVM_CHANNEL_RETAINER: + return 26; // "param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS" + + case NV_MEMORY_FABRIC: + return 27; // "param_NV00F8_ALLOCATION_PARAMETERS" + + case NVC9FA_VIDEO_OFA: + case NVCDFA_VIDEO_OFA: + case NVC6FA_VIDEO_OFA: + case NVC7FA_VIDEO_OFA: + case NVB8FA_VIDEO_OFA: + return 28; // "param_NVC9FA_VIDEO_OFA" + + case NV2081_BINAPI: + case NV2082_BINAPI_PRIVILEGED: + return 29; // "param_NV2081_ALLOC_PARAMETERS" + + default: + return UNION_UNKNOWN_FIELD_PRINT; + } +} + + + + +// Union member index functions for NV2080_CTRL_FB_FS_INFO_QUERY_DATA +uint32_t _get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D(NvU32 cmd) +{ + switch (cmd) + { + case NV2080_CTRL_FB_FS_INFO_INVALID_QUERY: + return 0; // "inv" + + case NV2080_CTRL_FB_FS_INFO_FBP_MASK: + return 1; // "fbp" + + case NV2080_CTRL_FB_FS_INFO_LTC_MASK: + return 2; // "ltc" + + case NV2080_CTRL_FB_FS_INFO_LTS_MASK: + return 3; // "lts" + + case NV2080_CTRL_FB_FS_INFO_FBPA_MASK: + return 4; // "fbpa" + + case NV2080_CTRL_FB_FS_INFO_ROP_MASK: + return 5; // "rop" + + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK: + return 6; // "dmLtc" + + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK: + return 7; // "dmLts" + + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK: + return 8; // "dmFbpa" + + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK: + return 9; // "dmRop" + + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK: + return 10; // "dmFbpaSubp" + + case NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK: + return 11; // "fbpaSubp" + + case NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP: + return 12; // "fbpLogicalMap" + + default: + return UNION_UNKNOWN_FIELD_PRINT; + } +} + + + + +// Union member index functions for NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA +uint32_t _get_union_member_index_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D(NvU32 cmd) +{ + switch (cmd) + { + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT: + return 0; // "gpcCountData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP: + return 1; // "chipletGpcMapData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK: + return 2; // "tpcMaskData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK: + return 3; // "ppcMaskData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP: + return 4; // "partitionGpcMapData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK: + return 5; // "syspipeMaskData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS: + return 6; // "partitionChipletSyspipeData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK: + return 7; // "dmGpcMaskData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID: + return 8; // "partitionSyspipeIdData" + + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK: + return 9; // "ropMaskData" + + default: + return UNION_UNKNOWN_FIELD_PRINT; + } +} + + + + // Union member index functions for NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type uint32_t _get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_type_v21_04(NvU32 cmd) { @@ -530,6 +3715,33 @@ uint32_t _get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_D #endif #ifdef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD +static NV_STATUS get_union_member_index_NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00_api_bundle(void *msg, NvS32 bytes_remaining, uint32_t* index) +{ + NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00 *param = msg; + + if ((NvS32)(NV_OFFSETOF(NV5080_CTRL_DEFERRED_API_V2_PARAMS_v06_00, cmd) + sizeof(param->cmd)) > bytes_remaining) + return NV_ERR_BUFFER_TOO_SMALL; + *index = _get_union_member_index_NV5080_CTRL_DEFERRED_API_V2_PARAMS_api_bundle_v06_00(param->cmd); + return NV_OK; +} +static NV_STATUS get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D_queryParams(void *msg, NvS32 bytes_remaining, uint32_t* index) +{ + NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D *param = msg; + + if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_FB_FS_INFO_QUERY_v1A_1D, queryType) + sizeof(param->queryType)) > bytes_remaining) + return NV_ERR_BUFFER_TOO_SMALL; + *index = _get_union_member_index_NV2080_CTRL_FB_FS_INFO_QUERY_DATA_v1A_1D(param->queryType); + return NV_OK; +} +static NV_STATUS get_union_member_index_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D_queryData(void *msg, NvS32 bytes_remaining, uint32_t* index) +{ + NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D *param = msg; + + if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARAMS_v1A_1D, queryType) + sizeof(param->queryType)) > bytes_remaining) + return NV_ERR_BUFFER_TOO_SMALL; + *index = _get_union_member_index_NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_DATA_v1A_1D(param->queryType); + return NV_OK; +} static NV_STATUS get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04_data(void *msg, NvS32 bytes_remaining, uint32_t* index) { NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_data_v21_04 *param = msg; @@ -545,22 +3757,35 @@ static NV_STATUS get_union_member_index_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE #ifdef SDK_ARRAY_LENGTH_FUNCTIONS // Array length functions for gpu_exec_reg_ops: -static NV_STATUS get_array_length_gpu_exec_reg_ops_v03_00_operations(void *msg, NvS32 bytes_remaining, uint32_t* length) +static NV_STATUS get_array_length_gpu_exec_reg_ops_v12_01_operations(void *msg, NvS32 bytes_remaining, uint32_t* length) { - gpu_exec_reg_ops_v03_00 *param = msg; + gpu_exec_reg_ops_v12_01 *param = msg; - if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v03_00, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining) + if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v12_01, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining) return NV_ERR_BUFFER_TOO_SMALL; *length = param->reg_op_params.regOpCount; return NV_OK; } -static NV_STATUS get_array_length_gpu_exec_reg_ops_v12_01_operations(void *msg, NvS32 bytes_remaining, uint32_t* length) + +// Array length functions for NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS: +static NV_STATUS get_array_length_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06_smErrorStateArray(void *msg, NvS32 bytes_remaining, uint32_t* length) { - gpu_exec_reg_ops_v12_01 *param = msg; + NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 *param = msg; - if ((NvS32)(NV_OFFSETOF(gpu_exec_reg_ops_v12_01, reg_op_params.regOpCount) + sizeof(param->reg_op_params.regOpCount)) > bytes_remaining) + if ((NvS32)(NV_OFFSETOF(NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06, numSMsToRead) + sizeof(param->numSMsToRead)) > bytes_remaining) return NV_ERR_BUFFER_TOO_SMALL; - *length = param->reg_op_params.regOpCount; + *length = param->numSMsToRead; + return NV_OK; +} + +// Array length functions for NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS: +static NV_STATUS get_array_length_NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04_blackList(void *msg, NvS32 bytes_remaining, uint32_t* length) +{ + NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04 *param = msg; + + if ((NvS32)(NV_OFFSETOF(NV2080_CTRL_FB_GET_OFFLINED_PAGES_PARAMS_v15_04, validEntries) + sizeof(param->validEntries)) > bytes_remaining) + return NV_ERR_BUFFER_TOO_SMALL; + *length = param->validEntries; return NV_OK; } diff --git a/src/nvidia/generated/g_sec2_context_nvoc.c b/src/nvidia/generated/g_sec2_context_nvoc.c index 47572b83f6..600d4bc3f7 100644 --- a/src/nvidia/generated/g_sec2_context_nvoc.c +++ b/src/nvidia/generated/g_sec2_context_nvoc.c @@ -172,10 +172,6 @@ static void __nvoc_thunk_RmResource_sec2ctxControl_Epilogue(struct Sec2Context * rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_sec2ctxControlLookup(struct Sec2Context *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_ChannelDescendant_sec2ctxGetSwMethods(struct Sec2Context *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return chandesGetSwMethods((struct ChannelDescendant *)(((unsigned char *)pChannelDescendant) + __nvoc_rtti_Sec2Context_ChannelDescendant.offset), ppMethods, pNumMethods); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_sec2ctxCanCopy(struct Sec2Context *pResour return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_sec2ctxIsPartialUnmapSupported(struct Sec2Context *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_sec2ctxPreDestruct(struct Sec2Context *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Sec2Context_RsResource.offset)); } @@ -323,8 +323,6 @@ static void __nvoc_init_funcTable_Sec2Context_1(Sec2Context *pThis, RmHalspecOwn pThis->__sec2ctxControl_Epilogue__ = &__nvoc_thunk_RmResource_sec2ctxControl_Epilogue; - pThis->__sec2ctxControlLookup__ = &__nvoc_thunk_RsResource_sec2ctxControlLookup; - pThis->__sec2ctxGetSwMethods__ = &__nvoc_thunk_ChannelDescendant_sec2ctxGetSwMethods; pThis->__sec2ctxGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_sec2ctxGetInternalObjectHandle; @@ -347,6 +345,8 @@ static void __nvoc_init_funcTable_Sec2Context_1(Sec2Context *pThis, RmHalspecOwn pThis->__sec2ctxCanCopy__ = &__nvoc_thunk_RsResource_sec2ctxCanCopy; + pThis->__sec2ctxIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_sec2ctxIsPartialUnmapSupported; + pThis->__sec2ctxPreDestruct__ = &__nvoc_thunk_RsResource_sec2ctxPreDestruct; pThis->__sec2ctxIsDuplicate__ = &__nvoc_thunk_RsResource_sec2ctxIsDuplicate; @@ -381,23 +381,31 @@ void __nvoc_init_Sec2Context(Sec2Context *pThis, RmHalspecOwner *pRmhalspecowner __nvoc_init_funcTable_Sec2Context(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Sec2Context *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Sec2Context), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Sec2Context)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Sec2Context); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -415,16 +423,25 @@ NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context **ppThis, Dynamic *pParent, N status = __nvoc_ctor_Sec2Context(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_Sec2Context_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Sec2Context_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Sec2Context)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_sec2_context_nvoc.h b/src/nvidia/generated/g_sec2_context_nvoc.h index 61f74b0949..013f08ba62 100644 --- a/src/nvidia/generated/g_sec2_context_nvoc.h +++ b/src/nvidia/generated/g_sec2_context_nvoc.h @@ -42,11 +42,16 @@ extern "C" { * RM internal class representing NVXXXX_TSEC. Class is used for channel work * submission. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SEC2_CONTEXT_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Sec2Context { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -72,7 +77,6 @@ struct Sec2Context { NV_STATUS (*__sec2ctxInternalControlForward__)(struct Sec2Context *, NvU32, void *, NvU32); NV_STATUS (*__sec2ctxUnmapFrom__)(struct Sec2Context *, RS_RES_UNMAP_FROM_PARAMS *); void (*__sec2ctxControl_Epilogue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__sec2ctxControlLookup__)(struct Sec2Context *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__sec2ctxGetSwMethods__)(struct Sec2Context *, const METHOD **, NvU32 *); NvHandle (*__sec2ctxGetInternalObjectHandle__)(struct Sec2Context *); NV_STATUS (*__sec2ctxControl__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -84,6 +88,7 @@ struct Sec2Context { NV_STATUS (*__sec2ctxUnregisterEvent__)(struct Sec2Context *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__sec2ctxControlSerialization_Prologue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__sec2ctxCanCopy__)(struct Sec2Context *); + NvBool (*__sec2ctxIsPartialUnmapSupported__)(struct Sec2Context *); void (*__sec2ctxPreDestruct__)(struct Sec2Context *); NV_STATUS (*__sec2ctxIsDuplicate__)(struct Sec2Context *, NvHandle, NvBool *); void (*__sec2ctxControlSerialization_Epilogue__)(struct Sec2Context *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -134,7 +139,6 @@ NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context**, Dynamic*, NvU32, struct CA #define sec2ctxInternalControlForward(pGpuResource, command, pParams, size) sec2ctxInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define sec2ctxUnmapFrom(pResource, pParams) sec2ctxUnmapFrom_DISPATCH(pResource, pParams) #define sec2ctxControl_Epilogue(pResource, pCallContext, pParams) sec2ctxControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define sec2ctxControlLookup(pResource, pParams, ppEntry) sec2ctxControlLookup_DISPATCH(pResource, pParams, ppEntry) #define sec2ctxGetSwMethods(pChannelDescendant, ppMethods, pNumMethods) sec2ctxGetSwMethods_DISPATCH(pChannelDescendant, ppMethods, pNumMethods) #define sec2ctxGetInternalObjectHandle(pGpuResource) sec2ctxGetInternalObjectHandle_DISPATCH(pGpuResource) #define sec2ctxControl(pGpuResource, pCallContext, pParams) sec2ctxControl_DISPATCH(pGpuResource, pCallContext, pParams) @@ -146,6 +150,7 @@ NV_STATUS __nvoc_objCreate_Sec2Context(Sec2Context**, Dynamic*, NvU32, struct CA #define sec2ctxUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) sec2ctxUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define sec2ctxControlSerialization_Prologue(pResource, pCallContext, pParams) sec2ctxControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define sec2ctxCanCopy(pResource) sec2ctxCanCopy_DISPATCH(pResource) +#define sec2ctxIsPartialUnmapSupported(pResource) sec2ctxIsPartialUnmapSupported_DISPATCH(pResource) #define sec2ctxPreDestruct(pResource) sec2ctxPreDestruct_DISPATCH(pResource) #define sec2ctxIsDuplicate(pResource, hMemory, pDuplicate) sec2ctxIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define sec2ctxControlSerialization_Epilogue(pResource, pCallContext, pParams) sec2ctxControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -232,10 +237,6 @@ static inline void sec2ctxControl_Epilogue_DISPATCH(struct Sec2Context *pResourc pResource->__sec2ctxControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS sec2ctxControlLookup_DISPATCH(struct Sec2Context *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__sec2ctxControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS sec2ctxGetSwMethods_DISPATCH(struct Sec2Context *pChannelDescendant, const METHOD **ppMethods, NvU32 *pNumMethods) { return pChannelDescendant->__sec2ctxGetSwMethods__(pChannelDescendant, ppMethods, pNumMethods); } @@ -280,6 +281,10 @@ static inline NvBool sec2ctxCanCopy_DISPATCH(struct Sec2Context *pResource) { return pResource->__sec2ctxCanCopy__(pResource); } +static inline NvBool sec2ctxIsPartialUnmapSupported_DISPATCH(struct Sec2Context *pResource) { + return pResource->__sec2ctxIsPartialUnmapSupported__(pResource); +} + static inline void sec2ctxPreDestruct_DISPATCH(struct Sec2Context *pResource) { pResource->__sec2ctxPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_sec2_utils_nvoc.c b/src/nvidia/generated/g_sec2_utils_nvoc.c index 1b73316cc2..f2cc26c1f5 100644 --- a/src/nvidia/generated/g_sec2_utils_nvoc.c +++ b/src/nvidia/generated/g_sec2_utils_nvoc.c @@ -109,21 +109,26 @@ void __nvoc_init_Sec2Utils(Sec2Utils *pThis) { __nvoc_init_funcTable_Sec2Utils(pThis); } -NV_STATUS __nvoc_objCreate_Sec2Utils(Sec2Utils **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance) { +NV_STATUS __nvoc_objCreate_Sec2Utils(Sec2Utils **ppThis, Dynamic *pParent, NvU32 createFlags, struct OBJGPU * arg_pGpu, KERNEL_MIG_GPU_INSTANCE * arg_pKernelMIGGPUInstance) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Sec2Utils *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Sec2Utils), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Sec2Utils)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Sec2Utils); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -138,16 +143,25 @@ NV_STATUS __nvoc_objCreate_Sec2Utils(Sec2Utils **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_Sec2Utils(pThis, arg_pGpu, arg_pKernelMIGGPUInstance); if (status != NV_OK) goto __nvoc_objCreate_Sec2Utils_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Sec2Utils_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Sec2Utils)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_sec2_utils_nvoc.h b/src/nvidia/generated/g_sec2_utils_nvoc.h index be2b2f4d6b..85996f82b8 100644 --- a/src/nvidia/generated/g_sec2_utils_nvoc.h +++ b/src/nvidia/generated/g_sec2_utils_nvoc.h @@ -61,11 +61,16 @@ typedef struct MEMORY_DESCRIPTOR *pMemDesc; } SEC2UTILS_BUFFER_INFO; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SEC2_UTILS_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Sec2Utils { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_sem_surf_nvoc.c b/src/nvidia/generated/g_sem_surf_nvoc.c index 5e44ae444d..47df115d88 100644 --- a/src/nvidia/generated/g_sem_surf_nvoc.c +++ b/src/nvidia/generated/g_sem_surf_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_semsurfControl_Epilogue(struct SemaphoreSurf rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_semsurfControlLookup(struct SemaphoreSurface *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_semsurfGetInternalObjectHandle(struct SemaphoreSurface *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SemaphoreSurface_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RmResource_semsurfControlSerialization_Prologue(st return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_semsurfIsPartialUnmapSupported(struct SemaphoreSurface *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_semsurfPreDestruct(struct SemaphoreSurface *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SemaphoreSurface_RsResource.offset)); } @@ -362,8 +362,6 @@ static void __nvoc_init_funcTable_SemaphoreSurface_1(SemaphoreSurface *pThis) { pThis->__semsurfControl_Epilogue__ = &__nvoc_thunk_RmResource_semsurfControl_Epilogue; - pThis->__semsurfControlLookup__ = &__nvoc_thunk_RsResource_semsurfControlLookup; - pThis->__semsurfGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_semsurfGetInternalObjectHandle; pThis->__semsurfControl__ = &__nvoc_thunk_GpuResource_semsurfControl; @@ -378,6 +376,8 @@ static void __nvoc_init_funcTable_SemaphoreSurface_1(SemaphoreSurface *pThis) { pThis->__semsurfControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_semsurfControlSerialization_Prologue; + pThis->__semsurfIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_semsurfIsPartialUnmapSupported; + pThis->__semsurfPreDestruct__ = &__nvoc_thunk_RsResource_semsurfPreDestruct; pThis->__semsurfIsDuplicate__ = &__nvoc_thunk_RsResource_semsurfIsDuplicate; @@ -405,21 +405,26 @@ void __nvoc_init_SemaphoreSurface(SemaphoreSurface *pThis) { __nvoc_init_funcTable_SemaphoreSurface(pThis); } -NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; SemaphoreSurface *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SemaphoreSurface), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(SemaphoreSurface)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SemaphoreSurface); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -434,16 +439,25 @@ NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface **ppThis, Dynamic * status = __nvoc_ctor_SemaphoreSurface(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_SemaphoreSurface_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_SemaphoreSurface_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(SemaphoreSurface)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_sem_surf_nvoc.h b/src/nvidia/generated/g_sem_surf_nvoc.h index 2976801316..66786fdf02 100644 --- a/src/nvidia/generated/g_sem_surf_nvoc.h +++ b/src/nvidia/generated/g_sem_surf_nvoc.h @@ -82,8 +82,9 @@ typedef struct { NvHandle hSubDevice; NvHandle hSemaphoreMem; NvHandle hMaxSubmittedMem; - NvHandle hEvent; + NvHandle *phEvents; NVOS10_EVENT_KERNEL_CALLBACK_EX callback; + NvU32 numEvents; /* The client-mappable semaphore memory region and associated data */ NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS layout; @@ -93,6 +94,7 @@ typedef struct { NvP64 maxSubmittedKernAddr; NvU8 *pSem; NvU8 *pMaxSubmitted; + NvU64 slotCount; /* Client active CPU waiters list XXX Should be per (offset,value) pair */ SEM_INDEX_LISTENERS listenerMap; @@ -107,11 +109,16 @@ typedef struct { NvBool bHasMonitoredFence; } SEM_SHARED_DATA; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SEM_SURF_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct SemaphoreSurface { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -138,7 +145,6 @@ struct SemaphoreSurface { NV_STATUS (*__semsurfInternalControlForward__)(struct SemaphoreSurface *, NvU32, void *, NvU32); NV_STATUS (*__semsurfUnmapFrom__)(struct SemaphoreSurface *, RS_RES_UNMAP_FROM_PARAMS *); void (*__semsurfControl_Epilogue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__semsurfControlLookup__)(struct SemaphoreSurface *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__semsurfGetInternalObjectHandle__)(struct SemaphoreSurface *); NV_STATUS (*__semsurfControl__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__semsurfUnmap__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -146,6 +152,7 @@ struct SemaphoreSurface { NV_STATUS (*__semsurfGetMemoryMappingDescriptor__)(struct SemaphoreSurface *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__semsurfControlFilter__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__semsurfControlSerialization_Prologue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__semsurfIsPartialUnmapSupported__)(struct SemaphoreSurface *); void (*__semsurfPreDestruct__)(struct SemaphoreSurface *); NV_STATUS (*__semsurfIsDuplicate__)(struct SemaphoreSurface *, NvHandle, NvBool *); void (*__semsurfControlSerialization_Epilogue__)(struct SemaphoreSurface *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -199,7 +206,6 @@ NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface**, Dynamic*, NvU32, #define semsurfInternalControlForward(pGpuResource, command, pParams, size) semsurfInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define semsurfUnmapFrom(pResource, pParams) semsurfUnmapFrom_DISPATCH(pResource, pParams) #define semsurfControl_Epilogue(pResource, pCallContext, pParams) semsurfControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define semsurfControlLookup(pResource, pParams, ppEntry) semsurfControlLookup_DISPATCH(pResource, pParams, ppEntry) #define semsurfGetInternalObjectHandle(pGpuResource) semsurfGetInternalObjectHandle_DISPATCH(pGpuResource) #define semsurfControl(pGpuResource, pCallContext, pParams) semsurfControl_DISPATCH(pGpuResource, pCallContext, pParams) #define semsurfUnmap(pGpuResource, pCallContext, pCpuMapping) semsurfUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -207,6 +213,7 @@ NV_STATUS __nvoc_objCreate_SemaphoreSurface(SemaphoreSurface**, Dynamic*, NvU32, #define semsurfGetMemoryMappingDescriptor(pRmResource, ppMemDesc) semsurfGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define semsurfControlFilter(pResource, pCallContext, pParams) semsurfControlFilter_DISPATCH(pResource, pCallContext, pParams) #define semsurfControlSerialization_Prologue(pResource, pCallContext, pParams) semsurfControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define semsurfIsPartialUnmapSupported(pResource) semsurfIsPartialUnmapSupported_DISPATCH(pResource) #define semsurfPreDestruct(pResource) semsurfPreDestruct_DISPATCH(pResource) #define semsurfIsDuplicate(pResource, hMemory, pDuplicate) semsurfIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define semsurfControlSerialization_Epilogue(pResource, pCallContext, pParams) semsurfControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -294,10 +301,6 @@ static inline void semsurfControl_Epilogue_DISPATCH(struct SemaphoreSurface *pRe pResource->__semsurfControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS semsurfControlLookup_DISPATCH(struct SemaphoreSurface *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__semsurfControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle semsurfGetInternalObjectHandle_DISPATCH(struct SemaphoreSurface *pGpuResource) { return pGpuResource->__semsurfGetInternalObjectHandle__(pGpuResource); } @@ -326,6 +329,10 @@ static inline NV_STATUS semsurfControlSerialization_Prologue_DISPATCH(struct Sem return pResource->__semsurfControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool semsurfIsPartialUnmapSupported_DISPATCH(struct SemaphoreSurface *pResource) { + return pResource->__semsurfIsPartialUnmapSupported__(pResource); +} + static inline void semsurfPreDestruct_DISPATCH(struct SemaphoreSurface *pResource) { pResource->__semsurfPreDestruct__(pResource); } @@ -352,6 +359,28 @@ NV_STATUS semsurfConstruct_IMPL(struct SemaphoreSurface *arg_semaphoreSurf, CALL void semsurfDestruct_IMPL(struct SemaphoreSurface *pSemSurf); #define __nvoc_semsurfDestruct(pSemSurf) semsurfDestruct_IMPL(pSemSurf) +NvU64 semsurfGetValue_IMPL(struct SemaphoreSurface *pSemSurf, NvU64 index); + +#ifdef __nvoc_sem_surf_h_disabled +static inline NvU64 semsurfGetValue(struct SemaphoreSurface *pSemSurf, NvU64 index) { + NV_ASSERT_FAILED_PRECOMP("SemaphoreSurface was disabled!"); + return 0; +} +#else //__nvoc_sem_surf_h_disabled +#define semsurfGetValue(pSemSurf, index) semsurfGetValue_IMPL(pSemSurf, index) +#endif //__nvoc_sem_surf_h_disabled + +NvBool semsurfValidateIndex_IMPL(struct SemaphoreSurface *pSemSurf, NvU64 index); + +#ifdef __nvoc_sem_surf_h_disabled +static inline NvBool semsurfValidateIndex(struct SemaphoreSurface *pSemSurf, NvU64 index) { + NV_ASSERT_FAILED_PRECOMP("SemaphoreSurface was disabled!"); + return NV_FALSE; +} +#else //__nvoc_sem_surf_h_disabled +#define semsurfValidateIndex(pSemSurf, index) semsurfValidateIndex_IMPL(pSemSurf, index) +#endif //__nvoc_sem_surf_h_disabled + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_spdm_nvoc.c b/src/nvidia/generated/g_spdm_nvoc.c index d3e7b667fb..1f451c91b4 100644 --- a/src/nvidia/generated/g_spdm_nvoc.c +++ b/src/nvidia/generated/g_spdm_nvoc.c @@ -128,6 +128,50 @@ static void __nvoc_init_funcTable_Spdm_1(Spdm *pThis, RmHalspecOwner *pRmhalspec pThis->__spdmGetAttestationReport__ = &spdmGetAttestationReport_46f6a7; } + // Hal function -- spdmCheckAndExecuteKeyUpdate + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmCheckAndExecuteKeyUpdate__ = &spdmCheckAndExecuteKeyUpdate_GH100; + } + // default + else + { + pThis->__spdmCheckAndExecuteKeyUpdate__ = &spdmCheckAndExecuteKeyUpdate_46f6a7; + } + + // Hal function -- spdmSendInitRmDataCommand + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmSendInitRmDataCommand__ = &spdmSendInitRmDataCommand_GH100; + } + // default + else + { + pThis->__spdmSendInitRmDataCommand__ = &spdmSendInitRmDataCommand_46f6a7; + } + + // Hal function -- spdmRegisterForHeartbeats + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmRegisterForHeartbeats__ = &spdmRegisterForHeartbeats_GH100; + } + // default + else + { + pThis->__spdmRegisterForHeartbeats__ = &spdmRegisterForHeartbeats_46f6a7; + } + + // Hal function -- spdmUnregisterFromHeartbeats + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmUnregisterFromHeartbeats__ = &spdmUnregisterFromHeartbeats_GH100; + } + // default + else + { + pThis->__spdmUnregisterFromHeartbeats__ = &spdmUnregisterFromHeartbeats_46f6a7; + } + // Hal function -- spdmDeviceInit if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ { @@ -193,6 +237,17 @@ static void __nvoc_init_funcTable_Spdm_1(Spdm *pThis, RmHalspecOwner *pRmhalspec { pThis->__spdmGetCertificates__ = &spdmGetCertificates_46f6a7; } + + // Hal function -- spdmGetReqEncapCertificates + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__spdmGetReqEncapCertificates__ = &spdmGetReqEncapCertificates_GH100; + } + // default + else + { + pThis->__spdmGetReqEncapCertificates__ = &spdmGetReqEncapCertificates_46f6a7; + } } void __nvoc_init_funcTable_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -207,23 +262,31 @@ void __nvoc_init_Spdm(Spdm *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_Spdm(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_Spdm(Spdm **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_Spdm(Spdm **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Spdm *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Spdm), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Spdm)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Spdm); pThis->__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_Object); @@ -241,16 +304,25 @@ NV_STATUS __nvoc_objCreate_Spdm(Spdm **ppThis, Dynamic *pParent, NvU32 createFla status = __nvoc_ctor_Spdm(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_Spdm_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Spdm_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Spdm)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_spdm_nvoc.h b/src/nvidia/generated/g_spdm_nvoc.h index 6cf4cb3807..efd67d58be 100644 --- a/src/nvidia/generated/g_spdm_nvoc.h +++ b/src/nvidia/generated/g_spdm_nvoc.h @@ -37,6 +37,7 @@ extern "C" { #include "gpu/gpu.h" #include "nvport/nvport.h" +#include "objtmr.h" /****************************************************************************\ * * @@ -59,37 +60,54 @@ extern "C" { default: _IMPL; \ } + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SPDM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Spdm { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; struct Object *__nvoc_pbase_Object; struct Spdm *__nvoc_pbase_Spdm; - NV_STATUS (*__spdmGetCertChains__)(struct OBJGPU *, struct Spdm *, void *, NvU32 *, void *, NvU32 *); - NV_STATUS (*__spdmGetAttestationReport__)(struct OBJGPU *, struct Spdm *, NvU8 *, void *, NvU32 *, NvBool *, void *, NvU32 *); - NV_STATUS (*__spdmDeviceInit__)(struct OBJGPU *, struct Spdm *); - NV_STATUS (*__spdmDeviceDeinit__)(struct OBJGPU *, struct Spdm *, NvBool); - NV_STATUS (*__spdmDeviceSecuredSessionSupported__)(struct OBJGPU *, struct Spdm *); - NV_STATUS (*__spdmCheckConnection__)(struct OBJGPU *, struct Spdm *); - NV_STATUS (*__spdmMessageProcess__)(struct OBJGPU *, struct Spdm *, NvU8 *, NvU32, NvU8 *, NvU32 *); - NV_STATUS (*__spdmGetCertificates__)(struct OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmGetCertChains__)(OBJGPU *, struct Spdm *, void *, NvU32 *, void *, NvU32 *); + NV_STATUS (*__spdmGetAttestationReport__)(OBJGPU *, struct Spdm *, NvU8 *, void *, NvU32 *, NvBool *, void *, NvU32 *); + NV_STATUS (*__spdmCheckAndExecuteKeyUpdate__)(OBJGPU *, struct Spdm *, NvU32); + NV_STATUS (*__spdmSendInitRmDataCommand__)(OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmRegisterForHeartbeats__)(OBJGPU *, struct Spdm *, NvU32); + NV_STATUS (*__spdmUnregisterFromHeartbeats__)(OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmDeviceInit__)(OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmDeviceDeinit__)(OBJGPU *, struct Spdm *, NvBool); + NV_STATUS (*__spdmDeviceSecuredSessionSupported__)(OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmCheckConnection__)(OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmMessageProcess__)(OBJGPU *, struct Spdm *, NvU8 *, NvU32, NvU8 *, NvU32 *); + NV_STATUS (*__spdmGetCertificates__)(OBJGPU *, struct Spdm *); + NV_STATUS (*__spdmGetReqEncapCertificates__)(OBJGPU *, struct Spdm *, NvU8 **, NvU32 *); void *pLibspdmContext; NvU32 libspdmContextSize; void *pLibspdmScratch; NvU32 libspdmScratchSize; + NvBool bSessionEstablished; NvU32 sessionId; + NvBool bUsePolling; + MEMORY_DESCRIPTOR *pPayloadBufferMemDesc; + NvU32 payloadBufferSize; NvU32 guestId; NvU32 endpointId; NvU8 *pAttestationCertChain; size_t attestationCertChainSize; void *pDeviceIOContext; - void *pLastExchange; - size_t lastExchangeSize; + void *pMsgLog; + size_t msgLogMaxSize; NvBool bExportSecretCleared; + NvU32 sessionMsgCount; + PTMR_EVENT pHeartbeatEvent; + NvU32 heartbeatPeriodSec; }; #ifndef __NVOC_CLASS_Spdm_TYPEDEF__ @@ -124,6 +142,14 @@ NV_STATUS __nvoc_objCreate_Spdm(Spdm**, Dynamic*, NvU32); #define spdmGetCertChains_HAL(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) spdmGetCertChains_DISPATCH(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize) #define spdmGetAttestationReport(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) spdmGetAttestationReport_DISPATCH(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) #define spdmGetAttestationReport_HAL(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) spdmGetAttestationReport_DISPATCH(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize) +#define spdmCheckAndExecuteKeyUpdate(pGpu, pSpdm, keyUpdateTriggerId) spdmCheckAndExecuteKeyUpdate_DISPATCH(pGpu, pSpdm, keyUpdateTriggerId) +#define spdmCheckAndExecuteKeyUpdate_HAL(pGpu, pSpdm, keyUpdateTriggerId) spdmCheckAndExecuteKeyUpdate_DISPATCH(pGpu, pSpdm, keyUpdateTriggerId) +#define spdmSendInitRmDataCommand(pGpu, pSpdm) spdmSendInitRmDataCommand_DISPATCH(pGpu, pSpdm) +#define spdmSendInitRmDataCommand_HAL(pGpu, pSpdm) spdmSendInitRmDataCommand_DISPATCH(pGpu, pSpdm) +#define spdmRegisterForHeartbeats(pGpu, pSpdm, heartbeatPeriodSec) spdmRegisterForHeartbeats_DISPATCH(pGpu, pSpdm, heartbeatPeriodSec) +#define spdmRegisterForHeartbeats_HAL(pGpu, pSpdm, heartbeatPeriodSec) spdmRegisterForHeartbeats_DISPATCH(pGpu, pSpdm, heartbeatPeriodSec) +#define spdmUnregisterFromHeartbeats(pGpu, pSpdm) spdmUnregisterFromHeartbeats_DISPATCH(pGpu, pSpdm) +#define spdmUnregisterFromHeartbeats_HAL(pGpu, pSpdm) spdmUnregisterFromHeartbeats_DISPATCH(pGpu, pSpdm) #define spdmDeviceInit(pGpu, pSpdm) spdmDeviceInit_DISPATCH(pGpu, pSpdm) #define spdmDeviceInit_HAL(pGpu, pSpdm) spdmDeviceInit_DISPATCH(pGpu, pSpdm) #define spdmDeviceDeinit(pGpu, pSpdm, bForceClear) spdmDeviceDeinit_DISPATCH(pGpu, pSpdm, bForceClear) @@ -136,6 +162,8 @@ NV_STATUS __nvoc_objCreate_Spdm(Spdm**, Dynamic*, NvU32); #define spdmMessageProcess_HAL(pGpu, pSpdm, pRequest, requestSize, pResponse, pResponseSize) spdmMessageProcess_DISPATCH(pGpu, pSpdm, pRequest, requestSize, pResponse, pResponseSize) #define spdmGetCertificates(pGpu, pSpdm) spdmGetCertificates_DISPATCH(pGpu, pSpdm) #define spdmGetCertificates_HAL(pGpu, pSpdm) spdmGetCertificates_DISPATCH(pGpu, pSpdm) +#define spdmGetReqEncapCertificates(pGpu, pSpdm, pEncapCertChain, pEncapCertChainSize) spdmGetReqEncapCertificates_DISPATCH(pGpu, pSpdm, pEncapCertChain, pEncapCertChainSize) +#define spdmGetReqEncapCertificates_HAL(pGpu, pSpdm, pEncapCertChain, pEncapCertChainSize) spdmGetReqEncapCertificates_DISPATCH(pGpu, pSpdm, pEncapCertChain, pEncapCertChainSize) NV_STATUS spdmConstruct_IMPL(struct Spdm *arg_pSpdm); @@ -144,11 +172,25 @@ void spdmDestruct_IMPL(struct Spdm *pSpdm); #define __nvoc_spdmDestruct(pSpdm) spdmDestruct_IMPL(pSpdm) -NV_STATUS spdmContextInit_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm); +NV_STATUS spdmSetupCommunicationBuffers_IMPL(OBJGPU *pGpu, struct Spdm *pSpdm); #ifdef __nvoc_spdm_h_disabled -static inline NV_STATUS spdmContextInit(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmSetupCommunicationBuffers(OBJGPU *pGpu, struct Spdm *pSpdm) { + NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_spdm_h_disabled +#define spdmSetupCommunicationBuffers(pGpu, pSpdm) spdmSetupCommunicationBuffers_IMPL(pGpu, pSpdm) +#endif //__nvoc_spdm_h_disabled + +#define spdmSetupCommunicationBuffers_HAL(pGpu, pSpdm) spdmSetupCommunicationBuffers(pGpu, pSpdm) + +NV_STATUS spdmContextInit_IMPL(OBJGPU *pGpu, struct Spdm *pSpdm); + + +#ifdef __nvoc_spdm_h_disabled +static inline NV_STATUS spdmContextInit(OBJGPU *pGpu, struct Spdm *pSpdm) { NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -158,11 +200,11 @@ static inline NV_STATUS spdmContextInit(struct OBJGPU *pGpu, struct Spdm *pSpdm) #define spdmContextInit_HAL(pGpu, pSpdm) spdmContextInit(pGpu, pSpdm) -NV_STATUS spdmContextDeinit_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear); +NV_STATUS spdmContextDeinit_IMPL(OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear); #ifdef __nvoc_spdm_h_disabled -static inline NV_STATUS spdmContextDeinit(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { +static inline NV_STATUS spdmContextDeinit(OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -172,11 +214,11 @@ static inline NV_STATUS spdmContextDeinit(struct OBJGPU *pGpu, struct Spdm *pSpd #define spdmContextDeinit_HAL(pGpu, pSpdm, bForceClear) spdmContextDeinit(pGpu, pSpdm, bForceClear) -NV_STATUS spdmStart_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm); +NV_STATUS spdmStart_IMPL(OBJGPU *pGpu, struct Spdm *pSpdm); #ifdef __nvoc_spdm_h_disabled -static inline NV_STATUS spdmStart(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmStart(OBJGPU *pGpu, struct Spdm *pSpdm) { NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -186,11 +228,11 @@ static inline NV_STATUS spdmStart(struct OBJGPU *pGpu, struct Spdm *pSpdm) { #define spdmStart_HAL(pGpu, pSpdm) spdmStart(pGpu, pSpdm) -NV_STATUS spdmRetrieveExportSecret_IMPL(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keySize, NvU8 *pKeyOut); +NV_STATUS spdmRetrieveExportSecret_IMPL(OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keySize, NvU8 *pKeyOut); #ifdef __nvoc_spdm_h_disabled -static inline NV_STATUS spdmRetrieveExportSecret(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keySize, NvU8 *pKeyOut) { +static inline NV_STATUS spdmRetrieveExportSecret(OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keySize, NvU8 *pKeyOut) { NV_ASSERT_FAILED_PRECOMP("Spdm was disabled!"); return NV_ERR_NOT_SUPPORTED; } @@ -200,86 +242,136 @@ static inline NV_STATUS spdmRetrieveExportSecret(struct OBJGPU *pGpu, struct Spd #define spdmRetrieveExportSecret_HAL(pGpu, pSpdm, keySize, pKeyOut) spdmRetrieveExportSecret(pGpu, pSpdm, keySize, pKeyOut) -NV_STATUS spdmGetCertChains_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize); +NV_STATUS spdmGetCertChains_GH100(OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize); -static inline NV_STATUS spdmGetCertChains_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize) { +static inline NV_STATUS spdmGetCertChains_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS spdmGetCertChains_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize) { +static inline NV_STATUS spdmGetCertChains_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm, void *pKeyExCertChain, NvU32 *pKeyExCertChainSize, void *pAttestationCertChain, NvU32 *pAttestationCertChainSize) { return pSpdm->__spdmGetCertChains__(pGpu, pSpdm, pKeyExCertChain, pKeyExCertChainSize, pAttestationCertChain, pAttestationCertChainSize); } -NV_STATUS spdmGetAttestationReport_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize); +NV_STATUS spdmGetAttestationReport_GH100(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize); -static inline NV_STATUS spdmGetAttestationReport_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize) { +static inline NV_STATUS spdmGetAttestationReport_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS spdmGetAttestationReport_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize) { +static inline NV_STATUS spdmGetAttestationReport_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pNonce, void *pAttestationReport, NvU32 *pAttestationReportSize, NvBool *pbIsCecAttestationReportPresent, void *pCecAttestationReport, NvU32 *pCecAttestationReportSize) { return pSpdm->__spdmGetAttestationReport__(pGpu, pSpdm, pNonce, pAttestationReport, pAttestationReportSize, pbIsCecAttestationReportPresent, pCecAttestationReport, pCecAttestationReportSize); } -NV_STATUS spdmDeviceInit_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); +NV_STATUS spdmCheckAndExecuteKeyUpdate_GH100(OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keyUpdateTriggerId); + +static inline NV_STATUS spdmCheckAndExecuteKeyUpdate_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keyUpdateTriggerId) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmCheckAndExecuteKeyUpdate_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 keyUpdateTriggerId) { + return pSpdm->__spdmCheckAndExecuteKeyUpdate__(pGpu, pSpdm, keyUpdateTriggerId); +} + +NV_STATUS spdmSendInitRmDataCommand_GH100(OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmSendInitRmDataCommand_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmSendInitRmDataCommand_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmSendInitRmDataCommand__(pGpu, pSpdm); +} + +NV_STATUS spdmRegisterForHeartbeats_GH100(OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 heartbeatPeriodSec); -static inline NV_STATUS spdmDeviceInit_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmRegisterForHeartbeats_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 heartbeatPeriodSec) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS spdmDeviceInit_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmRegisterForHeartbeats_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm, NvU32 heartbeatPeriodSec) { + return pSpdm->__spdmRegisterForHeartbeats__(pGpu, pSpdm, heartbeatPeriodSec); +} + +NV_STATUS spdmUnregisterFromHeartbeats_GH100(OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmUnregisterFromHeartbeats_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmUnregisterFromHeartbeats_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm) { + return pSpdm->__spdmUnregisterFromHeartbeats__(pGpu, pSpdm); +} + +NV_STATUS spdmDeviceInit_GH100(OBJGPU *pGpu, struct Spdm *pSpdm); + +static inline NV_STATUS spdmDeviceInit_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmDeviceInit_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm) { return pSpdm->__spdmDeviceInit__(pGpu, pSpdm); } -NV_STATUS spdmDeviceDeinit_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear); +NV_STATUS spdmDeviceDeinit_GH100(OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear); -static inline NV_STATUS spdmDeviceDeinit_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { +static inline NV_STATUS spdmDeviceDeinit_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS spdmDeviceDeinit_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { +static inline NV_STATUS spdmDeviceDeinit_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm, NvBool bForceClear) { return pSpdm->__spdmDeviceDeinit__(pGpu, pSpdm, bForceClear); } -NV_STATUS spdmDeviceSecuredSessionSupported_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); +NV_STATUS spdmDeviceSecuredSessionSupported_GH100(OBJGPU *pGpu, struct Spdm *pSpdm); -static inline NV_STATUS spdmDeviceSecuredSessionSupported_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmDeviceSecuredSessionSupported_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS spdmDeviceSecuredSessionSupported_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmDeviceSecuredSessionSupported_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm) { return pSpdm->__spdmDeviceSecuredSessionSupported__(pGpu, pSpdm); } -NV_STATUS spdmCheckConnection_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); +NV_STATUS spdmCheckConnection_GH100(OBJGPU *pGpu, struct Spdm *pSpdm); -static inline NV_STATUS spdmCheckConnection_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmCheckConnection_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS spdmCheckConnection_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmCheckConnection_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm) { return pSpdm->__spdmCheckConnection__(pGpu, pSpdm); } -NV_STATUS spdmMessageProcess_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize); +NV_STATUS spdmMessageProcess_GH100(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize); -static inline NV_STATUS spdmMessageProcess_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize) { +static inline NV_STATUS spdmMessageProcess_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS spdmMessageProcess_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize) { +static inline NV_STATUS spdmMessageProcess_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 *pRequest, NvU32 requestSize, NvU8 *pResponse, NvU32 *pResponseSize) { return pSpdm->__spdmMessageProcess__(pGpu, pSpdm, pRequest, requestSize, pResponse, pResponseSize); } -NV_STATUS spdmGetCertificates_GH100(struct OBJGPU *pGpu, struct Spdm *pSpdm); +NV_STATUS spdmGetCertificates_GH100(OBJGPU *pGpu, struct Spdm *pSpdm); -static inline NV_STATUS spdmGetCertificates_46f6a7(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmGetCertificates_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS spdmGetCertificates_DISPATCH(struct OBJGPU *pGpu, struct Spdm *pSpdm) { +static inline NV_STATUS spdmGetCertificates_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm) { return pSpdm->__spdmGetCertificates__(pGpu, pSpdm); } +NV_STATUS spdmGetReqEncapCertificates_GH100(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 **pEncapCertChain, NvU32 *pEncapCertChainSize); + +static inline NV_STATUS spdmGetReqEncapCertificates_46f6a7(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 **pEncapCertChain, NvU32 *pEncapCertChainSize) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS spdmGetReqEncapCertificates_DISPATCH(OBJGPU *pGpu, struct Spdm *pSpdm, NvU8 **pEncapCertChain, NvU32 *pEncapCertChainSize) { + return pSpdm->__spdmGetReqEncapCertificates__(pGpu, pSpdm, pEncapCertChain, pEncapCertChainSize); +} + #undef PRIVATE_FIELD diff --git a/src/nvidia/generated/g_standard_mem_nvoc.c b/src/nvidia/generated/g_standard_mem_nvoc.c index 4deebbd565..6352d006d0 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.c +++ b/src/nvidia/generated/g_standard_mem_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_stdmemControl_Epilogue(struct StandardMemory rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_stdmemControlLookup(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_stdmemControl(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_stdmemControlSerialization_Prologue(str return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_stdmemIsPartialUnmapSupported(struct StandardMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_StandardMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_stdmemIsReady(struct StandardMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_StandardMemory_Memory.offset), bCopyConstructorContext); } @@ -261,8 +261,6 @@ static void __nvoc_init_funcTable_StandardMemory_1(StandardMemory *pThis) { pThis->__stdmemControl_Epilogue__ = &__nvoc_thunk_RmResource_stdmemControl_Epilogue; - pThis->__stdmemControlLookup__ = &__nvoc_thunk_RsResource_stdmemControlLookup; - pThis->__stdmemControl__ = &__nvoc_thunk_Memory_stdmemControl; pThis->__stdmemUnmap__ = &__nvoc_thunk_Memory_stdmemUnmap; @@ -275,6 +273,8 @@ static void __nvoc_init_funcTable_StandardMemory_1(StandardMemory *pThis) { pThis->__stdmemControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_stdmemControlSerialization_Prologue; + pThis->__stdmemIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_stdmemIsPartialUnmapSupported; + pThis->__stdmemIsReady__ = &__nvoc_thunk_Memory_stdmemIsReady; pThis->__stdmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_stdmemCheckCopyPermissions; @@ -306,21 +306,26 @@ void __nvoc_init_StandardMemory(StandardMemory *pThis) { __nvoc_init_funcTable_StandardMemory(pThis); } -NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; StandardMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(StandardMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(StandardMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_StandardMemory); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -335,16 +340,25 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory **ppThis, Dynamic *pPar status = __nvoc_ctor_StandardMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_StandardMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_StandardMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(StandardMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_standard_mem_nvoc.h b/src/nvidia/generated/g_standard_mem_nvoc.h index eae441bc61..1802285cca 100644 --- a/src/nvidia/generated/g_standard_mem_nvoc.h +++ b/src/nvidia/generated/g_standard_mem_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -55,11 +55,16 @@ typedef struct MemoryManager MemoryManager; /*! * Allocator for normal virtual, video and system memory */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_STANDARD_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct StandardMemory { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -81,13 +86,13 @@ struct StandardMemory { NvBool (*__stdmemIsGpuMapAllowed__)(struct StandardMemory *, struct OBJGPU *); NV_STATUS (*__stdmemUnmapFrom__)(struct StandardMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__stdmemControl_Epilogue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__stdmemControlLookup__)(struct StandardMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__stdmemControl__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemUnmap__)(struct StandardMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__stdmemGetMemInterMapParams__)(struct StandardMemory *, RMRES_MEM_INTER_MAP_PARAMS *); NV_STATUS (*__stdmemGetMemoryMappingDescriptor__)(struct StandardMemory *, MEMORY_DESCRIPTOR **); NV_STATUS (*__stdmemControlFilter__)(struct StandardMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__stdmemControlSerialization_Prologue__)(struct StandardMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__stdmemIsPartialUnmapSupported__)(struct StandardMemory *); NV_STATUS (*__stdmemIsReady__)(struct StandardMemory *, NvBool); NV_STATUS (*__stdmemCheckCopyPermissions__)(struct StandardMemory *, struct OBJGPU *, struct Device *); void (*__stdmemPreDestruct__)(struct StandardMemory *); @@ -137,13 +142,13 @@ NV_STATUS __nvoc_objCreate_StandardMemory(StandardMemory**, Dynamic*, NvU32, CAL #define stdmemIsGpuMapAllowed(pMemory, pGpu) stdmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define stdmemUnmapFrom(pResource, pParams) stdmemUnmapFrom_DISPATCH(pResource, pParams) #define stdmemControl_Epilogue(pResource, pCallContext, pParams) stdmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define stdmemControlLookup(pResource, pParams, ppEntry) stdmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define stdmemControl(pMemory, pCallContext, pParams) stdmemControl_DISPATCH(pMemory, pCallContext, pParams) #define stdmemUnmap(pMemory, pCallContext, pCpuMapping) stdmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define stdmemGetMemInterMapParams(pMemory, pParams) stdmemGetMemInterMapParams_DISPATCH(pMemory, pParams) #define stdmemGetMemoryMappingDescriptor(pMemory, ppMemDesc) stdmemGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define stdmemControlFilter(pResource, pCallContext, pParams) stdmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define stdmemControlSerialization_Prologue(pResource, pCallContext, pParams) stdmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define stdmemIsPartialUnmapSupported(pResource) stdmemIsPartialUnmapSupported_DISPATCH(pResource) #define stdmemIsReady(pMemory, bCopyConstructorContext) stdmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define stdmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) stdmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define stdmemPreDestruct(pResource) stdmemPreDestruct_DISPATCH(pResource) @@ -215,10 +220,6 @@ static inline void stdmemControl_Epilogue_DISPATCH(struct StandardMemory *pResou pResource->__stdmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS stdmemControlLookup_DISPATCH(struct StandardMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__stdmemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS stdmemControl_DISPATCH(struct StandardMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__stdmemControl__(pMemory, pCallContext, pParams); } @@ -243,6 +244,10 @@ static inline NV_STATUS stdmemControlSerialization_Prologue_DISPATCH(struct Stan return pResource->__stdmemControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool stdmemIsPartialUnmapSupported_DISPATCH(struct StandardMemory *pResource) { + return pResource->__stdmemIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS stdmemIsReady_DISPATCH(struct StandardMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__stdmemIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_subdevice_diag_nvoc.c b/src/nvidia/generated/g_subdevice_diag_nvoc.c index 024ea06e22..96f89eaaf1 100644 --- a/src/nvidia/generated/g_subdevice_diag_nvoc.c +++ b/src/nvidia/generated/g_subdevice_diag_nvoc.c @@ -171,10 +171,6 @@ static void __nvoc_thunk_RmResource_diagapiControl_Epilogue(struct DiagApi *pRes rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_diagapiControlLookup(struct DiagApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_diagapiGetInternalObjectHandle(struct DiagApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_DiagApi_GpuResource.offset)); } @@ -203,6 +199,10 @@ static NvBool __nvoc_thunk_RsResource_diagapiCanCopy(struct DiagApi *pResource) return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_diagapiIsPartialUnmapSupported(struct DiagApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_diagapiPreDestruct(struct DiagApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_DiagApi_RsResource.offset)); } @@ -566,8 +566,6 @@ static void __nvoc_init_funcTable_DiagApi_1(DiagApi *pThis) { pThis->__diagapiControl_Epilogue__ = &__nvoc_thunk_RmResource_diagapiControl_Epilogue; - pThis->__diagapiControlLookup__ = &__nvoc_thunk_RsResource_diagapiControlLookup; - pThis->__diagapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_diagapiGetInternalObjectHandle; pThis->__diagapiUnmap__ = &__nvoc_thunk_GpuResource_diagapiUnmap; @@ -582,6 +580,8 @@ static void __nvoc_init_funcTable_DiagApi_1(DiagApi *pThis) { pThis->__diagapiCanCopy__ = &__nvoc_thunk_RsResource_diagapiCanCopy; + pThis->__diagapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_diagapiIsPartialUnmapSupported; + pThis->__diagapiPreDestruct__ = &__nvoc_thunk_RsResource_diagapiPreDestruct; pThis->__diagapiIsDuplicate__ = &__nvoc_thunk_RsResource_diagapiIsDuplicate; @@ -617,21 +617,26 @@ void __nvoc_init_DiagApi(DiagApi *pThis) { __nvoc_init_funcTable_DiagApi(pThis); } -NV_STATUS __nvoc_objCreate_DiagApi(DiagApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_DiagApi(DiagApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; DiagApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(DiagApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(DiagApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_DiagApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -646,16 +651,25 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi **ppThis, Dynamic *pParent, NvU32 cre status = __nvoc_ctor_DiagApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_DiagApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_DiagApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(DiagApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_subdevice_diag_nvoc.h b/src/nvidia/generated/g_subdevice_diag_nvoc.h index f9742b9c3a..8057531c6a 100644 --- a/src/nvidia/generated/g_subdevice_diag_nvoc.h +++ b/src/nvidia/generated/g_subdevice_diag_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -44,11 +44,16 @@ extern "C" { /*! * RM internal class representing NV20_SUBDEVICE_DIAG */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SUBDEVICE_DIAG_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct DiagApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -89,7 +94,6 @@ struct DiagApi { NV_STATUS (*__diagapiInternalControlForward__)(struct DiagApi *, NvU32, void *, NvU32); NV_STATUS (*__diagapiUnmapFrom__)(struct DiagApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__diagapiControl_Epilogue__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__diagapiControlLookup__)(struct DiagApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__diagapiGetInternalObjectHandle__)(struct DiagApi *); NV_STATUS (*__diagapiUnmap__)(struct DiagApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); NV_STATUS (*__diagapiGetMemInterMapParams__)(struct DiagApi *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -97,6 +101,7 @@ struct DiagApi { NV_STATUS (*__diagapiUnregisterEvent__)(struct DiagApi *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__diagapiControlSerialization_Prologue__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__diagapiCanCopy__)(struct DiagApi *); + NvBool (*__diagapiIsPartialUnmapSupported__)(struct DiagApi *); void (*__diagapiPreDestruct__)(struct DiagApi *); NV_STATUS (*__diagapiIsDuplicate__)(struct DiagApi *, NvHandle, NvBool *); void (*__diagapiControlSerialization_Epilogue__)(struct DiagApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -163,7 +168,6 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi**, Dynamic*, NvU32, struct CALL_CONTE #define diagapiInternalControlForward(pGpuResource, command, pParams, size) diagapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define diagapiUnmapFrom(pResource, pParams) diagapiUnmapFrom_DISPATCH(pResource, pParams) #define diagapiControl_Epilogue(pResource, pCallContext, pParams) diagapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define diagapiControlLookup(pResource, pParams, ppEntry) diagapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define diagapiGetInternalObjectHandle(pGpuResource) diagapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define diagapiUnmap(pGpuResource, pCallContext, pCpuMapping) diagapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) #define diagapiGetMemInterMapParams(pRmResource, pParams) diagapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) @@ -171,6 +175,7 @@ NV_STATUS __nvoc_objCreate_DiagApi(DiagApi**, Dynamic*, NvU32, struct CALL_CONTE #define diagapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) diagapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define diagapiControlSerialization_Prologue(pResource, pCallContext, pParams) diagapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define diagapiCanCopy(pResource) diagapiCanCopy_DISPATCH(pResource) +#define diagapiIsPartialUnmapSupported(pResource) diagapiIsPartialUnmapSupported_DISPATCH(pResource) #define diagapiPreDestruct(pResource) diagapiPreDestruct_DISPATCH(pResource) #define diagapiIsDuplicate(pResource, hMemory, pDuplicate) diagapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define diagapiControlSerialization_Epilogue(pResource, pCallContext, pParams) diagapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -320,10 +325,6 @@ static inline void diagapiControl_Epilogue_DISPATCH(struct DiagApi *pResource, s pResource->__diagapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS diagapiControlLookup_DISPATCH(struct DiagApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__diagapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle diagapiGetInternalObjectHandle_DISPATCH(struct DiagApi *pGpuResource) { return pGpuResource->__diagapiGetInternalObjectHandle__(pGpuResource); } @@ -352,6 +353,10 @@ static inline NvBool diagapiCanCopy_DISPATCH(struct DiagApi *pResource) { return pResource->__diagapiCanCopy__(pResource); } +static inline NvBool diagapiIsPartialUnmapSupported_DISPATCH(struct DiagApi *pResource) { + return pResource->__diagapiIsPartialUnmapSupported__(pResource); +} + static inline void diagapiPreDestruct_DISPATCH(struct DiagApi *pResource) { pResource->__diagapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index 838ebad186..8ede4d8d03 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -171,10 +171,6 @@ static void __nvoc_thunk_RmResource_subdeviceControl_Epilogue(struct Subdevice * rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_subdeviceControlLookup(struct Subdevice *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_subdeviceGetInternalObjectHandle(struct Subdevice *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_Subdevice_GpuResource.offset)); } @@ -207,6 +203,10 @@ static NvBool __nvoc_thunk_RsResource_subdeviceCanCopy(struct Subdevice *pResour return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_subdeviceIsPartialUnmapSupported(struct Subdevice *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_RsResource_subdeviceIsDuplicate(struct Subdevice *pResource, NvHandle hMemory, NvBool *pDuplicate) { return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_Subdevice_RsResource.offset), hMemory, pDuplicate); } @@ -253,12 +253,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200812u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetNameString_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) - /*flags=*/ 0x200a12u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200812u) + /*flags=*/ 0x200812u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800110u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS), @@ -268,12 +268,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [2] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a12u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4812u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetShortNameString_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a12u) - /*flags=*/ 0x4a12u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4812u) + /*flags=*/ 0x4812u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800111u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS), @@ -463,12 +463,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [15] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a50u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryEccStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) - /*flags=*/ 0xa50u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryEccStatus_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a50u) + /*flags=*/ 0x400a50u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080012fu, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS), @@ -508,12 +508,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [18] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryEccConfiguration_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800133u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS), @@ -523,12 +523,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [19] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400204u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuSetEccConfiguration_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuSetEccConfiguration_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400204u) + /*flags=*/ 0x400204u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800134u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS), @@ -538,12 +538,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [20] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400204u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuResetEccErrorStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuResetEccErrorStatus_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400204u) + /*flags=*/ 0x400204u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800136u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS), @@ -673,12 +673,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [29] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetGidInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) - /*flags=*/ 0xa50u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + /*flags=*/ 0x850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080014au, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS), @@ -733,12 +733,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [33] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryIllumSupport_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryIllumSupport_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800153u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS), @@ -838,12 +838,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [40] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryScrubberStatus_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuQueryScrubberStatus_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080015fu, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS), @@ -1048,12 +1048,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [54] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400200u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuReportNonReplayableFault_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) - /*flags=*/ 0x200u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400200u) + /*flags=*/ 0x400200u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800177u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS), @@ -1138,12 +1138,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [60] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetPartitionCapacity_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800181u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS), @@ -1378,12 +1378,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [76] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGetP2pCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x208001a0u, /*paramSize=*/ sizeof(NV2080_CTRL_GET_P2P_CAPS_PARAMS), @@ -1423,12 +1423,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [79] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetChipDetails_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) - /*flags=*/ 0x4210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404210u) + /*flags=*/ 0x404210u, /*accessRight=*/0x0u, /*methodId=*/ 0x208001a4u, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS), @@ -1483,12 +1483,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [83] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x208001afu, /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS), @@ -1498,21 +1498,51 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [84] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalConfComputeEncryptionControl_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGpuGetConstructedFalconInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, /*accessRight=*/0x0u, - /*methodId=*/ 0x208001b2u, - /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS), + /*methodId=*/ 0x208001b0u, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalConfComputeEncryptionControl" + /*func=*/ "subdeviceCtrlCmdGpuGetConstructedFalconInfo" #endif }, { /* [85] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x640u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGspStartTrace_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x640u) + /*flags=*/ 0x640u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001e3u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalGspStartTrace" +#endif + }, + { /* [86] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlGpuGetFipsStatus_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + /*flags=*/ 0x204u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x208001e4u, + /*paramSize=*/ sizeof(NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlGpuGetFipsStatus" +#endif + }, + { /* [87] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1527,7 +1557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetNotification" #endif }, - { /* [86] */ + { /* [88] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1542,7 +1572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetTrigger" #endif }, - { /* [87] */ + { /* [89] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1557,7 +1587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetMemoryNotifies" #endif }, - { /* [88] */ + { /* [90] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1572,7 +1602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetSemaphoreMemory" #endif }, - { /* [89] */ + { /* [91] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1587,7 +1617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetSemaMemValidation" #endif }, - { /* [90] */ + { /* [92] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1602,7 +1632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventSetTriggerFifo" #endif }, - { /* [91] */ + { /* [93] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1617,7 +1647,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEventVideoBindEvtbuf" #endif }, - { /* [92] */ + { /* [94] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080030au, + /*paramSize=*/ sizeof(NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf" +#endif + }, + { /* [95] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1632,7 +1677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerSchedule" #endif }, - { /* [93] */ + { /* [96] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1647,7 +1692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerCancel" #endif }, - { /* [94] */ + { /* [97] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1662,7 +1707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetTime" #endif }, - { /* [95] */ + { /* [98] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1677,7 +1722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetRegisterOffset" #endif }, - { /* [96] */ + { /* [99] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1692,7 +1737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerGetGpuCpuTimeCorrelationInfo" #endif }, - { /* [97] */ + { /* [100] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1707,7 +1752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdTimerSetGrTickFreq" #endif }, - { /* [98] */ + { /* [101] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1722,7 +1767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cReadBuffer" #endif }, - { /* [99] */ + { /* [102] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1737,7 +1782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cWriteBuffer" #endif }, - { /* [100] */ + { /* [103] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1752,7 +1797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cReadReg" #endif }, - { /* [101] */ + { /* [104] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1767,13 +1812,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdI2cWriteReg" #endif }, - { /* [102] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [105] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400212u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetSKUInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetSKUInfo_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400212u) + /*flags=*/ 0x400212u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800808u, /*paramSize=*/ sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS), @@ -1782,13 +1827,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetSKUInfo" #endif }, - { /* [103] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [106] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetPostTime_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetPostTime_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800809u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS), @@ -1797,7 +1842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetPostTime" #endif }, - { /* [104] */ + { /* [107] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1812,7 +1857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetUefiSupport" #endif }, - { /* [105] */ + { /* [108] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1827,13 +1872,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetNbsiV2" #endif }, - { /* [106] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [109] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetInfoV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBiosGetInfoV2_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800810u, /*paramSize=*/ sizeof(NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS), @@ -1842,7 +1887,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBiosGetInfoV2" #endif }, - { /* [107] */ + { /* [110] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1857,13 +1902,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetStaticInfo" #endif }, - { /* [108] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [111] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5c0600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdMemSysGetStaticConfig_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdMemSysGetStaticConfig_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x5c0600u) + /*flags=*/ 0x5c0600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a1cu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS), @@ -1872,13 +1917,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysGetStaticConfig" #endif }, - { /* [109] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [112] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) + /*flags=*/ 0x400600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a1du, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS), @@ -1887,13 +1932,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer" #endif }, - { /* [110] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [113] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) + /*flags=*/ 0x400600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a1eu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS), @@ -1902,7 +1947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer" #endif }, - { /* [111] */ + { /* [114] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1917,7 +1962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetCaps" #endif }, - { /* [112] */ + { /* [115] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1932,7 +1977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags" #endif }, - { /* [113] */ + { /* [116] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1947,7 +1992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetGlobalSmOrder" #endif }, - { /* [114] */ + { /* [117] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1962,7 +2007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMsencGetCaps" #endif }, - { /* [115] */ + { /* [118] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1977,7 +2022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFloorsweepingMasks" #endif }, - { /* [116] */ + { /* [119] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -1992,7 +2037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferPtes" #endif }, - { /* [117] */ + { /* [120] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2007,7 +2052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFlcnSetVideoEventBufferMemory" #endif }, - { /* [118] */ + { /* [121] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2022,7 +2067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetInfo" #endif }, - { /* [119] */ + { /* [122] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2037,7 +2082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetZcullInfo" #endif }, - { /* [120] */ + { /* [123] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2052,7 +2097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetRopInfo" #endif }, - { /* [121] */ + { /* [124] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2067,7 +2112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPpcMasks" #endif }, - { /* [122] */ + { /* [125] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2e00u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2082,7 +2127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetContextBuffersInfo" #endif }, - { /* [123] */ + { /* [126] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2097,13 +2142,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetSmIssueRateModifier" #endif }, - { /* [124] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) + { /* [127] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGetChipInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) - /*flags=*/ 0x4600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404600u) + /*flags=*/ 0x404600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a36u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS), @@ -2112,7 +2157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetChipInfo" #endif }, - { /* [125] */ + { /* [128] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2127,7 +2172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsRecordSize" #endif }, - { /* [126] */ + { /* [129] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2142,13 +2187,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetFecsTraceDefines" #endif }, - { /* [127] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) + { /* [130] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c4600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGetDeviceInfoTable_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) - /*flags=*/ 0x4600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c4600u) + /*flags=*/ 0x1c4600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a40u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS), @@ -2157,7 +2202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetDeviceInfoTable" #endif }, - { /* [128] */ + { /* [131] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2172,22 +2217,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetUserRegisterAccessMap" #endif }, - { /* [129] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [132] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGetConstructedFalconInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + /*flags=*/ 0x2600u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20800a42u, - /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS), + /*methodId=*/ 0x20800a44u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdInternalGetConstructedFalconInfo" + /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange" #endif }, - { /* [130] */ + { /* [133] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2202,7 +2247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrInternalStaticGetPdbProperties" #endif }, - { /* [131] */ + { /* [134] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2217,7 +2262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayWriteInstMem" #endif }, - { /* [132] */ + { /* [135] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2232,7 +2277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRecoverAllComputeContexts" #endif }, - { /* [133] */ + { /* [136] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2247,7 +2292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetIpVersion" #endif }, - { /* [134] */ + { /* [137] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2262,7 +2307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetSmcMode" #endif }, - { /* [135] */ + { /* [138] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2277,7 +2322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetupRgLineIntr" #endif }, - { /* [136] */ + { /* [139] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2292,7 +2337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysSetPartitionableMem" #endif }, - { /* [137] */ + { /* [140] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2307,7 +2352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoPromoteRunlistBuffers" #endif }, - { /* [138] */ + { /* [141] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2322,7 +2367,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetImportedImpData" #endif }, - { /* [139] */ + { /* [142] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdIsEgpuBridge_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800a55u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdIsEgpuBridge" +#endif + }, + { /* [143] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2337,7 +2397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries" #endif }, - { /* [140] */ + { /* [144] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2352,13 +2412,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetChannelPushbuffer" #endif }, - { /* [141] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [145] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGmmuGetStaticInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) + /*flags=*/ 0x400600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a59u, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS), @@ -2367,7 +2427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGmmuGetStaticInfo" #endif }, - { /* [142] */ + { /* [146] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2382,7 +2442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetHeapReservationSize" #endif }, - { /* [143] */ + { /* [147] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2397,7 +2457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdIntrGetKernelTable" #endif }, - { /* [144] */ + { /* [148] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2412,7 +2472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayGetDisplayMask" #endif }, - { /* [145] */ + { /* [149] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2e50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2427,7 +2487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumChannels" #endif }, - { /* [146] */ + { /* [150] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2442,7 +2502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetProfiles" #endif }, - { /* [147] */ + { /* [151] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2457,7 +2517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetPartitionableEngines" #endif }, - { /* [148] */ + { /* [152] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2472,7 +2532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetSwizzIdFbMemPageRanges" #endif }, - { /* [149] */ + { /* [153] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2487,7 +2547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKMemSysGetMIGMemoryConfig" #endif }, - { /* [150] */ + { /* [154] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2502,7 +2562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetZbcReferenced" #endif }, - { /* [151] */ + { /* [155] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2517,7 +2577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRcWatchdogTimeout" #endif }, - { /* [152] */ + { /* [156] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2532,7 +2592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysGetMIGMemoryPartitionTable" #endif }, - { /* [153] */ + { /* [157] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2547,7 +2607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysL2InvalidateEvict" #endif }, - { /* [154] */ + { /* [158] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2562,7 +2622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysFlushL2AllRamsAndCaches" #endif }, - { /* [155] */ + { /* [159] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2577,7 +2637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysDisableNvlinkPeers" #endif }, - { /* [156] */ + { /* [160] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2592,7 +2652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMemSysProgramRawCompressionMode" #endif }, - { /* [157] */ + { /* [161] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2607,7 +2667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusFlushWithSysmembar" #endif }, - { /* [158] */ + { /* [162] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2622,7 +2682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal" #endif }, - { /* [159] */ + { /* [163] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2637,7 +2697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote" #endif }, - { /* [160] */ + { /* [164] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2652,7 +2712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusDestroyP2pMailbox" #endif }, - { /* [161] */ + { /* [165] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2667,7 +2727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusCreateC2cPeerMapping" #endif }, - { /* [162] */ + { /* [166] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2682,37 +2742,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalBusRemoveC2cPeerMapping" #endif }, - { /* [163] */ + { /* [167] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayUnixConsole_IMPL, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayPreUnixConsole_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a76u, - /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS), + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdDisplayUnixConsole" + /*func=*/ "subdeviceCtrlCmdDisplayPreUnixConsole" #endif }, - { /* [164] */ + { /* [168] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayPostVgaRestore_IMPL, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdDisplayPostUnixConsole_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*flags=*/ 0x600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a77u, - /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS), + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdDisplayPostVgaRestore" + /*func=*/ "subdeviceCtrlCmdDisplayPostUnixConsole" #endif }, - { /* [165] */ + { /* [169] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2727,7 +2787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfCudaLimitDisable" #endif }, - { /* [166] */ + { /* [170] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2742,7 +2802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit" #endif }, - { /* [167] */ + { /* [171] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2757,7 +2817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfOptpCliClear" #endif }, - { /* [168] */ + { /* [172] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2772,7 +2832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncSetControl" #endif }, - { /* [169] */ + { /* [173] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2787,7 +2847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfSyncGpuBoostSetLimits" #endif }, - { /* [170] */ + { /* [174] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2802,7 +2862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGpuBoostSyncGetInfo" #endif }, - { /* [171] */ + { /* [175] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2817,7 +2877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfGetAuxPowerState" #endif }, - { /* [172] */ + { /* [176] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2832,7 +2892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubPeerConnConfig" #endif }, - { /* [173] */ + { /* [177] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2847,7 +2907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubFirstLinkPeerId" #endif }, - { /* [174] */ + { /* [178] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2862,7 +2922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubGetHshubIdForLinks" #endif }, - { /* [175] */ + { /* [179] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2877,7 +2937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubGetNumUnits" #endif }, - { /* [176] */ + { /* [180] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2892,7 +2952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubNextHshubId" #endif }, - { /* [177] */ + { /* [181] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2907,7 +2967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdHshubEgmConfig" #endif }, - { /* [178] */ + { /* [182] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2922,7 +2982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationCheck" #endif }, - { /* [179] */ + { /* [183] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2937,7 +2997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPerfmonClientReservationSet" #endif }, - { /* [180] */ + { /* [184] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2952,13 +3012,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_2x" #endif }, - { /* [181] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [185] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) + /*flags=*/ 0x400600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a9bu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS), @@ -2967,13 +3027,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer" #endif }, - { /* [182] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [186] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) + /*flags=*/ 0x400600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800a9cu, /*paramSize=*/ 0, @@ -2982,7 +3042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer" #endif }, - { /* [183] */ + { /* [187] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2997,7 +3057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuRegisterClientShadowFaultBuffer" #endif }, - { /* [184] */ + { /* [188] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3012,7 +3072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuUnregisterClientShadowFaultBuffer" #endif }, - { /* [185] */ + { /* [189] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3027,7 +3087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGmmuCopyReservedSplitGVASpacePdesServer" #endif }, - { /* [186] */ + { /* [190] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3042,7 +3102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostSet_3x" #endif }, - { /* [187] */ + { /* [191] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3057,7 +3117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfBoostClear_3x" #endif }, - { /* [188] */ + { /* [192] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3072,7 +3132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance" #endif }, - { /* [189] */ + { /* [193] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3087,13 +3147,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance" #endif }, - { /* [190] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + { /* [194] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBifGetStaticInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - /*flags=*/ 0x600u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) + /*flags=*/ 0x400600u, /*accessRight=*/0x0u, /*methodId=*/ 0x20800aacu, /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS), @@ -3102,7 +3162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifGetStaticInfo" #endif }, - { /* [191] */ + { /* [195] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3117,7 +3177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr" #endif }, - { /* [192] */ + { /* [196] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3132,7 +3192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr" #endif }, - { /* [193] */ + { /* [197] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3147,7 +3207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifGetAspmL1Flags" #endif }, - { /* [194] */ + { /* [198] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3162,7 +3222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount" #endif }, - { /* [195] */ + { /* [199] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3177,7 +3237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuMap" #endif }, - { /* [196] */ + { /* [200] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3192,7 +3252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuUnmap" #endif }, - { /* [197] */ + { /* [201] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3207,7 +3267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalSetP2pCaps" #endif }, - { /* [198] */ + { /* [202] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3222,7 +3282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalRemoveP2pCaps" #endif }, - { /* [199] */ + { /* [203] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3237,7 +3297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetPcieP2pCaps" #endif }, - { /* [200] */ + { /* [204] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3252,7 +3312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifSetPcieRo" #endif }, - { /* [201] */ + { /* [205] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3267,7 +3327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles" #endif }, - { /* [202] */ + { /* [206] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3282,7 +3342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCcuSetStreamState" #endif }, - { /* [203] */ + { /* [207] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3297,7 +3357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalInitGpuIntr" #endif }, - { /* [204] */ + { /* [208] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3312,7 +3372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncOptimizeTiming" #endif }, - { /* [205] */ + { /* [209] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3327,7 +3387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncGetDisplayIds" #endif }, - { /* [206] */ + { /* [210] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3342,7 +3402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncSetStereoSync" #endif }, - { /* [207] */ + { /* [211] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3357,7 +3417,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFbsrInit" #endif }, - { /* [208] */ + { /* [212] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3372,7 +3432,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFbsrSendRegionInfo" #endif }, - { /* [209] */ + { /* [213] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3387,7 +3447,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncGetVactiveLines" #endif }, - { /* [210] */ + { /* [214] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3402,7 +3462,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb" #endif }, - { /* [211] */ + { /* [215] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3417,7 +3477,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPostInitBrightcStateLoad" #endif }, - { /* [212] */ + { /* [216] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3432,7 +3492,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetNumActiveLinksPerIoctrl" #endif }, - { /* [213] */ + { /* [217] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3447,7 +3507,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalNvlinkGetTotalNumLinksPerIoctrl" #endif }, - { /* [214] */ + { /* [218] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3462,7 +3522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncIsDisplayIdValid" #endif }, - { /* [215] */ + { /* [219] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3477,7 +3537,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGsyncSetOrRestoreGpioRasterSync" #endif }, - { /* [216] */ + { /* [220] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3492,7 +3552,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalSmbpbiPfmReqHndlrCapUpdate" #endif }, - { /* [217] */ + { /* [221] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3507,7 +3567,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrStateLoadSync" #endif }, - { /* [218] */ + { /* [222] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3522,7 +3582,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalThermPfmReqHndlrStateInitSync" #endif }, - { /* [219] */ + { /* [223] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3537,7 +3597,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetPm1State" #endif }, - { /* [220] */ + { /* [224] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3552,7 +3612,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrSetPm1State" #endif }, - { /* [221] */ + { /* [225] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3567,7 +3627,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrUpdateEdppLimit" #endif }, - { /* [222] */ + { /* [226] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3582,7 +3642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalThermPfmReqHndlrUpdateTgpuLimit" #endif }, - { /* [223] */ + { /* [227] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3597,7 +3657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTgpMode" #endif }, - { /* [224] */ + { /* [228] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3612,7 +3672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrConfigureTurboV2" #endif }, - { /* [225] */ + { /* [229] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3627,7 +3687,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo" #endif }, - { /* [226] */ + { /* [230] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3642,7 +3702,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping" #endif }, - { /* [227] */ + { /* [231] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3657,7 +3717,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPerfPfmReqHndlrSetVpstate" #endif }, - { /* [228] */ + { /* [232] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2610u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3672,7 +3732,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalFifoGetNumSecureChannels" #endif }, - { /* [229] */ + { /* [233] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3687,7 +3747,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSpdmPartition" #endif }, - { /* [230] */ + { /* [234] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3702,7 +3762,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetCoherentFbApertureSize" #endif }, - { /* [231] */ + { /* [235] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3717,7 +3777,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBifDisableSystemMemoryAccess" #endif }, - { /* [232] */ + { /* [236] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3732,7 +3792,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplayPinsetsToLockpins" #endif }, - { /* [233] */ + { /* [237] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3747,7 +3807,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalDetectHsVideoBridge" #endif }, - { /* [234] */ + { /* [238] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3762,7 +3822,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDisplaySetSliLinkGpioSwControl" #endif }, - { /* [235] */ + { /* [239] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3777,7 +3837,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalSetStaticEdidData" #endif }, - { /* [236] */ + { /* [240] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3792,7 +3852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys" #endif }, - { /* [237] */ + { /* [241] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3807,7 +3867,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalConfComputeDeriveLceKeys" #endif }, - { /* [238] */ + { /* [242] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdInternalConfComputeSetGpuState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ae7u, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdInternalConfComputeSetGpuState" +#endif + }, + { /* [243] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3822,7 +3897,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated" #endif }, - { /* [239] */ + { /* [244] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3837,7 +3912,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalDisplayPreModeSet" #endif }, - { /* [240] */ + { /* [245] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3852,7 +3927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalDisplayPostModeSet" #endif }, - { /* [241] */ + { /* [246] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3867,7 +3942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalConfComputeGetStaticInfo" #endif }, - { /* [242] */ + { /* [247] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3882,7 +3957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp" #endif }, - { /* [243] */ + { /* [248] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3897,7 +3972,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGetLocalAtsConfig" #endif }, - { /* [244] */ + { /* [249] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3912,7 +3987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalSetPeerAtsConfig" #endif }, - { /* [245] */ + { /* [250] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3927,7 +4002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalPmgrPfmReqHndlrGetEdppLimitInfo" #endif }, - { /* [246] */ + { /* [251] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3942,7 +4017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalInitUserSharedData" #endif }, - { /* [247] */ + { /* [252] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3957,7 +4032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalUserSharedDataSetDataPoll" #endif }, - { /* [248] */ + { /* [253] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3972,7 +4047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetGpfifo" #endif }, - { /* [249] */ + { /* [254] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3987,7 +4062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoBindEngines" #endif }, - { /* [250] */ + { /* [255] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4002,7 +4077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetOperationalProperties" #endif }, - { /* [251] */ + { /* [256] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4017,7 +4092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetPhysicalChannelCount" #endif }, - { /* [252] */ + { /* [257] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4032,7 +4107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetInfo" #endif }, - { /* [253] */ + { /* [258] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4047,7 +4122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableChannels" #endif }, - { /* [254] */ + { /* [259] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4062,7 +4137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetChannelMemInfo" #endif }, - { /* [255] */ + { /* [260] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4077,7 +4152,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetUserdLocation" #endif }, - { /* [256] */ + { /* [261] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoObjschedSwGetLog_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080110eu, + /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdFifoObjschedSwGetLog" +#endif + }, + { /* [262] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4092,7 +4182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetDeviceInfoTable" #endif }, - { /* [257] */ + { /* [263] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4107,7 +4197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoClearFaultedBit" #endif }, - { /* [258] */ + { /* [264] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2310u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4122,7 +4212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoRunlistSetSchedPolicy" #endif }, - { /* [259] */ + { /* [265] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4137,7 +4227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoUpdateChannelInfo" #endif }, - { /* [260] */ + { /* [266] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4152,7 +4242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableUsermodeChannels" #endif }, - { /* [261] */ + { /* [267] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4167,7 +4257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb" #endif }, - { /* [262] */ + { /* [268] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4182,8 +4272,68 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetAllocatedChannels" #endif }, - { /* [263] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [269] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoDisableChannelsForKeyRotation_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080111au, + /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdFifoDisableChannelsForKeyRotation" +#endif + }, + { /* [270] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoObjschedGetState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801120u, + /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdFifoObjschedGetState" +#endif + }, + { /* [271] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoObjschedSetState_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801121u, + /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdFifoObjschedSetState" +#endif + }, + { /* [272] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFifoObjschedGetCaps_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20801122u, + /*paramSize=*/ sizeof(NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdFifoObjschedGetCaps" +#endif + }, + { /* [273] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrGetInfo_IMPL, @@ -4197,7 +4347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfo" #endif }, - { /* [264] */ + { /* [274] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4212,7 +4362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullMode" #endif }, - { /* [265] */ + { /* [275] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4227,7 +4377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullInfo" #endif }, - { /* [266] */ + { /* [276] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4242,13 +4392,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmMode" #endif }, - { /* [267] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + { /* [277] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x802a10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrCtxswZcullBind_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) - /*flags=*/ 0x2210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x802a10u) + /*flags=*/ 0x802a10u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801208u, /*paramSize=*/ sizeof(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS), @@ -4257,7 +4407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullBind" #endif }, - { /* [268] */ + { /* [278] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4272,7 +4422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmBind" #endif }, - { /* [269] */ + { /* [279] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4287,7 +4437,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetGpcTileMap" #endif }, - { /* [270] */ + { /* [280] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4302,7 +4452,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswSmpcMode" #endif }, - { /* [271] */ + { /* [281] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4317,7 +4467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmToGpcTpcMappings" #endif }, - { /* [272] */ + { /* [282] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4332,7 +4482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetCtxswPreemptionMode" #endif }, - { /* [273] */ + { /* [283] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4347,7 +4497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPreemptionBind" #endif }, - { /* [274] */ + { /* [284] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4362,7 +4512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrPcSamplingMode" #endif }, - { /* [275] */ + { /* [285] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4377,7 +4527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetROPInfo" #endif }, - { /* [276] */ + { /* [286] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4392,7 +4542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswStats" #endif }, - { /* [277] */ + { /* [287] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4407,7 +4557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferSize" #endif }, - { /* [278] */ + { /* [288] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x80000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4422,7 +4572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferInfo" #endif }, - { /* [279] */ + { /* [289] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4437,7 +4587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGlobalSmOrder" #endif }, - { /* [280] */ + { /* [290] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4452,7 +4602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCurrentResidentChannel" #endif }, - { /* [281] */ + { /* [291] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4467,7 +4617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetVatAlarmData" #endif }, - { /* [282] */ + { /* [292] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4482,7 +4632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetAttributeBufferSize" #endif }, - { /* [283] */ + { /* [293] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4497,7 +4647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolQuerySize" #endif }, - { /* [284] */ + { /* [294] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4512,7 +4662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolInitialize" #endif }, - { /* [285] */ + { /* [295] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4527,7 +4677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolAddSlots" #endif }, - { /* [286] */ + { /* [296] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4542,7 +4692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolRemoveSlots" #endif }, - { /* [287] */ + { /* [297] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4557,7 +4707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [288] */ + { /* [298] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4572,7 +4722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [289] */ + { /* [299] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4587,7 +4737,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcMask" #endif }, - { /* [290] */ + { /* [300] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4602,7 +4752,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetTpcMask" #endif }, - { /* [291] */ + { /* [301] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4617,7 +4767,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [292] */ + { /* [302] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4632,7 +4782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetEngineContextProperties" #endif }, - { /* [293] */ + { /* [303] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4647,7 +4797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmIssueRateModifier" #endif }, - { /* [294] */ + { /* [304] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4662,7 +4812,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUid" #endif }, - { /* [295] */ + { /* [305] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4677,7 +4827,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPhysGpcMask" #endif }, - { /* [296] */ + { /* [306] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4692,7 +4842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPpcMask" #endif }, - { /* [297] */ + { /* [307] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4707,7 +4857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetNumTpcsForGpc" #endif }, - { /* [298] */ + { /* [308] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4722,7 +4872,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswModes" #endif }, - { /* [299] */ + { /* [309] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4737,7 +4887,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcTileMap" #endif }, - { /* [300] */ + { /* [310] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4752,7 +4902,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullMask" #endif }, - { /* [301] */ + { /* [311] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4767,7 +4917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2" #endif }, - { /* [302] */ + { /* [312] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4782,22 +4932,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGfxGpcAndTpcInfo" #endif }, - { /* [303] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [313] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFbGetInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKGrCtxswSetupBind_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, - /*methodId=*/ 0x20801301u, - /*paramSize=*/ sizeof(NV2080_CTRL_FB_GET_INFO_PARAMS), + /*methodId=*/ 0x2080123au, + /*paramSize=*/ sizeof(NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS), /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdFbGetInfo" + /*func=*/ "subdeviceCtrlCmdKGrCtxswSetupBind" #endif }, - { /* [304] */ + { /* [314] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4812,7 +4962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfoV2" #endif }, - { /* [305] */ + { /* [315] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4827,7 +4977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCarveoutAddressInfo" #endif }, - { /* [306] */ + { /* [316] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4842,7 +4992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCalibrationLockFailed" #endif }, - { /* [307] */ + { /* [317] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4857,7 +5007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbFlushGpuCache" #endif }, - { /* [308] */ + { /* [318] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4872,7 +5022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicy" #endif }, - { /* [309] */ + { /* [319] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4887,7 +5037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetBar1Offset" #endif }, - { /* [310] */ + { /* [320] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4902,7 +5052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicy" #endif }, - { /* [311] */ + { /* [321] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4917,13 +5067,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbIsKind" #endif }, - { /* [312] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) + { /* [322] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a10u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFbGetGpuCacheInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) - /*flags=*/ 0xa10u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a10u) + /*flags=*/ 0x400a10u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801315u, /*paramSize=*/ sizeof(NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS), @@ -4932,7 +5082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheInfo" #endif }, - { /* [313] */ + { /* [323] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4947,7 +5097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicyV2" #endif }, - { /* [314] */ + { /* [324] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4962,7 +5112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2" #endif }, - { /* [315] */ + { /* [325] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4977,7 +5127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFBRegionInfo" #endif }, - { /* [316] */ + { /* [326] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4992,13 +5142,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetOfflinedPages" #endif }, - { /* [317] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) + { /* [327] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a50u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFbGetLTCInfoForFBP_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) - /*flags=*/ 0xa50u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a50u) + /*flags=*/ 0x2a50u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801328u, /*paramSize=*/ sizeof(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS), @@ -5007,7 +5157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetLTCInfoForFBP" #endif }, - { /* [318] */ + { /* [328] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5022,7 +5172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbCBCOp" #endif }, - { /* [319] */ + { /* [329] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5037,7 +5187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCtagsForCbcEviction" #endif }, - { /* [320] */ + { /* [330] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5052,7 +5202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetupVprRegion" #endif }, - { /* [321] */ + { /* [331] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5067,7 +5217,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCliManagedOfflinedPages" #endif }, - { /* [322] */ + { /* [332] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5082,7 +5232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCompBitCopyConstructInfo" #endif }, - { /* [323] */ + { /* [333] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5097,7 +5247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetRrd" #endif }, - { /* [324] */ + { /* [334] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5112,7 +5262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetReadLimit" #endif }, - { /* [325] */ + { /* [335] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5127,7 +5277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetWriteLimit" #endif }, - { /* [326] */ + { /* [336] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5142,7 +5292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbPatchPbrForMining" #endif }, - { /* [327] */ + { /* [337] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5157,7 +5307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetMemAlignment" #endif }, - { /* [328] */ + { /* [338] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5172,13 +5322,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRemappedRows" #endif }, - { /* [329] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [339] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFbGetFsInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801346u, /*paramSize=*/ sizeof(NV2080_CTRL_FB_GET_FS_INFO_PARAMS), @@ -5187,7 +5337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFsInfo" #endif }, - { /* [330] */ + { /* [340] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5202,7 +5352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRowRemapperHistogram" #endif }, - { /* [331] */ + { /* [341] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5217,7 +5367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetDynamicOfflinedPages" #endif }, - { /* [332] */ + { /* [342] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5232,7 +5382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbUpdateNumaStatus" #endif }, - { /* [333] */ + { /* [343] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5247,7 +5397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetNumaInfo" #endif }, - { /* [334] */ + { /* [344] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4811u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5262,7 +5412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout" #endif }, - { /* [335] */ + { /* [345] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4813u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5277,7 +5427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetArchInfo" #endif }, - { /* [336] */ + { /* [346] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5292,7 +5442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcServiceInterrupts" #endif }, - { /* [337] */ + { /* [347] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5307,7 +5457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetManufacturer" #endif }, - { /* [338] */ + { /* [348] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5322,7 +5472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcQueryHostclkSlowdownStatus" #endif }, - { /* [339] */ + { /* [349] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5337,7 +5487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcSetHostclkSlowdownStatus" #endif }, - { /* [340] */ + { /* [350] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5352,7 +5502,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcChangeReplayableFaultOwnership" #endif }, - { /* [341] */ + { /* [351] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdMcGetEngineNotificationIntrVectors_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080170du, + /*paramSize=*/ sizeof(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdMcGetEngineNotificationIntrVectors" +#endif + }, + { /* [352] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdMcGetStaticIntrTable_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080170eu, + /*paramSize=*/ sizeof(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdMcGetStaticIntrTable" +#endif + }, + { /* [353] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5367,7 +5547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciInfo" #endif }, - { /* [342] */ + { /* [354] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5382,7 +5562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfo" #endif }, - { /* [343] */ + { /* [355] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5397,7 +5577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciBarInfo" #endif }, - { /* [344] */ + { /* [356] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5412,7 +5592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLinkWidth" #endif }, - { /* [345] */ + { /* [357] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5427,7 +5607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieSpeed" #endif }, - { /* [346] */ + { /* [358] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5442,7 +5622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetHwbcUpstreamPcieSpeed" #endif }, - { /* [347] */ + { /* [359] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5457,7 +5637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetHwbcUpstreamPcieSpeed" #endif }, - { /* [348] */ + { /* [360] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5472,7 +5652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusHWBCGetUpstreamBAR0" #endif }, - { /* [349] */ + { /* [361] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5487,7 +5667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusServiceGpuMultifunctionState" #endif }, - { /* [350] */ + { /* [362] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5502,7 +5682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexCounters" #endif }, - { /* [351] */ + { /* [363] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5517,7 +5697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexCounters" #endif }, - { /* [352] */ + { /* [364] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5532,7 +5712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusFreezePexCounters" #endif }, - { /* [353] */ + { /* [365] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5547,7 +5727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexLaneCounters" #endif }, - { /* [354] */ + { /* [366] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5562,7 +5742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieLtrLatency" #endif }, - { /* [355] */ + { /* [367] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5577,7 +5757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLtrLatency" #endif }, - { /* [356] */ + { /* [368] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5592,7 +5772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexUtilCounters" #endif }, - { /* [357] */ + { /* [369] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5607,7 +5787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexUtilCounters" #endif }, - { /* [358] */ + { /* [370] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5622,7 +5802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetBFD" #endif }, - { /* [359] */ + { /* [371] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5637,7 +5817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetAspmDisableFlags" #endif }, - { /* [360] */ + { /* [372] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5652,7 +5832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfoV2" #endif }, - { /* [361] */ + { /* [373] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5667,7 +5847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusControlPublicAspmBits" #endif }, - { /* [362] */ + { /* [374] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5682,7 +5862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkPeerIdMask" #endif }, - { /* [363] */ + { /* [375] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5697,7 +5877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetEomParameters" #endif }, - { /* [364] */ + { /* [376] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5712,7 +5892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetUphyDlnCfgSpace" #endif }, - { /* [365] */ + { /* [377] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5727,13 +5907,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetEomStatus" #endif }, - { /* [366] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) + { /* [378] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) - /*flags=*/ 0x6210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404210u) + /*flags=*/ 0x404210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20801829u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS), @@ -5742,7 +5922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieReqAtomicsCaps" #endif }, - { /* [367] */ + { /* [379] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5757,13 +5937,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics" #endif }, - { /* [368] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [380] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetC2CInfo_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + /*flags=*/ 0x2210u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080182bu, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS), @@ -5772,7 +5952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetC2CInfo" #endif }, - { /* [369] */ + { /* [381] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10000u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5787,13 +5967,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSysmemAccess" #endif }, - { /* [370] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) + { /* [382] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x500200u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusSetP2pMapping_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) - /*flags=*/ 0x100200u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusSetP2pMapping_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x500200u) + /*flags=*/ 0x500200u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080182eu, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS), @@ -5802,13 +5982,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetP2pMapping" #endif }, - { /* [371] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) + { /* [383] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x500200u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusUnsetP2pMapping_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) - /*flags=*/ 0x100200u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusUnsetP2pMapping_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x500200u) + /*flags=*/ 0x500200u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080182fu, /*paramSize=*/ sizeof(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS), @@ -5817,13 +5997,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusUnsetP2pMapping" #endif }, - { /* [372] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [384] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdKPerfBoost_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + /*flags=*/ 0x2850u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080200au, /*paramSize=*/ sizeof(NV2080_CTRL_PERF_BOOST_PARAMS), @@ -5832,7 +6012,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKPerfBoost" #endif }, - { /* [373] */ + { /* [385] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfGetLevelInfo_V2_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080200bu, + /*paramSize=*/ sizeof(NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdPerfGetLevelInfo_V2" +#endif + }, + { /* [386] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfGetPowerstate_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080205au, + /*paramSize=*/ sizeof(NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdPerfGetPowerstate" +#endif + }, + { /* [387] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5847,7 +6057,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfSetPowerstate" #endif }, - { /* [374] */ + { /* [388] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfNotifyVideoevent_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080205du, + /*paramSize=*/ sizeof(NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdPerfNotifyVideoevent" +#endif + }, + { /* [389] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfGetCurrentPstate_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802068u, + /*paramSize=*/ sizeof(NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdPerfGetCurrentPstate" +#endif + }, + { /* [390] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5862,7 +6102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpGetControl" #endif }, - { /* [375] */ + { /* [391] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5877,7 +6117,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpSetControl" #endif }, - { /* [376] */ + { /* [392] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20802087u, + /*paramSize=*/ sizeof(NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample" +#endif + }, + { /* [393] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5892,7 +6147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfSetAuxPowerState" #endif }, - { /* [377] */ + { /* [394] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5907,13 +6162,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfReservePerfmonHw" #endif }, - { /* [378] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [395] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x20802096u, /*paramSize=*/ sizeof(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS), @@ -5922,7 +6177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2" #endif }, - { /* [379] */ + { /* [396] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5937,7 +6192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReadVirtualMem" #endif }, - { /* [380] */ + { /* [397] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5952,7 +6207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorCount" #endif }, - { /* [381] */ + { /* [398] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5967,7 +6222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSetCleanErrorHistory" #endif }, - { /* [382] */ + { /* [399] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5982,7 +6237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetWatchdogInfo" #endif }, - { /* [383] */ + { /* [400] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5997,7 +6252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcDisableWatchdog" #endif }, - { /* [384] */ + { /* [401] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6012,7 +6267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcEnableWatchdog" #endif }, - { /* [385] */ + { /* [402] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6027,7 +6282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReleaseWatchdogRequests" #endif }, - { /* [386] */ + { /* [403] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6042,7 +6297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcRecovery" #endif }, - { /* [387] */ + { /* [404] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6057,7 +6312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcRecovery" #endif }, - { /* [388] */ + { /* [405] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6072,7 +6327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSoftDisableWatchdog" #endif }, - { /* [389] */ + { /* [406] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6087,7 +6342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcInfo" #endif }, - { /* [390] */ + { /* [407] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6102,7 +6357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcInfo" #endif }, - { /* [391] */ + { /* [408] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6117,7 +6372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorV2" #endif }, - { /* [392] */ + { /* [409] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6132,7 +6387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioProgramDirection" #endif }, - { /* [393] */ + { /* [410] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6147,7 +6402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioProgramOutput" #endif }, - { /* [394] */ + { /* [411] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6162,7 +6417,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioReadInput" #endif }, - { /* [395] */ + { /* [412] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6177,7 +6432,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdInternalGpioActivateHwFunction" #endif }, - { /* [396] */ + { /* [413] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6192,7 +6447,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDumpSize" #endif }, - { /* [397] */ + { /* [414] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6207,7 +6462,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDump" #endif }, - { /* [398] */ + { /* [415] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6222,7 +6477,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetNocatJournalRpt" #endif }, - { /* [399] */ + { /* [416] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6237,7 +6492,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdSetNocatJournalData" #endif }, - { /* [400] */ + { /* [417] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvdInsertNocatJournalRecord_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) + /*flags=*/ 0x7u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080240cu, + /*paramSize=*/ sizeof(NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvdInsertNocatJournalRecord" +#endif + }, + { /* [418] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6252,7 +6522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [401] */ + { /* [419] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6267,7 +6537,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaGetInfo" #endif }, - { /* [402] */ + { /* [420] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6282,7 +6552,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPmgrGetModuleInfo" #endif }, - { /* [403] */ + { /* [421] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6297,7 +6567,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGpuProcessPostGc6ExitTasks" #endif }, - { /* [404] */ + { /* [422] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6312,7 +6582,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGc6Entry" #endif }, - { /* [405] */ + { /* [423] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6327,7 +6597,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGc6Exit" #endif }, - { /* [406] */ + { /* [424] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6342,7 +6612,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLpwrDifrCtrl" #endif }, - { /* [407] */ + { /* [425] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6357,7 +6627,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdLpwrDifrPrefetchResponse" #endif }, - { /* [408] */ + { /* [426] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6372,7 +6642,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCaps" #endif }, - { /* [409] */ + { /* [427] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6387,7 +6657,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCePceMask" #endif }, - { /* [410] */ + { /* [428] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6402,7 +6672,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCapsV2" #endif }, - { /* [411] */ + { /* [429] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6417,7 +6687,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdatePceLceMappings" #endif }, - { /* [412] */ + { /* [430] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6432,7 +6702,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdateClassDB" #endif }, - { /* [413] */ + { /* [431] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100e40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6447,7 +6717,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetPhysicalCaps" #endif }, - { /* [414] */ + { /* [432] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c0200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6462,7 +6732,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetFaultMethodBufferSize" #endif }, - { /* [415] */ + { /* [433] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6477,7 +6747,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetHubPceMask" #endif }, - { /* [416] */ + { /* [434] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6492,7 +6762,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllCaps" #endif }, - { /* [417] */ + { /* [435] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6507,13 +6777,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllPhysicalCaps" #endif }, - { /* [418] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + { /* [436] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBusGetNvlinkCaps_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - /*flags=*/ 0x850u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + /*flags=*/ 0x2850u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803001u, /*paramSize=*/ sizeof(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS), @@ -6522,7 +6792,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkCaps" #endif }, - { /* [419] */ + { /* [437] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6537,7 +6807,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkStatus" #endif }, - { /* [420] */ + { /* [438] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6552,7 +6822,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkErrInfo" #endif }, - { /* [421] */ + { /* [439] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6567,7 +6837,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetNvlinkCounters" #endif }, - { /* [422] */ + { /* [440] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6582,7 +6852,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdClearNvlinkCounters" #endif }, - { /* [423] */ + { /* [441] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6597,7 +6867,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts" #endif }, - { /* [424] */ + { /* [442] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6612,7 +6882,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupEom" #endif }, - { /* [425] */ + { /* [443] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6627,7 +6897,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetPowerState" #endif }, - { /* [426] */ + { /* [444] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6642,7 +6912,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinGetLinkFomValues" #endif }, - { /* [427] */ + { /* [445] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6657,7 +6927,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkEccErrors" #endif }, - { /* [428] */ + { /* [446] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6672,7 +6942,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkReadTpCounters" #endif }, - { /* [429] */ + { /* [447] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6687,7 +6957,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableNvlinkPeer" #endif }, - { /* [430] */ + { /* [448] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6702,7 +6972,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLpCounters" #endif }, - { /* [431] */ + { /* [449] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6717,7 +6987,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkCoreCallback" #endif }, - { /* [432] */ + { /* [450] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6732,7 +7002,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetAliEnabled" #endif }, - { /* [433] */ + { /* [451] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6747,7 +7017,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid" #endif }, - { /* [434] */ + { /* [452] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6762,7 +7032,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateHshubMux" #endif }, - { /* [435] */ + { /* [453] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6777,7 +7047,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreSetupNvlinkPeer" #endif }, - { /* [436] */ + { /* [454] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6792,7 +7062,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostSetupNvlinkPeer" #endif }, - { /* [437] */ + { /* [455] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6807,7 +7077,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkRemoveNvlinkMapping" #endif }, - { /* [438] */ + { /* [456] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6822,7 +7092,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSaveRestoreHshubState" #endif }, - { /* [439] */ + { /* [457] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6837,7 +7107,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramBufferready" #endif }, - { /* [440] */ + { /* [458] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6852,7 +7122,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateCurrentConfig" #endif }, - { /* [441] */ + { /* [459] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6867,7 +7137,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetLoopbackMode" #endif }, - { /* [442] */ + { /* [460] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6882,7 +7152,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdatePeerLinkMask" #endif }, - { /* [443] */ + { /* [461] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6897,7 +7167,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateLinkConnection" #endif }, - { /* [444] */ + { /* [462] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6912,7 +7182,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinksPostTopology" #endif }, - { /* [445] */ + { /* [463] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6927,7 +7197,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreLinkTrainAli" #endif }, - { /* [446] */ + { /* [464] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6942,7 +7212,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetRefreshCounters" #endif }, - { /* [447] */ + { /* [465] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6957,7 +7227,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkClearRefreshCounters" #endif }, - { /* [448] */ + { /* [466] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6972,7 +7242,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet" #endif }, - { /* [449] */ + { /* [467] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6987,7 +7257,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkLinkTrainAli" #endif }, - { /* [450] */ + { /* [468] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7002,7 +7272,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo" #endif }, - { /* [451] */ + { /* [469] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7017,7 +7287,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo" #endif }, - { /* [452] */ + { /* [470] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7032,7 +7302,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramLinkSpeed" #endif }, - { /* [453] */ + { /* [471] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7047,7 +7317,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkAreLinksTrained" #endif }, - { /* [454] */ + { /* [472] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7062,7 +7332,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkResetLinks" #endif }, - { /* [455] */ + { /* [473] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7077,7 +7347,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDisableDlInterrupts" #endif }, - { /* [456] */ + { /* [474] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7092,7 +7362,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkAndClockInfo" #endif }, - { /* [457] */ + { /* [475] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7107,7 +7377,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupNvlinkSysmem" #endif }, - { /* [458] */ + { /* [476] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7122,7 +7392,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessForcedConfigs" #endif }, - { /* [459] */ + { /* [477] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7137,7 +7407,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLaneShutdownProps" #endif }, - { /* [460] */ + { /* [478] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7152,7 +7422,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableSysmemNvlinkAts" #endif }, - { /* [461] */ + { /* [479] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7167,7 +7437,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkHshubGetSysmemNvlinkMask" #endif }, - { /* [462] */ + { /* [480] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7182,7 +7452,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr" #endif }, - { /* [463] */ + { /* [481] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7197,7 +7467,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo" #endif }, - { /* [464] */ + { /* [482] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7212,7 +7482,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinks" #endif }, - { /* [465] */ + { /* [483] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7227,7 +7497,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessInitDisabledLinks" #endif }, - { /* [466] */ + { /* [484] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7242,7 +7512,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEomControl" #endif }, - { /* [467] */ + { /* [485] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7257,7 +7527,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetL1Threshold" #endif }, - { /* [468] */ + { /* [486] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7272,7 +7542,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetL1Threshold" #endif }, - { /* [469] */ + { /* [487] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1240u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7287,7 +7557,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkInbandSendData" #endif }, - { /* [470] */ + { /* [488] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7302,7 +7572,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDirectConnectCheck" #endif }, - { /* [471] */ + { /* [489] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7317,7 +7587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostFaultUp" #endif }, - { /* [472] */ + { /* [490] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7332,22 +7602,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetPortEvents" #endif }, - { /* [473] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*pFunc=*/ (void (*)(void)) NULL, -#else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkCycleLink_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - /*flags=*/ 0x204u, - /*accessRight=*/0x0u, - /*methodId=*/ 0x20803045u, - /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS), - /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), -#if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "subdeviceCtrlCmdNvlinkCycleLink" -#endif - }, - { /* [474] */ + { /* [491] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7362,7 +7617,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdIsNvlinkReducedConfig" #endif }, - { /* [475] */ + { /* [492] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7377,7 +7632,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [476] */ + { /* [493] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7392,7 +7647,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [477] */ + { /* [494] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7407,7 +7662,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [478] */ + { /* [495] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7422,7 +7677,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [479] */ + { /* [496] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7437,7 +7692,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [480] */ + { /* [497] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7452,7 +7707,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [481] */ + { /* [498] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7467,7 +7722,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [482] */ + { /* [499] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7482,7 +7737,37 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [483] */ + { /* [500] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdEccGetEciCounters_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803401u, + /*paramSize=*/ sizeof(NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdEccGetEciCounters" +#endif + }, + { /* [501] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdEccGetVolatileCounts_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + /*flags=*/ 0x210u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803402u, + /*paramSize=*/ sizeof(NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdEccGetVolatileCounts" +#endif + }, + { /* [502] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7497,7 +7782,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [484] */ + { /* [503] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7512,7 +7797,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [485] */ + { /* [504] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7527,7 +7812,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [486] */ + { /* [505] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7542,13 +7827,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [487] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a11u) + { /* [506] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404a11u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGspGetFeatures_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a11u) - /*flags=*/ 0x4a11u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdGspGetFeatures_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404a11u) + /*flags=*/ 0x404a11u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803601u, /*paramSize=*/ sizeof(NV2080_CTRL_GSP_GET_FEATURES_PARAMS), @@ -7557,7 +7842,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [488] */ + { /* [507] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7572,7 +7857,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetRmHeapStats" #endif }, - { /* [489] */ + { /* [508] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7587,7 +7872,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [490] */ + { /* [509] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7602,7 +7887,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [491] */ + { /* [510] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7617,7 +7902,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [492] */ + { /* [511] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7632,7 +7917,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [493] */ + { /* [512] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7647,7 +7932,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [494] */ + { /* [513] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7662,7 +7947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [495] */ + { /* [514] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7677,7 +7962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" #endif }, - { /* [496] */ + { /* [515] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7692,7 +7977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" #endif }, - { /* [497] */ + { /* [516] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7707,7 +7992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" #endif }, - { /* [498] */ + { /* [517] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7722,7 +8007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" #endif }, - { /* [499] */ + { /* [518] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7737,7 +8022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" #endif }, - { /* [500] */ + { /* [519] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7752,7 +8037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" #endif }, - { /* [501] */ + { /* [520] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7767,7 +8052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" #endif }, - { /* [502] */ + { /* [521] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7782,7 +8067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" #endif }, - { /* [503] */ + { /* [522] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7797,7 +8082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" #endif }, - { /* [504] */ + { /* [523] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7812,7 +8097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" #endif }, - { /* [505] */ + { /* [524] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7827,7 +8112,22 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" #endif }, - { /* [506] */ + { /* [525] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdVgpuMgrInternalFreeStates_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x2080400cu, + /*paramSize=*/ sizeof(NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalFreeStates" +#endif + }, + { /* [526] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7842,7 +8142,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [507] */ + { /* [527] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7857,13 +8157,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlSetEcThrottleMode" #endif }, - { /* [508] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + { /* [528] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x2080a083u, /*paramSize=*/ sizeof(NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM), @@ -7872,7 +8172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples" #endif }, - { /* [509] */ + { /* [529] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7892,7 +8192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 510, + /*numEntries=*/ 530, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -7952,21 +8252,39 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceControlFilter__ = &subdeviceControlFilter_IMPL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdBiosGetInfoV2__ = &subdeviceCtrlCmdBiosGetInfoV2_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBiosGetInfoV2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdBiosGetInfoV2__ = &subdeviceCtrlCmdBiosGetInfoV2_ac1694; + } + else + { + pThis->__subdeviceCtrlCmdBiosGetInfoV2__ = &subdeviceCtrlCmdBiosGetInfoV2_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdBiosGetNbsiV2__ = &subdeviceCtrlCmdBiosGetNbsiV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdBiosGetSKUInfo__ = &subdeviceCtrlCmdBiosGetSKUInfo_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBiosGetSKUInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdBiosGetSKUInfo__ = &subdeviceCtrlCmdBiosGetSKUInfo_VF; + } + else + { + pThis->__subdeviceCtrlCmdBiosGetSKUInfo__ = &subdeviceCtrlCmdBiosGetSKUInfo_92bfc3; + } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdBiosGetPostTime__ = &subdeviceCtrlCmdBiosGetPostTime_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBiosGetPostTime + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdBiosGetPostTime__ = &subdeviceCtrlCmdBiosGetPostTime_VF; + } + else + { + pThis->__subdeviceCtrlCmdBiosGetPostTime__ = &subdeviceCtrlCmdBiosGetPostTime_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdBiosGetUefiSupport__ = &subdeviceCtrlCmdBiosGetUefiSupport_IMPL; @@ -7992,8 +8310,16 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdMcChangeReplayableFaultOwnership__ = &subdeviceCtrlCmdMcChangeReplayableFaultOwnership_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - pThis->__subdeviceCtrlCmdMcServiceInterrupts__ = &subdeviceCtrlCmdMcServiceInterrupts_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + pThis->__subdeviceCtrlCmdMcServiceInterrupts__ = &subdeviceCtrlCmdMcServiceInterrupts_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdMcGetEngineNotificationIntrVectors__ = &subdeviceCtrlCmdMcGetEngineNotificationIntrVectors_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdMcGetStaticIntrTable__ = &subdeviceCtrlCmdMcGetStaticIntrTable_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) @@ -8104,15 +8430,21 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusGetEomStatus__ = &subdeviceCtrlCmdBusGetEomStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) - pThis->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__ = &subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBusGetPcieReqAtomicsCaps + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__ = &subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_VF; + } + else + { + pThis->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__ = &subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x6210u) pThis->__subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics__ = &subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__subdeviceCtrlCmdBusGetC2CInfo__ = &subdeviceCtrlCmdBusGetC2CInfo_IMPL; #endif @@ -8120,13 +8452,25 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBusSysmemAccess__ = &subdeviceCtrlCmdBusSysmemAccess_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) - pThis->__subdeviceCtrlCmdBusSetP2pMapping__ = &subdeviceCtrlCmdBusSetP2pMapping_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBusSetP2pMapping + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdBusSetP2pMapping__ = &subdeviceCtrlCmdBusSetP2pMapping_VGPUSTUB; + } + else + { + pThis->__subdeviceCtrlCmdBusSetP2pMapping__ = &subdeviceCtrlCmdBusSetP2pMapping_5baef9; + } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100200u) - pThis->__subdeviceCtrlCmdBusUnsetP2pMapping__ = &subdeviceCtrlCmdBusUnsetP2pMapping_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBusUnsetP2pMapping + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdBusUnsetP2pMapping__ = &subdeviceCtrlCmdBusUnsetP2pMapping_VGPUSTUB; + } + else + { + pThis->__subdeviceCtrlCmdBusUnsetP2pMapping__ = &subdeviceCtrlCmdBusUnsetP2pMapping_5baef9; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGetNvlinkCounters__ = &subdeviceCtrlCmdGetNvlinkCounters_IMPL; @@ -8136,7 +8480,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdClearNvlinkCounters__ = &subdeviceCtrlCmdClearNvlinkCounters_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) pThis->__subdeviceCtrlCmdBusGetNvlinkCaps__ = &subdeviceCtrlCmdBusGetNvlinkCaps_IMPL; #endif @@ -8352,10 +8696,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkGetPortEvents__ = &subdeviceCtrlCmdNvlinkGetPortEvents_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - pThis->__subdeviceCtrlCmdNvlinkCycleLink__ = &subdeviceCtrlCmdNvlinkCycleLink_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdI2cReadBuffer__ = &subdeviceCtrlCmdI2cReadBuffer_IMPL; #endif @@ -8372,13 +8712,25 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdI2cWriteReg__ = &subdeviceCtrlCmdI2cWriteReg_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples__ = &subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples__ = &subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_VF; + } + else + { + pThis->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples__ = &subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_5baef9; + } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2__ = &subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2__ = &subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_VF; + } + else + { + pThis->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2__ = &subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_5baef9; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x212u) pThis->__subdeviceCtrlCmdPerfRatedTdpGetControl__ = &subdeviceCtrlCmdPerfRatedTdpGetControl_IMPL; @@ -8388,7 +8740,14 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdPerfRatedTdpSetControl__ = &subdeviceCtrlCmdPerfRatedTdpSetControl_KERNEL; // Hal function -- subdeviceCtrlCmdPerfReservePerfmonHw - pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL; + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_46f6a7; + } + else + { + pThis->__subdeviceCtrlCmdPerfReservePerfmonHw__ = &subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL; + } // Hal function -- subdeviceCtrlCmdPerfSetAuxPowerState pThis->__subdeviceCtrlCmdPerfSetAuxPowerState__ = &subdeviceCtrlCmdPerfSetAuxPowerState_KERNEL; @@ -8396,7 +8755,57 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * // Hal function -- subdeviceCtrlCmdPerfSetPowerstate pThis->__subdeviceCtrlCmdPerfSetPowerstate__ = &subdeviceCtrlCmdPerfSetPowerstate_KERNEL; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) + // Hal function -- subdeviceCtrlCmdPerfGetLevelInfo_V2 + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdPerfGetLevelInfo_V2__ = &subdeviceCtrlCmdPerfGetLevelInfo_V2_VF; + } + else + { + pThis->__subdeviceCtrlCmdPerfGetLevelInfo_V2__ = &subdeviceCtrlCmdPerfGetLevelInfo_V2_92bfc3; + } + + // Hal function -- subdeviceCtrlCmdPerfGetCurrentPstate + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdPerfGetCurrentPstate__ = &subdeviceCtrlCmdPerfGetCurrentPstate_VF; + } + else + { + pThis->__subdeviceCtrlCmdPerfGetCurrentPstate__ = &subdeviceCtrlCmdPerfGetCurrentPstate_92bfc3; + } + + // Hal function -- subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample__ = &subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_VF; + } + else + { + pThis->__subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample__ = &subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_92bfc3; + } + + // Hal function -- subdeviceCtrlCmdPerfGetPowerstate + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdPerfGetPowerstate__ = &subdeviceCtrlCmdPerfGetPowerstate_VF; + } + else + { + pThis->__subdeviceCtrlCmdPerfGetPowerstate__ = &subdeviceCtrlCmdPerfGetPowerstate_92bfc3; + } + + // Hal function -- subdeviceCtrlCmdPerfNotifyVideoevent + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdPerfNotifyVideoevent__ = &subdeviceCtrlCmdPerfNotifyVideoevent_ac1694; + } + else + { + pThis->__subdeviceCtrlCmdPerfNotifyVideoevent__ = &subdeviceCtrlCmdPerfNotifyVideoevent_92bfc3; + } + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) pThis->__subdeviceCtrlCmdKPerfBoost__ = &subdeviceCtrlCmdKPerfBoost_IMPL; #endif @@ -8431,10 +8840,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * // Hal function -- subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp pThis->__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__ = &subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_46f6a7; -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) - pThis->__subdeviceCtrlCmdFbGetInfo__ = &subdeviceCtrlCmdFbGetInfo_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdFbGetInfoV2__ = &subdeviceCtrlCmdFbGetInfoV2_IMPL; #endif @@ -8467,7 +8872,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2__ = &subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa10u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400a10u) pThis->__subdeviceCtrlCmdFbGetGpuCacheInfo__ = &subdeviceCtrlCmdFbGetGpuCacheInfo_IMPL; #endif @@ -8483,7 +8888,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFbSetupVprRegion__ = &subdeviceCtrlCmdFbSetupVprRegion_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2a50u) pThis->__subdeviceCtrlCmdFbGetLTCInfoForFBP__ = &subdeviceCtrlCmdFbGetLTCInfoForFBP_IMPL; #endif @@ -8499,7 +8904,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFbGetRemappedRows__ = &subdeviceCtrlCmdFbGetRemappedRows_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__subdeviceCtrlCmdFbGetFsInfo__ = &subdeviceCtrlCmdFbGetFsInfo_IMPL; #endif @@ -8519,9 +8924,15 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFbGetNumaInfo__ = &subdeviceCtrlCmdFbGetNumaInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdMemSysGetStaticConfig__ = &subdeviceCtrlCmdMemSysGetStaticConfig_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdMemSysGetStaticConfig + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdMemSysGetStaticConfig__ = &subdeviceCtrlCmdMemSysGetStaticConfig_VGPUSTUB; + } + else + { + pThis->__subdeviceCtrlCmdMemSysGetStaticConfig__ = &subdeviceCtrlCmdMemSysGetStaticConfig_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdMemSysSetPartitionableMem__ = &subdeviceCtrlCmdMemSysSetPartitionableMem_IMPL; @@ -8599,6 +9010,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFifoDisableChannels__ = &subdeviceCtrlCmdFifoDisableChannels_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__subdeviceCtrlCmdFifoDisableChannelsForKeyRotation__ = &subdeviceCtrlCmdFifoDisableChannelsForKeyRotation_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) pThis->__subdeviceCtrlCmdFifoDisableUsermodeChannels__ = &subdeviceCtrlCmdFifoDisableUsermodeChannels_IMPL; #endif @@ -8611,6 +9026,28 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFifoGetUserdLocation__ = &subdeviceCtrlCmdFifoGetUserdLocation_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdFifoObjschedSwGetLog__ = &subdeviceCtrlCmdFifoObjschedSwGetLog_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdFifoObjschedGetState__ = &subdeviceCtrlCmdFifoObjschedGetState_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdFifoObjschedSetState__ = &subdeviceCtrlCmdFifoObjschedSetState_IMPL; +#endif + + // Hal function -- subdeviceCtrlCmdFifoObjschedGetCaps + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdFifoObjschedGetCaps__ = &subdeviceCtrlCmdFifoObjschedGetCaps_ac1694; + } + else + { + pThis->__subdeviceCtrlCmdFifoObjschedGetCaps__ = &subdeviceCtrlCmdFifoObjschedGetCaps_5baef9; + } + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c2200u) pThis->__subdeviceCtrlCmdFifoGetDeviceInfoTable__ = &subdeviceCtrlCmdFifoGetDeviceInfoTable_IMPL; #endif @@ -8667,7 +9104,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrCtxswZcullMode__ = &subdeviceCtrlCmdKGrCtxswZcullMode_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x802a10u) pThis->__subdeviceCtrlCmdKGrCtxswZcullBind__ = &subdeviceCtrlCmdKGrCtxswZcullBind_IMPL; #endif @@ -8683,6 +9120,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdKGrCtxswPmBind__ = &subdeviceCtrlCmdKGrCtxswPmBind_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) + pThis->__subdeviceCtrlCmdKGrCtxswSetupBind__ = &subdeviceCtrlCmdKGrCtxswSetupBind_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__subdeviceCtrlCmdKGrSetGpcTileMap__ = &subdeviceCtrlCmdKGrSetGpcTileMap_IMPL; #endif @@ -8882,12 +9323,21 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdGpuSetOptimusInfo__ = &subdeviceCtrlCmdGpuSetOptimusInfo_IMPL; #endif +} + +static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200a12u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200812u) pThis->__subdeviceCtrlCmdGpuGetNameString__ = &subdeviceCtrlCmdGpuGetNameString_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a12u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4812u) pThis->__subdeviceCtrlCmdGpuGetShortNameString__ = &subdeviceCtrlCmdGpuGetShortNameString_IMPL; #endif @@ -8903,7 +9353,7 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetNvencSwSessionInfo__ = &subdeviceCtrlCmdGpuGetNvencSwSessionInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) pThis->__subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2__ = &subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_IMPL; #endif @@ -8990,25 +9440,22 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuGetInforomObjectVersion__ = &subdeviceCtrlCmdGpuGetInforomObjectVersion_IMPL; #endif -} - -static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuQueryInforomEccSupport__ = &subdeviceCtrlCmdGpuQueryInforomEccSupport_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) - pThis->__subdeviceCtrlCmdGpuQueryEccStatus__ = &subdeviceCtrlCmdGpuQueryEccStatus_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdGpuQueryEccStatus + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdGpuQueryEccStatus__ = &subdeviceCtrlCmdGpuQueryEccStatus_VF; + } + else + { + pThis->__subdeviceCtrlCmdGpuQueryEccStatus__ = &subdeviceCtrlCmdGpuQueryEccStatus_92bfc3; + } -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404210u) pThis->__subdeviceCtrlCmdGpuGetChipDetails__ = &subdeviceCtrlCmdGpuGetChipDetails_IMPL; #endif @@ -9056,13 +9503,19 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetId__ = &subdeviceCtrlCmdGpuGetId_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) pThis->__subdeviceCtrlCmdGpuGetGidInfo__ = &subdeviceCtrlCmdGpuGetGidInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdGpuQueryIllumSupport__ = &subdeviceCtrlCmdGpuQueryIllumSupport_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdGpuQueryIllumSupport + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdGpuQueryIllumSupport__ = &subdeviceCtrlCmdGpuQueryIllumSupport_VF; + } + else + { + pThis->__subdeviceCtrlCmdGpuQueryIllumSupport__ = &subdeviceCtrlCmdGpuQueryIllumSupport_5baef9; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuGetIllum__ = &subdeviceCtrlCmdGpuGetIllum_IMPL; @@ -9072,9 +9525,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuSetIllum__ = &subdeviceCtrlCmdGpuSetIllum_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdGpuQueryScrubberStatus__ = &subdeviceCtrlCmdGpuQueryScrubberStatus_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdGpuQueryScrubberStatus + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdGpuQueryScrubberStatus__ = &subdeviceCtrlCmdGpuQueryScrubberStatus_VF; + } + else + { + pThis->__subdeviceCtrlCmdGpuQueryScrubberStatus__ = &subdeviceCtrlCmdGpuQueryScrubberStatus_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGpuGetVprCaps__ = &subdeviceCtrlCmdGpuGetVprCaps_IMPL; @@ -9096,7 +9555,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuQueryFunctionStatus__ = &subdeviceCtrlCmdGpuQueryFunctionStatus_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400200u) pThis->__subdeviceCtrlCmdGpuReportNonReplayableFault__ = &subdeviceCtrlCmdGpuReportNonReplayableFault_IMPL; #endif @@ -9148,7 +9607,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetEngineLoadTimes__ = &subdeviceCtrlCmdGpuGetEngineLoadTimes_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) pThis->__subdeviceCtrlCmdGetP2pCaps__ = &subdeviceCtrlCmdGetP2pCaps_IMPL; #endif @@ -9164,6 +9623,14 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetDrainAndResetStatus__ = &subdeviceCtrlCmdGpuGetDrainAndResetStatus_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdGpuGetConstructedFalconInfo__ = &subdeviceCtrlCmdGpuGetConstructedFalconInfo_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) + pThis->__subdeviceCtrlGpuGetFipsStatus__ = &subdeviceCtrlGpuGetFipsStatus_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdEventSetTrigger__ = &subdeviceCtrlCmdEventSetTrigger_IMPL; #endif @@ -9192,6 +9659,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdEventVideoBindEvtbuf__ = &subdeviceCtrlCmdEventVideoBindEvtbuf_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf__ = &subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdTimerCancel__ = &subdeviceCtrlCmdTimerCancel_IMPL; #endif @@ -9288,6 +9759,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvdSetNocatJournalData__ = &subdeviceCtrlCmdNvdSetNocatJournalData_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) + pThis->__subdeviceCtrlCmdNvdInsertNocatJournalRecord__ = &subdeviceCtrlCmdNvdInsertNocatJournalRecord_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) pThis->__subdeviceCtrlCmdPmgrGetModuleInfo__ = &subdeviceCtrlCmdPmgrGetModuleInfo_IMPL; #endif @@ -9373,16 +9848,42 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__subdeviceCtrlCmdGpuQueryEccConfiguration__ = &subdeviceCtrlCmdGpuQueryEccConfiguration_IMPL; + pThis->__subdeviceCtrlCmdEccGetEciCounters__ = &subdeviceCtrlCmdEccGetEciCounters_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - pThis->__subdeviceCtrlCmdGpuSetEccConfiguration__ = &subdeviceCtrlCmdGpuSetEccConfiguration_IMPL; +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) + pThis->__subdeviceCtrlCmdEccGetVolatileCounts__ = &subdeviceCtrlCmdEccGetVolatileCounts_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) - pThis->__subdeviceCtrlCmdGpuResetEccErrorStatus__ = &subdeviceCtrlCmdGpuResetEccErrorStatus_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdGpuQueryEccConfiguration + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdGpuQueryEccConfiguration__ = &subdeviceCtrlCmdGpuQueryEccConfiguration_VF; + } + else + { + pThis->__subdeviceCtrlCmdGpuQueryEccConfiguration__ = &subdeviceCtrlCmdGpuQueryEccConfiguration_92bfc3; + } + + // Hal function -- subdeviceCtrlCmdGpuSetEccConfiguration + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdGpuSetEccConfiguration__ = &subdeviceCtrlCmdGpuSetEccConfiguration_VF; + } + else + { + pThis->__subdeviceCtrlCmdGpuSetEccConfiguration__ = &subdeviceCtrlCmdGpuSetEccConfiguration_92bfc3; + } + + // Hal function -- subdeviceCtrlCmdGpuResetEccErrorStatus + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdGpuResetEccErrorStatus__ = &subdeviceCtrlCmdGpuResetEccErrorStatus_VF; + } + else + { + pThis->__subdeviceCtrlCmdGpuResetEccErrorStatus__ = &subdeviceCtrlCmdGpuResetEccErrorStatus_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__subdeviceCtrlCmdFlaRange__ = &subdeviceCtrlCmdFlaRange_IMPL; @@ -9400,9 +9901,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFlaGetFabricMemStats__ = &subdeviceCtrlCmdFlaGetFabricMemStats_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4a11u) - pThis->__subdeviceCtrlCmdGspGetFeatures__ = &subdeviceCtrlCmdGspGetFeatures_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdGspGetFeatures + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdGspGetFeatures__ = &subdeviceCtrlCmdGspGetFeatures_KERNEL; + } + else + { + pThis->__subdeviceCtrlCmdGspGetFeatures__ = &subdeviceCtrlCmdGspGetFeatures_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdGspGetRmHeapStats__ = &subdeviceCtrlCmdGspGetRmHeapStats_IMPL; @@ -9412,7 +9919,7 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdGpuGetActivePartitionIds__ = &subdeviceCtrlCmdGpuGetActivePartitionIds_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) pThis->__subdeviceCtrlCmdGpuGetPartitionCapacity__ = &subdeviceCtrlCmdGpuGetPartitionCapacity_IMPL; #endif @@ -9464,6 +9971,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__ = &subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2600u) + pThis->__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__ = &subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) pThis->__subdeviceCtrlCmdOsUnixGc6BlockerRefCnt__ = &subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL; #endif @@ -9549,26 +10060,26 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdDisplayUnixConsole__ = &subdeviceCtrlCmdDisplayUnixConsole_IMPL; + pThis->__subdeviceCtrlCmdDisplayPreUnixConsole__ = &subdeviceCtrlCmdDisplayPreUnixConsole_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdDisplayPostVgaRestore__ = &subdeviceCtrlCmdDisplayPostVgaRestore_IMPL; + pThis->__subdeviceCtrlCmdDisplayPostUnixConsole__ = &subdeviceCtrlCmdDisplayPostUnixConsole_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) pThis->__subdeviceCtrlCmdMsencGetCaps__ = &subdeviceCtrlCmdMsencGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) pThis->__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) pThis->__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__ = &subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x404600u) pThis->__subdeviceCtrlCmdInternalGetChipInfo__ = &subdeviceCtrlCmdInternalGetChipInfo_IMPL; #endif @@ -9576,20 +10087,20 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalGetUserRegisterAccessMap__ = &subdeviceCtrlCmdInternalGetUserRegisterAccessMap_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1c4600u) pThis->__subdeviceCtrlCmdInternalGetDeviceInfoTable__ = &subdeviceCtrlCmdInternalGetDeviceInfoTable_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalGetConstructedFalconInfo__ = &subdeviceCtrlCmdInternalGetConstructedFalconInfo_IMPL; + pThis->__subdeviceCtrlCmdInternalRecoverAllComputeContexts__ = &subdeviceCtrlCmdInternalRecoverAllComputeContexts_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalRecoverAllComputeContexts__ = &subdeviceCtrlCmdInternalRecoverAllComputeContexts_IMPL; + pThis->__subdeviceCtrlCmdInternalGetSmcMode__ = &subdeviceCtrlCmdInternalGetSmcMode_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalGetSmcMode__ = &subdeviceCtrlCmdInternalGetSmcMode_IMPL; + pThis->__subdeviceCtrlCmdIsEgpuBridge__ = &subdeviceCtrlCmdIsEgpuBridge_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) @@ -9620,15 +10131,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries__ = &subdeviceCtrlCmdInternalVmmuGetSpaForGpaEntries_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) pThis->__subdeviceCtrlCmdGmmuGetStaticInfo__ = &subdeviceCtrlCmdGmmuGetStaticInfo_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) pThis->__subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer__ = &subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400600u) pThis->__subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer__ = &subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer_IMPL; #endif @@ -9720,9 +10231,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalGcxEntryPrerequisite__ = &subdeviceCtrlCmdInternalGcxEntryPrerequisite_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdBifGetStaticInfo__ = &subdeviceCtrlCmdBifGetStaticInfo_IMPL; -#endif + // Hal function -- subdeviceCtrlCmdBifGetStaticInfo + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__subdeviceCtrlCmdBifGetStaticInfo__ = &subdeviceCtrlCmdBifGetStaticInfo_VGPUSTUB; + } + else + { + pThis->__subdeviceCtrlCmdBifGetStaticInfo__ = &subdeviceCtrlCmdBifGetStaticInfo_92bfc3; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) pThis->__subdeviceCtrlCmdBifGetAspmL1Flags__ = &subdeviceCtrlCmdBifGetAspmL1Flags_IMPL; @@ -9887,6 +10404,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateInfo_IMPL; #endif +} + +static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { + RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; + const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; + PORT_UNREFERENCED_VARIABLE(pThis); + PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); + PORT_UNREFERENCED_VARIABLE(rmVariantHal); + PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping__ = &subdeviceCtrlCmdInternalPerfPfmReqHndlrGetVpstateMapping_IMPL; @@ -9909,15 +10435,15 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalConfComputeEncryptionControl__ = &subdeviceCtrlCmdInternalConfComputeEncryptionControl_IMPL; + pThis->__subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys__ = &subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys__ = &subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_IMPL; + pThis->__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__ = &subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) - pThis->__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__ = &subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_IMPL; + pThis->__subdeviceCtrlCmdInternalConfComputeSetGpuState__ = &subdeviceCtrlCmdInternalConfComputeSetGpuState_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) @@ -9928,6 +10454,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdInternalUserSharedDataSetDataPoll__ = &subdeviceCtrlCmdInternalUserSharedDataSetDataPoll_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x640u) + pThis->__subdeviceCtrlCmdInternalGspStartTrace__ = &subdeviceCtrlCmdInternalGspStartTrace_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__ = &subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL; #endif @@ -9972,6 +10502,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig__ = &subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdVgpuMgrInternalFreeStates__ = &subdeviceCtrlCmdVgpuMgrInternalFreeStates_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) pThis->__subdeviceCtrlCmdGetAvailableHshubMask__ = &subdeviceCtrlCmdGetAvailableHshubMask_IMPL; #endif @@ -10025,17 +10559,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceUnmapFrom__ = &__nvoc_thunk_RsResource_subdeviceUnmapFrom; pThis->__subdeviceControl_Epilogue__ = &__nvoc_thunk_RmResource_subdeviceControl_Epilogue; -} - -static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { - RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal; - const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx; - PORT_UNREFERENCED_VARIABLE(pThis); - PORT_UNREFERENCED_VARIABLE(pRmhalspecowner); - PORT_UNREFERENCED_VARIABLE(rmVariantHal); - PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); - - pThis->__subdeviceControlLookup__ = &__nvoc_thunk_RsResource_subdeviceControlLookup; pThis->__subdeviceGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_subdeviceGetInternalObjectHandle; @@ -10053,6 +10576,8 @@ static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCanCopy__ = &__nvoc_thunk_RsResource_subdeviceCanCopy; + pThis->__subdeviceIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_subdeviceIsPartialUnmapSupported; + pThis->__subdeviceIsDuplicate__ = &__nvoc_thunk_RsResource_subdeviceIsDuplicate; pThis->__subdeviceControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_subdeviceControlSerialization_Epilogue; @@ -10088,23 +10613,31 @@ void __nvoc_init_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_Subdevice(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_Subdevice(Subdevice **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_Subdevice(Subdevice **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; Subdevice *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(Subdevice), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(Subdevice)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_Subdevice); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -10122,16 +10655,25 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice **ppThis, Dynamic *pParent, NvU32 status = __nvoc_ctor_Subdevice(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_Subdevice_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_Subdevice_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(Subdevice)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 3486a21a0f..27fdf8f8b9 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -99,11 +99,16 @@ typedef struct P2PApi P2PApi; * unicast semantics; that is, operations involving a subdevice are applied to * the associated GPU only. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SUBDEVICE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct Subdevice { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -130,6 +135,8 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdMcSetHostclkSlowdownStatus__)(struct Subdevice *, NV2080_CTRL_MC_SET_HOSTCLK_SLOWDOWN_STATUS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdMcChangeReplayableFaultOwnership__)(struct Subdevice *, NV2080_CTRL_MC_CHANGE_REPLAYABLE_FAULT_OWNERSHIP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdMcServiceInterrupts__)(struct Subdevice *, NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdMcGetEngineNotificationIntrVectors__)(struct Subdevice *, NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdMcGetStaticIntrTable__)(struct Subdevice *, NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdDmaInvalidateTLB__)(struct Subdevice *, NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdDmaGetInfo__)(struct Subdevice *, NV2080_CTRL_DMA_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBusGetPciInfo__)(struct Subdevice *, NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS *); @@ -219,7 +226,6 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkGetL1Threshold__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_L1_THRESHOLD_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdIsNvlinkReducedConfig__)(struct Subdevice *, NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkGetPortEvents__)(struct Subdevice *, NV2080_CTRL_NVLINK_GET_PORT_EVENTS_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdNvlinkCycleLink__)(struct Subdevice *, NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cWriteBuffer__)(struct Subdevice *, NV2080_CTRL_I2C_WRITE_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdI2cReadReg__)(struct Subdevice *, NV2080_CTRL_I2C_RW_REG_PARAMS *); @@ -231,6 +237,11 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdPerfReservePerfmonHw__)(struct Subdevice *, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdPerfSetAuxPowerState__)(struct Subdevice *, NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdPerfSetPowerstate__)(struct Subdevice *, NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdPerfGetLevelInfo_V2__)(struct Subdevice *, NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdPerfGetCurrentPstate__)(struct Subdevice *, NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample__)(struct Subdevice *, NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdPerfGetPowerstate__)(struct Subdevice *, NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdPerfNotifyVideoevent__)(struct Subdevice *, NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKPerfBoost__)(struct Subdevice *, NV2080_CTRL_PERF_BOOST_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetFBRegionInfo__)(struct Subdevice *, NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetBar1Offset__)(struct Subdevice *, NV2080_CTRL_FB_GET_BAR1_OFFSET_PARAMS *); @@ -240,7 +251,6 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalMemmgrGetVgpuHostRmReservedFb__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMMGR_GET_VGPU_CONFIG_HOST_RESERVED_FB_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout__)(struct Subdevice *, NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdFbGetInfo__)(struct Subdevice *, NV2080_CTRL_FB_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetInfoV2__)(struct Subdevice *, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFbGetCarveoutAddressInfo__)(struct Subdevice *, NV2080_CTRL_FB_GET_SYSTEM_CARVEOUT_ADDRESS_SPACE_INFO *); NV_STATUS (*__subdeviceCtrlCmdFbGetCalibrationLockFailed__)(struct Subdevice *, NV2080_CTRL_FB_GET_CALIBRATION_LOCK_FAILED_PARAMS *); @@ -282,9 +292,14 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGetPhysicalChannelCount__)(struct Subdevice *, NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoGetInfo__)(struct Subdevice *, NV2080_CTRL_FIFO_GET_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoDisableChannels__)(struct Subdevice *, NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdFifoDisableChannelsForKeyRotation__)(struct Subdevice *, NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoDisableUsermodeChannels__)(struct Subdevice *, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoGetChannelMemInfo__)(struct Subdevice *, NV2080_CTRL_CMD_FIFO_GET_CHANNEL_MEM_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoGetUserdLocation__)(struct Subdevice *, NV2080_CTRL_CMD_FIFO_GET_USERD_LOCATION_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdFifoObjschedSwGetLog__)(struct Subdevice *, NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdFifoObjschedGetState__)(struct Subdevice *, NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdFifoObjschedSetState__)(struct Subdevice *, NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdFifoObjschedGetCaps__)(struct Subdevice *, NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoGetDeviceInfoTable__)(struct Subdevice *, NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb__)(struct Subdevice *, NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFifoClearFaultedBit__)(struct Subdevice *, NV2080_CTRL_CMD_FIFO_CLEAR_FAULTED_BIT_PARAMS *); @@ -303,6 +318,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdKGrGetZcullInfo__)(struct Subdevice *, NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrCtxswPmMode__)(struct Subdevice *, NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrCtxswPmBind__)(struct Subdevice *, NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdKGrCtxswSetupBind__)(struct Subdevice *, NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrSetGpcTileMap__)(struct Subdevice *, NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrCtxswSmpcMode__)(struct Subdevice *, NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdKGrPcSamplingMode__)(struct Subdevice *, NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *); @@ -421,6 +437,8 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdGetGpuFabricProbeInfo__)(struct Subdevice *, NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetResetStatus__)(struct Subdevice *, NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuGetDrainAndResetStatus__)(struct Subdevice *, NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdGpuGetConstructedFalconInfo__)(struct Subdevice *, NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *); + NV_STATUS (*__subdeviceCtrlGpuGetFipsStatus__)(struct Subdevice *, NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetTrigger__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdEventSetTriggerFifo__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_TRIGGER_FIFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetNotification__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS *); @@ -428,6 +446,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdEventSetSemaphoreMemory__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventSetSemaMemValidation__)(struct Subdevice *, NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEventVideoBindEvtbuf__)(struct Subdevice *, NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf__)(struct Subdevice *, NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdTimerCancel__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdTimerSchedule__)(struct Subdevice *, NV2080_CTRL_CMD_TIMER_SCHEDULE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdTimerGetTime__)(struct Subdevice *, NV2080_CTRL_TIMER_GET_TIME_PARAMS *); @@ -452,6 +471,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvdGetDump__)(struct Subdevice *, NV2080_CTRL_NVD_GET_DUMP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvdGetNocatJournalRpt__)(struct Subdevice *, NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvdSetNocatJournalData__)(struct Subdevice *, NV2080_CTRL_NVD_SET_NOCAT_JOURNAL_DATA_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvdInsertNocatJournalRecord__)(struct Subdevice *, NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdPmgrGetModuleInfo__)(struct Subdevice *, NV2080_CTRL_PMGR_MODULE_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuProcessPostGc6ExitTasks__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdGc6Entry__)(struct Subdevice *, NV2080_CTRL_GC6_ENTRY_PARAMS *); @@ -473,6 +493,8 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_FLAGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalFlcnSetVideoEventBufferMemory__)(struct Subdevice *, NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdEccGetClientExposedCounters__)(struct Subdevice *, NV2080_CTRL_ECC_GET_CLIENT_EXPOSED_COUNTERS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdEccGetEciCounters__)(struct Subdevice *, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdEccGetVolatileCounts__)(struct Subdevice *, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuQueryEccConfiguration__)(struct Subdevice *, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuSetEccConfiguration__)(struct Subdevice *, NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGpuResetEccErrorStatus__)(struct Subdevice *, NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS *); @@ -496,6 +518,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles__)(struct Subdevice *, NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__)(struct Subdevice *, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixGc6BlockerRefCnt__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixAllowDisallowGcoff__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_ALLOW_DISALLOW_GCOFF_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdOsUnixAudioDynamicPower__)(struct Subdevice *, NV2080_CTRL_OS_UNIX_AUDIO_DYNAMIC_POWER_PARAMS *); @@ -517,17 +540,17 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalDisplayPreModeSet__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalDisplayPostModeSet__)(struct Subdevice *); - NV_STATUS (*__subdeviceCtrlCmdDisplayUnixConsole__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdDisplayPostVgaRestore__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdDisplayPreUnixConsole__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdDisplayPostUnixConsole__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdMsencGetCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_REGISTER_ACCESS_CNTR_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer__)(struct Subdevice *, NV2080_CTRL_INTERNAL_UVM_UNREGISTER_ACCESS_CNTR_BUFFER_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetChipInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetUserRegisterAccessMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPU_GET_USER_REGISTER_ACCESS_MAP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalGetDeviceInfoTable__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalGetConstructedFalconInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalRecoverAllComputeContexts__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalGetSmcMode__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdIsEgpuBridge__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalBusFlushWithSysmembar__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_LOCAL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_BUS_SETUP_P2P_MAILBOX_REMOTE_PARAMS *); @@ -607,11 +630,12 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalDetectHsVideoBridge__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeEncryptionControl__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_LCE_KEYS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalConfComputeSetGpuState__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalInitUserSharedData__)(struct Subdevice *, NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdInternalUserSharedDataSetDataPoll__)(struct Subdevice *, NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdInternalGspStartTrace__)(struct Subdevice *, NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *); @@ -623,6 +647,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MGR_CONFIG_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdVgpuMgrInternalFreeStates__)(struct Subdevice *, NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdGetAvailableHshubMask__)(struct Subdevice *, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *); NV_STATUS (*__subdeviceCtrlSetEcThrottleMode__)(struct Subdevice *, NV2080_CTRL_CMD_HSHUB_SET_EC_THROTTLE_MODE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCcuMap__)(struct Subdevice *, NV2080_CTRL_INTERNAL_CCU_MAP_INFO_PARAMS *); @@ -641,7 +666,6 @@ struct Subdevice { NV_STATUS (*__subdeviceGetRegBaseOffsetAndSize__)(struct Subdevice *, struct OBJGPU *, NvU32 *, NvU32 *); NV_STATUS (*__subdeviceUnmapFrom__)(struct Subdevice *, RS_RES_UNMAP_FROM_PARAMS *); void (*__subdeviceControl_Epilogue__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__subdeviceControlLookup__)(struct Subdevice *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__subdeviceGetInternalObjectHandle__)(struct Subdevice *); NV_STATUS (*__subdeviceControl__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__subdeviceUnmap__)(struct Subdevice *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -650,6 +674,7 @@ struct Subdevice { NV_STATUS (*__subdeviceUnregisterEvent__)(struct Subdevice *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__subdeviceControlSerialization_Prologue__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__subdeviceCanCopy__)(struct Subdevice *); + NvBool (*__subdeviceIsPartialUnmapSupported__)(struct Subdevice *); NV_STATUS (*__subdeviceIsDuplicate__)(struct Subdevice *, NvHandle, NvBool *); void (*__subdeviceControlSerialization_Epilogue__)(struct Subdevice *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); PEVENTNOTIFICATION *(*__subdeviceGetNotificationListPtr__)(struct Subdevice *); @@ -661,7 +686,7 @@ struct Subdevice { struct Device *pDevice; NvBool bMaxGrTickFreqRequested; NvU64 P2PfbMappedBytes; - NvU32 notifyActions[183]; + NvU32 notifyActions[187]; NvHandle hNotifierMemory; struct Memory *pNotifierMemory; NvHandle hSemMemory; @@ -684,6 +709,7 @@ struct Subdevice { NvBool bSchedPolicySet; NvBool bGcoffDisallowed; NvBool bUpdateTGP; + NvBool bVFRefCntIncRequested; }; #ifndef __NVOC_CLASS_Subdevice_TYPEDEF__ @@ -718,9 +744,12 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceInternalControlForward(pSubdevice, command, pParams, size) subdeviceInternalControlForward_DISPATCH(pSubdevice, command, pParams, size) #define subdeviceControlFilter(pSubdevice, pCallContext, pParams) subdeviceControlFilter_DISPATCH(pSubdevice, pCallContext, pParams) #define subdeviceCtrlCmdBiosGetInfoV2(pSubdevice, pBiosInfoParams) subdeviceCtrlCmdBiosGetInfoV2_DISPATCH(pSubdevice, pBiosInfoParams) +#define subdeviceCtrlCmdBiosGetInfoV2_HAL(pSubdevice, pBiosInfoParams) subdeviceCtrlCmdBiosGetInfoV2_DISPATCH(pSubdevice, pBiosInfoParams) #define subdeviceCtrlCmdBiosGetNbsiV2(pSubdevice, pNbsiParams) subdeviceCtrlCmdBiosGetNbsiV2_DISPATCH(pSubdevice, pNbsiParams) #define subdeviceCtrlCmdBiosGetSKUInfo(pSubdevice, pBiosGetSKUInfoParams) subdeviceCtrlCmdBiosGetSKUInfo_DISPATCH(pSubdevice, pBiosGetSKUInfoParams) +#define subdeviceCtrlCmdBiosGetSKUInfo_HAL(pSubdevice, pBiosGetSKUInfoParams) subdeviceCtrlCmdBiosGetSKUInfo_DISPATCH(pSubdevice, pBiosGetSKUInfoParams) #define subdeviceCtrlCmdBiosGetPostTime(pSubdevice, pBiosPostTime) subdeviceCtrlCmdBiosGetPostTime_DISPATCH(pSubdevice, pBiosPostTime) +#define subdeviceCtrlCmdBiosGetPostTime_HAL(pSubdevice, pBiosPostTime) subdeviceCtrlCmdBiosGetPostTime_DISPATCH(pSubdevice, pBiosPostTime) #define subdeviceCtrlCmdBiosGetUefiSupport(pSubdevice, pUEFIParams) subdeviceCtrlCmdBiosGetUefiSupport_DISPATCH(pSubdevice, pUEFIParams) #define subdeviceCtrlCmdMcGetArchInfo(pSubdevice, pArchInfoParams) subdeviceCtrlCmdMcGetArchInfo_DISPATCH(pSubdevice, pArchInfoParams) #define subdeviceCtrlCmdMcGetManufacturer(pSubdevice, pManufacturerParams) subdeviceCtrlCmdMcGetManufacturer_DISPATCH(pSubdevice, pManufacturerParams) @@ -728,6 +757,8 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdMcSetHostclkSlowdownStatus(pSubdevice, pParams) subdeviceCtrlCmdMcSetHostclkSlowdownStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdMcChangeReplayableFaultOwnership(pSubdevice, pReplayableFaultOwnrshpParams) subdeviceCtrlCmdMcChangeReplayableFaultOwnership_DISPATCH(pSubdevice, pReplayableFaultOwnrshpParams) #define subdeviceCtrlCmdMcServiceInterrupts(pSubdevice, pServiceInterruptParams) subdeviceCtrlCmdMcServiceInterrupts_DISPATCH(pSubdevice, pServiceInterruptParams) +#define subdeviceCtrlCmdMcGetEngineNotificationIntrVectors(pSubdevice, pParams) subdeviceCtrlCmdMcGetEngineNotificationIntrVectors_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdMcGetStaticIntrTable(pSubdevice, pParams) subdeviceCtrlCmdMcGetStaticIntrTable_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdDmaInvalidateTLB(pSubdevice, pParams) subdeviceCtrlCmdDmaInvalidateTLB_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdDmaGetInfo(pSubdevice, pDmaInfoParams) subdeviceCtrlCmdDmaGetInfo_DISPATCH(pSubdevice, pDmaInfoParams) #define subdeviceCtrlCmdBusGetPciInfo(pSubdevice, pPciInfoParams) subdeviceCtrlCmdBusGetPciInfo_DISPATCH(pSubdevice, pPciInfoParams) @@ -756,11 +787,14 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdBusGetUphyDlnCfgSpace(pSubdevice, pParams) subdeviceCtrlCmdBusGetUphyDlnCfgSpace_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetEomStatus(pSubdevice, pParams) subdeviceCtrlCmdBusGetEomStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetPcieReqAtomicsCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_HAL(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics(pSubdevice, pParams) subdeviceCtrlCmdBusGetPcieSupportedGpuAtomics_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetC2CInfo(pSubdevice, pParams) subdeviceCtrlCmdBusGetC2CInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusSysmemAccess(pSubdevice, pParams) subdeviceCtrlCmdBusSysmemAccess_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusSetP2pMapping(pSubdevice, pParams) subdeviceCtrlCmdBusSetP2pMapping_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusSetP2pMapping_HAL(pSubdevice, pParams) subdeviceCtrlCmdBusSetP2pMapping_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusUnsetP2pMapping(pSubdevice, pParams) subdeviceCtrlCmdBusUnsetP2pMapping_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBusUnsetP2pMapping_HAL(pSubdevice, pParams) subdeviceCtrlCmdBusUnsetP2pMapping_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetNvlinkCounters(pSubdevice, pParams) subdeviceCtrlCmdGetNvlinkCounters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdClearNvlinkCounters(pSubdevice, pParams) subdeviceCtrlCmdClearNvlinkCounters_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBusGetNvlinkCaps(pSubdevice, pParams) subdeviceCtrlCmdBusGetNvlinkCaps_DISPATCH(pSubdevice, pParams) @@ -817,13 +851,14 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkGetL1Threshold(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetL1Threshold_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdIsNvlinkReducedConfig(pSubdevice, pParams) subdeviceCtrlCmdIsNvlinkReducedConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkGetPortEvents(pSubdevice, pParams) subdeviceCtrlCmdNvlinkGetPortEvents_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdNvlinkCycleLink(pSubdevice, pParams) subdeviceCtrlCmdNvlinkCycleLink_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdI2cReadBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cWriteBuffer(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cWriteBuffer_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cReadReg(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cReadReg_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdI2cWriteReg(pSubdevice, pI2cParams) subdeviceCtrlCmdI2cWriteReg_DISPATCH(pSubdevice, pI2cParams) #define subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples(pSubdevice, pParams) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_HAL(pSubdevice, pParams) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2(pSubdevice, pParams) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_HAL(pSubdevice, pParams) subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdPerfRatedTdpGetControl(pSubdevice, pControlParams) subdeviceCtrlCmdPerfRatedTdpGetControl_DISPATCH(pSubdevice, pControlParams) #define subdeviceCtrlCmdPerfRatedTdpSetControl(pSubdevice, pControlParams) subdeviceCtrlCmdPerfRatedTdpSetControl_DISPATCH(pSubdevice, pControlParams) #define subdeviceCtrlCmdPerfRatedTdpSetControl_HAL(pSubdevice, pControlParams) subdeviceCtrlCmdPerfRatedTdpSetControl_DISPATCH(pSubdevice, pControlParams) @@ -833,6 +868,16 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdPerfSetAuxPowerState_HAL(pSubdevice, pPowerStateParams) subdeviceCtrlCmdPerfSetAuxPowerState_DISPATCH(pSubdevice, pPowerStateParams) #define subdeviceCtrlCmdPerfSetPowerstate(pSubdevice, pPowerInfoParams) subdeviceCtrlCmdPerfSetPowerstate_DISPATCH(pSubdevice, pPowerInfoParams) #define subdeviceCtrlCmdPerfSetPowerstate_HAL(pSubdevice, pPowerInfoParams) subdeviceCtrlCmdPerfSetPowerstate_DISPATCH(pSubdevice, pPowerInfoParams) +#define subdeviceCtrlCmdPerfGetLevelInfo_V2(pSubdevice, pLevelInfoParams) subdeviceCtrlCmdPerfGetLevelInfo_V2_DISPATCH(pSubdevice, pLevelInfoParams) +#define subdeviceCtrlCmdPerfGetLevelInfo_V2_HAL(pSubdevice, pLevelInfoParams) subdeviceCtrlCmdPerfGetLevelInfo_V2_DISPATCH(pSubdevice, pLevelInfoParams) +#define subdeviceCtrlCmdPerfGetCurrentPstate(pSubdevice, pInfoParams) subdeviceCtrlCmdPerfGetCurrentPstate_DISPATCH(pSubdevice, pInfoParams) +#define subdeviceCtrlCmdPerfGetCurrentPstate_HAL(pSubdevice, pInfoParams) subdeviceCtrlCmdPerfGetCurrentPstate_DISPATCH(pSubdevice, pInfoParams) +#define subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample(pSubdevice, pSampleParams) subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_DISPATCH(pSubdevice, pSampleParams) +#define subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_HAL(pSubdevice, pSampleParams) subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_DISPATCH(pSubdevice, pSampleParams) +#define subdeviceCtrlCmdPerfGetPowerstate(pSubdevice, powerInfoParams) subdeviceCtrlCmdPerfGetPowerstate_DISPATCH(pSubdevice, powerInfoParams) +#define subdeviceCtrlCmdPerfGetPowerstate_HAL(pSubdevice, powerInfoParams) subdeviceCtrlCmdPerfGetPowerstate_DISPATCH(pSubdevice, powerInfoParams) +#define subdeviceCtrlCmdPerfNotifyVideoevent(pSubdevice, pVideoEventParams) subdeviceCtrlCmdPerfNotifyVideoevent_DISPATCH(pSubdevice, pVideoEventParams) +#define subdeviceCtrlCmdPerfNotifyVideoevent_HAL(pSubdevice, pVideoEventParams) subdeviceCtrlCmdPerfNotifyVideoevent_DISPATCH(pSubdevice, pVideoEventParams) #define subdeviceCtrlCmdKPerfBoost(pSubdevice, pBoostParams) subdeviceCtrlCmdKPerfBoost_DISPATCH(pSubdevice, pBoostParams) #define subdeviceCtrlCmdFbGetFBRegionInfo(pSubdevice, pGFBRIParams) subdeviceCtrlCmdFbGetFBRegionInfo_DISPATCH(pSubdevice, pGFBRIParams) #define subdeviceCtrlCmdFbGetBar1Offset(pSubdevice, pFbMemParams) subdeviceCtrlCmdFbGetBar1Offset_DISPATCH(pSubdevice, pFbMemParams) @@ -843,7 +888,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout(pSubdevice, pParams) subdeviceCtrlCmdGbGetSemaphoreSurfaceLayout_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_HAL(pSubdevice, pParams) subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdFbGetInfo(pSubdevice, pFbInfoParams) subdeviceCtrlCmdFbGetInfo_DISPATCH(pSubdevice, pFbInfoParams) #define subdeviceCtrlCmdFbGetInfoV2(pSubdevice, pFbInfoParams) subdeviceCtrlCmdFbGetInfoV2_DISPATCH(pSubdevice, pFbInfoParams) #define subdeviceCtrlCmdFbGetCarveoutAddressInfo(pSubdevice, pParams) subdeviceCtrlCmdFbGetCarveoutAddressInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbGetCalibrationLockFailed(pSubdevice, pGCLFParams) subdeviceCtrlCmdFbGetCalibrationLockFailed_DISPATCH(pSubdevice, pGCLFParams) @@ -866,6 +910,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdFbUpdateNumaStatus(pSubdevice, pParams) subdeviceCtrlCmdFbUpdateNumaStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbGetNumaInfo(pSubdevice, pParams) subdeviceCtrlCmdFbGetNumaInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdMemSysGetStaticConfig(pSubdevice, pParams) subdeviceCtrlCmdMemSysGetStaticConfig_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdMemSysGetStaticConfig_HAL(pSubdevice, pParams) subdeviceCtrlCmdMemSysGetStaticConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdMemSysSetPartitionableMem(pSubdevice, pParams) subdeviceCtrlCmdMemSysSetPartitionableMem_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKMemSysGetMIGMemoryConfig(pSubdevice, pParams) subdeviceCtrlCmdKMemSysGetMIGMemoryConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFbSetZbcReferenced(pSubdevice, pParams) subdeviceCtrlCmdFbSetZbcReferenced_DISPATCH(pSubdevice, pParams) @@ -885,9 +930,15 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGetPhysicalChannelCount(pSubdevice, pParams) subdeviceCtrlCmdGetPhysicalChannelCount_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFifoGetInfo(pSubdevice, pFifoInfoParams) subdeviceCtrlCmdFifoGetInfo_DISPATCH(pSubdevice, pFifoInfoParams) #define subdeviceCtrlCmdFifoDisableChannels(pSubdevice, pDisableChannelParams) subdeviceCtrlCmdFifoDisableChannels_DISPATCH(pSubdevice, pDisableChannelParams) +#define subdeviceCtrlCmdFifoDisableChannelsForKeyRotation(pSubdevice, pDisableChannelParams) subdeviceCtrlCmdFifoDisableChannelsForKeyRotation_DISPATCH(pSubdevice, pDisableChannelParams) #define subdeviceCtrlCmdFifoDisableUsermodeChannels(pSubdevice, pParams) subdeviceCtrlCmdFifoDisableUsermodeChannels_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFifoGetChannelMemInfo(pSubdevice, pChannelMemParams) subdeviceCtrlCmdFifoGetChannelMemInfo_DISPATCH(pSubdevice, pChannelMemParams) #define subdeviceCtrlCmdFifoGetUserdLocation(pSubdevice, pUserdLocationParams) subdeviceCtrlCmdFifoGetUserdLocation_DISPATCH(pSubdevice, pUserdLocationParams) +#define subdeviceCtrlCmdFifoObjschedSwGetLog(pSubdevice, pParams) subdeviceCtrlCmdFifoObjschedSwGetLog_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdFifoObjschedGetState(pSubdevice, pParams) subdeviceCtrlCmdFifoObjschedGetState_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdFifoObjschedSetState(pSubdevice, pParams) subdeviceCtrlCmdFifoObjschedSetState_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdFifoObjschedGetCaps(pSubdevice, pParams) subdeviceCtrlCmdFifoObjschedGetCaps_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdFifoObjschedGetCaps_HAL(pSubdevice, pParams) subdeviceCtrlCmdFifoObjschedGetCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFifoGetDeviceInfoTable(pSubdevice, pParams) subdeviceCtrlCmdFifoGetDeviceInfoTable_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb(pSubdevice, pParams) subdeviceCtrlCmdFifoSetupVfZombieSubctxPdb_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFifoClearFaultedBit(pSubdevice, pParams) subdeviceCtrlCmdFifoClearFaultedBit_DISPATCH(pSubdevice, pParams) @@ -906,6 +957,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdKGrGetZcullInfo(pSubdevice, pZcullInfoParams) subdeviceCtrlCmdKGrGetZcullInfo_DISPATCH(pSubdevice, pZcullInfoParams) #define subdeviceCtrlCmdKGrCtxswPmMode(pSubdevice, pParams) subdeviceCtrlCmdKGrCtxswPmMode_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrCtxswPmBind(pSubdevice, pParams) subdeviceCtrlCmdKGrCtxswPmBind_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdKGrCtxswSetupBind(pSubdevice, pParams) subdeviceCtrlCmdKGrCtxswSetupBind_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrSetGpcTileMap(pSubdevice, pParams) subdeviceCtrlCmdKGrSetGpcTileMap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrCtxswSmpcMode(pSubdevice, pParams) subdeviceCtrlCmdKGrCtxswSmpcMode_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdKGrPcSamplingMode(pSubdevice, pParams) subdeviceCtrlCmdKGrPcSamplingMode_DISPATCH(pSubdevice, pParams) @@ -985,6 +1037,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetInforomObjectVersion(pSubdevice, pVersionInfo) subdeviceCtrlCmdGpuGetInforomObjectVersion_DISPATCH(pSubdevice, pVersionInfo) #define subdeviceCtrlCmdGpuQueryInforomEccSupport(pSubdevice) subdeviceCtrlCmdGpuQueryInforomEccSupport_DISPATCH(pSubdevice) #define subdeviceCtrlCmdGpuQueryEccStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuQueryEccStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuQueryEccStatus_HAL(pSubdevice, pParams) subdeviceCtrlCmdGpuQueryEccStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetChipDetails(pSubdevice, pParams) subdeviceCtrlCmdGpuGetChipDetails_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetOEMBoardInfo(pSubdevice, pBoardInfo) subdeviceCtrlCmdGpuGetOEMBoardInfo_DISPATCH(pSubdevice, pBoardInfo) #define subdeviceCtrlCmdGpuGetOEMInfo(pSubdevice, pOemInfo) subdeviceCtrlCmdGpuGetOEMInfo_DISPATCH(pSubdevice, pOemInfo) @@ -999,9 +1052,11 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGpuGetId(pSubdevice, pIdParams) subdeviceCtrlCmdGpuGetId_DISPATCH(pSubdevice, pIdParams) #define subdeviceCtrlCmdGpuGetGidInfo(pSubdevice, pGidInfoParams) subdeviceCtrlCmdGpuGetGidInfo_DISPATCH(pSubdevice, pGidInfoParams) #define subdeviceCtrlCmdGpuQueryIllumSupport(pSubdevice, pConfigParams) subdeviceCtrlCmdGpuQueryIllumSupport_DISPATCH(pSubdevice, pConfigParams) +#define subdeviceCtrlCmdGpuQueryIllumSupport_HAL(pSubdevice, pConfigParams) subdeviceCtrlCmdGpuQueryIllumSupport_DISPATCH(pSubdevice, pConfigParams) #define subdeviceCtrlCmdGpuGetIllum(pSubdevice, pConfigParams) subdeviceCtrlCmdGpuGetIllum_DISPATCH(pSubdevice, pConfigParams) #define subdeviceCtrlCmdGpuSetIllum(pSubdevice, pConfigParams) subdeviceCtrlCmdGpuSetIllum_DISPATCH(pSubdevice, pConfigParams) #define subdeviceCtrlCmdGpuQueryScrubberStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuQueryScrubberStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuQueryScrubberStatus_HAL(pSubdevice, pParams) subdeviceCtrlCmdGpuQueryScrubberStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetVprCaps(pSubdevice, pParams) subdeviceCtrlCmdGpuGetVprCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetVprInfo(pSubdevice, pParams) subdeviceCtrlCmdGpuGetVprInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetPids(pSubdevice, pGetPidsParams) subdeviceCtrlCmdGpuGetPids_DISPATCH(pSubdevice, pGetPidsParams) @@ -1024,6 +1079,8 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdGetGpuFabricProbeInfo(pSubdevice, pParams) subdeviceCtrlCmdGetGpuFabricProbeInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetResetStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuGetResetStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetDrainAndResetStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuGetDrainAndResetStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuGetConstructedFalconInfo(pSubdevice, pParams) subdeviceCtrlCmdGpuGetConstructedFalconInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlGpuGetFipsStatus(pSubdevice, pParams) subdeviceCtrlGpuGetFipsStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEventSetTrigger(pSubdevice) subdeviceCtrlCmdEventSetTrigger_DISPATCH(pSubdevice) #define subdeviceCtrlCmdEventSetTriggerFifo(pSubdevice, pTriggerFifoParams) subdeviceCtrlCmdEventSetTriggerFifo_DISPATCH(pSubdevice, pTriggerFifoParams) #define subdeviceCtrlCmdEventSetNotification(pSubdevice, pSetEventParams) subdeviceCtrlCmdEventSetNotification_DISPATCH(pSubdevice, pSetEventParams) @@ -1031,6 +1088,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdEventSetSemaphoreMemory(pSubdevice, pSetSemMemoryParams) subdeviceCtrlCmdEventSetSemaphoreMemory_DISPATCH(pSubdevice, pSetSemMemoryParams) #define subdeviceCtrlCmdEventSetSemaMemValidation(pSubdevice, pSetSemaMemValidationParams) subdeviceCtrlCmdEventSetSemaMemValidation_DISPATCH(pSubdevice, pSetSemaMemValidationParams) #define subdeviceCtrlCmdEventVideoBindEvtbuf(pSubdevice, pBindParams) subdeviceCtrlCmdEventVideoBindEvtbuf_DISPATCH(pSubdevice, pBindParams) +#define subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf(pSubdevice, pBindParams) subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf_DISPATCH(pSubdevice, pBindParams) #define subdeviceCtrlCmdTimerCancel(pSubdevice) subdeviceCtrlCmdTimerCancel_DISPATCH(pSubdevice) #define subdeviceCtrlCmdTimerSchedule(pSubdevice, pParams) subdeviceCtrlCmdTimerSchedule_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdTimerGetTime(pSubdevice, pParams) subdeviceCtrlCmdTimerGetTime_DISPATCH(pSubdevice, pParams) @@ -1055,6 +1113,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvdGetDump(pSubdevice, pDumpParams) subdeviceCtrlCmdNvdGetDump_DISPATCH(pSubdevice, pDumpParams) #define subdeviceCtrlCmdNvdGetNocatJournalRpt(pSubdevice, pReportParams) subdeviceCtrlCmdNvdGetNocatJournalRpt_DISPATCH(pSubdevice, pReportParams) #define subdeviceCtrlCmdNvdSetNocatJournalData(pSubdevice, pReportParams) subdeviceCtrlCmdNvdSetNocatJournalData_DISPATCH(pSubdevice, pReportParams) +#define subdeviceCtrlCmdNvdInsertNocatJournalRecord(pSubdevice, pReportParams) subdeviceCtrlCmdNvdInsertNocatJournalRecord_DISPATCH(pSubdevice, pReportParams) #define subdeviceCtrlCmdPmgrGetModuleInfo(pSubdevice, pModuleInfoParams) subdeviceCtrlCmdPmgrGetModuleInfo_DISPATCH(pSubdevice, pModuleInfoParams) #define subdeviceCtrlCmdGpuProcessPostGc6ExitTasks(pSubdevice) subdeviceCtrlCmdGpuProcessPostGc6ExitTasks_DISPATCH(pSubdevice) #define subdeviceCtrlCmdGc6Entry(pSubdevice, pParams) subdeviceCtrlCmdGc6Entry_DISPATCH(pSubdevice, pParams) @@ -1076,14 +1135,20 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags(pSubdevice, pParams) subdeviceCtrlCmdInternalFlcnSetVideoEventBufferFlags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalFlcnSetVideoEventBufferMemory(pSubdevice, pParams) subdeviceCtrlCmdInternalFlcnSetVideoEventBufferMemory_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdEccGetClientExposedCounters(pSubdevice, pParams) subdeviceCtrlCmdEccGetClientExposedCounters_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdEccGetEciCounters(pSubdevice, pParams) subdeviceCtrlCmdEccGetEciCounters_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdEccGetVolatileCounts(pSubdevice, pParams) subdeviceCtrlCmdEccGetVolatileCounts_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuQueryEccConfiguration(pSubdevice, pConfig) subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH(pSubdevice, pConfig) +#define subdeviceCtrlCmdGpuQueryEccConfiguration_HAL(pSubdevice, pConfig) subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH(pSubdevice, pConfig) #define subdeviceCtrlCmdGpuSetEccConfiguration(pSubdevice, pConfig) subdeviceCtrlCmdGpuSetEccConfiguration_DISPATCH(pSubdevice, pConfig) +#define subdeviceCtrlCmdGpuSetEccConfiguration_HAL(pSubdevice, pConfig) subdeviceCtrlCmdGpuSetEccConfiguration_DISPATCH(pSubdevice, pConfig) #define subdeviceCtrlCmdGpuResetEccErrorStatus(pSubdevice, pParams) subdeviceCtrlCmdGpuResetEccErrorStatus_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdGpuResetEccErrorStatus_HAL(pSubdevice, pParams) subdeviceCtrlCmdGpuResetEccErrorStatus_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlaRange(pSubdevice, pParams) subdeviceCtrlCmdFlaRange_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlaSetupInstanceMemBlock(pSubdevice, pParams) subdeviceCtrlCmdFlaSetupInstanceMemBlock_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlaGetRange(pSubdevice, pParams) subdeviceCtrlCmdFlaGetRange_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlaGetFabricMemStats(pSubdevice, pParams) subdeviceCtrlCmdFlaGetFabricMemStats_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGspGetFeatures(pSubdevice, pGspFeaturesParams) subdeviceCtrlCmdGspGetFeatures_DISPATCH(pSubdevice, pGspFeaturesParams) +#define subdeviceCtrlCmdGspGetFeatures_HAL(pSubdevice, pGspFeaturesParams) subdeviceCtrlCmdGspGetFeatures_DISPATCH(pSubdevice, pGspFeaturesParams) #define subdeviceCtrlCmdGspGetRmHeapStats(pSubdevice, pGspRmHeapStatsParams) subdeviceCtrlCmdGspGetRmHeapStats_DISPATCH(pSubdevice, pGspRmHeapStatsParams) #define subdeviceCtrlCmdGpuGetActivePartitionIds(pSubdevice, pParams) subdeviceCtrlCmdGpuGetActivePartitionIds_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGpuGetPartitionCapacity(pSubdevice, pParams) subdeviceCtrlCmdGpuGetPartitionCapacity_DISPATCH(pSubdevice, pParams) @@ -1099,6 +1164,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles(pSubdevice, pParams) subdeviceCtrlCmdInternalStaticKMIGmgrGetComputeInstanceProfiles_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrExportGPUInstance_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange(pSubdevice, pParams) subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixGc6BlockerRefCnt(pSubdevice, pParams) subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixAllowDisallowGcoff(pSubdevice, pParams) subdeviceCtrlCmdOsUnixAllowDisallowGcoff_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdOsUnixAudioDynamicPower(pSubdevice, pParams) subdeviceCtrlCmdOsUnixAudioDynamicPower_DISPATCH(pSubdevice, pParams) @@ -1120,17 +1186,17 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated(pSubdevice) subdeviceCtrlCmdInternalDisplayAcpiSubsytemActivated_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalDisplayPreModeSet(pSubdevice) subdeviceCtrlCmdInternalDisplayPreModeSet_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalDisplayPostModeSet(pSubdevice) subdeviceCtrlCmdInternalDisplayPostModeSet_DISPATCH(pSubdevice) -#define subdeviceCtrlCmdDisplayUnixConsole(pSubdevice, pParams) subdeviceCtrlCmdDisplayUnixConsole_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdDisplayPostVgaRestore(pSubdevice, pParams) subdeviceCtrlCmdDisplayPostVgaRestore_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdDisplayPreUnixConsole(pSubdevice, pParams) subdeviceCtrlCmdDisplayPreUnixConsole_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdDisplayPostUnixConsole(pSubdevice, pParams) subdeviceCtrlCmdDisplayPostUnixConsole_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdMsencGetCaps(pSubdevice, pParams) subdeviceCtrlCmdMsencGetCaps_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmRegisterAccessCntrBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer(pSubdevice, pParams) subdeviceCtrlCmdInternalUvmUnregisterAccessCntrBuffer_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetChipInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalGetChipInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetUserRegisterAccessMap(pSubdevice, pParams) subdeviceCtrlCmdInternalGetUserRegisterAccessMap_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGetDeviceInfoTable(pSubdevice, pParams) subdeviceCtrlCmdInternalGetDeviceInfoTable_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalGetConstructedFalconInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalGetConstructedFalconInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalRecoverAllComputeContexts(pSubdevice) subdeviceCtrlCmdInternalRecoverAllComputeContexts_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalGetSmcMode(pSubdevice, pParams) subdeviceCtrlCmdInternalGetSmcMode_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdIsEgpuBridge(pSubdevice, pParams) subdeviceCtrlCmdIsEgpuBridge_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalBusFlushWithSysmembar(pSubdevice) subdeviceCtrlCmdInternalBusFlushWithSysmembar_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal(pSubdevice, pParams) subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote(pSubdevice, pParams) subdeviceCtrlCmdInternalBusSetupP2pMailboxRemote_DISPATCH(pSubdevice, pParams) @@ -1164,6 +1230,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalPerfGetAuxPowerState(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfGetAuxPowerState_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalGcxEntryPrerequisite(pSubdevice, pGcxEntryPrerequisite) subdeviceCtrlCmdInternalGcxEntryPrerequisite_DISPATCH(pSubdevice, pGcxEntryPrerequisite) #define subdeviceCtrlCmdBifGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBifGetStaticInfo_HAL(pSubdevice, pParams) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetAspmL1Flags(pSubdevice, pParams) subdeviceCtrlCmdBifGetAspmL1Flags_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifSetPcieRo(pSubdevice, pParams) subdeviceCtrlCmdBifSetPcieRo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifDisableSystemMemoryAccess(pSubdevice, pParams) subdeviceCtrlCmdBifDisableSystemMemoryAccess_DISPATCH(pSubdevice, pParams) @@ -1210,11 +1277,12 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit(pSubdevice) subdeviceCtrlCmdInternalPmgrUnsetDynamicBoostLimit_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalDetectHsVideoBridge(pSubdevice) subdeviceCtrlCmdInternalDetectHsVideoBridge_DISPATCH(pSubdevice) #define subdeviceCtrlCmdInternalConfComputeGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeGetStaticInfo_DISPATCH(pSubdevice, pParams) -#define subdeviceCtrlCmdInternalConfComputeEncryptionControl(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeEncryptionControl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalConfComputeDeriveLceKeys(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalConfComputeSetGpuState(pSubdevice, pParams) subdeviceCtrlCmdInternalConfComputeSetGpuState_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalInitUserSharedData(pSubdevice, pParams) subdeviceCtrlCmdInternalInitUserSharedData_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdInternalUserSharedDataSetDataPoll(pSubdevice, pParams) subdeviceCtrlCmdInternalUserSharedDataSetDataPoll_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdInternalGspStartTrace(pSubdevice, pParams) subdeviceCtrlCmdInternalGspStartTrace_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType_DISPATCH(pSubdevice, pParams) @@ -1226,6 +1294,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdVgpuMgrInternalFreeStates(pSubdevice, pParams) subdeviceCtrlCmdVgpuMgrInternalFreeStates_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdGetAvailableHshubMask(pSubdevice, pParams) subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlSetEcThrottleMode(pSubdevice, pParams) subdeviceCtrlSetEcThrottleMode_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCcuMap(pSubdevice, pParams) subdeviceCtrlCmdCcuMap_DISPATCH(pSubdevice, pParams) @@ -1244,7 +1313,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) subdeviceGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) #define subdeviceUnmapFrom(pResource, pParams) subdeviceUnmapFrom_DISPATCH(pResource, pParams) #define subdeviceControl_Epilogue(pResource, pCallContext, pParams) subdeviceControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define subdeviceControlLookup(pResource, pParams, ppEntry) subdeviceControlLookup_DISPATCH(pResource, pParams, ppEntry) #define subdeviceGetInternalObjectHandle(pGpuResource) subdeviceGetInternalObjectHandle_DISPATCH(pGpuResource) #define subdeviceControl(pGpuResource, pCallContext, pParams) subdeviceControl_DISPATCH(pGpuResource, pCallContext, pParams) #define subdeviceUnmap(pGpuResource, pCallContext, pCpuMapping) subdeviceUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -1253,6 +1321,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) subdeviceUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define subdeviceControlSerialization_Prologue(pResource, pCallContext, pParams) subdeviceControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define subdeviceCanCopy(pResource) subdeviceCanCopy_DISPATCH(pResource) +#define subdeviceIsPartialUnmapSupported(pResource) subdeviceIsPartialUnmapSupported_DISPATCH(pResource) #define subdeviceIsDuplicate(pResource, hMemory, pDuplicate) subdeviceIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define subdeviceControlSerialization_Epilogue(pResource, pCallContext, pParams) subdeviceControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define subdeviceGetNotificationListPtr(pNotifier) subdeviceGetNotificationListPtr_DISPATCH(pNotifier) @@ -1277,7 +1346,14 @@ static inline NV_STATUS subdeviceControlFilter_DISPATCH(struct Subdevice *pSubde return pSubdevice->__subdeviceControlFilter__(pSubdevice, pCallContext, pParams); } -NV_STATUS subdeviceCtrlCmdBiosGetInfoV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *pBiosInfoParams); +static inline NV_STATUS subdeviceCtrlCmdBiosGetInfoV2_ac1694(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *pBiosInfoParams) { + return NV_OK; +} + +static inline NV_STATUS subdeviceCtrlCmdBiosGetInfoV2_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *pBiosInfoParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdBiosGetInfoV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *pBiosInfoParams) { return pSubdevice->__subdeviceCtrlCmdBiosGetInfoV2__(pSubdevice, pBiosInfoParams); @@ -1289,13 +1365,23 @@ static inline NV_STATUS subdeviceCtrlCmdBiosGetNbsiV2_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdBiosGetNbsiV2__(pSubdevice, pNbsiParams); } -NV_STATUS subdeviceCtrlCmdBiosGetSKUInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pBiosGetSKUInfoParams); +NV_STATUS subdeviceCtrlCmdBiosGetSKUInfo_VF(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pBiosGetSKUInfoParams); + +static inline NV_STATUS subdeviceCtrlCmdBiosGetSKUInfo_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pBiosGetSKUInfoParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdBiosGetSKUInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pBiosGetSKUInfoParams) { return pSubdevice->__subdeviceCtrlCmdBiosGetSKUInfo__(pSubdevice, pBiosGetSKUInfoParams); } -NV_STATUS subdeviceCtrlCmdBiosGetPostTime_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS *pBiosPostTime); +NV_STATUS subdeviceCtrlCmdBiosGetPostTime_VF(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS *pBiosPostTime); + +static inline NV_STATUS subdeviceCtrlCmdBiosGetPostTime_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS *pBiosPostTime) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdBiosGetPostTime_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS *pBiosPostTime) { return pSubdevice->__subdeviceCtrlCmdBiosGetPostTime__(pSubdevice, pBiosPostTime); @@ -1343,6 +1429,18 @@ static inline NV_STATUS subdeviceCtrlCmdMcServiceInterrupts_DISPATCH(struct Subd return pSubdevice->__subdeviceCtrlCmdMcServiceInterrupts__(pSubdevice, pServiceInterruptParams); } +NV_STATUS subdeviceCtrlCmdMcGetEngineNotificationIntrVectors_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdMcGetEngineNotificationIntrVectors_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdMcGetEngineNotificationIntrVectors__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdMcGetStaticIntrTable_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdMcGetStaticIntrTable_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdMcGetStaticIntrTable__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdDmaInvalidateTLB_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdDmaInvalidateTLB_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS *pParams) { @@ -1505,7 +1603,12 @@ static inline NV_STATUS subdeviceCtrlCmdBusGetEomStatus_DISPATCH(struct Subdevic return pSubdevice->__subdeviceCtrlCmdBusGetEomStatus__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_VF(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdBusGetPcieReqAtomicsCaps__(pSubdevice, pParams); @@ -1529,13 +1632,21 @@ static inline NV_STATUS subdeviceCtrlCmdBusSysmemAccess_DISPATCH(struct Subdevic return pSubdevice->__subdeviceCtrlCmdBusSysmemAccess__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdBusSetP2pMapping_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdBusSetP2pMapping_VGPUSTUB(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusSetP2pMapping_5baef9(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS subdeviceCtrlCmdBusSetP2pMapping_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdBusSetP2pMapping__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdBusUnsetP2pMapping_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdBusUnsetP2pMapping_VGPUSTUB(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBusUnsetP2pMapping_5baef9(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS subdeviceCtrlCmdBusUnsetP2pMapping_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdBusUnsetP2pMapping__(pSubdevice, pParams); @@ -1877,12 +1988,6 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkGetPortEvents_DISPATCH(struct Subd return pSubdevice->__subdeviceCtrlCmdNvlinkGetPortEvents__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdNvlinkCycleLink_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdNvlinkCycleLink_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_CYCLE_LINK_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdNvlinkCycleLink__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdI2cReadBuffer_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams); static inline NV_STATUS subdeviceCtrlCmdI2cReadBuffer_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_I2C_READ_BUFFER_PARAMS *pI2cParams) { @@ -1907,13 +2012,21 @@ static inline NV_STATUS subdeviceCtrlCmdI2cWriteReg_DISPATCH(struct Subdevice *p return pSubdevice->__subdeviceCtrlCmdI2cWriteReg__(pSubdevice, pI2cParams); } -NV_STATUS subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *pParams); +NV_STATUS subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_VF(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *pParams); + +static inline NV_STATUS subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_5baef9(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *pParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *pParams) { return pSubdevice->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_VF(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_5baef9(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS *pParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2__(pSubdevice, pParams); @@ -1933,6 +2046,10 @@ static inline NV_STATUS subdeviceCtrlCmdPerfRatedTdpSetControl_DISPATCH(struct S NV_STATUS subdeviceCtrlCmdPerfReservePerfmonHw_KERNEL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *pPerfmonParams); +static inline NV_STATUS subdeviceCtrlCmdPerfReservePerfmonHw_46f6a7(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *pPerfmonParams) { + return NV_ERR_NOT_SUPPORTED; +} + static inline NV_STATUS subdeviceCtrlCmdPerfReservePerfmonHw_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_RESERVE_PERFMON_HW_PARAMS *pPerfmonParams) { return pSubdevice->__subdeviceCtrlCmdPerfReservePerfmonHw__(pSubdevice, pPerfmonParams); } @@ -1949,6 +2066,63 @@ static inline NV_STATUS subdeviceCtrlCmdPerfSetPowerstate_DISPATCH(struct Subdev return pSubdevice->__subdeviceCtrlCmdPerfSetPowerstate__(pSubdevice, pPowerInfoParams); } +NV_STATUS subdeviceCtrlCmdPerfGetLevelInfo_V2_VF(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS *pLevelInfoParams); + +static inline NV_STATUS subdeviceCtrlCmdPerfGetLevelInfo_V2_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS *pLevelInfoParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS subdeviceCtrlCmdPerfGetLevelInfo_V2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS *pLevelInfoParams) { + return pSubdevice->__subdeviceCtrlCmdPerfGetLevelInfo_V2__(pSubdevice, pLevelInfoParams); +} + +NV_STATUS subdeviceCtrlCmdPerfGetCurrentPstate_VF(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS *pInfoParams); + +static inline NV_STATUS subdeviceCtrlCmdPerfGetCurrentPstate_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS *pInfoParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS subdeviceCtrlCmdPerfGetCurrentPstate_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS *pInfoParams) { + return pSubdevice->__subdeviceCtrlCmdPerfGetCurrentPstate__(pSubdevice, pInfoParams); +} + +NV_STATUS subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_VF(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS *pSampleParams); + +static inline NV_STATUS subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS *pSampleParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS *pSampleParams) { + return pSubdevice->__subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample__(pSubdevice, pSampleParams); +} + +NV_STATUS subdeviceCtrlCmdPerfGetPowerstate_VF(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS *powerInfoParams); + +static inline NV_STATUS subdeviceCtrlCmdPerfGetPowerstate_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS *powerInfoParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS subdeviceCtrlCmdPerfGetPowerstate_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS *powerInfoParams) { + return pSubdevice->__subdeviceCtrlCmdPerfGetPowerstate__(pSubdevice, powerInfoParams); +} + +static inline NV_STATUS subdeviceCtrlCmdPerfNotifyVideoevent_ac1694(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS *pVideoEventParams) { + return NV_OK; +} + +static inline NV_STATUS subdeviceCtrlCmdPerfNotifyVideoevent_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS *pVideoEventParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS subdeviceCtrlCmdPerfNotifyVideoevent_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_NOTIFY_VIDEOEVENT_PARAMS *pVideoEventParams) { + return pSubdevice->__subdeviceCtrlCmdPerfNotifyVideoevent__(pSubdevice, pVideoEventParams); +} + NV_STATUS subdeviceCtrlCmdKPerfBoost_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams); static inline NV_STATUS subdeviceCtrlCmdKPerfBoost_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PERF_BOOST_PARAMS *pBoostParams) { @@ -2005,12 +2179,6 @@ static inline NV_STATUS subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp_DISP return pSubdevice->__subdeviceCtrlCmdInternalMemmgrMemoryTransferWithGsp__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdFbGetInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams); - -static inline NV_STATUS subdeviceCtrlCmdFbGetInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams) { - return pSubdevice->__subdeviceCtrlCmdFbGetInfo__(pSubdevice, pFbInfoParams); -} - NV_STATUS subdeviceCtrlCmdFbGetInfoV2_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pFbInfoParams); static inline NV_STATUS subdeviceCtrlCmdFbGetInfoV2_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pFbInfoParams) { @@ -2137,7 +2305,12 @@ static inline NV_STATUS subdeviceCtrlCmdFbGetNumaInfo_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdFbGetNumaInfo__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdMemSysGetStaticConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdMemSysGetStaticConfig_VGPUSTUB(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdMemSysGetStaticConfig_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdMemSysGetStaticConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdMemSysGetStaticConfig__(pSubdevice, pParams); @@ -2259,6 +2432,12 @@ static inline NV_STATUS subdeviceCtrlCmdFifoDisableChannels_DISPATCH(struct Subd return pSubdevice->__subdeviceCtrlCmdFifoDisableChannels__(pSubdevice, pDisableChannelParams); } +NV_STATUS subdeviceCtrlCmdFifoDisableChannelsForKeyRotation_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS *pDisableChannelParams); + +static inline NV_STATUS subdeviceCtrlCmdFifoDisableChannelsForKeyRotation_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS *pDisableChannelParams) { + return pSubdevice->__subdeviceCtrlCmdFifoDisableChannelsForKeyRotation__(pSubdevice, pDisableChannelParams); +} + NV_STATUS subdeviceCtrlCmdFifoDisableUsermodeChannels_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdFifoDisableUsermodeChannels_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS *pParams) { @@ -2277,6 +2456,36 @@ static inline NV_STATUS subdeviceCtrlCmdFifoGetUserdLocation_DISPATCH(struct Sub return pSubdevice->__subdeviceCtrlCmdFifoGetUserdLocation__(pSubdevice, pUserdLocationParams); } +NV_STATUS subdeviceCtrlCmdFifoObjschedSwGetLog_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdFifoObjschedSwGetLog_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_SW_GET_LOG_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdFifoObjschedSwGetLog__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdFifoObjschedGetState_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdFifoObjschedGetState_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdFifoObjschedGetState__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdFifoObjschedSetState_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdFifoObjschedSetState_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_SET_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdFifoObjschedSetState__(pSubdevice, pParams); +} + +static inline NV_STATUS subdeviceCtrlCmdFifoObjschedGetCaps_ac1694(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS *pParams) { + return NV_OK; +} + +static inline NV_STATUS subdeviceCtrlCmdFifoObjschedGetCaps_5baef9(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS *pParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS subdeviceCtrlCmdFifoObjschedGetCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdFifoObjschedGetCaps__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdFifoGetDeviceInfoTable_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdFifoGetDeviceInfoTable_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *pParams) { @@ -2385,6 +2594,12 @@ static inline NV_STATUS subdeviceCtrlCmdKGrCtxswPmBind_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdKGrCtxswPmBind__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdKGrCtxswSetupBind_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdKGrCtxswSetupBind_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GR_CTXSW_SETUP_BIND_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdKGrCtxswSetupBind__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdKGrSetGpcTileMap_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdKGrSetGpcTileMap_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS *pParams) { @@ -2853,7 +3068,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuQueryInforomEccSupport_DISPATCH(struc return pSubdevice->__subdeviceCtrlCmdGpuQueryInforomEccSupport__(pSubdevice); } -NV_STATUS subdeviceCtrlCmdGpuQueryEccStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdGpuQueryEccStatus_VF(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuQueryEccStatus_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdGpuQueryEccStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdGpuQueryEccStatus__(pSubdevice, pParams); @@ -2937,7 +3157,11 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetGidInfo_DISPATCH(struct Subdevice return pSubdevice->__subdeviceCtrlCmdGpuGetGidInfo__(pSubdevice, pGidInfoParams); } -NV_STATUS subdeviceCtrlCmdGpuQueryIllumSupport_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS *pConfigParams); +NV_STATUS subdeviceCtrlCmdGpuQueryIllumSupport_VF(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS *pConfigParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuQueryIllumSupport_5baef9(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS *pConfigParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS subdeviceCtrlCmdGpuQueryIllumSupport_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS *pConfigParams) { return pSubdevice->__subdeviceCtrlCmdGpuQueryIllumSupport__(pSubdevice, pConfigParams); @@ -2955,7 +3179,12 @@ static inline NV_STATUS subdeviceCtrlCmdGpuSetIllum_DISPATCH(struct Subdevice *p return pSubdevice->__subdeviceCtrlCmdGpuSetIllum__(pSubdevice, pConfigParams); } -NV_STATUS subdeviceCtrlCmdGpuQueryScrubberStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdGpuQueryScrubberStatus_VF(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuQueryScrubberStatus_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdGpuQueryScrubberStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdGpuQueryScrubberStatus__(pSubdevice, pParams); @@ -3093,6 +3322,18 @@ static inline NV_STATUS subdeviceCtrlCmdGpuGetDrainAndResetStatus_DISPATCH(struc return pSubdevice->__subdeviceCtrlCmdGpuGetDrainAndResetStatus__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdGpuGetConstructedFalconInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuGetConstructedFalconInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdGpuGetConstructedFalconInfo__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlGpuGetFipsStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlGpuGetFipsStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlGpuGetFipsStatus__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdEventSetTrigger_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdEventSetTrigger_DISPATCH(struct Subdevice *pSubdevice) { @@ -3135,6 +3376,12 @@ static inline NV_STATUS subdeviceCtrlCmdEventVideoBindEvtbuf_DISPATCH(struct Sub return pSubdevice->__subdeviceCtrlCmdEventVideoBindEvtbuf__(pSubdevice, pBindParams); } +NV_STATUS subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS *pBindParams); + +static inline NV_STATUS subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS *pBindParams) { + return pSubdevice->__subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf__(pSubdevice, pBindParams); +} + NV_STATUS subdeviceCtrlCmdTimerCancel_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdTimerCancel_DISPATCH(struct Subdevice *pSubdevice) { @@ -3279,6 +3526,12 @@ static inline NV_STATUS subdeviceCtrlCmdNvdSetNocatJournalData_DISPATCH(struct S return pSubdevice->__subdeviceCtrlCmdNvdSetNocatJournalData__(pSubdevice, pReportParams); } +NV_STATUS subdeviceCtrlCmdNvdInsertNocatJournalRecord_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS *pReportParams); + +static inline NV_STATUS subdeviceCtrlCmdNvdInsertNocatJournalRecord_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS *pReportParams) { + return pSubdevice->__subdeviceCtrlCmdNvdInsertNocatJournalRecord__(pSubdevice, pReportParams); +} + NV_STATUS subdeviceCtrlCmdPmgrGetModuleInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_PMGR_MODULE_INFO_PARAMS *pModuleInfoParams); static inline NV_STATUS subdeviceCtrlCmdPmgrGetModuleInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_PMGR_MODULE_INFO_PARAMS *pModuleInfoParams) { @@ -3405,19 +3658,46 @@ static inline NV_STATUS subdeviceCtrlCmdEccGetClientExposedCounters_DISPATCH(str return pSubdevice->__subdeviceCtrlCmdEccGetClientExposedCounters__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdGpuQueryEccConfiguration_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *pConfig); +NV_STATUS subdeviceCtrlCmdEccGetEciCounters_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdEccGetEciCounters_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_ECI_COUNTERS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdEccGetEciCounters__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdEccGetVolatileCounts_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdEccGetVolatileCounts_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_ECC_GET_VOLATILE_COUNTS_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdEccGetVolatileCounts__(pSubdevice, pParams); +} + +NV_STATUS subdeviceCtrlCmdGpuQueryEccConfiguration_VF(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *pConfig); + +static inline NV_STATUS subdeviceCtrlCmdGpuQueryEccConfiguration_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *pConfig) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdGpuQueryEccConfiguration_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *pConfig) { return pSubdevice->__subdeviceCtrlCmdGpuQueryEccConfiguration__(pSubdevice, pConfig); } -NV_STATUS subdeviceCtrlCmdGpuSetEccConfiguration_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *pConfig); +NV_STATUS subdeviceCtrlCmdGpuSetEccConfiguration_VF(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *pConfig); + +static inline NV_STATUS subdeviceCtrlCmdGpuSetEccConfiguration_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *pConfig) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdGpuSetEccConfiguration_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *pConfig) { return pSubdevice->__subdeviceCtrlCmdGpuSetEccConfiguration__(pSubdevice, pConfig); } -NV_STATUS subdeviceCtrlCmdGpuResetEccErrorStatus_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdGpuResetEccErrorStatus_VF(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdGpuResetEccErrorStatus_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdGpuResetEccErrorStatus_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdGpuResetEccErrorStatus__(pSubdevice, pParams); @@ -3447,7 +3727,12 @@ static inline NV_STATUS subdeviceCtrlCmdFlaGetFabricMemStats_DISPATCH(struct Sub return pSubdevice->__subdeviceCtrlCmdFlaGetFabricMemStats__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdGspGetFeatures_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_GSP_GET_FEATURES_PARAMS *pGspFeaturesParams); +NV_STATUS subdeviceCtrlCmdGspGetFeatures_KERNEL(struct Subdevice *pSubdevice, NV2080_CTRL_GSP_GET_FEATURES_PARAMS *pGspFeaturesParams); + +static inline NV_STATUS subdeviceCtrlCmdGspGetFeatures_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_GSP_GET_FEATURES_PARAMS *pGspFeaturesParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdGspGetFeatures_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_GSP_GET_FEATURES_PARAMS *pGspFeaturesParams) { return pSubdevice->__subdeviceCtrlCmdGspGetFeatures__(pSubdevice, pGspFeaturesParams); @@ -3543,6 +3828,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_DISPATC return pSubdevice->__subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalKMIGmgrPromoteGpuInstanceMemRange__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdOsUnixGc6BlockerRefCnt_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_OS_UNIX_GC6_BLOCKER_REFCNT_PARAMS *pParams) { @@ -3669,16 +3960,16 @@ static inline NV_STATUS subdeviceCtrlCmdInternalDisplayPostModeSet_DISPATCH(stru return pSubdevice->__subdeviceCtrlCmdInternalDisplayPostModeSet__(pSubdevice); } -NV_STATUS subdeviceCtrlCmdDisplayUnixConsole_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdDisplayPreUnixConsole_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdDisplayUnixConsole_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdDisplayUnixConsole__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdDisplayPreUnixConsole_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplayPreUnixConsole__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdDisplayPostVgaRestore_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdDisplayPostUnixConsole_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS *pParams); -static inline NV_STATUS subdeviceCtrlCmdDisplayPostVgaRestore_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdDisplayPostVgaRestore__(pSubdevice, pParams); +static inline NV_STATUS subdeviceCtrlCmdDisplayPostUnixConsole_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_UNIX_CONSOLE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdDisplayPostUnixConsole__(pSubdevice, pParams); } NV_STATUS subdeviceCtrlCmdMsencGetCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS *pParams); @@ -3717,12 +4008,6 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGetDeviceInfoTable_DISPATCH(stru return pSubdevice->__subdeviceCtrlCmdInternalGetDeviceInfoTable__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalGetConstructedFalconInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdInternalGetConstructedFalconInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalGetConstructedFalconInfo__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdInternalRecoverAllComputeContexts_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdInternalRecoverAllComputeContexts_DISPATCH(struct Subdevice *pSubdevice) { @@ -3735,6 +4020,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGetSmcMode_DISPATCH(struct Subde return pSubdevice->__subdeviceCtrlCmdInternalGetSmcMode__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdIsEgpuBridge_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdIsEgpuBridge_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_EGPU_BRIDGE_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdIsEgpuBridge__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalBusFlushWithSysmembar_IMPL(struct Subdevice *pSubdevice); static inline NV_STATUS subdeviceCtrlCmdInternalBusFlushWithSysmembar_DISPATCH(struct Subdevice *pSubdevice) { @@ -3927,7 +4218,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGcxEntryPrerequisite_DISPATCH(st return pSubdevice->__subdeviceCtrlCmdInternalGcxEntryPrerequisite__(pSubdevice, pGcxEntryPrerequisite); } -NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams); +NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_VGPUSTUB(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_92bfc3(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams) { + NV_ASSERT_PRECOMP(0); + return NV_ERR_NOT_SUPPORTED; +} static inline NV_STATUS subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams) { return pSubdevice->__subdeviceCtrlCmdBifGetStaticInfo__(pSubdevice, pParams); @@ -4209,12 +4505,6 @@ static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeGetStaticInfo_DISPATC return pSubdevice->__subdeviceCtrlCmdInternalConfComputeGetStaticInfo__(pSubdevice, pParams); } -NV_STATUS subdeviceCtrlCmdInternalConfComputeEncryptionControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS *pParams); - -static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeEncryptionControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS *pParams) { - return pSubdevice->__subdeviceCtrlCmdInternalConfComputeEncryptionControl__(pSubdevice, pParams); -} - NV_STATUS subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeDeriveSwlKeys_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_CONF_COMPUTE_DERIVE_SWL_KEYS_PARAMS *pParams) { @@ -4227,6 +4517,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeDeriveLceKeys_DISPATC return pSubdevice->__subdeviceCtrlCmdInternalConfComputeDeriveLceKeys__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalConfComputeSetGpuState_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalConfComputeSetGpuState_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalConfComputeSetGpuState__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdInternalInitUserSharedData_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdInternalInitUserSharedData_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS *pParams) { @@ -4239,6 +4535,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalUserSharedDataSetDataPoll_DISPAT return pSubdevice->__subdeviceCtrlCmdInternalUserSharedDataSetDataPoll__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdInternalGspStartTrace_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdInternalGspStartTrace_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_INTERNAL_GSP_START_TRACE_INFO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdInternalGspStartTrace__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pParams) { @@ -4305,6 +4607,12 @@ static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig_DISPATCH return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdVgpuMgrInternalFreeStates_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdVgpuMgrInternalFreeStates_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdVgpuMgrInternalFreeStates__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdGetAvailableHshubMask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *pParams) { @@ -4389,10 +4697,6 @@ static inline void subdeviceControl_Epilogue_DISPATCH(struct Subdevice *pResourc pResource->__subdeviceControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS subdeviceControlLookup_DISPATCH(struct Subdevice *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__subdeviceControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle subdeviceGetInternalObjectHandle_DISPATCH(struct Subdevice *pGpuResource) { return pGpuResource->__subdeviceGetInternalObjectHandle__(pGpuResource); } @@ -4425,6 +4729,10 @@ static inline NvBool subdeviceCanCopy_DISPATCH(struct Subdevice *pResource) { return pResource->__subdeviceCanCopy__(pResource); } +static inline NvBool subdeviceIsPartialUnmapSupported_DISPATCH(struct Subdevice *pResource) { + return pResource->__subdeviceIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS subdeviceIsDuplicate_DISPATCH(struct Subdevice *pResource, NvHandle hMemory, NvBool *pDuplicate) { return pResource->__subdeviceIsDuplicate__(pResource, hMemory, pDuplicate); } @@ -4465,6 +4773,10 @@ static inline void subdeviceRestoreLockedClock(struct Subdevice *pSubdevice, str return; } +static inline void subdeviceRestoreVF(struct Subdevice *pSubdevice, struct CALL_CONTEXT *pCallContext) { + return; +} + static inline void subdeviceReleaseNvlinkErrorInjectionMode(struct Subdevice *pSubdevice, struct CALL_CONTEXT *pCallContext) { return; } diff --git a/src/nvidia/generated/g_sw_test_nvoc.c b/src/nvidia/generated/g_sw_test_nvoc.c index 5ca8111510..4229aa51c4 100644 --- a/src/nvidia/generated/g_sw_test_nvoc.c +++ b/src/nvidia/generated/g_sw_test_nvoc.c @@ -176,10 +176,6 @@ static void __nvoc_thunk_RmResource_swtestControl_Epilogue(struct SoftwareMethod rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_swtestControlLookup(struct SoftwareMethodTest *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_swtestGetInternalObjectHandle(struct SoftwareMethodTest *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_SoftwareMethodTest_GpuResource.offset)); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_swtestCanCopy(struct SoftwareMethodTest *p return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_swtestIsPartialUnmapSupported(struct SoftwareMethodTest *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_swtestPreDestruct(struct SoftwareMethodTest *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SoftwareMethodTest_RsResource.offset)); } @@ -317,8 +317,6 @@ static void __nvoc_init_funcTable_SoftwareMethodTest_1(SoftwareMethodTest *pThis pThis->__swtestControl_Epilogue__ = &__nvoc_thunk_RmResource_swtestControl_Epilogue; - pThis->__swtestControlLookup__ = &__nvoc_thunk_RsResource_swtestControlLookup; - pThis->__swtestGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_swtestGetInternalObjectHandle; pThis->__swtestControl__ = &__nvoc_thunk_GpuResource_swtestControl; @@ -339,6 +337,8 @@ static void __nvoc_init_funcTable_SoftwareMethodTest_1(SoftwareMethodTest *pThis pThis->__swtestCanCopy__ = &__nvoc_thunk_RsResource_swtestCanCopy; + pThis->__swtestIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_swtestIsPartialUnmapSupported; + pThis->__swtestPreDestruct__ = &__nvoc_thunk_RsResource_swtestPreDestruct; pThis->__swtestIsDuplicate__ = &__nvoc_thunk_RsResource_swtestIsDuplicate; @@ -373,23 +373,31 @@ void __nvoc_init_SoftwareMethodTest(SoftwareMethodTest *pThis, RmHalspecOwner *p __nvoc_init_funcTable_SoftwareMethodTest(pThis); } -NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; SoftwareMethodTest *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SoftwareMethodTest), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(SoftwareMethodTest)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SoftwareMethodTest); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -407,16 +415,25 @@ NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest **ppThis, Dynam status = __nvoc_ctor_SoftwareMethodTest(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_SoftwareMethodTest_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_SoftwareMethodTest_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(SoftwareMethodTest)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_sw_test_nvoc.h b/src/nvidia/generated/g_sw_test_nvoc.h index 2aafc6a715..d5272562b7 100644 --- a/src/nvidia/generated/g_sw_test_nvoc.h +++ b/src/nvidia/generated/g_sw_test_nvoc.h @@ -40,11 +40,16 @@ extern "C" { /*! * RM internal class representing NV04_SOFTWARE_TEST */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SW_TEST_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct SoftwareMethodTest { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -71,7 +76,6 @@ struct SoftwareMethodTest { NV_STATUS (*__swtestInternalControlForward__)(struct SoftwareMethodTest *, NvU32, void *, NvU32); NV_STATUS (*__swtestUnmapFrom__)(struct SoftwareMethodTest *, RS_RES_UNMAP_FROM_PARAMS *); void (*__swtestControl_Epilogue__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__swtestControlLookup__)(struct SoftwareMethodTest *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__swtestGetInternalObjectHandle__)(struct SoftwareMethodTest *); NV_STATUS (*__swtestControl__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__swtestUnmap__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -82,6 +86,7 @@ struct SoftwareMethodTest { NV_STATUS (*__swtestUnregisterEvent__)(struct SoftwareMethodTest *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__swtestControlSerialization_Prologue__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__swtestCanCopy__)(struct SoftwareMethodTest *); + NvBool (*__swtestIsPartialUnmapSupported__)(struct SoftwareMethodTest *); void (*__swtestPreDestruct__)(struct SoftwareMethodTest *); NV_STATUS (*__swtestIsDuplicate__)(struct SoftwareMethodTest *, NvHandle, NvBool *); void (*__swtestControlSerialization_Epilogue__)(struct SoftwareMethodTest *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -133,7 +138,6 @@ NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest**, Dynamic*, Nv #define swtestInternalControlForward(pGpuResource, command, pParams, size) swtestInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define swtestUnmapFrom(pResource, pParams) swtestUnmapFrom_DISPATCH(pResource, pParams) #define swtestControl_Epilogue(pResource, pCallContext, pParams) swtestControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define swtestControlLookup(pResource, pParams, ppEntry) swtestControlLookup_DISPATCH(pResource, pParams, ppEntry) #define swtestGetInternalObjectHandle(pGpuResource) swtestGetInternalObjectHandle_DISPATCH(pGpuResource) #define swtestControl(pGpuResource, pCallContext, pParams) swtestControl_DISPATCH(pGpuResource, pCallContext, pParams) #define swtestUnmap(pGpuResource, pCallContext, pCpuMapping) swtestUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -144,6 +148,7 @@ NV_STATUS __nvoc_objCreate_SoftwareMethodTest(SoftwareMethodTest**, Dynamic*, Nv #define swtestUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) swtestUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define swtestControlSerialization_Prologue(pResource, pCallContext, pParams) swtestControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define swtestCanCopy(pResource) swtestCanCopy_DISPATCH(pResource) +#define swtestIsPartialUnmapSupported(pResource) swtestIsPartialUnmapSupported_DISPATCH(pResource) #define swtestPreDestruct(pResource) swtestPreDestruct_DISPATCH(pResource) #define swtestIsDuplicate(pResource, hMemory, pDuplicate) swtestIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define swtestControlSerialization_Epilogue(pResource, pCallContext, pParams) swtestControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -209,10 +214,6 @@ static inline void swtestControl_Epilogue_DISPATCH(struct SoftwareMethodTest *pR pResource->__swtestControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS swtestControlLookup_DISPATCH(struct SoftwareMethodTest *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__swtestControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle swtestGetInternalObjectHandle_DISPATCH(struct SoftwareMethodTest *pGpuResource) { return pGpuResource->__swtestGetInternalObjectHandle__(pGpuResource); } @@ -253,6 +254,10 @@ static inline NvBool swtestCanCopy_DISPATCH(struct SoftwareMethodTest *pResource return pResource->__swtestCanCopy__(pResource); } +static inline NvBool swtestIsPartialUnmapSupported_DISPATCH(struct SoftwareMethodTest *pResource) { + return pResource->__swtestIsPartialUnmapSupported__(pResource); +} + static inline void swtestPreDestruct_DISPATCH(struct SoftwareMethodTest *pResource) { pResource->__swtestPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_swintr_nvoc.c b/src/nvidia/generated/g_swintr_nvoc.c index e837fc36b5..3428b8b5db 100644 --- a/src/nvidia/generated/g_swintr_nvoc.c +++ b/src/nvidia/generated/g_swintr_nvoc.c @@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_SwIntr = /*pExportInfo=*/ &__nvoc_export_info_SwIntr }; -static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[168]) { +static void __nvoc_thunk_SwIntr_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pSwIntr, IntrServiceRecord pRecords[171]) { swintrRegisterIntrService(pGpu, (struct SwIntr *)(((unsigned char *)pSwIntr) - __nvoc_rtti_SwIntr_IntrService.offset), pRecords); } @@ -244,21 +244,26 @@ void __nvoc_init_SwIntr(SwIntr *pThis) { __nvoc_init_funcTable_SwIntr(pThis); } -NV_STATUS __nvoc_objCreate_SwIntr(SwIntr **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_SwIntr(SwIntr **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; SwIntr *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SwIntr), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(SwIntr)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SwIntr); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -273,16 +278,25 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_SwIntr(pThis); if (status != NV_OK) goto __nvoc_objCreate_SwIntr_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_SwIntr_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(SwIntr)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_swintr_nvoc.h b/src/nvidia/generated/g_swintr_nvoc.h index 0ddf289eb6..3b5dcc2587 100644 --- a/src/nvidia/generated/g_swintr_nvoc.h +++ b/src/nvidia/generated/g_swintr_nvoc.h @@ -44,11 +44,16 @@ extern "C" { #include "gpu/eng_state.h" #include "kernel/gpu/intr/intr_service.h" + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SWINTR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct SwIntr { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -125,9 +130,9 @@ NV_STATUS __nvoc_objCreate_SwIntr(SwIntr**, Dynamic*, NvU32); #define swintrStatePostLoad(pGpu, pEngstate, arg0) swintrStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define swintrConstructEngine(pGpu, pEngstate, arg0) swintrConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define swintrIsPresent(pGpu, pEngstate) swintrIsPresent_DISPATCH(pGpu, pEngstate) -void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[168]); +void swintrRegisterIntrService_IMPL(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[171]); -static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[168]) { +static inline void swintrRegisterIntrService_DISPATCH(OBJGPU *pGpu, struct SwIntr *pSwIntr, IntrServiceRecord pRecords[171]) { pSwIntr->__swintrRegisterIntrService__(pGpu, pSwIntr, pRecords); } diff --git a/src/nvidia/generated/g_syncgpuboost_nvoc.c b/src/nvidia/generated/g_syncgpuboost_nvoc.c index c66b76f8b9..79295a18ea 100644 --- a/src/nvidia/generated/g_syncgpuboost_nvoc.c +++ b/src/nvidia/generated/g_syncgpuboost_nvoc.c @@ -116,10 +116,6 @@ static void __nvoc_thunk_RsResource_syncgpuboostAddAdditionalDependants(struct R resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pReference); } -static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmapFrom(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); -} - static NV_STATUS __nvoc_thunk_RmResource_syncgpuboostControlSerialization_Prologue(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); } @@ -136,6 +132,10 @@ static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmap(struct SyncGpuBoost * return resUnmap((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pCallContext, pCpuMapping); } +static NvBool __nvoc_thunk_RsResource_syncgpuboostIsPartialUnmapSupported(struct SyncGpuBoost *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_syncgpuboostPreDestruct(struct SyncGpuBoost *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset)); } @@ -156,8 +156,8 @@ static void __nvoc_thunk_RmResource_syncgpuboostControl_Epilogue(struct SyncGpuB rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostControlLookup(struct SyncGpuBoost *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams, ppEntry); +static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostUnmapFrom(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SyncGpuBoost_RsResource.offset), pParams); } static NV_STATUS __nvoc_thunk_RsResource_syncgpuboostMap(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { @@ -223,8 +223,6 @@ static void __nvoc_init_funcTable_SyncGpuBoost_1(SyncGpuBoost *pThis) { pThis->__syncgpuboostAddAdditionalDependants__ = &__nvoc_thunk_RsResource_syncgpuboostAddAdditionalDependants; - pThis->__syncgpuboostUnmapFrom__ = &__nvoc_thunk_RsResource_syncgpuboostUnmapFrom; - pThis->__syncgpuboostControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_syncgpuboostControlSerialization_Prologue; pThis->__syncgpuboostControl_Prologue__ = &__nvoc_thunk_RmResource_syncgpuboostControl_Prologue; @@ -233,6 +231,8 @@ static void __nvoc_init_funcTable_SyncGpuBoost_1(SyncGpuBoost *pThis) { pThis->__syncgpuboostUnmap__ = &__nvoc_thunk_RsResource_syncgpuboostUnmap; + pThis->__syncgpuboostIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_syncgpuboostIsPartialUnmapSupported; + pThis->__syncgpuboostPreDestruct__ = &__nvoc_thunk_RsResource_syncgpuboostPreDestruct; pThis->__syncgpuboostMapTo__ = &__nvoc_thunk_RsResource_syncgpuboostMapTo; @@ -243,7 +243,7 @@ static void __nvoc_init_funcTable_SyncGpuBoost_1(SyncGpuBoost *pThis) { pThis->__syncgpuboostControl_Epilogue__ = &__nvoc_thunk_RmResource_syncgpuboostControl_Epilogue; - pThis->__syncgpuboostControlLookup__ = &__nvoc_thunk_RsResource_syncgpuboostControlLookup; + pThis->__syncgpuboostUnmapFrom__ = &__nvoc_thunk_RsResource_syncgpuboostUnmapFrom; pThis->__syncgpuboostMap__ = &__nvoc_thunk_RsResource_syncgpuboostMap; @@ -265,21 +265,26 @@ void __nvoc_init_SyncGpuBoost(SyncGpuBoost *pThis) { __nvoc_init_funcTable_SyncGpuBoost(pThis); } -NV_STATUS __nvoc_objCreate_SyncGpuBoost(SyncGpuBoost **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_SyncGpuBoost(SyncGpuBoost **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; SyncGpuBoost *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SyncGpuBoost), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(SyncGpuBoost)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SyncGpuBoost); pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -294,16 +299,25 @@ NV_STATUS __nvoc_objCreate_SyncGpuBoost(SyncGpuBoost **ppThis, Dynamic *pParent, status = __nvoc_ctor_SyncGpuBoost(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_SyncGpuBoost_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_SyncGpuBoost_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(SyncGpuBoost)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_syncgpuboost_nvoc.h b/src/nvidia/generated/g_syncgpuboost_nvoc.h index 5d91bb07bc..e8e8207ae4 100644 --- a/src/nvidia/generated/g_syncgpuboost_nvoc.h +++ b/src/nvidia/generated/g_syncgpuboost_nvoc.h @@ -39,11 +39,16 @@ extern "C" { #include "rmapi/resource.h" #include "class/cl0060.h" + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SYNCGPUBOOST_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct SyncGpuBoost { const struct NVOC_RTTI *__nvoc_rtti; struct RmResource __nvoc_base_RmResource; @@ -60,17 +65,17 @@ struct SyncGpuBoost { NvU32 (*__syncgpuboostGetRefCount__)(struct SyncGpuBoost *); NV_STATUS (*__syncgpuboostControlFilter__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__syncgpuboostAddAdditionalDependants__)(struct RsClient *, struct SyncGpuBoost *, RsResourceRef *); - NV_STATUS (*__syncgpuboostUnmapFrom__)(struct SyncGpuBoost *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__syncgpuboostControlSerialization_Prologue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__syncgpuboostControl_Prologue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__syncgpuboostCanCopy__)(struct SyncGpuBoost *); NV_STATUS (*__syncgpuboostUnmap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RsCpuMapping *); + NvBool (*__syncgpuboostIsPartialUnmapSupported__)(struct SyncGpuBoost *); void (*__syncgpuboostPreDestruct__)(struct SyncGpuBoost *); NV_STATUS (*__syncgpuboostMapTo__)(struct SyncGpuBoost *, RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__syncgpuboostIsDuplicate__)(struct SyncGpuBoost *, NvHandle, NvBool *); void (*__syncgpuboostControlSerialization_Epilogue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); void (*__syncgpuboostControl_Epilogue__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__syncgpuboostControlLookup__)(struct SyncGpuBoost *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); + NV_STATUS (*__syncgpuboostUnmapFrom__)(struct SyncGpuBoost *, RS_RES_UNMAP_FROM_PARAMS *); NV_STATUS (*__syncgpuboostMap__)(struct SyncGpuBoost *, struct CALL_CONTEXT *, RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__syncgpuboostAccessCallback__)(struct SyncGpuBoost *, struct RsClient *, void *, RsAccessRight); NvU32 gpuBoostGroupId; @@ -112,17 +117,17 @@ NV_STATUS __nvoc_objCreate_SyncGpuBoost(SyncGpuBoost**, Dynamic*, NvU32, struct #define syncgpuboostGetRefCount(pResource) syncgpuboostGetRefCount_DISPATCH(pResource) #define syncgpuboostControlFilter(pResource, pCallContext, pParams) syncgpuboostControlFilter_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostAddAdditionalDependants(pClient, pResource, pReference) syncgpuboostAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) -#define syncgpuboostUnmapFrom(pResource, pParams) syncgpuboostUnmapFrom_DISPATCH(pResource, pParams) #define syncgpuboostControlSerialization_Prologue(pResource, pCallContext, pParams) syncgpuboostControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControl_Prologue(pResource, pCallContext, pParams) syncgpuboostControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostCanCopy(pResource) syncgpuboostCanCopy_DISPATCH(pResource) #define syncgpuboostUnmap(pResource, pCallContext, pCpuMapping) syncgpuboostUnmap_DISPATCH(pResource, pCallContext, pCpuMapping) +#define syncgpuboostIsPartialUnmapSupported(pResource) syncgpuboostIsPartialUnmapSupported_DISPATCH(pResource) #define syncgpuboostPreDestruct(pResource) syncgpuboostPreDestruct_DISPATCH(pResource) #define syncgpuboostMapTo(pResource, pParams) syncgpuboostMapTo_DISPATCH(pResource, pParams) #define syncgpuboostIsDuplicate(pResource, hMemory, pDuplicate) syncgpuboostIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define syncgpuboostControlSerialization_Epilogue(pResource, pCallContext, pParams) syncgpuboostControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) #define syncgpuboostControl_Epilogue(pResource, pCallContext, pParams) syncgpuboostControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define syncgpuboostControlLookup(pResource, pParams, ppEntry) syncgpuboostControlLookup_DISPATCH(pResource, pParams, ppEntry) +#define syncgpuboostUnmapFrom(pResource, pParams) syncgpuboostUnmapFrom_DISPATCH(pResource, pParams) #define syncgpuboostMap(pResource, pCallContext, pParams, pCpuMapping) syncgpuboostMap_DISPATCH(pResource, pCallContext, pParams, pCpuMapping) #define syncgpuboostAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) syncgpuboostAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) static inline NvBool syncgpuboostShareCallback_DISPATCH(struct SyncGpuBoost *pResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { @@ -157,10 +162,6 @@ static inline void syncgpuboostAddAdditionalDependants_DISPATCH(struct RsClient pResource->__syncgpuboostAddAdditionalDependants__(pClient, pResource, pReference); } -static inline NV_STATUS syncgpuboostUnmapFrom_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { - return pResource->__syncgpuboostUnmapFrom__(pResource, pParams); -} - static inline NV_STATUS syncgpuboostControlSerialization_Prologue_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pResource->__syncgpuboostControlSerialization_Prologue__(pResource, pCallContext, pParams); } @@ -177,6 +178,10 @@ static inline NV_STATUS syncgpuboostUnmap_DISPATCH(struct SyncGpuBoost *pResourc return pResource->__syncgpuboostUnmap__(pResource, pCallContext, pCpuMapping); } +static inline NvBool syncgpuboostIsPartialUnmapSupported_DISPATCH(struct SyncGpuBoost *pResource) { + return pResource->__syncgpuboostIsPartialUnmapSupported__(pResource); +} + static inline void syncgpuboostPreDestruct_DISPATCH(struct SyncGpuBoost *pResource) { pResource->__syncgpuboostPreDestruct__(pResource); } @@ -197,8 +202,8 @@ static inline void syncgpuboostControl_Epilogue_DISPATCH(struct SyncGpuBoost *pR pResource->__syncgpuboostControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS syncgpuboostControlLookup_DISPATCH(struct SyncGpuBoost *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__syncgpuboostControlLookup__(pResource, pParams, ppEntry); +static inline NV_STATUS syncgpuboostUnmapFrom_DISPATCH(struct SyncGpuBoost *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__syncgpuboostUnmapFrom__(pResource, pParams); } static inline NV_STATUS syncgpuboostMap_DISPATCH(struct SyncGpuBoost *pResource, struct CALL_CONTEXT *pCallContext, RS_CPU_MAP_PARAMS *pParams, RsCpuMapping *pCpuMapping) { diff --git a/src/nvidia/generated/g_system_mem_nvoc.c b/src/nvidia/generated/g_system_mem_nvoc.c index 31fbc7115b..1e9e56a3c0 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.c +++ b/src/nvidia/generated/g_system_mem_nvoc.c @@ -146,10 +146,6 @@ static void __nvoc_thunk_RmResource_sysmemControl_Epilogue(struct SystemMemory * rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_sysmemControlLookup(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_sysmemControl(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), pCallContext, pParams); } @@ -178,6 +174,10 @@ static NvBool __nvoc_thunk_StandardMemory_sysmemCanCopy(struct SystemMemory *pSt return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_SystemMemory_StandardMemory.offset)); } +static NvBool __nvoc_thunk_RsResource_sysmemIsPartialUnmapSupported(struct SystemMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_SystemMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_sysmemIsReady(struct SystemMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_SystemMemory_Memory.offset), bCopyConstructorContext); } @@ -213,12 +213,12 @@ static NvBool __nvoc_thunk_RmResource_sysmemAccessCallback(struct SystemMemory * static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_SystemMemory[] = { { /* [0] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x801u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) sysmemCtrlCmdGetSurfaceNumPhysPages_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x801u) + /*flags=*/ 0x801u, /*accessRight=*/0x0u, /*methodId=*/ 0x3e0102u, /*paramSize=*/ sizeof(NV003E_CTRL_GET_SURFACE_NUM_PHYS_PAGES_PARAMS), @@ -228,12 +228,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_SystemMe #endif }, { /* [1] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x801u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) sysmemCtrlCmdGetSurfacePhysPages_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) - /*flags=*/ 0x0u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x801u) + /*flags=*/ 0x801u, /*accessRight=*/0x0u, /*methodId=*/ 0x3e0103u, /*paramSize=*/ sizeof(NV003E_CTRL_GET_SURFACE_PHYS_PAGES_PARAMS), @@ -283,11 +283,11 @@ NV_STATUS __nvoc_ctor_SystemMemory(SystemMemory *pThis, CALL_CONTEXT * arg_pCall static void __nvoc_init_funcTable_SystemMemory_1(SystemMemory *pThis) { PORT_UNREFERENCED_VARIABLE(pThis); -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x801u) pThis->__sysmemCtrlCmdGetSurfaceNumPhysPages__ = &sysmemCtrlCmdGetSurfaceNumPhysPages_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x801u) pThis->__sysmemCtrlCmdGetSurfacePhysPages__ = &sysmemCtrlCmdGetSurfacePhysPages_IMPL; #endif @@ -313,8 +313,6 @@ static void __nvoc_init_funcTable_SystemMemory_1(SystemMemory *pThis) { pThis->__sysmemControl_Epilogue__ = &__nvoc_thunk_RmResource_sysmemControl_Epilogue; - pThis->__sysmemControlLookup__ = &__nvoc_thunk_RsResource_sysmemControlLookup; - pThis->__sysmemControl__ = &__nvoc_thunk_Memory_sysmemControl; pThis->__sysmemUnmap__ = &__nvoc_thunk_Memory_sysmemUnmap; @@ -329,6 +327,8 @@ static void __nvoc_init_funcTable_SystemMemory_1(SystemMemory *pThis) { pThis->__sysmemCanCopy__ = &__nvoc_thunk_StandardMemory_sysmemCanCopy; + pThis->__sysmemIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_sysmemIsPartialUnmapSupported; + pThis->__sysmemIsReady__ = &__nvoc_thunk_Memory_sysmemIsReady; pThis->__sysmemCheckCopyPermissions__ = &__nvoc_thunk_Memory_sysmemCheckCopyPermissions; @@ -361,21 +361,26 @@ void __nvoc_init_SystemMemory(SystemMemory *pThis) { __nvoc_init_funcTable_SystemMemory(pThis); } -NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; SystemMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(SystemMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(SystemMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_SystemMemory); pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -390,16 +395,25 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory **ppThis, Dynamic *pParent, status = __nvoc_ctor_SystemMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_SystemMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_SystemMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(SystemMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_system_mem_nvoc.h b/src/nvidia/generated/g_system_mem_nvoc.h index 6f6951d1cc..fdf2f5e479 100644 --- a/src/nvidia/generated/g_system_mem_nvoc.h +++ b/src/nvidia/generated/g_system_mem_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -37,11 +37,16 @@ extern "C" { #include "mem_mgr/standard_mem.h" #include "gpu/mem_mgr/heap_base.h" + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SYSTEM_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct SystemMemory { const struct NVOC_RTTI *__nvoc_rtti; struct StandardMemory __nvoc_base_StandardMemory; @@ -65,7 +70,6 @@ struct SystemMemory { NvBool (*__sysmemIsGpuMapAllowed__)(struct SystemMemory *, struct OBJGPU *); NV_STATUS (*__sysmemUnmapFrom__)(struct SystemMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__sysmemControl_Epilogue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__sysmemControlLookup__)(struct SystemMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__sysmemControl__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemUnmap__)(struct SystemMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__sysmemGetMemInterMapParams__)(struct SystemMemory *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -73,6 +77,7 @@ struct SystemMemory { NV_STATUS (*__sysmemControlFilter__)(struct SystemMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__sysmemControlSerialization_Prologue__)(struct SystemMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__sysmemCanCopy__)(struct SystemMemory *); + NvBool (*__sysmemIsPartialUnmapSupported__)(struct SystemMemory *); NV_STATUS (*__sysmemIsReady__)(struct SystemMemory *, NvBool); NV_STATUS (*__sysmemCheckCopyPermissions__)(struct SystemMemory *, struct OBJGPU *, struct Device *); void (*__sysmemPreDestruct__)(struct SystemMemory *); @@ -123,7 +128,6 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory**, Dynamic*, NvU32, CALL_CO #define sysmemIsGpuMapAllowed(pMemory, pGpu) sysmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define sysmemUnmapFrom(pResource, pParams) sysmemUnmapFrom_DISPATCH(pResource, pParams) #define sysmemControl_Epilogue(pResource, pCallContext, pParams) sysmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define sysmemControlLookup(pResource, pParams, ppEntry) sysmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define sysmemControl(pMemory, pCallContext, pParams) sysmemControl_DISPATCH(pMemory, pCallContext, pParams) #define sysmemUnmap(pMemory, pCallContext, pCpuMapping) sysmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define sysmemGetMemInterMapParams(pMemory, pParams) sysmemGetMemInterMapParams_DISPATCH(pMemory, pParams) @@ -131,6 +135,7 @@ NV_STATUS __nvoc_objCreate_SystemMemory(SystemMemory**, Dynamic*, NvU32, CALL_CO #define sysmemControlFilter(pResource, pCallContext, pParams) sysmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define sysmemControlSerialization_Prologue(pResource, pCallContext, pParams) sysmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define sysmemCanCopy(pStandardMemory) sysmemCanCopy_DISPATCH(pStandardMemory) +#define sysmemIsPartialUnmapSupported(pResource) sysmemIsPartialUnmapSupported_DISPATCH(pResource) #define sysmemIsReady(pMemory, bCopyConstructorContext) sysmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define sysmemCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) sysmemCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define sysmemPreDestruct(pResource) sysmemPreDestruct_DISPATCH(pResource) @@ -208,10 +213,6 @@ static inline void sysmemControl_Epilogue_DISPATCH(struct SystemMemory *pResourc pResource->__sysmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS sysmemControlLookup_DISPATCH(struct SystemMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__sysmemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS sysmemControl_DISPATCH(struct SystemMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__sysmemControl__(pMemory, pCallContext, pParams); } @@ -240,6 +241,10 @@ static inline NvBool sysmemCanCopy_DISPATCH(struct SystemMemory *pStandardMemory return pStandardMemory->__sysmemCanCopy__(pStandardMemory); } +static inline NvBool sysmemIsPartialUnmapSupported_DISPATCH(struct SystemMemory *pResource) { + return pResource->__sysmemIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS sysmemIsReady_DISPATCH(struct SystemMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__sysmemIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_system_nvoc.c b/src/nvidia/generated/g_system_nvoc.c index 7660371458..085d007a0d 100644 --- a/src/nvidia/generated/g_system_nvoc.c +++ b/src/nvidia/generated/g_system_nvoc.c @@ -144,21 +144,26 @@ void __nvoc_init_OBJSYS(OBJSYS *pThis) { __nvoc_init_funcTable_OBJSYS(pThis); } -NV_STATUS __nvoc_objCreate_OBJSYS(OBJSYS **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJSYS(OBJSYS **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJSYS *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJSYS), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJSYS)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJSYS); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -173,16 +178,25 @@ NV_STATUS __nvoc_objCreate_OBJSYS(OBJSYS **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_OBJSYS(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJSYS_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJSYS_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJSYS)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_system_nvoc.h b/src/nvidia/generated/g_system_nvoc.h index 15301c988a..3609c19f70 100644 --- a/src/nvidia/generated/g_system_nvoc.h +++ b/src/nvidia/generated/g_system_nvoc.h @@ -47,6 +47,8 @@ extern "C" { #include "os/capability.h" #include "containers/btree.h" +#include "containers/multimap.h" + #define SYS_GET_INSTANCE() (g_pSys) #define SYS_GET_GPUMGR(p) ((p)->pGpuMgr) #define SYS_GET_GSYNCMGR(p) ((p)->pGsyncMgr) @@ -342,11 +344,23 @@ typedef struct NvU32 genRegsMiscIoAdr; } SYS_VGA_POST_STATE; +typedef struct +{ + void *pData; +} SysMemExportCacheEntry; + +MAKE_MULTIMAP(SYS_MEM_EXPORT_CACHE, SysMemExportCacheEntry); + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_SYSTEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJSYS { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -400,11 +414,17 @@ struct OBJSYS { NvU32 binMask; PNODE pMemFilterList; NvBool PDB_PROP_SYS_IS_QSYNC_FW_REVISION_CHECK_DISABLED; + NvBool PDB_PROP_SYS_GPU_LOCK_MIDPATH_ENABLED; NvU64 rmInstanceId; NvU32 currentCid; NvBool bUseDeferredClientListFree; NvU32 clientListDeferredFreeLimit; OS_RM_CAPS *pOsRmCaps; + SYS_MEM_EXPORT_CACHE sysMemExportCache; + PORT_RWLOCK *pSysMemExportModuleLock; + volatile NvU64 sysExportObjectCounter; + NvHandle hSysMemExportClient; + NvBool bSysUuidBasedMemExportSupport; struct OBJGPUMGR *pGpuMgr; struct OBJGSYNCMGR *pGsyncMgr; struct OBJVGPUMGR *pVgpuMgr; @@ -450,6 +470,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJSYS; #define PDB_PROP_SYS_REGISTRY_OVERRIDES_INITIALIZED_BASE_NAME PDB_PROP_SYS_REGISTRY_OVERRIDES_INITIALIZED #define PDB_PROP_SYS_IS_EFI_INIT_BASE_CAST #define PDB_PROP_SYS_IS_EFI_INIT_BASE_NAME PDB_PROP_SYS_IS_EFI_INIT +#define PDB_PROP_SYS_GPU_LOCK_MIDPATH_ENABLED_BASE_CAST +#define PDB_PROP_SYS_GPU_LOCK_MIDPATH_ENABLED_BASE_NAME PDB_PROP_SYS_GPU_LOCK_MIDPATH_ENABLED #define PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS_BASE_CAST #define PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS_BASE_NAME PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS #define PDB_PROP_SYS_POWER_BATTERY_BASE_CAST diff --git a/src/nvidia/generated/g_third_party_p2p_nvoc.c b/src/nvidia/generated/g_third_party_p2p_nvoc.c index 6d5027aee4..2b61586127 100644 --- a/src/nvidia/generated/g_third_party_p2p_nvoc.c +++ b/src/nvidia/generated/g_third_party_p2p_nvoc.c @@ -119,21 +119,26 @@ void __nvoc_init_P2PTokenShare(P2PTokenShare *pThis) { __nvoc_init_funcTable_P2PTokenShare(pThis); } -NV_STATUS __nvoc_objCreate_P2PTokenShare(P2PTokenShare **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_P2PTokenShare(P2PTokenShare **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; P2PTokenShare *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(P2PTokenShare), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(P2PTokenShare)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_P2PTokenShare); pThis->__nvoc_base_RsShared.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -148,16 +153,25 @@ NV_STATUS __nvoc_objCreate_P2PTokenShare(P2PTokenShare **ppThis, Dynamic *pParen status = __nvoc_ctor_P2PTokenShare(pThis); if (status != NV_OK) goto __nvoc_objCreate_P2PTokenShare_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_P2PTokenShare_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_RsShared.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(P2PTokenShare)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; @@ -301,10 +315,6 @@ static void __nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue(struct ThirdPa rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_thirdpartyp2pControlLookup(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle(struct ThirdPartyP2P *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ThirdPartyP2P_GpuResource.offset)); } @@ -337,6 +347,10 @@ static NvBool __nvoc_thunk_RsResource_thirdpartyp2pCanCopy(struct ThirdPartyP2P return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_thirdpartyp2pIsPartialUnmapSupported(struct ThirdPartyP2P *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_thirdpartyp2pPreDestruct(struct ThirdPartyP2P *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ThirdPartyP2P_RsResource.offset)); } @@ -522,8 +536,6 @@ static void __nvoc_init_funcTable_ThirdPartyP2P_1(ThirdPartyP2P *pThis) { pThis->__thirdpartyp2pControl_Epilogue__ = &__nvoc_thunk_RmResource_thirdpartyp2pControl_Epilogue; - pThis->__thirdpartyp2pControlLookup__ = &__nvoc_thunk_RsResource_thirdpartyp2pControlLookup; - pThis->__thirdpartyp2pGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_thirdpartyp2pGetInternalObjectHandle; pThis->__thirdpartyp2pControl__ = &__nvoc_thunk_GpuResource_thirdpartyp2pControl; @@ -540,6 +552,8 @@ static void __nvoc_init_funcTable_ThirdPartyP2P_1(ThirdPartyP2P *pThis) { pThis->__thirdpartyp2pCanCopy__ = &__nvoc_thunk_RsResource_thirdpartyp2pCanCopy; + pThis->__thirdpartyp2pIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_thirdpartyp2pIsPartialUnmapSupported; + pThis->__thirdpartyp2pPreDestruct__ = &__nvoc_thunk_RsResource_thirdpartyp2pPreDestruct; pThis->__thirdpartyp2pIsDuplicate__ = &__nvoc_thunk_RsResource_thirdpartyp2pIsDuplicate; @@ -567,21 +581,26 @@ void __nvoc_init_ThirdPartyP2P(ThirdPartyP2P *pThis) { __nvoc_init_funcTable_ThirdPartyP2P(pThis); } -NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ThirdPartyP2P *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ThirdPartyP2P), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ThirdPartyP2P)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ThirdPartyP2P); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -596,16 +615,25 @@ NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P **ppThis, Dynamic *pParen status = __nvoc_ctor_ThirdPartyP2P(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ThirdPartyP2P_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ThirdPartyP2P_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ThirdPartyP2P)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_third_party_p2p_nvoc.h b/src/nvidia/generated/g_third_party_p2p_nvoc.h index e5f2e5d83f..b81d3d9f72 100644 --- a/src/nvidia/generated/g_third_party_p2p_nvoc.h +++ b/src/nvidia/generated/g_third_party_p2p_nvoc.h @@ -197,11 +197,16 @@ typedef struct ThirdPartyP2P ThirdPartyP2P; #endif /* __nvoc_class_id_ThirdPartyP2P */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_THIRD_PARTY_P2P_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct P2PTokenShare { const struct NVOC_RTTI *__nvoc_rtti; struct RsShared __nvoc_base_RsShared; @@ -248,11 +253,16 @@ void shrp2pDestruct_IMPL(struct P2PTokenShare *pP2PTokenShare); #undef PRIVATE_FIELD + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_THIRD_PARTY_P2P_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ThirdPartyP2P { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -278,7 +288,6 @@ struct ThirdPartyP2P { NV_STATUS (*__thirdpartyp2pInternalControlForward__)(struct ThirdPartyP2P *, NvU32, void *, NvU32); NV_STATUS (*__thirdpartyp2pUnmapFrom__)(struct ThirdPartyP2P *, RS_RES_UNMAP_FROM_PARAMS *); void (*__thirdpartyp2pControl_Epilogue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__thirdpartyp2pControlLookup__)(struct ThirdPartyP2P *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__thirdpartyp2pGetInternalObjectHandle__)(struct ThirdPartyP2P *); NV_STATUS (*__thirdpartyp2pControl__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__thirdpartyp2pUnmap__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -287,6 +296,7 @@ struct ThirdPartyP2P { NV_STATUS (*__thirdpartyp2pControlFilter__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__thirdpartyp2pControlSerialization_Prologue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__thirdpartyp2pCanCopy__)(struct ThirdPartyP2P *); + NvBool (*__thirdpartyp2pIsPartialUnmapSupported__)(struct ThirdPartyP2P *); void (*__thirdpartyp2pPreDestruct__)(struct ThirdPartyP2P *); NV_STATUS (*__thirdpartyp2pIsDuplicate__)(struct ThirdPartyP2P *, NvHandle, NvBool *); void (*__thirdpartyp2pControlSerialization_Epilogue__)(struct ThirdPartyP2P *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -353,7 +363,6 @@ NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P**, Dynamic*, NvU32, struc #define thirdpartyp2pInternalControlForward(pGpuResource, command, pParams, size) thirdpartyp2pInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define thirdpartyp2pUnmapFrom(pResource, pParams) thirdpartyp2pUnmapFrom_DISPATCH(pResource, pParams) #define thirdpartyp2pControl_Epilogue(pResource, pCallContext, pParams) thirdpartyp2pControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define thirdpartyp2pControlLookup(pResource, pParams, ppEntry) thirdpartyp2pControlLookup_DISPATCH(pResource, pParams, ppEntry) #define thirdpartyp2pGetInternalObjectHandle(pGpuResource) thirdpartyp2pGetInternalObjectHandle_DISPATCH(pGpuResource) #define thirdpartyp2pControl(pGpuResource, pCallContext, pParams) thirdpartyp2pControl_DISPATCH(pGpuResource, pCallContext, pParams) #define thirdpartyp2pUnmap(pGpuResource, pCallContext, pCpuMapping) thirdpartyp2pUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -362,6 +371,7 @@ NV_STATUS __nvoc_objCreate_ThirdPartyP2P(ThirdPartyP2P**, Dynamic*, NvU32, struc #define thirdpartyp2pControlFilter(pResource, pCallContext, pParams) thirdpartyp2pControlFilter_DISPATCH(pResource, pCallContext, pParams) #define thirdpartyp2pControlSerialization_Prologue(pResource, pCallContext, pParams) thirdpartyp2pControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define thirdpartyp2pCanCopy(pResource) thirdpartyp2pCanCopy_DISPATCH(pResource) +#define thirdpartyp2pIsPartialUnmapSupported(pResource) thirdpartyp2pIsPartialUnmapSupported_DISPATCH(pResource) #define thirdpartyp2pPreDestruct(pResource) thirdpartyp2pPreDestruct_DISPATCH(pResource) #define thirdpartyp2pIsDuplicate(pResource, hMemory, pDuplicate) thirdpartyp2pIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define thirdpartyp2pControlSerialization_Epilogue(pResource, pCallContext, pParams) thirdpartyp2pControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -441,10 +451,6 @@ static inline void thirdpartyp2pControl_Epilogue_DISPATCH(struct ThirdPartyP2P * pResource->__thirdpartyp2pControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS thirdpartyp2pControlLookup_DISPATCH(struct ThirdPartyP2P *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__thirdpartyp2pControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle thirdpartyp2pGetInternalObjectHandle_DISPATCH(struct ThirdPartyP2P *pGpuResource) { return pGpuResource->__thirdpartyp2pGetInternalObjectHandle__(pGpuResource); } @@ -477,6 +483,10 @@ static inline NvBool thirdpartyp2pCanCopy_DISPATCH(struct ThirdPartyP2P *pResour return pResource->__thirdpartyp2pCanCopy__(pResource); } +static inline NvBool thirdpartyp2pIsPartialUnmapSupported_DISPATCH(struct ThirdPartyP2P *pResource) { + return pResource->__thirdpartyp2pIsPartialUnmapSupported__(pResource); +} + static inline void thirdpartyp2pPreDestruct_DISPATCH(struct ThirdPartyP2P *pResource) { pResource->__thirdpartyp2pPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_timed_sema_nvoc.c b/src/nvidia/generated/g_timed_sema_nvoc.c index 68969079ce..167554140b 100644 --- a/src/nvidia/generated/g_timed_sema_nvoc.c +++ b/src/nvidia/generated/g_timed_sema_nvoc.c @@ -176,10 +176,6 @@ static void __nvoc_thunk_RmResource_tsemaControl_Epilogue(struct TimedSemaSwObje rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_tsemaControlLookup(struct TimedSemaSwObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_tsemaGetInternalObjectHandle(struct TimedSemaSwObject *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_TimedSemaSwObject_GpuResource.offset)); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_tsemaCanCopy(struct TimedSemaSwObject *pRe return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_tsemaIsPartialUnmapSupported(struct TimedSemaSwObject *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_tsemaPreDestruct(struct TimedSemaSwObject *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimedSemaSwObject_RsResource.offset)); } @@ -383,8 +383,6 @@ static void __nvoc_init_funcTable_TimedSemaSwObject_1(TimedSemaSwObject *pThis) pThis->__tsemaControl_Epilogue__ = &__nvoc_thunk_RmResource_tsemaControl_Epilogue; - pThis->__tsemaControlLookup__ = &__nvoc_thunk_RsResource_tsemaControlLookup; - pThis->__tsemaGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_tsemaGetInternalObjectHandle; pThis->__tsemaControl__ = &__nvoc_thunk_GpuResource_tsemaControl; @@ -405,6 +403,8 @@ static void __nvoc_init_funcTable_TimedSemaSwObject_1(TimedSemaSwObject *pThis) pThis->__tsemaCanCopy__ = &__nvoc_thunk_RsResource_tsemaCanCopy; + pThis->__tsemaIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_tsemaIsPartialUnmapSupported; + pThis->__tsemaPreDestruct__ = &__nvoc_thunk_RsResource_tsemaPreDestruct; pThis->__tsemaIsDuplicate__ = &__nvoc_thunk_RsResource_tsemaIsDuplicate; @@ -439,23 +439,31 @@ void __nvoc_init_TimedSemaSwObject(TimedSemaSwObject *pThis, RmHalspecOwner *pRm __nvoc_init_funcTable_TimedSemaSwObject(pThis); } -NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; TimedSemaSwObject *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(TimedSemaSwObject), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(TimedSemaSwObject)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_TimedSemaSwObject); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -473,16 +481,25 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject **ppThis, Dynamic status = __nvoc_ctor_TimedSemaSwObject(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_TimedSemaSwObject_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_TimedSemaSwObject_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(TimedSemaSwObject)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_timed_sema_nvoc.h b/src/nvidia/generated/g_timed_sema_nvoc.h index 8a346c2630..898f8128c6 100644 --- a/src/nvidia/generated/g_timed_sema_nvoc.h +++ b/src/nvidia/generated/g_timed_sema_nvoc.h @@ -52,11 +52,16 @@ MAKE_LIST(GF100_TIMED_SEM_ENTRY_LIST, GF100_TIMED_SEM_ENTRY); /*! * RM internal class representing GF100_TIMED_SEMAPHORE_SW */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_TIMED_SEMA_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct TimedSemaSwObject { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -86,7 +91,6 @@ struct TimedSemaSwObject { NV_STATUS (*__tsemaInternalControlForward__)(struct TimedSemaSwObject *, NvU32, void *, NvU32); NV_STATUS (*__tsemaUnmapFrom__)(struct TimedSemaSwObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__tsemaControl_Epilogue__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__tsemaControlLookup__)(struct TimedSemaSwObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__tsemaGetInternalObjectHandle__)(struct TimedSemaSwObject *); NV_STATUS (*__tsemaControl__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__tsemaUnmap__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -97,6 +101,7 @@ struct TimedSemaSwObject { NV_STATUS (*__tsemaUnregisterEvent__)(struct TimedSemaSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__tsemaControlSerialization_Prologue__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__tsemaCanCopy__)(struct TimedSemaSwObject *); + NvBool (*__tsemaIsPartialUnmapSupported__)(struct TimedSemaSwObject *); void (*__tsemaPreDestruct__)(struct TimedSemaSwObject *); NV_STATUS (*__tsemaIsDuplicate__)(struct TimedSemaSwObject *, NvHandle, NvBool *); void (*__tsemaControlSerialization_Epilogue__)(struct TimedSemaSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -164,7 +169,6 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject**, Dynamic*, NvU3 #define tsemaInternalControlForward(pGpuResource, command, pParams, size) tsemaInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define tsemaUnmapFrom(pResource, pParams) tsemaUnmapFrom_DISPATCH(pResource, pParams) #define tsemaControl_Epilogue(pResource, pCallContext, pParams) tsemaControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define tsemaControlLookup(pResource, pParams, ppEntry) tsemaControlLookup_DISPATCH(pResource, pParams, ppEntry) #define tsemaGetInternalObjectHandle(pGpuResource) tsemaGetInternalObjectHandle_DISPATCH(pGpuResource) #define tsemaControl(pGpuResource, pCallContext, pParams) tsemaControl_DISPATCH(pGpuResource, pCallContext, pParams) #define tsemaUnmap(pGpuResource, pCallContext, pCpuMapping) tsemaUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -175,6 +179,7 @@ NV_STATUS __nvoc_objCreate_TimedSemaSwObject(TimedSemaSwObject**, Dynamic*, NvU3 #define tsemaUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) tsemaUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define tsemaControlSerialization_Prologue(pResource, pCallContext, pParams) tsemaControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define tsemaCanCopy(pResource) tsemaCanCopy_DISPATCH(pResource) +#define tsemaIsPartialUnmapSupported(pResource) tsemaIsPartialUnmapSupported_DISPATCH(pResource) #define tsemaPreDestruct(pResource) tsemaPreDestruct_DISPATCH(pResource) #define tsemaIsDuplicate(pResource, hMemory, pDuplicate) tsemaIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define tsemaControlSerialization_Epilogue(pResource, pCallContext, pParams) tsemaControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -264,10 +269,6 @@ static inline void tsemaControl_Epilogue_DISPATCH(struct TimedSemaSwObject *pRes pResource->__tsemaControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS tsemaControlLookup_DISPATCH(struct TimedSemaSwObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__tsemaControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle tsemaGetInternalObjectHandle_DISPATCH(struct TimedSemaSwObject *pGpuResource) { return pGpuResource->__tsemaGetInternalObjectHandle__(pGpuResource); } @@ -308,6 +309,10 @@ static inline NvBool tsemaCanCopy_DISPATCH(struct TimedSemaSwObject *pResource) return pResource->__tsemaCanCopy__(pResource); } +static inline NvBool tsemaIsPartialUnmapSupported_DISPATCH(struct TimedSemaSwObject *pResource) { + return pResource->__tsemaIsPartialUnmapSupported__(pResource); +} + static inline void tsemaPreDestruct_DISPATCH(struct TimedSemaSwObject *pResource) { pResource->__tsemaPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_tmr_nvoc.c b/src/nvidia/generated/g_tmr_nvoc.c index 564a7904b8..b79c8ae837 100644 --- a/src/nvidia/generated/g_tmr_nvoc.c +++ b/src/nvidia/generated/g_tmr_nvoc.c @@ -163,10 +163,6 @@ static void __nvoc_thunk_RmResource_tmrapiControl_Epilogue(struct TimerApi *pRes rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_tmrapiControlLookup(struct TimerApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_tmrapiGetInternalObjectHandle(struct TimerApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_TimerApi_GpuResource.offset)); } @@ -203,6 +199,10 @@ static NvBool __nvoc_thunk_RsResource_tmrapiCanCopy(struct TimerApi *pResource) return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_tmrapiIsPartialUnmapSupported(struct TimerApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_tmrapiPreDestruct(struct TimerApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_TimerApi_RsResource.offset)); } @@ -333,8 +333,6 @@ static void __nvoc_init_funcTable_TimerApi_1(TimerApi *pThis) { pThis->__tmrapiControl_Epilogue__ = &__nvoc_thunk_RmResource_tmrapiControl_Epilogue; - pThis->__tmrapiControlLookup__ = &__nvoc_thunk_RsResource_tmrapiControlLookup; - pThis->__tmrapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_tmrapiGetInternalObjectHandle; pThis->__tmrapiControl__ = &__nvoc_thunk_GpuResource_tmrapiControl; @@ -353,6 +351,8 @@ static void __nvoc_init_funcTable_TimerApi_1(TimerApi *pThis) { pThis->__tmrapiCanCopy__ = &__nvoc_thunk_RsResource_tmrapiCanCopy; + pThis->__tmrapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_tmrapiIsPartialUnmapSupported; + pThis->__tmrapiPreDestruct__ = &__nvoc_thunk_RsResource_tmrapiPreDestruct; pThis->__tmrapiIsDuplicate__ = &__nvoc_thunk_RsResource_tmrapiIsDuplicate; @@ -388,21 +388,26 @@ void __nvoc_init_TimerApi(TimerApi *pThis) { __nvoc_init_funcTable_TimerApi(pThis); } -NV_STATUS __nvoc_objCreate_TimerApi(TimerApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_TimerApi(TimerApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; TimerApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(TimerApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(TimerApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_TimerApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -417,16 +422,25 @@ NV_STATUS __nvoc_objCreate_TimerApi(TimerApi **ppThis, Dynamic *pParent, NvU32 c status = __nvoc_ctor_TimerApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_TimerApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_TimerApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(TimerApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_tmr_nvoc.h b/src/nvidia/generated/g_tmr_nvoc.h index bcf25d9de0..a599b1b8a3 100644 --- a/src/nvidia/generated/g_tmr_nvoc.h +++ b/src/nvidia/generated/g_tmr_nvoc.h @@ -80,11 +80,16 @@ typedef NV_STATUS (*TIMEPROC_COUNTDOWN)(OBJGPU *, THREAD_STATE_NODE *); /*! * RM internal class representing NV01_TIMER (child of SubDevice) */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_TMR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct TimerApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -111,7 +116,6 @@ struct TimerApi { NV_STATUS (*__tmrapiInternalControlForward__)(struct TimerApi *, NvU32, void *, NvU32); NV_STATUS (*__tmrapiUnmapFrom__)(struct TimerApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__tmrapiControl_Epilogue__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__tmrapiControlLookup__)(struct TimerApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__tmrapiGetInternalObjectHandle__)(struct TimerApi *); NV_STATUS (*__tmrapiControl__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__tmrapiUnmap__)(struct TimerApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -121,6 +125,7 @@ struct TimerApi { NV_STATUS (*__tmrapiUnregisterEvent__)(struct TimerApi *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__tmrapiControlSerialization_Prologue__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__tmrapiCanCopy__)(struct TimerApi *); + NvBool (*__tmrapiIsPartialUnmapSupported__)(struct TimerApi *); void (*__tmrapiPreDestruct__)(struct TimerApi *); NV_STATUS (*__tmrapiIsDuplicate__)(struct TimerApi *, NvHandle, NvBool *); void (*__tmrapiControlSerialization_Epilogue__)(struct TimerApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -172,7 +177,6 @@ NV_STATUS __nvoc_objCreate_TimerApi(TimerApi**, Dynamic*, NvU32, struct CALL_CON #define tmrapiInternalControlForward(pGpuResource, command, pParams, size) tmrapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define tmrapiUnmapFrom(pResource, pParams) tmrapiUnmapFrom_DISPATCH(pResource, pParams) #define tmrapiControl_Epilogue(pResource, pCallContext, pParams) tmrapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define tmrapiControlLookup(pResource, pParams, ppEntry) tmrapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define tmrapiGetInternalObjectHandle(pGpuResource) tmrapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define tmrapiControl(pGpuResource, pCallContext, pParams) tmrapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define tmrapiUnmap(pGpuResource, pCallContext, pCpuMapping) tmrapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -182,6 +186,7 @@ NV_STATUS __nvoc_objCreate_TimerApi(TimerApi**, Dynamic*, NvU32, struct CALL_CON #define tmrapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) tmrapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define tmrapiControlSerialization_Prologue(pResource, pCallContext, pParams) tmrapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define tmrapiCanCopy(pResource) tmrapiCanCopy_DISPATCH(pResource) +#define tmrapiIsPartialUnmapSupported(pResource) tmrapiIsPartialUnmapSupported_DISPATCH(pResource) #define tmrapiPreDestruct(pResource) tmrapiPreDestruct_DISPATCH(pResource) #define tmrapiIsDuplicate(pResource, hMemory, pDuplicate) tmrapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define tmrapiControlSerialization_Epilogue(pResource, pCallContext, pParams) tmrapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -249,10 +254,6 @@ static inline void tmrapiControl_Epilogue_DISPATCH(struct TimerApi *pResource, s pResource->__tmrapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS tmrapiControlLookup_DISPATCH(struct TimerApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__tmrapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle tmrapiGetInternalObjectHandle_DISPATCH(struct TimerApi *pGpuResource) { return pGpuResource->__tmrapiGetInternalObjectHandle__(pGpuResource); } @@ -289,6 +290,10 @@ static inline NvBool tmrapiCanCopy_DISPATCH(struct TimerApi *pResource) { return pResource->__tmrapiCanCopy__(pResource); } +static inline NvBool tmrapiIsPartialUnmapSupported_DISPATCH(struct TimerApi *pResource) { + return pResource->__tmrapiIsPartialUnmapSupported__(pResource); +} + static inline void tmrapiPreDestruct_DISPATCH(struct TimerApi *pResource) { pResource->__tmrapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_traceable_nvoc.h b/src/nvidia/generated/g_traceable_nvoc.h index 039ead032c..fd31119f2f 100644 --- a/src/nvidia/generated/g_traceable_nvoc.h +++ b/src/nvidia/generated/g_traceable_nvoc.h @@ -35,11 +35,16 @@ extern "C" { #include "core/core.h" + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_TRACEABLE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJTRACEABLE { const struct NVOC_RTTI *__nvoc_rtti; struct OBJTRACEABLE *__nvoc_pbase_OBJTRACEABLE; diff --git a/src/nvidia/generated/g_usermode_api_nvoc.c b/src/nvidia/generated/g_usermode_api_nvoc.c index 4beb464cbe..3a46659254 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.c +++ b/src/nvidia/generated/g_usermode_api_nvoc.c @@ -145,10 +145,6 @@ static void __nvoc_thunk_RmResource_usrmodeControl_Epilogue(struct UserModeApi * rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_usrmodeControlLookup(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_usrmodeControl(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), pCallContext, pParams); } @@ -169,6 +165,10 @@ static NV_STATUS __nvoc_thunk_RmResource_usrmodeControlSerialization_Prologue(st return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_usrmodeIsPartialUnmapSupported(struct UserModeApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UserModeApi_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_usrmodeIsReady(struct UserModeApi *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_UserModeApi_Memory.offset), bCopyConstructorContext); } @@ -265,8 +265,6 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis) { pThis->__usrmodeControl_Epilogue__ = &__nvoc_thunk_RmResource_usrmodeControl_Epilogue; - pThis->__usrmodeControlLookup__ = &__nvoc_thunk_RsResource_usrmodeControlLookup; - pThis->__usrmodeControl__ = &__nvoc_thunk_Memory_usrmodeControl; pThis->__usrmodeUnmap__ = &__nvoc_thunk_Memory_usrmodeUnmap; @@ -277,6 +275,8 @@ static void __nvoc_init_funcTable_UserModeApi_1(UserModeApi *pThis) { pThis->__usrmodeControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_usrmodeControlSerialization_Prologue; + pThis->__usrmodeIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_usrmodeIsPartialUnmapSupported; + pThis->__usrmodeIsReady__ = &__nvoc_thunk_Memory_usrmodeIsReady; pThis->__usrmodeCheckCopyPermissions__ = &__nvoc_thunk_Memory_usrmodeCheckCopyPermissions; @@ -308,21 +308,26 @@ void __nvoc_init_UserModeApi(UserModeApi *pThis) { __nvoc_init_funcTable_UserModeApi(pThis); } -NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; UserModeApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UserModeApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(UserModeApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UserModeApi); pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -337,16 +342,25 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi **ppThis, Dynamic *pParent, N status = __nvoc_ctor_UserModeApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_UserModeApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_UserModeApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(UserModeApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_usermode_api_nvoc.h b/src/nvidia/generated/g_usermode_api_nvoc.h index ddda4e4f55..c046d5d4e6 100644 --- a/src/nvidia/generated/g_usermode_api_nvoc.h +++ b/src/nvidia/generated/g_usermode_api_nvoc.h @@ -44,11 +44,16 @@ extern "C" { * because GpuResource can only map regmem, whereas for HOPPER+, we will need to map sysmem with an * effective address space of fbmem if the user requests the GMMU/BAR1 mapping for the VF pages. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_USERMODE_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct UserModeApi { const struct NVOC_RTTI *__nvoc_rtti; struct Memory __nvoc_base_Memory; @@ -71,12 +76,12 @@ struct UserModeApi { NvBool (*__usrmodeIsGpuMapAllowed__)(struct UserModeApi *, struct OBJGPU *); NV_STATUS (*__usrmodeUnmapFrom__)(struct UserModeApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__usrmodeControl_Epilogue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__usrmodeControlLookup__)(struct UserModeApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__usrmodeControl__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeUnmap__)(struct UserModeApi *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__usrmodeGetMemoryMappingDescriptor__)(struct UserModeApi *, MEMORY_DESCRIPTOR **); NV_STATUS (*__usrmodeControlFilter__)(struct UserModeApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__usrmodeControlSerialization_Prologue__)(struct UserModeApi *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__usrmodeIsPartialUnmapSupported__)(struct UserModeApi *); NV_STATUS (*__usrmodeIsReady__)(struct UserModeApi *, NvBool); NV_STATUS (*__usrmodeCheckCopyPermissions__)(struct UserModeApi *, struct OBJGPU *, struct Device *); void (*__usrmodePreDestruct__)(struct UserModeApi *); @@ -129,12 +134,12 @@ NV_STATUS __nvoc_objCreate_UserModeApi(UserModeApi**, Dynamic*, NvU32, CALL_CONT #define usrmodeIsGpuMapAllowed(pMemory, pGpu) usrmodeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define usrmodeUnmapFrom(pResource, pParams) usrmodeUnmapFrom_DISPATCH(pResource, pParams) #define usrmodeControl_Epilogue(pResource, pCallContext, pParams) usrmodeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define usrmodeControlLookup(pResource, pParams, ppEntry) usrmodeControlLookup_DISPATCH(pResource, pParams, ppEntry) #define usrmodeControl(pMemory, pCallContext, pParams) usrmodeControl_DISPATCH(pMemory, pCallContext, pParams) #define usrmodeUnmap(pMemory, pCallContext, pCpuMapping) usrmodeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define usrmodeGetMemoryMappingDescriptor(pMemory, ppMemDesc) usrmodeGetMemoryMappingDescriptor_DISPATCH(pMemory, ppMemDesc) #define usrmodeControlFilter(pResource, pCallContext, pParams) usrmodeControlFilter_DISPATCH(pResource, pCallContext, pParams) #define usrmodeControlSerialization_Prologue(pResource, pCallContext, pParams) usrmodeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define usrmodeIsPartialUnmapSupported(pResource) usrmodeIsPartialUnmapSupported_DISPATCH(pResource) #define usrmodeIsReady(pMemory, bCopyConstructorContext) usrmodeIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define usrmodeCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) usrmodeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define usrmodePreDestruct(pResource) usrmodePreDestruct_DISPATCH(pResource) @@ -198,10 +203,6 @@ static inline void usrmodeControl_Epilogue_DISPATCH(struct UserModeApi *pResourc pResource->__usrmodeControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS usrmodeControlLookup_DISPATCH(struct UserModeApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__usrmodeControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS usrmodeControl_DISPATCH(struct UserModeApi *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__usrmodeControl__(pMemory, pCallContext, pParams); } @@ -222,6 +223,10 @@ static inline NV_STATUS usrmodeControlSerialization_Prologue_DISPATCH(struct Use return pResource->__usrmodeControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool usrmodeIsPartialUnmapSupported_DISPATCH(struct UserModeApi *pResource) { + return pResource->__usrmodeIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS usrmodeIsReady_DISPATCH(struct UserModeApi *pMemory, NvBool bCopyConstructorContext) { return pMemory->__usrmodeIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c index 8d5b503680..5cb7e3c56d 100644 --- a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c +++ b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue(struct UvmChanne rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_uvmchanrtnrControlLookup(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle(struct UvmChannelRetainer *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmChannelRetainer_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_uvmchanrtnrCanCopy(struct UvmChannelRetain return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_uvmchanrtnrIsPartialUnmapSupported(struct UvmChannelRetainer *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_uvmchanrtnrPreDestruct(struct UvmChannelRetainer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmChannelRetainer_RsResource.offset)); } @@ -264,8 +264,6 @@ static void __nvoc_init_funcTable_UvmChannelRetainer_1(UvmChannelRetainer *pThis pThis->__uvmchanrtnrControl_Epilogue__ = &__nvoc_thunk_RmResource_uvmchanrtnrControl_Epilogue; - pThis->__uvmchanrtnrControlLookup__ = &__nvoc_thunk_RsResource_uvmchanrtnrControlLookup; - pThis->__uvmchanrtnrGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_uvmchanrtnrGetInternalObjectHandle; pThis->__uvmchanrtnrControl__ = &__nvoc_thunk_GpuResource_uvmchanrtnrControl; @@ -282,6 +280,8 @@ static void __nvoc_init_funcTable_UvmChannelRetainer_1(UvmChannelRetainer *pThis pThis->__uvmchanrtnrCanCopy__ = &__nvoc_thunk_RsResource_uvmchanrtnrCanCopy; + pThis->__uvmchanrtnrIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_uvmchanrtnrIsPartialUnmapSupported; + pThis->__uvmchanrtnrPreDestruct__ = &__nvoc_thunk_RsResource_uvmchanrtnrPreDestruct; pThis->__uvmchanrtnrIsDuplicate__ = &__nvoc_thunk_RsResource_uvmchanrtnrIsDuplicate; @@ -309,23 +309,31 @@ void __nvoc_init_UvmChannelRetainer(UvmChannelRetainer *pThis, RmHalspecOwner *p __nvoc_init_funcTable_UvmChannelRetainer(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; UvmChannelRetainer *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UvmChannelRetainer), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(UvmChannelRetainer)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UvmChannelRetainer); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -343,16 +351,25 @@ NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer **ppThis, Dynam status = __nvoc_ctor_UvmChannelRetainer(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_UvmChannelRetainer_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_UvmChannelRetainer_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(UvmChannelRetainer)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h index e9d173d22d..f4f3edd5b2 100644 --- a/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h +++ b/src/nvidia/generated/g_uvm_channel_retainer_nvoc.h @@ -54,11 +54,16 @@ typedef struct OBJGPU OBJGPU; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_UVM_CHANNEL_RETAINER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct UvmChannelRetainer { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -79,7 +84,6 @@ struct UvmChannelRetainer { NV_STATUS (*__uvmchanrtnrInternalControlForward__)(struct UvmChannelRetainer *, NvU32, void *, NvU32); NV_STATUS (*__uvmchanrtnrUnmapFrom__)(struct UvmChannelRetainer *, RS_RES_UNMAP_FROM_PARAMS *); void (*__uvmchanrtnrControl_Epilogue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__uvmchanrtnrControlLookup__)(struct UvmChannelRetainer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__uvmchanrtnrGetInternalObjectHandle__)(struct UvmChannelRetainer *); NV_STATUS (*__uvmchanrtnrControl__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmchanrtnrUnmap__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -88,6 +92,7 @@ struct UvmChannelRetainer { NV_STATUS (*__uvmchanrtnrControlFilter__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmchanrtnrControlSerialization_Prologue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__uvmchanrtnrCanCopy__)(struct UvmChannelRetainer *); + NvBool (*__uvmchanrtnrIsPartialUnmapSupported__)(struct UvmChannelRetainer *); void (*__uvmchanrtnrPreDestruct__)(struct UvmChannelRetainer *); NV_STATUS (*__uvmchanrtnrIsDuplicate__)(struct UvmChannelRetainer *, NvHandle, NvBool *); void (*__uvmchanrtnrControlSerialization_Epilogue__)(struct UvmChannelRetainer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -137,7 +142,6 @@ NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer**, Dynamic*, Nv #define uvmchanrtnrInternalControlForward(pGpuResource, command, pParams, size) uvmchanrtnrInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define uvmchanrtnrUnmapFrom(pResource, pParams) uvmchanrtnrUnmapFrom_DISPATCH(pResource, pParams) #define uvmchanrtnrControl_Epilogue(pResource, pCallContext, pParams) uvmchanrtnrControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define uvmchanrtnrControlLookup(pResource, pParams, ppEntry) uvmchanrtnrControlLookup_DISPATCH(pResource, pParams, ppEntry) #define uvmchanrtnrGetInternalObjectHandle(pGpuResource) uvmchanrtnrGetInternalObjectHandle_DISPATCH(pGpuResource) #define uvmchanrtnrControl(pGpuResource, pCallContext, pParams) uvmchanrtnrControl_DISPATCH(pGpuResource, pCallContext, pParams) #define uvmchanrtnrUnmap(pGpuResource, pCallContext, pCpuMapping) uvmchanrtnrUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -146,6 +150,7 @@ NV_STATUS __nvoc_objCreate_UvmChannelRetainer(UvmChannelRetainer**, Dynamic*, Nv #define uvmchanrtnrControlFilter(pResource, pCallContext, pParams) uvmchanrtnrControlFilter_DISPATCH(pResource, pCallContext, pParams) #define uvmchanrtnrControlSerialization_Prologue(pResource, pCallContext, pParams) uvmchanrtnrControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define uvmchanrtnrCanCopy(pResource) uvmchanrtnrCanCopy_DISPATCH(pResource) +#define uvmchanrtnrIsPartialUnmapSupported(pResource) uvmchanrtnrIsPartialUnmapSupported_DISPATCH(pResource) #define uvmchanrtnrPreDestruct(pResource) uvmchanrtnrPreDestruct_DISPATCH(pResource) #define uvmchanrtnrIsDuplicate(pResource, hMemory, pDuplicate) uvmchanrtnrIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define uvmchanrtnrControlSerialization_Epilogue(pResource, pCallContext, pParams) uvmchanrtnrControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -209,10 +214,6 @@ static inline void uvmchanrtnrControl_Epilogue_DISPATCH(struct UvmChannelRetaine pResource->__uvmchanrtnrControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS uvmchanrtnrControlLookup_DISPATCH(struct UvmChannelRetainer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__uvmchanrtnrControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle uvmchanrtnrGetInternalObjectHandle_DISPATCH(struct UvmChannelRetainer *pGpuResource) { return pGpuResource->__uvmchanrtnrGetInternalObjectHandle__(pGpuResource); } @@ -245,6 +246,10 @@ static inline NvBool uvmchanrtnrCanCopy_DISPATCH(struct UvmChannelRetainer *pRes return pResource->__uvmchanrtnrCanCopy__(pResource); } +static inline NvBool uvmchanrtnrIsPartialUnmapSupported_DISPATCH(struct UvmChannelRetainer *pResource) { + return pResource->__uvmchanrtnrIsPartialUnmapSupported__(pResource); +} + static inline void uvmchanrtnrPreDestruct_DISPATCH(struct UvmChannelRetainer *pResource) { pResource->__uvmchanrtnrPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_uvm_nvoc.c b/src/nvidia/generated/g_uvm_nvoc.c index 8b63ff2b09..1d22e29c5b 100644 --- a/src/nvidia/generated/g_uvm_nvoc.c +++ b/src/nvidia/generated/g_uvm_nvoc.c @@ -83,7 +83,7 @@ static NV_STATUS __nvoc_thunk_OBJUVM_engstateStateInitUnlocked(OBJGPU *pGpu, str return uvmStateInitUnlocked(pGpu, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_OBJENGSTATE.offset)); } -static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[168]) { +static void __nvoc_thunk_OBJUVM_intrservRegisterIntrService(OBJGPU *arg0, struct IntrService *pUvm, IntrServiceRecord arg1[171]) { uvmRegisterIntrService(arg0, (struct OBJUVM *)(((unsigned char *)pUvm) - __nvoc_rtti_OBJUVM_IntrService.offset), arg1); } @@ -209,6 +209,26 @@ static void __nvoc_init_funcTable_OBJUVM_1(OBJUVM *pThis, RmHalspecOwner *pRmhal pThis->__uvmStateInitUnlocked__ = &uvmStateInitUnlocked_IMPL; + // Hal function -- uvmAccessCntrBufferUnregister + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__uvmAccessCntrBufferUnregister__ = &uvmAccessCntrBufferUnregister_IMPL; + } + else + { + pThis->__uvmAccessCntrBufferUnregister__ = &uvmAccessCntrBufferUnregister_ac1694; + } + + // Hal function -- uvmAccessCntrBufferRegister + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__uvmAccessCntrBufferRegister__ = &uvmAccessCntrBufferRegister_IMPL; + } + else + { + pThis->__uvmAccessCntrBufferRegister__ = &uvmAccessCntrBufferRegister_ac1694; + } + pThis->__uvmRegisterIntrService__ = &uvmRegisterIntrService_IMPL; pThis->__uvmServiceInterrupt__ = &uvmServiceInterrupt_IMPL; @@ -266,23 +286,31 @@ void __nvoc_init_OBJUVM(OBJUVM *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_OBJUVM(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJUVM *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJUVM), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJUVM)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJUVM); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -300,16 +328,25 @@ NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_OBJUVM(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_OBJUVM_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJUVM_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJUVM)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_uvm_nvoc.h b/src/nvidia/generated/g_uvm_nvoc.h index ca702a102c..f25a182747 100644 --- a/src/nvidia/generated/g_uvm_nvoc.h +++ b/src/nvidia/generated/g_uvm_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -98,11 +98,16 @@ typedef enum typedef struct OBJUVM *POBJUVM; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_UVM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJUVM { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -113,6 +118,8 @@ struct OBJUVM { struct OBJUVM *__nvoc_pbase_OBJUVM; void (*__uvmStateDestroy__)(OBJGPU *, struct OBJUVM *); NV_STATUS (*__uvmStateInitUnlocked__)(OBJGPU *, struct OBJUVM *); + NV_STATUS (*__uvmAccessCntrBufferUnregister__)(OBJGPU *, struct OBJUVM *, NvU32); + NV_STATUS (*__uvmAccessCntrBufferRegister__)(OBJGPU *, struct OBJUVM *, NvU32, NvU32, RmPhysAddr *); void (*__uvmRegisterIntrService__)(OBJGPU *, struct OBJUVM *, IntrServiceRecord *); NvU32 (*__uvmServiceInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceInterruptArguments *); NV_STATUS (*__uvmStateLoad__)(POBJGPU, struct OBJUVM *, NvU32); @@ -168,6 +175,10 @@ NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM**, Dynamic*, NvU32); #define uvmStateDestroy(pGpu, pUvm) uvmStateDestroy_DISPATCH(pGpu, pUvm) #define uvmStateInitUnlocked(pGpu, pUvm) uvmStateInitUnlocked_DISPATCH(pGpu, pUvm) +#define uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister_DISPATCH(arg0, arg1, accessCounterIndex) +#define uvmAccessCntrBufferUnregister_HAL(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister_DISPATCH(arg0, arg1, accessCounterIndex) +#define uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister_DISPATCH(arg0, arg1, accessCounterIndex, arg2, arg3) +#define uvmAccessCntrBufferRegister_HAL(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister_DISPATCH(arg0, arg1, accessCounterIndex, arg2, arg3) #define uvmRegisterIntrService(arg0, pUvm, arg1) uvmRegisterIntrService_DISPATCH(arg0, pUvm, arg1) #define uvmServiceInterrupt(arg0, pUvm, arg1) uvmServiceInterrupt_DISPATCH(arg0, pUvm, arg1) #define uvmStateLoad(pGpu, pEngstate, arg0) uvmStateLoad_DISPATCH(pGpu, pEngstate, arg0) @@ -240,38 +251,6 @@ static inline NV_STATUS uvmDestroyAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM * #define uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) -static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { - return NV_OK; -} - - -#ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrBufferUnregister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { - NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister_ac1694(arg0, arg1, accessCounterIndex) -#endif //__nvoc_uvm_h_disabled - -#define uvmAccessCntrBufferUnregister_HAL(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) - -static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { - return NV_OK; -} - - -#ifdef __nvoc_uvm_h_disabled -static inline NV_STATUS uvmAccessCntrBufferRegister(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { - NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_uvm_h_disabled -#define uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister_ac1694(arg0, arg1, accessCounterIndex, arg2, arg3) -#endif //__nvoc_uvm_h_disabled - -#define uvmAccessCntrBufferRegister_HAL(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) - NV_STATUS uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex); @@ -674,9 +653,29 @@ static inline NV_STATUS uvmStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct OBJUV return pUvm->__uvmStateInitUnlocked__(pGpu, pUvm); } -void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[168]); +NV_STATUS uvmAccessCntrBufferUnregister_IMPL(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex); + +static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { + return NV_OK; +} + +static inline NV_STATUS uvmAccessCntrBufferUnregister_DISPATCH(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) { + return arg1->__uvmAccessCntrBufferUnregister__(arg0, arg1, accessCounterIndex); +} + +NV_STATUS uvmAccessCntrBufferRegister_IMPL(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3); + +static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { + return NV_OK; +} + +static inline NV_STATUS uvmAccessCntrBufferRegister_DISPATCH(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) { + return arg1->__uvmAccessCntrBufferRegister__(arg0, arg1, accessCounterIndex, arg2, arg3); +} + +void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[171]); -static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[168]) { +static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[171]) { pUvm->__uvmRegisterIntrService__(arg0, pUvm, arg1); } diff --git a/src/nvidia/generated/g_uvm_sw_nvoc.c b/src/nvidia/generated/g_uvm_sw_nvoc.c index f8d3622479..281f605c13 100644 --- a/src/nvidia/generated/g_uvm_sw_nvoc.c +++ b/src/nvidia/generated/g_uvm_sw_nvoc.c @@ -176,10 +176,6 @@ static void __nvoc_thunk_RmResource_uvmswControl_Epilogue(struct UvmSwObject *pR rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_uvmswControlLookup(struct UvmSwObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_uvmswGetInternalObjectHandle(struct UvmSwObject *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_UvmSwObject_GpuResource.offset)); } @@ -220,6 +216,10 @@ static NvBool __nvoc_thunk_RsResource_uvmswCanCopy(struct UvmSwObject *pResource return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_uvmswIsPartialUnmapSupported(struct UvmSwObject *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_uvmswPreDestruct(struct UvmSwObject *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_UvmSwObject_RsResource.offset)); } @@ -328,8 +328,6 @@ static void __nvoc_init_funcTable_UvmSwObject_1(UvmSwObject *pThis, RmHalspecOwn pThis->__uvmswControl_Epilogue__ = &__nvoc_thunk_RmResource_uvmswControl_Epilogue; - pThis->__uvmswControlLookup__ = &__nvoc_thunk_RsResource_uvmswControlLookup; - pThis->__uvmswGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_uvmswGetInternalObjectHandle; pThis->__uvmswControl__ = &__nvoc_thunk_GpuResource_uvmswControl; @@ -350,6 +348,8 @@ static void __nvoc_init_funcTable_UvmSwObject_1(UvmSwObject *pThis, RmHalspecOwn pThis->__uvmswCanCopy__ = &__nvoc_thunk_RsResource_uvmswCanCopy; + pThis->__uvmswIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_uvmswIsPartialUnmapSupported; + pThis->__uvmswPreDestruct__ = &__nvoc_thunk_RsResource_uvmswPreDestruct; pThis->__uvmswIsDuplicate__ = &__nvoc_thunk_RsResource_uvmswIsDuplicate; @@ -384,23 +384,31 @@ void __nvoc_init_UvmSwObject(UvmSwObject *pThis, RmHalspecOwner *pRmhalspecowner __nvoc_init_funcTable_UvmSwObject(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; UvmSwObject *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(UvmSwObject), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(UvmSwObject)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_UvmSwObject); pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -418,16 +426,25 @@ NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject **ppThis, Dynamic *pParent, N status = __nvoc_ctor_UvmSwObject(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_UvmSwObject_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_UvmSwObject_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_ChannelDescendant.__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(UvmSwObject)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_uvm_sw_nvoc.h b/src/nvidia/generated/g_uvm_sw_nvoc.h index b3d8ce58a6..2a23ec3e19 100644 --- a/src/nvidia/generated/g_uvm_sw_nvoc.h +++ b/src/nvidia/generated/g_uvm_sw_nvoc.h @@ -40,11 +40,16 @@ extern "C" { /*! * RM internal class representing GP100_UVM_SW */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_UVM_SW_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct UvmSwObject { const struct NVOC_RTTI *__nvoc_rtti; struct ChannelDescendant __nvoc_base_ChannelDescendant; @@ -71,7 +76,6 @@ struct UvmSwObject { NV_STATUS (*__uvmswInternalControlForward__)(struct UvmSwObject *, NvU32, void *, NvU32); NV_STATUS (*__uvmswUnmapFrom__)(struct UvmSwObject *, RS_RES_UNMAP_FROM_PARAMS *); void (*__uvmswControl_Epilogue__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__uvmswControlLookup__)(struct UvmSwObject *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__uvmswGetInternalObjectHandle__)(struct UvmSwObject *); NV_STATUS (*__uvmswControl__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__uvmswUnmap__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -82,6 +86,7 @@ struct UvmSwObject { NV_STATUS (*__uvmswUnregisterEvent__)(struct UvmSwObject *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__uvmswControlSerialization_Prologue__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__uvmswCanCopy__)(struct UvmSwObject *); + NvBool (*__uvmswIsPartialUnmapSupported__)(struct UvmSwObject *); void (*__uvmswPreDestruct__)(struct UvmSwObject *); NV_STATUS (*__uvmswIsDuplicate__)(struct UvmSwObject *, NvHandle, NvBool *); void (*__uvmswControlSerialization_Epilogue__)(struct UvmSwObject *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -139,7 +144,6 @@ NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject**, Dynamic*, NvU32, struct CA #define uvmswInternalControlForward(pGpuResource, command, pParams, size) uvmswInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define uvmswUnmapFrom(pResource, pParams) uvmswUnmapFrom_DISPATCH(pResource, pParams) #define uvmswControl_Epilogue(pResource, pCallContext, pParams) uvmswControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define uvmswControlLookup(pResource, pParams, ppEntry) uvmswControlLookup_DISPATCH(pResource, pParams, ppEntry) #define uvmswGetInternalObjectHandle(pGpuResource) uvmswGetInternalObjectHandle_DISPATCH(pGpuResource) #define uvmswControl(pGpuResource, pCallContext, pParams) uvmswControl_DISPATCH(pGpuResource, pCallContext, pParams) #define uvmswUnmap(pGpuResource, pCallContext, pCpuMapping) uvmswUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -150,6 +154,7 @@ NV_STATUS __nvoc_objCreate_UvmSwObject(UvmSwObject**, Dynamic*, NvU32, struct CA #define uvmswUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) uvmswUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define uvmswControlSerialization_Prologue(pResource, pCallContext, pParams) uvmswControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define uvmswCanCopy(pResource) uvmswCanCopy_DISPATCH(pResource) +#define uvmswIsPartialUnmapSupported(pResource) uvmswIsPartialUnmapSupported_DISPATCH(pResource) #define uvmswPreDestruct(pResource) uvmswPreDestruct_DISPATCH(pResource) #define uvmswIsDuplicate(pResource, hMemory, pDuplicate) uvmswIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define uvmswControlSerialization_Epilogue(pResource, pCallContext, pParams) uvmswControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -217,10 +222,6 @@ static inline void uvmswControl_Epilogue_DISPATCH(struct UvmSwObject *pResource, pResource->__uvmswControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS uvmswControlLookup_DISPATCH(struct UvmSwObject *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__uvmswControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle uvmswGetInternalObjectHandle_DISPATCH(struct UvmSwObject *pGpuResource) { return pGpuResource->__uvmswGetInternalObjectHandle__(pGpuResource); } @@ -261,6 +262,10 @@ static inline NvBool uvmswCanCopy_DISPATCH(struct UvmSwObject *pResource) { return pResource->__uvmswCanCopy__(pResource); } +static inline NvBool uvmswIsPartialUnmapSupported_DISPATCH(struct UvmSwObject *pResource) { + return pResource->__uvmswIsPartialUnmapSupported__(pResource); +} + static inline void uvmswPreDestruct_DISPATCH(struct UvmSwObject *pResource) { pResource->__uvmswPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.c b/src/nvidia/generated/g_vaspace_api_nvoc.c index 1c37028df5..cf80206eec 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.c +++ b/src/nvidia/generated/g_vaspace_api_nvoc.c @@ -141,10 +141,6 @@ static void __nvoc_thunk_RmResource_vaspaceapiControl_Epilogue(struct VaSpaceApi rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vaspaceapiControlLookup(struct VaSpaceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle(struct VaSpaceApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VaSpaceApi_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NV_STATUS __nvoc_thunk_RmResource_vaspaceapiControlSerialization_Prologue return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RmResource.offset), pCallContext, pParams); } +static NvBool __nvoc_thunk_RsResource_vaspaceapiIsPartialUnmapSupported(struct VaSpaceApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_vaspaceapiPreDestruct(struct VaSpaceApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VaSpaceApi_RsResource.offset)); } @@ -381,8 +381,6 @@ static void __nvoc_init_funcTable_VaSpaceApi_1(VaSpaceApi *pThis) { pThis->__vaspaceapiControl_Epilogue__ = &__nvoc_thunk_RmResource_vaspaceapiControl_Epilogue; - pThis->__vaspaceapiControlLookup__ = &__nvoc_thunk_RsResource_vaspaceapiControlLookup; - pThis->__vaspaceapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vaspaceapiGetInternalObjectHandle; pThis->__vaspaceapiControl__ = &__nvoc_thunk_GpuResource_vaspaceapiControl; @@ -397,6 +395,8 @@ static void __nvoc_init_funcTable_VaSpaceApi_1(VaSpaceApi *pThis) { pThis->__vaspaceapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vaspaceapiControlSerialization_Prologue; + pThis->__vaspaceapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_vaspaceapiIsPartialUnmapSupported; + pThis->__vaspaceapiPreDestruct__ = &__nvoc_thunk_RsResource_vaspaceapiPreDestruct; pThis->__vaspaceapiIsDuplicate__ = &__nvoc_thunk_RsResource_vaspaceapiIsDuplicate; @@ -424,21 +424,26 @@ void __nvoc_init_VaSpaceApi(VaSpaceApi *pThis) { __nvoc_init_funcTable_VaSpaceApi(pThis); } -NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; VaSpaceApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VaSpaceApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(VaSpaceApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VaSpaceApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -453,16 +458,25 @@ NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi **ppThis, Dynamic *pParent, NvU status = __nvoc_ctor_VaSpaceApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_VaSpaceApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_VaSpaceApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(VaSpaceApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_vaspace_api_nvoc.h b/src/nvidia/generated/g_vaspace_api_nvoc.h index 2282100057..9d5357c32a 100644 --- a/src/nvidia/generated/g_vaspace_api_nvoc.h +++ b/src/nvidia/generated/g_vaspace_api_nvoc.h @@ -53,11 +53,16 @@ typedef enum VASPACEAPI_MANAGE_PAGE_LEVELS_TRIM, } VASPACEAPI_MANAGE_PAGE_LEVELS_ACTION; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VASPACE_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct VaSpaceApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -85,7 +90,6 @@ struct VaSpaceApi { NV_STATUS (*__vaspaceapiInternalControlForward__)(struct VaSpaceApi *, NvU32, void *, NvU32); NV_STATUS (*__vaspaceapiUnmapFrom__)(struct VaSpaceApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__vaspaceapiControl_Epilogue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vaspaceapiControlLookup__)(struct VaSpaceApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__vaspaceapiGetInternalObjectHandle__)(struct VaSpaceApi *); NV_STATUS (*__vaspaceapiControl__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vaspaceapiUnmap__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -93,6 +97,7 @@ struct VaSpaceApi { NV_STATUS (*__vaspaceapiGetMemoryMappingDescriptor__)(struct VaSpaceApi *, struct MEMORY_DESCRIPTOR **); NV_STATUS (*__vaspaceapiControlFilter__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vaspaceapiControlSerialization_Prologue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__vaspaceapiIsPartialUnmapSupported__)(struct VaSpaceApi *); void (*__vaspaceapiPreDestruct__)(struct VaSpaceApi *); NV_STATUS (*__vaspaceapiIsDuplicate__)(struct VaSpaceApi *, NvHandle, NvBool *); void (*__vaspaceapiControlSerialization_Epilogue__)(struct VaSpaceApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -148,7 +153,6 @@ NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi**, Dynamic*, NvU32, struct CALL #define vaspaceapiInternalControlForward(pGpuResource, command, pParams, size) vaspaceapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define vaspaceapiUnmapFrom(pResource, pParams) vaspaceapiUnmapFrom_DISPATCH(pResource, pParams) #define vaspaceapiControl_Epilogue(pResource, pCallContext, pParams) vaspaceapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vaspaceapiControlLookup(pResource, pParams, ppEntry) vaspaceapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vaspaceapiGetInternalObjectHandle(pGpuResource) vaspaceapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define vaspaceapiControl(pGpuResource, pCallContext, pParams) vaspaceapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define vaspaceapiUnmap(pGpuResource, pCallContext, pCpuMapping) vaspaceapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -156,6 +160,7 @@ NV_STATUS __nvoc_objCreate_VaSpaceApi(VaSpaceApi**, Dynamic*, NvU32, struct CALL #define vaspaceapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vaspaceapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) #define vaspaceapiControlFilter(pResource, pCallContext, pParams) vaspaceapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define vaspaceapiControlSerialization_Prologue(pResource, pCallContext, pParams) vaspaceapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vaspaceapiIsPartialUnmapSupported(pResource) vaspaceapiIsPartialUnmapSupported_DISPATCH(pResource) #define vaspaceapiPreDestruct(pResource) vaspaceapiPreDestruct_DISPATCH(pResource) #define vaspaceapiIsDuplicate(pResource, hMemory, pDuplicate) vaspaceapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define vaspaceapiControlSerialization_Epilogue(pResource, pCallContext, pParams) vaspaceapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -247,10 +252,6 @@ static inline void vaspaceapiControl_Epilogue_DISPATCH(struct VaSpaceApi *pResou pResource->__vaspaceapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vaspaceapiControlLookup_DISPATCH(struct VaSpaceApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vaspaceapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle vaspaceapiGetInternalObjectHandle_DISPATCH(struct VaSpaceApi *pGpuResource) { return pGpuResource->__vaspaceapiGetInternalObjectHandle__(pGpuResource); } @@ -279,6 +280,10 @@ static inline NV_STATUS vaspaceapiControlSerialization_Prologue_DISPATCH(struct return pResource->__vaspaceapiControlSerialization_Prologue__(pResource, pCallContext, pParams); } +static inline NvBool vaspaceapiIsPartialUnmapSupported_DISPATCH(struct VaSpaceApi *pResource) { + return pResource->__vaspaceapiIsPartialUnmapSupported__(pResource); +} + static inline void vaspaceapiPreDestruct_DISPATCH(struct VaSpaceApi *pResource) { pResource->__vaspaceapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_vaspace_nvoc.h b/src/nvidia/generated/g_vaspace_nvoc.h index 2613cc0cb0..de61b41a60 100644 --- a/src/nvidia/generated/g_vaspace_nvoc.h +++ b/src/nvidia/generated/g_vaspace_nvoc.h @@ -240,11 +240,16 @@ typedef enum /*! * Abstract base class of an RM-managed virtual address space. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VASPACE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJVASPACE { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; @@ -263,7 +268,7 @@ struct OBJVASPACE { void (*__vaspaceUnmap__)(struct OBJVASPACE *, struct OBJGPU *, const NvU64, const NvU64); NV_STATUS (*__vaspaceReserveMempool__)(struct OBJVASPACE *, struct OBJGPU *, struct Device *, NvU64, NvU64, NvU32); struct OBJEHEAP *(*__vaspaceGetHeap__)(struct OBJVASPACE *); - NvU64 (*__vaspaceGetMapPageSize__)(struct OBJVASPACE *, struct OBJGPU *, EMEMBLOCK *); + NvU64 (*__vaspaceGetMapPageSize__)(struct OBJVASPACE *, struct OBJGPU *, struct EMEMBLOCK *); NvU64 (*__vaspaceGetBigPageSize__)(struct OBJVASPACE *); NvBool (*__vaspaceIsMirrored__)(struct OBJVASPACE *); NvBool (*__vaspaceIsFaultCapable__)(struct OBJVASPACE *); @@ -427,12 +432,12 @@ static inline struct OBJEHEAP *vaspaceGetHeap_DISPATCH(struct OBJVASPACE *pVAS) return pVAS->__vaspaceGetHeap__(pVAS); } -static inline NvU64 vaspaceGetMapPageSize_07238a(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 vaspaceGetMapPageSize_07238a(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock) { NV_ASSERT_PRECOMP(((NvBool)(0 != 0))); return 0U; } -static inline NvU64 vaspaceGetMapPageSize_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, EMEMBLOCK *pMemBlock) { +static inline NvU64 vaspaceGetMapPageSize_DISPATCH(struct OBJVASPACE *pVAS, struct OBJGPU *pGpu, struct EMEMBLOCK *pMemBlock) { return pVAS->__vaspaceGetMapPageSize__(pVAS, pGpu, pMemBlock); } diff --git a/src/nvidia/generated/g_vblank_callback_nvoc.c b/src/nvidia/generated/g_vblank_callback_nvoc.c index 302c1b9b38..1150e3bc1d 100644 --- a/src/nvidia/generated/g_vblank_callback_nvoc.c +++ b/src/nvidia/generated/g_vblank_callback_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_vblcbControl_Epilogue(struct VblankCallback rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vblcbControlLookup(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle(struct VblankCallback *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VblankCallback_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_vblcbCanCopy(struct VblankCallback *pResou return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_vblcbIsPartialUnmapSupported(struct VblankCallback *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_vblcbPreDestruct(struct VblankCallback *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VblankCallback_RsResource.offset)); } @@ -282,8 +282,6 @@ static void __nvoc_init_funcTable_VblankCallback_1(VblankCallback *pThis) { pThis->__vblcbControl_Epilogue__ = &__nvoc_thunk_RmResource_vblcbControl_Epilogue; - pThis->__vblcbControlLookup__ = &__nvoc_thunk_RsResource_vblcbControlLookup; - pThis->__vblcbGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vblcbGetInternalObjectHandle; pThis->__vblcbControl__ = &__nvoc_thunk_GpuResource_vblcbControl; @@ -300,6 +298,8 @@ static void __nvoc_init_funcTable_VblankCallback_1(VblankCallback *pThis) { pThis->__vblcbCanCopy__ = &__nvoc_thunk_RsResource_vblcbCanCopy; + pThis->__vblcbIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_vblcbIsPartialUnmapSupported; + pThis->__vblcbPreDestruct__ = &__nvoc_thunk_RsResource_vblcbPreDestruct; pThis->__vblcbIsDuplicate__ = &__nvoc_thunk_RsResource_vblcbIsDuplicate; @@ -327,21 +327,26 @@ void __nvoc_init_VblankCallback(VblankCallback *pThis) { __nvoc_init_funcTable_VblankCallback(pThis); } -NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; VblankCallback *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VblankCallback), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(VblankCallback)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VblankCallback); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -356,16 +361,25 @@ NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback **ppThis, Dynamic *pPar status = __nvoc_ctor_VblankCallback(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_VblankCallback_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_VblankCallback_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(VblankCallback)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_vblank_callback_nvoc.h b/src/nvidia/generated/g_vblank_callback_nvoc.h index 76c3b9aa3a..fb7290c072 100644 --- a/src/nvidia/generated/g_vblank_callback_nvoc.h +++ b/src/nvidia/generated/g_vblank_callback_nvoc.h @@ -48,11 +48,16 @@ extern "C" { /*! * RM internal class representing NV9010_VBLANK_CALLBACK */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VBLANK_CALLBACK_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct VblankCallback { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -74,7 +79,6 @@ struct VblankCallback { NV_STATUS (*__vblcbInternalControlForward__)(struct VblankCallback *, NvU32, void *, NvU32); NV_STATUS (*__vblcbUnmapFrom__)(struct VblankCallback *, RS_RES_UNMAP_FROM_PARAMS *); void (*__vblcbControl_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vblcbControlLookup__)(struct VblankCallback *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__vblcbGetInternalObjectHandle__)(struct VblankCallback *); NV_STATUS (*__vblcbControl__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbUnmap__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -83,6 +87,7 @@ struct VblankCallback { NV_STATUS (*__vblcbControlFilter__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vblcbControlSerialization_Prologue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vblcbCanCopy__)(struct VblankCallback *); + NvBool (*__vblcbIsPartialUnmapSupported__)(struct VblankCallback *); void (*__vblcbPreDestruct__)(struct VblankCallback *); NV_STATUS (*__vblcbIsDuplicate__)(struct VblankCallback *, NvHandle, NvBool *); void (*__vblcbControlSerialization_Epilogue__)(struct VblankCallback *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -135,7 +140,6 @@ NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback**, Dynamic*, NvU32, CAL #define vblcbInternalControlForward(pGpuResource, command, pParams, size) vblcbInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define vblcbUnmapFrom(pResource, pParams) vblcbUnmapFrom_DISPATCH(pResource, pParams) #define vblcbControl_Epilogue(pResource, pCallContext, pParams) vblcbControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vblcbControlLookup(pResource, pParams, ppEntry) vblcbControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vblcbGetInternalObjectHandle(pGpuResource) vblcbGetInternalObjectHandle_DISPATCH(pGpuResource) #define vblcbControl(pGpuResource, pCallContext, pParams) vblcbControl_DISPATCH(pGpuResource, pCallContext, pParams) #define vblcbUnmap(pGpuResource, pCallContext, pCpuMapping) vblcbUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -144,6 +148,7 @@ NV_STATUS __nvoc_objCreate_VblankCallback(VblankCallback**, Dynamic*, NvU32, CAL #define vblcbControlFilter(pResource, pCallContext, pParams) vblcbControlFilter_DISPATCH(pResource, pCallContext, pParams) #define vblcbControlSerialization_Prologue(pResource, pCallContext, pParams) vblcbControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vblcbCanCopy(pResource) vblcbCanCopy_DISPATCH(pResource) +#define vblcbIsPartialUnmapSupported(pResource) vblcbIsPartialUnmapSupported_DISPATCH(pResource) #define vblcbPreDestruct(pResource) vblcbPreDestruct_DISPATCH(pResource) #define vblcbIsDuplicate(pResource, hMemory, pDuplicate) vblcbIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define vblcbControlSerialization_Epilogue(pResource, pCallContext, pParams) vblcbControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -199,10 +204,6 @@ static inline void vblcbControl_Epilogue_DISPATCH(struct VblankCallback *pResour pResource->__vblcbControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vblcbControlLookup_DISPATCH(struct VblankCallback *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vblcbControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle vblcbGetInternalObjectHandle_DISPATCH(struct VblankCallback *pGpuResource) { return pGpuResource->__vblcbGetInternalObjectHandle__(pGpuResource); } @@ -235,6 +236,10 @@ static inline NvBool vblcbCanCopy_DISPATCH(struct VblankCallback *pResource) { return pResource->__vblcbCanCopy__(pResource); } +static inline NvBool vblcbIsPartialUnmapSupported_DISPATCH(struct VblankCallback *pResource) { + return pResource->__vblcbIsPartialUnmapSupported__(pResource); +} + static inline void vblcbPreDestruct_DISPATCH(struct VblankCallback *pResource) { pResource->__vblcbPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_vgpuapi_nvoc.c b/src/nvidia/generated/g_vgpuapi_nvoc.c new file mode 100644 index 0000000000..499e944d6e --- /dev/null +++ b/src/nvidia/generated/g_vgpuapi_nvoc.c @@ -0,0 +1,435 @@ +#define NVOC_VGPUAPI_H_PRIVATE_ACCESS_ALLOWED +#include "nvoc/runtime.h" +#include "nvoc/rtti.h" +#include "nvtypes.h" +#include "nvport/nvport.h" +#include "nvport/inline/util_valist.h" +#include "utils/nvassert.h" +#include "g_vgpuapi_nvoc.h" + +#ifdef DEBUG +char __nvoc_class_id_uniqueness_check_0x7774f5 = 1; +#endif + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_VgpuApi; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_Object; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RsResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResourceCommon; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_RmResource; + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_GpuResource; + +void __nvoc_init_VgpuApi(VgpuApi*); +void __nvoc_init_funcTable_VgpuApi(VgpuApi*); +NV_STATUS __nvoc_ctor_VgpuApi(VgpuApi*, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +void __nvoc_init_dataField_VgpuApi(VgpuApi*); +void __nvoc_dtor_VgpuApi(VgpuApi*); +extern const struct NVOC_EXPORT_INFO __nvoc_export_info_VgpuApi; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuApi_VgpuApi = { + /*pClassDef=*/ &__nvoc_class_def_VgpuApi, + /*dtor=*/ (NVOC_DYNAMIC_DTOR) &__nvoc_dtor_VgpuApi, + /*offset=*/ 0, +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuApi_Object = { + /*pClassDef=*/ &__nvoc_class_def_Object, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuApi_RsResource = { + /*pClassDef=*/ &__nvoc_class_def_RsResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuApi_RmResourceCommon = { + /*pClassDef=*/ &__nvoc_class_def_RmResourceCommon, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuApi, __nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuApi_RmResource = { + /*pClassDef=*/ &__nvoc_class_def_RmResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuApi, __nvoc_base_GpuResource.__nvoc_base_RmResource), +}; + +static const struct NVOC_RTTI __nvoc_rtti_VgpuApi_GpuResource = { + /*pClassDef=*/ &__nvoc_class_def_GpuResource, + /*dtor=*/ &__nvoc_destructFromBase, + /*offset=*/ NV_OFFSETOF(VgpuApi, __nvoc_base_GpuResource), +}; + +static const struct NVOC_CASTINFO __nvoc_castinfo_VgpuApi = { + /*numRelatives=*/ 6, + /*relatives=*/ { + &__nvoc_rtti_VgpuApi_VgpuApi, + &__nvoc_rtti_VgpuApi_GpuResource, + &__nvoc_rtti_VgpuApi_RmResource, + &__nvoc_rtti_VgpuApi_RmResourceCommon, + &__nvoc_rtti_VgpuApi_RsResource, + &__nvoc_rtti_VgpuApi_Object, + }, +}; + +const struct NVOC_CLASS_DEF __nvoc_class_def_VgpuApi = +{ + /*classInfo=*/ { + /*size=*/ sizeof(VgpuApi), + /*classId=*/ classId(VgpuApi), + /*providerId=*/ &__nvoc_rtti_provider, +#if NV_PRINTF_STRINGS_ALLOWED + /*name=*/ "VgpuApi", +#endif + }, + /*objCreatefn=*/ (NVOC_DYNAMIC_OBJ_CREATE) &__nvoc_objCreateDynamic_VgpuApi, + /*pCastInfo=*/ &__nvoc_castinfo_VgpuApi, + /*pExportInfo=*/ &__nvoc_export_info_VgpuApi +}; + +static NvBool __nvoc_thunk_GpuResource_vgpuapiShareCallback(struct VgpuApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return gpuresShareCallback((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuApi_GpuResource.offset), pInvokingClient, pParentRef, pSharePolicy); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuapiCheckMemInterUnmap(struct VgpuApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return rmresCheckMemInterUnmap((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuApi_RmResource.offset), bSubdeviceHandleProvided); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuapiMapTo(struct VgpuApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return resMapTo((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuapiGetMapAddrSpace(struct VgpuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return gpuresGetMapAddrSpace((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuApi_GpuResource.offset), pCallContext, mapFlags, pAddrSpace); +} + +static NvU32 __nvoc_thunk_RsResource_vgpuapiGetRefCount(struct VgpuApi *pResource) { + return resGetRefCount((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vgpuapiAddAdditionalDependants(struct RsClient *pClient, struct VgpuApi *pResource, RsResourceRef *pReference) { + resAddAdditionalDependants(pClient, (struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset), pReference); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuapiControl_Prologue(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControl_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuapiGetRegBaseOffsetAndSize(struct VgpuApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return gpuresGetRegBaseOffsetAndSize((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuApi_GpuResource.offset), pGpu, pOffset, pSize); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuapiInternalControlForward(struct VgpuApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return gpuresInternalControlForward((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuApi_GpuResource.offset), command, pParams, size); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuapiUnmapFrom(struct VgpuApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return resUnmapFrom((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset), pParams); +} + +static void __nvoc_thunk_RmResource_vgpuapiControl_Epilogue(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RmResource.offset), pCallContext, pParams); +} + +static NvHandle __nvoc_thunk_GpuResource_vgpuapiGetInternalObjectHandle(struct VgpuApi *pGpuResource) { + return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuApi_GpuResource.offset)); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuapiControl(struct VgpuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return gpuresControl((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuApi_GpuResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuapiUnmap(struct VgpuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return gpuresUnmap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuApi_GpuResource.offset), pCallContext, pCpuMapping); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuapiGetMemInterMapParams(struct VgpuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return rmresGetMemInterMapParams((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuApi_RmResource.offset), pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuapiGetMemoryMappingDescriptor(struct VgpuApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return rmresGetMemoryMappingDescriptor((struct RmResource *)(((unsigned char *)pRmResource) + __nvoc_rtti_VgpuApi_RmResource.offset), ppMemDesc); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuapiControlFilter(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return resControlFilter((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_RmResource_vgpuapiControlSerialization_Prologue(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return rmresControlSerialization_Prologue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RmResource.offset), pCallContext, pParams); +} + +static NvBool __nvoc_thunk_RsResource_vgpuapiCanCopy(struct VgpuApi *pResource) { + return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset)); +} + +static NvBool __nvoc_thunk_RsResource_vgpuapiIsPartialUnmapSupported(struct VgpuApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset)); +} + +static void __nvoc_thunk_RsResource_vgpuapiPreDestruct(struct VgpuApi *pResource) { + resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset)); +} + +static NV_STATUS __nvoc_thunk_RsResource_vgpuapiIsDuplicate(struct VgpuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return resIsDuplicate((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RsResource.offset), hMemory, pDuplicate); +} + +static void __nvoc_thunk_RmResource_vgpuapiControlSerialization_Epilogue(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + rmresControlSerialization_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RmResource.offset), pCallContext, pParams); +} + +static NV_STATUS __nvoc_thunk_GpuResource_vgpuapiMap(struct VgpuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return gpuresMap((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuApi_GpuResource.offset), pCallContext, pParams, pCpuMapping); +} + +static NvBool __nvoc_thunk_RmResource_vgpuapiAccessCallback(struct VgpuApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return rmresAccessCallback((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuApi_RmResource.offset), pInvokingClient, pAllocParams, accessRight); +} + +#if !defined(NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG) +#define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(x) (0) +#endif + +static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VgpuApi[] = +{ + { /* [0] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0800103u, + /*paramSize=*/ sizeof(NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties" +#endif + }, + { /* [1] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuapiCtrlCmdVgpuDisplayCleanupSurface_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0800104u, + /*paramSize=*/ sizeof(NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuapiCtrlCmdVgpuDisplayCleanupSurface" +#endif + }, + { /* [2] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuapiCtrlCmdVGpuGetConfig_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa0800301u, + /*paramSize=*/ sizeof(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuapiCtrlCmdVGpuGetConfig" +#endif + }, + +}; + +const struct NVOC_EXPORT_INFO __nvoc_export_info_VgpuApi = +{ + /*numEntries=*/ 3, + /*pExportEntries=*/ __nvoc_exported_method_def_VgpuApi +}; + +void __nvoc_dtor_GpuResource(GpuResource*); +void __nvoc_dtor_VgpuApi(VgpuApi *pThis) { + __nvoc_vgpuapiDestruct(pThis); + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); + PORT_UNREFERENCED_VARIABLE(pThis); +} + +void __nvoc_init_dataField_VgpuApi(VgpuApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); +} + +NV_STATUS __nvoc_ctor_GpuResource(GpuResource* , struct CALL_CONTEXT *, struct RS_RES_ALLOC_PARAMS_INTERNAL *); +NV_STATUS __nvoc_ctor_VgpuApi(VgpuApi *pThis, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { + NV_STATUS status = NV_OK; + status = __nvoc_ctor_GpuResource(&pThis->__nvoc_base_GpuResource, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_VgpuApi_fail_GpuResource; + __nvoc_init_dataField_VgpuApi(pThis); + + status = __nvoc_vgpuapiConstruct(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_ctor_VgpuApi_fail__init; + goto __nvoc_ctor_VgpuApi_exit; // Success + +__nvoc_ctor_VgpuApi_fail__init: + __nvoc_dtor_GpuResource(&pThis->__nvoc_base_GpuResource); +__nvoc_ctor_VgpuApi_fail_GpuResource: +__nvoc_ctor_VgpuApi_exit: + + return status; +} + +static void __nvoc_init_funcTable_VgpuApi_1(VgpuApi *pThis) { + PORT_UNREFERENCED_VARIABLE(pThis); + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties__ = &vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuapiCtrlCmdVgpuDisplayCleanupSurface__ = &vgpuapiCtrlCmdVgpuDisplayCleanupSurface_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuapiCtrlCmdVGpuGetConfig__ = &vgpuapiCtrlCmdVGpuGetConfig_IMPL; +#endif + + pThis->__vgpuapiShareCallback__ = &__nvoc_thunk_GpuResource_vgpuapiShareCallback; + + pThis->__vgpuapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vgpuapiCheckMemInterUnmap; + + pThis->__vgpuapiMapTo__ = &__nvoc_thunk_RsResource_vgpuapiMapTo; + + pThis->__vgpuapiGetMapAddrSpace__ = &__nvoc_thunk_GpuResource_vgpuapiGetMapAddrSpace; + + pThis->__vgpuapiGetRefCount__ = &__nvoc_thunk_RsResource_vgpuapiGetRefCount; + + pThis->__vgpuapiAddAdditionalDependants__ = &__nvoc_thunk_RsResource_vgpuapiAddAdditionalDependants; + + pThis->__vgpuapiControl_Prologue__ = &__nvoc_thunk_RmResource_vgpuapiControl_Prologue; + + pThis->__vgpuapiGetRegBaseOffsetAndSize__ = &__nvoc_thunk_GpuResource_vgpuapiGetRegBaseOffsetAndSize; + + pThis->__vgpuapiInternalControlForward__ = &__nvoc_thunk_GpuResource_vgpuapiInternalControlForward; + + pThis->__vgpuapiUnmapFrom__ = &__nvoc_thunk_RsResource_vgpuapiUnmapFrom; + + pThis->__vgpuapiControl_Epilogue__ = &__nvoc_thunk_RmResource_vgpuapiControl_Epilogue; + + pThis->__vgpuapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vgpuapiGetInternalObjectHandle; + + pThis->__vgpuapiControl__ = &__nvoc_thunk_GpuResource_vgpuapiControl; + + pThis->__vgpuapiUnmap__ = &__nvoc_thunk_GpuResource_vgpuapiUnmap; + + pThis->__vgpuapiGetMemInterMapParams__ = &__nvoc_thunk_RmResource_vgpuapiGetMemInterMapParams; + + pThis->__vgpuapiGetMemoryMappingDescriptor__ = &__nvoc_thunk_RmResource_vgpuapiGetMemoryMappingDescriptor; + + pThis->__vgpuapiControlFilter__ = &__nvoc_thunk_RsResource_vgpuapiControlFilter; + + pThis->__vgpuapiControlSerialization_Prologue__ = &__nvoc_thunk_RmResource_vgpuapiControlSerialization_Prologue; + + pThis->__vgpuapiCanCopy__ = &__nvoc_thunk_RsResource_vgpuapiCanCopy; + + pThis->__vgpuapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_vgpuapiIsPartialUnmapSupported; + + pThis->__vgpuapiPreDestruct__ = &__nvoc_thunk_RsResource_vgpuapiPreDestruct; + + pThis->__vgpuapiIsDuplicate__ = &__nvoc_thunk_RsResource_vgpuapiIsDuplicate; + + pThis->__vgpuapiControlSerialization_Epilogue__ = &__nvoc_thunk_RmResource_vgpuapiControlSerialization_Epilogue; + + pThis->__vgpuapiMap__ = &__nvoc_thunk_GpuResource_vgpuapiMap; + + pThis->__vgpuapiAccessCallback__ = &__nvoc_thunk_RmResource_vgpuapiAccessCallback; +} + +void __nvoc_init_funcTable_VgpuApi(VgpuApi *pThis) { + __nvoc_init_funcTable_VgpuApi_1(pThis); +} + +void __nvoc_init_GpuResource(GpuResource*); +void __nvoc_init_VgpuApi(VgpuApi *pThis) { + pThis->__nvoc_pbase_VgpuApi = pThis; + pThis->__nvoc_pbase_Object = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object; + pThis->__nvoc_pbase_RsResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource; + pThis->__nvoc_pbase_RmResourceCommon = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RmResourceCommon; + pThis->__nvoc_pbase_RmResource = &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource; + pThis->__nvoc_pbase_GpuResource = &pThis->__nvoc_base_GpuResource; + __nvoc_init_GpuResource(&pThis->__nvoc_base_GpuResource); + __nvoc_init_funcTable_VgpuApi(pThis); +} + +NV_STATUS __nvoc_objCreate_VgpuApi(VgpuApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ + NV_STATUS status; + Object *pParentObj = NULL; + VgpuApi *pThis; + + // Assign `pThis`, allocating memory unless suppressed by flag. + status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VgpuApi), (void**)&pThis, (void**)ppThis); + if (status != NV_OK) + return status; + + // Zero is the initial value for everything. + portMemSet(pThis, 0, sizeof(VgpuApi)); + + // Initialize runtime type information. + __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VgpuApi); + + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + + // Link the child into the parent if there is one unless flagged not to do so. + if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + { + pParentObj = dynamicCast(pParent, Object); + objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + } + else + { + pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.pParent = NULL; + } + + __nvoc_init_VgpuApi(pThis); + status = __nvoc_ctor_VgpuApi(pThis, arg_pCallContext, arg_pParams); + if (status != NV_OK) goto __nvoc_objCreate_VgpuApi_cleanup; + + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. + *ppThis = pThis; + + return NV_OK; + +__nvoc_objCreate_VgpuApi_cleanup: + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. + if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) + portMemSet(pThis, 0, sizeof(VgpuApi)); + else + { + portMemFree(pThis); + *ppThis = NULL; + } + + // coverity[leaked_storage:FALSE] + return status; +} + +NV_STATUS __nvoc_objCreateDynamic_VgpuApi(VgpuApi **ppThis, Dynamic *pParent, NvU32 createFlags, va_list args) { + NV_STATUS status; + struct CALL_CONTEXT * arg_pCallContext = va_arg(args, struct CALL_CONTEXT *); + struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams = va_arg(args, struct RS_RES_ALLOC_PARAMS_INTERNAL *); + + status = __nvoc_objCreate_VgpuApi(ppThis, pParent, createFlags, arg_pCallContext, arg_pParams); + + return status; +} + diff --git a/src/nvidia/generated/g_vgpuapi_nvoc.h b/src/nvidia/generated/g_vgpuapi_nvoc.h new file mode 100644 index 0000000000..97bc3e8b56 --- /dev/null +++ b/src/nvidia/generated/g_vgpuapi_nvoc.h @@ -0,0 +1,284 @@ +#ifndef _G_VGPUAPI_NVOC_H_ +#define _G_VGPUAPI_NVOC_H_ +#include "nvoc/runtime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_vgpuapi_nvoc.h" + +#ifndef _VGPUAPI_H_ +#define _VGPUAPI_H_ + +#include "core/core.h" +#include "rmapi/client.h" +#include "gpu/gpu_resource.h" +#include "rmapi/control.h" +#include "ctrl/ctrla080.h" + + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. +#ifdef NVOC_VGPUAPI_H_PRIVATE_ACCESS_ALLOWED +#define PRIVATE_FIELD(x) x +#else +#define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) +#endif + +struct VgpuApi { + const struct NVOC_RTTI *__nvoc_rtti; + struct GpuResource __nvoc_base_GpuResource; + struct Object *__nvoc_pbase_Object; + struct RsResource *__nvoc_pbase_RsResource; + struct RmResourceCommon *__nvoc_pbase_RmResourceCommon; + struct RmResource *__nvoc_pbase_RmResource; + struct GpuResource *__nvoc_pbase_GpuResource; + struct VgpuApi *__nvoc_pbase_VgpuApi; + NV_STATUS (*__vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties__)(struct VgpuApi *, NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES *); + NV_STATUS (*__vgpuapiCtrlCmdVgpuDisplayCleanupSurface__)(struct VgpuApi *, NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *); + NV_STATUS (*__vgpuapiCtrlCmdVGpuGetConfig__)(struct VgpuApi *, NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *); + NvBool (*__vgpuapiShareCallback__)(struct VgpuApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); + NV_STATUS (*__vgpuapiCheckMemInterUnmap__)(struct VgpuApi *, NvBool); + NV_STATUS (*__vgpuapiMapTo__)(struct VgpuApi *, RS_RES_MAP_TO_PARAMS *); + NV_STATUS (*__vgpuapiGetMapAddrSpace__)(struct VgpuApi *, struct CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); + NvU32 (*__vgpuapiGetRefCount__)(struct VgpuApi *); + void (*__vgpuapiAddAdditionalDependants__)(struct RsClient *, struct VgpuApi *, RsResourceRef *); + NV_STATUS (*__vgpuapiControl_Prologue__)(struct VgpuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vgpuapiGetRegBaseOffsetAndSize__)(struct VgpuApi *, struct OBJGPU *, NvU32 *, NvU32 *); + NV_STATUS (*__vgpuapiInternalControlForward__)(struct VgpuApi *, NvU32, void *, NvU32); + NV_STATUS (*__vgpuapiUnmapFrom__)(struct VgpuApi *, RS_RES_UNMAP_FROM_PARAMS *); + void (*__vgpuapiControl_Epilogue__)(struct VgpuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvHandle (*__vgpuapiGetInternalObjectHandle__)(struct VgpuApi *); + NV_STATUS (*__vgpuapiControl__)(struct VgpuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vgpuapiUnmap__)(struct VgpuApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); + NV_STATUS (*__vgpuapiGetMemInterMapParams__)(struct VgpuApi *, RMRES_MEM_INTER_MAP_PARAMS *); + NV_STATUS (*__vgpuapiGetMemoryMappingDescriptor__)(struct VgpuApi *, struct MEMORY_DESCRIPTOR **); + NV_STATUS (*__vgpuapiControlFilter__)(struct VgpuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vgpuapiControlSerialization_Prologue__)(struct VgpuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NvBool (*__vgpuapiCanCopy__)(struct VgpuApi *); + NvBool (*__vgpuapiIsPartialUnmapSupported__)(struct VgpuApi *); + void (*__vgpuapiPreDestruct__)(struct VgpuApi *); + NV_STATUS (*__vgpuapiIsDuplicate__)(struct VgpuApi *, NvHandle, NvBool *); + void (*__vgpuapiControlSerialization_Epilogue__)(struct VgpuApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); + NV_STATUS (*__vgpuapiMap__)(struct VgpuApi *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *); + NvBool (*__vgpuapiAccessCallback__)(struct VgpuApi *, struct RsClient *, void *, RsAccessRight); + NODE node; + NvHandle handle; + NvHandle hDevice; +}; + +#ifndef __NVOC_CLASS_VgpuApi_TYPEDEF__ +#define __NVOC_CLASS_VgpuApi_TYPEDEF__ +typedef struct VgpuApi VgpuApi; +#endif /* __NVOC_CLASS_VgpuApi_TYPEDEF__ */ + +#ifndef __nvoc_class_id_VgpuApi +#define __nvoc_class_id_VgpuApi 0x7774f5 +#endif /* __nvoc_class_id_VgpuApi */ + +extern const struct NVOC_CLASS_DEF __nvoc_class_def_VgpuApi; + +#define __staticCast_VgpuApi(pThis) \ + ((pThis)->__nvoc_pbase_VgpuApi) + +#ifdef __nvoc_vgpuapi_h_disabled +#define __dynamicCast_VgpuApi(pThis) ((VgpuApi*)NULL) +#else //__nvoc_vgpuapi_h_disabled +#define __dynamicCast_VgpuApi(pThis) \ + ((VgpuApi*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(VgpuApi))) +#endif //__nvoc_vgpuapi_h_disabled + + +NV_STATUS __nvoc_objCreateDynamic_VgpuApi(VgpuApi**, Dynamic*, NvU32, va_list); + +NV_STATUS __nvoc_objCreate_VgpuApi(VgpuApi**, Dynamic*, NvU32, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams); +#define __objCreate_VgpuApi(ppNewObj, pParent, createFlags, arg_pCallContext, arg_pParams) \ + __nvoc_objCreate_VgpuApi((ppNewObj), staticCast((pParent), Dynamic), (createFlags), arg_pCallContext, arg_pParams) + +#define vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties(pVgpuApi, pParams) vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties_DISPATCH(pVgpuApi, pParams) +#define vgpuapiCtrlCmdVgpuDisplayCleanupSurface(pVgpuApi, pParams) vgpuapiCtrlCmdVgpuDisplayCleanupSurface_DISPATCH(pVgpuApi, pParams) +#define vgpuapiCtrlCmdVGpuGetConfig(pVgpuApi, pParams) vgpuapiCtrlCmdVGpuGetConfig_DISPATCH(pVgpuApi, pParams) +#define vgpuapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vgpuapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) +#define vgpuapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vgpuapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) +#define vgpuapiMapTo(pResource, pParams) vgpuapiMapTo_DISPATCH(pResource, pParams) +#define vgpuapiGetMapAddrSpace(pGpuResource, pCallContext, mapFlags, pAddrSpace) vgpuapiGetMapAddrSpace_DISPATCH(pGpuResource, pCallContext, mapFlags, pAddrSpace) +#define vgpuapiGetRefCount(pResource) vgpuapiGetRefCount_DISPATCH(pResource) +#define vgpuapiAddAdditionalDependants(pClient, pResource, pReference) vgpuapiAddAdditionalDependants_DISPATCH(pClient, pResource, pReference) +#define vgpuapiControl_Prologue(pResource, pCallContext, pParams) vgpuapiControl_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vgpuapiGetRegBaseOffsetAndSize(pGpuResource, pGpu, pOffset, pSize) vgpuapiGetRegBaseOffsetAndSize_DISPATCH(pGpuResource, pGpu, pOffset, pSize) +#define vgpuapiInternalControlForward(pGpuResource, command, pParams, size) vgpuapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) +#define vgpuapiUnmapFrom(pResource, pParams) vgpuapiUnmapFrom_DISPATCH(pResource, pParams) +#define vgpuapiControl_Epilogue(pResource, pCallContext, pParams) vgpuapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define vgpuapiGetInternalObjectHandle(pGpuResource) vgpuapiGetInternalObjectHandle_DISPATCH(pGpuResource) +#define vgpuapiControl(pGpuResource, pCallContext, pParams) vgpuapiControl_DISPATCH(pGpuResource, pCallContext, pParams) +#define vgpuapiUnmap(pGpuResource, pCallContext, pCpuMapping) vgpuapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) +#define vgpuapiGetMemInterMapParams(pRmResource, pParams) vgpuapiGetMemInterMapParams_DISPATCH(pRmResource, pParams) +#define vgpuapiGetMemoryMappingDescriptor(pRmResource, ppMemDesc) vgpuapiGetMemoryMappingDescriptor_DISPATCH(pRmResource, ppMemDesc) +#define vgpuapiControlFilter(pResource, pCallContext, pParams) vgpuapiControlFilter_DISPATCH(pResource, pCallContext, pParams) +#define vgpuapiControlSerialization_Prologue(pResource, pCallContext, pParams) vgpuapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) +#define vgpuapiCanCopy(pResource) vgpuapiCanCopy_DISPATCH(pResource) +#define vgpuapiIsPartialUnmapSupported(pResource) vgpuapiIsPartialUnmapSupported_DISPATCH(pResource) +#define vgpuapiPreDestruct(pResource) vgpuapiPreDestruct_DISPATCH(pResource) +#define vgpuapiIsDuplicate(pResource, hMemory, pDuplicate) vgpuapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) +#define vgpuapiControlSerialization_Epilogue(pResource, pCallContext, pParams) vgpuapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) +#define vgpuapiMap(pGpuResource, pCallContext, pParams, pCpuMapping) vgpuapiMap_DISPATCH(pGpuResource, pCallContext, pParams, pCpuMapping) +#define vgpuapiAccessCallback(pResource, pInvokingClient, pAllocParams, accessRight) vgpuapiAccessCallback_DISPATCH(pResource, pInvokingClient, pAllocParams, accessRight) +NV_STATUS vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties_IMPL(struct VgpuApi *pVgpuApi, NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES *pParams); + +static inline NV_STATUS vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties_DISPATCH(struct VgpuApi *pVgpuApi, NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES *pParams) { + return pVgpuApi->__vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties__(pVgpuApi, pParams); +} + +NV_STATUS vgpuapiCtrlCmdVgpuDisplayCleanupSurface_IMPL(struct VgpuApi *pVgpuApi, NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams); + +static inline NV_STATUS vgpuapiCtrlCmdVgpuDisplayCleanupSurface_DISPATCH(struct VgpuApi *pVgpuApi, NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams) { + return pVgpuApi->__vgpuapiCtrlCmdVgpuDisplayCleanupSurface__(pVgpuApi, pParams); +} + +NV_STATUS vgpuapiCtrlCmdVGpuGetConfig_IMPL(struct VgpuApi *pVgpuApi, NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *pParams); + +static inline NV_STATUS vgpuapiCtrlCmdVGpuGetConfig_DISPATCH(struct VgpuApi *pVgpuApi, NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *pParams) { + return pVgpuApi->__vgpuapiCtrlCmdVGpuGetConfig__(pVgpuApi, pParams); +} + +static inline NvBool vgpuapiShareCallback_DISPATCH(struct VgpuApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { + return pGpuResource->__vgpuapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); +} + +static inline NV_STATUS vgpuapiCheckMemInterUnmap_DISPATCH(struct VgpuApi *pRmResource, NvBool bSubdeviceHandleProvided) { + return pRmResource->__vgpuapiCheckMemInterUnmap__(pRmResource, bSubdeviceHandleProvided); +} + +static inline NV_STATUS vgpuapiMapTo_DISPATCH(struct VgpuApi *pResource, RS_RES_MAP_TO_PARAMS *pParams) { + return pResource->__vgpuapiMapTo__(pResource, pParams); +} + +static inline NV_STATUS vgpuapiGetMapAddrSpace_DISPATCH(struct VgpuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, NvU32 mapFlags, NV_ADDRESS_SPACE *pAddrSpace) { + return pGpuResource->__vgpuapiGetMapAddrSpace__(pGpuResource, pCallContext, mapFlags, pAddrSpace); +} + +static inline NvU32 vgpuapiGetRefCount_DISPATCH(struct VgpuApi *pResource) { + return pResource->__vgpuapiGetRefCount__(pResource); +} + +static inline void vgpuapiAddAdditionalDependants_DISPATCH(struct RsClient *pClient, struct VgpuApi *pResource, RsResourceRef *pReference) { + pResource->__vgpuapiAddAdditionalDependants__(pClient, pResource, pReference); +} + +static inline NV_STATUS vgpuapiControl_Prologue_DISPATCH(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vgpuapiControl_Prologue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vgpuapiGetRegBaseOffsetAndSize_DISPATCH(struct VgpuApi *pGpuResource, struct OBJGPU *pGpu, NvU32 *pOffset, NvU32 *pSize) { + return pGpuResource->__vgpuapiGetRegBaseOffsetAndSize__(pGpuResource, pGpu, pOffset, pSize); +} + +static inline NV_STATUS vgpuapiInternalControlForward_DISPATCH(struct VgpuApi *pGpuResource, NvU32 command, void *pParams, NvU32 size) { + return pGpuResource->__vgpuapiInternalControlForward__(pGpuResource, command, pParams, size); +} + +static inline NV_STATUS vgpuapiUnmapFrom_DISPATCH(struct VgpuApi *pResource, RS_RES_UNMAP_FROM_PARAMS *pParams) { + return pResource->__vgpuapiUnmapFrom__(pResource, pParams); +} + +static inline void vgpuapiControl_Epilogue_DISPATCH(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vgpuapiControl_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NvHandle vgpuapiGetInternalObjectHandle_DISPATCH(struct VgpuApi *pGpuResource) { + return pGpuResource->__vgpuapiGetInternalObjectHandle__(pGpuResource); +} + +static inline NV_STATUS vgpuapiControl_DISPATCH(struct VgpuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pGpuResource->__vgpuapiControl__(pGpuResource, pCallContext, pParams); +} + +static inline NV_STATUS vgpuapiUnmap_DISPATCH(struct VgpuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__vgpuapiUnmap__(pGpuResource, pCallContext, pCpuMapping); +} + +static inline NV_STATUS vgpuapiGetMemInterMapParams_DISPATCH(struct VgpuApi *pRmResource, RMRES_MEM_INTER_MAP_PARAMS *pParams) { + return pRmResource->__vgpuapiGetMemInterMapParams__(pRmResource, pParams); +} + +static inline NV_STATUS vgpuapiGetMemoryMappingDescriptor_DISPATCH(struct VgpuApi *pRmResource, struct MEMORY_DESCRIPTOR **ppMemDesc) { + return pRmResource->__vgpuapiGetMemoryMappingDescriptor__(pRmResource, ppMemDesc); +} + +static inline NV_STATUS vgpuapiControlFilter_DISPATCH(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vgpuapiControlFilter__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vgpuapiControlSerialization_Prologue_DISPATCH(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + return pResource->__vgpuapiControlSerialization_Prologue__(pResource, pCallContext, pParams); +} + +static inline NvBool vgpuapiCanCopy_DISPATCH(struct VgpuApi *pResource) { + return pResource->__vgpuapiCanCopy__(pResource); +} + +static inline NvBool vgpuapiIsPartialUnmapSupported_DISPATCH(struct VgpuApi *pResource) { + return pResource->__vgpuapiIsPartialUnmapSupported__(pResource); +} + +static inline void vgpuapiPreDestruct_DISPATCH(struct VgpuApi *pResource) { + pResource->__vgpuapiPreDestruct__(pResource); +} + +static inline NV_STATUS vgpuapiIsDuplicate_DISPATCH(struct VgpuApi *pResource, NvHandle hMemory, NvBool *pDuplicate) { + return pResource->__vgpuapiIsDuplicate__(pResource, hMemory, pDuplicate); +} + +static inline void vgpuapiControlSerialization_Epilogue_DISPATCH(struct VgpuApi *pResource, struct CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + pResource->__vgpuapiControlSerialization_Epilogue__(pResource, pCallContext, pParams); +} + +static inline NV_STATUS vgpuapiMap_DISPATCH(struct VgpuApi *pGpuResource, struct CALL_CONTEXT *pCallContext, struct RS_CPU_MAP_PARAMS *pParams, struct RsCpuMapping *pCpuMapping) { + return pGpuResource->__vgpuapiMap__(pGpuResource, pCallContext, pParams, pCpuMapping); +} + +static inline NvBool vgpuapiAccessCallback_DISPATCH(struct VgpuApi *pResource, struct RsClient *pInvokingClient, void *pAllocParams, RsAccessRight accessRight) { + return pResource->__vgpuapiAccessCallback__(pResource, pInvokingClient, pAllocParams, accessRight); +} + +NV_STATUS vgpuapiConstruct_IMPL(struct VgpuApi *arg_pVgpuApi, struct CALL_CONTEXT *arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL *arg_pParams); + +#define __nvoc_vgpuapiConstruct(arg_pVgpuApi, arg_pCallContext, arg_pParams) vgpuapiConstruct_IMPL(arg_pVgpuApi, arg_pCallContext, arg_pParams) +void vgpuapiDestruct_IMPL(struct VgpuApi *pVgpuApi); + +#define __nvoc_vgpuapiDestruct(pVgpuApi) vgpuapiDestruct_IMPL(pVgpuApi) +#undef PRIVATE_FIELD + + +#endif // _VGPUAPI_H_ + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // _G_VGPUAPI_NVOC_H_ diff --git a/src/nvidia/generated/g_vgpuconfigapi_nvoc.c b/src/nvidia/generated/g_vgpuconfigapi_nvoc.c index 4ccd392450..a6c24e5ccc 100644 --- a/src/nvidia/generated/g_vgpuconfigapi_nvoc.c +++ b/src/nvidia/generated/g_vgpuconfigapi_nvoc.c @@ -163,10 +163,6 @@ static void __nvoc_thunk_RmResource_vgpuconfigapiControl_Epilogue(struct VgpuCon rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vgpuconfigapiControlLookup(struct VgpuConfigApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_vgpuconfigapiGetInternalObjectHandle(struct VgpuConfigApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VgpuConfigApi_GpuResource.offset)); } @@ -203,6 +199,10 @@ static NvBool __nvoc_thunk_RsResource_vgpuconfigapiCanCopy(struct VgpuConfigApi return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_vgpuconfigapiIsPartialUnmapSupported(struct VgpuConfigApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_vgpuconfigapiPreDestruct(struct VgpuConfigApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VgpuConfigApi_RsResource.offset)); } @@ -346,7 +346,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VgpuConf #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_IMPL, + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo_IMPL, #endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*flags=*/ 0x10u, /*accessRight=*/0x0u, @@ -354,7 +354,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VgpuConf /*paramSize=*/ 0, /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED - /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigMdevRegister" + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo" #endif }, { /* [8] */ @@ -520,6 +520,66 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VgpuConf /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), #if NV_PRINTF_STRINGS_ALLOWED /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId" +#endif + }, + { /* [19] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + /*flags=*/ 0x4u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa081011bu, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo" +#endif + }, + { /* [20] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa081011cu, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements" +#endif + }, + { /* [21] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa081011du, + /*paramSize=*/ sizeof(NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability" +#endif + }, + { /* [22] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) vgpuconfigapiCtrlCmdVgpuConfigSetCapability_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + /*flags=*/ 0x10u, + /*accessRight=*/0x0u, + /*methodId=*/ 0xa081011eu, + /*paramSize=*/ sizeof(NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_VgpuConfigApi.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "vgpuconfigapiCtrlCmdVgpuConfigSetCapability" #endif }, @@ -527,7 +587,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_VgpuConf const struct NVOC_EXPORT_INFO __nvoc_export_info_VgpuConfigApi = { - /*numEntries=*/ 19, + /*numEntries=*/ 23, /*pExportEntries=*/ __nvoc_exported_method_def_VgpuConfigApi }; @@ -595,12 +655,20 @@ static void __nvoc_init_funcTable_VgpuConfigApi_1(VgpuConfigApi *pThis) { pThis->__vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification__ = &vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigSetCapability__ = &vgpuconfigapiCtrlCmdVgpuConfigSetCapability_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__vgpuconfigapiCtrlCmdVgpuConfigNotifyStart__ = &vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) - pThis->__vgpuconfigapiCtrlCmdVgpuConfigMdevRegister__ = &vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_IMPL; + pThis->__vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements__ = &vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements_IMPL; +#endif + +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo__ = &vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo_IMPL; #endif #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) @@ -635,6 +703,10 @@ static void __nvoc_init_funcTable_VgpuConfigApi_1(VgpuConfigApi *pThis) { pThis->__vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo__ = &vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) + pThis->__vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability__ = &vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) pThis->__vgpuconfigapiCtrlCmdGetVgpuDriversCaps__ = &vgpuconfigapiCtrlCmdGetVgpuDriversCaps_IMPL; #endif @@ -647,6 +719,10 @@ static void __nvoc_init_funcTable_VgpuConfigApi_1(VgpuConfigApi *pThis) { pThis->__vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId__ = &vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + pThis->__vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo__ = &vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo_IMPL; +#endif + pThis->__vgpuconfigapiShareCallback__ = &__nvoc_thunk_GpuResource_vgpuconfigapiShareCallback; pThis->__vgpuconfigapiCheckMemInterUnmap__ = &__nvoc_thunk_RmResource_vgpuconfigapiCheckMemInterUnmap; @@ -673,8 +749,6 @@ static void __nvoc_init_funcTable_VgpuConfigApi_1(VgpuConfigApi *pThis) { pThis->__vgpuconfigapiControl_Epilogue__ = &__nvoc_thunk_RmResource_vgpuconfigapiControl_Epilogue; - pThis->__vgpuconfigapiControlLookup__ = &__nvoc_thunk_RsResource_vgpuconfigapiControlLookup; - pThis->__vgpuconfigapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vgpuconfigapiGetInternalObjectHandle; pThis->__vgpuconfigapiControl__ = &__nvoc_thunk_GpuResource_vgpuconfigapiControl; @@ -693,6 +767,8 @@ static void __nvoc_init_funcTable_VgpuConfigApi_1(VgpuConfigApi *pThis) { pThis->__vgpuconfigapiCanCopy__ = &__nvoc_thunk_RsResource_vgpuconfigapiCanCopy; + pThis->__vgpuconfigapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_vgpuconfigapiIsPartialUnmapSupported; + pThis->__vgpuconfigapiPreDestruct__ = &__nvoc_thunk_RsResource_vgpuconfigapiPreDestruct; pThis->__vgpuconfigapiIsDuplicate__ = &__nvoc_thunk_RsResource_vgpuconfigapiIsDuplicate; @@ -728,21 +804,26 @@ void __nvoc_init_VgpuConfigApi(VgpuConfigApi *pThis) { __nvoc_init_funcTable_VgpuConfigApi(pThis); } -NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; VgpuConfigApi *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VgpuConfigApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(VgpuConfigApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VgpuConfigApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -757,16 +838,25 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi **ppThis, Dynamic *pParen status = __nvoc_ctor_VgpuConfigApi(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_VgpuConfigApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_VgpuConfigApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(VgpuConfigApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_vgpuconfigapi_nvoc.h b/src/nvidia/generated/g_vgpuconfigapi_nvoc.h index ba828374ab..b01729baf7 100644 --- a/src/nvidia/generated/g_vgpuconfigapi_nvoc.h +++ b/src/nvidia/generated/g_vgpuconfigapi_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -45,11 +45,16 @@ extern "C" { // Virtual GPU configuration information // + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VGPUCONFIGAPI_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct VgpuConfigApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -68,8 +73,10 @@ struct VgpuConfigApi { NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigSetCapability__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigNotifyStart__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS *); - NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigMdevRegister__)(struct VgpuConfigApi *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo__)(struct VgpuConfigApi *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap__)(struct VgpuConfigApi *, NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS *); @@ -78,9 +85,11 @@ struct VgpuConfigApi { NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_DOORBELL_EMULATION_SUPPORT_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo__)(struct VgpuConfigApi *, NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability__)(struct VgpuConfigApi *, NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdGetVgpuDriversCaps__)(struct VgpuConfigApi *, NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS *); NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS *); + NV_STATUS (*__vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo__)(struct VgpuConfigApi *, NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS *); NvBool (*__vgpuconfigapiShareCallback__)(struct VgpuConfigApi *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__vgpuconfigapiCheckMemInterUnmap__)(struct VgpuConfigApi *, NvBool); NV_STATUS (*__vgpuconfigapiGetOrAllocNotifShare__)(struct VgpuConfigApi *, NvHandle, NvHandle, struct NotifShare **); @@ -94,7 +103,6 @@ struct VgpuConfigApi { NV_STATUS (*__vgpuconfigapiInternalControlForward__)(struct VgpuConfigApi *, NvU32, void *, NvU32); NV_STATUS (*__vgpuconfigapiUnmapFrom__)(struct VgpuConfigApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__vgpuconfigapiControl_Epilogue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vgpuconfigapiControlLookup__)(struct VgpuConfigApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__vgpuconfigapiGetInternalObjectHandle__)(struct VgpuConfigApi *); NV_STATUS (*__vgpuconfigapiControl__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vgpuconfigapiUnmap__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -104,6 +112,7 @@ struct VgpuConfigApi { NV_STATUS (*__vgpuconfigapiUnregisterEvent__)(struct VgpuConfigApi *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__vgpuconfigapiControlSerialization_Prologue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vgpuconfigapiCanCopy__)(struct VgpuConfigApi *); + NvBool (*__vgpuconfigapiIsPartialUnmapSupported__)(struct VgpuConfigApi *); void (*__vgpuconfigapiPreDestruct__)(struct VgpuConfigApi *); NV_STATUS (*__vgpuconfigapiIsDuplicate__)(struct VgpuConfigApi *, NvHandle, NvBool *); void (*__vgpuconfigapiControlSerialization_Epilogue__)(struct VgpuConfigApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -148,8 +157,10 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi**, Dynamic*, NvU32, struc #define vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification(pVgpuConfigApi, pSetEventParams) vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_DISPATCH(pVgpuConfigApi, pSetEventParams) +#define vgpuconfigapiCtrlCmdVgpuConfigSetCapability(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigSetCapability_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigNotifyStart(pVgpuConfigApi, pNotifyParams) vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_DISPATCH(pVgpuConfigApi, pNotifyParams) -#define vgpuconfigapiCtrlCmdVgpuConfigMdevRegister(pVgpuConfigApi) vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_DISPATCH(pVgpuConfigApi) +#define vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo(pVgpuConfigApi) vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo_DISPATCH(pVgpuConfigApi) #define vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity(pVgpuConfigApi, pEncoderParams) vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_DISPATCH(pVgpuConfigApi, pEncoderParams) #define vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap_DISPATCH(pVgpuConfigApi, pParams) @@ -158,9 +169,11 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi**, Dynamic*, NvU32, struc #define vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetDoorbellEmulationSupport_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdGetVgpuDriversCaps(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdGetVgpuDriversCaps_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_DISPATCH(pVgpuConfigApi, pParams) +#define vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo(pVgpuConfigApi, pParams) vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo_DISPATCH(pVgpuConfigApi, pParams) #define vgpuconfigapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) vgpuconfigapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define vgpuconfigapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) vgpuconfigapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) #define vgpuconfigapiGetOrAllocNotifShare(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) vgpuconfigapiGetOrAllocNotifShare_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, ppNotifShare) @@ -174,7 +187,6 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi**, Dynamic*, NvU32, struc #define vgpuconfigapiInternalControlForward(pGpuResource, command, pParams, size) vgpuconfigapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define vgpuconfigapiUnmapFrom(pResource, pParams) vgpuconfigapiUnmapFrom_DISPATCH(pResource, pParams) #define vgpuconfigapiControl_Epilogue(pResource, pCallContext, pParams) vgpuconfigapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vgpuconfigapiControlLookup(pResource, pParams, ppEntry) vgpuconfigapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vgpuconfigapiGetInternalObjectHandle(pGpuResource) vgpuconfigapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define vgpuconfigapiControl(pGpuResource, pCallContext, pParams) vgpuconfigapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define vgpuconfigapiUnmap(pGpuResource, pCallContext, pCpuMapping) vgpuconfigapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -184,6 +196,7 @@ NV_STATUS __nvoc_objCreate_VgpuConfigApi(VgpuConfigApi**, Dynamic*, NvU32, struc #define vgpuconfigapiUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) vgpuconfigapiUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define vgpuconfigapiControlSerialization_Prologue(pResource, pCallContext, pParams) vgpuconfigapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vgpuconfigapiCanCopy(pResource) vgpuconfigapiCanCopy_DISPATCH(pResource) +#define vgpuconfigapiIsPartialUnmapSupported(pResource) vgpuconfigapiIsPartialUnmapSupported_DISPATCH(pResource) #define vgpuconfigapiPreDestruct(pResource) vgpuconfigapiPreDestruct_DISPATCH(pResource) #define vgpuconfigapiIsDuplicate(pResource, hMemory, pDuplicate) vgpuconfigapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define vgpuconfigapiControlSerialization_Epilogue(pResource, pCallContext, pParams) vgpuconfigapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -227,16 +240,28 @@ static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_DISPA return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification__(pVgpuConfigApi, pSetEventParams); } +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetCapability_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetCapability_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigSetCapability__(pVgpuConfigApi, pParams); +} + NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS *pNotifyParams); static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS *pNotifyParams) { return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigNotifyStart__(pVgpuConfigApi, pNotifyParams); } -NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_IMPL(struct VgpuConfigApi *pVgpuConfigApi); +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS *pParams); -static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi) { - return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigMdevRegister__(pVgpuConfigApi); +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements__(pVgpuConfigApi, pParams); +} + +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo_IMPL(struct VgpuConfigApi *pVgpuConfigApi); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo__(pVgpuConfigApi); } NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS *pEncoderParams); @@ -287,6 +312,12 @@ static inline NV_STATUS vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_DISPATCH return pVgpuConfigApi->__vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo__(pVgpuConfigApi, pParams); } +NV_STATUS vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability__(pVgpuConfigApi, pParams); +} + NV_STATUS vgpuconfigapiCtrlCmdGetVgpuDriversCaps_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *pParams); static inline NV_STATUS vgpuconfigapiCtrlCmdGetVgpuDriversCaps_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *pParams) { @@ -305,6 +336,12 @@ static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_DISPATCH(s return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId__(pVgpuConfigApi, pParams); } +NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo_IMPL(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS *pParams); + +static inline NV_STATUS vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo_DISPATCH(struct VgpuConfigApi *pVgpuConfigApi, NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS *pParams) { + return pVgpuConfigApi->__vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo__(pVgpuConfigApi, pParams); +} + static inline NvBool vgpuconfigapiShareCallback_DISPATCH(struct VgpuConfigApi *pGpuResource, struct RsClient *pInvokingClient, struct RsResourceRef *pParentRef, RS_SHARE_POLICY *pSharePolicy) { return pGpuResource->__vgpuconfigapiShareCallback__(pGpuResource, pInvokingClient, pParentRef, pSharePolicy); } @@ -357,10 +394,6 @@ static inline void vgpuconfigapiControl_Epilogue_DISPATCH(struct VgpuConfigApi * pResource->__vgpuconfigapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vgpuconfigapiControlLookup_DISPATCH(struct VgpuConfigApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vgpuconfigapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle vgpuconfigapiGetInternalObjectHandle_DISPATCH(struct VgpuConfigApi *pGpuResource) { return pGpuResource->__vgpuconfigapiGetInternalObjectHandle__(pGpuResource); } @@ -397,6 +430,10 @@ static inline NvBool vgpuconfigapiCanCopy_DISPATCH(struct VgpuConfigApi *pResour return pResource->__vgpuconfigapiCanCopy__(pResource); } +static inline NvBool vgpuconfigapiIsPartialUnmapSupported_DISPATCH(struct VgpuConfigApi *pResource) { + return pResource->__vgpuconfigapiIsPartialUnmapSupported__(pResource); +} + static inline void vgpuconfigapiPreDestruct_DISPATCH(struct VgpuConfigApi *pResource) { pResource->__vgpuconfigapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_video_mem_nvoc.c b/src/nvidia/generated/g_video_mem_nvoc.c index 0461224aa1..e65fc0f45c 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.c +++ b/src/nvidia/generated/g_video_mem_nvoc.c @@ -150,10 +150,6 @@ static void __nvoc_thunk_RmResource_vidmemControl_Epilogue(struct VideoMemory *p rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vidmemControlLookup(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_vidmemControl(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), pCallContext, pParams); } @@ -182,6 +178,10 @@ static NvBool __nvoc_thunk_StandardMemory_vidmemCanCopy(struct VideoMemory *pSta return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VideoMemory_StandardMemory.offset)); } +static NvBool __nvoc_thunk_RsResource_vidmemIsPartialUnmapSupported(struct VideoMemory *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VideoMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_vidmemIsReady(struct VideoMemory *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VideoMemory_Memory.offset), bCopyConstructorContext); } @@ -271,8 +271,6 @@ static void __nvoc_init_funcTable_VideoMemory_1(VideoMemory *pThis) { pThis->__vidmemControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemControl_Epilogue; - pThis->__vidmemControlLookup__ = &__nvoc_thunk_RsResource_vidmemControlLookup; - pThis->__vidmemControl__ = &__nvoc_thunk_Memory_vidmemControl; pThis->__vidmemUnmap__ = &__nvoc_thunk_Memory_vidmemUnmap; @@ -287,6 +285,8 @@ static void __nvoc_init_funcTable_VideoMemory_1(VideoMemory *pThis) { pThis->__vidmemCanCopy__ = &__nvoc_thunk_StandardMemory_vidmemCanCopy; + pThis->__vidmemIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_vidmemIsPartialUnmapSupported; + pThis->__vidmemIsReady__ = &__nvoc_thunk_Memory_vidmemIsReady; pThis->__vidmemPreDestruct__ = &__nvoc_thunk_RsResource_vidmemPreDestruct; @@ -317,21 +317,26 @@ void __nvoc_init_VideoMemory(VideoMemory *pThis) { __nvoc_init_funcTable_VideoMemory(pThis); } -NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; VideoMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VideoMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(VideoMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VideoMemory); pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -346,16 +351,25 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory **ppThis, Dynamic *pParent, N status = __nvoc_ctor_VideoMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_VideoMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_VideoMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(VideoMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_video_mem_nvoc.h b/src/nvidia/generated/g_video_mem_nvoc.h index 100eaefb69..baf46af861 100644 --- a/src/nvidia/generated/g_video_mem_nvoc.h +++ b/src/nvidia/generated/g_video_mem_nvoc.h @@ -51,11 +51,16 @@ typedef struct Device Device; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VIDEO_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct VideoMemory { const struct NVOC_RTTI *__nvoc_rtti; struct StandardMemory __nvoc_base_StandardMemory; @@ -78,7 +83,6 @@ struct VideoMemory { NvBool (*__vidmemIsGpuMapAllowed__)(struct VideoMemory *, struct OBJGPU *); NV_STATUS (*__vidmemUnmapFrom__)(struct VideoMemory *, RS_RES_UNMAP_FROM_PARAMS *); void (*__vidmemControl_Epilogue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vidmemControlLookup__)(struct VideoMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__vidmemControl__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemUnmap__)(struct VideoMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__vidmemGetMemInterMapParams__)(struct VideoMemory *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -86,6 +90,7 @@ struct VideoMemory { NV_STATUS (*__vidmemControlFilter__)(struct VideoMemory *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemControlSerialization_Prologue__)(struct VideoMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vidmemCanCopy__)(struct VideoMemory *); + NvBool (*__vidmemIsPartialUnmapSupported__)(struct VideoMemory *); NV_STATUS (*__vidmemIsReady__)(struct VideoMemory *, NvBool); void (*__vidmemPreDestruct__)(struct VideoMemory *); NV_STATUS (*__vidmemIsDuplicate__)(struct VideoMemory *, NvHandle, NvBool *); @@ -134,7 +139,6 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory**, Dynamic*, NvU32, CALL_CONT #define vidmemIsGpuMapAllowed(pMemory, pGpu) vidmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define vidmemUnmapFrom(pResource, pParams) vidmemUnmapFrom_DISPATCH(pResource, pParams) #define vidmemControl_Epilogue(pResource, pCallContext, pParams) vidmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vidmemControlLookup(pResource, pParams, ppEntry) vidmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vidmemControl(pMemory, pCallContext, pParams) vidmemControl_DISPATCH(pMemory, pCallContext, pParams) #define vidmemUnmap(pMemory, pCallContext, pCpuMapping) vidmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define vidmemGetMemInterMapParams(pMemory, pParams) vidmemGetMemInterMapParams_DISPATCH(pMemory, pParams) @@ -142,6 +146,7 @@ NV_STATUS __nvoc_objCreate_VideoMemory(VideoMemory**, Dynamic*, NvU32, CALL_CONT #define vidmemControlFilter(pResource, pCallContext, pParams) vidmemControlFilter_DISPATCH(pResource, pCallContext, pParams) #define vidmemControlSerialization_Prologue(pResource, pCallContext, pParams) vidmemControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemCanCopy(pStandardMemory) vidmemCanCopy_DISPATCH(pStandardMemory) +#define vidmemIsPartialUnmapSupported(pResource) vidmemIsPartialUnmapSupported_DISPATCH(pResource) #define vidmemIsReady(pMemory, bCopyConstructorContext) vidmemIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define vidmemPreDestruct(pResource) vidmemPreDestruct_DISPATCH(pResource) #define vidmemIsDuplicate(pMemory, hMemory, pDuplicate) vidmemIsDuplicate_DISPATCH(pMemory, hMemory, pDuplicate) @@ -198,10 +203,6 @@ static inline void vidmemControl_Epilogue_DISPATCH(struct VideoMemory *pResource pResource->__vidmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vidmemControlLookup_DISPATCH(struct VideoMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vidmemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS vidmemControl_DISPATCH(struct VideoMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__vidmemControl__(pMemory, pCallContext, pParams); } @@ -230,6 +231,10 @@ static inline NvBool vidmemCanCopy_DISPATCH(struct VideoMemory *pStandardMemory) return pStandardMemory->__vidmemCanCopy__(pStandardMemory); } +static inline NvBool vidmemIsPartialUnmapSupported_DISPATCH(struct VideoMemory *pResource) { + return pResource->__vidmemIsPartialUnmapSupported__(pResource); +} + static inline NV_STATUS vidmemIsReady_DISPATCH(struct VideoMemory *pMemory, NvBool bCopyConstructorContext) { return pMemory->__vidmemIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c index 2ef2f11abc..009576fbf4 100644 --- a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c +++ b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.c @@ -163,10 +163,6 @@ static void __nvoc_thunk_RmResource_vidmemAccessBitBufControl_Epilogue(struct Vi rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vidmemAccessBitBufControlLookup(struct VidmemAccessBitBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_vidmemAccessBitBufGetInternalObjectHandle(struct VidmemAccessBitBuffer *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_VidmemAccessBitBuffer_GpuResource.offset)); } @@ -203,6 +199,10 @@ static NvBool __nvoc_thunk_RsResource_vidmemAccessBitBufCanCopy(struct VidmemAcc return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_vidmemAccessBitBufIsPartialUnmapSupported(struct VidmemAccessBitBuffer *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_vidmemAccessBitBufPreDestruct(struct VidmemAccessBitBuffer *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VidmemAccessBitBuffer_RsResource.offset)); } @@ -341,8 +341,6 @@ static void __nvoc_init_funcTable_VidmemAccessBitBuffer_1(VidmemAccessBitBuffer pThis->__vidmemAccessBitBufControl_Epilogue__ = &__nvoc_thunk_RmResource_vidmemAccessBitBufControl_Epilogue; - pThis->__vidmemAccessBitBufControlLookup__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufControlLookup; - pThis->__vidmemAccessBitBufGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufGetInternalObjectHandle; pThis->__vidmemAccessBitBufControl__ = &__nvoc_thunk_GpuResource_vidmemAccessBitBufControl; @@ -361,6 +359,8 @@ static void __nvoc_init_funcTable_VidmemAccessBitBuffer_1(VidmemAccessBitBuffer pThis->__vidmemAccessBitBufCanCopy__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufCanCopy; + pThis->__vidmemAccessBitBufIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufIsPartialUnmapSupported; + pThis->__vidmemAccessBitBufPreDestruct__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufPreDestruct; pThis->__vidmemAccessBitBufIsDuplicate__ = &__nvoc_thunk_RsResource_vidmemAccessBitBufIsDuplicate; @@ -396,23 +396,31 @@ void __nvoc_init_VidmemAccessBitBuffer(VidmemAccessBitBuffer *pThis, RmHalspecOw __nvoc_init_funcTable_VidmemAccessBitBuffer(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; VidmemAccessBitBuffer *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VidmemAccessBitBuffer), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(VidmemAccessBitBuffer)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VidmemAccessBitBuffer); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -430,16 +438,25 @@ NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer **ppThis, status = __nvoc_ctor_VidmemAccessBitBuffer(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_VidmemAccessBitBuffer_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_VidmemAccessBitBuffer_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(VidmemAccessBitBuffer)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h index 988d1eefb0..fdf3eba593 100644 --- a/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h +++ b/src/nvidia/generated/g_vidmem_access_bit_buffer_nvoc.h @@ -76,11 +76,16 @@ typedef struct /*! * RM internal class representing VIDMEM_ACCESS_BIT_BUFFER */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VIDMEM_ACCESS_BIT_BUFFER_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct VidmemAccessBitBuffer { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -107,7 +112,6 @@ struct VidmemAccessBitBuffer { NV_STATUS (*__vidmemAccessBitBufInternalControlForward__)(struct VidmemAccessBitBuffer *, NvU32, void *, NvU32); NV_STATUS (*__vidmemAccessBitBufUnmapFrom__)(struct VidmemAccessBitBuffer *, RS_RES_UNMAP_FROM_PARAMS *); void (*__vidmemAccessBitBufControl_Epilogue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vidmemAccessBitBufControlLookup__)(struct VidmemAccessBitBuffer *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__vidmemAccessBitBufGetInternalObjectHandle__)(struct VidmemAccessBitBuffer *); NV_STATUS (*__vidmemAccessBitBufControl__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vidmemAccessBitBufUnmap__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -117,6 +121,7 @@ struct VidmemAccessBitBuffer { NV_STATUS (*__vidmemAccessBitBufUnregisterEvent__)(struct VidmemAccessBitBuffer *, NvHandle, NvHandle, NvHandle, NvHandle); NV_STATUS (*__vidmemAccessBitBufControlSerialization_Prologue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vidmemAccessBitBufCanCopy__)(struct VidmemAccessBitBuffer *); + NvBool (*__vidmemAccessBitBufIsPartialUnmapSupported__)(struct VidmemAccessBitBuffer *); void (*__vidmemAccessBitBufPreDestruct__)(struct VidmemAccessBitBuffer *); NV_STATUS (*__vidmemAccessBitBufIsDuplicate__)(struct VidmemAccessBitBuffer *, NvHandle, NvBool *); void (*__vidmemAccessBitBufControlSerialization_Epilogue__)(struct VidmemAccessBitBuffer *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -168,7 +173,6 @@ NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer**, Dynami #define vidmemAccessBitBufInternalControlForward(pGpuResource, command, pParams, size) vidmemAccessBitBufInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define vidmemAccessBitBufUnmapFrom(pResource, pParams) vidmemAccessBitBufUnmapFrom_DISPATCH(pResource, pParams) #define vidmemAccessBitBufControl_Epilogue(pResource, pCallContext, pParams) vidmemAccessBitBufControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vidmemAccessBitBufControlLookup(pResource, pParams, ppEntry) vidmemAccessBitBufControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vidmemAccessBitBufGetInternalObjectHandle(pGpuResource) vidmemAccessBitBufGetInternalObjectHandle_DISPATCH(pGpuResource) #define vidmemAccessBitBufControl(pGpuResource, pCallContext, pParams) vidmemAccessBitBufControl_DISPATCH(pGpuResource, pCallContext, pParams) #define vidmemAccessBitBufUnmap(pGpuResource, pCallContext, pCpuMapping) vidmemAccessBitBufUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -178,6 +182,7 @@ NV_STATUS __nvoc_objCreate_VidmemAccessBitBuffer(VidmemAccessBitBuffer**, Dynami #define vidmemAccessBitBufUnregisterEvent(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) vidmemAccessBitBufUnregisterEvent_DISPATCH(pNotifier, hNotifierClient, hNotifierResource, hEventClient, hEvent) #define vidmemAccessBitBufControlSerialization_Prologue(pResource, pCallContext, pParams) vidmemAccessBitBufControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vidmemAccessBitBufCanCopy(pResource) vidmemAccessBitBufCanCopy_DISPATCH(pResource) +#define vidmemAccessBitBufIsPartialUnmapSupported(pResource) vidmemAccessBitBufIsPartialUnmapSupported_DISPATCH(pResource) #define vidmemAccessBitBufPreDestruct(pResource) vidmemAccessBitBufPreDestruct_DISPATCH(pResource) #define vidmemAccessBitBufIsDuplicate(pResource, hMemory, pDuplicate) vidmemAccessBitBufIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define vidmemAccessBitBufControlSerialization_Epilogue(pResource, pCallContext, pParams) vidmemAccessBitBufControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -263,10 +268,6 @@ static inline void vidmemAccessBitBufControl_Epilogue_DISPATCH(struct VidmemAcce pResource->__vidmemAccessBitBufControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vidmemAccessBitBufControlLookup_DISPATCH(struct VidmemAccessBitBuffer *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vidmemAccessBitBufControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle vidmemAccessBitBufGetInternalObjectHandle_DISPATCH(struct VidmemAccessBitBuffer *pGpuResource) { return pGpuResource->__vidmemAccessBitBufGetInternalObjectHandle__(pGpuResource); } @@ -303,6 +304,10 @@ static inline NvBool vidmemAccessBitBufCanCopy_DISPATCH(struct VidmemAccessBitBu return pResource->__vidmemAccessBitBufCanCopy__(pResource); } +static inline NvBool vidmemAccessBitBufIsPartialUnmapSupported_DISPATCH(struct VidmemAccessBitBuffer *pResource) { + return pResource->__vidmemAccessBitBufIsPartialUnmapSupported__(pResource); +} + static inline void vidmemAccessBitBufPreDestruct_DISPATCH(struct VidmemAccessBitBuffer *pResource) { pResource->__vidmemAccessBitBufPreDestruct__(pResource); } diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c index e84daf6234..52e5562175 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.c @@ -275,23 +275,31 @@ void __nvoc_init_VirtMemAllocator(VirtMemAllocator *pThis, RmHalspecOwner *pRmha __nvoc_init_funcTable_VirtMemAllocator(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; VirtMemAllocator *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtMemAllocator), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(VirtMemAllocator)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtMemAllocator); pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); @@ -309,16 +317,25 @@ NV_STATUS __nvoc_objCreate_VirtMemAllocator(VirtMemAllocator **ppThis, Dynamic * status = __nvoc_ctor_VirtMemAllocator(pThis, pRmhalspecowner); if (status != NV_OK) goto __nvoc_objCreate_VirtMemAllocator_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_VirtMemAllocator_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_OBJENGSTATE.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(VirtMemAllocator)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h index 51872b6159..882c3be376 100644 --- a/src/nvidia/generated/g_virt_mem_allocator_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_allocator_nvoc.h @@ -7,7 +7,7 @@ extern "C" { #endif /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -88,11 +88,16 @@ typedef struct _def_dma_bar1p2p_mapping_params } DMA_BAR1P2P_MAPPING_PRARAMS; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VIRT_MEM_ALLOCATOR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct VirtMemAllocator { const struct NVOC_RTTI *__nvoc_rtti; struct OBJENGSTATE __nvoc_base_OBJENGSTATE; @@ -513,6 +518,12 @@ struct DMA_PAGE_ARRAY // page array operations void dmaPageArrayInit(DMA_PAGE_ARRAY *pPageArray, void *pPageData, NvU32 pageCount); + +#define DMA_PAGE_ARRAY_FLAGS_NONE 0ULL + +void dmaPageArrayInitWithFlags(DMA_PAGE_ARRAY *pPageArray, void *pPageData, NvU32 pageCount, + NvU64 flags); + void dmaPageArrayInitFromMemDesc(DMA_PAGE_ARRAY *pPageArray, MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation); diff --git a/src/nvidia/generated/g_virt_mem_mgr_nvoc.c b/src/nvidia/generated/g_virt_mem_mgr_nvoc.c index 2adccb09c3..c5ae70fab9 100644 --- a/src/nvidia/generated/g_virt_mem_mgr_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_mgr_nvoc.c @@ -103,21 +103,26 @@ void __nvoc_init_OBJVMM(OBJVMM *pThis) { __nvoc_init_funcTable_OBJVMM(pThis); } -NV_STATUS __nvoc_objCreate_OBJVMM(OBJVMM **ppThis, Dynamic *pParent, NvU32 createFlags) { +NV_STATUS __nvoc_objCreate_OBJVMM(OBJVMM **ppThis, Dynamic *pParent, NvU32 createFlags) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; OBJVMM *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(OBJVMM), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(OBJVMM)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_OBJVMM); pThis->__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -132,16 +137,25 @@ NV_STATUS __nvoc_objCreate_OBJVMM(OBJVMM **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_OBJVMM(pThis); if (status != NV_OK) goto __nvoc_objCreate_OBJVMM_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_OBJVMM_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(OBJVMM)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_virt_mem_mgr_nvoc.h b/src/nvidia/generated/g_virt_mem_mgr_nvoc.h index 6b721b98cb..726e590ebc 100644 --- a/src/nvidia/generated/g_virt_mem_mgr_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_mgr_nvoc.h @@ -53,11 +53,16 @@ typedef struct OBJVMM OBJVMM; + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VIRT_MEM_MGR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct OBJVMM { const struct NVOC_RTTI *__nvoc_rtti; struct Object __nvoc_base_Object; diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.c b/src/nvidia/generated/g_virt_mem_range_nvoc.c index a29bd470ea..4e42884cbf 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.c +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.c @@ -155,10 +155,6 @@ static void __nvoc_thunk_RmResource_vmrangeControl_Epilogue(struct VirtualMemory rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_vmrangeControlLookup(struct VirtualMemoryRange *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemoryRange_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_vmrangeControl(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), pCallContext, pParams); } @@ -187,6 +183,10 @@ static NvBool __nvoc_thunk_StandardMemory_vmrangeCanCopy(struct VirtualMemoryRan return stdmemCanCopy((struct StandardMemory *)(((unsigned char *)pStandardMemory) + __nvoc_rtti_VirtualMemoryRange_StandardMemory.offset)); } +static NvBool __nvoc_thunk_VirtualMemory_vmrangeIsPartialUnmapSupported(struct VirtualMemoryRange *pVirtualMemory) { + return virtmemIsPartialUnmapSupported((struct VirtualMemory *)(((unsigned char *)pVirtualMemory) + __nvoc_rtti_VirtualMemoryRange_VirtualMemory.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_vmrangeIsReady(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { return memIsReady((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemoryRange_Memory.offset), bCopyConstructorContext); } @@ -275,8 +275,6 @@ static void __nvoc_init_funcTable_VirtualMemoryRange_1(VirtualMemoryRange *pThis pThis->__vmrangeControl_Epilogue__ = &__nvoc_thunk_RmResource_vmrangeControl_Epilogue; - pThis->__vmrangeControlLookup__ = &__nvoc_thunk_RsResource_vmrangeControlLookup; - pThis->__vmrangeControl__ = &__nvoc_thunk_Memory_vmrangeControl; pThis->__vmrangeUnmap__ = &__nvoc_thunk_Memory_vmrangeUnmap; @@ -291,6 +289,8 @@ static void __nvoc_init_funcTable_VirtualMemoryRange_1(VirtualMemoryRange *pThis pThis->__vmrangeCanCopy__ = &__nvoc_thunk_StandardMemory_vmrangeCanCopy; + pThis->__vmrangeIsPartialUnmapSupported__ = &__nvoc_thunk_VirtualMemory_vmrangeIsPartialUnmapSupported; + pThis->__vmrangeIsReady__ = &__nvoc_thunk_Memory_vmrangeIsReady; pThis->__vmrangeCheckCopyPermissions__ = &__nvoc_thunk_Memory_vmrangeCheckCopyPermissions; @@ -324,21 +324,26 @@ void __nvoc_init_VirtualMemoryRange(VirtualMemoryRange *pThis) { __nvoc_init_funcTable_VirtualMemoryRange(pThis); } -NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; VirtualMemoryRange *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtualMemoryRange), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(VirtualMemoryRange)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtualMemoryRange); pThis->__nvoc_base_VirtualMemory.__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -353,16 +358,25 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange **ppThis, Dynam status = __nvoc_ctor_VirtualMemoryRange(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_VirtualMemoryRange_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_VirtualMemoryRange_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_VirtualMemory.__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(VirtualMemoryRange)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_virt_mem_range_nvoc.h b/src/nvidia/generated/g_virt_mem_range_nvoc.h index 2ab6b0ed05..ce83d95f84 100644 --- a/src/nvidia/generated/g_virt_mem_range_nvoc.h +++ b/src/nvidia/generated/g_virt_mem_range_nvoc.h @@ -42,11 +42,16 @@ extern "C" { * Describes a range of typeless virtual memory memory. Used as * a target space for RmMapMemoryDma. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VIRT_MEM_RANGE_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct VirtualMemoryRange { const struct NVOC_RTTI *__nvoc_rtti; struct VirtualMemory __nvoc_base_VirtualMemory; @@ -69,7 +74,6 @@ struct VirtualMemoryRange { NvBool (*__vmrangeIsGpuMapAllowed__)(struct VirtualMemoryRange *, struct OBJGPU *); NV_STATUS (*__vmrangeUnmapFrom__)(struct VirtualMemoryRange *, struct RS_RES_UNMAP_FROM_PARAMS *); void (*__vmrangeControl_Epilogue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__vmrangeControlLookup__)(struct VirtualMemoryRange *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__vmrangeControl__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vmrangeUnmap__)(struct VirtualMemoryRange *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__vmrangeGetMemInterMapParams__)(struct VirtualMemoryRange *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -77,6 +81,7 @@ struct VirtualMemoryRange { NV_STATUS (*__vmrangeControlFilter__)(struct VirtualMemoryRange *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__vmrangeControlSerialization_Prologue__)(struct VirtualMemoryRange *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__vmrangeCanCopy__)(struct VirtualMemoryRange *); + NvBool (*__vmrangeIsPartialUnmapSupported__)(struct VirtualMemoryRange *); NV_STATUS (*__vmrangeIsReady__)(struct VirtualMemoryRange *, NvBool); NV_STATUS (*__vmrangeCheckCopyPermissions__)(struct VirtualMemoryRange *, struct OBJGPU *, struct Device *); void (*__vmrangePreDestruct__)(struct VirtualMemoryRange *); @@ -125,7 +130,6 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange**, Dynamic*, Nv #define vmrangeIsGpuMapAllowed(pMemory, pGpu) vmrangeIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define vmrangeUnmapFrom(pVirtualMemory, pParams) vmrangeUnmapFrom_DISPATCH(pVirtualMemory, pParams) #define vmrangeControl_Epilogue(pResource, pCallContext, pParams) vmrangeControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define vmrangeControlLookup(pResource, pParams, ppEntry) vmrangeControlLookup_DISPATCH(pResource, pParams, ppEntry) #define vmrangeControl(pMemory, pCallContext, pParams) vmrangeControl_DISPATCH(pMemory, pCallContext, pParams) #define vmrangeUnmap(pMemory, pCallContext, pCpuMapping) vmrangeUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define vmrangeGetMemInterMapParams(pMemory, pParams) vmrangeGetMemInterMapParams_DISPATCH(pMemory, pParams) @@ -133,6 +137,7 @@ NV_STATUS __nvoc_objCreate_VirtualMemoryRange(VirtualMemoryRange**, Dynamic*, Nv #define vmrangeControlFilter(pResource, pCallContext, pParams) vmrangeControlFilter_DISPATCH(pResource, pCallContext, pParams) #define vmrangeControlSerialization_Prologue(pResource, pCallContext, pParams) vmrangeControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define vmrangeCanCopy(pStandardMemory) vmrangeCanCopy_DISPATCH(pStandardMemory) +#define vmrangeIsPartialUnmapSupported(pVirtualMemory) vmrangeIsPartialUnmapSupported_DISPATCH(pVirtualMemory) #define vmrangeIsReady(pMemory, bCopyConstructorContext) vmrangeIsReady_DISPATCH(pMemory, bCopyConstructorContext) #define vmrangeCheckCopyPermissions(pMemory, pDstGpu, pDstDevice) vmrangeCheckCopyPermissions_DISPATCH(pMemory, pDstGpu, pDstDevice) #define vmrangePreDestruct(pResource) vmrangePreDestruct_DISPATCH(pResource) @@ -184,10 +189,6 @@ static inline void vmrangeControl_Epilogue_DISPATCH(struct VirtualMemoryRange *p pResource->__vmrangeControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS vmrangeControlLookup_DISPATCH(struct VirtualMemoryRange *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__vmrangeControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS vmrangeControl_DISPATCH(struct VirtualMemoryRange *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__vmrangeControl__(pMemory, pCallContext, pParams); } @@ -216,6 +217,10 @@ static inline NvBool vmrangeCanCopy_DISPATCH(struct VirtualMemoryRange *pStandar return pStandardMemory->__vmrangeCanCopy__(pStandardMemory); } +static inline NvBool vmrangeIsPartialUnmapSupported_DISPATCH(struct VirtualMemoryRange *pVirtualMemory) { + return pVirtualMemory->__vmrangeIsPartialUnmapSupported__(pVirtualMemory); +} + static inline NV_STATUS vmrangeIsReady_DISPATCH(struct VirtualMemoryRange *pMemory, NvBool bCopyConstructorContext) { return pMemory->__vmrangeIsReady__(pMemory, bCopyConstructorContext); } diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.c b/src/nvidia/generated/g_virtual_mem_nvoc.c index 8f68959439..c9ef183f99 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.c +++ b/src/nvidia/generated/g_virtual_mem_nvoc.c @@ -110,6 +110,10 @@ static NV_STATUS __nvoc_thunk_VirtualMemory_resUnmapFrom(struct RsResource *pVir return virtmemUnmapFrom((struct VirtualMemory *)(((unsigned char *)pVirtualMemory) - __nvoc_rtti_VirtualMemory_RsResource.offset), pParams); } +static NvBool __nvoc_thunk_VirtualMemory_resIsPartialUnmapSupported(struct RsResource *pVirtualMemory) { + return virtmemIsPartialUnmapSupported((struct VirtualMemory *)(((unsigned char *)pVirtualMemory) - __nvoc_rtti_VirtualMemory_RsResource.offset)); +} + static NV_STATUS __nvoc_thunk_Memory_virtmemCheckMemInterUnmap(struct VirtualMemory *pMemory, NvBool bSubdeviceHandleProvided) { return memCheckMemInterUnmap((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), bSubdeviceHandleProvided); } @@ -146,10 +150,6 @@ static void __nvoc_thunk_RmResource_virtmemControl_Epilogue(struct VirtualMemory rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_virtmemControlLookup(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_VirtualMemory_RsResource.offset), pParams, ppEntry); -} - static NV_STATUS __nvoc_thunk_Memory_virtmemControl(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return memControl((struct Memory *)(((unsigned char *)pMemory) + __nvoc_rtti_VirtualMemory_Memory.offset), pCallContext, pParams); } @@ -249,10 +249,14 @@ static void __nvoc_init_funcTable_VirtualMemory_1(VirtualMemory *pThis) { pThis->__virtmemUnmapFrom__ = &virtmemUnmapFrom_IMPL; + pThis->__virtmemIsPartialUnmapSupported__ = &virtmemIsPartialUnmapSupported_0c883b; + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resMapTo__ = &__nvoc_thunk_VirtualMemory_resMapTo; pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resUnmapFrom__ = &__nvoc_thunk_VirtualMemory_resUnmapFrom; + pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__resIsPartialUnmapSupported__ = &__nvoc_thunk_VirtualMemory_resIsPartialUnmapSupported; + pThis->__virtmemCheckMemInterUnmap__ = &__nvoc_thunk_Memory_virtmemCheckMemInterUnmap; pThis->__virtmemShareCallback__ = &__nvoc_thunk_RmResource_virtmemShareCallback; @@ -271,8 +275,6 @@ static void __nvoc_init_funcTable_VirtualMemory_1(VirtualMemory *pThis) { pThis->__virtmemControl_Epilogue__ = &__nvoc_thunk_RmResource_virtmemControl_Epilogue; - pThis->__virtmemControlLookup__ = &__nvoc_thunk_RsResource_virtmemControlLookup; - pThis->__virtmemControl__ = &__nvoc_thunk_Memory_virtmemControl; pThis->__virtmemUnmap__ = &__nvoc_thunk_Memory_virtmemUnmap; @@ -319,21 +321,26 @@ void __nvoc_init_VirtualMemory(VirtualMemory *pThis) { __nvoc_init_funcTable_VirtualMemory(pThis); } -NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory **ppThis, Dynamic *pParent, NvU32 createFlags, CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; VirtualMemory *pThis; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(VirtualMemory), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(VirtualMemory)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_VirtualMemory); pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; + // Link the child into the parent if there is one unless flagged not to do so. if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); @@ -348,16 +355,25 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory **ppThis, Dynamic *pParen status = __nvoc_ctor_VirtualMemory(pThis, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_VirtualMemory_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_VirtualMemory_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_StandardMemory.__nvoc_base_Memory.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(VirtualMemory)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_virtual_mem_nvoc.h b/src/nvidia/generated/g_virtual_mem_nvoc.h index 3b209ea6a7..c988263c9f 100644 --- a/src/nvidia/generated/g_virtual_mem_nvoc.h +++ b/src/nvidia/generated/g_virtual_mem_nvoc.h @@ -45,11 +45,16 @@ extern "C" { * * The NV01_MEMORY_VIRTUAL subclass class is typeless. */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_VIRTUAL_MEM_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct VirtualMemory { const struct NVOC_RTTI *__nvoc_rtti; struct StandardMemory __nvoc_base_StandardMemory; @@ -62,6 +67,7 @@ struct VirtualMemory { struct VirtualMemory *__nvoc_pbase_VirtualMemory; NV_STATUS (*__virtmemMapTo__)(struct VirtualMemory *, struct RS_RES_MAP_TO_PARAMS *); NV_STATUS (*__virtmemUnmapFrom__)(struct VirtualMemory *, struct RS_RES_UNMAP_FROM_PARAMS *); + NvBool (*__virtmemIsPartialUnmapSupported__)(struct VirtualMemory *); NV_STATUS (*__virtmemCheckMemInterUnmap__)(struct VirtualMemory *, NvBool); NvBool (*__virtmemShareCallback__)(struct VirtualMemory *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); NV_STATUS (*__virtmemGetMapAddrSpace__)(struct VirtualMemory *, CALL_CONTEXT *, NvU32, NV_ADDRESS_SPACE *); @@ -71,7 +77,6 @@ struct VirtualMemory { NV_STATUS (*__virtmemControl_Prologue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__virtmemIsGpuMapAllowed__)(struct VirtualMemory *, struct OBJGPU *); void (*__virtmemControl_Epilogue__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__virtmemControlLookup__)(struct VirtualMemory *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NV_STATUS (*__virtmemControl__)(struct VirtualMemory *, CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__virtmemUnmap__)(struct VirtualMemory *, CALL_CONTEXT *, RsCpuMapping *); NV_STATUS (*__virtmemGetMemInterMapParams__)(struct VirtualMemory *, RMRES_MEM_INTER_MAP_PARAMS *); @@ -125,6 +130,7 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory**, Dynamic*, NvU32, CALL_ #define virtmemMapTo(pVirtualMemory, pParams) virtmemMapTo_DISPATCH(pVirtualMemory, pParams) #define virtmemUnmapFrom(pVirtualMemory, pParams) virtmemUnmapFrom_DISPATCH(pVirtualMemory, pParams) +#define virtmemIsPartialUnmapSupported(pVirtualMemory) virtmemIsPartialUnmapSupported_DISPATCH(pVirtualMemory) #define virtmemCheckMemInterUnmap(pMemory, bSubdeviceHandleProvided) virtmemCheckMemInterUnmap_DISPATCH(pMemory, bSubdeviceHandleProvided) #define virtmemShareCallback(pResource, pInvokingClient, pParentRef, pSharePolicy) virtmemShareCallback_DISPATCH(pResource, pInvokingClient, pParentRef, pSharePolicy) #define virtmemGetMapAddrSpace(pMemory, pCallContext, mapFlags, pAddrSpace) virtmemGetMapAddrSpace_DISPATCH(pMemory, pCallContext, mapFlags, pAddrSpace) @@ -134,7 +140,6 @@ NV_STATUS __nvoc_objCreate_VirtualMemory(VirtualMemory**, Dynamic*, NvU32, CALL_ #define virtmemControl_Prologue(pResource, pCallContext, pParams) virtmemControl_Prologue_DISPATCH(pResource, pCallContext, pParams) #define virtmemIsGpuMapAllowed(pMemory, pGpu) virtmemIsGpuMapAllowed_DISPATCH(pMemory, pGpu) #define virtmemControl_Epilogue(pResource, pCallContext, pParams) virtmemControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define virtmemControlLookup(pResource, pParams, ppEntry) virtmemControlLookup_DISPATCH(pResource, pParams, ppEntry) #define virtmemControl(pMemory, pCallContext, pParams) virtmemControl_DISPATCH(pMemory, pCallContext, pParams) #define virtmemUnmap(pMemory, pCallContext, pCpuMapping) virtmemUnmap_DISPATCH(pMemory, pCallContext, pCpuMapping) #define virtmemGetMemInterMapParams(pMemory, pParams) virtmemGetMemInterMapParams_DISPATCH(pMemory, pParams) @@ -161,6 +166,14 @@ static inline NV_STATUS virtmemUnmapFrom_DISPATCH(struct VirtualMemory *pVirtual return pVirtualMemory->__virtmemUnmapFrom__(pVirtualMemory, pParams); } +static inline NvBool virtmemIsPartialUnmapSupported_0c883b(struct VirtualMemory *pVirtualMemory) { + return ((NvBool)(0 == 0)); +} + +static inline NvBool virtmemIsPartialUnmapSupported_DISPATCH(struct VirtualMemory *pVirtualMemory) { + return pVirtualMemory->__virtmemIsPartialUnmapSupported__(pVirtualMemory); +} + static inline NV_STATUS virtmemCheckMemInterUnmap_DISPATCH(struct VirtualMemory *pMemory, NvBool bSubdeviceHandleProvided) { return pMemory->__virtmemCheckMemInterUnmap__(pMemory, bSubdeviceHandleProvided); } @@ -197,10 +210,6 @@ static inline void virtmemControl_Epilogue_DISPATCH(struct VirtualMemory *pResou pResource->__virtmemControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS virtmemControlLookup_DISPATCH(struct VirtualMemory *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__virtmemControlLookup__(pResource, pParams, ppEntry); -} - static inline NV_STATUS virtmemControl_DISPATCH(struct VirtualMemory *pMemory, CALL_CONTEXT *pCallContext, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { return pMemory->__virtmemControl__(pMemory, pCallContext, pParams); } diff --git a/src/nvidia/generated/g_zbc_api_nvoc.c b/src/nvidia/generated/g_zbc_api_nvoc.c index 641523029e..a48f87cdf8 100644 --- a/src/nvidia/generated/g_zbc_api_nvoc.c +++ b/src/nvidia/generated/g_zbc_api_nvoc.c @@ -137,10 +137,6 @@ static void __nvoc_thunk_RmResource_zbcapiControl_Epilogue(struct ZbcApi *pResou rmresControl_Epilogue((struct RmResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RmResource.offset), pCallContext, pParams); } -static NV_STATUS __nvoc_thunk_RsResource_zbcapiControlLookup(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return resControlLookup((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset), pParams, ppEntry); -} - static NvHandle __nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle(struct ZbcApi *pGpuResource) { return gpuresGetInternalObjectHandle((struct GpuResource *)(((unsigned char *)pGpuResource) + __nvoc_rtti_ZbcApi_GpuResource.offset)); } @@ -173,6 +169,10 @@ static NvBool __nvoc_thunk_RsResource_zbcapiCanCopy(struct ZbcApi *pResource) { return resCanCopy((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); } +static NvBool __nvoc_thunk_RsResource_zbcapiIsPartialUnmapSupported(struct ZbcApi *pResource) { + return resIsPartialUnmapSupported((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); +} + static void __nvoc_thunk_RsResource_zbcapiPreDestruct(struct ZbcApi *pResource) { resPreDestruct((struct RsResource *)(((unsigned char *)pResource) + __nvoc_rtti_ZbcApi_RsResource.offset)); } @@ -275,12 +275,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_ZbcApi[] #endif }, { /* [5] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) /*pFunc=*/ (void (*)(void)) NULL, #else - /*pFunc=*/ (void (*)(void)) zbcapiCtrlCmdGetZbcClearTableSize_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - /*flags=*/ 0x210u, + /*pFunc=*/ (void (*)(void)) zbcapiCtrlCmdGetZbcClearTableSize_DISPATCH, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x400210u) + /*flags=*/ 0x400210u, /*accessRight=*/0x0u, /*methodId=*/ 0x90960106u, /*paramSize=*/ sizeof(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS), @@ -376,9 +376,15 @@ static void __nvoc_init_funcTable_ZbcApi_1(ZbcApi *pThis, RmHalspecOwner *pRmhal pThis->__zbcapiCtrlCmdSetZbcStencilClear__ = &zbcapiCtrlCmdSetZbcStencilClear_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) - pThis->__zbcapiCtrlCmdGetZbcClearTableSize__ = &zbcapiCtrlCmdGetZbcClearTableSize_IMPL; -#endif + // Hal function -- zbcapiCtrlCmdGetZbcClearTableSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */ + { + pThis->__zbcapiCtrlCmdGetZbcClearTableSize__ = &zbcapiCtrlCmdGetZbcClearTableSize_VF; + } + else + { + pThis->__zbcapiCtrlCmdGetZbcClearTableSize__ = &zbcapiCtrlCmdGetZbcClearTableSize_5baef9; + } #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) pThis->__zbcapiCtrlCmdGetZbcClearTableEntry__ = &zbcapiCtrlCmdGetZbcClearTableEntry_IMPL; @@ -406,8 +412,6 @@ static void __nvoc_init_funcTable_ZbcApi_1(ZbcApi *pThis, RmHalspecOwner *pRmhal pThis->__zbcapiControl_Epilogue__ = &__nvoc_thunk_RmResource_zbcapiControl_Epilogue; - pThis->__zbcapiControlLookup__ = &__nvoc_thunk_RsResource_zbcapiControlLookup; - pThis->__zbcapiGetInternalObjectHandle__ = &__nvoc_thunk_GpuResource_zbcapiGetInternalObjectHandle; pThis->__zbcapiControl__ = &__nvoc_thunk_GpuResource_zbcapiControl; @@ -424,6 +428,8 @@ static void __nvoc_init_funcTable_ZbcApi_1(ZbcApi *pThis, RmHalspecOwner *pRmhal pThis->__zbcapiCanCopy__ = &__nvoc_thunk_RsResource_zbcapiCanCopy; + pThis->__zbcapiIsPartialUnmapSupported__ = &__nvoc_thunk_RsResource_zbcapiIsPartialUnmapSupported; + pThis->__zbcapiPreDestruct__ = &__nvoc_thunk_RsResource_zbcapiPreDestruct; pThis->__zbcapiIsDuplicate__ = &__nvoc_thunk_RsResource_zbcapiIsDuplicate; @@ -451,23 +457,31 @@ void __nvoc_init_ZbcApi(ZbcApi *pThis, RmHalspecOwner *pRmhalspecowner) { __nvoc_init_funcTable_ZbcApi(pThis, pRmhalspecowner); } -NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) { +NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi **ppThis, Dynamic *pParent, NvU32 createFlags, struct CALL_CONTEXT * arg_pCallContext, struct RS_RES_ALLOC_PARAMS_INTERNAL * arg_pParams) +{ NV_STATUS status; - Object *pParentObj; + Object *pParentObj = NULL; ZbcApi *pThis; RmHalspecOwner *pRmhalspecowner; + // Assign `pThis`, allocating memory unless suppressed by flag. status = __nvoc_handleObjCreateMemAlloc(createFlags, sizeof(ZbcApi), (void**)&pThis, (void**)ppThis); if (status != NV_OK) return status; + // Zero is the initial value for everything. portMemSet(pThis, 0, sizeof(ZbcApi)); + // Initialize runtime type information. __nvoc_initRtti(staticCast(pThis, Dynamic), &__nvoc_class_def_ZbcApi); pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object.createFlags = createFlags; - if (pParent != NULL && !(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) + // pParent must be a valid object that derives from a halspec owner class. + NV_ASSERT_OR_RETURN(pParent != NULL, NV_ERR_INVALID_ARGUMENT); + + // Link the child into the parent unless flagged not to do so. + if (!(createFlags & NVOC_OBJ_CREATE_FLAGS_PARENT_HALSPEC_ONLY)) { pParentObj = dynamicCast(pParent, Object); objAddChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); @@ -485,16 +499,25 @@ NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi **ppThis, Dynamic *pParent, NvU32 creat status = __nvoc_ctor_ZbcApi(pThis, pRmhalspecowner, arg_pCallContext, arg_pParams); if (status != NV_OK) goto __nvoc_objCreate_ZbcApi_cleanup; + // Assignment has no effect if NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT is set. *ppThis = pThis; return NV_OK; __nvoc_objCreate_ZbcApi_cleanup: - // do not call destructors here since the constructor already called them + + // Unlink the child from the parent if it was linked above. + if (pParentObj != NULL) + objRemoveChild(pParentObj, &pThis->__nvoc_base_GpuResource.__nvoc_base_RmResource.__nvoc_base_RsResource.__nvoc_base_Object); + + // Do not call destructors here since the constructor already called them. if (createFlags & NVOC_OBJ_CREATE_FLAGS_IN_PLACE_CONSTRUCT) portMemSet(pThis, 0, sizeof(ZbcApi)); else + { portMemFree(pThis); + *ppThis = NULL; + } // coverity[leaked_storage:FALSE] return status; diff --git a/src/nvidia/generated/g_zbc_api_nvoc.h b/src/nvidia/generated/g_zbc_api_nvoc.h index 858728ce53..7421cc2b93 100644 --- a/src/nvidia/generated/g_zbc_api_nvoc.h +++ b/src/nvidia/generated/g_zbc_api_nvoc.h @@ -42,11 +42,16 @@ extern "C" { /*! * RM internal class representing GF100_ZBC_CLEAR */ + +// Private field names are wrapped in PRIVATE_FIELD, which does nothing for +// the matching C source file, but causes diagnostics to be issued if another +// source file references the field. #ifdef NVOC_ZBC_API_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x) #endif + struct ZbcApi { const struct NVOC_RTTI *__nvoc_rtti; struct GpuResource __nvoc_base_GpuResource; @@ -74,7 +79,6 @@ struct ZbcApi { NV_STATUS (*__zbcapiInternalControlForward__)(struct ZbcApi *, NvU32, void *, NvU32); NV_STATUS (*__zbcapiUnmapFrom__)(struct ZbcApi *, RS_RES_UNMAP_FROM_PARAMS *); void (*__zbcapiControl_Epilogue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); - NV_STATUS (*__zbcapiControlLookup__)(struct ZbcApi *, struct RS_RES_CONTROL_PARAMS_INTERNAL *, const struct NVOC_EXPORTED_METHOD_DEF **); NvHandle (*__zbcapiGetInternalObjectHandle__)(struct ZbcApi *); NV_STATUS (*__zbcapiControl__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__zbcapiUnmap__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RsCpuMapping *); @@ -83,6 +87,7 @@ struct ZbcApi { NV_STATUS (*__zbcapiControlFilter__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NV_STATUS (*__zbcapiControlSerialization_Prologue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); NvBool (*__zbcapiCanCopy__)(struct ZbcApi *); + NvBool (*__zbcapiIsPartialUnmapSupported__)(struct ZbcApi *); void (*__zbcapiPreDestruct__)(struct ZbcApi *); NV_STATUS (*__zbcapiIsDuplicate__)(struct ZbcApi *, NvHandle, NvBool *); void (*__zbcapiControlSerialization_Epilogue__)(struct ZbcApi *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); @@ -125,6 +130,7 @@ NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define zbcapiCtrlCmdSetZbcClearTable(pZbcApi, pSetZBCClearTableParams) zbcapiCtrlCmdSetZbcClearTable_DISPATCH(pZbcApi, pSetZBCClearTableParams) #define zbcapiCtrlCmdSetZbcStencilClear(pZbcApi, pSetZBCClearParams) zbcapiCtrlCmdSetZbcStencilClear_DISPATCH(pZbcApi, pSetZBCClearParams) #define zbcapiCtrlCmdGetZbcClearTableSize(pZbcApi, pGetZBCClearTableSizeParams) zbcapiCtrlCmdGetZbcClearTableSize_DISPATCH(pZbcApi, pGetZBCClearTableSizeParams) +#define zbcapiCtrlCmdGetZbcClearTableSize_HAL(pZbcApi, pGetZBCClearTableSizeParams) zbcapiCtrlCmdGetZbcClearTableSize_DISPATCH(pZbcApi, pGetZBCClearTableSizeParams) #define zbcapiCtrlCmdGetZbcClearTableEntry(pZbcApi, pGetZBCClearTableEntryParams) zbcapiCtrlCmdGetZbcClearTableEntry_DISPATCH(pZbcApi, pGetZBCClearTableEntryParams) #define zbcapiShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) zbcapiShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) #define zbcapiCheckMemInterUnmap(pRmResource, bSubdeviceHandleProvided) zbcapiCheckMemInterUnmap_DISPATCH(pRmResource, bSubdeviceHandleProvided) @@ -137,7 +143,6 @@ NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define zbcapiInternalControlForward(pGpuResource, command, pParams, size) zbcapiInternalControlForward_DISPATCH(pGpuResource, command, pParams, size) #define zbcapiUnmapFrom(pResource, pParams) zbcapiUnmapFrom_DISPATCH(pResource, pParams) #define zbcapiControl_Epilogue(pResource, pCallContext, pParams) zbcapiControl_Epilogue_DISPATCH(pResource, pCallContext, pParams) -#define zbcapiControlLookup(pResource, pParams, ppEntry) zbcapiControlLookup_DISPATCH(pResource, pParams, ppEntry) #define zbcapiGetInternalObjectHandle(pGpuResource) zbcapiGetInternalObjectHandle_DISPATCH(pGpuResource) #define zbcapiControl(pGpuResource, pCallContext, pParams) zbcapiControl_DISPATCH(pGpuResource, pCallContext, pParams) #define zbcapiUnmap(pGpuResource, pCallContext, pCpuMapping) zbcapiUnmap_DISPATCH(pGpuResource, pCallContext, pCpuMapping) @@ -146,6 +151,7 @@ NV_STATUS __nvoc_objCreate_ZbcApi(ZbcApi**, Dynamic*, NvU32, struct CALL_CONTEXT #define zbcapiControlFilter(pResource, pCallContext, pParams) zbcapiControlFilter_DISPATCH(pResource, pCallContext, pParams) #define zbcapiControlSerialization_Prologue(pResource, pCallContext, pParams) zbcapiControlSerialization_Prologue_DISPATCH(pResource, pCallContext, pParams) #define zbcapiCanCopy(pResource) zbcapiCanCopy_DISPATCH(pResource) +#define zbcapiIsPartialUnmapSupported(pResource) zbcapiIsPartialUnmapSupported_DISPATCH(pResource) #define zbcapiPreDestruct(pResource) zbcapiPreDestruct_DISPATCH(pResource) #define zbcapiIsDuplicate(pResource, hMemory, pDuplicate) zbcapiIsDuplicate_DISPATCH(pResource, hMemory, pDuplicate) #define zbcapiControlSerialization_Epilogue(pResource, pCallContext, pParams) zbcapiControlSerialization_Epilogue_DISPATCH(pResource, pCallContext, pParams) @@ -203,7 +209,11 @@ static inline NV_STATUS zbcapiCtrlCmdSetZbcStencilClear_DISPATCH(struct ZbcApi * return pZbcApi->__zbcapiCtrlCmdSetZbcStencilClear__(pZbcApi, pSetZBCClearParams); } -NV_STATUS zbcapiCtrlCmdGetZbcClearTableSize_IMPL(struct ZbcApi *pZbcApi, NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *pGetZBCClearTableSizeParams); +NV_STATUS zbcapiCtrlCmdGetZbcClearTableSize_VF(struct ZbcApi *pZbcApi, NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *pGetZBCClearTableSizeParams); + +static inline NV_STATUS zbcapiCtrlCmdGetZbcClearTableSize_5baef9(struct ZbcApi *pZbcApi, NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *pGetZBCClearTableSizeParams) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} static inline NV_STATUS zbcapiCtrlCmdGetZbcClearTableSize_DISPATCH(struct ZbcApi *pZbcApi, NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *pGetZBCClearTableSizeParams) { return pZbcApi->__zbcapiCtrlCmdGetZbcClearTableSize__(pZbcApi, pGetZBCClearTableSizeParams); @@ -259,10 +269,6 @@ static inline void zbcapiControl_Epilogue_DISPATCH(struct ZbcApi *pResource, str pResource->__zbcapiControl_Epilogue__(pResource, pCallContext, pParams); } -static inline NV_STATUS zbcapiControlLookup_DISPATCH(struct ZbcApi *pResource, struct RS_RES_CONTROL_PARAMS_INTERNAL *pParams, const struct NVOC_EXPORTED_METHOD_DEF **ppEntry) { - return pResource->__zbcapiControlLookup__(pResource, pParams, ppEntry); -} - static inline NvHandle zbcapiGetInternalObjectHandle_DISPATCH(struct ZbcApi *pGpuResource) { return pGpuResource->__zbcapiGetInternalObjectHandle__(pGpuResource); } @@ -295,6 +301,10 @@ static inline NvBool zbcapiCanCopy_DISPATCH(struct ZbcApi *pResource) { return pResource->__zbcapiCanCopy__(pResource); } +static inline NvBool zbcapiIsPartialUnmapSupported_DISPATCH(struct ZbcApi *pResource) { + return pResource->__zbcapiIsPartialUnmapSupported__(pResource); +} + static inline void zbcapiPreDestruct_DISPATCH(struct ZbcApi *pResource) { pResource->__zbcapiPreDestruct__(pResource); } diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index b9a9887041..81db377a0a 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -225,8 +225,6 @@ // #define RMCFG_FEATURE_PLATFORM_UNKNOWN 0 // Running on an unknown platform #define RMCFG_FEATURE_PLATFORM_WINDOWS 0 // Running on Windows -#define RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM 0 // Running on Windows LDDM -#define RMCFG_FEATURE_PLATFORM_WINDOWS_VISTA 0 // aka PLATFORM_WINDOWS_LDDM #define RMCFG_FEATURE_PLATFORM_UNIX 1 // Running on Unix #define RMCFG_FEATURE_PLATFORM_DCE 0 // Running on Display Control Engine (DCE, an ARM Cortex R5 on Tegra) #define RMCFG_FEATURE_PLATFORM_SIM 0 // Running on Simulator @@ -270,6 +268,7 @@ #define RMCFG_FEATURE_DCE_CLIENT_RM 0 // DCE client RM #define RMCFG_FEATURE_PROTOBUF 1 // Protobuf data encoding for OCA data dumps #define RMCFG_FEATURE_RELEASE_BUILD 1 // Release Build +#define RMCFG_FEATURE_RM_NEW_TRACER_ETW 0 // New Event Tracing for Windows (ETW) in RM #define RMCFG_FEATURE_VERIF_ONLY_CONTROLS 0 // Allow verify only control cmds to be used on verif builds (determined by this feature) #define RMCFG_FEATURE_PAGE_RETIREMENT 1 // Offlining bad memory pages from the FB heap #define RMCFG_FEATURE_PMA 1 // Physical memory allocator @@ -289,6 +288,7 @@ #define RMCFG_FEATURE_SYNC_GPU_BOOST 1 // Synchronized GPU Boost #define RMCFG_FEATURE_NVSR_ON_NVDISPLAY 1 // NVSR on Nvdisplay #define RMCFG_FEATURE_MODS_FEATURES 0 // Flag for enabling MODS required features in RM +#define RMCFG_FEATURE_MULTINODE_FABRIC_IMEX 1 // Multinode fabric memory import/export support #define RMCFG_FEATURE_MANUAL_TRIGGER_BA_DMA_MODE 0 // Support for manually actuated BA DMA mode data collection. #define RMCFG_FEATURE_RM_DRIVEN_BA_DMA_MODE 0 // Support for RM-driven BA DMA mode data collection. #define RMCFG_FEATURE_VBLANK_CALLBACK 1 // Vblank callback functionality within RM @@ -344,15 +344,13 @@ #define RMCFG_CLASS_NV01_MEMORY_LIST_SYSTEM 1 #define RMCFG_CLASS_NV01_MEMORY_LIST_FBMEM 1 #define RMCFG_CLASS_NV01_MEMORY_LIST_OBJECT 1 -#define RMCFG_CLASS_NV_IMEX_SESSION 0 +#define RMCFG_CLASS_NV_IMEX_SESSION 1 #define RMCFG_CLASS_NV01_MEMORY_FLA 1 -#define RMCFG_CLASS_NV_MEMORY_EXPORT 0 -#define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORT_V2 0 +#define RMCFG_CLASS_NV_MEMORY_EXPORT 1 #define RMCFG_CLASS_NV_CE_UTILS 1 #define RMCFG_CLASS_NV_MEMORY_FABRIC 1 -#define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORT_V2 0 -#define RMCFG_CLASS_NV_MEMORY_FABRIC_EXPORTED_REF 0 -#define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORTED_REF 0 +#define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORT_V2 1 +#define RMCFG_CLASS_NV_MEMORY_FABRIC_IMPORTED_REF 1 #define RMCFG_CLASS_FABRIC_VASPACE_A 1 #define RMCFG_CLASS_NV_MEMORY_MULTICAST_FABRIC 1 #define RMCFG_CLASS_NV_FB_SEGMENT 0 @@ -526,11 +524,14 @@ #define RMCFG_CLASS_GT200_DEBUGGER 1 // CUDA Debugger support #define RMCFG_CLASS_NV40_I2C 1 // I2C operations #define RMCFG_CLASS_NV_E3_THREED 0 // Tegra 3D class +#define RMCFG_CLASS_KEPLER_DEVICE_VGPU 1 // KEPLER virtual gpu #define RMCFG_CLASS_NVA081_VGPU_CONFIG 1 // virtual gpu configuration #define RMCFG_CLASS_NVA084_KERNEL_HOST_VGPU_DEVICE 1 // Kernel component of the host virtual gpu device #define RMCFG_CLASS_NV0060_SYNC_GPU_BOOST 1 // Synchronized GPU Boost Class. Defines a set of GPUs for Synchronized Boost #define RMCFG_CLASS_GP100_UVM_SW 1 // UVM SW class to support SW methods for fault cancel +#define RMCFG_CLASS_NVENC_SW_SESSION 1 // GPU NVENC Software Session #define RMCFG_CLASS_NV_EVENT_BUFFER 1 // Event buffer class used to share event data with UMD +#define RMCFG_CLASS_NVFBC_SW_SESSION 1 // GPU NVFBC Software Session #define RMCFG_CLASS_NV_CONFIDENTIAL_COMPUTE 1 // Confidential Computing Class #define RMCFG_CLASS_NV_COUNTER_COLLECTION_UNIT 1 // Counter Collection Unit Class #define RMCFG_CLASS_NV_SEMAPHORE_SURFACE 1 // GPU Semaphore encapsulation class @@ -650,6 +651,7 @@ #define RMCFG_MODULE_CG 1 // Clock Gating Object Engine. #define RMCFG_MODULE_RPPG 1 // RAM Periphery Power Gating Object Engine. #define RMCFG_MODULE_EI 1 // Engine Idle Framework Object Engine. +#define RMCFG_MODULE_LPWR_SEQ 1 // LPWR Unified Sequencer Feature for Power Gating #define RMCFG_MODULE_DPU 0 // Display Falcon #define RMCFG_MODULE_PMGR 0 // PCB Manager engine #define RMCFG_MODULE_KERNEL_PMGR 1 // Kernel controls for Pmgr @@ -701,18 +703,16 @@ #define RMCFG_MODULE_HWPM 0 // Hardware Performance Monitor #define RMCFG_MODULE_NVLINK 0 // NVLINK High-speed GPU interconnect #define RMCFG_MODULE_KERNEL_NVLINK 1 // Nvlink on Kernel(CPU) RM -#define RMCFG_MODULE_KERNEL_NVLINK 1 // Nvlink on Kernel(CPU) RM #define RMCFG_MODULE_IOCTRL 0 // NVLINK Ioctrl #define RMCFG_MODULE_HSHUB 0 // High Speed Hub #define RMCFG_MODULE_HSHUBMANAGER 0 // High Speed Hub Manager #define RMCFG_MODULE_KERNEL_HSHUB 1 // High Speed Hub on Kernel(CPU) RM -#define RMCFG_MODULE_KERNEL_HSHUB 1 // High Speed Hub on Kernel(CPU) RM #define RMCFG_MODULE_GPUMON 1 // GPU Monitoring #define RMCFG_MODULE_GPUBOOSTMGR 1 // Sync Gpu Boost Manager #define RMCFG_MODULE_GRIDDISPLAYLESS 0 // GRID Displayless #define RMCFG_MODULE_WINDOW 0 // NvDisplay WINDOW channel #define RMCFG_MODULE_RPC 1 // RPC Engine for VGPU -#define RMCFG_MODULE_RPCSTRUCTURECOPY 0 // RPC structure copying for VGPU +#define RMCFG_MODULE_RPCSTRUCTURECOPY 1 // RPC structure copying for VGPU #define RMCFG_MODULE_NVJPG 0 // Video JPEG (NVJPG) Engine #define RMCFG_MODULE_KERNEL_NVJPG 1 #define RMCFG_MODULE_KERNEL_FSP 1 // FSP on Kernel(CPU) RM @@ -818,6 +818,11 @@ #define RMCFG_API_NV_ESC_RM_UNMAP_MEMORY_DMA 1 // aka NV04_UNMAP_MEMORY_DMA #define RMCFG_API_Nv04UnmapMemoryDma 1 // aka NV04_UNMAP_MEMORY_DMA #define RMCFG_API_NvRmUnmapMemoryDma 1 // aka NV04_UNMAP_MEMORY_DMA +#define RMCFG_API_NV04_UNMAP_MEMORY_DMA2 1 +#define RMCFG_API_NVOS47_PARAMETERS 1 // aka NV04_UNMAP_MEMORY_DMA2 +#define RMCFG_API_NV_ESC_RM_UNMAP_MEMORY_DMA 1 // aka NV04_UNMAP_MEMORY_DMA2 +#define RMCFG_API_Nv04UnmapMemoryDmaPartial 1 // aka NV04_UNMAP_MEMORY_DMA2 +#define RMCFG_API_NvRmUnmapMemoryDmaPartial 1 // aka NV04_UNMAP_MEMORY_DMA2 #define RMCFG_API_NV04_ALLOC_CONTEXT_DMA 1 #define RMCFG_API_NVOS39_PARAMETERS 1 // aka NV04_ALLOC_CONTEXT_DMA #define RMCFG_API_NV_ESC_RM_ALLOC_CONTEXT_DMA2 1 // aka NV04_ALLOC_CONTEXT_DMA diff --git a/src/nvidia/inc/kernel/compute/imex_session_api.h b/src/nvidia/inc/kernel/compute/imex_session_api.h new file mode 100644 index 0000000000..ef727dd47e --- /dev/null +++ b/src/nvidia/inc/kernel/compute/imex_session_api.h @@ -0,0 +1,3 @@ + +#include "g_imex_session_api_nvoc.h" + diff --git a/src/nvidia/inc/kernel/core/bin_data.h b/src/nvidia/inc/kernel/core/bin_data.h index 019dd4b5c2..3c9c78d6cf 100644 --- a/src/nvidia/inc/kernel/core/bin_data.h +++ b/src/nvidia/inc/kernel/core/bin_data.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -64,7 +64,11 @@ void bindataRelease(PBINDATA_RUNTIME_INFO pBinInfo); // NV_STATUS bindataWriteToBuffer(const BINDATA_STORAGE *pBinStorage, NvU8 *pBuffer, NvU32 bufferSize); NvU32 bindataGetBufferSize(const BINDATA_STORAGE *pBinStorage); +NV_STATUS bindataStorageAcquireData(const BINDATA_STORAGE *pBinStorage, const void **ppData); +void bindataStorageReleaseData(void *pData); +void bindataInitialize(void); +void bindataDestroy(void); // // Bindata Archive support diff --git a/src/nvidia/inc/kernel/core/info_block.h b/src/nvidia/inc/kernel/core/info_block.h index f77da15663..d32f98b455 100644 --- a/src/nvidia/inc/kernel/core/info_block.h +++ b/src/nvidia/inc/kernel/core/info_block.h @@ -23,26 +23,14 @@ #ifndef _INFO_BLOCK_H_ #define _INFO_BLOCK_H_ +#include "nvtypes.h" + // // HAL privata data management. // typedef struct ENG_INFO_LINK_NODE *PENG_INFO_LINK_NODE; typedef struct ENG_INFO_LINK_NODE ENG_INFO_LINK_NODE; -// new style typedef for info block functions, simple typedef. -// Used by hal .def files via INFO_BLOCK_GROUP template in Gpuhal.def -typedef void *EngGetInfoBlockFn(PENG_INFO_LINK_NODE pHead, NvU32 dataId); -typedef void *EngAddInfoBlockFn(PENG_INFO_LINK_NODE *ppHead, NvU32 dataId, NvU32 size); -typedef void EngDeleteInfoBlockFn(PENG_INFO_LINK_NODE *ppHead, NvU32 dataId); -typedef NvBool EngTestInfoBlockFn(PENG_INFO_LINK_NODE pHead, NvU32 dataId); - -// old style typedef for info block functions (ptr to fn) -// delete these 4 typedefs once all .def files converted to use OBJECT_INTERFACES -typedef EngGetInfoBlockFn *EngGetInfoBlock; -typedef EngAddInfoBlockFn *EngAddInfoBlock; -typedef EngDeleteInfoBlockFn *EngDeleteInfoBlock; -typedef EngTestInfoBlockFn *EngTestInfoBlock; - struct ENG_INFO_LINK_NODE { diff --git a/src/nvidia/inc/kernel/core/locks.h b/src/nvidia/inc/kernel/core/locks.h index e39dedda7a..2f84bf13d6 100644 --- a/src/nvidia/inc/kernel/core/locks.h +++ b/src/nvidia/inc/kernel/core/locks.h @@ -111,6 +111,9 @@ typedef struct // Attempt acquire even if it potentially violates the locking order // But do not block in a way that could cause a deadlock #define GPU_LOCK_FLAGS_SAFE_LOCK_UPGRADE NVBIT(2) +// Additionally acquire the GPU alloc lock (implied if locking all GPUs) +// to prevent the set of lockable GPUs from changing +#define GPU_LOCK_FLAGS_LOCK_ALLOC NVBIT(3) // // RM Lock Related Functions diff --git a/src/nvidia/inc/kernel/core/printf.h b/src/nvidia/inc/kernel/core/printf.h index 36168ae378..9fe54b93b2 100644 --- a/src/nvidia/inc/kernel/core/printf.h +++ b/src/nvidia/inc/kernel/core/printf.h @@ -138,7 +138,6 @@ void osFlushLog(void); #define DBG_BREAKPOINT() DBG_BREAKPOINT_EX(NULL, 0) -#define DBG_BREAKPOINT_EX_ARGS_IGNORED 1 #define REL_DBG_BREAKPOINT_MSG(msg) \ do \ { \ @@ -150,7 +149,6 @@ void osFlushLog(void); #define DBG_BREAKPOINT() #define DBG_BREAKPOINT_EX(PGPU, LEVEL) -#define DBG_BREAKPOINT_EX_ARGS_IGNORED 1 #define REL_DBG_BREAKPOINT_MSG(msg) \ do \ @@ -228,70 +226,6 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length); #define DBG_RMMSG_CHECK(level) (0) #endif // NV_PRINTF_STRINGS_ALLOWED - - -//****************************************************************************** -// POWER SANITY CHECKS -//****************************************************************************** -// -// Make sure the GPU is in full power or resuming from D3 state. Else, -// bailout from the calling function. An exception for systems, which support -// surprise removal feature. See Bugs 440565, 479003, and 499228.DO NOT IGNORE -// OR REMOVE THIS ASSERT. If you have problems with it, please talk to cplummer. -// -// bAllowWithoutSysmemAccess: Allow this RM Control when sysmem access is not available -// from the GPU. SHould be NV_TRUE only for NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS -// -// On systems supporting surprise removal, if the GPU is in D3 cold -// and still attached we would consider it a true D3 cold state -// and return NOT_FULL_POWER. See bug 1679965. -// -// -#define API_GPU_FULL_POWER_SANITY_CHECK(pGpu, bGpuAccess, bAllowWithoutSysmemAccess) \ - if ((!gpuIsGpuFullPower(pGpu)) && \ - (!(pGpu)->getProperty((pGpu), \ - PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ - { \ - DBG_BREAKPOINT(); \ - if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ - } \ - else if (gpuIsSurpriseRemovalSupported(pGpu) && \ - (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ - } \ - } \ - if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ - } - -#define API_GPU_FULL_POWER_SANITY_CHECK_OR_GOTO(pGpu, bGpuAccess, bAllowWithoutSysmemAccess, status, tag) \ - if ((!gpuIsGpuFullPower(pGpu)) && \ - (!(pGpu)->getProperty((pGpu), \ - PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))) \ - { \ - DBG_BREAKPOINT(); \ - if (bGpuAccess || (!gpuIsSurpriseRemovalSupported(pGpu))) \ - { \ - status = NV_ERR_GPU_NOT_FULL_POWER; \ - goto tag; \ - } \ - else if (gpuIsSurpriseRemovalSupported(pGpu) && \ - (pGpu)->getProperty((pGpu), PDB_PROP_GPU_IS_CONNECTED)) \ - { \ - status = NV_ERR_GPU_NOT_FULL_POWER; \ - goto tag; \ - } \ - } \ - if (!(bAllowWithoutSysmemAccess) && !gpuCheckSysmemAccess(pGpu)) \ - { \ - return NV_ERR_GPU_NOT_FULL_POWER; \ - } - - #if defined(PORT_IS_FUNC_SUPPORTED) #if PORT_IS_FUNC_SUPPORTED(portMemExValidate) #define DBG_VAL_PTR(p) portMemExValidate(p, NV_TRUE) @@ -301,13 +235,19 @@ void nvDbgDumpBufferBytes(void *pBuffer, NvU32 length); #define DBG_VAL_PTR(p) #endif +#define NV_ERROR_LOG(pGpu, num, fmt, ...) \ + nvErrorLog_va((void*)pGpu, num, fmt, ##__VA_ARGS__); \ + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \ + NV_PRINTF_ADD_PREFIX("Xid %d: " fmt), num, ##__VA_ARGS__) + +#define NV_ERROR_LOG_DATA(pGpu, num, fmt, ...) \ + portDbgPrintf(NV_PRINTF_ADD_PREFIX(fmt), ##__VA_ARGS__); \ + NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, \ + NV_PRINTF_ADD_PREFIX(fmt), ##__VA_ARGS__) void nvErrorLog(void *pVoid, NvU32 num, const char *pFormat, va_list arglist); void nvErrorLog_va(void * pGpu, NvU32 num, const char * pFormat, ...); -// memory allocation tracking data structs and globals -#define MAX_STACK_LEVEL 6 - #ifdef __cplusplus } #endif diff --git a/src/nvidia/inc/kernel/disp/nvfbc_session.h b/src/nvidia/inc/kernel/disp/nvfbc_session.h new file mode 100644 index 0000000000..1a0da76105 --- /dev/null +++ b/src/nvidia/inc/kernel/disp/nvfbc_session.h @@ -0,0 +1,3 @@ + +#include "g_nvfbc_session_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h index cc843e8b6e..abf1bb7178 100644 --- a/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h +++ b/src/nvidia/inc/kernel/gpu/ce/kernel_ce_private.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,7 +28,8 @@ #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" -#define CE_GET_LOWEST_AVAILABLE_IDX(x) portUtilCountTrailingZeros32(x) +#define CE_GET_LOWEST_AVAILABLE_IDX(x) \ + (x == 0 || x == 0xFFFFFFFF) ? 0xFFFFFFFF : portUtilCountTrailingZeros32(x) /*! * @brief Obtain relative CE index. @@ -55,14 +56,17 @@ NV_STATUS ceIndexFromType(OBJGPU *pGpu, Device *pDevice, RM_ENGINE_TYPE rmEngine { KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); MIG_INSTANCE_REF ref; + NvBool bEnginePresent; status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); - if (status != NV_OK) return status; - status = kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, rmEngineType, &localRmEngType); + bEnginePresent = kmigmgrIsLocalEngineInInstance(pGpu, pKernelMIGManager, rmEngineType, ref); + if (!bEnginePresent) + return NV_ERR_INVALID_ARGUMENT; + status = kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, rmEngineType, &localRmEngType); if (status != NV_OK) return status; } diff --git a/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h b/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h index a71d402d96..a85322f52e 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h +++ b/src/nvidia/inc/kernel/gpu/gpu_acpi_data.h @@ -33,6 +33,14 @@ #define MAX_DSM_SUPPORTED_FUNCS_RTN_LEN 8 // # bytes to store supported functions +/* Indicates the current state of mux */ +typedef enum +{ + dispMuxState_None = 0, + dispMuxState_IntegratedGPU, + dispMuxState_DiscreteGPU, +} DISPMUXSTATE; + typedef struct { // supported function status and cache NvU32 suppFuncStatus; @@ -88,6 +96,7 @@ typedef struct MUX_METHOD_DATA NvU32 tableLen; MUX_METHOD_DATA_ELEMENT acpiIdMuxModeTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; MUX_METHOD_DATA_ELEMENT acpiIdMuxPartTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; + MUX_METHOD_DATA_ELEMENT acpiIdMuxStateTable[NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS]; } MUX_METHOD_DATA; typedef struct CAPS_METHOD_DATA diff --git a/src/nvidia/inc/kernel/gpu/gpu_child_list.h b/src/nvidia/inc/kernel/gpu/gpu_child_list.h index 1eed847071..c4d7feb2f2 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_child_list.h +++ b/src/nvidia/inc/kernel/gpu/gpu_child_list.h @@ -199,7 +199,7 @@ GPU_CHILD_SINGLE_INST( OBJRC, GPU_GET_RC, 1, NV_FALSE, pRC ) #endif #if GPU_CHILD_MODULE(STEREO) - GPU_CHILD_SINGLE_INST( OBJSTEREO, GPU_GET_STEREO, 1, NV_FALSE, pStereo ) + GPU_CHILD_SINGLE_INST( Stereo, GPU_GET_STEREO, 1, NV_FALSE, pStereo ) #endif #if GPU_CHILD_MODULE(INTR) GPU_CHILD_SINGLE_INST( Intr, GPU_GET_INTR, 1, NV_FALSE, pIntr ) @@ -276,6 +276,9 @@ #if GPU_CHILD_MODULE(HWPM) GPU_CHILD_SINGLE_INST( OBJHWPM, GPU_GET_HWPM, 1, NV_FALSE, pHwpm ) #endif +#if GPU_CHILD_MODULE(KERNEL_HWPM) + GPU_CHILD_SINGLE_INST( KernelHwpm, GPU_GET_KERNEL_HWPM, 1, NV_FALSE, pKernelHwpm ) +#endif #if GPU_CHILD_MODULE(GRIDDISPLAYLESS) GPU_CHILD_SINGLE_INST( OBJGRIDDISPLAYLESS, GPU_GET_GRIDDISPLAYLESS, 1, NV_FALSE, pGridDisplayless ) #endif @@ -295,7 +298,7 @@ GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, pKernelFsp ) #endif #if GPU_CHILD_MODULE(OFA) - GPU_CHILD_MULTI_INST( OBJOFA, GPU_GET_OFA, GPU_MAX_OFAS, NV_FALSE, pOfa ) + GPU_CHILD_MULTI_INST( OBJOFA, GPU_GET_OFA, GPU_MAX_OFAS, NV_FALSE, pOfa ) #endif #if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE) GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute ) diff --git a/src/nvidia/inc/kernel/gpu/gpu_engine_type.h b/src/nvidia/inc/kernel/gpu/gpu_engine_type.h index 441f8fef96..2f31e0cd44 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_engine_type.h +++ b/src/nvidia/inc/kernel/gpu/gpu_engine_type.h @@ -71,30 +71,31 @@ typedef enum RM_ENGINE_TYPE_NVENC0 = (0x00000025), RM_ENGINE_TYPE_NVENC1 = (0x00000026), RM_ENGINE_TYPE_NVENC2 = (0x00000027), - RM_ENGINE_TYPE_VP = (0x00000028), - RM_ENGINE_TYPE_ME = (0x00000029), - RM_ENGINE_TYPE_PPP = (0x0000002a), - RM_ENGINE_TYPE_MPEG = (0x0000002b), - RM_ENGINE_TYPE_SW = (0x0000002c), - RM_ENGINE_TYPE_TSEC = (0x0000002d), - RM_ENGINE_TYPE_VIC = (0x0000002e), - RM_ENGINE_TYPE_MP = (0x0000002f), - RM_ENGINE_TYPE_SEC2 = (0x00000030), - RM_ENGINE_TYPE_HOST = (0x00000031), - RM_ENGINE_TYPE_DPU = (0x00000032), - RM_ENGINE_TYPE_PMU = (0x00000033), - RM_ENGINE_TYPE_FBFLCN = (0x00000034), - RM_ENGINE_TYPE_NVJPEG0 = (0x00000035), - RM_ENGINE_TYPE_NVJPEG1 = (0x00000036), - RM_ENGINE_TYPE_NVJPEG2 = (0x00000037), - RM_ENGINE_TYPE_NVJPEG3 = (0x00000038), - RM_ENGINE_TYPE_NVJPEG4 = (0x00000039), - RM_ENGINE_TYPE_NVJPEG5 = (0x0000003a), - RM_ENGINE_TYPE_NVJPEG6 = (0x0000003b), - RM_ENGINE_TYPE_NVJPEG7 = (0x0000003c), - RM_ENGINE_TYPE_OFA0 = (0x0000003d), - RM_ENGINE_TYPE_RESERVED3e = (0x0000003e), - RM_ENGINE_TYPE_LAST = (0x0000003f), + RM_ENGINE_TYPE_RESERVED28 = (0x00000028), + RM_ENGINE_TYPE_VP = (0x00000029), + RM_ENGINE_TYPE_ME = (0x0000002a), + RM_ENGINE_TYPE_PPP = (0x0000002b), + RM_ENGINE_TYPE_MPEG = (0x0000002c), + RM_ENGINE_TYPE_SW = (0x0000002d), + RM_ENGINE_TYPE_TSEC = (0x0000002e), + RM_ENGINE_TYPE_VIC = (0x0000002f), + RM_ENGINE_TYPE_MP = (0x00000030), + RM_ENGINE_TYPE_SEC2 = (0x00000031), + RM_ENGINE_TYPE_HOST = (0x00000032), + RM_ENGINE_TYPE_DPU = (0x00000033), + RM_ENGINE_TYPE_PMU = (0x00000034), + RM_ENGINE_TYPE_FBFLCN = (0x00000035), + RM_ENGINE_TYPE_NVJPEG0 = (0x00000036), + RM_ENGINE_TYPE_NVJPEG1 = (0x00000037), + RM_ENGINE_TYPE_NVJPEG2 = (0x00000038), + RM_ENGINE_TYPE_NVJPEG3 = (0x00000039), + RM_ENGINE_TYPE_NVJPEG4 = (0x0000003a), + RM_ENGINE_TYPE_NVJPEG5 = (0x0000003b), + RM_ENGINE_TYPE_NVJPEG6 = (0x0000003c), + RM_ENGINE_TYPE_NVJPEG7 = (0x0000003d), + RM_ENGINE_TYPE_OFA0 = (0x0000003e), + RM_ENGINE_TYPE_RESERVED3f = (0x0000003f), + RM_ENGINE_TYPE_LAST = (0x00000040), } RM_ENGINE_TYPE; // diff --git a/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h b/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h index 54e83a0e18..06aefd2fd3 100644 --- a/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h +++ b/src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h @@ -26,6 +26,7 @@ #include "nvlink_inband_msg.h" +#include "ctrl/ctrl2080/ctrl2080nvlink.h" #define GPU_FABRIC_PROBE_SEC_TO_NS 1000000000ULL @@ -53,6 +54,7 @@ NV_STATUS gpuFabricProbeGetFlaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 NV_STATUS gpuFabricProbeGetFlaAddressRange(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pFlaAddressRange); NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes); NV_STATUS gpuFabricProbeGetFabricCliqueId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricCliqueId); +NV_STATUS gpuFabricProbeGetFabricHealthStatus(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricHealthStatusMask); NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel); @@ -61,4 +63,14 @@ NvBool gpuFabricProbeIsSupported(OBJGPU *pGpu); NV_STATUS gpuFabricProbeSetBwMode(NvU8 mode); NV_STATUS gpuFabricProbeGetlinkMaskToBeReduced(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, NvU32 *linkMaskToBeReduced); +NV_STATUS gpuFabricProbeReceiveUpdateKernelCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams); +NV_STATUS gpuFabricProbeReceiveKernelCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams); +NV_STATUS gpuFabricProbeReceivePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams); +NV_STATUS gpuFabricProbeReceiveUpdatePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams); + + #endif // GPU_FABRIC_PROBE_H diff --git a/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h b/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h index 3fda944adb..2554f47e67 100644 --- a/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h +++ b/src/nvidia/inc/kernel/gpu/gr/kernel_graphics_context_buffers.h @@ -59,7 +59,8 @@ NV_ENUM_DEF(GR_GLOBALCTX_BUFFER, GR_GLOBALCTX_BUFFER_DEF) NV_ENUM_ENTRY(x, GR_CTX_BUFFER_BETA_CB, 0x00000005) \ NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PAGEPOOL, 0x00000006) \ NV_ENUM_ENTRY(x, GR_CTX_BUFFER_RTV_CB, 0x00000007) \ - NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PATCH, 0x00000008) + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_PATCH, 0x00000008) \ + NV_ENUM_ENTRY(x, GR_CTX_BUFFER_SETUP, 0x00000009) NV_ENUM_DEF(GR_CTX_BUFFER, GR_CTX_BUFFER_DEF) diff --git a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h index 6632ed1636..5d4a3a3647 100644 --- a/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h @@ -27,8 +27,7 @@ // // This header describes the set of static GPU configuration information // that is collected during GSP RM init and made available to the -// CPU RM (aka GSP client) via the NV_RM_RPC_GET_STATIC_INFO() and -// NV_RM_RPC_GET_GSP_STATIC_INFO() calls. +// CPU RM (aka GSP client) via NV_RM_RPC_GET_GSP_STATIC_INFO() call. #include "ctrl/ctrl0080/ctrl0080gpu.h" #include "ctrl/ctrl0080/ctrl0080gr.h" @@ -78,7 +77,6 @@ typedef struct GspStaticConfigInfo_t NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS zcullInfo[MAX_GPC_COUNT]; NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo; NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams; - COMPUTE_BRANDING_TYPE computeBranding; NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps; NvU32 sriovMaxGfid; @@ -155,6 +153,7 @@ typedef struct GspSystemInfo NvU64 gpuPhysInstAddr; NvU64 nvDomainBusDeviceFunc; NvU64 simAccessBufPhysAddr; + NvU64 notifyOpSharedSurfacePhysAddr; NvU64 pcieAtomicsOpMask; NvU64 consoleMemSize; NvU64 maxUserVa; @@ -171,6 +170,7 @@ typedef struct GspSystemInfo NvBool bUpstreamL1Unsupported; NvBool bUpstreamL1PorSupported; NvBool bUpstreamL1PorMobileOnly; + NvBool bSystemHasMux; NvU8 upstreamAddressValid; BUSINFO FHBBusInfo; BUSINFO chipsetIDInfo; @@ -179,6 +179,7 @@ typedef struct GspSystemInfo NvBool bIsPassthru; NvU64 sysTimerOffsetNs; GSP_VF_INFO gspVFInfo; + NvBool isGridBuild; } GspSystemInfo; diff --git a/kernel-open/common/inc/nv-register-module.h b/src/nvidia/inc/kernel/gpu/gsp/gsp_trace_rats_macro.h similarity index 57% rename from kernel-open/common/inc/nv-register-module.h rename to src/nvidia/inc/kernel/gpu/gsp/gsp_trace_rats_macro.h index bd4545f603..3f415c379a 100644 --- a/kernel-open/common/inc/nv-register-module.h +++ b/src/nvidia/inc/kernel/gpu/gsp/gsp_trace_rats_macro.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,35 +21,24 @@ * DEALINGS IN THE SOFTWARE. */ +/* + * This file defines macros to place tracepoints for RATS (RM All-around Trace + * System). The names of the functions and variables associated with this are + * temporary as we begin to unify all RM tracing tools under one system. + */ -#ifndef _NV_REGISTER_MODULE_H_ -#define _NV_REGISTER_MODULE_H_ - -#include -#include -#include - -#include "nvtypes.h" - -typedef struct nvidia_module_s { - struct module *owner; - - /* nvidia0, nvidia1 ..*/ - const char *module_name; +#ifndef GSP_TRACE_RATS_MACRO_H +#define GSP_TRACE_RATS_MACRO_H - /* module instance */ - NvU32 instance; +#include "core/core.h" - /* file operations */ - int (*open)(struct inode *, struct file *filp); - int (*close)(struct inode *, struct file *filp); - int (*mmap)(struct file *filp, struct vm_area_struct *vma); - int (*ioctl)(struct inode *, struct file * file, unsigned int cmd, unsigned long arg); - unsigned int (*poll)(struct file * file, poll_table *wait); +#define GSP_TRACING_RATS_ENABLED 0 +#define GSP_TRACE_RATS_ADD_RECORD(recordIdentifier, pGpu, info) (void) 0 -} nvidia_module_t; +#define KERNEL_GSP_TRACING_RATS_ENABLED 0 -int nvidia_register_module(nvidia_module_t *); -int nvidia_unregister_module(nvidia_module_t *); +#ifndef GET_RATS_TIMESTAMP_NS +#define GET_RATS_TIMESTAMP_NS() NV_ASSERT(0) +#endif #endif diff --git a/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm.h b/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm.h new file mode 100644 index 0000000000..0278c4a060 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm.h @@ -0,0 +1,3 @@ + +#include "g_kern_hwpm_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm_common_defs.h b/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm_common_defs.h new file mode 100644 index 0000000000..4df5b6052d --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm_common_defs.h @@ -0,0 +1,3 @@ + +#include "g_kern_hwpm_common_defs_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm_power.h b/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm_power.h new file mode 100644 index 0000000000..98aa8b7e68 --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/hwpm/kern_hwpm_power.h @@ -0,0 +1,3 @@ + +#include "g_kern_hwpm_power_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h index 464549e001..7e119fa042 100644 --- a/src/nvidia/inc/kernel/gpu/intr/engine_idx.h +++ b/src/nvidia/inc/kernel/gpu/intr/engine_idx.h @@ -78,79 +78,82 @@ #define MC_ENGINE_IDX_NVENC 38 #define MC_ENGINE_IDX_NVENC1 39 #define MC_ENGINE_IDX_NVENC2 40 -#define MC_ENGINE_IDX_C2C 41 -#define MC_ENGINE_IDX_LTC 42 -#define MC_ENGINE_IDX_FBHUB 43 -#define MC_ENGINE_IDX_HDACODEC 44 -#define MC_ENGINE_IDX_GMMU 45 -#define MC_ENGINE_IDX_SEC2 46 -#define MC_ENGINE_IDX_FSP 47 -#define MC_ENGINE_IDX_NVLINK 48 -#define MC_ENGINE_IDX_GSP 49 -#define MC_ENGINE_IDX_NVJPG 50 +#define MC_ENGINE_IDX_RESERVED41 41 +#define MC_ENGINE_IDX_C2C 42 +#define MC_ENGINE_IDX_LTC 43 +#define MC_ENGINE_IDX_FBHUB 44 +#define MC_ENGINE_IDX_HDACODEC 45 +#define MC_ENGINE_IDX_GMMU 46 +#define MC_ENGINE_IDX_SEC2 47 +#define MC_ENGINE_IDX_FSP 48 +#define MC_ENGINE_IDX_NVLINK 49 +#define MC_ENGINE_IDX_GSP 50 +#define MC_ENGINE_IDX_NVJPG 51 #define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG #define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG -#define MC_ENGINE_IDX_NVJPEG1 51 -#define MC_ENGINE_IDX_NVJPEG2 52 -#define MC_ENGINE_IDX_NVJPEG3 53 -#define MC_ENGINE_IDX_NVJPEG4 54 -#define MC_ENGINE_IDX_NVJPEG5 55 -#define MC_ENGINE_IDX_NVJPEG6 56 -#define MC_ENGINE_IDX_NVJPEG7 57 -#define MC_ENGINE_IDX_REPLAYABLE_FAULT 58 -#define MC_ENGINE_IDX_ACCESS_CNTR 59 -#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 60 -#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 61 -#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 62 -#define MC_ENGINE_IDX_INFO_FAULT 63 -#define MC_ENGINE_IDX_BSP 64 +#define MC_ENGINE_IDX_NVJPEG1 52 +#define MC_ENGINE_IDX_NVJPEG2 53 +#define MC_ENGINE_IDX_NVJPEG3 54 +#define MC_ENGINE_IDX_NVJPEG4 55 +#define MC_ENGINE_IDX_NVJPEG5 56 +#define MC_ENGINE_IDX_NVJPEG6 57 +#define MC_ENGINE_IDX_NVJPEG7 58 +#define MC_ENGINE_IDX_REPLAYABLE_FAULT 59 +#define MC_ENGINE_IDX_ACCESS_CNTR 60 +#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT 61 +#define MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR 62 +#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR 63 +#define MC_ENGINE_IDX_INFO_FAULT 64 +#define MC_ENGINE_IDX_BSP 65 #define MC_ENGINE_IDX_NVDEC MC_ENGINE_IDX_BSP #define MC_ENGINE_IDX_NVDEC0 MC_ENGINE_IDX_NVDEC -#define MC_ENGINE_IDX_NVDEC1 65 -#define MC_ENGINE_IDX_NVDEC2 66 -#define MC_ENGINE_IDX_NVDEC3 67 -#define MC_ENGINE_IDX_NVDEC4 68 -#define MC_ENGINE_IDX_NVDEC5 69 -#define MC_ENGINE_IDX_NVDEC6 70 -#define MC_ENGINE_IDX_NVDEC7 71 -#define MC_ENGINE_IDX_CPU_DOORBELL 72 -#define MC_ENGINE_IDX_PRIV_DOORBELL 73 -#define MC_ENGINE_IDX_MMU_ECC_ERROR 74 -#define MC_ENGINE_IDX_BLG 75 -#define MC_ENGINE_IDX_PERFMON 76 -#define MC_ENGINE_IDX_BUF_RESET 77 -#define MC_ENGINE_IDX_XBAR 78 -#define MC_ENGINE_IDX_ZPW 79 -#define MC_ENGINE_IDX_OFA0 80 -#define MC_ENGINE_IDX_RESERVED81 81 -#define MC_ENGINE_IDX_TEGRA 82 -#define MC_ENGINE_IDX_GR 83 +#define MC_ENGINE_IDX_NVDEC1 66 +#define MC_ENGINE_IDX_NVDEC2 67 +#define MC_ENGINE_IDX_NVDEC3 68 +#define MC_ENGINE_IDX_NVDEC4 69 +#define MC_ENGINE_IDX_NVDEC5 70 +#define MC_ENGINE_IDX_NVDEC6 71 +#define MC_ENGINE_IDX_NVDEC7 72 +#define MC_ENGINE_IDX_CPU_DOORBELL 73 +#define MC_ENGINE_IDX_PRIV_DOORBELL 74 +#define MC_ENGINE_IDX_MMU_ECC_ERROR 75 +#define MC_ENGINE_IDX_BLG 76 +#define MC_ENGINE_IDX_PERFMON 77 +#define MC_ENGINE_IDX_BUF_RESET 78 +#define MC_ENGINE_IDX_XBAR 79 +#define MC_ENGINE_IDX_ZPW 80 +#define MC_ENGINE_IDX_OFA0 81 +#define MC_ENGINE_IDX_RESERVED81 82 +#define MC_ENGINE_IDX_TEGRA 83 +#define MC_ENGINE_IDX_GR 84 #define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR -#define MC_ENGINE_IDX_GR1 84 -#define MC_ENGINE_IDX_GR2 85 -#define MC_ENGINE_IDX_GR3 86 -#define MC_ENGINE_IDX_GR4 87 -#define MC_ENGINE_IDX_GR5 88 -#define MC_ENGINE_IDX_GR6 89 -#define MC_ENGINE_IDX_GR7 90 -#define MC_ENGINE_IDX_ESCHED 91 +#define MC_ENGINE_IDX_GR1 85 +#define MC_ENGINE_IDX_GR2 86 +#define MC_ENGINE_IDX_GR3 87 +#define MC_ENGINE_IDX_GR4 88 +#define MC_ENGINE_IDX_GR5 89 +#define MC_ENGINE_IDX_GR6 90 +#define MC_ENGINE_IDX_GR7 91 +#define MC_ENGINE_IDX_ESCHED 92 #define MC_ENGINE_IDX_ESCHED__SIZE 64 -#define MC_ENGINE_IDX_GR_FECS_LOG 155 +#define MC_ENGINE_IDX_GR_FECS_LOG 156 #define MC_ENGINE_IDX_GR0_FECS_LOG MC_ENGINE_IDX_GR_FECS_LOG -#define MC_ENGINE_IDX_GR1_FECS_LOG 156 -#define MC_ENGINE_IDX_GR2_FECS_LOG 157 -#define MC_ENGINE_IDX_GR3_FECS_LOG 158 -#define MC_ENGINE_IDX_GR4_FECS_LOG 159 -#define MC_ENGINE_IDX_GR5_FECS_LOG 160 -#define MC_ENGINE_IDX_GR6_FECS_LOG 161 -#define MC_ENGINE_IDX_GR7_FECS_LOG 162 -#define MC_ENGINE_IDX_TMR_SWRL 163 -#define MC_ENGINE_IDX_DISP_GSP 164 -#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 165 -#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 166 -#define MC_ENGINE_IDX_PXUC 167 +#define MC_ENGINE_IDX_GR1_FECS_LOG 157 +#define MC_ENGINE_IDX_GR2_FECS_LOG 158 +#define MC_ENGINE_IDX_GR3_FECS_LOG 159 +#define MC_ENGINE_IDX_GR4_FECS_LOG 160 +#define MC_ENGINE_IDX_GR5_FECS_LOG 161 +#define MC_ENGINE_IDX_GR6_FECS_LOG 162 +#define MC_ENGINE_IDX_GR7_FECS_LOG 163 +#define MC_ENGINE_IDX_TMR_SWRL 164 +#define MC_ENGINE_IDX_DISP_GSP 165 +#define MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU 166 +#define MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_CPU 167 +#define MC_ENGINE_IDX_PXUC 168 +#define MC_ENGINE_IDX_SYSLTC 169 +#define MC_ENGINE_IDX_LRCC 170 // This must be kept as the max bit if we need to add more engines -#define MC_ENGINE_IDX_MAX 168 +#define MC_ENGINE_IDX_MAX 171 // Index GR reference #define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x)) diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h b/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h index 6ec30074a4..001120f519 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/ce_utils.h @@ -1,121 +1,3 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ #include "g_ce_utils_nvoc.h" -#ifndef CE_UTILS_H -#define CE_UTILS_H - -#include "gpu/gpu_resource.h" // GpuResource -#include "class/cl0050.h" -#include "ctrl/ctrl0050.h" - -#include "kernel/gpu/mem_mgr/channel_utils.h" - -typedef struct -{ - MEMORY_DESCRIPTOR *pMemDesc; - NvU64 offset; - NvU64 length; - NvU32 pattern; - NvU64 flags; - NvU64 submittedWorkId; // Payload to poll for async completion -} CEUTILS_MEMSET_PARAMS; - -typedef struct -{ - MEMORY_DESCRIPTOR *pSrcMemDesc; - MEMORY_DESCRIPTOR *pDstMemDesc; - NvU64 dstOffset; - NvU64 srcOffset; - NvU64 length; - NvU64 flags; - NvU64 submittedWorkId; // Payload to poll for async completion -} CEUTILS_MEMCOPY_PARAMS; - -class KernelChannel; - -NVOC_PREFIX(ceutils) class CeUtils : Object -{ -public: - NV_STATUS ceutilsConstruct(CeUtils *pCeUtils, OBJGPU *pGpu, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance, - NV0050_ALLOCATION_PARAMETERS *pAllocParams); - void ceutilsDestruct(CeUtils *pCeUtils); - - NV_STATUS ceutilsMemset(CeUtils *pCeUtils, CEUTILS_MEMSET_PARAMS *pParams); - NV_STATUS ceutilsMemcopy(CeUtils *pCeUtils, CEUTILS_MEMCOPY_PARAMS *pParams); - - NvU64 ceutilsUpdateProgress(CeUtils *pCeUtils); - void ceutilsServiceInterrupts(CeUtils *pCeUtils); - - // - // Internal states - // - - NvHandle hClient; - NvHandle hDevice; - NvHandle hSubdevice; - - OBJCHANNEL *pChannel; - OBJGPU *pGpu; - - KernelCE *pKCe; - NvBool bUseVasForCeCopy; - NvU32 hTdCopyClass; - NvU64 lastSubmittedPayload; - NvU64 lastCompletedPayload; - - // Only used by fifo lite implementation - KernelChannel *pLiteKernelChannel; -}; - - -#if defined(DEBUG) || defined (DEVELOP) -NVOC_PREFIX(ceutilsapi) class CeUtilsApi : GpuResource -{ -public: - NV_STATUS ceutilsapiConstruct(CeUtilsApi *pCeUtilsApi, CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams) - : GpuResource(pCallContext, pParams); - - void ceutilsapiDestruct(CeUtilsApi *pCeUtilsApi); - - // - // Below APIs are only provided for SRT testing, thus only available for debug or - // develop driver builds - // - // - RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMSET, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) - NV_STATUS ceutilsapiCtrlCmdMemset(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMSET_PARAMS *pParams); - - RMCTRL_EXPORT(NV0050_CTRL_CMD_MEMCOPY, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) - NV_STATUS ceutilsapiCtrlCmdMemcopy(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_MEMCOPY_PARAMS *pParams); - - RMCTRL_EXPORT(NV0050_CTRL_CMD_CHECK_PROGRESS, RMCTRL_FLAGS(PRIVILEGED, API_LOCK_READONLY)) - NV_STATUS ceutilsapiCtrlCmdCheckProgress(CeUtilsApi *pCeUtilsApi, NV0050_CTRL_CHECK_PROGRESS_PARAMS *pParams); - - CeUtils *pCeUtils; -}; -#endif - -#endif // CE_UTILS_H diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h index d68a34d936..0da2fdd320 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h @@ -127,9 +127,6 @@ NV_STATUS scrubberConstruct(struct OBJGPU *pGpu, struct Heap *pHeap); * */ -NV_STATUS vgpuAllocGuestPmaScrubberSharedBuffer(struct OBJGPU *pGpu, OBJMEMSCRUB *pScrubber); -void vgpuFreeGuestPmaScrubberSharedBuffer(struct OBJGPU *pGpu, OBJMEMSCRUB *pScrubber); - void scrubberDestruct(struct OBJGPU *pGpu, struct Heap *pHeap, OBJMEMSCRUB *pMemscrub); diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h deleted file mode 100644 index 685cbbaf7e..0000000000 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/*! - * @brief Implement PMA address tree - * - */ - -#ifndef ADDRTREE_H -#define ADDRTREE_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "map_defines.h" - -// Declare this before its definition because it refers to itself -typedef struct addrtree_node ADDRTREE_NODE; - -struct addrtree_node -{ - NvU32 level; // The level this node belongs to - NvU32 numChildren; // The number of children in the children array - NvU64 frame; // The first frame this node holds - NvU64 state[PMA_BITS_PER_PAGE]; // Tracks the actual state for each map - NvU64 seeChild[PMA_BITS_PER_PAGE]; // Whether this node is partially allocated - // If it is partially allocated, we must go to the children - // to find the correct information. - - ADDRTREE_NODE *parent; // The node's parent - ADDRTREE_NODE *children; // Pointer to an array of children -}; - -typedef struct addrtree_level -{ - NvU64 nodeCount; // Count of total number of nodes on this level - ADDRTREE_NODE *pNodeList; // Pointer to the start of the list of nodes on this level - NvU32 pageSizeShift; // Page size this level is tracking - NvU32 maxFramesPerNode; // The max number of this level frames per node -} ADDRTREE_LEVEL; - -typedef struct pma_addrtree -{ - NvU64 totalFrames; // Total number of 64KB frames being tracked - NvU32 levelCount; // Number of levels in this tree - ADDRTREE_LEVEL *levels; // List of levels in the tree - ADDRTREE_NODE *root; // Start of the node list - NvU64 numPaddingFrames; // Number of 64KB frames needed for padding for alignment - - NvU64 frameEvictionsInProcess; // Count of frame evictions in-process - PMA_STATS *pPmaStats; // Point back to the public struct in PMA structure - NvBool bProtected; // The memory segment tracked by this tree is protected (VPR/CPR) -} PMA_ADDRTREE; - -/*! - * @brief Initializes the addrtree for PMA uses - * - * Allocates the address tree structure for all the pages being managed in this tree. - * Address Tree implementation will use a default configuration for its own level - * structures. - * - * @param[in] numPages The number of pages being managed in this tree - * @param[in] addrBase The base address of this region. Required for addrtree alignment - * @param[in] pPmaStats Pointer to the PMA-wide stats structure - * @param[in] bProtected The tree tracks pages in protected memory - * - * @return PMA_ADDRTREE Pointer to the addrtree if succeeded, NULL otherwise - */ -void *pmaAddrtreeInit(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected); - -/*! - * @brief Destroys the addrtree and free the memory - * - * @param[in] pMap The addrtree to destroy - * - * @return void - */ -void pmaAddrtreeDestroy(void *pMap); - -/*! - * @brief Get/set number of evicting frames - * Used for sanity checking in PMA layer as well as performance optimization - * for the map layer to scan faster. - */ -NvU64 pmaAddrtreeGetEvictingFrames(void *pMap); -void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess); - - -/*! - * @brief Scans the addrtree for contiguous space that has the certain status. - * - * @param[in] pMap The addrtree to be scanned - * @param[in] addrBase The base address of this region - * @param[in] rangeStart The start of the restricted range - * @param[in] rangeEnd The end of the restricted range - * @param[in] numPages The number of pages we are scanning for - * @param[out] freeList A list of free frame numbers -- contains only 1 element - * @param[in] pageSize Size of one page - * @param[in] alignment Alignment requested by client - * @param[out] pagesAllocated Number of pages this call allocated - * @param[in] bSkipEvict Whether it's ok to skip the scan for evictable pages - * - * @return NV_OK if succeeded - * @return NV_ERR_IN_USE if found pages that can be evicted - * @return NV_ERR_NO_MEMORY if no available pages could be found - */ -NV_STATUS pmaAddrtreeScanContiguous( - void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); - -NV_STATUS pmaAddrtreeScanDiscontiguous( - void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, - NvU64 numPages, NvU64 *freelist, NvU64 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); - -void pmaAddrtreePrintTree(void *pMap, const char* str); - - -/*! - * @brief Changes the state & attrib bits specified by mask - * - * Changes the state of the bits given the physical frame number - * TODO: all four interfaces need to be merged from PMA level so we can remove them! - * - * @param[in] pMap The addrtree to change - * @param[in] frameNum The frame number to change - * @param[in] newState The new state to change to - * @param[in] newStateMask Specific bits to write - * - * @return void - */ -void pmaAddrtreeChangeStateAttribEx(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); -void pmaAddrtreeChangePageStateAttribEx(void * pMap, NvU64 startFrame, NvU64 pageSize, - PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); - -/*! - * @brief Changes the state & attrib bits specified by mask - * - * Changes the state of the bits given the physical frame number - * and the number of frames to change - * - * @param[in] pMap The addrtree to change - * @param[in] frameNum The frame number to change - * @param[in] numFrames The number of frames to change - * @param[in] newState The new state to change to - * @param[in] newStateMask Specific bits to write - * - * @return void - */ -void pmaAddrtreeChangeBlockStateAttrib(void *pMap, NvU64 frameNum, - NvU64 numFrames, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask); - -/*! - * @brief Read the page state & attrib bits - * - * Read the state of the page given the physical frame number - * - * @param[in] pMap The addrtree to read - * @param[in] frameNum The frame number to read - * @param[in] readAttrib Read attribute bits as well - * - * @return PAGESTATUS of the frame - */ -PMA_PAGESTATUS pmaAddrtreeRead(void *pMap, NvU64 frameNum, NvBool readAttrib); - - -/*! - * @brief Gets the total size of specified PMA managed region. - * - * Gets the total size of current PMA managed region in the FB. - * - * @param[in] pMap Pointer to the addrtree for the region - * @param[in] pBytesTotal Pointer that will return total bytes for current region. - * - */ -void pmaAddrtreeGetSize(void *pMap, NvU64 *pBytesTotal); - - -/*! - * @brief Gets the size of the maximum free chunk of memory in specified region. - * - * Gets the size of the maximum free chunk of memory in the specified PMA managed - * region of the FB. - * - * @param[in] pMap Pointer to the addrtree for the region - * @param[in] pLargestFree Pointer that will return largest free in current region. - * - */ -void pmaAddrtreeGetLargestFree(void *pMap, NvU64 *pLargestFree); - -/*! - * @brief Returns the address range that is completely available for eviction. - * - Should be ALLOC_UNPIN. - * In NUMA, OS manages memory and PMA will only track allocated memory in ALLOC_PIN - * and ALLOC_UNPIN state. FREE memory is managed by OS and cannot be tracked by PMA - * and hence PMA cannot consider FREE memory for eviction and can only consider frames - * in known state to PMA or eviction. ALLOC_PIN cannot be evicted and hence only ALLOC_UNPIN - * can be evictable. - * - * - * @param[in] pMap Pointer to the regmap for the region - * @param[in] addrBase Base address of the region - * @param[in] actualSize Size of the eviction range - * @param[in] pageSize Pagesize - * @param[out] evictStart Starting address of the eviction range - * @param[out] evictEnd End address of the eviction range. - * - * Returns: - * - NV_OK If there is evictable range of given size : actualSize - * - * - NV_ERR_NO_MEMORY if no contiguous range is evictable. - */ -NV_STATUS pmaAddrtreeScanContiguousNumaEviction(void *pMap, NvU64 addrBase, - NvLength actualSize, NvU64 pageSize, NvU64 *evictStart, NvU64 *evictEnd); - -#ifdef __cplusplus -} -#endif - -#endif // ADDRTREE_H diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h index cd70f63c14..239e74cf10 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,7 +22,7 @@ */ /*! - * @brief Contains common defines between addrtree and regmap + * @brief Contains common defines for regmap */ #ifndef MAP_DEFINES_H @@ -44,30 +44,11 @@ extern "C" { #define PMA_GRANULARITY 0x10000 #define PMA_PAGE_SHIFT 16 -// -// _PMA_1GB will cause overflows with an NvU32. It's bigger than NvU32 can store, -// but compilation still fails when using a NvU64 instead -// So just use bitshift. -// 1 << _TREE_64KB == sizeof(1 frame) -// - -#define _TREE_64KB 16 -#define _TREE_128KB 17 -#define _TREE_2MB 21 -#define _TREE_128MB 27 -#define _TREE_512MB 29 -#define _TREE_32GB 35 -#define _TREE_2TB 40 - // Defines shared between pma.c and regmap.c -#define _PMA_64KB (64 * 1024) -#define _PMA_128KB (128 * 1024) -#define _PMA_2MB (2 * 1024 * 1024) -#define _PMA_512MB (512 * 1024 * 1024) - -// Scanning function return code -#define EVICTABLE -2 -#define ALL_FREE -3 +#define _PMA_64KB (64ULL * 1024) +#define _PMA_128KB (128ULL * 1024) +#define _PMA_2MB (2ULL * 1024 * 1024) +#define _PMA_512MB (512ULL * 1024 * 1024) typedef NvU32 PMA_PAGESTATUS; diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h index 442b867d4b..f8d63e9de4 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h @@ -42,7 +42,6 @@ #include "nvport/nvport.h" #include "regmap.h" -#include "addrtree.h" #include "nvmisc.h" #if defined(SRT_BUILD) @@ -72,7 +71,7 @@ typedef struct SCRUB_NODE SCRUB_NODE; #define PMA_INIT_NUMA NVBIT(2) #define PMA_INIT_INTERNAL NVBIT(3) // Used after heap is removed #define PMA_INIT_FORCE_PERSISTENCE NVBIT(4) -#define PMA_INIT_ADDRTREE NVBIT(5) +// unused #define PMA_INIT_NUMA_AUTO_ONLINE NVBIT(6) // These flags are used for querying PMA's config and/or state. @@ -178,8 +177,8 @@ typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 phys */ typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected); typedef void (*pmaMapDestroy_t)(void *pMap); -typedef void (*pmaMapChangeStateAttribEx_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); -typedef void (*pmaMapChangePageStateAttribEx_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); +typedef void (*pmaMapChangeStateAttrib_t)(void *pMap, NvU64 frameNum, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); +typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU64 pageSize, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); typedef void (*pmaMapChangeBlockStateAttrib_t)(void *pMap, NvU64 frameNum, NvU64 numFrames, PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib); typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, @@ -200,8 +199,8 @@ struct _PMA_MAP_INFO NvU32 mode; pmaMapInit_t pmaMapInit; pmaMapDestroy_t pmaMapDestroy; - pmaMapChangeStateAttribEx_t pmaMapChangeStateAttribEx; - pmaMapChangePageStateAttribEx_t pmaMapChangePageStateAttribEx; + pmaMapChangeStateAttrib_t pmaMapChangeStateAttrib; + pmaMapChangePageStateAttrib_t pmaMapChangePageStateAttrib; pmaMapChangeBlockStateAttrib_t pmaMapChangeBlockStateAttrib; pmaMapRead_t pmaMapRead; pmaMapScanContiguous_t pmaMapScanContiguous; @@ -474,33 +473,6 @@ NV_STATUS pmaAllocatePagesBroadcast(PMA **pPma, NvU32 pmaCount, NvLength allocat */ NV_STATUS pmaPinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize); - -/*! - * @brief Marks previously pinned pages as unpinned. - * - * It will return an error and rollback any change if any page is not - * previously marked "pinned". Behaviour is undefined is any blacklisted - * pages are unpinned. - * - * @param[in] pPages - * Array of base addresses of pages to pin - * - * @param[in] pageCount - * Number of pages to pin - * - * @param[in] pageSize - * Page size of each page being unpinned - * - * @return - * NV_ERR_GENERIC: - * Unexpected error. We try hard to avoid returning this error - * code,because it is not very informative. - * TODO some error for rollback - * - */ -NV_STATUS pmaUnpinPages(PMA *pPma, NvU64 *pPages, NvLength pageCount, NvU64 pageSize); - - /*! * @brief Marks a list of pages as free. * This operation is also used by RM to mark pages as "scrubbed" for the diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h index 8de31675f8..35cde9567f 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h @@ -103,8 +103,8 @@ void pmaRegmapSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess); * * @return void */ -void pmaRegmapChangePageStateAttribEx(void * pMap, NvU64 frameNumStart, NvU64 pageSize, - PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); +void pmaRegmapChangePageStateAttrib(void * pMap, NvU64 startFrame, NvU64 pageSize, + PMA_PAGESTATUS newState, PMA_PAGESTATUS newStateMask); /*! * @brief Changes the state & attrib bits specified by mask @@ -118,9 +118,9 @@ void pmaRegmapChangePageStateAttribEx(void * pMap, NvU64 frameNumStart, NvU64 pa * * @return void */ -void pmaRegmapChangeStateAttribEx(void *pMap, NvU64 frameNum, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask); +void pmaRegmapChangeStateAttrib(void *pMap, NvU64 frameNum, + PMA_PAGESTATUS newState, + PMA_PAGESTATUS newStateMask); /*! * @brief Changes the state & attrib bits specified by mask diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h b/src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h index bca3f4f863..9780a0d57a 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/sec2_utils.h @@ -1,112 +1,3 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ #include "g_sec2_utils_nvoc.h" -#ifndef SEC2_UTILS_H -#define SEC2_UTILS_H - -#include "gpu/gpu_resource.h" // GpuResource - -#include "kernel/gpu/mem_mgr/channel_utils.h" - -#include "kernel/gpu/conf_compute/ccsl_context.h" - -#define SEC2_AUTH_TAG_BUF_SIZE_BYTES (16) -#define SHA_256_HASH_SIZE_BYTES (32) - -typedef struct -{ - MEMORY_DESCRIPTOR *pMemDesc; - NvU64 offset; - NvU64 length; - NvU64 submittedWorkId; -} SEC2UTILS_MEMSET_PARAMS; - -typedef struct -{ - NvHandle hPhysMem; - NvHandle hVirtMem; - NvHandle hVASpace; - NvU64 gpuVA; - NvU64 size; - MEMORY_DESCRIPTOR *pMemDesc; -} SEC2UTILS_BUFFER_INFO; - -NVOC_PREFIX(sec2utils) class Sec2Utils : Object -{ -public: - NV_STATUS sec2utilsConstruct(Sec2Utils *psec2utils, OBJGPU *pGpu, KERNEL_MIG_GPU_INSTANCE *pKernelMIGGPUInstance); - - void sec2utilsDestruct(Sec2Utils *psec2utils); - - NV_STATUS sec2utilsMemset(Sec2Utils *psec2utils, SEC2UTILS_MEMSET_PARAMS *pParams); - - NvU64 sec2utilsUpdateProgress(Sec2Utils *psec2utils); - void sec2utilsServiceInterrupts(Sec2Utils *psec2utils); - - // - // Internal states - // - - NvHandle hClient; - NvHandle hDevice; - NvHandle hSubdevice; - - OBJCHANNEL *pChannel; - OBJGPU *pGpu; - - NvU32 sec2Class; - NvU64 lastSubmittedPayload; - NvU64 lastCompletedPayload; - - CCSL_CONTEXT *pCcslCtx; - - // - // 4K page consisting of 128 auth tag buffers. - // One buffer is used per sec2 method stream. - // RM scrubber can submit multiple scrub method streams per sec2 operation. - // - SEC2UTILS_BUFFER_INFO scrubMthdAuthTagBuf; - - // - // 4K page consisting of 128 auth tag buffers. - // One buffer is used per scrubber operation (not per sec2 scrub method stream). - // One scrub op corresponds to one call to sec2UtilsMemSet - // - SEC2UTILS_BUFFER_INFO semaMthdAuthTagBuf; - - // - // Updated by RM to point to current auth tag buffer index (0-127) - // so its incremented for every scrub method stream. - // - NvU32 authTagPutIndex; - - // - // Updated by SEC2 engine to point to last used/ last "seen" auth tag buffer index. - // This is updated based on completion of every scrub method stream. - // - NvU32 authTagGetIndex; -}; - -#endif // SEC2_UTILS_H diff --git a/src/nvidia/inc/kernel/gpu/nvenc/nvencsession.h b/src/nvidia/inc/kernel/gpu/nvenc/nvencsession.h new file mode 100644 index 0000000000..2253f276fc --- /dev/null +++ b/src/nvidia/inc/kernel/gpu/nvenc/nvencsession.h @@ -0,0 +1,3 @@ + +#include "g_nvencsession_nvoc.h" + diff --git a/src/nvidia/inc/kernel/gpu/perf/kern_cuda_limit.h b/src/nvidia/inc/kernel/gpu/perf/kern_cuda_limit.h index dcd8ccf11e..596da0b1f5 100644 --- a/src/nvidia/inc/kernel/gpu/perf/kern_cuda_limit.h +++ b/src/nvidia/inc/kernel/gpu/perf/kern_cuda_limit.h @@ -25,13 +25,14 @@ #define KERNEL_CUDA_LIMIT_H /* ------------------------ Includes --------------------------------------- */ -#include "gpu/device/device.h" /* ------------------------ Macros ----------------------------------------- */ /* ------------------------ Datatypes -------------------------------------- */ +typedef struct Device Device; + /* -------------------- Function Prototypes -------------------------------- */ // Device CLI interfaces diff --git a/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h b/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h index fffe04183d..d971568ef8 100644 --- a/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h +++ b/src/nvidia/inc/kernel/gpu/rc/kernel_rc_watchdog_private.h @@ -79,6 +79,7 @@ typedef struct { NvNotification *notifiers[NV_MAX_SUBDEVICES]; NvNotification *errorContext; NvNotification *notifierToken; + NvBool bHandleValid; } KernelWatchdog; diff --git a/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_event.h b/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_event.h index 58e765d52c..0d43306ff3 100644 --- a/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_event.h +++ b/src/nvidia/inc/kernel/gpu/subdevice/subdevice_ctrl_event.h @@ -55,3 +55,7 @@ NV_STATUS subdeviceCtrlCmdEventVideoBindEvtbuf(Subdevice *pSubdevice, NV2080_CTRL_EVENT_VIDEO_BIND_EVTBUF_PARAMS *pBindParams); + RMCTRL_EXPORT(NV2080_CTRL_CMD_EVENT_RATS_GSP_TRACE_BIND_EVTBUF, + RMCTRL_FLAGS(PRIVILEGED)) + NV_STATUS subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf(Subdevice *pSubdevice, + NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS *pBindParams); diff --git a/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h b/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h index 181d88d51b..cfd78616a9 100644 --- a/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h +++ b/src/nvidia/inc/kernel/gpu_mgr/gpu_mgr_sli.h @@ -24,6 +24,7 @@ #ifndef _RMSLIGPUMGR_H_ #define _RMSLIGPUMGR_H_ +NvBool gpumgrAreGpusInitialized(NvU32 gpuMask); void gpumgrDetectSliLinkFromGpus(NvBool, NvU32, NvU32, NvU32 *, NvU32 *, NvBool *, NvU32 *, NvU32 *); NvBool gpumgrDetectHighSpeedVideoBridges(NvU32 linkOutputMask); NvBool gpumgrUpdateSliLinkRouting(OBJGPU *pGpuParent, OBJGPU *pGpuChild, diff --git a/src/nvidia/inc/kernel/mem_mgr/mem_export.h b/src/nvidia/inc/kernel/mem_mgr/mem_export.h new file mode 100644 index 0000000000..d2066317c0 --- /dev/null +++ b/src/nvidia/inc/kernel/mem_mgr/mem_export.h @@ -0,0 +1,3 @@ + +#include "g_mem_export_nvoc.h" + diff --git a/src/nvidia/inc/kernel/mem_mgr/mem_fabric_import_ref.h b/src/nvidia/inc/kernel/mem_mgr/mem_fabric_import_ref.h new file mode 100644 index 0000000000..0bb1bb4266 --- /dev/null +++ b/src/nvidia/inc/kernel/mem_mgr/mem_fabric_import_ref.h @@ -0,0 +1,3 @@ + +#include "g_mem_fabric_import_ref_nvoc.h" + diff --git a/src/nvidia/inc/kernel/mem_mgr/mem_fabric_import_v2.h b/src/nvidia/inc/kernel/mem_mgr/mem_fabric_import_v2.h new file mode 100644 index 0000000000..3fdc8382d8 --- /dev/null +++ b/src/nvidia/inc/kernel/mem_mgr/mem_fabric_import_v2.h @@ -0,0 +1,3 @@ + +#include "g_mem_fabric_import_v2_nvoc.h" + diff --git a/src/nvidia/inc/kernel/mem_mgr/mem_list.h b/src/nvidia/inc/kernel/mem_mgr/mem_list.h index 37a3d49026..b73605616d 100644 --- a/src/nvidia/inc/kernel/mem_mgr/mem_list.h +++ b/src/nvidia/inc/kernel/mem_mgr/mem_list.h @@ -1,45 +1,3 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ #include "g_mem_list_nvoc.h" -#ifndef _MEMORY_LIST_H_ -#define _MEMORY_LIST_H_ - -#include "mem_mgr/mem.h" - -/*! - * These classes are used by the vGPU support to create memory objects for memory - * assigned to a guest VM. - */ -NVOC_PREFIX(memlist) class MemoryList : Memory -{ -public: - NV_STATUS memlistConstruct(MemoryList *pMemoryList, CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams) : - Memory(pCallContext, pParams); - - virtual NvBool memlistCanCopy(MemoryList *pMemoryList); -}; - -#endif diff --git a/src/nvidia/inc/kernel/os/capability.h b/src/nvidia/inc/kernel/os/capability.h index e2fa861a5d..ce58969f52 100644 --- a/src/nvidia/inc/kernel/os/capability.h +++ b/src/nvidia/inc/kernel/os/capability.h @@ -34,6 +34,8 @@ typedef struct OS_RM_CAPS OS_RM_CAPS; #define NV_RM_CAP_SYS_SMC_CONFIG (NV_RM_CAP_SYS_BASE + 2) #define NV_RM_CAP_SYS_SMC_MONITOR (NV_RM_CAP_SYS_BASE + 3) +#define NV_RM_CAP_SYS_FABRIC_IMEX_MGMT (NV_RM_CAP_SYS_BASE + 4) + #define NV_RM_CAP_SMC_PARTITION_BASE 0x100 #define NV_RM_CAP_SMC_PARTITION_ACCESS (NV_RM_CAP_SMC_PARTITION_BASE + 0) diff --git a/src/nvidia/inc/kernel/platform/p2p/p2p_caps.h b/src/nvidia/inc/kernel/platform/p2p/p2p_caps.h index 1bd045d18b..d6121d882b 100644 --- a/src/nvidia/inc/kernel/platform/p2p/p2p_caps.h +++ b/src/nvidia/inc/kernel/platform/p2p/p2p_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,7 @@ typedef enum { P2P_CONNECTIVITY_UNKNOWN = 0, - P2P_CONNECTIVITY_PCIE, + P2P_CONNECTIVITY_PCIE_PROPRIETARY, P2P_CONNECTIVITY_PCIE_BAR1, P2P_CONNECTIVITY_NVLINK, P2P_CONNECTIVITY_NVLINK_INDIRECT, diff --git a/src/nvidia/inc/kernel/platform/sli/sli.h b/src/nvidia/inc/kernel/platform/sli/sli.h index 79b3c60caf..cdce96851d 100644 --- a/src/nvidia/inc/kernel/platform/sli/sli.h +++ b/src/nvidia/inc/kernel/platform/sli/sli.h @@ -31,7 +31,6 @@ #include "core/core.h" #include "nvlimits.h" -#include "gpu_mgr/gpu_mgr.h" #define IsDeviceDestroyed(p) (gpuGetDeviceInstance(p) == NV_MAX_DEVICES) diff --git a/src/nvidia/inc/kernel/rmapi/binary_api.h b/src/nvidia/inc/kernel/rmapi/binary_api.h index df57afcf0b..cfae46e863 100644 --- a/src/nvidia/inc/kernel/rmapi/binary_api.h +++ b/src/nvidia/inc/kernel/rmapi/binary_api.h @@ -1,61 +1,3 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ #include "g_binary_api_nvoc.h" -#ifndef BINARY_API_H -#define BINARY_API_H - -#include "core/core.h" -#include "rmapi/resource.h" -#include "gpu/gpu_resource.h" -#include "resserv/rs_resource.h" -#include "rmapi/control.h" - -NVOC_PREFIX(binapi) class BinaryApi : GpuResource -{ -public: - NV_STATUS binapiConstruct(BinaryApi *pResource, - CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams) : - GpuResource(pCallContext, pParams); - - virtual NV_STATUS binapiControl(BinaryApi *pResource, CALL_CONTEXT *pCallContext, - RS_RES_CONTROL_PARAMS_INTERNAL *pParams); - -}; - -NVOC_PREFIX(binapipriv) class BinaryApiPrivileged : BinaryApi -{ -public: - NV_STATUS binapiprivConstruct(BinaryApiPrivileged *pResource, CALL_CONTEXT *pCallContext, - RS_RES_ALLOC_PARAMS_INTERNAL *pParams) : - BinaryApi(pCallContext, pParams); - - virtual NV_STATUS binapiprivControl(BinaryApiPrivileged *pResource, CALL_CONTEXT *pCallContext, - RS_RES_CONTROL_PARAMS_INTERNAL *pParams); - -}; - -#endif - diff --git a/src/nvidia/inc/kernel/rmapi/control.h b/src/nvidia/inc/kernel/rmapi/control.h index 98fda3034b..54f040f134 100644 --- a/src/nvidia/inc/kernel/rmapi/control.h +++ b/src/nvidia/inc/kernel/rmapi/control.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -141,8 +141,17 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC #define _RMCTRL_PREP_ACCESS_ARG(x) | NVBIT(NV_CONCATENATE(RS_ACCESS_, x)) #define ACCESS_RIGHTS(...) (0 NV_FOREACH_ARG_NOCOMMA(_RMCTRL_PREP_ACCESS_ARG, __VA_ARGS__)) +// This define is currently unused. +// In the future it will be used by NVOC to validate control flags. +// 1. PHYSICAL_IMPLEMENTED_ON_VGPU_GUEST should be set only if ROUTE_TO_PHYSICAL is set +// 2. PHYSICAL_IMPLEMENTED_ON_VGPU_GUEST and ROUTE_TO_VGPU_HOST shouldn't be set at the same time +#define NVOC_EXPORTED_METHOD_FLAGS_VALID(ctrlFlags) \ + ((ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) || !(ctrlFlags & RMCTRL_FLAGS_PHYSICAL_IMPLEMENTED_ON_VGPU_GUEST)) && \ + (!(ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST) || !(ctrlFlags & RMCTRL_FLAGS_PHYSICAL_IMPLEMENTED_ON_VGPU_GUEST)) + #define NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(ctrlFlags) \ - (ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) + ((ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) && \ + (!(ctrlFlags & RMCTRL_FLAGS_PHYSICAL_IMPLEMENTED_ON_VGPU_GUEST))) // // 'FLAGS' Attribute @@ -296,9 +305,25 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC // #define RMCTRL_FLAGS_CACHEABLE_BY_INPUT 0x000200000 + +// This flag specifies that ROUTE_TO_PHYSICAL control is implemented on vGPU Guest RM. +// If a ROUTE_TO_PHYSICAL control is supported within vGPU Guest RM, +// it should either have this flag set (indicating the implementation in the vGPU Guest RM) or +// the ROUTE_TO_VGPU_HOST flag set (indicating the implementation in vGPU Host RM). +// Without either of these flags set, the control will return NV_ERR_NOT_SUPPORTED. +// +#define RMCTRL_FLAGS_PHYSICAL_IMPLEMENTED_ON_VGPU_GUEST 0x000400000 + // The combination of cacheable flags #define RMCTRL_FLAGS_CACHEABLE_ANY (RMCTRL_FLAGS_CACHEABLE | RMCTRL_FLAGS_CACHEABLE_BY_INPUT) +// +// This flag specifies that two client handles need to be locked. +// An entry is required for any control calls that set this in +// serverControlLookupSecondClient or Resource Server will NV_ASSERT(0). +// +#define RMCTRL_FLAGS_DUAL_CLIENT_LOCK 0x000800000 + // // 'ACCESS_RIGHTS' Attribute // ------------------------ diff --git a/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h b/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h index b910bf413a..f5fc2e728c 100644 --- a/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h +++ b/src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h @@ -60,6 +60,7 @@ NV_STATUS nvGpuOpsDeviceDestroy(struct gpuDevice *device); NV_STATUS nvGpuOpsAddressSpaceCreate(struct gpuDevice *device, NvU64 vaBase, NvU64 vaSize, + NvBool enableAts, gpuAddressSpaceHandle *vaSpace, UvmGpuAddressSpaceInfo *vaSpaceInfo); @@ -93,11 +94,6 @@ NV_STATUS nvGpuOpsPmaPinPages(void *pPma, NvU64 pageSize, NvU32 flags); -NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, - NvU64 *pPages, - NvLength pageCount, - NvU64 pageSize); - NV_STATUS nvGpuOpsTsgAllocate(gpuAddressSpaceHandle vaSpace, const gpuTsgAllocParams *params, gpuTsgHandle *tsgHandle); @@ -279,11 +275,14 @@ NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel, NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device); +NV_STATUS nvGpuOpsTogglePrefetchFaults(gpuFaultInfo *pFaultInfo, NvBool bEnable); + // Interface used for CCSL NV_STATUS nvGpuOpsCcslContextInit(struct ccslContext_t **ctx, gpuChannelHandle channel); NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx); +NV_STATUS nvGpuOpsCcslContextUpdate(struct ccslContext_t *ctx); NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, NvU8 direction); NV_STATUS nvGpuOpsCcslEncrypt(struct ccslContext_t *ctx, @@ -316,5 +315,7 @@ NV_STATUS nvGpuOpsIncrementIv(struct ccslContext_t *ctx, NvU8 direction, NvU64 increment, NvU8 *iv); +NV_STATUS nvGpuOpsLogDeviceEncryption(struct ccslContext_t *ctx, + NvU32 bufferSize); #endif /* _NV_GPU_OPS_H_*/ diff --git a/src/nvidia/inc/kernel/rmapi/rmapi.h b/src/nvidia/inc/kernel/rmapi/rmapi.h index 74f0e96c6f..f1b530950b 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi.h @@ -229,12 +229,12 @@ struct _RM_API NvU64 offset, NvU64 length, NvU32 flags, NvU64 *pDmaOffset, API_SECURITY_INFO *pSecInfo); // Unmap dma memory with default security attributes - NV_STATUS (*Unmap)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, NvHandle hMemory, - NvU32 flags, NvU64 dmaOffset); + NV_STATUS (*Unmap)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, + NvU32 flags, NvU64 dmaOffset, NvU64 size); // Unmap dma memory - NV_STATUS (*UnmapWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, NvHandle hMemory, - NvU32 flags, NvU64 dmaOffset, API_SECURITY_INFO *pSecInfo); + NV_STATUS (*UnmapWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, + NvU32 flags, NvU64 dmaOffset, NvU64 size, API_SECURITY_INFO *pSecInfo); API_SECURITY_INFO defaultSecInfo; NvBool bHasDefaultSecInfo; diff --git a/src/nvidia/inc/kernel/rmapi/rmapi_specific.h b/src/nvidia/inc/kernel/rmapi/rmapi_specific.h new file mode 100644 index 0000000000..a3fe6f8494 --- /dev/null +++ b/src/nvidia/inc/kernel/rmapi/rmapi_specific.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _RMAPI_SPECIFIC_H +#define _RMAPI_SPECIFIC_H + +#include "nvstatus.h" +#include "nvtypes.h" + +#include "resserv/rs_resource.h" + +/** + * Make custom modifications to class-specific allocation params as needed. + * + * @param[inout] ppResDesc Resource descriptor used for the allocation, may change if + * the class's ID changes as a result of this function. + * @param[in] pRmAllocParams Allocation params + * + * @return NV_ERR_INVALID_CLASS if an invalid class transition happens, NV_OK otherwise. + */ +NV_STATUS rmapiFixupAllocParams(RS_RESOURCE_DESC **ppResDesc, RS_RES_ALLOC_PARAMS_INTERNAL *pRmAllocParams); + +/** + * Returns NV_TRUE if the control call specific by cmd can be invoked at an increased + * IRQL level, NV_FALSE otherwise. + * + * @param[in] cmd Control call ID + * + * @return NV_TRUE if control can be RAISED_IRQL, NV_FALSE otherwise. + */ +NvBool rmapiRmControlCanBeRaisedIrql(NvU32 cmd); + +/** + * Returns NV_TRUE if the control call specific by cmd can bypass acquiring locks, + * NV_FALSE otherwise. + * + * @param[in] cmd Control call ID + * + * @return NV_TRUE if control can be BYPASS_LOCK, NV_FALSE otherwise. + */ +NvBool rmapiRmControlCanBeBypassLock(NvU32 cmd); + +#endif // _RMAPI_SPECIFIC_H diff --git a/src/nvidia/inc/kernel/rmapi/rmapi_utils.h b/src/nvidia/inc/kernel/rmapi/rmapi_utils.h index 56efc82901..1c4a18228a 100644 --- a/src/nvidia/inc/kernel/rmapi/rmapi_utils.h +++ b/src/nvidia/inc/kernel/rmapi/rmapi_utils.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,6 +25,7 @@ #include "rmapi/rmapi.h" + // // Alloc a client, device and subdevice handle for a gpu // @@ -58,6 +59,9 @@ NvBool rmapiutilIsExternalClassIdInternalOnly(NvU32 externalClassId); // // Return the flags and access right associated with this RM control command // + NV_STATUS rmapiutilGetControlInfo(NvU32 cmd, NvU32 *pFlags, NvU32 *pAccessRight); +NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(NvU32 cmd); + #endif /* RMAPI_UTILS_H */ diff --git a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h index bdfedd5f17..4e5e975e50 100644 --- a/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h +++ b/src/nvidia/inc/kernel/virtualization/common_vgpu_mgr.h @@ -58,6 +58,11 @@ typedef struct NvU8 vgpuClass[VGPU_STRING_BUFFER_SIZE]; NvU8 license[NV_GRID_LICENSE_INFO_MAX_LENGTH]; NvU8 licensedProductName[NV_GRID_LICENSE_INFO_MAX_LENGTH]; + NvU32 placementSize; + NvU16 supportedPlacementIds[MAX_VGPU_DEVICES_PER_PGPU]; + NvU32 supportedChidOffsets[MAX_VGPU_DEVICES_PER_PGPU]; + NvU32 channelCount; + NvU32 placementCount; NvU32 maxInstance; NvU32 numHeads; NvU32 maxResolutionX; @@ -98,6 +103,7 @@ vgpuMgrReserveSystemChannelIDs(OBJGPU *pGpu, NvU32 *pChannelCount, Device *pMigDevice, NvU32 numChannels, + NvU16 placementId, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList); diff --git a/src/nvidia/inc/libraries/containers/eheap_old.h b/src/nvidia/inc/libraries/containers/eheap_old.h index 6c19e8b0e7..de89d30510 100644 --- a/src/nvidia/inc/libraries/containers/eheap_old.h +++ b/src/nvidia/inc/libraries/containers/eheap_old.h @@ -20,8 +20,8 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#ifndef _EHEAP_H_ -#define _EHEAP_H_ +#ifndef EHEAP_H +#define EHEAP_H /*! * @brief @@ -33,11 +33,10 @@ #include "containers/btree.h" #include "utils/nvrange.h" -typedef struct OBJEHEAP *POBJEHEAP; typedef struct OBJEHEAP OBJEHEAP; -typedef struct EMEMBLOCK *PEMEMBLOCK; -typedef struct EMEMBLOCK +typedef struct EMEMBLOCK EMEMBLOCK; +struct EMEMBLOCK { NvU64 begin; NvU64 end; @@ -46,30 +45,30 @@ typedef struct EMEMBLOCK NvU32 refCount; NvU32 owner; NODE node; - PEMEMBLOCK prevFree; - PEMEMBLOCK nextFree; - PEMEMBLOCK prev; - PEMEMBLOCK next; + EMEMBLOCK *prevFree; + EMEMBLOCK *nextFree; + EMEMBLOCK *prev; + EMEMBLOCK *next; void *pData; -} EMEMBLOCK; +}; typedef NvBool EHeapOwnershipComparator(void*, void*); -typedef NV_STATUS (*EHeapDestruct)(POBJEHEAP); -typedef NV_STATUS (*EHeapAlloc)(POBJEHEAP, NvU32, NvU32 *, NvU64 *, NvU64 *, NvU64 , NvU64, PEMEMBLOCK*, void*, EHeapOwnershipComparator*); -typedef NV_STATUS (*EHeapFree)(POBJEHEAP, NvU64); -typedef void (*EHeapInfo)(POBJEHEAP, NvU64 *, NvU64 *,NvU64 *, NvU64 *, NvU32 *, NvU64 *); -typedef void (*EHeapInfoForRange)(POBJEHEAP, NV_RANGE, NvU64 *, NvU64 *, NvU32 *, NvU64 *); -typedef NV_STATUS (*EHeapGetSize)(POBJEHEAP, NvU64 *); -typedef NV_STATUS (*EHeapGetFree)(POBJEHEAP, NvU64 *); -typedef NV_STATUS (*EHeapGetBase)(POBJEHEAP, NvU64 *); -typedef PEMEMBLOCK (*EHeapGetBlock)(POBJEHEAP, NvU64, NvBool bReturnFreeBlock); -typedef NV_STATUS (*EHeapSetAllocRange)(POBJEHEAP, NvU64 rangeLo, NvU64 rangeHi); -typedef NV_STATUS (*EHeapTraversalFn)(POBJEHEAP, void *pEnv, PEMEMBLOCK, NvU32 *pContinue, NvU32 *pInvalCursor); -typedef NV_STATUS (*EHeapTraverse)(POBJEHEAP, void *pEnv, EHeapTraversalFn, NvS32 direction); -typedef NvU32 (*EHeapGetNumBlocks)(POBJEHEAP); -typedef NV_STATUS (*EHeapGetBlockInfo)(POBJEHEAP, NvU32, NVOS32_HEAP_DUMP_BLOCK *); -typedef NV_STATUS (*EHeapSetOwnerIsolation)(POBJEHEAP, NvBool bEnable, NvU32 granularity); +typedef NV_STATUS (*EHeapDestruct)(OBJEHEAP *); +typedef NV_STATUS (*EHeapAlloc)(OBJEHEAP *, NvU32, NvU32 *, NvU64 *, NvU64 *, NvU64 , NvU64, EMEMBLOCK **, void*, EHeapOwnershipComparator*); +typedef NV_STATUS (*EHeapFree)(OBJEHEAP *, NvU64); +typedef void (*EHeapInfo)(OBJEHEAP *, NvU64 *, NvU64 *,NvU64 *, NvU64 *, NvU32 *, NvU64 *); +typedef void (*EHeapInfoForRange)(OBJEHEAP *, NV_RANGE, NvU64 *, NvU64 *, NvU32 *, NvU64 *); +typedef NV_STATUS (*EHeapGetSize)(OBJEHEAP *, NvU64 *); +typedef NV_STATUS (*EHeapGetFree)(OBJEHEAP *, NvU64 *); +typedef NV_STATUS (*EHeapGetBase)(OBJEHEAP *, NvU64 *); +typedef EMEMBLOCK *(*EHeapGetBlock)(OBJEHEAP *, NvU64, NvBool bReturnFreeBlock); +typedef NV_STATUS (*EHeapSetAllocRange)(OBJEHEAP *, NvU64 rangeLo, NvU64 rangeHi); +typedef NV_STATUS (*EHeapTraversalFn)(OBJEHEAP *, void *pEnv, EMEMBLOCK *, NvU32 *pContinue, NvU32 *pInvalCursor); +typedef NV_STATUS (*EHeapTraverse)(OBJEHEAP *, void *pEnv, EHeapTraversalFn, NvS32 direction); +typedef NvU32 (*EHeapGetNumBlocks)(OBJEHEAP *); +typedef NV_STATUS (*EHeapGetBlockInfo)(OBJEHEAP *, NvU32, NVOS32_HEAP_DUMP_BLOCK *); +typedef NV_STATUS (*EHeapSetOwnerIsolation)(OBJEHEAP *, NvBool bEnable, NvU32 granularity); struct OBJEHEAP { @@ -97,8 +96,8 @@ struct OBJEHEAP NvU64 rangeHi; NvBool bOwnerIsolation; NvU32 ownerGranularity; - PEMEMBLOCK pBlockList; - PEMEMBLOCK pFreeBlockList; + EMEMBLOCK *pBlockList; + EMEMBLOCK *pFreeBlockList; NvU32 memHandle; NvU32 numBlocks; NvU32 sizeofMemBlock; @@ -107,10 +106,10 @@ struct OBJEHEAP // be allocated at heap construction time so that // we will not call portMemAllocNonPaged during eheapAlloc. NvU32 numPreAllocMemStruct; - PEMEMBLOCK pFreeMemStructList; - PEMEMBLOCK pPreAllocAddr; + EMEMBLOCK *pFreeMemStructList; + EMEMBLOCK *pPreAllocAddr; }; -extern void constructObjEHeap(POBJEHEAP, NvU64, NvU64, NvU32, NvU32); +extern void constructObjEHeap(OBJEHEAP *, NvU64, NvU64, NvU32, NvU32); -#endif // _EHEAP_H_ +#endif // EHEAP_H diff --git a/src/nvidia/inc/libraries/nvlog/internal/nvlog_printf_internal.h b/src/nvidia/inc/libraries/nvlog/internal/nvlog_printf_internal.h index a236b6ddf1..28e5d0902e 100644 --- a/src/nvidia/inc/libraries/nvlog/internal/nvlog_printf_internal.h +++ b/src/nvidia/inc/libraries/nvlog/internal/nvlog_printf_internal.h @@ -22,8 +22,7 @@ */ /** - * @file - * @brief Internal macro definitions for NVLOG_PRINTF + * Internal macro definitions for NVLOG_PRINTF * * Macro magic example: (Assuming nothing gets compiled out) * 0) NV_PRINTF(LEVEL_ERROR, "Bla %d %d", arg0, arg1) @@ -58,6 +57,7 @@ // NVLOG_PARSING is defined if the file is being compiled for the parser run // #if defined(NVLOG_PARSING) + // // Since the '@' symbol is not found in C code, using it here makes it trivial // for the parser code to extract the needed info from preprocessed source. @@ -69,6 +69,7 @@ _NVLOG_PRINTF2(_NVLOG_COUNTER, __FILE__, __LINE__, tag, route, level, format, __VA_ARGS__) #elif !NVLOG_ENABLED + #define _NVLOG_PRINTF _NVLOG_NOTHING #else // NVLOG_ENABLED && !defined(NVLOG_PARSING) @@ -97,37 +98,37 @@ NVLOG_PRINTF_PROTO nvlogPrint_printf6; NV_STATUS nvlogPrint_printf(NvU32 dbgLevel, NvU32 file, NvU32 line, ...); -#if NVLOG_LEVEL <= 0x0 +#if NVLOG_LEVEL <= LEVEL_SILENT #define NVLOG_PRINT_LEVEL_0x0 nvlogPrint_printf0 #else #define NVLOG_PRINT_LEVEL_0x0 _NVLOG_NOTHING #endif -#if NVLOG_LEVEL <= 0x1 +#if NVLOG_LEVEL <= LEVEL_INFO #define NVLOG_PRINT_LEVEL_0x1 nvlogPrint_printf1 #else #define NVLOG_PRINT_LEVEL_0x1 _NVLOG_NOTHING #endif -#if NVLOG_LEVEL <= 0x2 +#if NVLOG_LEVEL <= LEVEL_NOTICE #define NVLOG_PRINT_LEVEL_0x2 nvlogPrint_printf2 #else #define NVLOG_PRINT_LEVEL_0x2 _NVLOG_NOTHING #endif -#if NVLOG_LEVEL <= 0x3 +#if NVLOG_LEVEL <= LEVEL_WARNING #define NVLOG_PRINT_LEVEL_0x3 nvlogPrint_printf3 #else #define NVLOG_PRINT_LEVEL_0x3 _NVLOG_NOTHING #endif -#if NVLOG_LEVEL <= 0x4 +#if NVLOG_LEVEL <= LEVEL_ERROR #define NVLOG_PRINT_LEVEL_0x4 nvlogPrint_printf4 #else #define NVLOG_PRINT_LEVEL_0x4 _NVLOG_NOTHING #endif -#if NVLOG_LEVEL <= 0x5 +#if NVLOG_LEVEL <= LEVEL_HW_ERROR #define NVLOG_PRINT_LEVEL_0x5 nvlogPrint_printf5 #else #define NVLOG_PRINT_LEVEL_0x5 _NVLOG_NOTHING #endif -#if NVLOG_LEVEL <= 0x6 +#if NVLOG_LEVEL <= LEVEL_FATAL #define NVLOG_PRINT_LEVEL_0x6 nvlogPrint_printf6 #else #define NVLOG_PRINT_LEVEL_0x6 _NVLOG_NOTHING diff --git a/src/nvidia/inc/libraries/nvlog/nvlog.h b/src/nvidia/inc/libraries/nvlog/nvlog.h index 4922df6c81..17697a2e8c 100644 --- a/src/nvidia/inc/libraries/nvlog/nvlog.h +++ b/src/nvidia/inc/libraries/nvlog/nvlog.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -240,6 +240,10 @@ NV_STATUS nvlogPrintUpdate(void); */ NV_STATUS nvlogPrintDestroy(void); +// +// NvLog ETW functions +// + /** * @brief Global NvLog ETW capture state function * @@ -247,6 +251,23 @@ NV_STATUS nvlogPrintDestroy(void); */ NV_STATUS nvlogETWCaptureState(void); +/** + * @brief Pushes all buffer tags to ETW + */ +void nvlogETWPushTags(void); + +/** + * @brief Pushes an nvlog buffer header to ETW + */ +void nvlogETWPushBufferHeader(NVLOG_BUFFER *pBuffer); + +/** + * @brief Pushes an nvlog entry to ETW + * + * @return NV_TRUE on success + */ +NvBool nvlogETWPush(NVLOG_BUFFER *pBuffer, NvU8 *pData, NvU32 dataSize); + // // Global initialization macros // diff --git a/src/nvidia/inc/libraries/nvlog/nvlog_printf.h b/src/nvidia/inc/libraries/nvlog/nvlog_printf.h index 43a8fac19a..fbce4b3dcb 100644 --- a/src/nvidia/inc/libraries/nvlog/nvlog_printf.h +++ b/src/nvidia/inc/libraries/nvlog/nvlog_printf.h @@ -22,8 +22,7 @@ */ /** - * @file - * @brief NvLog call that logs prints. + * NvLog call that logs prints. * * This is the traditional NvLog component. When enabled, it will also activate * preprocessing of all source files to detect calls to NVLOG_PRINTF, and @@ -32,8 +31,10 @@ * This file just defines the macros used by NV_PRINTF and others clients */ -#ifndef _NVLOG_PRINTF_H_ -#define _NVLOG_PRINTF_H_ +#ifndef NVLOG_PRINTF_H +#define NVLOG_PRINTF_H + +#include "utils/nvprintf_level.h" #ifdef __cplusplus extern "C" { @@ -46,7 +47,7 @@ extern "C" { #ifndef NVLOG_LEVEL /// @brief Level below which all prints will be compiled out. -#define NVLOG_LEVEL 2 +#define NVLOG_LEVEL LEVEL_NOTICE #endif /// @brief Maximum number of arguments to NVLOG_PRINTF @@ -88,4 +89,4 @@ extern "C" { } //extern "C" #endif -#endif // _NVLOG_PRINTF_H_ +#endif // NVLOG_PRINTF_H diff --git a/src/nvidia/inc/libraries/nvoc/prelude.h b/src/nvidia/inc/libraries/nvoc/prelude.h index 74f16e2bc9..c6cbeabea1 100644 --- a/src/nvidia/inc/libraries/nvoc/prelude.h +++ b/src/nvidia/inc/libraries/nvoc/prelude.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,7 @@ #ifndef _NVOC_PRELUDE_H_ #define _NVOC_PRELUDE_H_ +#include "nvtypes.h" #include "utils/nvmacro.h" /* Calls the macro named in the first parameter with the rest of the given arguments. Written diff --git a/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h b/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h index 0748ae050d..b24f1623c6 100644 --- a/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h +++ b/src/nvidia/inc/libraries/nvport/inline/debug_unix_kernel_os.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -39,9 +39,6 @@ extern "C" { #endif #include "nv-kernel-interface-api.h" -#include "utils/nvprintf_level.h" -#include "os-interface.h" - void NV_API_CALL os_dbg_breakpoint(void); void NV_API_CALL out_string(const char *str); int NV_API_CALL nv_printf(NvU32 debuglevel, const char *format, ...); @@ -62,11 +59,11 @@ portDbgPrintString out_string(str); } -#define portDbgPrintf(fmt, ...) nv_printf(NV_DBG_FORCE_LEVEL(LEVEL_INFO), fmt, ##__VA_ARGS__) +#define portDbgPrintf(fmt, ...) nv_printf(0xFFFFFFFF, fmt, ##__VA_ARGS__) #undef portDbgPrintf_SUPPORTED #define portDbgPrintf_SUPPORTED 1 -#define portDbgExPrintfLevel(level, fmt, ...) nv_printf(NV_DBG_FORCE_LEVEL(level), fmt, ##__VA_ARGS__) +#define portDbgExPrintfLevel(level, fmt, ...) nv_printf(level, fmt, ##__VA_ARGS__) #undef portDbgExPrintfLevel_SUPPORTED #define portDbgExPrintfLevel_SUPPORTED 1 diff --git a/src/nvidia/inc/libraries/poolalloc.h b/src/nvidia/inc/libraries/poolalloc.h index 8485ad838e..bf076d07e0 100644 --- a/src/nvidia/inc/libraries/poolalloc.h +++ b/src/nvidia/inc/libraries/poolalloc.h @@ -83,10 +83,11 @@ MAKE_LIST(PoolPageHandleList, POOLALLOC_HANDLE); /*! * @brief Callback function to upstream allocators for allocating new pages * - * This function only allocate 1 page at a time right now + * This function can allocate multiple pages at a time * * @param[in] ctxPtr Provides context to upstream allocator - * @param[in] pageSize Not really needed. For debugging only + * @param[in] pageSize Size of page to ask for from upstream + * @param[in] numPages Number of pages to allocate * @param[out] pPage The output page handle from upstream * * @return NV_OK if successfully allocated NvF32 totalTest, doneTest, failTest; the page @@ -96,7 +97,7 @@ MAKE_LIST(PoolPageHandleList, POOLALLOC_HANDLE); * */ typedef NV_STATUS (*allocCallback_t)(void *ctxPtr, NvU64 pageSize, - POOLALLOC_HANDLE *pPage); + NvU64 numPages, POOLALLOC_HANDLE *pPage); /*! * @brief Callback function to upstream allocators for freeing unused pages diff --git a/src/nvidia/inc/libraries/resserv/rs_client.h b/src/nvidia/inc/libraries/resserv/rs_client.h index 8a4e0f525a..a0836bc1b5 100644 --- a/src/nvidia/inc/libraries/resserv/rs_client.h +++ b/src/nvidia/inc/libraries/resserv/rs_client.h @@ -296,7 +296,7 @@ NVOC_PREFIX(client) class RsClient : Object * @param[in] pMapperRef The reference that was was used to create the mapping * @param[in] pParams parameters describing the unmapping */ - virtual void clientInterUnmap(RsClient *pClient, RsResourceRef *pMapperRef, RS_INTER_UNMAP_PARAMS *pParams); + virtual NV_STATUS clientInterUnmap(RsClient *pClient, RsResourceRef *pMapperRef, RS_INTER_UNMAP_PARAMS *pParams); /** * Generate an unused handle for a resource. The handle will be generated in the white-listed range that was diff --git a/src/nvidia/inc/libraries/resserv/rs_resource.h b/src/nvidia/inc/libraries/resserv/rs_resource.h index 2be5031505..7b0368c734 100644 --- a/src/nvidia/inc/libraries/resserv/rs_resource.h +++ b/src/nvidia/inc/libraries/resserv/rs_resource.h @@ -275,9 +275,9 @@ NVOC_PREFIX(res) class RsResource : Object * @param[in] pParams * @param[out] ppEntry */ - virtual NV_STATUS resControlLookup(RsResource *pResource, - RS_RES_CONTROL_PARAMS_INTERNAL *pParams, - const struct NVOC_EXPORTED_METHOD_DEF **ppEntry); + NV_STATUS resControlLookup(RsResource *pResource, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams, + const struct NVOC_EXPORTED_METHOD_DEF **ppEntry); /** * Dispatch resource control call @@ -369,6 +369,12 @@ NVOC_PREFIX(res) class RsResource : Object */ virtual NV_STATUS resUnmap(RsResource *pResource, CALL_CONTEXT *pCallContext, RsCpuMapping *pCpuMapping); + /** + * Returns true if partial unmap is supported by the resource + * If true, resUnmapFrom() can be called to unmap a mapping partially + */ + virtual NvBool resIsPartialUnmapSupported(RsResource *pResource) { return NV_FALSE; } + /** * Maps to this resource from another resource * Not all resources can be mapped to, in such a case returns NV_ERR_INVALID_OBJECT_HANDLE @@ -547,13 +553,14 @@ struct RS_INTER_UNMAP_PARAMS { NvHandle hClient; NvHandle hMapper; - NvHandle hMappable; NvHandle hDevice; NvU32 flags; NvU64 dmaOffset; ///< [in] RS-TODO rename this - void *pMemDesc; ///< MEMORY_DESCRIPTOR * + NvU64 size; // Internal use only + NvHandle hMappable; + void *pMemDesc; ///< MEMORY_DESCRIPTOR * RS_LOCK_INFO *pLockInfo; ///< [inout] Locking flags and state API_SECURITY_INFO *pSecInfo; ///< [in] Security Info @@ -571,6 +578,7 @@ struct RsInterMapping RsResourceRef *pContextRef; ///< A resource used to provide additional context for the mapping (e.g. hDevice) NvU32 flags; ///< Flags passed when mapping, same flags also passed when unmapping NvU64 dmaOffset; + NvU64 size; void *pMemDesc; }; MAKE_LIST(RsInterMappingList, RsInterMapping); @@ -828,7 +836,6 @@ void refRemoveDependant(RsResourceRef *pResourceRef, RsResourceRef *pDependantRe * @param[inout] ppMapping Writes the resulting inter-mapping, if successfully created (Add) or found (Find) * @param[in] pMapping The inter-mapping to remove (Remove) */ -NV_STATUS refFindInterMapping(RsResourceRef *pMapperRef, RsResourceRef *pMappableRef, RsResourceRef *pContextRef, NvU64 dmaOffset, RsInterMapping **ppMapping); NV_STATUS refAddInterMapping(RsResourceRef *pMapperRef, RsResourceRef *pMappableRef, RsResourceRef *pContextRef, RsInterMapping **ppMapping); void refRemoveInterMapping(RsResourceRef *pMapperRef, RsInterMapping *pMapping); diff --git a/src/nvidia/inc/libraries/resserv/rs_server.h b/src/nvidia/inc/libraries/resserv/rs_server.h index 98db50617c..fe63a0b45f 100644 --- a/src/nvidia/inc/libraries/resserv/rs_server.h +++ b/src/nvidia/inc/libraries/resserv/rs_server.h @@ -526,10 +526,24 @@ extern NV_STATUS serverAllocApiCopyOut(RsServer *pServer, NV_STATUS status, API_ * Obtain a second client handle to lock if required for the allocation. * @param[in] externalClassId External class ID of resource * @param[in] pAllocParams Class-specific allocation parameters + * @param[out] phSecondClient Second client handle to lock on success * - * @return Second client to lock, if any + * @return NV_OK on success + NV_ERR_INVALID_STATE if allocation is incorrectly configured with RS_FLAGS_DUAL_CLIENT_LOCK without having updated this function. */ -extern NvHandle serverAllocLookupSecondClient(NvU32 externalClassId, void *pAllocParams); +extern NV_STATUS serverAllocLookupSecondClient(NvU32 externalClassId, void *pAllocParams, NvHandle *phSecondClient); + +/** + * Obtain a second client handle to lock if required for the control (DISCOURAGED). + * @param[in] cmd Control call ID + * @param[in] pControlParams Control-specific parameters + * @param[in] pCookie Control call cookie to check flags for + * @param[out] phSecondClient Second client handle to lock on success + * + * @return NV_OK on success + NV_ERR_INVALID_STATE if allocation is incorrectly configured with RMCTRL_FLAGS_DUAL_CLIENT_LOCK without having updated this function. + */ +extern NV_STATUS serverControlLookupSecondClient(NvU32 cmd, void *pControlParams, RS_CONTROL_COOKIE *pCookie, NvHandle *phSecondClient); /** * Acquires a top-level lock. User-implemented. diff --git a/src/nvidia/inc/libraries/tls/tls.h b/src/nvidia/inc/libraries/tls/tls.h index f86055213f..e7a66c5bca 100644 --- a/src/nvidia/inc/libraries/tls/tls.h +++ b/src/nvidia/inc/libraries/tls/tls.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -126,6 +126,7 @@ enum { TLS_ENTRY_ID_RESSERV_1, TLS_ENTRY_ID_CURRENT_GPU_INSTANCE, TLS_ENTRY_ID_PRIORITY, + TLS_ENTRY_ID_GPUMGR_EXPANDED_GPU_VISIBILITY, TLS_ENTRY_ID_DYNAMIC, // dynamic allocations start here TLS_ENTRY_ID_TAG_START = 0x100000 // Custom tags start here }; diff --git a/src/nvidia/inc/libraries/utils/nvassert.h b/src/nvidia/inc/libraries/utils/nvassert.h index cfab009081..68cee83bf2 100644 --- a/src/nvidia/inc/libraries/utils/nvassert.h +++ b/src/nvidia/inc/libraries/utils/nvassert.h @@ -114,8 +114,6 @@ void __coverity_panic__(void); #endif // defined(__COVERITY__) #endif // !defined(COVERITY_ASSERT_FAIL) -const char *nvAssertStatusToString(NV_STATUS nvStatusIn); - /* * NV_ASSERT_FAILED, NV_ASSERT_OK_FAILED, NV_CHECK_FAILED, and NV_CHECK_OK_FAILED * These macros are defined in three flavors: @@ -146,8 +144,8 @@ void nvAssertOkFailed(NvU32 status); #define NV_ASSERT_FAILED(exprStr) \ do { \ - static const LIBOS_SECTION_LOGGING char exprStrArg[] = {exprStr}; \ - NV_PRINTF(LEVEL_ERROR, "Assertion failed: %s\n", exprStrArg); \ + NV_LOG_SPECIAL(LEVEL_ERROR, RM_GSP_LOG_SPECIAL_ASSERT_FAILED, \ + exprStr "\n"); \ nvAssertFailed(); \ COVERITY_ASSERT_FAIL(); \ PORT_BREAKPOINT(); \ @@ -155,9 +153,8 @@ void nvAssertOkFailed(NvU32 status); #define NV_ASSERT_OK_FAILED(exprStr, status) \ do { \ - static const LIBOS_SECTION_LOGGING char exprStrArg[] = {exprStr}; \ - NV_PRINTF(LEVEL_ERROR, "Assertion failed: %s (0x%08X) returned from %s\n", \ - nvAssertStatusToString(status), status, exprStrArg); \ + NV_LOG_SPECIAL(LEVEL_ERROR, RM_GSP_LOG_SPECIAL_ASSERT_OK_FAILED, \ + exprStr "\n", status); \ nvAssertOkFailed(status); \ COVERITY_ASSERT_FAIL(); \ PORT_BREAKPOINT(); \ @@ -165,15 +162,14 @@ void nvAssertOkFailed(NvU32 status); #define NV_CHECK_FAILED(level, exprStr) \ do { \ - static const LIBOS_SECTION_LOGGING char exprStrArg[] = {exprStr}; \ - NV_PRINTF(level, "Check failed: %s\n", exprStrArg); \ + NV_LOG_SPECIAL(level, RM_GSP_LOG_SPECIAL_CHECK_FAILED, \ + exprStr "\n"); \ } while(0) \ #define NV_CHECK_OK_FAILED(level, exprStr, status) \ do { \ - static const LIBOS_SECTION_LOGGING char exprStrArg[] = {exprStr}; \ - NV_PRINTF(level, "Check failed: %s (0x%08X) returned from %s\n", \ - nvAssertStatusToString(status), status, exprStrArg); \ + NV_LOG_SPECIAL(level, RM_GSP_LOG_SPECIAL_CHECK_OK_FAILED, \ + exprStr "\n", status); \ } while (0) #else // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) diff --git a/src/nvidia/inc/libraries/utils/nvprintf.h b/src/nvidia/inc/libraries/utils/nvprintf.h index d615f28cce..f0ad602134 100644 --- a/src/nvidia/inc/libraries/utils/nvprintf.h +++ b/src/nvidia/inc/libraries/utils/nvprintf.h @@ -21,13 +21,12 @@ * DEALINGS IN THE SOFTWARE. */ - /** - * @file - * @brief Standard printf logging interface - */ +/** + * Standard printf logging interface + */ -#ifndef _NV_UTILS_PRINTF_H_ -#define _NV_UTILS_PRINTF_H_ +#ifndef NVPRINTF_H +#define NVPRINTF_H #include "utils/nvprintf_level.h" @@ -62,20 +61,24 @@ extern "C" { #define MAKE_NV_PRINTF_STR MAKE_LIBOS_LOGGING_STR // NVLOG is not used on GSP-RM. -#undef NVLOG_LEVEL -#define NVLOG_LEVEL LEVEL_FATAL +#undef NVLOG_ENABLED +#define NVLOG_ENABLED 0 // Direct dmesg printing through NV_PRINTF_STRING is a no-op on GSP-RM #define NV_PRINTF_STRING(module, level, format, ...) -#if defined(GSP_PLUGIN_BUILD) - +#if defined(GSP_PLUGIN_BUILD) void log_vgpu_log_entry(const NvU64 n_args, const NvU64 * args); +#define LIBOS_LOG_ENTRY log_vgpu_log_entry +#else +void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); +#define LIBOS_LOG_ENTRY log_rm_log_entry +#endif #define NV_PRINTF(level, format, ...) do { \ if (NV_PRINTF_LEVEL_ENABLED(level)) \ { \ - LIBOS_LOG_INTERNAL(log_vgpu_log_entry, level, \ + LIBOS_LOG_INTERNAL(LIBOS_LOG_ENTRY, level, \ format, ##__VA_ARGS__); \ } \ } while (0) @@ -83,39 +86,23 @@ void log_vgpu_log_entry(const NvU64 n_args, const NvU64 * args); #define NV_PRINTF_EX(module, level, format, ...) do { \ if (NV_PRINTF_LEVEL_ENABLED(level)) \ { \ - LIBOS_LOG_INTERNAL(log_vgpu_log_entry, level, \ + LIBOS_LOG_INTERNAL(LIBOS_LOG_ENTRY, level, \ format, ##__VA_ARGS__); \ } \ } while (0) -#define NVLOG_PRINTF(...) - -#else - -void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); - -#define NV_PRINTF(level, format, ...) do { \ +#define NV_LOG_SPECIAL(level, special, ...) do { \ if (NV_PRINTF_LEVEL_ENABLED(level)) \ { \ - LIBOS_LOG_INTERNAL(log_rm_log_entry, level, \ - format, ##__VA_ARGS__); \ + LIBOS_LOG_INTERNAL_SPECIAL(LIBOS_LOG_ENTRY, level, \ + special, ##__VA_ARGS__); \ } \ } while (0) -#define NV_PRINTF_EX(module, level, format, ...) do { \ - if (NV_PRINTF_LEVEL_ENABLED(level)) \ - { \ - LIBOS_LOG_INTERNAL(log_rm_log_entry, level, \ - format, ##__VA_ARGS__); \ - } \ -} while (0) - -#endif // NVOC - #else // defined(NVRM) && NVOS_IS_LIBOS /** - * @defgroup NV_UTILS_PRINTF Utility Printing Macros + * @defgroup NV_PRINTF Utility Printing Macros * * @brief Provides a light abstraction layer for printf logging. * @@ -126,6 +113,13 @@ void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); * @{ */ +#if defined(NVRM) && !defined(NVWATCH) +#undef NV_PRINTF_PREFIX +#define NV_PRINTF_PREFIX "NVRM" +#undef NV_PRINTF_PREFIX_SEPARATOR +#define NV_PRINTF_PREFIX_SEPARATOR ": " +#endif + #ifndef NV_PRINTF_PREFIX /** * @brief Prefix to prepend to all messages printed by @ref NV_PRINTF. @@ -159,7 +153,6 @@ void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); #endif #include NV_PORT_HEADER - // Include logging header, falling back to NvLog if not provided. #ifndef NV_LOG_HEADER #define NV_LOG_HEADER "nvlog/nvlog_printf.h" @@ -197,8 +190,6 @@ void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); NV_PRINTF_EX(NV_PRINTF_MODULE, level, NV_PRINTF_ADD_PREFIX(format), ##__VA_ARGS__) #endif - - /** * @def NV_PRINTF_EX(module, level, format, args...) * @brief Extended version of the standard @ref NV_PRINTF @@ -222,7 +213,6 @@ void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); } while (0) #endif - /** * @def NV_PRINTF_STRINGS_ALLOWED * @brief This switch controls whether strings are allowed to appear in the @@ -238,16 +228,12 @@ void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); #endif #endif // NV_PRINTF_STRINGS_ALLOWED - - // // Default values for the compile time switches: // - Strings are allowed on DEBUG and QA builds, and all MODS builds // - NV_PRINTF is only available if strings are allowed // - All levels are available if NV_PRINTF is available. - - // // Special handling for RM internal prints so we have equivalent functionality // between NV_PRINTF and DBG_PRINTF. This is needed to seamlessly migrate RM to @@ -256,11 +242,6 @@ void log_rm_log_entry(const NvU64 n_args, const NvU64 * args); // #if defined(NVRM) && !defined(NVWATCH) -#undef NV_PRINTF_PREFIX -#define NV_PRINTF_PREFIX "NVRM" -#undef NV_PRINTF_PREFIX_SEPARATOR -#define NV_PRINTF_PREFIX_SEPARATOR ": " - #if NV_PRINTF_STRINGS_ALLOWED // Declare internal RM print function: @@ -285,8 +266,8 @@ void NVRM_PRINTF_FUNCTION(const char *file, // RM always has printf enabled #define NV_PRINTF_ENABLED 1 -#endif // defined(NVRM) && !defined(NVWATCH) +#endif // defined(NVRM) && !defined(NVWATCH) // // Default definitions if none are specified @@ -356,7 +337,6 @@ void NVRM_PRINTF_FUNCTION(const char *file, } while (0) #endif - // // NV_FILE and NV_FUNCTION macros are used to wrap the __FILE__ and __FUNCTION__ // macros, respectively, to enable passing them as parameters on release builds @@ -416,4 +396,4 @@ void NVRM_PRINTF_FUNCTION(const char *file, #endif //__cplusplus /// @} -#endif // _NV_UTILS_PRINTF_H_ +#endif // NVPRINTF_H diff --git a/src/nvidia/inc/libraries/utils/nvprintf_level.h b/src/nvidia/inc/libraries/utils/nvprintf_level.h index 3da4aeb442..2d6f275cc3 100644 --- a/src/nvidia/inc/libraries/utils/nvprintf_level.h +++ b/src/nvidia/inc/libraries/utils/nvprintf_level.h @@ -21,8 +21,8 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef NV_UTILS_PRINTF_LEVEL_H -#define NV_UTILS_PRINTF_LEVEL_H +#ifndef NVPRINTF_LEVEL_H +#define NVPRINTF_LEVEL_H /// @defgroup NV_PRINTF_LEVELS Printf verbosity levels /// @{ @@ -54,4 +54,11 @@ #define NV_PRINTF_LEVEL_ENABLED(level) ((level) >= NV_PRINTF_LEVEL) #endif -#endif +// Values for NV_LOG_SPECIAL to specify how log entries are encoded. +#define RM_GSP_LOG_SPECIAL_NONE 0x0 +#define RM_GSP_LOG_SPECIAL_ASSERT_FAILED 0x1 +#define RM_GSP_LOG_SPECIAL_ASSERT_OK_FAILED 0x2 +#define RM_GSP_LOG_SPECIAL_CHECK_FAILED 0x3 +#define RM_GSP_LOG_SPECIAL_CHECK_OK_FAILED 0x4 + +#endif // NVPRINTF_LEVEL_H diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c b/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c index 0a72ac2cc5..f7a530b129 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c @@ -270,8 +270,7 @@ static NV_STATUS _rmAllocGetHeapSize NvU64 *pHeapSize ) { - NV2080_CTRL_FB_GET_INFO_PARAMS fbInfoParams = {0}; - NV2080_CTRL_FB_INFO fbInfoEntries[1] = {{0}}; + NV2080_CTRL_FB_GET_INFO_V2_PARAMS fbInfoParams = {0}; NV_STATUS status; NvHandle hSubDevice; NvBool bMustFreeSubDevice; @@ -283,17 +282,14 @@ static NV_STATUS _rmAllocGetHeapSize return status; fbInfoParams.fbInfoListSize = 1; - fbInfoParams.fbInfoList = NV_PTR_TO_NvP64(&fbInfoEntries); - - fbInfoEntries[0].index = NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE; + fbInfoParams.fbInfoList[0].index = NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE; status = pContext->RmControl(pContext, hClient, hSubDevice, - NV2080_CTRL_CMD_FB_GET_INFO, + NV2080_CTRL_CMD_FB_GET_INFO_V2, &fbInfoParams, sizeof(fbInfoParams)); - - *pHeapSize = ((NvU64)fbInfoEntries[0].data << 10); + *pHeapSize = ((NvU64)fbInfoParams.fbInfoList[0].data << 10); if (bMustFreeSubDevice) { diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_control.c b/src/nvidia/interface/deprecated/rmapi_deprecated_control.c index e8b9de2d0e..3ef4b0c5a6 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_control.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_control.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,11 +28,14 @@ #include "ctrl/ctrl2080/ctrl2080bios.h" // NV2080_CTRL_CMD_BIOS_GET_INFO #include "ctrl/ctrl2080/ctrl2080bus.h" // NV2080_CTRL_CMD_BUS_GET_INFO #include "ctrl/ctrl2080/ctrl2080clk.h" // NV2080_CTRL_CMD_CLK_* +#include "ctrl/ctrl2080/ctrl2080fb.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" // NV2080_CTRL_CMD_GPU_GET_INFO #include "ctrl/ctrl2080/ctrl2080perf.h" // NV2080_CTRL_CMD_PERF_* #include "ctrl/ctrl0080/ctrl0080perf.h" // NV0080_CTRL_CMD_PERF_GET_CAPS #include "ctrl/ctrl0080/ctrl0080bsp.h" // NV0080_CTRL_CMD_BSP_GET_CAPS +#include "ctrl/ctrl0080/ctrl0080msenc.h" // NV0080_CTRL_CMD_MSENC_GET_CAPS #include "ctrl/ctrl0073/ctrl0073dp.h" // NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES +#include "rmapi/rmapi_utils.h" // // TODO - deprecation shim shouldn't depend on RM internals @@ -63,6 +66,8 @@ static NV_STATUS V2_CONVERTER(_NV2080_CTRL_CMD_BUS_GET_INFO)(API_SECURITY_INFO * static NV_STATUS V2_CONVERTER(_NV0080_CTRL_CMD_BSP_GET_CAPS)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); static NV_STATUS V2_CONVERTER(_NV2080_CTRL_CMD_GPU_GET_INFO)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); static NV_STATUS V2_CONVERTER(_NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); +static NV_STATUS V2_CONVERTER(_NV0080_CTRL_CMD_MSENC_GET_CAPS)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); +static NV_STATUS V2_CONVERTER(_NV2080_CTRL_CMD_FB_GET_INFO)(API_SECURITY_INFO *pSecInfo, DEPRECATED_CONTEXT *pContextInternal, NVOS54_PARAMETERS *pArgs); typedef struct { @@ -80,6 +85,8 @@ static const RmDeprecatedControlEntry rmDeprecatedControlTable[] = { NV0080_CTRL_CMD_BSP_GET_CAPS, V2_CONVERTER(_NV0080_CTRL_CMD_BSP_GET_CAPS), NV_FALSE}, { NV2080_CTRL_CMD_GPU_GET_INFO, V2_CONVERTER(_NV2080_CTRL_CMD_GPU_GET_INFO), NV_FALSE}, { NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES, V2_CONVERTER(_NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES), NV_FALSE}, + { NV0080_CTRL_CMD_MSENC_GET_CAPS, V2_CONVERTER(_NV0080_CTRL_CMD_MSENC_GET_CAPS), NV_FALSE}, + { NV2080_CTRL_CMD_FB_GET_INFO, V2_CONVERTER(_NV2080_CTRL_CMD_FB_GET_INFO), NV_FALSE}, { 0, NULL, NV_FALSE } }; @@ -98,6 +105,7 @@ RmDeprecatedControlHandler RmDeprecatedGetControlHandler(NVOS54_PARAMETERS *pArg NV_STATUS nvStatus; RsClient *pClient = NULL; POBJGPU pGpu = NULL; + NvBool gssLegacyVgpuCall = NV_FALSE; NV_CHECK_OK_OR_ELSE(nvStatus, LEVEL_ERROR, @@ -131,8 +139,10 @@ RmDeprecatedControlHandler RmDeprecatedGetControlHandler(NVOS54_PARAMETERS *pArg } } + gssLegacyVgpuCall = ((pGpu != NULL) && IS_VIRTUAL(pGpu)); + // Check if the cmd is part of the legacy GSS control. - if (pGpu && IS_GSP_CLIENT(pGpu) && IsGssLegacyCall(pArgs->cmd)) + if (pGpu != NULL && IsGssLegacyCall(pArgs->cmd) && (IS_GSP_CLIENT(pGpu) || gssLegacyVgpuCall)) { extern NV_STATUS RmGssLegacyRpcCmd(API_SECURITY_INFO*, DEPRECATED_CONTEXT*, NVOS54_PARAMETERS*); return RmGssLegacyRpcCmd; @@ -159,6 +169,7 @@ typedef struct NvU32 paramStructOffset; NvU32 listSizeOffset; NvBool bListSizeIsCount; + NvU32 maxListSize; } params[CONTROL_PARAM_TOKEN_MAX_POINTERS]; NvU32 paramCount; } CONTROL_PARAM_TOKEN; @@ -177,6 +188,7 @@ static void _ctrlparamsTokenInit pToken->params[0].paramStructOffset = 0; pToken->params[0].listSizeOffset = (NvU32)~0; pToken->params[0].bListSizeIsCount = NV_FALSE; + pToken->params[0].maxListSize = 0; pToken->paramCount = 1; } @@ -186,7 +198,8 @@ static NV_STATUS _ctrlparamsTokenAddEmbeddedPtr NvU32 paramStructOffset, NvU32 listSizeOffset, NvBool bListSizeIsCount, - NvU32 listItemSize + NvU32 listItemSize, + NvU32 maxListSize ) { if (pToken->paramCount >= CONTROL_PARAM_TOKEN_MAX_POINTERS) @@ -202,6 +215,7 @@ static NV_STATUS _ctrlparamsTokenAddEmbeddedPtr pToken->params[pToken->paramCount].listSizeOffset = listSizeOffset; pToken->params[pToken->paramCount].bListSizeIsCount = bListSizeIsCount; pToken->params[pToken->paramCount].paramSize = listItemSize; + pToken->params[pToken->paramCount].maxListSize = maxListSize; pToken->paramCount++; return NV_OK; } @@ -210,10 +224,10 @@ static NV_STATUS _ctrlparamsTokenAddEmbeddedPtr _ctrlparamsTokenInit(&token, pArgs->params, sizeof(paramType)) #define CTRL_PARAMS_TOKEN_ADD_EMBEDDED(token, paramType, pArgs, listField, listSizeField, \ - listSizeIsCount, listElemType) \ + listSizeIsCount, listElemType, maxListSize) \ _ctrlparamsTokenAddEmbeddedPtr(&token, NV_OFFSETOF(paramType, listField), \ NV_OFFSETOF(paramType, listSizeField), \ - listSizeIsCount, sizeof(listElemType)) + listSizeIsCount, sizeof(listElemType), maxListSize) static NV_STATUS ctrlparamAcquire ( @@ -255,6 +269,12 @@ static NV_STATUS ctrlparamAcquire continue; } + if (listItemCount > pToken->params[i].maxListSize) + { + status = NV_ERR_OUT_OF_RANGE; + goto done; + } + // // Either the listItemCount is the actual count of items, in which // case we need to read the size of individual items and (safely) @@ -356,16 +376,19 @@ static void ctrlparamRelease do { \ NV_STATUS status; \ CONTROL_PARAM_TOKEN token; \ + newParamsType *pParams2; \ + NvU64 maxListSize = sizeof(pParams2->newListField); \ + if (listSizeIsCount) \ + maxListSize /= sizeof(listElemType); \ CTRL_PARAMS_TOKEN_INIT(token, oldParamsType, pArgs); \ \ NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, \ CTRL_PARAMS_TOKEN_ADD_EMBEDDED(token, oldParamsType, pArgs, oldListField, \ - listSizeField, listSizeIsCount, listElemType)); \ + listSizeField, listSizeIsCount, listElemType, maxListSize)); \ status = ctrlparamAcquire(pSecInfo, &token, pArgs); \ if (status == NV_OK) \ { \ oldParamsType *pParams = NvP64_VALUE(pArgs->params); \ - newParamsType *pParams2; \ NvU32 listSize = listSizeIsCount ? /* overflow checked in ctrlparamAcquire() */ \ pParams->listSizeField * sizeof(listElemType) : \ pParams->listSizeField; \ @@ -609,14 +632,15 @@ static NV_STATUS V2_CONVERTER(_NV0080_CTRL_CMD_BSP_GET_CAPS) NV_TRUE, // return path, ie, copy out back to user // Custom data in from user { - if (pParams->capsTblSize != NV0080_CTRL_BSP_CAPS_TBL_SIZE) - { - NV_PRINTF(LEVEL_ERROR, "pParams capsTblSize %d invalid\n", - pParams->capsTblSize); - portMemFree(pParams2); - return NV_ERR_INVALID_ARGUMENT; - } - pParams2->instanceId = pParams->instanceId; + if (pParams->capsTblSize != NV0080_CTRL_BSP_CAPS_TBL_SIZE) + { + NV_PRINTF(LEVEL_ERROR, "pParams capsTblSize %d invalid\n", + pParams->capsTblSize); + portMemFree(pParams2); + ctrlparamRelease(pSecInfo, &token, pArgs); + return NV_ERR_INVALID_ARGUMENT; + } + pParams2->instanceId = pParams->instanceId; }, // Custom data out back to user {} // array has been filled. @@ -742,3 +766,56 @@ static NV_STATUS V2_CONVERTER(_NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES) return status; } +static NV_STATUS V2_CONVERTER(_NV0080_CTRL_CMD_MSENC_GET_CAPS) +( + API_SECURITY_INFO *pSecInfo, + DEPRECATED_CONTEXT *pContextInternal, + NVOS54_PARAMETERS *pArgs +) +{ + CONVERT_TO_V2_EX(NV0080_CTRL_CMD_MSENC_GET_CAPS_V2, // newCmd + NV0080_CTRL_MSENC_GET_CAPS_PARAMS, // oldParamsType + NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS,// newParamsType + capsTbl, // oldListField + capsTbl, // newListField + capsTblSize, // listSizeField + NV_TRUE, // listSizeIsCount + NvU8, // listElemType + NV_TRUE, // for below custom to run, this must be TRUE. + NV_TRUE, // return path, ie, copy out back to user + // Custom data in from user + { + if (pParams->capsTblSize != NV0080_CTRL_MSENC_CAPS_TBL_SIZE) + { + NV_PRINTF(LEVEL_ERROR, "pParams capsTblSize %d invalid\n", + pParams->capsTblSize); + portMemFree(pParams2); + ctrlparamRelease(pSecInfo, &token, pArgs); + return NV_ERR_INVALID_ARGUMENT; + } + pParams2->instanceId = 0; + }, + // Custom data out back to user + {} // array has been filled. + ); +} + +static NV_STATUS V2_CONVERTER(_NV2080_CTRL_CMD_FB_GET_INFO) +( + API_SECURITY_INFO *pSecInfo, + DEPRECATED_CONTEXT *pContextInternal, + NVOS54_PARAMETERS *pArgs +) +{ + CONVERT_TO_V2(NV2080_CTRL_CMD_FB_GET_INFO_V2, // newCmd + NV2080_CTRL_FB_GET_INFO_PARAMS, // oldParamsType + NV2080_CTRL_FB_GET_INFO_V2_PARAMS,// newParamsType + fbInfoList, // oldListField + fbInfoList, // newListField + fbInfoListSize, // listSizeField + NV_TRUE, // listSizeIsCount + NV2080_CTRL_FB_INFO, // listElemType + NV_TRUE, // for below custom to run, this must be TRUE. + NV_TRUE // return path, ie, copy out back to user + ); +} diff --git a/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c b/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c index c18384e92d..a9f3c50f20 100644 --- a/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c +++ b/src/nvidia/interface/deprecated/rmapi_deprecated_vidheapctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -137,6 +137,8 @@ _rmVidHeapControlAllocCommon if (pUserParams->flags & NVOS32_ALLOC_FLAGS_VIRTUAL) externalClassId = NV50_MEMORY_VIRTUAL; + else if (FLD_TEST_DRF(OS32, _ATTR2, _USE_EGM, _TRUE, pUserParams->attr2)) + externalClassId = NV_MEMORY_EXTENDED_USER; else if (FLD_TEST_DRF(OS32, _ATTR, _LOCATION, _VIDMEM, pUserParams->attr)) externalClassId = NV01_MEMORY_LOCAL_USER; else @@ -181,6 +183,7 @@ _nvos32FunctionAllocSize _IN(width, AllocSize.width) \ _IN_OUT(size, AllocSize.size) \ _IN(alignment, AllocSize.alignment) \ + _IN(numaNode, AllocSize.numaNode) \ _IN_OUT(offset, AllocSize.offset) \ _IN_OUT(attr, AllocSize.attr) \ _IN_OUT(attr2, AllocSize.attr2) \ @@ -226,6 +229,7 @@ _nvos32FunctionAllocSizeRange _IN(rangeHi, AllocSizeRange.rangeEnd) \ _IN_OUT(size, AllocSizeRange.size) \ _IN(alignment, AllocSizeRange.alignment) \ + _IN(numaNode, AllocSizeRange.numaNode) \ _IN_OUT(offset, AllocSizeRange.offset) \ _IN_OUT(attr, AllocSizeRange.attr) \ _IN_OUT(attr2, AllocSizeRange.attr2) \ @@ -287,6 +291,7 @@ _nvos32FunctionAllocTiledPitchHeight _IN(pitch, AllocTiledPitchHeight.pitch) \ _IN_OUT(size, AllocTiledPitchHeight.size) \ _IN(alignment, AllocTiledPitchHeight.alignment) \ + _IN(numaNode, AllocTiledPitchHeight.numaNode) \ _IN_OUT(offset, AllocTiledPitchHeight.offset) \ _IN_OUT(attr, AllocTiledPitchHeight.attr) \ _IN_OUT(attr2, AllocTiledPitchHeight.attr2) \ @@ -341,8 +346,7 @@ _nvos32FunctionInfo NVOS32_PARAMETERS *pArgs ) { - NV2080_CTRL_FB_GET_INFO_PARAMS fbInfoParams = {0}; - NV2080_CTRL_FB_INFO fbInfoEntries[6] = {{0}}; + NV2080_CTRL_FB_GET_INFO_V2_PARAMS fbInfoParams = {0}; NV_STATUS status; NvHandle hSubDevice; NvBool bMustFreeSubDevice; @@ -356,26 +360,25 @@ _nvos32FunctionInfo return status; fbInfoParams.fbInfoListSize = 6; - fbInfoParams.fbInfoList = NV_PTR_TO_NvP64(&fbInfoEntries); - fbInfoEntries[0].index = NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE; - fbInfoEntries[1].index = NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE; - fbInfoEntries[2].index = NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB; - fbInfoEntries[3].index = NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB; - fbInfoEntries[4].index = NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB; - fbInfoEntries[5].index = NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB; + fbInfoParams.fbInfoList[0].index = NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE; + fbInfoParams.fbInfoList[1].index = NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE; + fbInfoParams.fbInfoList[2].index = NV2080_CTRL_FB_INFO_INDEX_FB_TAX_SIZE_KB; + fbInfoParams.fbInfoList[3].index = NV2080_CTRL_FB_INFO_INDEX_HEAP_BASE_KB; + fbInfoParams.fbInfoList[4].index = NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_SIZE_KB; + fbInfoParams.fbInfoList[5].index = NV2080_CTRL_FB_INFO_INDEX_LARGEST_FREE_REGION_BASE_KB; status = pContext->RmControl(pContext, hClient, hSubDevice, - NV2080_CTRL_CMD_FB_GET_INFO, + NV2080_CTRL_CMD_FB_GET_INFO_V2, &fbInfoParams, sizeof(fbInfoParams)); - pArgs->free = ((NvU64)fbInfoEntries[0].data << 10); - pArgs->total = ((NvU64)fbInfoEntries[1].data << 10); - pArgs->total += ((NvU64)fbInfoEntries[2].data << 10); // For vGPU, add FB tax incurred by host RM - pArgs->data.Info.base = ((NvU64)fbInfoEntries[3].data << 10); - pArgs->data.Info.size = ((NvU64)fbInfoEntries[4].data << 10); - pArgs->data.Info.offset = ((NvU64)fbInfoEntries[5].data << 10); + pArgs->free = ((NvU64)fbInfoParams.fbInfoList[0].data << 10); + pArgs->total = ((NvU64)fbInfoParams.fbInfoList[1].data << 10); + pArgs->total += ((NvU64)fbInfoParams.fbInfoList[2].data << 10); // For vGPU, add FB tax incurred by host RM + pArgs->data.Info.base = ((NvU64)fbInfoParams.fbInfoList[3].data << 10); + pArgs->data.Info.size = ((NvU64)fbInfoParams.fbInfoList[4].data << 10); + pArgs->data.Info.offset = ((NvU64)fbInfoParams.fbInfoList[5].data << 10); if (bMustFreeSubDevice) { diff --git a/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c b/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c index 58287f0377..c213be0ff8 100644 --- a/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c +++ b/src/nvidia/interface/deprecated/rmapi_gss_legacy_control.c @@ -24,6 +24,8 @@ #include "gpu/gpu.h" #include "core/locks.h" +#include "vgpu/rpc.h" +#include "rmapi/rmapi_utils.h" #include "g_finn_rm_api.h" @@ -99,13 +101,26 @@ NV_STATUS RmGssLegacyRpcCmd if (status != NV_OK) goto done; - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - status = pRmApi->Control(pRmApi, - pArgs->hClient, - pArgs->hObject, - pArgs->cmd, - pKernelParams, - pArgs->paramsSize); + if (IS_VIRTUAL(pGpu)) + { + NV_RM_RPC_API_CONTROL(pGpu, + pArgs->hClient, + pArgs->hObject, + pArgs->cmd, + pKernelParams, + pArgs->paramsSize, + status); + } + else + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + status = pRmApi->Control(pRmApi, + pArgs->hClient, + pArgs->hObject, + pArgs->cmd, + pKernelParams, + pArgs->paramsSize); + } done: if (gpuMaskRelease != 0) diff --git a/src/nvidia/interface/nv_sriov_defines.h b/src/nvidia/interface/nv_sriov_defines.h index 8208a5ff7d..1edb1aac17 100644 --- a/src/nvidia/interface/nv_sriov_defines.h +++ b/src/nvidia/interface/nv_sriov_defines.h @@ -49,12 +49,12 @@ // Top half serviced interrupts (serviced by both guest and host) -#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST 2:2 -#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST_EN (0x1) -#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST_DIS (0x0) -#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_REQUEST) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_LOCKLESS_OP_REQUEST 2:2 +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_LOCKLESS_OP_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_LOCKLESS_OP_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_LOCKLESS_OP_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_LOCKLESS_OP_REQUEST) -#define NV_DOORBELL_NOTIFY_LEAF_TOP_HALF_MASK NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE) +#define NV_DOORBELL_NOTIFY_LEAF_TOP_HALF_MASK NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_LOCKLESS_OP_HANDLE) // Host PF interrupts diff --git a/src/nvidia/interface/nv_uvm_types.h b/src/nvidia/interface/nv_uvm_types.h index 2bf5b24259..5a020fb62f 100644 --- a/src/nvidia/interface/nv_uvm_types.h +++ b/src/nvidia/interface/nv_uvm_types.h @@ -131,6 +131,8 @@ typedef struct UvmGpuMemoryInfo_tag // This is only valid if deviceDescendant is NV_TRUE. // When egm is NV_TRUE, this is also the UUID of the GPU // for which EGM is local. + // If the GPU has SMC enabled, the UUID is the GI UUID. + // Otherwise, it is the UUID for the physical GPU. // Note: If the allocation is owned by a device in // an SLI group and the allocation is broadcast // across the SLI group, this UUID will be any one @@ -544,6 +546,10 @@ typedef struct UvmGpuP2PCapsParams_tag // the GPUs are direct peers. NvU32 peerIds[2]; + // Out: peerId[i] contains gpu[i]'s EGM peer id of gpu[1 - i]. Only defined + // if the GPUs are direct peers and EGM enabled in the system. + NvU32 egmPeerIds[2]; + // Out: UVM_LINK_TYPE NvU32 p2pLink; @@ -572,8 +578,11 @@ typedef struct UvmPlatformInfo_tag // Out: ATS (Address Translation Services) is supported NvBool atsSupported; - // Out: AMD SEV (Secure Encrypted Virtualization) is enabled - NvBool sevEnabled; + // Out: True if HW trusted execution, such as AMD's SEV-SNP or Intel's TDX, + // is enabled in the VM, indicating that Confidential Computing must be + // also enabled in the GPU(s); these two security features are either both + // enabled, or both disabled. + NvBool confComputingEnabled; } UvmPlatformInfo; typedef struct UvmGpuClientInfo_tag @@ -604,7 +613,8 @@ typedef struct UvmGpuInfo_tag // Printable gpu name char name[UVM_GPU_NAME_LENGTH]; - // Uuid of this gpu + // Uuid of the physical GPU or GI UUID if nvUvmInterfaceGetGpuInfo() + // requested information for a valid SMC partition. NvProcessorUuid uuid; // Gpu architecture; NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_* @@ -688,8 +698,12 @@ typedef struct UvmGpuInfo_tag NvU64 nvswitchMemoryWindowStart; // local EGM properties + // NV_TRUE if EGM is enabled NvBool egmEnabled; + // Peer ID to reach local EGM when EGM is enabled NvU8 egmPeerId; + // EGM base address to offset in the GMMU PTE entry for EGM mappings + NvU64 egmBaseAddr; } UvmGpuInfo; typedef struct UvmGpuFbInfo_tag @@ -778,21 +792,21 @@ typedef NV_STATUS (*uvmEventResume_t) (void); /******************************************************************************* uvmEventStartDevice This function will be called by the GPU driver once it has finished its - initialization to tell the UVM driver that this GPU has come up. + initialization to tell the UVM driver that this physical GPU has come up. */ typedef NV_STATUS (*uvmEventStartDevice_t) (const NvProcessorUuid *pGpuUuidStruct); /******************************************************************************* uvmEventStopDevice - This function will be called by the GPU driver to let UVM know that a GPU - is going down. + This function will be called by the GPU driver to let UVM know that a + physical GPU is going down. */ typedef NV_STATUS (*uvmEventStopDevice_t) (const NvProcessorUuid *pGpuUuidStruct); /******************************************************************************* uvmEventIsrTopHalf_t This function will be called by the GPU driver to let UVM know - that an interrupt has occurred. + that an interrupt has occurred on the given physical GPU. Returns: NV_OK if the UVM driver handled the interrupt @@ -894,11 +908,6 @@ typedef struct UvmGpuFaultInfo_tag // CSL context used for performing decryption of replayable faults when // Confidential Computing is enabled. UvmCslContext cslCtx; - - // Indicates whether UVM owns the replayable fault buffer. - // The value of this field is always NV_TRUE When Confidential Computing - // is disabled. - NvBool bUvmOwnsHwFaultBuffer; } replayable; struct { diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index df02e1cbc1..05cfa54b84 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -447,6 +447,15 @@ #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_NCOH NV_REG_STR_RM_INST_LOC_NCOH #define NV_REG_STR_RM_INST_LOC_4_FECS_EVENT_BUF_VID NV_REG_STR_RM_INST_LOC_VID +// +// Overrides for the GFXP SETUP buffer +// +#define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER 25:24 // GFXP SETUP buffer +#define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_DEFAULT NV_REG_STR_RM_INST_LOC_DEFAULT +#define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_COH NV_REG_STR_RM_INST_LOC_COH +#define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_NCOH NV_REG_STR_RM_INST_LOC_NCOH +#define NV_REG_STR_RM_INST_LOC_4_GFXP_SETUP_BUFFER_VID NV_REG_STR_RM_INST_LOC_VID + #define NV_REG_STR_RM_GSP_STATUS_QUEUE_SIZE "RmGspStatusQueueSize" // TYPE DWORD // Set the GSP status queue size in KB (for GSP to CPU RPC status and event communication) @@ -707,6 +716,23 @@ #define NV_REG_STR_RM_L2_CLEAN_FB_PULL_DISABLED (0x00000001) #define NV_REG_STR_RM_L2_CLEAN_FB_PULL_DEFAULT (0x00000000) +// +// Type: DWORD +// This regkey overrides BL8, 16, and 24 kinds to only be of GENERIC_MEMORY or +// GENERIC_MEMORY_COMPRESSIBLE kinds. +// 0 - No override +// > 0 - Override memkind to GMK +// bit 0: override BL8 type +// bit 1: override BL16 type +// bit 2: override BL24 type +// ex. 0x00001000 means override all types +#define NV_REG_STR_RM_OVERRIDE_TO_GMK "RMOverrideToGMK" +#define NV_REG_STR_RM_OVERRIDE_TO_GMK_DISABLED (0x00000000) +#define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL8 (0x00000001) +#define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL16 (0x00000002) +#define NV_REG_STR_RM_OVERRIDE_TO_GMK_BL24 (0x00000004) +#define NV_REG_STR_RM_OVERRIDE_TO_GMK_ALL (0x00000007) + // Enable backtrace dumping at assertion failure. // If physical RM or RCDB is unavailable, then this regkey controls the behaviour of backtrace // printing. @@ -824,15 +850,6 @@ #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES_NO (0x00000000) #define NV_REG_STR_RM_ENABLE_PMA_MANAGED_PTABLES_DEFAULT (0x00000001) -// -// Type DWORD -// Controls enable of Address Tree memory tracking instead of regmap -// for the PMA memory manager. -// -#define NV_REG_STR_RM_ENABLE_ADDRTREE "RMEnableAddrtree" -#define NV_REG_STR_RM_ENABLE_ADDRTREE_YES (0x00000001) -#define NV_REG_STR_RM_ENABLE_ADDRTREE_NO (0x00000000) - // // Type DWORD // Disable global CeUtils instance creation after fifo scheduling enablement @@ -893,7 +910,36 @@ // Encoding: Boolean // If set, allow MapMemoryDma calls to be made on channel objects +#define NV_REG_STR_SECONDARY_BUS_RESET_ENABLED "RMSecBusResetEnable" +// Type DWORD +// Encoding boolean +// Default FALSE + +#define NV_REG_STR_FORCE_PCIE_CONFIG_SAVE "RMForcePcieConfigSave" +// Type DWORD +// Encoding boolean +// Default FALSE + +#define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE "RMPcieFlrDevinitTimeout" +#define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE_MIN_ALLOWED 1 +#define NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE_MAX_ALLOWED 4 +// Type DWORD +// Regkey to change FLR devinit timeout value. Increase in scale value increases +// the timeout value and vice versa. +// Scale value has to be greater than 0 since flr devinit timeout can't be 0 +// Scale value for now is limited to 4 which translates to maximum of +// 3.6seconds(900ms*4) timeout value. // + +#define NV_REG_STR_RM_PCIE_FLR_POLICY "RMPcieFLRPolicy" +#define NV_REG_STR_RM_PCIE_FLR_POLICY_DEFAULT 0 +#define NV_REG_STR_RM_PCIE_FLR_POLICY_FORCE_DISABLE 1 +// Type DWORD +// Regkey to force disable Function Level Reset +// Note that we don't want to provision for force enabling FLR since as per current design - +// For Pre-Turing boards, FLR will be strictly disabled since it's not supported in HW +// Default policy could be different for different boards though + // Type DWORD // Encoding Numeric Value // Overrides chipset-based P2P configurations. @@ -1166,17 +1212,15 @@ // // 0 - Disables Video event trace usage (default) // > 0 - Enable video event trace and define sizes for different buffers -// bit 0 - 15: sizes of the hardware staging buffer in 4K pages // bit 16 - 30: sizes of the event buffer in 4K pages // bit 31 - 31: Enable always logging: // By default, video engines only log video events when there is // at least one eventbuffer bound and enabled. If this flag is set, // video engines will always log events even without a consumer. This // is helpful for debugging purposes. -// Example: 0x01000008 means a 32K staging buffer and a 1M event buffer. +// Example: 0x01000000 means 1MB event buffer. #define NV_REG_STR_RM_VIDEO_EVENT_TRACE "RmVideoEventTrace" #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED (0x00000000) -#define NV_REG_STR_RM_VIDEO_EVENT_TRACE_STAGING_BUFFER_SIZE_IN_4k 15:0 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_EVENT_BUFFER_SIZE_IN_4k 30:16 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG 31:31 #define NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_DISABLED 0x00000000 @@ -1699,6 +1743,19 @@ // between every consecutive probe retries until success. // +#define NV_REG_STR_RM_UUID_BASED_MEMORY_SHARING "RmUuidBasedMemorySharing" +// Type DWORD +// Enable UUID-based memory sharing (import/export) +// +// 0 - Default +// 0 - Disabled +// 1 - Enabled +// +// The security framework to support multi-tenancy when using UUID-based memory +// sharing is not yet implemented. Thus, the users are advised to enable +// this regkey only in single-tenant or controlled/trusted environments. +// + // Enable plugin logs in ftrace buffer. // 0 - Default // 0 - Disabled @@ -2062,6 +2119,18 @@ #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE_DISABLED 0x0 #define NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS_AUTO_UPDATE_ENABLED 0x1 +// +// Type: DWORD +// +// If the midpath spinning feature of the GPU lock is enabled. +// +// 0 (default) - Midpath Spinning disabled +// 1 - Midpath spinning enabled +// +#define NV_REG_STR_RM_GPU_LOCK_MIDPATH "RMGpuLockMidpath" +#define NV_REG_STR_RM_GPU_LOCK_MIDPATH_DISABLED 0x00000000 +#define NV_REG_STR_RM_GPU_LOCK_MIDPATH_ENABLED 0x00000001 + // // This regkey controls the GPU load failure test. // Supported only on DEBUG, DEVELOP, or RELEASE drivers built with the parameter INSTRUMENT_RM=true @@ -2087,4 +2156,112 @@ #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_STAGE_POSTLOAD 0x00000004 #define NV_REG_STR_GPU_LOAD_FAILURE_TEST_ENGINEINDEX 31:5 +// +// Type: DWORD +// Encoding: +// 0 - Disable MIG auto online mode on driver load +// 1 - Enable MIG auto online mode on driver load +// +#define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE "RMSetMIGAutoOnlineMode" +#define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE_DISABLED 0 +#define NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE_ENABLED 1 + +// +// Type: DWORD +// Encoding: +// 0 - Disable multi gpu mode +// 1 - Enable protected pcie +// +#define NV_REG_STR_RM_CC_MULTI_GPU_MODE "RmCCMultiGpuMode" +#define NV_REG_STR_RM_CC_MULTI_GPU_MODE_NONE 0x00000000 +#define NV_REG_STR_RM_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001 + +// This regkey allows RM to access CPR vidmem over BARs when HCC devtools mode is ON +#define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC "RmForceBarAccessOnHcc" +#define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC_NO 0x00000000 +#define NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC_YES 0x00000001 + +// +// TYPE DWORD +// This regkey allows to change the state of NVENC sessions stats reporting. +// Note : Currently only used and works for Grid. +// 0 - Disable NVENC session stats reporting. +// 1 - Enable NVENC session stats reporting. +// +#define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE "EncSessionStatsReportingState" +#define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_DISABLED 0x00000000 +#define NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_ENABLED 0x00000001 + +// TYPE DWORD +// Set to provide ECC state in guest +// Used for vGPU +// The value default is set if ECC is enabled in USM profile. +// +#define NV_REG_STR_RM_GUEST_ECC_STATE "RMGuestECCState" +#define NV_REG_STR_RM_GUEST_ECC_STATE_DISABLED 0x00000000 +#define NV_REG_STR_RM_GUEST_ECC_STATE_ENABLED 0x00000001 +#define NV_REG_STR_RM_GUEST_ECC_STATE_DEFAULT 0x00000001 + +// +// Type DWORD +// This regkey force-disables write-combine iomap allocations, used for chipsets where +// write-combine is broken. +// +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC "RmForceDisableIomapWC" +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES 0x00000001 +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO 0x00000000 +#define NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_DEFAULT NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_NO + +// +// Type: Dword +// This regkey toggles whether to release API lock during initialization to +// allow multiple GPUS to initialize in parallel +// 0 - API lock will not be released +// 1 - API lock will be released +// 2 - API lock release determined by platform (default) +// +#define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING "RmRelaxedGspInitLocking" +#define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DISABLE 0x00000000 +#define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_ENABLE 0x00000001 +#define NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DEFAULT 0x00000002 + +// +// Regkey to configure Per VM RunList. +// Type Dword +// BIT 0:0 - Overall PVMRL enable/disable. +// 0 - Disable / Default - 1 HW runlist per engine. +// 1 - Enable - 1 SW runlist per VM for some engines. +// BIT 1:1 - Adaptive Round Robin Scheduler +// 0 - Enable / Default - Use Adaptive Round Robin Scheduler +// 1 - Disable - Use Legacy PVMRL +// BIT 7:4 - PVMRL scheduler to run. +// 0 - equal share / Default - equal share amongst running vGPUs. +// 1 - fixed share - fixed share of the physical GPU. +// BIT 21:12 - PVMRL Scheduling frequency. +// 0 - Default timeslice. +// F - Timeslice = 1000 / F. +// BIT 23:16 - PVMRL timeslice in ms (Milli-seconds). +// 0 - Default timeslice. +// T - Timeslice of T ms. +// BIT 31:24 - ARR Average Factor +// 0 - Default Average Factor +// F - Average Factor = F +// +#define NV_REG_STR_RM_PVMRL "RmPVMRL" +#define NV_REG_STR_RM_PVMRL_ENABLE 0:0 +#define NV_REG_STR_RM_PVMRL_ENABLE_DEFAULT 0x00000000 +#define NV_REG_STR_RM_PVMRL_ENABLE_NO 0x00000000 +#define NV_REG_STR_RM_PVMRL_ENABLE_YES 0x00000001 +#define NV_REG_STR_RM_PVMRL_ARR_DISABLE 1:1 +#define NV_REG_STR_RM_PVMRL_ARR_DISABLE_DEFAULT 0x00000000 +#define NV_REG_STR_RM_PVMRL_ARR_DISABLE_NO 0x00000000 +#define NV_REG_STR_RM_PVMRL_ARR_DISABLE_YES 0x00000001 +#define NV_REG_STR_RM_PVMRL_SCHED_POLICY 7:4 +#define NV_REG_STR_RM_PVMRL_SCHED_POLICY_DEFAULT 0x00000000 +#define NV_REG_STR_RM_PVMRL_SCHED_POLICY_VGPU_EQUAL_SHARE 0x00000000 +#define NV_REG_STR_RM_PVMRL_SCHED_POLICY_VGPU_FIXED_SHARE 0x00000001 +#define NV_REG_STR_RM_PVMRL_FREQUENCY 21:12 +#define NV_REG_STR_RM_PVMRL_TIMESLICE 23:16 +#define NV_REG_STR_RM_PVMRL_AVERAGE_FACTOR 31:24 + #endif // NVRM_REGISTRY_H diff --git a/src/nvidia/kernel/inc/gpu/error_cont.h b/src/nvidia/kernel/inc/gpu/error_cont.h new file mode 100644 index 0000000000..703e48998d --- /dev/null +++ b/src/nvidia/kernel/inc/gpu/error_cont.h @@ -0,0 +1,225 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file error_cont.h + * @brief Holds data structures, defines and policy table required by the + * Ampere Error Containment feature / code. + */ + +#ifndef _ERROR_CONT_H_ +#define _ERROR_CONT_H_ + +/* ------------------------ Includes ---------------------------------------- */ +#include "core/core.h" +#include "kernel/gpu/gpu_engine_type.h" +#include "nverror.h" + +/* ------------------------ Forward Definitions ----------------------------- */ + +typedef struct Device Device; + +/* ------------------------ Datatypes --------------------------------------- */ + +/*! + * Error Containment error id enum + */ +typedef enum _NV_ERROR_CONT_ERR_ID +{ + NV_ERROR_CONT_ERR_ID_E01_FB_ECC_DED = 0, // FD Error ID: E01: FB ECC DED + NV_ERROR_CONT_ERR_ID_E02_FB_ECC_DED_IN_CBC_STORE = 1, // FD Error ID: E02: FB ECC DED in CBC + NV_ERROR_CONT_ERR_ID_E05_LTC_ECC_DSTG = 2, // FD Error ID: E05: LTC ECC in data region + NV_ERROR_CONT_ERR_ID_E06_LTC_UNSUPPORTED_CLIENT_POISON = 3, // FD Error ID: E06: LTC Unsupported client poison + NV_ERROR_CONT_ERR_ID_E07_LTC_ECC_TSTG = 4, // FD Error ID: E07: LTC Tag Parity error + NV_ERROR_CONT_ERR_ID_E08_LTC_ECC_RSTG = 5, // FD Error ID: E08: LTC CBC Parity error + NV_ERROR_CONT_ERR_ID_E09_FBHUB_POISON = 6, // FD Error ID: E09: FBHUB Poison error + NV_ERROR_CONT_ERR_ID_E10_SM_POISON = 7, // FD Error ID: E10: SM Poison error + NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL = 8, // FD Error ID: E12: CE Poison error in user channel + NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL = 9, // FD Error ID: E12: CE Poison error in kernel channel + NV_ERROR_CONT_ERR_ID_E13_MMU_POISON = 10, // FD Error ID: E13: MMU Poison error + NV_ERROR_CONT_ERR_ID_E16_GCC_POISON = 11, // FD Error ID: E16: GCC Poison error + NV_ERROR_CONT_ERR_ID_E17_CTXSW_POISON = 12, // FD Error ID: E17: GPCCS/TPCCS Poison error + NV_ERROR_CONT_ERR_ID_E20_XALEP_POISON = 13, // FD Error ID: E20: XALEP_EGRESS Poison error +} NV_ERROR_CONT_ERR_ID; + +/*! + * Error Containment settings per error id, when SMC memory partitioning is disable or enabled. + */ +typedef struct _NV_ERROR_CONT_SMC_DIS_EN_SETTING +{ + NvU32 rcErrorCode; + NvBool bGpuResetReqd; + NvBool bGpuDrainAndResetReqd; + NvBool bPrintSmcPartitionInfo; + NvU32 nv2080Notifier; +} NV_ERROR_CONT_SMC_DIS_EN_SETTING; + +/*! + * Error Containment state table tracking policy settings for each error id + */ +typedef struct _NV_ERROR_CONT_STATE_TABLE +{ + NV_ERROR_CONT_ERR_ID errorCode; + NV_ERROR_CONT_SMC_DIS_EN_SETTING smcDisEnSetting[2]; // 0: SMC memory partitioning disabled, + // 1: SMC memory partitioning enabled +} NV_ERROR_CONT_STATE_TABLE; + +/*! + * Struct for LTC location + */ +typedef struct _NV_ERROR_CONT_LOCATION_LTC +{ + NvU32 partition; + NvU32 slice; +} NV_ERROR_CONT_LOCATION_LTC; + +/*! + * Struct for DRAM location + */ +typedef struct _NV_ERROR_CONT_LOCATION_DRAM +{ + NvU32 partition; + NvU32 subPartition; + NvU64 physicalAddress; +} NV_ERROR_CONT_LOCATION_DRAM; + +/*! + * Struct for Engine id + */ +typedef struct _NV_ERROR_CONT_LOCATION_ENG_ID +{ + RM_ENGINE_TYPE rmEngineId; + Device *pDevice; +} NV_ERROR_CONT_LOCATION_ENG_ID; + +/*! + * Error Containment location type + */ +typedef enum _NV_ERROR_CONT_LOCATION_TYPE +{ + NV_ERROR_CONT_LOCATION_TYPE_NONE = 0, // No location information available + NV_ERROR_CONT_LOCATION_TYPE_DRAM = 1, // DRAM location + NV_ERROR_CONT_LOCATION_TYPE_LTC = 2, // LTC location + NV_ERROR_CONT_LOCATION_TYPE_ENGINE = 3 // Engine location +} NV_ERROR_CONT_LOCATION_TYPE; + +/*! + * Union for Error Containment location information + */ +typedef union _NV_ERROR_CONT_LOCATION_INFO +{ + NV_ERROR_CONT_LOCATION_DRAM dramLoc; // DRAM location + NV_ERROR_CONT_LOCATION_LTC ltcLoc; // LTC location + NV_ERROR_CONT_LOCATION_ENG_ID engineLoc; // Engine location +} NV_ERROR_CONT_LOCATION_INFO; + +typedef struct _NV_ERROR_CONT_LOCATION +{ + NV_ERROR_CONT_LOCATION_TYPE locType; + NV_ERROR_CONT_LOCATION_INFO locInfo; +} NV_ERROR_CONT_LOCATION; + +/* ------------------------ Macros ------------------------------------------ */ + +#define ROBUST_CHANNEL_CONTAINED_ERROR_STR "Contained" +#define ROBUST_CHANNEL_UNCONTAINED_ERROR_STR "Uncontained" +#define NO_XID NV_U32_MAX +#define NO_NV2080_NOTIFIER NV2080_NOTIFIERS_MAXCOUNT +#define NV_ERR_CONT_LOCATION_STRING_SIZE_MAX 64 + +/*! + * Error Containment error types string + */ +#define NV_ERROR_CONT_ERR_ID_STRING_PUBLIC {"FB DED", \ + "DED CBC", \ + "LTC Data", \ + "LTC GPC", \ + "LTC TAG", \ + "LTC CBC", \ + "FBHUB", \ + "SM", \ + "CE User Channel", \ + "CE Kernel Channel", \ + "MMU", \ + "GCC", \ + "CTXSW", \ + "PCIE"}; + +/*! + * Error Containment state table showing policy settings for each error id + * + * Where: + * RC_Recovery_Type: + * Type of RC recovery handling in response to a given error. Possible values: + * + * - NO_RC : No RC Recovery performed. Subsequent 2nd interrupt by engine + * consuming poison will determine the RC Recovery type. + * - RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE : RC Recovery compute channels of only the processes whose + * channels were loaded on halted TSG when _E10_SM_POISON or + * _E12A_CE_POISON_IN_USER_CHANNEL occurs. + * - RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION : RC Recovery compute channels of only specific MIG partition + * as that error can be attributed to a specific MIG partition. + * - RC_ALL_COMPUTE_CHANNELS : RC Recovery ALL compute channels on a GPU that saw this interrupt. + * (If MIG is enabled, then RC Recovery compute channels in all MIG partitions) + * - CE_TSG_RESET : Reset the halted CE Engine. Impacts the CE channels loaded on the TSG when the CE Halted. + * This is used in NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL & + * NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL along with additional + * Compute Channels RC policy (either RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE or + * RC_ALL_COMPUTE_CHANNELS). + */ +#define NV_ERROR_CONT_STATE_TABLE_SETTINGS \ +{ \ + /* errorCode , rcErrorCode , bGpuResetReqd, bGpuDrainAndResetReqd, bPrintSmcPartitionInfo, nv2080Notifier , Dynamic Page Blacklisting , RC_Recovery_Type */ \ + { NV_ERROR_CONT_ERR_ID_E01_FB_ECC_DED , {{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , Yes(PMA but not subheap) , NO_RC */ }, \ + {NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , Yes(PMA but not subheap) , NO_RC */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E02_FB_ECC_DED_IN_CBC_STORE , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , Yes(PMA but not subheap) , RC_ALL_COMPUTE_CHANNELS */ }, \ + {ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , Yes(PMA but not subheap) , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E05_LTC_ECC_DSTG , {{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , No , NO_RC */ }, \ + {NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , No , NO_RC */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E06_LTC_UNSUPPORTED_CLIENT_POISON, {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \ + {ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E07_LTC_ECC_TSTG , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \ + {ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E08_LTC_ECC_RSTG , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \ + {ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E09_FBHUB_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \ + {ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E10_SM_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \ + {ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE + CE_TSG_RESET */ }, \ + {ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE + CE_TSG_RESET */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS + CE_TSG_RESET */ }, \ + {ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS + CE_TSG_RESET */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E13_MMU_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , NO_RC */ }, \ + {ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , NO_RC */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E16_GCC_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \ + {ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E17_CTXSW_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \ + {ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \ + { NV_ERROR_CONT_ERR_ID_E20_XALEP_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \ + {ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}} \ +} + +/* ------------------------ Function Prototypes ----------------------------- */ + +#endif // _ERROR_CONT_H_ diff --git a/src/nvidia/kernel/inc/objrpc.h b/src/nvidia/kernel/inc/objrpc.h index a5c62a3050..95c11c300e 100644 --- a/src/nvidia/kernel/inc/objrpc.h +++ b/src/nvidia/kernel/inc/objrpc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -37,10 +37,14 @@ #include "ctrl/ctrl0080/ctrl0080fb.h" // rmcontrol params (from hal) #include "ctrl/ctrl0080/ctrl0080dma.h" // rmcontrol params (from hal) #include "gpu/gsp/message_queue.h" +#include "libraries/utils/nvbitvector.h" + +#include "objrpcstructurecopy.h" typedef struct GSP_FIRMWARE GSP_FIRMWARE; typedef struct _object_vgpu OBJVGPU, *POBJVGPU; +TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR); #include "g_rpc_hal.h" // For RPC_HAL_IFACES #include "g_rpc_odb.h" // For RPC_HAL_IFACES @@ -53,7 +57,9 @@ typedef struct _object_vgpu OBJVGPU, *POBJVGPU; typedef struct RpcHistoryEntry { NvU32 function; - NvU32 data[3]; + NvU64 data[2]; + NvU64 ts_start; + NvU64 ts_end; } RpcHistoryEntry; struct OBJRPC{ @@ -68,6 +74,7 @@ struct OBJRPC{ NvU32 *message_buffer_priv; MEMORY_DESCRIPTOR *pMemDesc_mesg; NvU32 maxRpcSize; + NvU32 largeRpcSize; // UVM Message buffer fields NvU32 *message_buffer_uvm; @@ -79,9 +86,12 @@ struct OBJRPC{ RpcHistoryEntry rpcHistory[RPC_HISTORY_DEPTH]; NvU32 rpcHistoryCurrent; + RpcHistoryEntry rpcEventHistory[RPC_HISTORY_DEPTH]; + NvU32 rpcEventHistoryCurrent; NvU32 timeoutCount; NvBool bQuietPrints; + OBJRPCSTRUCTURECOPY rpcStructureCopy; }; // @@ -94,25 +104,35 @@ struct OBJRPC{ #define vgpu_rpc_message_header_v ((rpc_message_header_v*)(pRpc->message_buffer)) #define rpc_message (vgpu_rpc_message_header_v->rpc_message_data) +static inline void _objrpcStructureCopyAssignIpVersion(struct OBJRPCSTRUCTURECOPY* pRpcStructureCopy, NvU32 ipVersion) +{ + pRpcStructureCopy->__nvoc_pbase_Object->ipVersion = ipVersion; +} + static inline void _objrpcAssignIpVersion(struct OBJRPC* pRpc, NvU32 ipVersion) { pRpc->__nvoc_pbase_Object->ipVersion = ipVersion; } -// Initialize and free RPC infrastructure -NV_STATUS initRpcInfrastructure_VGPU(OBJGPU *pGpu); -NV_STATUS freeRpcInfrastructure_VGPU(OBJGPU *pGpu); OBJRPC *initRpcObject(OBJGPU *pGpu); void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion); void rpcObjIfacesSetup(OBJRPC *pRpc); NV_STATUS rpcWriteCommonHeader(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 func, NvU32 paramLength); NV_STATUS rpcWriteCommonHeaderSim(OBJGPU *pGpu); -NV_STATUS _allocRpcMemDesc(OBJGPU *pGpu, NvU64 size, NvBool bContig, NV_ADDRESS_SPACE addrSpace, MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv); -void _freeRpcMemDesc(OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv); NV_STATUS vgpuGspSetupBuffers(OBJGPU *pGpu); void vgpuGspTeardownBuffers(OBJGPU *pGpu); NV_STATUS vgpuReinitializeRpcInfraOnStateLoad(OBJGPU *pGpu); +// Initialize and free RPC infrastructure +NV_STATUS initRpcInfrastructure_VGPU(OBJGPU *pGpu); +NV_STATUS freeRpcInfrastructure_VGPU(OBJGPU *pGpu); + +NV_STATUS _allocRpcMemDesc(OBJGPU *pGpu, NvU64 size, NvBool bContig, NV_ADDRESS_SPACE addrSpace, NvU32 memFlags, + MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv); +void _freeRpcMemDesc(OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv); + +NV_STATUS rpcDmaControl_wrapper(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize); // // OBJGPU RPC member accessors. // Historically, they have been defined inline by the following macros. diff --git a/src/nvidia/kernel/inc/objrpcstructurecopy.h b/src/nvidia/kernel/inc/objrpcstructurecopy.h new file mode 100644 index 0000000000..d68a304b9b --- /dev/null +++ b/src/nvidia/kernel/inc/objrpcstructurecopy.h @@ -0,0 +1,42 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _OBJRPCSTRUCTURECOPY_H_ +#define _OBJRPCSTRUCTURECOPY_H_ + +#include "vgpu/sdk-structures.h" +#include "ctrl/ctrl0080/ctrl0080bsp.h" // rmcontrol params (from hal) +#include "ctrl/ctrl2080/ctrl2080gr.h" // rmcontrol params (from hal) +#include "ctrl/ctrl2080/ctrl2080clk.h" // rmcontrol params (from hal) +#include "g_rpcstructurecopy_hal.h" // For RPCSTRUCTURECOPY_HAL_IFACES +#include "g_rpcstructurecopy_odb.h" // For RPCSTRUCTURECOPY_HAL_IFACES + +struct OBJRPCSTRUCTURECOPY{ + OBJECT_BASE_DEFINITION(RPCSTRUCTURECOPY); + + struct { + NvU32 ipVersion; + }__nvoc_pbase_Object[1]; // This nested structure mechanism is to bypass NVOC +}; + +#endif //_OBJRPCSTRUCTURECOPY_H_ diff --git a/src/nvidia/kernel/inc/vgpu/dev_vgpu.h b/src/nvidia/kernel/inc/vgpu/dev_vgpu.h new file mode 100644 index 0000000000..27c95995bb --- /dev/null +++ b/src/nvidia/kernel/inc/vgpu/dev_vgpu.h @@ -0,0 +1,324 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __vgpu_dev_nv_vgpu_h__ +#define __vgpu_dev_nv_vgpu_h__ + +#include "nvtypes.h" +#include "nvmisc.h" + +#include "nvctassert.h" + +/******************************************************************************/ +/* EMULATED REGISTERS - START */ +/******************************************************************************/ + +#define NV_VGPU_GUEST_OS_TYPE_ARCH 2:0 /* -W-4F */ +#define NV_VGPU_GUEST_OS_TYPE_ARCH_UNKNOWN 0 /* -W--V */ +#define NV_VGPU_GUEST_OS_TYPE_ARCH_AARCH64 1 /* -W--V */ +#define NV_VGPU_GUEST_OS_TYPE_ARCH_X86_64 2 /* -W--V */ +#define NV_VGPU_GUEST_OS_TYPE_ARCH_INVALID 3 /* -W--V */ +#define NV_VGPU_GUEST_OS_TYPE_OS 7:3 /* -W-4F */ +#define NV_VGPU_GUEST_OS_TYPE_OS_UNKNOWN 0 /* -W--V */ +#define NV_VGPU_GUEST_OS_TYPE_OS_LINUX 1 /* -W--V */ +#define NV_VGPU_GUEST_OS_TYPE_OS_WINDOWS7 2 /* -W--V */ +#define NV_VGPU_GUEST_OS_TYPE_OS_WINDOWS10 3 /* -W--V */ +#define NV_VGPU_GUEST_OS_TYPE_OS_INVALID 4 /* -W--V */ +// All remaining values for NV_VGPU_GUEST_OS_TYPE_OS are reserved/not supported. +#define NV_VGPU_GUEST_OS_TYPE_PAGE_SIZE 15:8 /* -W-4F */ + +#define NV_VGPU_SHARED_MEMORY__SIZE_1 4 /* */ +#define NV_VGPU_SHARED_MEMORY_TARGET 1:0 /* RWIVF */ +#define NV_VGPU_SHARED_MEMORY_TARGET_PHYS_NVM 0x00000001 /* RW--V */ +#define NV_VGPU_SHARED_MEMORY_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */ +#define NV_VGPU_SHARED_MEMORY_STATUS 3:3 /* RWIVF */ +#define NV_VGPU_SHARED_MEMORY_STATUS_INVALID 0x00000000 /* RW--V */ +#define NV_VGPU_SHARED_MEMORY_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_VGPU_SHARED_MEMORY_SIZE 5:4 /* RWIVF */ +#define NV_VGPU_SHARED_MEMORY_SIZE_4KB 0x00000000 /* RW--V */ +#define NV_VGPU_SHARED_MEMORY_ADDR_LO 31:12 /* RWIVF */ + +#define NV_VGPU_SHARED_MEMORY_HI_ADDR 19:0 /* RWIVF */ + +/******************************************************************************/ +/* EMULATED REGISTERS - END */ +/******************************************************************************/ + +/******************************************************************************/ +/* SHARED MEMORY - START */ +/******************************************************************************/ + +/* vGPU Current Pstate */ +#define NV_VGPU_SHARED_MEMORY_POINTER_CURRENT_PSTATE 0x00000090 +#define NV_VGPU_SHARED_MEMORY_POINTER_CURRENT_PSTATE_VALUE 31:0 + +/* vGPU ECC errors */ +#define NV_VGPU_SHARED_MEMORY_POINTER_ECC_TYPE 0x00000094 +#define NV_VGPU_SHARED_MEMORY_POINTER_ECC_TYPE_VALUE 31:0 +#define NV_VGPU_SHARED_MEMORY_POINTER_ECC_UNIT 0x00000098 +#define NV_VGPU_SHARED_MEMORY_POINTER_ECC_UNIT_VALUE 31:0 +#define NV_VGPU_SHARED_MEMORY_POINTER_ECC_ERROR_COUNT 0x0000009c +#define NV_VGPU_SHARED_MEMORY_POINTER_ECC_ERROR_COUNT_VALUE 31:0 + +/* vGPU backdoor VNC state */ +#define NV_VGPU_SHARED_MEMORY_POINTER_VNC 0x000000a0 +#define NV_VGPU_SHARED_MEMORY_POINTER_VNC_STATE 31:0 +#define NV_VGPU_SHARED_MEMORY_POINTER_VNC_STATE_ENABLED 0x00000001 +#define NV_VGPU_SHARED_MEMORY_POINTER_VNC_STATE_DISABLED 0x00000000 + +/* vGPU backdoor VNC support */ +#define NV_VGPU_SHARED_MEMORY_POINTER_VNC_SUPPORT 0x000000a4 +#define NV_VGPU_SHARED_MEMORY_POINTER_VNC_SUPPORT_VALUE 31:0 +#define NV_VGPU_SHARED_MEMORY_POINTER_VNC_SUPPORT_ENABLED 0x0001 +#define NV_VGPU_SHARED_MEMORY_POINTER_VNC_SUPPORT_DISABLED 0x0000 + +/* ecc fatal poison error*/ +#define NV_VGPU_SHARED_MEMORY_POINTER_ECC_POISON_ERROR 0x000000a8 +#define NV_VGPU_SHARED_MEMORY_POINTER_ECC_POISON_ERROR_VALUE 31:0 + +/* NvEnc Stats Reporting State */ +#define NV_VGPU_SHARED_MEMORY_POINTER_NVENC_STATS_REPORTING_STATE 0x000000ac +#define NV_VGPU_SHARED_MEMORY_POINTER_NVENC_STATS_REPORTING_STATE_VALUE 31:0 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVENC_STATS_REPORTING_STATE_DISABLED 0x00000000 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVENC_STATS_REPORTING_STATE_ENABLED 0x00000001 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED 0x00000002 + +/* Nvlink inband message response available*/ +#define NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE 0x000000b0 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE_NONE 0x00000000 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE_PROBE 0:0 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE_PROBE_CLEAR 0x00000000 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE_PROBE_PENDING 0x00000001 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE_MC_SETUP 1:1 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE_MC_SETUP_CLEAR 0x00000000 +#define NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE_MC_SETUP_PENDING 0x00000001 + +/******************************************************************************/ +/* SHARED MEMORY - END */ +/******************************************************************************/ + +/******************************************************************************/ +/* EVENT MEMORY - START */ +/******************************************************************************/ + +/* Event ring entry (9 words) */ +#define NV_VGPU_EV__SIZE_1 0x0000000a /* */ +#define NV_VGPU_EV_HCLIENT 0x00000000 /* RW-4R */ +#define NV_VGPU_EV_HOBJECT 0x00000004 /* RW-4R */ +#define NV_VGPU_EV_NOTIFY_INDEX 0x00000008 /* RW-4R */ +#define NV_VGPU_EV_FLAGS 0x0000000c /* RW-4R */ +#define NV_VGPU_EV_FLAGS_ALLOCATED 3:0 /* RW-4R */ +#define NV_VGPU_EV_FLAGS_ALLOCATED_GUEST 0x00000000 /* RW--V */ +#define NV_VGPU_EV_FLAGS_ALLOCATED_PLUGIN 0x00000001 /* RW--V */ +#define NV_VGPU_EV_FLAGS_HAS_NOTIFIER_DATA 4:4 /* RW-4R */ +#define NV_VGPU_EV_FLAGS_HAS_NOTIFIER_DATA_FALSE 0x00000000 /* RW--V */ +#define NV_VGPU_EV_FLAGS_HAS_NOTIFIER_DATA_TRUE 0x00000001 /* RW--V */ +#define NV_VGPU_EV_FLAGS_TYPE 31:16 /* RW-4R */ +#define NV_VGPU_EV_FLAGS_TYPE_ROBUST_CHANNEL_ERROR 0x00000000 /* RW--V */ +#define NV_VGPU_EV_FLAGS_TYPE_EVENT_INTR_MTHD 0x00000001 /* RW--V */ +#define NV_VGPU_EV_FLAGS_TYPE_VBLANK_INTR 0x00000002 /* RW--V */ +#define NV_VGPU_EV_FLAGS_TYPE_VNC 0x00000003 /* RW--V */ +#define NV_VGPU_EV_FLAGS_TYPE_PSTATE 0x00000004 /* RW--V */ +#define NV_VGPU_EV_FLAGS_TYPE_ECC 0x00000005 /* RW--V */ +#define NV_VGPU_EV_FLAGS_TYPE_NVENC_REPORTING_STATE 0x00000006 /* RW--V */ +#define NV_VGPU_EV_FLAGS_TYPE_INBAND_RESPONSE 0x00000007 /* RW--V */ +#define NV_VGPU_EV_NOTIFIER_TIMESTAMP 0x00000010 /* RW-4R */ +#define NV_VGPU_EV_NOTIFIER_TIMESTAMP_HI 0x00000014 /* RW-4R */ +#define NV_VGPU_EV_NOTIFIER_INFO32 0x00000018 /* RW-4R */ +#define NV_VGPU_EV_NOTIFIER_INFO16 0x0000001c /* RW-4R */ +#define NV_VGPU_EV_NOTIFIER_INFO16_VALUE 15:0 /* RW-4R */ +#define NV_VGPU_EV_NOTIFIER_STATUS 0x00000020 /* RW-4R */ +#define NV_VGPU_EV_ROBUST_CHANNEL_ERROR_CHID 0x00000024 /* RW-4R */ + +typedef struct { + volatile NvU32 hClient; + volatile NvU32 hObject; + volatile NvU32 notifyIndex; + volatile NvU32 flags; + volatile NvU32 timestampLo; + volatile NvU32 timestampHi; + volatile NvU32 info32; + volatile NvU32 info16; + volatile NvU32 status; + volatile NvU32 rcChid; +} VGPU_EVENT_BUF_ENTRY; + +#define VGPU_EVENT_BUF_ENTRY_SIZE (sizeof(VGPU_EVENT_BUF_ENTRY)) +#define VGPU_EVENT_BUF_ENTRY_COUNT (RM_PAGE_SIZE / VGPU_EVENT_BUF_ENTRY_SIZE) + +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, hClient ) == NV_VGPU_EV_HCLIENT); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, hObject ) == NV_VGPU_EV_HOBJECT); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, notifyIndex) == NV_VGPU_EV_NOTIFY_INDEX); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, flags ) == NV_VGPU_EV_FLAGS); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, timestampLo) == NV_VGPU_EV_NOTIFIER_TIMESTAMP); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, timestampHi) == NV_VGPU_EV_NOTIFIER_TIMESTAMP_HI); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, info32 ) == NV_VGPU_EV_NOTIFIER_INFO32); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, info16 ) == NV_VGPU_EV_NOTIFIER_INFO16); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, status ) == NV_VGPU_EV_NOTIFIER_STATUS); +ct_assert(NV_OFFSETOF(VGPU_EVENT_BUF_ENTRY, rcChid ) == NV_VGPU_EV_ROBUST_CHANNEL_ERROR_CHID); +ct_assert(VGPU_EVENT_BUF_ENTRY_SIZE == (NV_VGPU_EV__SIZE_1 * sizeof (NvU32))); + +/******************************************************************************/ +/* EVENT MEMORY - END */ +/******************************************************************************/ + +/* virtual GPU */ +#ifndef NV_XVE_ID_DEVICE_CHIP_VGPU +#define NV_XVE_ID_DEVICE_CHIP_VGPU 0x00000f00 /* R---V */ +#endif + +/******************************************************************************/ +/* GSP Control buffer shared between Guest RM and GSP Plugin - START */ +/******************************************************************************/ +/******************************************************************************/ +/* GSP Control buffer format - Version 1 - START */ +/******************************************************************************/ + +#define VGPU_GSP_BUF_ADDR_V1_VALIDITY 0:0 +#define VGPU_GSP_BUF_ADDR_V1_VALIDITY_INVALID 0x00000000 +#define VGPU_GSP_BUF_ADDR_V1_VALIDITY_VALID 0x00000001 +#define VGPU_GSP_BUF_ADDR_V1_APERTURE 2:1 +#define VGPU_GSP_BUF_ADDR_V1_APERTURE_INVALID 0x00000000 +#define VGPU_GSP_BUF_ADDR_V1_APERTURE_SYSMEM 0x00000001 +#define VGPU_GSP_BUF_ADDR_V1_APERTURE_FBMEM 0x00000002 +#define VGPU_GSP_BUF_ADDR_V2_SIZE 4:3 +#define VGPU_GSP_BUF_ADDR_V2_SIZE_4K 0x00000000 +#define VGPU_GSP_BUF_ADDR_V2_SIZE_128K 0x00000001 +#define VGPU_GSP_BUF_ADDR_V1_PFN 63:12 + +#define VGPU_GSP_CTRL_BUF_V1_VERSION 1 +#define VGPU_GSP_CTRL_BUF_V2_VERSION 2 + +/****** Control buffer: written by guest RM and read by GSP vGPU plugin *******/ + +#define VGPU_GSP_CTRL_BUF_SIZE_V1 4096 + +typedef struct { + NvU64 addr; + NvU64 bar2Offset; +} VGPU_GSP_BUF_INFO; + +typedef union { + struct { + volatile NvU32 version; // Version of control buffer format + volatile NvU32 requestId; // Request sequence number + volatile VGPU_GSP_BUF_INFO responseBuf; // Response buffer address + volatile VGPU_GSP_BUF_INFO msgBuf; // RPC message buffer address + volatile VGPU_GSP_BUF_INFO sharedMem; // Shared memory buffer + volatile VGPU_GSP_BUF_INFO eventBuf; // Event buffer address + volatile NvU32 getEventBuf; // GET index in circular event buffe + volatile NvU32 guestEccStatus; // guest ecc status + volatile NvU64 sysmemBitMapTablePfn; // Root node's pfn value of dirty sysmem tracking table + volatile NvU32 guestOsType; // Guest OS type + } ; + volatile NvU8 buf[VGPU_GSP_CTRL_BUF_SIZE_V1]; +} VGPU_GSP_CTRL_BUF_V1; + +// check size +ct_assert(sizeof(VGPU_GSP_CTRL_BUF_V1) == VGPU_GSP_CTRL_BUF_SIZE_V1); + +// check field offset +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, version ) == 0x000); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, requestId ) == 0x004); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, responseBuf ) == 0x008); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, msgBuf ) == 0x018); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, sharedMem ) == 0x028); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, eventBuf ) == 0x038); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, getEventBuf ) == 0x048); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, guestEccStatus ) == 0x04C); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, sysmemBitMapTablePfn ) == 0x050); +ct_assert(NV_OFFSETOF(VGPU_GSP_CTRL_BUF_V1, guestOsType ) == 0x058); + +/****** Response buffer: written by GSP vGPU plugin and read by guest RM ******/ + +#define VGPU_GSP_RESPONSE_BUF_SIZE_V1 4096 + +typedef union { + struct { + volatile NvU32 responseId; // Response sequence number + volatile NvU32 putEventBuf; // PUT index in circular event buffer + volatile NvU32 hostEccStatus; // host ecc status + volatile NvU32 usmType; // Host USM Type + }; + volatile NvU8 buf[VGPU_GSP_RESPONSE_BUF_SIZE_V1]; +} VGPU_GSP_RESPONSE_BUF_V1; + +// check size +ct_assert(sizeof(VGPU_GSP_RESPONSE_BUF_V1) == VGPU_GSP_RESPONSE_BUF_SIZE_V1); + +// check field offset +ct_assert(NV_OFFSETOF(VGPU_GSP_RESPONSE_BUF_V1, responseId ) == 0x000); +ct_assert(NV_OFFSETOF(VGPU_GSP_RESPONSE_BUF_V1, putEventBuf ) == 0x004); +ct_assert(NV_OFFSETOF(VGPU_GSP_RESPONSE_BUF_V1, hostEccStatus ) == 0x008); +ct_assert(NV_OFFSETOF(VGPU_GSP_RESPONSE_BUF_V1, usmType ) == 0x00C); + +/******************************************************************************/ +/* GSP Control buffer format - Version 1 - END */ +/******************************************************************************/ + +// Control buffer format for Guest RM +typedef union { + volatile VGPU_GSP_CTRL_BUF_V1 v1; +} VGPU_GSP_CTRL_BUF_RM; + +// Control buffer format for GSP vGPU Plugin +typedef union { + volatile const VGPU_GSP_CTRL_BUF_V1 v1; +} VGPU_GSP_CTRL_BUF_PLUGIN; + +// Response buffer format for Guest RM +typedef union { + volatile const VGPU_GSP_RESPONSE_BUF_V1 v1; +} VGPU_GSP_RESPONSE_BUF_RM; + +// Response buffer format for GSP vGPU Plugin +typedef union { + volatile VGPU_GSP_RESPONSE_BUF_V1 v1; +} VGPU_GSP_RESPONSE_BUF_PLUGIN; + +/******************************************************************************/ +/* GSP Control buffer shared between Guest RM and GSP Plugin - END */ +/******************************************************************************/ + +// VGPU GSP dirty sysmem tracking pfn format +#define VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_VALIDITY 0:0 +#define VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_VALIDITY_INVALID 0x00000000 +#define VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_VALIDITY_VALID 0x00000001 +#define VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_APERTURE 2:1 +#define VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_APERTURE_INVALID 0x00000000 +#define VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_APERTURE_SYSMEM 0x00000001 +#define VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_APERTURE_FBMEM 0x00000002 +#define VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_PFN 63:12 + +#define MAX_PFNS_PER_4K_PAGE 512 + +// VGPU GSP dirty sysmem tracking root node format +typedef struct { + NvU16 nodeCount; // count of allocated bitmap nodes + NvU16 padding1; + NvU32 padding2; + NvU64 nodePfns[MAX_PFNS_PER_4K_PAGE - 1]; +} VGPU_GSP_SYSMEM_BITMAP_ROOT_NODE; + +ct_assert(sizeof(VGPU_GSP_SYSMEM_BITMAP_ROOT_NODE) == 0x1000); +#endif // __vgpu_dev_nv_vgpu_h__ diff --git a/src/nvidia/kernel/inc/vgpu/rm_plugin_shared_code.h b/src/nvidia/kernel/inc/vgpu/rm_plugin_shared_code.h new file mode 100644 index 0000000000..fac83704ab --- /dev/null +++ b/src/nvidia/kernel/inc/vgpu/rm_plugin_shared_code.h @@ -0,0 +1,6738 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * IMPORTANT NOTE: + * This file contains C functions shared between resman and plugin. + * Make sure that this file is included only once in resman and only once in plugin code. + * Else, make sure that all the functions in this file are static functions. + */ + +/* + * The structures and functions are used in below sequence: + * + * Some call is made from guest RM to the RPC framework in RM. + * Step 1. Guest RM : copies the parameters from guest SDK structures to RPC structures (serialization) + * Step 2. Plugin : copies the parameters from RPC structures to host SDK structures (de-serialization) + * (Host RM side operations, like RM control, alloc, free etc.) + * Step 3. Plugin : copies the parameters from host SDK structures to RPC structures (serialization) + * Step 4. Guest RM : copies the parameters from RPC structures to guest SDK structures (de-serialization) + * The data is returned to the caller. + */ + +/* + * Copy DMA Control Parameters structure element by element. + * Depending upon the cmd, copy parameters from pParams to params_in + */ + +#include "ctrl/ctrl208f/ctrl208fdma.h" // NV208F_CTRL_DMA_GET_VAS_BLOCK_DETAILS_PARAMS +#include "ctrl/ctrla16f.h" // NVA16F_CTRL_GET_CLASS_ENGINEID +#include "ctrl/ctrl90e6.h" // NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK +#include "ctrl/ctrl90f1.h" +#include "ctrl/ctrl90cd.h" +#include "ctrl/ctrl0080.h" +#include "nvctassert.h" + +// Copy elements from RPC structures to SDK structures (Step 2 or step 4 listed above) +#ifdef VMIOP_BUILD +typedef vmiop_error_t return_t; +#define serialize_deserialize(u) serialize_##u##_HAL +#define getIpVersion() pObjRpcStructureCopy->ipVersion +#define SUCCESS_T vmiop_success +#define FAILURE_T vmiop_error_inval +#define COPY_INPUT_PARAMETERS +#if VMIOPLUGINCFG_FEATURE_ENABLED(PLATFORM_LDDM) +#define UMED_BUILD +#endif +#endif + +#ifdef RESMAN_BUILD +typedef NV_STATUS return_t; +#define serialize_deserialize(u) deserialize_##u##_HAL +#define getIpVersion() pObjRpcStructureCopy->__nvoc_pbase_Object->ipVersion +#define SUCCESS_T NV_OK +#define FAILURE_T NV_ERR_INVALID_ARGUMENT +#define COPY_OUTPUT_PARAMETERS +#endif + +#ifdef GSP_FW_BUILD +typedef NV_STATUS return_t; +#define SUCCESS_T NV_OK +#define FAILURE_T NV_ERR_INVALID_ARGUMENT +#define COPY_INPUT_PARAMETERS +#define vmiop_assert NV_ASSERT +#endif + +#define NV_ADDR_UNKNOWN 0 // Address space is unknown +#define NV_ADDR_SYSMEM 1 // System memory (PCI) +#define NV_ADDR_FBMEM 2 // Frame buffer memory space +#define NV_ADDR_REGMEM 3 // NV register memory space +#define NV_ADDR_VIRTUAL 4 // Virtual address space only +#define NV_ADDR_FABRIC 5 // Multi-node fabric address space + +#define NV2080_NOTIFIERS_MAXCOUNT_R525 178 +#define NV2080_NOTIFIERS_MAXCOUNT_R470 162 + +#define NV_CHECK_AND_ALIGN_OFFSET(offset, bAlign) { \ + if (bAlign) { \ + offset = NV_ALIGN_UP(offset, sizeof(NvU64)); \ + } \ + } + +#ifndef GSP_FW_BUILD +#ifdef BUILD_COMMON_RPCS + +static +return_t deserialize_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01(NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 *src = (void*)(buffer); + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *dest = pParams; + + if (dest && src) { + dest->hResolution = src->hResolution; + dest->vResolution = src->vResolution; + dest->averageEncodeLatency = src->averageEncodeLatency; + dest->averageEncodeFps = src->averageEncodeFps; + dest->timestampBufferSize = 0; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01(NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 *src = (void*)(buffer); + NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef VMIOP_BUILD + dest->engineID = deserialize_engineType(src->engineID); +#else + dest->engineID = src->engineID; +#endif + dest->subdeviceInstance = src->subdeviceInstance; + dest->resetReason = src->resetReason; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00(NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 *src = (void*)(buffer); + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *dest = pParams; + + if (src && dest) { + dest->exceptType = src->exceptType; +#ifdef VMIOP_BUILD + dest->engineID = deserialize_engineType(src->engineID); +#else + dest->engineID = src->engineID; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09(NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 *src = (void*)(buffer); + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *dest = pParams; + + if (src && dest) { + dest->faultType = src->faultType; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00(NV2080_CTRL_PERF_BOOST_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 *src = (void*)(buffer); + NV2080_CTRL_PERF_BOOST_PARAMS *dest = pParams; + + if (src && dest) { + dest->flags = src->flags; + dest->duration = src->duration; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 *src = (void*)(buffer); + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *dest = pParams; + + if (src && dest) { + NvU32 i; + for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { + dest->value.colorFB[i] = src->value.colorFB[i]; + dest->value.colorDS[i] = src->value.colorDS[i]; + } + dest->value.depth = src->value.depth; + dest->value.stencil = src->value.stencil; // Changed in v04_00 + dest->indexSize = src->indexSize; + dest->indexUsed = src->indexUsed; + dest->format = src->format; + dest->valType = src->valType; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 *src = (void*)(buffer); + NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *dest = pParams; + + if (src && dest) { + NvU32 i; + for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { + dest->colorFB[i] = src->colorFB[i]; + dest->colorDS[i] = src->colorDS[i]; + } + dest->format = src->format; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 *src = (void*)(buffer); + NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *dest = pParams; + + if (src && dest) { + dest->depth = src->depth; + dest->format = src->format; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 *src = (void*)(buffer); + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *dest = pParams; + + if (src && dest) { + dest->bEnable = src->bEnable; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00(NVA06C_CTRL_TIMESLICE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 *src = (void*)(buffer); + NVA06C_CTRL_TIMESLICE_PARAMS *dest = pParams; + + if (src && dest) { + dest->timesliceUs = src->timesliceUs; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 *src = (void*)(buffer); + NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *dest = pParams; + NvU32 i; + + if (src && dest) { + if (src->numChannels > NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES) { + return FAILURE_T; + } + + dest->bDisable = src->bDisable; + dest->numChannels = src->numChannels; + dest->bOnlyDisableScheduling = src->bOnlyDisableScheduling; + dest->bRewindGpPut = src->bRewindGpPut; + dest->pRunlistPreemptEvent = NULL; // vGPU do not support guest kernel handles + + for (i = 0; i < src->numChannels ; i++) + { + dest->hClientList[i] = src->hClientList[i]; + dest->hChannelList[i] = src->hChannelList[i]; + } + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A(NVA06C_CTRL_PREEMPT_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA06C_CTRL_PREEMPT_PARAMS_v09_0A *src = (void*)(buffer); + NVA06C_CTRL_PREEMPT_PARAMS *dest = pParams; + + if (src && dest) { + dest->bWait = src->bWait; + dest->bManualTimeout = src->bManualTimeout; + dest->timeoutUs = src->timeoutUs; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *src = (void*)(buffer); + NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *dest = pParams; + + if (src && dest) { + dest->tsgInterleaveLevel = src->tsgInterleaveLevel; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *src = (void*)(buffer); + NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *dest = pParams; + + if (src && dest) { + dest->channelInterleaveLevel = src->channelInterleaveLevel; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 *src = (void*)(buffer); + NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *dest = pParams; + + if (src && dest) { + NvU32 i; + + dest->flags = src->flags; + dest->hClient = src->hClient; + dest->hChannel = src->hChannel; + for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END; ++i) + dest->vMemPtrs[i] = src->vMemPtrs[i]; + dest->gfxpPreemptMode = src->gfxpPreemptMode; + dest->cilpPreemptMode = src->cilpPreemptMode; + dest->grRouteInfo.flags = src->grRouteInfo.flags; + dest->grRouteInfo.route = src->grRouteInfo.route; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01(NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 *src = (void*)(buffer); + NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *dest = pParams; + + if (src && dest) { + dest->flags = src->flags; + dest->hChannel = src->hChannel; + dest->gfxpPreemptMode = src->gfxpPreemptMode; + dest->cilpPreemptMode = src->cilpPreemptMode; + dest->grRouteInfo.flags = src->grRouteInfo.flags; + dest->grRouteInfo.route = src->grRouteInfo.route; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 *src = (void*)(buffer); + NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *dest = pParams; + + if (src && dest) { + dest->hClient = src->hClient; + dest->hChannel = src->hChannel; + dest->vMemPtr = src->vMemPtr; + dest->zcullMode = src->zcullMode; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 *src = (void*)(buffer); + NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef VMIOP_BUILD + dest->engineType = deserialize_engineType(src->engineType); +#else + dest->engineType = src->engineType; +#endif + dest->hClient = src->hClient; + dest->ChID = src->ChID; + dest->hChanClient = src->hChanClient; + dest->hObject = src->hObject; + dest->hVirtMemory = src->hVirtMemory; + dest->physAddress = src->physAddress; + dest->physAttr = src->physAttr; + dest->hDmaHandle = src->hDmaHandle; + dest->index = src->index; + dest->size = src->size; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 *src = (void*)(buffer); + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *dest = pParams; + + if (src && dest) { + NvU32 i; + + if (src->numLevelsToCopy > GMMU_FMT_MAX_LEVELS_v1A_12) { + return FAILURE_T; + } + + dest->hSubDevice = src->hSubDevice; + dest->subDeviceId = src->subDeviceId; + dest->pageSize = src->pageSize; + dest->virtAddrLo = src->virtAddrLo; + dest->virtAddrHi = src->virtAddrHi; + dest->numLevelsToCopy = src->numLevelsToCopy; + + for (i = 0; i < dest->numLevelsToCopy; i++) + { + dest->levels[i].physAddress = src->levels[i].physAddress; + dest->levels[i].aperture = src->levels[i].aperture; + dest->levels[i].size = src->levels[i].size; + dest->levels[i].pageShift = src->levels[i].pageShift; + } + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS +#endif + +#ifdef BUILD_COMMON_RPCS + +static +return_t deserialize_GET_BRAND_CAPS_v25_12(NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_OUTPUT_PARAMETERS + rpc_get_brand_caps_v25_12 *src = (void*)(buffer); + NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *dest = pParams; + + if (src && dest) { + dest->brands = src->brands; + } + else + return FAILURE_T; +#endif + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01(NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_OUTPUT_PARAMETERS + NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 *src = (void*)(buffer); + NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *dest = pParams; + + if (src && dest) { + dest->engines = src->engines; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00(NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *dest = pParams; + + if (src && dest) { + dest->hTargetChannel = src->hTargetChannel; + dest->numSMsToClear = src->numSMsToClear; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06(NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset, + NvU32 startingSMOffset) +{ + NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i, smIdDest; +#endif + + if (src->numSMsToRead > VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + dest->hTargetChannel = src->hTargetChannel; + dest->startingSM = src->startingSM; + dest->numSMsToRead = src->numSMsToRead; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + for (i = 0; i < src->numSMsToRead; ++i) + { + smIdDest = startingSMOffset + i; + dest->smErrorStateArray[smIdDest].hwwGlobalEsr = src->smErrorStateArray[i].hwwGlobalEsr; + dest->smErrorStateArray[smIdDest].hwwWarpEsr = src->smErrorStateArray[i].hwwWarpEsr; + dest->smErrorStateArray[smIdDest].hwwWarpEsrPc = src->smErrorStateArray[i].hwwWarpEsrPc; + dest->smErrorStateArray[smIdDest].hwwGlobalEsrReportMask = src->smErrorStateArray[i].hwwGlobalEsrReportMask; + dest->smErrorStateArray[smIdDest].hwwWarpEsrReportMask = src->smErrorStateArray[i].hwwWarpEsrReportMask; + dest->smErrorStateArray[smIdDest].hwwEsrAddr = src->smErrorStateArray[i].hwwEsrAddr; + dest->smErrorStateArray[smIdDest].hwwWarpEsrPc64 = src->smErrorStateArray[i].hwwWarpEsrPc64; + /* New fields added in version v21_06 */ + dest->smErrorStateArray[smIdDest].hwwCgaEsr = src->smErrorStateArray[i].hwwCgaEsr; + dest->smErrorStateArray[smIdDest].hwwCgaEsrReportMask = src->smErrorStateArray[i].hwwCgaEsrReportMask; + } + dest->mmuFault.valid = src->mmuFault.valid; + dest->mmuFault.faultInfo = src->mmuFault.faultInfo; + dest->mmuFaultInfo = src->mmuFault.faultInfo; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00(NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *dest = pParams; + + if (src && dest) { + dest->exceptionMask = src->exceptionMask; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 *src = (void*)(buffer); + NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *dest = pParams; + NvU32 i; + + if (src && dest) + { +#ifdef VMIOP_BUILD + dest->engineType = deserialize_engineType(src->engineType); +#else + dest->engineType = src->engineType; +#endif + dest->hClient = src->hClient; + dest->ChID = src->ChID; + dest->hChanClient = src->hChanClient; + dest->hObject = src->hObject; + dest->hVirtMemory = src->hVirtMemory; + dest->virtAddress = src->virtAddress; + dest->size = src->size; + dest->entryCount = src->entryCount; + + if (dest->entryCount > NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES) { + return FAILURE_T; + } + + for (i = 0; i < dest->entryCount; i++) { + dest->promoteEntry[i].gpuPhysAddr = src->promoteEntry[i].gpuPhysAddr; + dest->promoteEntry[i].gpuVirtAddr = src->promoteEntry[i].gpuVirtAddr; + dest->promoteEntry[i].size = src->promoteEntry[i].size; + dest->promoteEntry[i].physAttr = src->promoteEntry[i].physAttr; + dest->promoteEntry[i].bufferId = src->promoteEntry[i].bufferId; + dest->promoteEntry[i].bInitialize = src->promoteEntry[i].bInitialize; + dest->promoteEntry[i].bNonmapped = src->promoteEntry[i].bNonmapped; + } + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06(NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 *src = (void*)(buffer); + NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_OUTPUT_PARAMETERS + dest->waitForEvent = src->waitForEvent; + dest->hResidentChannel = src->hResidentChannel; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *dest = pParams; + + if (src && dest) { + NvU32 idx = 0; +#ifdef COPY_INPUT_PARAMETERS + if (src->regOpCount > NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS) { + return FAILURE_T; + } + + dest->bNonTransactional = src->bNonTransactional; + dest->regOpCount = src->regOpCount; + + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regOp = src->regOps[idx].regOp; + dest->regOps[idx].regType = src->regOps[idx].regType; + dest->regOps[idx].regQuad = src->regOps[idx].regQuad; + dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; + dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; + dest->regOps[idx].regOffset = src->regOps[idx].regOffset; + dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; + dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regStatus = src->regOps[idx].regStatus; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->action = src->action; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06(NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->hTargetChannel = src->hTargetChannel; + dest->smID = src->smID; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->smErrorState.hwwGlobalEsr = src->smErrorState.hwwGlobalEsr; + dest->smErrorState.hwwWarpEsr = src->smErrorState.hwwWarpEsr; + dest->smErrorState.hwwWarpEsrPc = src->smErrorState.hwwWarpEsrPc; + dest->smErrorState.hwwGlobalEsrReportMask = src->smErrorState.hwwGlobalEsrReportMask; + dest->smErrorState.hwwWarpEsrReportMask = src->smErrorState.hwwWarpEsrReportMask; + dest->smErrorState.hwwEsrAddr = src->smErrorState.hwwEsrAddr; + dest->smErrorState.hwwWarpEsrPc64 = src->smErrorState.hwwWarpEsrPc64; + /* New fields added in version v21_06 */ + dest->smErrorState.hwwCgaEsr = src->smErrorState.hwwCgaEsr; + dest->smErrorState.hwwCgaEsrReportMask = src->smErrorState.hwwCgaEsrReportMask; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->hTargetChannel = src->hTargetChannel; + dest->smID = src->smID; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->action = src->action; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->stopTriggerType = src->stopTriggerType; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00(NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 *src = (void*)(buffer); + NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *dest = pParams; + + if (src && dest) { + dest->hVASpace = src->hVASpace; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07(NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 *src = (void*)(buffer); + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->ceEngineType = src->ceEngineType; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->pceMask = src->pceMask; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 *src = (void*)(buffer); + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *dest = pParams; + + if (src && dest) { + ct_assert(NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE == 4); + +#ifdef COPY_INPUT_PARAMETERS + dest->index = src->index; + dest->tableType = src->tableType; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { + dest->value.colorFB[i] = src->value.colorFB[i]; + dest->value.colorDS[i] = src->value.colorDS[i]; + } + dest->value.depth = src->value.depth; + dest->value.stencil = src->value.stencil; + dest->format = src->format; + dest->index = src->index; + dest->bIndexValid = src->bIndexValid; + dest->tableType = src->tableType; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00(NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00 *src = (void*)(buffer); + NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + + for (i = 0; i < NV2080_CTRL_BUS_MAX_NUM_GPUS; i++) { + dest->nvlinkPeerIdMask[i] = src->nvlinkPeerIdMask[i]; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 *src = (void*)(buffer); + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + + dest->enabledLinkMask = src->enabledLinkMask; + + FOR_EACH_INDEX_IN_MASK(32, i, src->enabledLinkMask) + { + NV2080_CTRL_NVLINK_DEVICE_INFO *deviceInfo_d = NULL; + NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 *deviceInfo_s = NULL; + + if (i >= NV2080_CTRL_NVLINK_MAX_LINKS_v23_04) + break; + + dest->linkInfo[i].capsTbl = src->linkInfo[i].capsTbl; + dest->linkInfo[i].phyType = src->linkInfo[i].phyType; + dest->linkInfo[i].subLinkWidth = src->linkInfo[i].subLinkWidth; + dest->linkInfo[i].linkState = src->linkInfo[i].linkState; + dest->linkInfo[i].rxSublinkStatus = src->linkInfo[i].rxSublinkStatus; + dest->linkInfo[i].txSublinkStatus = src->linkInfo[i].txSublinkStatus; + dest->linkInfo[i].nvlinkVersion = src->linkInfo[i].nvlinkVersion; + dest->linkInfo[i].nciVersion = src->linkInfo[i].nciVersion; + dest->linkInfo[i].phyVersion = src->linkInfo[i].phyVersion; + dest->linkInfo[i].nvlinkLinkClockKHz = src->linkInfo[i].nvlinkLinkClockKHz; + dest->linkInfo[i].nvlinkLineRateMbps = src->linkInfo[i].nvlinkLineRateMbps; + dest->linkInfo[i].connected = src->linkInfo[i].connected; + dest->linkInfo[i].remoteDeviceLinkNumber = src->linkInfo[i].remoteDeviceLinkNumber; + dest->linkInfo[i].localDeviceLinkNumber = src->linkInfo[i].localDeviceLinkNumber; + + deviceInfo_d = &dest->linkInfo[i].remoteDeviceInfo; + deviceInfo_s = &src->linkInfo[i].remoteDeviceInfo; + + deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags; + deviceInfo_d->domain = deviceInfo_s->domain; + deviceInfo_d->bus = deviceInfo_s->bus; + deviceInfo_d->device = deviceInfo_s->device; + deviceInfo_d->function = deviceInfo_s->function; + deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId; + deviceInfo_d->deviceType = deviceInfo_s->deviceType; + portMemCopy(deviceInfo_d->deviceUUID, + sizeof(deviceInfo_d->deviceUUID), + deviceInfo_s->deviceUUID, + sizeof(deviceInfo_s->deviceUUID)); + + deviceInfo_d = &dest->linkInfo[i].localDeviceInfo; + deviceInfo_s = &src->linkInfo[i].localDeviceInfo; + + deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags; + deviceInfo_d->domain = deviceInfo_s->domain; + deviceInfo_d->bus = deviceInfo_s->bus; + deviceInfo_d->device = deviceInfo_s->device; + deviceInfo_d->function = deviceInfo_s->function; + deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId; + deviceInfo_d->deviceType = deviceInfo_s->deviceType; + portMemCopy(deviceInfo_d->deviceUUID, + sizeof(deviceInfo_d->deviceUUID), + deviceInfo_s->deviceUUID, + sizeof(deviceInfo_s->deviceUUID)); + } + FOR_EACH_INDEX_IN_MASK_END; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D *src = (void*)(buffer); + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + memcpy(dest->gpuIds, src->gpuIds, (sizeof(NvU32) * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)); + dest->gpuCount = src->gpuCount; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->p2pCaps = src->p2pCaps; + dest->p2pOptimalReadCEs = src->p2pOptimalReadCEs; + dest->p2pOptimalWriteCEs = src->p2pOptimalWriteCEs; + portMemCopy(dest->p2pCapsStatus, NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D, + src->p2pCapsStatus, NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D); +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A *src = (void*)(buffer); + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *dest = pParams; + + if (src && dest) { + if (src->grpACount == 0 || + src->grpACount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS || + src->grpBCount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + NvU32 idx = 0; + + dest->grpACount = src->grpACount; + dest->grpBCount = src->grpBCount; + + for (idx = 0; idx < NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS; idx++) { + dest->gpuIdGrpA[idx] = src->gpuIdGrpA[idx]; + dest->gpuIdGrpB[idx] = src->gpuIdGrpB[idx]; + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 grpAIdx = 0, grpBIdx= 0; + NvBool bReflexive = NV_FALSE; + + // Check for the reflexive case + if (src->grpBCount == 0) { + bReflexive = NV_TRUE; + } + + for (grpAIdx = 0; grpAIdx < src->grpACount; grpAIdx++) { + for (grpBIdx = 0; bReflexive ? grpBIdx <= grpAIdx : grpBIdx < src->grpBCount; grpBIdx++) { + dest->p2pCaps[grpAIdx][grpBIdx] = src->p2pCaps[grpAIdx].array[grpBIdx]; + dest->a2bOptimalReadCes[grpAIdx][grpBIdx] = src->a2bOptimalReadCes[grpAIdx].array[grpBIdx]; + dest->a2bOptimalWriteCes[grpAIdx][grpBIdx] = src->a2bOptimalWriteCes[grpAIdx].array[grpBIdx]; + dest->b2aOptimalReadCes[grpAIdx][grpBIdx] = src->b2aOptimalReadCes[grpAIdx].array[grpBIdx]; + dest->b2aOptimalWriteCes[grpAIdx][grpBIdx] = src->b2aOptimalWriteCes[grpAIdx].array[grpBIdx]; + } + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02(NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 *src = (void*)(buffer); + NV2080_CTRL_GET_P2P_CAPS_PARAMS *dest = pParams; + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + if (!src->bAllCaps && (src->peerGpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)) + return FAILURE_T; + + dest->bAllCaps = src->bAllCaps; + dest->bUseUuid = src->bUseUuid; + + if (!src->bAllCaps) + { + NvU32 i; + dest->peerGpuCount = src->peerGpuCount; + + for (i = 0; i < src->peerGpuCount; ++i) + { + portMemCopy(dest->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE_v21_02, + src->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE_v21_02); + } + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + + if (src->peerGpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS) + return FAILURE_T; + + if (src->bAllCaps) + { + dest->peerGpuCount = src->peerGpuCount; + } + + for (i = 0; i < src->peerGpuCount; ++i) + { + if (src->bAllCaps) + { + portMemCopy(dest->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE_v21_02, + src->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE_v21_02); + } + + dest->peerGpuCaps[i].p2pCaps = src->peerGpuCaps[i].p2pCaps; + dest->peerGpuCaps[i].p2pOptimalReadCEs = src->peerGpuCaps[i].p2pOptimalReadCEs; + dest->peerGpuCaps[i].p2pOptimalWriteCEs = src->peerGpuCaps[i].p2pOptimalWriteCEs; + portMemCopy(dest->peerGpuCaps[i].p2pCapsStatus, + sizeof(dest->peerGpuCaps[i].p2pCapsStatus), + src->peerGpuCaps[i].p2pCapsStatus, + sizeof(src->peerGpuCaps[i].p2pCapsStatus)); + dest->peerGpuCaps[i].busPeerId = src->peerGpuCaps[i].busPeerId; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F(NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F *src = (void*)(buffer); + NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *dest = pParams; + + if (src && dest) + { + dest->ctxsw = src->ctxsw; + } + else + return FAILURE_T; +#endif + + return SUCCESS_T; +} + +static +return_t deserialize_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F(NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F *src = (void*)(buffer); + NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *dest = pParams; + + if (src && dest) + { + dest->ctxsw = src->ctxsw; + } + else + return FAILURE_T; +#endif + + return SUCCESS_T; +} + +static +return_t deserialize_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F(NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F *src = (void*)(buffer); + NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *dest = pParams; + NvU32 idx = 0; + + if (src && dest) + { + if (src->regOpCount > NVB0CC_REGOPS_MAX_COUNT) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + dest->regOpCount = src->regOpCount; + dest->mode = src->mode; + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regOp = src->regOps[idx].regOp; + dest->regOps[idx].regType = src->regOps[idx].regType; + dest->regOps[idx].regQuad = src->regOps[idx].regQuad; + dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; + dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; + dest->regOps[idx].regOffset = src->regOps[idx].regOffset; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; + dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->bPassed = src->bPassed; + dest->bDirect = src->bDirect; + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regStatus = src->regOps[idx].regStatus; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 *src = (void*)(buffer); + NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->hMemPmaBuffer = src->hMemPmaBuffer; + dest->pmaBufferOffset = src->pmaBufferOffset; + dest->pmaBufferSize = src->pmaBufferSize; + dest->hMemPmaBytesAvailable = src->hMemPmaBytesAvailable; + dest->pmaBytesAvailableOffset = src->pmaBytesAvailableOffset; + dest->ctxsw = src->ctxsw; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->pmaBufferVA = src->pmaBufferVA; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 *src = (void*)(buffer); + NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->bytesConsumed = src->bytesConsumed; + dest->bUpdateAvailableBytes = src->bUpdateAvailableBytes; + dest->bWait = src->bWait; + dest->bReturnPut = src->bReturnPut; + dest->pmaChannelIdx = src->pmaChannelIdx; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->bytesAvailable = src->bytesAvailable; + dest->putPtr = src->putPtr; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 *src = (void*)(buffer); + NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *dest = pParams; + + if (src && dest) { + NvU32 idx = 0; +#ifdef COPY_INPUT_PARAMETERS + if (src->regOpCount > NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07) { + return FAILURE_T; + } + + dest->bNonTransactional = src->bNonTransactional; + dest->regOpCount = src->regOpCount; + dest->hClientTarget = src->hClientTarget; + dest->hChannelTarget = src->hChannelTarget; + + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regOp = src->regOps[idx].regOp; + dest->regOps[idx].regType = src->regOps[idx].regType; + dest->regOps[idx].regQuad = src->regOps[idx].regQuad; + dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; + dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; + dest->regOps[idx].regOffset = src->regOps[idx].regOffset; + dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; + dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + dest->smIds[idx] = src->smIds[idx]; + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regStatus = src->regOps[idx].regStatus; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS + +#endif + +#ifdef BUILD_COMMON_RPCS +static +return_t deserialize_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00(NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 *src = (void*)(buffer); + NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *dest = pParams; + + if (src && dest) + { + dest->hChannel = src->hChannel; + dest->property = src->property; + dest->value = src->value; + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS +#endif + +#ifdef BUILD_COMMON_RPCS +static +return_t deserialize_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v1A_1C( + NV2080_CTRL_GPU_EVICT_CTX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 *src = (void*)(buffer); + NV2080_CTRL_GPU_EVICT_CTX_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS +#ifdef VMIOP_BUILD + dest->engineType = deserialize_engineType(src->engineType); +#else + dest->engineType = src->engineType; +#endif + dest->hClient = src->hClient; + dest->ChID = src->ChID; + dest->hChanClient = src->hChanClient; + dest->hObject = src->hObject; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D(NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D *src = (void*)(buffer); + NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *dest = pParams; + NvU32 idx = 0; + + if (src && dest) + { + if (src->numQueries > NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D) { + return FAILURE_T; + } +#ifdef COPY_INPUT_PARAMETERS + dest->numQueries = src->numQueries; +#endif + for (idx = 0; idx < dest->numQueries; idx++) { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryType = src->queries[idx].queryType; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].status = src->queries[idx].status; +#endif + switch(dest->queries[idx].queryType) + { + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT: { +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.gpcCountData.gpcCount = src->queries[idx].queryData.gpcCountData.gpcCount; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.chipletGpcMapData.gpcId = src->queries[idx].queryData.chipletGpcMapData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.chipletGpcMapData.chipletGpcMap = src->queries[idx].queryData.chipletGpcMapData.chipletGpcMap; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.tpcMaskData.gpcId = src->queries[idx].queryData.tpcMaskData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.tpcMaskData.tpcMask = src->queries[idx].queryData.tpcMaskData.tpcMask; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.ppcMaskData.gpcId = src->queries[idx].queryData.ppcMaskData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.ppcMaskData.ppcMask = src->queries[idx].queryData.ppcMaskData.ppcMask; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.partitionGpcMapData.swizzId = src->queries[idx].queryData.partitionGpcMapData.swizzId; + dest->queries[idx].queryData.partitionGpcMapData.gpcId = src->queries[idx].queryData.partitionGpcMapData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.partitionGpcMapData.chipletGpcMap = src->queries[idx].queryData.partitionGpcMapData.chipletGpcMap; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK: { +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.syspipeMaskData.chipletSyspipeMask = src->queries[idx].queryData.syspipeMaskData.chipletSyspipeMask; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.partitionChipletSyspipeData.swizzId = src->queries[idx].queryData.partitionChipletSyspipeData.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount = src->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount; + + if (dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount > NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D) { + return FAILURE_T; + } + + for (idx = 0; idx < dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount; idx++) + dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeId[idx] = src->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeId[idx]; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.dmGpcMaskData.swizzId = src->queries[idx].queryData.dmGpcMaskData.swizzId; + dest->queries[idx].queryData.dmGpcMaskData.grIdx = src->queries[idx].queryData.dmGpcMaskData.grIdx; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.dmGpcMaskData.gpcEnMask = src->queries[idx].queryData.dmGpcMaskData.gpcEnMask; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID: { +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.partitionSyspipeIdData.syspipeId = src->queries[idx].queryData.partitionSyspipeIdData.syspipeId; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.ropMaskData.gpcId = src->queries[idx].queryData.ropMaskData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.ropMaskData.ropMask = src->queries[idx].queryData.ropMaskData.ropMask; +#endif + break; + } + default: + { + // Unknown query + return FAILURE_T; + } + } + } + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00(NV2080_CTRL_FB_GET_FS_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 *src = (void*)(buffer); + NV2080_CTRL_FB_GET_FS_INFO_PARAMS *dest = pParams; + NvU32 idx = 0; + + if (src && dest) + { + if (src->numQueries > NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + dest->numQueries = src->numQueries; +#endif + for (idx = 0; idx < dest->numQueries; idx++) { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryType = src->queries[idx].queryType; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].status = src->queries[idx].status; +#endif + switch(dest->queries[idx].queryType) + { + case NV2080_CTRL_FB_FS_INFO_INVALID_QUERY: { +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i = 0; + for (i = 0; i < NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D; i++) { + dest->queries[idx].queryParams.inv.data[i] = src->queries[idx].queryParams.inv.data[i]; + } +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_FBP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.fbp.swizzId = src->queries[idx].queryParams.fbp.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.fbp.fbpEnMask = src->queries[idx].queryParams.fbp.fbpEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_LTC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.ltc.fbpIndex = src->queries[idx].queryParams.ltc.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.ltc.ltcEnMask = src->queries[idx].queryParams.ltc.ltcEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_LTS_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.lts.fbpIndex = src->queries[idx].queryParams.lts.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.lts.ltsEnMask = src->queries[idx].queryParams.lts.ltsEnMask; +#endif + + break; + } + case NV2080_CTRL_FB_FS_INFO_FBPA_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.fbpa.fbpIndex = src->queries[idx].queryParams.fbpa.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.fbpa.fbpaEnMask = src->queries[idx].queryParams.fbpa.fbpaEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_ROP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.rop.fbpIndex = src->queries[idx].queryParams.rop.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.rop.ropEnMask = src->queries[idx].queryParams.rop.ropEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmLtc.fbpIndex = src->queries[idx].queryParams.dmLtc.fbpIndex; + dest->queries[idx].queryParams.dmLtc.swizzId = src->queries[idx].queryParams.dmLtc.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmLtc.ltcEnMask = src->queries[idx].queryParams.dmLtc.ltcEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmLts.fbpIndex = src->queries[idx].queryParams.dmLts.fbpIndex; + dest->queries[idx].queryParams.dmLts.swizzId = src->queries[idx].queryParams.dmLts.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmLts.ltsEnMask = src->queries[idx].queryParams.dmLts.ltsEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmFbpa.fbpIndex = src->queries[idx].queryParams.dmFbpa.fbpIndex; + dest->queries[idx].queryParams.dmFbpa.swizzId = src->queries[idx].queryParams.dmFbpa.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmFbpa.fbpaEnMask = src->queries[idx].queryParams.dmFbpa.fbpaEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmRop.fbpIndex = src->queries[idx].queryParams.dmRop.fbpIndex; + dest->queries[idx].queryParams.dmRop.swizzId = src->queries[idx].queryParams.dmRop.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmRop.ropEnMask = src->queries[idx].queryParams.dmRop.ropEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmFbpaSubp.fbpIndex = src->queries[idx].queryParams.dmFbpaSubp.fbpIndex; + dest->queries[idx].queryParams.dmFbpaSubp.swizzId = src->queries[idx].queryParams.dmFbpaSubp.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmFbpaSubp.fbpaSubpEnMask = src->queries[idx].queryParams.dmFbpaSubp.fbpaSubpEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.fbpaSubp.fbpIndex = src->queries[idx].queryParams.fbpaSubp.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.fbpaSubp.fbpaSubpEnMask = src->queries[idx].queryParams.fbpaSubp.fbpaSubpEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.fbpLogicalMap.fbpIndex = src->queries[idx].queryParams.fbpLogicalMap.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.fbpLogicalMap.fbpLogicalIndex = src->queries[idx].queryParams.fbpLogicalMap.fbpLogicalIndex; +#endif + break; + } + default: + { + // Unknown query + return FAILURE_T; + } + } + } + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +#ifdef VMIOP_BUILD + +static +return_t deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06 *src = (void*)(buffer); + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->flags = src->flags; +#endif + +#ifdef COPY_OUTPUT_PARAMETERS + { + NvU32 i; + + dest->bFatalPoisonError = src->bFatalPoisonError; + + for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06; i++) + { + dest->units[i].enabled = src->units[i].enabled; + dest->units[i].scrubComplete = src->units[i].scrubComplete; + dest->units[i].supported = src->units[i].supported; + dest->units[i].dbe.count = src->units[i].dbe.count; + dest->units[i].dbeNonResettable.count = src->units[i].dbeNonResettable.count; + dest->units[i].sbe.count = src->units[i].sbe.count; + dest->units[i].sbeNonResettable.count = src->units[i].sbeNonResettable.count; + } + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +#endif // VMIOP_BUILD + +return_t deserialize_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E( + NVA06F_CTRL_STOP_CHANNEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E *src = (void*)(buffer); + NVA06F_CTRL_STOP_CHANNEL_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->bImmediate = src->bImmediate; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t deserialize_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F(NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F *src = (void*)(buffer); + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *dest = pParams; + + if (src && dest) + { + dest->pmaChannelIdx = src->pmaChannelIdx; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F(NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F *src = (void*)(buffer); + NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *dest = pParams; + + if (src && dest) + { + dest->hChannel = src->hChannel; + dest->samplingMode = src->samplingMode; + dest->grRouteInfo.flags = src->grRouteInfo.flags; + dest->grRouteInfo.route = src->grRouteInfo.route; + + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F(NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F *src = (void*)(buffer); + NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *dest = pParams; + + if (src && dest) + { + dest->bSetMaxFreq = src->bSetMaxFreq; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F(NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_OUTPUT_PARAMETERS + NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F *src = (void*)(buffer); + NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *dest = pParams; + NvU32 i = 0; + + if (src && dest) + { + dest->rm.clientActiveMask = src->rm.clientActiveMask; + dest->rm.bRegkeyLimitRatedTdp = src->rm.bRegkeyLimitRatedTdp; + dest->output = src->output; + + for (i = 0; i < NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F; i++) + { + dest->inputs[i] = src->inputs[i]; + } + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F(NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F *src = (void*)(buffer); + NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *dest = pParams; + + if (src && dest) + { + dest->client = src->client; + dest->input = src->input; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23( + NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 *src = (void*)(buffer); + NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *dest = pParams; + + if (src && dest) + { + dest->base = src->base; + dest->size = src->size; + dest->addressSpace = src->addressSpace; + dest->cacheAttrib = src->cacheAttrib; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t deserialize_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02(NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *dest = pParams; + + if (src && dest) + { + dest->smID = src->smID; + dest->bSingleStep = src->bSingleStep; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t deserialize_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 *src = (void*)(buffer); + NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *dest = pParams; + + if (src && dest) + { + dest->hChannelGroup = src->hChannelGroup; + dest->mode = src->mode; + dest->bEnableAllTpcs = src->bEnableAllTpcs; + dest->grRouteInfo.flags = src->grRouteInfo.flags; + dest->grRouteInfo.route = src->grRouteInfo.route; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t +deserialize_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07( + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 *src = + (void*)(buffer); + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *dest = pParams; + + if (src && dest) + { + NvU32 i; + + if (src->numValidEntries > + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07) + { + return FAILURE_T; + } + + dest->numValidEntries = src->numValidEntries; + + for (i = 0; i < src->numValidEntries; ++i) + { + dest->bar2Addr[i] = src->bar2Addr[i]; + dest->methodBufferMemdesc[i].base = + src->methodBufferMemdesc[i].base; + dest->methodBufferMemdesc[i].size = + src->methodBufferMemdesc[i].size; + dest->methodBufferMemdesc[i].alignment = + src->methodBufferMemdesc[i].alignment; + dest->methodBufferMemdesc[i].addressSpace = + src->methodBufferMemdesc[i].addressSpace; + dest->methodBufferMemdesc[i].cpuCacheAttrib = + src->methodBufferMemdesc[i].cpuCacheAttrib; + } + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t deserialize_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08(NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 *src = (void*)(buffer); + NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *dest = pParams; + + if (src && dest) + { + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->bMembytesPollingRequired = src->bMembytesPollingRequired; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t deserialize_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06(NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_OUTPUT_PARAMETERS + NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 *src = (void*)(buffer); + NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *dest = pParams; + + if (src && dest) + { + dest->bMode = src->bMode; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS +return_t deserialize_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A( + NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A *src = (void*)(buffer); + NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->hChannel = src->hChannel; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->totalBufferSize = src->totalBufferSize; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS +return_t deserialize_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A( + NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A *src = (void*)(buffer); + NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->hUserClient = src->hUserClient; + dest->hChannel = src->hChannel; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->alignment = src->alignment; + dest->size = src->size; + dest->bufferHandle = src->bufferHandle; + dest->pageCount = src->pageCount; + dest->physAddr = src->physAddr; + dest->aperture = src->aperture; + dest->kind = src->kind; + dest->pageSize = src->pageSize; + dest->bIsContigous = src->bIsContigous; + dest->bDeviceDescendant = src->bDeviceDescendant; + portMemCopy(dest->uuid, sizeof(dest->uuid), + src->uuid, sizeof(src->uuid)); +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_COMMON_RPCS +return_t deserialize_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_v1F_05( + NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 *src = (void*)(buffer); + NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *dest = pParams; + + if (src && dest) + { + dest->bZbcSurfacesExist = src->bZbcSurfacesExist; + } + else + return FAILURE_T; +#endif + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_COMMON_RPCS +static +return_t deserialize_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C( + NV00F8_CTRL_DESCRIBE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C *src = (void*)(buffer); + NV00F8_CTRL_DESCRIBE_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->offset = src->offset; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + + portMemSet(dest, 0, sizeof(*dest)); + + dest->totalPfns = src->totalPfns; + for (i = 0; i < NV00F8_CTRL_DESCRIBE_PFN_ARRAY_SIZE; i++) + { + dest->pfnArray[i] = src->pfnArray[i]; + } + dest->numPfns = src->numPfns; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C( + NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C *src = (void*)(buffer); + NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->totalSize = src->totalSize; + dest->freeSize = src->freeSize; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t deserialize_NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_v1F_0D(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B *src = (void *) buffer; + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->eccMask = src->eccMask; + dest->nvlinkMask = src->nvlinkMask; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_COMMON_RPCS +#endif + +#ifdef BUILD_COMMON_RPCS +return_t deserialize_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C(NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C *src = (void*)(buffer); + NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *dest = pParams; + + if (src && dest) + { + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->pmaBufferVA = src->pmaBufferVA; + dest->pmaBufferSize = src->pmaBufferSize; + dest->membytesVA = src->membytesVA; + dest->hwpmIBPA = src->hwpmIBPA; + dest->hwpmIBAperture = src->hwpmIBAperture; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +return_t deserialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE_v24_05(NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 *src = (void *) buffer; + NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *dest = pParams; + NvU32 i; + + if (src && dest) + { + if (src->execPartCount > NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05) { + return FAILURE_T; + } +#ifdef COPY_INPUT_PARAMETERS + dest->bQuery = src->bQuery; + dest->execPartCount = src->execPartCount; + + for (i = 0; i < dest->execPartCount; i++) { + dest->execPartInfo[i].gpcCount = src->execPartInfo[i].gpcCount; + + //Added in version v24_05 + dest->execPartInfo[i].gfxGpcCount = src->execPartInfo[i].gfxGpcCount; + + dest->execPartInfo[i].veidCount = src->execPartInfo[i].veidCount; + dest->execPartInfo[i].ceCount = src->execPartInfo[i].ceCount; + dest->execPartInfo[i].nvEncCount = src->execPartInfo[i].nvEncCount; + dest->execPartInfo[i].nvDecCount = src->execPartInfo[i].nvDecCount; + dest->execPartInfo[i].nvJpgCount = src->execPartInfo[i].nvJpgCount; + dest->execPartInfo[i].ofaCount = src->execPartInfo[i].ofaCount; + dest->execPartInfo[i].sharedEngFlag = src->execPartInfo[i].sharedEngFlag; + dest->execPartInfo[i].smCount = src->execPartInfo[i].smCount; + dest->execPartInfo[i].spanStart = src->execPartInfo[i].spanStart; + dest->execPartInfo[i].computeSize = src->execPartInfo[i].computeSize; + } +#endif + +#ifdef COPY_OUTPUT_PARAMETERS + for (i = 0; i < src->execPartCount; i++) { + dest->execPartId[i] = src->execPartId[i]; + dest->execPartInfo[i].computeSize = src->execPartInfo[i].computeSize; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t deserialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE_v1F_0A(NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 *src = (void *) buffer; + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + NvU32 i; + + if (src->execPartCount > NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05) { + return FAILURE_T; + } + + dest->execPartCount = src->execPartCount; + for (i = 0; i < dest->execPartCount; i++) { + dest->execPartId[i] = src->execPartId[i]; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t deserialize_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_v1F_0A(NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 *src = (void *) buffer; + NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->workSubmitToken = src->workSubmitToken; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t deserialize_NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_v1F_0A(NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 *src = (void *) buffer; + NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->index = src->index; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t deserialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 *src = (void*)(buffer); + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *dest = pParams; + if (src && dest) + { + dest->connectionType = src->connectionType; + dest->peerId = src->peerId; + dest->bSpaAccessOnly = src->bSpaAccessOnly; + dest->bUseUuid = src->bUseUuid; + + portMemCopy(dest->remoteGpuUuid, + VM_UUID_SIZE_v21_02, + src->remoteGpuUuid, + VM_UUID_SIZE_v21_02); + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +return_t deserialize_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 *src = (void*)(buffer); + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *dest = pParams; + + if (src && dest) + { + dest->connectionType = src->connectionType; + dest->peerId = src->peerId; + dest->bUseUuid = src->bUseUuid; + + portMemCopy(dest->remoteGpuUuid, + VM_UUID_SIZE_v21_02, + src->remoteGpuUuid, + VM_UUID_SIZE_v21_02); + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +#ifndef UMED_BUILD +return_t deserialize_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11(NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 *src = (void*)(buffer); + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *dest = pParams; + if (src && dest) + { + NvU32 i; + if (src->gpuInfoListSize > NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + dest->gpuInfoListSize = src->gpuInfoListSize; +#endif + + for (i = 0; i < NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11; i++) { +#ifdef COPY_INPUT_PARAMETERS + dest->gpuInfoList[i].index = src->gpuInfoList[i].index; +#endif + dest->gpuInfoList[i].data = src->gpuInfoList[i].data; + } + } + else + return FAILURE_T; + return SUCCESS_T; +} +#endif // UMED_BUILD + +return_t deserialize_NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK_v21_05( + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 *src = (void*)(buffer); + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *dest = pParams; + + if (src && dest) + { + dest->imbPhysAddr = src->imbPhysAddr; + dest->addrSpace = src->addrSpace; + dest->flaAction = src->flaAction; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +return_t deserialize_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 *src = (void*)(buffer); + NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->numCredits = src->numCredits; +#endif + } + else + return FAILURE_T; + return SUCCESS_T; +} + +return_t deserialize_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 *src = (void*)(buffer); + NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *dest = pParams; + + if (src && dest) + { + NvU32 i; + if (src->numEntries > NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08) { + return FAILURE_T; + } +#ifdef COPY_OUTPUT_PARAMETERS + dest->statusInfo.status = src->statusInfo.status; + dest->statusInfo.entryIndex = src->statusInfo.entryIndex; + for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { + dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; + } + +#endif +#ifdef COPY_INPUT_PARAMETERS + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->numEntries = src->numEntries; + + for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { + dest->creditInfo[i].chipletType = src->creditInfo[i].chipletType; + dest->creditInfo[i].chipletIndex = src->creditInfo[i].chipletIndex; + } +#endif + } + else + return FAILURE_T; + return SUCCESS_T; +} + +return_t deserialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 *src = (void*)(buffer); + NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *dest = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->statusInfo.status = src->statusInfo.status; + dest->statusInfo.entryIndex = src->statusInfo.entryIndex; +#endif +#ifdef COPY_INPUT_PARAMETERS + NvU32 i; + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->numEntries = src->numEntries; + + if (src->numEntries > NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08) { + return FAILURE_T; + } + + for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { + dest->creditInfo[i].chipletType = src->creditInfo[i].chipletType; + dest->creditInfo[i].chipletIndex = src->creditInfo[i].chipletIndex; + dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; + } +#endif + } + else + return FAILURE_T; + return SUCCESS_T; +} + +#ifndef UMED_BUILD +return_t deserialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 *src = (void*)(buffer); + NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *dest = pParams; + + if (src && dest) { + dest->value = src->value; + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#endif +#endif //GSP_FW_BUILD + +#undef COPY_INPUT_PARAMETERS +#undef COPY_OUTPUT_PARAMETERS + +// Copy elements from SDK structures to RPC structures (Step 1 or step 3 listed above) +#ifdef VMIOP_BUILD +#define COPY_OUTPUT_PARAMETERS +#endif + +#ifdef RESMAN_BUILD +#define COPY_INPUT_PARAMETERS +#endif + +#ifdef GSP_FW_BUILD +#define COPY_OUTPUT_PARAMETERS +#endif + +#ifndef GSP_FW_BUILD +#ifdef BUILD_COMMON_RPCS + +static +return_t serialize_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01(NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *src = pParams; + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 *dest = (void*)(buffer); + + if (src && dest) { + dest->hResolution = src->hResolution; + dest->vResolution = src->vResolution; + dest->averageEncodeLatency = src->averageEncodeLatency; + dest->averageEncodeFps = src->averageEncodeFps; + dest->timestampBufferSize = 0; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01(NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *src = pParams; + NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef VMIOP_BUILD + dest->engineID = serialize_engineType(src->engineID); +#else + dest->engineID = src->engineID; +#endif + dest->subdeviceInstance = src->subdeviceInstance; + dest->resetReason = src->resetReason; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00(NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *src = pParams; + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->exceptType = src->exceptType; +#ifdef VMIOP_BUILD + dest->engineID = serialize_engineType(src->engineID); +#else + dest->engineID = src->engineID; +#endif + } + else + return FAILURE_T; + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09(NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *src = pParams; + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 *dest = (void*)(buffer); + + if (src && dest) { + dest->faultType = src->faultType; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00(NV2080_CTRL_PERF_BOOST_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_PERF_BOOST_PARAMS *src = pParams; + NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->flags = src->flags; + dest->duration = src->duration; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *src = pParams; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 *dest = (void*)(buffer); + + if (src && dest) { + NvU32 i; + for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { + dest->value.colorFB[i] = src->value.colorFB[i]; + dest->value.colorDS[i] = src->value.colorDS[i]; + } + dest->value.depth = src->value.depth; + dest->value.stencil = src->value.stencil; // Changed in v04_00 + dest->indexSize = src->indexSize; + dest->indexUsed = src->indexUsed; + dest->format = src->format; + dest->valType = src->valType; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *src = pParams; + NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + NvU32 i; + for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { + dest->colorFB[i] = src->colorFB[i]; + dest->colorDS[i] = src->colorDS[i]; + } + dest->format = src->format; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *src = pParams; + NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->depth = src->depth; + dest->format = src->format; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *src = pParams; + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->bEnable = src->bEnable; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00(NVA06C_CTRL_TIMESLICE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVA06C_CTRL_TIMESLICE_PARAMS *src = pParams; + NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->timesliceUs = src->timesliceUs; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00(NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *src = pParams; + NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 *dest = (void*)(buffer); + NvU32 i; + + if (src && dest) { + if (src->numChannels > NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES) { + return FAILURE_T; + } + dest->bDisable = src->bDisable; + dest->numChannels = src->numChannels; + dest->bOnlyDisableScheduling = src->bOnlyDisableScheduling; + dest->bRewindGpPut = src->bRewindGpPut; + dest->pRunlistPreemptEvent = 0; // vGPU do not support guest kernel handles + + for (i = 0; i < src->numChannels ; i++) + { + dest->hClientList[i] = src->hClientList[i]; + dest->hChannelList[i] = src->hChannelList[i]; + } + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A(NVA06C_CTRL_PREEMPT_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA06C_CTRL_PREEMPT_PARAMS *src = pParams; + NVA06C_CTRL_PREEMPT_PARAMS_v09_0A *dest = (void*)(buffer); + + if (src && dest) { + dest->bWait = src->bWait; + dest->bManualTimeout = src->bManualTimeout; + dest->timeoutUs = src->timeoutUs; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *src = pParams; + NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *dest = (void*)(buffer); + + if (src && dest) { + dest->tsgInterleaveLevel = src->tsgInterleaveLevel; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *src = pParams; + NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *dest = (void*)(buffer); + + if (src && dest) { + dest->channelInterleaveLevel = src->channelInterleaveLevel; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01(NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *src = pParams; + NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 *dest = (void*)(buffer); + + if (src && dest) { + NvU32 i; + + dest->flags = src->flags; + dest->hClient = src->hClient; + dest->hChannel = src->hChannel; + for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END; ++i) + dest->vMemPtrs[i] = src->vMemPtrs[i]; + dest->gfxpPreemptMode = src->gfxpPreemptMode; + dest->cilpPreemptMode = src->cilpPreemptMode; + dest->grRouteInfo.flags = src->grRouteInfo.flags; + dest->grRouteInfo.route = src->grRouteInfo.route; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01(NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *src = pParams; + NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 *dest = (void*)(buffer); + + if (src && dest) { + dest->flags = src->flags; + dest->hChannel = src->hChannel; + dest->gfxpPreemptMode = src->gfxpPreemptMode; + dest->cilpPreemptMode = src->cilpPreemptMode; + dest->grRouteInfo.flags = src->grRouteInfo.flags; + dest->grRouteInfo.route = src->grRouteInfo.route; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00(NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *src = pParams; + NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->hClient = src->hClient; + dest->hChannel = src->hChannel; + dest->vMemPtr = src->vMemPtr; + dest->zcullMode = src->zcullMode; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00(NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *src = pParams; + NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef VMIOP_BUILD + dest->engineType = serialize_engineType(src->engineType); +#else + dest->engineType = src->engineType; +#endif + dest->hClient = src->hClient; + dest->ChID = src->ChID; + dest->hChanClient = src->hChanClient; + dest->hObject = src->hObject; + dest->hVirtMemory = src->hVirtMemory; + dest->physAddress = src->physAddress; + dest->physAttr = src->physAttr; + dest->hDmaHandle = src->hDmaHandle; + dest->index = src->index; + dest->size = src->size; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *src = pParams; + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 *dest = (void*)(buffer); + + if (src && dest) { + NvU32 i; + + if (src->numLevelsToCopy > GMMU_FMT_MAX_LEVELS_v1A_12) { + return FAILURE_T; + } + + dest->hSubDevice = src->hSubDevice; + dest->subDeviceId = src->subDeviceId; + dest->pageSize = src->pageSize; + dest->virtAddrLo = src->virtAddrLo; + dest->virtAddrHi = src->virtAddrHi; + dest->numLevelsToCopy = src->numLevelsToCopy; + + for (i = 0; i < dest->numLevelsToCopy; i++) + { + dest->levels[i].physAddress = src->levels[i].physAddress; + dest->levels[i].aperture = src->levels[i].aperture; + dest->levels[i].size = src->levels[i].size; + dest->levels[i].pageShift = src->levels[i].pageShift; + } + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS +#endif + +#ifdef BUILD_COMMON_RPCS + +static +return_t serialize_GET_BRAND_CAPS_v25_12(NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_OUTPUT_PARAMETERS + NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *src = pParams; + rpc_get_brand_caps_v25_12 *dest = (void*)(buffer); + + if (src && dest) { + dest->brands = src->brands; + } + else + return FAILURE_T; +#endif + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01(NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_OUTPUT_PARAMETERS + NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *src = pParams; + NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 *dest = (void*)(buffer); + + if (src && dest) { + dest->engines = src->engines; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00(NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->hTargetChannel = src->hTargetChannel; + dest->numSMsToClear = src->numSMsToClear; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06(NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; +#endif + +#ifdef COPY_INPUT_PARAMETERS + dest->hTargetChannel = src->hTargetChannel; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + if (src->numSMsToRead > VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06) { + return FAILURE_T; + } + + for (i = 0; i < src->numSMsToRead; ++i) + { + dest->smErrorStateArray[i].hwwGlobalEsr = src->smErrorStateArray[i].hwwGlobalEsr; + dest->smErrorStateArray[i].hwwWarpEsr = src->smErrorStateArray[i].hwwWarpEsr; + dest->smErrorStateArray[i].hwwWarpEsrPc = src->smErrorStateArray[i].hwwWarpEsrPc; + dest->smErrorStateArray[i].hwwGlobalEsrReportMask = src->smErrorStateArray[i].hwwGlobalEsrReportMask; + dest->smErrorStateArray[i].hwwWarpEsrReportMask = src->smErrorStateArray[i].hwwWarpEsrReportMask; + dest->smErrorStateArray[i].hwwEsrAddr = src->smErrorStateArray[i].hwwEsrAddr; + dest->smErrorStateArray[i].hwwWarpEsrPc64 = src->smErrorStateArray[i].hwwWarpEsrPc64; + /* New fields added in version v21_06 */ + dest->smErrorStateArray[i].hwwCgaEsr = src->smErrorStateArray[i].hwwCgaEsr; + dest->smErrorStateArray[i].hwwCgaEsrReportMask = src->smErrorStateArray[i].hwwCgaEsrReportMask; + } + dest->mmuFault.valid = src->mmuFault.valid; + dest->mmuFault.faultInfo = src->mmuFault.faultInfo; + dest->mmuFaultInfo = src->mmuFault.faultInfo; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00(NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->exceptionMask = src->exceptionMask; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20(NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *src = pParams; + NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 *dest = (void*)(buffer); + NvU32 i; + + if (src && dest) + { +#ifdef VMIOP_BUILD + dest->engineType = serialize_engineType(src->engineType); +#else + dest->engineType = src->engineType; +#endif + dest->hClient = src->hClient; + dest->ChID = src->ChID; + dest->hChanClient = src->hChanClient; + dest->hObject = src->hObject; + dest->hVirtMemory = src->hVirtMemory; + dest->virtAddress = src->virtAddress; + dest->size = src->size; + dest->entryCount = src->entryCount; + + if (dest->entryCount > NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES) { + return FAILURE_T; + } + + for (i = 0; i < dest->entryCount; i++) { + dest->promoteEntry[i].gpuPhysAddr = src->promoteEntry[i].gpuPhysAddr; + dest->promoteEntry[i].gpuVirtAddr = src->promoteEntry[i].gpuVirtAddr; + dest->promoteEntry[i].size = src->promoteEntry[i].size; + dest->promoteEntry[i].physAttr = src->promoteEntry[i].physAttr; + dest->promoteEntry[i].bufferId = src->promoteEntry[i].bufferId; + dest->promoteEntry[i].bInitialize = src->promoteEntry[i].bInitialize; + dest->promoteEntry[i].bNonmapped = src->promoteEntry[i].bNonmapped; + } + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06(NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *src = pParams; + NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_OUTPUT_PARAMETERS + dest->waitForEvent = src->waitForEvent; + dest->hResidentChannel = src->hResidentChannel; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 *dest = (void*)(buffer); + + if (src && dest) { + NvU32 idx = 0; +#ifdef COPY_INPUT_PARAMETERS + if (src->regOpCount > NV83DE_CTRL_GPU_EXEC_REG_OPS_MAX_OPS) { + return FAILURE_T; + } + + dest->bNonTransactional = src->bNonTransactional; + dest->regOpCount = src->regOpCount; + + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regOp = src->regOps[idx].regOp; + dest->regOps[idx].regType = src->regOps[idx].regType; + dest->regOps[idx].regQuad = src->regOps[idx].regQuad; + dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; + dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; + dest->regOps[idx].regOffset = src->regOps[idx].regOffset; + dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; + dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regStatus = src->regOps[idx].regStatus; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->action = src->action; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06(NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->hTargetChannel = src->hTargetChannel; + dest->smID = src->smID; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->smErrorState.hwwGlobalEsr = src->smErrorState.hwwGlobalEsr; + dest->smErrorState.hwwWarpEsr = src->smErrorState.hwwWarpEsr; + dest->smErrorState.hwwWarpEsrPc = src->smErrorState.hwwWarpEsrPc; + dest->smErrorState.hwwGlobalEsrReportMask = src->smErrorState.hwwGlobalEsrReportMask; + dest->smErrorState.hwwWarpEsrReportMask = src->smErrorState.hwwWarpEsrReportMask; + dest->smErrorState.hwwEsrAddr = src->smErrorState.hwwEsrAddr; + dest->smErrorState.hwwWarpEsrPc64 = src->smErrorState.hwwWarpEsrPc64; + /* New fields added in version v21_06 */ + dest->smErrorState.hwwCgaEsr = src->smErrorState.hwwCgaEsr; + dest->smErrorState.hwwCgaEsrReportMask = src->smErrorState.hwwCgaEsrReportMask; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->hTargetChannel = src->hTargetChannel; + dest->smID = src->smID; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->action = src->action; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06(NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->stopTriggerType = src->stopTriggerType; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00(NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *src = pParams; + NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) { + dest->hVASpace = src->hVASpace; + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07(NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *src = pParams; + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + dest->ceEngineType = src->ceEngineType; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->pceMask = src->pceMask; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *src = pParams; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 *dest = (void*)(buffer); + + if (src && dest) { + ct_assert(NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE == 4); + +#ifdef COPY_INPUT_PARAMETERS + dest->index = src->index; + dest->tableType = src->tableType; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + for (i = 0; i < NV9096_CTRL_SET_ZBC_COLOR_CLEAR_VALUE_SIZE; ++i) { + dest->value.colorFB[i] = src->value.colorFB[i]; + dest->value.colorDS[i] = src->value.colorDS[i]; + } + dest->value.depth = src->value.depth; + dest->value.stencil = src->value.stencil; + dest->format = src->format; + dest->index = src->index; + dest->bIndexValid = src->bIndexValid; + dest->tableType = src->tableType; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00(NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *src = pParams; + NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + + for (i = 0; i < NV2080_CTRL_BUS_MAX_NUM_GPUS; i++) { + dest->nvlinkPeerIdMask[i] = src->nvlinkPeerIdMask[i]; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *src = pParams; + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + + dest->enabledLinkMask = src->enabledLinkMask; + + FOR_EACH_INDEX_IN_MASK(32, i, src->enabledLinkMask) + { + NV2080_CTRL_NVLINK_DEVICE_INFO *deviceInfo_s = NULL; + NV2080_CTRL_NVLINK_DEVICE_INFO_v15_02 *deviceInfo_d = NULL; + + if (i >= NV2080_CTRL_NVLINK_MAX_LINKS_v23_04) + break; + + dest->linkInfo[i].capsTbl = src->linkInfo[i].capsTbl; + dest->linkInfo[i].phyType = src->linkInfo[i].phyType; + dest->linkInfo[i].subLinkWidth = src->linkInfo[i].subLinkWidth; + dest->linkInfo[i].linkState = src->linkInfo[i].linkState; + dest->linkInfo[i].rxSublinkStatus = src->linkInfo[i].rxSublinkStatus; + dest->linkInfo[i].txSublinkStatus = src->linkInfo[i].txSublinkStatus; + dest->linkInfo[i].nvlinkVersion = src->linkInfo[i].nvlinkVersion; + dest->linkInfo[i].nciVersion = src->linkInfo[i].nciVersion; + dest->linkInfo[i].phyVersion = src->linkInfo[i].phyVersion; + dest->linkInfo[i].nvlinkLinkClockKHz = src->linkInfo[i].nvlinkLinkClockKHz; + dest->linkInfo[i].nvlinkLineRateMbps = src->linkInfo[i].nvlinkLineRateMbps; + dest->linkInfo[i].connected = src->linkInfo[i].connected; + dest->linkInfo[i].remoteDeviceLinkNumber = src->linkInfo[i].remoteDeviceLinkNumber; + dest->linkInfo[i].localDeviceLinkNumber = src->linkInfo[i].localDeviceLinkNumber; + + deviceInfo_d = &dest->linkInfo[i].localDeviceInfo; + deviceInfo_s = &src->linkInfo[i].localDeviceInfo; + + deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags; + deviceInfo_d->domain = deviceInfo_s->domain; + deviceInfo_d->bus = deviceInfo_s->bus; + deviceInfo_d->device = deviceInfo_s->device; + deviceInfo_d->function = deviceInfo_s->function; + deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId; + deviceInfo_d->deviceType = deviceInfo_s->deviceType; + portMemCopy(deviceInfo_d->deviceUUID, + sizeof(deviceInfo_d->deviceUUID), + deviceInfo_s->deviceUUID, + sizeof(deviceInfo_s->deviceUUID)); + + deviceInfo_d = &dest->linkInfo[i].remoteDeviceInfo; + deviceInfo_s = &src->linkInfo[i].remoteDeviceInfo; + + deviceInfo_d->deviceIdFlags = deviceInfo_s->deviceIdFlags; + deviceInfo_d->domain = deviceInfo_s->domain; + deviceInfo_d->bus = deviceInfo_s->bus; + deviceInfo_d->device = deviceInfo_s->device; + deviceInfo_d->function = deviceInfo_s->function; + deviceInfo_d->pciDeviceId = deviceInfo_s->pciDeviceId; + deviceInfo_d->deviceType = deviceInfo_s->deviceType; + portMemCopy(deviceInfo_d->deviceUUID, + sizeof(deviceInfo_d->deviceUUID), + deviceInfo_s->deviceUUID, + sizeof(deviceInfo_s->deviceUUID)); + } + FOR_EACH_INDEX_IN_MASK_END; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *src = pParams; + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + portMemCopy(dest->gpuIds, (sizeof(NvU32) * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS), + src->gpuIds, (sizeof(NvU32) * NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)); + dest->gpuCount = src->gpuCount; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->p2pCaps = src->p2pCaps; + dest->p2pOptimalReadCEs = src->p2pOptimalReadCEs; + dest->p2pOptimalWriteCEs = src->p2pOptimalWriteCEs; + memcpy(dest->p2pCapsStatus, src->p2pCapsStatus, NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D); +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *src = pParams; + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A *dest = (void*)(buffer); + + if (src && dest) { + if (src->grpACount == 0 || + src->grpACount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS || + src->grpBCount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + NvU32 idx = 0; + + dest->grpACount = src->grpACount; + dest->grpBCount = src->grpBCount; + + for (idx = 0; idx < NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS; idx++) { + dest->gpuIdGrpA[idx] = src->gpuIdGrpA[idx]; + dest->gpuIdGrpB[idx] = src->gpuIdGrpB[idx]; + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 grpAIdx = 0, grpBIdx= 0; + + NvBool bReflexive = NV_FALSE; + + // Check for the reflexive case + if (src->grpBCount == 0) { + bReflexive = NV_TRUE; + } + + for (grpAIdx = 0; grpAIdx < src->grpACount; grpAIdx++) { + for (grpBIdx = 0; bReflexive ? grpBIdx <= grpAIdx : grpBIdx < src->grpBCount; grpBIdx++) { + dest->p2pCaps[grpAIdx].array[grpBIdx] = src->p2pCaps[grpAIdx][grpBIdx]; + dest->a2bOptimalReadCes[grpAIdx].array[grpBIdx] = src->a2bOptimalReadCes[grpAIdx][grpBIdx]; + dest->a2bOptimalWriteCes[grpAIdx].array[grpBIdx] = src->a2bOptimalWriteCes[grpAIdx][grpBIdx]; + dest->b2aOptimalReadCes[grpAIdx].array[grpBIdx] = src->b2aOptimalReadCes[grpAIdx][grpBIdx]; + dest->b2aOptimalWriteCes[grpAIdx].array[grpBIdx] = src->b2aOptimalWriteCes[grpAIdx][grpBIdx]; + } + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02(NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GET_P2P_CAPS_PARAMS *src = pParams; + NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 *dest = (void*)(buffer); + + if (src && dest) { +#ifdef COPY_INPUT_PARAMETERS + if (!src->bAllCaps && (src->peerGpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS)) + return FAILURE_T; + + dest->bAllCaps = src->bAllCaps; + dest->bUseUuid = src->bUseUuid; + + if (!src->bAllCaps) + { + NvU32 i; + dest->peerGpuCount = src->peerGpuCount; + + for (i = 0; i < src->peerGpuCount; ++i) + { + portMemCopy(dest->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE_v21_02, + src->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE_v21_02); + } + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + + if (src->peerGpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS) + return FAILURE_T; + + if (src->bAllCaps) + { + dest->peerGpuCount = src->peerGpuCount; + } + + for (i = 0; i < src->peerGpuCount; ++i) + { + if (src->bAllCaps) + { + portMemCopy(dest->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE_v21_02, + src->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE_v21_02); + } + + dest->peerGpuCaps[i].p2pCaps = src->peerGpuCaps[i].p2pCaps; + dest->peerGpuCaps[i].p2pOptimalReadCEs = src->peerGpuCaps[i].p2pOptimalReadCEs; + dest->peerGpuCaps[i].p2pOptimalWriteCEs = src->peerGpuCaps[i].p2pOptimalWriteCEs; + portMemCopy(dest->peerGpuCaps[i].p2pCapsStatus, + sizeof(dest->peerGpuCaps[i].p2pCapsStatus), + src->peerGpuCaps[i].p2pCapsStatus, + sizeof(src->peerGpuCaps[i].p2pCapsStatus)); + dest->peerGpuCaps[i].busPeerId = src->peerGpuCaps[i].busPeerId; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F(NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F *dest = (void*)(buffer); + NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *src = pParams; + + if (src && dest) + { + dest->ctxsw = src->ctxsw; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t serialize_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F(NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F *dest = (void*)(buffer); + NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *src = pParams; + if (src && dest) + { + dest->ctxsw = src->ctxsw; + } + else + return FAILURE_T; +#endif + + return SUCCESS_T; +} + +static +return_t serialize_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F(NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F *dest = (void*)(buffer); + NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *src = pParams; + NvU32 idx = 0; + + if (src && dest) + { + if (src->regOpCount > NVB0CC_REGOPS_MAX_COUNT) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + dest->regOpCount = src->regOpCount; + dest->mode = src->mode; + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regOp = src->regOps[idx].regOp; + dest->regOps[idx].regType = src->regOps[idx].regType; + dest->regOps[idx].regQuad = src->regOps[idx].regQuad; + dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; + dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; + dest->regOps[idx].regOffset = src->regOps[idx].regOffset; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; + dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->bPassed = src->bPassed; + dest->bDirect = src->bDirect; + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regStatus = src->regOps[idx].regStatus; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14(NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 *dest = (void*)(buffer); + NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->hMemPmaBuffer = src->hMemPmaBuffer; + dest->pmaBufferOffset = src->pmaBufferOffset; + dest->pmaBufferSize = src->pmaBufferSize; + dest->hMemPmaBytesAvailable = src->hMemPmaBytesAvailable; + dest->pmaBytesAvailableOffset = src->pmaBytesAvailableOffset; + dest->ctxsw = src->ctxsw; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->pmaBufferVA = src->pmaBufferVA; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 *dest = (void*)(buffer); + NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->bytesConsumed = src->bytesConsumed; + dest->bUpdateAvailableBytes = src->bUpdateAvailableBytes; + dest->bWait = src->bWait; + dest->bReturnPut = src->bReturnPut; + dest->pmaChannelIdx = src->pmaChannelIdx; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->bytesAvailable = src->bytesAvailable; + dest->putPtr = src->putPtr; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset){ + NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *src = pParams; + NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 *dest = (void*)(buffer); + + if (src && dest) { + NvU32 idx = 0; +#ifdef COPY_INPUT_PARAMETERS + if (src->regOpCount > NV2080_CTRL_MIGRATABLE_OPS_ARRAY_MAX_v21_07) { + return FAILURE_T; + } + + dest->bNonTransactional = src->bNonTransactional; + dest->regOpCount = src->regOpCount; + dest->hClientTarget = src->hClientTarget; + dest->hChannelTarget = src->hChannelTarget; + + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regOp = src->regOps[idx].regOp; + dest->regOps[idx].regType = src->regOps[idx].regType; + dest->regOps[idx].regQuad = src->regOps[idx].regQuad; + dest->regOps[idx].regGroupMask = src->regOps[idx].regGroupMask; + dest->regOps[idx].regSubGroupMask = src->regOps[idx].regSubGroupMask; + dest->regOps[idx].regOffset = src->regOps[idx].regOffset; + dest->regOps[idx].regAndNMaskLo = src->regOps[idx].regAndNMaskLo; + dest->regOps[idx].regAndNMaskHi = src->regOps[idx].regAndNMaskHi; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + dest->smIds[idx] = src->smIds[idx]; + } +#endif +#ifdef COPY_OUTPUT_PARAMETERS + for (idx = 0; idx < src->regOpCount; idx++) + { + dest->regOps[idx].regStatus = src->regOps[idx].regStatus; + dest->regOps[idx].regValueLo = src->regOps[idx].regValueLo; + dest->regOps[idx].regValueHi = src->regOps[idx].regValueHi; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS + +#endif + +#ifdef BUILD_COMMON_RPCS +static +return_t serialize_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00(NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *src = pParams; + NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) + { + dest->hChannel = src->hChannel; + dest->property = src->property; + dest->value = src->value; + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS +return_t serialize_NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A(NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS_v1A_1A *dest = (void*)(buffer); + NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->hUserClient = src->hUserClient; + dest->hChannel = src->hChannel; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + + if ((src->bufferCount == 0) || (src->bufferCount > GR_MAX_RPC_CTX_BUFFER_COUNT)) + return FAILURE_T; + + for (i = 0; i < src->bufferCount; i++) { + dest->ctxBufferInfo[i].alignment = src->ctxBufferInfo[i].alignment; + dest->ctxBufferInfo[i].size = src->ctxBufferInfo[i].size; + dest->ctxBufferInfo[i].bufferHandle = src->ctxBufferInfo[i].bufferHandle; + dest->ctxBufferInfo[i].pageCount = src->ctxBufferInfo[i].pageCount; + dest->ctxBufferInfo[i].physAddr = src->ctxBufferInfo[i].physAddr; + dest->ctxBufferInfo[i].bufferType = src->ctxBufferInfo[i].bufferType; + dest->ctxBufferInfo[i].aperture = src->ctxBufferInfo[i].aperture; + dest->ctxBufferInfo[i].kind = src->ctxBufferInfo[i].kind; + dest->ctxBufferInfo[i].pageSize = src->ctxBufferInfo[i].pageSize; + dest->ctxBufferInfo[i].bIsContigous = src->ctxBufferInfo[i].bIsContigous; + dest->ctxBufferInfo[i].bGlobalBuffer = src->ctxBufferInfo[i].bGlobalBuffer; + dest->ctxBufferInfo[i].bLocalBuffer = src->ctxBufferInfo[i].bLocalBuffer; + dest->ctxBufferInfo[i].bDeviceDescendant = src->ctxBufferInfo[i].bDeviceDescendant; + portMemCopy(dest->ctxBufferInfo[i].uuid, sizeof(dest->ctxBufferInfo[i].uuid), + src->ctxBufferInfo[i].uuid, sizeof(src->ctxBufferInfo[i].uuid)); + } + + dest->bufferCount = src->bufferCount; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +#endif + +#ifdef BUILD_COMMON_RPCS +static +return_t serialize_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v1A_1C( + NV2080_CTRL_GPU_EVICT_CTX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GPU_EVICT_CTX_PARAMS *src = pParams; + NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 *dest = (void*)(buffer); + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS +#ifdef VMIOP_BUILD + dest->engineType = serialize_engineType(src->engineType); +#else + dest->engineType = src->engineType; +#endif + dest->hClient = src->hClient; + dest->ChID = src->ChID; + dest->hChanClient = src->hChanClient; + dest->hObject = src->hObject; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D(NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D *dest = (void*)(buffer); + NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *src = pParams; + NvU32 idx = 0; + + if (src && dest) + { + if (src->numQueries > NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D) { + return FAILURE_T; + } +#ifdef COPY_INPUT_PARAMETERS + dest->numQueries = src->numQueries; +#endif + for (idx = 0; idx < dest->numQueries; idx++) { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryType = src->queries[idx].queryType; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].status = src->queries[idx].status; +#endif + switch(dest->queries[idx].queryType) + { + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_GPC_COUNT: { +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.gpcCountData.gpcCount = src->queries[idx].queryData.gpcCountData.gpcCount; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_GPC_MAP: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.chipletGpcMapData.gpcId = src->queries[idx].queryData.chipletGpcMapData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.chipletGpcMapData.chipletGpcMap = src->queries[idx].queryData.chipletGpcMapData.chipletGpcMap; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_TPC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.tpcMaskData.gpcId = src->queries[idx].queryData.tpcMaskData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.tpcMaskData.tpcMask = src->queries[idx].queryData.tpcMaskData.tpcMask; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PPC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.ppcMaskData.gpcId = src->queries[idx].queryData.ppcMaskData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.ppcMaskData.ppcMask = src->queries[idx].queryData.ppcMaskData.ppcMask; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_GPC_MAP: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.partitionGpcMapData.swizzId = src->queries[idx].queryData.partitionGpcMapData.swizzId; + dest->queries[idx].queryData.partitionGpcMapData.gpcId = src->queries[idx].queryData.partitionGpcMapData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.partitionGpcMapData.chipletGpcMap = src->queries[idx].queryData.partitionGpcMapData.chipletGpcMap; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_CHIPLET_SYSPIPE_MASK: { +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.syspipeMaskData.chipletSyspipeMask = src->queries[idx].queryData.syspipeMaskData.chipletSyspipeMask; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_CHIPLET_SYSPIPE_IDS: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.partitionChipletSyspipeData.swizzId = src->queries[idx].queryData.partitionChipletSyspipeData.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount = src->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount; + + if (dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount > NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D) { + return FAILURE_T; + } + + for (idx = 0; idx < dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeIdCount; idx++) + dest->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeId[idx] = src->queries[idx].queryData.partitionChipletSyspipeData.physSyspipeId[idx]; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PROFILER_MON_GPC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.dmGpcMaskData.swizzId = src->queries[idx].queryData.dmGpcMaskData.swizzId; + dest->queries[idx].queryData.dmGpcMaskData.grIdx = src->queries[idx].queryData.dmGpcMaskData.grIdx; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.dmGpcMaskData.gpcEnMask = src->queries[idx].queryData.dmGpcMaskData.gpcEnMask; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_PARTITION_SYSPIPE_ID: { +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.partitionSyspipeIdData.syspipeId = src->queries[idx].queryData.partitionSyspipeIdData.syspipeId; +#endif + break; + } + case NV2080_CTRL_GRMGR_GR_FS_INFO_QUERY_ROP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryData.ropMaskData.gpcId = src->queries[idx].queryData.ropMaskData.gpcId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryData.ropMaskData.ropMask = src->queries[idx].queryData.ropMaskData.ropMask; +#endif + break; + } + default: + { + // Unknown query + return FAILURE_T; + } + } + } + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00(NV2080_CTRL_FB_GET_FS_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 *dest = (void*)(buffer); + NV2080_CTRL_FB_GET_FS_INFO_PARAMS *src = pParams; + NvU32 idx = 0; + + if (src && dest) + { + if (src->numQueries > NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + dest->numQueries = src->numQueries; +#endif + for (idx = 0; idx < dest->numQueries; idx++) { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryType = src->queries[idx].queryType; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].status = src->queries[idx].status; +#endif + switch(dest->queries[idx].queryType) + { + case NV2080_CTRL_FB_FS_INFO_INVALID_QUERY: { +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i = 0; + for (i = 0; i < NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D; i++) { + dest->queries[idx].queryParams.inv.data[i] = src->queries[idx].queryParams.inv.data[i]; + } +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_FBP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.fbp.swizzId = src->queries[idx].queryParams.fbp.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.fbp.fbpEnMask = src->queries[idx].queryParams.fbp.fbpEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_LTC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.ltc.fbpIndex = src->queries[idx].queryParams.ltc.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.ltc.ltcEnMask = src->queries[idx].queryParams.ltc.ltcEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_LTS_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.lts.fbpIndex = src->queries[idx].queryParams.lts.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.lts.ltsEnMask = src->queries[idx].queryParams.lts.ltsEnMask; +#endif + + break; + } + case NV2080_CTRL_FB_FS_INFO_FBPA_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.fbpa.fbpIndex = src->queries[idx].queryParams.fbpa.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.fbpa.fbpaEnMask = src->queries[idx].queryParams.fbpa.fbpaEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_ROP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.rop.fbpIndex = src->queries[idx].queryParams.rop.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.rop.ropEnMask = src->queries[idx].queryParams.rop.ropEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmLtc.fbpIndex = src->queries[idx].queryParams.dmLtc.fbpIndex; + dest->queries[idx].queryParams.dmLtc.swizzId = src->queries[idx].queryParams.dmLtc.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmLtc.ltcEnMask = src->queries[idx].queryParams.dmLtc.ltcEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTS_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmLts.fbpIndex = src->queries[idx].queryParams.dmLts.fbpIndex; + dest->queries[idx].queryParams.dmLts.swizzId = src->queries[idx].queryParams.dmLts.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmLts.ltsEnMask = src->queries[idx].queryParams.dmLts.ltsEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmFbpa.fbpIndex = src->queries[idx].queryParams.dmFbpa.fbpIndex; + dest->queries[idx].queryParams.dmFbpa.swizzId = src->queries[idx].queryParams.dmFbpa.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmFbpa.fbpaEnMask = src->queries[idx].queryParams.dmFbpa.fbpaEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_ROP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmRop.fbpIndex = src->queries[idx].queryParams.dmRop.fbpIndex; + dest->queries[idx].queryParams.dmRop.swizzId = src->queries[idx].queryParams.dmRop.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmRop.ropEnMask = src->queries[idx].queryParams.dmRop.ropEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_PROFILER_MON_FBPA_SUBP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.dmFbpaSubp.fbpIndex = src->queries[idx].queryParams.dmFbpaSubp.fbpIndex; + dest->queries[idx].queryParams.dmFbpaSubp.swizzId = src->queries[idx].queryParams.dmFbpaSubp.swizzId; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.dmFbpaSubp.fbpaSubpEnMask = src->queries[idx].queryParams.dmFbpaSubp.fbpaSubpEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_FBPA_SUBP_MASK: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.fbpaSubp.fbpIndex = src->queries[idx].queryParams.fbpaSubp.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.fbpaSubp.fbpaSubpEnMask = src->queries[idx].queryParams.fbpaSubp.fbpaSubpEnMask; +#endif + break; + } + case NV2080_CTRL_FB_FS_INFO_FBP_LOGICAL_MAP: { +#ifdef COPY_INPUT_PARAMETERS + dest->queries[idx].queryParams.fbpLogicalMap.fbpIndex = src->queries[idx].queryParams.fbpLogicalMap.fbpIndex; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->queries[idx].queryParams.fbpLogicalMap.fbpLogicalIndex = src->queries[idx].queryParams.fbpLogicalMap.fbpLogicalIndex; +#endif + break; + } + default: + { + // Unknown query + return FAILURE_T; + } + } + } + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +#ifdef VMIOP_BUILD + +static +return_t serialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06 *dest = (void*)(buffer); + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->flags = src->flags; +#endif + +#ifdef COPY_OUTPUT_PARAMETERS + { + NvU32 i; + + dest->bFatalPoisonError = src->bFatalPoisonError; + + for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06; i++) + { + dest->units[i].enabled = src->units[i].enabled; + dest->units[i].scrubComplete = src->units[i].scrubComplete; + dest->units[i].supported = src->units[i].supported; + dest->units[i].dbe.count = src->units[i].dbe.count; + dest->units[i].dbeNonResettable.count = src->units[i].dbeNonResettable.count; + dest->units[i].sbe.count = src->units[i].sbe.count; + dest->units[i].sbeNonResettable.count = src->units[i].sbeNonResettable.count; + } + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +#endif // VMIOP_BUILD + +return_t serialize_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E( + NVA06F_CTRL_STOP_CHANNEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVA06F_CTRL_STOP_CHANNEL_PARAMS *src = pParams; + NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E *dest = (void*)(buffer); + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->bImmediate = src->bImmediate; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t serialize_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F(NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F *dest = (void*)(buffer); + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *src = pParams; + + if (src && dest) + { + dest->pmaChannelIdx = src->pmaChannelIdx; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F(NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F *dest = (void*)(buffer); + NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *src = pParams; + + if (src && dest) + { + dest->hChannel = src->hChannel; + dest->samplingMode = src->samplingMode; + dest->grRouteInfo.flags = src->grRouteInfo.flags; + dest->grRouteInfo.route = src->grRouteInfo.route; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F(NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F *dest = (void*)(buffer); + NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *src = pParams; + + if (src && dest) + { + dest->bSetMaxFreq = src->bSetMaxFreq; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F(NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_OUTPUT_PARAMETERS + NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F *dest = (void*)(buffer); + NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *src = pParams; + NvU32 i = 0; + + if (src && dest) + { + dest->rm.clientActiveMask = src->rm.clientActiveMask; + dest->rm.bRegkeyLimitRatedTdp = src->rm.bRegkeyLimitRatedTdp; + dest->output = src->output; + + for (i = 0; i < NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F; i++) + { + dest->inputs[i] = src->inputs[i]; + } + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F(NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F *dest = (void*)(buffer); + NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *src = pParams; + + if (src && dest) + { + dest->client = src->client; + dest->input = src->input; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23( + NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 *dest = (void*)(buffer); + NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *src = pParams; + + if (src && dest) + { + dest->base = src->base; + dest->size = src->size; + dest->addressSpace = src->addressSpace; + dest->cacheAttrib = src->cacheAttrib; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t serialize_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02(NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 *dest = (void*)(buffer); + NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *src = pParams; + + if (src && dest) + { + dest->smID = src->smID; + dest->bSingleStep = src->bSingleStep; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t serialize_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 *dest = (void*)(buffer); + NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *src = pParams; + + if (src && dest) + { + dest->hChannelGroup = src->hChannelGroup; + dest->mode = src->mode; + dest->bEnableAllTpcs = src->bEnableAllTpcs; + dest->grRouteInfo.flags = src->grRouteInfo.flags; + dest->grRouteInfo.route = src->grRouteInfo.route; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t +serialize_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07( + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 *dest = + (void*)(buffer); + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *src = pParams; + + if (src && dest) + { + NvU32 i; + if (src->numValidEntries > + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_MAX_RUNQUEUES_v1E_07) + { + return FAILURE_T; + } + + dest->numValidEntries = src->numValidEntries; + + for (i = 0; i < src->numValidEntries; ++i) + { + dest->bar2Addr[i] = src->bar2Addr[i]; + dest->methodBufferMemdesc[i].base = + src->methodBufferMemdesc[i].base; + dest->methodBufferMemdesc[i].size = + src->methodBufferMemdesc[i].size; + dest->methodBufferMemdesc[i].alignment = + src->methodBufferMemdesc[i].alignment; + dest->methodBufferMemdesc[i].addressSpace = + src->methodBufferMemdesc[i].addressSpace; + dest->methodBufferMemdesc[i].cpuCacheAttrib = + src->methodBufferMemdesc[i].cpuCacheAttrib; + } + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t serialize_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08(NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 *dest = (void*)(buffer); + NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *src = pParams; + + if (src && dest) + { + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->bMembytesPollingRequired = src->bMembytesPollingRequired; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} + +return_t serialize_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06(NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_OUTPUT_PARAMETERS + NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 *dest = (void*)(buffer); + NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *src = pParams; + + if (src && dest) + { + dest->bMode = src->bMode; + } + else + return FAILURE_T; + +#endif + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS +return_t serialize_NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A( + NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS_v1E_0A *dest = (void*)(buffer); + NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->hChannel = src->hChannel; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->totalBufferSize = src->totalBufferSize; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_LEGACY_RPCS +return_t serialize_NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A( + NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS_v1E_0A *dest = (void*)(buffer); + NV2080_CTRL_FLCN_GET_CTX_BUFFER_INFO_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->hUserClient = src->hUserClient; + dest->hChannel = src->hChannel; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + dest->alignment = src->alignment; + dest->size = src->size; + dest->bufferHandle = src->bufferHandle; + dest->pageCount = src->pageCount; + dest->physAddr = src->physAddr; + dest->aperture = src->aperture; + dest->kind = src->kind; + dest->pageSize = src->pageSize; + dest->bIsContigous = src->bIsContigous; + dest->bDeviceDescendant = src->bDeviceDescendant; + portMemCopy(dest->uuid, sizeof(dest->uuid), + src->uuid, sizeof(src->uuid)); +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#ifdef BUILD_COMMON_RPCS +static +return_t serialize_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C( + NV00F8_CTRL_DESCRIBE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C *dest = (void*)(buffer); + NV00F8_CTRL_DESCRIBE_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->offset = src->offset; +#endif +#ifdef COPY_OUTPUT_PARAMETERS + NvU32 i; + dest->totalPfns = src->totalPfns; + for (i = 0; i pfnArray[i] = src->pfnArray[i]; + } + dest->numPfns = src->numPfns; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t serialize_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C( + NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C *dest = (void*)(buffer); + NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->totalSize = src->totalSize; + dest->freeSize = src->freeSize; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t serialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE_v24_05(NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 *dest = (void *) buffer; + NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *src = pParams; + NvU32 i; + + if (src && dest) + { + if (src->execPartCount > NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + dest->bQuery = src->bQuery; + dest->execPartCount = src->execPartCount; + + for (i = 0; i < dest->execPartCount; i++) { + dest->execPartInfo[i].gpcCount = src->execPartInfo[i].gpcCount; + + // Added in version v24_05 + dest->execPartInfo[i].gfxGpcCount = src->execPartInfo[i].gfxGpcCount; + + dest->execPartInfo[i].veidCount = src->execPartInfo[i].veidCount; + dest->execPartInfo[i].ceCount = src->execPartInfo[i].ceCount; + dest->execPartInfo[i].nvEncCount = src->execPartInfo[i].nvEncCount; + dest->execPartInfo[i].nvDecCount = src->execPartInfo[i].nvDecCount; + dest->execPartInfo[i].nvJpgCount = src->execPartInfo[i].nvJpgCount; + dest->execPartInfo[i].ofaCount = src->execPartInfo[i].ofaCount; + dest->execPartInfo[i].sharedEngFlag = src->execPartInfo[i].sharedEngFlag; + dest->execPartInfo[i].smCount = src->execPartInfo[i].smCount; + dest->execPartInfo[i].spanStart = src->execPartInfo[i].spanStart; + dest->execPartInfo[i].computeSize = src->execPartInfo[i].computeSize; + } +#endif + +#ifdef COPY_OUTPUT_PARAMETERS + for (i = 0; i < src->execPartCount; i++) { + dest->execPartId[i] = src->execPartId[i]; + dest->execPartInfo[i].computeSize = src->execPartInfo[i].computeSize; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t serialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE_v1F_0A(NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 *dest = (void *) buffer; + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + NvU32 i; + + if (src->execPartCount > NVC637_CTRL_MAX_EXEC_PARTITIONS_v18_05) { + return FAILURE_T; + } + + dest->execPartCount = src->execPartCount; + for (i = 0; i < dest->execPartCount; i++) { + dest->execPartId[i] = src->execPartId[i]; + } +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t serialize_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_v1F_0A(NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 *dest = (void *) buffer; + NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->workSubmitToken = src->workSubmitToken; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t serialize_NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_v1F_0A(NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + + NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 *dest = (void *) buffer; + NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_INPUT_PARAMETERS + dest->index = src->index; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +return_t serialize_NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_v1F_0D(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B *dest = (void *) buffer; + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->eccMask = src->eccMask; + dest->nvlinkMask = src->nvlinkMask; +#endif + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +#endif + +#ifdef BUILD_COMMON_RPCS +return_t serialize_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_v1F_05( + NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 *dest = (void*)(buffer); + NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *src = pParams; + + if (src && dest) + { + dest->bZbcSurfacesExist = src->bZbcSurfacesExist; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} +#endif + +#ifdef BUILD_COMMON_RPCS +return_t serialize_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C(NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C *dest = (void*)(buffer); + NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *src = pParams; + + if (src && dest) + { + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->pmaBufferVA = src->pmaBufferVA; + dest->pmaBufferSize = src->pmaBufferSize; + dest->membytesVA = src->membytesVA; + dest->hwpmIBPA = src->hwpmIBPA; + dest->hwpmIBAperture = src->hwpmIBAperture; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +#ifdef BUILD_COMMON_RPCS +return_t serialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 *dest = (void*)(buffer); + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *src = pParams; + + if (src && dest) + { + dest->connectionType = src->connectionType; + dest->peerId = src->peerId; + dest->bSpaAccessOnly = src->bSpaAccessOnly; + dest->bUseUuid = src->bUseUuid; + + portMemCopy(dest->remoteGpuUuid, + VM_UUID_SIZE_v21_02, + src->remoteGpuUuid, + VM_UUID_SIZE_v21_02); + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} +#endif + +#ifdef BUILD_COMMON_RPCS +return_t serialize_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 *dest = (void*)(buffer); + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *src = pParams; + + if (src && dest) + { + dest->connectionType = src->connectionType; + dest->peerId = src->peerId; + dest->bUseUuid = src->bUseUuid; + + portMemCopy(dest->remoteGpuUuid, + VM_UUID_SIZE_v21_02, + src->remoteGpuUuid, + VM_UUID_SIZE_v21_02); + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +#ifndef UMED_BUILD +return_t serialize_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11(NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 *dest = (void*)(buffer); + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *src = pParams; + + if (src && dest) + { + NvU32 i; + if (src->gpuInfoListSize > NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11) { + return FAILURE_T; + } + +#ifdef COPY_INPUT_PARAMETERS + dest->gpuInfoListSize = src->gpuInfoListSize; +#endif + + for (i = 0; i < NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11; i++) { +#ifdef COPY_INPUT_PARAMETERS + dest->gpuInfoList[i].index = src->gpuInfoList[i].index; +#endif + dest->gpuInfoList[i].data = src->gpuInfoList[i].data; + } + } + else + return FAILURE_T; + return SUCCESS_T; +} +#endif // UMED_BUILD + +return_t serialize_NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK_v21_05( + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ +#ifdef COPY_INPUT_PARAMETERS + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 *dest = (void*)(buffer); + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *src = pParams; + + if (src && dest) + { + dest->imbPhysAddr = src->imbPhysAddr; + dest->addrSpace = src->addrSpace; + dest->flaAction = src->flaAction; + } + else + return FAILURE_T; +#endif + return SUCCESS_T; +} + +return_t serialize_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 *dest = (void*)(buffer); + NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *src = pParams; + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->numCredits = src->numCredits; +#endif + } + else + return FAILURE_T; + return SUCCESS_T; +} + +return_t serialize_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 *dest = (void*)(buffer); + NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *src = pParams; + if (src && dest) + { + NvU32 i; + if (src->numEntries > NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08) { + return FAILURE_T; + } +#ifdef COPY_OUTPUT_PARAMETERS + dest->statusInfo.status = src->statusInfo.status; + dest->statusInfo.entryIndex = src->statusInfo.entryIndex; + for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { + dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; + } +#endif +#ifdef COPY_INPUT_PARAMETERS + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->numEntries = src->numEntries; + + for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { + dest->creditInfo[i].chipletType = src->creditInfo[i].chipletType; + dest->creditInfo[i].chipletIndex = src->creditInfo[i].chipletIndex; + dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; + } +#endif + } + else + return FAILURE_T; + return SUCCESS_T; +} + +return_t serialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 *dest = (void*)(buffer); + NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *src = pParams; + + if (src && dest) + { +#ifdef COPY_OUTPUT_PARAMETERS + dest->statusInfo.status = src->statusInfo.status; + dest->statusInfo.entryIndex = src->statusInfo.entryIndex; +#endif +#ifdef COPY_INPUT_PARAMETERS + NvU32 i; + dest->pmaChannelIdx = src->pmaChannelIdx; + dest->numEntries = src->numEntries; + + if (src->numEntries > NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08) { + return FAILURE_T; + } + + for (i = 0; i < NVB0CC_MAX_CREDIT_INFO_ENTRIES_v21_08; i++) { + dest->creditInfo[i].chipletType = src->creditInfo[i].chipletType; + dest->creditInfo[i].chipletIndex = src->creditInfo[i].chipletIndex; + dest->creditInfo[i].numCredits = src->creditInfo[i].numCredits; + } +#endif + } + else + return FAILURE_T; + return SUCCESS_T; +} + +#ifndef UMED_BUILD +return_t serialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *src = pParams; + NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 *dest = (void*)(buffer); + + if (src && dest) { + dest->value = src->value; + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif + +#endif +#endif +#endif //GSP_FW_BUILD + +#if defined(BUILD_COMMON_RPCS) +static +return_t serialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FB_GET_INFO_V2_PARAMS *src = pParams; + NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A *dest = (void*)(buffer); + + if (src && dest) + { + NvU32 i; + + if ((src->fbInfoListSize == 0) || + (src->fbInfoListSize > NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A)) { + return FAILURE_T; + } + + dest->fbInfoListSize = src->fbInfoListSize; + + for (i = 0; i < src->fbInfoListSize; i++) { + dest->fbInfoList[i].index = src->fbInfoList[i].index; + dest->fbInfoList[i].data = src->fbInfoList[i].data; + } + } + else + return FAILURE_T; + + return SUCCESS_T; +} + +static +return_t deserialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A *src = (void*)(buffer); + NV2080_CTRL_FB_GET_INFO_V2_PARAMS *dest = pParams; + + if (src && dest) + { + NvU32 i; + + if ((src->fbInfoListSize == 0) || + (src->fbInfoListSize > NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A)) { + return FAILURE_T; + } + + dest->fbInfoListSize = src->fbInfoListSize; + + for (i = 0; i < src->fbInfoListSize; i++) { + dest->fbInfoList[i].index = src->fbInfoList[i].index; + dest->fbInfoList[i].data = src->fbInfoList[i].data; + } + } + else + return FAILURE_T; + + return SUCCESS_T; +} +#endif // defined(BUILD_COMMON_RPCS) + +#ifndef GSP_FW_BUILD +#ifdef BUILD_COMMON_RPCS +#ifndef RESMAN_BUILD +/** + * Copy static info from `buffer` to local VGPU_STATIC_INFO `pVSI` or vice versa. + * This routine is built into host (VMIOP) and guest (RM). + * VGPU host populates its local VGPU_STATIC_INFO struct and uses this function to serialize + * struct members into `buffer`. + * VGPU guest calls GET_CONSOLIDATED_STATIC_INFO RPC to receive `buffer`, and calls this routine + * to deserialize struct members from `buffer` into guest's VGPU_STATIC_INFO. + * + * Serialization and deserialization happens according to negotiated RPC protocol version. + * Struct members in VGPU_STATIC_INFO must not be reordered. Any additions to + * VGPU_STATIC_INFO should be done at the end of the struct, and handled in this function by + * checking for protocol version. + */ +static NV_STATUS consolidated_static_info_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy, + VGPU_STATIC_INFO *pVSI, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset, + NvBool bAlignOffset) +{ + NV_STATUS status = NVOS_STATUS_SUCCESS; + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CLK_GET_DOMAINS_PARAMS)(pObjRpcStructureCopy, + &pVSI->clkDomains, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CLK_GET_PUBLIC_DOMAINS_PARAMS)(pObjRpcStructureCopy, + &pVSI->clkPublicDomains, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS)(pObjRpcStructureCopy, + NULL, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_PERF_GET_TABLE_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->perfTableInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(vgpuPstateInfo)(pObjRpcStructureCopy, + &pVSI->pstateInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_DISPLAYLESS_INFO)(pObjRpcStructureCopy, + pVSI, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_STATIC_INFO)(pObjRpcStructureCopy, + pVSI, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS)(pObjRpcStructureCopy, + &pVSI->mcEngineNotificationIntrVectors, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_STATIC_INFO2)(pObjRpcStructureCopy, + pVSI, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CLK_GET_PUBLIC_DOMAIN_INFO_V2_PARAMS)(pObjRpcStructureCopy, + &pVSI->clkPublicDomainInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->grZcullInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_STATIC_PROPERTIES)(pObjRpcStructureCopy, + &pVSI->vgpuStaticProperties, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_FIFO_GET_DEVICE_INFO_TABLE)(pObjRpcStructureCopy, + &pVSI->fifoDeviceInfoTable, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES)(pObjRpcStructureCopy, + &pVSI->fbDynamicBlacklistedPages, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_BSP_GET_CAPS)(pObjRpcStructureCopy, + &pVSI->vgpuBspCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_PERF_VPSTATES_INFO)(pObjRpcStructureCopy, + &pVSI->perfVpstatesInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x1A0D0000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_GET_LATENCY_BUFFER_SIZE)(pObjRpcStructureCopy, + &pVSI->fifoLatencyBufferSize, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_CE_GET_CAPS_V2)(pObjRpcStructureCopy, + &pVSI->ceCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS)(pObjRpcStructureCopy, + &pVSI->nvlinkCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_FB_GET_LTC_INFO_FOR_FBP)(pObjRpcStructureCopy, + &pVSI->fbLtcInfoForFbp, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x1A0F0000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS)(pObjRpcStructureCopy, + &pVSI->busGetInfoV2, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_FLA_GET_RANGE_PARAMS)(pObjRpcStructureCopy, + &pVSI->flaInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x1A190000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS)(pObjRpcStructureCopy, + &pVSI->vgpuConfig, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x1A1F0000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS)(pObjRpcStructureCopy, + &pVSI->grSmIssueRateModifier, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x1E090000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS)(pObjRpcStructureCopy, + &pVSI->mcStaticIntrTable, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x1F080000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS)(pObjRpcStructureCopy, + &pVSI->pcieSupportedGpuAtomics, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x210A0000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS)(pObjRpcStructureCopy, + &pVSI->ceGetAllCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x22010000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->c2cInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x23020000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_PERF_PSTATES_INFO)(pObjRpcStructureCopy, + &pVSI->perfpstatesInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x25000000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS)(pObjRpcStructureCopy, + &pVSI->nvencCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x25010000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->constructedFalconInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x25030000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_P2P_CAPABILITY_PARAMS)(pObjRpcStructureCopy, + &pVSI->p2pCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x25050000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS)(pObjRpcStructureCopy, + &pVSI->deviceInfoTable, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x25060000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS)(pObjRpcStructureCopy, + &pVSI->memsysStaticConfig, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x250B0000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS)(pObjRpcStructureCopy, + &pVSI->busGetPcieReqAtomicsCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + +end: + return status; +} +#endif // RESMAN_BUILD + +static NV_STATUS static_data_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy, + VGPU_STATIC_INFO *pVSI, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset, + NvBool bAlignOffset) +{ + NV_STATUS status = NVOS_STATUS_SUCCESS; + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS)(pObjRpcStructureCopy, + (NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *)&pVSI->execPartitionInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_STATIC_DATA)(pObjRpcStructureCopy, + pVSI, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS)(pObjRpcStructureCopy, + &pVSI->eccStatus, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->vgxSystemInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->gidInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->SKUInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->fbRegionInfoParams, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS)(pObjRpcStructureCopy, + &pVSI->ciProfiles, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS)(pObjRpcStructureCopy, + &pVSI->zbcTableSizes[0], + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS)(pObjRpcStructureCopy, + NULL, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS)(pObjRpcStructureCopy, + &pVSI->mcEngineNotificationIntrVectors, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->grZcullInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_STATIC_PROPERTIES)(pObjRpcStructureCopy, + &pVSI->vgpuStaticProperties, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_FIFO_GET_DEVICE_INFO_TABLE)(pObjRpcStructureCopy, + &pVSI->fifoDeviceInfoTable, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES)(pObjRpcStructureCopy, + &pVSI->fbDynamicBlacklistedPages, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_BSP_GET_CAPS)(pObjRpcStructureCopy, + &pVSI->vgpuBspCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_GET_LATENCY_BUFFER_SIZE)(pObjRpcStructureCopy, + &pVSI->fifoLatencyBufferSize, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_CE_GET_CAPS_V2)(pObjRpcStructureCopy, + &pVSI->ceCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS)(pObjRpcStructureCopy, + &pVSI->nvlinkCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_FB_GET_LTC_INFO_FOR_FBP)(pObjRpcStructureCopy, + &pVSI->fbLtcInfoForFbp, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS)(pObjRpcStructureCopy, + &pVSI->busGetInfoV2, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_FLA_GET_RANGE_PARAMS)(pObjRpcStructureCopy, + &pVSI->flaInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS)(pObjRpcStructureCopy, + &pVSI->vgpuConfig, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS)(pObjRpcStructureCopy, + &pVSI->grSmIssueRateModifier, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS)(pObjRpcStructureCopy, + &pVSI->mcStaticIntrTable, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS)(pObjRpcStructureCopy, + &pVSI->pcieSupportedGpuAtomics, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS)(pObjRpcStructureCopy, + &pVSI->ceGetAllCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->c2cInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS)(pObjRpcStructureCopy, + &pVSI->nvencCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->constructedFalconInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(VGPU_P2P_CAPABILITY_PARAMS)(pObjRpcStructureCopy, + &pVSI->p2pCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS)(pObjRpcStructureCopy, + &pVSI->deviceInfoTable, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS)(pObjRpcStructureCopy, + &pVSI->memsysStaticConfig, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS)(pObjRpcStructureCopy, + &pVSI->busGetPcieReqAtomicsCaps, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(GPU_PARTITION_INFO)(pObjRpcStructureCopy, + &pVSI->gpuPartitionInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } + + if (getIpVersion() < 0x25130000) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS)(pObjRpcStructureCopy, + &pVSI->masterGetVfErrCntIntMsk, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + return status; + } +end: + return status; +} + +static NV_STATUS consolidated_gr_static_info_copy(OBJRPCSTRUCTURECOPY *pObjRpcStructureCopy, + VGPU_STATIC_INFO *pVSI, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset, + NvBool bAlignOffset) +{ + NV_STATUS status = NVOS_STATUS_SUCCESS; + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->grInfoParams, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS)(pObjRpcStructureCopy, + &pVSI->globalSmOrder, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->ropInfoParams, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS)(pObjRpcStructureCopy, + &pVSI->ppcMaskParams, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->ctxBuffInfo, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS)(pObjRpcStructureCopy, + &pVSI->smIssueRateModifier, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS)(pObjRpcStructureCopy, + &pVSI->floorsweepMaskParams, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS)(pObjRpcStructureCopy, + &pVSI->zcullInfoParams, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS)(pObjRpcStructureCopy, + &pVSI->fecsRecordSize, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS)(pObjRpcStructureCopy, + &pVSI->fecsTraceDefines, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + + NV_CHECK_AND_ALIGN_OFFSET(*offset, bAlignOffset) + status = serialize_deserialize(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS)(pObjRpcStructureCopy, + &pVSI->pdbTableParams, + buffer, + bufferSize, + offset); + if (status != NVOS_STATUS_SUCCESS) { + goto end; + } + +end: + return status; +} +#endif +#endif + +#if defined(CROSS_BRANCH_CONVERT) + +typedef struct { + NvU32 outType; +} GUEST_HOST_MAPPING; + +/* + * guest_to_host_enginetype_v1A_00 is used to convert engine type from r460 to + * r470. refer sdk/nvidia/inc/class/cl2080.h for definition. + */ +const GUEST_HOST_MAPPING guest_to_host_enginetype_v1A_00[] = +{ +// Out Engine Type In Engine Type + { NV2080_ENGINE_TYPE_NULL }, // 0x0 + { NV2080_ENGINE_TYPE_GR0 }, // 0x1 + { NV2080_ENGINE_TYPE_GR1 }, // 0x2 + { NV2080_ENGINE_TYPE_GR2 }, // 0x3 + { NV2080_ENGINE_TYPE_GR3 }, // 0x4 + { NV2080_ENGINE_TYPE_GR4 }, // 0x5 + { NV2080_ENGINE_TYPE_GR5 }, // 0x6 + { NV2080_ENGINE_TYPE_GR6 }, // 0x7 + { NV2080_ENGINE_TYPE_GR7 }, // 0x8 + { NV2080_ENGINE_TYPE_COPY0 }, // 0x9 + { NV2080_ENGINE_TYPE_COPY1 }, // 0xa + { NV2080_ENGINE_TYPE_COPY2 }, // 0xb + { NV2080_ENGINE_TYPE_COPY3 }, // 0xc + { NV2080_ENGINE_TYPE_COPY4 }, // 0xd + { NV2080_ENGINE_TYPE_COPY5 }, // 0xe + { NV2080_ENGINE_TYPE_COPY6 }, // 0xf + { NV2080_ENGINE_TYPE_COPY7 }, // 0x10 + { NV2080_ENGINE_TYPE_COPY8 }, // 0x11 + { NV2080_ENGINE_TYPE_COPY9 }, // 0x12 + { NV2080_ENGINE_TYPE_NVDEC0 }, // 0x13 + { NV2080_ENGINE_TYPE_NVDEC1 }, // 0x14 + { NV2080_ENGINE_TYPE_NVDEC2 }, // 0x15 + { NV2080_ENGINE_TYPE_NVDEC3 }, // 0x16 + { NV2080_ENGINE_TYPE_NVDEC4 }, // 0x17 + { NV2080_ENGINE_TYPE_NVENC0 }, // 0x18 + { NV2080_ENGINE_TYPE_NVENC1 }, // 0x19 + { NV2080_ENGINE_TYPE_NVENC2 }, // 0x1a + { NV2080_ENGINE_TYPE_VP }, // 0x1b + { NV2080_ENGINE_TYPE_ME }, // 0x1c + { NV2080_ENGINE_TYPE_PPP }, // 0x1d + { NV2080_ENGINE_TYPE_MPEG }, // 0x1e + { NV2080_ENGINE_TYPE_SW }, // 0x1f + { NV2080_ENGINE_TYPE_CIPHER }, // 0x20 + { NV2080_ENGINE_TYPE_VIC }, // 0x21 + { NV2080_ENGINE_TYPE_MP }, // 0x22 + { NV2080_ENGINE_TYPE_SEC2 }, // 0x23 + { NV2080_ENGINE_TYPE_HOST }, // 0x24 + { NV2080_ENGINE_TYPE_DPU }, // 0x25 + { NV2080_ENGINE_TYPE_PMU }, // 0x26 + { NV2080_ENGINE_TYPE_FBFLCN }, // 0x27 + { NV2080_ENGINE_TYPE_NVJPG }, // 0x28 + { NV2080_ENGINE_TYPE_OFA0 }, // 0x29 + { NV2080_ENGINE_TYPE_LAST_v1A_00 }, // 0x2a +}; + +// Convert a guest engineType to a host engineType. +NvU32 deserialize_engineType(NvU32 inEngineType) +{ + + if (vgx_internal_version_curr.major_number >= 0x1B) { + return inEngineType; + } + if (inEngineType >= 0x2a) { + return NV2080_ENGINE_TYPE_NULL; + } + return guest_to_host_enginetype_v1A_00[inEngineType].outType; +} + +/* + * host_to_guest_enginetype_v1A_00 is used to convert engine type from r470 to + * r460. refer sdk/nvidia/inc/class/cl2080.h for definition. + * unsupported/invalid engines are returned with NV2080_ENGINE_TYPE_NULL (this + * is considered invalid in RM) + */ +const GUEST_HOST_MAPPING host_to_guest_enginetype_v1A_00[] = +{ +// Out Engine Type In Engine Type + { 0x0 }, // NV2080_ENGINE_TYPE_NULL + { 0x1 }, // NV2080_ENGINE_TYPE_GR0 + { 0x2 }, // NV2080_ENGINE_TYPE_GR1 + { 0x3 }, // NV2080_ENGINE_TYPE_GR2 + { 0x4 }, // NV2080_ENGINE_TYPE_GR3 + { 0x5 }, // NV2080_ENGINE_TYPE_GR4 + { 0x6 }, // NV2080_ENGINE_TYPE_GR5 + { 0x7 }, // NV2080_ENGINE_TYPE_GR6 + { 0x8 }, // NV2080_ENGINE_TYPE_GR7 + { 0x9 }, // NV2080_ENGINE_TYPE_COPY0 + { 0xa }, // NV2080_ENGINE_TYPE_COPY1 + { 0xb }, // NV2080_ENGINE_TYPE_COPY2 + { 0xc }, // NV2080_ENGINE_TYPE_COPY3 + { 0xd }, // NV2080_ENGINE_TYPE_COPY4 + { 0xe }, // NV2080_ENGINE_TYPE_COPY5 + { 0xf }, // NV2080_ENGINE_TYPE_COPY6 + { 0x10 }, // NV2080_ENGINE_TYPE_COPY7 + { 0x11 }, // NV2080_ENGINE_TYPE_COPY8 + { 0x12 }, // NV2080_ENGINE_TYPE_COPY9 + { 0x13 }, // NV2080_ENGINE_TYPE_NVDEC0 + { 0x14 }, // NV2080_ENGINE_TYPE_NVDEC1 + { 0x15 }, // NV2080_ENGINE_TYPE_NVDEC2 + { 0x16 }, // NV2080_ENGINE_TYPE_NVDEC3 + { 0x17 }, // NV2080_ENGINE_TYPE_NVDEC4 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVDEC5 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVDEC6 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVDEC7 + { 0x18 }, // NV2080_ENGINE_TYPE_NVENC0 + { 0x19 }, // NV2080_ENGINE_TYPE_NVENC1 + { 0x1a }, // NV2080_ENGINE_TYPE_NVENC2 + { 0x1b }, // NV2080_ENGINE_TYPE_VP + { 0x1c }, // NV2080_ENGINE_TYPE_ME + { 0x1d }, // NV2080_ENGINE_TYPE_PPP + { 0x1e }, // NV2080_ENGINE_TYPE_MPEG + { 0x1f }, // NV2080_ENGINE_TYPE_SW + { 0x20 }, // NV2080_ENGINE_TYPE_CIPHER + { 0x21 }, // NV2080_ENGINE_TYPE_VIC + { 0x22 }, // NV2080_ENGINE_TYPE_MP + { 0x23 }, // NV2080_ENGINE_TYPE_SEC2 + { 0x24 }, // NV2080_ENGINE_TYPE_HOST + { 0x25 }, // NV2080_ENGINE_TYPE_DPU + { 0x26 }, // NV2080_ENGINE_TYPE_PMU + { 0x27 }, // NV2080_ENGINE_TYPE_FBFLCN + { 0x28 }, // NV2080_ENGINE_TYPE_NVJPEG0 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG1 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG2 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG3 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG4 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG5 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG6 + { NV2080_ENGINE_TYPE_NULL }, // NV2080_ENGINE_TYPE_NVJPEG7 + { 0x29 }, // NV2080_ENGINE_TYPE_OFA0 + { 0x2a }, // NV2080_ENGINE_TYPE_LAST +}; + +// Convert a host engineType to a guest engineType. +NvU32 serialize_engineType(NvU32 inEngineType) +{ + + if (vgx_internal_version_curr.major_number >= 0x1B) { + return inEngineType; + } + if (inEngineType >= 0x34) { + return NV2080_ENGINE_TYPE_NULL; + } + return host_to_guest_enginetype_v1A_00[inEngineType].outType; +} + +// Convert a host engineList to a guest engineList. +NvU64 searilize_engineCap(NvU64 inEngineCap) +{ + + if (vgx_internal_version_curr.major_number >= 0x1B) { + return inEngineCap; + } + NvU64 outEngineCap= 0, i = 0; + FOR_EACH_INDEX_IN_MASK(64, i, inEngineCap) + { + outEngineCap = outEngineCap | NVBIT64(serialize_engineType(i)); + } FOR_EACH_INDEX_IN_MASK_END; + return outEngineCap; +} + +// Convert a host notifier index to a guest notifier index. +NvU32 serialize_notifier(NvU32 inNotifier) +{ + if (vgx_internal_version_curr.major_number > 0x21) { + return inNotifier; + } + + if (vgx_internal_version_curr.major_number == 0x21 && + (REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R525)) { + return NV2080_NOTIFIERS_MAXCOUNT_R525; + } + + if (vgx_internal_version_curr.major_number == 0x1C && + (REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R470)) { + return NV2080_NOTIFIERS_MAXCOUNT_R470; + } + + return inNotifier; +} + +// Convert a guest notifier index to a host notifier index. +NvU32 deserialize_notifier(NvU32 inNotifier) +{ + if (vgx_internal_version_curr.major_number > 0x21) { + return inNotifier; + } + + if (vgx_internal_version_curr.major_number == 0x21 && + (REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R525)) { + return NV2080_NOTIFIERS_MAXCOUNT; + } + + if (vgx_internal_version_curr.major_number == 0x1C && + (REF_VAL(NV0005_NOTIFY_INDEX_INDEX, inNotifier) >= NV2080_NOTIFIERS_MAXCOUNT_R470)) { + return NV2080_NOTIFIERS_MAXCOUNT; + } + + return inNotifier; +} + +/* + * rcmask table is used to convert ROBUST_CHANNEL_* macros from r470 to r460. + * eg, ROBUST_CHANNEL_COPY0_ENGINE is defined as 22 in r470 and 19 in r460. + */ +const GUEST_HOST_MAPPING host_to_guest_rcmask_v1A_00[] = +{ +// Out rcmask // In rcmask + { 0 }, // 0 + { 1 }, // 1 + { 2 }, // 2 + { 3 }, // 3 + { 4 }, // 4 + { 5 }, // 5 + { 6 }, // 6 + { 7 }, // 7 + { 8 }, // 8 + { 9 }, // 9 + { 10 }, // 10 + { 11 }, // 11 + { 12 }, // 12 + { 13 }, // 13 + { 14 }, // 14 + { 15 }, // 15 + { 16 }, // 16 + { 17 }, // 17 + { 18 }, // 18 + { 0 }, // 19 + { 0 }, // 20 + { 0 }, // 21 + { 19 }, // 22 + { 20 }, // 23 + { 21 }, // 24 + { 22 }, // 25 + { 23 }, // 26 + { 24 }, // 27 + { 25 }, // 28 + { 26 }, // 29 + { 27 }, // 30 + { 28 }, // 31 + { 29 }, // 32 + { 0 }, // 33 + { 0 }, // 34 + { 0 }, // 35 + { 0 }, // 36 + { 0 }, // 37 + { 0 }, // 38 + { 0 }, // 39 + { 30 }, // 40 + { 31 }, // 41 + { 32 }, // 42 + { 33 }, // 43 + { 34 }, // 44 + { 35 }, // 45 + { 36 }, // 46 + { 37 }, // 47 + { 38 }, // 48 + { 39 }, // 49 + +}; + +// Convert a host rcmask to a guest rcmask. +NvU32 serialize_rcmask(NvU32 inType) +{ + + if (vgx_internal_version_curr.major_number >= 0x1B) { + return inType; + } + if (inType > 49) { + return 0; + } + return host_to_guest_rcmask_v1A_00[inType].outType; +} + +typedef struct { + NvU32 inType; + NvU32 outType; +} GUEST_HOST_MAPPING_TUPLE; + +/* + * mcbit table is used to convert MC_ENGINE_IDX_* macros from r470 to r460. + * Please refer engine_idx.h for definition. + * eg, MC_ENGINE_IDX_BSP is defined as 56 in r470 and 49 in r460. + */ +const GUEST_HOST_MAPPING_TUPLE host_to_guest_mcbit_v1A_00[] = +{ +// Host mcbit Guest mcbit + { 0, 0 }, + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + { 4, 4 }, + { 5, 5 }, + { 6, 6 }, + { 7, 7 }, + { 8, 8 }, + { 9, 9 }, + { 10, 10 }, + { 11, 11 }, + { 12, 12 }, + { 13, 13 }, + { 14, 14 }, + { 15, 15 }, + { 16, 16 }, + { 17, 17 }, + { 18, 18 }, + { 19, 19 }, + { 20, 20 }, + { 21, 21 }, + { 22, 22 }, + { 23, 23 }, + { 24, 24 }, + { 25, 25 }, + { 26, 26 }, + { 27, 27 }, + { 28, 28 }, + { 29, 30 }, + { 30, 31 }, + { 31, 32 }, + { 32, 0 }, + { 33, 0 }, + { 34, 34 }, + { 35, 35 }, + { 36, 36 }, + { 37, 37 }, + { 38, 38 }, + { 39, 0 }, + { 40, 40 }, + { 41, 41 }, + { 42, 42 }, + { 43, 0 }, + { 44, 0 }, + { 45, 0 }, + { 46, 0 }, + { 47, 0 }, + { 48, 0 }, + { 49, 0 }, + { 50, 43 }, + { 51, 44 }, + { 52, 45 }, + { 53, 46 }, + { 54, 47 }, + { 55, 48 }, + { 56, 49 }, + { 57, 50 }, + { 58, 51 }, + { 59, 52 }, + { 60, 53 }, + { 61, 0 }, + { 62, 0 }, + { 63, 0 }, + { 64, 54 }, + { 65, 55 }, + { 66, 56 }, + { 67, 57 }, + { 68, 58 }, + { 69, 59 }, + { 70, 60 }, + { 71, 61 }, + { 72, 62 }, + { 73, 63 }, + { 74, 64 }, + { 75, 65 }, + { 76, 66 }, + { 77, 67 }, + { 78, 68 }, + { 79, 69 }, + { 80, 70 }, + { 81, 71 }, + { 82, 72 }, + { 146, 104 }, + { 147, 105 }, + { 148, 106 }, + { 149, 107 }, + { 150, 108 }, + { 151, 109 }, + { 152, 110 }, + { 153, 111 }, + { 154, 112 }, + { 155, 113 }, +}; + +NvU32 get_index(NvU32 inType) { + NvU32 index = 0, l = 0; + NvU32 r = (sizeof(host_to_guest_mcbit_v1A_00) / (sizeof(NvU32) * 2)) - 1; + + do { + index = (l + r) / 2; + if (inType == host_to_guest_mcbit_v1A_00[index].inType) { + break; + } + if (r <= l) { + index = 0; + break; + } + if (inType > host_to_guest_mcbit_v1A_00[index].inType) { + l = index + 1; + continue; + } + if (inType < host_to_guest_mcbit_v1A_00[index].inType) { + r = index - 1; + continue; + } + } while(1); + + return index; +} + +// Convert a host rcmask to a guest rcmask. +NvU32 serialize_mcbit(NvU32 inType) +{ + + if (vgx_internal_version_curr.major_number >= 0x1B) { + return inType; + } + if (inType > 155) { + return 0; + } + return host_to_guest_mcbit_v1A_00[get_index(inType)].outType; +} + +#endif +#undef COPY_INPUT_PARAMETERS +#undef COPY_OUTPUT_PARAMETERS diff --git a/src/nvidia/kernel/inc/vgpu/rpc.h b/src/nvidia/kernel/inc/vgpu/rpc.h index 142796e5b5..57c0546b0f 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc.h +++ b/src/nvidia/kernel/inc/vgpu/rpc.h @@ -34,7 +34,7 @@ #define __vgpu_dev_nv_rpc_h__ #include "class/cl84a0.h" -#include "rpc_headers.h" +#include "vgpu/rpc_headers.h" #include "gpu/dce_client/dce_client.h" #include "objrpc.h" #include "rpc_vgpu.h" @@ -45,59 +45,6 @@ typedef struct ContextDma ContextDma; -#define NV_RM_STUB_RPC 0 - -#if NV_RM_STUB_RPC - -static inline void NV_RM_RPC_ALLOC_SHARE_DEVICE(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_ALLOC_MEMORY(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_ALLOC_CHANNEL(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_ALLOC_OBJECT(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_MAP_MEMORY_DMA(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_UNMAP_MEMORY_DMA(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_ALLOC_SUBDEVICE(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_DUP_OBJECT(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_IDLE_CHANNELS(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_ALLOC_EVENT(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_CONTROL(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_ALLOC(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_FREE(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_SET_GUEST_SYSTEM_INFO(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_PERF_GET_PSTATE_INFO(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_PERF_GET_VIRTUAL_PSTATE_INFO(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_PERF_GET_LEVEL_INFO(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_UNLOADING_GUEST_DRIVER(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_GPU_EXEC_REG_OPS(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_GET_STATIC_INFO(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_REGISTER_VIRTUAL_EVENT_BUFFER(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_UPDATE_BAR_PDE(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_SET_PAGE_DIRECTORY(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_UNSET_PAGE_DIRECTORY(OBJGPU *pGpu, ...) { return; } - -static inline void NV_RM_RPC_GET_GSP_STATIC_INFO(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_GSP_SET_SYSTEM_INFO(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_SET_REGISTRY(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_SUBDEV_EVENT_SET_NOTIFICATION(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_DUMP_PROTOBUF_COMPONENT(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_GSP_MSG_TIMING(OBJGPU *pGpu, ...) { return; } - -static inline void NV_RM_RPC_VGPU_PF_REG_READ32(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_INVALIDATE_TLB(OBJGPU *pGpu, ...) { return; } - -// RPC free stubs -static inline void NV_RM_RPC_SIM_FREE_INFRA(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_FREE(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_FREE_ON_ERROR(OBJGPU *pGpu, ...) { return; } - -// Simulation stubs -static inline void NV_RM_RPC_SIM_LOAD_ESCAPE_FUNCTIONS(OBJOS *pOS, ...) { return; } -static inline void NV_RM_RPC_SIM_UPDATE_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_SIM_DELETE_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } -static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { return; } - -#else // NV_RM_STUB_RPC - #define NV_RM_RPC_ALLOC_SHARE_DEVICE_FWCLIENT(pGpu, hclient, hdevice, hclientshare, htargetclient, htargetdevice, hclass, \ allocflags, vasize, vamode, bFirstDevice, status) \ do \ @@ -172,7 +119,7 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r && (!(IS_VIRTUAL_WITH_SRIOV(pGpu) && \ !gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && \ !NV_IS_MODS))) { \ - if (IS_GSP_CLIENT(pGpu) && IsT234DorBetter(pGpu)) \ + if (IS_DCE_CLIENT(pGpu)) \ { \ RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ NV_MEMORY_LIST_ALLOCATION_PARAMS listAllocParams = {0}; \ @@ -254,14 +201,23 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - NV_RM_RPC_ALLOC_SHARE_DEVICE_FWCLIENT(pGpu, hclient, hdevice, hclientshare, htargetclient, htargetdevice, hclass, \ - allocflags, vasize, vamode, bFirstDevice, status); \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + NV_RM_RPC_ALLOC_SHARE_DEVICE_FWCLIENT(pGpu, hclient, hdevice, hclientshare, htargetclient, htargetdevice, hclass, \ + allocflags, vasize, vamode, bFirstDevice, status); \ + } \ + else \ + status = rpcAllocShareDevice_HAL(pGpu, pRpc, hclient, hdevice, hclientshare, \ + htargetclient, htargetdevice, hclass, \ + allocflags, vasize, vamode); \ } else if (pRpc == NULL) \ - status = NV_ERR_INSUFFICIENT_RESOURCES; \ + return NV_ERR_INSUFFICIENT_RESOURCES; \ } \ while (0) +/* + * Control RPC macro + */ #define NV_RM_RPC_CONTROL(pGpu, hClient, hObject, cmd, pParams, paramSize, status) \ do \ { \ @@ -269,14 +225,34 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ - status = pRmApi->Control(pRmApi, hClient, hObject, cmd, \ - pParams, paramSize); \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ + status = pRmApi->Control(pRmApi, hClient, hObject, cmd, \ + pParams, paramSize); \ + } \ + else \ + { \ + status = rpcDmaControl_wrapper(pGpu, pRpc, hClient, hObject, \ + cmd, pParams, paramSize); \ + } \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while (0) +#define NV_RM_RPC_API_CONTROL(pGpu, hClient, hObject, cmd, pParams, paramSize, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + NV_ASSERT(pRpc != NULL); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + { \ + status = rpcRmApiControl_HAL(pGpu, pRpc, hClient, hObject, \ + cmd, pParams, paramSize); \ + } else if (pRpc == NULL) \ + status = NV_ERR_INSUFFICIENT_RESOURCES; \ + } while (0) + #define NV_RM_RPC_ALLOC_CHANNEL(pGpu, hclient, hparent, hchannel, hclass, \ pGpfifoAllocParams, pchid, status) \ do \ @@ -286,11 +262,18 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ - status = pRmApi->AllocWithHandle(pRmApi, hclient, hparent, hchannel, \ - hclass, pGpfifoAllocParams, \ - sizeof(*pGpfifoAllocParams)); \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ + status = pRmApi->AllocWithHandle(pRmApi, hclient, hparent, hchannel, \ + hclass, pGpfifoAllocParams, \ + sizeof(*pGpfifoAllocParams)); \ + } \ + else \ + { \ + status = rpcAllocChannelDma_HAL(pGpu, pRpc, hclient, hparent, hchannel, \ + hclass, pGpfifoAllocParams, pchid); \ + } \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } \ @@ -303,41 +286,62 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ - status = pRmApi->AllocWithHandle(pRmApi, hclient, hchannel, hobject, \ - hclass, params, paramsSize); \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ + status = pRmApi->AllocWithHandle(pRmApi, hclient, hchannel, hobject, \ + hclass, params, paramsSize); \ + } \ + else \ + { \ + status = rpcAllocObject_HAL(pGpu, pRpc, \ + hclient, hchannel, hobject, hclass, params);\ + } \ } \ } while (0) +/* + * free RPC macros + */ #define NV_RM_RPC_FREE(pGpu, hclient, hparent, hobject, status) \ do \ { \ - (void) hparent; \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ - status = pRmApi->Free(pRmApi, hclient, hobject); \ - } else if (pRpc == NULL) \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ + status = pRmApi->Free(pRmApi, hclient, hobject); \ + } \ + else \ + { \ + status = rpcFree_HAL(pGpu, pRpc, hclient, hparent, hobject); \ + } \ + } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while (0) #define NV_RM_RPC_FREE_ON_ERROR(pGpu, hclient, hparent, hobject) \ do \ { \ - (void) hparent; \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ NV_ASSERT(pRpc != NULL); \ /* used in failure cases, macro doesn't overwrite rmStatus */ \ if (pRpc != NULL) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ - pRmApi->Free(pRmApi, hclient, hobject); \ - } \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ + pRmApi->Free(pRmApi, hclient, hobject); \ + } \ + else \ + { \ + rpcFree_HAL(pGpu, pRpc, hclient, hparent, hobject); \ + } \ + } else if (pRpc == NULL) \ + status = NV_ERR_INSUFFICIENT_RESOURCES; \ } \ while (0) @@ -345,22 +349,28 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r hevent, hclass, idx, status) \ do \ { \ - (void) hchannel; \ OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ - NV0005_ALLOC_PARAMETERS allocParams = {0}; \ - allocParams.hParentClient = hparentclient; \ - allocParams.hClass = hclass; \ - allocParams.notifyIndex = idx | NV01_EVENT_CLIENT_RM; \ - allocParams.data = 0; \ - status = pRmApi->AllocWithHandle(pRmApi, hclient, \ - hobject, hevent, \ - hclass, &allocParams, \ - sizeof(allocParams)); \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ + NV0005_ALLOC_PARAMETERS allocParams = {0}; \ + allocParams.hParentClient = hparentclient; \ + allocParams.hClass = hclass; \ + allocParams.notifyIndex = idx | NV01_EVENT_CLIENT_RM; \ + allocParams.data = 0; \ + status = pRmApi->AllocWithHandle(pRmApi, hclient, \ + hobject, hevent, \ + hclass, &allocParams, \ + sizeof(allocParams)); \ + } \ + else \ + { \ + status = rpcAllocEvent_HAL(pGpu, pRpc, hclient, hparentclient, \ + hchannel, hobject, hevent, hclass, idx);\ + } \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) @@ -373,15 +383,20 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ - NV2080_ALLOC_PARAMETERS alloc_params = {0}; \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ + NV2080_ALLOC_PARAMETERS alloc_params = {0}; \ \ - alloc_params.subDeviceId = subDeviceInst; \ + alloc_params.subDeviceId = subDeviceInst; \ \ - status = pRmApi->AllocWithHandle(pRmApi, hclient, hdevice, hsubdevice, \ - hclass, &alloc_params, \ - sizeof(alloc_params)); \ + status = pRmApi->AllocWithHandle(pRmApi, hclient, hdevice, hsubdevice, \ + hclass, &alloc_params, \ + sizeof(alloc_params)); \ + } \ + else \ + status = rpcAllocSubdevice_HAL(pGpu, pRpc, hclient, hdevice, \ + hsubdevice, hclass, subDeviceInst); \ } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while (0) @@ -394,109 +409,33 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r NV_ASSERT(pRpc != NULL); \ if ((status == NV_OK) && (pRpc != NULL)) \ { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ - status = pRmApi->DupObject(pRmApi, hclient, hparent, \ - &hobject, hclient_src, \ - hobject_src, flags); \ + if (IS_GSP_CLIENT(pGpu)) \ + { \ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); \ + status = pRmApi->DupObject(pRmApi, hclient, hparent, \ + &hobject, hclient_src, \ + hobject_src, flags); \ + } \ + else \ + status = rpcDupObject_HAL(pGpu, pRpc, hclient, hparent, \ + hobject, hclient_src, \ + hobject_src, flags); \ if ((bAutoFreeRpc) && (pDstRef != NULL) && (status == NV_OK)) \ { \ RmResource *pRmResource; \ pRmResource = dynamicCast(((RsResourceRef*)pDstRef)->pResource, RmResource); \ pRmResource->bRpcFree = NV_TRUE; \ } \ - } else if (pRpc == NULL) \ + } else if (pRpc == NULL) \ status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while (0) -#define NV_RM_RPC_VGPU_PF_REG_READ32(pGpu, address, value, status) \ - do \ - { \ - OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ - NV_ASSERT(pRpc != NULL); \ - if ((status == NV_OK) && (pRpc != NULL)) \ - { \ - NV_ASSERT(IS_GSP_CLIENT(pGpu)); \ - status = rpcVgpuPfRegRead32_HAL(pGpu, pRpc, address, value, 0); \ - } else if (pRpc == NULL) \ - status = NV_ERR_INSUFFICIENT_RESOURCES; \ - } while (0) - -/* - * manage HW resources RPC macro - */ -#define NV_RM_RPC_MANAGE_HW_RESOURCE_ALLOC(pGpu, hclient, hdevice, hresource, \ - pfballocinfo, status) \ - do \ - { \ - OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ - NV_ASSERT(pRpc != NULL); \ - if ((status == NV_OK) && (pRpc != NULL)) \ - status = RmRpcHwResourceAlloc(pGpu, pRpc, hclient, hdevice, \ - hresource, pfballocinfo); \ - else if (pRpc == NULL) \ - status = NV_ERR_INSUFFICIENT_RESOURCES; \ - } while(0) - -#define NV_RM_RPC_MANAGE_HW_RESOURCE_FREE(pGpu, hclient, hdevice, hresource, \ - flags, status) \ - do \ - { \ - OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ - NV_ASSERT(pRpc != NULL); \ - if ((status == NV_OK) && (pRpc != NULL)) \ - status = RmRpcHwResourceFree(pGpu, pRpc, hclient, hdevice, \ - hresource, flags); \ - if (pRpc == NULL) \ - status = NV_ERR_INSUFFICIENT_RESOURCES; \ - } while(0) - -/* outgoing updates to the plugin */ -#define NV_RM_RPC_SIM_UPDATE_DISP_CONTEXT_DMA(pGpu, hclient, pcontextdma, physaddrnew, \ - physlimitnew, pagesize, ptekind) \ - do \ - { \ - NV_STATUS status; \ - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) \ - status = RmRpcSimUpdateDisplayContextDma(pGpu, hclient, pcontextdma, physaddrnew,\ - physlimitnew, pagesize, ptekind); \ - NV_ASSERT(status == NV_OK); \ - SLI_LOOP_END \ - } \ - while(0) - -#define NV_RM_RPC_SIM_DELETE_DISP_CONTEXT_DMA(pGpu, hclient, pcontextdma) \ - do \ - { \ - NV_STATUS status; \ - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) \ - status = RmRpcSimDeleteDisplayContextDma(pGpu, hclient, pcontextdma); \ - NV_ASSERT(status == NV_OK); \ - SLI_LOOP_END \ - } \ - while(0) - -#define NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(pGpu, hclient, pcontextdma, channelnum) \ - do \ - { \ - NV_STATUS status; \ - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) \ - status = RmRpcSimUpdateDispChannelInfo(pGpu, hclient, pcontextdma, channelnum); \ - NV_ASSERT(status == NV_OK); \ - SLI_LOOP_END \ - } \ - while(0) - -/* - * free RPC infrastructure for simulation (not VGPU object) - */ -#define NV_RM_RPC_SIM_FREE_INFRA(pGpu, status) \ - do \ - { \ - NV_ASSERT(status == NV_OK); \ - status = RmRpcSimFreeInfra(pGpu); \ - } \ - while (0) +static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_ALLOC(OBJGPU *pGpu, ...) { return; } +static inline void NV_RM_RPC_MANAGE_HW_RESOURCE_FREE(OBJGPU *pGpu, ...) { return; } +static inline void NV_RM_RPC_SIM_UPDATE_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } +static inline void NV_RM_RPC_SIM_DELETE_DISP_CONTEXT_DMA(OBJGPU *pGpu, ...) { return; } +static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { return; } +static inline void NV_RM_RPC_SIM_FREE_INFRA(OBJGPU *pGpu, ...) { return; } #define NV_RM_RPC_SET_GUEST_SYSTEM_INFO(pGpu, status) \ do \ @@ -509,17 +448,15 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) -#define NV_RM_RPC_PERF_GET_VIRTUAL_PSTATE_INFO(pGpu, hClient, hObject, pParams, \ - pClkInfos, status) \ - do \ - { \ - OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ - NV_ASSERT(pRpc != NULL); \ - if ((status == NV_OK) && (pRpc != NULL)) \ - status = RmRpcPerfGetVirtualPstateInfo(pGpu, pRpc, hClient, hObject,\ - pParams, pClkInfos); \ - else if (pRpc == NULL) \ - status = NV_ERR_INSUFFICIENT_RESOURCES; \ +#define NV_RM_RPC_SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER(pGpu, status, bitmapInfo) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + NV_ASSERT(pRpc != NULL); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcSetSysmemDirtyPageTrackingBuffer_HAL(pGpu, pRpc, bitmapInfo);\ + else if (pRpc == NULL) \ + status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while(0) #define NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, bInPMTransition, bGc6Entering, newPMLevel) \ @@ -546,17 +483,6 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r } \ while (0) -#define NV_RM_RPC_GET_STATIC_INFO(pGpu, status) \ - do \ - { \ - OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ - NV_ASSERT(pRpc != NULL); \ - if ((status == NV_OK) && (pRpc != NULL)) \ - status = rpcGetStaticInfo_HAL(pGpu, pRpc); \ - else if (pRpc == NULL) \ - status = NV_ERR_INSUFFICIENT_RESOURCES; \ - } while (0) - #define NV_RM_RPC_REGISTER_VIRTUAL_EVENT_BUFFER(pGpu, hClient, hSubdevice, hEventBuffer, hBufferHeader, hRecordBuffer, recordSize, recordCount, status) \ do \ { \ @@ -601,18 +527,18 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r status = NV_ERR_INSUFFICIENT_RESOURCES; \ } while (0) -#define NV_RM_RPC_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION(pGpu, operation, status) \ - do \ - { \ - /* Call into RPC layer */ \ - OBJRPC *pRpc; \ - pRpc = GPU_GET_RPC(pGpu); \ - if ((status == NV_OK) && (pRpc != NULL)) \ - { \ - status = rpcPmaScrubberSharedBufferGuestPagesOperation_HAL(pGpu, pRpc, operation); \ - } \ - } \ - while (0) +static inline void NV_RM_RPC_PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION(OBJGPU *pGpu, ...) { return; } + +#define NV_RM_RPC_INVALIDATE_TLB(pGpu, status, pdbAddress, regVal) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + NV_ASSERT(pRpc != NULL); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcInvalidateTlb_HAL(pGpu, pRpc, pdbAddress, regVal); \ + else if (pRpc == NULL) \ + status = NV_ERR_INSUFFICIENT_RESOURCES; \ + } while(0) // // DCE_CLIENT_RM specific RPCs @@ -690,6 +616,10 @@ static inline void NV_RM_RPC_SIM_UPDATE_DISP_CHANNEL_INFO(OBJGPU *pGpu, ...) { r #define NV_RM_RPC_RMFS_TEST(pGpu, numReps, testData1, testData2, \ testData3, status) do {} while(0) +void teardownSysmemPfnBitMap(OBJGPU *pGpu, OBJVGPU *pVGpu); + +NV_STATUS RmRpcPerfGetCurrentPstate(OBJGPU *pGpu, NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS *pParamStructPtr); + static inline NV_STATUS RmRpcSimFreeInfra(OBJGPU *pGpu, ...) { return NV_OK; } static inline NV_STATUS RmRpcSimUpdateDisplayContextDma(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcSimDeleteDisplayContextDma(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } @@ -697,7 +627,6 @@ static inline NV_STATUS RmRpcSimUpdateDispChannelInfo(OBJGPU *pGpu, ...) static inline NV_STATUS RmRpcHwResourceAlloc(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcHwResourceFree(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcPerfGetPstateInfo(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } -static inline NV_STATUS RmRpcPerfGetCurrentPstate(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcPerfGetVirtualPstateInfo(OBJGPU *pGpu, ...) { return NV_ERR_NOT_SUPPORTED; } static inline NV_STATUS RmRpcSimEscapeRead(OBJGPU *pGpu, const char *path, NvU32 index, @@ -721,6 +650,4 @@ typedef struct SimAccessBuffer volatile NvU32 seq; } SimAccessBuffer; -#endif // NV_RM_STUB_RPC - #endif // __vgpu_dev_nv_rpc_h__ diff --git a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h index 56effe2e1e..0cb029e616 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h @@ -2,214 +2,222 @@ #define _RPC_GLOBAL_ENUMS_H_ #ifndef X -# define X(UNIT, RPC) NV_VGPU_MSG_FUNCTION_##RPC, +# define X(UNIT, RPC, VAL) NV_VGPU_MSG_FUNCTION_##RPC = VAL, # define DEFINING_X_IN_RPC_GLOBAL_ENUMS_H enum { #endif - X(RM, NOP) // 0 - X(RM, SET_GUEST_SYSTEM_INFO) // 1 - X(RM, ALLOC_ROOT) // 2 - X(RM, ALLOC_DEVICE) // 3 deprecated - X(RM, ALLOC_MEMORY) // 4 - X(RM, ALLOC_CTX_DMA) // 5 - X(RM, ALLOC_CHANNEL_DMA) // 6 - X(RM, MAP_MEMORY) // 7 - X(RM, BIND_CTX_DMA) // 8 deprecated - X(RM, ALLOC_OBJECT) // 9 - X(RM, FREE) //10 - X(RM, LOG) //11 - X(RM, ALLOC_VIDMEM) //12 - X(RM, UNMAP_MEMORY) //13 - X(RM, MAP_MEMORY_DMA) //14 - X(RM, UNMAP_MEMORY_DMA) //15 - X(RM, GET_EDID) //16 - X(RM, ALLOC_DISP_CHANNEL) //17 - X(RM, ALLOC_DISP_OBJECT) //18 - X(RM, ALLOC_SUBDEVICE) //19 - X(RM, ALLOC_DYNAMIC_MEMORY) //20 - X(RM, DUP_OBJECT) //21 - X(RM, IDLE_CHANNELS) //22 - X(RM, ALLOC_EVENT) //23 - X(RM, SEND_EVENT) //24 - X(RM, REMAPPER_CONTROL) //25 deprecated - X(RM, DMA_CONTROL) //26 - X(RM, DMA_FILL_PTE_MEM) //27 - X(RM, MANAGE_HW_RESOURCE) //28 - X(RM, BIND_ARBITRARY_CTX_DMA) //29 deprecated - X(RM, CREATE_FB_SEGMENT) //30 - X(RM, DESTROY_FB_SEGMENT) //31 - X(RM, ALLOC_SHARE_DEVICE) //32 - X(RM, DEFERRED_API_CONTROL) //33 - X(RM, REMOVE_DEFERRED_API) //34 - X(RM, SIM_ESCAPE_READ) //35 - X(RM, SIM_ESCAPE_WRITE) //36 - X(RM, SIM_MANAGE_DISPLAY_CONTEXT_DMA) //37 - X(RM, FREE_VIDMEM_VIRT) //38 - X(RM, PERF_GET_PSTATE_INFO) //39 deprecated for vGPU, used by GSP - X(RM, PERF_GET_PERFMON_SAMPLE) //40 - X(RM, PERF_GET_VIRTUAL_PSTATE_INFO) //41 deprecated - X(RM, PERF_GET_LEVEL_INFO) //42 - X(RM, MAP_SEMA_MEMORY) //43 - X(RM, UNMAP_SEMA_MEMORY) //44 - X(RM, SET_SURFACE_PROPERTIES) //45 - X(RM, CLEANUP_SURFACE) //46 - X(RM, UNLOADING_GUEST_DRIVER) //47 - X(RM, TDR_SET_TIMEOUT_STATE) //48 - X(RM, SWITCH_TO_VGA) //49 - X(RM, GPU_EXEC_REG_OPS) //50 - X(RM, GET_STATIC_INFO) //51 - X(RM, ALLOC_VIRTMEM) //52 - X(RM, UPDATE_PDE_2) //53 - X(RM, SET_PAGE_DIRECTORY) //54 - X(RM, GET_STATIC_PSTATE_INFO) //55 - X(RM, TRANSLATE_GUEST_GPU_PTES) //56 - X(RM, RESERVED_57) //57 - X(RM, RESET_CURRENT_GR_CONTEXT) //58 - X(RM, SET_SEMA_MEM_VALIDATION_STATE) //59 - X(RM, GET_ENGINE_UTILIZATION) //60 - X(RM, UPDATE_GPU_PDES) //61 - X(RM, GET_ENCODER_CAPACITY) //62 - X(RM, VGPU_PF_REG_READ32) //63 - X(RM, SET_GUEST_SYSTEM_INFO_EXT) //64 - X(GSP, GET_GSP_STATIC_INFO) //65 - X(RM, RMFS_INIT) //66 - X(RM, RMFS_CLOSE_QUEUE) //67 - X(RM, RMFS_CLEANUP) //68 - X(RM, RMFS_TEST) //69 - X(RM, UPDATE_BAR_PDE) //70 - X(RM, CONTINUATION_RECORD) //71 - X(RM, GSP_SET_SYSTEM_INFO) //72 - X(RM, SET_REGISTRY) //73 - X(GSP, GSP_INIT_POST_OBJGPU) //74 deprecated - X(RM, SUBDEV_EVENT_SET_NOTIFICATION) //75 deprecated - X(GSP, GSP_RM_CONTROL) //76 - X(RM, GET_STATIC_INFO2) //77 - X(RM, DUMP_PROTOBUF_COMPONENT) //78 - X(RM, UNSET_PAGE_DIRECTORY) //79 - X(RM, GET_CONSOLIDATED_STATIC_INFO) //80 - X(RM, GMMU_REGISTER_FAULT_BUFFER) //81 deprecated - X(RM, GMMU_UNREGISTER_FAULT_BUFFER) //82 deprecated - X(RM, GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER) //83 deprecated - X(RM, GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER) //84 deprecated - X(RM, CTRL_SET_VGPU_FB_USAGE) //85 - X(RM, CTRL_NVFBC_SW_SESSION_UPDATE_INFO) //86 - X(RM, CTRL_NVENC_SW_SESSION_UPDATE_INFO) //87 - X(RM, CTRL_RESET_CHANNEL) //88 - X(RM, CTRL_RESET_ISOLATED_CHANNEL) //89 - X(RM, CTRL_GPU_HANDLE_VF_PRI_FAULT) //90 - X(RM, CTRL_CLK_GET_EXTENDED_INFO) //91 - X(RM, CTRL_PERF_BOOST) //92 - X(RM, CTRL_PERF_VPSTATES_GET_CONTROL) //93 - X(RM, CTRL_GET_ZBC_CLEAR_TABLE) //94 - X(RM, CTRL_SET_ZBC_COLOR_CLEAR) //95 - X(RM, CTRL_SET_ZBC_DEPTH_CLEAR) //96 - X(RM, CTRL_GPFIFO_SCHEDULE) //97 - X(RM, CTRL_SET_TIMESLICE) //98 - X(RM, CTRL_PREEMPT) //99 - X(RM, CTRL_FIFO_DISABLE_CHANNELS) //100 - X(RM, CTRL_SET_TSG_INTERLEAVE_LEVEL) //101 - X(RM, CTRL_SET_CHANNEL_INTERLEAVE_LEVEL) //102 - X(GSP, GSP_RM_ALLOC) //103 - X(RM, CTRL_GET_P2P_CAPS_V2) //104 - X(RM, CTRL_CIPHER_AES_ENCRYPT) //105 - X(RM, CTRL_CIPHER_SESSION_KEY) //106 - X(RM, CTRL_CIPHER_SESSION_KEY_STATUS) //107 - X(RM, CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES) //108 - X(RM, CTRL_DBG_READ_ALL_SM_ERROR_STATES) //109 - X(RM, CTRL_DBG_SET_EXCEPTION_MASK) //110 - X(RM, CTRL_GPU_PROMOTE_CTX) //111 - X(RM, CTRL_GR_CTXSW_PREEMPTION_BIND) //112 - X(RM, CTRL_GR_SET_CTXSW_PREEMPTION_MODE) //113 - X(RM, CTRL_GR_CTXSW_ZCULL_BIND) //114 - X(RM, CTRL_GPU_INITIALIZE_CTX) //115 - X(RM, CTRL_VASPACE_COPY_SERVER_RESERVED_PDES) //116 - X(RM, CTRL_FIFO_CLEAR_FAULTED_BIT) //117 - X(RM, CTRL_GET_LATEST_ECC_ADDRESSES) //118 - X(RM, CTRL_MC_SERVICE_INTERRUPTS) //119 - X(RM, CTRL_DMA_SET_DEFAULT_VASPACE) //120 - X(RM, CTRL_GET_CE_PCE_MASK) //121 - X(RM, CTRL_GET_ZBC_CLEAR_TABLE_ENTRY) //122 - X(RM, CTRL_GET_NVLINK_PEER_ID_MASK) //123 - X(RM, CTRL_GET_NVLINK_STATUS) //124 - X(RM, CTRL_GET_P2P_CAPS) //125 - X(RM, CTRL_GET_P2P_CAPS_MATRIX) //126 - X(RM, RESERVED_0) //127 - X(RM, CTRL_RESERVE_PM_AREA_SMPC) //128 - X(RM, CTRL_RESERVE_HWPM_LEGACY) //129 - X(RM, CTRL_B0CC_EXEC_REG_OPS) //130 - X(RM, CTRL_BIND_PM_RESOURCES) //131 - X(RM, CTRL_DBG_SUSPEND_CONTEXT) //132 - X(RM, CTRL_DBG_RESUME_CONTEXT) //133 - X(RM, CTRL_DBG_EXEC_REG_OPS) //134 - X(RM, CTRL_DBG_SET_MODE_MMU_DEBUG) //135 - X(RM, CTRL_DBG_READ_SINGLE_SM_ERROR_STATE) //136 - X(RM, CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE) //137 - X(RM, CTRL_DBG_SET_MODE_ERRBAR_DEBUG) //138 - X(RM, CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE) //139 - X(RM, CTRL_ALLOC_PMA_STREAM) //140 - X(RM, CTRL_PMA_STREAM_UPDATE_GET_PUT) //141 - X(RM, CTRL_FB_GET_INFO_V2) //142 - X(RM, CTRL_FIFO_SET_CHANNEL_PROPERTIES) //143 - X(RM, CTRL_GR_GET_CTX_BUFFER_INFO) //144 - X(RM, CTRL_KGR_GET_CTX_BUFFER_PTES) //145 - X(RM, CTRL_GPU_EVICT_CTX) //146 - X(RM, CTRL_FB_GET_FS_INFO) //147 - X(RM, CTRL_GRMGR_GET_GR_FS_INFO) //148 - X(RM, CTRL_STOP_CHANNEL) //149 - X(RM, CTRL_GR_PC_SAMPLING_MODE) //150 - X(RM, CTRL_PERF_RATED_TDP_GET_STATUS) //151 - X(RM, CTRL_PERF_RATED_TDP_SET_CONTROL) //152 - X(RM, CTRL_FREE_PMA_STREAM) //153 - X(RM, CTRL_TIMER_SET_GR_TICK_FREQ) //154 - X(RM, CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB) //155 - X(RM, GET_CONSOLIDATED_GR_STATIC_INFO) //156 - X(RM, CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP) //157 - X(RM, CTRL_GR_GET_TPC_PARTITION_MODE) //158 - X(RM, CTRL_GR_SET_TPC_PARTITION_MODE) //159 - X(UVM, UVM_PAGING_CHANNEL_ALLOCATE) //160 - X(UVM, UVM_PAGING_CHANNEL_DESTROY) //161 - X(UVM, UVM_PAGING_CHANNEL_MAP) //162 - X(UVM, UVM_PAGING_CHANNEL_UNMAP) //163 - X(UVM, UVM_PAGING_CHANNEL_PUSH_STREAM) //164 - X(UVM, UVM_PAGING_CHANNEL_SET_HANDLES) //165 - X(UVM, UVM_METHOD_STREAM_GUEST_PAGES_OPERATION) //166 - X(RM, CTRL_INTERNAL_QUIESCE_PMA_CHANNEL) //167 - X(RM, DCE_RM_INIT) //168 - X(RM, REGISTER_VIRTUAL_EVENT_BUFFER) //169 - X(RM, CTRL_EVENT_BUFFER_UPDATE_GET) //170 - X(RM, GET_PLCABLE_ADDRESS_KIND) //171 - X(RM, CTRL_PERF_LIMITS_SET_STATUS_V2) //172 - X(RM, CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM) //173 - X(RM, CTRL_GET_MMU_DEBUG_MODE) //174 - X(RM, CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS) //175 - X(RM, CTRL_FLCN_GET_CTX_BUFFER_SIZE) //176 - X(RM, CTRL_FLCN_GET_CTX_BUFFER_INFO) //177 - X(RM, DISABLE_CHANNELS) //178 - X(RM, CTRL_FABRIC_MEMORY_DESCRIBE) //179 - X(RM, CTRL_FABRIC_MEM_STATS) //180 - X(RM, SAVE_HIBERNATION_DATA) //181 - X(RM, RESTORE_HIBERNATION_DATA) //182 - X(RM, CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED) //183 - X(RM, CTRL_EXEC_PARTITIONS_CREATE) //184 - X(RM, CTRL_EXEC_PARTITIONS_DELETE) //185 - X(RM, CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN) //186 - X(RM, CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX) //187 - X(RM, PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION) //188 - X(RM, CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK) //189 - X(RM, SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER) //190 - X(RM, CTRL_SUBDEVICE_GET_P2P_CAPS) // 191 - X(RM, CTRL_BUS_SET_P2P_MAPPING) // 192 - X(RM, CTRL_BUS_UNSET_P2P_MAPPING) // 193 - X(RM, CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK) // 194 - X(RM, CTRL_GPU_MIGRATABLE_OPS) // 195 - X(RM, CTRL_GET_TOTAL_HS_CREDITS) // 196 - X(RM, CTRL_GET_HS_CREDITS) // 197 - X(RM, CTRL_SET_HS_CREDITS) // 198 - X(RM, CTRL_PM_AREA_PC_SAMPLER) // 199 - X(RM, INVALIDATE_TLB) // 200 - X(RM, CTRL_GPU_QUERY_ECC_STATUS) // 201 - X(RM, ECC_NOTIFIER_WRITE_ACK) // 202 - X(RM, NUM_FUNCTIONS) //END + X(RM, NOP, 0) + X(RM, SET_GUEST_SYSTEM_INFO, 1) + X(RM, ALLOC_ROOT, 2) + X(RM, ALLOC_DEVICE, 3) // deprecated + X(RM, ALLOC_MEMORY, 4) + X(RM, ALLOC_CTX_DMA, 5) + X(RM, ALLOC_CHANNEL_DMA, 6) + X(RM, MAP_MEMORY, 7) + X(RM, BIND_CTX_DMA, 8) // deprecated + X(RM, ALLOC_OBJECT, 9) + X(RM, FREE, 10) + X(RM, LOG, 11) + X(RM, ALLOC_VIDMEM, 12) + X(RM, UNMAP_MEMORY, 13) + X(RM, MAP_MEMORY_DMA, 14) + X(RM, UNMAP_MEMORY_DMA, 15) + X(RM, GET_EDID, 16) + X(RM, ALLOC_DISP_CHANNEL, 17) + X(RM, ALLOC_DISP_OBJECT, 18) + X(RM, ALLOC_SUBDEVICE, 19) + X(RM, ALLOC_DYNAMIC_MEMORY, 20) + X(RM, DUP_OBJECT, 21) + X(RM, IDLE_CHANNELS, 22) + X(RM, ALLOC_EVENT, 23) + X(RM, SEND_EVENT, 24) // deprecated + X(RM, REMAPPER_CONTROL, 25) // deprecated + X(RM, DMA_CONTROL, 26) // deprecated + X(RM, DMA_FILL_PTE_MEM, 27) + X(RM, MANAGE_HW_RESOURCE, 28) + X(RM, BIND_ARBITRARY_CTX_DMA, 29) // deprecated + X(RM, CREATE_FB_SEGMENT, 30) + X(RM, DESTROY_FB_SEGMENT, 31) + X(RM, ALLOC_SHARE_DEVICE, 32) + X(RM, DEFERRED_API_CONTROL, 33) + X(RM, REMOVE_DEFERRED_API, 34) + X(RM, SIM_ESCAPE_READ, 35) + X(RM, SIM_ESCAPE_WRITE, 36) + X(RM, SIM_MANAGE_DISPLAY_CONTEXT_DMA, 37) + X(RM, FREE_VIDMEM_VIRT, 38) + X(RM, PERF_GET_PSTATE_INFO, 39) // deprecated for vGPU, used by GSP + X(RM, PERF_GET_PERFMON_SAMPLE, 40) + X(RM, PERF_GET_VIRTUAL_PSTATE_INFO, 41) // deprecated + X(RM, PERF_GET_LEVEL_INFO, 42) + X(RM, MAP_SEMA_MEMORY, 43) + X(RM, UNMAP_SEMA_MEMORY, 44) + X(RM, SET_SURFACE_PROPERTIES, 45) + X(RM, CLEANUP_SURFACE, 46) + X(RM, UNLOADING_GUEST_DRIVER, 47) + X(RM, TDR_SET_TIMEOUT_STATE, 48) + X(RM, SWITCH_TO_VGA, 49) + X(RM, GPU_EXEC_REG_OPS, 50) + X(RM, GET_STATIC_INFO, 51) + X(RM, ALLOC_VIRTMEM, 52) + X(RM, UPDATE_PDE_2, 53) + X(RM, SET_PAGE_DIRECTORY, 54) + X(RM, GET_STATIC_PSTATE_INFO, 55) + X(RM, TRANSLATE_GUEST_GPU_PTES, 56) + X(RM, RESERVED_57, 57) + X(RM, RESET_CURRENT_GR_CONTEXT, 58) + X(RM, SET_SEMA_MEM_VALIDATION_STATE, 59) + X(RM, GET_ENGINE_UTILIZATION, 60) + X(RM, UPDATE_GPU_PDES, 61) + X(RM, GET_ENCODER_CAPACITY, 62) + X(RM, VGPU_PF_REG_READ32, 63) // deprecated + X(RM, SET_GUEST_SYSTEM_INFO_EXT, 64) + X(GSP, GET_GSP_STATIC_INFO, 65) + X(RM, RMFS_INIT, 66) + X(RM, RMFS_CLOSE_QUEUE, 67) + X(RM, RMFS_CLEANUP, 68) + X(RM, RMFS_TEST, 69) + X(RM, UPDATE_BAR_PDE, 70) + X(RM, CONTINUATION_RECORD, 71) + X(RM, GSP_SET_SYSTEM_INFO, 72) + X(RM, SET_REGISTRY, 73) + X(GSP, GSP_INIT_POST_OBJGPU, 74) // deprecated + X(RM, SUBDEV_EVENT_SET_NOTIFICATION, 75) // deprecated + X(GSP, GSP_RM_CONTROL, 76) + X(RM, GET_STATIC_INFO2, 77) + X(RM, DUMP_PROTOBUF_COMPONENT, 78) + X(RM, UNSET_PAGE_DIRECTORY, 79) + X(RM, GET_CONSOLIDATED_STATIC_INFO, 80) // deprecated + X(RM, GMMU_REGISTER_FAULT_BUFFER, 81) // deprecated + X(RM, GMMU_UNREGISTER_FAULT_BUFFER, 82) // deprecated + X(RM, GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER, 83) // deprecated + X(RM, GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER, 84) // deprecated + X(RM, CTRL_SET_VGPU_FB_USAGE, 85) + X(RM, CTRL_NVFBC_SW_SESSION_UPDATE_INFO, 86) + X(RM, CTRL_NVENC_SW_SESSION_UPDATE_INFO, 87) + X(RM, CTRL_RESET_CHANNEL, 88) + X(RM, CTRL_RESET_ISOLATED_CHANNEL, 89) + X(RM, CTRL_GPU_HANDLE_VF_PRI_FAULT, 90) + X(RM, CTRL_CLK_GET_EXTENDED_INFO, 91) + X(RM, CTRL_PERF_BOOST, 92) + X(RM, CTRL_PERF_VPSTATES_GET_CONTROL, 93) + X(RM, CTRL_GET_ZBC_CLEAR_TABLE, 94) + X(RM, CTRL_SET_ZBC_COLOR_CLEAR, 95) + X(RM, CTRL_SET_ZBC_DEPTH_CLEAR, 96) + X(RM, CTRL_GPFIFO_SCHEDULE, 97) + X(RM, CTRL_SET_TIMESLICE, 98) + X(RM, CTRL_PREEMPT, 99) + X(RM, CTRL_FIFO_DISABLE_CHANNELS, 100) + X(RM, CTRL_SET_TSG_INTERLEAVE_LEVEL, 101) + X(RM, CTRL_SET_CHANNEL_INTERLEAVE_LEVEL, 102) + X(GSP, GSP_RM_ALLOC, 103) + X(RM, CTRL_GET_P2P_CAPS_V2, 104) + X(RM, CTRL_CIPHER_AES_ENCRYPT, 105) + X(RM, CTRL_CIPHER_SESSION_KEY, 106) + X(RM, CTRL_CIPHER_SESSION_KEY_STATUS, 107) + X(RM, CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES, 108) + X(RM, CTRL_DBG_READ_ALL_SM_ERROR_STATES, 109) + X(RM, CTRL_DBG_SET_EXCEPTION_MASK, 110) + X(RM, CTRL_GPU_PROMOTE_CTX, 111) + X(RM, CTRL_GR_CTXSW_PREEMPTION_BIND, 112) + X(RM, CTRL_GR_SET_CTXSW_PREEMPTION_MODE, 113) + X(RM, CTRL_GR_CTXSW_ZCULL_BIND, 114) + X(RM, CTRL_GPU_INITIALIZE_CTX, 115) + X(RM, CTRL_VASPACE_COPY_SERVER_RESERVED_PDES, 116) + X(RM, CTRL_FIFO_CLEAR_FAULTED_BIT, 117) + X(RM, CTRL_GET_LATEST_ECC_ADDRESSES, 118) + X(RM, CTRL_MC_SERVICE_INTERRUPTS, 119) + X(RM, CTRL_DMA_SET_DEFAULT_VASPACE, 120) + X(RM, CTRL_GET_CE_PCE_MASK, 121) + X(RM, CTRL_GET_ZBC_CLEAR_TABLE_ENTRY, 122) + X(RM, CTRL_GET_NVLINK_PEER_ID_MASK, 123) + X(RM, CTRL_GET_NVLINK_STATUS, 124) + X(RM, CTRL_GET_P2P_CAPS, 125) + X(RM, CTRL_GET_P2P_CAPS_MATRIX, 126) + X(RM, RESERVED_0, 127) + X(RM, CTRL_RESERVE_PM_AREA_SMPC, 128) + X(RM, CTRL_RESERVE_HWPM_LEGACY, 129) + X(RM, CTRL_B0CC_EXEC_REG_OPS, 130) + X(RM, CTRL_BIND_PM_RESOURCES, 131) + X(RM, CTRL_DBG_SUSPEND_CONTEXT, 132) + X(RM, CTRL_DBG_RESUME_CONTEXT, 133) + X(RM, CTRL_DBG_EXEC_REG_OPS, 134) + X(RM, CTRL_DBG_SET_MODE_MMU_DEBUG, 135) + X(RM, CTRL_DBG_READ_SINGLE_SM_ERROR_STATE, 136) + X(RM, CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE, 137) + X(RM, CTRL_DBG_SET_MODE_ERRBAR_DEBUG, 138) + X(RM, CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE, 139) + X(RM, CTRL_ALLOC_PMA_STREAM, 140) + X(RM, CTRL_PMA_STREAM_UPDATE_GET_PUT, 141) + X(RM, CTRL_FB_GET_INFO_V2, 142) + X(RM, CTRL_FIFO_SET_CHANNEL_PROPERTIES, 143) + X(RM, CTRL_GR_GET_CTX_BUFFER_INFO, 144) + X(RM, CTRL_KGR_GET_CTX_BUFFER_PTES, 145) + X(RM, CTRL_GPU_EVICT_CTX, 146) + X(RM, CTRL_FB_GET_FS_INFO, 147) + X(RM, CTRL_GRMGR_GET_GR_FS_INFO, 148) + X(RM, CTRL_STOP_CHANNEL, 149) + X(RM, CTRL_GR_PC_SAMPLING_MODE, 150) + X(RM, CTRL_PERF_RATED_TDP_GET_STATUS, 151) + X(RM, CTRL_PERF_RATED_TDP_SET_CONTROL, 152) + X(RM, CTRL_FREE_PMA_STREAM, 153) + X(RM, CTRL_TIMER_SET_GR_TICK_FREQ, 154) + X(RM, CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB, 155) + X(RM, GET_CONSOLIDATED_GR_STATIC_INFO, 156) + X(RM, CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP, 157) + X(RM, CTRL_GR_GET_TPC_PARTITION_MODE, 158) + X(RM, CTRL_GR_SET_TPC_PARTITION_MODE, 159) + X(UVM, UVM_PAGING_CHANNEL_ALLOCATE, 160) + X(UVM, UVM_PAGING_CHANNEL_DESTROY, 161) + X(UVM, UVM_PAGING_CHANNEL_MAP, 162) + X(UVM, UVM_PAGING_CHANNEL_UNMAP, 163) + X(UVM, UVM_PAGING_CHANNEL_PUSH_STREAM, 164) + X(UVM, UVM_PAGING_CHANNEL_SET_HANDLES, 165) + X(UVM, UVM_METHOD_STREAM_GUEST_PAGES_OPERATION, 166) + X(RM, CTRL_INTERNAL_QUIESCE_PMA_CHANNEL, 167) + X(RM, DCE_RM_INIT, 168) + X(RM, REGISTER_VIRTUAL_EVENT_BUFFER, 169) + X(RM, CTRL_EVENT_BUFFER_UPDATE_GET, 170) + X(RM, GET_PLCABLE_ADDRESS_KIND, 171) + X(RM, CTRL_PERF_LIMITS_SET_STATUS_V2, 172) + X(RM, CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM, 173) + X(RM, CTRL_GET_MMU_DEBUG_MODE, 174) + X(RM, CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS, 175) + X(RM, CTRL_FLCN_GET_CTX_BUFFER_SIZE, 176) + X(RM, CTRL_FLCN_GET_CTX_BUFFER_INFO, 177) + X(RM, DISABLE_CHANNELS, 178) + X(RM, CTRL_FABRIC_MEMORY_DESCRIBE, 179) + X(RM, CTRL_FABRIC_MEM_STATS, 180) + X(RM, SAVE_HIBERNATION_DATA, 181) + X(RM, RESTORE_HIBERNATION_DATA, 182) + X(RM, CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED, 183) + X(RM, CTRL_EXEC_PARTITIONS_CREATE, 184) + X(RM, CTRL_EXEC_PARTITIONS_DELETE, 185) + X(RM, CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN, 186) + X(RM, CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX, 187) + X(RM, PMA_SCRUBBER_SHARED_BUFFER_GUEST_PAGES_OPERATION, 188) + X(RM, CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK, 189) + X(RM, SET_SYSMEM_DIRTY_PAGE_TRACKING_BUFFER, 190) + X(RM, CTRL_SUBDEVICE_GET_P2P_CAPS, 191) + X(RM, CTRL_BUS_SET_P2P_MAPPING, 192) + X(RM, CTRL_BUS_UNSET_P2P_MAPPING, 193) + X(RM, CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK, 194) + X(RM, CTRL_GPU_MIGRATABLE_OPS, 195) + X(RM, CTRL_GET_TOTAL_HS_CREDITS, 196) + X(RM, CTRL_GET_HS_CREDITS, 197) + X(RM, CTRL_SET_HS_CREDITS, 198) + X(RM, CTRL_PM_AREA_PC_SAMPLER, 199) + X(RM, INVALIDATE_TLB, 200) + X(RM, CTRL_GPU_QUERY_ECC_STATUS, 201) // deprecated + X(RM, ECC_NOTIFIER_WRITE_ACK, 202) + X(RM, CTRL_DBG_GET_MODE_MMU_DEBUG, 203) + X(RM, RM_API_CONTROL, 204) + X(RM, CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE, 205) + X(RM, CTRL_NVLINK_GET_INBAND_RECEIVED_DATA, 206) + X(RM, GET_STATIC_DATA, 207) + X(RM, RESERVED_208, 208) + X(RM, CTRL_GPU_GET_INFO_V2, 209) + X(RM, GET_BRAND_CAPS, 210) + X(RM, NUM_FUNCTIONS, 211) #ifdef DEFINING_X_IN_RPC_GLOBAL_ENUMS_H }; # undef X @@ -218,41 +226,44 @@ enum { // RPC Events. Used by GSP-RM. #ifndef E -# define E(RPC) NV_VGPU_MSG_EVENT_##RPC, +# define E(RPC, VAL) NV_VGPU_MSG_EVENT_##RPC = VAL, # define DEFINING_E_IN_RPC_GLOBAL_ENUMS_H enum { #endif - E(FIRST_EVENT = 0x1000) // 0x1000 - E(GSP_INIT_DONE) // 0x1001 - E(GSP_RUN_CPU_SEQUENCER) // 0x1002 - E(POST_EVENT) // 0x1003 - E(RC_TRIGGERED) // 0x1004 - E(MMU_FAULT_QUEUED) // 0x1005 - E(OS_ERROR_LOG) // 0x1006 - E(RG_LINE_INTR) // 0x1007 - E(GPUACCT_PERFMON_UTIL_SAMPLES) // 0x1008 - E(SIM_READ) // 0x1009 - E(SIM_WRITE) // 0x100a - E(SEMAPHORE_SCHEDULE_CALLBACK) // 0x100b - E(UCODE_LIBOS_PRINT) // 0x100c - E(VGPU_GSP_PLUGIN_TRIGGERED) // 0x100d - E(PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK) // 0x100e - E(PERF_BRIDGELESS_INFO_UPDATE) // 0x100f - E(VGPU_CONFIG) // 0x1010 - E(DISPLAY_MODESET) // 0x1011 - E(EXTDEV_INTR_SERVICE) // 0x1012 - E(NVLINK_INBAND_RECEIVED_DATA_256) // 0x1013 - E(NVLINK_INBAND_RECEIVED_DATA_512) // 0x1014 - E(NVLINK_INBAND_RECEIVED_DATA_1024) // 0x1015 - E(NVLINK_INBAND_RECEIVED_DATA_2048) // 0x1016 - E(NVLINK_INBAND_RECEIVED_DATA_4096) // 0x1017 - E(TIMED_SEMAPHORE_RELEASE) // 0x1018 - E(NVLINK_IS_GPU_DEGRADED) // 0x1019 - E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK) // 0x101a - E(NVLINK_FAULT_UP) // 0x101b - E(GSP_LOCKDOWN_NOTICE) // 0x101c - E(MIG_CI_CONFIG_UPDATE) // 0x101d - E(NUM_EVENTS) // END + E(FIRST_EVENT, 0x1000) + E(GSP_INIT_DONE, 0x1001) + E(GSP_RUN_CPU_SEQUENCER, 0x1002) + E(POST_EVENT, 0x1003) + E(RC_TRIGGERED, 0x1004) + E(MMU_FAULT_QUEUED, 0x1005) + E(OS_ERROR_LOG, 0x1006) + E(RG_LINE_INTR, 0x1007) + E(GPUACCT_PERFMON_UTIL_SAMPLES, 0x1008) + E(SIM_READ, 0x1009) + E(SIM_WRITE, 0x100a) + E(SEMAPHORE_SCHEDULE_CALLBACK, 0x100b) + E(UCODE_LIBOS_PRINT, 0x100c) + E(VGPU_GSP_PLUGIN_TRIGGERED, 0x100d) + E(PERF_GPU_BOOST_SYNC_LIMITS_CALLBACK, 0x100e) + E(PERF_BRIDGELESS_INFO_UPDATE, 0x100f) + E(VGPU_CONFIG, 0x1010) + E(DISPLAY_MODESET, 0x1011) + E(EXTDEV_INTR_SERVICE, 0x1012) + E(NVLINK_INBAND_RECEIVED_DATA_256, 0x1013) + E(NVLINK_INBAND_RECEIVED_DATA_512, 0x1014) + E(NVLINK_INBAND_RECEIVED_DATA_1024, 0x1015) + E(NVLINK_INBAND_RECEIVED_DATA_2048, 0x1016) + E(NVLINK_INBAND_RECEIVED_DATA_4096, 0x1017) + E(TIMED_SEMAPHORE_RELEASE, 0x1018) + E(NVLINK_IS_GPU_DEGRADED, 0x1019) + E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK, 0x101a) + E(NVLINK_FAULT_UP, 0x101b) + E(GSP_LOCKDOWN_NOTICE, 0x101c) + E(MIG_CI_CONFIG_UPDATE, 0x101d) + E(UPDATE_GSP_TRACE, 0x101e) + E(NVLINK_FATAL_ERROR_RECOVERY, 0x101f) + E(GSP_POST_NOCAT_RECORD, 0x1020) + E(NUM_EVENTS, 0x1021) #ifdef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H }; # undef E diff --git a/src/nvidia/kernel/inc/vgpu/rpc_headers.h b/src/nvidia/kernel/inc/vgpu/rpc_headers.h index 4f355095f6..eff711963b 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_headers.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_headers.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -118,7 +118,7 @@ * codes above 0xFF000000 and below 0xFF100000 must match one-for-one * the vmiop_error_t codes in vmioplugin.h, with 0xFF000000 added. */ -#define NV_VGPU_MSG_RESULT__VMIOP 0xFF000007:0xFF000000 /* RW--D */ +#define NV_VGPU_MSG_RESULT__VMIOP 0xFF00000a:0xFF000000 /* RW--D */ #define NV_VGPU_MSG_RESULT_VMIOP_INVAL 0xFF000001 /* RW--V */ #define NV_VGPU_MSG_RESULT_VMIOP_RESOURCE 0xFF000002 /* RW--V */ #define NV_VGPU_MSG_RESULT_VMIOP_RANGE 0xFF000003 /* RW--V */ @@ -126,8 +126,11 @@ #define NV_VGPU_MSG_RESULT_VMIOP_NOT_FOUND 0xFF000005 /* RW--V */ #define NV_VGPU_MSG_RESULT_VMIOP_NO_ADDRESS_SPACE 0xFF000006 /* RW--V */ #define NV_VGPU_MSG_RESULT_VMIOP_TIMEOUT 0xFF000007 /* RW--V */ +#define NV_VGPU_MSG_RESULT_VMIOP_NOT_ALLOWED_IN_CALLBACK 0xFF000008 /* RW--V */ +#define NV_VGPU_MSG_RESULT_VMIOP_ECC_MISMATCH 0xFF000009 /* RW--V */ +#define NV_VGPU_MSG_RESULT_VMIOP_NOT_SUPPORTED 0xFF00000a /* RW--V */ /* RPC-specific error codes */ -#define NV_VGPU_MSG_RESULT__RPC 0xFF100007:0xFF100000 /* RW--D */ +#define NV_VGPU_MSG_RESULT__RPC 0xFF100009:0xFF100000 /* RW--D */ #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION 0xFF100001 /* RW--V */ #define NV_VGPU_MSG_RESULT_RPC_INVALID_MESSAGE_FORMAT 0xFF100002 /* RW--V */ #define NV_VGPU_MSG_RESULT_RPC_HANDLE_NOT_FOUND 0xFF100003 /* RW--V */ @@ -136,6 +139,10 @@ #define NV_VGPU_MSG_RESULT_RPC_UNKNOWN_VMIOP_ERROR 0xFF100006 /* RW--V */ #define NV_VGPU_MSG_RESULT_RPC_RESERVED_HANDLE 0xFF100007 /* RW--V */ #define NV_VGPU_MSG_RESULT_RPC_CUDA_PROFILING_DISABLED 0xFF100008 /* RW--V */ +// This error code is used by plugin to notify the guest the that API control +// is recognized but not supported. It used by the guest to avoid printing +// error message about a failed API control. +#define NV_VGPU_MSG_RESULT_RPC_API_CONTROL_NOT_SUPPORTED 0xFF100009 /* RW--V */ /* RPC-specific code in result for incomplete request */ #define NV_VGPU_MSG_RESULT_RPC_PENDING 0xFFFFFFFF /* RW--V */ /* shared union field */ @@ -170,42 +177,47 @@ #define NV_VGPU_LOG_LEVEL_STATUS 0x00000003 /* RW--V */ #define NV_VGPU_LOG_LEVEL_DEBUG 0x00000004 /* RW--V */ -/* - * Enums specifying the BAR number that we are going to update its PDE - */ typedef enum { - NV_RPC_UPDATE_PDE_BAR_1, - NV_RPC_UPDATE_PDE_BAR_2, - NV_RPC_UPDATE_PDE_BAR_INVALID, -} NV_RPC_UPDATE_PDE_BAR_TYPE; + RPC_GR_BUFFER_TYPE_GRAPHICS = 0, + RPC_GR_BUFFER_TYPE_GRAPHICS_ZCULL = 1, + RPC_GR_BUFFER_TYPE_GRAPHICS_GRAPHICS_PM = 2, + RPC_GR_BUFFER_TYPE_COMPUTE_PREEMPT = 3, + RPC_GR_BUFFER_TYPE_GRAPHICS_PATCH = 4, + RPC_GR_BUFFER_TYPE_GRAPHICS_BUNDLE_CB = 5, + RPC_GR_BUFFER_TYPE_GRAPHICS_PAGEPOOL_GLOBAL = 6, + RPC_GR_BUFFER_TYPE_GRAPHICS_ATTRIBUTE_CB = 7, + RPC_GR_BUFFER_TYPE_GRAPHICS_RTV_CB_GLOBAL = 8, + RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_POOL = 9, + RPC_GR_BUFFER_TYPE_GRAPHICS_GFXP_CTRL_BLK = 10, + RPC_GR_BUFFER_TYPE_GRAPHICS_FECS_EVENT = 11, + RPC_GR_BUFFER_TYPE_GRAPHICS_PRIV_ACCESS_MAP = 12, + RPC_GR_BUFFER_TYPE_GRAPHICS_MAX = 13, +} RPC_GR_BUFFER_TYPE; /* - * UVM method stream guest pages operation + * Maximum entries that can be sent in a single pass of RPC. */ -typedef enum -{ - NV_RPC_GUEST_PAGE_MAP, - NV_RPC_GUEST_PAGE_UNMAP, -} NV_RPC_GUEST_PAGE_OPERATION; - -/* - * UVM method stream guest page size +#define VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC 512 + +/* Fetching NV2080_CTRL_GR_MAX_CTX_BUFFER_COUNT in single RPC mesaage + * causes RPC buffer to overflow. To accommodate, we will have to convert + * current RPC to multipass. But currently, RM allocates only + * (3 + GR_GLOBALCTX_BUFFER_COUNT) < 32 buffers and they accommodate in single + * RPC message size. Hence, not converting current RPC to multipass. + * and limiting the max buffer count per RPC to 32. */ -typedef enum -{ - NV_RPC_GUEST_PAGE_SIZE_4K, - NV_RPC_GUEST_PAGE_SIZE_UNSUPPORTED, -} NV_RPC_GUEST_PAGE_SIZE; +#define GR_MAX_RPC_CTX_BUFFER_COUNT 32 /* - * UVM paging channel VASPACE operation + * Enums specifying the BAR number that we are going to update its PDE */ typedef enum { - UVM_PAGING_CHANNEL_VASPACE_ALLOC, - UVM_PAGING_CHANNEL_VASPACE_FREE, -} UVM_PAGING_CHANNEL_VASPACE_OPERATION; + NV_RPC_UPDATE_PDE_BAR_1, + NV_RPC_UPDATE_PDE_BAR_2, + NV_RPC_UPDATE_PDE_BAR_INVALID, +} NV_RPC_UPDATE_PDE_BAR_TYPE; typedef struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS { @@ -221,13 +233,6 @@ typedef struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS } VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS; -/* - * Maximum guest pages that can be mapped for UVM method stream - */ -#define UVM_METHOD_STREAM_MAX_GUEST_PAGES_v1C_05 500 - -#define PMA_SCRUBBER_SHARED_BUFFER_MAX_GUEST_PAGES_v1F_0C 500 - /* * Maximum number of SMs that can be read in one RPC call to get error states */ diff --git a/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h b/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h index f9789daf26..76090de057 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_vgpu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,16 @@ #ifndef __vgpu_dev_nv_rpc_vgpu_h__ #define __vgpu_dev_nv_rpc_vgpu_h__ + +//****************************************************************************** +// +// Declarations for the RPC VGPU module. +// +// Description: +// This module declares the RPC interface functions/macros for VGPU. +// +//****************************************************************************** + static NV_INLINE void NV_RM_RPC_ALLOC_LOCAL_USER(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_ALLOC_VIDMEM(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_ALLOC_VIRTMEM(OBJGPU *pGpu, ...) { } @@ -36,29 +46,129 @@ static NV_INLINE void NV_RM_RPC_DESTROY_FB_SEGMENT(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_DEFERRED_API_CONTROL(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_REMOVE_DEFERRED_API(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_FREE_VIDMEM_VIRT(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_LOG(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_SET_GUEST_SYSTEM_INFO_EXT(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_GET_ENGINE_UTILIZATION(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_MAP_SEMA_MEMORY(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_UNMAP_SEMA_MEMORY(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_SET_SURFACE_PROPERTIES(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_CLEANUP_SURFACE(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_SWITCH_TO_VGA(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_TDR_SET_TIMEOUT_STATE(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_GET_CONSOLIDATED_STATIC_INFO(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_GET_CONSOLIDATED_GR_STATIC_INFO(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_GET_STATIC_PSTATE_INFO(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_UPDATE_PDE_2(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_TRANSLATE_GUEST_GPU_PTES(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_SET_SEMA_MEM_VALIDATION_STATE(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_RESET_CURRENT_GR_CONTEXT(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_GET_ENCODER_CAPACITY(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_GET_STATIC_INFO2(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_ALLOC_CONTEXT_DMA(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_GET_PLCABLE_ADDRESS_KIND(OBJGPU *pGpu, ...) { } static NV_INLINE void NV_RM_RPC_UPDATE_GPU_PDES(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_DISABLE_CHANNELS(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_SAVE_HIBERNATION_DATA(OBJGPU *pGpu, ...) { } -static NV_INLINE void NV_RM_RPC_RESTORE_HIBERNATION_DATA(OBJGPU *pGpu, ...) { } + +/* + * LOG RPC. This message produces a log line in the display plugin's log + * XXX: make this accept variable parameters like printf + */ +#define NV_RM_RPC_LOG(pgpu, logstr, loglevel) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pgpu); \ + if (pRpc != NULL) \ + rpcLog_HAL(pgpu, pRpc, logstr, loglevel); \ + } while(0) + +#define NV_RM_RPC_SET_GUEST_SYSTEM_INFO_EXT(pGpu, status) \ + do \ + { \ + /* VGPU only */ \ + OBJRPC *pRpc = GPU_GET_VGPU_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcSetGuestSystemInfoExt_HAL(pGpu,pRpc); \ + } while(0) + +#define NV_RM_RPC_SET_SURFACE_PROPERTIES(pGpu, hClient, pParams, bSkipCompare, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcSetSurfaceProperties_HAL(pGpu, pRpc, hClient, pParams, bSkipCompare); \ + } while (0) + +#define NV_RM_RPC_CLEANUP_SURFACE(pGpu, pParams, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcCleanupSurface_HAL(pGpu, pRpc, pParams); \ + } while (0) + +#define NV_RM_RPC_SWITCH_TO_VGA(pGpu, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcSwitchToVga_HAL(pGpu, pRpc); \ + } while (0) + +#define NV_RM_RPC_GET_STATIC_DATA(pGpu, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcGetStaticData_HAL(pGpu, pRpc); \ + } while (0) + +#define NV_RM_RPC_GET_CONSOLIDATED_GR_STATIC_INFO(pGpu, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcGetConsolidatedGrStaticInfo_HAL(pGpu, pRpc); \ + } while (0) + +#define NV_RM_RPC_GET_ENCODER_CAPACITY(pGpu, hClient, hObject, encoderCapacity, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcGetEncoderCapacity_HAL(pGpu, pRpc, hClient, hObject, encoderCapacity); \ + } while(0) + +#define NV_RM_RPC_DISABLE_CHANNELS(pGpu, bDisable, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcDisableChannels_HAL(pGpu, pRpc, bDisable); \ + } while(0) + +#define NV_RM_RPC_SAVE_HIBERNATION_DATA(pGpu, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcSaveHibernationData_HAL(pGpu, pRpc); \ + } while(0) + +#define NV_RM_RPC_RESTORE_HIBERNATION_DATA(pGpu, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcRestoreHibernationData_HAL(pGpu, pRpc); \ + } while(0) + +#define NV_RM_RPC_PERF_GET_LEVEL_INFO(pGpu, hClient, hObject, pParams, pPerfClkInfos, status) \ + do \ + { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + NV_ASSERT(pRpc != NULL); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcPerfGetLevelInfo_HAL(pGpu, pRpc, hClient, hObject, pParams, pPerfClkInfos); \ + else if (pRpc == NULL) \ + status = NV_ERR_INSUFFICIENT_RESOURCES; \ + } while(0) + +#define NV_RM_RPC_GET_ENGINE_UTILIZATION(pGpu, hClient, hObject, cmd, pParamStructPtr, paramSize, status) \ + do { \ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); \ + if ((status == NV_OK) && (pRpc != NULL)) \ + status = rpcGetEngineUtilizationWrapper_HAL(pGpu, pRpc, hClient, hObject, cmd, \ + pParamStructPtr, paramSize); \ + } while(0) \ #endif // __vgpu_dev_nv_rpc_vgpu_h__ diff --git a/src/nvidia/kernel/inc/vgpu/sdk-structures.h b/src/nvidia/kernel/inc/vgpu/sdk-structures.h index aae3e9b5e6..e4af860063 100644 --- a/src/nvidia/kernel/inc/vgpu/sdk-structures.h +++ b/src/nvidia/kernel/inc/vgpu/sdk-structures.h @@ -26,6 +26,7 @@ #define _RPC_SDK_STRUCTURES_H_ #include +#include #include #include #include @@ -39,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +54,7 @@ #include #include #include +#include #include #include @@ -84,9 +87,6 @@ typedef struct vmiopd_SM_info { #define OBJ_MAX_HEADS_v03_00 4 #define OBJ_MAX_HEADS_v24_08 8 - -#define MAX_NVDEC_ENGINES 5 // Maximum number of NVDEC engines - // NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES(256) / NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES(32) #define MAX_ITERATIONS_DEVICE_INFO_TABLE 8 @@ -136,6 +136,7 @@ typedef struct vmiopd_SM_info { #define NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03 240 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1B_05 8 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v1B_05 0x19 +#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07 0x1a #define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03 10 #define NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03 12 #define NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09 32 @@ -146,30 +147,12 @@ typedef struct vmiopd_SM_info { #define NV2080_CTRL_MAX_PCES_v21_0A 32 #define NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A 2 -//NV2080_CTRL_PERF_PSTATES_INFO data union enums for r535 code -#define NV2080_CTRL_PERF_PSTATE_VERSION_INVALID_v23_02 0x00 -#define NV2080_CTRL_PERF_PSTATE_VERSION_MODEL_10_v23_02 0xFE -#define NV2080_CTRL_PERF_PSTATE_VERSION_2X_v23_02 0x20 -#define NV2080_CTRL_PERF_PSTATE_VERSION_3X_v23_02 0xFD -#define NV2080_CTRL_PERF_PSTATE_VERSION_30_v23_02 0x30 -#define NV2080_CTRL_PERF_PSTATE_VERSION_35_v23_02 0x35 -#define NV2080_CTRL_PERF_PSTATE_VERSION_40_v23_02 0x40 -#define NV2080_CTRL_PERF_PSTATE_VERSION_PMU_INIT_1X_v23_02 0xFC -#define NV2080_CTRL_PERF_PSTATE_VERSION_70_v23_02 0x70 -#define NV2080_CTRL_PERF_PSTATE_VERSION_DISABLED_v23_02 NV_U8_MAX - -//NV2080_CTRL_PERF_PSTATES_INFO data union enums for chips_a -#define NV2080_CTRL_PERF_PSTATES_TYPE_BASE_v24_01 0x00U -#define NV2080_CTRL_PERF_PSTATES_TYPE_MODEL_10_v24_01 0x01U -#define NV2080_CTRL_PERF_PSTATES_TYPE_2X_v24_01 0x02U -#define NV2080_CTRL_PERF_PSTATES_TYPE_3X_v24_01 0x03U -#define NV2080_CTRL_PERF_PSTATES_TYPE_30_v24_01 0x04U -#define NV2080_CTRL_PERF_PSTATES_TYPE_35_v24_01 0x05U -#define NV2080_CTRL_PERF_PSTATES_TYPE_PMU_INIT_1X_v24_01 0x07U -#define NV2080_CTRL_PERF_PSTATES_TYPE_70_v24_01 0x08U -#define NV2080_CTRL_PERF_PSTATES_TYPE_50_v24_01 0x09U -#define NV2080_CTRL_PERF_PSTATES_TYPE_5X_v24_01 0x0AU -#define NV2080_CTRL_PERF_PSTATES_TYPE_INVALID_v24_01 NV2080_CTRL_BOARDOBJGRP_CLASS_TYPE_INVALID +// Host USM type +#define NV_VGPU_CONFIG_USM_TYPE_DEFAULT 0x00000000 /* R-XVF */ +#define NV_VGPU_CONFIG_USM_TYPE_NVS 0x00000001 /* R-XVF */ +#define NV_VGPU_CONFIG_USM_TYPE_QUADRO 0x00000002 /* R-XVF */ +#define NV_VGPU_CONFIG_USM_TYPE_GEFORCE 0x00000003 /* R-XVF */ +#define NV_VGPU_CONFIG_USM_TYPE_COMPUTE 0x00000004 /* R-XVF */ // Defined this intermediate RM-RPC structure for making RPC call from Guest as // we have the restriction of passing max 4kb of data to plugin and the @@ -203,43 +186,6 @@ struct pte_desc } pte_pde[] NV_ALIGN_BYTES(8); // PTE when IDR==0; PDE when IDR > 0 }; -/* - * VGPU_CACHED_RMCTRL_LIST - * - * This macro contains the list of RmCtrls which return static values and can be cached in - * guest RM. - * - * To cache a RmCtrl, add it to VGPU_CACHED_RMCTRL_LIST in the format: - * VGPU_CACHED_RMCTRL_ENTRY(, ) - */ - -#define VGPU_CACHED_RMCTRL_LIST \ - VGPU_CACHED_RMCTRL_ENTRY(NV2080_CTRL_CMD_PERF_VPSTATES_GET_INFO, NV2080_CTRL_PERF_VPSTATES_INFO) - -enum VGPU_CACHED_RMCTRL_INDICES -{ - #define VGPU_CACHED_RMCTRL_ENTRY(ctrlCmd,type) \ - VGPU_CACHED_RMCTRL_IDX_##ctrlCmd, - - VGPU_CACHED_RMCTRL_LIST - - #undef VGPU_CACHED_RMCTRL_ENTRY - - VGPU_CACHED_RMCTRL_IDX_COUNT, -}; - -typedef struct vgpu_cached_rmctrl -{ - void *ptr; - NvBool bCached; - NV_STATUS status; -}vgpu_cached_rmctrl; - -typedef struct vgpu_cached_rmctrl_list -{ - vgpu_cached_rmctrl vgpu_cached_rmctrls[VGPU_CACHED_RMCTRL_IDX_COUNT]; -} vgpu_cached_rmctrl_list; - typedef struct VGPU_BSP_CAPS { NvU8 capsTbl[NV0080_CTRL_BSP_CAPS_TBL_SIZE]; @@ -300,5 +246,218 @@ typedef struct VGPU_BSP_CAPS // NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT #define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08 13 +#define MAX_NVDEC_ENGINES_V1A_07 5 +#define MAX_NVDEC_ENGINES_V25_00 8 +#define NV0080_CTRL_MSENC_CAPS_TBL_SIZE_V25_00 4 +#define NV0080_CTRL_NVJPG_CAPS_TBL_SIZE_V18_0C 9 +#define NV0080_CTRL_BSP_CAPS_TBL_SIZE_V09_10 8 +#define NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS_V25_01 0x40 +#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES_V25_05 256 + +#define NV0080_CTRL_GR_CAPS_TBL_SIZE_v25_0E 23 +#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E 5 +#define RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E 13 +#define NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07 4 + +#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11 0x00000041 + +typedef struct _GPU_PARTITION_INFO +{ + NvU32 swizzId; + NvU32 grEngCount; + NvU32 veidCount; + NvU32 ceCount; + NvU32 gpcCount; + NvU32 virtualGpcCount; + NvU32 gfxGpcCount; + NvU32 gpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 virtualGpcsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 gfxGpcPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 veidsPerGr[NV2080_CTRL_GPU_MAX_SMC_IDS]; + NvU32 nvDecCount; + NvU32 nvEncCount; + NvU32 nvJpgCount; + NvU32 partitionFlag; + NvU32 smCount; + NvU32 nvOfaCount; + NvU64 memSize; + NvBool bValid; + NV2080_CTRL_GPU_PARTITION_SPAN span; + NvU64 validCTSIdMask; +} GPU_PARTITION_INFO; + +typedef struct _GPU_EXEC_PARTITION_INFO +{ + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NVC637_CTRL_EXEC_PARTITIONS_INFO execPartInfo[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} GPU_EXEC_PARTITION_INFO; + +typedef struct +{ + NvBool bGpuSupportsFabricProbe; +} VGPU_P2P_CAPABILITY_PARAMS; + +typedef struct _GPU_EXEC_SYSPIPE_INFO { + NvU32 execPartCount; + NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; + NvU32 syspipeId[NVC637_CTRL_MAX_EXEC_PARTITIONS]; +} GPU_EXEC_SYSPIPE_INFO; + +typedef struct _VGPU_STATIC_PROPERTIES +{ + NvU32 encSessionStatsReportingState; + NvBool bProfilingTracingEnabled; + NvBool bDebuggingEnabled; + NvU32 channelCount; + NvBool bPblObjNotPresent; //Valid only in case of GA100 SRIOV Heavy +} VGPU_STATIC_PROPERTIES; + +struct _vgpu_static_info +{ + NvU32 gfxpBufferSize[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; + NvU32 gfxpBufferAlignment[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL]; + NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS fbLtcInfoForFbp[MAX_FBPS]; + NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS mcStaticIntrTable; + NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS grZcullInfo; + NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS fifoDeviceInfoTable[MAX_ITERATIONS_DEVICE_INFO_TABLE]; + NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS fbDynamicBlacklistedPages[MAX_ITERATIONS_DYNAMIC_BLACKLIST]; + NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS fifoLatencyBufferSize[NV2080_ENGINE_TYPE_LAST]; + NV2080_CTRL_CE_GET_CAPS_V2_PARAMS ceCaps[NV2080_ENGINE_TYPE_COPY_SIZE]; + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS nvlinkCaps; + NV2080_CTRL_BUS_GET_INFO_V2_PARAMS busGetInfoV2; + NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS grSmIssueRateModifier; + NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS pcieSupportedGpuAtomics; + NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS ceGetAllCaps; + NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS c2cInfo; + NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS vgxSystemInfo; + NVA080_CTRL_VGPU_GET_CONFIG_PARAMS vgpuConfig; + NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS SKUInfo; + NvU64 engineList; + NvU32 pcieGpuLinkCaps; + NvBool bFlaSupported; + NV2080_CTRL_FLA_GET_RANGE_PARAMS flaInfo; + NvBool bPerRunlistChannelRamEnabled; + NvU32 subProcessIsolation; + VGPU_STATIC_PROPERTIES vgpuStaticProperties; + NvU64 maxSupportedPageSize; + GPU_PARTITION_INFO gpuPartitionInfo; // Default (Admin created) EXEC-I PARTITION INFO + NvBool bC2CLinkUp; + NvBool bSelfHostedMode; + NvBool bLocalEgmEnabled; + NvU32 localEgmPeerId; + NvU32 ceFaultMethodBufferDepth; + NvU8 grCapsBits[NV0080_CTRL_GR_CAPS_TBL_SIZE]; + NvBool bPerSubCtxheaderSupported; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS grInfoParams; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS ctxBuffInfo; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS ppcMaskParams; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS globalSmOrder; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS smIssueRateModifier; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS floorsweepMaskParams; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS fecsRecordSize; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS fecsTraceDefines; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS pdbTableParams; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS ropInfoParams; + NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS zcullInfoParams; + NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS ciProfiles; + NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS mcEngineNotificationIntrVectors; + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS eccStatus; + NvBool guestManagedHwAlloc; + NvU8 jpegCaps[NV0080_CTRL_NVJPG_CAPS_TBL_SIZE]; + NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS nvencCaps; + VGPU_BSP_CAPS vgpuBspCaps[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; + NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS constructedFalconInfo; + GPU_EXEC_PARTITION_INFO execPartitionInfo; + NV2080_CTRL_GPU_GET_GID_INFO_PARAMS gidInfo; + NvU64 fbTaxLength; + NvU64 fbLength; + NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS fbRegionInfoParams; + NvU32 grBufferSize[RPC_GR_BUFFER_TYPE_GRAPHICS_MAX]; + NvU32 fbioMask; + NvBool bSplitVasBetweenServerClientRm; + NvU8 adapterName[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU16 adapterName_Unicode[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvBool poisonFuseEnabled; + NvBool bAtsSupported; + NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS deviceInfoTable; + NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS memsysStaticConfig; + VGPU_P2P_CAPABILITY_PARAMS p2pCaps; + NvU32 fbBusWidth; + NvU32 fbpMask; + NvU32 ltcMask; + NvU32 ltsCount; + NvU32 sizeL2Cache; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS zbcTableSizes[NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT]; + NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS busGetPcieReqAtomicsCaps; + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS masterGetVfErrCntIntMsk; +}; + +typedef struct _vgpu_static_info VGPU_STATIC_INFO, VGPU_STATIC_INFO2; +typedef struct _vgpu_static_info VGPU_STATIC_DATA; + +typedef NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS VGPU_FB_GET_LTC_INFO_FOR_FBP[MAX_FBPS]; +typedef VGPU_BSP_CAPS VGPU_BSP_GET_CAPS[NV2080_CTRL_CMD_INTERNAL_MAX_BSPS]; +typedef NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS VGPU_FIFO_GET_DEVICE_INFO_TABLE[MAX_ITERATIONS_DEVICE_INFO_TABLE]; +typedef NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES[MAX_ITERATIONS_DYNAMIC_BLACKLIST]; +typedef NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS VGPU_GET_LATENCY_BUFFER_SIZE[NV2080_ENGINE_TYPE_LAST]; +typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS VGPU_CE_GET_CAPS_V2[NV2080_ENGINE_TYPE_COPY_SIZE]; + +typedef struct GSP_FIRMWARE GSP_FIRMWARE; + +ct_assert(NV2080_CTRL_GPU_ECC_UNIT_COUNT == NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06); +ct_assert(NV2080_ENGINE_TYPE_LAST == 0x40); +ct_assert(NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE == NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09); +ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERIES == NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00); +ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE == NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D); +ct_assert(NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES == NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D); +ct_assert(NV2080_CTRL_GRMGR_MAX_SMC_IDS == NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D); +ct_assert((NV0080_CTRL_GR_INFO_INDEX_MAX + 1) == NV0080_CTRL_GR_INFO_MAX_SIZE_24_07); +ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_ENGINES == NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04); +ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_SM == NV2080_CTRL_INTERNAL_GR_MAX_SM_v1E_03); +ct_assert(NV2080_CTRL_INTERNAL_GR_MAX_GPC == NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03); +ct_assert(NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT == + NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07); +ct_assert(NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT == NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03); +ct_assert(NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS == NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F); +ct_assert(NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL == NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03); +ct_assert(VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06 < NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03); +ct_assert(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE == NV2080_CTRL_FB_INFO_MAX_LIST_SIZE_24_0A); +ct_assert(NV2080_CTRL_GPU_MAX_SMC_IDS == 8); +ct_assert(NV2080_GPU_MAX_GID_LENGTH == 0x000000100); +ct_assert(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES == 16); +ct_assert(NV2080_GPU_MAX_NAME_STRING_LENGTH == 0x0000040); +ct_assert(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES == 256); +ct_assert(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX == NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX_v1E_09); +ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_DEVICES == 256); +ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES == 32); +ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES == 16); +ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA == 2); +ct_assert(NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN == 16); +ct_assert(NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES == 64); +ct_assert(NV2080_CTRL_CE_CAPS_TBL_SIZE == NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A); +ct_assert(NV2080_ENGINE_TYPE_COPY_SIZE == NV2080_ENGINE_TYPE_COPY_SIZE_v24_09); +ct_assert(NV2080_ENGINE_TYPE_NVENC_SIZE <= 4); +ct_assert(NV2080_ENGINE_TYPE_NVDEC_SIZE == 8); +ct_assert(NV2080_ENGINE_TYPE_NVJPEG_SIZE == 8); +ct_assert(NV2080_ENGINE_TYPE_GR_SIZE == 8); +ct_assert(NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE == NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D); +ct_assert(NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS == NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_v21_02); +ct_assert(VM_UUID_SIZE == VM_UUID_SIZE_v21_02); +ct_assert(NV2080_CTRL_MAX_PCES == NV2080_CTRL_MAX_PCES_v21_0A); +ct_assert(NV0080_CTRL_MSENC_CAPS_TBL_SIZE_V25_00 == NV0080_CTRL_MSENC_CAPS_TBL_SIZE); +ct_assert(MAX_NVDEC_ENGINES_V1A_07 <= NV2080_CTRL_CMD_INTERNAL_MAX_BSPS); +ct_assert(MAX_NVDEC_ENGINES_V25_00 == NV2080_CTRL_CMD_INTERNAL_MAX_BSPS); +ct_assert(NV0080_CTRL_NVJPG_CAPS_TBL_SIZE_V18_0C == NV0080_CTRL_NVJPG_CAPS_TBL_SIZE); +ct_assert(NV0080_CTRL_BSP_CAPS_TBL_SIZE_V09_10 == NV0080_CTRL_BSP_CAPS_TBL_SIZE); +ct_assert(NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS_V25_01 == NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS); +ct_assert(NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES_V25_05 == NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES); +ct_assert(NV0080_CTRL_GR_CAPS_TBL_SIZE_v25_0E == NV0080_CTRL_GR_CAPS_TBL_SIZE); +ct_assert(NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E == NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL); +ct_assert(RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E == RPC_GR_BUFFER_TYPE_GRAPHICS_MAX); +ct_assert(NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07 == NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT); +ct_assert(NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE_v25_11 == NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE); + #endif /*_RPC_SDK_STRUCTURES_H_*/ diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_events.h b/src/nvidia/kernel/inc/vgpu/vgpu_events.h index 2ba9cb04c1..2bc3c52af5 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_events.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_events.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,26 +42,20 @@ #include "ctrl/ctrl0080/ctrl0080nvjpg.h" #include "vgpu/rpc_headers.h" -#include "gpu/device/device.h" - #include "vgpu/sdk-structures.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "vgpu/dev_vgpu.h" typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR; typedef struct HOST_VGPU_DEVICE HOST_VGPU_DEVICE; typedef struct KERNEL_HOST_VGPU_DEVICE KERNEL_HOST_VGPU_DEVICE; typedef struct _object_vgpu OBJVGPU, *POBJVGPU; +typedef struct Device Device; // Create and destroy OBJVGPU *object NV_STATUS vgpuCreateObject(OBJGPU *pGpu); void vgpuDestructObject(OBJGPU *pGpu); -// Check if a VGPU event is pending -NvBool vgpuGetPendingEvent(OBJGPU *pGpu, THREAD_STATE_NODE *pThreadState); - -// Service VGPU events -void vgpuService(OBJGPU *pGpu); - // Overwrite registry keys void vgpuInitRegistryOverWrite(OBJGPU *pGpu); @@ -81,20 +75,193 @@ NV_STATUS vgpuIsCallingContextPlugin(OBJGPU *pGpu, NvBool *pIsCallingContextPlug // Get the GFID from DeviceInfo NV_STATUS vgpuGetGfidFromDeviceInfo(OBJGPU *pGpu, Device *pDevice, NvU32 *pGfid); -// Update Interrupt using shared memory through vGPU -void vgpuUpdateShmIntr(OBJGPU *pGpu, NvU32 offset, NvU32 value, THREAD_STATE_NODE *pThreadState); +// Check if a VGPU event is pending +NvBool vgpuGetPendingEvent(OBJGPU *pGpu, THREAD_STATE_NODE *pThreadState); + +// Service VGPU events +void vgpuService(OBJGPU *pGpu); + +#define GPU_GET_VGPU(pGpu) (NvVGPU_Table[gpuGetInstance(pGpu)]) + +#define NV_VGPU_MAX_INSTANCES 16 + +extern OBJVGPU *NvVGPU_Table[NV_VGPU_MAX_INSTANCES]; + +#define NV_VGPU_RPC_TIMEOUT_USEC(pGpu) (10 * 1000000) + +struct _vgpu_last_surface_info +{ + /* Stores last primary surface information in displayless mode */ + NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES last_surface; + /* cached headClient */ + NvHandle hClient; +}; +typedef struct _vgpu_last_surface_info VGPU_LAST_SURFACE_INFO; + +typedef struct vgpu_sysmem_segment_node { + NvU64 seg_start_address; // start page of the segment + NvU64 next_free_address; // Next free page of the segment + NvU32 page_count; // total number of pages in segment + NvU64 *pfn_list; // list of sysmem pages to which the segment is mapped + ListNode vgpuSysmemSegmentNode; +} VGPU_SYSMEM_SEGMENT_NODE, *VGPU_SYSMEM_SEGMENT_NODE_P; + +MAKE_INTRUSIVE_LIST(VGPU_SYSMEM_SEGMENT_NODE_LIST, VGPU_SYSMEM_SEGMENT_NODE, vgpuSysmemSegmentNode); + +typedef struct +{ + MEMORY_DESCRIPTOR *pMemDesc; + NvU32 *pMemory; + void *pPriv; + NvU64 pfn; +} VGPU_MEM_INFO; + +typedef struct +{ + VGPU_MEM_INFO mem; + NvU32 get; + NvU32 put; +} VGPU_MEM_RING_INFO; + +// +// Structure to hold hibernation state data +// +typedef struct vgpu_hibernation_data +{ + NvU32 size; + NvU8 *buffer; +}VGPU_HIBERNATION_DATA; + +// +// per-vGPU device instance +// +struct _object_vgpu +{ + VGPU_MEM_RING_INFO eventRing; + VGPU_MEM_RING_INFO sendRing; + VGPU_MEM_RING_INFO recvRing; + VGPU_MEM_INFO sharedMemory; + + VGPU_MEM_INFO gspCtrlBufInfo; + VGPU_MEM_INFO gspResponseBufInfo; + VGPU_MEM_INFO gspMessageBuf; + + // CPU plugin shared memory buffer + NvU32 *shared_memory; + + // Shared memory format for Guest RM + VGPU_GSP_CTRL_BUF_RM *gspCtrlBuf; + VGPU_GSP_RESPONSE_BUF_RM *gspResponseBuf; + + NvBool bGspPlugin; + NvBool bIsBar2Physical; + // Start offset of FB to use in Physical BAR2 mode + NvU64 allocFbOffsetBar2Physical; + + // Message sequence counter + NvU32 sequence_base; + NvU32 sequence_gsp_request; + + /* Stores last primary surface information in displayless mode */ + VGPU_LAST_SURFACE_INFO last_surface_info; + + /* Flag indicates whether VNC support enabled */ + NvBool bVncSupported; + /* Flag indicates current VNC state */ + NvBool bVncConnected; + /* Size of the staging buffer size */ + NvU32 staging_buffer_size; + /* Stores the timestamp of the latest FB usage update to host */ + NvU64 last_fb_update_timestamp; + /* Stores the value of the latest FB usage update to host */ + NvU64 last_fb_used_value; + /* GET/PUT pointer are inside the rings */ + NvBool gpInRing; + /* Get static information from host RM or plugin */ + VGPU_STATIC_INFO _vgpuStaticInfo; // Always use GPU_GET_STATIC_INFO accessor. + /* Stores whether interrupt using shared memory is active */ + NvBool shmInterruptActive; + /* Cache NV_VGPU_CONFIG_USM_TYPE value in the Guest */ + NvU32 vgpuConfigUsmType; + /* Cache ECC supported value in the Guest */ + NvBool bECCSupported; + /* Cache ECC status value in the Guest */ + NvBool bECCEnabled; + /* RPC fully initialized */ + NvBool bRpcInitialized; + /* GSP buffers initialized */ + NvBool bGspBuffersInitialized; + + /* RPC HAL objects */ + struct OBJRPC *pRpc; + + /* Stores whether page retirement is enabled or not */ + NvBool page_retirement_enabled; + /* GR engine index */ + NvU32 grIndex; + + VGPU_SYSMEM_SEGMENT_NODE_LIST listVgpuSysmemSegments; + + VGPU_HIBERNATION_DATA hibernationData; + +}; + +// +// (1) One bit represents one 4K sysmep page = 2^12 +// (2) One 4K page of bit map will contain 32K bits of (1). This represents 128MB of sysmem = 2^27 +// (3) One pass transfers 512 PFN of (2) from guest to plugin. This represents 64GB of sysmem = 2^36 +// (4) The provision is to have 16384 passes (NV_VGPU_SYSMEM_BITMAP_PASS_ID). +// That will cover up to 1 PB of guest PA. +// +#define MAX_PFNS_PER_4K_PAGE 512 +#define MAX_PFNS_PER_SYSMEM_BITMAP_NODE (16 * 1024 * 1024) // Max PFNs that can be tracked per node (64 GB memory) +#define MAX_SYSMEM_PFN_BITMAP_NODE 16384 + +#define _UINT64_SIZE 64 +#define _UINT64_SHIFT 6 + +#define PAGE_BITIDX64(n) ((n) & (_UINT64_SIZE - 1)) +#define PAGE_MAPIDX64(n) ((n) >> _UINT64_SHIFT) + +#define SETBIT64(bits, offset) (bits | NVBIT64(offset)) +#define CLEARBIT64(bits, offset) (bits & ~NVBIT64(offset)) + +typedef struct vgpu_sysmem_pfn_bitmap_node { + NvU64 *sysmemPfnMap; // BitMap to track the sysmem PFN allocation, shared with vGPU plugin, Size = 64GB + NvU64 *sysmemPfnMap_priv; + MEMORY_DESCRIPTOR *pMemDesc_sysmemPfnMap; // Describe shared page + NvU64 nodeStartPfn; + NvU64 nodeEndPfn; + NvU64 sizeInBytes; + NvU32 index; + ListNode listNode; // For intrusive lists +} VGPU_SYSMEM_PFN_BITMAP_NODE, * VGPU_SYSMEM_PFN_BITMAP_NODE_P; + +MAKE_INTRUSIVE_LIST(VGPU_SYSMEM_PFN_BITMAP_NODE_LIST, VGPU_SYSMEM_PFN_BITMAP_NODE, listNode); + +typedef struct vgpu_sysmem_pfn_info { + NvU64 guestMaxPfn; // Max guest PFN; Initialized for 64 GB RAM + NvU64 sizeInBytes; + NvU16 *sysmemPfnRefCount; // An array to store the Guest PFN ref count, Size = guestMaxPfn + NvBool bSysmemPfnInfoInitialized; + + NvU64 *sysmemPfnRing; // Ring to pass the PFNs of 4K chunks of shared memory + NvU64 *sysmemPfnRing_priv; + NvU64 sysmemPfnRing_pfn; + MEMORY_DESCRIPTOR *pMemDesc_sysmemPfnRing; // Describe shared page + + VGPU_SYSMEM_PFN_BITMAP_NODE_LIST listVgpuSysmemPfnBitmapHead; + VGPU_SYSMEM_PFN_BITMAP_NODE_P bitmapNodes[MAX_SYSMEM_PFN_BITMAP_NODE]; +} VGPU_SYSMEM_PFN_INFO; -// Check if SW stalling interrupt is pending, using shared memory -NV_STATUS vgpuShmIsSwPending(OBJGPU *pGpu, NvU32 *isSwPending); +typedef VGPU_SYSMEM_PFN_INFO* VGPU_SYSMEM_PFN_INFO_P; -// Check if non-stalling interrupts are enabled, using shared memory -NV_STATUS vgpuShmIsNonStallEnabled(OBJGPU *pGpu, NvU32 *isNonStallEnabled); +extern VGPU_SYSMEM_PFN_INFO vgpuSysmemPfnInfo; -// Check if non-stall interrupts are pening, using shared memory -NV_STATUS vgpuIsNonStallPending(OBJGPU *pGpu, PMC_ENGINE_BITVECTOR pEngines); +NV_STATUS nv0000CtrlCmdDiagProfileRpc(RmCtrlParams *pRmCtrlParams); +NV_STATUS nv0000CtrlCmdDiagDumpRpc(RmCtrlParams *pRmCtrlParams); -// Service non-stalling interrupts using shared memory -NV_STATUS vgpuServiceNonStall(OBJGPU *pGpu, PMC_ENGINE_BITVECTOR pEngines); +#define shm32(x) (*(pVGpu->shared_memory + ((x) / sizeof(NvU32)))) // Initialize and free event infrastructure NV_STATUS _setupEventInfrastructure(OBJGPU *pGpu, OBJVGPU *pVGpu); diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_util.h b/src/nvidia/kernel/inc/vgpu/vgpu_util.h new file mode 100644 index 0000000000..4bf085983b --- /dev/null +++ b/src/nvidia/kernel/inc/vgpu/vgpu_util.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +//****************************************************************************** +// +// Declarations for VGPU util functions. +// +//****************************************************************************** + +#ifndef __vgpu_util_h__ +#define __vgpu_util_h__ + +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_desc.h" + +#include "vgpu/vgpu_events.h" + +#include "vgpu/dev_vgpu.h" + +NV_STATUS vgpuAllocSysmemPfnBitMapNode(OBJGPU *pGpu, VGPU_SYSMEM_PFN_BITMAP_NODE_P *node, NvU32 index); +NvU64 vgpuGspSysmemPfnMakeBufferAddress(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pfn); +void vgpuFreeSysmemPfnBitMapNode(VGPU_SYSMEM_PFN_BITMAP_NODE_P node); +NV_STATUS vgpuUpdateSysmemPfnBitMap(OBJGPU *pGpu, MEMORY_DESCRIPTOR *pMemDesc, NvBool bAlloc); + +static inline NvBool vgpuIsGuestManagedHwAlloc(OBJGPU *pGpu) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + return pVSI && pVSI->guestManagedHwAlloc; +} + +#endif // __vgpu_util_h__ diff --git a/src/nvidia/kernel/inc/vgpu/vgpu_version.h b/src/nvidia/kernel/inc/vgpu/vgpu_version.h index a28a876eef..d6e3a09eac 100644 --- a/src/nvidia/kernel/inc/vgpu/vgpu_version.h +++ b/src/nvidia/kernel/inc/vgpu/vgpu_version.h @@ -30,13 +30,15 @@ #define RPC_VERSION_FROM_VGX_VERSION(major, minor) ( DRF_NUM(_RPC, _VERSION_NUMBER, _MAJOR, major) | \ DRF_NUM(_RPC, _VERSION_NUMBER, _MINOR, minor)) -#define VGX_MAJOR_VERSION_NUMBER 0x24 -#define VGX_MINOR_VERSION_NUMBER 0x0A +#define VGX_MAJOR_VERSION_NUMBER 0x25 +#define VGX_MINOR_VERSION_NUMBER 0x18 #define VGX_MAJOR_VERSION_NUMBER_VGPU_12_0 0x1A #define VGX_MINOR_VERSION_NUMBER_VGPU_12_0 0x18 #define VGX_MAJOR_VERSION_NUMBER_VGPU_13_0 0x1C #define VGX_MINOR_VERSION_NUMBER_VGPU_13_0 0x0A +#define VGX_MAJOR_VERSION_NUMBER_VGPU_16_0 0x23 +#define VGX_MAJOR_VERSION_NUMBER_VGPU_17_0 0x25 /** * This macro have the mapping between internal (RPC) and external version @@ -49,6 +51,7 @@ * 2. This is the first break in migration compatibility after a release. */ #define NV_VGPU_GRIDSW_INTERNAL_TO_EXTERNAL_VERSION_MAPPING \ + {{0x25, 0x0}, {0x25, 0x18}, {0x14, 0x1}}, \ {{0x24, 0x0}, {0x24, 0x0A}, {0x13, 0x1}}, \ {{0x23, 0x0}, {0x23, 0x05}, {0x12, 0x1}}, \ {{0x22, 0x0}, {0x22, 0x02}, {0x11, 0x1}}, \ @@ -96,7 +99,7 @@ /* WARNING: Should be updated with each vGPU release, if there is a break in * migration compatibility during the development of that release. */ -#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x13 +#define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR 0x14 #define NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR 0x1 /* WARNING: Should be updated with each vGPU release, if minimum supported diff --git a/src/nvidia/kernel/inc/vgpuapi.h b/src/nvidia/kernel/inc/vgpuapi.h new file mode 100644 index 0000000000..661560a643 --- /dev/null +++ b/src/nvidia/kernel/inc/vgpuapi.h @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "g_vgpuapi_nvoc.h" + +#ifndef _VGPUAPI_H_ +#define _VGPUAPI_H_ + +#include "core/core.h" +#include "rmapi/client.h" +#include "gpu/gpu_resource.h" +#include "rmapi/control.h" +#include "ctrl/ctrla080.h" + +NVOC_PREFIX(vgpuapi) class VgpuApi : GpuResource +{ +public: + NV_STATUS vgpuapiConstruct(VgpuApi *pVgpuApi, CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams) + : GpuResource(pCallContext, pParams); + void vgpuapiDestruct(VgpuApi *pVgpuApi); + + NODE node; + NvHandle handle; + NvHandle hDevice; + + // + // RMCTRL Exported methods -- Category: VGPU_DISPLAY + // + RMCTRL_EXPORT(NVA080_CTRL_CMD_VGPU_DISPLAY_SET_SURFACE_PROPERTIES, + RMCTRL_FLAGS(NON_PRIVILEGED)) + NV_STATUS vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties(VgpuApi *pVgpuApi, + NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES *pParams); + + RMCTRL_EXPORT(NVA080_CTRL_CMD_VGPU_DISPLAY_CLEANUP_SURFACE, + RMCTRL_FLAGS(NON_PRIVILEGED)) + NV_STATUS vgpuapiCtrlCmdVgpuDisplayCleanupSurface(VgpuApi *pVgpuApi, + NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams); + + // + // RMCTRL Exported methods -- Category: VGPU_OTHERS + // + RMCTRL_EXPORT(NVA080_CTRL_CMD_VGPU_GET_CONFIG, + RMCTRL_FLAGS(NON_PRIVILEGED)) + NV_STATUS vgpuapiCtrlCmdVGpuGetConfig(VgpuApi *pVgpuApi, + NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *pParams); + +}; + +#endif // _VGPUAPI_H_ diff --git a/src/nvidia/kernel/nvd/nv/dbgbuffer.c b/src/nvidia/kernel/nvd/nv/dbgbuffer.c index 801b0f28e2..b51ca753dd 100644 --- a/src/nvidia/kernel/nvd/nv/dbgbuffer.c +++ b/src/nvidia/kernel/nvd/nv/dbgbuffer.c @@ -23,7 +23,6 @@ #include "os/os.h" #include "dbgbuffer.h" -#include "gpu/subdevice/subdevice.h" #include "rmapi/client.h" NV_STATUS diff --git a/src/nvidia/kernel/nvd/nv/nvdctrl.c b/src/nvidia/kernel/nvd/nv/nvdctrl.c index 28c0b57926..f373ad834a 100644 --- a/src/nvidia/kernel/nvd/nv/nvdctrl.c +++ b/src/nvidia/kernel/nvd/nv/nvdctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -243,44 +243,10 @@ subdeviceCtrlCmdNvdSetNocatJournalData_IMPL rcdbSetNocatTdrReason(&pReportParams->nocatJournalData.tdrReason); break; - case NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_INSERT_RECORD: - portMemSet(&newEntry, 0, sizeof(newEntry)); - - // fill in the newEntry structure with the data from the insertData. - newEntry.recType = pReportParams->nocatJournalData.insertData.recType; - newEntry.pSource = (char *)pReportParams->nocatJournalData.insertData.source; - newEntry.bugcheck = pReportParams->nocatJournalData.insertData.bugcheck; - newEntry.subsystem = pReportParams->nocatJournalData.insertData.subsystem; - newEntry.errorCode = pReportParams->nocatJournalData.insertData.errorCode; - - // for now we are not supporting external events with diag buffers. - newEntry.pDiagBuffer = NULL; - newEntry.diagBufferLen = 0; - newEntry.pFaultingEngine = (char *)pReportParams->nocatJournalData.insertData.faultingEngine; - - // do we want to allow NULL strings? - if (FLD_TEST_DRF(2080_CTRL, _NOCAT_INSERT, _ALLOW_NULL_STR, _NO, - pReportParams->nocatJournalData.insertData.flags)) - { - if (pReportParams->nocatJournalData.insertData.source[0] != '\0') - { - // don't pass in a pointer to null source string. - newEntry.pSource = NULL; - } - if (pReportParams->nocatJournalData.insertData.faultingEngine[0] != '\0') - { - // don't pass in a pointer to null faulting engine string. - newEntry.pFaultingEngine = NULL; - } - } - pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_INSERT_RECORDS_IDX]++; - rcdbNocatInsertNocatError(NULL, &newEntry); - break; - case NV2080_CTRL_NOCAT_JOURNAL_DATA_TYPE_SET_TAG: if ((pReportParams->nocatJournalData.tagData.tag[0] == '\0') || FLD_TEST_DRF(2080_CTRL, _NOCAT_TAG, _CLEAR, _YES, - pReportParams->nocatJournalData.insertData.flags)) + pReportParams->nocatJournalData.tagData.flags)) { // clear the tag portMemSet(pRcdb->nocatJournalDescriptor.tag, 0, @@ -317,3 +283,41 @@ subdeviceCtrlCmdNvdSetNocatJournalData_IMPL return NV_OK; } +/*! +* @brief Set the NOCAT TDR data collected by KMD in the NOCAT journal record +* +* @returns NV_OK on success +*/ +NV_STATUS +subdeviceCtrlCmdNvdInsertNocatJournalRecord_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_NVD_INSERT_NOCAT_JOURNAL_RECORD_PARAMS* pRecordParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + Journal *pRcdb = SYS_GET_RCDB(pSys); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + NOCAT_JOURNAL_PARAMS newEntry; + + portMemSet(&newEntry, 0, sizeof(newEntry)); + + // fill in the newEntry structure with the data from the insertData. + newEntry.timestamp = pRecordParams->nocatJournalRecord.timestamp; + newEntry.recType = pRecordParams->nocatJournalRecord.recType; + newEntry.bugcheck = pRecordParams->nocatJournalRecord.bugcheck; + newEntry.pSource = (char *)pRecordParams->nocatJournalRecord.source; + newEntry.subsystem = pRecordParams->nocatJournalRecord.subsystem; + newEntry.errorCode = pRecordParams->nocatJournalRecord.errorCode; + newEntry.pDiagBuffer = pRecordParams->nocatJournalRecord.diagBuffer; + newEntry.diagBufferLen = pRecordParams->nocatJournalRecord.diagBufferLen; + newEntry.pFaultingEngine = (char *)pRecordParams->nocatJournalRecord.faultingEngine; + newEntry.tdrReason = pRecordParams->nocatJournalRecord.tdrReason; + + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX]++; + rcdbNocatInsertNocatError(pGpu, &newEntry); + + return NV_OK; +} + diff --git a/src/nvidia/kernel/vgpu/ampere/rpcga102.c b/src/nvidia/kernel/vgpu/ampere/rpcga102.c new file mode 100644 index 0000000000..26f25526e8 --- /dev/null +++ b/src/nvidia/kernel/vgpu/ampere/rpcga102.c @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file rpcga102.c + * @brief Ampere HAL routines + */ + +#include "nvtypes.h" +#include "nv_sriov_defines.h" +#include "gpu/gpu.h" +#include "gpu/gpu_access.h" +#include "published/ampere/ga102/dev_vm.h" + +void rpcVgpuGspWriteScratchRegister_GA102(OBJGPU *pGpu, NvU64 scratchRegVal) +{ + // Write the scratch register + GPU_VREG_WR32(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(NV_VF_SCRATCH_REGISTER_GUEST_RPC_HI), + NvU64_HI32(scratchRegVal)); + GPU_VREG_WR32(pGpu, + NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(NV_VF_SCRATCH_REGISTER_GUEST_RPC_LO), + NvU64_LO32(scratchRegVal)); +} + +void rpcVgpuGspRingDoorbell_GA102(OBJGPU *pGpu, NvU32 doorbellToken) +{ + // Ring the setup doorbell to send the request + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_DOORBELL, doorbellToken); +} + diff --git a/src/nvidia/kernel/vgpu/maxwell/rpcgm204.c b/src/nvidia/kernel/vgpu/maxwell/rpcgm204.c new file mode 100644 index 0000000000..8e18a9b3dc --- /dev/null +++ b/src/nvidia/kernel/vgpu/maxwell/rpcgm204.c @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +//****************************************************************************** +// +// Module: rpcgm204.c +// +// Description: +// This module implements RPC fuctions for maxwell family. +// +//****************************************************************************** + +#include "vgpu/rpc.h" +#include "vgpu/dev_vgpu.h" +#include "gpu/bif/kernel_bif.h" +#include "g_rpc_private.h" + +NV_STATUS rpcGetEngineUtilizationWrapper_GM204(OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void *pParamStructPtr, + NvU32 paramSize) + +{ + + NV_STATUS status; + + status = rpcGetEngineUtilization_HAL(pGpu, pRpc, hClient, hObject, cmd, + pParamStructPtr, paramSize); + + return status; +} + diff --git a/src/nvidia/kernel/vgpu/nv/objvgpu.c b/src/nvidia/kernel/vgpu/nv/objvgpu.c index b4c44f5d14..e8ff7d7020 100644 --- a/src/nvidia/kernel/vgpu/nv/objvgpu.c +++ b/src/nvidia/kernel/vgpu/nv/objvgpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,16 +22,32 @@ */ #include "core/core.h" +#include "core/locks.h" #include "os/os.h" #include "gpu/gpu.h" #include "vgpu/vgpu_version.h" #include "gpu/device/device.h" +#include "gpu/mem_mgr/mem_scrub.h" #include "rmapi/rs_utils.h" #include "virtualization/hypervisor/hypervisor.h" #include "virtualization/kernel_vgpu_mgr.h" +#include "vgpu/vgpu_events.h" +#include "vgpu/rpc.h" +#include "vgpu/vgpu_util.h" #include "nvRmReg.h" +OBJVGPU *NvVGPU_Table[NV_VGPU_MAX_INSTANCES]; + +static void vgpuGetUsmType(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + // Cache NV_VGPU_CONFIG_USM_TYPE field + { + // From GSP response buffer + pVGpu->vgpuConfigUsmType = pVGpu->gspResponseBuf->v1.usmType; + } +} + // Create vGpu object and initialize RPC infrastructure NV_STATUS vgpuCreateObject @@ -39,7 +55,80 @@ vgpuCreateObject OBJGPU *pGpu ) { - NV_STATUS rmStatus = NV_OK; + NV_STATUS rmStatus = NV_OK; + OBJVGPU *pVGpu; + NvU32 gpuMaskRelease = 0; + NvBool bLockAcquired = NV_FALSE; + + if (gpuGetInstance(pGpu) >= NV_VGPU_MAX_INSTANCES) + { + rmStatus = NV_ERR_NOT_SUPPORTED; + NV_PRINTF(LEVEL_ERROR, + "vGPU instances more than %d are not supported\n", + NV_VGPU_MAX_INSTANCES); + goto error_exit; + } + + if (NvVGPU_Table[gpuGetInstance(pGpu)] != NULL) + { + rmStatus = NV_ERR_INVALID_DEVICE; + NV_PRINTF(LEVEL_ERROR, ": %d vGPU instance already allocated\n", + gpuGetInstance(pGpu)); + goto error_exit; + } + + if (hypervisorIsType(OS_HYPERVISOR_HYPERV)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED, NV_FALSE); + } + + pVGpu = portMemAllocNonPaged(sizeof(OBJVGPU)); + if (pVGpu == NULL) + { + rmStatus = NV_ERR_NO_MEMORY; + NV_PRINTF(LEVEL_ERROR, + "cannot allocate memory for OBJVGPU (instance %d)\n", + gpuGetInstance(pGpu)); + goto error_exit; + } + + NvVGPU_Table[gpuGetInstance(pGpu)] = pVGpu; + + rmStatus = initRpcInfrastructure_VGPU(pGpu); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM_RPC: _initRpcInfrastructure: failed.\n"); + NV_ASSERT(0); + goto error_exit; + } + + if (!rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskRelease)) + { + // Acquire lock + NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuMaskRelease)); + bLockAcquired = NV_TRUE; + } + + NV_RM_RPC_GET_STATIC_DATA(pGpu, rmStatus); + + if (bLockAcquired && gpuMaskRelease != 0) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM_RPC: GET_STATIC_DATA : failed.\n"); + goto error_exit; + } + + vgpuGetUsmType(pGpu, pVGpu); + +error_exit: return rmStatus; } @@ -50,6 +139,30 @@ vgpuDestructObject OBJGPU *pGpu ) { + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + NV_STATUS rmStatus = NV_OK; + + // Sysmem PFN Bitmap teardown invokes RPC for GSP enabled + // case. Hence this needs to happen before RPC teardown + if (pVGpu != NULL) + teardownSysmemPfnBitMap(pGpu, pVGpu); + + NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, rmStatus, NV_FALSE, NV_FALSE, 0); + + { + rmStatus = freeRpcInfrastructure_VGPU(pGpu); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: _freeRpcInfrastructure: failed.\n"); + NV_ASSERT(0); + } + } + + vgpuGspTeardownBuffers(pGpu); + + portMemFree(pVGpu); + NvVGPU_Table[gpuGetInstance(pGpu)] = NULL; } // Overwrite registry keys @@ -78,6 +191,17 @@ vgpuInitRegistryOverWrite } } + if (IS_VIRTUAL(pGpu)) + { + if (NV_OK != osReadRegistryDword(pGpu, + NV_REG_STR_RM_WATCHDOG_TIMEOUT, + &data)) + { + osWriteRegistryDword(pGpu, NV_REG_STR_RM_WATCHDOG_TIMEOUT, 2); + } + + } + NvU32 min = 0, max = 0; /* Default user provided vGPU supported range is set to be the @@ -152,9 +276,42 @@ vgpuGetCallingContextHostVgpuDevice { *ppHostVgpuDevice = NULL; + Device *pDevice = NULL; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + if (IS_GSP_CLIENT(pGpu)) return NV_ERR_NOT_SUPPORTED; + // This check is needed to handle cases where this function was called + // without client (for example, during adapter initialization). + if (resservGetTlsCallContext() == NULL) + { + return NV_OK; + } + + pDevice = vgpuGetCallingContextDevice(pGpu); + if (pDevice == NULL) + { + // There are several places where this function can be called without TLS call context + // in SRIOV-heavy mode. Return error only for SRIOV-full. + NV_ASSERT_OR_RETURN(!gpuIsSriovEnabled(pGpu) || IS_SRIOV_HEAVY(pGpu), NV_ERR_OBJECT_NOT_FOUND); + return NV_OK; + } + + pKernelHostVgpuDevice = pDevice->pKernelHostVgpuDevice; + + NV_ASSERT_OR_RETURN((pKernelHostVgpuDevice != NULL) == + !!(pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE), + NV_ERR_INVALID_STATE); + + if (pKernelHostVgpuDevice != NULL) + { + if (pKernelHostVgpuDevice->pHostVgpuDevice == NULL) + return NV_ERR_INVALID_STATE; + + *ppHostVgpuDevice = pKernelHostVgpuDevice->pHostVgpuDevice; + } + return NV_OK; } diff --git a/src/nvidia/kernel/vgpu/nv/rpc.c b/src/nvidia/kernel/vgpu/nv/rpc.c index 18189004e7..458b69d476 100644 --- a/src/nvidia/kernel/vgpu/nv/rpc.c +++ b/src/nvidia/kernel/vgpu/nv/rpc.c @@ -28,9 +28,6 @@ // //****************************************************************************** -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED - #include "os/os.h" #include "core/system.h" #include "core/locks.h" @@ -57,6 +54,34 @@ #include "os/os.h" #include "objtmr.h" #include "lib/base_utils.h" +#if defined(NV_UNIX) && RMCFG_FEATURE_GSP_CLIENT_RM +#include "os-interface.h" +#endif + +#include "nv_sriov_defines.h" +#include "nvRmReg.h" +#include "vgpu/dev_vgpu.h" +#include "vgpu/vgpu_util.h" +#include "gpu/device/device.h" +#include "gpu/mem_mgr/context_dma.h" +#include "gpu/mem_mgr/heap.h" +#include "gpu/mem_mgr/mem_scrub.h" +#include "kernel/gpu/gr/kernel_graphics_object.h" +#include "gpu/fifo/kernel_channel.h" +#include "kernel/gpu/fifo/kernel_channel_group_api.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "gpu/bus/kern_bus.h" + +#include "class/clc4c0.h" // VOLTA_COMPUTE_B, not known to RMCFG/Classes.pm +#include "class/cl85b5sw.h" // GT212_DMA_COPY alloc parameters +#include "ctrl/ctrl0000/ctrl0000gpuacct.h" +#include "ctrl/ctrl0000/ctrl0000gpu.h" +#include "ctrl/ctrl0000/ctrl0000system.h" +#include "ctrl/ctrl83de.h" +#include "ctrl/ctrla0bc.h" +#include "ctrl/ctrla0bd.h" +#include "ctrl/ctrlc36f.h" +#include "ctrl/ctrl503c.h" #include "gpu/conf_compute/conf_compute.h" @@ -65,7 +90,6 @@ #undef SDK_ALL_CLASSES_INCLUDE_FULL_HEADER #include "nverror.h" - #define RPC_STRUCTURES #define RPC_GENERIC_UNION #include "g_rpc-structures.h" @@ -85,6 +109,17 @@ #include "gpu/gsp/message_queue_priv.h" static NvBool bProfileRPC = NV_FALSE; +static NvU64 startTimeInNs, endTimeInNs, elapsedTimeInNs; + +static NV_STATUS updateHostVgpuFbUsage(OBJGPU *pGpu, NvHandle hClient, NvHandle hDevice, + NvHandle hSubdevice); + +static NV_STATUS _rpcSendMessage_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC); +static NV_STATUS _rpcRecvPoll_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC, NvU32 expectedFunc); +void setGuestEccStatus(OBJGPU *pGpu); + +typedef NV_STATUS dma_control_copy_params_to_rpc_buffer_v(NvU32 cmd, void *Params, void *params_in); +typedef NV_STATUS dma_control_copy_params_from_rpc_buffer_v(NvU32 cmd, void *params_in, void *Params); typedef struct rpc_meter_list { @@ -101,6 +136,14 @@ typedef struct rpc_meter_head static RPC_METER_HEAD rpcMeterHead; static NvU32 rpcProfilerEntryCount; +typedef struct rpc_dump_internal_rec +{ + RPC_METER_LIST *pHead; + NvU32 entryOffset; +} RPC_DUMP_REC; + +static RPC_DUMP_REC rpcDumpRec; + typedef struct rpc_vgx_version { NvU32 majorNum; @@ -108,1142 +151,8427 @@ typedef struct rpc_vgx_version } RPC_VGX_VERSION; static RPC_VGX_VERSION rpcVgxVersion; + static NvBool bSkipRpcVersionHandshake = NV_FALSE; -void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion) +// SYSMEM pfn bitMap info +VGPU_SYSMEM_PFN_INFO vgpuSysmemPfnInfo = {.bitmapNodes = {NULL}}; + +#define RESMAN_BUILD +#define BUILD_LEGACY_RPCS +#define BUILD_COMMON_RPCS +#include "vgpu/rm_plugin_shared_code.h" +#undef BUILD_COMMON_RPCS +#undef BUILD_LEGACY_RPCS +#undef RESMAN_BUILD + +void vgpuUpdateGuestOsType(OBJGPU *pGpu, OBJVGPU *pVGpu) { - OBJHAL *pHal = GPU_GET_HAL(pGpu); - PMODULEDESCRIPTOR pMod = objhalGetModuleDescriptor(pHal); - IGRP_IP_VERSIONS_TABLE_INFO info = {0}; +#if defined(NVCPU_X86_64) + const NvU32 guest_os_type_arch = NV_VGPU_GUEST_OS_TYPE_ARCH_X86_64; +#elif defined(NVCPU_AARCH64) + const NvU32 guest_os_type_arch = NV_VGPU_GUEST_OS_TYPE_ARCH_AARCH64; +#else + const NvU32 guest_os_type_arch = NV_VGPU_GUEST_OS_TYPE_ARCH_INVALID; +#endif - _objrpcAssignIpVersion(pRpc, ipVersion); - pMod->pHalSetIfaces->rpcHalIfacesSetupFn(&pRpc->_hal); - info.pGpu = pGpu; - info.pDynamic = (void*) pRpc; - rpc_iGrp_ipVersions_getInfo_HAL(pRpc, &info); - info.ifacesWrapupFn(&info); +#if defined(NV_UNIX) + const NvU32 guest_os_type_os = NV_VGPU_GUEST_OS_TYPE_OS_LINUX; +#else + const NvU32 guest_os_type_os = NV_VGPU_GUEST_OS_TYPE_OS_INVALID; +#endif + const NvU32 guest_os_page_size = nvLogBase2(osGetPageSize()) - 12; + + NvU32 guest_os = DRF_NUM(_VGPU, _GUEST_OS_TYPE, _ARCH, guest_os_type_arch) | + DRF_NUM(_VGPU, _GUEST_OS_TYPE, _OS, guest_os_type_os) | + DRF_NUM(_VGPU, _GUEST_OS_TYPE, _PAGE_SIZE, guest_os_page_size); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + pVGpu->gspCtrlBuf->v1.guestOsType = guest_os; + } } -NV_STATUS rpcConstruct_IMPL(OBJGPU *pGpu, OBJRPC *pRpc) +static NV_STATUS +_allocRpcMemDescSysmem( + OBJGPU *pGpu, + NvU64 size, + NvBool bContig, + NvU32 memdescFlag, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer, + void **ppMemPriv) { - NV_STATUS rmStatus = NV_OK; - return rmStatus; + NV_STATUS status = NV_OK; + + NV_ASSERT_OK_OR_RETURN( + memdescCreate(ppMemDesc, + pGpu, + size, + 0, + bContig, + ADDR_SYSMEM, + NV_MEMORY_CACHED, + memdescFlag)); + + memdescSetFlag(*ppMemDesc, MEMDESC_FLAGS_KERNEL_MODE, NV_TRUE); + + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_104, + (*ppMemDesc)); + NV_ASSERT_OK_OR_GOTO( + status, + status, + fail_alloc); + + NV_ASSERT_OK_OR_GOTO( + status, + memdescMapOld(*ppMemDesc, + 0, // Offset + size, + memdescGetFlag(*ppMemDesc, MEMDESC_FLAGS_KERNEL_MODE), + NV_PROTECT_READ_WRITE, + ppMemBuffer, + ppMemPriv), + fail_map); + + return NV_OK; + +fail_map: + memdescFree(*ppMemDesc); +fail_alloc: + memdescDestroy(*ppMemDesc); + + return status; } -void rpcDestroy_IMPL(OBJGPU *pGpu, OBJRPC *pRpc) +static void +_freeRpcMemDescSysmem( + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer, + void **ppMemPriv) { + memdescUnmapOld(*ppMemDesc, + memdescGetFlag(*ppMemDesc, MEMDESC_FLAGS_KERNEL_MODE), + 0, + *ppMemBuffer, + *ppMemPriv); + memdescFree(*ppMemDesc); + memdescDestroy(*ppMemDesc); } -NV_STATUS rpcSendMessage_IMPL(OBJGPU *pGpu, OBJRPC *pRpc) +static NV_STATUS +_allocRpcMemDescFbBar2Virtual( + OBJGPU *pGpu, + NvU64 size, + NvBool bContig, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer) { - NV_PRINTF(LEVEL_ERROR, "virtual function not implemented.\n"); - return NV_ERR_NOT_SUPPORTED; + NV_STATUS status = NV_OK; + + NV_ASSERT_OK_OR_RETURN( + memdescCreate(ppMemDesc, + pGpu, + size, + RM_PAGE_SIZE, + bContig, + ADDR_FBMEM, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE)); + + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_105, + (*ppMemDesc)); + NV_ASSERT_OK_OR_GOTO( + status, + status, + fail_alloc); + + *ppMemBuffer = kbusMapRmAperture_HAL(pGpu, *ppMemDesc); + if (*ppMemBuffer == NULL) + { + NV_PRINTF(LEVEL_ERROR, "RPC: BAR2 map failed\n"); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto fail_map; + } + + return NV_OK; + +fail_map: + memdescFree(*ppMemDesc); +fail_alloc: + memdescDestroy(*ppMemDesc); + + return status; } -NV_STATUS rpcRecvPoll_IMPL(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 expectedFunc) +static void +_freeRpcMemDescFbBar2Virtual( + OBJGPU *pGpu, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer) { - NV_PRINTF(LEVEL_ERROR, "virtual function not implemented.\n"); - return NV_ERR_NOT_SUPPORTED; + kbusUnmapRmAperture_HAL(pGpu, *ppMemDesc, ppMemBuffer, NV_TRUE); + memdescFree(*ppMemDesc); + memdescDestroy(*ppMemDesc); } -static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc) +static NV_STATUS +_allocRpcMemDescFbBar2Physical( + OBJGPU *pGpu, + NvU64 size, + NvBool bContig, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer) { - NV_STATUS status = NV_OK; - RPC_METER_LIST *pNewEntry = NULL; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); - // should not be called in broadcast mode - NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); + NV_ASSERT_OK_OR_RETURN( + memdescCreate(ppMemDesc, + pGpu, + size, + RM_PAGE_SIZE, + bContig, + ADDR_FBMEM, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE)); - if (bProfileRPC) - { - // Create a new entry for our RPC profiler - pNewEntry = portMemAllocNonPaged(sizeof(RPC_METER_LIST)); - if (pNewEntry == NULL) - { - NV_PRINTF(LEVEL_ERROR, "failed to allocate RPC meter memory!\n"); - NV_ASSERT(0); - return NV_ERR_INSUFFICIENT_RESOURCES; - } + memdescDescribe(*ppMemDesc, + ADDR_FBMEM, + pVGpu->allocFbOffsetBar2Physical, + size); - portMemSet(pNewEntry, 0, sizeof(RPC_METER_LIST)); + pVGpu->allocFbOffsetBar2Physical += size; - if (rpcMeterHead.pHead == NULL) - rpcMeterHead.pHead = pNewEntry; - else - rpcMeterHead.pTail->pNext = pNewEntry; + *ppMemBuffer = kbusCpuOffsetInBar2WindowGet(pGpu, pKernelBus, *ppMemDesc); - rpcMeterHead.pTail = pNewEntry; + return NV_OK; +} - pNewEntry->rpcData.rpcDataTag = vgpu_rpc_message_header_v->function; +static void +_freeRpcMemDescFbBar2Physical( + MEMORY_DESCRIPTOR **ppMemDesc) +{ + memdescDestroy(*ppMemDesc); +} - rpcProfilerEntryCount++; +static NV_STATUS +_allocRpcMemDescFb( + OBJGPU *pGpu, + NvU64 size, + NvBool bContig, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer) +{ + NV_STATUS status; + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); - osGetPerformanceCounter(&pNewEntry->rpcData.startTimeInNs); + if (pVGpu->bIsBar2Physical) + { + status = _allocRpcMemDescFbBar2Physical(pGpu, size, bContig, ppMemDesc, ppMemBuffer); + } + else + { + status = _allocRpcMemDescFbBar2Virtual(pGpu, size, bContig, ppMemDesc, ppMemBuffer); } - // For HCC, cache expectedFunc value before encrypting. - NvU32 expectedFunc = vgpu_rpc_message_header_v->function; + return status; +} - status = rpcSendMessage(pGpu, pRpc); - if (status != NV_OK) +static void +_freeRpcMemDescFb( + OBJGPU *pGpu, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + if (pVGpu->bIsBar2Physical) { - NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, - "rpcSendMessage failed with status 0x%08x for fn %d!\n", - status, vgpu_rpc_message_header_v->function); - // - // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC - // buffers full and not being serviced) can make things worse, i.e. turn RPC - // failures into app hangs such that even nvidia-bug-report.sh gets stuck. - // Avoid this for now while still returning the correct error in other cases. - // - return (status == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : status; + _freeRpcMemDescFbBar2Physical(ppMemDesc); + } + else + { + _freeRpcMemDescFbBar2Virtual(pGpu, ppMemDesc, ppMemBuffer); + } +} + +NV_STATUS +_allocRpcMemDesc( + OBJGPU *pGpu, + NvU64 size, + NvBool bContig, + NV_ADDRESS_SPACE addrSpace, + NvU32 memFlags, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer, + void **ppMemPriv) +{ + NV_STATUS status; + + *ppMemDesc = NULL; + *ppMemBuffer = NULL; + *ppMemPriv = NULL; + + switch (addrSpace) + { + case ADDR_SYSMEM: + status = _allocRpcMemDescSysmem(pGpu, size, bContig, memFlags, ppMemDesc, ppMemBuffer, ppMemPriv); + break; + case ADDR_FBMEM: + status = _allocRpcMemDescFb(pGpu, size, bContig, ppMemDesc, ppMemBuffer); + break; + default: + NV_PRINTF(LEVEL_ERROR, "RPC: unknown memory address space %d\n", addrSpace); + status = NV_ERR_NOT_SUPPORTED; + break; } - // Use cached expectedFunc here because vgpu_rpc_message_header_v is encrypted for HCC. - status = rpcRecvPoll(pGpu, pRpc, expectedFunc); if (status != NV_OK) { - if (status == NV_ERR_TIMEOUT) - { - NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, - "rpcRecvPoll timedout for fn %d!\n", - vgpu_rpc_message_header_v->function); - } - else - { - NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, - "rpcRecvPoll failed with status 0x%08x for fn %d!\n", - status, vgpu_rpc_message_header_v->function); - } - return status; + *ppMemPriv = NULL; + *ppMemBuffer = NULL; + *ppMemDesc = NULL; } - if (bProfileRPC) - osGetPerformanceCounter(&pNewEntry->rpcData.endTimeInNs); + return status; +} - // Now check if RPC really succeeded - if (vgpu_rpc_message_header_v->rpc_result != NV_VGPU_MSG_RESULT_SUCCESS) - { - NV_PRINTF(LEVEL_WARNING, "RPC failed with status 0x%08x for fn %d!\n", - vgpu_rpc_message_header_v->rpc_result, - vgpu_rpc_message_header_v->function); +void +_freeRpcMemDesc( + OBJGPU *pGpu, + MEMORY_DESCRIPTOR **ppMemDesc, + void **ppMemBuffer, + void **ppMemPriv) +{ + NV_ADDRESS_SPACE addrSpace; + // Already free, return early + if (*ppMemDesc == NULL) + return; - if (vgpu_rpc_message_header_v->rpc_result < DRF_BASE(NV_VGPU_MSG_RESULT__VMIOP)) - return vgpu_rpc_message_header_v->rpc_result; + addrSpace = memdescGetAddressSpace(*ppMemDesc); - return NV_ERR_GENERIC; + switch (addrSpace) + { + case ADDR_SYSMEM: + _freeRpcMemDescSysmem(ppMemDesc, ppMemBuffer, ppMemPriv); + break; + case ADDR_FBMEM: + _freeRpcMemDescFb(pGpu, ppMemDesc, ppMemBuffer); + break; + default: + NV_PRINTF(LEVEL_ERROR, "RPC: unknown memory address space %d\n", addrSpace); + break; } - return NV_OK; + *ppMemPriv = NULL; + *ppMemBuffer = NULL; + *ppMemDesc = NULL; } -static NV_STATUS _issueRpcAsync(OBJGPU *pGpu, OBJRPC *pRpc) +static void _freeSharedMemory(OBJGPU *pGpu, OBJVGPU *pVGpu) { - NV_STATUS status; + _freeRpcMemDesc(pGpu, + &pVGpu->sharedMemory.pMemDesc, + (void**)&pVGpu->shared_memory, + (void**)&pVGpu->sharedMemory.pPriv); +} - // should not be called in broadcast mode - NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); +static NV_STATUS _allocSharedMemory(OBJGPU *pGpu, OBJVGPU *pVGpu, NV_ADDRESS_SPACE addrSpace, NvU32 memFlags) +{ + NV_STATUS status; - status = rpcSendMessage(pGpu, pRpc); + status = _allocRpcMemDesc(pGpu, + RM_PAGE_SIZE, + NV_MEMORY_CONTIGUOUS, + addrSpace, + memFlags, + &pVGpu->sharedMemory.pMemDesc, + (void**)&pVGpu->shared_memory, + (void**)&pVGpu->sharedMemory.pPriv); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "rpcSendMessage failed with status 0x%08x for fn %d!\n", - status, vgpu_rpc_message_header_v->function); - NV_ASSERT(0); - // - // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC - // buffers full and not being serviced) can make things worse, i.e. turn RPC - // failures into app hangs such that even nvidia-bug-report.sh gets stuck. - // Avoid this for now while still returning the correct error in other cases. - // - return (status == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : status; + NV_PRINTF(LEVEL_ERROR, "RPC: Shared memory setup failed: 0x%x\n", status); + return status; } return NV_OK; } -static NV_STATUS _issueRpcLarge -( - OBJGPU *pGpu, - OBJRPC *pRpc, - NvU32 bufSize, - const void *pBuffer, - NvBool bBidirectional, - NvBool bWait -) +// Different address space configs on different arch +// AD10x +// - Memory is always allocated on FBMEM +// GH100+ +// - Memory is allocated on SYSMEM when BAR2 is in physical mode +// - memory is allocated on FBMEM when BAR2 switches virtual mode +// GH180 +// - Memory is allocated on SYSMEM initially +// - Memory is allocated on FBMEM after C2C mapping is completed +// +static NV_STATUS _setupGspSharedMemory(OBJGPU *pGpu, OBJVGPU *pVGpu) { - NvU8 *pBuf8 = (NvU8 *)pBuffer; - NV_STATUS nvStatus = NV_OK; - NvU32 expectedFunc = vgpu_rpc_message_header_v->function; - NvU32 entryLength; - NvU32 remainingSize = bufSize; - NvU32 recordCount = 0; - - // should not be called in broadcast mode - NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); + NV_ADDRESS_SPACE addressSpace = ADDR_FBMEM; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 memFlags = 0; - // Copy the initial buffer - entryLength = NV_MIN(bufSize, pRpc->maxRpcSize); + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + memFlags = MEMDESC_FLAGS_CPU_ONLY; - if ((NvU8 *)vgpu_rpc_message_header_v != pBuf8) - portMemCopy(vgpu_rpc_message_header_v, entryLength, pBuf8, entryLength); + if (IsGH100orBetter(pGpu) && (!kbusIsBar2Initialized(pKernelBus))) + addressSpace = ADDR_SYSMEM; - // Set the correct length for this queue entry. - vgpu_rpc_message_header_v->length = entryLength; + NV_ASSERT_OK_OR_RETURN(_allocSharedMemory(pGpu, pVGpu, addressSpace, memFlags)); - nvStatus = rpcSendMessage(pGpu, pRpc); - if (nvStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "rpcSendMessage failed with status 0x%08x for fn %d!\n", - nvStatus, expectedFunc); - NV_ASSERT(0); - // - // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC - // buffers full and not being serviced) can make things worse, i.e. turn RPC - // failures into app hangs such that even nvidia-bug-report.sh gets stuck. - // Avoid this for now while still returning the correct error in other cases. - // - return (nvStatus == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : nvStatus; - } - remainingSize -= entryLength; - pBuf8 += entryLength; + pVGpu->sharedMemory.pfn = memdescGetPte(pVGpu->sharedMemory.pMemDesc, AT_GPU, 0) >> RM_PAGE_SHIFT; - // Copy the remaining buffers - entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v); - while (remainingSize != 0) - { - if (entryLength > remainingSize) - entryLength = remainingSize; + // shm interrupt is not used in full SR-IOV + pVGpu->shmInterruptActive = NV_FALSE; - ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); - if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED)) - { - // Zero out the entire RPC message header to clear the state of previous chunk. - portMemSet(vgpu_rpc_message_header_v, 0, sizeof(rpc_message_header_v)); - } + // Initialize shared memory page. + portMemSet(pVGpu->shared_memory, 0, RM_PAGE_SIZE); - portMemCopy(rpc_message, entryLength, pBuf8, entryLength); + return NV_OK; +} - // Set the correct length for this queue entry. - vgpu_rpc_message_header_v->length = entryLength + sizeof(rpc_message_header_v); - vgpu_rpc_message_header_v->function = NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD; +static void _teardownGspSharedMemory(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + pVGpu->shmInterruptActive = NV_FALSE; - nvStatus = rpcSendMessage(pGpu, pRpc); - if (nvStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "rpcSendMessage failed with status 0x%08x for fn %d continuation record (remainingSize=0x%x)!\n", - nvStatus, expectedFunc, remainingSize); - NV_ASSERT(0); - // - // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC - // buffers full and not being serviced) can make things worse, i.e. turn RPC - // failures into app hangs such that even nvidia-bug-report.sh gets stuck. - // Avoid this for now while still returning the correct error in other cases. - // - return (nvStatus == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : nvStatus; - } + _freeSharedMemory(pGpu, pVGpu); +} - remainingSize -= entryLength; - pBuf8 += entryLength; - recordCount++; +static NV_STATUS _initSysmemPfnRing(OBJGPU *pGpu) +{ + NV_STATUS status = NV_OK; + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 memFlags = 0; + + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + memFlags = MEMDESC_FLAGS_CPU_ONLY; + + status = _allocRpcMemDesc(pGpu, + RM_PAGE_SIZE, + NV_MEMORY_CONTIGUOUS, + ADDR_SYSMEM, + memFlags, + &vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing, + (void**)&vgpuSysmemPfnInfo.sysmemPfnRing, + (void**)&vgpuSysmemPfnInfo.sysmemPfnRing_priv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: PFN ring setup failed: 0x%x\n", status); + return status; } - if (!bWait) + vgpuSysmemPfnInfo.sysmemPfnRing_pfn = memdescGetPte(vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing, AT_GPU, 0) >> RM_PAGE_SHIFT; + + if (pVGpu->bGspPlugin) { - // In case of Async RPC, we are done here. - return nvStatus; + pVGpu->gspCtrlBuf->v1.sysmemBitMapTablePfn = + vgpuGspSysmemPfnMakeBufferAddress(vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing, + vgpuSysmemPfnInfo.sysmemPfnRing_pfn); } - // Always receive at least one.. + return status; +} + +static void _freeSysmemPfnRing(OBJGPU *pGpu) +{ + + _freeRpcMemDesc(pGpu, + &vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing, + (void**)&vgpuSysmemPfnInfo.sysmemPfnRing, + (void**)&vgpuSysmemPfnInfo.sysmemPfnRing_priv); +} + +static NV_STATUS _setupSysmemPfnBitMap(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status = NV_OK; + VGPU_SYSMEM_PFN_BITMAP_NODE_P node = NULL; + + if (RMCFG_FEATURE_PLATFORM_MODS || + !pGpu->getProperty(pGpu, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED)) + return NV_OK; + + if (vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing == NULL) + { + listInitIntrusive(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)); + } + + // Initialize the per vGPU sysmem segment list. + listInitIntrusive(&pVGpu->listVgpuSysmemSegments); + + if (listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)) == 0) + { + status = _initSysmemPfnRing(pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: Failed to init sysmem pfn ring\n"); + goto done; + } + + // + // (1) One bit represents one 4K sysmem page = 2^12 + // (2) One 4K page of bit map will contain 32K bits of (1). This represents 128MB of sysmem = 2^27 + // (3) One pass transfers 512 PFN of (2) from guest to plugin. This represents 64GB of sysmem = 2^36 + // (4) The provision is to have 16384 passes. That will cover upto 1 PB of guest PA. + // + // Initial bitmap allocation is for (3), i.e., first 64GB of guest PA + // and corresponding node is added to listVgpuSysmemPfnBitmapHead list. + // + status = vgpuAllocSysmemPfnBitMapNode(pGpu, &node, + listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead))); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: Failed to alloc sysmem pfn bitmap node\n"); + goto done; + } + + listAppendExisting(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead), node); + + vgpuSysmemPfnInfo.guestMaxPfn = node->nodeEndPfn; + vgpuSysmemPfnInfo.sizeInBytes = vgpuSysmemPfnInfo.guestMaxPfn / 8; + + // Alloc the ref count buffer + vgpuSysmemPfnInfo.sysmemPfnRefCount = portMemAllocNonPaged(sizeof(NvU16) * (vgpuSysmemPfnInfo.sizeInBytes * 8)); + if (vgpuSysmemPfnInfo.sysmemPfnRefCount == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to allocate sysmem pfn refcount array\n"); + NV_ASSERT(0); + status = NV_ERR_INSUFFICIENT_RESOURCES; + listRemove(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead), node); + goto done; + } + portMemSet(vgpuSysmemPfnInfo.sysmemPfnRefCount, 0, sizeof(NvU16) * vgpuSysmemPfnInfo.guestMaxPfn); + + } + + // Increase the refcount of sysmem PFN bitMap memory descriptor at head + // for this device, so that memory is not deleted when device which actually + // allocated it is disabled. + if (listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)) > 0) + { + node = listHead(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)); + // increase refCount of first bitmap node descriptor + memdescAddRef(node->pMemDesc_sysmemPfnMap); + } + +done: + if (status != NV_OK) + { + if (node) + { + vgpuFreeSysmemPfnBitMapNode(node); + } + + portMemFree(vgpuSysmemPfnInfo.sysmemPfnRefCount); + + vgpuSysmemPfnInfo.guestMaxPfn = 0; + vgpuSysmemPfnInfo.sizeInBytes = 0; + } + else + { + vgpuSysmemPfnInfo.bSysmemPfnInfoInitialized = NV_TRUE; + } + + return status; +} + +static NV_STATUS updateSharedBufferInfoInSysmemPfnBitMap(OBJGPU *pGpu, OBJVGPU *pVGpu, NvBool add) +{ + NV_STATUS status = NV_OK; + + if (RMCFG_FEATURE_PLATFORM_MODS || + !pGpu->getProperty(pGpu, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED)) + return NV_OK; + + if ((pVGpu->gspCtrlBufInfo.pMemDesc != NULL) && + (memdescGetAddressSpace(pVGpu->gspCtrlBufInfo.pMemDesc) == ADDR_SYSMEM)) + { + status = vgpuUpdateSysmemPfnBitMap(pGpu, pVGpu->gspCtrlBufInfo.pMemDesc, add); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update ctrl buff sysmem info in PFN bitmap, error 0x%x\n", status); + return status; + } + } + + if ((pVGpu->gspResponseBufInfo.pMemDesc != NULL) && + (memdescGetAddressSpace(pVGpu->gspResponseBufInfo.pMemDesc) == ADDR_SYSMEM)) + { + status = vgpuUpdateSysmemPfnBitMap(pGpu, pVGpu->gspResponseBufInfo.pMemDesc, add); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update response buff sysmem info in PFN bitmap, error 0x%x\n", status); + return status; + } + } + + if ((pVGpu->gspMessageBuf.pMemDesc != NULL) && + (memdescGetAddressSpace(pVGpu->gspMessageBuf.pMemDesc) == ADDR_SYSMEM)) + { + status = vgpuUpdateSysmemPfnBitMap(pGpu, pVGpu->gspMessageBuf.pMemDesc, add); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update message buff sysmem info in PFN bitmap, error 0x%x\n", status); + return status; + } + } + + if ((pVGpu->eventRing.mem.pMemDesc != NULL) && + (memdescGetAddressSpace(pVGpu->eventRing.mem.pMemDesc) == ADDR_SYSMEM)) + { + status = vgpuUpdateSysmemPfnBitMap(pGpu, pVGpu->eventRing.mem.pMemDesc, add); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update event mem sysmem in PFN bitmap, error 0x%x\n", status); + return status; + } + } + + if ((pVGpu->sharedMemory.pMemDesc != NULL) && + (memdescGetAddressSpace(pVGpu->sharedMemory.pMemDesc) == ADDR_SYSMEM)) + { + status = vgpuUpdateSysmemPfnBitMap(pGpu, pVGpu->sharedMemory.pMemDesc, add); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update shared mem sysmem info in PFN bitmap, error 0x%x\n", status); + return status; + } + } + + if ((vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing != NULL) && + (memdescGetAddressSpace(vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing) == ADDR_SYSMEM)) + { + VGPU_SYSMEM_PFN_BITMAP_NODE_P head = NULL; + if (listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)) > 0) + { + head = listHead(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)); + } + + if (head && head->pMemDesc_sysmemPfnMap->RefCount == 1) + { + status = vgpuUpdateSysmemPfnBitMap(pGpu, vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing, add); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update PFN bitmap sysmem info in PFN bitmap, error 0x%x\n", status); + return status; + } + } + } + + return status; +} +void teardownSysmemPfnBitMap(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + VGPU_SYSMEM_PFN_BITMAP_NODE_P head = NULL; + + if (RMCFG_FEATURE_PLATFORM_MODS || + !pGpu->getProperty(pGpu, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED)) + return; + + if (listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)) > 0) + { + head = listHead(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)); + + // decrease refCount of first bitmap node descriptor + memdescRemoveRef(head->pMemDesc_sysmemPfnMap); + } + + // The sysmem PFN bitMap list is global, so free only when last device is being freed. + if (head && head->pMemDesc_sysmemPfnMap->RefCount == 1) + { + VGPU_SYSMEM_PFN_BITMAP_NODE_P node; + VGPU_SYSMEM_PFN_BITMAP_NODE_P nodeNext; + + _freeSysmemPfnRing(pGpu); + + for (node = listHead(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)); + node != NULL; + node = nodeNext) + { + nodeNext = listNext(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead), node); + listRemove(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead), node); + vgpuFreeSysmemPfnBitMapNode(node); + } + + portMemFree(vgpuSysmemPfnInfo.sysmemPfnRefCount); + + vgpuSysmemPfnInfo.guestMaxPfn = 0; + vgpuSysmemPfnInfo.sizeInBytes = 0; + + vgpuSysmemPfnInfo.bSysmemPfnInfoInitialized = NV_FALSE; + } +} + +static void rpcStructureCopySetIpVersion(OBJGPU *pGpu, OBJRPCSTRUCTURECOPY *pRpcStructureCopy, NvU32 ipVersion) +{ + OBJHAL *pHal = GPU_GET_HAL(pGpu); + PMODULEDESCRIPTOR pMod = objhalGetModuleDescriptor(pHal); + IGRP_IP_VERSIONS_TABLE_INFO info = {0}; + + _objrpcStructureCopyAssignIpVersion(pRpcStructureCopy, ipVersion); + pMod->pHalSetIfaces->rpcstructurecopyHalIfacesSetupFn(&pRpcStructureCopy->_hal); + info.pGpu = pGpu; + info.pDynamic = (void*) pRpcStructureCopy; + rpcstructurecopy_iGrp_ipVersions_getInfo_HAL(pRpcStructureCopy, &info); + info.ifacesWrapupFn(&info); +} + +void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion) +{ + OBJHAL *pHal = GPU_GET_HAL(pGpu); + PMODULEDESCRIPTOR pMod = objhalGetModuleDescriptor(pHal); + IGRP_IP_VERSIONS_TABLE_INFO info = {0}; + + _objrpcAssignIpVersion(pRpc, ipVersion); + pMod->pHalSetIfaces->rpcHalIfacesSetupFn(&pRpc->_hal); + info.pGpu = pGpu; + info.pDynamic = (void*) pRpc; + rpc_iGrp_ipVersions_getInfo_HAL(pRpc, &info); + info.ifacesWrapupFn(&info); + + rpcStructureCopySetIpVersion(pGpu, &pRpc->rpcStructureCopy, ipVersion); +} + +NV_STATUS rpcConstruct_IMPL(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_STATUS rmStatus = NV_OK; + + pRpc->maxRpcSize = RM_PAGE_SIZE; + + return rmStatus; +} + +void rpcDestroy_IMPL(OBJGPU *pGpu, OBJRPC *pRpc) +{ +} + +NV_STATUS vgpuReinitializeRpcInfraOnStateLoad(OBJGPU *pGpu) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + NV_STATUS rmStatus = NV_OK; + + NV_ASSERT_OR_RETURN(IS_VIRTUAL_WITH_SRIOV(pGpu), NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN((pVGpu->eventRing.mem.pMemory != NULL), NV_ERR_INVALID_STATE); + + portMemSet(pVGpu->eventRing.mem.pMemory, 0, RM_PAGE_SIZE); + + NV_RM_RPC_SET_GUEST_SYSTEM_INFO(pGpu, rmStatus); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: Failed to set GUEST_SYSTEM_INFO on resume from hibernate:0x%x\n", rmStatus); + bSkipRpcVersionHandshake = NV_FALSE; + } + + return rmStatus; +} + +static NV_STATUS _setupGspControlBuffer(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 memFlags = 0; + + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + memFlags = MEMDESC_FLAGS_CPU_ONLY; + + status = _allocRpcMemDesc(pGpu, + RM_PAGE_SIZE, + NV_MEMORY_CONTIGUOUS, + ADDR_SYSMEM, + memFlags, + &pVGpu->gspCtrlBufInfo.pMemDesc, + (void**)&pVGpu->gspCtrlBufInfo.pMemory, + (void**)&pVGpu->gspCtrlBufInfo.pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: GSP Shared memory setup failed: 0x%x\n", status); + return status; + } + + pVGpu->gspCtrlBufInfo.pfn = memdescGetPte(pVGpu->gspCtrlBufInfo.pMemDesc, AT_GPU, 0) >> RM_PAGE_SHIFT; + + pVGpu->gspCtrlBuf = (VGPU_GSP_CTRL_BUF_RM*)pVGpu->gspCtrlBufInfo.pMemory; + + portMemSet(pVGpu->gspCtrlBuf, 0, memdescGetSize(pVGpu->gspCtrlBufInfo.pMemDesc)); + + return NV_OK; +} + +static void _teardownGspControlBuffer(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + pVGpu->gspCtrlBuf = NULL; + + pVGpu->gspCtrlBufInfo.pfn = 0; + + _freeRpcMemDesc(pGpu, + &pVGpu->gspCtrlBufInfo.pMemDesc, + (void**)&pVGpu->gspCtrlBufInfo.pMemory, + (void**)&pVGpu->gspCtrlBufInfo.pPriv); +} + +static NV_STATUS _setupGspResponseBuffer(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 memFlags = 0; + + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + memFlags = MEMDESC_FLAGS_CPU_ONLY; + + status = _allocRpcMemDesc(pGpu, + RM_PAGE_SIZE, + NV_MEMORY_CONTIGUOUS, + ADDR_SYSMEM, + memFlags, + &pVGpu->gspResponseBufInfo.pMemDesc, + (void**)&pVGpu->gspResponseBufInfo.pMemory, + (void**)&pVGpu->gspResponseBufInfo.pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: GSP Response memory setup failed: 0x%x\n", status); + return status; + } + + pVGpu->gspResponseBufInfo.pfn = memdescGetPte(pVGpu->gspResponseBufInfo.pMemDesc, AT_GPU, 0) >> RM_PAGE_SHIFT; + + pVGpu->gspResponseBuf = (VGPU_GSP_RESPONSE_BUF_RM*)pVGpu->gspResponseBufInfo.pMemory; + + portMemSet(pVGpu->gspResponseBuf, 0, memdescGetSize(pVGpu->gspResponseBufInfo.pMemDesc)); + + return NV_OK; +} + +static void _teardownGspResponseBuffer(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + pVGpu->gspResponseBuf = NULL; + + pVGpu->gspResponseBufInfo.pfn = 0; + + _freeRpcMemDesc(pGpu, + &pVGpu->gspResponseBufInfo.pMemDesc, + (void**)&pVGpu->gspResponseBufInfo.pMemory, + (void**)&pVGpu->gspResponseBufInfo.pPriv); +} + +// Different address space configs on different arch +// AD10x +// - Memory is always allocated on FBMEM +// GH100+ +// - Memory is allocated on SYSMEM when BAR2 is in physical mode +// - memory is allocated on FBMEM when BAR2 switches virtual mode +// GH180 +// - Memory is allocated on SYSMEM initially +// - Memory is allocated on FBMEM after C2C mapping is completed +static NV_STATUS _setupGspMessageBuffer(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status; + NV_ADDRESS_SPACE addressSpace = ADDR_FBMEM; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 memFlags = 0; + + if(kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + memFlags = MEMDESC_FLAGS_CPU_ONLY; + + if (IsGH100orBetter(pGpu) && (!kbusIsBar2Initialized(pKernelBus))) + addressSpace = ADDR_SYSMEM; + + status = _allocRpcMemDesc(pGpu, + RM_PAGE_SIZE_128K, + NV_MEMORY_CONTIGUOUS, + addressSpace, + memFlags, + &pVGpu->gspMessageBuf.pMemDesc, + (void**)&pVGpu->gspMessageBuf.pMemory, + (void**)&pVGpu->gspMessageBuf.pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: GSP Message memory setup failed: 0x%x\n", status); + return status; + } + + pVGpu->gspMessageBuf.pfn = memdescGetPte(pVGpu->gspMessageBuf.pMemDesc, AT_GPU, 0) >> RM_PAGE_SHIFT; + + portMemSet(pVGpu->gspMessageBuf.pMemory, 0, memdescGetSize(pVGpu->gspMessageBuf.pMemDesc)); + + return NV_OK; +} + +static void _teardownGspMessageBuffer(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + pVGpu->gspMessageBuf.pfn = 0; + + _freeRpcMemDesc(pGpu, + &pVGpu->gspMessageBuf.pMemDesc, + (void**)&pVGpu->gspMessageBuf.pMemory, + (void**)&pVGpu->gspMessageBuf.pPriv); +} + +static NvU64 vgpuGspMakeBufferAddress(VGPU_MEM_INFO *pMemInfo) +{ + NV_ADDRESS_SPACE addressSpace = memdescGetAddressSpace(pMemInfo->pMemDesc); + NvU64 gspBufferAddr = REF_DEF64(VGPU_GSP_BUF_ADDR_V1_VALIDITY, _VALID) | + REF_NUM64(VGPU_GSP_BUF_ADDR_V1_PFN, pMemInfo->pfn); + NvU64 size = memdescGetSize(pMemInfo->pMemDesc); + + switch (addressSpace) + { + case ADDR_SYSMEM: + gspBufferAddr |= REF_DEF64(VGPU_GSP_BUF_ADDR_V1_APERTURE, _SYSMEM); + break; + case ADDR_FBMEM: + gspBufferAddr |= REF_DEF64(VGPU_GSP_BUF_ADDR_V1_APERTURE, _FBMEM); + break; + default: + NV_PRINTF(LEVEL_ERROR, "RPC: Invlid address space %d\n", addressSpace); + gspBufferAddr = VGPU_GSP_BUF_ADDR_V1_VALIDITY_INVALID; + break; + } + + switch (size) + { + case RM_PAGE_SIZE: + gspBufferAddr |= REF_DEF64(VGPU_GSP_BUF_ADDR_V2_SIZE, _4K); + break; + case RM_PAGE_SIZE_128K: + gspBufferAddr |= REF_DEF64(VGPU_GSP_BUF_ADDR_V2_SIZE, _128K); + break; + default: + NV_PRINTF(LEVEL_ERROR, "RPC: Invalid buffer size %lld\n", size); + gspBufferAddr = VGPU_GSP_BUF_ADDR_V1_VALIDITY_INVALID; + break; + } + + return gspBufferAddr; +} + +static NV_STATUS _vgpuGspWaitForResponse(OBJGPU *pGpu) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + RMTIMEOUT timeout; + + if (pVGpu->gspCtrlBuf == NULL) + return NV_ERR_INVALID_STATE; + + gpuSetTimeout(pGpu, NV_VGPU_RPC_TIMEOUT_USEC(pGpu), &timeout, GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE); + + // Check the response against the request sequence number. + while (pVGpu->gspResponseBuf->v1.responseId != pVGpu->sequence_gsp_request) + { + if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) + return NV_ERR_TIMEOUT; + } + + // Issue a read memory barrier to prevent reads from the RPC message buffer before this point. + portAtomicMemoryFenceLoad(); + + return NV_OK; +} + +static void _vgpuGspSendRequest(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 doorbellToken) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + if (pVGpu->gspCtrlBuf == NULL) + return; + + // Set the request sequence number + pVGpu->gspCtrlBuf->v1.requestId = ++pVGpu->sequence_gsp_request; + + // Issue a write memory barrier, to complete any previous writes on the RPC + // message and control buffer, before hitting the doorbell. + portAtomicMemoryFenceStore(); + + // Ring the doorbell to send the request + rpcVgpuGspRingDoorbell_HAL(pRpc, pGpu, doorbellToken); +} + +static NV_STATUS _vgpuGspSendRpcRequest(OBJGPU *pGpu, OBJRPC *pRpc) +{ + // Send the RPC request + _vgpuGspSendRequest(pGpu, pRpc, NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_HANDLE); + + return NV_OK; +} + +static NV_STATUS _vgpuGspSendSetupRequest(OBJGPU *pGpu, NvU64 scratchRegVal) +{ + OBJRPC *pRpc = GPU_GET_RPC(pGpu); + + // Write the scratch registers + rpcVgpuGspWriteScratchRegister_HAL(pRpc, pGpu, scratchRegVal); + + // Send the Setup request + _vgpuGspSendRequest(pGpu, pRpc, NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_HANDLE); + + // Wait for the response + return _vgpuGspWaitForResponse(pGpu); +} + +static NV_STATUS _vgpuGspTeardownCommunicationWithPlugin(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status; + + if (pVGpu->gspCtrlBuf == NULL) + return NV_ERR_INVALID_STATE; + + pVGpu->gspCtrlBuf->v1.msgBuf.addr = VGPU_GSP_BUF_ADDR_V1_VALIDITY_INVALID; + + status = _vgpuGspSendSetupRequest(pGpu, VGPU_GSP_BUF_ADDR_V1_VALIDITY_INVALID); + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "Communication teardown with GSP Plugin failed 0x%x\n", status); + + return status; +} + +static NV_STATUS _vgpuGspSetupCommunicationWithPlugin(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status; + NvU64 addrCtrlBuf; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + if (pVGpu->gspCtrlBuf == NULL) + return NV_ERR_INVALID_STATE; + + // Init the request sequence number + pVGpu->sequence_gsp_request = pVGpu->gspResponseBuf->v1.responseId; + + pVGpu->gspCtrlBuf->v1.version = VGPU_GSP_CTRL_BUF_V2_VERSION; + pVGpu->gspCtrlBuf->v1.responseBuf.addr = vgpuGspMakeBufferAddress(&pVGpu->gspResponseBufInfo); + pVGpu->gspCtrlBuf->v1.msgBuf.addr = vgpuGspMakeBufferAddress(&pVGpu->gspMessageBuf); + pVGpu->gspCtrlBuf->v1.sharedMem.addr = vgpuGspMakeBufferAddress(&pVGpu->sharedMemory); + pVGpu->gspCtrlBuf->v1.eventBuf.addr = vgpuGspMakeBufferAddress(&pVGpu->eventRing.mem); + + // + // Save the BAR2 offsets for the buffers located in FBMEM + // [*] pCpuMapping -> BAR2 is mapped at this location + // [*] PteAdjust -> The byte offset at which the memory allocation begins within the first PTE + // [*] BAR2 CPU Virtual address + // - pVGpu->gspMessageBuf.pMemory + // - pVGpu->shared_memory + // - pVGpu->eventRing.mem.pMemory + // + + if (memdescGetAddressSpace(pVGpu->gspMessageBuf.pMemDesc) == ADDR_FBMEM) + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + pVGpu->gspCtrlBuf->v1.msgBuf.bar2Offset = ((NvU64)(pVGpu->gspMessageBuf.pMemory)) - + ((NvU64)(pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping)) - + pVGpu->gspMessageBuf.pMemDesc->PteAdjust; + } + else + { + pVGpu->gspCtrlBuf->v1.msgBuf.bar2Offset = memdescGetPte(pVGpu->gspMessageBuf.pMemDesc, AT_GPU, 0); + } + } + if (memdescGetAddressSpace(pVGpu->sharedMemory.pMemDesc) == ADDR_FBMEM) + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + pVGpu->gspCtrlBuf->v1.sharedMem.bar2Offset = ((NvU64)(pVGpu->shared_memory)) - + ((NvU64)(pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping)) - + pVGpu->gspMessageBuf.pMemDesc->PteAdjust; + } + else + { + pVGpu->gspCtrlBuf->v1.sharedMem.bar2Offset = memdescGetPte(pVGpu->sharedMemory.pMemDesc, AT_GPU, 0); + } + } + if (memdescGetAddressSpace(pVGpu->eventRing.mem.pMemDesc) == ADDR_FBMEM) + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) + { + pVGpu->gspCtrlBuf->v1.eventBuf.bar2Offset = ((NvU64)(pVGpu->eventRing.mem.pMemory)) - + ((NvU64)(pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping)) - + pVGpu->gspMessageBuf.pMemDesc->PteAdjust; + } + else + { + pVGpu->gspCtrlBuf->v1.eventBuf.bar2Offset = memdescGetPte(pVGpu->eventRing.mem.pMemDesc, AT_GPU, 0); + } + } + + // + // In VGPU-GSP architecture, dirty sysmem pfns bitmaps are passed as 3 + // level table. GSP control buffer is used to pass the address of root node + // to the VGPU-GSP plugin. VGPU-GSP plugin maps the table at the time + // of migration to read bitmap data. + // First level of node has table information (bitmap node count) and + // 511 pfn entries which points to second level node. + // Second level of nodes has 512 pfn entries which points to third level + // nodes. + // Third level of node has 4K size bitmap data. 4K size page has + // 4096 * 8 bits and each bit represents a 4k sysmem page. So + // each 4k size bitmap data tracks 128MB of sysmem. Each bitmap node is of + // size 2Mb which effectively tracks 64GB of sysmem. If sysmem page size + // changes, total trackable memory size will also change. + // Three level table can track total of 511 * 512 * 4096 * 8 * 4096 + // = 32,704 GB = 31.9 TB sysmem. + // + // vgpuGspSetupBuffers is called from kbusStateInitLockedKernel_GM107 and + // initRpcInfrastructure_VGPU. pMemDesc_sysmemPfnRing is not allocated when + // the first call for this function comes from initRpcInfrastructure_VGPU. + // Second call for this function comes from kbusStateInitLockedKernel_GM107 + // and sets correct value of sysmemBitMapTablePfn. + if (vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing == NULL) + { + pVGpu->gspCtrlBuf->v1.sysmemBitMapTablePfn = VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_VALIDITY_INVALID; + } + else + { + pVGpu->gspCtrlBuf->v1.sysmemBitMapTablePfn = + vgpuGspSysmemPfnMakeBufferAddress(vgpuSysmemPfnInfo.pMemDesc_sysmemPfnRing, + vgpuSysmemPfnInfo.sysmemPfnRing_pfn); + } + + addrCtrlBuf = vgpuGspMakeBufferAddress(&pVGpu->gspCtrlBufInfo); + + NV_PRINTF(LEVEL_INFO, "RPC: BAR2 Physical 0x%x\n", pVGpu->bIsBar2Physical ? 1 : 0); + NV_PRINTF(LEVEL_INFO, "RPC: Control buf addr 0x%llx\n", addrCtrlBuf); + NV_PRINTF(LEVEL_INFO, "RPC: Response buf addr 0x%llx\n", pVGpu->gspCtrlBuf->v1.responseBuf.addr); + NV_PRINTF(LEVEL_INFO, "RPC: Message buf addr 0x%llx\n", pVGpu->gspCtrlBuf->v1.msgBuf.addr); + NV_PRINTF(LEVEL_INFO, "RPC: Message buf BAR2 offset 0x%llx\n", pVGpu->gspCtrlBuf->v1.msgBuf.bar2Offset); + NV_PRINTF(LEVEL_INFO, "RPC: Shared buf addr 0x%llx\n", pVGpu->gspCtrlBuf->v1.sharedMem.addr); + NV_PRINTF(LEVEL_INFO, "RPC: Shared buf BAR2 offset 0x%llx\n", pVGpu->gspCtrlBuf->v1.sharedMem.bar2Offset); + NV_PRINTF(LEVEL_INFO, "RPC: Event buf addr 0x%llx\n", pVGpu->gspCtrlBuf->v1.eventBuf.addr); + NV_PRINTF(LEVEL_INFO, "RPC: Event buf BAR2 offset 0x%llx\n", pVGpu->gspCtrlBuf->v1.eventBuf.bar2Offset); + + status = _vgpuGspSendSetupRequest(pGpu, addrCtrlBuf); + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "Communication setup with GSP plugin failed 0x%x\n", status); + + return status; +} + +void vgpuGspTeardownBuffers(OBJGPU *pGpu) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + if (!pVGpu->bGspPlugin) + { + return; + } + + pVGpu->bGspBuffersInitialized = NV_FALSE; + + // First teardown with GSP and then teardown the buffers + _vgpuGspTeardownCommunicationWithPlugin(pGpu, pVGpu); + + _teardownGspSharedMemory(pGpu, pVGpu); + + _teardownGspEventInfrastructure(pGpu, pVGpu); + + _teardownGspMessageBuffer(pGpu, pVGpu); + + _teardownGspResponseBuffer(pGpu, pVGpu); + + _teardownGspControlBuffer(pGpu, pVGpu); +} + +NV_STATUS vgpuGspSetupBuffers(OBJGPU *pGpu) +{ + NV_STATUS status = NV_OK; + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + pVGpu->bIsBar2Physical = pKernelBus->bIsBar2SetupInPhysicalMode; + pVGpu->allocFbOffsetBar2Physical = 0xa00000; + + rpcSendMessage_FNPTR(pVGpu->pRpc) = _rpcSendMessage_VGPUGSP; + rpcRecvPoll_FNPTR(pVGpu->pRpc) = _rpcRecvPoll_VGPUGSP; + + status = _setupGspControlBuffer(pGpu, pVGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: GSP Shared memory setup failed: 0x%x\n", status); + goto fail; + } + + status = _setupGspResponseBuffer(pGpu, pVGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: GSP Response memory setup failed: 0x%x\n", status); + goto fail; + } + + status = _setupGspMessageBuffer(pGpu, pVGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: GSP Message buffer setup failed: 0x%x\n", status); + goto fail; + } + + if (pVGpu->pRpc && pVGpu->bGspPlugin) + { + pVGpu->pRpc->message_buffer = pVGpu->gspMessageBuf.pMemory; + pVGpu->pRpc->largeRpcSize = RM_PAGE_SIZE_128K; + } + status = _setupGspEventInfrastructure(pGpu, pVGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: Event setup failed: 0x%x\n", status); + goto fail; + } + + status = _setupGspSharedMemory(pGpu, pVGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: Shared memory setup failed: 0x%x\n", status); + goto fail; + } + + // Update Guest OS Type, before establishing communication with GSP. + vgpuUpdateGuestOsType(pGpu, pVGpu); + + status = _vgpuGspSetupCommunicationWithPlugin(pGpu, pVGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: GSP Setup failed: 0x%x\n", status); + goto fail; + } + + // Update Guest ECC status based on Host ECC status, after establishing RPC with GSP. + setGuestEccStatus(pGpu); + + pVGpu->bGspBuffersInitialized = NV_TRUE; + + return NV_OK; + +fail: + vgpuGspTeardownBuffers(pGpu); + + return status; +} + +void setGuestEccStatus(OBJGPU *pGpu) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + NvU32 data32 = 0; + + // + // Emulated registers are not supported on vgpu-gsp. ECC state toggling is + // handled through gsp control buffer + // + if (pVGpu->bGspPlugin) + { + pVGpu->bECCSupported = pVGpu->gspResponseBuf->v1.hostEccStatus ? NV_TRUE : NV_FALSE; + } + + pVGpu->bECCEnabled = pVGpu->bECCSupported; + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GUEST_ECC_STATE, &data32) == NV_OK) + { + if (NV_REG_STR_RM_GUEST_ECC_STATE_DISABLED == data32) + { + if (pVGpu->bECCSupported) + { + // Allow disabling of ECC irrespective of host ECC status. + pVGpu->bECCEnabled = NV_FALSE; + portDbgPrintf("Guest explicitly disabled ECC support.\n"); + } + } + else + { + if (!pVGpu->bECCSupported) + { + portDbgPrintf("Error: Guest trying to enable ECC on unsupported configuration.\n"); + } + } + } + if (pVGpu->bGspPlugin) + { + pVGpu->gspCtrlBuf->v1.guestEccStatus = pVGpu->bECCEnabled ? 1 : 0; + } +} + +// This is a one time (per-device) initialization. +NV_STATUS initRpcInfrastructure_VGPU(OBJGPU *pGpu) +{ + OBJVGPU *pVGpu; + NV_STATUS rmStatus = NV_OK; + + // should not be called in broadcast mode + NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); + + pVGpu = GPU_GET_VGPU(pGpu); + portMemSet(pVGpu, 0, sizeof(OBJVGPU)); + + pVGpu->bGspPlugin = IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu); + + pVGpu->pRpc = initRpcObject(pGpu); + if (pVGpu->pRpc == NULL) + { + rmStatus = NV_ERR_INVALID_POINTER; + goto fail; + } + + if (pVGpu->bGspPlugin) + { + rmStatus = vgpuGspSetupBuffers(pGpu); + } + else + { + rmStatus = NV_ERR_NOT_SUPPORTED; + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC buffers setup failed: 0x%x\n", rmStatus); + goto fail; + } + + if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) + { + NvU32 gpuMaskRelease = 0; + NvBool bLockAcquired = NV_FALSE; + + if (!rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskRelease)) + { + // Acquire lock + NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuMaskRelease)); + bLockAcquired = NV_TRUE; + } + + NV_RM_RPC_SET_GUEST_SYSTEM_INFO(pGpu, rmStatus); + + if (bLockAcquired && gpuMaskRelease != 0) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM_RPC: SET_GUEST_SYSTEM_INFO : failed.\n"); + if (NV_ERR_NOT_SUPPORTED == rmStatus) + { + nvErrorLog_va(pGpu, VGPU_START_ERROR, "vGPU type is not supported"); + } + goto fail; + } + } + + rmStatus = _setupSysmemPfnBitMap(pGpu, pVGpu); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: Sysmem PFN bitmap setup failed: 0x%x\n", rmStatus); + goto fail; + } + + rmStatus = updateSharedBufferInfoInSysmemPfnBitMap(pGpu, pVGpu, NV_TRUE); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: Sysmem PFN bitmap update failed for shared buffer sysmem pages failed: 0x%x\n", rmStatus); + goto fail; + } + + pVGpu->bVncSupported = !!(*(NvU32 *)(pVGpu->shared_memory + + (NV_VGPU_SHARED_MEMORY_POINTER_VNC_SUPPORT / sizeof(NvU32)))); + + pVGpu->bVncConnected = !!(*(NvU32 *)(pVGpu->shared_memory + + (NV_VGPU_SHARED_MEMORY_POINTER_VNC / sizeof(NvU32)))); + + // Set a flag indicating that the rpc initialization is done + pVGpu->bRpcInitialized = NV_TRUE; + + return NV_OK; + +fail: + teardownSysmemPfnBitMap(pGpu, pVGpu); + + if (pVGpu->bGspPlugin) + { + vgpuGspTeardownBuffers(pGpu); + } + + if (pVGpu->pRpc) + { + rpcDestroy(pGpu, pVGpu->pRpc); + portMemFree(pVGpu->pRpc); + pVGpu->pRpc = NULL; + } + + return rmStatus; +} +// End of initRpcInfrastructure_VGPU() + +NV_STATUS freeRpcInfrastructure_VGPU(OBJGPU *pGpu) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + NV_STATUS rmStatus = NV_OK; + + // should not be called in broadcast mode + NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); + + // Return early if RPC is not initialized + if (!pVGpu->bRpcInitialized) + { + return NV_ERR_INVALID_STATE; + } + + rmStatus = updateSharedBufferInfoInSysmemPfnBitMap(pGpu, pVGpu, NV_FALSE); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC: Sysmem PFN bitmap update failed for shared buffer sysmem pages failed: 0x%x\n", rmStatus); + } + + if (pVGpu->bGspPlugin) + { + vgpuGspTeardownBuffers(pGpu); + } + + if (pVGpu->pRpc) + { + rpcDestroy(pGpu, pVGpu->pRpc); + portMemFree(pVGpu->pRpc); + pVGpu->pRpc = NULL; + } + + pVGpu->bRpcInitialized = NV_FALSE; + + return rmStatus; +} + +NV_STATUS rpcSendMessage_IMPL(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_PRINTF(LEVEL_ERROR, "virtual function not implemented.\n"); + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS rpcRecvPoll_IMPL(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 expectedFunc) +{ + NV_PRINTF(LEVEL_ERROR, "virtual function not implemented.\n"); + return NV_ERR_NOT_SUPPORTED; +} + +static NV_STATUS _rpcSendMessage_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRpc) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + vgpu_rpc_message_header_v->sequence = pVGpu->sequence_base++; + + return _vgpuGspSendRpcRequest(pGpu, pRpc); +} + +static NV_STATUS _rpcRecvPoll_VGPUGSP(OBJGPU *pGpu, OBJRPC *pRPC, NvU32 expectedFunc) +{ + return _vgpuGspWaitForResponse(pGpu); +} + +static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_STATUS status = NV_OK; + RPC_METER_LIST *pNewEntry = NULL; + + // should not be called in broadcast mode + NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); + NV_CHECK(LEVEL_ERROR, rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + + if (bProfileRPC) + { + // Create a new entry for our RPC profiler + pNewEntry = portMemAllocNonPaged(sizeof(RPC_METER_LIST)); + if (pNewEntry == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to allocate RPC meter memory!\n"); + NV_ASSERT(0); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + portMemSet(pNewEntry, 0, sizeof(RPC_METER_LIST)); + + if (rpcMeterHead.pHead == NULL) + rpcMeterHead.pHead = pNewEntry; + else + rpcMeterHead.pTail->pNext = pNewEntry; + + rpcMeterHead.pTail = pNewEntry; + + pNewEntry->rpcData.rpcDataTag = vgpu_rpc_message_header_v->function; + + rpcProfilerEntryCount++; + + osGetPerformanceCounter(&pNewEntry->rpcData.startTimeInNs); + } + + // For HCC, cache expectedFunc value before encrypting. + NvU32 expectedFunc = vgpu_rpc_message_header_v->function; + + status = rpcSendMessage(pGpu, pRpc); + if (status != NV_OK) + { + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "rpcSendMessage failed with status 0x%08x for fn %d!\n", + status, vgpu_rpc_message_header_v->function); + // + // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC + // buffers full and not being serviced) can make things worse, i.e. turn RPC + // failures into app hangs such that even nvidia-bug-report.sh gets stuck. + // Avoid this for now while still returning the correct error in other cases. + // + return (status == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : status; + } + + // Use cached expectedFunc here because vgpu_rpc_message_header_v is encrypted for HCC. + status = rpcRecvPoll(pGpu, pRpc, expectedFunc); + if (status != NV_OK) + { + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "rpcRecvPoll timedout for fn %d!\n", + vgpu_rpc_message_header_v->function); + } + else + { + NV_PRINTF_COND(pRpc->bQuietPrints, LEVEL_INFO, LEVEL_ERROR, + "rpcRecvPoll failed with status 0x%08x for fn %d!\n", + status, vgpu_rpc_message_header_v->function); + } + return status; + } + + if (bProfileRPC) + osGetPerformanceCounter(&pNewEntry->rpcData.endTimeInNs); + + // Now check if RPC really succeeded + if (vgpu_rpc_message_header_v->rpc_result != NV_VGPU_MSG_RESULT_SUCCESS) + { + if (vgpu_rpc_message_header_v->rpc_result == NV_VGPU_MSG_RESULT_RPC_API_CONTROL_NOT_SUPPORTED) + return NV_VGPU_MSG_RESULT_RPC_API_CONTROL_NOT_SUPPORTED; + + NV_PRINTF(LEVEL_WARNING, "RPC failed with status 0x%08x for fn %d!\n", + vgpu_rpc_message_header_v->rpc_result, + vgpu_rpc_message_header_v->function); + + if (vgpu_rpc_message_header_v->rpc_result < DRF_BASE(NV_VGPU_MSG_RESULT__VMIOP)) + return vgpu_rpc_message_header_v->rpc_result; + + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +static NV_STATUS _issueRpcAsync(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_STATUS status; + + // should not be called in broadcast mode + NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); + + status = rpcSendMessage(pGpu, pRpc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "rpcSendMessage failed with status 0x%08x for fn %d!\n", + status, vgpu_rpc_message_header_v->function); + NV_ASSERT(0); + // + // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC + // buffers full and not being serviced) can make things worse, i.e. turn RPC + // failures into app hangs such that even nvidia-bug-report.sh gets stuck. + // Avoid this for now while still returning the correct error in other cases. + // + return (status == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : status; + } + + return NV_OK; +} + +static NV_STATUS _issueRpcLarge +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvU32 bufSize, + const void *pBuffer, + NvBool bBidirectional, + NvBool bWait +) +{ + NvU8 *pBuf8 = (NvU8 *)pBuffer; + NV_STATUS nvStatus = NV_OK; + NvU32 expectedFunc = vgpu_rpc_message_header_v->function; + NvU32 entryLength; + NvU32 remainingSize = bufSize; + NvU32 recordCount = 0; + + // should not be called in broadcast mode + NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE); + + // Copy the initial buffer + entryLength = NV_MIN(bufSize, pRpc->maxRpcSize); + + if ((NvU8 *)vgpu_rpc_message_header_v != pBuf8) + portMemCopy(vgpu_rpc_message_header_v, entryLength, pBuf8, entryLength); + + // Set the correct length for this queue entry. + vgpu_rpc_message_header_v->length = entryLength; + + nvStatus = rpcSendMessage(pGpu, pRpc); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "rpcSendMessage failed with status 0x%08x for fn %d!\n", + nvStatus, expectedFunc); + NV_ASSERT(0); + // + // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC + // buffers full and not being serviced) can make things worse, i.e. turn RPC + // failures into app hangs such that even nvidia-bug-report.sh gets stuck. + // Avoid this for now while still returning the correct error in other cases. + // + return (nvStatus == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : nvStatus; + } + remainingSize -= entryLength; + pBuf8 += entryLength; + + // Copy the remaining buffers + entryLength = pRpc->maxRpcSize - sizeof(rpc_message_header_v); + while (remainingSize != 0) + { + if (entryLength > remainingSize) + entryLength = remainingSize; + + if (gpuIsCCFeatureEnabled(pGpu)) + { + // Zero out the entire RPC message header to clear the state of previous chunk. + portMemSet(vgpu_rpc_message_header_v, 0, sizeof(rpc_message_header_v)); + } + + portMemCopy(rpc_message, entryLength, pBuf8, entryLength); + + // Set the correct length for this queue entry. + vgpu_rpc_message_header_v->length = entryLength + sizeof(rpc_message_header_v); + vgpu_rpc_message_header_v->function = NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD; + + nvStatus = rpcSendMessage(pGpu, pRpc); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "rpcSendMessage failed with status 0x%08x for fn %d continuation record (remainingSize=0x%x)!\n", + nvStatus, expectedFunc, remainingSize); + NV_ASSERT(0); + // + // It has been observed that returning NV_ERR_BUSY_RETRY in a bad state (RPC + // buffers full and not being serviced) can make things worse, i.e. turn RPC + // failures into app hangs such that even nvidia-bug-report.sh gets stuck. + // Avoid this for now while still returning the correct error in other cases. + // + return (nvStatus == NV_ERR_BUSY_RETRY) ? NV_ERR_GENERIC : nvStatus; + } + + remainingSize -= entryLength; + pBuf8 += entryLength; + recordCount++; + } + + if (!bWait) + { + // In case of Async RPC, we are done here. + return nvStatus; + } + + // Always receive at least one.. nvStatus = rpcRecvPoll(pGpu, pRpc, expectedFunc); if (nvStatus != NV_OK) { - if (nvStatus == NV_ERR_TIMEOUT) + if (nvStatus == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll timedout for fn %d!\n", + vgpu_rpc_message_header_v->function); + } + else + { + NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll failed with status 0x%08x for fn %d!\n", + nvStatus, vgpu_rpc_message_header_v->function); + } + NV_ASSERT(0); + return nvStatus; + } + + pBuf8 = (NvU8 *)pBuffer; + remainingSize = bufSize; + entryLength = NV_MIN(bufSize, vgpu_rpc_message_header_v->length); + NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE); + + if (((NvU8 *)vgpu_rpc_message_header_v != pBuf8) && bBidirectional) + portMemCopy(pBuf8, entryLength, vgpu_rpc_message_header_v, entryLength); + + remainingSize -= entryLength; + pBuf8 += entryLength; + + // For bidirectional transfer messages, need to receive all other frames as well + if (bBidirectional && (recordCount > 0)) + { + while (remainingSize > 0) + { + nvStatus = rpcRecvPoll(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD); + if (nvStatus != NV_OK) + { + if (nvStatus == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "rpcRecvPoll timedout for fn %d continuation record (remainingSize=0x%x)!\n", + vgpu_rpc_message_header_v->function, remainingSize); + } + else + { + NV_PRINTF(LEVEL_ERROR, + "rpcRecvPoll failed with status 0x%08x for fn %d continuation record! (remainingSize=0x%x)\n", + nvStatus, vgpu_rpc_message_header_v->function, remainingSize); + } + NV_ASSERT(0); + return nvStatus; + } + + entryLength = vgpu_rpc_message_header_v->length; + NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE); + NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength >= sizeof(rpc_message_header_v), NV_ERR_INVALID_STATE); + entryLength -= sizeof(rpc_message_header_v); + + if (entryLength > remainingSize) + entryLength = remainingSize; + + portMemCopy(pBuf8, entryLength, rpc_message, entryLength); + remainingSize -= entryLength; + pBuf8 += entryLength; + recordCount--; + } + vgpu_rpc_message_header_v->function = expectedFunc; + NV_ASSERT(recordCount == 0); + } + + // Now check if RPC really succeeded + if (vgpu_rpc_message_header_v->rpc_result != NV_VGPU_MSG_RESULT_SUCCESS) + { + NV_PRINTF(LEVEL_WARNING, "RPC failed with status 0x%08x for fn %d!\n", + vgpu_rpc_message_header_v->rpc_result, + vgpu_rpc_message_header_v->function); + + if (vgpu_rpc_message_header_v->rpc_result < DRF_BASE(NV_VGPU_MSG_RESULT__VMIOP)) + return vgpu_rpc_message_header_v->rpc_result; + + return NV_ERR_GENERIC; + } + + return NV_OK; +} + +static NV_STATUS _issueRpcAndWaitLarge +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvU32 bufSize, + const void *pBuffer, + NvBool bBidirectional +) +{ + return _issueRpcLarge(pGpu, pRpc, bufSize, pBuffer, + bBidirectional, + NV_TRUE); //bWait +} + +static NV_STATUS _issueRpcAsyncLarge +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvU32 bufSize, + const void *pBuffer +) +{ + return _issueRpcLarge(pGpu, pRpc, bufSize, pBuffer, + NV_FALSE, //bBidirectional + NV_FALSE); //bWait +} + +static NV_STATUS _issuePteDescRpc +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvU32 offsetToPTE, + NvU32 pageCount, + RmPhysAddr *guestPages, + NvBool physicallyContiguous +) +{ + rpc_message_header_v *pHdr = vgpu_rpc_message_header_v; + void *pAllocatedRecord = NULL; + struct pte_desc *pPteDesc; + NvU64 contigBase; + NV_STATUS nvStatus = NV_OK; + NvU32 recordSize; + NvU32 i; + DMA_PAGE_ARRAY pageArray; + + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pRpc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(guestPages != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pHdr != NULL, NV_ERR_INVALID_ARGUMENT); + + recordSize = offsetToPTE + NV_OFFSETOF(struct pte_desc, pte_pde[0].pte) + + (pageCount * NV_VGPU_PTE_64_SIZE); + + if (recordSize > pRpc->maxRpcSize) + { + // Multiple queue entries. Create a temporary buffer for the PTEs. + pAllocatedRecord = portMemAllocNonPaged(recordSize); + if (pAllocatedRecord == NULL) + { + NV_PRINTF(LEVEL_ERROR, "no memory for allocated record\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + // Copy in the record so far. + portMemCopy(pAllocatedRecord, pHdr->length, pHdr, pHdr->length); + + // Point to the allocated record. + pHdr = (rpc_message_header_v *)pAllocatedRecord; + } + + dmaPageArrayInit(&pageArray, guestPages, pageCount); + + pPteDesc = (struct pte_desc *)NvP64_PLUS_OFFSET(pHdr, offsetToPTE); + pPteDesc->idr = NV_VGPU_PTEDESC_IDR_NONE; + pPteDesc->length = pageCount; + contigBase = (dmaPageArrayGetPhysAddr(&pageArray, 0) >> RM_PAGE_SHIFT); + + for (i = 0; i < pageCount; i++) + { + if (physicallyContiguous) + pPteDesc->pte_pde[i].pte = contigBase + i; + else + pPteDesc->pte_pde[i].pte = + (dmaPageArrayGetPhysAddr(&pageArray, i) >> RM_PAGE_SHIFT); + } + + nvStatus = _issueRpcAndWaitLarge(pGpu, pRpc, recordSize, pHdr, NV_FALSE); + + portMemFree(pAllocatedRecord); + + return nvStatus; +} + +static NV_STATUS getStaticDataRpcBufferSize(OBJGPU *pGpu, OBJRPCSTRUCTURECOPY *pObjStructurecopy, NvU32 *bufferSize) +{ + NV_STATUS status = NV_OK; + NvBool align_offset = NV_FALSE; + + NV_ASSERT_OR_RETURN(bufferSize != NULL, NV_ERR_INVALID_ARGUMENT); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + align_offset = NV_TRUE; + + status = static_data_copy(pObjStructurecopy, NULL, NULL, 0, bufferSize, align_offset); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: Get static data RPC bufferSize: failed.\n"); + NV_ASSERT_OR_RETURN(status == NV_OK, status); + } + + return status; +} + +static NV_STATUS copyPayloadToStaticData(OBJGPU *pGpu, OBJRPCSTRUCTURECOPY *pObjStructurecopy, NvU8 *pPayload, NvU32 payloadSize, VGPU_STATIC_INFO *pVSI) +{ + NvU32 offset = 0; + NV_STATUS status = NV_OK; + NvBool align_offset = NV_FALSE; + + NV_ASSERT_OR_RETURN(pPayload != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_ARGUMENT); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + align_offset = NV_TRUE; + + status = static_data_copy(pObjStructurecopy, pVSI, pPayload, payloadSize, &offset, align_offset); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: copyPayloadToStaticData: failed.\n"); + NV_ASSERT_OR_RETURN(status == NV_OK, status); + } + + return status; +} + +static NV_STATUS getConsolidatedGrRpcBufferSize(OBJGPU *pGpu, OBJRPCSTRUCTURECOPY *pObjStructurecopy, NvU32 *bufferSize) +{ + NV_STATUS status = NV_OK; + NvBool align_offset = NV_FALSE; + + NV_ASSERT_OR_RETURN(bufferSize != NULL, NV_ERR_INVALID_ARGUMENT); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + align_offset = NV_TRUE; + + status = consolidated_gr_static_info_copy(pObjStructurecopy, NULL, NULL, 0, bufferSize, align_offset); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: getConsolidatedGrRpcBufferSize: failed.\n"); + NV_ASSERT(0); + return status; + } + + return status; +} + +static NV_STATUS copyPayloadToGrStaticInfo(OBJGPU *pGpu, OBJRPCSTRUCTURECOPY *pObjStructurecopy, NvU8 *pConsolidatedRpcPayload, NvU32 payloadSize, VGPU_STATIC_INFO *pVSI) +{ + NvU32 offset = 0; + NV_STATUS status = NV_OK; + NvBool align_offset = NV_FALSE; + + NV_ASSERT_OR_RETURN(pConsolidatedRpcPayload != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_ARGUMENT); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + align_offset = NV_TRUE; + + status = consolidated_gr_static_info_copy(pObjStructurecopy, pVSI, pConsolidatedRpcPayload, payloadSize, &offset, align_offset); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: copyPayloadToGrStaticInfo: failed.\n"); + NV_ASSERT(0); + return status; + } + + return status; +} + +static +NV_STATUS _setRmReturnParams_v(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 hClass, void *pKernelCreateParams) +{ + NV_STATUS status = NV_OK; + switch(hClass) + { + case FERMI_CONTEXT_SHARE_A: + { + NV_CTXSHARE_ALLOCATION_PARAMETERS *pContextShareParams = pKernelCreateParams; + pContextShareParams->subctxId = rpc_message->alloc_object_v.params.param_FERMI_CONTEXT_SHARE_A.subctxId; + break; + } + + default: + break; + } + return status; +} + +// Serialize object creation parameters into ALLOC_OBJECT RPC message buffer +NV_STATUS _serializeClassParams_v(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 hClass, void *pCreateParms) +{ + alloc_object_params_v *params = &rpc_message->alloc_object_v.params; + NvU32 param_length = 0; + + switch (hClass) + { + case ADA_A: + case HOPPER_A: + { + NV_GR_ALLOCATION_PARAMETERS *pGrAllocParam = pCreateParms; + + params->param_NV50_TESLA.version = pGrAllocParam->version; + params->param_NV50_TESLA.flags = pGrAllocParam->flags; + params->param_NV50_TESLA.size = pGrAllocParam->size; + params->param_NV50_TESLA.caps = pGrAllocParam->caps; + + param_length = sizeof(params->param_NV50_TESLA); + break; + } + + case AMPERE_DMA_COPY_B: + case HOPPER_DMA_COPY_A: + { + NV85B5_ALLOCATION_PARAMETERS *pNv85b5CreateParms = pCreateParms; + + params->param_GT212_DMA_COPY.version = pNv85b5CreateParms->version; + params->param_GT212_DMA_COPY.engineInstance = pNv85b5CreateParms->engineInstance; + + param_length = sizeof(params->param_GT212_DMA_COPY); + break; + } + + case GF100_DISP_SW: + { + NV9072_ALLOCATION_PARAMETERS *pParams = pCreateParms; + + /* + * The first two parameters are no longer in NV9072_ALLOCATION_PARAMETERS, + * but we keep them for binary compatibility. + */ + + params->param_GF100_DISP_SW._reserved1 = 0; + params->param_GF100_DISP_SW._reserved2 = 0; + params->param_GF100_DISP_SW.logicalHeadId = pParams->logicalHeadId; + params->param_GF100_DISP_SW.displayMask = pParams->displayMask; + params->param_GF100_DISP_SW.caps = pParams->caps; + + param_length = sizeof(params->param_GF100_DISP_SW); + break; + } + + case FERMI_CONTEXT_SHARE_A: + { + NV_CTXSHARE_ALLOCATION_PARAMETERS *pParams = pCreateParms; + params->param_FERMI_CONTEXT_SHARE_A.hVASpace = pParams->hVASpace; + params->param_FERMI_CONTEXT_SHARE_A.flags = pParams->flags; + params->param_FERMI_CONTEXT_SHARE_A.subctxId = pParams->subctxId; + + param_length = sizeof(params->param_FERMI_CONTEXT_SHARE_A); + break; + } + + case NVC9B7_VIDEO_ENCODER: + { + NV_MSENC_ALLOCATION_PARAMETERS *pParams = pCreateParms; + params->param_NVD0B7_VIDEO_ENCODER.size = pParams->size; + params->param_NVD0B7_VIDEO_ENCODER.prohibitMultipleInstances = pParams->prohibitMultipleInstances; + params->param_NVD0B7_VIDEO_ENCODER.engineInstance = pParams->engineInstance; + + param_length = sizeof(params->param_NVD0B7_VIDEO_ENCODER); + break; + } + + case FERMI_VASPACE_A: + { + NV_VASPACE_ALLOCATION_PARAMETERS *pParams = pCreateParms; + params->param_FERMI_VASPACE_A.index = pParams->index; + params->param_FERMI_VASPACE_A.flags = pParams->flags; + params->param_FERMI_VASPACE_A.vaSize = pParams->vaSize; + params->param_FERMI_VASPACE_A.bigPageSize = pParams->bigPageSize; + params->param_FERMI_VASPACE_A.vaBase = pParams->vaBase; + + param_length = sizeof(params->param_FERMI_VASPACE_A); + break; + } + + case GT200_DEBUGGER: + { + NV83DE_ALLOC_PARAMETERS *pParams = pCreateParms; + params->param_NV83DE_ALLOC_PARAMETERS.hAppClient = pParams->hAppClient; + params->param_NV83DE_ALLOC_PARAMETERS.hClass3dObject = pParams->hClass3dObject; + + param_length = sizeof(params->param_NV83DE_ALLOC_PARAMETERS); + break; + } + + case NVENC_SW_SESSION: + { + NVA0BC_ALLOC_PARAMETERS *pParams = pCreateParms; + params->param_NVENC_SW_SESSION.codecType = pParams->codecType; + params->param_NVENC_SW_SESSION.hResolution = pParams->hResolution; + params->param_NVENC_SW_SESSION.vResolution = pParams->vResolution; + + param_length = sizeof(params->param_NVENC_SW_SESSION); + break; + } + + case NVB8B0_VIDEO_DECODER: + case NVC9B0_VIDEO_DECODER: + { + NV_BSP_ALLOCATION_PARAMETERS *pParams = pCreateParms; + params->param_NVC4B0_VIDEO_DECODER.size = pParams->size; + params->param_NVC4B0_VIDEO_DECODER.prohibitMultipleInstances = pParams->prohibitMultipleInstances; + params->param_NVC4B0_VIDEO_DECODER.engineInstance = pParams->engineInstance; + + param_length = sizeof(params->param_NVC4B0_VIDEO_DECODER); + break; + } + + case NVFBC_SW_SESSION: + { + NVA0BD_ALLOC_PARAMETERS *pParams = pCreateParms; + params->param_NVFBC_SW_SESSION.displayOrdinal = pParams->displayOrdinal; + params->param_NVFBC_SW_SESSION.sessionType = pParams->sessionType; + params->param_NVFBC_SW_SESSION.sessionFlags = pParams->sessionFlags; + params->param_NVFBC_SW_SESSION.hMaxResolution = pParams->hMaxResolution; + params->param_NVFBC_SW_SESSION.vMaxResolution = pParams->vMaxResolution; + + param_length = sizeof(params->param_NVFBC_SW_SESSION); + break; + } + + case KEPLER_CHANNEL_GROUP_A: + { + NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS *pParams = pCreateParms; + params->param_KEPLER_CHANNEL_GROUP_A.hObjectError = pParams->hObjectError; + params->param_KEPLER_CHANNEL_GROUP_A.hVASpace = pParams->hVASpace; + params->param_KEPLER_CHANNEL_GROUP_A.engineType = pParams->engineType; + + param_length = sizeof(params->param_KEPLER_CHANNEL_GROUP_A); + break; + } + + case AMPERE_SMC_PARTITION_REF: + { + NVC637_ALLOCATION_PARAMETERS *pParams = pCreateParms; + params->param_NVC637_ALLOCATION_PARAMETERS.swizzId = pParams->swizzId; + param_length = sizeof(params->param_NVC637_ALLOCATION_PARAMETERS); + break; + } + + case NV01_MEMORY_FLA: + { + NV_FLA_MEMORY_ALLOCATION_PARAMS *pParams = pCreateParms; + + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.type = pParams->type; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.flags = pParams->flags; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.attr = pParams->attr; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.attr2 = pParams->attr2; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.base = pParams->base; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.align = pParams->align; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.limit = pParams->limit; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.flagsOs02 = pParams->flagsOs02; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.hExportSubdevice = pParams->hExportSubdevice; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.hExportHandle = pParams->hExportHandle; + params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS.hExportClient = pParams->hExportClient; + + param_length = sizeof(params->param_NV_FLA_MEMORY_ALLOCATION_PARAMS); + break; + } + + case AMPERE_SMC_EXEC_PARTITION_REF: + { + NVC638_ALLOCATION_PARAMETERS *pParams = pCreateParms; + params->param_NVC638_ALLOCATION_PARAMETERS.execPartitionId = pParams->execPartitionId; + param_length = sizeof(params->param_NVC638_ALLOCATION_PARAMETERS); + break; + } + case NV50_THIRD_PARTY_P2P: + { + NV503C_ALLOC_PARAMETERS *pParams = pCreateParms; + if (pParams != NULL) + { + params->param_NV503C_ALLOC_PARAMETERS.flags = pParams->flags; + param_length = sizeof(params->param_NV503C_ALLOC_PARAMETERS); + } + break; + } + + case MAXWELL_PROFILER_DEVICE: + { + NVB2CC_ALLOC_PARAMETERS *pParams = pCreateParms; + params->param_NVB2CC_ALLOC_PARAMETERS.hClientTarget = pParams->hClientTarget; + params->param_NVB2CC_ALLOC_PARAMETERS.hContextTarget = pParams->hContextTarget; + param_length = sizeof(params->param_NVB2CC_ALLOC_PARAMETERS); + break; + } + + case ADA_COMPUTE_A: + case HOPPER_COMPUTE_A: + { + NV_GR_ALLOCATION_PARAMETERS *pParams = pCreateParms; + if (pParams != NULL) { + params->param_NV_GR_ALLOCATION_PARAMETERS.version = pParams->version; + params->param_NV_GR_ALLOCATION_PARAMETERS.flags = pParams->flags; + params->param_NV_GR_ALLOCATION_PARAMETERS.size = pParams->size; + params->param_NV_GR_ALLOCATION_PARAMETERS.caps = pParams->caps; + + param_length = sizeof(params->param_NV_GR_ALLOCATION_PARAMETERS); + } + break; + } + + case UVM_CHANNEL_RETAINER: + { + NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS *pParams = pCreateParms; + if (pParams != NULL) { + params->param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS.hClient = pParams->hClient; + params->param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS.hChannel = pParams->hChannel; + + param_length = sizeof(params->param_NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS); + } + break; + } + + case NV50_P2P: + { + NV503B_ALLOC_PARAMETERS *pParams = pCreateParms; + if (pParams != NULL) { + params->param_NV503B_ALLOC_PARAMETERS.hSubDevice = pParams->hSubDevice; + params->param_NV503B_ALLOC_PARAMETERS.hPeerSubDevice = pParams->hPeerSubDevice; + params->param_NV503B_ALLOC_PARAMETERS.subDevicePeerIdMask = pParams->subDevicePeerIdMask; + params->param_NV503B_ALLOC_PARAMETERS.peerSubDevicePeerIdMask = pParams->peerSubDevicePeerIdMask; + params->param_NV503B_ALLOC_PARAMETERS.mailboxBar1Addr = pParams->mailboxBar1Addr; + params->param_NV503B_ALLOC_PARAMETERS.mailboxTotalSize = pParams->mailboxTotalSize; + params->param_NV503B_ALLOC_PARAMETERS.flags = pParams->flags; + + param_length = sizeof(params->param_NV503B_ALLOC_PARAMETERS); + } + break; + } + + case NV_MEMORY_FABRIC: + { + NV00F8_ALLOCATION_PARAMETERS *pParams = pCreateParms; + if (pParams != NULL) { + params->param_NV00F8_ALLOCATION_PARAMETERS.alignment = pParams->alignment; + params->param_NV00F8_ALLOCATION_PARAMETERS.allocSize = pParams->allocSize; + params->param_NV00F8_ALLOCATION_PARAMETERS.pageSize = pParams->pageSize; + params->param_NV00F8_ALLOCATION_PARAMETERS.allocFlags = pParams->allocFlags; + params->param_NV00F8_ALLOCATION_PARAMETERS.map.offset = pParams->map.offset; + params->param_NV00F8_ALLOCATION_PARAMETERS.map.hVidMem = pParams->map.hVidMem; + params->param_NV00F8_ALLOCATION_PARAMETERS.map.flags = pParams->map.flags; + + param_length = sizeof(params->param_NV00F8_ALLOCATION_PARAMETERS); + } + break; + } + + case NVC9FA_VIDEO_OFA: + case NVC6FA_VIDEO_OFA: + case NVC7FA_VIDEO_OFA: + case NVB8FA_VIDEO_OFA: + { + alloc_object_params_v* params = &rpc_message->alloc_object_v.params; + NV_OFA_ALLOCATION_PARAMETERS *pParams = pCreateParms; + if (pParams != NULL) { + params->param_NVC9FA_VIDEO_OFA.size = pParams->size; + params->param_NVC9FA_VIDEO_OFA.prohibitMultipleInstances = pParams->prohibitMultipleInstances; + + param_length = sizeof(params->param_NVC9FA_VIDEO_OFA); + } + break; + } + + case NVB8D1_VIDEO_NVJPG: + case NVC9D1_VIDEO_NVJPG: + { + const NV_NVJPG_ALLOCATION_PARAMETERS *pParams = pCreateParms; + + params->param_NV_NVJPG_ALLOCATION_PARAMETERS.size = pParams->size; + params->param_NV_NVJPG_ALLOCATION_PARAMETERS.prohibitMultipleInstances = pParams->prohibitMultipleInstances; + params->param_NV_NVJPG_ALLOCATION_PARAMETERS.engineInstance = pParams->engineInstance; + param_length = sizeof(params->param_NV_NVJPG_ALLOCATION_PARAMETERS); + break; + } + default: + return NV_ERR_INVALID_CLASS; + } + + rpc_message->alloc_object_v.param_len = param_length; + + // all done. + return NV_OK; +} + +NV_STATUS _serializeClassParams_v25_08(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 hClass, void *pCreateParms) +{ + + switch (hClass) + { + case NV2081_BINAPI: + case NV2082_BINAPI_PRIVILEGED: + return NV_OK; + default: + return _serializeClassParams_v(pGpu, pRpc, hClass, pCreateParms); + } + + // all done. + return NV_OK; +} + +/* Copy params from RPC buffer*/ +static NV_STATUS engine_utilization_copy_params_from_rpc_buffer_v09_0C(NvU32 cmd, void *params_in, void *Params) +{ + vgpuGetEngineUtilization_data_v *pParams = Params; + + switch (cmd) + { + + case NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE: + { + NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 *src = &pParams->vidPerfmonSample; + NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS *dest = params_in; + + dest->clkPercentBusy = src->clkPercentBusy; + dest->samplingPeriodUs = src->samplingPeriodUs; + break; + } + + case NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE: + { + NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS_v09_0C *src = &pParams->getAccountingState; + NV0000_CTRL_GPUACCT_GET_ACCOUNTING_STATE_PARAMS *dest = params_in; + + dest->state = src->state; + + break; + } + + case NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE: + { + break; + } + + case NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO: + { + NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C *src = &pParams->procAccountingInfo; + NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS *dest = params_in; + + dest->gpuUtil = src->gpuUtil; + dest->fbUtil = src->fbUtil; + dest->maxFbUsage = src->maxFbUsage; + dest->startTime = src->startTime; + dest->endTime = src->endTime; + + break; + } + + case NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA: + { + break; + } + + default: + { + NV_PRINTF(LEVEL_ERROR, + "Unknown Engine Utilization Control Command 0x%x\n", + cmd); + return NV_ERR_NOT_SUPPORTED; + break; + } + } + return NV_OK; +} + +/* Copy params to RPC buffer*/ +static NV_STATUS engine_utilization_copy_params_to_rpc_buffer_v09_0C(NvU32 cmd, void *Params, void *params_in) +{ + vgpuGetEngineUtilization_data_v *pParams = Params; + + switch (cmd) + { + + case NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE: + { + NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS *src = params_in; + NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS_v05_00 *dest = &pParams->vidPerfmonSample; + + dest->engineType = src->engineType; + break; + } + + case NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_STATE: + { + break; + } + + case NV0000_CTRL_CMD_GPUACCT_SET_ACCOUNTING_STATE: + { + NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS *src = params_in; + NV0000_CTRL_GPUACCT_SET_ACCOUNTING_STATE_PARAMS_v09_0C *dest = &pParams->setAccountingState; + + dest->newState = src->newState; + + break; + } + + case NV0000_CTRL_CMD_GPUACCT_GET_PROC_ACCOUNTING_INFO: + { + NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS *src = params_in; + NV0000_CTRL_GPUACCT_GET_PROC_ACCOUNTING_INFO_PARAMS_v09_0C *dest = &pParams->procAccountingInfo; + + dest->gpuId = src->gpuId; + dest->pid = src->pid; + break; + } + + case NV0000_CTRL_CMD_GPUACCT_CLEAR_ACCOUNTING_DATA: + { + break; + } + + default: + { + NV_PRINTF(LEVEL_ERROR, + "Unknown Engine Utilization Control Command 0x%x\n", + cmd); + return NV_ERR_NOT_SUPPORTED; + } + } + return NV_OK; +} + +/* Copy params from RPC buffer*/ +static NV_STATUS engine_utilization_copy_params_from_rpc_buffer_v1E_0D(NvU32 cmd, void *params_in, void *Params) +{ + + switch (cmd) + { + default: + return engine_utilization_copy_params_from_rpc_buffer_v09_0C(cmd, params_in, Params); + } + + return NV_OK; +} + +/* Copy params to RPC buffer*/ +static NV_STATUS engine_utilization_copy_params_to_rpc_buffer_v1E_0D(NvU32 cmd, void *Params, void *params_in) +{ + + switch (cmd) + { + default: + return engine_utilization_copy_params_to_rpc_buffer_v09_0C(cmd, Params, params_in); + } + + return NV_OK; +} + +/* Copy params from RPC buffer*/ +static NV_STATUS engine_utilization_copy_params_from_rpc_buffer_v1F_0E(NvU32 cmd, void *params_in, void *Params) +{ + vgpuGetEngineUtilization_data_v1F_0E *pParams = Params; + + switch (cmd) + { + case NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2: + { + NvU32 i; + NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E *src = pParams->gpumonPerfmonsampleV2; + NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE *dest = params_in; + + for (i = 0; i < NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E; i++) + { + dest[i].base.timeStamp = src[i].timeStamp; + + dest[i].fb.util = src[i].fb.util; + dest[i].fb.procId = src[i].fb.procId; + + dest[i].gr.util = src[i].gr.util; + dest[i].gr.procId = src[i].gr.procId; + + dest[i].nvenc.util = src[i].nvenc.util; + dest[i].nvenc.procId = src[i].nvenc.procId; + + dest[i].nvdec.util = src[i].nvdec.util; + dest[i].nvdec.procId = src[i].nvdec.procId; + } + break; + } + + default: + return engine_utilization_copy_params_from_rpc_buffer_v1E_0D(cmd, params_in, Params); + } + + return NV_OK; +} + +/* Copy params to RPC buffer*/ +static NV_STATUS engine_utilization_copy_params_to_rpc_buffer_v1F_0E(NvU32 cmd, void *Params, void *params_in) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2: + { + break; + } + default: + return engine_utilization_copy_params_to_rpc_buffer_v1E_0D(cmd, Params, params_in); + } + + return NV_OK; +} + +NV_STATUS rpcLog_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, const char *logstr, NvU32 loglevel) +{ + NV_STATUS status; + NvU32 length; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_LOG, sizeof(rpc_log_v03_00)); + if (status != NV_OK) + return status; + + length = (NvU32)portStringLength(logstr) + 1; + if (length > sizeof(rpc_log_v03_00) + pRpc->maxRpcSize) + { + NV_PRINTF(LEVEL_ERROR, "LOG RPC - string too long\n"); + return NV_ERR_BUFFER_TOO_SMALL; + } + + rpc_message->log_v03_00.level = loglevel; + rpc_message->log_v03_00.log_len = length; + + portStringCopy(rpc_message->log_v03_00.log_msg, rpc_message->log_v03_00.log_len, + logstr, length); + + status = _issueRpcAndWait(pGpu, pRpc); + return status; +} + +static void +_freeGfxpBuffer +( + OBJGPU *pGpu, + Device *pDevice, + NvHandle hChannel, + KernelGraphicsContext *pKernelGraphicsContext +) +{ + NV_STATUS status = NV_OK; + Subdevice *pSubDevice = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvHandle hClient = NV01_NULL_OBJECT; + RsClient *pClient; + NvU32 subdeviceInstance; + NvU8 i; + + VGPU_GFXP_BUFFERS * pVgpuGfxpBuffers = kgrctxGetVgpuGfxpBuffers(pGpu, pKernelGraphicsContext); + + if ((pGpu == NULL) || + (pDevice == NULL) || + (pKernelGraphicsContext == NULL) || + (pVgpuGfxpBuffers == NULL)) + { + return; + } + + pClient = RES_GET_CLIENT(pDevice); + hClient = pClient->hClient; + subdeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + + if ((subdeviceGetByInstance(pClient, RES_GET_HANDLE(pDevice), + subdeviceInstance, &pSubDevice) == NV_OK) && + pVgpuGfxpBuffers->bIsBufferAllocated) + { + NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS pParams; + portMemSet(&pParams, 0, sizeof(pParams)); + pParams.hClient = hClient; + pParams.hChannel = hChannel; + pParams.gfxpPreemptMode = NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_WFI; + pParams.flags = DRF_DEF(2080_CTRL_GR_SET_CTXSW, _PREEMPTION_MODE_FLAGS, _GFXP, _SET); + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + + for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL; i++) + { + pParams.vMemPtrs[i] = 0; + } + NV_RM_RPC_CONTROL(pGpu, + hClient, + RES_GET_HANDLE(pSubDevice), + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND, + &pParams, + sizeof(pParams), + status); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: rpc call to bind gfxp buffer for WFI mode failed : %x\n", + status); + goto exit; + } + } + + for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL; i++) + { + if (pVgpuGfxpBuffers->dmaOffset[i]) + { + NV_ASSERT_OK(pRmApi->Unmap(pRmApi, + hClient, + RES_GET_HANDLE(pDevice), + pVgpuGfxpBuffers->hDma[i], + 0, + pVgpuGfxpBuffers->dmaOffset[i], + 0)); + } + + if (pVgpuGfxpBuffers->hDma[i]) + { + NV_ASSERT_OK(pRmApi->Free(pRmApi, hClient, pVgpuGfxpBuffers->hDma[i])); + } + + if (pVgpuGfxpBuffers->hMemory[i]) + { + NV_ASSERT_OK(pRmApi->Free(pRmApi, hClient, pVgpuGfxpBuffers->hMemory[i])); + } + } + +exit : + portMemFree(pVgpuGfxpBuffers); + kgrctxSetVgpuGfxpBuffers(pKernelGraphicsContext, NULL); +} + +static +void validateRpcForSriov(OBJGPU *pGpu, NvU32 hClass, NvBool *rpcToHost) +{ + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && + !NV_IS_MODS) + { + switch (hClass) + { + case NV01_MEMORY_VIRTUAL: + *rpcToHost = !gpuIsSplitVasManagementServerClientRmEnabled(pGpu); + break; + + default: + *rpcToHost = NV_TRUE; + break; + } + } +} + +static NV_STATUS +_rpcFreeBuffersForKGrObj +( + OBJGPU *pGpu, + RsClient *pRsClient, + RsResourceRef *pResourceRef +) +{ + KernelGraphicsObject *pKernelGraphicsObject; + KernelGraphicsContext *pKernelGraphicsContext; + RsResourceRef *pParentRef; + RsResourceRef *pChannelParentRef; + + VGPU_GFXP_BUFFERS* pVgpuGfxpBuffers; + + pKernelGraphicsObject = dynamicCast(pResourceRef->pResource, KernelGraphicsObject); + NV_ASSERT_OR_RETURN(pKernelGraphicsObject != NULL, NV_ERR_INVALID_OBJECT); + pKernelGraphicsContext = kgrobjGetKernelGraphicsContext(pGpu, pKernelGraphicsObject); + NV_ASSERT_OR_RETURN(pKernelGraphicsContext != NULL, NV_ERR_INVALID_OBJECT_PARENT); + + pVgpuGfxpBuffers = kgrctxGetVgpuGfxpBuffers(pGpu, pKernelGraphicsContext); + + // Parent should be KernelChannel, and parent of that might be KernelChannelGroupApi + pParentRef = pResourceRef->pParentRef; + NV_ASSERT_OR_RETURN(pParentRef != NULL, NV_ERR_INVALID_OBJECT_PARENT); + pChannelParentRef = pParentRef->pParentRef; + NV_ASSERT_OR_RETURN(pChannelParentRef != NULL, NV_ERR_INVALID_OBJECT_PARENT); + + if ((pVgpuGfxpBuffers != NULL) && + (pVgpuGfxpBuffers->bIsBufferAllocated)) + { + NV_ASSERT_OR_RETURN(pVgpuGfxpBuffers->refCountChannel != 0, NV_ERR_INVALID_STATE); + + --(pVgpuGfxpBuffers->refCountChannel); + } + else + { + NV_PRINTF(LEVEL_ERROR, + "No vGPU GFxP buffers associated! hChannel: 0x%x\n", pParentRef->hResource); + return NV_OK; + } + + if (pVgpuGfxpBuffers->refCountChannel == 0) + { + NvHandle handle; + + // + // The handle for SET_CTXSW_PREEMPTION_MODE_GFX_GFXP depends whether + // this belongs to a group or not + // + if (dynamicCast(pChannelParentRef->pResource, KernelChannelGroupApi)) + { + // Parent of parent = KernelChannelGroupApi + handle = pChannelParentRef->hResource; + } + else + { + // Parent = KernelChannel + handle = pParentRef->hResource; + } + + _freeGfxpBuffer(pGpu, GPU_RES_GET_DEVICE(pKernelGraphicsObject), + handle, pKernelGraphicsContext); + } + + return NV_OK; +} + +static NV_STATUS _rpcFreePrologue(OBJGPU *pGpu, NvHandle hClient, NvHandle hParent, + NvHandle hObject, NvBool *rpcToHost) +{ + NV_STATUS status; + RsClient *pRsClient; + RsResourceRef *pResourceRef = NULL; + NvU32 objType = 0; + NvU32 classId = 0; + + /* + * As of now GFxP buffers for a GR context in Linux and iGPUs are created by the Guest + * RM during 3D object allocation time. Hence if this is a 3D object try and + * free the GFxP buffers, if any, associated with the corresponding GR + * context. + */ + if ((status = serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get client under lock: 0x%x! hClient: 0x%x\n", + status, hClient); + goto cleanup; + } + + if (((status = clientGetResourceRef(pRsClient, hObject, &pResourceRef)) != NV_OK) || + (pResourceRef == NULL)) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get resource ref: 0x%x! hObject: 0x%x\n", status, + hObject); + goto cleanup; + } + + classId = pResourceRef->externalClassId; + + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && + !NV_IS_MODS) + { + Memory *pMemory = dynamicCast(pResourceRef->pResource, Memory); + NvU32 categoryClassId = 0; + + if (pMemory != NULL) + { + categoryClassId = pMemory->categoryClassId; + + if ((categoryClassId == NV01_MEMORY_LOCAL_USER) || + (categoryClassId == NV01_MEMORY_FLA) || + (categoryClassId == NV50_MEMORY_VIRTUAL) || + (categoryClassId == NV01_MEMORY_SYSTEM) || + (categoryClassId == NV01_MEMORY_SYSTEM_OS_DESCRIPTOR)) + { + *rpcToHost = NV_FALSE; + + if (categoryClassId == NV01_MEMORY_LOCAL_USER) + { + if (RMCFG_FEATURE_PLATFORM_UNIX) + { + NvHandle hClientLocal = pGpu->hDefaultClientShare; + NvHandle hDeviceLocal = pGpu->hDefaultClientShareDevice; + NvHandle hSubdeviceLocal = pGpu->hDefaultClientShareSubDevice; + if (IS_MIG_IN_USE(pGpu)) + { + Subdevice *pSubdeviceLocal; + NV_CHECK_OR_RETURN(LEVEL_ERROR, pMemory->pDevice != NULL, NV_ERR_INVALID_STATE); + + hClientLocal = hClient; + hDeviceLocal = RES_GET_HANDLE(pMemory->pDevice); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + subdeviceGetByInstance(pRsClient, hDeviceLocal, 0, &pSubdeviceLocal)); + + hSubdeviceLocal = RES_GET_HANDLE(pSubdeviceLocal); + } + + status = updateHostVgpuFbUsage(pGpu, hClientLocal, hDeviceLocal, hSubdeviceLocal); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to update FB usage to host : 0x%x\n", status); + } + } + } + + return NV_OK; + } + } + + if (classId == NV01_EVENT_OS_EVENT) { + /* For full SRIOV, host cannot access memory with the help of memory handle + * So skip Free RPC for this + */ + RsResourceRef *pParent = pResourceRef->pParentRef; + + if (pParent->externalClassId == NV01_CONTEXT_DMA_FROM_MEMORY) + { + *rpcToHost = NV_FALSE; + return NV_OK; + } + } + } + + validateRpcForSriov(pGpu, classId, rpcToHost); + + /* check if the object is of type 3D, else return */ + kgrmgrGetGrObjectType(classId, &objType); + if (RMCFG_FEATURE_PLATFORM_UNIX && + (objType == GR_OBJECT_TYPE_3D) && + IsPASCALorBetter(pGpu)) + { + NV_ASSERT_OK_OR_RETURN(_rpcFreeBuffersForKGrObj(pGpu, pRsClient, pResourceRef)); + } + +cleanup: + + return NV_OK; +} + +NV_STATUS rpcFree_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hParent, NvHandle hObject) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + NVOS00_PARAMETERS_v03_00 *rpc_params; + rpc_params = &rpc_message->free_v03_00.params; + NvBool rpcToHost = NV_TRUE; + + if ((status = _rpcFreePrologue(pGpu, hClient, hParent, hObject, &rpcToHost)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC Free prologue failed: 0x%x!\n", status); + } + + if (rpcToHost == NV_FALSE) + return NV_OK; + + // issue FREE RPC + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_FREE, sizeof(rpc_free_v03_00)); + if (status != NV_OK) + return status; + + rpc_params->hRoot = hClient; + rpc_params->hObjectParent = hParent; + rpc_params->hObjectOld = hObject; + + status = _issueRpcAndWait(pGpu, pRpc); + + return status; +} + +NV_STATUS rpcAllocRoot_v07_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + NvU32 processID = 0; + RmClient *pClient = NULL; +#if defined (NV_UNIX) + CALL_CONTEXT *pCallContext = NULL; +#endif + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_ROOT, sizeof(rpc_alloc_root_v07_00)); + if (status != NV_OK) + return status; + + // + // Get guest process ID and process name (if applicable) from client database + // + rpc_message->alloc_root_v07_00.processName[0] = '\0'; + + pClient = serverutilGetClientUnderLock(hClient); + if (pClient == NULL) + { + return NV_ERR_INVALID_CLIENT; + } + +#if defined (NV_UNIX) + pCallContext = resservGetTlsCallContext(); + NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); + + if (pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL) + { + processID = KERNEL_PID; + } + else +#endif + { + processID = pClient->ProcID; + NV_ASSERT(processID == osGetCurrentProcess()); + osGetCurrentProcessName(rpc_message->alloc_root_v07_00.processName, NV_PROC_NAME_MAX_LENGTH); + } + + // + // Set RM allocated resource handle range for guest RM. This minimize clash of handles with host RM + // during VM migration. + // + if (IS_VIRTUAL(pGpu)) + { + ct_assert((RS_UNIQUE_HANDLE_BASE + RS_UNIQUE_HANDLE_RANGE/2 - VGPU_RESERVED_HANDLE_RANGE) == + VGPU_RESERVED_HANDLE_BASE); + + status = clientSetHandleGenerator(staticCast(pClient, RsClient), RS_UNIQUE_HANDLE_BASE, + RS_UNIQUE_HANDLE_RANGE/2 - VGPU_RESERVED_HANDLE_RANGE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: Failed to set guest client resource handle range %x\n", status); + } + } + + rpc_message->alloc_root_v07_00.hClient = hClient; + rpc_message->alloc_root_v07_00.processID = processID; + + status = _issueRpcAndWait(pGpu, pRpc); + return status; +} + +#define PSAPI_VERSION 1 +NV_STATUS rpcAllocShareDevice_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hClientShare, + NvHandle hTargetClient, NvHandle hTargetDevice, + NvU32 hClass, NvU32 flags, NvU64 vaSize, NvU32 vaMode) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + NV_DEVICE_ALLOCATION_PARAMETERS_v03_00 *rpc_params; + + rpc_params = &rpc_message->alloc_share_device_v03_00.params; + + // The ALLOC_DEVICE RPC is a bit special as it's the first client based RPC that + // can be issued (as we need a pGpu, which requires a hDevice). So, at this point + // we send both an ALLOC_ROOT and ALLOC_DEVICE RPC. + + // issue ALLOC_ROOT RPC + status = rpcAllocRoot_HAL(pGpu, pRpc, hClient); + if (status != NV_OK) + return status; + + // issue ALLOC_SHARE_DEVICE RPC + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_SHARE_DEVICE, + sizeof(rpc_alloc_share_device_v03_00)); + if (status != NV_OK) + return status; + + rpc_message->alloc_share_device_v03_00.hClient = hClient; + rpc_message->alloc_share_device_v03_00.hDevice = hDevice; + rpc_params->hClientShare = hClientShare; + rpc_params->hTargetClient = hTargetClient; + rpc_params->hTargetDevice = hTargetDevice; + rpc_message->alloc_share_device_v03_00.hClass = hClass; + rpc_params->flags = flags; + rpc_params->vaSpaceSize = vaSize; + rpc_params->vaMode = vaMode; + + status = _issueRpcAndWait(pGpu, pRpc); + return status; +} + +NV_STATUS rpcAllocMemory_v13_01(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hMemory, NvU32 hClass, + NvU32 flags, MEMORY_DESCRIPTOR *pMemDesc) +{ + NV_STATUS status = NV_OK; + + if (pMemDesc == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: AllocMemory: pMemDesc arg was NULL\n"); + return NV_ERR_GENERIC; + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY, sizeof(rpc_alloc_memory_v13_01)); + if (status != NV_OK) + return status; + + rpc_message->alloc_memory_v13_01.hClient = hClient; + rpc_message->alloc_memory_v13_01.hDevice = hDevice; + rpc_message->alloc_memory_v13_01.hMemory = hMemory; + rpc_message->alloc_memory_v13_01.hClass = hClass; + rpc_message->alloc_memory_v13_01.flags = flags; + rpc_message->alloc_memory_v13_01.pteAdjust = pMemDesc->PteAdjust; + rpc_message->alloc_memory_v13_01.format = memdescGetPteKind(pMemDesc); + rpc_message->alloc_memory_v13_01.length = pMemDesc->Size; + rpc_message->alloc_memory_v13_01.pageCount = (NvU32)pMemDesc->PageCount; + + if (IS_GSP_CLIENT(pGpu)) + { + status = _issuePteDescRpc(pGpu, pRpc, + NV_OFFSETOF(rpc_message_header_v, rpc_message_data[0].alloc_memory_v13_01.pteDesc), + pMemDesc->PageCount, + memdescGetPteArray(pMemDesc, AT_GPU), + memdescGetContiguity(pMemDesc, AT_GPU)); + } + + return status; +} + +NV_STATUS rpcAllocChannelDma_v1F_04(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hChannel, NvU32 hClass, + NV_CHANNEL_ALLOC_PARAMS *pGpfifoAllocParams, NvU32 *pChID) +{ + NV_STATUS status; + NV_CHANNEL_ALLOC_PARAMS_v1F_04 *pChannelGPFIFOAllocParms; + + NV_CHECK_OR_RETURN(LEVEL_INFO, pGpfifoAllocParams != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_INFO, pChID != NULL, NV_ERR_INVALID_ARGUMENT); + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_CHANNEL_DMA, sizeof(rpc_alloc_channel_dma_v1F_04)); + if (status != NV_OK) + return status; + + rpc_message->alloc_channel_dma_v1F_04.hClient = hClient; + rpc_message->alloc_channel_dma_v1F_04.hDevice = hDevice; + rpc_message->alloc_channel_dma_v1F_04.hChannel = hChannel; + rpc_message->alloc_channel_dma_v1F_04.hClass = hClass; + rpc_message->alloc_channel_dma_v1F_04.chid = *pChID; + + pChannelGPFIFOAllocParms = &rpc_message->alloc_channel_dma_v1F_04.params; + + pChannelGPFIFOAllocParms->hObjectError = pGpfifoAllocParams->hObjectError; + pChannelGPFIFOAllocParms->hObjectBuffer = pGpfifoAllocParams->hObjectBuffer; + pChannelGPFIFOAllocParms->gpFifoOffset = pGpfifoAllocParams->gpFifoOffset; + pChannelGPFIFOAllocParms->gpFifoEntries = pGpfifoAllocParams->gpFifoEntries; + pChannelGPFIFOAllocParms->flags = pGpfifoAllocParams->flags; + pChannelGPFIFOAllocParms->internalFlags = pGpfifoAllocParams->internalFlags; + pChannelGPFIFOAllocParms->hContextShare = pGpfifoAllocParams->hContextShare; + pChannelGPFIFOAllocParms->hVASpace = pGpfifoAllocParams->hVASpace; + pChannelGPFIFOAllocParms->hPhysChannelGroup = pGpfifoAllocParams->hPhysChannelGroup; + pChannelGPFIFOAllocParms->hUserdMemory[0] = pGpfifoAllocParams->hUserdMemory[0]; + pChannelGPFIFOAllocParms->userdOffset[0] = pGpfifoAllocParams->userdOffset[0]; + pChannelGPFIFOAllocParms->engineType = pGpfifoAllocParams->engineType; + pChannelGPFIFOAllocParms->hObjectEccError = pGpfifoAllocParams->hObjectEccError; + pChannelGPFIFOAllocParms->subDeviceId = pGpfifoAllocParams->subDeviceId; + pChannelGPFIFOAllocParms->instanceMem.base = pGpfifoAllocParams->instanceMem.base; + pChannelGPFIFOAllocParms->instanceMem.size = pGpfifoAllocParams->instanceMem.size; + pChannelGPFIFOAllocParms->instanceMem.addressSpace = pGpfifoAllocParams->instanceMem.addressSpace; + pChannelGPFIFOAllocParms->instanceMem.cacheAttrib = pGpfifoAllocParams->instanceMem.cacheAttrib; + pChannelGPFIFOAllocParms->ramfcMem.base = pGpfifoAllocParams->ramfcMem.base; + pChannelGPFIFOAllocParms->ramfcMem.size = pGpfifoAllocParams->ramfcMem.size; + pChannelGPFIFOAllocParms->ramfcMem.addressSpace = pGpfifoAllocParams->ramfcMem.addressSpace; + pChannelGPFIFOAllocParms->ramfcMem.cacheAttrib = pGpfifoAllocParams->ramfcMem.cacheAttrib; + pChannelGPFIFOAllocParms->userdMem.base = pGpfifoAllocParams->userdMem.base; + pChannelGPFIFOAllocParms->userdMem.size = pGpfifoAllocParams->userdMem.size; + pChannelGPFIFOAllocParms->userdMem.addressSpace = pGpfifoAllocParams->userdMem.addressSpace; + pChannelGPFIFOAllocParms->userdMem.cacheAttrib = pGpfifoAllocParams->userdMem.cacheAttrib; + pChannelGPFIFOAllocParms->mthdbufMem.base = pGpfifoAllocParams->mthdbufMem.base; + pChannelGPFIFOAllocParms->mthdbufMem.size = pGpfifoAllocParams->mthdbufMem.size; + pChannelGPFIFOAllocParms->mthdbufMem.addressSpace = pGpfifoAllocParams->mthdbufMem.addressSpace; + pChannelGPFIFOAllocParms->mthdbufMem.cacheAttrib = pGpfifoAllocParams->mthdbufMem.cacheAttrib; + pChannelGPFIFOAllocParms->errorNotifierMem.base = pGpfifoAllocParams->errorNotifierMem.base; + pChannelGPFIFOAllocParms->errorNotifierMem.size = pGpfifoAllocParams->errorNotifierMem.size; + pChannelGPFIFOAllocParms->errorNotifierMem.addressSpace = pGpfifoAllocParams->errorNotifierMem.addressSpace; + pChannelGPFIFOAllocParms->errorNotifierMem.cacheAttrib = pGpfifoAllocParams->errorNotifierMem.cacheAttrib; + pChannelGPFIFOAllocParms->eccErrorNotifierMem.base = pGpfifoAllocParams->eccErrorNotifierMem.base; + pChannelGPFIFOAllocParms->eccErrorNotifierMem.size = pGpfifoAllocParams->eccErrorNotifierMem.size; + pChannelGPFIFOAllocParms->eccErrorNotifierMem.addressSpace = pGpfifoAllocParams->eccErrorNotifierMem.addressSpace; + pChannelGPFIFOAllocParms->eccErrorNotifierMem.cacheAttrib = pGpfifoAllocParams->eccErrorNotifierMem.cacheAttrib; + + rpc_message->alloc_channel_dma_v1F_04.flags = 0; + + // issue ALLOC_CHANNEL RPC + status = _issueRpcAndWait(pGpu, pRpc); + if (status == NV_OK) + { + *pChID = rpc_message->alloc_channel_dma_v1F_04.chid; // return allocated channel ID + } + return status; +} + +static void +_allocateGfxpBuffer +( + OBJGPU *pGpu, + Device *pDevice, + NvHandle hChannel, + KernelChannel *pKernelChannel, + KernelGraphicsContext *pKernelGraphicsContext +) +{ + VGPU_STATIC_INFO *pVSI = NULL; + RsClient *pClient = RES_GET_CLIENT(pDevice); + Subdevice *pSubDevice = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NV_STATUS status = NV_OK; + NvBool bAcquireLock = NV_FALSE; + NvU64 dmaOffset[NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL] = {0}; + NvHandle hMemory, hDma; + NvHandle hClient; + NV_MEMORY_ALLOCATION_PARAMS memAllocParams; + NvU32 subdeviceInstance; + NvU8 i; + + NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS pParams; + VGPU_GFXP_BUFFERS* pVgpuGfxpBuffers = NULL; + + NV_ASSERT(kgrctxGetVgpuGfxpBuffers(pGpu, pKernelGraphicsContext) == NULL); + + if ((pGpu == NULL) || + (pClient == NULL) || + (pKernelChannel == NULL) || + (pKernelGraphicsContext == NULL)) + { + return; + } + + subdeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + pVSI = GPU_GET_STATIC_INFO(pGpu); + hClient = pClient->hClient; + + NV_ASSERT_OR_RETURN_VOID(pVSI != NULL); + + pVgpuGfxpBuffers = portMemAllocNonPaged(sizeof(*(pVgpuGfxpBuffers))); + if (pVgpuGfxpBuffers == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "failed to allocate memory for pKernelGraphicsContext->pVgpuGfxpBuffers!\n"); + return; + } + + portMemSet(pVgpuGfxpBuffers, 0, + sizeof(*(pVgpuGfxpBuffers))); + + for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL; i++) + { + // Skip allocation of GR_CTXSW_PREMPTION_BIND_BUFFERS with size == 0. + if (pVSI->gfxpBufferSize[i] == 0) + { + continue; + } + + status = clientGenResourceHandle(pClient, &hMemory); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "cannot get unique memory handle for vidmem : %x\n", + status); + goto exit; + } + + portMemSet(&memAllocParams, 0, sizeof(NV_MEMORY_ALLOCATION_PARAMS)); + + memAllocParams.owner = HEAP_OWNER_RM_CLIENT_GENERIC; + memAllocParams.type = NVOS32_TYPE_IMAGE; + memAllocParams.size = pVSI->gfxpBufferSize[i]; + memAllocParams.flags = NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE; + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); + memAllocParams.alignment = pVSI->gfxpBufferAlignment[i]; + + // + // Release GPU lock before calling VidHeapControl. + // Avoid releasing/acquiring the GPU lock in the middle of a function. + // TODO: Clean this up. See bug 200520471 + // + if (rmGpuLockIsOwner()) + { + rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); + bAcquireLock = NV_TRUE; + } + + status = pRmApi->AllocWithHandle(pRmApi, + hClient, + RES_GET_HANDLE(pDevice), + hMemory, + NV01_MEMORY_LOCAL_USER, + &memAllocParams, + sizeof(memAllocParams)); + + if (bAcquireLock) + { + // Reacquire GPU lock + if (rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_RPC) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to acquire lock\n"); + status = NV_ERR_GENERIC; + goto exit; + } + } + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate vidmem for gfxp: 0x%x\n", status); + goto exit; + } + + pVgpuGfxpBuffers->hMemory[i] = hMemory; + + status = clientGenResourceHandle(pClient, &hDma); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "cannot get unique memory handle for virtmem : %x\n", + status); + goto exit; + } + + + portMemSet(&memAllocParams, 0, sizeof(NV_MEMORY_ALLOCATION_PARAMS)); + + memAllocParams.owner = HEAP_OWNER_RM_CLIENT_GENERIC; + memAllocParams.type = NVOS32_TYPE_IMAGE; + memAllocParams.size = pVSI->gfxpBufferSize[i]; + memAllocParams.flags = NVOS32_ALLOC_FLAGS_VIRTUAL | + NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE; + memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _ANY); + memAllocParams.hVASpace = pKernelChannel->hVASpace; + memAllocParams.alignment = pVSI->gfxpBufferAlignment[i]; + + status = pRmApi->AllocWithHandle(pRmApi, + hClient, + RES_GET_HANDLE(pDevice), + hDma, + NV50_MEMORY_VIRTUAL, + &memAllocParams, + sizeof(memAllocParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Call to allocate virtmem for gfxp failed : %x\n", + status); + goto exit; + } + + pVgpuGfxpBuffers->hDma[i] = hDma; + + status = pRmApi->Map(pRmApi, + hClient, + RES_GET_HANDLE(pDevice), + hDma, + hMemory, + 0, + pVSI->gfxpBufferSize[i], + NV04_MAP_MEMORY_FLAGS_NONE, + &dmaOffset[i]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Call to map gfxp buffer to gpu va failed : %x\n", + status); + goto exit; + } + + pVgpuGfxpBuffers->dmaOffset[i] = dmaOffset[i]; + } + + if((status = subdeviceGetByInstance(pClient, RES_GET_HANDLE(pDevice), + subdeviceInstance, &pSubDevice)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "cannot get subdevice handle\n"); + goto exit; + } + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + + portMemSet(&pParams, 0, sizeof(pParams)); + pParams.hClient = hClient; + pParams.hChannel = hChannel; + pParams.gfxpPreemptMode = NV2080_CTRL_SET_CTXSW_PREEMPTION_MODE_GFX_GFXP; + pParams.flags = DRF_DEF(2080_CTRL_GR_SET_CTXSW, _PREEMPTION_MODE_FLAGS, _GFXP, _SET); + for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL; i++) + { + pParams.vMemPtrs[i] = dmaOffset[i]; + } + + NV_RM_RPC_CONTROL(pGpu, + hClient, + RES_GET_HANDLE(pSubDevice), + NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND, + &pParams, + sizeof(pParams), + status); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: rpc call to bind gfxp buffer failed : %x\n", + status); + goto exit; + } + pVgpuGfxpBuffers->bIsBufferAllocated = NV_TRUE; + pVgpuGfxpBuffers->refCountChannel = 1; + + kgrctxSetVgpuGfxpBuffers(pKernelGraphicsContext, pVgpuGfxpBuffers); + +exit : + if (status != NV_OK) + { + _freeGfxpBuffer(pGpu, pDevice, hChannel, pKernelGraphicsContext); + } +} + +static NV_STATUS +_rpcAllocBuffersForKGrObj +( + OBJGPU *pGpu, + NvHandle hClient, + NvHandle hObject +) +{ + RsClient *pRsClient; + RsResourceRef *pResourceRef; + RsResourceRef *pParentRef; + RsResourceRef *pChannelParentRef; + KernelGraphicsObject *pKernelGraphicsObject; + KernelGraphicsContext *pKernelGraphicsContext; + VGPU_GFXP_BUFFERS* pVgpuGfxpBuffers; + + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, hObject, &pResourceRef)); + + pKernelGraphicsObject = dynamicCast(pResourceRef->pResource, KernelGraphicsObject); + NV_ASSERT_OR_RETURN(pKernelGraphicsObject != NULL, NV_ERR_INVALID_OBJECT_PARENT); + pKernelGraphicsContext = kgrobjGetKernelGraphicsContext(pGpu, pKernelGraphicsObject); + NV_ASSERT_OR_RETURN(pKernelGraphicsContext != NULL, NV_ERR_INVALID_OBJECT_PARENT); + + pVgpuGfxpBuffers = kgrctxGetVgpuGfxpBuffers(pGpu, pKernelGraphicsContext); + + // Parent should be KernelChannel, and parent of that might be KernelChannelGroupApi + pParentRef = pResourceRef->pParentRef; + NV_ASSERT_OR_RETURN(pParentRef != NULL, NV_ERR_INVALID_OBJECT_PARENT); + pChannelParentRef = pParentRef->pParentRef; + NV_ASSERT_OR_RETURN(pChannelParentRef != NULL, NV_ERR_INVALID_OBJECT_PARENT); + + if ((pVgpuGfxpBuffers != NULL) && + (pVgpuGfxpBuffers->bIsBufferAllocated)) + { + pVgpuGfxpBuffers->refCountChannel++; + } + else + { + KernelChannel *pKernelChannel = dynamicCast(pParentRef->pResource, KernelChannel); + NvHandle handle; + + // + // The handle for SET_CTXSW_PREEMPTION_MODE_GFX_GFXP depends whether + // this belongs to a group or not + // + if (dynamicCast(pChannelParentRef->pResource, KernelChannelGroupApi)) + { + // Parent of parent = KernelChannelGroupApi + handle = pChannelParentRef->hResource; + } + else + { + // Parent = KernelChannel + handle = pParentRef->hResource; + } + + _allocateGfxpBuffer(pGpu, GPU_RES_GET_DEVICE(pKernelGraphicsObject), + handle, pKernelChannel, pKernelGraphicsContext); + } + + return NV_OK; +} + +static NV_STATUS +_rpcAllocObjectPrologue +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + NvU32 classId, + NvBool *rpcToHost +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NvU32 objType; + + validateRpcForSriov(pGpu, classId, rpcToHost); + + // Check whether UVM class is supported on given vGPU. + if (((classId == GP100_UVM_SW) || (classId == UVM_CHANNEL_RETAINER)) && + !IS_GSP_CLIENT(pGpu) && + !FLD_TEST_DRF(A080, _CTRL_CMD_VGPU_GET_CONFIG, + _PARAMS_UVM_FEATURES_API_ENABLED, + _TRUE, pVSI->vgpuConfig.uvmEnabledFeatures)) + { + NV_PRINTF(LEVEL_ERROR, "UVM (0x%x) object allocation is not supported\n", + classId); + return NV_ERR_NOT_SUPPORTED; + } + + // Display classes are added for DCE, vGPU Guest does not support those. + if (IS_VIRTUAL(pGpu)) + { + + switch (classId) + { + + case NVC67B_WINDOW_IMM_CHANNEL_DMA: + case NVC67E_WINDOW_CHANNEL_DMA: + case NVC770_DISPLAY: + case NVC77D_CORE_CHANNEL_DMA: + case NVC670_DISPLAY: + case NVC67D_CORE_CHANNEL_DMA: + case NV04_DISPLAY_COMMON: + { + + NV_PRINTF(LEVEL_ERROR, "Display Class (0x%x) object allocation is not supported\n", + classId); + return NV_ERR_NOT_SUPPORTED; + } + } + + } + + kgrmgrGetGrObjectType(classId, &objType); + if (RMCFG_FEATURE_PLATFORM_UNIX && + (objType == GR_OBJECT_TYPE_3D) && + IsPASCALorBetter(pGpu)) + { + NV_ASSERT_OK_OR_RETURN(_rpcAllocBuffersForKGrObj(pGpu, hClient, hObject)); + } + + return NV_OK; +} + +NV_STATUS rpcAllocObject_v(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hChannel, NvHandle hObject, + NvU32 hClass, void *params) +{ + NV_STATUS status; + NvBool rpcToHost = NV_TRUE; + + status = _rpcAllocObjectPrologue(pGpu, pRpc, hClient, hObject, hClass, &rpcToHost); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Alloc object RPC prologue failed (status: 0x%x) for hObject: 0x%x, " + "hClass: 0x%x, hChannel: 0x%x, hClient: 0x%x\n", status, + hObject, hClass, hChannel, hClient); + return status; + } + + if (rpcToHost == NV_FALSE) + return status; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT, sizeof(rpc_alloc_object_v)); + if (status != NV_OK) + return status; + + rpc_message->alloc_object_v.hClient = hClient; + rpc_message->alloc_object_v.hParent = hChannel; + rpc_message->alloc_object_v.hObject = hObject; + rpc_message->alloc_object_v.hClass = hClass ; + rpc_message->alloc_object_v.param_len = 0; + + if (params != NULL) + { + status = _serializeClassParams_v(pGpu, pRpc, hClass, params); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RmAllocObjectEx: vGPU: object RPC skipped (handle = 0x%08x, class = " + "0x%x) with non-NULL params ptr\n", hObject, hClass); + + // XXX: No RPC for unsupported classes. This must be taken care of. + // Return failure so that we can identify when this situation arises. + NV_ASSERT(0); + return status; + } + } + + status = _issueRpcAndWait(pGpu, pRpc); + + // Populate return values! + if ((status == NV_OK) && params) + { + status = _setRmReturnParams_v(pGpu, pRpc, hClass, params); + } + + return status; +} + +NV_STATUS rpcAllocObject_v25_08(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hChannel, NvHandle hObject, + NvU32 hClass, void *params) +{ + NV_STATUS status; + NvBool rpcToHost = NV_TRUE; + + status = _rpcAllocObjectPrologue(pGpu, pRpc, hClient, hObject, hClass, &rpcToHost); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Alloc object RPC prologue failed (status: 0x%x) for hObject: 0x%x, " + "hClass: 0x%x, hChannel: 0x%x, hClient: 0x%x\n", status, + hObject, hClass, hChannel, hClient); + return status; + } + + if (rpcToHost == NV_FALSE) + return status; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_OBJECT, sizeof(rpc_alloc_object_v)); + if (status != NV_OK) + return status; + + rpc_message->alloc_object_v.hClient = hClient; + rpc_message->alloc_object_v.hParent = hChannel; + rpc_message->alloc_object_v.hObject = hObject; + rpc_message->alloc_object_v.hClass = hClass ; + rpc_message->alloc_object_v.param_len = 0; + + if (params != NULL) + { + status = _serializeClassParams_v25_08(pGpu, pRpc, hClass, params); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RmAllocObjectEx: vGPU: object RPC skipped (handle = 0x%08x, class = " + "0x%x) with non-NULL params ptr\n", hObject, hClass); + + // XXX: No RPC for unsupported classes. This must be taken care of. + // Return failure so that we can identify when this situation arises. + NV_ASSERT(0); + return status; + } + } + + status = _issueRpcAndWait(pGpu, pRpc); + + // Populate return values! + if ((status == NV_OK) && params) + { + status = _setRmReturnParams_v(pGpu, pRpc, hClass, params); + } + + return status; +} + +NV_STATUS rpcMapMemoryDma_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hDma, NvHandle hMemory, + NvU64 offset, NvU64 length, NvU32 flags, NvU64 *pDmaOffset) +{ + NV_STATUS status; + NVOS46_PARAMETERS_v03_00 *rpc_params = &rpc_message->map_memory_dma_v03_00.params; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA, sizeof(rpc_map_memory_dma_v03_00)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hDevice = hDevice; + rpc_params->hDma = hDma; + rpc_params->hMemory = hMemory; + rpc_params->flags = flags; + + rpc_params->offset = offset; + rpc_params->length = length; + rpc_params->dmaOffset = *pDmaOffset; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status == NV_OK) + { + *pDmaOffset = rpc_params->dmaOffset; + } + return status; +} + +NV_STATUS rpcUnmapMemoryDma_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hDma, + NvHandle hMemory, NvU32 flags, NvU64 pDmaOffset) +{ + NV_STATUS status; + NVOS47_PARAMETERS_v03_00 *rpc_params = &rpc_message->unmap_memory_dma_v03_00.params; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA, sizeof(rpc_unmap_memory_dma_v03_00)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hDevice = hDevice; + rpc_params->hDma = hDma; + rpc_params->hMemory = hMemory; + rpc_params->flags = flags; + rpc_params->dmaOffset = pDmaOffset; + + status = _issueRpcAndWait(pGpu, pRpc); + return status; +} + +NV_STATUS rpcAllocSubdevice_v08_01(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hSubDevice, + NvU32 hClass, NvU32 subDeviceInst) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + NVOS21_PARAMETERS_v03_00 *rpc_params = &rpc_message->alloc_subdevice_v08_01.params; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_SUBDEVICE, sizeof(rpc_alloc_subdevice_v08_01)); + if (status != NV_OK) + return status; + + rpc_params->hRoot = hClient; + rpc_params->hObjectParent = hDevice; + rpc_params->hObjectNew = hSubDevice; + rpc_params->hClass = hClass; + rpc_message->alloc_subdevice_v08_01.subDeviceInst = subDeviceInst; + + status = _issueRpcAndWait(pGpu, pRpc); + + return status; +} + +NV_STATUS rpcDupObject_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hParent, NvHandle hObject, + NvHandle hClientSrc, NvHandle hObjectSrc, NvU32 flags) +{ + NV_STATUS status = NV_OK; + NVOS55_PARAMETERS_v03_00 *rpc_params = &rpc_message->dup_object_v03_00.params; + + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && + !NV_IS_MODS) + { + Memory *pMemory = NULL; + RsResourceRef *pResourceRef = NULL; + NvU32 categoryClassId = 0; + RsClient *pRsClient; + + if ((status = serverGetClientUnderLock(&g_resServ, hClientSrc, &pRsClient)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get client under lock: 0x%x! hClient: 0x%x\n", + status, hClient); + return status; + } + + if (((status = clientGetResourceRef(pRsClient, hObjectSrc, &pResourceRef)) != NV_OK) || + (pResourceRef == NULL)) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get resource ref: 0x%x! hObject: 0x%x\n", status, + hObject); + return status; + } + + pMemory = dynamicCast(pResourceRef->pResource, Memory); + + if (pMemory != NULL) + { + categoryClassId = pMemory->categoryClassId; + + if ((categoryClassId == NV01_MEMORY_LOCAL_USER) || + (categoryClassId == NV01_MEMORY_FLA) || + (categoryClassId == NV50_MEMORY_VIRTUAL) || + (categoryClassId == NV01_MEMORY_SYSTEM) || + (categoryClassId == NV01_MEMORY_SYSTEM_OS_DESCRIPTOR)) + { + return NV_OK; + } + } + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_DUP_OBJECT, sizeof(rpc_dup_object_v03_00)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hParent = hParent; + rpc_params->hObject = hObject; + rpc_params->hClientSrc = hClientSrc; + rpc_params->hObjectSrc = hObjectSrc; + rpc_params->flags = flags; + + status = _issueRpcAndWait(pGpu, pRpc); + return status; +} + +/* max entries is how many 3 DWORD entries fit in what remains of the message_buffer */ +#define IDLE_CHANNELS_MAX_ENTRIES_v03_00 \ + ((pRpc->maxRpcSize - (sizeof(rpc_message_header_v) + sizeof(rpc_idle_channels_v03_00))) / sizeof(idle_channel_list_v03_00)) + +NV_STATUS rpcIdleChannels_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle *phClients, NvHandle *phDevices, NvHandle *phChannels, + NvU32 numEntries, NvU32 flags, NvU32 timeout) +{ + NV_STATUS status; + NvU32 i; + + if (numEntries > IDLE_CHANNELS_MAX_ENTRIES_v03_00) + { + // unable to fit all the entries in the message buffer + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: IdleChannels: requested %u entries (but only room for %u)\n", + numEntries, (NvU32)IDLE_CHANNELS_MAX_ENTRIES_v03_00); + return NV_ERR_GENERIC; + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS, + sizeof(rpc_idle_channels_v03_00) + numEntries * sizeof(idle_channel_list_v03_00)); + if (status != NV_OK) + return status; + + rpc_message->idle_channels_v03_00.flags = flags; + rpc_message->idle_channels_v03_00.timeout = timeout; + rpc_message->idle_channels_v03_00.nchannels = numEntries; + + for (i = 0; i < numEntries; i++) + { + rpc_message->idle_channels_v03_00.channel_list[i].phClient = ((NvU32) phClients[i]); + rpc_message->idle_channels_v03_00.channel_list[i].phDevice = ((NvU32) phDevices[i]); + rpc_message->idle_channels_v03_00.channel_list[i].phChannel = ((NvU32) phChannels[i]); + } + + status = _issueRpcAndWait(pGpu, pRpc); + return status; +} + +NV_STATUS rpcAllocEvent_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hParentClient, NvHandle hChannel, + NvHandle hObject, NvHandle hEvent, NvU32 hClass, NvU32 notifyIndex) +{ + NV_STATUS status; + + /* For full SRIOV, host cannot access memory with the help of memory handle + * So skip ALLOC_EVENT RPC for memory object. + */ + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && + !NV_IS_MODS) + { + RsClient *pRsClient; + RsResourceRef *pResourceRef = NULL; + + if ((status = serverGetClientUnderLock(&g_resServ, hParentClient, &pRsClient)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get client(0x%x) under lock: 0x%x!\n", + hParentClient, status); + return NV_ERR_INVALID_ARGUMENT; + } + + if (((status = clientGetResourceRef(pRsClient, hObject, &pResourceRef)) != NV_OK) || + (pResourceRef == NULL)) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to get resource ref: 0x%x! hObject: 0x%x\n", status, + hObject); + return NV_ERR_INVALID_ARGUMENT; + } + + if (pResourceRef->externalClassId == NV01_CONTEXT_DMA_FROM_MEMORY) + { + return NV_OK; + } + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_EVENT, sizeof(rpc_alloc_event_v03_00)); + if (status != NV_OK) + return status; + + rpc_message->alloc_event_v03_00.hClient = hClient; + rpc_message->alloc_event_v03_00.hParentClient = hParentClient; + rpc_message->alloc_event_v03_00.hChannel = hChannel; + rpc_message->alloc_event_v03_00.hObject = hObject; + rpc_message->alloc_event_v03_00.hEvent = hEvent; + rpc_message->alloc_event_v03_00.hClass = hClass; + rpc_message->alloc_event_v03_00.notifyIndex = notifyIndex; + + status = _issueRpcAndWait(pGpu, pRpc); + return status; +} + +NV_STATUS rpcDmaControl_v23_02(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcDmaControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcDmaControl_v24_01(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcDmaControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcDmaControl_v24_05(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcDmaControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcDmaControl_wrapper(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + if ((pParamStructPtr == NULL && paramSize != 0) || + (pParamStructPtr != NULL && paramSize == 0)) + { + NV_PRINTF(LEVEL_ERROR, "NVRM_RPC: Bad pParamStructPtr/paramSize \n"); + return NV_ERR_INVALID_PARAMETER; + } + + switch(cmd) + { + case NV2080_CTRL_CMD_FB_GET_DYNAMIC_OFFLINED_PAGES: + { + NvU32 i; + NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS *pFbDynamicOfflinedPages = NULL; + + pFbDynamicOfflinedPages = (NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS *)pParamStructPtr; + + i = pFbDynamicOfflinedPages->baseIndex / NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES; + if (i >= MAX_ITERATIONS_DYNAMIC_BLACKLIST) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pFbDynamicOfflinedPages->validEntries = pVSI->fbDynamicBlacklistedPages[i].validEntries; + if (pFbDynamicOfflinedPages->validEntries > NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES) + { + return NV_ERR_INVALID_ARGUMENT; + } + + portMemCopy(&pFbDynamicOfflinedPages->offlined, + pFbDynamicOfflinedPages->validEntries * sizeof(NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO), + &pVSI->fbDynamicBlacklistedPages[i].offlined, + pFbDynamicOfflinedPages->validEntries * sizeof(NV2080_CTRL_FB_DYNAMIC_OFFLINED_ADDRESS_INFO)); + pFbDynamicOfflinedPages->bMore = pVSI->fbDynamicBlacklistedPages[i].bMore; + return NV_OK; + } + + case NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE: + { + NvU32 i; + NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *pFifoDeviceInfoTable = NULL; + + pFifoDeviceInfoTable = (NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *)pParamStructPtr; + + i = pFifoDeviceInfoTable->baseIndex / NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES; + if (i >= MAX_ITERATIONS_DEVICE_INFO_TABLE) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pFifoDeviceInfoTable->numEntries = pVSI->fifoDeviceInfoTable[i].numEntries; + if (pFifoDeviceInfoTable->numEntries > NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pFifoDeviceInfoTable->bMore = pVSI->fifoDeviceInfoTable[i].bMore; + + portMemCopy(&pFifoDeviceInfoTable->entries, + pFifoDeviceInfoTable->numEntries * sizeof(NV2080_CTRL_FIFO_DEVICE_ENTRY), + pVSI->fifoDeviceInfoTable[i].entries, + pFifoDeviceInfoTable->numEntries * sizeof(NV2080_CTRL_FIFO_DEVICE_ENTRY)); + return NV_OK; + } + + case NV2080_CTRL_CMD_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS: + { + NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *pMcEngineNotificationIntrVectors = NULL; + pMcEngineNotificationIntrVectors = (NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS*)pParamStructPtr; + + *pMcEngineNotificationIntrVectors = pVSI->mcEngineNotificationIntrVectors; + return NV_OK; + } + + case NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE: + { + NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *pMcStaticIntrTable = (NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS*)pParamStructPtr; + + *pMcStaticIntrTable = pVSI->mcStaticIntrTable; + return NV_OK; + } + + case NV2080_CTRL_CMD_GR_GET_ZCULL_INFO: + { + NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *pGrZcullInfo = (NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *)pParamStructPtr; + + *pGrZcullInfo = pVSI->grZcullInfo; + return NV_OK; + } + + case NV0080_CTRL_CMD_FIFO_IDLE_CHANNELS: + return NV_ERR_NOT_SUPPORTED; + + case NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO: + return rpcCtrlNvencSwSessionUpdateInfo_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV906F_CTRL_CMD_RESET_CHANNEL: + return rpcCtrlResetChannel_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL: + return rpcCtrlResetIsolatedChannel_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT: + return rpcCtrlGpuHandleVfPriFault_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_PERF_BOOST: + return rpcCtrlPerfBoost_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE: + return rpcCtrlGetZbcClearTable_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV9096_CTRL_CMD_SET_ZBC_COLOR_CLEAR: + return rpcCtrlSetZbcColorClear_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV9096_CTRL_CMD_SET_ZBC_DEPTH_CLEAR: + return rpcCtrlSetZbcDepthClear_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVA06C_CTRL_CMD_GPFIFO_SCHEDULE: + case NVA06F_CTRL_CMD_GPFIFO_SCHEDULE: + return rpcCtrlGpfifoSchedule_HAL(pGpu, pRpc, hClient, hObject, cmd , pParamStructPtr); + + case NVA06C_CTRL_CMD_SET_TIMESLICE: + return rpcCtrlSetTimeslice_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS: + return rpcCtrlFifoDisableChannels_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVA06C_CTRL_CMD_PREEMPT: + return rpcCtrlPreempt_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVA06C_CTRL_CMD_SET_INTERLEAVE_LEVEL: + return rpcCtrlSetTsgInterleaveLevel_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVA06F_CTRL_CMD_SET_INTERLEAVE_LEVEL: + return rpcCtrlSetChannelInterleaveLevel_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES: + return rpcCtrlDbgClearAllSmErrorStates_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK: + return rpcCtrlDbgSetExceptionMask_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GPU_PROMOTE_CTX: + return rpcCtrlGpuPromoteCtx_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_FB_GET_LTC_INFO_FOR_FBP: + { + NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS *pFbLtcInfoForFbp = (NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS *)pParamStructPtr; + + if (pFbLtcInfoForFbp->fbpIndex >= MAX_FBPS) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pFbLtcInfoForFbp->ltcCount = pVSI->fbLtcInfoForFbp[pFbLtcInfoForFbp->fbpIndex].ltcCount; + pFbLtcInfoForFbp->ltcMask = pVSI->fbLtcInfoForFbp[pFbLtcInfoForFbp->fbpIndex].ltcMask; + + return NV_OK; + } + + case NV2080_CTRL_CMD_CE_GET_CAPS_V2: + { + NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *pCeCaps = (NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *)pParamStructPtr; + NvU32 i; + NvU32 ceNumber; + + // If engine disabled, return error and not empty caps. + if ((pVSI->engineList & NVBIT64(pCeCaps->ceEngineType)) == 0) + { + portMemSet(&pCeCaps->capsTbl, 0, NV2080_CTRL_CE_CAPS_TBL_SIZE); + return NV_ERR_NOT_SUPPORTED; + } + + ceNumber = NV2080_ENGINE_TYPE_COPY_IDX(pCeCaps->ceEngineType); + + if (ceNumber >= NV2080_ENGINE_TYPE_COPY_SIZE) + { + return NV_ERR_INVALID_ARGUMENT; + } + + for (i = 0; i < NV2080_ENGINE_TYPE_COPY_SIZE; i++) + { + if (pCeCaps->ceEngineType == pVSI->ceCaps[i].ceEngineType) + { + portMemCopy(&pCeCaps->capsTbl, NV2080_CTRL_CE_CAPS_TBL_SIZE, + &pVSI->ceCaps[i].capsTbl, NV2080_CTRL_CE_CAPS_TBL_SIZE); + + return NV_OK; + } + } + + return NV_ERR_NOT_SUPPORTED; + } + + case NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS: + { + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *pNvLinkCaps = (NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *)pParamStructPtr; + + portMemCopy(pNvLinkCaps, sizeof(pVSI->nvlinkCaps), + &pVSI->nvlinkCaps, sizeof(pVSI->nvlinkCaps)); + + return NV_OK; + } + + case NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND: + return rpcCtrlGrCtxswPreemptionBind_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE: + return rpcCtrlGrSetCtxswPreemptionMode_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND: + return rpcCtrlGrCtxswZcullBind_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GPU_INITIALIZE_CTX: + return rpcCtrlGpuInitializeCtx_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES: + return rpcCtrlVaspaceCopyServerReservedPdes_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS: + return rpcCtrlMcServiceInterrupts_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0080_CTRL_DMA_SET_DEFAULT_VASPACE: + return rpcCtrlDmaSetDefaultVaspace_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK: + return rpcCtrlGetCePceMask_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY: + return rpcCtrlGetZbcClearTableEntry_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_BUS_GET_NVLINK_PEER_ID_MASK: + return rpcCtrlGetNvlinkPeerIdMask_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS: + return rpcCtrlGetNvlinkStatus_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX: + return rpcCtrlGetP2pCapsMatrix_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_RESERVE_PM_AREA_SMPC: + return rpcCtrlReservePmAreaSmpc_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_RESERVE_HWPM_LEGACY: + return rpcCtrlReserveHwpmLegacy_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_EXEC_REG_OPS: + return rpcCtrlB0ccExecRegOps_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_BIND_PM_RESOURCES: + return rpcCtrlBindPmResources_HAL(pGpu, pRpc, hClient, hObject); + + case NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT: + return rpcCtrlDbgSuspendContext_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_RESUME_CONTEXT: + return rpcCtrlDbgResumeContext_HAL(pGpu, pRpc, hClient, hObject); + + case NV83DE_CTRL_CMD_DEBUG_EXEC_REG_OPS: + return rpcCtrlDbgExecRegOps_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_SET_MODE_MMU_DEBUG: + return rpcCtrlDbgSetModeMmuDebug_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE: + return rpcCtrlDbgClearSingleSmErrorState_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_SET_MODE_ERRBAR_DEBUG: + return rpcCtrlDbgSetModeErrbarDebug_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE: + return rpcCtrlDbgSetNextStopTriggerType_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY: + return rpcUnsetPageDirectory_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM: + case NVB0CC_CTRL_CMD_INTERNAL_ALLOC_PMA_STREAM: + return rpcCtrlAllocPmaStream_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_PMA_STREAM_UPDATE_GET_PUT: + return rpcCtrlPmaStreamUpdateGetPut_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_FB_GET_INFO_V2: + return rpcCtrlFbGetInfoV2_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0080_CTRL_CMD_FIFO_SET_CHANNEL_PROPERTIES: + return rpcCtrlFifoSetChannelProperties_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GPU_EVICT_CTX: + return rpcCtrlGpuEvictCtx_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVA06F_CTRL_CMD_STOP_CHANNEL: + return rpcCtrlStopChannel_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_FB_GET_FS_INFO: + return rpcCtrlFbGetFsInfo_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO: + return rpcCtrlGrmgrGetGrFsInfo_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE: + return rpcCtrlGrPcSamplingMode_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL: + return rpcCtrlPerfRatedTdpSetControl_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_FREE_PMA_STREAM: + return rpcCtrlFreePmaStream_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ: + return rpcCtrlTimerSetGrTickFreq_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER: + { + NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *pParams = pParamStructPtr; + + pParams->imla0 = pVSI->grSmIssueRateModifier.imla0; + pParams->fmla16 = pVSI->grSmIssueRateModifier.fmla16; + pParams->dp = pVSI->grSmIssueRateModifier.dp; + pParams->fmla32 = pVSI->grSmIssueRateModifier.fmla32; + pParams->ffma = pVSI->grSmIssueRateModifier.ffma; + pParams->imla1 = pVSI->grSmIssueRateModifier.imla1; + pParams->imla2 = pVSI->grSmIssueRateModifier.imla2; + pParams->imla3 = pVSI->grSmIssueRateModifier.imla3; + pParams->imla4 = pVSI->grSmIssueRateModifier.imla4; + return NV_OK; + } + + case NV2080_CTRL_CMD_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB: + return rpcCtrlFifoSetupVfZombieSubctxPdb_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_SET_SINGLE_SM_SINGLE_STEP: + return rpcCtrlDbgSetSingleSmSingleStep_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0080_CTRL_CMD_GR_GET_TPC_PARTITION_MODE: + return rpcCtrlGrGetTpcPartitionMode_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE: + return rpcCtrlGrSetTpcPartitionMode_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL: + return rpcCtrlInternalQuiescePmaChannel_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_BUS_GET_INFO_V2: + { + NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *pParams = pParamStructPtr; + NvU32 i; + + if (pParams->busInfoListSize > NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09) + { + return NV_ERR_INVALID_ARGUMENT; + } + + for (i = 0; i < pParams->busInfoListSize; i++) + { + pParams->busInfoList[i].data = pVSI->busGetInfoV2.busInfoList[pParams->busInfoList[i].index].data; + } + + return NV_OK; + } + + case NV0080_CTRL_CMD_FIFO_GET_LATENCY_BUFFER_SIZE: + { + NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS *pFifoLatecyBufferSize = (NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS *)pParamStructPtr; + NvU32 i; + + for (i = 0; i < NV2080_ENGINE_TYPE_LAST_v1C_09; i++) + { + if (pFifoLatecyBufferSize->engineID == pVSI->fifoLatencyBufferSize[i].engineID) + { + pFifoLatecyBufferSize->gpEntries = pVSI->fifoLatencyBufferSize[i].gpEntries; + pFifoLatecyBufferSize->pbEntries = pVSI->fifoLatencyBufferSize[i].pbEntries; + break; + } + } + + NV_ASSERT_OR_RETURN(i < NV2080_ENGINE_TYPE_LAST_v1C_09, NV_ERR_INVALID_ARGUMENT); + + return NV_OK; + } + + case NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM: + return rpcCtrlInternalSriovPromotePmaStream_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0090_CTRL_CMD_GET_MMU_DEBUG_MODE: + return rpcCtrlGetMmuDebugMode_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVA06C_CTRL_CMD_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS: + return rpcCtrlInternalPromoteFaultMethodBuffers_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV00F8_CTRL_CMD_DESCRIBE: + return rpcCtrlFabricMemoryDescribe_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_FLA_GET_FABRIC_MEM_STATS: + return rpcCtrlFabricMemStats_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED: + return rpcCtrlInternalMemsysSetZbcReferenced_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS: + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *pParams = NULL; + + pParams = (NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *)pParamStructPtr; + + for (NvU32 i = 0; i < NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08; i++) { + pParams->atomicOp[i].bSupported = pVSI->pcieSupportedGpuAtomics.atomicOp[i].bSupported; + pParams->atomicOp[i].attributes = pVSI->pcieSupportedGpuAtomics.atomicOp[i].attributes; + } + return NV_OK; + } + + case NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE: + return rpcCtrlExecPartitionsDelete_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN: + return rpcCtrlGpfifoGetWorkSubmitToken_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX: + return rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK: + return rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS: + return rpcCtrlGetP2pCaps_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2: + return rpcCtrlGetP2pCapsV2_HAL(pGpu, pRpc, pParamStructPtr); + + case NV2080_CTRL_CMD_GET_P2P_CAPS: + return rpcCtrlSubdeviceGetP2pCaps_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING: + return rpcCtrlBusSetP2pMapping_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_BUS_UNSET_P2P_MAPPING: + return rpcCtrlBusUnsetP2pMapping_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK: + return rpcCtrlFlaSetupInstanceMemBlock_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_READ_ALL_SM_ERROR_STATES: + return rpcCtrlDbgReadAllSmErrorStates_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_READ_SINGLE_SM_ERROR_STATE: + return rpcCtrlDbgReadSingleSmErrorState_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GPU_MIGRATABLE_OPS: + return rpcCtrlGpuMigratableOps_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS: + return rpcCtrlGetTotalHsCredits_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_GET_HS_CREDITS: + return rpcCtrlGetHsCredits_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NVB0CC_CTRL_CMD_SET_HS_CREDITS: + return rpcCtrlSetHsCredits_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GPU_GET_INFO_V2: + return rpcCtrlGpuGetInfoV2_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV0080_CTRL_CMD_GPU_GET_BRAND_CAPS: + return rpcGetBrandCaps_HAL(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); + + case NV2080_CTRL_CMD_CE_GET_ALL_CAPS: + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pParams = NULL; + + pParams = (NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *)pParamStructPtr; + + pParams->present = pVSI->ceGetAllCaps.present; + + for (NvU32 i = 0; i < NV2080_CTRL_MAX_PCES_v21_0A; i++) { + portMemCopy(pParams->capsTbl[i], (sizeof(NvU8) * NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A), + pVSI->ceGetAllCaps.capsTbl[i], (sizeof(NvU8) * NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A)); + } + return NV_OK; + } + + case NVB0CC_CTRL_CMD_RESERVE_PM_AREA_PC_SAMPLER: + case NVB0CC_CTRL_CMD_RELEASE_PM_AREA_PC_SAMPLER: + return rpcCtrlPmAreaPcSampler_HAL(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr); + + case NV2080_CTRL_CMD_BUS_GET_C2C_INFO: + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *pParams = NULL; + + pParams = (NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *)pParamStructPtr; + + pParams->bIsLinkUp = pVSI->c2cInfo.bIsLinkUp; + pParams->nrLinks = pVSI->c2cInfo.nrLinks; + pParams->linkMask = pVSI->c2cInfo.linkMask; + pParams->perLinkBwMBps = pVSI->c2cInfo.perLinkBwMBps; + pParams->remoteType = pVSI->c2cInfo.remoteType; + + return NV_OK; + } + + case NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS: + return rpcCtrlGpuQueryEccStatus_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_GPU_RESET_ECC_ERROR_STATUS: + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NvU32 i; + for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06; i++) + { + if (pVSI->eccStatus.units[i].supported) + { + pVSI->eccStatus.units[i].sbe.count = 0; + pVSI->eccStatus.units[i].dbe.count = 0; + } + } + return NV_OK; + } + + case NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE: + return rpcCtrlExecPartitionsCreate_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV83DE_CTRL_CMD_DEBUG_GET_MODE_MMU_DEBUG: + return rpcCtrlDbgGetModeMmuDebug_HAL(pGpu, pRpc, hClient, hObject, pParamStructPtr); + + case NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE: + return rpcCtrlCmdInternalGpuStartFabricProbe_HAL(pGpu, pRpc, pParamStructPtr); + + case NVA06F_CTRL_CMD_BIND : + { + return NV_OK; + } + + case NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES: + { + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (gpuIsClientRmAllocatedCtxBufferEnabled(pGpu)) + { + NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS *pParams =(NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS *)pParamStructPtr; + NvU32 size = 0; + NvU32 alignment = RM_PAGE_SIZE; + NvU32 engine; + + pParams->size = 0; + pParams->alignment = 0; + + engine = DRF_VAL(0080_CTRL_FIFO, _GET_ENGINE_CONTEXT_PROPERTIES, _ENGINE_ID, + pParams->engineId); + + switch(engine) + { + case NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS: + case NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL: + case NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PREEMPT: + case NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SPILL: + case NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PAGEPOOL: + case NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_BETACB: + case NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_RTV: + pParams->size = NV_MAX(pVSI->ctxBuffInfo.engineContextBuffersInfo[0].engine[engine].size, size); + pParams->alignment = NV_MAX(pVSI->ctxBuffInfo.engineContextBuffersInfo[0].engine[engine].alignment, alignment); + status = NV_OK; + break; + + default: + status = NV_ERR_NOT_SUPPORTED; + } + return status; + } + + return status; + } + + default: + { + NV_PRINTF(LEVEL_ERROR, "DMA Control Command cmd 0x%x NOT supported\n", cmd); + } + } + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS rpcCtrlStopChannel_v1A_1E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVA06F_CTRL_STOP_CHANNEL_PARAMS *pParams = (NVA06F_CTRL_STOP_CHANNEL_PARAMS *)pParamStructPtr; + rpc_ctrl_stop_channel_v1A_1E *rpc_params = &rpc_message->ctrl_stop_channel_v1A_1E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_STOP_CHANNEL, + sizeof(rpc_ctrl_stop_channel_v1A_1E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpuEvictCtx_v1A_1C(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GPU_EVICT_CTX_PARAMS *pParams = (NV2080_CTRL_GPU_EVICT_CTX_PARAMS *)pParamStructPtr; + rpc_ctrl_gpu_evict_ctx_v1A_1C *rpc_params = &rpc_message->ctrl_gpu_evict_ctx_v1A_1C; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPU_EVICT_CTX, + sizeof(rpc_ctrl_gpu_evict_ctx_v1A_1C)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v1A_1C(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v1A_1C(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlFbGetFsInfo_v24_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_FB_GET_FS_INFO_PARAMS *pParams = (NV2080_CTRL_FB_GET_FS_INFO_PARAMS *)pParamStructPtr; + rpc_ctrl_fb_get_fs_info_v24_00 *rpc_buffer_params = &rpc_message->ctrl_fb_get_fs_info_v24_00; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_FS_INFO, + sizeof(rpc_ctrl_fb_get_fs_info_v24_00)); + if (status != NV_OK) + return status; + + ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERIES_v24_00 == NV2080_CTRL_FB_FS_INFO_MAX_QUERIES); + ct_assert(NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE_v1A_1D == NV2080_CTRL_FB_FS_INFO_MAX_QUERY_SIZE); + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Get FB FS Info RPC failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGrmgrGetGrFsInfo_v1A_1D(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *pParams = (NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS *)pParamStructPtr; + rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D *rpc_buffer_params = &rpc_message->ctrl_grmgr_get_gr_fs_info_v1A_1D; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_GRMGR_GET_GR_FS_INFO, + sizeof(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D)); + if (status != NV_OK) + return status; + + ct_assert(NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES_v1A_1D == NV2080_CTRL_GRMGR_GR_FS_INFO_MAX_QUERIES); + ct_assert(NV2080_CTRL_GRMGR_MAX_SMC_IDS_v1A_1D == NV2080_CTRL_GRMGR_MAX_SMC_IDS); + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Get GR FS Info RPC failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + return status; +} + +NV_STATUS rpcCtrlFlaSetupInstanceMemBlock_v21_05 +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr +) +{ + NV_STATUS status; + NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS *pParams = (NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS*)pParamStructPtr; + rpc_ctrl_fla_setup_instance_mem_block_v21_05 *rpc_params = &rpc_message->ctrl_fla_setup_instance_mem_block_v21_05; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK, + sizeof(rpc_ctrl_fla_setup_instance_mem_block_v21_05)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK_v21_05( + pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_CMD_FLA_SETUP_INSTANCE_MEM_BLOCK_v21_05( + pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetTotalHsCredits_v21_08(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *pParams = (NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS *)pParamStructPtr; + rpc_ctrl_get_total_hs_credits_v21_08 *rpc_buffer_params = &rpc_message->ctrl_get_total_hs_credits_v21_08; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_GET_TOTAL_HS_CREDITS, + sizeof(rpc_ctrl_get_total_hs_credits_v21_08)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to get total hs credits failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetHsCredits_v21_08(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *pParams = (NVB0CC_CTRL_GET_HS_CREDITS_PARAMS *)pParamStructPtr; + rpc_ctrl_get_hs_credits_v21_08 *rpc_buffer_params = &rpc_message->ctrl_get_hs_credits_v21_08; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_GET_HS_CREDITS, + sizeof(rpc_ctrl_get_hs_credits_v21_08)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to get hs credits failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + return status; +} + +NV_STATUS rpcCtrlSetHsCredits_v21_08(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *pParams = (NVB0CC_CTRL_SET_HS_CREDITS_PARAMS *)pParamStructPtr; + rpc_ctrl_set_hs_credits_v21_08 *rpc_buffer_params = &rpc_message->ctrl_set_hs_credits_v21_08; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_SET_HS_CREDITS, + sizeof(rpc_ctrl_set_hs_credits_v21_08)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to set hs credits failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + return status; +} + +NV_STATUS rpcCtrlPmAreaPcSampler_v21_0B(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd,void *pParamStructPtr) +{ + NV_STATUS status; + rpc_ctrl_pm_area_pc_sampler_v21_0B *rpc_buffer_params = &rpc_message->ctrl_pm_area_pc_sampler_v21_0B; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_PM_AREA_PC_SAMPLER, + sizeof(rpc_ctrl_pm_area_pc_sampler_v21_0B)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + rpc_buffer_params->cmd = cmd; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + return status; +} + +static NV_STATUS rpcRmApiControl_wrapper(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + NvU8 *dest = (NvU8 *)&rpc_message->rm_api_control_v.rm_api_params; + NvU8 *pParams = pParamStructPtr; + NvU32 rpc_param_header_size = sizeof(rpc_rm_api_control_v); + NVOS54_PARAMETERS_v03_00 *rpc_params = &rpc_message->rm_api_control_v.params; + NV_STATUS status; + + const NvU32 fixed_param_size = sizeof(rpc_message_header_v) + sizeof(NVOS54_PARAMETERS_v03_00); + NvU32 message_buffer_remaining = pRpc->largeRpcSize - fixed_param_size; + + if (message_buffer_remaining < paramSize) + { + return NV_ERR_NOT_SUPPORTED; + } + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_RM_API_CONTROL, + rpc_param_header_size); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + rpc_params->cmd = cmd; + rpc_params->paramsSize = paramSize; + + portMemCopy(dest, paramSize, pParams, paramSize); + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + { + if (status == NV_VGPU_MSG_RESULT_RPC_API_CONTROL_NOT_SUPPORTED) + { + status = NV_ERR_NOT_SUPPORTED; + } + else + { + NV_PRINTF(LEVEL_ERROR, "API control 0x%x failed with status 0x%x\n", rpc_params->cmd, status); + } + return status; + } + portMemCopy(pParams, paramSize, dest, paramSize); + + return rpc_params->status; +} + +NV_STATUS rpcRmApiControl_v25_0D(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcRmApiControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcRmApiControl_v25_0F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcRmApiControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcRmApiControl_v25_10(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcRmApiControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcRmApiControl_v25_14(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcRmApiControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcRmApiControl_v25_15(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcRmApiControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcRmApiControl_v25_16(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcRmApiControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcRmApiControl_v25_17(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcRmApiControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcRmApiControl_v25_18(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + return rpcRmApiControl_wrapper(pGpu, pRpc, hClient, hObject, cmd, pParamStructPtr, paramSize); +} + +NV_STATUS rpcGetBrandCaps_v25_12(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, + void *pParamStructPtr, NvU32 paramSize) +{ + NV_STATUS status; + NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS *pParams = (NV0080_CTRL_GPU_GET_BRAND_CAPS_PARAMS*)pParamStructPtr; + rpc_get_brand_caps_v25_12 *rpc_params = &rpc_message->get_brand_caps_v25_12; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_GET_BRAND_CAPS, + sizeof(rpc_get_brand_caps_v25_12)); + if (status != NV_OK) + return status; + + status = serialize_GET_BRAND_CAPS_v25_12(pParams, (NvU8 *)rpc_params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to get brand caps failed with error 0x%x\n", status); + return status; + } + + status = deserialize_GET_BRAND_CAPS_v25_12(pParams, (NvU8 *)rpc_params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlNvencSwSessionUpdateInfo_v1A_09(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams = (NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *)pParamStructPtr; + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 *rpc_ctrl_params = &rpc_message->ctrl_nvenc_sw_session_update_info_v1A_09.nvencSessionUpdate; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_NVENC_SW_SESSION_UPDATE_INFO, + sizeof(rpc_ctrl_nvenc_sw_session_update_info_v1A_09)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_nvenc_sw_session_update_info_v1A_09.hClient = hClient; + rpc_message->ctrl_nvenc_sw_session_update_info_v1A_09.hObject = hObject; + + status = serialize_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlResetChannel_v1A_09(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *pParams = (NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS *)pParamStructPtr; + NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 *rpc_ctrl_params = &rpc_message->ctrl_reset_channel_v1A_09.resetChannel; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_RESET_CHANNEL, + sizeof(rpc_ctrl_reset_channel_v1A_09)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_reset_channel_v1A_09.hClient = hClient; + rpc_message->ctrl_reset_channel_v1A_09.hObject = hObject; + + status = serialize_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlResetIsolatedChannel_v1A_09(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *pParams = (NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *)pParamStructPtr; + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 *rpc_ctrl_params = &rpc_message->ctrl_reset_isolated_channel_v1A_09.resetIsolatedChannel; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_RESET_ISOLATED_CHANNEL, + sizeof(rpc_ctrl_reset_isolated_channel_v1A_09)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_reset_isolated_channel_v1A_09.hClient = hClient; + rpc_message->ctrl_reset_isolated_channel_v1A_09.hObject = hObject; + + status = serialize_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpuHandleVfPriFault_v1A_09(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *pParams = (NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS *)pParamStructPtr; + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 *rpc_ctrl_params = &rpc_message->ctrl_gpu_handle_vf_pri_fault_v1A_09.handleVfPriFault; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPU_HANDLE_VF_PRI_FAULT, + sizeof(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_gpu_handle_vf_pri_fault_v1A_09.hClient = hClient; + rpc_message->ctrl_gpu_handle_vf_pri_fault_v1A_09.hObject = hObject; + + status = serialize_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlPerfBoost_v1A_09(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_PERF_BOOST_PARAMS *pParams = (NV2080_CTRL_PERF_BOOST_PARAMS *)pParamStructPtr; + NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 *rpc_ctrl_params = &rpc_message->ctrl_perf_boost_v1A_09.perfBoost; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_PERF_BOOST, + sizeof(rpc_ctrl_perf_boost_v1A_09)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_perf_boost_v1A_09.hClient = hClient; + rpc_message->ctrl_perf_boost_v1A_09.hObject = hObject; + + status = serialize_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetZbcClearTable_v1A_09(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *pParams = (NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS *)pParamStructPtr; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 *rpc_ctrl_params = &rpc_message->ctrl_get_zbc_clear_table_v1A_09.getZbcClearTable; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE, + sizeof(rpc_ctrl_get_zbc_clear_table_v1A_09)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_get_zbc_clear_table_v1A_09.hClient = hClient; + rpc_message->ctrl_get_zbc_clear_table_v1A_09.hObject = hObject; + + status = serialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlSetZbcColorClear_v1A_09(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *pParams = (NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS *)pParamStructPtr; + NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 *rpc_ctrl_params = &rpc_message->ctrl_set_zbc_color_clear_v1A_09.setZbcColorClr; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_COLOR_CLEAR, + sizeof(rpc_ctrl_set_zbc_color_clear_v1A_09)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_set_zbc_color_clear_v1A_09.hClient = hClient; + rpc_message->ctrl_set_zbc_color_clear_v1A_09.hObject = hObject; + + status = serialize_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlSetZbcDepthClear_v1A_09(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *pParams = (NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS *)pParamStructPtr; + NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 *rpc_ctrl_params = &rpc_message->ctrl_set_zbc_depth_clear_v1A_09.setZbcDepthClr; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_SET_ZBC_DEPTH_CLEAR, + sizeof(rpc_ctrl_set_zbc_depth_clear_v1A_09)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_set_zbc_depth_clear_v1A_09.hClient = hClient; + rpc_message->ctrl_set_zbc_depth_clear_v1A_09.hObject = hObject; + + status = serialize_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpfifoSchedule_v1A_0A(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, NvU32 cmd, void *pParamStructPtr) +{ + NV_STATUS status; + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *pParams = (NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *)pParamStructPtr; + NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 *rpc_ctrl_params = &rpc_message->ctrl_gpfifo_schedule_v1A_0A.gpfifoSchedule; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SCHEDULE, + sizeof(rpc_ctrl_gpfifo_schedule_v1A_0A)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_gpfifo_schedule_v1A_0A.hClient = hClient; + rpc_message->ctrl_gpfifo_schedule_v1A_0A.hObject = hObject; + rpc_message->ctrl_gpfifo_schedule_v1A_0A.cmd = cmd; + + status = serialize_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlSetTimeslice_v1A_0A(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVA06C_CTRL_TIMESLICE_PARAMS *pParams = (NVA06C_CTRL_TIMESLICE_PARAMS *)pParamStructPtr; + NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 *rpc_ctrl_params = &rpc_message->ctrl_set_timeslice_v1A_0A.setTimeSlice; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_SET_TIMESLICE, + sizeof(rpc_ctrl_set_timeslice_v1A_0A)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_set_timeslice_v1A_0A.hClient = hClient; + rpc_message->ctrl_set_timeslice_v1A_0A.hObject = hObject; + + status = serialize_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlFifoDisableChannels_v1A_0A(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *pParams = (NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS *)pParamStructPtr; + NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 *rpc_ctrl_params = &rpc_message->ctrl_fifo_disable_channels_v1A_0A.fifoDisableChannels; + + ct_assert(NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES == 64); + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_FIFO_DISABLE_CHANNELS, + sizeof(rpc_ctrl_fifo_disable_channels_v1A_0A)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_fifo_disable_channels_v1A_0A.hClient = hClient; + rpc_message->ctrl_fifo_disable_channels_v1A_0A.hObject = hObject; + + status = serialize_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlPreempt_v1A_0A(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVA06C_CTRL_PREEMPT_PARAMS *pParams = (NVA06C_CTRL_PREEMPT_PARAMS *)pParamStructPtr; + NVA06C_CTRL_PREEMPT_PARAMS_v09_0A *rpc_ctrl_params = &rpc_message->ctrl_preempt_v1A_0A.cmdPreempt; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_PREEMPT, + sizeof(rpc_ctrl_preempt_v1A_0A)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_preempt_v1A_0A.hClient = hClient; + rpc_message->ctrl_preempt_v1A_0A.hObject = hObject; + + status = serialize_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlSetTsgInterleaveLevel_v1A_0A(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams = (NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS *)pParamStructPtr; + NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *rpc_ctrl_params = &rpc_message->ctrl_set_tsg_interleave_level_v1A_0A.interleaveLevelTSG; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_SET_TSG_INTERLEAVE_LEVEL, + sizeof(rpc_ctrl_set_tsg_interleave_level_v1A_0A)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_set_tsg_interleave_level_v1A_0A.hClient = hClient; + rpc_message->ctrl_set_tsg_interleave_level_v1A_0A.hObject = hObject; + + status = serialize_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlSetChannelInterleaveLevel_v1A_0A(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *pParams = (NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS *)pParamStructPtr; + NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 *rpc_ctrl_params = &rpc_message->ctrl_set_channel_interleave_level_v1A_0A.interleaveLevelChannel; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_SET_CHANNEL_INTERLEAVE_LEVEL, + sizeof(rpc_ctrl_set_channel_interleave_level_v1A_0A)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_set_channel_interleave_level_v1A_0A.hClient = hClient; + rpc_message->ctrl_set_channel_interleave_level_v1A_0A.hObject = hObject; + + status = serialize_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGrCtxswPreemptionBind_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *pParams = (NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS *)pParamStructPtr; + rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E *rpc_params = &rpc_message->ctrl_gr_ctxsw_preemption_bind_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_PREEMPTION_BIND, + sizeof(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGrSetCtxswPreemptionMode_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *pParams = (NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS *)pParamStructPtr; + rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E *rpc_params = &rpc_message->ctrl_gr_set_ctxsw_preemption_mode_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_CTXSW_PREEMPTION_MODE, + sizeof(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGrCtxswZcullBind_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *pParams = (NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *)pParamStructPtr; + rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E *rpc_params = &rpc_message->ctrl_gr_ctxsw_zcull_bind_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GR_CTXSW_ZCULL_BIND, + sizeof(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpuInitializeCtx_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *pParams = (NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS *)pParamStructPtr; + rpc_ctrl_gpu_initialize_ctx_v1A_0E *rpc_params = &rpc_message->ctrl_gpu_initialize_ctx_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPU_INITIALIZE_CTX, + sizeof(rpc_ctrl_gpu_initialize_ctx_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlVaspaceCopyServerReservedPdes_v1E_04(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *pParams = (NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS *)pParamStructPtr; + rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 *rpc_params = &rpc_message->ctrl_vaspace_copy_server_reserved_pdes_v1E_04; + + ct_assert(GMMU_FMT_MAX_LEVELS_v1A_12 == GMMU_FMT_MAX_LEVELS); + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES, + sizeof(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlMcServiceInterrupts_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *pParams = (NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS *)pParamStructPtr; + rpc_ctrl_mc_service_interrupts_v1A_0E *rpc_params = &rpc_message->ctrl_mc_service_interrupts_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_MC_SERVICE_INTERRUPTS, + sizeof(rpc_ctrl_mc_service_interrupts_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetP2pCapsV2_v1F_0D +( + OBJGPU *pGpu, + OBJRPC *pRpc, + void *pParamStructPtr +) +{ + NV_STATUS status; + NvU32 headerLength; + NvU32 index = 0; + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *pParams = (NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS *)pParamStructPtr; + + headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_ctrl_get_p2p_caps_v2_v1F_0D); + if (headerLength > pRpc->maxRpcSize) + { + NV_PRINTF(LEVEL_ERROR, + "vGPU P2P_V2 parameters size (0x%x) exceed message_buffer " + "size (0x%x)\n", headerLength, pRpc->maxRpcSize); + + NV_ASSERT(0); + return NV_ERR_BUFFER_TOO_SMALL; + } + + if (pParams->gpuCount >= NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS) + { + NV_ASSERT(0); + return NV_ERR_INVALID_DATA; + } + + /* + * Not all 1024 entries can be fit in 4k RPC buffer. Hence we fetch in + * 2 iterations. + */ + for (index = 0; index < NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED / VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC; index++) + { + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_V2, + sizeof(rpc_ctrl_get_p2p_caps_v2_v1F_0D)); + if (status != NV_OK) + goto exit; + + /* Fill up the input values to the RPC */ + rpc_message->ctrl_get_p2p_caps_v2_v1F_0D.iter = index; + rpc_message->ctrl_get_p2p_caps_v2_v1F_0D.gpuCount = pParams->gpuCount; + portMemCopy(rpc_message->ctrl_get_p2p_caps_v2_v1F_0D.gpuIds, + NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS * sizeof(NvU32), + pParams->gpuIds, + NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS * sizeof(NvU32)); + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to fetch P2P caps failed with error 0x%x\n", status); + goto exit; + } + + if (index == 0) + { + /* + * Copy this only once as the values stays the same across + * iterations. + */ + pParams->p2pCaps = rpc_message->ctrl_get_p2p_caps_v2_v1F_0D.p2pCaps; + pParams->p2pOptimalReadCEs = rpc_message->ctrl_get_p2p_caps_v2_v1F_0D.p2pOptimalReadCEs; + pParams->p2pOptimalWriteCEs = rpc_message->ctrl_get_p2p_caps_v2_v1F_0D.p2pOptimalWriteCEs; + + portMemCopy(pParams->p2pCapsStatus, + NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D, + rpc_message->ctrl_get_p2p_caps_v2_v1F_0D.p2pCapsStatus, + NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D); + } + + /* + * Copy 512 entries at a time. The value of the iter detemines which + * blob of 512 entries be copied during this RPC call. + */ + portMemCopy((pParams->busPeerIds + index * VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC), + VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC * sizeof(NvU32), + rpc_message->ctrl_get_p2p_caps_v2_v1F_0D.busPeerIds, + VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC * sizeof(NvU32)); + } + +exit: + return status; +} + +NV_STATUS rpcCtrlSubdeviceGetP2pCaps_v21_02(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GET_P2P_CAPS_PARAMS *pParams = (NV2080_CTRL_GET_P2P_CAPS_PARAMS *)pParamStructPtr; + rpc_ctrl_subdevice_get_p2p_caps_v21_02 *rpc_params = &rpc_message->ctrl_subdevice_get_p2p_caps_v21_02; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_SUBDEVICE_GET_P2P_CAPS, + sizeof(rpc_ctrl_subdevice_get_p2p_caps_v21_02)); + if (status != NV_OK) + return status; + + status = serialize_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02(pParams, (NvU8 *)(&rpc_params->ctrlParams), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02(pParams, (NvU8 *)(&rpc_params->ctrlParams), 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpuPromoteCtx_v1A_20(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *pParams = (NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *)pParamStructPtr; + NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 *rpc_ctrl_params = &rpc_message->ctrl_gpu_promote_ctx_v1A_20.promoteCtx; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPU_PROMOTE_CTX, + sizeof(rpc_ctrl_gpu_promote_ctx_v1A_20)); + if (status != NV_OK) + return status; + + rpc_message->ctrl_gpu_promote_ctx_v1A_20.hClient = hClient; + rpc_message->ctrl_gpu_promote_ctx_v1A_20.hObject = hObject; + + status = serialize_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20(pParams, + (NvU8 *) rpc_ctrl_params, + 0, NULL); + return status; +} + +NV_STATUS rpcCtrlReservePmAreaSmpc_v1A_0F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *pParams = (NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS *)pParamStructPtr; + rpc_ctrl_reserve_pm_area_smpc_v1A_0F *rpc_buffer_params = &rpc_message->ctrl_reserve_pm_area_smpc_v1A_0F; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_PM_AREA_SMPC, + sizeof(rpc_ctrl_reserve_pm_area_smpc_v1A_0F)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to acquire SMPC reservation failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlReserveHwpmLegacy_v1A_0F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *pParams = (NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS *)pParamStructPtr; + rpc_ctrl_reserve_hwpm_legacy_v1A_0F *rpc_buffer_params = &rpc_message->ctrl_reserve_hwpm_legacy_v1A_0F; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_RESERVE_HWPM_LEGACY, + sizeof(rpc_ctrl_reserve_hwpm_legacy_v1A_0F)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to acquire HWPM reservation failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlB0ccExecRegOps_v1A_0F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *pParams = (NVB0CC_CTRL_EXEC_REG_OPS_PARAMS *)pParamStructPtr; + rpc_ctrl_b0cc_exec_reg_ops_v1A_0F *rpc_buffer_params = &rpc_message->ctrl_b0cc_exec_reg_ops_v1A_0F; + + ct_assert(NVB0CC_REGOPS_MAX_COUNT == 124); + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_B0CC_EXEC_REG_OPS, + sizeof(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Profiler RegOps RPC failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlBindPmResources_v1A_0F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject) +{ + NV_STATUS status = NV_OK; + rpc_ctrl_bind_pm_resources_v1A_0F *rpc_buffer_params = &rpc_message->ctrl_bind_pm_resources_v1A_0F; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_BIND_PM_RESOURCES, + sizeof(rpc_ctrl_bind_pm_resources_v1A_0F)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to bind PM resources failed with error 0x%x\n", status); + return status; + } + + return status; +} + +NV_STATUS rpcCtrlAllocPmaStream_v1A_14(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *pParams = (NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS *)pParamStructPtr; + rpc_ctrl_alloc_pma_stream_v1A_14 *rpc_buffer_params = &rpc_message->ctrl_alloc_pma_stream_v1A_14; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_ALLOC_PMA_STREAM, + sizeof(rpc_ctrl_alloc_pma_stream_v1A_14)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "PMA Stream allocation RPC failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlPmaStreamUpdateGetPut_v1A_14(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams = (NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *)pParamStructPtr; + rpc_ctrl_pma_stream_update_get_put_v1A_14 *rpc_buffer_params = &rpc_message->ctrl_pma_stream_update_get_put_v1A_14; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_PMA_STREAM_UPDATE_GET_PUT, + sizeof(rpc_ctrl_pma_stream_update_get_put_v1A_14)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "PMA Stream update get/put RPC failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + + +NV_STATUS rpcCtrlGrPcSamplingMode_v1A_1F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *pParams = (NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS *)pParamStructPtr; + rpc_ctrl_gr_pc_sampling_mode_v1A_1F *rpc_buffer_params = &rpc_message->ctrl_gr_pc_sampling_mode_v1A_1F; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_GR_PC_SAMPLING_MODE, + sizeof(rpc_ctrl_gr_pc_sampling_mode_v1A_1F)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Set PC sampling mode RPC failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlPerfRatedTdpGetStatus_v1A_1F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *pParams = (NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS *)pParamStructPtr; + rpc_ctrl_perf_rated_tdp_get_status_v1A_1F *rpc_buffer_params = &rpc_message->ctrl_perf_rated_tdp_get_status_v1A_1F; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_GET_STATUS, + sizeof(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F)); + if (status != NV_OK) + return status; + + ct_assert(NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS_v1A_1F == NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS); + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to fetch RATED_TDP status failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlPerfRatedTdpSetControl_v1A_1F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *pParams = (NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS *)pParamStructPtr; + rpc_ctrl_perf_rated_tdp_set_control_v1A_1F *rpc_buffer_params = &rpc_message->ctrl_perf_rated_tdp_set_control_v1A_1F; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_PERF_RATED_TDP_SET_CONTROL, + sizeof(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to set RATED_TDP control action failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlFreePmaStream_v1A_1F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *pParams = (NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *)pParamStructPtr; + rpc_ctrl_free_pma_stream_v1A_1F *rpc_buffer_params = &rpc_message->ctrl_free_pma_stream_v1A_1F; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_FREE_PMA_STREAM, + sizeof(rpc_ctrl_free_pma_stream_v1A_1F)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "PMA Stream free RPC failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlTimerSetGrTickFreq_v1A_1F(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *pParams = (NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS *)pParamStructPtr; + rpc_ctrl_timer_set_gr_tick_freq_v1A_1F *rpc_buffer_params = &rpc_message->ctrl_timer_set_gr_tick_freq_v1A_1F; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_TIMER_SET_GR_TICK_FREQ, + sizeof(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to set GR update/tick frequency failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlFifoSetupVfZombieSubctxPdb_v1A_23( + OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *pParams = + (NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS *)pParamStructPtr; + + rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 *rpc_params = &rpc_message->ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB, + sizeof(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgSetSingleSmSingleStep_v1C_02(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *pParams = (NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 *rpc_buffer_params = &rpc_message->ctrl_dbg_set_single_sm_single_step_v1C_02; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_SINGLE_SM_SINGLE_STEP, + sizeof(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to set single SM single step failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlGrGetTpcPartitionMode_v1C_04(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *pParams = (NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *)pParamStructPtr; + rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 *rpc_buffer_params = &rpc_message->ctrl_gr_get_tpc_partition_mode_v1C_04; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_GR_GET_TPC_PARTITION_MODE, + sizeof(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to get gr tpc partition mode failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlGrSetTpcPartitionMode_v1C_04(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *pParams = (NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *)pParamStructPtr; + rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 *rpc_buffer_params = &rpc_message->ctrl_gr_set_tpc_partition_mode_v1C_04; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_GR_SET_TPC_PARTITION_MODE, + sizeof(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to set gr tpc partition mode failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlInternalMemsysSetZbcReferenced_v1F_05 +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr +) +{ + NV_STATUS status; + NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *pParams = + (NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS *)pParamStructPtr; + + rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 *rpc_params = &rpc_message->ctrl_internal_memsys_set_zbc_referenced_v1F_05; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED, + sizeof(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_v1F_05(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to internal memsys set zbc referenced failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_v1F_05(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlFabricMemoryDescribe_v1E_0C +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr +) +{ + NV_STATUS status; + NV00F8_CTRL_DESCRIBE_PARAMS *pParams = + (NV00F8_CTRL_DESCRIBE_PARAMS *)pParamStructPtr; + + rpc_ctrl_fabric_memory_describe_v1E_0C *rpc_params = &rpc_message->ctrl_fabric_memory_describe_v1E_0C; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEMORY_DESCRIBE, + sizeof(rpc_ctrl_fabric_memory_describe_v1E_0C)); + if (status != NV_OK) + { + return status; + } + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + { + return status; + } + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to 00f8 describe failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlFabricMemStats_v1E_0C +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr +) +{ + NV_STATUS status; + NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *pParams = + (NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS *)pParamStructPtr; + + rpc_ctrl_fabric_mem_stats_v1E_0C *rpc_params = &rpc_message->ctrl_fabric_mem_stats_v1E_0C; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_FABRIC_MEM_STATS, + sizeof(rpc_ctrl_fabric_mem_stats_v1E_0C)); + if (status != NV_OK) + { + return status; + } + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + { + return status; + } + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to fabric memory stats failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + + return status; +} + +NV_STATUS +rpcCtrlInternalPromoteFaultMethodBuffers_v1E_07 +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *pParams = + (NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS *)pParamStructPtr; + rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 *rpc_buffer_params = + &rpc_message->ctrl_internal_promote_fault_method_buffers_v1E_07; + + status = rpcWriteCommonHeader( pGpu, pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS, + sizeof(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07)); + + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07( + pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to promote fault method buffers failed with error 0x%x\n", + status); + return status; + } + + status = deserialize_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07( + pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + + +NV_STATUS rpcCtrlInternalQuiescePmaChannel_v1C_08(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *pParams = (NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS *)pParamStructPtr; + rpc_ctrl_internal_quiesce_pma_channel_v1C_08 *rpc_buffer_params = &rpc_message->ctrl_internal_quiesce_pma_channel_v1C_08; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL, + sizeof(rpc_ctrl_internal_quiesce_pma_channel_v1C_08)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Quiesce PMA channel RPC failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlInternalSriovPromotePmaStream_v1C_0C(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams = (NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *)pParamStructPtr; + rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C *rpc_buffer_params = &rpc_message->ctrl_internal_sriov_promote_pma_stream_v1C_0C; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM, + sizeof(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to promote PMA stream for full SRIOV failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlDbgClearAllSmErrorStates_v1A_0C(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *pParams = (NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C *rpc_params = &rpc_message->ctrl_dbg_clear_all_sm_error_states_v1A_0C; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_ALL_SM_ERROR_STATES, + sizeof(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgSetExceptionMask_v1A_0C(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *pParams = (NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_set_exception_mask_v1A_0C *rpc_params = &rpc_message->ctrl_dbg_set_exception_mask_v1A_0C; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_EXCEPTION_MASK, + sizeof(rpc_ctrl_dbg_set_exception_mask_v1A_0C)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgReadAllSmErrorStates_v21_06(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status, numSMsRead = 0; + NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *pParams = (NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_read_all_sm_error_states_v21_06 *rpc_params = &rpc_message->ctrl_dbg_read_all_sm_error_states_v21_06; + + if (pRpc->maxRpcSize < + (sizeof(rpc_message_header_v) + + sizeof(rpc_ctrl_dbg_read_all_sm_error_states_v21_06))) + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: Insufficient space in message buffer to copy all SMs error states\n"); + return NV_ERR_BUFFER_TOO_SMALL; + + } + + if (pParams->numSMsToRead > NV83DE_CTRL_DEBUG_MAX_SMS_PER_CALL_v16_03) + return NV_ERR_INVALID_ARGUMENT; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_ALL_SM_ERROR_STATES, + sizeof(rpc_ctrl_dbg_read_all_sm_error_states_v21_06)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + while (numSMsRead < pParams->numSMsToRead) { + rpc_params->ctrlParams.startingSM = pParams->startingSM + numSMsRead; + rpc_params->ctrlParams.numSMsToRead = NV_MIN(pParams->numSMsToRead - numSMsRead, VGPU_RPC_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PER_RPC_v21_06); + status = serialize_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL, numSMsRead); + if (status != NV_OK) + return status; + numSMsRead += rpc_params->ctrlParams.numSMsToRead; + } + return status; +} + +NV_STATUS rpcCtrlExecPartitionsCreate_v24_05(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *pParams = + (NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS *)pParamStructPtr; + + rpc_ctrl_exec_partitions_create_v24_05 *rpc_params = &rpc_message->ctrl_exec_partitions_create_v24_05; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_CREATE, + sizeof(rpc_ctrl_exec_partitions_create_v24_05)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE_v24_05(pParams, (NvU8 *) &rpc_params->execPartitionsCreate, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status == NV_OK) + { + status = rpc_params->status; + + if (rpc_params->status == NV_OK) + { + status = deserialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_CREATE_v24_05(pParams, (NvU8 *) &rpc_params->execPartitionsCreate, 0, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM_RPC: deserialize exec partition creation params : failed.\n"); + goto exit; + } + + NV_RM_RPC_GET_CONSOLIDATED_GR_STATIC_INFO(pGpu, status); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM_RPC: GET_CONSOLIDATED_GR_STATIC_INFO : failed.\n"); + } + } + } + else + { + NV_PRINTF(LEVEL_ERROR, "RPC to create exec partitions failed with error 0x%x\n", status); + } + +exit: + return status; +} + +NV_STATUS rpcCtrlExecPartitionsDelete_v1F_0A +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr +) +{ + NV_STATUS status; + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *pParams = + (NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS *)pParamStructPtr; + + rpc_ctrl_exec_partitions_delete_v1F_0A *rpc_params = &rpc_message->ctrl_exec_partitions_delete_v1F_0A; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_EXEC_PARTITIONS_DELETE, + sizeof(rpc_ctrl_exec_partitions_delete_v1F_0A)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE_v1F_0A(pParams, (NvU8 *) &rpc_params->execPartitionsDelete, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to delete exec partitions failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE_v1F_0A(pParams, (NvU8 *) &rpc_params->execPartitionsDelete, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpfifoGetWorkSubmitToken_v1F_0A +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr +) +{ + NV_STATUS status; + NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *pParams = + (NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS *)pParamStructPtr; + + rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A *rpc_params = &rpc_message->ctrl_gpfifo_get_work_submit_token_v1F_0A; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_GET_WORK_SUBMIT_TOKEN, + sizeof(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_v1F_0A(pParams, (NvU8 *) &rpc_params->workSubmitToken, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to get work submit token failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_v1F_0A(pParams, (NvU8 *) &rpc_params->workSubmitToken, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_v1F_0A +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr +) +{ + NV_STATUS status; + NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *pParams = + (NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS *)pParamStructPtr; + + rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A *rpc_params = &rpc_message->ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX, + sizeof(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_v1F_0A(pParams, (NvU8 *) &rpc_params->setWorkSubmitTokenIndex, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to set work submit token notify index failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_v1F_0A(pParams, (NvU8 *) &rpc_params->setWorkSubmitTokenIndex, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_v1F_0D +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + void *pParamStructPtr +) +{ + NV_STATUS status; + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams = + (NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *)pParamStructPtr; + + rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D *rpc_params = &rpc_message->ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D; + + if ((IS_VIRTUAL_WITH_SRIOV(pGpu)) && (!IS_MIG_IN_USE(pGpu))) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + pParams->eccMask = pVSI->masterGetVfErrCntIntMsk.eccMask; + pParams->nvlinkMask = pVSI->masterGetVfErrCntIntMsk.nvlinkMask; + status = NV_OK; + return status; + } + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK, + sizeof(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_v1F_0D(pParams, (NvU8 *) &rpc_params->vfErrContIntrMask, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "RPC to get vf error cont intr mask failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_v1F_0D(pParams, (NvU8 *) &rpc_params->vfErrContIntrMask, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgSuspendContext_v1A_10(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *pParams = (NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_suspend_context_v1A_10 *rpc_params = &rpc_message->ctrl_dbg_suspend_context_v1A_10; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_SUSPEND_CONTEXT, + sizeof(rpc_ctrl_dbg_suspend_context_v1A_10)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgResumeContext_v1A_10(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject) +{ + NV_STATUS status; + rpc_ctrl_dbg_resume_context_v1A_10 *rpc_params = &rpc_message->ctrl_dbg_resume_context_v1A_10; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_RESUME_CONTEXT, + sizeof(rpc_ctrl_dbg_resume_context_v1A_10)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = _issueRpcAndWait(pGpu, pRpc); + + return status; +} + +NV_STATUS rpcCtrlDbgExecRegOps_v1A_10(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *pParams = (NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_exec_reg_ops_v1A_10 *rpc_params = &rpc_message->ctrl_dbg_exec_reg_ops_v1A_10; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_EXEC_REG_OPS, + sizeof(rpc_ctrl_dbg_exec_reg_ops_v1A_10)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgSetModeMmuDebug_v1A_10(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *pParams = (NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 *rpc_params = &rpc_message->ctrl_dbg_set_mode_mmu_debug_v1A_10; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_MMU_DEBUG, + sizeof(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgClearSingleSmErrorState_v1A_10(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *pParams = (NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 *rpc_params = &rpc_message->ctrl_dbg_clear_single_sm_error_state_v1A_10; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE, + sizeof(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgReadSingleSmErrorState_v21_06(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *pParams = (NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_read_single_sm_error_state_v21_06 *rpc_params = &rpc_message->ctrl_dbg_read_single_sm_error_state_v21_06; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_READ_SINGLE_SM_ERROR_STATE, + sizeof(rpc_ctrl_dbg_read_single_sm_error_state_v21_06)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgSetModeErrbarDebug_v1A_10(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *pParams = (NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 *rpc_params = &rpc_message->ctrl_dbg_set_mode_errbar_debug_v1A_10; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_MODE_ERRBAR_DEBUG, + sizeof(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDbgSetNextStopTriggerType_v1A_10(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *pParams = (NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 *rpc_params = &rpc_message->ctrl_dbg_set_next_stop_trigger_type_v1A_10; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_SET_NEXT_STOP_TRIGGER_TYPE, + sizeof(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlDmaSetDefaultVaspace_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *pParams = (NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS *)pParamStructPtr; + rpc_ctrl_dma_set_default_vaspace_v1A_0E *rpc_params = &rpc_message->ctrl_dma_set_default_vaspace_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DMA_SET_DEFAULT_VASPACE, + sizeof(rpc_ctrl_dma_set_default_vaspace_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetCePceMask_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pParams = (NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *)pParamStructPtr; + rpc_ctrl_get_ce_pce_mask_v1A_0E *rpc_params = &rpc_message->ctrl_get_ce_pce_mask_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GET_CE_PCE_MASK, + sizeof(rpc_ctrl_get_ce_pce_mask_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetZbcClearTableEntry_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *pParams = (NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS *)pParamStructPtr; + rpc_ctrl_get_zbc_clear_table_entry_v1A_0E *rpc_params = &rpc_message->ctrl_get_zbc_clear_table_entry_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY, + sizeof(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetNvlinkPeerIdMask_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *pParams = (NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS *)pParamStructPtr; + rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E *rpc_params = &rpc_message->ctrl_get_nvlink_peer_id_mask_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_PEER_ID_MASK, + sizeof(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetNvlinkStatus_v23_04(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *pParams = (NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS *)pParamStructPtr; + rpc_ctrl_get_nvlink_status_v23_04 *rpc_params = &rpc_message->ctrl_get_nvlink_status_v23_04; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GET_NVLINK_STATUS, + sizeof(rpc_ctrl_get_nvlink_status_v23_04)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetP2pCaps_v1F_0D(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *pParams = (NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS *)pParamStructPtr; + rpc_ctrl_get_p2p_caps_v1F_0D *rpc_params = &rpc_message->ctrl_get_p2p_caps_v1F_0D; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS, + sizeof(rpc_ctrl_get_p2p_caps_v1F_0D)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetP2pCapsMatrix_v1A_0E(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *pParams = (NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *)pParamStructPtr; + rpc_ctrl_get_p2p_caps_matrix_v1A_0E *rpc_params = &rpc_message->ctrl_get_p2p_caps_matrix_v1A_0E; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GET_P2P_CAPS_MATRIX, + sizeof(rpc_ctrl_get_p2p_caps_matrix_v1A_0E)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlFbGetInfoV2_v25_0A(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams = (NV2080_CTRL_FB_GET_INFO_V2_PARAMS *)pParamStructPtr; + rpc_ctrl_fb_get_info_v2_v25_0A *rpc_params = &rpc_message->ctrl_fb_get_info_v2_v25_0A; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_FB_GET_INFO_V2, + sizeof(rpc_ctrl_fb_get_info_v2_v25_0A)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGetMmuDebugMode_v1E_06(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status = NV_OK; + NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *pParams = (NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS *)pParamStructPtr; + rpc_ctrl_get_mmu_debug_mode_v1E_06 *rpc_buffer_params = &rpc_message->ctrl_get_mmu_debug_mode_v1E_06; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_GET_MMU_DEBUG_MODE, + sizeof(rpc_ctrl_get_mmu_debug_mode_v1E_06)); + if (status != NV_OK) + return status; + + rpc_buffer_params->hClient = hClient; + rpc_buffer_params->hObject = hObject; + + status = serialize_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to get MMU debug mode failed with error 0x%x\n", status); + return status; + } + + status = deserialize_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06(pParams, (NvU8 *)&(rpc_buffer_params->params), 0, NULL); + + return status; +} + +NV_STATUS rpcCtrlFifoSetChannelProperties_v1A_16(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *pParams = (NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS *)pParamStructPtr; + rpc_ctrl_fifo_set_channel_properties_v1A_16 *rpc_params = &rpc_message->ctrl_fifo_set_channel_properties_v1A_16; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_FIFO_SET_CHANNEL_PROPERTIES, + sizeof(rpc_ctrl_fifo_set_channel_properties_v1A_16)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlBusSetP2pMapping_v21_03(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams = (NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *)pParamStructPtr; + rpc_ctrl_bus_set_p2p_mapping_v21_03 *rpc_params = &rpc_message->ctrl_bus_set_p2p_mapping_v21_03; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_BUS_SET_P2P_MAPPING, + sizeof(rpc_ctrl_bus_set_p2p_mapping_v21_03)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlBusUnsetP2pMapping_v21_03(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams = (NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *)pParamStructPtr; + rpc_ctrl_bus_unset_p2p_mapping_v21_03 *rpc_params = &rpc_message->ctrl_bus_unset_p2p_mapping_v21_03; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_BUS_UNSET_P2P_MAPPING, + sizeof(rpc_ctrl_bus_unset_p2p_mapping_v21_03)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpuGetInfoV2_v25_11(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams = (NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *)pParamStructPtr; + rpc_ctrl_gpu_get_info_v2_v25_11 *rpc_params = &rpc_message->ctrl_gpu_get_info_v2_v25_11; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPU_GET_INFO_V2, + sizeof(rpc_ctrl_gpu_get_info_v2_v25_11)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11(pParams, (NvU8 *) &rpc_params->params, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpuMigratableOps_v21_07(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *pParams = (NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS *)pParamStructPtr; + rpc_ctrl_gpu_migratable_ops_v21_07 *rpc_params = &rpc_message->ctrl_gpu_migratable_ops_v21_07; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_GPU_MIGRATABLE_OPS, + sizeof(rpc_ctrl_gpu_migratable_ops_v21_07)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS rpcCtrlGpuQueryEccStatus_v24_06(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS rpcCtrlDbgGetModeMmuDebug_v25_04(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, void *pParamStructPtr) +{ + NV_STATUS status; + NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *pParams = (NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS *)pParamStructPtr; + rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 *rpc_params = &rpc_message->ctrl_dbg_get_mode_mmu_debug_v25_04; + + status = rpcWriteCommonHeader(pGpu, + pRpc, + NV_VGPU_MSG_FUNCTION_CTRL_DBG_GET_MODE_MMU_DEBUG, + sizeof(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04)); + if (status != NV_OK) + return status; + + rpc_params->hClient = hClient; + rpc_params->hObject = hObject; + + status = serialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + if (status != NV_OK) + return status; + + status = deserialize_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04(pParams, (NvU8 *) &rpc_params->ctrlParams, 0, NULL); + return status; +} + +NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NV_STATUS status = NV_OK; + NvS32 message_buffer_remaining; + NvU32 data_len; + + if (pGpuMgr->numGpuHandles == 0) + { + rpcVgxVersion.majorNum = 0; + rpcVgxVersion.minorNum = 0; + } + + // + // Skip RPC version handshake if we've already done it on one GPU. + // + // For GSP: Multi GPU setup can have pre-Turing GPUs + // and GSP offload is disabled for all pre-Turing GPUs. + // Don't skip RPC version handshake for GSP_CLIENT or if VGPU-GSP plugin offload is enabled. + // There are different GSPs/plugins for different GPUs and we need to have a handshake with all of them. + // + + if (pGpuMgr->numGpuHandles > 1 && !IS_GSP_CLIENT(pGpu) && !(IS_VIRTUAL(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu))) + { + if (rpcVgxVersion.majorNum != 0) { - NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll timedout for fn %d!\n", - vgpu_rpc_message_header_v->function); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && !bSkipRpcVersionHandshake) + { + bSkipRpcVersionHandshake = NV_TRUE; + } + else + { + NV_PRINTF(LEVEL_INFO, + "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", + gpuGetInstance(pGpu)); + goto skip_ver_handshake; + } } else { - NV_PRINTF(LEVEL_ERROR, "rpcRecvPoll failed with status 0x%08x for fn %d!\n", - nvStatus, vgpu_rpc_message_header_v->function); + status = NV_ERR_GENERIC; + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: RPC version handshake already failed. Bailing out for device" + " instance 0x%x\n", gpuGetInstance(pGpu)); + goto skip_ver_handshake; } - NV_ASSERT(0); - return nvStatus; } - pBuf8 = (NvU8 *)pBuffer; - remainingSize = bufSize; - entryLength = NV_MIN(bufSize, vgpu_rpc_message_header_v->length); - NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE); + message_buffer_remaining = pRpc->maxRpcSize - (sizeof(rpc_message_header_v) + + sizeof(rpc_set_guest_system_info_v)); - if (((NvU8 *)vgpu_rpc_message_header_v != pBuf8) && bBidirectional) - portMemCopy(pBuf8, entryLength, vgpu_rpc_message_header_v, entryLength); + if (message_buffer_remaining < 0) + { + // unable to fit the data in the message buffer + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: SetGuestSystemInfo: Insufficient space on message buffer\n"); - remainingSize -= entryLength; - pBuf8 += entryLength; + return NV_ERR_BUFFER_TOO_SMALL; + } - // For bidirectional transfer messages, need to receive all other frames as well - if (bBidirectional && (recordCount > 0)) + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO, + sizeof(rpc_set_guest_system_info_v)); + if (status != NV_OK) + return status; + + if(sizeof(NV_VERSION_STRING) < NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE) { - while (remainingSize > 0) + data_len = NV_ROUNDUP((NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE), sizeof(NvU32)); + rpc_message->set_guest_system_info_v.guestDriverVersionBufferLength = data_len; + portStringCopy(rpc_message->set_guest_system_info_v.guestDriverVersion, + sizeof(rpc_message->set_guest_system_info_v.guestDriverVersion), + (const char*)NV_VERSION_STRING, data_len); + } + else + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + if(sizeof(NV_BUILD_BRANCH_VERSION) < NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE) + { + data_len = NV_ROUNDUP((NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE), sizeof(NvU32)); + rpc_message->set_guest_system_info_v.guestVersionBufferLength = data_len; + portStringCopy(rpc_message->set_guest_system_info_v.guestVersion, + sizeof(rpc_message->set_guest_system_info_v.guestVersion), + (const char*)NV_BUILD_BRANCH_VERSION, data_len); + } + else + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + if (sizeof(NV_DISPLAY_DRIVER_TITLE) < NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE) + { + data_len = NV_ROUNDUP((NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE), sizeof(NvU32)); + rpc_message->set_guest_system_info_v.guestTitleBufferLength = data_len; + portStringCopy(rpc_message->set_guest_system_info_v.guestTitle, + sizeof(rpc_message->set_guest_system_info_v.guestTitle), + (const char*)NV_DISPLAY_DRIVER_TITLE, data_len); + } + else + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + rpc_message->set_guest_system_info_v.guestClNum = NV_BUILD_CHANGELIST_NUM; + rpc_message->set_guest_system_info_v.vgxVersionMajorNum = VGX_MAJOR_VERSION_NUMBER; + rpc_message->set_guest_system_info_v.vgxVersionMinorNum = VGX_MINOR_VERSION_NUMBER; + + status = _issueRpcAndWait(pGpu, pRpc); + + if ((status == NV_OK) && (vgpu_rpc_message_header_v->rpc_result_private != NV_OK)) + { + status = vgpu_rpc_message_header_v->rpc_result_private; + if ((rpc_message->set_guest_system_info_v.vgxVersionMajorNum != VGX_MAJOR_VERSION_NUMBER) || + (rpc_message->set_guest_system_info_v.vgxVersionMinorNum != VGX_MINOR_VERSION_NUMBER)) { - nvStatus = rpcRecvPoll(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CONTINUATION_RECORD); - if (nvStatus != NV_OK) + if (RPC_VERSION_FROM_VGX_VERSION(rpc_message->set_guest_system_info_v.vgxVersionMajorNum, + rpc_message->set_guest_system_info_v.vgxVersionMinorNum) >= + RPC_VERSION_FROM_VGX_VERSION(NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR, + NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR)) { - if (nvStatus == NV_ERR_TIMEOUT) - { - NV_PRINTF(LEVEL_ERROR, - "rpcRecvPoll timedout for fn %d continuation record (remainingSize=0x%x)!\n", - vgpu_rpc_message_header_v->function, remainingSize); - } - else - { - NV_PRINTF(LEVEL_ERROR, - "rpcRecvPoll failed with status 0x%08x for fn %d continuation record! (remainingSize=0x%x)\n", - nvStatus, vgpu_rpc_message_header_v->function, remainingSize); - } - NV_ASSERT(0); - return nvStatus; + NV_PRINTF(LEVEL_WARNING, + "NVRM_RPC: SetGuestSystemInfo: Guest VGX version (%d.%d) is newer than " + "the host VGX version (%d.%d)\n" + "NVRM_RPC: SetGuestSystemInfo: Retrying with the VGX version requested " + "by the host.\n", VGX_MAJOR_VERSION_NUMBER, + VGX_MINOR_VERSION_NUMBER, + rpc_message->set_guest_system_info_v.vgxVersionMajorNum, + rpc_message->set_guest_system_info_v.vgxVersionMinorNum); + status = _issueRpcAndWait(pGpu, pRpc); + } + else + { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: SetGuestSystemInfo: The host version (%d.%d) is too old.\n" + "NVRM_RPC: SetGuestSystemInfo: Minimum required host version is %d.%d.\n", + rpc_message->set_guest_system_info_v.vgxVersionMajorNum, + rpc_message->set_guest_system_info_v.vgxVersionMinorNum, + NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR, + NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR); + + NV_RM_RPC_LOG(pGpu, "######## Guest NVIDIA Driver Information: ########", NV_VGPU_LOG_LEVEL_NOTICE); + NV_RM_RPC_LOG(pGpu, "Driver Version: "NV_VERSION_STRING, NV_VGPU_LOG_LEVEL_NOTICE); + NV_RM_RPC_LOG(pGpu, "Incompatible Guest/Host drivers: Host VGX version is older than the minimum version " + "supported by the Guest. Disabling vGPU.", NV_VGPU_LOG_LEVEL_ERROR); + } + } + } + + if (status == NV_OK) + { + if (rpcVgxVersion.majorNum != 0) + { + if (rpcVgxVersion.majorNum != rpc_message->set_guest_system_info_v.vgxVersionMajorNum || + rpcVgxVersion.minorNum != rpc_message->set_guest_system_info_v.vgxVersionMinorNum) + { + return NV_ERR_INVALID_STATE; } + } + + rpcVgxVersion.majorNum = rpc_message->set_guest_system_info_v.vgxVersionMajorNum; + rpcVgxVersion.minorNum = rpc_message->set_guest_system_info_v.vgxVersionMinorNum; + } + +skip_ver_handshake: + if (status == NV_OK) + { + rpcSetIpVersion(pGpu, pRpc, + RPC_VERSION_FROM_VGX_VERSION(rpcVgxVersion.majorNum, + rpcVgxVersion.minorNum)); + + NV_RM_RPC_SET_GUEST_SYSTEM_INFO_EXT(pGpu, status); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SET_GUEST_SYSTEM_INFO_EXT : failed.\n"); + } + } + + return status; +} + +NV_STATUS rpcSetGuestSystemInfoExt_v15_02(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_STATUS status = NV_OK; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO_EXT, + sizeof(rpc_set_guest_system_info_ext_v15_02)); + if (status != NV_OK) + return status; + + if (sizeof(STRINGIZE(NV_BUILD_BRANCH)) < NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE) + { + portStringCopy(rpc_message->set_guest_system_info_ext_v15_02.guestDriverBranch, + sizeof(rpc_message->set_guest_system_info_ext_v15_02.guestDriverBranch), + (const char*)STRINGIZE(NV_BUILD_BRANCH), sizeof(STRINGIZE(NV_BUILD_BRANCH))); + } + else + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + rpc_message->set_guest_system_info_ext_v15_02.domain = gpuGetDomain(pGpu); + rpc_message->set_guest_system_info_ext_v15_02.bus = gpuGetBus(pGpu); + rpc_message->set_guest_system_info_ext_v15_02.device = gpuGetDevice(pGpu); + + status = _issueRpcAndWait(pGpu, pRpc); + + return status; +} + +NV_STATUS RmRpcPerfGetCurrentPstate(OBJGPU *pGpu, + NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS *pParamStructPtr) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + pParamStructPtr->currPstate = *(pVGpu->shared_memory + + (NV_VGPU_SHARED_MEMORY_POINTER_CURRENT_PSTATE / sizeof(NvU32))); + + return NV_OK; +} + +NV_STATUS rpcPerfGetLevelInfo_v03_00(OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS *pParams, + NV2080_CTRL_PERF_GET_CLK_INFO *pPerfClkInfos) +{ + NV_STATUS status = NV_OK; + NvU32 i, message_buffer_remaining, paramSize; + NvU32 *mbuf_ptr, *param_ptr; + + // calculate variable param size + paramSize = pParams->perfGetClkInfoListSize * sizeof(NV2080_CTRL_PERF_GET_CLK_INFO); + + message_buffer_remaining = pRpc->maxRpcSize - (sizeof(rpc_message_header_v) + + sizeof(rpc_perf_get_level_info_v03_00)); + if (message_buffer_remaining < paramSize) + { + // unable to fit all the entries in the message buffer + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: PerfGetLevelInfo : requested %u bytes (but only room for %u)\n", + paramSize, message_buffer_remaining); + return NV_ERR_GENERIC; + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_PERF_GET_LEVEL_INFO, sizeof(rpc_perf_get_level_info_v03_00)); + if (status != NV_OK) + return status; - entryLength = vgpu_rpc_message_header_v->length; - NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE); - NV_CHECK_OR_RETURN(LEVEL_ERROR, entryLength >= sizeof(rpc_message_header_v), NV_ERR_INVALID_STATE); - entryLength -= sizeof(rpc_message_header_v); + rpc_message->perf_get_level_info_v03_00.hClient = hClient; + rpc_message->perf_get_level_info_v03_00.hObject = hObject; + rpc_message->perf_get_level_info_v03_00.level = pParams->level; + rpc_message->perf_get_level_info_v03_00.flags = pParams->flags; + rpc_message->perf_get_level_info_v03_00.perfGetClkInfoListSize = pParams->perfGetClkInfoListSize; + rpc_message->perf_get_level_info_v03_00.param_size = paramSize; - if (entryLength > remainingSize) - entryLength = remainingSize; + mbuf_ptr = &rpc_message->perf_get_level_info_v03_00.params[0]; - portMemCopy(pBuf8, entryLength, rpc_message, entryLength); - remainingSize -= entryLength; - pBuf8 += entryLength; - recordCount--; + // copy params into the message buffer + if (pPerfClkInfos) + { + param_ptr = (NvU32 *)pPerfClkInfos; + for (i = 0; i < (pParams->perfGetClkInfoListSize * sizeof(NV2080_CTRL_PERF_GET_CLK_INFO)); i = i + sizeof(NvU32)) + { + *mbuf_ptr++ = *param_ptr++; } - vgpu_rpc_message_header_v->function = expectedFunc; - NV_ASSERT(recordCount == 0); } - // Now check if RPC really succeeded - if (vgpu_rpc_message_header_v->rpc_result != NV_VGPU_MSG_RESULT_SUCCESS) - { - NV_PRINTF(LEVEL_WARNING, "RPC failed with status 0x%08x for fn %d!\n", - vgpu_rpc_message_header_v->rpc_result, - vgpu_rpc_message_header_v->function); + status = _issueRpcAndWait(pGpu, pRpc); - if (vgpu_rpc_message_header_v->rpc_result < DRF_BASE(NV_VGPU_MSG_RESULT__VMIOP)) - return vgpu_rpc_message_header_v->rpc_result; + if (status == NV_OK) + { + pParams->flags = rpc_message->perf_get_level_info_v03_00.flags; + mbuf_ptr = &rpc_message->perf_get_level_info_v03_00.params[0]; - return NV_ERR_GENERIC; + // copy message buffer back to params + if (pPerfClkInfos) + { + param_ptr = (NvU32 *)pPerfClkInfos; + for (i = 0; i < (pParams->perfGetClkInfoListSize * sizeof(NV2080_CTRL_PERF_GET_CLK_INFO)); i = i + sizeof(NvU32)) + { + *param_ptr++ = *mbuf_ptr++; + } + } } + return status; +} - return NV_OK; +NV_STATUS rpcSetSurfaceProperties_v07_07(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, + NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES *pParams, NvBool bSkipCompare) +{ + NV_STATUS status = NV_OK; + status = NV_ERR_NOT_SUPPORTED; + + return status; } -static NV_STATUS _issueRpcAndWaitLarge -( - OBJGPU *pGpu, - OBJRPC *pRpc, - NvU32 bufSize, - const void *pBuffer, - NvBool bBidirectional -) +NV_STATUS rpcCleanupSurface_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams) { - return _issueRpcLarge(pGpu, pRpc, bufSize, pBuffer, - bBidirectional, - NV_TRUE); //bWait + NV_STATUS status = NV_OK; + status = NV_ERR_NOT_SUPPORTED; + + return status; } -static NV_STATUS _issueRpcAsyncLarge -( - OBJGPU *pGpu, - OBJRPC *pRpc, - NvU32 bufSize, - const void *pBuffer -) +NV_STATUS rpcUnloadingGuestDriver_v1F_07(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bInPMTransition, NvBool bGc6Entering, NvU32 newPMLevel) { - return _issueRpcLarge(pGpu, pRpc, bufSize, pBuffer, - NV_FALSE, //bBidirectional - NV_FALSE); //bWait + NV_STATUS status = NV_OK; + NvU32 headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_unloading_guest_driver_v1F_07); + if (headerLength > pRpc->maxRpcSize) + { + NV_PRINTF(LEVEL_ERROR, + "Unloading guest driver parameters size (0x%x) exceed message_buffer " + "size (0x%x)\n", headerLength, pRpc->maxRpcSize); + + NV_ASSERT(0); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER, sizeof(rpc_unloading_guest_driver_v1F_07)); + if (status != NV_OK) + return status; + rpc_message->unloading_guest_driver_v1F_07.bInPMTransition = bInPMTransition; + rpc_message->unloading_guest_driver_v1F_07.bGc6Entering = bGc6Entering; + rpc_message->unloading_guest_driver_v1F_07.newLevel = newPMLevel; + + status = _issueRpcAndWait(pGpu, pRpc); + + return status; } -static NV_STATUS _issuePteDescRpc +NV_STATUS +cliresCtrlCmdDiagDumpRpc_IMPL ( - OBJGPU *pGpu, - OBJRPC *pRpc, - NvU32 offsetToPTE, - NvU32 pageCount, - RmPhysAddr *guestPages, - NvBool physicallyContiguous + RmClientResource *pRmCliRes, + NV0000_CTRL_DIAG_DUMP_RPC_PARAMS *pRpcDumpParams ) { - rpc_message_header_v *pHdr = vgpu_rpc_message_header_v; - void *pAllocatedRecord = NULL; - struct pte_desc *pPteDesc; - NvU64 contigBase; - NV_STATUS nvStatus = NV_OK; - NvU32 recordSize; - NvU32 i; - DMA_PAGE_ARRAY pageArray; + NvU32 i = 0; - NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pRpc != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(guestPages != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pHdr != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(!bProfileRPC, NV_ERR_INVALID_STATE); - recordSize = offsetToPTE + NV_OFFSETOF(struct pte_desc, pte_pde[0].pte) + - (pageCount * NV_VGPU_PTE_64_SIZE); + if (rpcDumpRec.entryOffset == 0) + rpcDumpRec.pHead = rpcMeterHead.pHead; - if (recordSize > pRpc->maxRpcSize) + if (pRpcDumpParams->firstEntryOffset != rpcDumpRec.entryOffset) { - // Multiple queue entries. Create a temporary buffer for the PTEs. - pAllocatedRecord = portMemAllocNonPaged(recordSize); - if (pAllocatedRecord == NULL) + rpcDumpRec.pHead = rpcMeterHead.pHead; + + while (i < pRpcDumpParams->firstEntryOffset) { - NV_PRINTF(LEVEL_ERROR, "no memory for allocated record\n"); - return NV_ERR_INSUFFICIENT_RESOURCES; + NV_ASSERT_OR_RETURN(rpcDumpRec.pHead, NV_ERR_INVALID_ARGUMENT); + rpcDumpRec.pHead = rpcDumpRec.pHead->pNext; + i++; } + } - // Copy in the record so far. - portMemCopy(pAllocatedRecord, pHdr->length, pHdr, pHdr->length); + i = 0; + while (rpcDumpRec.pHead && + (i < NV0000_CTRL_DIAG_RPC_MAX_ENTRIES)) + { + pRpcDumpParams->rpcProfilerBuffer[i++] = + rpcDumpRec.pHead->rpcData; + rpcDumpRec.pHead = rpcDumpRec.pHead->pNext; + } - // Point to the allocated record. - pHdr = (rpc_message_header_v *)pAllocatedRecord; + // Still have content left inside + if (rpcDumpRec.pHead) + { + pRpcDumpParams->remainingEntryCount = + rpcProfilerEntryCount - i - pRpcDumpParams->firstEntryOffset; } + else + pRpcDumpParams->remainingEntryCount = 0; - dmaPageArrayInit(&pageArray, guestPages, pageCount); + pRpcDumpParams->outputEntryCount = i; + pRpcDumpParams->elapsedTimeInNs = elapsedTimeInNs; + rpcDumpRec.entryOffset = i; - pPteDesc = (struct pte_desc *)NvP64_PLUS_OFFSET(pHdr, offsetToPTE); - pPteDesc->idr = NV_VGPU_PTEDESC_IDR_NONE; - pPteDesc->length = pageCount; - contigBase = (dmaPageArrayGetPhysAddr(&pageArray, 0) >> RM_PAGE_SHIFT); + return NV_OK; +} - for (i = 0; i < pageCount; i++) +NV_STATUS +cliresCtrlCmdDiagProfileRpc_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_DIAG_PROFILE_RPC_PARAMS *pRpcProfileParams +) +{ + switch (pRpcProfileParams->rpcProfileCmd) { - if (physicallyContiguous) - pPteDesc->pte_pde[i].pte = contigBase + i; - else - pPteDesc->pte_pde[i].pte = - (dmaPageArrayGetPhysAddr(&pageArray, i) >> RM_PAGE_SHIFT); - } - - nvStatus = _issueRpcAndWaitLarge(pGpu, pRpc, recordSize, pHdr, NV_FALSE); + case NV0000_CTRL_PROFILE_RPC_CMD_DISABLE: + bProfileRPC = NV_FALSE; + osGetPerformanceCounter(&endTimeInNs); + elapsedTimeInNs += endTimeInNs - startTimeInNs; + break; + case NV0000_CTRL_PROFILE_RPC_CMD_ENABLE: + bProfileRPC = NV_TRUE; + osGetPerformanceCounter(&startTimeInNs); + break; + case NV0000_CTRL_PROFILE_RPC_CMD_RESET: + { + RPC_METER_LIST * pHead = rpcMeterHead.pHead; + RPC_METER_LIST * pTmp = NULL; - portMemFree(pAllocatedRecord); + while (pHead) + { + pTmp = pHead->pNext; + portMemFree(pHead); + pHead = NULL; + pHead = pTmp; + } + rpcMeterHead.pHead = NULL; + rpcMeterHead.pTail = NULL; + rpcProfilerEntryCount = 0; + elapsedTimeInNs = 0; + break; + } + default: + return NV_ERR_INVALID_ARGUMENT; + } - return nvStatus; + return NV_OK; } -NV_STATUS rpcAllocMemory_v13_01(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hMemory, NvU32 hClass, - NvU32 flags, MEMORY_DESCRIPTOR *pMemDesc) +NV_STATUS rpcSwitchToVga_v03_00(OBJGPU *pGpu, OBJRPC *pRpc) { + OBJVGPU *pVgpu = GPU_GET_VGPU(pGpu); NV_STATUS status = NV_OK; - if (pMemDesc == NULL) + /* return if vnc support is disabled */ + if(pVgpu && !pVgpu->bVncSupported) { - NV_PRINTF(LEVEL_ERROR, - "NVRM_RPC: AllocMemory: pMemDesc arg was NULL\n"); - return NV_ERR_GENERIC; + return status; } - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_ALLOC_MEMORY, sizeof(rpc_alloc_memory_v13_01)); + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SWITCH_TO_VGA, 0); if (status != NV_OK) return status; - rpc_message->alloc_memory_v13_01.hClient = hClient; - rpc_message->alloc_memory_v13_01.hDevice = hDevice; - rpc_message->alloc_memory_v13_01.hMemory = hMemory; - rpc_message->alloc_memory_v13_01.hClass = hClass; - rpc_message->alloc_memory_v13_01.flags = flags; - rpc_message->alloc_memory_v13_01.pteAdjust = pMemDesc->PteAdjust; - rpc_message->alloc_memory_v13_01.format = memdescGetPteKind(pMemDesc); - rpc_message->alloc_memory_v13_01.length = pMemDesc->Size; - rpc_message->alloc_memory_v13_01.pageCount = (NvU32)pMemDesc->PageCount; + return _issueRpcAndWait(pGpu, pRpc); +} - if (IS_GSP_CLIENT(pGpu)) +NV_STATUS rpcGpuExecRegOps_v12_01(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, + NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS *pParams, + NV2080_CTRL_GPU_REG_OP *pRegOps) +{ + NV_STATUS status; + NvU32 i, j, regOpsExecuted = 0; + + if (pParams == NULL) { - status = _issuePteDescRpc(pGpu, pRpc, - NV_OFFSETOF(rpc_message_header_v, rpc_message_data[0].alloc_memory_v13_01.pteDesc), - pMemDesc->PageCount, - memdescGetPteArray(pMemDesc, AT_GPU), - memdescGetContiguity(pMemDesc, AT_GPU)); + return NV_ERR_INVALID_ARGUMENT; } - return status; -} + if (pParams->regOpCount == 0) + { + NV_PRINTF(LEVEL_ERROR,"RegOps RPC failed: Invalid regOp count - requested 0x%x regOps\n", pParams->regOpCount); + return NV_ERR_INVALID_ARGUMENT; + } -NV_STATUS rpcMapMemoryDma_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hDma, NvHandle hMemory, - NvU64 offset, NvU64 length, NvU32 flags, NvU64 *pDmaOffset) -{ - NV_STATUS status; - NVOS46_PARAMETERS_v03_00 *rpc_params = &rpc_message->map_memory_dma_v03_00.params; + /* RPC message buffer can accomodate a maximum of VGPU_MAX_REGOPS_PER_RPC regops only. + * This value must be adjusted(if required) in case of any change to the internal + * RegOps RPC structures. + */ + if (pRpc->maxRpcSize < + (sizeof(rpc_message_header_v) + + sizeof(rpc_gpu_exec_reg_ops_v12_01) + + VGPU_MAX_REGOPS_PER_RPC * sizeof(NV2080_CTRL_GPU_REG_OP_v03_00))) { + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: rpcGpuExecRegOps_v12_01: Insufficient space on message buffer\n"); + return NV_ERR_BUFFER_TOO_SMALL; + } - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_MAP_MEMORY_DMA, sizeof(rpc_map_memory_dma_v03_00)); + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS, + sizeof(rpc_gpu_exec_reg_ops_v12_01)); if (status != NV_OK) return status; - rpc_params->hClient = hClient; - rpc_params->hDevice = hDevice; - rpc_params->hDma = hDma; - rpc_params->hMemory = hMemory; - rpc_params->flags = flags; + rpc_message->gpu_exec_reg_ops_v12_01.hClient = hClient; + rpc_message->gpu_exec_reg_ops_v12_01.hObject = hObject; - rpc_params->offset = offset; - rpc_params->length = length; - rpc_params->dmaOffset = *pDmaOffset; + // copy params into the message buffer + rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.hClientTarget = pParams->hClientTarget; + rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.hChannelTarget = pParams->hChannelTarget; + rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.regOpCount = pParams->regOpCount; + rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.grRouteInfo.flags = pParams->grRouteInfo.flags; + rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.grRouteInfo.route = pParams->grRouteInfo.route; - status = _issueRpcAndWait(pGpu, pRpc); + while (regOpsExecuted < pParams->regOpCount){ + for (i = 0, j = regOpsExecuted; i < VGPU_MAX_REGOPS_PER_RPC && j < pParams->regOpCount; i++, j++) + { + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regOp = pRegOps[j].regOp; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regType = pRegOps[j].regType; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regStatus = pRegOps[j].regStatus; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regQuad = pRegOps[j].regQuad; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regGroupMask = pRegOps[j].regGroupMask; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regSubGroupMask = pRegOps[j].regSubGroupMask; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regOffset = pRegOps[j].regOffset; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regValueHi = pRegOps[j].regValueHi; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regValueLo = pRegOps[j].regValueLo; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regAndNMaskHi = pRegOps[j].regAndNMaskHi; + rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regAndNMaskLo = pRegOps[j].regAndNMaskLo; + } + rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.regOpCount = i; - if (status == NV_OK) - { - *pDmaOffset = rpc_params->dmaOffset; + status = _issueRpcAndWait(pGpu, pRpc); + + if (status == NV_OK) + { + status = vgpu_rpc_message_header_v->rpc_result_private; + if (status == NV_OK) + { + for (i = 0, j = regOpsExecuted; i < VGPU_MAX_REGOPS_PER_RPC && j < pParams->regOpCount; i++, j++) + { + pRegOps[j].regStatus = rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regStatus; + pRegOps[j].regValueHi = rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regValueHi; + pRegOps[j].regValueLo = rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regValueLo; + } + } + else + { + NV_PRINTF(LEVEL_ERROR,"RegOps RPC failed: skipping 0x%x regOps\n", pParams->regOpCount - regOpsExecuted); + } + } + regOpsExecuted = j; } + return status; } -NV_STATUS rpcUnmapMemoryDma_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, NvHandle hDma, - NvHandle hMemory, NvU32 flags, NvU64 pDmaOffset) +NV_STATUS rpcGetConsolidatedStaticInfo_v1A_05(OBJGPU *pGpu, OBJRPC *pRpc) { - NV_STATUS status; - NVOS47_PARAMETERS_v03_00 *rpc_params = &rpc_message->unmap_memory_dma_v03_00.params; - - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNMAP_MEMORY_DMA, sizeof(rpc_unmap_memory_dma_v03_00)); - if (status != NV_OK) - return status; - - rpc_params->hClient = hClient; - rpc_params->hDevice = hDevice; - rpc_params->hDma = hDma; - rpc_params->hMemory = hMemory; - rpc_params->flags = flags; - rpc_params->dmaOffset = pDmaOffset; - - status = _issueRpcAndWait(pGpu, pRpc); - return status; + return NV_ERR_NOT_SUPPORTED; } -/* max entries is how many 3 DWORD entries fit in what remains of the message_buffer */ -#define IDLE_CHANNELS_MAX_ENTRIES_v03_00 \ - ((pRpc->maxRpcSize - (sizeof(rpc_message_header_v) + sizeof(rpc_idle_channels_v03_00))) / sizeof(idle_channel_list_v03_00)) - -NV_STATUS rpcIdleChannels_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle *phClients, NvHandle *phDevices, NvHandle *phChannels, - NvU32 numEntries, NvU32 flags, NvU32 timeout) +NV_STATUS rpcGetStaticData_v25_0E(OBJGPU *pGpu, OBJRPC *pRpc) { NV_STATUS status; - NvU32 i; + NvU32 headerLength; + NvU32 offset = 0, remainedBytes = 0; + NvU32 size = 0, maxPayloadSize = 0, totalRpcSize = 0; + NvU8 *pRpcPayload = NULL; - if (numEntries > IDLE_CHANNELS_MAX_ENTRIES_v03_00) + headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_get_static_data_v25_0E); + if (headerLength > pRpc->maxRpcSize) { - // unable to fit all the entries in the message buffer NV_PRINTF(LEVEL_ERROR, - "NVRM_RPC: IdleChannels: requested %u entries (but only room for %u)\n", - numEntries, (NvU32)IDLE_CHANNELS_MAX_ENTRIES_v03_00); - return NV_ERR_GENERIC; + "vGPU static data parameters size (0x%x) exceed message_buffer " + "size (0x%x)\n", headerLength, pRpc->maxRpcSize); + return NV_ERR_INSUFFICIENT_RESOURCES; } - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_IDLE_CHANNELS, - sizeof(rpc_idle_channels_v03_00) + numEntries * sizeof(idle_channel_list_v03_00)); - if (status != NV_OK) - return status; + status = getStaticDataRpcBufferSize(pGpu, &pRpc->rpcStructureCopy, &totalRpcSize); + maxPayloadSize = pRpc->maxRpcSize - headerLength; - rpc_message->idle_channels_v03_00.flags = flags; - rpc_message->idle_channels_v03_00.timeout = timeout; - rpc_message->idle_channels_v03_00.nchannels = numEntries; + remainedBytes = totalRpcSize; - for (i = 0; i < numEntries; i++) + // Create a temporary buffer + pRpcPayload = portMemAllocNonPaged(totalRpcSize); + if (pRpcPayload == NULL) { - rpc_message->idle_channels_v03_00.channel_list[i].phClient = ((NvU32) phClients[i]); - rpc_message->idle_channels_v03_00.channel_list[i].phDevice = ((NvU32) phDevices[i]); - rpc_message->idle_channels_v03_00.channel_list[i].phChannel = ((NvU32) phChannels[i]); + NV_PRINTF(LEVEL_ERROR, "no memory for temporary buffer\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; } - status = _issueRpcAndWait(pGpu, pRpc); - return status; -} + offset = 0; + while (remainedBytes) + { + if (remainedBytes > maxPayloadSize) + { + size = maxPayloadSize; + } + else + { + size = remainedBytes; + } -NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) -{ - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); - NV_STATUS status = NV_OK; - NvS32 message_buffer_remaining; - NvU32 data_len; + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GET_STATIC_DATA, + sizeof(rpc_get_static_data_v25_0E) + size); + if (status != NV_OK) + goto exit; - if (pGpuMgr->numGpuHandles == 0) - { - rpcVgxVersion.majorNum = 0; - rpcVgxVersion.minorNum = 0; - } + rpc_message->get_static_data_v25_0E.offset = offset; + rpc_message->get_static_data_v25_0E.size = size; - // - // Skip RPC version handshake if we've already done it on one GPU. - // - // For GSP: Multi GPU setup can have pre-Turing GPUs - // and GSP offload is disabled for all pre-Turing GPUs. - // Don't skip RPC version handshake for GSP_CLIENT or if VGPU-GSP plugin offload is enabled. - // There are different GSPs/plugins for different GPUs and we need to have a handshake with all of them. - // + status = _issueRpcAndWait(pGpu, pRpc); - if (pGpuMgr->numGpuHandles > 1 && !IS_GSP_CLIENT(pGpu) && !(IS_VIRTUAL(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu))) - { - if (rpcVgxVersion.majorNum != 0) + if (status == NV_OK) { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && !bSkipRpcVersionHandshake) - { - bSkipRpcVersionHandshake = NV_TRUE; - } - else - { - NV_PRINTF(LEVEL_INFO, - "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", - gpuGetInstance(pGpu)); - goto skip_ver_handshake; - } + portMemCopy(pRpcPayload + offset, size, rpc_message->get_static_data_v25_0E.payload, size); + offset += size; + remainedBytes -= size; } else { - status = NV_ERR_GENERIC; + goto exit; + } + } + + if (status == NV_OK) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + status = copyPayloadToStaticData(pGpu, &pRpc->rpcStructureCopy, pRpcPayload, totalRpcSize, pVSI); + if (status != NV_OK) + { NV_PRINTF(LEVEL_ERROR, - "NVRM_RPC: RPC version handshake already failed. Bailing out for device" - " instance 0x%x\n", gpuGetInstance(pGpu)); - goto skip_ver_handshake; + "Failed to copy the data from RPC to Static Info buffer. Status :%x\n", status); + goto exit; + } + + NV_RM_RPC_GET_CONSOLIDATED_GR_STATIC_INFO(pGpu, status); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NVRM_RPC: GET_CONSOLIDATED_GR_STATIC_INFO failed.\n"); + goto exit; } } - message_buffer_remaining = pRpc->maxRpcSize - (sizeof(rpc_message_header_v) + - sizeof(rpc_set_guest_system_info_v)); +exit : + portMemFree(pRpcPayload); - if (message_buffer_remaining < 0) + return status; +} + +NV_STATUS rpcGetConsolidatedGrStaticInfo_v1B_04(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_STATUS status; + NvU32 headerLength; + NvU32 offset = 0, remainedBytes = 0; + NvU32 size = 0, maxPayloadSize = 0, totalConsolidatedRpcSize = 0; + NvU8 *pConsolidatedRpcPayload = NULL; + + + headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_get_consolidated_gr_static_info_v1B_04); + if (headerLength > pRpc->maxRpcSize) { - // unable to fit the data in the message buffer NV_PRINTF(LEVEL_ERROR, - "NVRM_RPC: SetGuestSystemInfo: Insufficient space on message buffer\n"); + "vGPU consolidated static information parameters size (0x%x) exceed message_buffer " + "size (0x%x)\n", headerLength, pRpc->maxRpcSize); - return NV_ERR_BUFFER_TOO_SMALL; + NV_ASSERT(0); + return NV_ERR_INSUFFICIENT_RESOURCES; } - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SET_GUEST_SYSTEM_INFO, - sizeof(rpc_set_guest_system_info_v)); - if (status != NV_OK) - return status; + status = getConsolidatedGrRpcBufferSize(pGpu, &pRpc->rpcStructureCopy, &totalConsolidatedRpcSize); + maxPayloadSize = pRpc->maxRpcSize - headerLength; - if(sizeof(NV_VERSION_STRING) < NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE) - { - data_len = NV_ROUNDUP((NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE), sizeof(NvU32)); - rpc_message->set_guest_system_info_v.guestDriverVersionBufferLength = data_len; - portStringCopy(rpc_message->set_guest_system_info_v.guestDriverVersion, - sizeof(rpc_message->set_guest_system_info_v.guestDriverVersion), - (const char*)NV_VERSION_STRING, data_len); - } - else - { - return NV_ERR_BUFFER_TOO_SMALL; - } + remainedBytes = totalConsolidatedRpcSize; - if(sizeof(NV_BUILD_BRANCH_VERSION) < NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE) - { - data_len = NV_ROUNDUP((NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE), sizeof(NvU32)); - rpc_message->set_guest_system_info_v.guestVersionBufferLength = data_len; - portStringCopy(rpc_message->set_guest_system_info_v.guestVersion, - sizeof(rpc_message->set_guest_system_info_v.guestVersion), - (const char*)NV_BUILD_BRANCH_VERSION, data_len); - } - else + // Create a temporary buffer + pConsolidatedRpcPayload = portMemAllocNonPaged(totalConsolidatedRpcSize); + if (pConsolidatedRpcPayload == NULL) { - return NV_ERR_BUFFER_TOO_SMALL; + NV_PRINTF(LEVEL_ERROR, "no memory for temporary buffer\n"); + return NV_ERR_INSUFFICIENT_RESOURCES; } - if (sizeof(NV_DISPLAY_DRIVER_TITLE) < NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE) + offset = 0; + while (remainedBytes) { - data_len = NV_ROUNDUP((NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE), sizeof(NvU32)); - rpc_message->set_guest_system_info_v.guestTitleBufferLength = data_len; - portStringCopy(rpc_message->set_guest_system_info_v.guestTitle, - sizeof(rpc_message->set_guest_system_info_v.guestTitle), - (const char*)NV_DISPLAY_DRIVER_TITLE, data_len); + if (remainedBytes > maxPayloadSize) + { + size = maxPayloadSize; + } + else + { + size = remainedBytes; + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GET_CONSOLIDATED_GR_STATIC_INFO, + sizeof(rpc_get_consolidated_gr_static_info_v1B_04) + size); + if (status != NV_OK) + goto exit; + + rpc_message->get_consolidated_gr_static_info_v1B_04.offset = offset; + rpc_message->get_consolidated_gr_static_info_v1B_04.size = size; + + + status = _issueRpcAndWait(pGpu, pRpc); + if (status == NV_OK) + { + portMemCopy(pConsolidatedRpcPayload + offset, size, rpc_message->get_consolidated_gr_static_info_v1B_04.payload, size); + offset += size; + remainedBytes -= size; + } + else + { + goto exit; + } } - else + + if (status == NV_OK) { - return NV_ERR_BUFFER_TOO_SMALL; + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + status = copyPayloadToGrStaticInfo(pGpu, &pRpc->rpcStructureCopy, pConsolidatedRpcPayload, totalConsolidatedRpcSize, pVSI); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to copy the data from RPC to GR Static Info buffer. Status :%x\n", status); + goto exit; + } } - rpc_message->set_guest_system_info_v.guestClNum = NV_BUILD_CHANGELIST_NUM; - rpc_message->set_guest_system_info_v.vgxVersionMajorNum = VGX_MAJOR_VERSION_NUMBER; - rpc_message->set_guest_system_info_v.vgxVersionMinorNum = VGX_MINOR_VERSION_NUMBER; +exit : + portMemFree(pConsolidatedRpcPayload); - status = _issueRpcAndWait(pGpu, pRpc); + return status; +} - if ((status == NV_OK) && (vgpu_rpc_message_header_v->rpc_result_private != NV_OK)) +NV_STATUS rpcGetGspStaticInfo_v14_00(OBJGPU *pGpu, OBJRPC *pRpc) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + if (IS_GSP_CLIENT(pGpu)) { - status = vgpu_rpc_message_header_v->rpc_result_private; - if ((rpc_message->set_guest_system_info_v.vgxVersionMajorNum != VGX_MAJOR_VERSION_NUMBER) || - (rpc_message->set_guest_system_info_v.vgxVersionMinorNum != VGX_MINOR_VERSION_NUMBER)) + NvU32 headerLength; + GspStaticConfigInfo *pSCI = GPU_GET_GSP_STATIC_INFO(pGpu); + GspStaticConfigInfo *rpcInfo = (GspStaticConfigInfo *)&rpc_message->get_gsp_static_info_v14_00.data; + + NV_ASSERT_OR_RETURN(pSCI, NV_ERR_INVALID_POINTER); + + headerLength = sizeof(rpc_message_header_v) + + sizeof(GspStaticConfigInfo); + if (headerLength > pRpc->maxRpcSize) { - if (RPC_VERSION_FROM_VGX_VERSION(rpc_message->set_guest_system_info_v.vgxVersionMajorNum, - rpc_message->set_guest_system_info_v.vgxVersionMinorNum) >= - RPC_VERSION_FROM_VGX_VERSION(NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR, - NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR)) - { - NV_PRINTF(LEVEL_WARNING, - "NVRM_RPC: SetGuestSystemInfo: Guest VGX version (%d.%d) is newer than " - "the host VGX version (%d.%d)\n" - "NVRM_RPC: SetGuestSystemInfo: Retrying with the VGX version requested " - "by the host.\n", VGX_MAJOR_VERSION_NUMBER, - VGX_MINOR_VERSION_NUMBER, - rpc_message->set_guest_system_info_v.vgxVersionMajorNum, - rpc_message->set_guest_system_info_v.vgxVersionMinorNum); - status = _issueRpcAndWait(pGpu, pRpc); - } - else - { - NV_PRINTF(LEVEL_ERROR, - "NVRM_RPC: SetGuestSystemInfo: The host version (%d.%d) is too old.\n" - "NVRM_RPC: SetGuestSystemInfo: Minimum required host version is %d.%d.\n", - rpc_message->set_guest_system_info_v.vgxVersionMajorNum, - rpc_message->set_guest_system_info_v.vgxVersionMinorNum, - NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR, - NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR); + NV_PRINTF(LEVEL_ERROR, + "Gsp static info parameters size (0x%x) exceed message_buffer size (0x%x)\n", + headerLength, pRpc->maxRpcSize); + + NV_ASSERT(0); + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + status = rpcWriteCommonHeader(pGpu, pRpc, + NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO, + sizeof(GspStaticConfigInfo)); + if (status != NV_OK) + return status; + + status = _issueRpcAndWait(pGpu, pRpc); + NV_CHECK_OR_RETURN(LEVEL_INFO, status == NV_OK, status); - NV_RM_RPC_LOG(pGpu, "######## Guest NVIDIA Driver Information: ########", NV_VGPU_LOG_LEVEL_NOTICE); - NV_RM_RPC_LOG(pGpu, "Driver Version: "NV_VERSION_STRING, NV_VGPU_LOG_LEVEL_NOTICE); - NV_RM_RPC_LOG(pGpu, "Incompatible Guest/Host drivers: Host VGX version is older than the minimum version " - "supported by the Guest. Disabling vGPU.", NV_VGPU_LOG_LEVEL_ERROR); - } - } + // Copy info + portMemCopy(pSCI, sizeof(*pSCI), rpcInfo, sizeof(*rpcInfo)); } - if (status == NV_OK) - { - if (rpcVgxVersion.majorNum != 0) - { - if (rpcVgxVersion.majorNum != rpc_message->set_guest_system_info_v.vgxVersionMajorNum || - rpcVgxVersion.minorNum != rpc_message->set_guest_system_info_v.vgxVersionMinorNum) - { - return NV_ERR_INVALID_STATE; - } - } + return status; +} - rpcVgxVersion.majorNum = rpc_message->set_guest_system_info_v.vgxVersionMajorNum; - rpcVgxVersion.minorNum = rpc_message->set_guest_system_info_v.vgxVersionMinorNum; - } +NV_STATUS rpcUpdateBarPde_v15_00(OBJGPU *pGpu, OBJRPC *pRpc, NV_RPC_UPDATE_PDE_BAR_TYPE barType, NvU64 entryValue, NvU64 entryLevelShift) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; -skip_ver_handshake: - if (status == NV_OK) + if (IS_GSP_CLIENT(pGpu)) { - rpcSetIpVersion(pGpu, pRpc, - RPC_VERSION_FROM_VGX_VERSION(rpcVgxVersion.majorNum, - rpcVgxVersion.minorNum)); - - NV_RM_RPC_SET_GUEST_SYSTEM_INFO_EXT(pGpu, status); + UpdateBarPde_v15_00 *rpc_params = &rpc_message->update_bar_pde_v15_00.info; + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE, + sizeof(rpc_update_bar_pde_v15_00)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "SET_GUEST_SYSTEM_INFO_EXT : failed.\n"); + return status; } + + rpc_params->barType = barType; + rpc_params->entryValue = entryValue; + rpc_params->entryLevelShift = entryLevelShift; + + status = _issueRpcAndWait(pGpu, pRpc); } return status; } -NV_STATUS rpcUnloadingGuestDriver_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bInPMTransition, NvBool bGc6Entering, NvU32 newPMLevel) +NV_STATUS rpcSetPageDirectory_v1E_05(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, + NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pParams) { NV_STATUS status = NV_OK; + NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 *rpc_params = &rpc_message->set_page_directory_v1E_05.params; + + if (hypervisorIsType(OS_HYPERVISOR_HYPERV)) + { + if (!FLD_TEST_DRF(0080, _CTRL_DMA_SET_PAGE_DIRECTORY, _FLAGS_APERTURE, _VIDMEM, pParams->flags)) + { + NV_ASSERT(0); + return NV_ERR_NOT_SUPPORTED; + } + } - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER, 0); + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY, sizeof(rpc_set_page_directory_v1E_05)); if (status != NV_OK) return status; + rpc_message->set_page_directory_v1E_05.hClient = hClient; + rpc_message->set_page_directory_v1E_05.hDevice = hDevice; + + rpc_params->physAddress = pParams->physAddress; + rpc_params->numEntries = pParams->numEntries; + rpc_params->flags = pParams->flags; + rpc_params->hVASpace = pParams->hVASpace; + rpc_params->chId = pParams->chId; + rpc_params->subDeviceId = pParams->subDeviceId; + rpc_params->pasid = pParams->pasid; + status = _issueRpcAndWait(pGpu, pRpc); return status; -} +} -NV_STATUS rpcUnloadingGuestDriver_v1F_07(OBJGPU *pGpu, OBJRPC *pRpc, NvBool bInPMTransition, NvBool bGc6Entering, NvU32 newPMLevel) +NV_STATUS rpcUnsetPageDirectory_v1E_05(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, + NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pParams) { NV_STATUS status = NV_OK; - NvU32 headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_unloading_guest_driver_v1F_07); - if (headerLength > pRpc->maxRpcSize) - { - NV_PRINTF(LEVEL_ERROR, - "Unloading guest driver parameters size (0x%x) exceed message_buffer " - "size (0x%x)\n", headerLength, pRpc->maxRpcSize); - - NV_ASSERT(0); - return NV_ERR_INSUFFICIENT_RESOURCES; - } + NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 *rpc_params = &rpc_message->unset_page_directory_v1E_05.params; - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNLOADING_GUEST_DRIVER, sizeof(rpc_unloading_guest_driver_v1F_07)); + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY, sizeof(rpc_unset_page_directory_v1E_05)); if (status != NV_OK) return status; - rpc_message->unloading_guest_driver_v1F_07.bInPMTransition = bInPMTransition; - rpc_message->unloading_guest_driver_v1F_07.bGc6Entering = bGc6Entering; - rpc_message->unloading_guest_driver_v1F_07.newLevel = newPMLevel; + + rpc_message->unset_page_directory_v1E_05.hClient = hClient; + rpc_message->unset_page_directory_v1E_05.hDevice = hDevice; + + rpc_params->hVASpace = pParams->hVASpace; + rpc_params->subDeviceId = pParams->subDeviceId; status = _issueRpcAndWait(pGpu, pRpc); return status; } -NV_STATUS rpcGpuExecRegOps_v12_01(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hObject, - NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS *pParams, - NV2080_CTRL_GPU_REG_OP *pRegOps) +NV_STATUS rpcSaveHibernationData_v1E_0E(OBJGPU *pGpu, OBJRPC *pRpc) { - NV_STATUS status; - NvU32 i, j, regOpsExecuted = 0; + NV_STATUS status = NV_OK; + NvU32 headerLength; + NvU32 offset = 0, remainedBytes = 0; + NvU32 size = 0, maxPayloadSize = 0, totalHibernationDataSize = 0; + OBJVGPU *pVgpu = GPU_GET_VGPU(pGpu); + NvU8 *pHibernationData = NULL; + rpc_save_hibernation_data_v1E_0E *shd = &rpc_message->save_hibernation_data_v1E_0E; + + headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_save_hibernation_data_v1E_0E); + maxPayloadSize = pRpc->maxRpcSize - headerLength; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA, + pRpc->maxRpcSize - sizeof(rpc_message_header_v)); + if (status != NV_OK) + goto exit; - if (pParams == NULL) - { - return NV_ERR_INVALID_ARGUMENT; - } + status = _issueRpcAndWait(pGpu, pRpc); - if (pParams->regOpCount == 0) + if (status == NV_OK) { - NV_PRINTF(LEVEL_ERROR,"RegOps RPC failed: Invalid regOp count - requested 0x%x regOps\n", pParams->regOpCount); - return NV_ERR_INVALID_ARGUMENT; - } + // + // If data size received in first RPC is zero, there is no plugin data + // to be saved, return early. + // + if (shd->remainedBytes == 0) + { + goto exit; + } - /* RPC message buffer can accomodate a maximum of VGPU_MAX_REGOPS_PER_RPC regops only. - * This value must be adjusted(if required) in case of any change to the internal - * RegOps RPC structures. - */ - if (pRpc->maxRpcSize < - (sizeof(rpc_message_header_v) + - sizeof(rpc_gpu_exec_reg_ops_v12_01) + - VGPU_MAX_REGOPS_PER_RPC * sizeof(NV2080_CTRL_GPU_REG_OP_v03_00))) { - NV_PRINTF(LEVEL_ERROR, - "NVRM_RPC: rpcGpuExecRegOps_v12_01: Insufficient space on message buffer\n"); - return NV_ERR_BUFFER_TOO_SMALL; - } + totalHibernationDataSize = shd->remainedBytes; + pVgpu->hibernationData.size = totalHibernationDataSize; - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GPU_EXEC_REG_OPS, - sizeof(rpc_gpu_exec_reg_ops_v12_01)); - if (status != NV_OK) - return status; + // Buffer to save hibernation data + pVgpu->hibernationData.buffer = portMemAllocNonPaged(totalHibernationDataSize); - rpc_message->gpu_exec_reg_ops_v12_01.hClient = hClient; - rpc_message->gpu_exec_reg_ops_v12_01.hObject = hObject; + if (pVgpu->hibernationData.buffer == NULL) + { + NV_PRINTF(LEVEL_ERROR, "No memory for hibernation buffer\n"); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto exit; + } - // copy params into the message buffer - rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.hClientTarget = pParams->hClientTarget; - rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.hChannelTarget = pParams->hChannelTarget; - rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.regOpCount = pParams->regOpCount; - rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.grRouteInfo.flags = pParams->grRouteInfo.flags; - rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.grRouteInfo.route = pParams->grRouteInfo.route; + pHibernationData = pVgpu->hibernationData.buffer; - while (regOpsExecuted < pParams->regOpCount){ - for (i = 0, j = regOpsExecuted; i < VGPU_MAX_REGOPS_PER_RPC && j < pParams->regOpCount; i++, j++) + // Copy payload chunk recieved in first RPC call + if (totalHibernationDataSize > maxPayloadSize) { - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regOp = pRegOps[j].regOp; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regType = pRegOps[j].regType; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regStatus = pRegOps[j].regStatus; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regQuad = pRegOps[j].regQuad; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regGroupMask = pRegOps[j].regGroupMask; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regSubGroupMask = pRegOps[j].regSubGroupMask; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regOffset = pRegOps[j].regOffset; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regValueHi = pRegOps[j].regValueHi; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regValueLo = pRegOps[j].regValueLo; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regAndNMaskHi = pRegOps[j].regAndNMaskHi; - rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regAndNMaskLo = pRegOps[j].regAndNMaskLo; + portMemCopy(pHibernationData, maxPayloadSize, shd->payload, maxPayloadSize); + } + else + { + portMemCopy(pHibernationData, totalHibernationDataSize, shd->payload, totalHibernationDataSize); + goto exit; } - rpc_message->gpu_exec_reg_ops_v12_01.params.reg_op_params.regOpCount = i; - status = _issueRpcAndWait(pGpu, pRpc); + remainedBytes = totalHibernationDataSize - maxPayloadSize; + offset = maxPayloadSize; - if (status == NV_OK) + // Pull remaining chunks of data + while (remainedBytes) { - status = vgpu_rpc_message_header_v->rpc_result_private; + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SAVE_HIBERNATION_DATA, + pRpc->maxRpcSize - sizeof(rpc_message_header_v)); + if (status != NV_OK) + goto exit; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (remainedBytes > maxPayloadSize) + size = maxPayloadSize; + else + size = remainedBytes; + if (status == NV_OK) { - for (i = 0, j = regOpsExecuted; i < VGPU_MAX_REGOPS_PER_RPC && j < pParams->regOpCount; i++, j++) - { - pRegOps[j].regStatus = rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regStatus; - pRegOps[j].regValueHi = rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regValueHi; - pRegOps[j].regValueLo = rpc_message->gpu_exec_reg_ops_v12_01.params.operations[i].regValueLo; - } + portMemCopy(pHibernationData + offset, size, shd->payload, size); + offset += size; + remainedBytes -= size; } else { - NV_PRINTF(LEVEL_ERROR,"RegOps RPC failed: skipping 0x%x regOps\n", pParams->regOpCount - regOpsExecuted); + goto exit; } } - regOpsExecuted = j; } - - return status; -} - -NV_STATUS rpcGetStaticInfo_v17_05(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v18_03(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v18_04(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v18_0E(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v18_10(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v18_11(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v18_13(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v18_16(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v19_00(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v1A_00(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetStaticInfo_v1A_05(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_OK; +exit: + if (status != NV_OK && pHibernationData) + { + portMemFree(pHibernationData); + } + bSkipRpcVersionHandshake = NV_FALSE; return status; } -NV_STATUS rpcGetStaticInfo_v20_01(OBJGPU *pGpu, OBJRPC *pRpc) +NV_STATUS rpcRestoreHibernationData_v1E_0E(OBJGPU *pGpu, OBJRPC *pRpc) { NV_STATUS status = NV_OK; - return status; -} - -NV_STATUS rpcGetGspStaticInfo_v14_00(OBJGPU *pGpu, OBJRPC *pRpc) -{ - NV_STATUS status = NV_ERR_NOT_SUPPORTED; - - if (IS_GSP_CLIENT(pGpu)) - { - NvU32 headerLength; - GspStaticConfigInfo *pSCI = GPU_GET_GSP_STATIC_INFO(pGpu); - GspStaticConfigInfo *rpcInfo = (GspStaticConfigInfo *)&rpc_message->get_gsp_static_info_v14_00.data; - - NV_ASSERT_OR_RETURN(pSCI, NV_ERR_INVALID_POINTER); + NvU32 headerLength; + NvU32 offset = 0, remainedBytes = 0; + NvU32 size = 0, maxPayloadSize = 0; + OBJVGPU *pVgpu = GPU_GET_VGPU(pGpu); + NvU8 *pHibernationData = pVgpu->hibernationData.buffer; + rpc_restore_hibernation_data_v1E_0E *rhd = &rpc_message->restore_hibernation_data_v1E_0E; + + headerLength = sizeof(rpc_message_header_v) + sizeof(rpc_restore_hibernation_data_v1E_0E); + maxPayloadSize = pRpc->maxRpcSize - headerLength; + remainedBytes = pVgpu->hibernationData.size; + offset = 0; - headerLength = sizeof(rpc_message_header_v) + - sizeof(GspStaticConfigInfo); - if (headerLength > pRpc->maxRpcSize) - { - NV_PRINTF(LEVEL_ERROR, - "Gsp static info parameters size (0x%x) exceed message_buffer size (0x%x)\n", - headerLength, pRpc->maxRpcSize); + // + // If hibernation data size is zero, there is no data to be restored, + // hence return early. + // + if (remainedBytes == 0) + { + goto exit; + } - NV_ASSERT(0); - return NV_ERR_INSUFFICIENT_RESOURCES; - } + while (remainedBytes) + { + if (remainedBytes > maxPayloadSize) + size = maxPayloadSize; + else + size = remainedBytes; - status = rpcWriteCommonHeader(pGpu, pRpc, - NV_VGPU_MSG_FUNCTION_GET_GSP_STATIC_INFO, - sizeof(GspStaticConfigInfo)); + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_RESTORE_HIBERNATION_DATA, + sizeof(rpc_restore_hibernation_data_v1E_0E) + size); if (status != NV_OK) - return status; + goto exit; + + rhd->remainedBytes = remainedBytes; + portMemCopy(rhd->payload, size, pHibernationData + offset, size); status = _issueRpcAndWait(pGpu, pRpc); - NV_CHECK_OR_RETURN(LEVEL_INFO, status == NV_OK, status); - // Copy info - portMemCopy(pSCI, sizeof(*pSCI), rpcInfo, sizeof(*rpcInfo)); + if (status == NV_OK) + { + offset += size; + remainedBytes -= size; + } + else + { + goto exit; + } } - +exit: + portMemFree(pHibernationData); return status; } -NV_STATUS rpcUpdateBarPde_v15_00(OBJGPU *pGpu, OBJRPC *pRpc, NV_RPC_UPDATE_PDE_BAR_TYPE barType, NvU64 entryValue, NvU64 entryLevelShift) +NV_STATUS rpcGetEngineUtilization_v09_0C_GetPidList(OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void *pInputParamStructPtr, + NvU32 inputParamSize) { - NV_STATUS status = NV_ERR_NOT_SUPPORTED; + NV_STATUS status = NV_OK; + NvU32 message_buffer_remaining; + NvU32 rpc_param_header_size; + vgpuGetEngineUtilization_data_v *pParams; + NvU32 i; - if (IS_GSP_CLIENT(pGpu)) + NvU32 paramSize = sizeof(NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_RPC_EX); + + rpc_param_header_size = sizeof(rpc_get_engine_utilization_v) - + sizeof(vgpuGetEngineUtilization_data_v); + + message_buffer_remaining = pRpc->maxRpcSize - + (sizeof(rpc_message_header_v) + + rpc_param_header_size); + if (message_buffer_remaining < paramSize) { - UpdateBarPde_v15_00 *rpc_params = &rpc_message->update_bar_pde_v15_00.info; + // unable to fit all the entries in the message buffer + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: SendDmaControl: requested %u bytes (but only room for %u)\n", + paramSize, message_buffer_remaining); + return NV_ERR_INVALID_ARGUMENT; + } - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UPDATE_BAR_PDE, - sizeof(rpc_update_bar_pde_v15_00)); - if (status != NV_OK) - { - return status; - } + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION, + rpc_param_header_size + paramSize); + if (status != NV_OK) + return status; - rpc_params->barType = barType; - rpc_params->entryValue = entryValue; - rpc_params->entryLevelShift = entryLevelShift; + rpc_message->get_engine_utilization_v.hClient = hClient; + rpc_message->get_engine_utilization_v.hObject = hObject; + rpc_message->get_engine_utilization_v.cmd = cmd; + + pParams = &rpc_message->get_engine_utilization_v.params; + + // copy params into the message buffer + NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS_v *rpcPidStruct = &pParams->getAccountingPidList; + NV0000_CTRL_GPUACCT_GET_ACCOUNTING_PIDS_PARAMS *rmPidStruct = pInputParamStructPtr; + + rpcPidStruct->gpuId = rmPidStruct->gpuId; + rpcPidStruct->passIndex = NV_RM_RPC_MORE_RPC_DATA_TO_READ; + while(rpcPidStruct->passIndex != NV_RM_RPC_NO_MORE_DATA_TO_READ) + { status = _issueRpcAndWait(pGpu, pRpc); - } + if (status != NV_OK || rpcPidStruct->pidCount == 0) + { + break; + } + for (i = 0; i < rpcPidStruct->pidCount; i++) + { + rmPidStruct->pidTbl[rmPidStruct->pidCount++] = rpcPidStruct->pidTable[i]; + } + } return status; } -NV_STATUS rpcSetPageDirectory_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, - NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pParams) +NV_STATUS rpcGetEngineUtilization_v09_0C(OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void *pParamStructPtr, + NvU32 paramSize) { - NV_STATUS status = NV_OK; - NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v03_00 *rpc_params = &rpc_message->set_page_directory_v03_00.params; + NV_STATUS status; + NvU32 message_buffer_remaining; + NvU32 rpc_param_header_size; + vgpuGetEngineUtilization_data_v *pParams; - if (hypervisorIsType(OS_HYPERVISOR_HYPERV)) + NV_ASSERT_OR_RETURN(pParamStructPtr != NULL, NV_ERR_INVALID_PARAMETER); + + if (cmd == NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS) { - if (!FLD_TEST_DRF(0080, _CTRL_DMA_SET_PAGE_DIRECTORY, _FLAGS_APERTURE, _VIDMEM, pParams->flags)) - { - NV_ASSERT(0); - return NV_ERR_NOT_SUPPORTED; - } + return rpcGetEngineUtilization_v09_0C_GetPidList(pGpu, + pRpc, + hClient, + hObject, + cmd, + pParamStructPtr, + paramSize); + } + + /* + * vgpuGetEngineUtilization_data_v07_01 gives the size of largest member of the union. + * Hence for correctly calculating size of rpc data, subtract size of rpc_get_engine_utilization + */ + rpc_param_header_size = sizeof(rpc_get_engine_utilization_v) - sizeof(vgpuGetEngineUtilization_data_v); + + message_buffer_remaining = pRpc->maxRpcSize - (sizeof(rpc_message_header_v) + + rpc_param_header_size); + if (message_buffer_remaining < paramSize) + { + // unable to fit all the entries in the message buffer + NV_PRINTF(LEVEL_ERROR, + "NVRM_RPC: SendDmaControl: requested %u bytes (but only room for %u)\n", + paramSize, message_buffer_remaining); + return NV_ERR_INVALID_ARGUMENT; } - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY, sizeof(rpc_set_page_directory_v03_00)); + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION, rpc_param_header_size + paramSize); if (status != NV_OK) return status; - rpc_message->set_page_directory_v03_00.hClient = hClient; - rpc_message->set_page_directory_v03_00.hDevice = hDevice; + rpc_message->get_engine_utilization_v.hClient = hClient; + rpc_message->get_engine_utilization_v.hObject = hObject; + rpc_message->get_engine_utilization_v.cmd = cmd; - rpc_params->physAddress = pParams->physAddress; - rpc_params->numEntries = pParams->numEntries; - rpc_params->flags = pParams->flags; - rpc_params->hVASpace = pParams->hVASpace; - rpc_params->chId = pParams->chId; - rpc_params->subDeviceId = pParams->subDeviceId; + pParams = &rpc_message->get_engine_utilization_v.params; - status = _issueRpcAndWait(pGpu, pRpc); + // copy params into the message buffer + status = engine_utilization_copy_params_to_rpc_buffer_v09_0C(cmd, pParams, pParamStructPtr); + if (status != NV_OK) + return status; + status = _issueRpcAndWait(pGpu, pRpc); + if (status == NV_OK) + { + // copy message buffer back to params + status = engine_utilization_copy_params_from_rpc_buffer_v09_0C(cmd, pParamStructPtr, pParams); + if (status != NV_OK) + return status; + } return status; - } -NV_STATUS rpcSetPageDirectory_v1E_05(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, - NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS *pParams) +NV_STATUS rpcGetEngineUtilization_v1F_0E(OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + NvU32 cmd, + void *pParamStructPtr, + NvU32 paramSize) { - NV_STATUS status = NV_OK; - NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 *rpc_params = &rpc_message->set_page_directory_v1E_05.params; + NV_STATUS status; + NvU32 message_buffer_remaining; + NvU32 rpc_param_header_size; + vgpuGetEngineUtilization_data_v1F_0E *pParams; - if (hypervisorIsType(OS_HYPERVISOR_HYPERV)) + NV_ASSERT_OR_RETURN(pParamStructPtr != NULL, NV_ERR_INVALID_PARAMETER); + + if (cmd == NV0000_CTRL_CMD_GPUACCT_GET_ACCOUNTING_PIDS) { - if (!FLD_TEST_DRF(0080, _CTRL_DMA_SET_PAGE_DIRECTORY, _FLAGS_APERTURE, _VIDMEM, pParams->flags)) - { - NV_ASSERT(0); - return NV_ERR_NOT_SUPPORTED; - } + return rpcGetEngineUtilization_v09_0C_GetPidList(pGpu, + pRpc, + hClient, + hObject, + cmd, + pParamStructPtr, + paramSize); } - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_SET_PAGE_DIRECTORY, sizeof(rpc_set_page_directory_v1E_05)); + if (cmd == NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2) + { + paramSize = ((paramSize / sizeof(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE)) * + sizeof(NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE_v1F_0E)); + } + + /* + * vGpu's getEngineUtilization_data_xxx gives the size of largest member of the union. + * Hence for correctly calculating size of rpc data, subtract size of rpc_get_engine_utilization + */ + rpc_param_header_size = sizeof(rpc_get_engine_utilization_v1F_0E) - sizeof(vgpuGetEngineUtilization_data_v1F_0E); + + message_buffer_remaining = pRpc->maxRpcSize - (sizeof(rpc_message_header_v) + + rpc_param_header_size); + if (message_buffer_remaining < paramSize) + { + // Unable to fit all the entries in the message buffer + NV_PRINTF(LEVEL_ERROR, "NVRM_RPC: SendDmaControl: requested %u bytes (but only room for %u)\n", + paramSize, message_buffer_remaining); + return NV_ERR_INVALID_ARGUMENT; + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GET_ENGINE_UTILIZATION, rpc_param_header_size + paramSize); if (status != NV_OK) return status; - rpc_message->set_page_directory_v1E_05.hClient = hClient; - rpc_message->set_page_directory_v1E_05.hDevice = hDevice; + rpc_message->get_engine_utilization_v1F_0E.hClient = hClient; + rpc_message->get_engine_utilization_v1F_0E.hObject = hObject; + rpc_message->get_engine_utilization_v1F_0E.cmd = cmd; - rpc_params->physAddress = pParams->physAddress; - rpc_params->numEntries = pParams->numEntries; - rpc_params->flags = pParams->flags; - rpc_params->hVASpace = pParams->hVASpace; - rpc_params->chId = pParams->chId; - rpc_params->subDeviceId = pParams->subDeviceId; - rpc_params->pasid = pParams->pasid; + pParams = &rpc_message->get_engine_utilization_v1F_0E.params; + + // Copy params into the message buffer + status = engine_utilization_copy_params_to_rpc_buffer_v1F_0E(cmd, pParams, pParamStructPtr); + if (status != NV_OK) + return status; status = _issueRpcAndWait(pGpu, pRpc); + if (status == NV_OK) + { + // Copy message buffer back to params + status = engine_utilization_copy_params_from_rpc_buffer_v1F_0E(cmd, pParamStructPtr, pParams); + if (status != NV_OK) + return status; + } return status; - } -NV_STATUS rpcUnsetPageDirectory_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, - NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pParams) +NV_STATUS rpcGetEncoderCapacity_v07_00(OBJGPU *pGpu, + OBJRPC *pRpc, + NvHandle hClient, + NvHandle hObject, + NvU32* encoderCapacity) { NV_STATUS status = NV_OK; - NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v03_00 *rpc_params = &rpc_message->unset_page_directory_v03_00.params; - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY, sizeof(rpc_unset_page_directory_v03_00)); + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_GET_ENCODER_CAPACITY, + sizeof(rpc_get_encoder_capacity_v07_00)); if (status != NV_OK) return status; - rpc_message->unset_page_directory_v03_00.hClient = hClient; - rpc_message->unset_page_directory_v03_00.hDevice = hDevice; - - rpc_params->hVASpace = pParams->hVASpace; - rpc_params->subDeviceId = pParams->subDeviceId; + rpc_message->get_encoder_capacity_v07_00.hClient = hClient; + rpc_message->get_encoder_capacity_v07_00.hObject = hObject; status = _issueRpcAndWait(pGpu, pRpc); + if (status == NV_OK) + { + *encoderCapacity = rpc_message->get_encoder_capacity_v07_00.encoderCapacity; + } + return status; } -NV_STATUS rpcUnsetPageDirectory_v1E_05(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient, NvHandle hDevice, - NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS *pParams) +NV_STATUS rpcVgpuPfRegRead32_v15_00(OBJGPU *pGpu, + OBJRPC *pRpc, + NvU64 address, + NvU32 *value, + NvU32 grEngId) +{ + // VGPU_PF_REG_READ32 RPC is no longer used starting with 25.0D + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS rpcDisableChannels_v1E_0B(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 bDisable) { NV_STATUS status = NV_OK; - NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 *rpc_params = &rpc_message->unset_page_directory_v1E_05.params; - status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_UNSET_PAGE_DIRECTORY, sizeof(rpc_unset_page_directory_v1E_05)); + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL_WITH_SRIOV(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + return NV_OK; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_DISABLE_CHANNELS, + sizeof(rpc_disable_channels_v1E_0B)); if (status != NV_OK) return status; - rpc_message->unset_page_directory_v1E_05.hClient = hClient; - rpc_message->unset_page_directory_v1E_05.hDevice = hDevice; - - rpc_params->hVASpace = pParams->hVASpace; - rpc_params->subDeviceId = pParams->subDeviceId; + rpc_message->disable_channels_v1E_0B.bDisable = bDisable; status = _issueRpcAndWait(pGpu, pRpc); return status; } -NV_STATUS rpcVgpuPfRegRead32_v15_00(OBJGPU *pGpu, - OBJRPC *pRpc, - NvU64 address, - NvU32 *value, - NvU32 grEngId) +NV_STATUS rpcInvalidateTlb_v23_03(POBJGPU pGpu, OBJRPC *pRpc, NvU64 pdbAddress, NvU32 regVal) { + NV_STATUS status = NV_OK; - NV_STATUS status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_VGPU_PF_REG_READ32, - sizeof(rpc_vgpu_pf_reg_read32_v15_00)); + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_INVALIDATE_TLB, + sizeof(rpc_invalidate_tlb_v23_03)); if (status != NV_OK) return status; - rpc_message->vgpu_pf_reg_read32_v15_00.address = address; - rpc_message->vgpu_pf_reg_read32_v15_00.grEngId = grEngId; + rpc_message->invalidate_tlb_v23_03.pdbAddress = pdbAddress; + rpc_message->invalidate_tlb_v23_03.regVal = regVal; status = _issueRpcAndWait(pGpu, pRpc); - if (status == NV_OK) + if (status != NV_OK) { - *value = rpc_message->vgpu_pf_reg_read32_v15_00.value; + NV_PRINTF(LEVEL_ERROR, + "Failed to invaldiate TLB rpc 0x%x\n", status); } return status; @@ -1268,6 +8596,7 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 { OBJSYS *pSys = SYS_GET_INSTANCE(); OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); GspSystemInfo *rpcInfo = (GspSystemInfo *)&rpc_message->gsp_set_system_info_v17_00.data; const NvU32 messageLength = sizeof(rpc_message_header_v) + sizeof(*rpcInfo); @@ -1310,12 +8639,20 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 if (IS_SIMULATION(pGpu)) { - KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - rpcInfo->simAccessBufPhysAddr = memdescGetPhysAddr(pKernelGsp->pMemDesc_simAccessBuf, AT_CPU, 0); + rpcInfo->simAccessBufPhysAddr = memdescGetPhysAddr(pKernelGsp->pMemDesc_simAccessBuf, AT_GPU, 0); } else { - rpcInfo->simAccessBufPhysAddr = 0; + rpcInfo->simAccessBufPhysAddr = 0ULL; + } + + if (pKernelGsp->pNotifyOpSurfMemDesc != NULL) + { + rpcInfo->notifyOpSharedSurfacePhysAddr = memdescGetPhysAddr(pKernelGsp->pNotifyOpSurfMemDesc, AT_GPU, 0); + } + else + { + rpcInfo->notifyOpSharedSurfacePhysAddr = 0ULL; } rpcInfo->pcieAtomicsOpMask = GPU_GET_KERNEL_BIF(pGpu) ? GPU_GET_KERNEL_BIF(pGpu)->osPcieAtomicsOpMask : 0U; @@ -1330,6 +8667,7 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 // Fill in the cached ACPI method data rpcInfo->acpiMethodData = pGpu->acpiMethodData; + rpcInfo->bSystemHasMux = pGpu->bSystemHasMux; // Fill in ASPM related GPU flags rpcInfo->bGpuBehindBridge = pGpu->getProperty(pGpu, PDB_PROP_GPU_BEHIND_BRIDGE); @@ -1355,6 +8693,10 @@ NV_STATUS rpcGspSetSystemInfo_v17_00 OBJTMR *pTmr = GPU_GET_TIMER(pGpu); rpcInfo->sysTimerOffsetNs = pTmr->sysTimerOffsetNs; +#if defined(NV_UNIX) && !RMCFG_FEATURE_MODS_FEATURES + rpcInfo->isGridBuild = os_is_grid_supported(); +#endif + status = _issueRpcAsync(pGpu, pRpc); } @@ -1479,53 +8821,10 @@ NV_STATUS rpcDumpProtobufComponent_v18_12 return status; } -NV_STATUS rpcRmfsInit_v15_00 -( - OBJGPU *pGpu, - OBJRPC *pRpc, - PMEMORY_DESCRIPTOR pStatusQueueMemDesc -) -{ - NV_STATUS status = NV_ERR_NOT_SUPPORTED; - - return status; -} - -NV_STATUS rpcRmfsCloseQueue_v15_00 -( - OBJGPU *pGpu, - OBJRPC *pRpc -) -{ - NV_STATUS status = NV_ERR_NOT_SUPPORTED; - - return status; -} - -NV_STATUS rpcRmfsCleanup_v15_00 -( - OBJGPU *pGpu, - OBJRPC *pRpc -) -{ - NV_STATUS status = NV_ERR_NOT_SUPPORTED; - - return status; -} - -NV_STATUS rpcRmfsTest_v15_00 -( - OBJGPU *pGpu, - OBJRPC *pRpc, - NvU32 numReps, - NvU32 flags, - NvU32 testData1, - NvU32 testData2 -) +static NV_STATUS updateHostVgpuFbUsage(OBJGPU *pGpu, NvHandle hClient, NvHandle hDevice, NvHandle hSubdevice) { - NV_STATUS status = NV_ERR_NOT_SUPPORTED; - return status; + return NV_OK; } #if NV_PRINTF_STRINGS_ALLOWED @@ -2031,3 +9330,75 @@ NV_STATUS rpcEccNotifierWriteAck_v23_05 return status; } + +NV_STATUS rpcCtrlCmdInternalGpuStartFabricProbe_v25_09 +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS *pParams +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE, + sizeof(rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09)); + + if (status != NV_OK) + return status; + + rpc_message->ctrl_cmd_internal_gpu_start_fabric_probe_v25_09.bwMode = pParams->bwMode; + + status = _issueRpcAndWait(pGpu, pRpc); + + return status; +} + +NV_STATUS rpcCtrlNvlinkGetInbandReceivedData_v25_0C +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pParams, + NvU16 message_type, + NvBool *more +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; + + rpc_ctrl_nvlink_get_inband_received_data_v25_0C* params = &rpc_message->ctrl_nvlink_get_inband_received_data_v25_0C; + + NvU32 rpc_data_size = sizeof(*params) - sizeof(params->payload.data); + + switch (message_type) + { + case NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP: + rpc_data_size += sizeof(nvlink_inband_gpu_probe_rsp_msg_t); + break; + case NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP: + // TODO: add support for this message type + return NV_ERR_NOT_SUPPORTED; + default: + return NV_ERR_NOT_SUPPORTED; + } + + status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_CTRL_NVLINK_GET_INBAND_RECEIVED_DATA, rpc_data_size); + + if (status != NV_OK) + return status; + + params->message_type = message_type; + + status = _issueRpcAndWait(pGpu, pRpc); + + if (status != NV_OK) + return status; + + if (params->payload.dataSize > sizeof(pParams->data)) + return NV_ERR_NO_MEMORY; + + *more = !! params->more; + pParams->dataSize = params->payload.dataSize; + + portMemCopy(pParams->data, pParams->dataSize, params->payload.data, pParams->dataSize); + + return status; +} diff --git a/src/nvidia/kernel/vgpu/nv/rpcstructurecopy.c b/src/nvidia/kernel/vgpu/nv/rpcstructurecopy.c new file mode 100644 index 0000000000..b7620400a9 --- /dev/null +++ b/src/nvidia/kernel/vgpu/nv/rpcstructurecopy.c @@ -0,0 +1,2045 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +//****************************************************************************** +// +// Description: +// Collection of functions to handle RPC structurecopy +// +//****************************************************************************** + +#include "vgpu/rpc.h" +#include "g_rpcstructurecopy_private.h" +#include "vgpu/sdk-structures.h" + +#define RPC_STRUCTURES +#define RPC_GENERIC_UNION +#include "g_rpc-structures.h" +#undef RPC_STRUCTURES +#undef RPC_GENERIC_UNION + +NV_STATUS deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS *fbLtcInfoForFbp, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + *offset += sizeof(NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D(VGPU_FB_GET_LTC_INFO_FOR_FBP *vgpuFbGetLtcInfoForFbp, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If vgpuFbGetLtcInfoForFbp and buffer are valid, then copy data and return the offset + if (vgpuFbGetLtcInfoForFbp && buffer) + { + VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D *vgpu_fb_get_ltc_info_for_fbp_v1A_0D = NULL; + NvU32 i; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgpu_fb_get_ltc_info_for_fbp_v1A_0D = (void*)(buffer + *offset); + + for (i = 0; i < MAX_FBPS; i++) + { + (*vgpuFbGetLtcInfoForFbp)[i].fbpIndex = vgpu_fb_get_ltc_info_for_fbp_v1A_0D->fbLtcInfoForFbp[i].fbpIndex; + (*vgpuFbGetLtcInfoForFbp)[i].ltcMask = vgpu_fb_get_ltc_info_for_fbp_v1A_0D->fbLtcInfoForFbp[i].ltcMask; + (*vgpuFbGetLtcInfoForFbp)[i].ltcCount = vgpu_fb_get_ltc_info_for_fbp_v1A_0D->fbLtcInfoForFbp[i].ltcCount; + } + } + + *offset += sizeof(VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *mcEngineNotificationIntrVectors, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If mcEngineNotificationIntrVectors and buffer are valid, then copy data and return the offset + if (mcEngineNotificationIntrVectors && buffer) + { + NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00 *mc_get_engine_notification_intr_vectors_v16_00 = NULL; + NvU32 i; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00)))) + return NV_ERR_BUFFER_TOO_SMALL; + + mc_get_engine_notification_intr_vectors_v16_00 = (void*)(buffer + *offset); + + mcEngineNotificationIntrVectors->numEntries = mc_get_engine_notification_intr_vectors_v16_00->numEntries; + + for (i = 0; i < mcEngineNotificationIntrVectors->numEntries; i++) + { + mcEngineNotificationIntrVectors->entries[i].nv2080EngineType = mc_get_engine_notification_intr_vectors_v16_00->entries[i].nv2080EngineType; + mcEngineNotificationIntrVectors->entries[i].notificationIntrVector = mc_get_engine_notification_intr_vectors_v16_00->entries[i].notificationIntrVector; + } + + } + + *offset += sizeof(NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *mcStaticIntrTable, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If mcStaticIntrs and buffer are valid, then copy data and return the offset + if (mcStaticIntrTable && buffer) + { + NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09 *mc_get_static_intr_table_v1E_09 = NULL; + NvU32 i; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09)))) + return NV_ERR_BUFFER_TOO_SMALL; + + mc_get_static_intr_table_v1E_09 = (void*)(buffer + *offset); + + mcStaticIntrTable->numEntries = mc_get_static_intr_table_v1E_09->numEntries; + + for (i = 0; i < mcStaticIntrTable->numEntries; i++) + { + mcStaticIntrTable->entries[i].nv2080IntrType = mc_get_static_intr_table_v1E_09->entries[i].nv2080IntrType; + mcStaticIntrTable->entries[i].pmcIntrMask = mc_get_static_intr_table_v1E_09->entries[i].pmcIntrMask; + mcStaticIntrTable->entries[i].intrVectorStall = mc_get_static_intr_table_v1E_09->entries[i].intrVectorStall; + mcStaticIntrTable->entries[i].intrVectorNonStall = mc_get_static_intr_table_v1E_09->entries[i].intrVectorNonStall; + } + + } + + *offset += sizeof(NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07(VGPU_FIFO_GET_DEVICE_INFO_TABLE *fifoDeviceInfoTablePtr, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If fifoDeviceInfoTablePtr and buffer are valid, then copy data and return the offset + if (fifoDeviceInfoTablePtr && buffer) + { + NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *fifoDeviceInfoTable = *fifoDeviceInfoTablePtr; + VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07 *vgpu_fifo_get_device_info_table_v1A_07 = NULL; + NvU32 i, j; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgpu_fifo_get_device_info_table_v1A_07 = (void*)(buffer + *offset); + + for (i = 0; i < MAX_ITERATIONS_DEVICE_INFO_TABLE; i++) + { + fifoDeviceInfoTable[i].baseIndex = vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].baseIndex; + fifoDeviceInfoTable[i].numEntries = vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].numEntries; + fifoDeviceInfoTable[i].bMore = vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].bMore; + + for (j = 0; j < NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES; j++) + { + portMemCopy(&fifoDeviceInfoTable[i].entries[j].engineData, + sizeof(fifoDeviceInfoTable[i].entries[j].engineData), + &vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].engineData, + sizeof(fifoDeviceInfoTable[i].entries[j].engineData)); + portMemCopy(&fifoDeviceInfoTable[i].entries[j].pbdmaIds, + sizeof(fifoDeviceInfoTable[i].entries[j].pbdmaIds), + &vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].pbdmaIds, + sizeof(fifoDeviceInfoTable[i].entries[j].pbdmaIds)); + portMemCopy(&fifoDeviceInfoTable[i].entries[j].pbdmaFaultIds, + sizeof(fifoDeviceInfoTable[i].entries[j].pbdmaFaultIds), + &vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].pbdmaFaultIds, + sizeof(fifoDeviceInfoTable[i].entries[j].pbdmaFaultIds)); + portMemCopy(&fifoDeviceInfoTable[i].entries[j].engineName, + sizeof(fifoDeviceInfoTable[i].entries[j].engineName), + &vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].engineName, + sizeof(fifoDeviceInfoTable[i].entries[j].engineName)); + fifoDeviceInfoTable[i].entries[j].numPbdmas = vgpu_fifo_get_device_info_table_v1A_07->fifoDeviceInfoTable[i].entries[j].numPbdmas; + } + } + } + + *offset += sizeof(VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES *fbDynamicBlacklistedPagesPtr, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If fbDynamicBlacklistedPagesPtr and buffer are valid, then copy data and return the offset + if (fbDynamicBlacklistedPagesPtr && buffer) + { + NV2080_CTRL_FB_GET_DYNAMIC_OFFLINED_PAGES_PARAMS *fbDynamicBlacklistedPages = *fbDynamicBlacklistedPagesPtr; + VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07 *vgpu_fb_get_dynamic_blacklisted_pages_v1A_07 = NULL; + NvU32 i, j; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgpu_fb_get_dynamic_blacklisted_pages_v1A_07 = (void*)(buffer + *offset); + + for (i = 0; i < MAX_ITERATIONS_DYNAMIC_BLACKLIST; i++) + { + fbDynamicBlacklistedPages[i].baseIndex = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].baseIndex; + fbDynamicBlacklistedPages[i].validEntries = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].validEntries; + fbDynamicBlacklistedPages[i].bMore = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].bMore; + + for (j = 0; j < NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_ENTRIES; j++) + { + fbDynamicBlacklistedPages[i].offlined[j].pageNumber = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].blackList[j].pageNumber; + fbDynamicBlacklistedPages[i].offlined[j].source = vgpu_fb_get_dynamic_blacklisted_pages_v1A_07->fbDynamicBlacklistedPages[i].blackList[j].source; + } + } + } + + *offset += sizeof(VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS *busGetInfoV2, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If busGetInfoV2 and buffer are valid, then copy data and return the offset + if (busGetInfoV2 && buffer) + { + NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09 *bus_get_info_v2_v1C_09 = NULL; + NvU32 i = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09)))) + return NV_ERR_BUFFER_TOO_SMALL; + + bus_get_info_v2_v1C_09 = (void*)(buffer + *offset); + + busGetInfoV2->busInfoListSize = bus_get_info_v2_v1C_09->busInfoListSize; + + if (bus_get_info_v2_v1C_09->busInfoListSize > NV2080_CTRL_BUS_INFO_MAX_LIST_SIZE_v1C_09) + { + return NV_ERR_OUT_OF_RANGE; + } + + for (i = 0; i < bus_get_info_v2_v1C_09->busInfoListSize; i++) + { + busGetInfoV2->busInfoList[i].index = bus_get_info_v2_v1C_09->busInfoList[i].index; + busGetInfoV2->busInfoList[i].data = bus_get_info_v2_v1C_09->busInfoList[i].data; + } + } + + *offset += sizeof(NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *grSmIssueRateModifier, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If pVSI and buffer are valid, then copy data and return the offset + if (grSmIssueRateModifier && buffer) + { + NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F *gr_get_sm_issue_rate_modifier_v1A_1F = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F)))) + return NV_ERR_BUFFER_TOO_SMALL; + + gr_get_sm_issue_rate_modifier_v1A_1F = (void*)(buffer + *offset); + + grSmIssueRateModifier->grRouteInfo.flags = gr_get_sm_issue_rate_modifier_v1A_1F->grRouteInfo.flags; + grSmIssueRateModifier->grRouteInfo.route = gr_get_sm_issue_rate_modifier_v1A_1F->grRouteInfo.route; + + grSmIssueRateModifier->imla0 = gr_get_sm_issue_rate_modifier_v1A_1F->imla0; + grSmIssueRateModifier->fmla16 = gr_get_sm_issue_rate_modifier_v1A_1F->fmla16; + grSmIssueRateModifier->dp = gr_get_sm_issue_rate_modifier_v1A_1F->dp; + grSmIssueRateModifier->fmla32 = gr_get_sm_issue_rate_modifier_v1A_1F->fmla32; + grSmIssueRateModifier->ffma = gr_get_sm_issue_rate_modifier_v1A_1F->ffma; + grSmIssueRateModifier->imla1 = gr_get_sm_issue_rate_modifier_v1A_1F->imla1; + grSmIssueRateModifier->imla2 = gr_get_sm_issue_rate_modifier_v1A_1F->imla2; + grSmIssueRateModifier->imla3 = gr_get_sm_issue_rate_modifier_v1A_1F->imla3; + grSmIssueRateModifier->imla4 = gr_get_sm_issue_rate_modifier_v1A_1F->imla4; + } + + *offset += sizeof(NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS *grInfoParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (grInfoParams && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07 *gr_info_v24_07 = NULL; + NvU32 i = 0, j = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07)))) + return NV_ERR_BUFFER_TOO_SMALL; + + gr_info_v24_07 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + for (j = 0; j < NV0080_CTRL_GR_INFO_MAX_SIZE_24_07; j++) + { + grInfoParams->engineInfo[i].infoList[j].index = gr_info_v24_07->engineInfo[i].infoList[j].index; + grInfoParams->engineInfo[i].infoList[j].data = gr_info_v24_07->engineInfo[i].infoList[j].data; + } + } + + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS *smOrderParams, NvU8 *buffer, + NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (smOrderParams && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01 *sm_order_v1F_01 = NULL; + NvU32 i = 0, j = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01)))) + return NV_ERR_BUFFER_TOO_SMALL; + + sm_order_v1F_01 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + for (j = 0; j globalSmOrder[i].globalSmId[j].gpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].gpcId; + smOrderParams->globalSmOrder[i].globalSmId[j].localTpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].localTpcId; + smOrderParams->globalSmOrder[i].globalSmId[j].localSmId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].localSmId; + smOrderParams->globalSmOrder[i].globalSmId[j].globalTpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].globalTpcId; + smOrderParams->globalSmOrder[i].globalSmId[j].virtualGpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].virtualGpcId; + smOrderParams->globalSmOrder[i].globalSmId[j].migratableTpcId = sm_order_v1F_01->globalSmOrder[i].globalSmId[j].migratableTpcId; + } + + smOrderParams->globalSmOrder[i].numSm = sm_order_v1F_01->globalSmOrder[i].numSm; + smOrderParams->globalSmOrder[i].numTpc = sm_order_v1F_01->globalSmOrder[i].numTpc; + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS *ropInfoParams, NvU8 *buffer, + NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (ropInfoParams && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05 *rop_info_v1B_05 = NULL; + NvU32 i = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05)))) + return NV_ERR_BUFFER_TOO_SMALL; + + rop_info_v1B_05 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + ropInfoParams->engineRopInfo[i].ropUnitCount = rop_info_v1B_05->engineRopInfo[i].ropUnitCount; + ropInfoParams->engineRopInfo[i].ropOperationsFactor = rop_info_v1B_05->engineRopInfo[i].ropOperationsFactor; + ropInfoParams->engineRopInfo[i].ropOperationsCount = rop_info_v1B_05->engineRopInfo[i].ropOperationsCount; + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS *ppcMaskParams, NvU8 *buffer, + NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (ppcMaskParams && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06 *ppc_mask_v1C_06 = NULL; + NvU32 i = 0, j = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06)))) + return NV_ERR_BUFFER_TOO_SMALL; + + ppc_mask_v1C_06 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + for (j = 0; j < NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03; j++) + { + ppcMaskParams->enginePpcMasks[i].mask[j] = ppc_mask_v1C_06->enginePpcMasks[i].mask[j]; + } + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS* ctxBuffInfo, NvU8* buffer, + NvU32 bufferSize, NvU32* offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (ctxBuffInfo && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07* ctx_buff_info_v25_07 = NULL; + NvU32 i = 0, j = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07)))) + return NV_ERR_BUFFER_TOO_SMALL; + + ctx_buff_info_v25_07 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + for (j = 0; j < NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT_v25_07; j++) + { + ctxBuffInfo->engineContextBuffersInfo[i].engine[j].size = ctx_buff_info_v25_07->engineContextBuffersInfo[i].engine[j].size; + ctxBuffInfo->engineContextBuffersInfo[i].engine[j].alignment = ctx_buff_info_v25_07->engineContextBuffersInfo[i].engine[j].alignment; + } + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B +( + NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS* pParams, + NvU8 *buffer, + NvU32 bufferSize, + NvU32 *offset +) +{ + if (offset == NULL) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if ((pParams != NULL) && (buffer != NULL)) + { + NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B *pParams_v25_0B = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B)))) + return NV_ERR_BUFFER_TOO_SMALL; + + pParams_v25_0B = (void*)(buffer + *offset); + + pParams->atomicsCaps = pParams_v25_0B->atomicsCaps; + } + + *offset += sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS *smIssueRateModifier,NvU8 *buffer, + NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (smIssueRateModifier && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05 *rate_modifier_v1B_05 = NULL; + NvU32 i = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05)))) + return NV_ERR_BUFFER_TOO_SMALL; + + rate_modifier_v1B_05 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + smIssueRateModifier->smIssueRateModifier[i].imla0 = rate_modifier_v1B_05->smIssueRateModifier[i].imla0; + smIssueRateModifier->smIssueRateModifier[i].imla1 = rate_modifier_v1B_05->smIssueRateModifier[i].imla1; + smIssueRateModifier->smIssueRateModifier[i].imla2 = rate_modifier_v1B_05->smIssueRateModifier[i].imla2; + smIssueRateModifier->smIssueRateModifier[i].imla3 = rate_modifier_v1B_05->smIssueRateModifier[i].imla3; + smIssueRateModifier->smIssueRateModifier[i].imla4 = rate_modifier_v1B_05->smIssueRateModifier[i].imla4; + smIssueRateModifier->smIssueRateModifier[i].fmla16 = rate_modifier_v1B_05->smIssueRateModifier[i].fmla16; + smIssueRateModifier->smIssueRateModifier[i].fmla32 = rate_modifier_v1B_05->smIssueRateModifier[i].fmla32; + smIssueRateModifier->smIssueRateModifier[i].ffma = rate_modifier_v1B_05->smIssueRateModifier[i].ffma; + smIssueRateModifier->smIssueRateModifier[i].dp = rate_modifier_v1B_05->smIssueRateModifier[i].dp; + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS *floorsweepMaskParams, NvU8 *buffer, + NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (floorsweepMaskParams && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03 *floorsweep_mask_params_v1D_03 = NULL; + NvU32 i = 0, j = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03)))) + return NV_ERR_BUFFER_TOO_SMALL; + + floorsweep_mask_params_v1D_03 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + for (j = 0; j < NV2080_CTRL_INTERNAL_GR_MAX_GPC_v1C_03; j++) + { + floorsweepMaskParams->floorsweepingMasks[i].tpcMask[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].tpcMask[j]; + floorsweepMaskParams->floorsweepingMasks[i].tpcCount[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].tpcCount[j]; + floorsweepMaskParams->floorsweepingMasks[i].numPesPerGpc[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].numPesPerGpc[j]; + floorsweepMaskParams->floorsweepingMasks[i].mmuPerGpc[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].mmuPerGpc[j]; + floorsweepMaskParams->floorsweepingMasks[i].zcullMask[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].zcullMask[j]; + } + + floorsweepMaskParams->floorsweepingMasks[i].gpcMask = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].gpcMask; + floorsweepMaskParams->floorsweepingMasks[i].physGpcMask = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].physGpcMask; + + for (j = 0; j < NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT_v1C_03; j++) + { + floorsweepMaskParams->floorsweepingMasks[i].tpcToPesMap[j] = floorsweep_mask_params_v1D_03->floorsweepingMasks[i].tpcToPesMap[j]; + } + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03); + + return NVOS_STATUS_SUCCESS; + +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS *zcullInfoParams, NvU8 *buffer, + NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (zcullInfoParams && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05 *zcull_info_v1B_05 = NULL; + NvU32 i = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05)))) + return NV_ERR_BUFFER_TOO_SMALL; + + zcull_info_v1B_05 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + zcullInfoParams->engineZcullInfo[i].widthAlignPixels = zcull_info_v1B_05->engineZcullInfo[i].widthAlignPixels; + zcullInfoParams->engineZcullInfo[i].heightAlignPixels = zcull_info_v1B_05->engineZcullInfo[i].heightAlignPixels; + zcullInfoParams->engineZcullInfo[i].pixelSquaresByAliquots = zcull_info_v1B_05->engineZcullInfo[i].pixelSquaresByAliquots; + zcullInfoParams->engineZcullInfo[i].aliquotTotal = zcull_info_v1B_05->engineZcullInfo[i].aliquotTotal; + zcullInfoParams->engineZcullInfo[i].zcullRegionByteMultiplier = zcull_info_v1B_05->engineZcullInfo[i].zcullRegionByteMultiplier; + zcullInfoParams->engineZcullInfo[i].zcullRegionHeaderSize = zcull_info_v1B_05->engineZcullInfo[i].zcullRegionHeaderSize; + zcullInfoParams->engineZcullInfo[i].zcullSubregionHeaderSize = zcull_info_v1B_05->engineZcullInfo[i].zcullSubregionHeaderSize; + zcullInfoParams->engineZcullInfo[i].subregionCount = zcull_info_v1B_05->engineZcullInfo[i].subregionCount; + zcullInfoParams->engineZcullInfo[i].subregionWidthAlignPixels = zcull_info_v1B_05->engineZcullInfo[i].subregionWidthAlignPixels; + zcullInfoParams->engineZcullInfo[i].subregionHeightAlignPixels = zcull_info_v1B_05->engineZcullInfo[i].subregionHeightAlignPixels; + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS *fecsRecordSize, NvU8 *buffer, + NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (fecsRecordSize && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05 *fecs_record_size_v1B_05 = NULL; + NvU32 i = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05)))) + return NV_ERR_BUFFER_TOO_SMALL; + + fecs_record_size_v1B_05 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + fecsRecordSize->fecsRecordSize[i].fecsRecordSize = fecs_record_size_v1B_05->fecsRecordSize[i].fecsRecordSize; + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS *fecsTraceDefines, NvU8 *buffer, + NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (fecsTraceDefines && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04 *fecs_trace_defines_v1D_04 = NULL; + NvU32 i = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04)))) + return NV_ERR_BUFFER_TOO_SMALL; + + fecs_trace_defines_v1D_04 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + fecsTraceDefines->fecsTraceDefines[i].fecsRecordSize = fecs_trace_defines_v1D_04->fecsTraceDefines[i].fecsRecordSize; + fecsTraceDefines->fecsTraceDefines[i].timestampHiTagMask = fecs_trace_defines_v1D_04->fecsTraceDefines[i].timestampHiTagMask; + fecsTraceDefines->fecsTraceDefines[i].timestampHiTagShift = fecs_trace_defines_v1D_04->fecsTraceDefines[i].timestampHiTagShift; + fecsTraceDefines->fecsTraceDefines[i].timestampVMask = fecs_trace_defines_v1D_04->fecsTraceDefines[i].timestampVMask; + fecsTraceDefines->fecsTraceDefines[i].numLowerBitsZeroShift = fecs_trace_defines_v1D_04->fecsTraceDefines[i].numLowerBitsZeroShift; + } + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS *grPdbPropertiesParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (grPdbPropertiesParams && buffer) + { + NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02 *gr_pdb_properties_v1E_02 = NULL; + NvU32 i = 0; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02)))) + return NV_ERR_BUFFER_TOO_SMALL; + + gr_pdb_properties_v1E_02 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_CTRL_INTERNAL_GR_MAX_ENGINES_1B_04; i++) + { + grPdbPropertiesParams->pdbTable[i].bPerSubCtxheaderSupported = gr_pdb_properties_v1E_02->pdbTable[i].bPerSubCtxheaderSupported; + } + + } + + *offset += sizeof(NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_STATIC_DATA_v25_0E(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If pVSI and buffer are valid, then copy data and return the offset + if (pVSI && buffer) + { + VGPU_STATIC_DATA_v25_0E *vgpu_static_data_v25_0E = NULL; + NvU32 i; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(VGPU_STATIC_DATA_v25_0E)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgpu_static_data_v25_0E = (void*)(buffer + *offset); + + pVSI->fbTaxLength = vgpu_static_data_v25_0E->fbTaxLength; + pVSI->fbLength = vgpu_static_data_v25_0E->fbLength; + pVSI->fbBusWidth = vgpu_static_data_v25_0E->fbBusWidth; + pVSI->fbioMask = vgpu_static_data_v25_0E->fbioMask; + pVSI->fbpMask = vgpu_static_data_v25_0E->fbpMask; + pVSI->ltcMask = vgpu_static_data_v25_0E->ltcMask; + pVSI->ltsCount = vgpu_static_data_v25_0E->ltsCount; + pVSI->subProcessIsolation = vgpu_static_data_v25_0E->subProcessIsolation; + pVSI->engineList = vgpu_static_data_v25_0E->engineList; + pVSI->sizeL2Cache = vgpu_static_data_v25_0E->sizeL2Cache; + pVSI->poisonFuseEnabled = vgpu_static_data_v25_0E->poisonFuseEnabled; + pVSI->guestManagedHwAlloc = vgpu_static_data_v25_0E->guestManagedHwAlloc; + + // gpuname + portMemCopy(pVSI->adapterName, sizeof(pVSI->adapterName), + vgpu_static_data_v25_0E->gpuName.adapterName, sizeof(pVSI->adapterName)); + portMemCopy(pVSI->adapterName_Unicode, sizeof(pVSI->adapterName_Unicode), + vgpu_static_data_v25_0E->gpuName.adapterName_Unicode, sizeof(pVSI->adapterName_Unicode)); + portMemCopy(pVSI->shortGpuNameString, sizeof(pVSI->shortGpuNameString), + vgpu_static_data_v25_0E->gpuName.shortGpuNameString, sizeof(pVSI->adapterName)); + + pVSI->bSplitVasBetweenServerClientRm = vgpu_static_data_v25_0E->bSplitVasBetweenServerClientRm; + pVSI->maxSupportedPageSize = vgpu_static_data_v25_0E->maxSupportedPageSize; + pVSI->bFlaSupported = vgpu_static_data_v25_0E->bFlaSupported; + pVSI->bPerRunlistChannelRamEnabled = vgpu_static_data_v25_0E->bPerRunlistChannelRamEnabled; + pVSI->bAtsSupported = vgpu_static_data_v25_0E->bAtsSupported; + + pVSI->bPerSubCtxheaderSupported = vgpu_static_data_v25_0E->bPerSubCtxheaderSupported; + pVSI->bC2CLinkUp = vgpu_static_data_v25_0E->bC2CLinkUp; + pVSI->bLocalEgmEnabled = vgpu_static_data_v25_0E->bLocalEgmEnabled; + pVSI->localEgmPeerId = vgpu_static_data_v25_0E->localEgmPeerId; + pVSI->bSelfHostedMode = vgpu_static_data_v25_0E->bSelfHostedMode; + + pVSI->ceFaultMethodBufferDepth = vgpu_static_data_v25_0E->ceFaultMethodBufferDepth; + pVSI->pcieGpuLinkCaps = vgpu_static_data_v25_0E->pcieGpuLinkCaps; + + portMemCopy(pVSI->grCapsBits, sizeof(pVSI->grCapsBits), + vgpu_static_data_v25_0E->grCapsBits, sizeof(vgpu_static_data_v25_0E->grCapsBits)); + + for (i = 0; i < NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_v25_0E; i++) + { + pVSI->gfxpBufferSize[i] = vgpu_static_data_v25_0E->gfxpBufferSize[i]; + pVSI->gfxpBufferAlignment[i] = vgpu_static_data_v25_0E->gfxpBufferAlignment[i]; + } + + for (i = 0; i < RPC_GR_BUFFER_TYPE_GRAPHICS_MAX_v25_0E; i++) + { + pVSI->grBufferSize[i] = vgpu_static_data_v25_0E->grBufferSize[i]; + } + + portMemCopy(pVSI->jpegCaps, sizeof(pVSI->jpegCaps), + vgpu_static_data_v25_0E->jpegCaps, sizeof(vgpu_static_data_v25_0E->jpegCaps)); + } + + *offset += sizeof(VGPU_STATIC_DATA_v25_0E); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *vgxSystemInfo, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If vgxSystemInfo and buffer are valid, then copy data and return the offset + if (vgxSystemInfo && buffer) + { + NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00 *vgx_system_info_v03_00 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgx_system_info_v03_00 = (void*)(buffer + *offset); + + portMemCopy(vgxSystemInfo->szHostDriverVersionBuffer, + sizeof(vgxSystemInfo->szHostDriverVersionBuffer), + vgx_system_info_v03_00->szHostDriverVersionBuffer, + sizeof(vgx_system_info_v03_00->szHostDriverVersionBuffer)); + portMemCopy(vgxSystemInfo->szHostVersionBuffer, + sizeof(vgxSystemInfo->szHostVersionBuffer), + vgx_system_info_v03_00->szHostVersionBuffer, + sizeof(vgx_system_info_v03_00->szHostVersionBuffer)); + portMemCopy(vgxSystemInfo->szHostTitleBuffer, + sizeof(vgxSystemInfo->szHostTitleBuffer), + vgx_system_info_v03_00->szHostTitleBuffer, + sizeof(vgx_system_info_v03_00->szHostTitleBuffer)); + + portMemCopy(vgxSystemInfo->szPluginTitleBuffer, + sizeof(vgxSystemInfo->szPluginTitleBuffer), + vgx_system_info_v03_00->szPluginTitleBuffer, + sizeof(vgx_system_info_v03_00->szPluginTitleBuffer)); + + portMemCopy(vgxSystemInfo->szHostUnameBuffer, + sizeof(vgxSystemInfo->szHostUnameBuffer), + vgx_system_info_v03_00->szHostUnameBuffer, + sizeof(vgx_system_info_v03_00->szHostUnameBuffer)); + + vgxSystemInfo->iHostChangelistNumber = vgx_system_info_v03_00->iHostChangelistNumber; + vgxSystemInfo->iPluginChangelistNumber = vgx_system_info_v03_00->iPluginChangelistNumber; + } + + *offset += sizeof(NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS *gidInfo, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If gidInfo and buffer are valid, then copy data and return the offset + if (gidInfo && buffer) + { + NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00 *gid_info_v03_00 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00)))) + return NV_ERR_BUFFER_TOO_SMALL; + + gid_info_v03_00 = (void*)(buffer + *offset); + + gidInfo->index = gid_info_v03_00->index; + gidInfo->flags = gid_info_v03_00->flags; + gidInfo->length = gid_info_v03_00->length; + portMemCopy(gidInfo->data, sizeof(gidInfo->data), gid_info_v03_00->data, sizeof(gid_info_v03_00->data)); + } + + *offset += sizeof(NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v03_00(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *skuInfo, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *skuInfo, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If skuInfo and buffer are valid, then copy data and return the offset + if (skuInfo && buffer) + { + NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E *sku_info_v25_0E = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E)))) + return NV_ERR_BUFFER_TOO_SMALL; + + sku_info_v25_0E = (void*)(buffer + *offset); + + skuInfo->BoardID = sku_info_v25_0E->BoardID; + skuInfo->skuConfigVersion = sku_info_v25_0E->skuConfigVersion; + portMemCopy(skuInfo->chipSKU, sizeof(skuInfo->chipSKU), + sku_info_v25_0E->chipSKU, sizeof(sku_info_v25_0E->chipSKU)); + portMemCopy(skuInfo->chipSKUMod, sizeof(skuInfo->chipSKUMod), + sku_info_v25_0E->chipSKUMod, sizeof(sku_info_v25_0E->chipSKUMod)); + portMemCopy(skuInfo->project, sizeof(skuInfo->project), + sku_info_v25_0E->project, sizeof(sku_info_v25_0E->project)); + portMemCopy(skuInfo->projectSKU, sizeof(skuInfo->projectSKU), + sku_info_v25_0E->projectSKU, sizeof(sku_info_v25_0E->projectSKU)); + portMemCopy(skuInfo->CDP, sizeof(skuInfo->CDP), + sku_info_v25_0E->CDP, sizeof(sku_info_v25_0E->CDP)); + portMemCopy(skuInfo->projectSKUMod, sizeof(skuInfo->projectSKUMod), + sku_info_v25_0E->projectSKUMod, sizeof(sku_info_v25_0E->projectSKUMod)); + skuInfo->businessCycle = sku_info_v25_0E->businessCycle; + } + + *offset += sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *fbRegionInfoParams, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If fbRegionInfoParams and buffer are valid, then copy data and return the offset + if (fbRegionInfoParams && buffer) + { + NvU32 i; + NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00 *fbRegionInfoParams_v03_00 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00)))) + return NV_ERR_BUFFER_TOO_SMALL; + + fbRegionInfoParams_v03_00 = (void*)(buffer + *offset); + + fbRegionInfoParams->numFBRegions = fbRegionInfoParams_v03_00->numFBRegions; + + for(i = 0; i < NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES; i++) + { + fbRegionInfoParams->fbRegion[i].base = fbRegionInfoParams_v03_00->fbRegion[i].base; + fbRegionInfoParams->fbRegion[i].limit = fbRegionInfoParams_v03_00->fbRegion[i].limit; + fbRegionInfoParams->fbRegion[i].reserved = fbRegionInfoParams_v03_00->fbRegion[i].reserved; + fbRegionInfoParams->fbRegion[i].performance = fbRegionInfoParams_v03_00->fbRegion[i].performance; + fbRegionInfoParams->fbRegion[i].supportCompressed = fbRegionInfoParams_v03_00->fbRegion[i].supportCompressed; + fbRegionInfoParams->fbRegion[i].supportISO = fbRegionInfoParams_v03_00->fbRegion[i].supportISO; + fbRegionInfoParams->fbRegion[i].bProtected = fbRegionInfoParams_v03_00->fbRegion[i].bProtected; + portMemCopy(&fbRegionInfoParams->fbRegion[i].blackList, + sizeof(fbRegionInfoParams->fbRegion[i].blackList), + &fbRegionInfoParams_v03_00->fbRegion[i].blackList, + sizeof(fbRegionInfoParams_v03_00->fbRegion[i].blackList)); + } + } + + *offset += sizeof(NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS *ciProfiles, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If ciProfiles and buffer are valid, then copy data and return the offset + if (ciProfiles && buffer) + { + NvU32 i; + NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04 *ciProfiles_v20_04 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04)))) + return NV_ERR_BUFFER_TOO_SMALL; + + ciProfiles_v20_04 = (void*)(buffer + *offset); + + NV_ASSERT(ciProfiles_v20_04->profileCount <= NV_ARRAY_ELEMENTS(ciProfiles->profiles)); + + ciProfiles->profileCount = ciProfiles_v20_04->profileCount; + for (i = 0; i < ciProfiles->profileCount; i++) + { + ciProfiles->profiles[i].gfxGpcCount = ciProfiles_v20_04->profiles[i].gfxGpcCount; + ciProfiles->profiles[i].computeSize = ciProfiles_v20_04->profiles[i].computeSize; + ciProfiles->profiles[i].gpcCount = ciProfiles_v20_04->profiles[i].gpcCount; + ciProfiles->profiles[i].veidCount = ciProfiles_v20_04->profiles[i].veidCount; + ciProfiles->profiles[i].smCount = ciProfiles_v20_04->profiles[i].smCount; + } + } + + *offset += sizeof(NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v18_07(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *execPartitionInfo, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v21_04(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *execPartitionInfo, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v21_09(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *execPartitionInfo, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS *execPartitionInfo, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If execPartitionInfo and buffer are valid, then copy data and return the offset + if (execPartitionInfo && buffer) + { + NvU32 i; + NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05 *execPartitionInfo_v24_05 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05)))) + return NV_ERR_BUFFER_TOO_SMALL; + + execPartitionInfo_v24_05 = (void*)(buffer + *offset); + + execPartitionInfo->execPartCount = execPartitionInfo_v24_05->execPartCount; + + for (i = 0; i < execPartitionInfo->execPartCount; i++) + { + NVC637_CTRL_EXEC_PARTITIONS_INFO *dst = &(execPartitionInfo->execPartInfo[i]); + + execPartitionInfo->execPartId[i] = execPartitionInfo_v24_05->execPartId[i]; + + dst->gpcCount = execPartitionInfo_v24_05->execPartInfo[i].gpcCount; + dst->gfxGpcCount = execPartitionInfo_v24_05->execPartInfo[i].gfxGpcCount; + dst->veidCount = execPartitionInfo_v24_05->execPartInfo[i].veidCount; + dst->ceCount = execPartitionInfo_v24_05->execPartInfo[i].ceCount; + dst->nvEncCount = execPartitionInfo_v24_05->execPartInfo[i].nvEncCount; + dst->nvDecCount = execPartitionInfo_v24_05->execPartInfo[i].nvDecCount; + dst->nvJpgCount = execPartitionInfo_v24_05->execPartInfo[i].nvJpgCount; + dst->ofaCount = execPartitionInfo_v24_05->execPartInfo[i].ofaCount; + dst->sharedEngFlag = execPartitionInfo_v24_05->execPartInfo[i].sharedEngFlag; + dst->smCount = execPartitionInfo_v24_05->execPartInfo[i].smCount; + dst->spanStart = execPartitionInfo_v24_05->execPartInfo[i].spanStart; + dst->computeSize = execPartitionInfo_v24_05->execPartInfo[i].computeSize; + } + } + + *offset += sizeof(NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *zbcTableSizes, + NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If zbcTableSizes and buffer are valid, then copy data and return the offset + if (zbcTableSizes && buffer) + { + NvU32 i; + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07 *zbcTableSizes_v1A_07 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07)))) + return NV_ERR_BUFFER_TOO_SMALL; + + zbcTableSizes_v1A_07 = (void*)(buffer + *offset); + + for (i = 0; i < NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07; i++) { + zbcTableSizes[i].indexStart = zbcTableSizes_v1A_07[i].indexStart; + zbcTableSizes[i].indexEnd = zbcTableSizes_v1A_07[i].indexEnd; + } + } + + *offset += sizeof(NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07) * NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT_v1A_07; + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_GPU_PARTITION_INFO_v12_01(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_GPU_PARTITION_INFO_v18_03(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_GPU_PARTITION_INFO_v20_01(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_GPU_PARTITION_INFO_v21_09(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_GPU_PARTITION_INFO_v24_05(GPU_PARTITION_INFO *gpuPartitionInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If gpuPartitionInfo and buffer are valid, then copy data and return the offset + if (gpuPartitionInfo && buffer) + { + NvU32 i; + GPU_PARTITION_INFO_v24_05 *gpu_partition_info_v24_05 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(GPU_PARTITION_INFO_v24_05)))) + return NV_ERR_BUFFER_TOO_SMALL; + + gpu_partition_info_v24_05 = (void*)(buffer + *offset); + + // GPU PARTITION INFO + gpuPartitionInfo->swizzId = gpu_partition_info_v24_05->swizzId; + gpuPartitionInfo->grEngCount = gpu_partition_info_v24_05->grEngCount; + gpuPartitionInfo->veidCount = gpu_partition_info_v24_05->veidCount; + gpuPartitionInfo->ceCount = gpu_partition_info_v24_05->ceCount; + gpuPartitionInfo->gpcCount = gpu_partition_info_v24_05->gpcCount; + gpuPartitionInfo->virtualGpcCount = gpu_partition_info_v24_05->virtualGpcCount; + gpuPartitionInfo->gfxGpcCount = gpu_partition_info_v24_05->gfxGpcCount; + gpuPartitionInfo->nvDecCount = gpu_partition_info_v24_05->nvDecCount; + gpuPartitionInfo->nvEncCount = gpu_partition_info_v24_05->nvEncCount; + gpuPartitionInfo->nvJpgCount = gpu_partition_info_v24_05->nvJpgCount; + gpuPartitionInfo->partitionFlag = gpu_partition_info_v24_05->partitionFlag; + gpuPartitionInfo->smCount = gpu_partition_info_v24_05->smCount; + gpuPartitionInfo->nvOfaCount = gpu_partition_info_v24_05->nvOfaCount; + gpuPartitionInfo->memSize = gpu_partition_info_v24_05->memSize; + gpuPartitionInfo->bValid = gpu_partition_info_v24_05->bValid; + gpuPartitionInfo->span.lo = gpu_partition_info_v24_05->span.lo; + gpuPartitionInfo->span.hi = gpu_partition_info_v24_05->span.hi; + gpuPartitionInfo->validCTSIdMask = gpu_partition_info_v24_05->validCTSIdMask; + + for (i = 0; i < gpuPartitionInfo->grEngCount; i++) + { + gpuPartitionInfo->gpcsPerGr[i] = gpu_partition_info_v24_05->gpcsPerGr[i]; + gpuPartitionInfo->veidsPerGr[i] = gpu_partition_info_v24_05->veidsPerGr[i]; + gpuPartitionInfo->virtualGpcsPerGr[i] = gpu_partition_info_v24_05->virtualGpcsPerGr[i]; + gpuPartitionInfo->gfxGpcPerGr[i] = gpu_partition_info_v24_05->gfxGpcPerGr[i]; + } + } + *offset += sizeof(GPU_PARTITION_INFO_v24_05); + + return NVOS_STATUS_SUCCESS; +} + +// NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS deserialization is used starting with v24_06 +NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v15_01(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v1A_04(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v1C_09(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v20_03(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *eccStatusParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If eccStatusParams and buffer are valid, then copy data and return the offset + if (eccStatusParams && buffer) + { + NvU32 i; + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06 *eccStatusParams_v24_06 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06)))) + return NV_ERR_BUFFER_TOO_SMALL; + + eccStatusParams_v24_06 = (void*)(buffer + *offset); + + eccStatusParams->bFatalPoisonError = eccStatusParams_v24_06->bFatalPoisonError; + + for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT_v24_06; i++) { + eccStatusParams->units[i].enabled = eccStatusParams_v24_06->units[i].enabled; + eccStatusParams->units[i].scrubComplete = eccStatusParams_v24_06->units[i].scrubComplete; + eccStatusParams->units[i].supported = eccStatusParams_v24_06->units[i].supported; + eccStatusParams->units[i].dbe.count = eccStatusParams_v24_06->units[i].dbe.count; + eccStatusParams->units[i].dbeNonResettable.count = eccStatusParams_v24_06->units[i].dbeNonResettable.count; + eccStatusParams->units[i].sbe.count = eccStatusParams_v24_06->units[i].sbe.count; + eccStatusParams->units[i].sbeNonResettable.count = eccStatusParams_v24_06->units[i].sbeNonResettable.count; + } + } + *offset += sizeof(NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *grZcullInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If grZcullInfo and buffer are valid, then copy data and return the offset + if (grZcullInfo && buffer) + { + NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01 *get_zcull_info_params_12_01 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01)))) + return NV_ERR_BUFFER_TOO_SMALL; + + get_zcull_info_params_12_01 = (void*)(buffer + *offset); + + grZcullInfo->widthAlignPixels = get_zcull_info_params_12_01->widthAlignPixels; + grZcullInfo->heightAlignPixels = get_zcull_info_params_12_01->heightAlignPixels; + grZcullInfo->pixelSquaresByAliquots = get_zcull_info_params_12_01->pixelSquaresByAliquots; + grZcullInfo->aliquotTotal = get_zcull_info_params_12_01->aliquotTotal; + grZcullInfo->zcullRegionByteMultiplier = get_zcull_info_params_12_01->zcullRegionByteMultiplier; + grZcullInfo->zcullRegionHeaderSize = get_zcull_info_params_12_01->zcullRegionHeaderSize; + grZcullInfo->zcullSubregionHeaderSize = get_zcull_info_params_12_01->zcullSubregionHeaderSize; + grZcullInfo->subregionCount = get_zcull_info_params_12_01->subregionCount; + grZcullInfo->subregionWidthAlignPixels = get_zcull_info_params_12_01->subregionWidthAlignPixels; + grZcullInfo->subregionHeightAlignPixels = get_zcull_info_params_12_01->subregionHeightAlignPixels; + + } + + *offset += sizeof(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_STATIC_PROPERTIES_v1B_01(VGPU_STATIC_PROPERTIES *vgpuStaticProperties, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If vgpuStaticProperties and buffer are valid, then copy data and return the offset + if (vgpuStaticProperties && buffer) + { + VGPU_STATIC_PROPERTIES_v1B_01 *vgpu_static_properties_v1B_01 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(VGPU_STATIC_PROPERTIES_v1B_01)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgpu_static_properties_v1B_01 = (void*)(buffer + *offset); + + // encSessionStatsReportingState + vgpuStaticProperties->encSessionStatsReportingState = vgpu_static_properties_v1B_01->encSessionStatsReportingState; + vgpuStaticProperties->bProfilingTracingEnabled = vgpu_static_properties_v1B_01->bProfilingTracingEnabled; + vgpuStaticProperties->bDebuggingEnabled = vgpu_static_properties_v1B_01->bDebuggingEnabled; + vgpuStaticProperties->channelCount = vgpu_static_properties_v1B_01->channelCount; + vgpuStaticProperties->bPblObjNotPresent = vgpu_static_properties_v1B_01->bPblObjNotPresent; + } + + *offset += sizeof(VGPU_STATIC_PROPERTIES_v1B_01); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_BSP_GET_CAPS_v25_00(VGPU_BSP_GET_CAPS *vgpuBspCaps, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If vgpuBspCaps and buffer are valid, then copy data and return the offset + if (vgpuBspCaps && buffer) + { + VGPU_BSP_GET_CAPS_v25_00 *vgpu_bsp_get_caps_v25_00 = NULL; + NvU32 i; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(VGPU_BSP_GET_CAPS_v25_00)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgpu_bsp_get_caps_v25_00 = (void*)(buffer + *offset); + + for (i = 0; i < MAX_NVDEC_ENGINES_V25_00; i++) + { + portMemCopy(&(*vgpuBspCaps)[i].capsTbl, NV0080_CTRL_BSP_CAPS_TBL_SIZE, + &vgpu_bsp_get_caps_v25_00->bspCaps[i].capsTblData, sizeof(vgpu_bsp_get_caps_v25_00->bspCaps[i].capsTblData)); + } + } + + *offset += sizeof(VGPU_BSP_GET_CAPS_v25_00); + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09(VGPU_GET_LATENCY_BUFFER_SIZE *vgpu_get_latency_buffer_size, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If vgpu_get_latency_buffer_size and buffer are valid, then copy data and return the offset + if (vgpu_get_latency_buffer_size && buffer) + { + VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09 *vgpu_get_latency_buffer_size_v1C_09 = NULL; + NV0080_CTRL_FIFO_GET_LATENCY_BUFFER_SIZE_PARAMS *fifoLatencyBufferSize = *vgpu_get_latency_buffer_size; + NvU32 i; + + if (bufferSize < (*offset + sizeof(VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09))) + return NV_ERR_NO_MEMORY; + + vgpu_get_latency_buffer_size_v1C_09 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_ENGINE_TYPE_LAST_v1C_09; i++) + { + fifoLatencyBufferSize[i].engineID = vgpu_get_latency_buffer_size_v1C_09->fifoLatencyBufferSize[i].engineID; + fifoLatencyBufferSize[i].gpEntries = vgpu_get_latency_buffer_size_v1C_09->fifoLatencyBufferSize[i].gpEntries; + fifoLatencyBufferSize[i].pbEntries = vgpu_get_latency_buffer_size_v1C_09->fifoLatencyBufferSize[i].pbEntries; + } + } + + // If vgpu_get_latency_buffer_size or buffer is NULL, then this will be used to determine the size of the + // static info buffer corresponding to the negotiated version + *offset += sizeof(VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_CE_GET_CAPS_V2_v24_09(VGPU_CE_GET_CAPS_V2 *ceCapsPtr, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If ceCapsPtr and buffer are valid, then copy data and return the offset + if (ceCapsPtr && buffer) + { + NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *ceCaps = *ceCapsPtr; + VGPU_CE_GET_CAPS_V2_v24_09 *vgpu_ce_get_caps_v2_v24_09 = NULL; + NvU32 i; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(VGPU_CE_GET_CAPS_V2_v24_09)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgpu_ce_get_caps_v2_v24_09 = (void*)(buffer + *offset); + + for (i = 0; i < NV2080_ENGINE_TYPE_COPY_SIZE_v24_09; i++) { + + ceCaps[i].ceEngineType = vgpu_ce_get_caps_v2_v24_09->ceCaps[i].ceEngineType; + portMemCopy(&ceCaps[i].capsTbl, NV2080_CTRL_CE_CAPS_TBL_SIZE, + &vgpu_ce_get_caps_v2_v24_09->ceCaps[i].capsTbl, NV2080_CTRL_CE_CAPS_TBL_SIZE); + } + } + + *offset += sizeof(VGPU_CE_GET_CAPS_V2_v24_09); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS *nvlinkCaps, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If nvlinkCaps and buffer are valid, then copy data and return the offset + if (nvlinkCaps && buffer) + { + NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02 *get_nvlink_caps_v15_02 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02)))) + return NV_ERR_BUFFER_TOO_SMALL; + + get_nvlink_caps_v15_02 = (void*)(buffer + *offset); + + nvlinkCaps->capsTbl = get_nvlink_caps_v15_02->capsTbl; + nvlinkCaps->lowestNvlinkVersion = get_nvlink_caps_v15_02->lowestNvlinkVersion; + nvlinkCaps->highestNvlinkVersion = get_nvlink_caps_v15_02->highestNvlinkVersion; + nvlinkCaps->lowestNciVersion = get_nvlink_caps_v15_02->lowestNciVersion; + nvlinkCaps->highestNciVersion = get_nvlink_caps_v15_02->highestNciVersion; + nvlinkCaps->discoveredLinkMask = get_nvlink_caps_v15_02->discoveredLinkMask; + nvlinkCaps->enabledLinkMask = get_nvlink_caps_v15_02->enabledLinkMask; + } + + *offset += sizeof(NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18(NV2080_CTRL_FLA_GET_RANGE_PARAMS *range_params, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If range_params and buffer are valid, then copy data and return the offset + if (range_params && buffer) + { + NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18 *range_params_v1A_18 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18)))) + return NV_ERR_BUFFER_TOO_SMALL; + + range_params_v1A_18 = (void*)(buffer + *offset); + + range_params->base = range_params_v1A_18->base; + range_params->size = range_params_v1A_18->size; + + } + + *offset += sizeof(NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *vgpuConfig, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If vgpuConfig and buffer are valid, then copy data and return the offset + if (vgpuConfig && buffer) + { + NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C *vgpu_get_config_params_v21_0C = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C)))) + return NV_ERR_BUFFER_TOO_SMALL; + + vgpu_get_config_params_v21_0C = (void*)(buffer + *offset); + + // vgpuConfig + vgpuConfig->frameRateLimiter = vgpu_get_config_params_v21_0C->frameRateLimiter; + vgpuConfig->swVSyncEnabled = vgpu_get_config_params_v21_0C->swVSyncEnabled; + vgpuConfig->cudaEnabled = vgpu_get_config_params_v21_0C->cudaEnabled; + vgpuConfig->pluginPteBlitEnabled = vgpu_get_config_params_v21_0C->pluginPteBlitEnabled; + vgpuConfig->disableWddm1xPreemption = vgpu_get_config_params_v21_0C->disableWddm1xPreemption; + vgpuConfig->debugBufferSize = vgpu_get_config_params_v21_0C->debugBufferSize; + vgpuConfig->debugBuffer = vgpu_get_config_params_v21_0C->debugBuffer; + vgpuConfig->guestFbOffset = vgpu_get_config_params_v21_0C->guestFbOffset; + vgpuConfig->mappableCpuHostAperture = vgpu_get_config_params_v21_0C->mappableCpuHostAperture; + vgpuConfig->linuxInterruptOptimization = vgpu_get_config_params_v21_0C->linuxInterruptOptimization; + vgpuConfig->vgpuDeviceCapsBits = vgpu_get_config_params_v21_0C->vgpuDeviceCapsBits; + vgpuConfig->maxPixels = vgpu_get_config_params_v21_0C->maxPixels; + vgpuConfig->uvmEnabledFeatures = vgpu_get_config_params_v21_0C->uvmEnabledFeatures; + vgpuConfig->enableKmdSysmemScratch = vgpu_get_config_params_v21_0C->enableKmdSysmemScratch; + } + + *offset += sizeof(NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS *pcieSupportedGpuAtomics, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If pcieSupportedGpuAtomics and buffer are valid, then copy data and return the offset + if (pcieSupportedGpuAtomics && buffer) + { + NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08 *pcie_supported_gpu_atomics_v1F_08 = NULL; + NvU32 i; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08)))) + return NV_ERR_BUFFER_TOO_SMALL; + + pcie_supported_gpu_atomics_v1F_08 = (void*)(buffer + *offset); + + NV_ASSERT_OR_RETURN(NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT <= NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08, + NV_ERR_INSUFFICIENT_RESOURCES); + + for (i = 0; i < NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT_v1F_08; i++) { + pcieSupportedGpuAtomics->atomicOp[i].bSupported = pcie_supported_gpu_atomics_v1F_08->atomicOp[i].bSupported; + pcieSupportedGpuAtomics->atomicOp[i].attributes = pcie_supported_gpu_atomics_v1F_08->atomicOp[i].attributes; + } + } + + *offset += sizeof(NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *cegetAllCaps, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If cegetAllCaps and buffer are valid, then copy data and return the offset + if (cegetAllCaps && buffer) + { + NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A *ce_get_all_caps_v21_0A = NULL; + NvU32 i; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A)))) + return NV_ERR_BUFFER_TOO_SMALL; + + ce_get_all_caps_v21_0A = (void*)(buffer + *offset); + + NV_ASSERT_OR_RETURN(NV2080_CTRL_MAX_PCES <= NV2080_CTRL_MAX_PCES_v21_0A, + NV_ERR_INSUFFICIENT_RESOURCES); + + NV_ASSERT_OR_RETURN(NV2080_CTRL_CE_CAPS_TBL_SIZE <= NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A, + NV_ERR_INSUFFICIENT_RESOURCES); + + cegetAllCaps->present = ce_get_all_caps_v21_0A->present; + + for (i = 0; i < NV2080_CTRL_MAX_PCES_v21_0A; i++) { + portMemCopy(cegetAllCaps->capsTbl[i], (sizeof(NvU8) * NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A), + ce_get_all_caps_v21_0A->ceCaps[i].capsTbl, (sizeof(NvU8) * NV2080_CTRL_CE_CAPS_TBL_SIZE_v21_0A)); + } + } + + *offset += sizeof(NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS *c2cInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + // If c2cInfo and buffer are valid, then copy data and return the offset + if (c2cInfo && buffer) + { + NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01 *c2c_info_v22_01 = NULL; + + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01)))) + return NV_ERR_BUFFER_TOO_SMALL; + + c2c_info_v22_01 = (void*)(buffer + *offset); + + c2cInfo->bIsLinkUp = c2c_info_v22_01->bIsLinkUp; + c2cInfo->nrLinks = c2c_info_v22_01->nrLinks; + c2cInfo->linkMask = c2c_info_v22_01->linkMask; + c2cInfo->perLinkBwMBps = c2c_info_v22_01->perLinkBwMBps; + c2cInfo->remoteType = c2c_info_v22_01->remoteType; + } + + *offset += sizeof(NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01); + + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00( + NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, + NvU32 *offset) +{ + NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00 *pParams_v25_00 = NULL; + + if (offset == NULL) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (pParams != NULL && buffer != NULL) + { + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(*pParams_v25_00)))) + return NV_ERR_BUFFER_TOO_SMALL; + + pParams_v25_00 = (void*)(buffer + *offset); + NV_ASSERT_OR_RETURN(NV0080_CTRL_MSENC_CAPS_TBL_SIZE_V25_00 <= + NV0080_CTRL_MSENC_CAPS_TBL_SIZE, + NV_ERR_INSUFFICIENT_RESOURCES); + + pParams->instanceId = pParams_v25_00->instanceId; + portMemCopy(pParams->capsTbl, sizeof(pParams->capsTbl), + pParams_v25_00->capsTbl, sizeof(pParams_v25_00->capsTbl)); + } + + *offset += sizeof(*pParams_v25_00); + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01( + NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01 *pParams_v25_01 = NULL; + + if (offset == NULL) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (pParams != NULL && buffer != NULL) + { + NvU32 i; + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(*pParams_v25_01)))) + return NV_ERR_BUFFER_TOO_SMALL; + + pParams_v25_01 = (void*)(buffer + *offset); + + pParams->numConstructedFalcons = pParams_v25_01->numConstructedFalcons; + for (i = 0; i < NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS; i++) { + NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO *dst = &(pParams->constructedFalconsTable[i]); + NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO_v25_01 *src = &(pParams_v25_01->constructedFalconsTable[i]); + + dst->engDesc = src->engDesc; + dst->ctxAttr = src->ctxAttr; + dst->ctxBufferSize = src->ctxBufferSize; + dst->addrSpaceList = src->addrSpaceList; + dst->registerBase = src->registerBase; + } + } + + *offset += sizeof(*pParams_v25_01); + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_P2P_CAPABILITY_PARAMS_v25_03( + VGPU_P2P_CAPABILITY_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, + NvU32 *offset) +{ + VGPU_P2P_CAPABILITY_PARAMS_v25_03 *pParams_v = NULL; + + if (offset == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pParams != NULL && buffer != NULL) + { + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(*pParams_v)))) + return NV_ERR_BUFFER_TOO_SMALL; + + pParams_v = (void*)(buffer + *offset); + + pParams->bGpuSupportsFabricProbe = pParams_v->bGpuSupportsFabricProbe; + } + + *offset += sizeof(*pParams_v); + return NV_OK; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05( + NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05 *pParams_v25_05 = NULL; + + if (offset == NULL) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (pParams != NULL && buffer != NULL) + { + NvU32 i; + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(*pParams_v25_05)))) + return NV_ERR_BUFFER_TOO_SMALL; + + pParams_v25_05 = (void*)(buffer + *offset); + + pParams->numEntries = pParams_v25_05->numEntries; + for (i = 0; i < NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES; i++) { + NV2080_CTRL_INTERNAL_DEVICE_INFO *dst = &(pParams->deviceInfoTable[i]); + NV2080_CTRL_INTERNAL_DEVICE_INFO_v25_05 *src = &(pParams_v25_05->deviceInfoTable[i]); + + dst->faultId = src->faultId; + dst->instanceId = src->instanceId; + dst->typeEnum = src->typeEnum; + dst->resetId = src->resetId; + dst->devicePriBase = src->devicePriBase; + dst->isEngine = src->isEngine; + dst->rlEngId = src->rlEngId; + dst->runlistPriBase = src->runlistPriBase; + dst->groupId = src->groupId; + } + } + + *offset += sizeof(*pParams_v25_05); + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06( + NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, + NvU32 *offset) +{ + NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06 *pParams_v25_06 = NULL; + + if (offset == NULL) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + + if (pParams != NULL && buffer != NULL) + { + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(*pParams_v25_06)))) + return NV_ERR_BUFFER_TOO_SMALL; + + pParams_v25_06 = (void*)(buffer + *offset); + + pParams->bOneToOneComptagLineAllocation = pParams_v25_06->bOneToOneComptagLineAllocation; + pParams->bUseOneToFourComptagLineAllocation = pParams_v25_06->bUseOneToFourComptagLineAllocation; + pParams->bUseRawModeComptaglineAllocation = pParams_v25_06->bUseRawModeComptaglineAllocation; + pParams->bDisableCompbitBacking = pParams_v25_06->bDisableCompbitBacking; + pParams->bDisablePostL2Compression = pParams_v25_06->bDisablePostL2Compression; + pParams->bEnabledEccFBPA = pParams_v25_06->bEnabledEccFBPA; + pParams->bL2PreFill = pParams_v25_06->bL2PreFill; + pParams->l2CacheSize = pParams_v25_06->l2CacheSize; + pParams->bFbpaPresent = pParams_v25_06->bFbpaPresent; + pParams->comprPageSize = pParams_v25_06->comprPageSize; + pParams->comprPageShift = pParams_v25_06->comprPageShift; + pParams->ramType = pParams_v25_06->ramType; + pParams->ltcCount = pParams_v25_06->ltcCount; + pParams->ltsPerLtcCount = pParams_v25_06->ltsPerLtcCount; + } + + *offset += sizeof(*pParams_v25_06); + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + if (!offset) + { + return NVOS_STATUS_ERROR_INVALID_ARGUMENT; + } + // If pParams and buffer are valid, then copy data and return the offset + if (pParams && buffer) + { + NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13 *pParams_v25_13 = NULL; + if ((bufferSize < *offset) || + (bufferSize < (*offset + sizeof(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13)))) + return NV_ERR_BUFFER_TOO_SMALL; + pParams_v25_13 = (void*)(buffer + *offset); + pParams->eccMask = pParams_v25_13->eccMask; + pParams->nvlinkMask = pParams_v25_13->nvlinkMask; + } + *offset += sizeof(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13); + return NVOS_STATUS_SUCCESS; +} + +// Stub functions for earlier versions + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v18_07(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v18_0C(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v18_0F(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v1A_02(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v1A_04(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v1A_07(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v1C_09(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v20_03(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v21_04(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v21_09(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO2_v24_05(VGPU_STATIC_INFO2 *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_SUCCESS; +} + +NV_STATUS deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v03_00(NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *grZcullInfo, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v07_00(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v09_04(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v12_00(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v12_01(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v12_06(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v12_0A(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v13_06(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v16_02(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v16_05(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v16_07(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v17_00(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v17_01(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v17_05(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v18_03(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v18_04(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v18_0E(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v18_10(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v18_11(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v18_13(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v18_16(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v19_00(VGPU_STATIC_INFO *vgpu_static_info, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v1A_00(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v1A_05(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v1B_03(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v1D_01(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v1F_02(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v1F_09(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v20_01(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v20_04(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v21_09(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v23_01(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_VGPU_STATIC_INFO_v24_05(VGPU_STATIC_INFO *pVSI, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} + +NV_STATUS deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B(NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS *pParams, NvU8 *buffer, NvU32 bufferSize, NvU32 *offset) +{ + return NVOS_STATUS_ERROR_NOT_SUPPORTED; +} diff --git a/src/nvidia/kernel/vgpu/nv/vgpu_events.c b/src/nvidia/kernel/vgpu/nv/vgpu_events.c new file mode 100644 index 0000000000..dc85ca1703 --- /dev/null +++ b/src/nvidia/kernel/vgpu/nv/vgpu_events.c @@ -0,0 +1,512 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +//****************************************************************************** +// +// Description: +// This module implements event ring buffers and +// the vGPU interrupt handler. +// +//****************************************************************************** + +#include "vgpu/vgpu_events.h" + +#include "kernel/core/core.h" +#include "kernel/core/locks.h" +#include "kernel/core/system.h" +#include "kernel/gpu/gpu.h" +#include "kernel/gpu/mem_mgr/heap.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/rc/kernel_rc.h" +#include "kernel/rmapi/event.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/gpu_fabric_probe.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/device/device.h" +#include "gpu/mem_sys/kern_mem_sys.h" + +#include "Nvcm.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "objtmr.h" +#include "os/os.h" +#include "vgpu/dev_vgpu.h" +#include "vgpu/rpc.h" +#include "vgpu/vgpu_util.h" + +#ifndef RM_PAGE_SIZE +#include "gpu/mem_mgr/virt_mem_allocator_common.h" +#endif + +#include "gpu/bus/kern_bus.h" + +// workitem callback for pstate change event +static void +_rmPstateEventCallback(NvU32 gpuInstance, void *pPstateParams); + +static inline NvU32 _readEventBufPut(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + return pVGpu->gspResponseBuf->v1.putEventBuf; +} + +static inline NvU32 _readEventBufGet(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + return pVGpu->gspCtrlBuf->v1.getEventBuf; +} + +static inline void _writeEventBufGet(OBJGPU *pGpu, OBJVGPU *pVGpu, NvU32 val) +{ + pVGpu->gspCtrlBuf->v1.getEventBuf = val; +} + +// This function is called when the first device is allocated. +// Different address space configs on different arch +// AD10x +// - Memory is always allocated on FBMEM +// GH100+ +// - Memory is allocated on SYSMEM when BAR2 is in physical mode +// - memory is allocated on FBMEM when BAR2 switches virtual mode +// GH180 +// - Memory is allocated on SYSMEM initially +// - Memory is allocated on FBMEM after C2C mapping is completed +// +NV_STATUS _setupGspEventInfrastructure(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status; + NV_ADDRESS_SPACE addressSpace = ADDR_FBMEM; + NvU32 memFlags = 0; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + memFlags = MEMDESC_FLAGS_CPU_ONLY; + + if (IsGH100orBetter(pGpu) && (!kbusIsBar2Initialized(pKernelBus))) + addressSpace = ADDR_SYSMEM; + + status = _allocRpcMemDesc(pGpu, + RM_PAGE_SIZE, + NV_MEMORY_CONTIGUOUS, + addressSpace, + memFlags, + &pVGpu->eventRing.mem.pMemDesc, + (void**)&pVGpu->eventRing.mem.pMemory, + (void**)&pVGpu->eventRing.mem.pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "_setupGspEventInfrastructure: GSP Event buf memory setup failed: 0x%x\n", status); + return status; + } + + pVGpu->eventRing.mem.pfn = memdescGetPte(pVGpu->eventRing.mem.pMemDesc, AT_GPU, 0) >> RM_PAGE_SHIFT; + + portMemSet(pVGpu->eventRing.mem.pMemory, 0, memdescGetSize(pVGpu->eventRing.mem.pMemDesc)); + + return NV_OK; +} + +// This function is called when the device is freed. +void _teardownGspEventInfrastructure(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + pVGpu->eventRing.mem.pfn = 0; + + _freeRpcMemDesc(pGpu, + &pVGpu->eventRing.mem.pMemDesc, + (void**)&pVGpu->eventRing.mem.pMemory, + (void**)&pVGpu->eventRing.mem.pPriv); +} + +// Check if a VGPU event is pending +NvBool +vgpuGetPendingEvent(OBJGPU *pGpu, THREAD_STATE_NODE *pThreadState) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + if (pVGpu->bGspPlugin) + { + if (_readEventBufPut(pGpu, pVGpu) != _readEventBufGet(pGpu, pVGpu)) + { + return NV_TRUE; + } + } + + return NV_FALSE; +} + +static void +vgpuRcErrorRecovery +( + OBJGPU *pGpu, + NvU32 chID, + NvU32 exceptType, + RM_ENGINE_TYPE rmEngineType +) +{ + CHID_MGR *pChidMgr = NULL; + KernelChannel *pKernelChannel; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NV_STATUS status = NV_OK; + FIFO_MMU_EXCEPTION_DATA mmuExceptionData = {0}; + + status = kfifoGetChidMgrFromType(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, + (NvU32)rmEngineType, &pChidMgr); + NV_ASSERT_OR_RETURN_VOID(status == NV_OK); + + pKernelChannel = kfifoChidMgrGetKernelChannel(pGpu, pKernelFifo, pChidMgr, + chID); + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, pKernelChannel != NULL); + + // + // In case of SRIOV, the notifier is updated before invoking the RPC for RC + // in case of an MMU fault. So skip notifying here if the exception type is + // 31 and SRIOV is enabled + // + if (exceptType != ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT || + (exceptType == ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT && + IS_VIRTUAL_WITHOUT_SRIOV(pGpu))) + { + // send the error notifier to clients + krcErrorSetNotifier(pGpu, GPU_GET_KERNEL_RC(pGpu), + pKernelChannel, + exceptType, + rmEngineType, + RC_NOTIFIER_SCOPE_TSG); + } + + // call back to KMD in case win7 + krcErrorInvokeCallback(pGpu, GPU_GET_KERNEL_RC(pGpu), + pKernelChannel, + &mmuExceptionData, + exceptType, + ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_FATAL, + rmEngineType, + INVALID_RCDB_RCDIAG_INDEX); +} + +void vgpuServiceEventGuestAllocated(OBJGPU *pGpu, OBJVGPU *pVGpu, VGPU_EVENT_BUF_ENTRY *pEventEntry) +{ + NV_STATUS status = NV_OK; + PEVENTNOTIFICATION *ppEventNotification; + NvHandle hClient = pEventEntry->hClient; + NvHandle hObject = pEventEntry->hObject; + NvU32 notifyIdx = pEventEntry->notifyIndex; + + // Find the PEVENTNOTIFICATION list of this object + status = CliGetEventNotificationList(hClient, hObject, NULL, &ppEventNotification); + if (status == NV_OK) + { + // Wake up all clients registered to listen for this event + notifyEvents(pGpu, *ppEventNotification, + notifyIdx, 0, 0, + NV_OK, NV_OS_WRITE_THEN_AWAKEN); + } +} + +void vgpuServiceEventRC(OBJGPU *pGpu, OBJVGPU *pVGpu, VGPU_EVENT_BUF_ENTRY *pEventEntry) +{ + NV_STATUS status = NV_OK; + NvHandle hClient = pEventEntry->hClient; + NvHandle hObject = pEventEntry->hObject; + NvU32 exceptType = pEventEntry->info32; + NvU32 nv2080EngineID = pEventEntry->info16 & DRF_SHIFTMASK(NV_VGPU_EV_NOTIFIER_INFO16_VALUE); + NvU32 chID = pEventEntry->rcChid; + RM_ENGINE_TYPE rmEngineType = gpuGetRmEngineType(nv2080EngineID); + + NV_PRINTF(LEVEL_ERROR, + "ROBUST_CHANNEL error occurred (hClient = 0x%x hFifo = 0x%x chID = %d exceptType = %d engineID = 0x%x (0x%x)) ...\n", + hClient, hObject, chID, exceptType, nv2080EngineID, rmEngineType); + + if (IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + RsClient *pClient = NULL; + Device *pDevice = NULL; + MIG_INSTANCE_REF ref; + + NV_ASSERT_OK_OR_ELSE(status, + serverGetClientUnderLock(&g_resServ, hClient, &pClient), return); + + NV_ASSERT_OK_OR_ELSE(status, + deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice), return); + + NV_ASSERT_OK_OR_ELSE(status, + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref), + return); + + NV_ASSERT_OK_OR_ELSE(status, + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, + rmEngineType, &rmEngineType), + return); + } + + vgpuRcErrorRecovery(pGpu, chID, exceptType, rmEngineType); +} + +void vgpuServiceEventVnc(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status = NV_OK; + + pVGpu->bVncConnected = !!(*(NvU32 *)(pVGpu->shared_memory + + (NV_VGPU_SHARED_MEMORY_POINTER_VNC / sizeof(NvU32)))); + + if (pVGpu->bVncConnected) + { + + /* Set surface property without comparison with cached, when console vnc connects */ + NV_RM_RPC_SET_SURFACE_PROPERTIES(pGpu, pVGpu->last_surface_info.hClient, + &(pVGpu->last_surface_info.last_surface), NV_TRUE, status); + if (status != NV_OK) { + NV_PRINTF(LEVEL_ERROR, + "SET_SURFACE_PROPERTY RPC failed with error : 0x%x\n", + status); + } + } +} + +void vgpuServiceEventPstate(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status = NV_OK; + NvU32 *pCurrPstate; + + pCurrPstate = (pVGpu->shared_memory + (NV_VGPU_SHARED_MEMORY_POINTER_CURRENT_PSTATE / sizeof(NvU32))); + + //Schedule OS workitem to call pstate change notifier + status = osQueueWorkItemWithFlags(pGpu, + _rmPstateEventCallback, + (void *)pCurrPstate, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW | + OS_QUEUE_WORKITEM_FLAGS_DONT_FREE_PARAMS); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to schedule Pstate callback! 0x%x\n", + status); + } +} + +void vgpuServiceEventEcc(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NvU32 ecc_type = * (NvU32 *)(pVGpu->shared_memory + (NV_VGPU_SHARED_MEMORY_POINTER_ECC_TYPE / sizeof(NvU32))); + NvU32 ecc_count = * (NvU32 *)(pVGpu->shared_memory + (NV_VGPU_SHARED_MEMORY_POINTER_ECC_ERROR_COUNT / sizeof(NvU32))); + NvU32 ecc_unit = * (NvU32 *)(pVGpu->shared_memory + (NV_VGPU_SHARED_MEMORY_POINTER_ECC_UNIT / sizeof(NvU32))); + + if (ecc_unit < NV2080_CTRL_GPU_ECC_UNIT_COUNT) + { + if (ecc_type == NV2080_NOTIFIERS_ECC_SBE) + { + pVSI->eccStatus.units[ecc_unit].sbe.count += ecc_count; + pVSI->eccStatus.units[ecc_unit].sbeNonResettable.count += ecc_count; + } + else + { + pVSI->eccStatus.units[ecc_unit].dbe.count += ecc_count; + pVSI->eccStatus.units[ecc_unit].dbeNonResettable.count += ecc_count; + } + + } + + if (gpuIsGlobalPoisonFuseEnabled(pGpu)) + { + pVSI->eccStatus.bFatalPoisonError = !!(* (NvU32 *)(pVGpu->shared_memory + + (NV_VGPU_SHARED_MEMORY_POINTER_ECC_POISON_ERROR / sizeof(NvU32)))); + } + + if (ecc_count) + { + + gpuNotifySubDeviceEvent(pGpu, ecc_type, NULL, 0, + (NvV32) ecc_count, (NvV16) ecc_unit); + } +} + +void vgpuServiceEventNvencReportingState(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + pGpu->encSessionStatsReportingState = + (*(NvU32 *)(pVGpu->shared_memory + (NV_VGPU_SHARED_MEMORY_POINTER_NVENC_STATS_REPORTING_STATE / sizeof(NvU32)))); +} + +void vgpuServiceEventInbandResponse(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + NV_STATUS status = NV_OK; + + OBJRPC * pRpc = GPU_GET_RPC(pGpu); + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pData = NULL; + NvBool more = NV_TRUE; + + if (!pVGpu->bGspPlugin) + return; + + while (more) + { + NvU32 inband_resp_state = (*(volatile NvU32 *)(pVGpu->shared_memory + + (NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE / sizeof(NvU32)))); + + if (inband_resp_state == NV_VGPU_SHARED_MEMORY_POINTER_NVLINK_INBAND_RESPONSE_NONE) + { + break; + } + if (pData == NULL) + { + pData = portMemAllocNonPaged(sizeof(*pData)); + } + portMemSet(pData, 0, sizeof(*pData)); + + if (FLD_TEST_DRF(_VGPU_SHARED_MEMORY_POINTER, _NVLINK_INBAND_RESPONSE, _PROBE, _PENDING, inband_resp_state)) + { + status = rpcCtrlNvlinkGetInbandReceivedData_HAL(pGpu, pRpc, pData, + NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP, &more); + if (status != NV_OK) + goto cleanup; + + status = knvlinkInbandMsgCallbackDispatcher(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), + sizeof(*pData), (void*)pData); + if (status != NV_OK) + goto cleanup; + + break; + } + if (FLD_TEST_DRF(_VGPU_SHARED_MEMORY_POINTER, _NVLINK_INBAND_RESPONSE, _MC_SETUP, _PENDING, inband_resp_state)) + { + /*TODO: add multicast support here.*/ + break; + } + break; + } +cleanup: + if (pData != NULL) + portMemFree(pData); +} + +void vgpuServiceEvents(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + VGPU_EVENT_BUF_ENTRY *pEventEntry; + NvU32 flags; + + pVGpu->eventRing.get = _readEventBufGet(pGpu, pVGpu); + pVGpu->eventRing.put = _readEventBufPut(pGpu, pVGpu); + + // process all pending events + while (pVGpu->eventRing.get != pVGpu->eventRing.put) + { + pEventEntry = ((VGPU_EVENT_BUF_ENTRY*) pVGpu->eventRing.mem.pMemory) + pVGpu->eventRing.get; + + flags = pEventEntry->flags; + + if (FLD_TEST_DRF(_VGPU, _EV_FLAGS, _ALLOCATED, _GUEST, flags)) + { + vgpuServiceEventGuestAllocated(pGpu, pVGpu, pEventEntry); + } + else if (FLD_TEST_DRF(_VGPU, _EV_FLAGS, _ALLOCATED, _PLUGIN, flags)) + { + // Plugin allocated events may/may not have guest-side equivalents + switch (DRF_VAL(_VGPU, _EV_FLAGS, _TYPE, flags)) + { + case NV_VGPU_EV_FLAGS_TYPE_ROBUST_CHANNEL_ERROR: + vgpuServiceEventRC(pGpu, pVGpu, pEventEntry); + break; + + case NV_VGPU_EV_FLAGS_TYPE_VNC: + vgpuServiceEventVnc(pGpu, pVGpu); + break; + + case NV_VGPU_EV_FLAGS_TYPE_PSTATE: + vgpuServiceEventPstate(pGpu, pVGpu); + break; + + case NV_VGPU_EV_FLAGS_TYPE_ECC: + vgpuServiceEventEcc(pGpu, pVGpu); + break; + + case NV_VGPU_EV_FLAGS_TYPE_NVENC_REPORTING_STATE: + vgpuServiceEventNvencReportingState(pGpu, pVGpu); + break; + + case NV_VGPU_EV_FLAGS_TYPE_INBAND_RESPONSE: + vgpuServiceEventInbandResponse(pGpu, pVGpu); + break; + + default: + NV_PRINTF(LEVEL_ERROR, "Unsupported vgpu event type %d\n", + DRF_VAL(_VGPU, _EV_FLAGS, _TYPE, flags)); + break; + } + } + + // update the get/put pointers + pVGpu->eventRing.get = (pVGpu->eventRing.get + 1) % VGPU_EVENT_BUF_ENTRY_COUNT; + _writeEventBufGet(pGpu, pVGpu, pVGpu->eventRing.get); + pVGpu->eventRing.put = _readEventBufPut(pGpu, pVGpu); + } +} + +void vgpuServiceGspPlugin(OBJGPU *pGpu, OBJVGPU *pVGpu) +{ + vgpuServiceEvents(pGpu, pVGpu); +} + +// Service a VGPU event (bottom half/DPC) +void vgpuService(OBJGPU *pGpu) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + if (pVGpu->bGspPlugin) + vgpuServiceGspPlugin(pGpu, pVGpu); +} + +/* + * Workitem callback for pstate change event + * + * To run at PASSIVE_LEVEL, we queue a workitem for + * gpuNotifySubDeviceEvent(). + * So this callback will notify all the guest rmclients + * registered for NV2080_NOTIFIERS_PSTATE_CHANGE event. + */ +static void +_rmPstateEventCallback +( + NvU32 gpuInstance, + void *pCurrPstate +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + NvU64 startTime = 0; + NvU32 currPstate = *(NvU32 *)pCurrPstate; + Nv2080PStateChangeNotification pstateParams; + + tmrGetCurrentTime(pTmr, &startTime); + + if (FULL_GPU_SANITY_CHECK(pGpu)) + { + pstateParams.timeStamp.nanoseconds[0] = NvU64_HI32(startTime); + pstateParams.timeStamp.nanoseconds[1] = NvU64_LO32(startTime); + pstateParams.NewPstate = currPstate; + + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_PSTATE_CHANGE, + &pstateParams, sizeof(pstateParams), currPstate, 0); + } + else + { + NV_PRINTF(LEVEL_ERROR, + "GPU sanity check failed! gpuInstance = 0x%x.\n", + gpuInstance); + } +} diff --git a/src/nvidia/kernel/vgpu/nv/vgpu_util.c b/src/nvidia/kernel/vgpu/nv/vgpu_util.c new file mode 100644 index 0000000000..c9a94b966c --- /dev/null +++ b/src/nvidia/kernel/vgpu/nv/vgpu_util.c @@ -0,0 +1,452 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +//****************************************************************************** +// +// Description: +// Various vgpu utility functions. +// +//****************************************************************************** + +#include "core/core.h" +#include "os/os.h" +#include "gpu/gpu.h" +#include "gpu/device/device.h" +#include "vgpu/dev_vgpu.h" +#include "vgpu/vgpu_events.h" +#include "vgpu/vgpu_util.h" +#include "gpu/mem_mgr/virt_mem_allocator.h" +#include "vgpu/rpc.h" +#include "core/system.h" +#include "gpu/mem_mgr/mem_desc.h" + +#include "gpu/bus/kern_bus.h" + +/*! + * @brief Function to free memorry associated with sysmem PFN bitmap node. + */ +void vgpuFreeSysmemPfnBitMapNode(VGPU_SYSMEM_PFN_BITMAP_NODE_P node) +{ + if (node) + { + if (node->sysmemPfnMap && node->pMemDesc_sysmemPfnMap) + memdescUnmapOld(node->pMemDesc_sysmemPfnMap, + memdescGetFlag(node->pMemDesc_sysmemPfnMap, MEMDESC_FLAGS_KERNEL_MODE), + osGetCurrentProcess(), + (void *)node->sysmemPfnMap, + (void *)node->sysmemPfnMap_priv); + + if ((node->pMemDesc_sysmemPfnMap) && (node->pMemDesc_sysmemPfnMap->Allocated)) + memdescFree(node->pMemDesc_sysmemPfnMap); + + memdescDestroy(node->pMemDesc_sysmemPfnMap); + + portMemFree(node); + } +} + +NvU64 vgpuGspSysmemPfnMakeBufferAddress(MEMORY_DESCRIPTOR *pMemDesc, NvU64 pfn) +{ + NV_ADDRESS_SPACE addressSpace = memdescGetAddressSpace(pMemDesc); + NvU64 pfnBufferAddr = REF_DEF64(VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_VALIDITY, _VALID) | + REF_NUM64(VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_PFN, pfn); + switch (addressSpace) + { + case ADDR_SYSMEM: + pfnBufferAddr |= REF_DEF64(VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_APERTURE, _SYSMEM); + break; + default: + NV_PRINTF(LEVEL_ERROR, "Dirty sysmem pfn: Invlid address space %d\n", addressSpace); + pfnBufferAddr = VGPU_GSP_SYSMEM_PFN_BITMAP_BUF_ADDR_VALIDITY_INVALID; + break; + + } + return pfnBufferAddr; +} + +/*! + * @brief Function to alloc sysmem PFN bitmap node. + * + * Sysmem PFN bitmap node is allocated either during RPC infrastructure + * initialization or while expanding the sysmem PFN bitmap list. + * This function is responsible for allocting the node, writing the pfns in the + * sysmem PFN ring page to facilitate the plugin to access the bitmap PFNs and + * asking the plugin to map the bitmap pages by writing to emulated NV_VGPU_SYSMEM_BITMAP + * bar0 register. + * + * @param[in] pGpu OBJGPU *object pointer + * @param[in] node VGPU_SYSMEM_PFN_BITMAP_NODE pointer + * @param[in] index Index assigned to the node when it is added to linked list + */ +NV_STATUS vgpuAllocSysmemPfnBitMapNode(OBJGPU *pGpu, VGPU_SYSMEM_PFN_BITMAP_NODE_P *node, NvU32 index) +{ + NV_STATUS status = NV_OK; + NvU64 pfn; + NvU64 *dest; + NvU32 i; + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + VGPU_GSP_SYSMEM_BITMAP_ROOT_NODE *sysmemBitmapRootNode = NULL; + NvU32 memFlags = 0; + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + memFlags = MEMDESC_FLAGS_CPU_ONLY; + + if (index != listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)) || + node == NULL) { + status = NV_ERR_INVALID_ARGUMENT; + NV_PRINTF(LEVEL_ERROR, + "Invalid argumets passed while allocating sysmem pfn bitmap node \n"); + return status; + } + + *node = portMemAllocNonPaged(sizeof(VGPU_SYSMEM_PFN_BITMAP_NODE)); + if (*node == NULL) { + status = NV_ERR_NO_MEMORY; + NV_PRINTF(LEVEL_ERROR, + "failed to allocate memory for sysmem pfn bitmap node \n"); + return status; + } + + portMemSet(*node, 0, sizeof(VGPU_SYSMEM_PFN_BITMAP_NODE)); + + (*node)->pMemDesc_sysmemPfnMap = NULL; + (*node)->sysmemPfnMap = NULL; + (*node)->sysmemPfnMap_priv = NULL; + (*node)->nodeStartPfn = index * MAX_PFNS_PER_SYSMEM_BITMAP_NODE; + (*node)->nodeEndPfn = (index + 1) * MAX_PFNS_PER_SYSMEM_BITMAP_NODE; + (*node)->index = index; + + if (pVGpu->bGspPlugin) + { + // Allocate an extra 4K memory to hold pfn data of level 2 table entries. + (*node)->sizeInBytes = (MAX_PFNS_PER_SYSMEM_BITMAP_NODE / 8) + + RM_PAGE_SIZE; + } else { + (*node)->sizeInBytes = MAX_PFNS_PER_SYSMEM_BITMAP_NODE / 8; + } + + status = memdescCreate(&((*node)->pMemDesc_sysmemPfnMap), pGpu, + (*node)->sizeInBytes, + 0, + NV_MEMORY_NONCONTIGUOUS, + ADDR_SYSMEM, + NV_MEMORY_CACHED, + memFlags); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Cannot alloc memory descriptor for sysmem pfn bitmap node (size = 0x%llx)\n", + (*node)->sizeInBytes); + goto done; + } + + memdescSetFlag((*node)->pMemDesc_sysmemPfnMap, MEMDESC_FLAGS_KERNEL_MODE, NV_TRUE); + + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_88, + (*node)->pMemDesc_sysmemPfnMap); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Cannot alloc sysmem pfn bitmap node buffer\n"); + goto done; + } + + status = memdescMapOld((*node)->pMemDesc_sysmemPfnMap, + 0, // Offset + (*node)->sizeInBytes, + memdescGetFlag((*node)->pMemDesc_sysmemPfnMap, MEMDESC_FLAGS_KERNEL_MODE), + NV_PROTECT_READ_WRITE, + (void **)&((*node)->sysmemPfnMap), + (void **)&((*node)->sysmemPfnMap_priv)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Cannot map sysmem pfn bitmap node buffer (size = 0x%llx)\n", + (*node)->sizeInBytes); + goto done; + } + + if (pVGpu->bGspPlugin) + { + dest = (*node)->sysmemPfnMap + ((MAX_PFNS_PER_SYSMEM_BITMAP_NODE / 8) / sizeof(NvU64)); + } + else + { + dest = vgpuSysmemPfnInfo.sysmemPfnRing; + } + + for (i = 0; i < MAX_PFNS_PER_4K_PAGE; i++) + { + pfn = (memdescGetPte((*node)->pMemDesc_sysmemPfnMap, AT_GPU, i) >> (NvU32) RM_PAGE_SHIFT); + // writing the pfns in the ring page to facilitate the plugin to access the sysmem pfn map + dest[i] = pfn; + } + + if (pVGpu->bGspPlugin) + { + sysmemBitmapRootNode = (VGPU_GSP_SYSMEM_BITMAP_ROOT_NODE *)vgpuSysmemPfnInfo.sysmemPfnRing; + if (index < (MAX_PFNS_PER_4K_PAGE - 1)) + { + sysmemBitmapRootNode->nodePfns[index] = + vgpuGspSysmemPfnMakeBufferAddress((*node)->pMemDesc_sysmemPfnMap, + (memdescGetPte((*node)->pMemDesc_sysmemPfnMap, + AT_GPU, MAX_PFNS_PER_4K_PAGE) >> (NvU32) RM_PAGE_SHIFT)); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Exhausted limit of dirty sysmem tracking. Migration will not work correctly.\n"); + NV_ASSERT(0); + } + sysmemBitmapRootNode->nodeCount = index + 1; + } + + // Add pointer to the node in bitmapNodes array at input index for faster lookups + vgpuSysmemPfnInfo.bitmapNodes[index] = *node; + +done: + if (status != NV_OK) + { + vgpuFreeSysmemPfnBitMapNode(*node); + } + + return status; +} + +/*! + * @brief Function to expand sysmem PFN bitmap list based on input pfn + * + * Each sysmem PFN bitmap node represets the bitmap of 64GB sysmem block. + * Whenever we encouter a PFN which goes beyond the max tracked PFN, sysmem PFN + * bitmap list is expanded to track the new PFN. + * This function is responsible for adding the VGPU_SYSMEM_PFN_BITMAP_NODE nodes + * to the list until input PFN can be tracked and also reallocating the refcount + * buffer to accomodate the new sysmem PFN. + * + * @param[in] pGpu OBJGPU *object pointer + * @param[in] pfn New sysmem PFN not being tracked + */ +static NV_STATUS vgpuExpandSysmemPfnBitMapList(OBJGPU *pGpu, NvU64 pfn) +{ + NV_STATUS status = NV_OK; + VGPU_SYSMEM_PFN_BITMAP_NODE_P node = NULL; + VGPU_SYSMEM_PFN_BITMAP_NODE_P nodeNext = NULL; + NvU16 *temp_pfn_ref_count = NULL; + NvU64 old_max_pfn = vgpuSysmemPfnInfo.guestMaxPfn; + + do + { + node = NULL; + + // Add a new bitmap node to track allocations in subsequent 64GB PA space. + status = vgpuAllocSysmemPfnBitMapNode(pGpu, &node, + listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead))); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to alloc sysmem pfn bitmap node\n"); + goto done; + } + + listAppendExisting(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead), node); + + vgpuSysmemPfnInfo.guestMaxPfn = node->nodeEndPfn; + vgpuSysmemPfnInfo.sizeInBytes = vgpuSysmemPfnInfo.guestMaxPfn / 8; + + } while (vgpuSysmemPfnInfo.guestMaxPfn < pfn); + + // Alloc the ref count buffer + temp_pfn_ref_count = portMemAllocNonPaged(sizeof(NvU16) * vgpuSysmemPfnInfo.guestMaxPfn); + if (temp_pfn_ref_count == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to allocate sysmem pfn refcount array\n"); + NV_ASSERT(0); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto done; + } + portMemSet(temp_pfn_ref_count, 0, sizeof(NvU16) * vgpuSysmemPfnInfo.guestMaxPfn); + + // copy old ref count memory to new + portMemCopy(NvP64_VALUE(temp_pfn_ref_count), + (sizeof(NvU16) * vgpuSysmemPfnInfo.guestMaxPfn), + NvP64_VALUE(vgpuSysmemPfnInfo.sysmemPfnRefCount), + (sizeof(NvU16) * old_max_pfn)); + + portMemFree(vgpuSysmemPfnInfo.sysmemPfnRefCount); + vgpuSysmemPfnInfo.sysmemPfnRefCount = temp_pfn_ref_count; + +done: + if (status != NV_OK) + { + + portMemFree(vgpuSysmemPfnInfo.sysmemPfnRefCount); + + for (node = listHead(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)); + node != NULL; + node = nodeNext) + { + nodeNext = listNext(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead), node); + listRemove(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead), node); + vgpuFreeSysmemPfnBitMapNode(node); + } + } + + return status; +} + +/*! + * @brief Helper function to update sysmem PFN bitmap based on input pfn + * + * Each sysmem PFN bitmap node represets the bitmap of 64GB sysmem block. + * This function is responsible for identifying the the VGPU_SYSMEM_PFN_BITMAP_NODE node + * based on input PFN and then set/clear the corresponding bit based on whether it is + * allocation request or free. + * + * @param[in] pfn sysmem PFN corrsponding to which bitmap needs to be updated + * @param[in] bAlloc to identify is bit correspond to PFN needs to be set/cleared + */ +static NV_STATUS _updateSysmemPfnBitMap +( + NvU64 pfn, + NvBool bAlloc +) +{ + NV_STATUS status = NV_OK; + NvU32 mapIndex, bitIndex; + NvU64 bits; + NvU32 bitmapNodeIndex, nodeBitIndex; + VGPU_SYSMEM_PFN_BITMAP_NODE_P node = NULL; + + bitmapNodeIndex = pfn / MAX_PFNS_PER_SYSMEM_BITMAP_NODE; + nodeBitIndex = pfn % MAX_PFNS_PER_SYSMEM_BITMAP_NODE; + + if (bitmapNodeIndex < listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead))) + { + node = vgpuSysmemPfnInfo.bitmapNodes[bitmapNodeIndex]; + } + + if (node) + { + mapIndex = PAGE_MAPIDX64(nodeBitIndex); + bitIndex = PAGE_BITIDX64(nodeBitIndex); + + if (bAlloc) + { + bits = node->sysmemPfnMap[mapIndex]; + node->sysmemPfnMap[mapIndex] = SETBIT64(bits, bitIndex); + vgpuSysmemPfnInfo.sysmemPfnRefCount[pfn] += 1; + } + else + { + NV_CHECK(LEVEL_INFO, (vgpuSysmemPfnInfo.sysmemPfnRefCount[pfn] > 0)); + + if (vgpuSysmemPfnInfo.sysmemPfnRefCount[pfn] > 0) + { + vgpuSysmemPfnInfo.sysmemPfnRefCount[pfn] -= 1; + + if (vgpuSysmemPfnInfo.sysmemPfnRefCount[pfn] == 0) + { + bits = node->sysmemPfnMap[mapIndex]; + node->sysmemPfnMap[mapIndex] = CLEARBIT64(bits, bitIndex); + } + } + } + } + else + { + status = NV_ERR_OBJECT_NOT_FOUND; + } + + return status; +} + +/*! + * @brief Function to update sysmem PFN bitmap based on input pfn + * + * Sysmem PFN bitmap is updated whenever there is sysmem allocation or free. + * Whenever we encouter a PFN which goes beyond the max tracked PFN sysmem PFN + * bitmap list is expanded to track the new PFN. + * This function is responsible for updating the bitmap for the sysmem PFNs under + * the input memory desriptor and expanding the bitmap list if we encouter a PFN + * which goes beyond the max tracked PFN + * + * @param[in] pGpu OBJGPU *object pointer + * @param[in] pMemDesc Memory descriptor corresponding to the sysmem + * @param[in] bAlloc To identify if memory is being allocated or freed + */ +NV_STATUS vgpuUpdateSysmemPfnBitMap +( + OBJGPU *pGpu, + MEMORY_DESCRIPTOR *pMemDesc, + NvBool bAlloc +) +{ + NV_STATUS status = NV_OK; + NvU32 i; + NvU64 pfn; + + // Return early if sysmem dirty page tracking is disabled + if (!(pGpu->getProperty(pGpu, PDB_PROP_GPU_SRIOV_SYSMEM_DIRTY_PAGE_TRACKING_ENABLED))) + { + return NV_OK; + } + else + { + if (!vgpuSysmemPfnInfo.bSysmemPfnInfoInitialized) + return NV_OK; + } + + NV_ASSERT_OR_RETURN(listCount(&(vgpuSysmemPfnInfo.listVgpuSysmemPfnBitmapHead)) > 0, + NV_ERR_INVALID_OPERATION); + NV_ASSERT_OR_RETURN((vgpuSysmemPfnInfo.sysmemPfnRefCount != NULL), + NV_ERR_INVALID_OPERATION); + + for (i = 0; i < pMemDesc->PageCount; i++) + { + pfn = (memdescGetPte(pMemDesc, AT_CPU, i) >> RM_PAGE_SHIFT); + + if (bAlloc) + { + if (pfn > vgpuSysmemPfnInfo.guestMaxPfn) + { + status = vgpuExpandSysmemPfnBitMapList(pGpu, pfn); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Cannot re-allocate sysmem PFN bitmap :%x\n", + status); + return status; + } + } + } + + status = _updateSysmemPfnBitMap(pfn, bAlloc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Sysmem PFN bitmap update failed :%x\n", status); + return status; + } + } + + return status; +} + diff --git a/src/nvidia/kernel/vgpu/nv/vgpuapi.c b/src/nvidia/kernel/vgpu/nv/vgpuapi.c new file mode 100644 index 0000000000..615e5f6475 --- /dev/null +++ b/src/nvidia/kernel/vgpu/nv/vgpuapi.c @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "os/os.h" + +#include "vgpuapi.h" +#include "gpu/gpu.h" + +NV_STATUS +vgpuapiConstruct_IMPL +( + VgpuApi *pVgpuApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuApi); + NvHandle hDevice = pParams->hParent; + NvHandle hVgpu = pParams->hResource; + + // KEPLER_DEVICE_VGPU is only supported for virtaul GPU + if (!IS_VIRTUAL(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + pVgpuApi->handle = hVgpu; + pVgpuApi->hDevice = hDevice; + + pVgpuApi->node.Data = (void *)pVgpuApi; + pVgpuApi->node.keyStart = hVgpu; + pVgpuApi->node.keyEnd = hVgpu; + + return rmStatus; +} + +void +vgpuapiDestruct_IMPL +( + VgpuApi *pResource +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pResource); + CALL_CONTEXT *pCallContext; + RS_RES_FREE_PARAMS_INTERNAL *pParams; + + resGetFreeParams(staticCast(pResource, RsResource), &pCallContext, &pParams); + + // KEPLER_DEVICE_VGPU is only supported for virtual GPU + if (!IS_VIRTUAL(pGpu)) + { + pParams->status = NV_ERR_NOT_SUPPORTED; + return; + } + + pParams->status = NV_OK; +} + diff --git a/src/nvidia/kernel/vgpu/nv/vgpuctrl.c b/src/nvidia/kernel/vgpu/nv/vgpuctrl.c new file mode 100644 index 0000000000..caef4798ed --- /dev/null +++ b/src/nvidia/kernel/vgpu/nv/vgpuctrl.c @@ -0,0 +1,132 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/system.h" +#include "core/locks.h" +#include "os/os.h" +#include "gpu/device/device.h" +#include "rmapi/control.h" +#include "vgpu/rpc.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "vgpu/vgpu_events.h" + +#include "vgpuapi.h" + +NV_STATUS +vgpuapiCtrlCmdVgpuDisplaySetSurfaceProperties_IMPL +( + VgpuApi *pVgpuApi, + NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuApi); + NV_STATUS rmStatus = NV_OK; + + // + // For RM-managed heaps, look up the memory object from the passed-in + // hMemory and overwrite the offset and surfaceKind fields. For + // externally-managed heaps, we just pass through these parameters from the + // client directly. + // + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL)) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + Memory *pMemory = NULL; + + NvU64 physOffset = 0; + NvU32 pageKind = 0; + // unused + NvU32 _memAperture, _comprOffset, _comprFormat; + NvU32 _lineMin, _lineMax, _zcullId, _gpuCacheAttr, _gpuP2PCacheAttr; + NvU64 _contigSegmentSize; + + // Find the allocation from the hMemory + rmStatus = memGetByHandle(RES_GET_CLIENT(pVgpuApi), pParams->hMemory, &pMemory); + if (rmStatus != NV_OK) + return rmStatus; + + // Verify the allocation is on the same GPU as this VGPU object + if (GPU_RES_GET_GPU(pMemory->pDevice) != pGpu) + return NV_ERR_INVALID_OBJECT_PARENT; + + // Verify the allocation is in video memory. + if (memdescGetAddressSpace(pMemory->pMemDesc) != ADDR_FBMEM) + { + return NV_ERR_INVALID_OBJECT; + } + + // Look up the page kind. + rmStatus = memmgrGetSurfacePhysAttr_HAL(pGpu, pMemoryManager, pMemory, + &physOffset, &_memAperture, &pageKind, + &_comprOffset, &_comprFormat, &_lineMin, &_lineMax, + &_zcullId, &_gpuCacheAttr, &_gpuP2PCacheAttr, + &_contigSegmentSize); + if (rmStatus != NV_OK) + return rmStatus; + + physOffset += pParams->offset; + if (physOffset > 0xffffffffull) + return NV_ERR_INVALID_OFFSET; + + pParams->offset = NvU64_LO32(physOffset); + pParams->surfaceKind = pageKind; + } + + NV_RM_RPC_SET_SURFACE_PROPERTIES(pGpu, RES_GET_CLIENT_HANDLE(pVgpuApi), + pParams, NV_FALSE, rmStatus); + + return rmStatus; +} + +NV_STATUS +vgpuapiCtrlCmdVgpuDisplayCleanupSurface_IMPL +( + VgpuApi *pVgpuApi, + NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuApi); + NV_STATUS rmStatus = NV_OK; + + NV_RM_RPC_CLEANUP_SURFACE(pGpu, pParams, rmStatus); + + return rmStatus; +} + +NV_STATUS +vgpuapiCtrlCmdVGpuGetConfig_IMPL +( + VgpuApi *pVgpuApi, + NVA080_CTRL_VGPU_GET_CONFIG_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuApi); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_STATUS rmStatus = NV_OK; + + if (pVSI != NULL) + portMemCopy(pParams, sizeof(pVSI->vgpuConfig), &pVSI->vgpuConfig, sizeof(pVSI->vgpuConfig)); + + return rmStatus; +} + diff --git a/src/nvidia/src/kernel/compute/fabric.c b/src/nvidia/src/kernel/compute/fabric.c index 84c3f33373..dbbd08e76c 100644 --- a/src/nvidia/src/kernel/compute/fabric.c +++ b/src/nvidia/src/kernel/compute/fabric.c @@ -25,6 +25,7 @@ * @file * @brief This file contains the functions managing the NVLink fabric */ +#define NVOC_FABRIC_H_PRIVATE_ACCESS_ALLOWED #include "os/os.h" #include "compute/fabric.h" @@ -140,48 +141,549 @@ _fabricCacheFind } void -fabricMulticastFabricOpsMutexAcquire_IMPL +fabricWakeUpThreadCallback +( + void *pData +) +{ + osWakeUp((OS_WAIT_QUEUE*)pData); +} + +static NvBool +_fabricCacheInvokeCallback +( + FabricCache *pCache, + NvU64 key1, + NvU64 key2, + NvU64 key3, + void (*pCb)(void *pData) +) +{ + FabricCacheMapEntry *pMapEntry; + + pMapEntry = _fabricCacheFind(pCache, key1, key2, key3); + if (pMapEntry == NULL) + return NV_FALSE; + + (*pCb)(pMapEntry->pData); + + return NV_TRUE; +} + +static void +_fabricWaitOnUnimportCallback +( + void *pCbData +) +{ + NvU64 unimportEventId = (NvU64)pCbData; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + OS_WAIT_QUEUE *pWq; + + if ((pWq = fabricUnimportCacheGet(pFabric, unimportEventId)) != NULL) + { + osWaitInterruptible(pWq); + fabricUnimportCacheDelete(pFabric, unimportEventId); + osFreeWaitQueue(pWq); + } +} + +static void +_fabricUnsetUnimportCallback +( + NV00F1_CTRL_FABRIC_EVENT *pEvent +) +{ + THREAD_STATE_NODE *pThreadNode; + THREAD_STATE_FREE_CALLBACK callback; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + OS_WAIT_QUEUE *pWq; + NV_STATUS status; + + // Nothing to do + if (pEvent->type != NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_UNIMPORT) + return; + + status = threadStateGetCurrent(&pThreadNode, NULL); + NV_ASSERT_OR_RETURN_VOID(status == NV_OK); + + callback.pCb = _fabricWaitOnUnimportCallback; + callback.pCbData = (void*)pEvent->id; + + threadStateRemoveCallbackOnFree(pThreadNode, &callback); + + pWq = fabricUnimportCacheGet(pFabric, pEvent->id); + if (pWq != NULL) + { + fabricUnimportCacheDelete(pFabric, pEvent->id); + osFreeWaitQueue(pWq); + } +} + +static NV_STATUS +_fabricSetUnimportCallback +( + NV00F1_CTRL_FABRIC_EVENT *pEvent +) +{ + THREAD_STATE_NODE *pThreadNode = NULL; + THREAD_STATE_FREE_CALLBACK callback; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status; + OS_WAIT_QUEUE *pWq = NULL; + + // Nothing to do + if (pEvent->type != NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_UNIMPORT) + return NV_OK; + + status = threadStateGetCurrent(&pThreadNode, NULL); + if (status != NV_OK) + return status; + + callback.pCb = _fabricWaitOnUnimportCallback; + callback.pCbData = (void*)pEvent->id; + + status = osAllocWaitQueue(&pWq); + if (status != NV_OK) + return status; + + status = fabricUnimportCacheInsert(pFabric, pEvent->id, pWq); + if (status != NV_OK) + goto fail; + + status = threadStateEnqueueCallbackOnFree(pThreadNode, &callback); + if (status != NV_OK) + goto fail; + + return NV_OK; + +fail: + fabricUnimportCacheDelete(pFabric, pEvent->id); + + if (pWq != NULL) + osFreeWaitQueue(pWq); + + return status; +} + +static NV_STATUS +_fabricNotifyEvent(Fabric *pFabric) +{ + if (pFabric->pOsImexEvent == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Unable to notify ImexSessionApi\n"); + return NV_ERR_NOT_READY; + } + + osSetEvent(NULL, pFabric->pOsImexEvent); + + return NV_OK; +} + +NV_STATUS +fabricSetImexEvent_IMPL +( + Fabric *pFabric, + NvP64 pOsEvent +) +{ + // + // RS-TODO: Thread-safety of the cached pOsImexEvent is + // guaranteed by the RMAPI lock. If the semantics of the RMAPI + // lock change in the future then we would need to revisit this. + // + if ((pOsEvent != NULL) && (pFabric->pOsImexEvent != NULL)) + return NV_ERR_IN_USE; + + pFabric->pOsImexEvent = pOsEvent; + + return NV_OK; +} + +NvP64 +fabricGetImexEvent_IMPL ( Fabric *pFabric ) { - portSyncMutexAcquire(pFabric->pMulticastFabricOpsMutex); + return pFabric->pOsImexEvent; +} + +void +fabricSetNodeId_IMPL +( + Fabric *pFabric, + NvU16 nodeId +) +{ + pFabric->nodeId = nodeId; +} + +NvU16 +fabricGetNodeId_IMPL +( + Fabric *pFabric +) +{ + return pFabric->nodeId; +} + +NV_STATUS +fabricPostEventsV2_IMPL +( + Fabric *pFabric, + NV00F1_CTRL_FABRIC_EVENT *pEvents, + NvU32 numEvents +) +{ + NV_STATUS status = NV_OK; + NV00F1_CTRL_FABRIC_EVENT *pNode; + NvU32 i, j; + + if (numEvents == 0) + return NV_OK; + + portSyncRwLockAcquireWrite(pFabric->pListLock); + + for (i = 0; i < numEvents; i++) + { + pNode = listAppendNew(&pFabric->fabricEventListV2); + if (pNode == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + status = _fabricSetUnimportCallback(&pEvents[i]); + if (status != NV_OK) + goto done; + + portMemCopy(pNode, sizeof(*pNode), &pEvents[i], sizeof(pEvents[i])); + } + + status = _fabricNotifyEvent(pFabric); + +done: + if (status != NV_OK) + { + for (j = 0; j < i; j++) + { + pNode = listTail(&pFabric->fabricEventListV2); + _fabricUnsetUnimportCallback(pNode); + listRemove(&pFabric->fabricEventListV2, pNode); + } + } + + portSyncRwLockReleaseWrite(pFabric->pListLock); + return status; +} + +NvBool +fabricExtractEventsV2_IMPL +( + Fabric *pFabric, + NV00F1_CTRL_FABRIC_EVENT *pEventArray, + NvU32 *pNumEvents +) +{ + NV00F1_CTRL_FABRIC_EVENT *pEvent; + NvU32 count = 0; + NvBool bMoreEvents; + + portSyncRwLockAcquireWrite(pFabric->pListLock); + + while ((count < *pNumEvents) && + ((pEvent = listHead(&pFabric->fabricEventListV2)) != NULL)) + { + portMemCopy(&pEventArray[count], sizeof(*pEvent), + pEvent, sizeof(*pEvent)); + + listRemove(&pFabric->fabricEventListV2, pEvent); + + count++; + } + + *pNumEvents = count; + + bMoreEvents = listCount(&pFabric->fabricEventListV2) > 0; + + portSyncRwLockReleaseWrite(pFabric->pListLock); + + return bMoreEvents; +} + +void +fabricFlushUnhandledEvents_IMPL +( + Fabric *pFabric +) +{ + void *pEvent; + + portSyncRwLockAcquireWrite(pFabric->pListLock); + + while ((pEvent = listHead(&pFabric->fabricEventListV2)) != NULL) + listRemove(&pFabric->fabricEventListV2, pEvent); + + portSyncRwLockReleaseWrite(pFabric->pListLock); +} + +NvU64 +fabricGenerateEventId_IMPL +( + Fabric *pFabric +) +{ + return portAtomicExIncrementU64(&pFabric->eventId); +} + +static void +_fabricCacheIterateAll +( + FabricCache *pCache, + void (*pCb)(void *pData) +) +{ + FabricCacheIter mmIter; + FabricCacheEntry *pEntry; + FabricCacheMapIter mIter; + FabricCacheMapEntry *pMapEntry; + + mmIter = multimapItemIterAll(pCache); + + while (multimapItemIterNext(&mmIter)) + { + pEntry = mmIter.pValue; + mIter = mapIterAll(&pEntry->map); + + while (mapIterNext(&mIter)) + { + pMapEntry = mIter.pValue; + (*pCb)(pMapEntry->pData); + } + } +} + +static void +_fabricCacheClearAll +( + FabricCache *pCache +) +{ + FabricCacheIter mmIter; + FabricCacheEntry *pEntry; + + mmIter = multimapItemIterAll(pCache); + + while (multimapItemIterNext(&mmIter)) + { + pEntry = mmIter.pValue; + mapClear(&pEntry->map); + } + + multimapClear(pCache); +} + +NV_STATUS +fabricImportCacheInsert_IMPL +( + Fabric *pFabric, + const NvUuid *pExportUuid, + NvU64 key, + void *pData +) +{ + NV_STATUS status; + + portSyncRwLockAcquireWrite(pFabric->pImportCacheLock); + + status = _fabricCacheInsert(&pFabric->importCache, + NV_UUID_HI(pExportUuid), + NV_UUID_LO(pExportUuid), + key, pData); + + portSyncRwLockReleaseWrite(pFabric->pImportCacheLock); + + return status; +} + +void +fabricImportCacheDelete_IMPL +( + Fabric *pFabric, + const NvUuid *pExportUuid, + NvU64 key +) +{ + portSyncRwLockAcquireWrite(pFabric->pImportCacheLock); + + _fabricCacheDelete(&pFabric->importCache, + NV_UUID_HI(pExportUuid), + NV_UUID_LO(pExportUuid), + key); + + portSyncRwLockReleaseWrite(pFabric->pImportCacheLock); } void -fabricMulticastFabricOpsMutexRelease_IMPL +fabricImportCacheClear_IMPL ( Fabric *pFabric ) { - portSyncMutexRelease(pFabric->pMulticastFabricOpsMutex); + portSyncRwLockAcquireWrite(pFabric->pImportCacheLock); + + _fabricCacheClearAll(&pFabric->importCache); + + portSyncRwLockReleaseWrite(pFabric->pImportCacheLock); +} + +void* +fabricImportCacheGet_IMPL +( + Fabric *pFabric, + const NvUuid *pExportUuid, + NvU64 key +) +{ + FabricCacheMapEntry *pMapEntry; + + portSyncRwLockAcquireRead(pFabric->pImportCacheLock); + + pMapEntry = _fabricCacheFind(&pFabric->importCache, + NV_UUID_HI(pExportUuid), + NV_UUID_LO(pExportUuid), + key); + + portSyncRwLockReleaseRead(pFabric->pImportCacheLock); + + return (pMapEntry == NULL ? NULL : pMapEntry->pData); } NV_STATUS -fabricMulticastSetupCacheInsertUnderLock_IMPL +fabricUnimportCacheInsert_IMPL +( + Fabric *pFabric, + NvU64 unimportEventId, + void *pData +) +{ + NV_STATUS status; + + portSyncRwLockAcquireWrite(pFabric->pUnimportCacheLock); + + status = _fabricCacheInsert(&pFabric->unimportCache, + unimportEventId, 0, 0, pData); + + portSyncRwLockReleaseWrite(pFabric->pUnimportCacheLock); + + return status; +} + +void +fabricUnimportCacheDelete_IMPL +( + Fabric *pFabric, + NvU64 unimportEventId +) +{ + portSyncRwLockAcquireWrite(pFabric->pUnimportCacheLock); + + _fabricCacheDelete(&pFabric->unimportCache, unimportEventId, 0, 0); + + portSyncRwLockReleaseWrite(pFabric->pUnimportCacheLock); +} + +void* +fabricUnimportCacheGet_IMPL +( + Fabric *pFabric, + NvU64 unimportEventId +) +{ + FabricCacheMapEntry *pMapEntry; + + portSyncRwLockAcquireRead(pFabric->pUnimportCacheLock); + + pMapEntry = _fabricCacheFind(&pFabric->unimportCache, + unimportEventId, 0, 0); + + portSyncRwLockReleaseRead(pFabric->pUnimportCacheLock); + + return (pMapEntry == NULL ? NULL : pMapEntry->pData); +} + +NvBool +fabricUnimportCacheInvokeCallback_IMPL +( + Fabric *pFabric, + NvU64 unimportEventId, + void (*pCb)(void *pData) +) +{ + NvBool result; + + portSyncRwLockAcquireWrite(pFabric->pUnimportCacheLock); + + result = _fabricCacheInvokeCallback(&pFabric->unimportCache, + unimportEventId, 0, 0, pCb); + + portSyncRwLockReleaseWrite(pFabric->pUnimportCacheLock); + + return result; +} + +void +fabricUnimportCacheIterateAll_IMPL +( + Fabric *pFabric, + void (*pCb)(void *pData) +) +{ + portSyncRwLockAcquireWrite(pFabric->pUnimportCacheLock); + + _fabricCacheIterateAll(&pFabric->unimportCache, pCb); + + portSyncRwLockReleaseWrite(pFabric->pUnimportCacheLock); +} + +NV_STATUS +fabricMulticastSetupCacheInsert_IMPL ( Fabric *pFabric, NvU64 requestId, void *pData ) { - return _fabricCacheInsert(&pFabric->fabricMulticastCache, - 0, requestId, 0, pData); + NV_STATUS status; + + portSyncRwLockAcquireWrite(pFabric->pMulticastFabriCacheLock); + + status = _fabricCacheInsert(&pFabric->fabricMulticastCache, + 0, requestId, 0, pData); + + portSyncRwLockReleaseWrite(pFabric->pMulticastFabriCacheLock); + + return status; } void -fabricMulticastSetupCacheDeleteUnderLock_IMPL +fabricMulticastSetupCacheDelete_IMPL ( Fabric *pFabric, NvU64 requestId ) { + portSyncRwLockAcquireWrite(pFabric->pMulticastFabriCacheLock); + _fabricCacheDelete(&pFabric->fabricMulticastCache, 0, requestId, 0); + + portSyncRwLockReleaseWrite(pFabric->pMulticastFabriCacheLock); } void* -fabricMulticastSetupCacheGetUnderLock_IMPL +fabricMulticastSetupCacheGet_IMPL ( Fabric *pFabric, NvU64 requestId @@ -189,37 +691,53 @@ fabricMulticastSetupCacheGetUnderLock_IMPL { FabricCacheMapEntry *pMapEntry; + portSyncRwLockAcquireRead(pFabric->pMulticastFabriCacheLock); + pMapEntry = _fabricCacheFind(&pFabric->fabricMulticastCache, 0, requestId, 0); + portSyncRwLockReleaseRead(pFabric->pMulticastFabriCacheLock); + return (pMapEntry == NULL ? NULL : pMapEntry->pData); } NV_STATUS -fabricMulticastCleanupCacheInsertUnderLock_IMPL +fabricMulticastCleanupCacheInsert_IMPL ( Fabric *pFabric, NvU64 requestId, void *pData ) { - return _fabricCacheInsert(&pFabric->fabricMulticastCache, - 1, requestId, 0, pData); + NV_STATUS status; + + portSyncRwLockAcquireWrite(pFabric->pMulticastFabriCacheLock); + + status = _fabricCacheInsert(&pFabric->fabricMulticastCache, + 1, requestId, 0, pData); + + portSyncRwLockReleaseWrite(pFabric->pMulticastFabriCacheLock); + + return status; } void -fabricMulticastCleanupCacheDeleteUnderLock_IMPL +fabricMulticastCleanupCacheDelete_IMPL ( Fabric *pFabric, NvU64 requestId ) { + portSyncRwLockAcquireWrite(pFabric->pMulticastFabriCacheLock); + _fabricCacheDelete(&pFabric->fabricMulticastCache, 1, requestId, 0); + + portSyncRwLockReleaseWrite(pFabric->pMulticastFabriCacheLock); } void* -fabricMulticastCleanupCacheGetUnderLock_IMPL +fabricMulticastCleanupCacheGet_IMPL ( Fabric *pFabric, NvU64 requestId @@ -227,12 +745,32 @@ fabricMulticastCleanupCacheGetUnderLock_IMPL { FabricCacheMapEntry *pMapEntry; + portSyncRwLockAcquireRead(pFabric->pMulticastFabriCacheLock); + pMapEntry = _fabricCacheFind(&pFabric->fabricMulticastCache, 1, requestId, 0); + portSyncRwLockReleaseRead(pFabric->pMulticastFabriCacheLock); + return (pMapEntry == NULL ? NULL : pMapEntry->pData); } +void +fabricMulticastCleanupCacheInvokeCallback_IMPL +( + Fabric *pFabric, + NvU64 requestId, + void (*pCb)(void *pData) +) +{ + portSyncRwLockAcquireWrite(pFabric->pMulticastFabriCacheLock); + + (void)_fabricCacheInvokeCallback(&pFabric->fabricMulticastCache, + 1, requestId, 0, pCb); + + portSyncRwLockReleaseWrite(pFabric->pMulticastFabriCacheLock); +} + void fabricSetFmSessionFlags_IMPL ( @@ -260,17 +798,68 @@ fabricConstruct_IMPL { NV_STATUS status = NV_OK; - pFabric->pMulticastFabricOpsMutex = - portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + listInit(&pFabric->fabricEventListV2, portMemAllocatorGetGlobalNonPaged()); + multimapInit(&pFabric->importCache, portMemAllocatorGetGlobalNonPaged()); + multimapInit(&pFabric->unimportCache, portMemAllocatorGetGlobalNonPaged()); + + multimapInit(&pFabric->fabricMulticastCache, + portMemAllocatorGetGlobalNonPaged()); + + pFabric->pListLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); - if (pFabric->pMulticastFabricOpsMutex == NULL) + if (pFabric->pListLock == NULL) { status = NV_ERR_NO_MEMORY; goto fail; } - multimapInit(&pFabric->fabricMulticastCache, - portMemAllocatorGetGlobalNonPaged()); + pFabric->pImportCacheLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + + if (pFabric->pImportCacheLock == NULL) + { + status = NV_ERR_NO_MEMORY; + goto fail; + } + + pFabric->pUnimportCacheLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + + if (pFabric->pUnimportCacheLock == NULL) + { + status = NV_ERR_NO_MEMORY; + goto fail; + } + + pFabric->pFabricImportModuleLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + + if (pFabric->pFabricImportModuleLock == NULL) + { + status = NV_ERR_NO_MEMORY; + goto fail; + } + + pFabric->nodeId = NV_FABRIC_INVALID_NODE_ID; + + pFabric->pMulticastFabricModuleLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + + if (pFabric->pMulticastFabricModuleLock == NULL) + { + status = NV_ERR_NO_MEMORY; + goto fail; + } + + pFabric->pMulticastFabriCacheLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + + if (pFabric->pMulticastFabriCacheLock == NULL) + { + status = NV_ERR_NO_MEMORY; + goto fail; + } return NV_OK; @@ -291,9 +880,35 @@ fabricDestruct_IMPL multimapDestroy(&pFabric->fabricMulticastCache); - if (pFabric->pMulticastFabricOpsMutex != NULL) - portSyncMutexDestroy(pFabric->pMulticastFabricOpsMutex); + if (pFabric->pMulticastFabricModuleLock != NULL) + portSyncRwLockDestroy(pFabric->pMulticastFabricModuleLock); + + if (pFabric->pMulticastFabriCacheLock != NULL) + portSyncRwLockDestroy(pFabric->pMulticastFabriCacheLock); + + NV_ASSERT(listCount(&pFabric->fabricEventListV2) == 0); + + NV_ASSERT(multimapCountItems(&pFabric->unimportCache) == 0); + NV_ASSERT(multimapCountItems(&pFabric->importCache) == 0); + + NV_ASSERT(pFabric->nodeId == NV_FABRIC_INVALID_NODE_ID); + + if (pFabric->pFabricImportModuleLock != NULL) + portSyncRwLockDestroy(pFabric->pFabricImportModuleLock); + if (pFabric->pUnimportCacheLock != NULL) + portSyncRwLockDestroy(pFabric->pUnimportCacheLock); + + if (pFabric->pImportCacheLock != NULL) + portSyncRwLockDestroy(pFabric->pImportCacheLock); + + if (pFabric->pListLock != NULL) + portSyncRwLockDestroy(pFabric->pListLock); + + multimapDestroy(&pFabric->unimportCache); + multimapDestroy(&pFabric->importCache); + + listDestroy(&pFabric->fabricEventListV2); } void @@ -306,23 +921,11 @@ fabricMulticastWaitOnTeamCleanupCallback Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); OS_WAIT_QUEUE *pWq; - fabricMulticastFabricOpsMutexAcquire(pFabric); - - pWq = (OS_WAIT_QUEUE *)fabricMulticastCleanupCacheGetUnderLock_IMPL(pFabric, - inbandReqId); - fabricMulticastFabricOpsMutexRelease(pFabric); - + pWq = (OS_WAIT_QUEUE *)fabricMulticastCleanupCacheGet(pFabric, inbandReqId); if (pWq == NULL) return; osWaitInterruptible(pWq); - - fabricMulticastFabricOpsMutexAcquire(pFabric); - - fabricMulticastCleanupCacheDeleteUnderLock_IMPL(pFabric, - inbandReqId); - - fabricMulticastFabricOpsMutexRelease(pFabric); - + fabricMulticastCleanupCacheDelete(pFabric, inbandReqId); osFreeWaitQueue(pWq); } diff --git a/src/nvidia/src/kernel/compute/imex_session_api.c b/src/nvidia/src/kernel/compute/imex_session_api.c new file mode 100644 index 0000000000..d45571809c --- /dev/null +++ b/src/nvidia/src/kernel/compute/imex_session_api.c @@ -0,0 +1,388 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/*! + * @file + * @brief This file contains the functions managing the ImexSession + */ + +#define NVOC_IMEX_SESSION_API_H_PRIVATE_ACCESS_ALLOWED + +#include "core/core.h" +#include "compute/imex_session_api.h" +#include "resserv/rs_client.h" +#include "core/system.h" +#include "rmapi/client.h" +#include "gpu/device/device.h" +#include "os/os.h" +#include "class/cl00f1.h" +#include "compute/fabric.h" +#include "gpu_mgr/gpu_mgr.h" +#include "kernel/gpu/gpu.h" +#include "ctrl/ctrl0080/ctrl0080internal.h" +#include "rmapi/rs_utils.h" +#include "core/locks.h" +#include "resserv/rs_resource.h" +#include "mem_mgr/mem_fabric_import_v2.h" +#include "mem_mgr/mem_export.h" + +#include "mem_mgr/mem_multicast_fabric.h" + +static void +_performRcAndDisableChannels +( + OBJGPU *pGpu, + NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS *pParams +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + if (pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalDevice, + NV0080_CTRL_CMD_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS, + pParams, + sizeof(*pParams)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to disable channels for GPU %d\n", pGpu->gpuInstance); + } +} + +static NvBool +_checkClientDesiredImporterAndClearCache +( + RsClient *pRsClient, + NvU16 nodeId +) +{ + RS_ITERATOR it = clientRefIter(pRsClient, 0, classId(MemoryFabricImportV2), + RS_ITERATE_CHILDREN, NV_TRUE); + NvBool bMatch = NV_FALSE; + + while (clientRefIterNext(pRsClient, &it)) + { + MemoryFabricImportV2 *pMemoryFabricImportV2 = + dynamicCast(it.pResourceRef->pResource, MemoryFabricImportV2); + + if (pMemoryFabricImportV2 == NULL) + continue; + + // Importer of any node or perfect match + if ((nodeId == NV_FABRIC_INVALID_NODE_ID) || + (pMemoryFabricImportV2->expNodeId == nodeId)) + { + bMatch = NV_TRUE; + + // Clear cache to avoid imports on stale cache. + memoryfabricimportv2RemoveFromCache(pMemoryFabricImportV2); + } + } + + it = clientRefIter(pRsClient, 0, classId(MemoryMulticastFabric), + RS_ITERATE_CHILDREN, NV_TRUE); + + while (clientRefIterNext(pRsClient, &it)) + { + MemoryMulticastFabric *pMemoryMulticastFabric = + dynamicCast(it.pResourceRef->pResource, MemoryMulticastFabric); + + if ((pMemoryMulticastFabric == NULL) || + (!pMemoryMulticastFabric->bImported)) + continue; + + // Importer of any node or perfect match + if ((nodeId == NV_FABRIC_INVALID_NODE_ID) || + (pMemoryMulticastFabric->expNodeId == nodeId)) + { + bMatch = NV_TRUE; + + // Clear cache to avoid imports on stale cache. + memorymulticastfabricRemoveFromCache(pMemoryMulticastFabric); + } + } + + return bMatch; +} + +void +rcAndDisableOutstandingClientsWithImportedMemory +( + OBJGPU *pGpu, + NvU16 nodeId +) +{ + RmClient **ppClient; + Device *pDevice; + NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS params; + NvU32 gpuMask = 0; + NvU32 gpuCount = 0; + NvU32 gpuInstance = 0; + + NV_ASSERT(rmapiLockIsOwner()); + + if (pGpu == NULL) + { + gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); + } + else + { + gpuCount = 1; + gpuMask = NVBIT(pGpu->gpuInstance); + } + + if (gpuCount != 0) + { + NV_ASSERT(rmGpuLockIsOwner() || + rmGpuGroupLockIsOwner(0, GPU_LOCK_GRP_MASK, &gpuMask)); + } + + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + params.numClients = 0; + + for (ppClient = serverutilGetFirstClientUnderLock(); + ppClient; + ppClient = serverutilGetNextClientUnderLock(ppClient)) + { + RmClient *pClient = *ppClient; + RsClient *pRsClient = staticCast(pClient, RsClient); + + // Skip kernel clients like UVM or check if the client is IMEX capable + if ((rmclientGetCachedPrivilege(pClient) >= RS_PRIV_LEVEL_KERNEL) || + (rmclientIsCapable(pClient, NV_RM_CAP_SYS_FABRIC_IMEX_MGMT))) + continue; + + // + // DO NOT SKIP the clients for any other condition than the + // privileged trusted clients before this check. We must + // disable clients even if they have not subscribed to a device + // but have imported device-less fabric memory. + // + if (!_checkClientDesiredImporterAndClearCache(pRsClient, nodeId)) + continue; + + // Disable client from performing new alloc or duping. + pRsClient->bActive = NV_FALSE; + + // Not subscribed to this device.. + if (deviceGetByGpu(pRsClient, pGpu, NV_TRUE, &pDevice) != NV_OK) + continue; + + params.clientHandles[params.numClients] = pRsClient->hClient; + params.numClients++; + + // Flush if the client handle array is full + if (params.numClients == + NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS) + { + _performRcAndDisableChannels(pGpu, ¶ms); + params.numClients = 0; + } + } + + if (params.numClients != 0) + _performRcAndDisableChannels(pGpu, ¶ms); + } +} + +NV_STATUS +imexsessionapiConstruct_IMPL +( + ImexSessionApi *pImexSessionApi, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV00F1_ALLOCATION_PARAMETERS *pUserParams = pParams->pAllocParams; + OBJSYS *pSys = SYS_GET_INSTANCE(); + Fabric *pFabric = SYS_GET_FABRIC(pSys); + NvHandle hClient = pCallContext->pClient->hClient; + NV_STATUS status; + NvP64 pImexOsEvent = NvP64_NULL; + + NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); + + if ((pUserParams->flags != 0) || + (pUserParams->pOsEvent == NULL) || + (pUserParams->nodeId == NV_FABRIC_INVALID_NODE_ID)) + { + NV_PRINTF(LEVEL_ERROR, "Invalid input value\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + status = osUserHandleToKernelPtr(hClient, pUserParams->pOsEvent, + &pImexOsEvent); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Invalid event handle: 0x%x\n", status); + return status; + } + + // + // This check also ensure that there is only one IMEX instance listening + // to events. + // + status = fabricSetImexEvent(pFabric, pImexOsEvent); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unable to set event: 0x%x\n", status); + goto fail_dereference; + } + + osRmCapInitDescriptor(&pImexSessionApi->dupedCapDescriptor); + + status = osRmCapAcquire(pSys->pOsRmCaps, + NV_RM_CAP_SYS_FABRIC_IMEX_MGMT, + pUserParams->capDescriptor, + &pImexSessionApi->dupedCapDescriptor); + // + // On platforms where capability isn't implemented, + // enforce the admin-only check. + // + if (status == NV_ERR_NOT_SUPPORTED) + { + if (!rmclientIsAdminByHandle(hClient, pCallContext->secInfo.privLevel)) + { + NV_PRINTF(LEVEL_ERROR, "insufficient permissions\n"); + status = NV_ERR_INSUFFICIENT_PERMISSIONS; + goto fail_unset_event; + } + } + else if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Capability validation failed\n"); + goto fail_unset_event; + } + + fabricSetNodeId(pFabric, pUserParams->nodeId); + pImexSessionApi->flags = pUserParams->flags; + + return NV_OK; + +fail_unset_event: + NV_ASSERT_OK(fabricSetImexEvent(pFabric, NULL)); + +fail_dereference: + osDereferenceObjectCount(pImexOsEvent); + + return status; +} + +void +imexsessionapiDestruct_IMPL +( + ImexSessionApi *pImexSessionApi +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + Fabric *pFabric = SYS_GET_FABRIC(pSys); + NvP64 pImexOsEvent = fabricGetImexEvent(pFabric); + + // Invalidate export cache to block future imports on this node ID. + memoryexportClearCache(fabricGetNodeId(pFabric)); + + // Invalidate IMEX event and cached node ID + NV_ASSERT_OK(fabricSetImexEvent(pFabric, NULL)); + fabricSetNodeId(pFabric, NV_FABRIC_INVALID_NODE_ID); + + // Release event and IMEX cap + osDereferenceObjectCount(pImexOsEvent); + osRmCapRelease(pImexSessionApi->dupedCapDescriptor); + + // Flush pending events and wake up threads waiting on them + fabricFlushUnhandledEvents(pFabric); + fabricUnimportCacheIterateAll(pFabric, fabricWakeUpThreadCallback); + + if (!(pImexSessionApi->flags & NV00F1_ALLOC_DISABLE_CHANNEL_RECOVERY)) + { + rcAndDisableOutstandingClientsWithImportedMemory(NULL, NV_FABRIC_INVALID_NODE_ID); + } + + NV_PRINTF(LEVEL_WARNING, "IMEX daemon shutdown!\n"); +} + +NV_STATUS +imexsessionapiCtrlCmdGetFabricEvents_IMPL +( + ImexSessionApi *pImexSessionApi, + NV00F1_CTRL_GET_FABRIC_EVENTS_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + Fabric *pFabric = SYS_GET_FABRIC(pSys); + + pParams->numEvents = NV00F1_CTRL_GET_FABRIC_EVENTS_ARRAY_SIZE; + pParams->bMoreEvents = fabricExtractEventsV2(pFabric, + pParams->eventArray, + &pParams->numEvents); + + return NV_OK; +} + +NV_STATUS +imexsessionapiCtrlCmdFinishMemUnimport_IMPL +( + ImexSessionApi *pImexSessionApi, + NV00F1_CTRL_FINISH_MEM_UNIMPORT_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + Fabric *pFabric = SYS_GET_FABRIC(pSys); + NV00F1_CTRL_FABRIC_UNIMPORT_TOKEN *pTokenArray = pParams->tokenArray; + NvU32 i; + + if ((pParams->numTokens == 0) || + (pParams->numTokens > NV00F1_CTRL_FINISH_MEM_UNIMPORT_ARRAY_SIZE)) + return NV_ERR_INVALID_ARGUMENT; + + for (i = 0; i < pParams->numTokens; i++) + { + // + // Ignore errors if the unimport event ID is not found. This could + // happen if thread has already exited. + // + (void)fabricUnimportCacheInvokeCallback(pFabric, + pTokenArray[i].unimportEventId, + fabricWakeUpThreadCallback); + } + + return NV_OK; +} + +NV_STATUS +imexsessionapiCtrlCmdDisableImporters_IMPL +( + ImexSessionApi *pImexSessionApi, + NV00F1_CTRL_DISABLE_IMPORTERS_PARAMS *pParams +) +{ + + if (pImexSessionApi->flags & NV00F1_ALLOC_DISABLE_CHANNEL_RECOVERY) + return NV_ERR_NOT_SUPPORTED; + + rcAndDisableOutstandingClientsWithImportedMemory(NULL, pParams->nodeId); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/core/bin_data.c b/src/nvidia/src/kernel/core/bin_data.c index 5cd2e1f594..f56acfee42 100644 --- a/src/nvidia/src/kernel/core/bin_data.c +++ b/src/nvidia/src/kernel/core/bin_data.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -327,6 +327,71 @@ bindataArchiveGetStorage( return NULL; } +void bindataInitialize(void) +{ +} + +void bindataDestroy(void) +{ +} + +/*! + * Enable zero copy of bindata. If executed on GSP and if the bindata section is uncompressed, + * populate ppData with the location in the elf file. + * Otherwise, allocate buffers in heap and copy the bindata. + * Assumes pBinstorage and ppData are valid + * + * @param[out] ppData pointer to elf section/allocated buffer + * @param[in] pBinStorage Pointer to Bindata Storage + * + * @return NV_OK if operation is successful + * NV_ERR_NO_MEMORY if buffer allocation fails + */ +NV_STATUS bindataStorageAcquireData( + const BINDATA_STORAGE *pBinStorage, + const void **ppData +) +{ + NV_STATUS status = NV_OK; + + { + NvU32 bufferSize = bindataGetBufferSize(pBinStorage); + *ppData = portMemAllocNonPaged(bufferSize); + + if (*ppData == NULL) + { + NV_PRINTF(LEVEL_ERROR, "bindata memory alloc failed\n"); + return NV_ERR_NO_MEMORY; + } + + status = bindataWriteToBuffer(pBinStorage, (NvU8 *)*ppData, bufferSize); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "bindataWriteToBuffer failed. Freeing alloced memory, return code %u\n", status); + portMemFree((void*)*ppData); + *ppData = NULL; + return status; + } + } + return status; +} + +/*! + * Skip calling free on unallocated bindata zero copy pointers + * calls free in non gsp cases + * @param[in] pData Pointer to be freed + * + */ +void bindataStorageReleaseData( + void *pData +) +{ + { + portMemFree(pData); + } +} // File Overriding Feature is only enabled under MODS diff --git a/src/nvidia/src/kernel/core/bin_data_pvt.h b/src/nvidia/src/kernel/core/bin_data_pvt.h index a24181287a..99be5be616 100644 --- a/src/nvidia/src/kernel/core/bin_data_pvt.h +++ b/src/nvidia/src/kernel/core/bin_data_pvt.h @@ -45,7 +45,6 @@ // public module directory // - // // Private data structure for binary data management // diff --git a/src/nvidia/src/kernel/core/locks.c b/src/nvidia/src/kernel/core/locks.c index 77ceede7e6..136eb5048a 100644 --- a/src/nvidia/src/kernel/core/locks.c +++ b/src/nvidia/src/kernel/core/locks.c @@ -36,12 +36,34 @@ #include "objtmr.h" #include #include +#include "gpu_mgr/gpu_mgr.h" #include #include "kernel/gpu/intr/intr.h" #include #include "gpu/disp/kern_disp.h" #include "ctrl/ctrl0000/ctrl0000system.h" +// +// These values were chosen based on some performance testing data +// for a particular use case that should be a good example of multiple +// threads contending for the GPU lock. See bug 4035405. +// +static const NvU32 MIDPATH_RETRIES = 20; +static const NvU32 MIDPATH_DELAY_USEC = 30; + +// +// An invalid gpuInst value representing the absence of a GPU lock. +// - Loops over gpuInst values should terminate upon seeing this value. +// - maxLockableGpuInst will have this value when there are no GPU locks. +// +static const NvU32 GPU_INST_INVALID = (NvU32) (-1); + +// +// A placeholder gpuInst value representing the GPU alloc lock in loops over +// gpuInst values. +// +static const NvU32 GPU_INST_ALLOC_LOCK = 0xff; + // // GPU lock // @@ -109,6 +131,9 @@ typedef struct // Tracks largest valid gpuInstance for which a lock has been allocated. // This is useful to pare down the # of loop iterations we need to make // when searching for lockable GPUs. + // + // When there are no lockable GPUs, this will GPU_INST_INVALID. + // // Requires holding API, pLock or any GPU to read, API+pLock+GPUs to write. // NvU32 maxLockableGpuInst; @@ -118,6 +143,17 @@ typedef struct // GPULOCK gpuLocks[NV_MAX_DEVICES]; + // + // GPU alloc lock + // + // Taken by rmGpuLockAlloc as well as _rmGpuLocksAcquire for GPUS_LOCK_ALL + // or when given flag GPUS_LOCK_FLAG_LOCK_ALLOC to prevent new GPU locks + // from being added from underneath the thread holding the locks. + // + // Ordered before all per-GPU locks in gpuLocks. + // + GPULOCK gpuAllocLock; + // // Lock call trace info. // @@ -136,10 +172,117 @@ typedef struct static GPULOCKINFO rmGpuLockInfo; +static NV_STATUS _rmGpuLockInit(GPULOCK *pGpuLock); +static void _rmGpuLockDestroy(GPULOCK *pGpuLock); + static NV_STATUS _rmGpuLocksAcquire(NvU32, NvU32, NvU32, void *, NvU32 *); static NvU32 _rmGpuLocksRelease(NvU32, NvU32, OBJGPU *, void *); + +static NvBool _rmGpuAllocLockIsOwner(void); static NvBool _rmGpuLockIsOwner(NvU32); + +// +// Determines the gpuInst value for the first iteration of a loop +// iterating forwards over gpuInst values. Loop iterations look like: +// - GPU_INST_ALLOC_LOCK, 0, ..., max (normally) +// - GPU_INST_ALLOC_LOCK (if max == GPU_INST_INVALID) +// +static inline NvU32 _gpuInstLoopHead(NvU32 max) +{ + // + // Note: given the ordering of the GPU alloc lock before the per-GPU locks, + // the "max" parameter of this function is not technically needed, however + // it is kept for consistency with _gpuInstLoopTail. + // + + return GPU_INST_ALLOC_LOCK; +} + +// +// Determines the gpuInst value for the next iteration of a loop +// iterating forwards over gpuInst values. Loop iterations look like: +// - GPU_INST_ALLOC_LOCK, 0, ..., max (normally) +// - GPU_INST_ALLOC_LOCK (if max == GPU_INST_INVALID) +// +static inline NvU32 _gpuInstLoopNext(NvU32 i, NvU32 max) +{ + if (i == GPU_INST_ALLOC_LOCK) + { + if (max == GPU_INST_INVALID) + { + return GPU_INST_INVALID; + } + else + { + return 0; + } + } + else if (i == max) + { + return GPU_INST_INVALID; + } + else + { + return i + 1; + } +} + +// +// Determines the gpuInst value for the first iteration of a loop +// iterating backwards over gpuInst values. Loop iterations look like: +// - max, ..., 0, GPU_INST_ALLOC_LOCK (normally) +// - GPU_INST_ALLOC_LOCK (if max == GPU_INST_INVALID) +// +static inline NvU32 _gpuInstLoopTail(NvU32 max) +{ + if (max == GPU_INST_INVALID) + { + return GPU_INST_ALLOC_LOCK; + } + else + { + return max; + } +} + +// +// Determines the gpuInst value for the next iteration of a loop +// iterating backwards over gpuInst values. Loop iterations look like: +// - max, ..., 0, GPU_INST_ALLOC_LOCK (normally) +// - GPU_INST_ALLOC_LOCK (if max == GPU_INST_INVALID) +// +static inline NvU32 _gpuInstLoopPrev(NvU32 i, NvU32 max) +{ + // + // Note: given the ordering of the GPU alloc lock before the per-GPU locks, + // the "max" parameter of this function is not technically needed, however + // it is kept for consistency with _gpuInstLoopNext. + // + + if (i == 0) + { + return GPU_INST_ALLOC_LOCK; + } + else if (i == GPU_INST_ALLOC_LOCK) + { + return GPU_INST_INVALID; + } + else + { + return i - 1; + } +} + +// +// Determines whether a loop iterating over gpuInst values using +// _gpuInstLoopNext or _gpuInstLoopPrev should continue. +// +static inline NvBool _gpuInstLoopShouldContinue(NvU32 i) +{ + return (i != GPU_INST_INVALID); +} + // // rmGpuLockInfoInit // @@ -148,15 +291,30 @@ static NvBool _rmGpuLockIsOwner(NvU32); NV_STATUS rmGpuLockInfoInit(void) { + NV_STATUS status; + portMemSet(&rmGpuLockInfo, 0, sizeof(rmGpuLockInfo)); rmGpuLockInfo.pLock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); if (rmGpuLockInfo.pLock == NULL) return NV_ERR_INSUFFICIENT_RESOURCES; - rmGpuLockInfo.maxLockableGpuInst = (NvU32)-1; + rmGpuLockInfo.maxLockableGpuInst = GPU_INST_INVALID; + + // Initialize the GPU alloc lock + status = _rmGpuLockInit(&rmGpuLockInfo.gpuAllocLock); + if (status != NV_OK) + { + goto err_out; + } return NV_OK; + +err_out: + if (rmGpuLockInfo.pLock != NULL) + portSyncSpinlockDestroy(rmGpuLockInfo.pLock); + + return status; } // @@ -174,6 +332,94 @@ rmGpuLockInfoDestroy(void) if (rmGpuLockInfo.pLock != NULL) portSyncSpinlockDestroy(rmGpuLockInfo.pLock); + + // + // Destroy the GPU alloc lock + // Note: this operation wakes all threads still waiting on the semaphore. + // + _rmGpuLockDestroy(&rmGpuLockInfo.gpuAllocLock); +} + +// +// _rmGpuLockInit +// +// Initialize a GPULOCK struct. +// +// This operation is common between: +// - GPU alloc lock (performed in rmGpuLockInfoInit) +// - Per-GPU locks (performed in rmGpuLockAlloc) +// +static NV_STATUS +_rmGpuLockInit(GPULOCK *pGpuLock) +{ + // clear struct for good measure and then init everything + portMemSet(pGpuLock, 0, sizeof(*pGpuLock)); + + pGpuLock->pWaitSema = portSyncSemaphoreCreate(portMemAllocatorGetGlobalNonPaged(), 0); + if (pGpuLock->pWaitSema == NULL) + { + return NV_ERR_NO_MEMORY; + } + + pGpuLock->count = 1; + pGpuLock->bRunning = NV_FALSE; + pGpuLock->bSignaled = NV_FALSE; + pGpuLock->threadId = ~(NvU64)0; + + return NV_OK; +} + +// +// _rmGpuLockDestroy +// +// Destroy/cleanup a GPULOCK struct. +// +// For the per-GPU locks, this function must only be called after +// the GPU has been removed from the lockable mask (otherwise another thread +// could come in and take the lock). +// +// Note: this operation wakes all threads still waiting on the semaphore. +// +// This operation is common between: +// - GPU alloc lock (performed in rmGpuLockInfoDestroy) +// - Per-GPU locks (performed in rmGpuLockFree) +// +static void +_rmGpuLockDestroy(GPULOCK *pGpuLock) +{ + if (pGpuLock->pWaitSema != NULL) + { + // + // At this point, we may still have threads waiting on the semaphore, + // and possibly one thread holding the lock. + // Wake up all threads that are waiting, and wait until the holding one + // is done. + // + while (pGpuLock->count <= 0) // volatile read + { + portSyncSemaphoreRelease(pGpuLock->pWaitSema); + osSchedule(); // Yield execution + portSyncSemaphoreAcquire(pGpuLock->pWaitSema); + } + portSyncSemaphoreDestroy(pGpuLock->pWaitSema); + pGpuLock->pWaitSema = NULL; + } + + portMemSet(pGpuLock, 0, sizeof(*pGpuLock)); +} + +// +// _rmGpuAllocLockIsOwner +// +// Returns NV_TRUE if calling thread currently owns the GPU alloc lock. +// +static NvBool +_rmGpuAllocLockIsOwner(void) +{ + GPULOCK *pAllocLock = &rmGpuLockInfo.gpuAllocLock; + OS_THREAD_HANDLE threadId; + osGetCurrentThread(&threadId); + return pAllocLock->threadId == threadId; } // @@ -185,7 +431,6 @@ NV_STATUS rmGpuLockAlloc(NvU32 gpuInst) { GPULOCK *pGpuLock; - NvU32 gpuMask, gpuLockedMask; NV_STATUS status; NvU64 threadId = ~0; NvU64 timestamp; @@ -207,47 +452,38 @@ rmGpuLockAlloc(NvU32 gpuInst) if (status != NV_OK) return status; - // clear struct for good measure and then init everything - portMemSet(pGpuLock, 0, sizeof(*pGpuLock)); - - pGpuLock->pWaitSema = portSyncSemaphoreCreate(portMemAllocatorGetGlobalNonPaged(), 0); - if (pGpuLock->pWaitSema == NULL) + // initialize GPULOCK structure for this lock + status = _rmGpuLockInit(pGpuLock); + if (status != NV_OK) { - status = NV_ERR_NO_MEMORY; goto done; } - pGpuLock->count = 1; - pGpuLock->bRunning = NV_FALSE; - pGpuLock->bSignaled = NV_FALSE; - pGpuLock->threadId = ~(NvU64)0; - // - // Before updating the gpusLockableMask value we need to grab the - // locks for all *other* GPUs. This ensures that the gpusLockableMask - // value cannot change in between acquire/release calls issued by - // a different thread. Reading this is safe under API lock. + // Before updating the gpusLockableMask value we need to grab + // the GPU alloc lock. + // + // This ensures that the gpusLockableMask value cannot change in between + // acquire/release calls issued by a different thread. Reading this is safe + // under API lock. // - gpuMask = rmGpuLockInfo.gpusLockableMask; - // LOCK: acquire GPU locks - status = _rmGpuLocksAcquire(gpuMask, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT, - NV_RETURN_ADDRESS(), &gpuLockedMask); - if (status == NV_WARN_NOTHING_TO_DO) - { - // Verify that this is a valid case - i.e. we're attaching first GPU. - NV_ASSERT(gpuMask == 0); - status = NV_OK; - } + // LOCK: acquire GPU alloc lock + // (only the GPU alloc lock is needed, so gpuMask is passed as zero) + status = _rmGpuLocksAcquire(0x0, GPU_LOCK_FLAGS_LOCK_ALLOC, RM_LOCK_MODULES_INIT, + NV_RETURN_ADDRESS(), NULL); if (status != NV_OK) + { + NV_ASSERT_FAILED("failed to acquire GPU alloc lock"); goto done; + } portSyncSpinlockAcquire(rmGpuLockInfo.pLock); // add the GPU to the lockable mask rmGpuLockInfo.gpusLockableMask |= NVBIT(gpuInst); // save this gpuInst if it's the largest we've seen so far - if (rmGpuLockInfo.maxLockableGpuInst == (NvU32)-1) + if (rmGpuLockInfo.maxLockableGpuInst == GPU_INST_INVALID) { rmGpuLockInfo.maxLockableGpuInst = gpuInst; } @@ -270,14 +506,17 @@ rmGpuLockAlloc(NvU32 gpuInst) portSyncSpinlockRelease(rmGpuLockInfo.pLock); - // UNLOCK: release GPU locks - _rmGpuLocksRelease(gpuLockedMask, GPUS_LOCK_FLAGS_NONE, NULL, NV_RETURN_ADDRESS()); + // UNLOCK: release GPU alloc lock + _rmGpuLocksRelease(0x0, GPU_LOCK_FLAGS_LOCK_ALLOC, NULL, NV_RETURN_ADDRESS()); done: if (status != NV_OK) { if (pGpuLock->pWaitSema) + { portSyncSemaphoreDestroy(pGpuLock->pWaitSema); + pGpuLock->pWaitSema = NULL; + } // free intr mask lock rmIntrMaskLockFree(gpuInst); @@ -327,6 +566,12 @@ rmGpuLockFree(NvU32 gpuInst) if (status != NV_OK && status != NV_WARN_NOTHING_TO_DO) return; + // + // Note: we don't need the GPU alloc lock here, as we will hold both: + // - pLock (the spinlock) which locks out rmGpuLockAlloc + // - all other per-GPU locks which locks out anyone taking any per-GPU lock + // + portSyncSpinlockAcquire(rmGpuLockInfo.pLock); // remove the GPU from the lockable mask rmGpuLockInfo.gpusLockableMask &= ~NVBIT(gpuInst); @@ -359,7 +604,7 @@ rmGpuLockFree(NvU32 gpuInst) else { // no locks left so start over - rmGpuLockInfo.maxLockableGpuInst = (NvU32)-1; + rmGpuLockInfo.maxLockableGpuInst = GPU_INST_INVALID; } } portSyncSpinlockRelease(rmGpuLockInfo.pLock); @@ -367,24 +612,11 @@ rmGpuLockFree(NvU32 gpuInst) // UNLOCK: release GPU locks _rmGpuLocksRelease(gpuLockedMask, GPUS_LOCK_FLAGS_NONE, NULL, NV_RETURN_ADDRESS()); - if (pGpuLock->pWaitSema) - { - // - // At this point, we may still have threads waiting on the semaphore, - // and possibly one thread holding the lock. - // Wake up all threads that are waiting, and wait until the holding one - // is done. - // - while (pGpuLock->count <= 0) // volatile read - { - portSyncSemaphoreRelease(pGpuLock->pWaitSema); - osSchedule(); // Yield execution - portSyncSemaphoreAcquire(pGpuLock->pWaitSema); - } - portSyncSemaphoreDestroy(pGpuLock->pWaitSema); - } - - portMemSet(pGpuLock, 0, sizeof(*pGpuLock)); + // + // cleanup GPULOCK structure for this lock + // note: this operations wakes all threads still waiting on the semaphore + // + _rmGpuLockDestroy(pGpuLock); // free intr mask lock rmIntrMaskLockFree(gpuInst); @@ -488,6 +720,7 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG NV_STATUS status = NV_OK; NvU32 gpuInst; NvU32 gpuMaskLocked = 0; + GPULOCK *pAllocLock = &rmGpuLockInfo.gpuAllocLock; GPULOCK *pGpuLock; NvBool bHighIrql, bCondAcquireCheck; NvU32 maxLockableGpuInst; @@ -497,6 +730,8 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG NvU64 timestamp; NvU64 startWaitTime; NvBool bLockAll = NV_FALSE; + NvBool bAcquireAllocLock = NV_FALSE; + NvU32 loopCount; bHighIrql = (portSyncExSafeToSleep() == NV_FALSE); bCondAcquireCheck = ((flags & GPU_LOCK_FLAGS_COND_ACQUIRE) != 0); @@ -511,16 +746,30 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG // If caller wishes to lock all GPUs then convert incoming mask // to set that are actually lockable. // + // Also acquire the GPU alloc lock to ensure that the set of + // lockable GPUs will not change from underneath caller. + // if (gpuMask == GPUS_LOCK_ALL) { gpuMask = rmGpuLockInfo.gpusLockableMask; bLockAll = NV_TRUE; + bAcquireAllocLock = NV_TRUE; } // - // We may get a gpuMask of zero during setup of the first GPU attached. + // If GPU alloc lock was explicitly requested then acquire it. // - if (gpuMask == 0) + // Callers may acquire just the GPU alloc lock (and not any per-GPU locks) + // by passing a gpuMask of zero. Notably, rmGpuLockAlloc does this. + // + // Otherwise, if we get a gpuMask of zero, it is because the acquire is + // occurring before the first GPU is attached, so just return early. + // + if (flags & GPU_LOCK_FLAGS_LOCK_ALLOC) + { + bAcquireAllocLock = NV_TRUE; + } + else if (gpuMask == 0) { status = NV_WARN_NOTHING_TO_DO; goto done; @@ -551,9 +800,14 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG goto done; } } - // Cache global variable so it doesn't change in the middle of the loop. + + // + // Cache global variable maxLockableGpuInst so it doesn't change in the + // middle of the loop. If any per-GPU locks (not just the GPU alloc lock) + // is being acquired, sanity check against NV_MAX_DEVICES. + // maxLockableGpuInst = rmGpuLockInfo.maxLockableGpuInst; - if (maxLockableGpuInst >= NV_MAX_DEVICES) + if ((gpuMask != 0) && (maxLockableGpuInst >= NV_MAX_DEVICES)) { DBG_BREAKPOINT(); status = NV_ERR_INVALID_STATE; @@ -566,22 +820,37 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG // In safe mode, we never attempt to acquire locks we already own.. gpuMask &= ~ownedMask; + + if (_rmGpuAllocLockIsOwner()) + { + bAcquireAllocLock = NV_FALSE; + } + // If we already own everything we need, just bail early. - if (gpuMask == 0) + if ((!bAcquireAllocLock) && (gpuMask == 0)) { status = NV_WARN_NOTHING_TO_DO; goto done; } - // If we own a higher order lock than one of the needed ones, we are - // violating the locking order and need to do a conditional acquire - // clz32(0) == ctz(0) == 32: - // owned=0b00001100, needed=0b00110000: ((32-28) > 4), bCond=FALSE - // owned=0b00001100, needed=0b00110010: ((32-28) > 1), bCond=TRUE - // owned=0b11000011, needed=0b00010000: ((32-24) > 4), bCond=TRUE - // owned=0b00000000, needed=0b00000001: ((32-32) > 0), bCond=FALSE - if ((32-portUtilCountLeadingZeros32(ownedMask)) > portUtilCountTrailingZeros32(gpuMask)) + if (bAcquireAllocLock && (ownedMask != 0)) + { + // If we need the GPU alloc lock and already own any per-GPU lock, + // we need to do conditional acquire as the GPU alloc lock is + // ordered before all per-GPU locks. + + bCondAcquireCheck = NV_TRUE; + } + else if ((32-portUtilCountLeadingZeros32(ownedMask)) > portUtilCountTrailingZeros32(gpuMask)) { + // If we own a higher order lock than one of the needed ones, we are + // violating the locking order and need to do a conditional acquire + // clz32(0) == ctz(0) == 32: + // owned=0b00001100, needed=0b00110000: ((32-28) > 4), bCond=FALSE + // owned=0b00001100, needed=0b00110010: ((32-28) > 1), bCond=TRUE + // owned=0b11000011, needed=0b00010000: ((32-24) > 4), bCond=TRUE + // owned=0b00000000, needed=0b00000001: ((32-32) > 0), bCond=FALSE + bCondAcquireCheck = NV_TRUE; } } @@ -597,14 +866,25 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG // if (bCondAcquireCheck || bHighIrql) { - for (gpuInst = 0; - gpuInst <= maxLockableGpuInst; - gpuInst++) + // Iterate over gpuInst: GPU_INST_ALLOC_LOCK, 0, ..., maxLockableGpuInst + for (gpuInst = _gpuInstLoopHead(maxLockableGpuInst); + _gpuInstLoopShouldContinue(gpuInst); + gpuInst = _gpuInstLoopNext(gpuInst, maxLockableGpuInst)) { - if ((gpuMask & NVBIT(gpuInst)) == 0) - continue; + if (gpuInst == GPU_INST_ALLOC_LOCK) + { + if (!bAcquireAllocLock) + continue; - pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + pGpuLock = pAllocLock; + } + else + { + if ((gpuMask & NVBIT(gpuInst)) == 0) + continue; + + pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + } // // The conditional check takes precedence here. @@ -635,27 +915,39 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG // // Now (attempt) to acquire the locks... // - for (gpuInst = 0; - gpuInst <= maxLockableGpuInst; - gpuInst++) - { - // skip any not in the mask - if ((gpuMask & NVBIT(gpuInst)) == 0) - continue; - // - // We might have released the spinlock while sleeping on a previous - // semaphore, so check if current GPU wasn't deleted during that time - // - if ((NVBIT(gpuInst) & rmGpuLockInfo.gpusLockableMask) == 0) + // Iterate over gpuInst: GPU_INST_ALLOC_LOCK, 0, ..., maxLockableGpuInst + for (gpuInst = _gpuInstLoopHead(maxLockableGpuInst); + _gpuInstLoopShouldContinue(gpuInst); + gpuInst = _gpuInstLoopNext(gpuInst, maxLockableGpuInst)) + { + if (gpuInst == GPU_INST_ALLOC_LOCK) { - NV_PRINTF(LEVEL_NOTICE, - "GPU lock %d freed while we were waiting on a previous lock\n", - gpuInst); - continue; + if (!bAcquireAllocLock) + continue; + + pGpuLock = pAllocLock; } + else + { + // skip any not in the mask + if ((gpuMask & NVBIT(gpuInst)) == 0) + continue; - pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + // + // We might have released the spinlock while sleeping on a previous + // semaphore, so check if current GPU wasn't deleted during that time + // + if ((NVBIT(gpuInst) & rmGpuLockInfo.gpusLockableMask) == 0) + { + NV_PRINTF(LEVEL_NOTICE, + "GPU lock %d freed while we were waiting on a previous lock\n", + gpuInst); + continue; + } + + pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + } // // Check to see if the lock is not free...we should only fall into this @@ -688,16 +980,68 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG // assert, happens with the stack trace: // osTimerCallback->osRun1HzCallbacksNow->>rmGpuLocksAcquire) // - if (_rmGpuLockIsOwner(NVBIT(gpuInst))) + if (gpuInst == GPU_INST_ALLOC_LOCK) { - NV_PRINTF(LEVEL_INFO, - "GPU lock is already acquired by this thread\n"); - NV_ASSERT(0); - // - // TODO: RM-1493 undo previous acquires - // - status = NV_ERR_STATE_IN_USE; - goto done; + if (_rmGpuAllocLockIsOwner()) + { + NV_ASSERT_FAILED("GPU alloc lock already acquired by this thread"); + // TODO: RM-1493 undo previous acquires + status = NV_ERR_STATE_IN_USE; + goto done; + } + } + else + { + if (_rmGpuLockIsOwner(NVBIT(gpuInst))) + { + NV_ASSERT_FAILED("GPU lock already acquired by this thread"); + // TODO: RM-1493 undo previous acquires + status = NV_ERR_STATE_IN_USE; + goto done; + } + } + + // + // There are 3 possible paths when taking the GPU locks: + // + // 1. Fast path: Use the spinlock to check if the GPU lock is + // available. If so, acquire the GPU lock via the + // spinlock, and avoid a blocking (sleeping) + // wait on the GPU lock semaphore. + // + // 2. Middle path: Loop and retry the fast path (above), with a + // short delay (but *without* sleeping) between + // retries. This provides a significant performance + // boost for some use cases, such as those in + // Bug 4035405. + // + // 3. Slow path: Block on the semaphore and wait for the lock. + // + if (pSys->getProperty(pSys, PDB_PROP_SYS_GPU_LOCK_MIDPATH_ENABLED)) + { + for (loopCount = 0; loopCount < MIDPATH_RETRIES; ++loopCount) + { + portSyncSpinlockRelease(rmGpuLockInfo.pLock); + osDelayUs(MIDPATH_DELAY_USEC); + portSyncSpinlockAcquire(rmGpuLockInfo.pLock); + + // gpu lock could be freed while we're out of the spinlock. + if ((gpuInst != GPU_INST_ALLOC_LOCK) && + ((rmGpuLockInfo.gpusLockableMask & NVBIT(gpuInst)) == 0)) + { + NV_PRINTF(LEVEL_WARNING, + "GPU lock %d freed while threads were still waiting.\n", + gpuInst); + // Skip this GPU, keep trying any others. + goto next_gpu_instance; + } + + if (!pGpuLock->bRunning) + { + portAtomicDecrementS32(&pGpuLock->count); + goto per_gpu_lock_acquired; + } + } } portAtomicDecrementS32(&pGpuLock->count); @@ -707,7 +1051,8 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG portSyncSemaphoreAcquire(pGpuLock->pWaitSema); portSyncSpinlockAcquire(rmGpuLockInfo.pLock); - if ((rmGpuLockInfo.gpusLockableMask & NVBIT(gpuInst)) == 0) + if ((gpuInst != GPU_INST_ALLOC_LOCK) && + ((rmGpuLockInfo.gpusLockableMask & NVBIT(gpuInst)) == 0)) { NV_PRINTF(LEVEL_WARNING, "GPU lock %d freed while threads were still waiting.\n", @@ -729,18 +1074,21 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG { portAtomicDecrementS32(&pGpuLock->count); } - +per_gpu_lock_acquired: // indicate that we are running pGpuLock->bRunning = NV_TRUE; // save off thread that owns this GPUs lock osGetCurrentThread(&pGpuLock->threadId); - // now disable interrupts - _gpuLocksAcquireDisableInterrupts(gpuInst, flags); + if (gpuInst != GPU_INST_ALLOC_LOCK) + { + // now disable interrupts + _gpuLocksAcquireDisableInterrupts(gpuInst, flags); - // mark this one as locked - gpuMaskLocked |= NVBIT(gpuInst); + // mark this one as locked + gpuMaskLocked |= NVBIT(gpuInst); + } // add acquire record to GPUs lock trace osGetCurrentTick(×tamp); @@ -792,6 +1140,11 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG NV_ASSERT(gpuMaskLocked == rmGpuLockInfo.gpusLockableMask); } + if (bAcquireAllocLock) + { + NV_ASSERT(_rmGpuAllocLockIsOwner()); + } + if (pGpuLockedMask) *pGpuLockedMask = gpuMaskLocked; @@ -806,7 +1159,12 @@ _rmGpuLocksAcquire(NvU32 gpuMask, NvU32 flags, NvU32 module, void *ra, NvU32 *pG return status; } - return (gpuMaskLocked == 0) ? NV_WARN_NOTHING_TO_DO : NV_OK; + if ((gpuMaskLocked == 0) && !(flags & GPU_LOCK_FLAGS_LOCK_ALLOC)) + { + return NV_WARN_NOTHING_TO_DO; + } + + return NV_OK; } // @@ -1224,7 +1582,9 @@ static NvU32 _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) { static volatile NvU32 bug200413011_WAR_WakeUpMask; + static volatile NvU32 bug200413011_WAR_AllocLockWakeUp; OBJSYS *pSys = SYS_GET_INSTANCE(); + GPULOCK *pAllocLock = &rmGpuLockInfo.gpuAllocLock; GPULOCK *pGpuLock; NvU32 gpuMaskWakeup = 0; NvU32 gpuInst; @@ -1236,12 +1596,24 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) NvU64 priorityPrev = 0; NvU64 timestamp; NvU64 startHoldTime = 0; + NvBool bReleaseAllocLock = NV_FALSE; + NvBool bAllocLockWakeup = NV_FALSE; NV_STATUS status; + // + // If the GPU alloc lock is held, release it after releasing any GPU lock. + // Releasing any GPU lock means the thread no longer needs "all" GPUs, so + // rmGpuLockAlloc should be allowed to add new GPU locks again. + // + if (_rmGpuAllocLockIsOwner()) + { + bReleaseAllocLock = NV_TRUE; + } + // // We may get a gpuMask of zero during setup of the first GPU attached. // - if (gpuMask == 0) + if ((gpuMask == 0) && (!bReleaseAllocLock)) return NV_OK; // @@ -1256,9 +1628,12 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) // In some error recovery cases we want to be able to force release a lock. // Log all such issues, but don't bail early to enable recovery paths. // - NV_ASSERT(_rmGpuLockIsOwner(gpuMask)); + if (gpuMask != 0) + { + NV_ASSERT(_rmGpuLockIsOwner(gpuMask)); - _gpuLocksReleaseHandleDeferredWork(gpuMask); + _gpuLocksReleaseHandleDeferredWork(gpuMask); + } threadPriorityBoost(&priority, &priorityPrev); portSyncSpinlockAcquire(rmGpuLockInfo.pLock); @@ -1286,11 +1661,26 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) } // Find the highest GPU instance that's locked, to be used for loop bounds - highestInstanceInGpuMask = 31 - portUtilCountLeadingZeros32(gpuMask); - if (highestInstanceInGpuMask > rmGpuLockInfo.maxLockableGpuInst) + if (gpuMask == 0) + { + // + // rmGpuLockAlloc may release the GPU alloc lock while passing + // a gpuMask of 0. + // + // In that case, restrict the gpuInst loops below to one iteration over + // GPU_INST_ALLOC_LOCK by setting highestInstanceInGpuMask to + // GPU_INST_INVALID. + // + highestInstanceInGpuMask = GPU_INST_INVALID; + } + else { - NV_PRINTF(LEVEL_WARNING, "GPU mask for release (0x%08x) has higher instance that maxLockableGpuIns (%d)\n", - highestInstanceInGpuMask, rmGpuLockInfo.maxLockableGpuInst); + highestInstanceInGpuMask = 31 - portUtilCountLeadingZeros32(gpuMask); + if (highestInstanceInGpuMask > rmGpuLockInfo.maxLockableGpuInst) + { + NV_PRINTF(LEVEL_WARNING, "GPU mask for release (0x%08x) has higher instance that maxLockableGpuIns (%d)\n", + highestInstanceInGpuMask, rmGpuLockInfo.maxLockableGpuInst); + } } // @@ -1300,14 +1690,26 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) // have something waiting. If any of them do, then we queue up a DPC // to handle the release of all of them. // - for (gpuInst = highestInstanceInGpuMask; - gpuInst != (NvU32)-1; - gpuInst--) + + // Iterate over gpuInst: highestInstanceInGpuMask, ..., 0, GPU_INST_ALLOC_LOCK + for (gpuInst = _gpuInstLoopTail(highestInstanceInGpuMask); + _gpuInstLoopShouldContinue(gpuInst); + gpuInst = _gpuInstLoopPrev(gpuInst, highestInstanceInGpuMask)) { - if ((gpuMask & NVBIT(gpuInst)) == 0) - continue; + if (gpuInst == GPU_INST_ALLOC_LOCK) + { + if (!bReleaseAllocLock) + continue; - pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + pGpuLock = pAllocLock; + } + else + { + if ((gpuMask & NVBIT(gpuInst)) == 0) + continue; + + pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + } // Start of GPU lock hold time is the first acquired GPU lock if (pSys->getProperty(pSys, PDB_PROP_SYS_RM_LOCK_TIME_COLLECT)) @@ -1317,7 +1719,15 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) { if (!pGpuLock->bSignaled) { - gpuMaskWakeup |= NVBIT(gpuInst); + if (gpuInst == GPU_INST_ALLOC_LOCK) + { + bAllocLockWakeup = NV_TRUE; + } + else + { + gpuMaskWakeup |= NVBIT(gpuInst); + } + if (bSemaCanWake) pGpuLock->bSignaled = NV_TRUE; } @@ -1335,19 +1745,30 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) // is waiting and we are running at an elevated processor level (i.e. // we're here from a call in our ISR). // - if (gpuMaskWakeup == 0 || bSemaCanWake) + if (((gpuMaskWakeup == 0) && (!bAllocLockWakeup)) || bSemaCanWake) { - for (gpuInst = highestInstanceInGpuMask; - gpuInst != (NvU32)-1; - gpuInst--) + // Iterate over gpuInst: highestInstanceInGpuMask, ..., 0, GPU_INST_ALLOC_LOCK + for (gpuInst = _gpuInstLoopTail(highestInstanceInGpuMask); + _gpuInstLoopShouldContinue(gpuInst); + gpuInst = _gpuInstLoopPrev(gpuInst, highestInstanceInGpuMask)) { - if ((gpuMask & NVBIT(gpuInst)) == 0) - continue; + if (gpuInst == GPU_INST_ALLOC_LOCK) + { + if (!bReleaseAllocLock) + continue; - pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + pGpuLock = pAllocLock; + } + else + { + if ((gpuMask & NVBIT(gpuInst)) == 0) + continue; - // now enable interrupts - _gpuLocksReleaseEnableInterrupts(gpuInst, flags); + pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + + // now enable interrupts + _gpuLocksReleaseEnableInterrupts(gpuInst, flags); + } // indicate that the API is not running NV_ASSERT(pGpuLock->threadId == threadId); @@ -1357,8 +1778,11 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) portAtomicIncrementS32(&pGpuLock->count); NV_ASSERT(pGpuLock->count <= 1); - // update gpusLockedMask - rmGpuLockInfo.gpusLockedMask &= ~NVBIT(gpuInst); + if (gpuInst != GPU_INST_ALLOC_LOCK) + { + // update gpusLockedMask + rmGpuLockInfo.gpusLockedMask &= ~NVBIT(gpuInst); + } // add release record to GPUs lock trace osGetCurrentTick(×tamp); @@ -1379,27 +1803,45 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) if (bSemaCanWake) { - NvU32 extraWakeUp; + NvU32 extraWakeUp, allocLockWakeUp; do { extraWakeUp = bug200413011_WAR_WakeUpMask; } while (!portAtomicCompareAndSwapU32(&bug200413011_WAR_WakeUpMask, 0, extraWakeUp)); + do { allocLockWakeUp = bug200413011_WAR_AllocLockWakeUp; } + while (!portAtomicCompareAndSwapU32(&bug200413011_WAR_AllocLockWakeUp, 0, allocLockWakeUp)); gpuMaskWakeup |= extraWakeUp; + if (allocLockWakeUp != 0) + { + bAllocLockWakeup = NV_TRUE; + } } // // Handle wake up(s). // - if (gpuMaskWakeup != 0) + if ((gpuMaskWakeup != 0) || bAllocLockWakeup) { if (bSemaCanWake) { - for (gpuInst = highestInstanceInGpuMask; - gpuInst != (NvU32)-1; - gpuInst--) + // Iterate over gpuInst: highestInstanceInGpuMask, ..., 0, GPU_INST_ALLOC_LOCK + for (gpuInst = _gpuInstLoopTail(highestInstanceInGpuMask); + _gpuInstLoopShouldContinue(gpuInst); + gpuInst = _gpuInstLoopPrev(gpuInst, highestInstanceInGpuMask)) { - if ((gpuMaskWakeup & NVBIT(gpuInst)) == 0) - continue; + if (gpuInst == GPU_INST_ALLOC_LOCK) + { + if (!bAllocLockWakeup) + continue; + + pGpuLock = pAllocLock; + } + else + { + if ((gpuMaskWakeup & NVBIT(gpuInst)) == 0) + continue; + + pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; + } - pGpuLock = &rmGpuLockInfo.gpuLocks[gpuInst]; if (pGpuLock->pWaitSema) portSyncSemaphoreRelease(pGpuLock->pWaitSema); else @@ -1410,26 +1852,58 @@ _rmGpuLocksRelease(NvU32 gpuMask, NvU32 flags, OBJGPU *pDpcGpu, void *ra) } else { + NvBool bDpcReleaseAll = NV_FALSE; + if (pDpcGpu == NULL) { NV_PRINTF(LEVEL_ERROR, "Releasing GPU locks (mask:0x%08x) at raised IRQL without a DPC GPU at %p. Attempting to recover..\n", gpuMask, ra); portAtomicOrU32(&bug200413011_WAR_WakeUpMask, gpuMaskWakeup); + if (bAllocLockWakeup) + { + portAtomicOrU32(&bug200413011_WAR_AllocLockWakeUp, 0x1); + } status = NV_SEMA_RELEASE_FAILED; goto done; } + + // // Use a dpc to release the locks. - NV_ASSERT((gpuMask == gpumgrGetGpuMask(pDpcGpu)) || - (gpuMask == rmGpuLockInfo.gpusLockedMask)); - if (gpuMask == gpumgrGetGpuMask(pDpcGpu)) + // + // This path can handle either: + // - releasing a single GPU lock + // - releasing all locked GPU locks + // + + if (_rmGpuAllocLockIsOwner()) { - status = osGpuLocksQueueRelease(pDpcGpu, DPC_RELEASE_SINGLE_GPU_LOCK); + // + // If GPU alloc lock is held, caller should have locked all + // GPUs, so dpc should release all. This ensures ownership of + // the GPU alloc lock is transferred properly. + // + bDpcReleaseAll = NV_TRUE; + } + if (gpuMask != gpumgrGetGpuMask(pDpcGpu)) + { + // + // If the mask being released is not a single GPU, caller + // should have locked all GPUs, so dpc should release all. + // + bDpcReleaseAll = NV_TRUE; + } + + if (bDpcReleaseAll) + { + NV_ASSERT(gpuMask == rmGpuLockInfo.gpusLockedMask); + status = osGpuLocksQueueRelease(pDpcGpu, DPC_RELEASE_ALL_GPU_LOCKS); goto done; } else { - status = osGpuLocksQueueRelease(pDpcGpu, DPC_RELEASE_ALL_GPU_LOCKS); + NV_ASSERT(gpuMask == gpumgrGetGpuMask(pDpcGpu)); + status = osGpuLocksQueueRelease(pDpcGpu, DPC_RELEASE_SINGLE_GPU_LOCK); goto done; } } @@ -1740,6 +2214,7 @@ rmDeviceGpuLockIsOwner(NvU32 gpuInst) NV_STATUS rmGpuLockSetOwner(OS_THREAD_HANDLE threadId) { + GPULOCK *pAllocLock = &rmGpuLockInfo.gpuAllocLock; GPULOCK *pGpuLock; NvU32 gpuInst; NvU32 maxLockableGpuInst; @@ -1766,6 +2241,13 @@ rmGpuLockSetOwner(OS_THREAD_HANDLE threadId) pGpuLock->threadId = threadId; } + // also set owner of the GPU alloc lock (which should have also been acquired) + if (threadId != GPUS_LOCK_OWNER_PENDING_DPC_REFRESH) + { + NV_ASSERT_OR_RETURN(pAllocLock->threadId == GPUS_LOCK_OWNER_PENDING_DPC_REFRESH, NV_ERR_INVALID_STATE); + } + pAllocLock->threadId = threadId; + return NV_OK; } @@ -1791,6 +2273,8 @@ rmGpuLockGetTimes(NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS *pParams) NV_STATUS rmDeviceGpuLockSetOwner(OBJGPU *pGpu, OS_THREAD_HANDLE threadId) { + GPULOCK *pAllocLock = &rmGpuLockInfo.gpuAllocLock; + NvBool bSetAllocLockOwner = NV_FALSE; GPULOCK *pGpuLock; NvU32 gpuInst; NvU32 gpuMask; @@ -1799,6 +2283,12 @@ rmDeviceGpuLockSetOwner(OBJGPU *pGpu, OS_THREAD_HANDLE threadId) if (pSys->getProperty(pSys, PDB_PROP_SYS_IS_GSYNC_ENABLED)) { + if (_rmGpuAllocLockIsOwner() || + ((threadId != GPUS_LOCK_OWNER_PENDING_DPC_REFRESH) && + (pAllocLock->threadId == GPUS_LOCK_OWNER_PENDING_DPC_REFRESH))) + { + bSetAllocLockOwner = NV_TRUE; + } gpuMask = rmGpuLockInfo.gpusLockedMask; } else @@ -1828,6 +2318,16 @@ rmDeviceGpuLockSetOwner(OBJGPU *pGpu, OS_THREAD_HANDLE threadId) pGpuLock->threadId = threadId; } + // also set owner of the GPU alloc lock if needed + if (bSetAllocLockOwner) + { + if (threadId != GPUS_LOCK_OWNER_PENDING_DPC_REFRESH) + { + NV_ASSERT_OR_RETURN(pAllocLock->threadId == GPUS_LOCK_OWNER_PENDING_DPC_REFRESH, NV_ERR_INVALID_STATE); + } + pAllocLock->threadId = threadId; + } + return NV_OK; } diff --git a/src/nvidia/src/kernel/core/system.c b/src/nvidia/src/kernel/core/system.c index 6ae4010399..eb5f4d5eab 100644 --- a/src/nvidia/src/kernel/core/system.c +++ b/src/nvidia/src/kernel/core/system.c @@ -56,6 +56,7 @@ #include "power/gpu_boost_mgr.h" #include "compute/fabric.h" #include "gpu_mgr/gpu_db.h" +#include "core/bin_data.h" // local static functions static NV_STATUS _sysCreateOs(OBJSYS *); @@ -93,6 +94,81 @@ static sysChildObject sysChildObjects[] = { NV_OFFSETOF(OBJSYS, pGpuDb), classInfo(GpuDb), NV_TRUE }, }; +static void +_sysDestroyMemExportCache(OBJSYS *pSys) +{ + if (pSys->pSysMemExportModuleLock != NULL) + { + portSyncRwLockDestroy(pSys->pSysMemExportModuleLock); + pSys->pSysMemExportModuleLock = NULL; + } + + NV_ASSERT(multimapCountItems(&pSys->sysMemExportCache) == 0); + + multimapDestroy(&pSys->sysMemExportCache); +} + +static NV_STATUS +_sysInitMemExportCache(OBJSYS *pSys) +{ + multimapInit(&pSys->sysMemExportCache, portMemAllocatorGetGlobalNonPaged()); + + pSys->pSysMemExportModuleLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + if (pSys->pSysMemExportModuleLock == NULL) + { + _sysDestroyMemExportCache(pSys); + return NV_ERR_NO_MEMORY; + } + + return NV_OK; +} + +static void +_sysDestroyMemExportClient(OBJSYS *pSys) +{ + RM_API *pRmApi; + + if (pSys->hSysMemExportClient == 0) + return; + + // Acquire lock to keep rmapiGetInterface() happy. + NV_ASSERT(rmapiLockAcquire(API_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_DESTROY) == NV_OK); + + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_ASSERT(pRmApi->Free(pRmApi, pSys->hSysMemExportClient, + pSys->hSysMemExportClient) == NV_OK); + + rmapiLockRelease(); + + pSys->hSysMemExportClient = 0; +} + +static NV_STATUS +_sysInitMemExportClient(OBJSYS *pSys) +{ + RM_API *pRmApi; + NV_STATUS status; + + // Acquire lock to keep rmapiGetInterface() happy. + status = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT); + if (status != NV_OK) + return status; + + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + status = pRmApi->AllocWithHandle(pRmApi, NV01_NULL_OBJECT, + NV01_NULL_OBJECT, NV01_NULL_OBJECT, + NV01_ROOT, &pSys->hSysMemExportClient, + sizeof(pSys->hSysMemExportClient)); + + rmapiLockRelease(); + + return status; +} + NV_STATUS sysConstruct_IMPL(OBJSYS *pSys) { @@ -150,10 +226,22 @@ sysConstruct_IMPL(OBJSYS *pSys) if (status != NV_OK) goto failed; + status = _sysInitMemExportCache(pSys); + if (status != NV_OK) + goto failed; + + status = _sysInitMemExportClient(pSys); + if (status != NV_OK) + goto failed; + + bindataInitialize(); + return NV_OK; failed: + _sysDestroyMemExportCache(pSys); + _sysDeleteChildObjects(pSys); g_pSys = NULL; @@ -169,6 +257,9 @@ sysConstruct_IMPL(OBJSYS *pSys) void sysDestruct_IMPL(OBJSYS *pSys) { + _sysDestroyMemExportCache(pSys); + + _sysDestroyMemExportClient(pSys); // // Any of these operations might fail but go ahead and @@ -193,6 +284,7 @@ sysDestruct_IMPL(OBJSYS *pSys) RMTRACE_DESTROY(); RMTRACE_DESTROY_NEW(); + bindataDestroy(); } // @@ -348,6 +440,11 @@ _sysRegistryOverrideResourceServer pSys->clientListDeferredFreeLimit = data32; } + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_UUID_BASED_MEMORY_SHARING, + &data32) == NV_OK) + { + pSys->bSysUuidBasedMemExportSupport = !!data32; + } } static void @@ -693,6 +790,11 @@ sysInitRegistryOverrides_IMPL pSys->setProperty(pSys, PDB_PROP_SYS_ROUTE_TO_PHYSICAL_LOCK_BYPASS, !!data32); } + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GPU_LOCK_MIDPATH, &data32) == NV_OK) + { + pSys->setProperty(pSys, PDB_PROP_SYS_GPU_LOCK_MIDPATH_ENABLED, !!data32); + } + gpumgrSetGpuNvlinkBwModeFromRegistry(pGpu); } diff --git a/src/nvidia/src/kernel/core/thread_state.c b/src/nvidia/src/kernel/core/thread_state.c index 50255109ae..1294a4fe4f 100644 --- a/src/nvidia/src/kernel/core/thread_state.c +++ b/src/nvidia/src/kernel/core/thread_state.c @@ -39,6 +39,7 @@ #include "os/os.h" #include "containers/map.h" #include "nvrm_registry.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/gpu_timeout.h" diff --git a/src/nvidia/src/kernel/diagnostics/journal.c b/src/nvidia/src/kernel/diagnostics/journal.c index e9de9c9006..1be7bb1250 100644 --- a/src/nvidia/src/kernel/diagnostics/journal.c +++ b/src/nvidia/src/kernel/diagnostics/journal.c @@ -88,13 +88,14 @@ static NvBool rcdProbeAllGpusPresent(NvU64 ip); static volatile NvS32 probeGpuRecursion = 0; #endif #endif -static NvU32 _rcdbGetOcaRecordSizeWithHeader(Journal *pRcDB, RMCD_RECORD_TYPE type); +static NvU32 _rcdbGetOcaRecordSize(Journal *pRcDB, RMCD_RECORD_TYPE type); static volatile NvS32 concurrentRingBufferAccess = 0; static volatile NvS32 assertListRecursion = 0; static void rcdbFindRingBufferForType(Journal *pRcDB, RMCD_RECORD_TYPE recType, RING_BUFFER_LOG **ppRingBuffer); static NV_STATUS _rcdbGetNocatJournalRecord(OBJRCDB* pRcdb, NvU32 id, NvBool bExactMatch, RmRCCommonJournal_RECORD** ppReturnedCommon, RM_NOCAT_JOURNAL_ENTRY** ppReturnedJournal); +static NV_STATUS _rcdbReleaseNocatJournalRecord(RM_NOCAT_JOURNAL_ENTRY* pReturnedJournal); static NV_STATUS _rcdbNocatReportAssert(OBJGPU* pGpu, RmRCCommonAssert_RECORD* pAssert); // Global flag to make sure we never re-enter the nvLog code. @@ -678,7 +679,7 @@ rcdbGetRcDiagRecBoundaries_IMPL for (i = 0; i < pRingBuffer->numEntries; ++i) { // get a pointer to the record from the buffer. - pCommon = (RmRCCommonJournal_RECORD *)(((NvU8 *)pRingBuffer->pBuffer) + (_rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport) * ((logicalStartIdx + i) % pRingBuffer->maxEntries))); + pCommon = (RmRCCommonJournal_RECORD *)(((NvU8 *)pRingBuffer->pBuffer) + (rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport) * ((logicalStartIdx + i) % pRingBuffer->maxEntries))); pRecord = (RmRcDiag_RECORD*) &(pCommon[1]); // check to see if the record qualifies @@ -741,7 +742,7 @@ rcdbGetRcDiagRecBoundaries_IMPL return status; } -NV_STATUS +RmRCCommonJournal_RECORD * rcdbAddRcDiagRec_IMPL ( OBJGPU *pGpu, @@ -749,6 +750,7 @@ rcdbAddRcDiagRec_IMPL RmRcDiag_RECORD *pRmDiagWrapBuffRec ) { + RmRCCommonJournal_RECORD *pCommon; NvU32 usec; // Create Records, then write it. @@ -763,11 +765,32 @@ rcdbAddRcDiagRec_IMPL } osGetCurrentTime(&(pRmDiagWrapBuffRec->timeStamp), &usec); - rcdbAddRecToRingBuffer(pGpu, pRcDB, RmRcDiagReport, - sizeof(RmRcDiag_RECORD), (NvU8 *) pRmDiagWrapBuffRec); + pCommon = rcdbAddRecToRingBuffer(pGpu, pRcDB, RmRcDiagReport, + sizeof(RmRcDiag_RECORD), (NvU8 *)pRmDiagWrapBuffRec); pRcDB->RcErrRptRecordsDropped |= pRcDB->RcErrRptNextIdx >= MAX_RCDB_RCDIAG_WRAP_BUFF; - return NV_OK; + return pCommon; +} + +RmRCCommonJournal_RECORD * +rcdbAddRcDiagRecFromGsp_IMPL +( + OBJGPU *pGpu, + Journal *pRcDB, + RmRCCommonJournal_RECORD *pCommonGsp, + RmRcDiag_RECORD *pRmDiagGsp +) +{ + RmRCCommonJournal_RECORD *pCommonCpu; + + pCommonCpu = rcdbAddRcDiagRec(pGpu, pRcDB, pRmDiagGsp); + if (pCommonCpu) + { + NV_ASSERT(pCommonCpu->GPUTag == pCommonGsp->GPUTag); + pCommonCpu->stateMask |= pCommonGsp->stateMask; + } + + return pCommonCpu; } NV_STATUS @@ -807,7 +830,7 @@ _rcdbInternalGetRcDiagRec i %= pRingBuffer->maxEntries; // get a pointer to the record from the buffer. - pCommon = (RmRCCommonJournal_RECORD *)(((NvU8 *)pRingBuffer->pBuffer) + (_rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport) * i)); + pCommon = (RmRCCommonJournal_RECORD *)(((NvU8 *)pRingBuffer->pBuffer) + (rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport) * i)); pRecord = (RmRcDiag_RECORD*) &(pCommon[1]); // verify we have the record that was requested. @@ -837,6 +860,7 @@ _rcdbInternalGetRcDiagRec exit: return status; } + NV_STATUS rcdbGetRcDiagRec_IMPL ( @@ -847,19 +871,23 @@ rcdbGetRcDiagRec_IMPL NvU32 processId ) { - NV_STATUS status = NV_ERR_INVALID_INDEX; + NV_STATUS status; if (ppRmDiagWrapBuffRec == NULL) { return NV_ERR_INVALID_ARGUMENT; } - // assume we will fail. + *ppRmDiagWrapBuffRec = NULL; if (portAtomicIncrementS32(&concurrentRingBufferAccess) == 1) { status = _rcdbInternalGetRcDiagRec(pRcDB, reqIdx, ppRmDiagWrapBuffRec, owner, processId); } + else + { + status = NV_ERR_BUSY_RETRY; + } portAtomicDecrementS32(&concurrentRingBufferAccess); return status; } @@ -1853,7 +1881,7 @@ rcdbInsertRingBufferToList( NvU32 recordSize; NvU32 i; - recordSize = _rcdbGetOcaRecordSizeWithHeader(pRcDB, pRingBuffer->entryType); + recordSize = rcdbGetOcaRecordSizeWithHeader(pRcDB, pRingBuffer->entryType); // // Order does not matter here because the record will be inserted into the @@ -1885,7 +1913,7 @@ rcdbInsertRingBufferCollectionToList( NvU32 recSize = pCurrentBuffer->bufferSize; NV_ASSERT(pCurrentBuffer->maxEntries * - _rcdbGetOcaRecordSizeWithHeader(pRcDB, pCurrentBuffer->entryType) == + rcdbGetOcaRecordSizeWithHeader(pRcDB, pCurrentBuffer->entryType) == pCurrentBuffer->bufferSize); if (recSize > 0) @@ -2469,7 +2497,7 @@ rcdbCreateRingBuffer_IMPL rcdbFindRingBufferForType(pRcDB, type, &pRingBuffer); - entrySize = _rcdbGetOcaRecordSizeWithHeader(pRcDB, type); + entrySize = rcdbGetOcaRecordSizeWithHeader(pRcDB, type); if (entrySize == 0) { NV_ASSERT(entrySize != 0); @@ -2642,7 +2670,7 @@ rcdbDestroyRingBuffer_IMPL ** it is assumed the caller has successfully acquired the concurrentRingBufferAccess lock. ** failure to do so can result in concurrency issues. */ -RmRCCommonJournal_RECORD* +RmRCCommonJournal_RECORD * _rcdbAllocRecFromRingBuffer ( OBJGPU *pGpu, @@ -2671,10 +2699,10 @@ _rcdbAllocRecFromRingBuffer newItemIndex = (pRingBuffer->numEntries + pRingBuffer->headIndex) % pRingBuffer->maxEntries; // prepend the rmJournalCommon record to record. - pCommon = (RmRCCommonJournal_RECORD*)(pRingBuffer->pBuffer + (_rcdbGetOcaRecordSizeWithHeader(pRcDB, type) * newItemIndex)); + pCommon = (RmRCCommonJournal_RECORD*)(pRingBuffer->pBuffer + (rcdbGetOcaRecordSizeWithHeader(pRcDB, type) * newItemIndex)); pCommon->Header.cRecordGroup = RmGroup; pCommon->Header.cRecordType = type; - pCommon->Header.wRecordSize = (NvU16)_rcdbGetOcaRecordSizeWithHeader(pRcDB, type); + pCommon->Header.wRecordSize = (NvU16)rcdbGetOcaRecordSizeWithHeader(pRcDB, type); rcdbSetCommonJournalRecord(pGpu, pCommon); // Increment the number of entries or advance the head index. @@ -2706,7 +2734,7 @@ _rcdbAllocRecFromRingBuffer ** ** notes: */ -void +RmRCCommonJournal_RECORD * rcdbAddRecToRingBuffer_IMPL ( OBJGPU *pGpu, @@ -2716,10 +2744,9 @@ rcdbAddRecToRingBuffer_IMPL NvU8 *pRecord ) { - RmRCCommonJournal_RECORD - *pCommon; + RmRCCommonJournal_RECORD *pCommon = NULL; - NV_ASSERT(recordSize == rcdbGetOcaRecordSize(pRcDB, type)); + NV_ASSERT(recordSize == _rcdbGetOcaRecordSize(pRcDB, type)); if (portAtomicIncrementS32(&concurrentRingBufferAccess) == 1) { @@ -2731,10 +2758,11 @@ rcdbAddRecToRingBuffer_IMPL } } portAtomicDecrementS32(&concurrentRingBufferAccess); + + return pCommon; } -// Non-hal function to return the sizes of records that are not chip dependent. -NvU32 rcdbGetOcaRecordSize_IMPL(Journal *pRcDB, RMCD_RECORD_TYPE type) +static NvU32 _rcdbGetOcaRecordSize(Journal *pRcDB, RMCD_RECORD_TYPE type) { switch(type) { @@ -2748,11 +2776,12 @@ NvU32 rcdbGetOcaRecordSize_IMPL(Journal *pRcDB, RMCD_RECORD_TYPE type) return 0; } } -static NvU32 _rcdbGetOcaRecordSizeWithHeader(Journal *pRcDB, RMCD_RECORD_TYPE type) + +NvU32 rcdbGetOcaRecordSizeWithHeader_IMPL(Journal *pRcDB, RMCD_RECORD_TYPE type) { NvU32 recSz; - recSz = rcdbGetOcaRecordSize(pRcDB, type); + recSz = _rcdbGetOcaRecordSize(pRcDB, type); if (0 < recSz) { recSz += sizeof(RmRCCommonJournal_RECORD); @@ -2767,7 +2796,6 @@ static NvU32 _rcdbGetOcaRecordSizeWithHeader(Journal *pRcDB, RMCD_RECORD_TYPE ty return NV_ALIGN_UP(recSz, 8); } - NV_STATUS rcdbAddRmGpuDump ( @@ -3252,6 +3280,7 @@ RM_NOCAT_JOURNAL_ENTRY* _rcdbAllocNocatJournalRecord portMemSet(pNocatEntry, 0, sizeof(*pNocatEntry)); pNocatEntry->id = pDesc->nextRecordId++; pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX]++; + portAtomicIncrementS32(&pNocatEntry->inUse); } else { @@ -3337,7 +3366,7 @@ _rcdbGetNocatJournalRecord // we can't return a record. if ((pDesc->nextRecordId - pDesc->nextReportedId) == 0) { - pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX]++; + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX]++; return NV_ERR_OBJECT_NOT_FOUND; } @@ -3345,7 +3374,7 @@ _rcdbGetNocatJournalRecord rcdbFindRingBufferForType(pRcdb, RmNocatReport, &pRingBuffer); if (pRingBuffer == NULL) { - pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX]++; + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX]++; return NV_ERR_OBJECT_NOT_FOUND; } // determine how far back from the head our record should be. @@ -3361,21 +3390,27 @@ _rcdbGetNocatJournalRecord { // back out the offset from the newest/empty record. idx += pRingBuffer->numEntries - offset; + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX]++; } else if (bExactMatch) { // the record is not in the buffer, & we weren't asked for the closest match. - pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MISSED_IDX]++; + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX]++; return NV_ERR_OBJECT_NOT_FOUND; } + else + { + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX]++; + } // wrap the idx to the current size of the buffer. idx %= pRingBuffer->numEntries; // get a pointer to the common record & the record from the buffer. - pCommon = (RmRCCommonJournal_RECORD*)(((NvU8*)pRingBuffer->pBuffer) + (_rcdbGetOcaRecordSizeWithHeader(pRcdb, RmNocatReport) * idx)); + pCommon = (RmRCCommonJournal_RECORD*)(((NvU8*)pRingBuffer->pBuffer) + (rcdbGetOcaRecordSizeWithHeader(pRcdb, RmNocatReport) * idx)); // get a pointer to the data that follows the common header, that is the record data. pNocatEntry = (RM_NOCAT_JOURNAL_ENTRY*)(((NvU8*)pCommon) + sizeof(RmRCCommonJournal_RECORD)); + portAtomicIncrementS32(&pNocatEntry->inUse); // pass the record along if (ppReturnedCommon != NULL) @@ -3388,6 +3423,43 @@ _rcdbGetNocatJournalRecord } return NV_OK; } +/* +** _rcdbGetNocatJournalRecord returns a pointer to the requested record, +** or optionally the oldest record if the requested one is not available. +** +** parameters: +** pRcdb a pointer toe the Journal that contains the ring buffers +** id id of the record we are looking for +** bExactMatch indicates if we want an exact match, or the closest record. +** ppCommon a pointer to a pointer that will hold the pointer to +** the common part of the record. +** this can be NULL +** ppReturnedNocatEntry +** a pointer to a pointer that will hold the pointer to +** the nocat part of the record +** this can be NULL +** +** notes: +** it is assumed the caller has successfully acquired the concurrentRingBufferAccess lock. +** the lock should be held until access the buffer is completed. +** failure to do so can result in concurrency issues. +*/ +NV_STATUS +_rcdbReleaseNocatJournalRecord +( + RM_NOCAT_JOURNAL_ENTRY *pNocatEntry +) +{ + if (pNocatEntry == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + if (portAtomicDecrementS32(&pNocatEntry->inUse) != 0) + { + return NV_ERR_BUSY_RETRY; + } + return NV_OK; +} /* ** _rcdbGetNewestNocatJournalRecordForType returns a pointer to the newest record for the @@ -3507,14 +3579,16 @@ rcdbReportNextNocatJournalEntry pReturnedNocatEntry->nocatJournalEntry = pNocatEntry->nocatJournalEntry; // check if we lost any records. - pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES1_IDX] += + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX] += pNocatEntry->id - pDesc->nextReportedId; // update the NocatJournalNextReportedId pDesc->nextReportedId = pNocatEntry->id + 1; pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX]++; + _rcdbReleaseNocatJournalRecord(pNocatEntry); status = NV_OK; + } } else @@ -3523,9 +3597,10 @@ rcdbReportNextNocatJournalEntry status = NV_ERR_BUSY_RETRY; } portAtomicDecrementS32(&concurrentRingBufferAccess); - if (pRcdb->nocatJournalDescriptor.journalLocked) + if ((pRcdb->nocatJournalDescriptor.lockTimestamp != 0) && (rcdbGetNocatOutstandingCount(pRcdb) == 0)) { - pRcdb->nocatJournalDescriptor.journalLocked = rcdbGetNocatOutstandingCount(pRcdb) > 0; + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX]++; + pRcdb->nocatJournalDescriptor.lockTimestamp = 0; } return status; } @@ -3585,7 +3660,7 @@ _rcdbSendNocatJournalNotification OBJGPU *pGpu, Journal *pRcdb, NvU32 posted, - RmRCCommonJournal_RECORD *pCommon, + RmRCCommonJournal_RECORD *pCommon, // todo: pass in timestamp instead of common. NvU32 type ) { @@ -3601,7 +3676,7 @@ _rcdbSendNocatJournalNotification pCommon->timeStamp); // count the number of notifications. - pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX]++; + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX]++; return NV_OK; } @@ -3703,8 +3778,9 @@ void rcdbCleanupNocatGpuCache_IMPL(OBJGPU *pGpu) } + /* -** rcdbNocatPostError records a reported NOCAT error +** rcdbNocatInsertNocatError records a reported NOCAT error ** ** parameters: ** pGpu Pointer to GPU associated with the error @@ -3720,7 +3796,6 @@ rcdbNocatInsertNocatError( { OBJSYS *pSys = SYS_GET_INSTANCE(); Journal *pRcdb = SYS_GET_RCDB(pSys); - NvBool bInsertRecord; #if(NOCAT_PROBE_FB_MEMORY) NvBool bCheckFBState = NV_FALSE; #endif @@ -3730,7 +3805,7 @@ rcdbNocatInsertNocatError( const char *pSource = NULL; NvU32 diagBufferLen = 0; const char *pFaultingEngine = NULL; - + NvBool postRecord; // validate inputs. if (pRcdb == NULL) { @@ -3742,6 +3817,14 @@ rcdbNocatInsertNocatError( pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX]++; return 0; } + // assign a timestamp if none was provided + if (pNewEntry->timestamp == 0) + { + pNewEntry->timestamp = osGetTimestamp(); + } + + // initially set postRecord based on the current state of the lock; + postRecord = pRcdb->nocatJournalDescriptor.lockTimestamp == 0; // perform any record type specific setup switch (pNewEntry->recType) @@ -3754,38 +3837,58 @@ rcdbNocatInsertNocatError( case NV2080_NOCAT_JOURNAL_REC_TYPE_TDR: // lock the journal so we don't wrap over the record we are inserting. - bInsertRecord = NV_TRUE; - pRcdb->nocatJournalDescriptor.journalLocked = NV_TRUE; + if (pRcdb->nocatJournalDescriptor.lockTimestamp == 0) + { + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX]++; + } + else + { + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX]++; + } + + pRcdb->nocatJournalDescriptor.lockTimestamp = pNewEntry->timestamp; + postRecord = NV_TRUE; break; case NV2080_NOCAT_JOURNAL_REC_TYPE_RC: #if(NOCAT_PROBE_FB_MEMORY) bCheckFBState = NV_TRUE; #endif - // check if we should insert the record - bInsertRecord = !pRcdb->nocatJournalDescriptor.journalLocked; + // set the source pSource = "RC Error"; break; case NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT: - // check if we should insert the record - bInsertRecord = !pRcdb->nocatJournalDescriptor.journalLocked; - + // set the source pSource = "ASSERT"; break; case NV2080_NOCAT_JOURNAL_REC_TYPE_ENGINE: - // check if we should insert the record - bInsertRecord = !pRcdb->nocatJournalDescriptor.journalLocked; break; case NV2080_NOCAT_JOURNAL_REC_TYPE_UNKNOWN: default: - return NV_FALSE; + return 0; break; } - if (bInsertRecord) + // check if we should post the record when locked. + if (!postRecord) + { + if ((NvS64)(pNewEntry->timestamp - pRcdb->nocatJournalDescriptor.lockTimestamp) < 0) + { + // the record predates the lock, so it's Grandfathered in. + postRecord = NV_TRUE; + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_GRANDFATHERED_RECORD_IDX]++; + } + else + { + // we are dropping the record, count that. + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX]++; + } + } + if (postRecord) { + // is the buffer available? if (portAtomicIncrementS32(&concurrentRingBufferAccess) == 1) { // start recording this new record by allocating a record from the buffer. @@ -3794,6 +3897,9 @@ rcdbNocatInsertNocatError( { pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX]++; + // update the time stamp to the one supplied. + pCommon->timeStamp = pNewEntry->timestamp; + // save the record Id for the type. pRcdb->nocatJournalDescriptor.lastRecordId[pNewEntry->recType] = pRcdb->nocatJournalDescriptor.lastRecordId[NV2080_NOCAT_JOURNAL_REC_TYPE_ANY] = @@ -3885,32 +3991,30 @@ rcdbNocatInsertNocatError( _rcdbSetTdrReason(pRcdb, pNewEntry->tdrReason, (char*)pNocatEntry->nocatJournalEntry.tdrReason, sizeof(pNocatEntry->nocatJournalEntry.tdrReason)); + + _rcdbReleaseNocatJournalRecord(pNocatEntry); } else { + // record was not allocated, bail. + postRecord = NV_FALSE; pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX]++; } } else { // we are busy, so we can't insert the record, count the record as dropped & count the busy. + postRecord = NV_FALSE; pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX]++; - pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX]++; - bInsertRecord = NV_FALSE; } portAtomicDecrementS32(&concurrentRingBufferAccess); } - else - { - // we are dropping the record, count that. - pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_REQ_DROPPED_IDX]++; - } + // no matter what happened, trigger the event to indicate a record was processed. - _rcdbSendNocatJournalNotification(pGpu, pRcdb, bInsertRecord, pCommon, pNewEntry->recType); + _rcdbSendNocatJournalNotification(pGpu, pRcdb, postRecord, pCommon, pNewEntry->recType); return id; } - /* ** rcdbNocatInsertBugcheck is the interface to record a bugcheck NOCAT report ** @@ -3992,27 +4096,6 @@ rcdbNocatInsertEngineError( return rcdbNocatInsertNocatError(pGpu, &newEntry); } -/* -** rcdbNocatInitEngineErrorEvent initializes a parameter structure for an engine error event -** -** parameters: -** pNewEntry Pointer to event parameter structure to be initialized -*/ -NV_STATUS -rcdbNocatInitTDRErrorEvent -( - NOCAT_JOURNAL_PARAMS *pNewEntry -) -{ - if (pNewEntry == NULL) - { - return NV_ERR_INVALID_ARGUMENT; - } - portMemSet(pNewEntry, 0, sizeof(*pNewEntry)); - pNewEntry->recType = NV2080_NOCAT_JOURNAL_REC_TYPE_TDR; - return NV_OK; -} - /* ** rcdbNocatInsertTDRError records an TDR error, ** @@ -4049,7 +4132,8 @@ rcdbNocatInsertTDRError { NOCAT_JOURNAL_PARAMS newEntry; - rcdbNocatInitTDRErrorEvent(&newEntry); + portMemSet(&newEntry, 0, sizeof(newEntry)); + newEntry.recType = NV2080_NOCAT_JOURNAL_REC_TYPE_TDR; newEntry.pSource = pSource; newEntry.subsystem = subsystem; newEntry.errorCode = errorCode; @@ -4117,6 +4201,7 @@ _rcdbNocatReportAssert // start off assuming we will be recording a report portMemSet(&newEntry, 0, sizeof(newEntry)); + newEntry.timestamp = pAssertRec->common.timeStamp; newEntry.recType = NV2080_NOCAT_JOURNAL_REC_TYPE_ASSERT; newEntry.pSource = "ASSERT"; @@ -4167,6 +4252,8 @@ _rcdbNocatReportAssert pDiagData = (RM_NOCAT_ASSERT_DIAG_BUFFER*)&pNocatEntry->nocatJournalEntry.diagBuffer; pDiagData->count++; } + _rcdbReleaseNocatJournalRecord(pNocatEntry); + } } else @@ -4257,6 +4344,7 @@ NV_STATUS rcdbSetNocatTdrReason (char *)pNocatEntry->nocatJournalEntry.tdrReason, sizeof(pNocatEntry->nocatJournalEntry.tdrReason)); pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX]++; + _rcdbReleaseNocatJournalRecord(pNocatEntry); } } portAtomicDecrementS32(&concurrentRingBufferAccess); diff --git a/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c b/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c index b5f3bc5e2e..7db1180f18 100644 --- a/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c +++ b/src/nvidia/src/kernel/diagnostics/nv_debug_dump.c @@ -177,6 +177,7 @@ nvdEngineDumpCallbackHelper { NV_STATUS nvStatus = NV_OK; NvU8 startingDepth = prbEncNestingLevel(pPrbEnc); + OBJSYS *pSys = SYS_GET_INSTANCE(); if (!IS_GSP_CLIENT(pGpu) || !FLD_TEST_REF(NVD_ENGINE_FLAGS_SOURCE, _GSP, pEngineCallback->flags)) @@ -192,7 +193,8 @@ nvdEngineDumpCallbackHelper } if (IS_GSP_CLIENT(pGpu) && - !FLD_TEST_REF(NVD_ENGINE_FLAGS_SOURCE, _CPU, pEngineCallback->flags)) + !FLD_TEST_REF(NVD_ENGINE_FLAGS_SOURCE, _CPU, pEngineCallback->flags) && + !pSys->getProperty(pSys, PDB_PROP_SYS_IN_OCA_DATA_COLLECTION)) { NV_RM_RPC_DUMP_PROTOBUF_COMPONENT(pGpu, nvStatus, pPrbEnc, pNvDumpState, pEngineCallback->engDesc); diff --git a/src/nvidia/src/kernel/diagnostics/nvlog.c b/src/nvidia/src/kernel/diagnostics/nvlog.c index c75d185edc..e1527a3338 100644 --- a/src/nvidia/src/kernel/diagnostics/nvlog.c +++ b/src/nvidia/src/kernel/diagnostics/nvlog.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/diagnostics/nvlog_printf.c b/src/nvidia/src/kernel/diagnostics/nvlog_printf.c index 6dfbb484ec..d031c8bfe2 100644 --- a/src/nvidia/src/kernel/diagnostics/nvlog_printf.c +++ b/src/nvidia/src/kernel/diagnostics/nvlog_printf.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2002-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2002-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -225,11 +225,7 @@ _nvDbgPrepareString #if PORT_IS_FUNC_SUPPORTED(portDbgExPrintfLevel) static NvU32 _nvDbgLevelToPlatformLevel(NvBool bForce, NvU32 level) { -#if NVOS_IS_UNIX - return level; -#else return bForce ? LEVEL_FATAL : level; -#endif } #endif @@ -1287,7 +1283,7 @@ nvDbgRmMsgCheck // RmMsgPrefix - Add the RmMsg prefix to the passed in string, returning // the length of the formatted string. // -// Format: "NVRM file linenum function timestamp: " +// Format: "NVRM: file linenum function timestamp: " // NvU32 RmMsgPrefix @@ -1310,7 +1306,8 @@ RmMsgPrefix { portStringCopy(str + len, totalLen - len, NV_PRINTF_PREFIX, sizeof(NV_PRINTF_PREFIX)); len += sizeof(NV_PRINTF_PREFIX) - 1; - space = " "; + portStringCopy(str + len, totalLen - len, NV_PRINTF_PREFIX_SEPARATOR, sizeof(NV_PRINTF_PREFIX_SEPARATOR)); + len += sizeof(NV_PRINTF_PREFIX_SEPARATOR) - 1; } if (prefix & NVRM_MSG_PREFIX_FILE) diff --git a/src/nvidia/src/kernel/disp/nvfbc_session.c b/src/nvidia/src/kernel/disp/nvfbc_session.c new file mode 100644 index 0000000000..7a95f55bfb --- /dev/null +++ b/src/nvidia/src/kernel/disp/nvfbc_session.c @@ -0,0 +1,338 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "os/os.h" +#include "gpu_mgr/gpu_mgr.h" +#include "rmconfig.h" + +#include "vgpu/rpc.h" +#include "disp/nvfbc_session.h" +#include "rmapi/rs_utils.h" +#include "gpu/gpu.h" +#include "ctrl/ctrla0bd.h" + +#include "virtualization/hypervisor/hypervisor.h" + +#define NVFBC_SESSION_INVALIDATE_DATA_TIMEOUT 2000000000 // nano second granularity, 2 seconds + +static NvU32 sessionCounter = 0x01; + +NvBool nvfbcIsSessionDataStale(NvU64 lastUpdateTimeStamp) +{ + NvU64 currTime = 0; + + osGetPerformanceCounter(&currTime); + + if ((currTime >= lastUpdateTimeStamp) && + ((currTime - lastUpdateTimeStamp) >= NVFBC_SESSION_INVALIDATE_DATA_TIMEOUT)) + { + return NV_TRUE; + } + return NV_FALSE; +} + +NV_STATUS +nvfbcsessionConstruct_IMPL +( + NvfbcSession *pNvfbcSession, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NVA0BD_ALLOC_PARAMETERS *pNvA0BDAllocParams = pParams->pAllocParams; + PNVFBC_SESSION_LIST_ITEM pNvfbcSessionListItem = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pNvfbcSession); + RsClient *pRsClient = pCallContext->pClient; + NvHandle hClient = pRsClient->hClient; + RmClient *pClient; + NV_STATUS status = NV_OK; + + if (listCount(&(pGpu->nvfbcSessionList)) >= NV2080_GPU_NVFBC_MAX_SESSION_COUNT) + { + NV_PRINTF(LEVEL_WARNING, + "Creating NVFBC session above max session limit.\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + pClient = serverutilGetClientUnderLock(hClient); + if (pClient == NULL) + { + return NV_ERR_INVALID_CLIENT; + } + + if (IS_VIRTUAL(pGpu)) + { + NV_RM_RPC_ALLOC_OBJECT(pGpu, + pParams->hClient, + pParams->hParent, + pParams->hResource, + pParams->externalClassId, + pNvA0BDAllocParams, + sizeof(*pNvA0BDAllocParams), + status); + + if (status != NV_OK) + { + goto done; + } + } + + pNvfbcSessionListItem = listAppendNew(&(pGpu->nvfbcSessionList)); + if (pNvfbcSessionListItem == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pNvfbcSessionListItem, 0, sizeof(NVFBC_SESSION_LIST_ITEM)); + + /* + * When this class is allocated for NMOS or vGPU VM, vgpuInstanceId will be 0x00. + */ + + if (hypervisorIsVgxHyper()) + { + if (IS_GSP_CLIENT(pGpu)) { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + } + else + { + pNvfbcSession->nvfbcSessionEntry.vgpuInstanceId = 0; + pNvfbcSession->nvfbcSessionEntry.processId = pClient->ProcID; + } + + pNvfbcSession->nvfbcSessionEntry.sessionId = sessionCounter++; + pNvfbcSession->nvfbcSessionEntry.displayOrdinal = pNvA0BDAllocParams->displayOrdinal; + pNvfbcSession->nvfbcSessionEntry.sessionType = pNvA0BDAllocParams->sessionType; + + pNvfbcSession->nvfbcSessionEntry.sessionFlags = + FLD_TEST_DRF(A0BD_, NVFBC_SESSION_FLAG_DIFFMAP, _ENABLED, _TRUE, pNvA0BDAllocParams->sessionFlags) ? + NV2080_CTRL_NVFBC_SESSION_FLAG_DIFFMAP_ENABLED : 0; + pNvfbcSession->nvfbcSessionEntry.sessionFlags |= + FLD_TEST_DRF(A0BD_, NVFBC_SESSION_FLAG_CLASSIFICATIONMAP, _ENABLED, _TRUE, pNvA0BDAllocParams->sessionFlags) ? + NV2080_CTRL_NVFBC_SESSION_FLAG_CLASSIFICATIONMAP_ENABLED : 0; + + pNvfbcSession->nvfbcSessionEntry.hMaxResolution = pNvA0BDAllocParams->hMaxResolution; + pNvfbcSession->nvfbcSessionEntry.vMaxResolution = pNvA0BDAllocParams->vMaxResolution; + pNvfbcSession->nvfbcSessionEntry.averageFPS = 0; + pNvfbcSession->nvfbcSessionEntry.averageLatency = 0; + pNvfbcSession->nvfbcSessionEntry.lastUpdateTimeStamp = SESSION_UPDATE_TIMESTAMP_UNINITIALIZED; + + pNvfbcSessionListItem->hClient = hClient; + pNvfbcSessionListItem->sessionPtr = pNvfbcSession; + +done: + if (status != NV_OK && pNvfbcSessionListItem != NULL) + { + listRemove(&(pGpu->nvfbcSessionList), pNvfbcSessionListItem); + } + + return status; +} + +void +nvfbcsessionDestruct_IMPL +( + NvfbcSession *pNvfbcSession +) +{ + RS_RES_FREE_PARAMS_INTERNAL *pParams; + PNVFBC_SESSION_LIST_ITEM pNvfbcSessionListItem = NULL; + PNVFBC_SESSION_LIST_ITEM pNvfbcSessionListItemNext = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pNvfbcSession); + CALL_CONTEXT *pCallContext; + RsClient *pRsClient; + NvHandle hClient; + NvHandle hParent; + NvHandle hNvfbcSessionHandle; + NV_STATUS status = NV_OK; + + resGetFreeParams(staticCast(pNvfbcSession, RsResource), &pCallContext, &pParams); + + pRsClient = pCallContext->pClient; + hClient = pRsClient->hClient; + hParent = pCallContext->pResourceRef->pParentRef->hResource; + hNvfbcSessionHandle = pCallContext->pResourceRef->hResource; + + if (IS_VIRTUAL(pGpu)) + { + NV_RM_RPC_FREE(pGpu, hClient, hParent, hNvfbcSessionHandle, status); + NV_ASSERT(NV_OK == status); + } + + for (pNvfbcSessionListItem = listHead(&(pGpu->nvfbcSessionList)); + pNvfbcSessionListItem != NULL; + pNvfbcSessionListItem = pNvfbcSessionListItemNext) + { + pNvfbcSessionListItemNext = listNext(&(pGpu->nvfbcSessionList), pNvfbcSessionListItem); + if (pNvfbcSessionListItem != NULL && (pNvfbcSessionListItem->sessionPtr == pNvfbcSession)) + { + listRemove(&(pGpu->nvfbcSessionList), pNvfbcSessionListItem); + } + } + + pParams->status = status; +} + +NV_STATUS +nvfbcsessionCtrlCmdNvFBCSwSessionUpdateInfo_IMPL +( + NvfbcSession *pNvfbcSession, + NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS *pParams +) +{ + NVA0BD_CTRL_NVFBC_TIMESTAMP *pTimeStampBuffer = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pNvfbcSession); + NvU32 i; + NvU64 startTime; + NvU64 endTime; + NvU32 totalEntries; + NvU64 localAverageLatency; + NvU64 localAverageFPS; + NvU64 timeToCapture = 0; + NV_STATUS status = NV_OK; + + NV_PRINTF(LEVEL_INFO, "Enter function\n"); + + NV_ASSERT_OR_RETURN((pParams != NULL), NV_ERR_INVALID_POINTER); + + pNvfbcSession->nvfbcSessionEntry.hResolution = pParams->hResolution; + pNvfbcSession->nvfbcSessionEntry.vResolution = pParams->vResolution; + pNvfbcSession->nvfbcSessionEntry.totalGrabCalls = pParams->totalGrabCalls; + + // Clear out previous NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_xxx flag. + pNvfbcSession->nvfbcSessionEntry.sessionFlags &= ~(NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT | + NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE | + NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT); + // Find and assign NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_xxx flag. + switch (pParams->captureCallFlags) + { + case NVA0BD_NVFBC_WITH_WAIT_FALSE: + pNvfbcSession->nvfbcSessionEntry.sessionFlags |= NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_NO_WAIT; + break; + case NVA0BD_NVFBC_WITH_WAIT_INFINITE: + pNvfbcSession->nvfbcSessionEntry.sessionFlags |= NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_INFINITE; + break; + case NVA0BD_NVFBC_WITH_WAIT_TIMEOUT: + pNvfbcSession->nvfbcSessionEntry.sessionFlags |= NV2080_CTRL_NVFBC_SESSION_FLAG_CAPTURE_WITH_WAIT_TIMEOUT; + break; + } + + NV_ASSERT(pParams->timestampEntryCount <= NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES); + if (pParams->timestampEntryCount > NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES) + { + pParams->timestampEntryCount = NVA0BD_CTRL_CMD_NVFBC_MAX_TIMESTAMP_ENTRIES; + } + + if (pParams->timestampEntryCount != 0) + { + pTimeStampBuffer = pParams->timestampEntry; + + // Calculate Average Latency. + for (i = 0; i < pParams->timestampEntryCount; i++) + { + if (pTimeStampBuffer[i].startTime > pTimeStampBuffer[i].endTime) + { + timeToCapture += ((0xFFFFFFFFFFFFFFFFULL - pTimeStampBuffer[i].startTime) + pTimeStampBuffer[i].endTime); + } + else + { + timeToCapture += pTimeStampBuffer[i].endTime - pTimeStampBuffer[i].startTime; + } + } + + localAverageLatency = timeToCapture / pParams->timestampEntryCount; + // Mask with 0xFFFFFFFF since it should not be greater than 32bit range. + NV_ASSERT(localAverageLatency < 0xFFFFFFFF); + pNvfbcSession->nvfbcSessionEntry.averageLatency = localAverageLatency < 0xFFFFFFFF ? + (localAverageLatency & 0xFFFFFFFF) : + 0xFFFFFFFF; + + // Calculate Average FPS. + // Formula used to calculate FPS : n-1/(lastFrameTimestamp.startTime - firstFrameTimestamp.startTime) + // n is the total no of entries. + // If there is only one entry, we need to use firstFrameTimestamp.endtime as endTime. + startTime = pTimeStampBuffer[0].startTime; + if (pParams->timestampEntryCount > 1) + { + endTime = pTimeStampBuffer[pParams->timestampEntryCount - 1].startTime; + totalEntries = pParams->timestampEntryCount - 1; + } + else + { + endTime = pTimeStampBuffer[0].endTime; + totalEntries = pParams->timestampEntryCount; + } + + if (endTime >= startTime) + { + timeToCapture = endTime - startTime; + } + else + { + timeToCapture = (0xFFFFFFFFFFFFFFFFULL - startTime) + endTime; + } + + if (timeToCapture) + { + localAverageFPS = ((totalEntries * 1000 * 1000) / timeToCapture); + // Mask with 0xFFFFFFFF since it should not be greater than 32bit range. + NV_ASSERT(localAverageFPS < 0xFFFFFFFF); + pNvfbcSession->nvfbcSessionEntry.averageFPS = localAverageFPS < 0xFFFFFFFF ? + (localAverageFPS & 0xFFFFFFFF) : 0xFFFFFFFF; + } + else + { + pNvfbcSession->nvfbcSessionEntry.averageFPS = 0; + } + } + else + { + pNvfbcSession->nvfbcSessionEntry.averageLatency = pParams->averageLatency; + pNvfbcSession->nvfbcSessionEntry.averageFPS = pParams->averageFPS; + } + osGetPerformanceCounter(&pNvfbcSession->nvfbcSessionEntry.lastUpdateTimeStamp); + + if (IS_VIRTUAL(pGpu)) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + NVA0BD_CTRL_NVFBC_SW_SESSION_UPDATE_INFO_PARAMS rpcParams = { 0 }; + + rpcParams.hResolution = pParams->hResolution; + rpcParams.vResolution = pParams->vResolution; + rpcParams.captureCallFlags = pParams->captureCallFlags; + rpcParams.totalGrabCalls = pParams->totalGrabCalls; + rpcParams.averageLatency = pNvfbcSession->nvfbcSessionEntry.averageLatency; + rpcParams.averageFPS = pNvfbcSession->nvfbcSessionEntry.averageFPS; + rpcParams.timestampEntryCount = 0; + + NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, + &rpcParams, pRmCtrlParams->paramsSize, status); + } + + return status; +} + diff --git a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c index 8c288c1328..a4886fd8c8 100644 --- a/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c +++ b/src/nvidia/src/kernel/gpu/arch/ada/kern_gpu_ad102.c @@ -66,6 +66,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_AD102[] = GPU_CHILD_PRESENT(KernelFifo, 1), GPU_CHILD_PRESENT(KernelGmmu, 1), GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelHwpm, 1), GPU_CHILD_PRESENT(KernelMc, 1), GPU_CHILD_PRESENT(SwIntr, 1), GPU_CHILD_PRESENT(KernelNvlink, 1), diff --git a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c index d8a1137aaa..aa647ece9b 100644 --- a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +++ b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c @@ -24,12 +24,62 @@ #include "gpu/gpu.h" #include "gpu/gpu_child_class_defs.h" #include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "gpu/mem_mgr/mem_mgr.h" #include "published/ampere/ga100/dev_fb.h" #include "published/ampere/ga100/dev_vm.h" #include "published/ampere/ga100/dev_fuse.h" #include "virtualization/hypervisor/hypervisor.h" +// Error containment error id string description. +const char *ppErrContErrorIdStr[] = NV_ERROR_CONT_ERR_ID_STRING_PUBLIC; + +// Error containment table +NV_ERROR_CONT_STATE_TABLE g_errContStateTable[] = NV_ERROR_CONT_STATE_TABLE_SETTINGS; + +/*! + * @brief Get index of specified errorCode in the Error Containment state table + * + * @param[in] pGpu OBJGPU pointer + * @param[in] errorCode Error Containment error code + * @param[in] pTableIndex Index of specified errorCode in the Error Containment State table + * + * @returns NV_STATUS + */ +static NV_STATUS _gpuGetErrorContStateTableIndex_GA100(OBJGPU *pGpu, + NV_ERROR_CONT_ERR_ID errorCode, + NvU32 *pTableIndex); + +/*! + * @brief Send NV2080_NOTIFIER* + * + * @param[in] pGpu OBJGPU pointer + * @param[in] errorCode Error Containment error code + * @param[in] loc Location, SubLocation information + * @param[in] nv2080Notifier NV2080_NOTIFIER* + * + * @returns NV_STATUS + */ +static NV_STATUS _gpuNotifySubDeviceEventNotifier_GA100(OBJGPU *pGpu, + NV_ERROR_CONT_ERR_ID errorCode, + NV_ERROR_CONT_LOCATION loc, + NvU32 nv2080Notifier); + +/*! + * @brief Generate error log for corresponding error containment error code. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] errorCode Error Containment error code + * @param[in] loc Location, SubLocation information + * @param[in] pErrorContSmcSetting Error containment SMC Disable / Enable settings + * + * @returns NV_STATUS + */ +static NV_STATUS _gpuGenerateErrorLog_GA100(OBJGPU *pGpu, + NV_ERROR_CONT_ERR_ID errorCode, + NV_ERROR_CONT_LOCATION loc, + NV_ERROR_CONT_SMC_DIS_EN_SETTING *pErrorContSmcSetting); + /*! * @brief Read fuse for display supported status. * Some chips not marked displayless do not support display @@ -158,6 +208,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA100[] = GPU_CHILD_PRESENT(KernelFifo, 1), GPU_CHILD_PRESENT(KernelGmmu, 1), GPU_CHILD_PRESENT(KernelGraphics, 8), + GPU_CHILD_PRESENT(KernelHwpm, 1), GPU_CHILD_PRESENT(KernelMc, 1), GPU_CHILD_PRESENT(SwIntr, 1), GPU_CHILD_PRESENT(KernelNvlink, 1), @@ -208,6 +259,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GA102[] = GPU_CHILD_PRESENT(KernelFifo, 1), GPU_CHILD_PRESENT(KernelGmmu, 1), GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelHwpm, 1), GPU_CHILD_PRESENT(KernelMc, 1), GPU_CHILD_PRESENT(SwIntr, 1), GPU_CHILD_PRESENT(KernelNvlink, 1), @@ -225,3 +277,390 @@ gpuGetChildrenPresent_GA102(OBJGPU *pGpu, NvU32 *pNumEntries) return gpuChildrenPresent_GA102; } +/*! @brief Returns if a P2P object is allocated in SRIOV mode. + * + * @param[in] pGpu OBJGPU pointer + * + * @returns for baremetal, this should just return NV_TRUE + for SRIOV, return the SRIOV Info + */ +NvBool +gpuCheckIsP2PAllocated_GA100 +( + OBJGPU *pGpu +) +{ + if (!IS_VIRTUAL(pGpu) && !gpuIsSriovEnabled(pGpu)) + return NV_TRUE; + + return pGpu->sriovState.bP2PAllocated; +} + +/*! + * @brief Get index of specified errorCode in the Error Containment state table + * + * @param[in] pGpu OBJGPU pointer + * @param[in] errorCode Error Containment error code + * @param[in] pTableIndex Index of specified errorCode in the Error Containment state table + * + * @returns NV_STATUS + */ +static +NV_STATUS +_gpuGetErrorContStateTableIndex_GA100 +( + OBJGPU *pGpu, + NV_ERROR_CONT_ERR_ID errorCode, + NvU32 *pTableIndex +) +{ + NvU32 index; + NvU32 tableSize = NV_ARRAY_ELEMENTS(g_errContStateTable); + + NV_ASSERT_OR_RETURN(pTableIndex != NULL, NV_ERR_INVALID_ARGUMENT); + + for (index = 0; index < tableSize; index++) + { + if (errorCode == g_errContStateTable[index].errorCode) + { + *pTableIndex = index; + return NV_OK; + } + } + + return NV_ERR_INVALID_ARGUMENT; +} + +/*! + * @brief Send NV2080_NOTIFIER* + * + * @param[in] pGpu OBJGPU pointer + * @param[in] errorCode Error Containment error code + * @param[in] loc Location, SubLocation information + * @param[in] nv2080Notifier NV2080_NOTIFIER* + * + * @returns NV_STATUS + */ +static +NV_STATUS +_gpuNotifySubDeviceEventNotifier_GA100 +( + OBJGPU *pGpu, + NV_ERROR_CONT_ERR_ID errorCode, + NV_ERROR_CONT_LOCATION loc, + NvU32 nv2080Notifier +) +{ + NvV16 info16 = 0; + NvV32 info32 = 0; + RM_ENGINE_TYPE localRmEngineType = 0; + + // Return if no notifier needs to be sent for this errorCode. + if (nv2080Notifier == NO_NV2080_NOTIFIER) + { + return NV_OK; + } + + switch (errorCode) + { + // Intentional fall-through + case NV_ERROR_CONT_ERR_ID_E01_FB_ECC_DED: + case NV_ERROR_CONT_ERR_ID_E02_FB_ECC_DED_IN_CBC_STORE: + case NV_ERROR_CONT_ERR_ID_E09_FBHUB_POISON: + case NV_ERROR_CONT_ERR_ID_E20_XALEP_POISON: + info16 = FB_MEMORY_ERROR; + break; + + // Intentional fall-through + case NV_ERROR_CONT_ERR_ID_E05_LTC_ECC_DSTG: + case NV_ERROR_CONT_ERR_ID_E06_LTC_UNSUPPORTED_CLIENT_POISON: + case NV_ERROR_CONT_ERR_ID_E07_LTC_ECC_TSTG: + case NV_ERROR_CONT_ERR_ID_E08_LTC_ECC_RSTG: + info16 = LTC_ERROR; + break; + + case NV_ERROR_CONT_ERR_ID_E10_SM_POISON: + case NV_ERROR_CONT_ERR_ID_E16_GCC_POISON: + case NV_ERROR_CONT_ERR_ID_E17_CTXSW_POISON: + info16 = ROBUST_CHANNEL_GR_EXCEPTION; + break; + + // Intentional fall-through + case NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL: + case NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL: + NV_ASSERT_OR_RETURN(loc.locType == NV_ERROR_CONT_LOCATION_TYPE_ENGINE, NV_ERR_INVALID_ARGUMENT); + // + // If SMC is enabled, RM need to notify partition local engineId. Convert + // global ID to partition local if client has filled proper engineIDs + // + localRmEngineType = loc.locInfo.engineLoc.rmEngineId; + if (IS_MIG_IN_USE(pGpu) && + RM_ENGINE_TYPE_IS_VALID(loc.locInfo.engineLoc.rmEngineId)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + + NV_ASSERT_OK_OR_RETURN(kmigmgrGetInstanceRefFromDevice(pGpu, + pKernelMIGManager, + loc.locInfo.engineLoc.pDevice, + &ref)); + + if (!kmigmgrIsEngineInInstance(pGpu, pKernelMIGManager, loc.locInfo.engineLoc.rmEngineId, ref)) + { + // Notifier is requested for an unsupported engine + NV_PRINTF(LEVEL_ERROR, + "Notifier requested for an unsupported rm engine id (0x%x)\n", + loc.locInfo.engineLoc.rmEngineId); + return NV_ERR_INVALID_ARGUMENT; + } + + // Override the engine type with the local engine idx + NV_ASSERT_OK_OR_RETURN(kmigmgrGetGlobalToLocalEngineType(pGpu, + pKernelMIGManager, + ref, + loc.locInfo.engineLoc.rmEngineId, + &localRmEngineType)); + } + + info16 = ROBUST_CHANNEL_CE_ERROR(NV2080_ENGINE_TYPE_COPY_IDX(localRmEngineType)); + break; + + case NV_ERROR_CONT_ERR_ID_E13_MMU_POISON: + info16 = ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT; + break; + } + + gpuNotifySubDeviceEvent(pGpu, + nv2080Notifier, + NULL, + 0, + info32, // Unused + info16); + + return NV_OK; +} + +/*! + * @brief Generate error log for corresponding error containment error code. + * + * Format / example : + * 1) Contained Error with SMC Partition attribution (Error attributable to SMC Partition or process in SMC partition): + * 2) Contained Error with no SMC partitioning (Error attributable to process on GPU): + * 3) Uncontaned Error + * + * >> NVRM: Xid (PCI:0000:01:00 GPU-I:05): 94, pid=7194, Contained: CE User Channel (0x9). RST: No, D-RST: No + * >> NVRM: Xid (PCI:0000:01:00): 94, pid=7062, Contained: CE User Channel (0x9). RST: No, D-RST: No + * >> NVRM: Xid (PCI:0000:01:00): 95, pid=7062, Uncontained: LTC TAG (0x2,0x1). RST: Yes, D-RST: No + * + * @param[in] pGpu OBJGPU pointer + * @param[in] errorCode Error Containment error code + * @param[in] loc Location, SubLocation information + * @param[in] pErrorContSmcSetting Error containment SMC Disable / Enable settings + * + * @returns NV_STATUS + */ +static +NV_STATUS +_gpuGenerateErrorLog_GA100(OBJGPU *pGpu, + NV_ERROR_CONT_ERR_ID errorCode, + NV_ERROR_CONT_LOCATION loc, + NV_ERROR_CONT_SMC_DIS_EN_SETTING *pErrorContSmcSetting) +{ + RM_ENGINE_TYPE localRmEngineType; + NvU32 rcErrorCode = pErrorContSmcSetting->rcErrorCode; + + NV_ASSERT_OR_RETURN((pErrorContSmcSetting != NULL), NV_ERR_INVALID_ARGUMENT); + + switch (loc.locType) + { + case NV_ERROR_CONT_LOCATION_TYPE_DRAM: + nvErrorLog_va((void *)pGpu, + rcErrorCode, + "%s: %s (0x%x,0x%x). physAddr: 0x%08llx RST: %s, D-RST: %s", + rcErrorCode == ROBUST_CHANNEL_CONTAINED_ERROR ? + ROBUST_CHANNEL_CONTAINED_ERROR_STR : + ROBUST_CHANNEL_UNCONTAINED_ERROR_STR, + ppErrContErrorIdStr[errorCode], + loc.locInfo.dramLoc.partition, + loc.locInfo.dramLoc.subPartition, + loc.locInfo.dramLoc.physicalAddress, + pErrorContSmcSetting->bGpuResetReqd ? "Yes" : "No", + pErrorContSmcSetting->bGpuDrainAndResetReqd ? "Yes" : "No"); + break; + + case NV_ERROR_CONT_LOCATION_TYPE_LTC: + nvErrorLog_va((void *)pGpu, + rcErrorCode, + "%s: %s (0x%x,0x%x). RST: %s, D-RST: %s", + rcErrorCode == ROBUST_CHANNEL_CONTAINED_ERROR ? + ROBUST_CHANNEL_CONTAINED_ERROR_STR : + ROBUST_CHANNEL_UNCONTAINED_ERROR_STR, + ppErrContErrorIdStr[errorCode], + loc.locInfo.ltcLoc.partition, + loc.locInfo.ltcLoc.slice, + pErrorContSmcSetting->bGpuResetReqd ? "Yes" : "No", + pErrorContSmcSetting->bGpuDrainAndResetReqd ? "Yes" : "No"); + break; + + case NV_ERROR_CONT_LOCATION_TYPE_ENGINE: + NV_ASSERT_OR_RETURN(loc.locType == NV_ERROR_CONT_LOCATION_TYPE_ENGINE, NV_ERR_INVALID_ARGUMENT); + // + // If SMC is enabled, RM need to notify partition local engineId. Convert + // global ID to partition local if client has filled proper engineIDs + // + localRmEngineType = loc.locInfo.engineLoc.rmEngineId; + if (IS_MIG_IN_USE(pGpu) && + RM_ENGINE_TYPE_IS_VALID(loc.locInfo.engineLoc.rmEngineId)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + NV_ASSERT_OK_OR_RETURN(kmigmgrGetMIGReferenceFromEngineType(pGpu, + pKernelMIGManager, + loc.locInfo.engineLoc.rmEngineId, + &ref)); + // Override the engine type with the local engine idx + NV_ASSERT_OK_OR_RETURN(kmigmgrGetGlobalToLocalEngineType(pGpu, + pKernelMIGManager, + ref, + loc.locInfo.engineLoc.rmEngineId, + &localRmEngineType)); + } + + nvErrorLog_va((void *)pGpu, + rcErrorCode, + "%s: %s (0x%x). RST: %s, D-RST: %s", + rcErrorCode == ROBUST_CHANNEL_CONTAINED_ERROR ? + ROBUST_CHANNEL_CONTAINED_ERROR_STR : + ROBUST_CHANNEL_UNCONTAINED_ERROR_STR, + ppErrContErrorIdStr[errorCode], + gpuGetNv2080EngineType(localRmEngineType), + pErrorContSmcSetting->bGpuResetReqd ? "Yes" : "No", + pErrorContSmcSetting->bGpuDrainAndResetReqd ? "Yes" : "No"); + break; + + case NV_ERROR_CONT_LOCATION_TYPE_NONE: + nvErrorLog_va((void *)pGpu, + rcErrorCode, + "%s: %s. RST: %s, D-RST: %s", + rcErrorCode == ROBUST_CHANNEL_CONTAINED_ERROR ? + ROBUST_CHANNEL_CONTAINED_ERROR_STR : + ROBUST_CHANNEL_UNCONTAINED_ERROR_STR, + ppErrContErrorIdStr[errorCode], + pErrorContSmcSetting->bGpuResetReqd ? "Yes" : "No", + pErrorContSmcSetting->bGpuDrainAndResetReqd ? "Yes" : "No"); + break; + } + + return NV_OK; +} + +/*! + * @brief Determine Error Containment RC code, print Xid, send NV2080_NOTIFIER*, + * mark device for reset or mark device for drain and reset as indicated in + * error containment state table (refer gpu/error_cont.h). + * + * @param[in] pGpu OBJGPU pointer + * @param[in] errorCode Error Containment error code + * @param[in] loc Location, SubLocation information + * @param[out] pRcErrorCode RC Error code + * + * @returns NV_STATUS + */ +NV_STATUS +gpuUpdateErrorContainmentState_GA100 +( + OBJGPU *pGpu, + NV_ERROR_CONT_ERR_ID errorCode, + NV_ERROR_CONT_LOCATION loc, + NvU32 *pRcErrorCode +) +{ + NvU32 tableIndex = 0; + NvBool bIsSmcEnabled = NV_FALSE; + NvU32 smcDisEnSettingIndex = 0; + NvU32 rcErrorCode = 0; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NV_ERROR_CONT_SMC_DIS_EN_SETTING *pErrorContSmcSetting = NULL; + + if (!gpuIsGlobalPoisonFuseEnabled(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_ASSERT_OK_OR_RETURN(_gpuGetErrorContStateTableIndex_GA100(pGpu, errorCode, &tableIndex)); + + // Check if MIG GPU partitioning is enabled + if (IS_MIG_IN_USE(pGpu)) + { + bIsSmcEnabled = NV_TRUE; + } + + // MIG Memory partitioning config entry index. + if (pKernelMIGManager != NULL && kmigmgrIsMIGMemPartitioningEnabled(pGpu, pKernelMIGManager)) + { + smcDisEnSettingIndex = 1; + } + + pErrorContSmcSetting = &(g_errContStateTable[tableIndex].smcDisEnSetting[smcDisEnSettingIndex]); + + rcErrorCode = pErrorContSmcSetting->rcErrorCode; + + // Pass RC Error code if user requested it. + if (pRcErrorCode != NULL) + { + *pRcErrorCode = rcErrorCode; + } + + // Update partition attribution for this exception only if SMC is enabled. + if (pErrorContSmcSetting->bPrintSmcPartitionInfo && bIsSmcEnabled) + { + // Fall through on error. + gpuSetPartitionErrorAttribution_HAL(pGpu, + errorCode, + loc, + rcErrorCode); + } + + // Print Xid only if Ampere Error Containment XIDs printing is enabled and rcErrorCode is valid + if (gpuIsAmpereErrorContainmentXidEnabled(pGpu) && rcErrorCode != NO_XID) + { + NV_ASSERT_OK_OR_RETURN(_gpuGenerateErrorLog_GA100(pGpu, + errorCode, + loc, + pErrorContSmcSetting)); + } + + // Send NV2080_NOTIFIER* + if (pErrorContSmcSetting->nv2080Notifier != NO_NV2080_NOTIFIER) + { + NV_ASSERT_OK(_gpuNotifySubDeviceEventNotifier_GA100(pGpu, + errorCode, + loc, + pErrorContSmcSetting->nv2080Notifier)); + } + + // Set the scratch bit to indicate the GPU needs to be reset. + if ((pErrorContSmcSetting->bGpuResetReqd) && + (gpuMarkDeviceForReset(pGpu) != NV_OK)) + { + NV_PRINTF(LEVEL_ERROR, "Failed to mark GPU for pending reset"); + } + + // Set the scratch bit to indicate the GPU needs to be reset. + if (pErrorContSmcSetting->bGpuDrainAndResetReqd && + gpuMarkDeviceForDrainAndReset(pGpu) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to mark GPU for pending drain and reset"); + } + + return NV_OK; +} + +NvBool +gpuCheckIfFbhubPoisonIntrPending_GA100 +( + OBJGPU *pGpu +) +{ + return intrIsVectorPending_HAL(pGpu, GPU_GET_INTR(pGpu), NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT, NULL); +} diff --git a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c index af04f7c88a..8bde43da65 100644 --- a/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c +++ b/src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c @@ -25,6 +25,7 @@ #include "gpu/gpu_child_class_defs.h" #include "os/os.h" #include "nverror.h" +#include "vgpu/rpc.h" #include "published/hopper/gh100/hwproject.h" #include "published/hopper/gh100/dev_gc6_island.h" @@ -32,6 +33,7 @@ #include "published/hopper/gh100/dev_pmc.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" +#include "published/hopper/gh100/dev_vm.h" #include "published/hopper/gh100/dev_xtl_ep_pri.h" #include "ctrl/ctrl2080/ctrl2080mc.h" @@ -191,47 +193,6 @@ NvBool gpuIsAtsSupportedWithSmcMemPartitioning_GH100(OBJGPU *pGpu) return NV_FALSE; } -/*! - * @brief Read back device ID and subsystem ID - * - * @note This function is designed to avoid OBJBIF dependence for the case that - * RM need to get device id and subsystem id early in the init process, - * before OBJBIF is initialized. - * - * @param[in] pGpu GPU object pointer - * @param[out] pDevId Return value of device ID - * @param[out] pSsId Return value of subsystem ID - */ -void -gpuReadDeviceId_GH100 -( - OBJGPU *pGpu, - NvU32 *pDevId, - NvU32 *pSsId -) -{ - NvU32 deviceId; - NvU32 ssId; - - if (pDevId == NULL || pSsId == NULL) return; - - if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_ID, &deviceId) != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Unable to read NV_EP_PCFG_GPU_ID\n"); - return; - } - *pDevId = deviceId; - - if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_SUBSYSTEM_ID, &ssId) != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Unable to read NV_EP_PCFG_GPU_SUBSYSTEM_ID\n"); - return; - } - *pSsId = ssId; -} - /*! * @brief Handle SEC_FAULT * @@ -412,6 +373,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GH100[] = GPU_CHILD_PRESENT(KernelFifo, 1), GPU_CHILD_PRESENT(KernelGmmu, 1), GPU_CHILD_PRESENT(KernelGraphics, 8), + GPU_CHILD_PRESENT(KernelHwpm, 1), GPU_CHILD_PRESENT(KernelMc, 1), GPU_CHILD_PRESENT(SwIntr, 1), GPU_CHILD_PRESENT(KernelNvlink, 1), @@ -446,6 +408,15 @@ gpuDetermineSelfHostedMode_KERNEL_GH100 OBJGPU *pGpu ) { + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if (pVSI->bSelfHostedMode) + { + pGpu->bIsSelfHosted = NV_TRUE; + NV_PRINTF(LEVEL_INFO, "SELF HOSTED mode detected after reading VGPU static info.\n"); + } + } if (IS_GSP_CLIENT(pGpu)) { GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); @@ -511,3 +482,37 @@ gpuIsDevModeEnabledInHw_GH100 return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_20_CC, _DEV_ENABLED, _TRUE, val); } +/*! + * @brief Check if register being accessed is within guest BAR0 space. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] addr Address being validated + */ +NV_STATUS +gpuSanityCheckVirtRegAccess_GH100 +( + OBJGPU *pGpu, + NvU32 addr +) +{ + // Not applicable in PV mode + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) + { + return NV_OK; + } + + if ((addr >= DEVICE_BASE(NV_EP_PCFGM)) && + (addr < DEVICE_EXTENT(NV_EP_PCFGM))) + { + return NV_OK; + } + + // Check if address in NV_VIRTUAL_FUNCTION range, if not error out. + if ((addr < DRF_EXTENT(NV_VIRTUAL_FUNCTION_PRIV)) || + ((addr >= DRF_BASE(NV_VIRTUAL_FUNCTION)) && (addr < DRF_EXTENT(NV_VIRTUAL_FUNCTION)))) + { + return NV_OK; + } + + return NV_ERR_INVALID_ADDRESS; +} diff --git a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c index f9435dc09d..24076c46be 100644 --- a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c +++ b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/gpu_child_class_defs.h" #include "gpu_mgr/gpu_mgr_sli.h" @@ -30,6 +31,7 @@ #include "published/maxwell/gm107/dev_nv_xve.h" #include "published/maxwell/gm107/dev_nv_xve1.h" #include "published/maxwell/gm107/dev_fuse.h" +#include "published/maxwell/gm107/dev_pri_ringstation_sys.h" /*! * @brief Returns SR-IOV capabilities @@ -258,20 +260,6 @@ gpuWriteFunctionConfigRegEx_GM107 return NV_OK; } -void -gpuReadDeviceId_GM107 -( - OBJGPU *pGpu, - NvU32 *devId, - NvU32 *ssId -) -{ - if (devId == NULL || ssId == NULL) return; - - *devId = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_ID); - *ssId = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_PCFG) + NV_XVE_SUBSYSTEM); -} - /*! * @brief Perform gpu-dependent error handling for error during register read sanity check * @@ -377,6 +365,7 @@ gpuGetIdInfo_GM107(OBJGPU *pGpu) static const GPUCHILDORDER gpuChildOrderList_GM200[] = { + {classId(OBJVBIOS), GCO_ALL}, {classId(ConfidentialCompute), GCO_ALL}, {classId(Pxuc), GCO_ALL}, {classId(OBJBIF), GCO_ALL}, @@ -464,6 +453,7 @@ gpuChildOrderList_GM200[] = {classId(OBJGPULOG), GCO_LIST_INIT | GCO_LIST_LOAD}, {classId(OBJGPUMON), GCO_ALL}, {classId(OBJGPULOG), GCO_LIST_UNLOAD | GCO_LIST_DESTROY}, + {classId(KernelHwpm), GCO_ALL}, {classId(OBJHWPM), GCO_ALL}, {classId(OBJSWENG), GCO_ALL}, {classId(OBJGRIDDISPLAYLESS), GCO_ALL}, @@ -509,6 +499,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_GM200[] = GPU_CHILD_PRESENT(KernelFifo, 1), GPU_CHILD_PRESENT(KernelGmmu, 1), GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelHwpm, 1), GPU_CHILD_PRESENT(KernelMc, 1), GPU_CHILD_PRESENT(SwIntr, 1), GPU_CHILD_PRESENT(KernelPerf, 1), @@ -634,3 +625,42 @@ gpuDetectSliLinkFromGpus_GK104 } } } + +/*! + * @brief Get error that arises during sanity check on a register read value + * + * @param[in] pGpu GPU object pointer + * @param[in] value Register value + * @param[out] pErrorString Error string pointer + * + * @return void + */ +void +gpuGetSanityCheckRegReadError_GM107 +( + OBJGPU *pGpu, + NvU32 value, + const char **pErrorString +) +{ +#define PRI_ERROR(err) \ +if (DRF_VAL(_PPRIV, _SYS_PRI_ERROR, _CODE, value) == err) \ +{ \ + *pErrorString = #err; \ +} + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_FECS_ERR); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_PRI_TIMEOUT); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_HOST_FB_ACK_TIMEOUT); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_TIMEOUT); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_DECODE); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_RESET); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_FLOORSWEEP); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_STUCK_ACK); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_0_EXPECTED_ACK); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_FENCE_ERROR); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_SUBID_ERROR); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_ORPHAN); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_DEAD_RING); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_TRAP); + PRI_ERROR(NV_PPRIV_SYS_PRI_ERROR_CODE_FECS_PRI_CLIENT_ERR); +} diff --git a/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c b/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c index 81e1eb7e78..36ccd128c3 100644 --- a/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c +++ b/src/nvidia/src/kernel/gpu/arch/pascal/kern_gpu_gp100.c @@ -22,6 +22,7 @@ */ #include "core/core.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/eng_desc.h" #include "gpu/gpu_child_class_defs.h" diff --git a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c index f251f423ab..e5f9a94794 100644 --- a/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/arch/turing/kern_gpu_tu102.c @@ -22,9 +22,18 @@ */ #include "gpu/gpu.h" #include "gpu/gpu_child_class_defs.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/mem_mgr/rm_page_size.h" +#include "jt.h" + #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/hwproject.h" -#include "jt.h" +#include "published/turing/tu102/dev_nv_xve.h" +#include "published/turing/tu102/dev_gc6_island.h" +#include "published/turing/tu102/dev_gc6_island_addendum.h" /*! * @brief Returns SR-IOV capabilities @@ -63,6 +72,7 @@ gpuGetSriovCaps_TU102 pParams->bEmulateVFBar0TlbInvalidationRegister = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE); pParams->bClientRmAllocatedCtxBuffer = gpuIsClientRmAllocatedCtxBufferEnabled(pGpu); pParams->bNonPowerOf2ChannelCountSupported = gpuIsNonPowerOf2ChannelCountSupported(pGpu); + pParams->bVfResizableBAR1Supported = gpuIsVfResizableBAR1Supported(pGpu); return NV_OK; } @@ -133,6 +143,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU102[] = GPU_CHILD_PRESENT(KernelFifo, 1), GPU_CHILD_PRESENT(KernelGmmu, 1), GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelHwpm, 1), GPU_CHILD_PRESENT(KernelMc, 1), GPU_CHILD_PRESENT(SwIntr, 1), GPU_CHILD_PRESENT(KernelNvlink, 1), @@ -163,6 +174,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU104[] = GPU_CHILD_PRESENT(KernelFifo, 1), GPU_CHILD_PRESENT(KernelGmmu, 1), GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelHwpm, 1), GPU_CHILD_PRESENT(KernelMc, 1), GPU_CHILD_PRESENT(SwIntr, 1), GPU_CHILD_PRESENT(KernelNvlink, 1), @@ -193,6 +205,7 @@ static const GPUCHILDPRESENT gpuChildrenPresent_TU106[] = GPU_CHILD_PRESENT(KernelFifo, 1), GPU_CHILD_PRESENT(KernelGmmu, 1), GPU_CHILD_PRESENT(KernelGraphics, 1), + GPU_CHILD_PRESENT(KernelHwpm, 1), GPU_CHILD_PRESENT(KernelMc, 1), GPU_CHILD_PRESENT(SwIntr, 1), GPU_CHILD_PRESENT(KernelNvlink, 1), @@ -258,3 +271,307 @@ gpuJtVersionSanityCheck_TU102 gpuJtVersionSanityCheck_TU102_EXIT: return status; } + +/*! + * @brief: Return base offset of register group + * + * @param[in] pGpu OBJGPU pointer + * regBase NvU32 value for requested register group + * @param[out] offset NvU32 pointer to return base offset + * + * @returns NV_OK if the register group is found. + */ +NV_STATUS +gpuGetRegBaseOffset_TU102(OBJGPU *pGpu, NvU32 regBase, NvU32 *pOffset) +{ + switch (regBase) + { + case NV_REG_BASE_USERMODE: + { + // + // Baremetal from Turing will not use the NV_USERMODE_* + // as - "NV_USERMODE is going away long term, and + // doesn't support any of the new remap + // type features". Since we would need the new features + // such as worksubmission doorbell register interrupting GSP, + // we will start using the physical registers through NV_VIRTUAL_FUNCTION + // even on host. + // + *pOffset = GPU_GET_VREG_OFFSET(pGpu, DRF_BASE(NV_VIRTUAL_FUNCTION)); + + return NV_OK; + } + default: + { + + return NV_ERR_NOT_SUPPORTED; + } + } +} + +/*! + * @brief Check if register being accessed is within guest BAR0 space. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] addr Address being validated + */ +NV_STATUS +gpuSanityCheckVirtRegAccess_TU102 +( + OBJGPU *pGpu, + NvU32 addr +) +{ + // Not applicable in PV mode + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) + { + return NV_OK; + } + + if ((addr >= DEVICE_BASE(NV_PCFG)) && + (addr < DEVICE_BASE(NV_PCFG) + PCIE_CONFIG_SPACE_SIZE)) + { + return NV_OK; + } + + // Check if address in NV_VIRTUAL_FUNCTION range, if not error out. + if ((addr < DRF_EXTENT(NV_VIRTUAL_FUNCTION_PRIV)) || + ((addr >= DRF_BASE(NV_VIRTUAL_FUNCTION)) && (addr < DRF_EXTENT(NV_VIRTUAL_FUNCTION)))) + { + return NV_OK; + } + + return NV_ERR_INVALID_ADDRESS; +} + +/* + * @brief Function that checks if ECC error occurred by reading various count + * registers/interrupt registers. This function is not floorsweeping-aware so + * PRI errors are ignored + */ +void +gpuCheckEccCounts_TU102 +( + OBJGPU *pGpu +) +{ + NvU32 dramCount = 0; + NvU32 ltcCount = 0; + NvU32 mmuCount = 0; + NvU32 pcieCount = 0; + + kmemsysGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu), &dramCount, <cCount); + mmuCount += kgmmuGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_GMMU(pGpu)); + pcieCount += kbifGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_BIF(pGpu)); + pcieCount += kbusGetEccCounts_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu)); + + // If counts > 0 or if poison interrupt pending, ECC error has occurred. + if (((dramCount + ltcCount + mmuCount + pcieCount) != 0) || gpuCheckIfFbhubPoisonIntrPending_HAL(pGpu)) + { + nvErrorLog_va((void *)pGpu, UNRECOVERABLE_ECC_ERROR_ESCAPE, + "An uncorrectable ECC error detected " + "(possible firmware handling failure) " + "DRAM:%d, LTC:%d, MMU:%d, PCIE:%d", dramCount, ltcCount, mmuCount, pcieCount); + } +} + +/* + * @brief Function that clears ECC error count registers. + */ +NV_STATUS +gpuClearEccCounts_TU102 +( + OBJGPU *pGpu +) +{ + NV_STATUS status = NV_OK; + + gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu); + + kmemsysClearEccCounts_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + + kgmmuClearEccCounts_HAL(pGpu, GPU_GET_KERNEL_GMMU(pGpu)); + + kbusClearEccCounts_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu)); + + status = kbifClearEccCounts_HAL(pGpu, GPU_GET_KERNEL_BIF(pGpu)); + if (status != NV_OK) + { + return status; + } + + return NV_OK; +} + +// +// This function checks for GFW boot completion status by reading +// NV_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED bits and +// return true if GFW boot has completed. +// +// Either pGpu or pgc6VirtAddr should be not null. +// This function needs to be called in early init code-path where OBJGPU +// has not created. For that case, the NV_PGC6 base address will be mapped +// and pgc6VirtAddr will contain the virtual address for NV_PGC6. +// If pgc6VirtAddr is not null, then read the register with MEM_RD32, +// otherwise use the GPU_REG_RD32. +// +// The current GFW boot progress value will be returned in gfwBootProgressVal. +// +static NvBool +_gpuIsGfwBootCompleted_TU102 +( + OBJGPU *pGpu, + NvU8 *pgc6VirtAddr, + NvU32 *gfwBootProgressVal +) +{ + NvU32 regVal; + + if (pgc6VirtAddr != NULL) + { + regVal = MEM_RD32(pgc6VirtAddr + + (NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK - + DEVICE_BASE(NV_PGC6))); + } + else + { + regVal = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK); + } + + // + // Before reading the actual GFW_BOOT status register, + // we want to check that FWSEC has lowered its PLM first. + // If not then obviously it has not completed. + // + if (!FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK, + _READ_PROTECTION_LEVEL0, _ENABLE, regVal)) + { + *gfwBootProgressVal = 0x0; + return NV_FALSE; + } + + if (pgc6VirtAddr != NULL) + { + regVal = MEM_RD32(pgc6VirtAddr + + (NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT - + DEVICE_BASE(NV_PGC6))); + } + else + { + regVal = GPU_REG_RD32(pGpu, NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT); + } + + *gfwBootProgressVal = DRF_VAL(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, + _PROGRESS, regVal); + + return FLD_TEST_DRF(_PGC6, _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, + _PROGRESS, _COMPLETED, regVal); +} + +#define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms +#define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s +#define GPU_GFW_BOOT_COMPLETION_TIMEOUT_US (FWSECLIC_PROG_START_TIMEOUT + \ + FWSECLIC_PROG_COMPLETE_TIMEOUT) +NV_STATUS +gpuWaitForGfwBootComplete_TU102 +( + OBJGPU *pGpu +) +{ + NvU32 timeoutUs = GPU_GFW_BOOT_COMPLETION_TIMEOUT_US; + NvU32 gfwBootProgressVal = 0; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + + // Use the OS timer since the GPU timer is not ready yet + gpuSetTimeout(pGpu, gpuScaleTimeout(pGpu, timeoutUs), &timeout, + GPU_TIMEOUT_FLAGS_OSTIMER); + + while (status == NV_OK) + { + if (_gpuIsGfwBootCompleted_TU102(pGpu, NULL, &gfwBootProgressVal)) + { + return NV_OK; + } + + status = gpuCheckTimeout(pGpu, &timeout); + } + + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: (progress 0x%x)\n", + gfwBootProgressVal); + return status; +} + +// +// Workaround for Bug 3809777. +// +// This function is not created through HAL infrastructure. It needs to be +// called when OBJGPU is not created. HAL infrastructure can’t be used for +// this case, so it has been added manually. It will be invoked directly by +// gpumgrIsDeviceMsixAllowed() after checking the GPU architecture. +// +// When driver is running inside guest in pass-through mode, check if MSI-X +// is enabled by reading NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP. The devinit +// can disable MSI-X capability, if configured. The hypervisor issues reset +// before launching VM. After reset, the MSI-X capability will be visible +// for some duration and then devinit hides the MSI-X capability. This +// devinit will run in the background. During this time, the hypervisor can +// assume that MSI-X capability is present in the GPU and configure the guest +// GPU PCIe device instance with MSI-X capability. When GPU tries to use the +// MSI-X interrupts later, then interrupt won’t be triggered. To identify +// this case, wait for GPU devinit completion and check if MSI-X capability +// is not hidden. +// +NvBool gpuIsMsixAllowed_TU102 +( + RmPhysAddr bar0BaseAddr +) +{ + NvU8 *vAddr; + NvU32 regVal; + NvU32 timeUs = 0; + NvU32 gfwBootProgressVal = 0; + NvBool bGfwBootCompleted = NV_FALSE; + + ct_assert(DRF_SIZE(NV_PGC6) <= RM_PAGE_SIZE); + vAddr = osMapKernelSpace(bar0BaseAddr + DEVICE_BASE(NV_PGC6), + RM_PAGE_SIZE, NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + if (vAddr == NULL) + { + return NV_FALSE; + } + + while (timeUs < GPU_GFW_BOOT_COMPLETION_TIMEOUT_US) + { + bGfwBootCompleted = _gpuIsGfwBootCompleted_TU102(NULL, vAddr, &gfwBootProgressVal); + if (bGfwBootCompleted) + { + break; + } + + osDelayUs(1000); + timeUs += 1000; + } + + osUnmapKernelSpace(vAddr, RM_PAGE_SIZE); + if (!bGfwBootCompleted) + { + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: (progress 0x%x)\n", + gfwBootProgressVal); + return NV_FALSE; + } + + vAddr = osMapKernelSpace(bar0BaseAddr + DEVICE_BASE(NV_PCFG) + + NV_XVE_PRIV_MISC_1, 4, NV_MEMORY_UNCACHED, + NV_PROTECT_READABLE); + if (vAddr == NULL) + { + return NV_FALSE; + } + + regVal = MEM_RD32(vAddr); + osUnmapKernelSpace(vAddr, 4); + + return FLD_TEST_DRF(_XVE, _PRIV_MISC_1, _CYA_HIDE_MSIX_CAP, _FALSE, regVal); +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c b/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c index e1228afb5f..6275f4f71b 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c @@ -85,4 +85,3 @@ _kbifPreOsCheckErotGrantAllowed_AD102 return FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _ALLOW, _YES, reg); } - diff --git a/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c b/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c index 771b9ce3b4..fa5310bf2e 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c @@ -24,6 +24,7 @@ /* ------------------------ Includes ---------------------------------------- */ #include "gpu/bif/kernel_bif.h" +#include "gpu/fifo/kernel_fifo.h" #include "published/ampere/ga100/dev_nv_xve_addendum.h" #include "published/ampere/ga100/dev_nv_xve.h" #include "published/ampere/ga100/dev_boot.h" @@ -330,3 +331,77 @@ kbifStoreBarRegOffsets_GA100 currOffset = currOffset + 4; } } + + +/*! + * @brief Get the NV_PMC_ENABLE bit of the valid Engines to reset. + * + * @param[in] pGpu The GPU object + * @param[in] pKernelBif KernelBif object pointer + * + * @return All valid engines in NV_PMC_ENABLE. + */ +NvU32 +kbifGetValidEnginesToReset_GA100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return (DRF_DEF(_PMC, _ENABLE, _PDISP, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PERFMON, _ENABLED)); +} + + +/*! + * @brief Get the NV_PMC_DEVICE_ENABLE bit of the valid Engines to reset. Gets this + * data by reading the device info table and returns engines with valid reset_id. + * + * @param[in] pGpu The GPU object + * @param[in] pKernelBif KernelBif object pointer + * + * @return All valid engines in NV_PMC_DEVICE_ENABLE. + */ +NvU32 +kbifGetValidDeviceEnginesToReset_GA100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + const NvU32 numEngines = kfifoGetNumEngines_HAL(pGpu, pKernelFifo); + NV_STATUS status; + NvU32 engineID; + NvU32 regVal = 0; + NvU32 resetIdx; + + // + // If hardware increases the size of this register in future chips, we would + // need to catch this and fork another HAL. + // + if ((sizeof(NvU32) * NV_PMC_DEVICE_ENABLE__SIZE_1) > sizeof(NvU32)) + { + NV_ASSERT_FAILED("Assert for Mcheck to catch increase in register size. Fork this HAL"); + } + + for (engineID = 0; engineID < numEngines; engineID++) + { + status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_INVALID, + engineID, ENGINE_INFO_TYPE_RESET, &resetIdx); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to get Reset index for engine ID (%u)\n", + engineID); + continue; + } + + // We got the resetIdx. Lets set the bit in NV_PMC_DEVICE_ENABLE. + regVal = FLD_IDX_SET_DRF(_PMC, _DEVICE_ENABLE, _STATUS_BIT, resetIdx, _ENABLE, regVal); + } + + return regVal; +} + + diff --git a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c index c19dd71c19..d508fcf379 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c @@ -30,15 +30,27 @@ #include "platform/chipset/chipset.h" #include "ctrl/ctrl2080/ctrl2080bus.h" -#include "published/hopper/gh100/dev_fb.h" -#include "published/hopper/gh100/dev_xtl_ep_pri.h" #include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h" + +#include "published/hopper/gh100/dev_fb.h" #include "published/hopper/gh100/hwproject.h" -#include "published/hopper/gh100/dev_pmc.h" +#include "published/hopper/gh100/dev_xtl_ep_pri.h" +#include "published/hopper/gh100/dev_nv_xpl.h" #include "published/hopper/gh100/dev_vm.h" +#include "published/hopper/gh100/dev_pmc.h" #include "os/os.h" +static NV_STATUS _kbifSavePcieConfigRegisters_GH100(OBJGPU *pGpu, KernelBif *pKernelBif, const PKBIF_XVE_REGMAP_REF pRegmapRef); +static NV_STATUS _kbifRestorePcieConfigRegisters_GH100(OBJGPU *pGpu, KernelBif *pKernelBif, const PKBIF_XVE_REGMAP_REF pRegmapRef); + +// Size of PCIe config space +#define PCIE_CONFIG_SPACE_MAX_SIZE 0x2FC + +// Devinit completion timeout after FLR +#define BIF_FLR_DEVINIT_COMPLETION_TIMEOUT_DEFAULT 900000 + + /*! * @brief Check if MSI is enabled in HW * @@ -719,12 +731,18 @@ kbifGetBusOptionsAddr_GH100 case BUS_OPTIONS_DEV_CONTROL_STATUS: *pAddrReg = NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS; break; + case BUS_OPTIONS_DEV_CONTROL_STATUS_2: + *pAddrReg = NV_EP_PCFG_GPU_DEVICE_CONTROL_STATUS_2; + break; case BUS_OPTIONS_LINK_CONTROL_STATUS: *pAddrReg = NV_EP_PCFG_GPU_LINK_CONTROL_STATUS; break; case BUS_OPTIONS_LINK_CAPABILITIES: *pAddrReg = NV_EP_PCFG_GPU_LINK_CAPABILITIES; break; + case BUS_OPTIONS_L1_PM_SUBSTATES_CTRL_1: + *pAddrReg = NV_EP_PCFG_GPU_L1_PM_SS_CONTROL_1_REGISTER; + break; default: NV_PRINTF(LEVEL_ERROR, "Invalid register type passed 0x%x\n", options); @@ -734,6 +752,354 @@ kbifGetBusOptionsAddr_GH100 return status; } +/*! + * @brief Helper function for _kbifSavePcieConfigRegisters_GH100() + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * @param[in] pRegmapRef Pointer to XVE Register map structure + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +static NV_STATUS +_kbifSavePcieConfigRegisters_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + const PKBIF_XVE_REGMAP_REF pRegmapRef +) +{ + NV_STATUS status; + NvU32 regOffset; + NvU32 bufOffset = 0; + + // Read and save entire config space + for (regOffset = 0x0; regOffset < PCIE_CONFIG_SPACE_MAX_SIZE; regOffset+=0x4) + { + status = GPU_BUS_CFG_CYCLE_RD32(pGpu, regOffset, + &pRegmapRef->bufBootConfigSpace[bufOffset]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Config read failed.\n"); + return status; + } + bufOffset++; + } + + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SECONDARY_BUS_RESET_SUPPORTED, NV_TRUE); + + return NV_OK; +} + +/*! + * @brief Helper function for _kbifRestorePcieConfigRegisters_GH100 + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * @param[in] pRegmapRef Pointer to XVE Register map structure + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +static NV_STATUS +_kbifRestorePcieConfigRegisters_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + const PKBIF_XVE_REGMAP_REF pRegmapRef +) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + void *pHandle; + NvU32 regOffset; + NvU32 bufOffset = 0; + NV_STATUS status; + + pHandle = osPciInitHandle(domain, bus, device, 0, NULL, NULL); + NV_ASSERT_OR_RETURN(pHandle, NV_ERR_INVALID_POINTER); + + // Restore entire config space + for (regOffset = 0x0; regOffset < PCIE_CONFIG_SPACE_MAX_SIZE; regOffset+=0x4) + { + status = GPU_BUS_CFG_CYCLE_WR32(pGpu, regOffset, + pRegmapRef->bufBootConfigSpace[bufOffset]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Config write failed.\n"); + NV_ASSERT(0); + return status; + } + bufOffset++; + } + + return NV_OK; +} + +/*! + * @brief Helper function saves MSIX vector control masks + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifSaveMsixTable_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 i; + NvU32 controlSize = kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif); + + for (i = 0U; i < controlSize; i++) + { + // Each MSIX table entry is 4 NvU32s + pKernelBif->xveRegmapRef[0].bufMsixTable[(i*4) + 0] = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(i)); + pKernelBif->xveRegmapRef[0].bufMsixTable[(i*4) + 1] = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI(i)); + pKernelBif->xveRegmapRef[0].bufMsixTable[(i*4) + 2] = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA(i)); + pKernelBif->xveRegmapRef[0].bufMsixTable[(i*4) + 3] = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i)); + } + + return NV_OK; +} + +/*! + * @brief Helper function to restore MSIX vector control masks + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifRestoreMsixTable_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 i; + NvU32 controlSize = kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif); + + // Initialize the base offset for the virtual registers for physical function + NvU32 vRegOffset = pGpu->sriovState.virtualRegPhysOffset; + + // In FLR path, we don't want to use usual register r/w macros + for (i = 0U; i < controlSize; i++) + { + // Each MSIX table entry is 4 NvU32s + osGpuWriteReg032(pGpu, vRegOffset + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(i), pKernelBif->xveRegmapRef[0].bufMsixTable[(i*4) + 0]); + osGpuWriteReg032(pGpu, vRegOffset + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI(i), pKernelBif->xveRegmapRef[0].bufMsixTable[(i*4) + 1]); + osGpuWriteReg032(pGpu, vRegOffset + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA(i), pKernelBif->xveRegmapRef[0].bufMsixTable[(i*4) + 2]); + osGpuWriteReg032(pGpu, vRegOffset + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i), pKernelBif->xveRegmapRef[0].bufMsixTable[(i*4) + 3]); + } + + return NV_OK; +} + +/*! + * @brief Wait for to get config access. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * @param[in] pTimeout Value in microseconds to dev init complete + * + * @return NV_OK if successful. + */ +NV_STATUS +kbifConfigAccessWait_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + RMTIMEOUT *pTimeout +) +{ + NvU32 regVal = 0; + NV_STATUS status = NV_OK; + + while (NV_TRUE) + { + // + // This read only register should be accessible over config cycle + // once devinit is complete without RM having to restore config space. + // This register is not really reset on FLR. + // + if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_EP_PCFG_GPU_ID, ®Val) == NV_OK) + { + if (FLD_TEST_DRF(_EP_PCFG_GPU, _ID, _VENDOR, _NVIDIA, regVal)) + { + break; + } + } + status = gpuCheckTimeout(pGpu, pTimeout); + + if (status == NV_ERR_TIMEOUT) + { + NV_ASSERT_FAILED("Timed out waiting for devinit to complete\n"); + return status; + } + // + // Put ourself into wait state for 1ms. This function runs in the context + // of DxgkDdiResetFromTimeout which is at PASSIVE_LEVEL(lower priority) + // which means it can be in wait state for longer delays of the order of + // milliseconds + // + osDelay(1); + } + + return status; +} + +/*! + * @brief Do function level reset for Fn0 of GPU + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + * + * @return NV_OK if successful + */ +NV_STATUS +kbifDoFunctionLevelReset_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvBool bMSIXEnabled; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + NvU32 flrDevInitTimeout; + NvU32 flrDevInitTimeoutScale = pKernelBif->flrDevInitTimeoutScale; + + // If this is non-windows platform or non-ESXi, we already use OS based interface + { + pKernelBif->bInFunctionLevelReset = NV_TRUE; + status = osDoFunctionLevelReset(pGpu); + if (status != NV_OK) + { + NV_ASSERT_FAILED("osDoFunctionLevelReset failed!\n"); + } + goto kbifDoFunctionLevelReset_GH100_exit; + } + + pKernelBif->bPreparingFunctionLevelReset = NV_TRUE; + status = kbifSavePcieConfigRegisters_HAL(pGpu, pKernelBif); + if (status != NV_OK) + { + NV_ASSERT_FAILED("Config registers save failed!\n"); + goto kbifDoFunctionLevelReset_GH100_exit; + } + + bMSIXEnabled = kbifIsMSIXEnabledInHW_HAL(pGpu, pKernelBif); + + if (bMSIXEnabled) + { + status = kbifSaveMsixTable_HAL(pGpu, pKernelBif); + if (status != NV_OK) + { + NV_ASSERT_FAILED("MSIX Table save failed!\n"); + goto kbifDoFunctionLevelReset_GH100_exit; + } + } + + // Once we save required registers, we are done with prep. phase for FLR + pKernelBif->bPreparingFunctionLevelReset = NV_FALSE; + + // Trigger FLR now + status = kbifTriggerFlr_HAL(pGpu, pKernelBif); + + if (status != NV_OK) + { + goto kbifDoFunctionLevelReset_GH100_exit; + } + + pKernelBif->bInFunctionLevelReset = NV_TRUE; + + // + // Wait for 10ms on Silicon for reset to propagate. Actually, HW is + // supposed to return CRS status for config requests until config + // space is not ready but we do expect at least 10ms for it to be ready + // so why poll? On RTL and emulation, CPU clocks don't scale to GPU clock + // so don't wait. + // + if (IS_SILICON(pGpu)) + { + osDelayUs(10000); + } + + // flrTimeoutScale is regkey based for easy debugging + flrDevInitTimeout = BIF_FLR_DEVINIT_COMPLETION_TIMEOUT_DEFAULT * + flrDevInitTimeoutScale; + + // + // After CRS_TIMEOUT, HW will auto-clear SEND_CRS bit which means config cycles + // will succeed but it is still possible that devinit is not complete yet. + // OS won't have a way to check that anyway but RM should do that here. + // TODO: Should we use this loop or just the PCI spec-defined 100ms delay + // now that we have a devinit wait in fspWaitForSecureBoot_HAL below? + // + gpuSetTimeout(pGpu, flrDevInitTimeout, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER); + + status = kbifConfigAccessWait_HAL(pGpu, pKernelBif, &timeout); + + if (status != NV_OK) + { + NV_ASSERT_FAILED("Timed out waiting for devinit to complete\n"); + goto kbifDoFunctionLevelReset_GH100_exit; + } + + status = kbifRestorePcieConfigRegisters_HAL(pGpu, pKernelBif); + if (status != NV_OK) + { + NV_ASSERT_FAILED("Config registers restore failed!\n"); + goto kbifDoFunctionLevelReset_GH100_exit; + } + + // As of GH100, miata rom cannot be run on simulation. + if (IS_SILICON(pGpu) || IS_EMULATION(pGpu)) + { + // On emulation VBIOS boot can take long so add prints for better visibility + if (IS_EMULATION(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Entering secure boot completion wait.\n"); + } + + status = NV_ERR_NOT_SUPPORTED; + if (status != NV_OK) + { + DBG_BREAKPOINT(); + NV_PRINTF(LEVEL_ERROR, "VBIOS boot failed!!\n"); + goto kbifDoFunctionLevelReset_GH100_exit; + } + + if (IS_EMULATION(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Exited secure boot completion wait with status = NV_OK.\n"); + } + } + + if (bMSIXEnabled) + { + // TODO-NM: Check if this needed for other NVPM flows like GC6 + status = kbifRestoreMsixTable_HAL(pGpu, pKernelBif); + if (status != NV_OK) + { + NV_ASSERT_FAILED("MSIX Table save failed!\n"); + } + } + +kbifDoFunctionLevelReset_GH100_exit: + pKernelBif->bPreparingFunctionLevelReset = NV_FALSE; + pKernelBif->bInFunctionLevelReset = NV_FALSE; + + return status; +} + + /*! * @brief Returns size of MSIX vector control table * @@ -750,7 +1116,6 @@ kbifGetMSIXTableVectorControlSize_GH100 return NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1; } - /*! * @brief Check and cache Function level reset support * @@ -990,6 +1355,94 @@ kbifStopSysMemRequests_GH100 return NV_OK; } +/*! + * @brief Save boot time PCIe Config space + * + * @param[in] pGpu GPU object pointer + * @param[in] pBif BIF object pointer + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifSavePcieConfigRegisters_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + + NV_STATUS status = NV_OK; + + // Skip config save on FMODEL (200684952), move to regmap (200700271) + if (IS_FMODEL(pGpu)) + { + return NV_OK; + } + + // + // Save config space if GPU is about to enter Function Level Reset + // OR if on non-windows platform, FORCE_PCIE_CONFIG_SAVE is set and SBR is + // enabled + // OR if on windows platform, SBR is enabled + // + if (!pKernelBif->bPreparingFunctionLevelReset && + !((RMCFG_FEATURE_PLATFORM_WINDOWS || + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_FORCE_PCIE_CONFIG_SAVE)) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED))) + { + NV_PRINTF(LEVEL_ERROR, "Config space save has been skipped.\n"); + return NV_OK; + } + + // Save pcie config space for function 0 + status = _kbifSavePcieConfigRegisters_GH100(pGpu, pKernelBif, + &pKernelBif->xveRegmapRef[0]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Saving PCIe config space failed for gpu.\n"); + NV_ASSERT(0); + return status; + } + + return status; +} + +/*! + * @brief Restore boot time PCIe Config space + * + * @param[in] pGpu GPU object pointer + * @param[in] pBif BIF object pointer + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifRestorePcieConfigRegisters_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NV_STATUS status = NV_OK; + + // Skip config restore on FMODEL (200684952), move to regmap (200700271) + if (IS_FMODEL(pGpu)) + { + return NV_OK; + } + + // Restore pcie config space for function 0 + status = _kbifRestorePcieConfigRegisters_GH100(pGpu, pKernelBif, + &pKernelBif->xveRegmapRef[0]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Restoring PCIe config space failed for gpu.\n"); + NV_ASSERT(0); + return status; + } + + return status; +} + /*! * @brief Waits for function issued transaction completions (sysmem to GPU) to arrive * @@ -1129,3 +1582,76 @@ kbifInit_GH100 return NV_OK; } +NvU32 +kbifGetEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 regVal; + NvU32 count = 0; + + // PCIE RBUF + regVal = GPU_REG_RD32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_RBUF); + count += DRF_VAL(_XPL_DL, _ERR_COUNT_RBUF, _UNCORR_ERR, regVal); + + // PCIE SEQ_LUT + regVal = GPU_REG_RD32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_SEQ_LUT); + count += DRF_VAL(_XPL_DL, _ERR_COUNT_SEQ_LUT, _UNCORR_ERR, regVal); + + // PCIE XTL + regVal = GPU_REG_RD32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS); + if (regVal != 0) + { + count += 1; + } + + // PCIE XTL + regVal = GPU_REG_RD32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS); + if (regVal != 0) + { + count += 1; + } + + return count; +} + +NV_STATUS +kbifClearEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + NvU32 regVal; + + // Reset XTL-EP status registers + GPU_REG_WR32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS, ~0); + GPU_REG_WR32(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS, ~0); + + // Reset XPL-EP error counters + regVal = DRF_DEF(_XPL, _DL_ERR_RESET, _RBUF_UNCORR_ERR_COUNT, _PENDING) | + DRF_DEF(_XPL, _DL_ERR_RESET, _SEQ_LUT_UNCORR_ERR_COUNT, _PENDING); + GPU_REG_WR32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_RESET, regVal); + + // Wait for the error counter reset to complete + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + for (;;) + { + status = gpuCheckTimeout(pGpu, &timeout); + + regVal = GPU_REG_RD32(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_RESET); + + if (FLD_TEST_DRF(_XPL, _DL_ERR_RESET, _RBUF_UNCORR_ERR_COUNT, _DONE, regVal) && + FLD_TEST_DRF(_XPL, _DL_ERR_RESET, _SEQ_LUT_UNCORR_ERR_COUNT, _DONE, regVal)) + break; + + if (status != NV_OK) + return status; + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c index bd7c0c20fb..2605eb3753 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c @@ -30,6 +30,7 @@ #include "published/maxwell/gm107/dev_boot.h" #include "published/maxwell/gm107/dev_nv_xve.h" +#include "published/maxwell/gm107/dev_nv_xve1.h" #include "published/maxwell/gm107/dev_nv_pcfg_xve_addendum.h" #include "published/maxwell/gm107/dev_nv_pcfg_xve1_addendum.h" @@ -50,6 +51,9 @@ static const NvU32 xveRegMapWrite[] = NV_PCFG_XVE_REGISTER_WR_MAP; static const NvU32 xve1RegMapValid[] = NV_PCFG_XVE1_REGISTER_VALID_MAP; static const NvU32 xve1RegMapWrite[] = NV_PCFG_XVE1_REGISTER_WR_MAP; +static NV_STATUS _kbifSavePcieConfigRegisters_GM107(OBJGPU *pGpu, KernelBif *pKernelBif, const PKBIF_XVE_REGMAP_REF pRegmapRef); +static NV_STATUS _kbifRestorePcieConfigRegisters_GM107(OBJGPU *pGpu, KernelBif *pKernelBif, const PKBIF_XVE_REGMAP_REF pRegmapRef); + /* ------------------------ Public Functions -------------------------------- */ /*! @@ -302,6 +306,355 @@ kbifPcieConfigDisableRelaxedOrdering_GM107 } } +/*! + * Helper function for bifSavePcieConfigRegisters_GM107() + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel Bif object pointer + * @param[in] pRegmapRef XVE Register map structure pointer + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +static NV_STATUS +_kbifSavePcieConfigRegisters_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + const PKBIF_XVE_REGMAP_REF pRegmapRef +) +{ + NV_STATUS status; + NvU16 index; + + // Read and save config space offset based on the bit map + for (index = 0; index < pRegmapRef->numXveRegMapValid; index++) + { + NvU16 i, regOffset, bufOffset; + NvU32 mask = 1; + + for (i = 0; i < sizeof(pRegmapRef->xveRegMapValid[0]) * 8; i++) + { + mask = 1 << i; + NV_ASSERT((pRegmapRef->xveRegMapWrite[index] & mask) == 0 || + (pRegmapRef->xveRegMapValid[index] & mask) != 0); + + if ((pRegmapRef->xveRegMapValid[index] & mask) == 0) + { + continue; + } + + bufOffset = (index * sizeof(pRegmapRef->xveRegMapValid[0]) * 8) + i; + regOffset = bufOffset * sizeof(pRegmapRef->bufBootConfigSpace[0]); + + status = PCI_FUNCTION_BUS_CFG_RD32(pGpu, pRegmapRef->nFunc, + regOffset, &pRegmapRef->bufBootConfigSpace[bufOffset]); + if (status != NV_OK) + { + return status; + } + } + } + + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SECONDARY_BUS_RESET_SUPPORTED, NV_TRUE); + + return NV_OK; +} + +/*! + * Save boot time PCIe Config space + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel Bif object pointer + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifSavePcieConfigRegisters_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NV_STATUS status; + + // + // Save config space if GPU is about to enter Function Level Reset + // OR if GPU is about to enter GC6 state + // OR if on non-windows platform, FORCE_PCIE_CONFIG_SAVE is set and SBR is snabled + // OR if on windows platform, SBR is enabled + // + if (!pKernelBif->bPreparingFunctionLevelReset && + !IS_GPU_GC6_STATE_ENTERING(pGpu) && + !((RMCFG_FEATURE_PLATFORM_WINDOWS || + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_FORCE_PCIE_CONFIG_SAVE)) && + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED))) + { + return NV_OK; + } + + // save pcie config space for function 0 + status = _kbifSavePcieConfigRegisters_GM107(pGpu, pKernelBif, + &pKernelBif->xveRegmapRef[0]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Saving PCIe config space failed for gpu.\n"); + NV_ASSERT(0); + return status; + } + + // No need to save/restore azalia config space if gpu is in GC6 cycle or if it is in FLR + if (IS_GPU_GC6_STATE_ENTERING(pGpu) || + pKernelBif->bPreparingFunctionLevelReset) + { + return NV_OK; + } + + // Return early if device is not multifunction (azalia is disabled or not present) + if (!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION)) + { + return NV_OK; + } + + // Save pcie config space for function 1 + status = _kbifSavePcieConfigRegisters_GM107(pGpu, pKernelBif, + &pKernelBif->xveRegmapRef[1]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Saving PCIe config space failed for azalia.\n"); + NV_ASSERT(0); + } + + return status; +} + +/*! + * Helper function for bifRestorePcieConfigRegisters_GM107() + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel Bif object pointer + * @param[in] pRegmapRef XVE Register map structure pointer + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +static NV_STATUS +_kbifRestorePcieConfigRegisters_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + const PKBIF_XVE_REGMAP_REF pRegmapRef +) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + NvU16 vendorId; + NvU16 deviceId; + NvU32 val; + NV_STATUS status; + void *handle; + NvU16 index; + RMTIMEOUT timeout; + NvBool bGcxPmuCfgRestore; + + bGcxPmuCfgRestore = pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_GCX_PMU_CFG_SPACE_RESTORE); + + handle = osPciInitHandle(domain, bus, device, pRegmapRef->nFunc, + &vendorId, &deviceId); + NV_ASSERT_OR_RETURN(handle, NV_ERR_INVALID_POINTER); + + if (IS_GPU_GC6_STATE_EXITING(pGpu) && + bGcxPmuCfgRestore) + { + // + // PMU Will Restore the config Space + // As a last step PMU should set CMD_MEMORY_SPACE ENABLED after it restores the config space + // Poll This register to see if PMU is finished or not otherwise timeout. + // + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + do + { + val = osPciReadDword(handle, NV_XVE_DEV_CTRL); + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "Timeout waiting for PCIE Config Space Restore from PMU, RM takes over\n"); + DBG_BREAKPOINT(); + + NvU32 *pReg = NULL; + pReg = &pRegmapRef->bufBootConfigSpace[NV_XVE_DEV_CTRL / + sizeof(pRegmapRef->bufBootConfigSpace[0])]; + *pReg = FLD_SET_DRF(_XVE, _DEV_CTRL, _CMD_MEMORY_SPACE, _ENABLED, *pReg); + osPciWriteDword(handle, NV_XVE_DEV_CTRL, pRegmapRef->bufBootConfigSpace[1]); + osPciWriteDword(handle, NV_XVE_BAR0, pRegmapRef->bufBootConfigSpace[4]); + + break; + } + } while (FLD_TEST_DRF(_XVE, _DEV_CTRL, _CMD_MEMORY_SPACE, _DISABLED, val)); + + return NV_OK; + } + + // Enable BAR0 accesses so we can restore config space more quickly. + kbifRestoreBar0_HAL(pGpu, pKernelBif, handle, pRegmapRef->bufBootConfigSpace); + + // Enable required fields of NV_XVE_DEV_CTRL + val = osPciReadDword(handle, NV_XVE_DEV_CTRL); + val = FLD_SET_DRF(_XVE, _DEV_CTRL, _CMD_MEMORY_SPACE, _ENABLED, val) | + FLD_SET_DRF(_XVE, _DEV_CTRL, _CMD_BUS_MASTER, _ENABLED, val); + osPciWriteDword(handle, NV_XVE_DEV_CTRL, val); + + // Restore only the valid config space offsets based on bit map + for (index = 0; index < pRegmapRef->numXveRegMapValid; index++) + { + NvU16 i, regOffset, bufOffset; + + for (i = 0; i < sizeof(pRegmapRef->xveRegMapValid[0]) * 8; i++) + { + if ((pRegmapRef->xveRegMapWrite[index] & (1 << i)) == 0) + { + continue; + } + + bufOffset = (index * sizeof(pRegmapRef->xveRegMapValid[0]) * 8) + i; + regOffset = bufOffset * sizeof(pRegmapRef->bufBootConfigSpace[0]); + if (regOffset == NV_XVE_DEV_CTRL) + { + continue; + } + + // + // This is a special case where we don't use the standard macro to write a register. + // The macro will not allow access when PDB_PROP_GPU_IS_LOST is true. + // This check is required to keep other accesses from touching the GPU for now. + // + osGpuWriteReg032(pGpu, + ((pRegmapRef->nFunc == 0) ? DEVICE_BASE(NV_PCFG) : DEVICE_BASE(NV_PCFG1)) + regOffset, + pRegmapRef->bufBootConfigSpace[bufOffset]); + + if (pRegmapRef->nFunc != 0) + { + status = PCI_FUNCTION_BUS_CFG_WR32(pGpu, pRegmapRef->nFunc, regOffset, + pRegmapRef->bufBootConfigSpace[bufOffset]); + if (status != NV_OK) + { + return status; + } + } + } + } + + // + // Restore saved value of NV_XVE_DEV_CTRL, the second register saved in the buffer. + // If we reach this point, it's RM-CPU restoration path. + // Check if PMU_CFG_SPACE_RESTORE property was enabled + // to confirm it's a debugging parallel restoration and + // set back to _ENABLE before restoration + // + if (bGcxPmuCfgRestore) + { + NvU32 *pReg = NULL; + pReg = &pRegmapRef->bufBootConfigSpace[NV_XVE_DEV_CTRL / + sizeof(pRegmapRef->bufBootConfigSpace[0])]; + *pReg = FLD_SET_DRF(_XVE, _DEV_CTRL, _CMD_MEMORY_SPACE, _ENABLED, *pReg); + + } + + osPciWriteDword(handle, NV_XVE_DEV_CTRL, pRegmapRef->bufBootConfigSpace[1]); + + return NV_OK; +} + +/*! + * Restore boot time PCIe Config space + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel Bif object pointer + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifRestorePcieConfigRegisters_GM107 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NV_STATUS status; + RMTIMEOUT timeout; + NvU64 timeStampStart; + NvU64 timeStampEnd; + + // Restore pcie config space for function 0 + status = _kbifRestorePcieConfigRegisters_GM107(pGpu, pKernelBif, + &pKernelBif->xveRegmapRef[0]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Restoring PCIe config space failed for gpu.\n"); + NV_ASSERT(0); + return status; + } + + // No need to save/restore azalia config space if gpu is in GC6 cycle or if it is in FLR + if (IS_GPU_GC6_STATE_EXITING(pGpu) || + pKernelBif->bInFunctionLevelReset) + { + // + // Check that GPU is really accessible. + // Skip on pre-silicon because there can be timing issues in the test between device ready and this code. + // Todo: find a safe timeout for pre-silicon runs + // + if (IS_SILICON(pGpu)) + { + // Check if GPU is actually accessible before continue + osGetPerformanceCounter(&timeStampStart); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + NvU32 pmcBoot0 = GPU_REG_RD32(pGpu, NV_PMC_BOOT_0); + + while (pmcBoot0 != pGpu->chipId0) + { + NV_PRINTF(LEVEL_INFO, + "GPU not back on the bus after %s, 0x%x != 0x%x!\n", + pKernelBif->bInFunctionLevelReset?"FLR":"GC6 exit", pmcBoot0, pGpu->chipId0); + pmcBoot0 = GPU_REG_RD32(pGpu, NV_PMC_BOOT_0); + NV_ASSERT(0); + status = gpuCheckTimeout(pGpu, &timeout); + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "Timeout GPU not back on the bus after %s,\n", pKernelBif->bInFunctionLevelReset?"FLR":"GC6 exit"); + DBG_BREAKPOINT(); + return status; + } + } + + osGetPerformanceCounter(&timeStampEnd); + NV_PRINTF(LEVEL_ERROR, + "Time spend on GPU back on bus is 0x%x ns,\n", + (NvU32)NV_MIN(NV_U32_MAX, timeStampEnd - timeStampStart)); + } + + return NV_OK; + } + + // Return early if device is not multifunction (azalia is disabled or not present) + if (!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_DEVICE_IS_MULTIFUNCTION)) + { + return NV_OK; + } + + // Restore pcie config space for function 1 + status = _kbifRestorePcieConfigRegisters_GM107(pGpu, pKernelBif, + &pKernelBif->xveRegmapRef[1]); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Restoring PCIe config space failed for azalia.\n"); + NV_ASSERT(0); + } + + return status; +} + /*! * @brief Get XVE status bits * @@ -626,12 +979,18 @@ kbifGetBusOptionsAddr_GM107 case BUS_OPTIONS_DEV_CONTROL_STATUS: *addrReg = NV_XVE_DEVICE_CONTROL_STATUS; break; + case BUS_OPTIONS_DEV_CONTROL_STATUS_2: + *addrReg = NV_XVE_DEVICE_CONTROL_STATUS_2; + break; case BUS_OPTIONS_LINK_CONTROL_STATUS: *addrReg = NV_XVE_LINK_CONTROL_STATUS; break; case BUS_OPTIONS_LINK_CAPABILITIES: *addrReg = NV_XVE_LINK_CAPABILITIES; break; + case BUS_OPTIONS_L1_PM_SUBSTATES_CTRL_1: + *addrReg = NV_XVE_L1_PM_SUBSTATES_CTRL1; + break; default: NV_PRINTF(LEVEL_ERROR, "Invalid register type passed 0x%x\n", options); @@ -654,7 +1013,7 @@ kbifDisableSysmemAccess_GM107 NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS params = {0}; // Only support on Windows - NV_ASSERT_OR_RETURN(RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM, NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN(RMCFG_FEATURE_PLATFORM_WINDOWS, NV_ERR_NOT_SUPPORTED); params.bDisable = bDisable; status = pRmApi->Control(pRmApi, diff --git a/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm200.c b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm200.c new file mode 100644 index 0000000000..42bac9a8ad --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm200.c @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* ------------------------- System Includes -------------------------------- */ +// TODO CLEANUP +#include "gpu/gpu.h" +#include "gpu/bif/kernel_bif.h" +#include "gpu/bus/kern_bus.h" +#include "platform/chipset/chipset.h" +#include "nvdevid.h" + +#include "published/maxwell/gm200/dev_boot.h" + +/*! + * @brief Get the PMC bit of the valid Engines to reset. + * + * @return All valid engines + */ +NvU32 +kbifGetValidEnginesToReset_GM200 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return (DRF_DEF(_PMC, _ENABLE, _PGRAPH, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PMEDIA, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PFIFO, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PWR, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PDISP, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVDEC, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _SEC, _ENABLED)); +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/pascal/kernel_bif_gp100.c b/src/nvidia/src/kernel/gpu/bif/arch/pascal/kernel_bif_gp100.c new file mode 100644 index 0000000000..670aec9d55 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bif/arch/pascal/kernel_bif_gp100.c @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* ------------------------- System Includes -------------------------------- */ +#include "gpu/gpu.h" +#include "gpu/bif/kernel_bif.h" +#include "published/pascal/gp100/dev_boot.h" + +/* ------------------------ Public Functions -------------------------------- */ + +/*! + * @brief Get the PMC bit of the valid Engines to reset. + * + * @return All valid engines + */ +NvU32 +kbifGetValidEnginesToReset_GP100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return (DRF_DEF(_PMC, _ENABLE, _PGRAPH, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PMEDIA, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE3, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE4, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE5, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PFIFO, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PWR, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PDISP, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVDEC, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _SEC, _ENABLED)); +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/pascal/kernel_bif_gp10X.c b/src/nvidia/src/kernel/gpu/bif/arch/pascal/kernel_bif_gp10X.c new file mode 100644 index 0000000000..14fd88e6d7 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bif/arch/pascal/kernel_bif_gp10X.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* ------------------------- System Includes -------------------------------- */ +#include "gpu/gpu.h" +#include "gpu/bif/kernel_bif.h" +#include "published/pascal/gp102/dev_boot.h" + +/* ------------------------ Public Functions -------------------------------- */ + + +/*! + * @brief Get the PMC bit of the valid Engines to reset. + * + * @return All valid engines + */ +NvU32 +kbifGetValidEnginesToReset_GP10X +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return (DRF_DEF(_PMC, _ENABLE, _PGRAPH, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PMEDIA, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PFIFO, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PDISP, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVDEC, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _SEC, _ENABLED)); +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c index 760f10f63c..7faa4edc31 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,8 +28,6 @@ #include "gpu/gpu.h" #include "platform/chipset/chipset.h" -#define NV_VGPU_EMU 0x0000FFFF:0x0000F000 /* RW--D */ - #include "virtualization/kernel_vgpu_mgr.h" #include "virtualization/hypervisor/hypervisor.h" @@ -37,6 +35,9 @@ #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/dev_nv_pcfg_xve_regmap.h" +#include "published/turing/tu102/dev_boot.h" + +#define RTLSIM_DELAY_SCALE_US 8 // XVE register map for PCIe config space static const NvU32 xveRegMapValid[] = NV_PCFG_XVE_REGISTER_VALID_MAP; @@ -131,12 +132,6 @@ kbifGetVFSparseMmapRegions_TU102 pSizes = portMemAllocStackOrHeap(NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES * sizeof(pSizes[0])); } - // For SRIOV heavy, trap BOOT_0 page - if (gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) - { - offsetStart = osPageSize; - } - // For VF TLB emulation, trap MMU FAULT BUFFER page if ((maxInstance > 1) && pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE)) { @@ -148,24 +143,9 @@ kbifGetVFSparseMmapRegions_TU102 offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + osPageSize; } - // For non-GSP, trap VGPU_EMU page - if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + // Trap MSI-X table page + if (!hypervisorIsType(OS_HYPERVISOR_HYPERV)) { - offsetEnd = DRF_BASE(NV_VGPU_EMU); - pOffsets[idx] = offsetStart; - pSizes[idx] = offsetEnd - offsetStart; - idx++; - - offsetStart = DRF_BASE(NV_VGPU_EMU) + osPageSize; - } - - // Trap MSI-X table page for non-Hyperv and Hyperv non-GSP cases - if (!hypervisorIsType(OS_HYPERVISOR_HYPERV) - ) - { - // Assert whenever the MSI-X table page is not immediately after - // the NV_VGPU_EMU page, as it will break the current assumption. - ct_assert((DRF_BASE(NV_VGPU_EMU) + DRF_SIZE(NV_VGPU_EMU)) == NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0)); offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0); @@ -429,10 +409,323 @@ kbifInitXveRegMap_TU102 NvU32 kbifGetMSIXTableVectorControlSize_TU102 ( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelBif *pKernelBif ) { return NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1; } +/*! + * This function saves MSIX vector control masks which can later be restored + * using bifRestoreMSIXVectorControlMasks_HAL. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Pointer to KernelBif object + * @param[out] *msixVectorMask MSIX vector control mask state for all + * MSIX table entries + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifSaveMSIXVectorControlMasks_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 *msixVectorMask +) +{ + NvU32 i; + NvU32 regVal; + NV_STATUS status = NV_OK; + NvU32 controlSize = kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif); + + //Sanity check for size + if (controlSize > 32U) + { + NV_PRINTF(LEVEL_ERROR, + "Size of MSIX vector control exceeds maximum assumed size!!\n"); + DBG_BREAKPOINT(); + + status = NV_ERR_BUFFER_TOO_SMALL; + goto kbifSaveMSIXVectorControlMasks_TU102_exit; + } + + // Set the bits in msixVectorMask if NV_MSIX_TABLE_VECTOR_CONTROL(i) is masked + *msixVectorMask = 0U; + for (i = 0U; i < controlSize; i++) + { + regVal = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i)); + + if (FLD_TEST_DRF(_VIRTUAL_FUNCTION_PRIV, _MSIX_TABLE_VECTOR_CONTROL, + _MASK_BIT, _MASKED, regVal)) + { + (*msixVectorMask) |= NVBIT(i); + } + } + +kbifSaveMSIXVectorControlMasks_TU102_exit: + return status; +} + +/*! + * This function restores MSIX vector control masks to the saved state. Vector + * control mask needs to be saved using bifSaveMSIXVectorControlMasks_HAL. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Pointer to KernelBif object + * @param[in] msixVectorMask State of MSIX vector control masks + * + * @return 'NV_OK' if successful, an RM error code otherwise. + */ +NV_STATUS +kbifRestoreMSIXVectorControlMasks_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 msixVectorMask +) +{ + NvU32 i; + NV_STATUS status = NV_OK; + NvU32 controlSize = kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif); + + // Initialize the base offset for the virtual registers for physical function + NvU32 vRegOffset = pGpu->sriovState.virtualRegPhysOffset; + + //Sanity check for size + if (controlSize > 32U) + { + NV_PRINTF(LEVEL_ERROR, + "Size of MSIX vector control exceeds maximum assumed size!!\n"); + DBG_BREAKPOINT(); + status = NV_ERR_BUFFER_TOO_SMALL; + goto kbifRestoreMSIXVectorControlMasks_TU102_exit; + } + + // + // Restore NV_MSIX_TABLE_VECTOR_CONTROL(i) based on msixVectorMask + // In FLR path, we don't want to use usual register r/w macros + // + for (i = 0U; i < controlSize; i++) + { + if ((NVBIT(i) & msixVectorMask) != 0U) + { + osGpuWriteReg032(pGpu, + vRegOffset + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i), + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED); + } + else + { + osGpuWriteReg032(pGpu, + vRegOffset + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i), + NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED); + } + } + +kbifRestoreMSIXVectorControlMasks_TU102_exit: + return status; +} + + +/** + * + * Do function level reset for Fn0. + * + */ +NV_STATUS +kbifDoFunctionLevelReset_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 domain = gpuGetDomain(pGpu); + NvU8 bus = gpuGetBus(pGpu); + NvU8 device = gpuGetDevice(pGpu); + void *handle = NULL; + NV_STATUS status = NV_OK; + NvU32 i; + NvU32 tempRegVal; + NvU16 vendorId; + NvU16 deviceId; + // 'i'th bit set to 1 indicates NV_MSIX_TABLE_VECTOR_CONTROL(i) is masked + NvU32 msixVectorMask; + NvBool bMSIXEnabled; + // volatile is required to prevent any compiler optimizations + volatile NvU32 tempRegValSwReset; + + // + // From the experimental data: We need to get the handle before asserting FLR + // GPU is always at function 0 + // + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + + pKernelBif->bPreparingFunctionLevelReset = NV_TRUE; + + status = kbifSavePcieConfigRegisters_HAL(pGpu, pKernelBif); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + NV_PRINTF(LEVEL_ERROR, "Config registers save failed!\n"); + goto bifDoFunctionLevelReset_TU102_exit; + } + + bMSIXEnabled = kbifIsMSIXEnabledInHW_HAL(pGpu, pKernelBif); + if (bMSIXEnabled) + { + status = kbifSaveMSIXVectorControlMasks_HAL(pGpu, pKernelBif, &msixVectorMask); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + NV_PRINTF(LEVEL_ERROR, "MSIX vector control registers save failed!\n"); + goto bifDoFunctionLevelReset_TU102_exit; + } + } + + pKernelBif->bPreparingFunctionLevelReset = NV_FALSE; + if (pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_FLR_PRE_CONDITIONING_REQUIRED)) + { + // + // SW WARs required for Function Level Reset - + // Clear Bus Master Enable bit in command register so that no more requests to sysmem are made by Fn0 + // Executing these WARs after save config space so that restore config space does not restore- + // incorrect command register + // For other WARs which are executed in bifPrepareForFullChipReset_HAL, gpu re-init sequence after FLR makes + // sure to revert these WARs + // + if (kbifStopSysMemRequests_HAL(pGpu, pKernelBif, NV_TRUE) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "BIF Stop Sys Mem requests failed.\n"); + DBG_BREAKPOINT(); + } + // Wait for number of sysmem transactions pending to go to 0 + if (kbifWaitForTransactionsComplete_HAL(pGpu, pKernelBif) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "BIF Wait for Transactions complete failed.\n"); + DBG_BREAKPOINT(); + } + } + + // Trigger FLR now + kbifTriggerFlr_HAL(pGpu, pKernelBif); + + pKernelBif->bInFunctionLevelReset = NV_TRUE; + + // wait a bit to make sure reset is propagated properly + if (IS_RTLSIM(pGpu)) + { + // + // On RTL sims the OS delay functions don't scale well. + // Instead we use reg reads as approximate delays + // + NV_PRINTF(LEVEL_ERROR, + "Do config reads of NV_XVE_SW_RESET to add delay\n"); + // Set 1ms/1000us delay - this would be acceptable delay for RTL sim + for( i = 0; i < (1000 * RTLSIM_DELAY_SCALE_US) ; i++) + { + // Only config reads and that too of sticky registers are supposed to work while Fn0 is under reset + tempRegValSwReset = osPciReadDword(handle, NV_XVE_SW_RESET); + } + // Printing tempRegValSwReset in order to use it and suppress compiler warnings(of variable set but not used) + NV_PRINTF(LEVEL_ERROR, "NV_XVE_SW_RESET read returned %x\n", + tempRegValSwReset); + } + else + { + // Wait for 100 ms before attempting to read PCI config space + osDelayUs(100000); + } + + status = kbifRestorePcieConfigRegisters_HAL(pGpu, pKernelBif); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + NV_PRINTF(LEVEL_ERROR, "Config registers restore failed!\n"); + goto bifDoFunctionLevelReset_TU102_exit; + } + + // As of GA10X, miata rom cannot be run on simulation. + if (IS_SILICON(pGpu) || IS_EMULATION(pGpu)) + { + // On emulation VBIOS boot can take long so add prints for better visibility + if (IS_EMULATION(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Entering secure boot completion wait.\n"); + } + status = NV_ERR_NOT_SUPPORTED; + if (status != NV_OK) + { + DBG_BREAKPOINT(); + NV_PRINTF(LEVEL_ERROR, "VBIOS boot failed!!\n"); + goto bifDoFunctionLevelReset_TU102_exit; + } + if (IS_EMULATION(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, + "Exited secure boot completion wait with status = NV_OK.\n"); + } + } + + if (bMSIXEnabled) + { + // TODO-NM: Check if this needed for other NVPM flows like GC6 + status = kbifRestoreMSIXVectorControlMasks_HAL(pGpu, pKernelBif, msixVectorMask); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + NV_PRINTF(LEVEL_ERROR, "MSIX vector control restore failed!\n"); + goto bifDoFunctionLevelReset_TU102_exit; + } + } + + // Re-init handle as well since gpu is reset + handle = osPciInitHandle(domain, bus, device, 0, &vendorId, &deviceId); + tempRegVal = osPciReadDword(handle, NV_XVE_ID); + if (!FLD_TEST_DRF(_XVE, _ID, _VENDOR, _NVIDIA, tempRegVal)) + { + status = NV_ERR_GENERIC; + goto bifDoFunctionLevelReset_TU102_exit; + } + +bifDoFunctionLevelReset_TU102_exit: + pKernelBif->bPreparingFunctionLevelReset = NV_FALSE; + pKernelBif->bInFunctionLevelReset = NV_FALSE; + return status; +} + +/*! + * @brief Get the PMC bit of the valid Engines to reset. + * + * @return All valid engines + */ +NvU32 +kbifGetValidEnginesToReset_TU102 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return (DRF_DEF(_PMC, _ENABLE, _PGRAPH, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PMEDIA, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE3, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE4, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE5, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE6, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE7, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE8, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PFIFO, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PWR, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PDISP, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVDEC0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVDEC1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVDEC2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _SEC, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PERFMON, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVJPG0, _ENABLED)); +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/bif/arch/volta/kernel_bif_gv100.c b/src/nvidia/src/kernel/gpu/bif/arch/volta/kernel_bif_gv100.c new file mode 100644 index 0000000000..f9d0fe771d --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bif/arch/volta/kernel_bif_gv100.c @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "gpu/bif/kernel_bif.h" + +// TODO CLEANUP +#include "published/volta/gv100/dev_boot.h" + +/*! + * @brief Get the PMC bit of the valid Engines to reset. + * + * @return All valid engines + */ +NvU32 +kbifGetValidEnginesToReset_GV100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return (DRF_DEF(_PMC, _ENABLE, _PGRAPH, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PMEDIA, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE3, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE4, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE5, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE6, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE7, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE8, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PFIFO, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PWR, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PDISP, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVDEC, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _SEC, _ENABLED)); +} diff --git a/src/nvidia/src/kernel/gpu/bif/arch/volta/kernel_bif_gv11b.c b/src/nvidia/src/kernel/gpu/bif/arch/volta/kernel_bif_gv11b.c new file mode 100644 index 0000000000..c2a64b08ce --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bif/arch/volta/kernel_bif_gv11b.c @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/bif/kernel_bif.h" + +#include "published/volta/gv11b/dev_boot.h" + + +/*! + * @brief Get the PMC bit of the valid Engines to reset. + * + * @return All valid engines + */ +NvU32 +kbifGetValidEnginesToReset_GV11B +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + return (DRF_DEF(_PMC, _ENABLE, _PGRAPH, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PMEDIA, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _CE2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PFIFO, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PWR, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _PDISP, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVDEC, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC0, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC1, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _NVENC2, _ENABLED) | + DRF_DEF(_PMC, _ENABLE, _SEC, _ENABLED)); +} diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c index 6a63381d97..39cc8812da 100644 --- a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c +++ b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c @@ -88,6 +88,9 @@ kbifConstructEngine_IMPL // Used to track when the link has gone into Recovery, which can cause CEs. pKernelBif->EnteredRecoverySinceErrorsLastChecked = NV_FALSE; + // Default scale is 1 and could be overriden by registry + pKernelBif->flrDevInitTimeoutScale = 1; + return NV_OK; } @@ -166,6 +169,12 @@ kbifStateLoad_IMPL // Check for stale PCI-E dev ctrl/status errors and AER errors kbifClearConfigErrors(pGpu, pKernelBif, NV_TRUE, KBIF_CLEAR_XVE_AER_ALL_MASK); + // Cache PCI config registers to be restored during resume + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH)) + { + kbifSavePcieConfigRegisters_HAL(pGpu, pKernelBif); + } + // // A vGPU cannot disappear and these accesses are // particularly expensive on vGPUs @@ -173,7 +182,7 @@ kbifStateLoad_IMPL if (pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_CHECK_IF_GPU_EXISTS_DEF) && !IS_VIRTUAL(pGpu)) { - osSchedule1SecondCallback(pGpu, _kbifCheckIfGpuExists, NULL, NV_OS_1HZ_REPEAT); + osSchedule1HzCallback(pGpu, _kbifCheckIfGpuExists, NULL, NV_OS_1HZ_REPEAT); } return NV_OK; @@ -435,7 +444,8 @@ kbifCheckAndRearmMSI_IMPL if (kbifIsMSIEnabled(pGpu, pKernelBif)) { - if (!IS_VIRTUAL(pGpu)) + if (!IS_VIRTUAL(pGpu) || + pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_ALLOW_REARM_MSI_FOR_VF)) { // Send EOI to rearm if (pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI)) @@ -723,6 +733,65 @@ _kbifInitRegistryOverrides pKernelBif->peerMappingOverride = !!data32; } + // Check if the PCIe SBR recovery feature is enabled. + if (osReadRegistryDword(pGpu, NV_REG_STR_SECONDARY_BUS_RESET_ENABLED, &data32) == NV_OK) + { + if (data32) + { + // The regkey was set to a non-zero value, enable the feature. + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED, NV_TRUE); + } + else + { + // The regkey was set to 0, disable the feature. + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_SECONDARY_BUS_RESET_ENABLED, NV_FALSE); + } + } + + // Check if saving of the PCIe config space during SBR is enabled. + if (osReadRegistryDword(pGpu, NV_REG_STR_FORCE_PCIE_CONFIG_SAVE, &data32) == NV_OK) + { + if (data32) + { + // The regkey was set to a non-zero value, enable config save + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_FORCE_PCIE_CONFIG_SAVE, NV_TRUE); + } + else + { + // The regkey was set to a 0, disable config save + pKernelBif->setProperty(pBif, PDB_PROP_KBIF_FORCE_PCIE_CONFIG_SAVE, NV_FALSE); + } + } + + // Check if Function Level Reset(FLR) is disabled + pKernelBif->bForceDisableFLR = NV_REG_STR_RM_PCIE_FLR_POLICY_DEFAULT; + if (osReadRegistryDword(pGpu, + NV_REG_STR_RM_PCIE_FLR_POLICY, &data32) == NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Pcie FLR Policy reg key = %d\n", data32); + + if (data32 == NV_REG_STR_RM_PCIE_FLR_POLICY_FORCE_DISABLE) + { + pKernelBif->bForceDisableFLR = NV_TRUE; + } + // There might be a requirement to handle (data32 == NV_REG_STR_RM_PCIE_FLR_POLICY_DEFAULT) case as per platform's policy + else + { + pKernelBif->bForceDisableFLR = NV_FALSE; + } + } + + // Check for FLR timeout scale override + if (osReadRegistryDword(pGpu, + NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE, &data32) == NV_OK) + { + if ((data32 >= NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE_MIN_ALLOWED) && + (data32 <= NV_REG_STR_RM_PCIE_FLR_DEVINIT_TIMEOUT_SCALE_MAX_ALLOWED)) + { + pKernelBif->flrDevInitTimeoutScale = data32; + } + } + } /*! @@ -742,11 +811,19 @@ _kbifCheckIfGpuExists { if (gpuVerifyExistence_HAL(pGpu) != NV_OK) { - osRemove1SecondRepeatingCallback(pGpu, _kbifCheckIfGpuExists, NULL); + osRemove1HzCallback(pGpu, _kbifCheckIfGpuExists, NULL); } } } +/*! + * @brief Get link capabilities register value + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return Register value + */ NvU32 kbifGetGpuLinkCapabilities_IMPL ( @@ -771,6 +848,14 @@ kbifGetGpuLinkCapabilities_IMPL return data; } +/*! + * @brief Get link control status register value + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return Register value + */ NvU32 kbifGetGpuLinkControlStatus_IMPL ( @@ -795,6 +880,102 @@ kbifGetGpuLinkControlStatus_IMPL return data; } +/*! + * @brief Get device control status register value + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return Register value + */ +NvU32 +kbifGetGpuDevControlStatus_IMPL +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 addrDevControlStatus = 0; + NvU32 data = 0; + + if (NV_OK != kbifGetBusOptionsAddr_HAL(pGpu, pKernelBif, BUS_OPTIONS_DEV_CONTROL_STATUS, &addrDevControlStatus)) + { + return 0; + } + + if (NV_OK != GPU_BUS_CFG_RD32(pGpu, addrDevControlStatus, &data )) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read %x\n", addrDevControlStatus); + return 0; + } + + return data; +} + +/*! + * @brief Get device control status 2 register value + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return Register value + */ +NvU32 +kbifGetGpuDevControlStatus2_IMPL +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 addrDevControlStatus2 = 0; + NvU32 data = 0; + + if (NV_OK != kbifGetBusOptionsAddr_HAL(pGpu, pKernelBif, BUS_OPTIONS_DEV_CONTROL_STATUS_2, &addrDevControlStatus2)) + { + return 0; + } + + if (NV_OK != GPU_BUS_CFG_RD32(pGpu, addrDevControlStatus2, &data )) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read %x\n", addrDevControlStatus2); + return 0; + } + + return data; +} + +/*! + * @brief Get L1 Substates control register value + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KernelBif object pointer + * + * @return Register value + */ +NvU32 +kbifGetGpuL1PmSubstatesCtrl1_IMPL +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 addrL1PmSubstatesCtrl1 = 0; + NvU32 data = 0; + + if (NV_OK != kbifGetBusOptionsAddr_HAL(pGpu, pKernelBif, BUS_OPTIONS_L1_PM_SUBSTATES_CTRL_1, &addrL1PmSubstatesCtrl1)) + { + return 0; + } + + if (NV_OK != GPU_BUS_CFG_RD32(pGpu, addrL1PmSubstatesCtrl1, &data )) + { + NV_PRINTF(LEVEL_ERROR, "Unable to read %x\n", addrL1PmSubstatesCtrl1); + return 0; + } + + return data; +} + static NvBool _doesBoardHaveMultipleGpusAndSwitch(OBJGPU *pGpu) { diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif_vgpu.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif_vgpu.c new file mode 100644 index 0000000000..d828baefe7 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bif/kernel_bif_vgpu.c @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/bif/kernel_bif.h" +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" +#include "vgpu/sdk-structures.h" + +/*! + * @brief Set the coherency cap for vGPU + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif Kernel BIF object pointer + */ +void +kbifInitDmaCaps_VGPUSTUB +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + // + // Ideally, we should query this from host RM. + // Current all VGPU systems support coherency. + // So it should be OK to hardcode it. + // + // As per Neo, we only want to expose CPU cache snoop caps. + // This is to force all VGPU memory allocations to be coherent. + // + pKernelBif->dmaCaps = REF_DEF(BIF_DMA_CAPS_SNOOP, _CTXDMA); +} + +/*! + * @brief Get static info for VGPU + * + * @param[in] pGpu GPU object pointer + * @param[in] pParams Static info parameters + * + * @return NV_OK + */ +NV_STATUS +subdeviceCtrlCmdBifGetStaticInfo_VGPUSTUB +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + // + // Ideally, we should query this from host RM. + // However, except for C2C, other parameters are do-not-care + // on guest RM as of today, hence enforcing default values + // + pParams->bIsC2CLinkUp = pVSI->bC2CLinkUp; + pParams->dmaWindowStartAddress = 0ull; + pParams->bPcieGen4Capable = NV_FALSE; + pParams->bIsDeviceMultiFunction = NV_FALSE; + pParams->bGcxPmuCfgSpaceRestore = NV_FALSE; + + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdBusGetPcieReqAtomicsCaps_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + portMemCopy(pParams, sizeof(*pParams), + &pVSI->busGetPcieReqAtomicsCaps, sizeof(pVSI->busGetPcieReqAtomicsCaps)); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c index 49508e6965..6b168270da 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c @@ -41,6 +41,7 @@ #include "mem_mgr/fabric_vaspace.h" #include "mem_mgr/virt_mem_mgr.h" #include +#include "platform/sli/sli.h" #include "published/ampere/ga100/dev_nv_xve.h" #include "published/ampere/ga100/dev_ram.h" // NV_RAMIN_ALLOC_SIZE diff --git a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c index 2feb9c52da..cc6a276633 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c @@ -61,6 +61,42 @@ // RM reserved memory region is mapped separately as it is not added to the kernel #define COHERENT_CPU_MAPPING_RM_RESV_REGION COHERENT_CPU_MAPPING_REGION_1 +/*! + * @brief Tear Down BAR1 Mailbox + * + * Destroys Bar1 VA Space. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * + * @returns void + */ +void +kbusTeardownMailbox_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 bar1Block = 0; + + // set bar1 mode to physical and vidmem so we don't accidentally corrupt sysmem + bar1Block = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR); + bar1Block = FLD_SET_DRF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _MODE, _PHYSICAL, bar1Block); + bar1Block = FLD_SET_DRF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _TARGET, _VID_MEM, bar1Block); + + // + // override the aperture to sysmem if FB is not present. + // + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) && RMCFG_FEATURE_MODS_FEATURES) + { + bar1Block = FLD_SET_DRF( + _VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _TARGET, _SYS_MEM_NONCOHERENT, bar1Block); + } + + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR, bar1Block); +} + /*! * @brief Gets the P2P write mailbox address size (NV_XAL_EP_P2P_WMBOX_ADDR_ADDR) * @@ -577,7 +613,7 @@ kbusTeardownBar2CpuAperture_GH100 kbusFlushVirtualBar2_HAL(pGpu, pKernelBus, NV_FALSE, gfid); - if (pKernelBus->virtualBar2[gfid].pCpuMapping) + if (pKernelBus->virtualBar2[gfid].pCpuMapping != NULL) { osUnmapPciMemoryKernelOld(pGpu, (void*)pKernelBus->virtualBar2[gfid].pCpuMapping); // Mark the BAR as un-initialized so that a later call @@ -876,8 +912,8 @@ kbusCreateCoherentCpuMapping_GH100 KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); NvP64 pCpuMapping = NvP64_NULL; NvU64 fbSize; - NvU64 busAddrStart; - NvU64 busAddrSize; + NvU64 busAddrStart[COHERENT_CPU_MAPPING_TOTAL_REGIONS]; + NvU64 busAddrSize[COHERENT_CPU_MAPPING_TOTAL_REGIONS]; NvU32 i; NvU64 memblockSize; NvU32 cachingMode[COHERENT_CPU_MAPPING_TOTAL_REGIONS]; @@ -906,8 +942,25 @@ kbusCreateCoherentCpuMapping_GH100 pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_RM_RESV_REGION] = fbSize - pKernelBus->coherentCpuMapping.size[COHERENT_CPU_MAPPING_REGION_0]; + for (i = COHERENT_CPU_MAPPING_REGION_0; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) + { + busAddrStart[i] = pKernelMemorySystem->coherentCpuFbBase + + pKernelBus->coherentCpuMapping.physAddr[i]; + busAddrSize[i] = pKernelBus->coherentCpuMapping.size[i]; + } + if (pKernelMemorySystem->bBug3656943WAR) { + if (IS_PASSTHRU(pGpu)) + { + // + // For passthrough case, reserved memory guest physical address + // comes from BAR1 address. + // + busAddrStart[COHERENT_CPU_MAPPING_RM_RESV_REGION] = + pKernelMemorySystem->coherentRsvdFbBase; + } + // // RM reserved region should be mapped as Normal Non-cacheable as a SW WAR // for the bug 3656943. NV_MEMORY_WRITECOMBINED translates to linux @@ -923,13 +976,11 @@ kbusCreateCoherentCpuMapping_GH100 for (i = COHERENT_CPU_MAPPING_REGION_0; i < pKernelBus->coherentCpuMapping.nrMapping; ++i) { - busAddrStart = pKernelMemorySystem->coherentCpuFbBase + pKernelBus->coherentCpuMapping.physAddr[i]; - busAddrSize = pKernelBus->coherentCpuMapping.size[i]; // In SHH, CPU uses coherent C2C link to access GPU memory and hence it can be accessed cached. status = osMapPciMemoryKernel64(pGpu, - (NvUPtr)busAddrStart, - (NvU64)busAddrSize, + (NvUPtr)busAddrStart[i], + (NvU64)busAddrSize[i], NV_PROTECT_READ_WRITE, &(pCpuMapping), cachingMode[i]); @@ -937,7 +988,8 @@ kbusCreateCoherentCpuMapping_GH100 NV_ASSERT_OR_RETURN(status == NV_OK, NV_ERR_GENERIC); pKernelBus->coherentCpuMapping.pCpuMapping[i] = (NvP64)pCpuMapping; - pKernelBus->coherentCpuMapping.size[i] = busAddrSize; + NV_PRINTF(LEVEL_INFO, "coherent link mapping. i: %d base: 0x%llx size: 0x%llx \n", + i, busAddrStart[i], busAddrSize[i]); NV_ASSERT_OR_RETURN(bFlush == NV_FALSE, NV_ERR_NOT_SUPPORTED); @@ -1004,17 +1056,23 @@ kbusVerifyCoherentLink_GH100 // Ensure the writes are flushed out of the CPU caches. osFlushGpuCoherentCpuCacheRange(pGpu->pOsGpuInfo, (NvUPtr)pOffset, size); - flagsClean = NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL | - NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN; - if (kmemsysIsL2CleanFbPull(pKernelMemorySystem)) - { - flagsClean |= NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL; - } - status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flagsClean); - if (NV_OK != status) + // L2 invalidate registers are not present in VF BAR0. PF driver should have tested this on host so + // skipping this on SRIOV guest + if (!IS_VIRTUAL(pGpu)) { - NV_PRINTF(LEVEL_ERROR, "L2 evict failed\n"); - goto busVerifyCoherentLink_failed; + flagsClean = NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL | + NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_CLEAN; + if (kmemsysIsL2CleanFbPull(pKernelMemorySystem)) + { + flagsClean |= NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_WAIT_FB_PULL; + } + + status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, flagsClean); + if (NV_OK != status) + { + NV_PRINTF(LEVEL_ERROR, "L2 evict failed\n"); + goto busVerifyCoherentLink_failed; + } } for(index = 0; index < size; index += 4) @@ -2209,26 +2267,6 @@ kbusAllocateFlaVaspace_GH100 "failed binding instblk for FLA, status=0x%x\n", status); goto free_instblk; } - if (GPU_GET_KERNEL_NVLINK(pGpu) != NULL) - { - NVLINK_INBAND_MSG_CALLBACK inbandMsgCbParams; - - inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP; - inbandMsgCbParams.pCallback = &memorymulticastfabricTeamSetupResponseCallback; - inbandMsgCbParams.wqItemFlags = OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW; - - status = knvlinkRegisterInbandCallback(pGpu, - GPU_GET_KERNEL_NVLINK(pGpu), - &inbandMsgCbParams); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Registering Inband Cb failed\n", - gpuGetInstance(pGpu)); - goto free_instblk; - } - - } // setup Unicast FLA range in Fabric VAS object if (!GPU_IS_NVSWITCH_DETECTED(pGpu)) @@ -2303,12 +2341,6 @@ kbusDestroyFla_GH100 // TODO: Remove this once legacy FLA VAS support is deprecated pRmApi->Free(pRmApi, pKernelBus->flaInfo.hClient, pKernelBus->flaInfo.hClient); portMemSet(&pKernelBus->flaInfo, 0, sizeof(pKernelBus->flaInfo)); - if (GPU_GET_KERNEL_NVLINK(pGpu) != NULL) - { - // Unregister the receive callback - NV_ASSERT_OK(knvlinkUnregisterInbandCallback(pGpu, GPU_GET_KERNEL_NVLINK(pGpu), - NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP)); - } } } } @@ -2560,3 +2592,276 @@ kbusRestoreBAR1ResizeSize_WAR_BUG_3249028_GH100 return NV_OK; } + +/*! + * @brief Bind BAR2 + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * @param[in] bar2Mode BAR2 binding mode + * + * @returns NV_OK on success. + */ +NV_STATUS +kbusBindBar2_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + BAR2_MODE bar2Mode +) +{ + NvU32 gfid; + RMTIMEOUT timeout; + NvU32 temp; + NvU32 valueLowAddr; + NvU32 valueHighAddr; + NvU32 instBlkAperture = 0; + NvU64 instBlkAddr = 0; + NV_STATUS status = NV_OK; + NvBool bIsModePhysical; + MEMORY_DESCRIPTOR *pMemDesc; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + if (pKernelBus->bar2[gfid].bBootstrap && + (NULL != pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap) && + kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + pMemDesc = pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap; + } + else + { + pMemDesc = pKernelBus->bar2[gfid].pInstBlkMemDesc; + } + + // + // Bind BAR2 to virtual. Carefully. We have not initialized PTEs yet. We will first + // map the BAR2 PTEs into BAR2. This allows us to use the BAR2 interface to invalidate + // the rest of the BAR2 PTEs. WC memory writes are faster than single BAR0 writes + // and this matters for RTL sim and emulation. + // + bIsModePhysical = (BAR2_MODE_PHYSICAL == bar2Mode); + + if (!bIsModePhysical) + { + instBlkAperture = kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pMemDesc); + instBlkAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + } + + valueLowAddr = + ((bIsModePhysical ? DRF_DEF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _TARGET, _VID_MEM) : + DRF_NUM(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _TARGET, instBlkAperture)) | + (bIsModePhysical ? DRF_DEF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _MODE, _PHYSICAL) : + DRF_DEF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _MODE, _VIRTUAL)) | + (bIsModePhysical ? DRF_NUM(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _PTR, 0x0) : + DRF_NUM(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _PTR, + NvU64_LO32(instBlkAddr >> NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_PTR_SHIFT)))); + + valueHighAddr = NvU64_HI32(instBlkAddr); + + // + // For BAR1 and BAR2 binds, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR should be written + // first followed with the HIGH. Write to the HIGH register triggers the bind. + // + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR, valueLowAddr); + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_HIGH_ADDR, valueHighAddr); + + osFlushCpuWriteCombineBuffer(); + + // Skip the wait if we are in the reset path (GPU most likely in a bad state) + if (!IS_VIRTUAL(pGpu) && API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + return status; + } + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + do + { + // + // To avoid deadlocks and non-deterministic virtual address + // translation behavior, after writing BAR2_BLOCK to bind BAR2 to a + // virtual address space, SW must ensure that the bind has completed + // prior to issuing any further BAR2 requests by polling for both + // NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PENDING to return to EMPTY and + // NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_OUTSTANDING to return to NV_FALSE. + // + // BAR2_PENDING indicates a Bar2 bind is waiting to be sent. + // BAR2_OUTSTANDING indicates a Bar2 bind is outstanding to FB. + // + temp = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR); + + if (FLD_TEST_DRF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _BAR2_PENDING, _EMPTY, temp) && + FLD_TEST_DRF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR2_BLOCK_LOW_ADDR, _BAR2_OUTSTANDING, _FALSE, temp)) + { + status = NV_OK; + break; + } + + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "timed out waiting for bar2 binding to complete\n"); + DBG_BREAKPOINT(); + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + osSpinLoop(); + } while (1); + + return status; +} + +/*! + * @brief Bind BAR1 instance block + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * + * @returns NV_OK on success. + */ +NV_STATUS +kbusBar1InstBlkBind_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 gfid; + NvU32 target; + NvU32 temp; + NvU32 ptrLow; + NvU32 ptrHigh; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + NvU32 blockMode = 0; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + // Nothing to be done in guest in the paravirtualization case. + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) + { + return NV_OK; + } + + switch (kgmmuGetMemAperture(pKernelGmmu, pKernelBus->bar1[gfid].pInstBlkMemDesc)) + { + case GMMU_APERTURE_VIDEO: + target = NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_VID_MEM; + break; + case GMMU_APERTURE_SYS_COH: + target = NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT; + break; + case GMMU_APERTURE_SYS_NONCOH: + target = NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT; + break; + default: + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + + // + // BAR1 address is 4K-aligned, we do not need to specify the lower 12 bit (11:0) of address. + // Thus we are storing the upper 32-bit of the 64-bit address pointer as BAR1_BLOCK_HIGH_ADDR[31:0], + // and the lower 20-bit of the 64-bit pointer as BAR1_BLOCK_LOW_ADDR[31:12]. + // + ptrLow = NvU64_LO32(pKernelBus->bar1[gfid].instBlockBase >> NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_PTR_SHIFT); + ptrHigh = NvU64_HI32(pKernelBus->bar1[gfid].instBlockBase); + + if (kbusIsBar1PhysicalModeEnabled(pKernelBus)) + { + blockMode = DRF_DEF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _MODE, _PHYSICAL); + } + else + { + blockMode = DRF_DEF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _MODE, _VIRTUAL); + } + + // + // For BAR1 and BAR2 binds, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR should be written + // first followed with the HIGH. Write to the HIGH register triggers the bind. + // + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR, + DRF_NUM(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _TARGET, target) | blockMode | + DRF_NUM(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _PTR, ptrLow)); + + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_HIGH_ADDR, + DRF_NUM(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_HIGH_ADDR, _PTR, ptrHigh)); + + osFlushCpuWriteCombineBuffer(); + + // Skip the wait if we are in the reset path (GPU most likely in a bad state) + if (!IS_VIRTUAL(pGpu) && API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + return status; + } + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + do + { + // + // To avoid deadlocks and non-deterministic virtual address + // translation behavior, after writing BAR1_BLOCK to bind BAR1 to a + // virtual address space, SW must ensure that the bind has completed + // prior to issuing any further BAR1 requests by polling for both + // NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_PENDING to return to EMPTY and + // NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR_OUTSTANDING to return to NV_FALSE. + // + // BAR1_PENDING indicates a Bar1 bind is waiting to be sent. + // BAR1_OUTSTANDING indicates a Bar1 bind is outstanding to FB. + // + temp = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR1_BLOCK_LOW_ADDR); + + if (FLD_TEST_DRF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _BAR1_PENDING, _EMPTY, temp) && + FLD_TEST_DRF(_VIRTUAL_FUNCTION_PRIV_FUNC, _BAR1_BLOCK_LOW_ADDR, _BAR1_OUTSTANDING, _FALSE, temp)) + { + status = NV_OK; + break; + } + + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "timed out waiting for bar1 binding to complete\n"); + DBG_BREAKPOINT(); + break; + } + status = gpuCheckTimeout(pGpu, &timeout); + osSpinLoop(); + } while (1); + + return status; +} + +NvU32 +kbusGetEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 regVal; + NvU32 count = 0; + + // PCIE RE ORDER + regVal = GPU_REG_RD32(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT); + count += DRF_VAL(_XAL_EP, _REORDER_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // PCIE P2PREQ + regVal = GPU_REG_RD32(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT); + count += DRF_VAL(_XAL_EP, _P2PREQ_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + return count; +} + +void +kbusClearEccCounts_GH100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + // Reset XAL-EP counts + GPU_REG_WR32(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT, 0); + GPU_REG_WR32(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT, 0); +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index fb1b2bc04c..cb98d8eefb 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -24,6 +24,7 @@ #include "core/core.h" #include "gpu/conf_compute/conf_compute.h" #include "gpu/gpu.h" +#include "gpu/device/device.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" #include "gpu/bif/kernel_bif.h" @@ -39,6 +40,7 @@ #include "rmapi/rs_utils.h" #include "vgpu/rpc.h" #include "nvRmReg.h" +#include "platform/sli/sli.h" #include "gpu/mem_mgr/fermi_dma.h" @@ -48,6 +50,8 @@ #include "class/cl90f1.h" // FERMI_VASPACE_A +#define MAXWELL_BAR2_VBIOS_OFFSET (BUS_BAR2_RM_APERTURE_MB<<20) + // // forwards // @@ -146,8 +150,13 @@ kbusStatePreInitLocked_GM107 { NV_PRINTF(LEVEL_INFO, "gpu:%d\n", pGpu->gpuInstance); + if (FLD_TEST_DRF(_REG_STR_RM, _INST_VPR, _INSTBLK, _TRUE, pGpu->instVprOverrides)) + { + pKernelBus->bInstProtectedMem = NV_TRUE; + } + // kbusInitBarsSize_HAL for VGPU is called in early phase - if (! IS_VIRTUAL(pGpu)) + if (!IS_VIRTUAL(pGpu)) { NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kbusInitBarsSize_HAL(pGpu, pKernelBus)); @@ -195,7 +204,7 @@ kbusSetupDefaultBar0Window // Do NOT ever move this BAR0 window away from the last 1MB since it's // shared with the vbios // - if (pMemorySystemConfig->bReservedMemAtBottom) + if (pMemoryManager->bReservedMemAtBottom) { offsetBar0 = memmgrGetRsvdMemoryBase(pMemoryManager); } @@ -276,10 +285,6 @@ kbusStateInitLockedKernel_GM107 _kbusInitP2P_GM107(pGpu, pKernelBus); } } - else - { - pKernelBus->bP2pInitialized = NV_TRUE; - } } if (!KBUS_BAR0_PRAMIN_DISABLED(pGpu)) @@ -287,6 +292,17 @@ kbusStateInitLockedKernel_GM107 kbusSetupDefaultBar0Window(pGpu, pKernelBus); } + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + vgpuGspTeardownBuffers(pGpu); + + if (pKernelBus->bIsBar2SetupInPhysicalMode) + { + kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); + pKernelBus->bIsBar2SetupInPhysicalMode= NV_FALSE; + } + } + // // Initialize BAR2 before initializing BAR1. That way, we can use BAR2 // rather than BAR0 to set up the BAR1 page table. This is faster because @@ -306,6 +322,23 @@ kbusStateInitLockedKernel_GM107 vgpuGspSetupBuffers(pGpu); } + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + pKernelBus->bFlaSupported = pVSI->bFlaSupported; + + NV_PRINTF(LEVEL_INFO, "Enabling FLA Support in Guest RM: %x, flabase: %llx, flaSize: %llx \n", + pVSI->bFlaSupported, pVSI->flaInfo.base, pVSI->flaInfo.size); + + // if FLA supported enable FLA VAS + if (kbusIsFlaSupported(pKernelBus)) + { + NV_STATUS status = kbusCheckFlaSupportedAndInit_HAL(pGpu, pKernelBus, pVSI->flaInfo.base, pVSI->flaInfo.size); + NV_ASSERT(status == NV_OK); + } + } + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) { // Verify that BAR2 and the MMU actually works @@ -334,10 +367,12 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) return NV_OK; } - ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); - - if (IS_GSP_CLIENT(pGpu) && (pConfCompute != NULL) && - !(pConfCompute->ccStaticInfo.bIsBar1Trusted && pConfCompute->ccStaticInfo.bIsPcieTrusted)) + // + // Block BAR2 whenever HCC is enabled irrespective of prod and devtools mode + // unless user has used regkey to force BAR access on devtools mode + // + if (IS_GSP_CLIENT(pGpu) && gpuIsCCFeatureEnabled(pGpu) && + !pKernelBus->bForceBarAccessOnHcc) { pKernelBus->bBarAccessBlocked = NV_TRUE; pKernelBus->bBar2TestSkipped = NV_TRUE; @@ -374,17 +409,25 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) // if (!RMCFG_FEATURE_PLATFORM_GSP) // contiguous BAR2 { - NV_PRINTF(LEVEL_INFO, "C2C is being used (contiguous/MONOLITHIC), update BAR2 cpuInvisibleBase: 0x%llX to 0, and cpuInvisibleLimit: 0x%llX to 0x%llX. Setting cpuVisibleLimit: 0x%llX to 0\n", - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit, - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, - pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit); - NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase == 0); NV_ASSERT(pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit >= pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase); - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit -= pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase; - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase = pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase; + if (pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase == (pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit + 1)) + { + NV_PRINTF(LEVEL_INFO, "Contiguous range, update BAR2 cpuInvisibleBase: 0x%llX to 0, and cpuInvisibleLimit: 0x%llX to 0x%llX.\n", + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit, + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit - pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase); + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit -= pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase; + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase = pKernelBus->bar2[GPU_GFID_PF].cpuVisibleBase; + } + else + { + NV_PRINTF(LEVEL_INFO, "Discontiguous range, retaining BAR2 cpuInvisibleBase: 0x%llX, and cpuInvisibleLimit: 0x%llX.\n", + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleBase, + pKernelBus->bar2[GPU_GFID_PF].cpuInvisibleLimit); + } } + NV_PRINTF(LEVEL_INFO, "Setting cpuVisibleLimit: 0x%llX to 0\n", pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit); pKernelBus->bar2[GPU_GFID_PF].cpuVisibleLimit = 0; pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; } @@ -398,6 +441,14 @@ kbusStateInitLocked_IMPL(OBJGPU *pGpu, KernelBus *pKernelBus) NV_ASSERT_OK_OR_RETURN(kbusStateInitLockedPhysical_HAL(pGpu, pKernelBus)); + if (pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc != NULL) + { + // Initialize the BAR1 instance block to zero + NV_ASSERT_OK_OR_RETURN(memmgrMemDescMemSet(GPU_GET_MEMORY_MANAGER(pGpu), + pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc, + 0, TRANSFER_FLAGS_NONE)); + } + return NV_OK; } @@ -438,7 +489,11 @@ kbusStatePreLoad_GM107 NV_ASSERT(IsTEGRA(pGpu)); } - NV_ASSERT_OK_OR_RETURN(kbusRestoreBar2_HAL(pKernelBus, flags)); + if (!IsMAXWELL(pGpu)) + { + // Bug 4351702 WAR: restore BAR2 after FBSR on Maxwell + NV_ASSERT_OK_OR_RETURN(kbusRestoreBar2_HAL(pKernelBus, flags)); + } } return NV_OK; @@ -452,6 +507,11 @@ kbusStateLoad_GM107 NvU32 flags ) { + if (IS_VIRTUAL(pGpu) && (flags & GPU_STATE_FLAGS_PRESERVING)) + { + NV_ASSERT_OK_OR_RETURN(kbusBar1InstBlkBind_HAL(pGpu, pKernelBus)); + } + if (!IS_GPU_GC6_STATE_EXITING(pGpu)) { if (!IS_VIRTUAL_WITH_FULL_SRIOV(pGpu)) @@ -474,6 +534,12 @@ kbusStateLoad_GM107 } } + if ((flags & GPU_STATE_FLAGS_PRESERVING) && IsMAXWELL(pGpu)) + { + // Bug 4351702 WAR: restore BAR2 after FBSR on Maxwell + NV_ASSERT_OK_OR_RETURN(kbusRestoreBar2_HAL(pKernelBus, flags)); + } + return NV_OK; } @@ -496,6 +562,13 @@ kbusRestoreBar2_GM107 NV_ASSERT_OK_OR_RETURN(kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF)); } + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + // Use BAR2 in physical mode to write the PDEs. + NV_ASSERT_OK_OR_RETURN(kbusBindBar2_HAL(pGpu, pKernelBus, BAR2_MODE_PHYSICAL)); + NV_ASSERT_OK_OR_RETURN(kbusCommitBar2PDEs_HAL(pGpu, pKernelBus)); + } + else { // // Only write PDEs here @@ -617,7 +690,7 @@ kbusStatePostLoad_GM107 (!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) && - !gpuIsSelfHosted(pGpu)) + (IsSLIEnabled(pGpu) || IsUnlinkedSLIEnabled(pGpu))) { _kbusLinkP2P_GM107(pGpu, pKernelBus); } @@ -627,6 +700,39 @@ kbusStatePostLoad_GM107 return status; } +/*! + * @brief Tear Down BAR1 Mailbox + * + * Destroys Bar1 VA Space. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * + * @returns void + */ +void +kbusTeardownMailbox_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU32 bar1Block; + + // set bar1 mode to physical and vidmem so we don't accidentally corrupt sysmem + bar1Block = GPU_REG_RD32(pGpu, NV_PBUS_BAR1_BLOCK); + bar1Block = FLD_SET_DRF(_PBUS, _BAR1_BLOCK, _MODE, _PHYSICAL, bar1Block); + bar1Block = FLD_SET_DRF(_PBUS, _BAR1_BLOCK, _TARGET, _VID_MEM, bar1Block); + + // + // override the aperture to sysmem if FB is not present. + // + if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB)) && RMCFG_FEATURE_MODS_FEATURES) + bar1Block = FLD_SET_DRF(_PBUS, _BAR1_BLOCK, _TARGET, _SYS_MEM_NONCOHERENT, bar1Block); + + GPU_REG_WR32(pGpu, NV_PBUS_BAR1_BLOCK, bar1Block); +} + NV_STATUS kbusStatePreUnload_GM107 ( @@ -635,8 +741,7 @@ kbusStatePreUnload_GM107 NvU32 flags ) { - if (!((flags & GPU_STATE_FLAGS_PRESERVING) || - IS_GPU_GC6_STATE_ENTERING(pGpu))) + if (!((flags & GPU_STATE_FLAGS_PRESERVING) || IS_GPU_GC6_STATE_ENTERING(pGpu))) { // // Get rid of the bars if this is not PM. There were/are issues with user-mode @@ -645,6 +750,7 @@ kbusStatePreUnload_GM107 // teardown bar1 path when entering suspend. // kbusDestroyBar1_HAL(pGpu, pKernelBus, GPU_GFID_PF); + kbusTeardownMailbox_HAL(pGpu, pKernelBus); } return NV_OK; @@ -689,7 +795,7 @@ kbusStateUnload_GM107 // RM managed P2P or unconfiguring HW P2P for OS suspend/hibernate (!kbusIsP2pMailboxClientAllocated(pKernelBus) || (flags & GPU_STATE_FLAGS_PM_TRANSITION)) - && !gpuIsSelfHosted(pGpu)) + && (IsSLIEnabled(pGpu) || IsUnlinkedSLIEnabled(pGpu))) { kbusUnlinkP2P_HAL(pGpu, pKernelBus); } @@ -733,7 +839,7 @@ kbusInitBar1_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) OBJVMM *pVmm = SYS_GET_VMM(pSys); NvU32 gpuMask = 0; NvBool bSmoothTransitionEnabled = ((pGpu->uefiScanoutSurfaceSizeInMB != 0) && - RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM); + RMCFG_FEATURE_PLATFORM_WINDOWS); NvBool bBar1P2PCapable; vaRangeMax = pKernelBus->bar1[gfid].apertureLength - 1; @@ -1196,6 +1302,12 @@ kbusInitBar2_GM107 status = kbusSetupBar2GpuVaSpace_HAL(pGpu, pKernelBus, gfid); NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + status = kbusSetupBar2PageTablesAtTopOfFb_HAL(pGpu, pKernelBus, gfid); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + } + status = kbusCommitBar2_HAL(pGpu, pKernelBus, GPU_STATE_DEFAULT); NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); @@ -1227,8 +1339,9 @@ kbusInitBar2_GM107 NV_STATUS kbusDestroyBar2_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) { - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; + // Tear down buffers to avoid leaking BAR2 mappings if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) { vgpuGspTeardownBuffers(pGpu); @@ -1238,8 +1351,7 @@ kbusDestroyBar2_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) // Nothing to be done in guest in the paravirtualization case or // if guest is running in SRIOV heavy mode. // - if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || - (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu)) { return NV_OK; } @@ -1275,6 +1387,23 @@ kbusDestroyBar2_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) kbusSendSysmembar(pGpu, pKernelBus); } + // + // Bring up BAR2 and RPC buffers again to allow RPC. + // On VGPU-GSP guest we have to retain the BAR2 mapping for RPC to GSP until the driver is + // unloaded. Therefore unmapping BAR2 is deferred until we send UNLOADING_GUEST_DRIVER RPC + // event. + // + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + kbusBar2BootStrapInPhysicalMode_HAL(pGpu, pKernelBus); + NV_ASSERT(IS_GFID_PF(gfid)); + } + + vgpuGspSetupBuffers(pGpu); + } + return status; } @@ -1295,8 +1424,7 @@ kbusSetupBar2CpuAperture_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) NV_STATUS status = NV_OK; // Nothing to be done in guest in the paravirtualization case. - if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || IS_GFID_VF(gfid) || - (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || IS_GFID_VF(gfid) || IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu)) { return NV_OK; } @@ -1322,6 +1450,8 @@ kbusSetupBar2CpuAperture_GM107(OBJGPU *pGpu, KernelBus *pKernelBus, NvU32 gfid) return NV_OK; } + NV_ASSERT_OR_RETURN(pKernelBus->bar2[gfid].physAddr != 0, NV_ERR_INVALID_STATE); + // // Map bar2 space -- only map the space we use in the RM. Some 32b OSes are *cramped* // for kernel virtual addresses. @@ -1371,8 +1501,7 @@ kbusTeardownBar2CpuAperture_GM107 ) { // Nothing to be done in guest in the paravirtualization case. - if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || IS_GFID_VF(gfid) || - (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || IS_VIRTUAL_WITH_HEAVY_SRIOV(pGpu) || IS_GFID_VF(gfid)) { return NV_OK; } @@ -1495,8 +1624,23 @@ kbusSetupBar2GpuVaSpace_GM107 pKernelBus->bar2[gfid].pteBase += memmgrGetRsvdMemoryBase(pMemoryManager); } - if (IS_GFID_PF(gfid) && - !KBUS_BAR0_PRAMIN_DISABLED(pGpu)) + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && + ((pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) || + ((ADDR_FBMEM == pKernelBus->PDEBAR2Aperture) && + (ADDR_FBMEM == pKernelBus->PTEBAR2Aperture)))) + { + pKernelBus->bar2[gfid].bBootstrap = NV_TRUE; + // + // Issue a bind in physical mode so that we may bootstrap the BAR2 + // tables and write the instance block using BAR2 PA mode. + // + status = kbusBindBar2_HAL(pGpu, pKernelBus, BAR2_MODE_PHYSICAL); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + status = kbusSetupBar2PageTablesAtBottomOfFb_HAL(pGpu, pKernelBus, gfid); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + } + else if (IS_GFID_PF(gfid) && !KBUS_BAR0_PRAMIN_DISABLED(pGpu)) { // Setup BAR0 window for page directory/table updates during BAR2 bootstrap status = kbusSetupBar0WindowBeforeBar2Bootstrap_HAL(pGpu, pKernelBus, &origVidOffset); @@ -1689,6 +1833,27 @@ kbusSetupBar2GpuVaSpace_GM107 pKernelBus->virtualBar2[gfid].pPDB = pKernelBus->bar2[gfid].pPDEMemDesc; } + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && + (pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap != NULL)) + { + // + // This should be done before BAR2 is switched to virtual mode + // because we can have flushes coming in when we start to use vitual BAR2. + // + status = kbusSetupCpuPointerForBusFlush_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + + if (pKernelBus->virtualBar2[gfid].pPageLevelsForBootstrap == NULL) + { + status = kbusPreInitVirtualBar2_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + } + + // Bind the temporary instance block w/ the temporary PDB. + status = kbusBindBar2_HAL(pGpu, pKernelBus, BAR2_MODE_VIRTUAL); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + } + kbusPatchBar2Pdb_HAL(pGpu, pKernelBus); cleanup: @@ -1803,6 +1968,13 @@ kbusTeardownBar2GpuVaSpace_GM107 NV_ASSERT_OK_OR_RETURN(mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, NULL)); + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + // Free the temporary instance block and page level instances. + kbusTeardownBar2PageTablesAtBottomOfFb_HAL(pGpu, pKernelBus, gfid); + kbusTeardownBar2InstBlkAtBottomOfFb_HAL(pGpu, pKernelBus, gfid); + } + mmuWalkDestroy(pKernelBus->bar2[gfid].pWalk); pKernelBus->bar2[gfid].pWalk = NULL; pKernelBus->bar2[gfid].pPDEMemDesc = NULL; @@ -3521,7 +3693,7 @@ kbusStateDestroy_GM107 if ((pKernelBif != NULL) && ((!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) && (kbusIsP2pInitialized(pKernelBus))) && - !gpuIsSelfHosted(pGpu)) + (IsSLIEnabled(pGpu) || IsUnlinkedSLIEnabled(pGpu))) { (void)_kbusDestroyP2P_GM107(pGpu, pKernelBus); } @@ -3844,10 +4016,6 @@ kbusInitBarsBaseInfo_GM107 KernelBus *pKernelBus ) { - // pKernelBus->pciBars[] should be initialized before the function gets called - NV_ASSERT_OR_RETURN(pKernelBus->pciBars[BUS_BAR_1] != 0, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(pKernelBus->pciBars[BUS_BAR_2] != 0, NV_ERR_INVALID_STATE); - pKernelBus->bar1[GPU_GFID_PF].physAddr = pKernelBus->pciBars[BUS_BAR_1]; pKernelBus->bar2[GPU_GFID_PF].physAddr = pKernelBus->pciBars[BUS_BAR_2]; @@ -4705,6 +4873,1069 @@ kbusBar1InstBlkVasUpdate_GM107 kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); kbusSendSysmembar(pGpu, pKernelBus); + NV_ASSERT_OK_OR_RETURN(kbusBar1InstBlkBind_HAL(pGpu, pKernelBus)); + + return NV_OK; +} + +/*! + * Previous bind sequence would just do a sysmembar after a flush. + * Now the flushes don't guarantee anything for the BIND itself. + * Just that previous reads/writes are complete. + * We need to use the BIND_STATUS register now. + * New procedure: + * - Write NV_PBUS_BLOCK_(BAR1|BAR2) + * - Poll NV_PBUS_BIND_STATUS to make sure the BIND completed. + */ +NV_STATUS +kbusBindBar2_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + BAR2_MODE bar2Mode +) +{ + RMTIMEOUT timeout; + NvU32 temp; + NvU32 value; + NvU32 instBlkAperture = 0; + NvU64 instBlkAddr = 0; + NV_STATUS status = NV_OK; + NvBool bIsModePhysical; + MEMORY_DESCRIPTOR *pMemDesc; + + if (pKernelBus->bar2[GPU_GFID_PF].bBootstrap && + (NULL != pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDescForBootstrap) && + kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + pMemDesc = pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDescForBootstrap; + } + else + { + pMemDesc = pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc; + } + + // + // Bind BAR2 to virtual. Carefully. We have not initialized PTEs yet. We will first + // map the BAR2 PTEs into BAR2. This allows us to use the BAR2 interface to invalidate + // the rest of the BAR2 PTEs. WC memory writes are faster than single BAR0 writes + // and this matters for RTL sim and emulation. DEBUG_CYA = OFF keeps the VBIOS + // aperture in physical addressing. + // + bIsModePhysical = (BAR2_MODE_PHYSICAL == bar2Mode); + + if (!bIsModePhysical) + { + instBlkAperture = kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pMemDesc); + instBlkAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + } + + value = ((bIsModePhysical ? DRF_DEF(_PBUS, _BAR2_BLOCK, _TARGET, _VID_MEM) : + DRF_NUM(_PBUS, _BAR2_BLOCK, _TARGET, instBlkAperture)) | + (bIsModePhysical ? DRF_DEF(_PBUS, _BAR2_BLOCK, _MODE, _PHYSICAL) : + DRF_DEF(_PBUS, _BAR2_BLOCK, _MODE, _VIRTUAL)) | + (bIsModePhysical ? DRF_NUM(_PBUS, _BAR2_BLOCK, _PTR, 0x0) : + DRF_NUM(_PBUS, _BAR2_BLOCK, _PTR, + NvU64_LO32(instBlkAddr >> GF100_BUS_INSTANCEBLOCK_SHIFT))) | + DRF_DEF(_PBUS, _BAR2_BLOCK, _DEBUG_CYA, _OFF)); + + GPU_REG_WR32(pGpu, NV_PBUS_BAR2_BLOCK, value); + + osFlushCpuWriteCombineBuffer(); + + // Skip the wait if we are in the reset path (GPU most likely in a bad state) + if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + return status; + } + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + do + { + // + // To avoid deadlocks and non-deterministic virtual address + // translation behavior, after writing BAR2_BLOCK to bind BAR2 to a + // virtual address space, SW must ensure that the bind has completed + // prior to issuing any further BAR2 requests by polling for both + // NV_PBUS_BIND_STATUS_BAR2_PENDING to return to EMPTY and + // NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING to return to FALSE. + // + // BAR2_PENDING indicates a Bar2 bind is waiting to be sent. + // BAR2_OUTSTANDING indicates a Bar2 bind is outstanding to FB. + // + temp = GPU_REG_RD32(pGpu, NV_PBUS_BIND_STATUS); + if (FLD_TEST_DRF(_PBUS, _BIND_STATUS, _BAR2_PENDING, _EMPTY, temp) && + FLD_TEST_DRF(_PBUS, _BIND_STATUS, _BAR2_OUTSTANDING, _FALSE, temp)) + { + status = NV_OK; + break; + } + + if (NV_ERR_TIMEOUT == status) + { + NV_PRINTF(LEVEL_ERROR, + "timed out waiting for bar2 binding to complete\n"); + DBG_BREAKPOINT(); + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + osSpinLoop(); + } while (1); + + return status; +} + +/*! + * @brief This sets up the instance block for BAR1 and BAR2 + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * @param[in] pEngCommon Engine whose instance mem is being written (Bar1 or Bar2) + * @param[in] pInstBlkMemDesc NULL if BAR2 aperture not set up yet: BAR2 instance block using BAR0 window + * @param[in] pPDB PDB pointer for the instance blocks PDB + * @param[in] vaLimit VALimit to set for this instance + * @param[in] bigPageSize VASPACE Big page size (relevant for maxwell+) + * + * @returns NV_STATUS +*/ +NV_STATUS +kbusInitInstBlk_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + PMEMORY_DESCRIPTOR pInstBlkMemDesc, + PMEMORY_DESCRIPTOR pPDB, + NvU64 vaLimit, + NvU64 bigPageSize, + OBJVASPACE *pVAS +) +{ + NvU32 windowOffset = 0; + NvU8 *pMap; + + if (pInstBlkMemDesc == NULL) + { + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + return kbusSetupBar2InstBlkAtBottomOfFb_HAL(pGpu, pKernelBus, pPDB, vaLimit, bigPageSize, GPU_GFID_PF); + } + // find the offset of the bar ctx block into the BAR0 window + NvU64 origVidOffset = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); + NV_ASSERT_OK_OR_RETURN(kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, pKernelBus->bar2[GPU_GFID_PF].instBlockBase & ~0xffffULL)); + // find the offset of the BAR2 instance block into the BAR0 window + windowOffset = NvU64_LO32(pKernelBus->bar2[GPU_GFID_PF].instBlockBase - kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus)); + GPU_REG_WR32(pGpu, windowOffset + NV_PRAMIN_DATA008(0) + SF_OFFSET(NV_RAMIN_ADR_LIMIT_LO), + NvU64_LO32(vaLimit) | 0xfff); + GPU_REG_WR32(pGpu, windowOffset + NV_PRAMIN_DATA008(0) + SF_OFFSET(NV_RAMIN_ADR_LIMIT_HI), + SF_NUM(_RAMIN_ADR_LIMIT, _HI, NvU64_HI32(vaLimit))); + GPU_REG_WR32(pGpu, windowOffset + NV_PRAMIN_DATA008(0) + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_HI), + SF_NUM(_RAMIN_PAGE_DIR_BASE, _HI, NvU64_HI32(memdescGetPhysAddr(pPDB, AT_GPU, 0)))); + GPU_REG_WR32(pGpu, windowOffset + NV_PRAMIN_DATA008(0) + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_TARGET), + SF_NUM(_RAMIN_PAGE_DIR_BASE, _TARGET, kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pPDB)) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _VOL, memdescGetVolatility(pPDB)) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _LO, NvU64_LO32(memdescGetPhysAddr(pPDB, AT_GPU, 0) >> PDB_SHIFT_FERMI))); + NV_ASSERT_OK_OR_RETURN(kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, origVidOffset)); + } + else + { + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + pMap = kbusMapRmAperture_HAL(pGpu, pInstBlkMemDesc); + if (pMap == NULL) + { + SLI_LOOP_RETURN(NV_ERR_INSUFFICIENT_RESOURCES); + } + kbusBar2InstBlkWrite_HAL(pGpu, pKernelBus, pMap, pPDB, vaLimit, bigPageSize); + kbusUnmapRmAperture_HAL(pGpu, pInstBlkMemDesc, &pMap, NV_TRUE); + if (pKernelBus->bar2[GPU_GFID_PF].bMigrating) + { + // + // Remove memdesc from cached mappings as the page tables backing + // this mapping will be discarded and the old VA to PA translation + // won't be valid. + // + kbusReleaseRmAperture_HAL(pGpu, pKernelBus, pInstBlkMemDesc); + } + SLI_LOOP_END + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + } return NV_OK; } +/*! + * @brief This sets up the instance block for BAR1 and BAR2 + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * @param[in] pMap Opaque pointer in CPU/GPU VASPACE + * @param[in] pPDB PDB pointer for BAR2 VAS. + * @param[in] vaLimit VALimit to set for this instance + * @param[in] bigPageSize VASPACE Big page size (relevant for maxwell+) + * + * @returns NV_STATUS +*/ +void +kbusBar2InstBlkWrite_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU8 *pMap, + PMEMORY_DESCRIPTOR pPDB, + NvU64 vaLimit, + NvU64 bigPageSize +) +{ + NV_ASSERT_OR_RETURN_VOID(NULL != pMap); + + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_ADR_LIMIT_LO), NvU64_LO32(vaLimit) | 0xfff); + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_ADR_LIMIT_HI), SF_NUM(_RAMIN_ADR_LIMIT, _HI, + NvU64_HI32(vaLimit))); + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_HI), + SF_NUM(_RAMIN_PAGE_DIR_BASE, _HI, + NvU64_HI32(memdescGetPhysAddr(pPDB, AT_GPU, 0)))); + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_TARGET), + SF_NUM(_RAMIN_PAGE_DIR_BASE, _TARGET, kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pPDB)) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _VOL, memdescGetVolatility(pPDB)) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _LO, + NvU64_LO32(memdescGetPhysAddr(pPDB, AT_GPU, 0) >> PDB_SHIFT_FERMI))); +} + +/*! + * @brief Sets up starting addresses for BAR2 page directories and tables + * within the bottom 32MB of FB for bootstrapping. + * + * In physical mode, BAR2 window points to bottom 32MB of FB. CPU + * mapping is created only for lower 16MB of this window. So, the BAR2 + * level instances should fit within the bottom 16M of FB if we intend to + * to use CPU mapping for bootstrapping the page level instances. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * + * @returns NV_OK + */ +NV_STATUS +kbusSetupBar2PageTablesAtBottomOfFb_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) +{ + NV_STATUS status = NV_OK; + + if ((ADDR_FBMEM == pKernelBus->PDEBAR2Aperture) && + (ADDR_FBMEM == pKernelBus->PTEBAR2Aperture)) + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU64 pageLvlSize; + NvU64 allocSize; + NvU64 physAddr; + + NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap); + + pageLvlSize = kbusGetSizeOfBar2PageDirs_HAL(pGpu, pKernelBus) + + kbusGetSizeOfBar2PageTables_HAL(pGpu, pKernelBus); + + physAddr = kgmmuGetBigPageSize_HAL(pKernelGmmu) + GF100_BUS_INSTANCEBLOCK_SIZE; + + status = memdescCreate(&pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap, + pGpu, + pageLvlSize, + RM_PAGE_SIZE, + NV_TRUE, + pKernelBus->PDEBAR2Aperture, + pKernelBus->PDEBAR2Attr, + MEMDESC_FLAGS_NONE); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + memdescDescribe(pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap, + pKernelBus->PDEBAR2Aperture, + physAddr, + pageLvlSize); + + physAddr = memdescGetPhysAddr(pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap, + AT_GPU, 0); + pKernelBus->bar2[gfid].pdeBaseForBootstrap = physAddr; + + physAddr += kbusGetSizeOfBar2PageDirs_HAL(pGpu, pKernelBus); + physAddr = NV_ROUNDUP(physAddr, RM_PAGE_SIZE); + pKernelBus->bar2[gfid].pteBaseForBootstrap = physAddr; + + allocSize = kgmmuGetBigPageSize_HAL(pKernelGmmu) + + GF100_BUS_INSTANCEBLOCK_SIZE + + pageLvlSize; + + if (allocSize >= (pKernelBus->bar2[gfid].rmApertureLimit + 1)) + { + NV_PRINTF(LEVEL_ERROR, + "Init memory size (0x%x) > BAR2 window mapped to CPU (0x%llx)\n", + NvU64_LO32(allocSize), pKernelBus->bar2[gfid].rmApertureLimit + 1); + memdescDestroy(pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + } + else + { + // Ensure that BAR2 page tables and directories are in same aperture. + NV_ASSERT(pKernelBus->PDEBAR2Aperture == pKernelBus->PTEBAR2Aperture); + } + + return status; +} + +/*! + * @brief Frees the BAR2 page level instances at the bottom of FB and the + memory descriptor that was allocated during init to describe the + * block of memory containing the page level instances. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * + * @returns + */ +void +kbusTeardownBar2PageTablesAtBottomOfFb_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) +{ + MMU_WALK_USER_CTX userCtx = {0}; + + userCtx.pGpu = pGpu; + + if (NULL != pKernelBus->bar2[gfid].pWalkForBootstrap) + { + NV_ASSERT_OK(mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalkForBootstrap, &userCtx)); + mmuWalkLevelInstancesForceFree(pKernelBus->bar2[gfid].pWalkForBootstrap); + NV_ASSERT_OK(mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalkForBootstrap, NULL)); + mmuWalkDestroy(pKernelBus->bar2[gfid].pWalkForBootstrap); + pKernelBus->bar2[gfid].pWalkForBootstrap = NULL; + + // Free staging buffer + memdescFree(pKernelBus->bar2[gfid].pWalkStagingBuffer); + memdescDestroy(pKernelBus->bar2[gfid].pWalkStagingBuffer); + pKernelBus->bar2[gfid].pWalkStagingBuffer = NULL; + } + + memdescDestroy(pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap); + pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap = NULL; +} + +/*! + * @brief This sets up a temporary instance block for BAR2 at the bottom of FB + * before BAR2 is bootstrapped. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * @param[in] pPDB PDB pointer for the instance block's PDB + * @param[in] vaLimit VALimit to set for this instance + * @param[in] bigPageSize VASPACE Big page size (relevant for maxwell+) + * + * @returns NV_STATUS + */ +NV_STATUS +kbusSetupBar2InstBlkAtBottomOfFb_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + PMEMORY_DESCRIPTOR pPDB, + NvU64 vaLimit, + NvU64 bigPageSize, + NvU32 gfid +) +{ + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU8 *pMap; + NV_STATUS status = NV_OK; + + if (ADDR_FBMEM == pKernelBus->InstBlkAperture) + { + NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap); + + if (NULL == pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap) + { + status = memdescCreate(&pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap, + pGpu, + GF100_BUS_INSTANCEBLOCK_SIZE, + GF100_BUS_INSTANCEBLOCK_SIZE, + NV_TRUE, + pKernelBus->InstBlkAperture, + pKernelBus->InstBlkAttr, + MEMDESC_FLAGS_NONE); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + memdescDescribe(pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap, + pKernelBus->InstBlkAperture, + kgmmuGetBigPageSize_HAL(pKernelGmmu), + GF100_BUS_INSTANCEBLOCK_SIZE); + } + + pMap = kbusCpuOffsetInBar2WindowGet(pGpu, pKernelBus, + pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap); + if (NULL == pMap) + { + memdescDestroy(pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap); + pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap = NULL; + NV_ASSERT_OR_RETURN(NULL != pMap, NV_ERR_INVALID_POINTER); + } + + // Write the instance block. + kbusBar2InstBlkWrite_HAL(pGpu, pKernelBus, pMap, pPDB, vaLimit, bigPageSize); + } + + return status; +} + +/*! + * @brief Frees the temporary instance block after instance block + * has moved to top of FB. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * + * @returns None + */ +void +kbusTeardownBar2InstBlkAtBottomOfFb_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) +{ + memdescDestroy(pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap); + pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap = NULL; +} + +/*! + * @brief Sets up the BAR2 page level instances at the top of FB. + * + * In physical mode, BAR2 window points to first 32MB of FB. The BAR2 + * window is fixed and cannot be moved around like NV_PRAMIN. So, if we + * we are to use BAR2 PA mode for bootstrapping the page tables, we have + * to place the page tables within first 32M of FB. Once the bootstrapping + * is done, we can use this function to initialize the PTEs at the top of + * FB. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * + * @returns NV_OK + */ +NV_STATUS +kbusSetupBar2PageTablesAtTopOfFb_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) +{ + MMU_WALK *pWalk = NULL; + const MMU_FMT_LEVEL *pLevelFmt = NULL; + MMU_WALK_USER_CTX userCtx = {0}; + MMU_WALK_FLAGS walkFlags = {0}; + NV_STATUS status; + + // Do nothing if BAR2 page directories/tables are in sysmem. + if ((ADDR_FBMEM != pKernelBus->PDEBAR2Aperture) || + (ADDR_FBMEM != pKernelBus->PTEBAR2Aperture)) + { + return NV_OK; + } + + pKernelBus->bar2[gfid].bMigrating = NV_TRUE; + + // Grab a CPU pointer to the actual BAR2 page tables at the top of FB. + status = kbusInitVirtualBar2_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + walkFlags.bUseIterative = gpuIsIterativeMmuWalkerEnabled(pGpu); + + // + // Initialize/allocate walker staging buffer only if PTEs in FBMEM + // and we are currently bootstrapping BAR2. + // + if (pKernelBus->bar2[gfid].pWalkStagingBuffer == NULL && + pKernelBus->PTEBAR2Aperture == ADDR_FBMEM && + pKernelBus->bar2[gfid].bBootstrap) + { + pKernelBus->bar2[gfid].pWalkStagingBuffer = kbusCreateStagingMemdesc(pGpu); + } + + // Create a new MMU_WALKER state for the actual page tables. + status = mmuWalkCreate(pKernelBus->bar2[gfid].pFmt->pRoot, + NULL, + &g_bar2WalkCallbacks, + walkFlags, + &pWalk, + (struct MMU_WALK_MEMDESC *) pKernelBus->bar2[gfid].pWalkStagingBuffer); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + // We want to lock the small page table + pLevelFmt = mmuFmtFindLevelWithPageShift(pKernelBus->bar2[gfid].pFmt->pRoot, + RM_PAGE_SHIFT); + + // Setup walk user context. + userCtx.pGpu = pGpu; + // + // Pre-reserve and init 4K tables through mappings made using the + // temporary page tables that were bootstrapped at the bottom of FB. + // + NV_ASSERT_OK_OR_GOTO(status, mmuWalkSetUserCtx(pWalk, &userCtx), cleanup); + + if (pKernelBus->bar2[gfid].cpuVisibleLimit != 0) + { + status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuVisibleBase, + pKernelBus->bar2[gfid].cpuVisibleLimit, NV_FALSE); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + status = mmuWalkSparsify(pWalk, pKernelBus->bar2[gfid].cpuVisibleBase, pKernelBus->bar2[gfid].cpuVisibleLimit, NV_TRUE); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + } + + if (pKernelBus->bar2[gfid].cpuInvisibleLimit != 0) + { + status = mmuWalkReserveEntries(pWalk, pLevelFmt, pKernelBus->bar2[gfid].cpuInvisibleBase, + pKernelBus->bar2[gfid].cpuInvisibleLimit, NV_FALSE); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + status = mmuWalkSparsify(pWalk, pKernelBus->bar2[gfid].cpuInvisibleBase, pKernelBus->bar2[gfid].cpuInvisibleLimit, NV_TRUE); + NV_ASSERT_OR_GOTO(NV_OK == status, cleanup); + } + + NV_ASSERT_OK_OR_GOTO(status, mmuWalkSetUserCtx(pWalk, NULL), cleanup); + + NV_PRINTF(LEVEL_INFO, "(BAR2 0x%llx, PDB 0x%llx): vaLimit = 0x%llx\n", + pKernelBus->bar2[gfid].instBlockBase, pKernelBus->bar2[gfid].pdeBase, + pKernelBus->bar2[gfid].vaLimit); + + memdescSetPageSize(pKernelBus->bar2[gfid].pPDEMemDesc, AT_GPU, + FERMI_SMALL_PAGESIZE); + + // Free the CPU pointer to the temporary BAR2 page tables. + if (NULL != pKernelBus->virtualBar2[gfid].pPageLevelsForBootstrap) + { + kbusUnmapRmAperture_HAL(pGpu, + pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap, + &pKernelBus->virtualBar2[gfid].pPageLevelsForBootstrap, + NV_TRUE); + // Release the memdesc from cached mappings. + kbusReleaseRmAperture_HAL(pGpu, pKernelBus, + pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap); + pKernelBus->virtualBar2[gfid].pPageLevelsForBootstrap = NULL; + } + + // + // Save the MMU walker state that was setup at bootstrap and commit the + // new walker state. + // + pKernelBus->bar2[gfid].pWalkForBootstrap = pKernelBus->bar2[gfid].pWalk; + pKernelBus->bar2[gfid].pWalk = pWalk; + +cleanup: + pKernelBus->bar2[gfid].bMigrating = NV_FALSE; + + if (NV_OK != status) + { + mmuWalkLevelInstancesForceFree(pWalk); + mmuWalkSetUserCtx(pWalk, NULL); + mmuWalkDestroy(pWalk); + + // Free staging buffer + memdescFree(pKernelBus->bar2[gfid].pWalkStagingBuffer); + memdescDestroy(pKernelBus->bar2[gfid].pWalkStagingBuffer); + pKernelBus->bar2[gfid].pWalkStagingBuffer = NULL; + } + + return status; +} + +NV_STATUS +kbusCommitBar2PDEs_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NV_STATUS status = NV_OK; + const MMU_FMT_LEVEL *pLevelFmt = NULL; + const GMMU_FMT *pBar2GmmuFmt = kbusGetBar2GmmuFmt_HAL(pKernelBus); + MMU_WALK_USER_CTX userCtx = {0}; + MMU_WALK *pTempWalk = NULL; + NvU32 gfid; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + // Do nothing if page directories/tables in sysmem + if ((ADDR_FBMEM != pKernelBus->PDEBAR2Aperture) || + (ADDR_FBMEM != pKernelBus->PTEBAR2Aperture)) + { + return NV_OK; + } + + userCtx.pGpu = pGpu; + + // For bootstrapping, use pWalkForBootstrap as the active MMU_WALK state. + pTempWalk = pKernelBus->bar2[gfid].pWalk; + pKernelBus->bar2[gfid].pWalk = pKernelBus->bar2[gfid].pWalkForBootstrap; + + // We want to lock the small page table. + pLevelFmt = mmuFmtFindLevelWithPageShift(pBar2GmmuFmt->pRoot, RM_PAGE_SHIFT); + + // Start the bootstrap. + pKernelBus->bar2[gfid].bBootstrap = NV_TRUE; + + // Commit PDEs for page level instances at bottom of FB. + status = mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalkForBootstrap, &userCtx); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + status = mmuWalkCommitPDEs(pKernelBus->bar2[gfid].pWalkForBootstrap, pLevelFmt, 0, + kbusGetVaLimitForBar2_HAL(pGpu, pKernelBus)); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + status = mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalkForBootstrap, NULL); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + // Get a CPU pointer to the page tables at the bottom of FB. + if (NULL == pKernelBus->virtualBar2[gfid].pPageLevelsForBootstrap) + { + status = kbusPreInitVirtualBar2_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + } + + // Bind the temporary instance block at the bottom of FB. + status = kbusBindBar2_HAL(pGpu, pKernelBus, BAR2_MODE_VIRTUAL); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + // End of bootstrap. + pKernelBus->bar2[gfid].bBootstrap = NV_FALSE; + + // Start the migration. + pKernelBus->bar2[gfid].bMigrating = NV_TRUE; + + // + // Get a CPU pointer to the page tables at the top of the FB. + // The PTEs for this mapping will be written in the page tables + // at the bottom of FB for this operation. We"ll later mirror + // these PTEs in the new page tables so that this mapping does + // not become invalid once we have migrated to the new page + // tables. See @ref busRewritePTEsForExistingMapping_VBAR2. + // + if (NULL == pKernelBus->virtualBar2[gfid].pPageLevels) + { + status = kbusInitVirtualBar2_HAL(pGpu, pKernelBus); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + } + + // Commit PDEs for page level instances at the top of FB. + status = mmuWalkSetUserCtx(pTempWalk, &userCtx); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + status = mmuWalkCommitPDEs(pTempWalk, pLevelFmt, 0, + kbusGetVaLimitForBar2_HAL(pGpu, pKernelBus)); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + status = mmuWalkSparsify(pTempWalk, 0, kbusGetVaLimitForBar2_HAL(pGpu, pKernelBus), NV_TRUE); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + status = mmuWalkSetUserCtx(pTempWalk, NULL); + NV_ASSERT_OR_RETURN(NV_OK == status, status); + + // Free the CPU pointer to the temporary BAR2 page tables. + if (NULL != pKernelBus->virtualBar2[gfid].pPageLevelsForBootstrap) + { + kbusUnmapRmAperture_HAL(pGpu, + pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap, + &pKernelBus->virtualBar2[gfid].pPageLevelsForBootstrap, + NV_TRUE); + // + // Release the memdesc from cached mappings as we"ll be discarding the old + // page tables after migration. + // + kbusReleaseRmAperture_HAL(pGpu, pKernelBus, + pKernelBus->virtualBar2[gfid].pPageLevelsMemDescForBootstrap); + pKernelBus->virtualBar2[gfid].pPageLevelsForBootstrap = NULL; + } + + // End of migration. + pKernelBus->bar2[gfid].bMigrating = NV_FALSE; + + // Restore the actual walker. + pKernelBus->bar2[gfid].pWalk = pTempWalk; + + return status; +} + +/*! + * @brief Commit BAR2 + * + * 1. Commit BAR2 inst blk in HW. + * 2. Acquire BAR2 aperture. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * @param[in] flags GPU state flag + * + * @returns NV_OK on success. + */ +NV_STATUS +kbusCommitBar2_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 flags +) +{ + NvU32 gfid; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + if (!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)) + { + + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && + pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc != NULL) + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + // + // Write the PTEs for the self mapping CPU pointer and the pointer + // to the page used for bus flushes in the new page tables for the + // pointers to remain valid after we switch to the new page tables. + // + NV_ASSERT_OK_OR_RETURN(kbusRewritePTEsForExistingMapping_HAL(pGpu, + pKernelBus, pKernelBus->virtualBar2[gfid].pPageLevelsMemDesc)); + + if (pKernelBus->pFlushMemDesc != NULL) + { + NV_ASSERT_OK_OR_RETURN(kbusRewritePTEsForExistingMapping_HAL(pGpu, + pKernelBus, pKernelBus->pFlushMemDesc)); + } + + // Kick out any entries associated w/ old PDB. + osFlushCpuWriteCombineBuffer(); + kbusFlush_HAL(pGpu, pKernelBus, BUS_FLUSH_VIDEO_MEMORY); + kgmmuInvalidateTlb_HAL(pGpu, pKernelGmmu, + pKernelBus->virtualBar2[gfid].pPDB, + pKernelBus->virtualBar2[gfid].flags, + PTE_DOWNGRADE, 0, NV_GMMU_INVAL_SCOPE_NON_LINK_TLBS); + // Update the PDB pointer just before binding w/ the new page tables. + pKernelBus->virtualBar2[gfid].pPDB = pKernelBus->bar2[gfid].pPDEMemDesc; + } + } + + NV_ASSERT_OK_OR_RETURN(kbusBindBar2_HAL(pGpu, pKernelBus, BAR2_MODE_VIRTUAL)); + + if (!(flags & GPU_STATE_FLAGS_GC6_TRANSITION) && + !kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) && + !KBUS_BAR0_PRAMIN_DISABLED(pGpu) && + !IS_GFID_VF(gfid)) + { + // we will initialize bar2 to the default big page size of the system + NV_ASSERT_OK_OR_RETURN(kbusInitVirtualBar2_HAL(pGpu, pKernelBus)); + NV_ASSERT_OK_OR_RETURN(kbusSetupCpuPointerForBusFlush_HAL(pGpu, pKernelBus)); + } + + return NV_OK; +} + +/*! + * Previous bind sequence would just do a sysmembar after a flush. + * Now the flushes don't guarantee anything for the BIND itself. + * Just that previous reads/writes are complete. + * We need to use the BIND_STATUS register now. + * New procedure: + * - Write NV_PBUS_BLOCK_(BAR1|BAR2|IFB) + * - Poll NV_PBUS_BIND_STATUS to make sure the BIND completed. + */ +NV_STATUS +kbusBar1InstBlkBind_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 target; + NvU32 temp; + NvU32 ptr; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + + // Nothing to be done in guest in the paravirtualization case. + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) + { + return NV_OK; + } + + switch (kgmmuGetMemAperture(pKernelGmmu, pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc)) + { + case GMMU_APERTURE_VIDEO: + target = NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM; + break; + case GMMU_APERTURE_SYS_COH: + target = NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT; + break; + case GMMU_APERTURE_SYS_NONCOH: + target = NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT; + break; + default: + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + ptr = NvU64_LO32(pKernelBus->bar1[GPU_GFID_PF].instBlockBase >> GF100_BUS_INSTANCEBLOCK_SHIFT); + + GPU_REG_WR32(pGpu, NV_PBUS_BAR1_BLOCK, + DRF_NUM(_PBUS, _BAR1_BLOCK, _TARGET, target) | + DRF_DEF(_PBUS, _BAR1_BLOCK, _MODE, _VIRTUAL) | + DRF_NUM(_PBUS, _BAR1_BLOCK, _PTR, ptr)); + + osFlushCpuWriteCombineBuffer(); + + // Skip the wait if we are in the reset path (GPU most likely in a bad state) + if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + return status; + } + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + do + { + // + // To avoid deadlocks and non-deterministic virtual address + // translation behavior, after writing BAR1_BLOCK to bind BAR1 to a + // virtual address space, SW must ensure that the bind has completed + // prior to issuing any further BAR1 requests by polling for both + // NV_PBUS_BIND_STATUS_BAR1_PENDING to return to EMPTY and + // NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING to return to FALSE. + // + // BAR1_PENDING indicates a Bar1 bind is waiting to be sent. + // BAR1_OUTSTANDING indicates a Bar1 bind is outstanding to FB. + // + temp = GPU_REG_RD32(pGpu, NV_PBUS_BIND_STATUS); + if (FLD_TEST_DRF(_PBUS, _BIND_STATUS, _BAR1_PENDING, _EMPTY, temp) && + FLD_TEST_DRF(_PBUS, _BIND_STATUS, _BAR1_OUTSTANDING, _FALSE, temp)) + { + status = NV_OK; + break; + } + + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "timed out waiting for bar1 binding to complete\n"); + DBG_BREAKPOINT(); + break; + } + status = gpuCheckTimeout(pGpu, &timeout); + osSpinLoop(); + } while (1); + + return status; +} + +/*! + * @brief Returns BAR1 VA Size that needs to be reserved for BSOD Surface + * + * + * @returns BAR1 VA Size that needs to be reserved + */ +NvU64 +kbusGetBar1ResvdVA_GM107 +( + KernelBus *pKernelBus +) +{ + // Using the old BAR1 reserved VA Size 0f 64MB + return NVBIT64(26); //64MB +} + +/*! + * Performs a physically addressed memory copy between system memory and video + * memory via BAR0 window + * + * Regions must be contiguous chunks. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * @param[in] pDstMemDesc Destination memory descriptor + * @param[in] dstOffset Offset into destination + * @param[in] pSrcMemDesc Source memory descriptor + * @param[in] srcOffset Offset into source + * @param[in] size Number of bytes to copy + * + * @returns None + */ +NV_STATUS +kbusMemoryCopy_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + MEMORY_DESCRIPTOR *pDstMemDesc, + NvU64 dstOffset, + MEMORY_DESCRIPTOR *pSrcMemDesc, + NvU64 srcOffset, + NvU64 size +) +{ + NV_STATUS status = NV_OK; + NvU8 *pSrcMem = NULL; + NvU8 *pDstMem = NULL; + void *pSrcPriv = NULL; + void *pDstPriv = NULL; + NvU64 bytes; + NvU64 offset = 0; + NvU64 bar0Window; + NvU64 bar0Offset = 0; + NvU32 data; + NvU32 i; + NvU64 source; + NvU64 dest; + + source = memdescGetPhysAddr(pSrcMemDesc, FORCE_VMMU_TRANSLATION(pSrcMemDesc, AT_GPU), srcOffset); + dest = memdescGetPhysAddr(pDstMemDesc, FORCE_VMMU_TRANSLATION(pDstMemDesc, AT_GPU), dstOffset); + + if (memdescGetAddressSpace(pSrcMemDesc) == ADDR_SYSMEM) + { + status = memdescMapOld(pSrcMemDesc, srcOffset, size, NV_TRUE /* kernel */, + NV_PROTECT_READ_WRITE, + (void **)&pSrcMem, &pSrcPriv); + if (status != NV_OK) + { + DBG_BREAKPOINT(); + return status; + } + } + + if (memdescGetAddressSpace(pDstMemDesc) == ADDR_SYSMEM) + { + status = memdescMapOld(pDstMemDesc, dstOffset, size, NV_TRUE /* kernel */, + NV_PROTECT_READ_WRITE, + (void **)&pDstMem, &pDstPriv); + if (status != NV_OK) + { + if (pSrcMem != NULL) + memdescUnmapOld(pSrcMemDesc, 1 /* kernel */, 0, pSrcMem, pSrcPriv); + DBG_BREAKPOINT(); + return status; + } + } + + if ((memdescGetAddressSpace(pSrcMemDesc) == ADDR_FBMEM) && + (memdescGetAddressSpace(pDstMemDesc) == ADDR_FBMEM)) + { + bar0Window = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); + + for (i = 0; i < size; i += 4) + { + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, + ((source + i) & ~0xffff)); + bar0Offset = ((source + i) & 0xffff); + + data = GPU_REG_RD32(pGpu, + (DRF_BASE(NV_PRAMIN) + (NvU32)bar0Offset)); + + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, + ((dest + i) & ~0xffff)); + bar0Offset = ((dest + i) & 0xffff); + + GPU_REG_WR32(pGpu, + (DRF_BASE(NV_PRAMIN) + (NvU32)bar0Offset), data); + } + + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, bar0Window); + kbusFlush_HAL(pGpu, pKernelBus, 0); + } + else if ((memdescGetAddressSpace(pSrcMemDesc) == ADDR_SYSMEM) && + (memdescGetAddressSpace(pDstMemDesc) == ADDR_SYSMEM)) + { + portMemCopy(pDstMem, (NvU32)size, pSrcMem, (NvU32)size); + } + else + { + bar0Window = kbusGetBAR0WindowVidOffset_HAL(pGpu, pKernelBus); + + while (size != 0) + { + if (memdescGetAddressSpace(pSrcMemDesc) == ADDR_FBMEM) + { + source += offset; + bar0Offset = (source & 0xffff); + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, + (source & ~0xffff)); + } + + if (memdescGetAddressSpace(pDstMemDesc) == ADDR_FBMEM) + { + dest += offset; + bar0Offset = (dest & 0xffff); + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, + (dest & ~0xffff)); + } + + bytes = NV_MIN(size, (0x10000 - bar0Offset)); + + for (i = 0; i < bytes; i += 4) + { + if (memdescGetAddressSpace(pSrcMemDesc) == ADDR_SYSMEM) + { + data = MEM_RD32(pSrcMem + offset + i); + } + else + { + data = GPU_REG_RD32(pGpu, + (DRF_BASE(NV_PRAMIN) + (NvU32)bar0Offset + i)); + } + + if (memdescGetAddressSpace(pDstMemDesc) == ADDR_SYSMEM) + { + MEM_WR32((pDstMem + offset + i), data); + } + else + { + GPU_REG_WR32(pGpu, + (DRF_BASE(NV_PRAMIN) + (NvU32)bar0Offset + i), + data); + } + } + + offset += bytes; + size -= bytes; + } + + kbusSetBAR0WindowVidOffset_HAL(pGpu, pKernelBus, bar0Window); + kbusFlush_HAL(pGpu, pKernelBus, 0); + } + + if (pSrcMem != NULL) + memdescUnmapOld(pSrcMemDesc, 1 /* kernel */, 0, pSrcMem, pSrcPriv); + if (pDstMem != NULL) + memdescUnmapOld(pDstMemDesc, 1 /* kernel */, 0, pDstMem, pDstPriv); + + return NV_OK; +} + +/*! + * @brief Disable P2P operations to get ready for a XVE sw reset. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBus KernelBus object pointer + * + * @return NV_OK + */ +NV_STATUS +kbusPrepareForXVEReset_GM107 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NV_STATUS status = NV_OK; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + + if ((!pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_READS_DISABLED) || + !pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED)) + && + !kbusIsP2pMailboxClientAllocated(pKernelBus)) + { + kbusUnlinkP2P_HAL(pGpu, pKernelBus); + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c index 260707d99e..1d56500465 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm200.c @@ -24,6 +24,7 @@ #include "core/core.h" #include "platform/chipset/chipset.h" #include "mem_mgr/vaspace.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" diff --git a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c index dd4755de40..d9a0406857 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c @@ -27,7 +27,12 @@ #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/fermi_dma.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "vgpu/vgpu_events.h" +#include "platform/sli/sli.h" + +#include "published/pascal/gp100/dev_ram.h" /*! * @brief Create a P2P mapping to a given peer GPU @@ -937,3 +942,248 @@ kbusGetNvlinkPeerNumberMask_GP100 return (pKernelBus->p2p.busNvlinkPeerNumberMask[peerId]); } + +/*! + * @brief Initialize NV_RAMIN_ADR_LIMIT at the given location + * + * @param[in] pGpu OBJGPU + * @param[in] pKernelBus KernelBus + * @param[in] pBar0Wr Controls whether to MEM_WR using pMap or GPU_REG_WR at addr + * @param[in] instBlockAddr physical address of the instance block to be written + * @param[in] pMap CPU mapped address to start from + * @param[in] vaLimit Virtual address limit to program + */ +void +kbusInstBlkWriteAddrLimit_GP100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvBool bBar0Wr, + NvU64 instBlockAddr, + NvU8 *pMap, + NvU64 vaLimit +) +{ + NV_STATUS status = NV_OK; + NvU32 adrLimitLo = (NvU64_LO32(vaLimit) | 0xfff); + NvU32 adrLimitHi = SF_NUM(_RAMIN_ADR_LIMIT, _HI, NvU64_HI32(vaLimit)); + + if (bBar0Wr) + { + status = kbusMemAccessBar0Window_HAL(pGpu, pKernelBus, + (instBlockAddr + SF_OFFSET(NV_RAMIN_ADR_LIMIT_LO)), + &adrLimitLo, + sizeof(NvU32), + NV_FALSE, + pKernelBus->InstBlkAperture); + NV_ASSERT_OR_RETURN_VOID(NV_OK == status); + + status = kbusMemAccessBar0Window_HAL(pGpu, pKernelBus, + (instBlockAddr + SF_OFFSET(NV_RAMIN_ADR_LIMIT_HI)), + &adrLimitHi, + sizeof(NvU32), + NV_FALSE, + pKernelBus->InstBlkAperture); + NV_ASSERT_OR_RETURN_VOID(NV_OK == status); + } + else + { + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_ADR_LIMIT_LO), adrLimitLo); + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_ADR_LIMIT_HI), adrLimitHi); + } +} + +NV_STATUS +kbusInitInstBlk_GP100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + PMEMORY_DESCRIPTOR pInstBlkMemDesc, // NULL if BAR2 aperture not set up yet: BAR2 instance block using BAR0 window + PMEMORY_DESCRIPTOR pPDB, + NvU64 vaLimit, + NvU64 bigPageSize, + OBJVASPACE *pVAS +) +{ + NvU8 *pMap; + NvBool newPteFormat = NV_FALSE; + NvU32 pageDirBaseHi = 0; + NvU32 pageDirBaseTarget = 0; + NvU32 gfid; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + NV_ASSERT_OR_RETURN(pKernelBus->bar2[gfid].pFmt != NULL, NV_ERR_INVALID_STATE); + newPteFormat = (GMMU_FMT_VERSION_2 == pKernelBus->bar2[gfid].pFmt->version); + + if (pInstBlkMemDesc == NULL) + { + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + return kbusSetupBar2InstBlkAtBottomOfFb_HAL(pGpu, pKernelBus, pPDB, vaLimit, bigPageSize, gfid); + } + + // Initialize NV_RAMIN_ADR_LIMIT at the given offset + kbusInstBlkWriteAddrLimit_HAL(pGpu, pKernelBus, NV_TRUE, + pKernelBus->bar2[gfid].instBlockBase, + NULL, + vaLimit); + + pageDirBaseHi = SF_NUM(_RAMIN_PAGE_DIR_BASE, _HI, NvU64_HI32(memdescGetPhysAddr(pPDB, AT_GPU, 0))); + NV_ASSERT_OK_OR_RETURN(kbusMemAccessBar0Window_HAL(pGpu, pKernelBus, + (pKernelBus->bar2[gfid].instBlockBase + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_HI)), + &pageDirBaseHi, + sizeof(NvU32), + NV_FALSE, + pKernelBus->InstBlkAperture)); + + // + // Set up the big page size in the memdesc for this address space + // + if (bigPageSize == FERMI_BIG_PAGESIZE_128K) + { + pageDirBaseTarget = SF_NUM(_RAMIN_PAGE_DIR_BASE, _TARGET, kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pPDB)) | + (newPteFormat ? + SF_DEF(_RAMIN, _USE_NEW_PT_FORMAT, _TRUE) : + SF_DEF(_RAMIN, _USE_NEW_PT_FORMAT, _FALSE)) | + SF_DEF(_RAMIN, _BIG_PAGE_SIZE, _128KB) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _VOL, memdescGetVolatility(pPDB)) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _LO, NvU64_LO32(memdescGetPhysAddr(pPDB, AT_GPU, 0) >> PDB_SHIFT_FERMI)); + } + else if (bigPageSize == FERMI_BIG_PAGESIZE_64K) + { + pageDirBaseTarget = SF_NUM(_RAMIN_PAGE_DIR_BASE, _TARGET, kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pPDB)) | + (newPteFormat ? + SF_DEF(_RAMIN, _USE_NEW_PT_FORMAT, _TRUE) : + SF_DEF(_RAMIN, _USE_NEW_PT_FORMAT, _FALSE)) | + SF_DEF(_RAMIN, _BIG_PAGE_SIZE, _64KB) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _VOL, memdescGetVolatility(pPDB)) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _LO, NvU64_LO32(memdescGetPhysAddr(pPDB, AT_GPU, 0) >> PDB_SHIFT_FERMI)); + } + NV_ASSERT_OK_OR_RETURN(kbusMemAccessBar0Window_HAL(pGpu, pKernelBus, + (pKernelBus->bar2[gfid].instBlockBase + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_TARGET)), + &pageDirBaseTarget, + sizeof(NvU32), + NV_FALSE, + pKernelBus->InstBlkAperture)); + } + else + { + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + pMap = kbusMapRmAperture_HAL(pGpu, pInstBlkMemDesc); + if (pMap == NULL) + { + SLI_LOOP_RETURN(NV_ERR_INSUFFICIENT_RESOURCES); + } + kbusBar2InstBlkWrite_HAL(pGpu, pKernelBus, pMap, pPDB, vaLimit, bigPageSize); + kbusUnmapRmAperture_HAL(pGpu, pInstBlkMemDesc, &pMap, NV_TRUE); + if (pKernelBus->bar2[gfid].bMigrating) + { + // + // Remove memdesc from cached mappings as the page tables backing + // this mapping will be discarded and the old VA to PA translation + // won't be valid. + // + kbusReleaseRmAperture_HAL(pGpu, pKernelBus, pInstBlkMemDesc); + } + SLI_LOOP_END + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + } + return NV_OK; +} + +void +kbusBar2InstBlkWrite_GP100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU8 *pMap, + PMEMORY_DESCRIPTOR pPDB, + NvU64 vaLimit, + NvU64 bigPageSize +) +{ + NvBool newPteFormat = NV_FALSE; + + NV_ASSERT_OR_RETURN_VOID(NULL != pMap); + NV_ASSERT_OR_RETURN_VOID(NULL != pKernelBus->bar2[GPU_GFID_PF].pFmt); + + newPteFormat = (GMMU_FMT_VERSION_2 == pKernelBus->bar2[GPU_GFID_PF].pFmt->version); + + // Initialize NV_RAMIN_ADR_LIMIT in the mapped instblk + kbusInstBlkWriteAddrLimit_HAL(pGpu, pKernelBus, NV_FALSE, 0x0, pMap, vaLimit); + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_HI), + SF_NUM(_RAMIN_PAGE_DIR_BASE, _HI, + NvU64_HI32(memdescGetPhysAddr(pPDB, AT_GPU, 0)))); + + if (bigPageSize == FERMI_BIG_PAGESIZE_128K) + { + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_TARGET), + SF_NUM(_RAMIN_PAGE_DIR_BASE, _TARGET, kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pPDB)) | + (newPteFormat ? + SF_DEF(_RAMIN, _USE_NEW_PT_FORMAT, _TRUE) : + SF_DEF(_RAMIN, _USE_NEW_PT_FORMAT, _FALSE)) | + SF_DEF(_RAMIN, _BIG_PAGE_SIZE, _128KB) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _VOL, memdescGetVolatility(pPDB)) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _LO, + NvU64_LO32(memdescGetPhysAddr(pPDB, AT_GPU, 0) >> PDB_SHIFT_FERMI))); + } + else if (bigPageSize == FERMI_BIG_PAGESIZE_64K) + { + MEM_WR32(pMap + SF_OFFSET(NV_RAMIN_PAGE_DIR_BASE_TARGET), + SF_NUM(_RAMIN_PAGE_DIR_BASE, _TARGET, kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pPDB)) | + (newPteFormat ? + SF_DEF(_RAMIN, _USE_NEW_PT_FORMAT, _TRUE) : + SF_DEF(_RAMIN, _USE_NEW_PT_FORMAT, _FALSE)) | + SF_DEF(_RAMIN, _BIG_PAGE_SIZE, _64KB) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _VOL, memdescGetVolatility(pPDB)) | + SF_NUM(_RAMIN_PAGE_DIR_BASE, _LO, + NvU64_LO32(memdescGetPhysAddr(pPDB, AT_GPU, 0) >> PDB_SHIFT_FERMI))); + } +} + +/*! + * @brief Calculate the base and limit of BAR2 cpu-invisible range + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + */ +void +kbusCalcCpuInvisibleBar2Range_GP100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + NvU32 gfid +) +{ + NvU32 cpuInvisibleSize = 0; + + if (pKernelBus->bar2[gfid].cpuInvisibleLimit == 0) + { + cpuInvisibleSize = kbusCalcCpuInvisibleBar2ApertureSize_HAL(pGpu, pKernelBus); + if (cpuInvisibleSize != 0) + { + cpuInvisibleSize--; + + if (pKernelBus->bar2[gfid].cpuInvisibleBase == 0) + { + if (!RMCFG_FEATURE_PLATFORM_GSP) + { + if (pKernelBus->bar2[gfid].cpuVisibleLimit != 0) + { + pKernelBus->bar2[gfid].cpuInvisibleBase = pKernelBus->bar2[gfid].cpuVisibleLimit + 1; + } + } + else + { + pKernelBus->bar2[gfid].cpuInvisibleBase = + kbusGetCpuInvisibleBar2BaseAdjust_HAL(pGpu, pKernelBus); + } + } + NV_PRINTF(LEVEL_INFO, "base: 0x%llx size: 0x%x\n", + pKernelBus->bar2[gfid].cpuInvisibleBase, cpuInvisibleSize + 1); + pKernelBus->bar2[gfid].cpuInvisibleLimit = pKernelBus->bar2[gfid].cpuInvisibleBase + cpuInvisibleSize; + } + } +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c b/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c index 4203346082..7468848915 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/turing/kern_bus_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,6 +25,10 @@ #include "gpu/gpu.h" #include "gpu/bus/kern_bus.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" +#include "vgpu/vgpu_events.h" + +#include "published/turing/tu102/dev_bus.h" +#include "published/turing/tu102/dev_vm.h" /*! * @brief Returns the first available peer Id excluding the nvlink peerIds @@ -71,3 +75,270 @@ kbusGetUnusedPciePeerId_TU102 } return BUS_INVALID_PEER; } + +/*! + * Previous bind sequence would just do a sysmembar after a flush. + * Now the flushes don't guarantee anything for the BIND itself. + * Just that previous reads/writes are complete. + * We need to use the BIND_STATUS register now. + * New procedure: + * - Write NV_PBUS_BLOCK_(BAR1|BAR2|IFB) + * - Poll NV_PBUS_BIND_STATUS to make sure the BIND completed. + */ +NV_STATUS +kbusBindBar2_TU102 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + BAR2_MODE bar2Mode +) +{ + NvU32 gfid; + RMTIMEOUT timeout; + NvU32 temp; + NvU32 value; + NvU32 instBlkAperture = 0; + NvU64 instBlkAddr = 0; + NV_STATUS status = NV_OK; + NvBool bIsModePhysical; + MEMORY_DESCRIPTOR *pMemDesc; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + if (pKernelBus->bar2[gfid].bBootstrap && + (NULL != pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap) && + kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + pMemDesc = pKernelBus->bar2[gfid].pInstBlkMemDescForBootstrap; + } + else + { + pMemDesc = pKernelBus->bar2[gfid].pInstBlkMemDesc; + } + + // + // Bind BAR2 to virtual. Carefully. We have not initialized PTEs yet. We will first + // map the BAR2 PTEs into BAR2. This allows us to use the BAR2 interface to invalidate + // the rest of the BAR2 PTEs. WC memory writes are faster than single BAR0 writes + // and this matters for RTL sim and emulation. DEBUG_CYA = OFF keeps the VBIOS + // aperture in physical addressing. + // + bIsModePhysical = (BAR2_MODE_PHYSICAL == bar2Mode); + + if (!bIsModePhysical) + { + instBlkAperture = kgmmuGetHwPteApertureFromMemdesc(GPU_GET_KERNEL_GMMU(pGpu), pMemDesc); + instBlkAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); + } + + value = ((bIsModePhysical ? DRF_DEF(_PBUS, _BAR2_BLOCK, _TARGET, _VID_MEM) : + DRF_NUM(_PBUS, _BAR2_BLOCK, _TARGET, instBlkAperture)) | + (bIsModePhysical ? DRF_DEF(_PBUS, _BAR2_BLOCK, _MODE, _PHYSICAL) : + DRF_DEF(_PBUS, _BAR2_BLOCK, _MODE, _VIRTUAL)) | + (bIsModePhysical ? DRF_NUM(_PBUS, _BAR2_BLOCK, _PTR, 0x0) : + DRF_NUM(_PBUS, _BAR2_BLOCK, _PTR, + NvU64_LO32(instBlkAddr >> GF100_BUS_INSTANCEBLOCK_SHIFT))) | + DRF_DEF(_PBUS, _BAR2_BLOCK, _DEBUG_CYA, _OFF)); + + { + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_BAR2_BLOCK, value); + } + + + osFlushCpuWriteCombineBuffer(); + + // Skip the wait if we are in the reset path (GPU most likely in a bad state) + if (!IS_VIRTUAL(pGpu) && API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + return status; + } + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + do + { + // + // To avoid deadlocks and non-deterministic virtual address + // translation behavior, after writing BAR2_BLOCK to bind BAR2 to a + // virtual address space, SW must ensure that the bind has completed + // prior to issuing any further BAR2 requests by polling for both + // NV_PBUS_BIND_STATUS_BAR2_PENDING to return to EMPTY and + // NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING to return to FALSE. + // + // BAR2_PENDING indicates a Bar2 bind is waiting to be sent. + // BAR2_OUTSTANDING indicates a Bar2 bind is outstanding to FB. + // + { + temp = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS); + } + if (FLD_TEST_DRF(_PBUS, _BIND_STATUS, _BAR2_PENDING, _EMPTY, temp) && + FLD_TEST_DRF(_PBUS, _BIND_STATUS, _BAR2_OUTSTANDING, _FALSE, temp)) + { + status = NV_OK; + break; + } + + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "timed out waiting for bar2 binding to complete\n"); + DBG_BREAKPOINT(); + break; + } + + status = gpuCheckTimeout(pGpu, &timeout); + osSpinLoop(); + } while (1); + + return status; +} + +NvU64 kbusGetCpuInvisibleBar2BaseAdjust_TU102 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + const GMMU_FMT* pFmt = NULL; + + NV_ASSERT_OR_RETURN(pKernelGmmu != NULL, 0); + pFmt = kgmmuFmtGetLatestSupportedFormat(pGpu, pKernelGmmu); + NV_ASSERT_OR_RETURN(pFmt != NULL, 0); + + // + // In RM-offload scenario, Kernel RM and Physical RM use their own GPU VA space respectively. + // + // The expectation is that the Physical RM base starts from the second PD entry of the topmost PD. + // + return mmuFmtEntryIndexVirtAddrLo(pFmt->pRoot, 0, 1 /* PD0[1] */); +} + +/*! + * Previous bind sequence would just do a sysmembar after a flush. + * Now the flushes don't guarantee anything for the BIND itself. + * Just that previous reads/writes are complete. + * We need to use the BIND_STATUS register now. + * New procedure: + * - Write NV_PBUS_BLOCK_(BAR1|BAR2|IFB) + * - Poll NV_PBUS_BIND_STATUS to make sure the BIND completed. + */ +NV_STATUS +kbusBar1InstBlkBind_TU102 +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 gfid; + NvU32 target; + NvU32 temp; + NvU32 ptr; + RMTIMEOUT timeout; + NV_STATUS status = NV_OK; + NvBool bIsModePhysical = NV_FALSE; + NvBool bBrokenFb = NV_FALSE; + + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + + // Nothing to be done in guest in the paravirtualization case. + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + return NV_OK; + } + + switch (kgmmuGetMemAperture(pKernelGmmu, pKernelBus->bar1[gfid].pInstBlkMemDesc)) + { + case GMMU_APERTURE_VIDEO: + target = NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM; + break; + case GMMU_APERTURE_SYS_COH: + target = NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT; + break; + case GMMU_APERTURE_SYS_NONCOH: + target = NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT; + break; + default: + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + ptr = NvU64_LO32(pKernelBus->bar1[gfid].instBlockBase >> GF100_BUS_INSTANCEBLOCK_SHIFT); + + bIsModePhysical = kbusIsBar1PhysicalModeEnabled(pKernelBus); + bBrokenFb = pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB); + + { + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_BAR1_BLOCK, + (((bIsModePhysical && !bBrokenFb) ? + DRF_DEF(_PBUS, _BAR1_BLOCK, _TARGET, _VID_MEM) : + DRF_NUM(_PBUS, _BAR1_BLOCK, _TARGET, target)) | + (bIsModePhysical ? DRF_DEF(_PBUS, _BAR1_BLOCK, _MODE, _PHYSICAL) : + DRF_DEF(_PBUS, _BAR1_BLOCK, _MODE, _VIRTUAL)) | + (bIsModePhysical ? DRF_NUM(_PBUS, _BAR1_BLOCK, _PTR, 0x0) : + DRF_NUM(_PBUS, _BAR1_BLOCK, _PTR, ptr)))); + } + + osFlushCpuWriteCombineBuffer(); + + // Skip the wait if we are in the reset path (GPU most likely in a bad state) + if (!IS_VIRTUAL(pGpu) && API_GPU_IN_RESET_SANITY_CHECK(pGpu)) + { + return status; + } + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + do + { + // + // To avoid deadlocks and non-deterministic virtual address + // translation behavior, after writing BAR1_BLOCK to bind BAR1 to a + // virtual address space, SW must ensure that the bind has completed + // prior to issuing any further BAR1 requests by polling for both + // NV_PBUS_BIND_STATUS_BAR1_PENDING to return to EMPTY and + // NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING to return to FALSE. + // + // BAR1_PENDING indicates a Bar1 bind is waiting to be sent. + // BAR1_OUTSTANDING indicates a Bar1 bind is outstanding to FB. + // + { + temp = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_BIND_STATUS); + } + if (FLD_TEST_DRF(_PBUS, _BIND_STATUS, _BAR1_PENDING, _EMPTY, temp) && + FLD_TEST_DRF(_PBUS, _BIND_STATUS, _BAR1_OUTSTANDING, _FALSE, temp)) + { + status = NV_OK; + break; + } + + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "timed out waiting for bar1 binding to complete\n"); + DBG_BREAKPOINT(); + break; + } + status = gpuCheckTimeout(pGpu, &timeout); + osSpinLoop(); + } while (1); + + return status; +} + +/*! + * @brief Returns BAR1 VA Size that needs to be reserved for BSOD Surface + * + * + * @returns BAR1 VA Size that needs to be reserved + */ +NvU64 +kbusGetBar1ResvdVA_TU102 +( + KernelBus *pKernelBus +) +{ + // + // Turing+ supports 8K displays which needs at least 127MB of BAR1 VA with + // 64KB/Big page size (used by KMD). Hence, doubling the prev size of 64MB + // + return NVBIT64(27); //128MB +} diff --git a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c index 2c38bdae87..682ccc0a78 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c @@ -26,6 +26,9 @@ #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/fifo/kernel_fifo.h" +#include "gpu/mmu/kern_gmmu.h" +#include "gpu/uvm/uvm.h" #include "os/os.h" // @ref busMigrateBarMapping_GV100 to see how FB region is organized @@ -386,3 +389,39 @@ kbusFlushSingle_GV100 return NV_OK; } + +NvU32 +kbusCalcCpuInvisibleBar2ApertureSize_GV100 +( + OBJGPU *pGpu, + KernelBus *pKernelBus) +{ + NvU32 i; + NvU32 apertureSize = 0; + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + + // Return 0 from the guest in the paravirtualization case. + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) || + pKernelGmmu == NULL) + { + return 0; + } + + // Add size required for replayable and non-replayable MMU fault buffers. + for (i = 0; i < NUM_FAULT_BUFFERS; i++) + { + NvU32 faultBufferSize; + + faultBufferSize = kgmmuSetAndGetDefaultFaultBufferSize_HAL(pGpu, pKernelGmmu, i, GPU_GFID_PF); + faultBufferSize = RM_ALIGN_UP(faultBufferSize, RM_PAGE_SIZE); + apertureSize += faultBufferSize; + } + + // Add size required for fault method buffers. Each run queue has its own method buffer. + apertureSize += (kfifoCalcTotalSizeOfFaultMethodBuffers_HAL(pGpu, pKernelFifo, NV_FALSE)); + apertureSize = RM_ALIGN_UP(apertureSize, RM_PAGE_SIZE); + + return apertureSize; +} diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus.c b/src/nvidia/src/kernel/gpu/bus/kern_bus.c index 738f410415..a99f08e0be 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus.c @@ -23,6 +23,7 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "gpu/device/device.h" #include "mem_mgr/vaspace.h" #include "mem_mgr/io_vaspace.h" #include "mem_mgr/gpu_vaspace.h" @@ -33,9 +34,9 @@ #include "kernel/gpu/nvbitmask.h" #include "platform/chipset/chipset.h" #include "rmapi/client.h" +#include "platform/sli/sli.h" #include "nvdevid.h" -#include "gpu/subdevice/subdevice.h" #include "gpu/gsp/gsp_static_config.h" #include "vgpu/rpc.h" @@ -181,7 +182,7 @@ kbusInitRegistryOverrides(OBJGPU *pGpu, KernelBus *pKernelBus) break; } - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) + if (RMCFG_FEATURE_PLATFORM_WINDOWS && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) { // // Aligns to unlinked SLI: Volta and up @@ -201,6 +202,12 @@ kbusInitRegistryOverrides(OBJGPU *pGpu, KernelBus *pKernelBus) pKernelBus->setProperty(pKernelBus, PDB_PROP_KBUS_RESTORE_BAR1_SIZE_BUG_3249028_WAR, !!data32); } + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC, &data32) == NV_OK && + data32 == NV_REG_STR_RM_FORCE_BAR_ACCESS_ON_HCC_YES && gpuIsCCDevToolsModeEnabled(pGpu)) + { + pKernelBus->bForceBarAccessOnHcc = NV_TRUE; + } + return NV_OK; } @@ -312,12 +319,31 @@ kbusDestruct_IMPL(KernelBus *pKernelBus) { OBJGPU *pGpu = ENG_GET_GPU(pKernelBus); + memdescFree(pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc); + memdescDestroy(pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc); + pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc = NULL; + memdescFree(pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc); + memdescDestroy(pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc); + pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc = NULL; + // // We need to clean-up the memory resources for BAR2 as late as possible, // and after all memory descriptors have been reclaimed. // kbusDestructVirtualBar2_HAL(pGpu, pKernelBus, NV_TRUE, GPU_GFID_PF); + // Unmap BAR2 mapping that was retained for RPC + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && + IS_VIRTUAL_WITH_SRIOV(pGpu) && + pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping != NULL) + { + // vgpuDestructObject should have been run + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + NV_ASSERT(pVGpu == NULL); + + osUnmapPciMemoryKernelOld(pGpu, pKernelBus->virtualBar2[GPU_GFID_PF].pCpuMapping); + } + return; } @@ -613,7 +639,7 @@ kbusCpuOffsetInBar2WindowGet_IMPL * @return VA limit of BAR2 */ NvU64 -kbusGetVaLimitForBar2_KERNEL +kbusGetVaLimitForBar2_FWCLIENT ( OBJGPU *pGpu, KernelBus *pKernelBus @@ -632,6 +658,56 @@ kbusGetVaLimitForBar2_KERNEL return limit; } +/*! + * @brief Calculates the BAR2 VA limit (in Byte units) + * Can be safely called only after kbusSetBarsApertureSize_HAL is executed. + */ +NvU64 kbusGetVaLimitForBar2_IMPL +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NvU64 limit = 0; + NvU32 gfid; + + NV_ASSERT_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid) == NV_OK, 0); + + // + // Return zero from the guest in the paravirtualization case or + // if guest is running in SRIOV heavy mode. + // + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + return 0; + } + + kbusCalcCpuInvisibleBar2Range_HAL(pGpu, pKernelBus, gfid); + + // + // we are just accounting here for possibility that + // we are on pre_PASCAL and so we set the va limit + // to account only for the cpuVisible Aperture + // + if (pKernelBus->bar2[gfid].cpuInvisibleLimit > pKernelBus->bar2[gfid].cpuInvisibleBase) + { + limit = pKernelBus->bar2[gfid].cpuInvisibleLimit; + } + else + { + limit = pKernelBus->bar2[gfid].cpuVisibleLimit; + } + NV_PRINTF(LEVEL_INFO, "va limit: 0x%llx\n", limit); + // + // pKernelBus->bar2.vaLimit is set by this function. + // Assert to ensure that this value doesn't get changed. + // + NV_ASSERT(pKernelBus->bar2[gfid].vaLimit == 0 || pKernelBus->bar2[gfid].vaLimit == limit); + + return limit; +} + /*! * Patch CPU-RM's SW cache of BAR1 PDB to GSP-RM's BAR1 PDB so that CPU-RM can * do TLB invalidation to correct VA space. @@ -655,7 +731,7 @@ kbusPatchBar1Pdb_GSPCLIENT MEMORY_DESCRIPTOR *pMemDesc = NULL; GVAS_GPU_STATE *pGpuState = gvaspaceGetGpuState(pGVAS, pGpu); const MMU_FMT_LEVEL *pRootFmt = pGpuState->pFmt->pRoot; - NvU32 rootSize = pRootFmt->entrySize; + NvU32 rootSize = mmuFmtLevelSize(pRootFmt); MMU_WALK_USER_CTX userCtx = {0}; GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); @@ -676,7 +752,7 @@ kbusPatchBar1Pdb_GSPCLIENT pRootFmt, vaspaceGetVaStart(pKernelBus->bar1[GPU_GFID_PF].pVAS), (MMU_WALK_MEMDESC*)pMemDesc, - mmuFmtLevelSize(pRootFmt), + rootSize, NV_TRUE, NV_TRUE, NV_FALSE); @@ -767,6 +843,16 @@ kbusPatchBar2Pdb_GSPCLIENT return NV_OK; } +NvBool +kbusCheckEngine_KERNEL +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + ENGDESCRIPTOR engDesc +) +{ + return kbusCheckEngineWithOrderList_KERNEL(pGpu, pKernelBus, engDesc, NV_TRUE); +} /*! * @brief Checks whether an engine is available or not. @@ -776,23 +862,25 @@ kbusPatchBar2Pdb_GSPCLIENT * rely on timeouts after a read of a register in the reg space for engine. * Instead, it * - Return TRUE for all engines which are must present in GPU. - * - Get information about CE, MSENC, NVJPG and OFA engines from plugin. - * - Rest engines are determined from HAL creation data. + * - Get information about CE, MSENC, NVJPG and OFA engines from plugin or GSP-RM. + * - If bCheckEngineOrder is true, the remaining engines are searched for in gpuChildOrderList_HAL. * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelBus KernelBus pointer * @param[in] engDesc ENGDESCRIPTOR pointer used to check Engine presence + * @param[in] bCheckEngineOrder If true, check gpuChildOrderList_HAL for engDesc as well * * @returns NV_TRUE if engine is available. * NV_FALSE if engine is not available or floorswept. * */ NvBool -kbusCheckEngine_KERNEL +kbusCheckEngineWithOrderList_KERNEL ( OBJGPU *pGpu, KernelBus *pKernelBus, - ENGDESCRIPTOR engDesc + ENGDESCRIPTOR engDesc, + NvBool bCheckEngineOrder ) { NvU32 rmEngineCaps[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX] = {0}; @@ -800,6 +888,21 @@ kbusCheckEngine_KERNEL NvBool bSupported; NV_STATUS status; + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if (pVSI == NULL) + { + return NV_FALSE; + } + + ct_assert(RM_ENGINE_TYPE_LAST <= 64); + ct_assert(NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX == 2); + + nv2080EngineCaps[0] = NvU64_LO32(pVSI->engineList); + nv2080EngineCaps[1] = NvU64_HI32(pVSI->engineList); + } + else { NvU32 i; GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); @@ -929,15 +1032,23 @@ kbusCheckEngine_KERNEL // HAL lists of GPU. So Add ASSERT there. // default: - bSupported = gpuIsEngDescSupported(pGpu, engDesc); - - if (!bSupported) + { + if (bCheckEngineOrder) { - NV_PRINTF(LEVEL_ERROR, "Unable to check engine ID: %d\n", - engDesc); - NV_ASSERT(bSupported); + bSupported = gpuIsEngDescSupported(pGpu, engDesc); + + if (!bSupported) + { + NV_PRINTF(LEVEL_ERROR, "Unable to check engine ID: 0x%x\n", + engDesc); + NV_ASSERT(bSupported); + } } + else + bSupported = NV_FALSE; + return bSupported; + } } } @@ -1266,3 +1377,19 @@ kbusIsGpuP2pAlive_IMPL { return (pKernelBus->totalP2pObjectsAliveRefCount > 0); } + +/** + * @brief Gets BAR0 size in bytes for VF + * + * @param[in] pGpu + * @param[in] pKernelBus + */ +NvU64 kbusGetVfBar0SizeBytes_IMPL +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + // Bar 0 size for VF is always 16MB + return 16llu << 20; +} diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c index 5eeb27dd5b..865a279c68 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2002-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -34,9 +34,12 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "vgpu/rpc.h" +#include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "gpu/subdevice/subdevice_diag.h" +#include "platform/sli/sli.h" +#include "ctrl/ctrl0080/ctrl0080host.h" #include "ctrl/ctrl2080/ctrl2080bus.h" #include "ctrl/ctrl208f/ctrl208fbus.h" @@ -339,6 +342,12 @@ getBusInfos(OBJGPU *pGpu, NV2080_CTRL_BUS_INFO *pBusInfos, NvU32 busInfoListSize } case NV2080_CTRL_BUS_INFO_INDEX_PCIE_GPU_LINK_CAPS: { + if (kbifIsPciBusFamily(pKernelBif) && IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + pBusInfos[i].data = pVSI->pcieGpuLinkCaps; + break; + } } case NV2080_CTRL_BUS_INFO_INDEX_PCIE_ROOT_LINK_CAPS: case NV2080_CTRL_BUS_INFO_INDEX_PCIE_UPSTREAM_LINK_CAPS: diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c index 9e330fe08f..9f7ee1cc10 100644 --- a/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_vbar2.c @@ -899,8 +899,11 @@ kbusMapBar2Aperture_VBAR2 // // Fail the mapping when BAR2 access to CPR vidmem is blocked (for HCC) // It is however legal to allow non-CPR vidmem to be mapped to BAR2 + // Certain mapping requests which arrive with a specific flag set are allowed + // to go through only in HCC devtools mode. // if (kbusIsBarAccessBlocked(pKernelBus) && + (!gpuIsCCDevToolsModeEnabled(pGpu) || !(flags & TRANSFER_FLAGS_PREFER_PROCESSOR)) && !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)) { os_dump_stack(); @@ -1020,8 +1023,11 @@ kbusUnmapBar2ApertureWithFlags_VBAR2 // // Fail the mapping when BAR2 access to CPR vidmem is blocked (for HCC) // It is however legal to allow non-CPR vidmem to be mapped to BAR2 + // Certain mapping requests which arrive with a specific flag set are allowed + // to go through only in HCC devtools mode. // if (kbusIsBarAccessBlocked(pKernelBus) && + (!gpuIsCCDevToolsModeEnabled(pGpu) || !(flags & TRANSFER_FLAGS_PREFER_PROCESSOR)) && !memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)) { NV_ASSERT(0); @@ -1207,3 +1213,46 @@ void kbusUnmapCpuInvisibleBar2Aperture_VBAR2 pVASpaceHiddenHeap->eheapFree(pVASpaceHiddenHeap, vAddr); } +/* + * @brief This function simply rewrites the PTEs for an already + * existing mapping cached in the usedMapList. + * + * This is currently used for updating the PTEs in the BAR2 page + * tables at the top of FB after bootstrapping is done. The PTEs + * for this mapping may be already existing in the page tables at + * the bottom of FB. But those PTEs will be discarded once migration + * to the page tables at the top of FB is done. So, before switching + * to the new page tables, we should be rewrite the PTEs so that the + * cached mapping does not become invalid. The *only* use case currently + * is the CPU pointer to the new page tables at the top of FB. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * @param[in] pMemDesc MEMORY_DESCRIPTOR pointer. + * + * @return NV_OK if operation is OK + * Error otherwise. + */ +NV_STATUS +kbusRewritePTEsForExistingMapping_VBAR2 +( + OBJGPU *pGpu, + KernelBus *pKernelBus, + PMEMORY_DESCRIPTOR pMemDesc +) +{ + VirtualBar2MapListIter it; + + it = listIterAll(&pKernelBus->virtualBar2[GPU_GFID_PF].usedMapList); + while (listIterNext(&it)) + { + VirtualBar2MapEntry *pMap = it.pValue; + + if (pMap->pMemDesc == pMemDesc) + { + return kbusUpdateRmAperture_HAL(pGpu, pKernelBus, pMemDesc, pMap->vAddr, + pMemDesc->Size, 0); + } + } + return NV_ERR_INVALID_OPERATION; +} diff --git a/src/nvidia/src/kernel/gpu/bus/kern_bus_vgpu.c b/src/nvidia/src/kernel/gpu/bus/kern_bus_vgpu.c new file mode 100644 index 0000000000..1afd4623bb --- /dev/null +++ b/src/nvidia/src/kernel/gpu/bus/kern_bus_vgpu.c @@ -0,0 +1,186 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/gpu.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/subdevice/subdevice.h" +#include "vgpu/rpc.h" + +/*! + * @brief Setup BAR2 in physical mode. + * + * 1. Setup Bar2 in physical mode. + * 2. Create CPU Mapping for BAR2. + * 3. Use PA mode to setup RPC buffers in FB memory. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelBus KernelBus pointer + * + * @returns NV_OK on success. + */ +NV_STATUS +kbusBar2BootStrapInPhysicalMode_VGPUSTUB +( + OBJGPU *pGpu, + KernelBus *pKernelBus +) +{ + NV_STATUS status = NV_OK; + + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + // + // Bind in physical mode so that we can allocate + // RPC buffers in BAR2 PA mode. + // + status = kbusBindBar2_HAL(pGpu, pKernelBus, BAR2_MODE_PHYSICAL); + + if (NV_OK != status) + { + NV_PRINTF(LEVEL_ERROR, "Unable to bind BAR2 to physical mode.\n"); + return status; + } + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + + status = kbusSetupBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + + pKernelBus->bIsBar2SetupInPhysicalMode = NV_TRUE; + +cleanup: + if (status != NV_OK) + { + kbusTeardownBar2CpuAperture_HAL(pGpu, pKernelBus, GPU_GFID_PF); + } + + return status; +} + +/*! + * @brief Initialize pciBarSizes[], set pKernelBus->bPciBarSizesValid + * + * @param[in] pGpu + * @param[in] pKernelBus + * + * @returns void + */ +NV_STATUS +kbusInitBarsSize_VGPUSTUB(OBJGPU *pGpu, KernelBus *pKernelBus) +{ + if (!pKernelBus->bPciBarSizesValid) + { + pKernelBus->pciBarSizes[0] = kbusGetVfBar0SizeBytes(pGpu, pKernelBus); + pKernelBus->pciBarSizes[1] = pGpu->fbLength; + pKernelBus->pciBarSizes[2] = BUS_BAR2_APERTURE_MB; + + pKernelBus->bPciBarSizesValid = NV_TRUE; + } + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdBusSetP2pMapping_VGPUSTUB +( + Subdevice *pSubdevice, + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJGPU *pRemoteGpu = gpumgrGetGpuFromId(pParams->remoteGpuId); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RS_RES_CONTROL_PARAMS_INTERNAL *pControlParams = pCallContext->pControlParams; + NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS shimParams = {0}; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pRemoteGpu != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pParams->bUseUuid == NV_FALSE, NV_ERR_NOT_SUPPORTED); + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pParams->connectionType != NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID, + NV_ERR_INVALID_ARGUMENT); + + portMemCopy(&shimParams, sizeof(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS), + pParams, sizeof(NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS)); + + portMemCopy(shimParams.remoteGpuUuid, sizeof(shimParams.remoteGpuUuid), + pRemoteGpu->gpuUuid.uuid, sizeof(pRemoteGpu->gpuUuid.uuid)); + + shimParams.bUseUuid = NV_TRUE; + + NV_RM_RPC_CONTROL(pGpu, + pControlParams->hClient, + pControlParams->hObject, + pControlParams->cmd, + &shimParams, + sizeof(shimParams), + status); + + return status; +} + +NV_STATUS +subdeviceCtrlCmdBusUnsetP2pMapping_VGPUSTUB +( + Subdevice *pSubdevice, + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJGPU *pRemoteGpu = gpumgrGetGpuFromId(pParams->remoteGpuId); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RS_RES_CONTROL_PARAMS_INTERNAL *pControlParams = pCallContext->pControlParams; + NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS shimParams = {0}; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pRemoteGpu != NULL, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pParams->bUseUuid == NV_FALSE, NV_ERR_NOT_SUPPORTED); + NV_CHECK_OR_RETURN(LEVEL_ERROR, + pParams->connectionType != NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING_CONNECTION_TYPE_INVALID, + NV_ERR_INVALID_ARGUMENT); + + portMemCopy(&shimParams, sizeof(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS), + pParams, sizeof(NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS)); + + portMemCopy(shimParams.remoteGpuUuid, sizeof(shimParams.remoteGpuUuid), + pRemoteGpu->gpuUuid.uuid, sizeof(pRemoteGpu->gpuUuid.uuid)); + + shimParams.bUseUuid = NV_TRUE; + + NV_RM_RPC_CONTROL(pGpu, + pControlParams->hClient, + pControlParams->hObject, + pControlParams->cmd, + &shimParams, + sizeof(shimParams), + status); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/bus/p2p.c b/src/nvidia/src/kernel/gpu/bus/p2p.c index 065746d306..b192e45cd3 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p.c @@ -170,6 +170,17 @@ NV_STATUS _createThirdPartyP2PMappingExtent NV_ASSERT_OR_RETURN((pMappingLength != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((pMemDesc != NULL), NV_ERR_INVALID_ARGUMENT); + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + if (FLD_TEST_DRF(A080, _CTRL_CMD_VGPU_GET_CONFIG, _PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED, + _FALSE, pVSI->vgpuConfig.vgpuDeviceCapsBits)) + { + return NV_ERR_NOT_SUPPORTED; + } + } + *ppExtentInfo = NULL; pKernelBus = GPU_GET_KERNEL_BUS(pGpu); @@ -376,6 +387,17 @@ NV_STATUS RmThirdPartyP2PMappingFree NV_ASSERT_OR_RETURN((pThirdPartyP2PInfo != NULL), NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((pDevice != NULL), NV_ERR_INVALID_STATE); + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + if (FLD_TEST_DRF(A080, _CTRL_CMD_VGPU_GET_CONFIG, _PARAMS_VGPU_DEV_CAPS_GPU_DIRECT_RDMA_ENABLED, + _FALSE, pVSI->vgpuConfig.vgpuDeviceCapsBits)) + { + return NV_ERR_NOT_SUPPORTED; + } + } + pKernelBus = GPU_GET_KERNEL_BUS(pGpu); length = pMappingInfo->length; @@ -623,6 +645,11 @@ NV_STATUS RmThirdPartyP2PNVLinkGetPages RmPhysAddr physAddr; KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + if (memdescGetPageSize(pMemDesc, AT_CPU) < NVRM_P2P_PAGESIZE_BIG_64K) + { + return NV_ERR_INVALID_STATE; + } + NV_ASSERT(!(address & (NVRM_P2P_PAGESIZE_BIG_64K - 1))); NV_ASSERT(!(length & (NVRM_P2P_PAGESIZE_BIG_64K - 1))); NV_ASSERT(!(offset & (NVRM_P2P_PAGESIZE_BIG_64K - 1))); diff --git a/src/nvidia/src/kernel/gpu/bus/p2p_api.c b/src/nvidia/src/kernel/gpu/bus/p2p_api.c index 29e09be9f7..c98befb0a3 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p_api.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p_api.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2009-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2009-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,6 +23,7 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" @@ -411,8 +412,8 @@ p2papiConstruct_IMPL p2pConnectionType = P2P_CONNECTIVITY_NVLINK; else if (REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED, p2pCaps)) p2pConnectionType = P2P_CONNECTIVITY_PCIE_BAR1; - else if (REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED, p2pCaps)) - p2pConnectionType = P2P_CONNECTIVITY_PCIE; + else if (REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED, p2pCaps)) + p2pConnectionType = P2P_CONNECTIVITY_PCIE_PROPRIETARY; else { NV_PRINTF(LEVEL_ERROR, "Unknown connection type\n"); @@ -424,9 +425,8 @@ p2papiConstruct_IMPL // - P2P reads or/and writes are supported // - The P2P connection is PCIE Mailbox based // - if ((bP2PWriteCapable || bP2PReadCapable) && - p2pConnectionType == P2P_CONNECTIVITY_PCIE) + p2pConnectionType == P2P_CONNECTIVITY_PCIE_PROPRIETARY) { status = kbusSetP2PMailboxBar1Area_HAL(pLocalGpu, pLocalKernelBus, pNv503bAllocParams->mailboxBar1Addr, diff --git a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c index 17c2b42329..bd7884295c 100644 --- a/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/third_party_p2p.c @@ -24,6 +24,7 @@ #include "core/core.h" #include "core/locks.h" #include "gpu/gpu.h" +#include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "gpu/bus/third_party_p2p.h" #include "platform/p2p/p2p_caps.h" diff --git a/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c b/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c index 5e770debcc..46d60e1645 100644 --- a/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c +++ b/src/nvidia/src/kernel/gpu/bus/third_party_p2p_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2011-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2011-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c index 11b60ae473..3d6dbd2835 100644 --- a/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c +++ b/src/nvidia/src/kernel/gpu/ccu/kernel_ccu.c @@ -34,44 +34,13 @@ #include "ctrl/ctrl2080/ctrl2080perf_cf.h" #include "utils/nvassert.h" -/*! - * Constrcutor for kccu class. - * - * @param[in] pGpu GPU object pointer. - * @param[in] pKernelCcu KernelCcu object pointer - * @param[in] engDesc KernelCcu Engine descriptor - * - * @return NV_OK If successfully constructed. - */ -NV_STATUS -kccuConstructEngine_IMPL -( - OBJGPU *pGpu, - KernelCcu *pKernelCcu, - ENGDESCRIPTOR engDesc -) +NV_STATUS kccuConstructEngine_IMPL(OBJGPU *pGpu, + KernelCcu *pKernelCcu, + ENGDESCRIPTOR engDesc) { - NV_PRINTF(LEVEL_INFO, "KernelCcu: Constructor\n"); - return NV_OK; } -/*! - * Destructor - * - * @param[in] pKernelCcu KernelCcu object pointer - */ -void -kccuDestruct_IMPL -( - KernelCcu *pKernelCcu -) -{ - NV_PRINTF(LEVEL_INFO, "KernelCcu: Destructor\n"); - - return; -} - /*! * Allocate memory for class members, create & map shared buffer and initialize counter start * address and head/tail timestamp address @@ -399,11 +368,6 @@ NV_STATUS kccuStateLoad_IMPL NV_PRINTF(LEVEL_INFO, "KernelCcu: State load \n"); - if (IS_VIRTUAL(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } - // Create device shared buffer status = _kccuInitDevSharedBuffer(pGpu, pKernelCcu); if (status != NV_OK) @@ -480,11 +444,6 @@ NV_STATUS kccuMemDescGetForShrBufId_IMPL { NV_PRINTF(LEVEL_INFO, "KernelCcu: Get memdesc for idx(%u) \n", idx); - if (IS_VIRTUAL(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } - if (idx >= CCU_SHRBUF_COUNT_MAX) { NV_PRINTF(LEVEL_ERROR, "CCU memdesc get failed for input idx(%u). Invalid index.\n", @@ -519,11 +478,6 @@ NV_STATUS kccuMemDescGetForSwizzId_IMPL { NvU32 idx = 0; - if (IS_VIRTUAL(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } - for (idx = CCU_MIG_SHRBUF_ID_START; idx < CCU_SHRBUF_COUNT_MAX; idx++) { if (*pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId == swizzId) @@ -687,11 +641,6 @@ NV_STATUS kccuMemDescGetForComputeInst_IMPL { NvU32 idx; - if (IS_VIRTUAL(pGpu)) - { - return NV_ERR_NOT_SUPPORTED; - } - for (idx = CCU_MIG_SHRBUF_ID_START; idx < CCU_SHRBUF_COUNT_MAX; idx++) { if (*pKernelCcu->shrBuf[idx].pCounterDstInfo->pSwizzId == swizzId && diff --git a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c index b9faa5d540..57fab53cf3 100644 --- a/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c +++ b/src/nvidia/src/kernel/gpu/ce/arch/hopper/kernel_ce_gh100.c @@ -45,6 +45,7 @@ #define NV_CE_NUM_FBPCE 4 #define NV_CE_NUM_PCES_NO_LINK_CASE 12 #define NV_CE_MAX_PCE_PER_GRCE 2 +#define NV_CE_HSHUBNVL_ID_0 2 /* * Table for setting the PCE2LCE mapping for WAR configs that cannot be implemented @@ -567,6 +568,61 @@ kceMapPceLceForGRCE_GH100 } } +/** + * @brief This function performs PCE-LCE mappings in the CC case where + * a 1-1 mapping is applied. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKCe KernelCE pointer + * @param[in] pceAvailableMaskPerHshub Pointer to CEs available per HSHUB + * @param[out] pLocalPceLceMap Pointer to PCE-LCE array + * @param[out] pLocalExposeCeMask Pointer to LCE Mask + */ +static void +kceMapPceLceForCC +( + OBJGPU *pGpu, + KernelCE *pKCe, + NvU32 *pceAvailableMaskPerHshub, + NvU32 *pLocalPceLceMap, + NvU32 *pLocalGrceMap, + NvU32 *pLocalExposeCeMask +) +{ + NvU32 pceIndex = 0; + NvU32 maxLceIdx, lceMask, lceIndex, grceIdx; + + // Apply 1-1 mapping for async LCEs + lceMask = NV_CE_MAX_LCE_MASK & (~kceGetGrceSupportedLceMask_HAL(pGpu, pKCe)); + maxLceIdx = lceMask; + HIGHESTBITIDX_32(maxLceIdx); + *pLocalExposeCeMask |= lceMask; + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + for(; lceIndex <= maxLceIdx; lceIndex++) + { + pLocalPceLceMap[pceIndex] = lceIndex; + lceMask &= (~(NVBIT32(lceIndex))); + pceIndex++; + } + + + // Map GRCEs as non sharing. At this point, no PCEs have been mapped + lceMask = kceGetGrceSupportedLceMask_HAL(pGpu, pKCe); + *pLocalExposeCeMask |= lceMask; + for (grceIdx = 0; grceIdx < NV_CE_MAX_GRCE; grceIdx++) + { + lceIndex = CE_GET_LOWEST_AVAILABLE_IDX(lceMask); + if (((NVBIT32(lceIndex) & NV_CE_MAX_LCE_MASK) != 0) && (pceIndex < kceGetPce2lceConfigSize1_HAL(pKCe))) + { + pLocalPceLceMap[pceIndex] = lceIndex; + lceMask &= (~(NVBIT32(lceIndex))); + pLocalGrceMap[grceIdx] = DRF_NUM(_CE, _GRCE_CONFIG, _SHARED, 0) | + DRF_DEF(_CE, _GRCE_CONFIG, _SHARED_LCE, _NONE); + pceIndex++; + } + } +} + /** * @brief This function assigns PCE-LCE mappings for NVLink peers * Based on HSHUBs that the links associated with a peer connect to, @@ -891,6 +947,14 @@ kceGetMappings_GH100 } + // In CC case a 1-1 mapping should be applied and other mappings are not required + if (gpuIsCCFeatureEnabled(pGpu)) + { + kceMapPceLceForCC(pGpu, pKCe, pTopoParams->pceAvailableMaskPerHshub, + pLocalPceLceMap, pLocalGrceMap, pExposeCeMask); + goto returnSuccess; + } + //Prepare the per-HSHUB/FBHUB available PCE mask kceGetAvailableHubPceMask(pGpu, pKCe, pTopoParams); @@ -929,5 +993,208 @@ kceGetMappings_GH100 } NV_PRINTF(LEVEL_INFO, "status = %d, statusC2C = %d\n", status, statusC2C); + +returnSuccess: + return NV_OK; +} + +NV_STATUS kceGetP2PCes_GH100(KernelCE *pKCe, OBJGPU *pGpu, NvU32 gpuMask, NvU32 *nvlinkP2PCeMask) +{ + // + // Currently Bug 4103154 requires an updated algorithm described below + // to assign the proper LCE. Cases without MODS enabled can default back + // to the previous version. + // + return kceGetP2PCes_GV100(pKCe, pGpu, gpuMask, nvlinkP2PCeMask); + + NvU32 gpuCount = gpumgrGetSubDeviceCount(gpuMask); + NvU32 minP2PLce = (NV_CE_EVEN_ASYNC_LCE_MASK | NV_CE_ODD_ASYNC_LCE_MASK) & NV_CE_MAX_LCE_MASK; + NvU32 i; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + if (pKernelNvlink == NULL) + { + return NV_WARN_NOTHING_TO_DO; + } + + if (knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink)) + { + return kceGetP2PCes_GV100(pKCe, pGpu, gpuMask, nvlinkP2PCeMask); + } + + LOWESTBITIDX_32(minP2PLce); + *nvlinkP2PCeMask = 0; + + if (gpuCount == 1) + { + *nvlinkP2PCeMask |= NVBIT(minP2PLce); + for (i = minP2PLce; i < gpuGetNumCEs(pGpu); i++) + { + *nvlinkP2PCeMask |= NVBIT(i); + + } + } + else if (gpuCount > 2) + { + // if gpuCount > 2, this is an invalid request. Print warning and return NV_OK + NV_PRINTF(LEVEL_INFO, "GPU %d invalid request for gpuCount %d\n", gpuGetInstance(pGpu), gpuCount); + return NV_ERR_INVALID_STATE; + } + else + { + OBJGPU *pRemoteGpu = NULL; + KernelCE *pKCeLoop = NULL; + NvU32 peerLinkMask = 0; + NvU32 gpuInstance = 0; + NvU32 phyLinkId, status, targetPceMask, numPces; + + // + // The LCE returned should be the LCE which has the most PCEs mapped + // on the given HSHUB. This HSHUB should be determined by + // tracking where the majority of links are connected. + // + NvU32 linksPerHshub[NV_CE_MAX_HSHUBS] = {0}; + NvU32 maxLinksConnectedHshub = 0; + NvU32 maxConnectedHshubId = NV_CE_MAX_HSHUBS; + NvU32 lceAssignedMask = 0; + KernelCE *maxLcePerHshub[NV_CE_MAX_HSHUBS] = {0}; + + NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS params; + + if (pKernelNvlink != NULL) + { + // Get the remote GPU + while ((pRemoteGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (pRemoteGpu != pGpu) + break; + } + + NV_ASSERT_OR_RETURN(pRemoteGpu != NULL, NV_ERR_INVALID_STATE); + gpuInstance = gpuGetInstance(pRemoteGpu); + + peerLinkMask = knvlinkGetLinkMaskToPeer(pGpu, pKernelNvlink, pRemoteGpu); + } + + portMemSet(¶ms, 0, sizeof(params)); + params.linkMask = peerLinkMask; + + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS, + (void *)¶ms, sizeof(params)); + NV_ASSERT_OK_OR_RETURN(status); + + + FOR_EACH_INDEX_IN_MASK(32, phyLinkId, peerLinkMask) + { + NvU32 hshubId = params.hshubIds[phyLinkId]; + linksPerHshub[hshubId]++; + + if (linksPerHshub[hshubId] > maxLinksConnectedHshub) + { + maxLinksConnectedHshub = linksPerHshub[hshubId]; + maxConnectedHshubId = hshubId; + } + } + FOR_EACH_INDEX_IN_MASK_END; + + // + // Iterate through all Async LCEs to track which HSHUB should + // be using which LCE. This is decided based on the majority. If + // there is a tie, then LCE with the lower index is preferred. + // + KCE_ITER_ALL_BEGIN(pGpu, pKCeLoop, minP2PLce) + NvU32 localMaxPcePerHshub = 0; + KernelCE *localMaxLcePerHshub; + NvU32 localMaxHshub = NV_CE_MAX_HSHUBS; + + // if LCE is stubbed or LCE is already assigned to another peer + if (pKCeLoop->bStubbed) + { + continue; + } + + // LCE is already assigned to this peer + if ((pKCeLoop->nvlinkPeerMask & NVBIT(gpuInstance)) != 0) + { + maxLcePerHshub[maxConnectedHshubId] = pKCeLoop; + break; + } + // LCE is already assigned to another peer + else if (pKCeLoop->nvlinkPeerMask != 0) + { + continue; + } + + NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS params = {0}; + + params.ceEngineType = NV2080_ENGINE_TYPE_COPY(pKCeLoop->publicID); + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK, + (void *)¶ms, sizeof(params)); + NV_ASSERT_OK_OR_RETURN(status); + + // + // An LCE may be utilized across several HSHUBs. Loop through all HSHUBs + // in order to decide which HSHUB holds the majority of this specific LCE. + // To help with this, create a mask of PCEs only on the HSHUB which the peer + // is most connected to by shifting the HSHUB PCE mask + // + + for (i = NV_CE_HSHUBNVL_ID_0; i < NV_CE_MAX_HSHUBS; i++) + { + targetPceMask = params.pceMask & ((NVBIT(NV_CE_PCE_PER_HSHUB) - 1) << ((i - NV_CE_HSHUBNVL_ID_0) * NV_CE_PCE_PER_HSHUB)); + numPces = nvPopCount32(targetPceMask); + if (numPces > localMaxPcePerHshub && !(lceAssignedMask & NVBIT(pKCeLoop->publicID))) + { + localMaxPcePerHshub = numPces; + localMaxLcePerHshub = pKCeLoop; + localMaxHshub = i; + } + } + + if (localMaxHshub < NV_CE_MAX_HSHUBS) + { + maxLcePerHshub[localMaxHshub] = localMaxLcePerHshub; + lceAssignedMask |= NVBIT(localMaxLcePerHshub->publicID); + } + + KCE_ITER_END + + if (maxLcePerHshub[maxConnectedHshubId] != NULL) + { + NV_PRINTF(LEVEL_INFO, + "GPU %d Assigning Peer %d to preferred LCE %d\n", + gpuGetInstance(pGpu), gpuInstance, + maxLcePerHshub[maxConnectedHshubId]->publicID); + } + else + { + // + // In the event that the preferred HSHUB's primary LCE is not available, + // choose the first available LCE which was found and set that index as + // the new preferred hshub. + // + for (i = 0; i < NV_CE_MAX_HSHUBS; i++) + { + if (maxLcePerHshub[i] != NULL) + { + NV_PRINTF(LEVEL_INFO, + "GPU %d Assigning Peer %d to first available LCE %d\n", + gpuGetInstance(pGpu), gpuInstance, + maxLcePerHshub[i]->publicID); + maxConnectedHshubId = i; + break; + } + } + } + + if (maxConnectedHshubId < NV_CE_MAX_HSHUBS) + { + maxLcePerHshub[maxConnectedHshubId]->nvlinkPeerMask = NVBIT(gpuInstance); + *nvlinkP2PCeMask = NVBIT(maxLcePerHshub[maxConnectedHshubId]->publicID); + } + } + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c index 0386851134..05ec23ab05 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c @@ -25,11 +25,11 @@ #include "gpu/ce/kernel_ce.h" #include "gpu/ce/kernel_ce_private.h" #include "gpu/eng_desc.h" -#include "gpu/subdevice/subdevice.h" #include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/intr/intr_service.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/common_nvlink.h" +#include "vgpu/sdk-structures.h" #include "nvRmReg.h" NV_STATUS kceConstructEngine_IMPL(OBJGPU *pGpu, KernelCE *pKCe, ENGDESCRIPTOR engDesc) @@ -62,7 +62,7 @@ NV_STATUS kceConstructEngine_IMPL(OBJGPU *pGpu, KernelCE *pKCe, ENGDESCRIPTOR en } // OBJCE::isPresent would compute this first - if (IS_GSP_CLIENT(pGpu)) + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu)) { pGpu->numCEs++; } @@ -424,6 +424,17 @@ NV_STATUS kceGetFaultMethodBufferSize_IMPL(OBJGPU *pGpu, NvU32 *size) RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS params = {0}; + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pVSI, NV_ERR_INVALID_STATE); + + *size = pVSI->ceFaultMethodBufferDepth; + + return NV_OK; + } + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE, ¶ms, sizeof(params))); diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c index 63ddca25a8..17cedc5f49 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_context.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c index d848183686..4601f13e3d 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c @@ -90,7 +90,7 @@ NvBool ceIsCeGrce(OBJGPU *pGpu, RM_ENGINE_TYPE rmCeEngineType) // check if gr is in the partnerList for (i = 0; i < partnerParams.numPartners; i++) { - if (partnerParams.partnerList[i] == NV2080_ENGINE_TYPE_GRAPHICS) + if (NV2080_ENGINE_TYPE_IS_GR(partnerParams.partnerList[i])) { return NV_TRUE; } diff --git a/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c b/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c index 02c5f50df5..5a54823969 100644 --- a/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c +++ b/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_gh100.c @@ -93,6 +93,11 @@ confComputeDeriveSecrets_GH100(ConfidentialCompute *pConfCompute, OBJGPU *pGpu = ENG_GET_GPU(pConfCompute); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + if (!IS_GSP_CLIENT(pGpu)) + { + return NV_OK; + } + switch (engine) { case MC_ENGINE_IDX_GSP: diff --git a/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c b/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c index 3c32d17765..d9dad8deb9 100644 --- a/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c +++ b/src/nvidia/src/kernel/gpu/conf_compute/arch/hopper/conf_compute_keystore_gh100.c @@ -142,47 +142,33 @@ confComputeKeyStoreDeriveKey_GH100(ConfidentialCompute *pConfCompute, NvU32 glob { const NvU32 slotIndex = getKeySlotFromGlobalKeyId(globalKeyId); cryptoBundle_t (*pKeyStore)[]; + uint8_t * pKey = NULL; + size_t keySize = 0; pKeyStore = pConfCompute->m_keySlot; NV_PRINTF(LEVEL_INFO, "Deriving key for global key ID %x.\n", globalKeyId); - // SEC2 HMAC keys are not generated from the EMK but from the encryption/decryption key. if ((globalKeyId == CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_HMAC_USER)) || (globalKeyId == CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_HMAC_KERN))) { - NvU32 sourceSlotIndex = 0; - - switch (CC_GKEYID_GET_LKEYID(globalKeyId)) - { - case CC_LKEYID_CPU_SEC2_HMAC_USER: - sourceSlotIndex = getKeySlotFromGlobalKeyId( - CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_USER)); - break; - case CC_LKEYID_CPU_SEC2_HMAC_KERN: - sourceSlotIndex = getKeySlotFromGlobalKeyId( - CC_GKEYID_GEN(CC_KEYSPACE_SEC2, CC_LKEYID_CPU_SEC2_DATA_KERN)); - break; - } - - if (!libspdm_sha256_hash_all((const void *)(*pKeyStore)[sourceSlotIndex].cryptBundle.key, - sizeof((*pKeyStore)[sourceSlotIndex].cryptBundle.key), - (uint8_t *)(*pKeyStore)[slotIndex].hmacBundle.key)) - { - return NV_ERR_FATAL_ERROR; - } + pKey = (uint8_t *)(*pKeyStore)[slotIndex].hmacBundle.key; + keySize = sizeof((*pKeyStore)[slotIndex].hmacBundle.key); } else { - if (!libspdm_hkdf_sha256_expand(pConfCompute->m_exportMasterKey, - sizeof(pConfCompute->m_exportMasterKey), - (const uint8_t *)(CC_GKEYID_GET_STR(globalKeyId)), - (size_t)portStringLength(CC_GKEYID_GET_STR(globalKeyId)), - (uint8_t *)(*pKeyStore)[slotIndex].cryptBundle.key, - sizeof((*pKeyStore)[slotIndex].cryptBundle.key))) - { - return NV_ERR_FATAL_ERROR; - } + pKey = (uint8_t *)(*pKeyStore)[slotIndex].cryptBundle.key; + keySize = sizeof((*pKeyStore)[slotIndex].cryptBundle.key); + } + + if (!libspdm_hkdf_sha256_expand(pConfCompute->m_exportMasterKey, + sizeof(pConfCompute->m_exportMasterKey), + (const uint8_t *)(CC_GKEYID_GET_STR(globalKeyId)), + (size_t)portStringLength(CC_GKEYID_GET_STR(globalKeyId)), + pKey, + keySize)) + { + return NV_ERR_FATAL_ERROR; } // LCEs will return an error / interrupt if the key is all 0s. @@ -378,7 +364,34 @@ confComputeKeyStoreRetrieveViaKeyId_GH100 NV_STATUS confComputeKeyStoreUpdateKey_GH100(ConfidentialCompute *pConfCompute, NvU32 globalKeyId) { - return NV_ERR_NOT_SUPPORTED; + const NvU32 slotIndex = getKeySlotFromGlobalKeyId(globalKeyId); + cryptoBundle_t (*pKeyStore)[]; + NvU8 tempMem[CC_AES_256_GCM_KEY_SIZE_BYTES]; + + pKeyStore = pConfCompute->m_keySlot; + + NV_PRINTF(LEVEL_INFO, "Updating key with global key ID %x.\n", globalKeyId); + + if (!libspdm_sha256_hash_all((const void *)(*pKeyStore)[slotIndex].cryptBundle.key, + sizeof((*pKeyStore)[slotIndex].cryptBundle.key), + tempMem)) + { + return NV_ERR_FATAL_ERROR; + } + + if (!libspdm_hkdf_sha256_expand(tempMem, + sizeof(tempMem), + (const uint8_t *)(CC_GKEYID_GET_STR(globalKeyId)), + (size_t)portStringLength(CC_GKEYID_GET_STR(globalKeyId)), + (uint8_t *)(*pKeyStore)[slotIndex].cryptBundle.key, + sizeof((*pKeyStore)[slotIndex].cryptBundle.key))) + { + return NV_ERR_FATAL_ERROR; + } + + portMemSet(tempMem, 0, (NvLength) sizeof(tempMem)); + + return NV_OK; } // diff --git a/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c b/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c index 522005dbd9..fdfad732d1 100644 --- a/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c +++ b/src/nvidia/src/kernel/gpu/conf_compute/ccsl.c @@ -106,6 +106,15 @@ writeKmbToContext } } +static NvBool +isChannel +( + pCcslContext pCtx +) +{ + return (pCtx->msgCounterSize == CSL_MSG_CTR_32) ? NV_TRUE : NV_FALSE; +} + NV_STATUS ccslIncrementCounter_IMPL ( @@ -116,6 +125,11 @@ ccslIncrementCounter_IMPL { NvU32 msgCounterLo = NvU32_BUILD(ctr[3], ctr[2], ctr[1], ctr[0]); + if (pCtx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + switch (pCtx->msgCounterSize) { case CSL_MSG_CTR_32: @@ -126,6 +140,7 @@ ccslIncrementCounter_IMPL if (msgCounterLo > (NV_U32_MAX - increment)) { + NV_PRINTF(LEVEL_ERROR, "CCSL Error! IV overflow detected!\n"); return NV_ERR_INSUFFICIENT_RESOURCES; } @@ -139,6 +154,7 @@ ccslIncrementCounter_IMPL if (msgCounterLo > (NV_U64_MAX - increment)) { + NV_PRINTF(LEVEL_ERROR, "CCSL Error! IV overflow detected!\n"); return NV_ERR_INSUFFICIENT_RESOURCES; } @@ -181,7 +197,7 @@ ccslContextInitViaChannel_IMPL if (ppCtx == NULL) { - return NV_ERR_INVALID_PARAMETER; + return NV_ERR_INVALID_ARGUMENT; } pCcslContext pCtx = portMemAllocNonPaged(sizeof(*pCtx)); @@ -264,7 +280,7 @@ ccslContextInitViaKeyId_KERNEL if (ppCtx == NULL) { - return NV_ERR_INVALID_PARAMETER; + return NV_ERR_INVALID_ARGUMENT; } pCcslContext pCtx = portMemAllocNonPaged(sizeof(*pCtx)); @@ -315,6 +331,12 @@ ccslContextClear_IMPL portMemFree(pCtx); } +NV_STATUS +ccslContextUpdate_KERNEL(pCcslContext pCtx) +{ + return NV_ERR_NOT_SUPPORTED; +} + NV_STATUS ccslRotateIv_IMPL ( @@ -322,10 +344,17 @@ ccslRotateIv_IMPL NvU8 direction ) { - OBJGPU *pGpu; - NvU32 gpuMask; - NvU32 gpuInstance = 0; - RM_API *pRmApi = NULL; + OBJGPU *pGpu; + NvU32 gpuMask; + NvU32 gpuInstance = 0; + RM_API *pRmApi = NULL; + NV_STATUS status = NV_OK; + NvU32 gpuMaskRelease; + + if (pCtx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV_PARAMS rotateIvParams; @@ -334,6 +363,11 @@ ccslRotateIv_IMPL return NV_ERR_INVALID_ARGUMENT; } + if (!isChannel(pCtx)) + { + return NV_ERR_INVALID_ARGUMENT; + } + portMemSet(&rotateIvParams, 0, sizeof(rotateIvParams)); if (direction == CCSL_DIR_HOST_TO_DEVICE) @@ -348,20 +382,50 @@ ccslRotateIv_IMPL (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) { + gpuMaskRelease = 0; if (IS_GSP_CLIENT(pGpu)) { - pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + // + // Attempt to acquire GPU lock. If unsuccessful then return error to UVM and it can + // try later. This is needed as UVM may need to rotate a channel's IV while + // RM is already holding a GPU lock. + // + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_RPC, &gpuMaskRelease); + + if (status == NV_OK) + { + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + } + else if (status == NV_ERR_STATE_IN_USE) + { + return status; + } + else + { + NV_PRINTF(LEVEL_INFO, "Converting %s to NV_ERR_GENERIC.\n", + nvstatusToString(status)); + return NV_ERR_GENERIC; + } } else { pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); } - NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, - pCtx->hClient, - pCtx->hChannel, - NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV, - &rotateIvParams, - sizeof(rotateIvParams))); + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pCtx->hClient, + pCtx->hChannel, + NVC56F_CTRL_ROTATE_SECURE_CHANNEL_IV, + &rotateIvParams, + sizeof(rotateIvParams)), + failed); + + if (IS_GSP_CLIENT(pGpu)) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } } switch (direction) @@ -392,6 +456,14 @@ ccslRotateIv_IMPL } return NV_OK; + +failed: + if (IS_GSP_CLIENT(pGpu)) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + + return status; } NV_STATUS @@ -407,6 +479,11 @@ ccslEncryptWithIv_IMPL NvU8 *authTagBuffer ) { + if (pCtx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; size_t outputBufferSize = bufferSize; @@ -447,9 +524,19 @@ ccslEncrypt_KERNEL NvU8 *authTagBuffer ) { + if (pCtx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; size_t outputBufferSize = bufferSize; + if (bufferSize == 0) + { + return NV_ERR_INVALID_ARGUMENT; + } + if (ccslIncrementCounter(pCtx, pCtx->ivOut, 1) != NV_OK) { return NV_ERR_INSUFFICIENT_RESOURCES; @@ -485,6 +572,11 @@ ccslDecrypt_KERNEL NvU8 const *authTagBuffer ) { + if (pCtx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + NvU8 iv[CC_AES_256_GCM_IV_SIZE_BYTES] = {0}; size_t outputBufferSize = bufferSize; @@ -541,6 +633,7 @@ static NV_STATUS ccslIncrementCounter192(NvU8 *ctr) } if (overflow) { + NV_PRINTF(LEVEL_ERROR, "CCSL Error! IV overflow detected!\n"); return NV_ERR_INSUFFICIENT_RESOURCES; } @@ -562,11 +655,16 @@ ccslSign_IMPL NvU8 *authTagBuffer ) { + if (pCtx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + void *hmac_ctx; - if (bufferSize == 0) + if ((bufferSize == 0) || !isChannel(pCtx)) { - return NV_ERR_INVALID_PARAMETER; + return NV_ERR_INVALID_ARGUMENT; } if (ccslIncrementCounter192(pCtx->nonce) != NV_OK) @@ -644,6 +742,11 @@ ccslQueryMessagePool_IMPL NvU64 limit; NvU64 messageCounter; + if (pCtx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + switch (direction) { case CCSL_DIR_HOST_TO_DEVICE: @@ -673,6 +776,11 @@ ccslIncrementIv_IMPL NV_STATUS status; void *ivPtr; + if (pCtx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + switch (direction) { case CCSL_DIR_HOST_TO_DEVICE: @@ -709,3 +817,13 @@ ccslIncrementIv_IMPL return NV_OK; } + +NV_STATUS +ccslLogDeviceEncryption_IMPL +( + pCcslContext pCtx, + NvU32 bufferSize +) +{ + return NV_ERR_NOT_SUPPORTED; +} diff --git a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c index 7c7c34e141..a3f8d4d188 100644 --- a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c +++ b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute.c @@ -39,11 +39,14 @@ #include "ctrl/ctrl2080/ctrl2080internal.h" #include "ctrl/ctrl2080/ctrl2080spdm.h" #include "kernel/gpu/conf_compute/ccsl.h" +#include "gpu/conf_compute/conf_compute_api.h" +#include "class/clcb33.h" +#include "spdm/rmspdmvendordef.h" /*! * Local object related functions */ -static void _confComputeInitRegistryOverrides(OBJGPU *, ConfidentialCompute*); +static NV_STATUS _confComputeInitRegistryOverrides(OBJGPU *, ConfidentialCompute*); NV_STATUS @@ -51,7 +54,15 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, ConfidentialCompute *pConfCompute, ENGDESCRIPTOR engDesc) { - pConfCompute->pSpdm = NULL; + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status = NV_OK; + NvU32 data = 0; + NvBool bForceEnableCC = 0; + + pConfCompute->pSpdm = NULL; + pConfCompute->pGspHeartbeatTimer = NULL; + pConfCompute->heartbeatPeriodSec = 0; + portMemSet(&pConfCompute->ccStaticInfo, 0, sizeof(pConfCompute->ccStaticInfo)); pConfCompute->gspProxyRegkeys = 0; @@ -70,10 +81,29 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_DEVTOOLS_MODE_ENABLED, NV_TRUE); } - _confComputeInitRegistryOverrides(pGpu, pConfCompute); + status = _confComputeInitRegistryOverrides(pGpu, pConfCompute); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Unexpected failure in confComputeConstructEngine! Status:0x%x\n", status); + return status; + } if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) { + bForceEnableCC = (osReadRegistryDword(pGpu, NV_REG_STR_RM_CONFIDENTIAL_COMPUTE, &data) == NV_OK) && + FLD_TEST_DRF(_REG_STR, _RM_CONFIDENTIAL_COMPUTE, _ENABLED, _YES, data); + + if (!RMCFG_FEATURE_PLATFORM_GSP && !RMCFG_FEATURE_PLATFORM_MODS && !bForceEnableCC) + { + if (!(sysGetStaticConfig(pSys)->bOsCCEnabled)) + { + NV_PRINTF(LEVEL_ERROR, "CPU does not support confidential compute.\n"); + NV_ASSERT(0); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED, NV_FALSE); + return NV_ERR_INVALID_OPERATION; + } + } + NV_CHECK_OR_RETURN(LEVEL_ERROR, confComputeIsGpuCcCapable_HAL(pGpu, pConfCompute), NV_ERR_INVALID_OPERATION); if (pGpu->getProperty(pGpu, PDB_PROP_GPU_APM_FEATURE_CAPABLE)) @@ -88,13 +118,24 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, else if (pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE)) { pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED, NV_TRUE); + pGpu->setProperty(pGpu, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED, NV_TRUE); } else { - NV_PRINTF(LEVEL_ERROR, "GPU does not support confidential compute"); + NV_PRINTF(LEVEL_ERROR, "GPU does not support confidential compute.\n"); NV_ASSERT(0); return NV_ERR_INVALID_OPERATION; } + + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_CC_MULTI_GPU_MODE, &data) == NV_OK) && + (data == NV_REG_STR_RM_CC_MULTI_GPU_MODE_PROTECTED_PCIE)) + { + NV_PRINTF(LEVEL_INFO, "Enabling protected PCIe\n"); + pConfCompute->setProperty(pConfCompute, + PDB_PROP_CONFCOMPUTE_MULTI_GPU_PROTECTED_PCIE_MODE_ENABLED, NV_TRUE); + pConfCompute->gspProxyRegkeys |= + DRF_DEF(GSP, _PROXY_REG, _CONF_COMPUTE_MULTI_GPU_MODE, _PROTECTED_PCIE); + } } return NV_OK; @@ -106,7 +147,7 @@ confComputeConstructEngine_IMPL(OBJGPU *pGpu, * @param[in] pGpu GPU object pointer * @param[in] pConfCompute ConfidentialCompute pointer */ -static void +static NV_STATUS _confComputeInitRegistryOverrides ( OBJGPU *pGpu, @@ -166,6 +207,23 @@ _confComputeInitRegistryOverrides pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, NV_FALSE); } } + + if (IS_FMODEL(pGpu)) + { + // Skip SPDM support on fmodel due to bugs 3553627 and 3556621. + NV_PRINTF(LEVEL_INFO, "Confidential Compute SPDM disabled on Fmodel.\n"); + pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED, NV_FALSE); + } + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + NV_STATUS status = objCreate(&pConfCompute->pSpdm, pConfCompute, Spdm); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM child object creation failed! Status:0x%x\n", status); + return status; + } + } } if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENABLED)) @@ -186,6 +244,8 @@ _confComputeInitRegistryOverrides } } } + + return NV_OK; } /*! @@ -197,7 +257,7 @@ _confComputeInitRegistryOverrides * to be initialized in the GPU child order list, and therefore * SPDM session establishment is the first thing to happen. If another * object precedes Confidential Compute - it will be initialized before - * SPDM session establishment. + * SPDM session establishment. * * @param[in] pGpu GPU object pointer * @param[in] pConfCompute ConfidentialCompute pointer @@ -211,26 +271,12 @@ confComputeEstablishSpdmSessionAndKeys_KERNEL { NV_STATUS status = NV_OK; - if (IS_FMODEL(pGpu)) - { - // Skip SPDM support on fmodel due to bugs 3553627 and 3556621. - return NV_OK; - } - // // Initialize SPDM session between Guest RM and SPDM Responder on GPU. // The session lifetime will track Confidential Compute object state lifetime. // if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) { - status = objCreate(&pConfCompute->pSpdm, pConfCompute, Spdm); - if (status != NV_OK) - { - return status; - } - - NV_ASSERT(pConfCompute->pSpdm); - // Initialize SPDM context & begin session. NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, spdmContextInit(pGpu, pConfCompute->pSpdm), @@ -259,13 +305,20 @@ confComputeEstablishSpdmSessionAndKeys_KERNEL confComputeDeriveSecrets_HAL(pConfCompute, MC_ENGINE_IDX_GSP), ErrorExit); - // Enable encryption for all traffic between CPU and GPU - status = confComputeStartEncryption_HAL(pGpu, pConfCompute); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "ConfCompute : Failed enabling encryption!"); - return status; - } + // Initialize encryption contexts for encrypted traffic between Kernel-RM and GSP. + NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, + &pConfCompute->pRpcCcslCtx, CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_LOCKED_RPC))); + + NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, + &pConfCompute->pDmaCcslCtx, CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_DMA))); + + NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, + &pConfCompute->pReplayableFaultCcslCtx, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT))); + + NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, + &pConfCompute->pNonReplayableFaultCcslCtx, + CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT))); } ErrorExit: @@ -278,14 +331,14 @@ confComputeEstablishSpdmSessionAndKeys_KERNEL * Note: This assumes that Confidential Compute is the first object * to be initialized in the GPU child order list, and therefore * SPDM deinitialization is the last thing to happen. If another - * object precedes Confidential Compute - it will be deinitialized - * before SPDM. + * object precedes Confidential Compute - it will be deinitialized + * before SPDM. * * @param[in] pGpu GPU object pointer * @param[in] pConfCompute ConfidentialCompute pointer */ static NV_STATUS -_confComputeDeinitSpdmSession +_confComputeDeinitSpdmSessionAndKeys ( OBJGPU *pGpu, ConfidentialCompute *pConfCompute @@ -293,12 +346,6 @@ _confComputeDeinitSpdmSession { NV_STATUS status = NV_OK; - if (IS_FMODEL(pGpu)) - { - // Skip SPDM support on fmodel due to bugs 3553627 and 3556621. - return NV_OK; - } - // // Tear down SPDM session between Guest RM and SPDM Responder on GPU. // We must do in pre-unload, before Responder is torn down entirely. @@ -308,10 +355,10 @@ _confComputeDeinitSpdmSession if (pConfCompute->pSpdm == NULL) { // - // If SPDM object doesn't exist, we must have failed earlier. - // Alert in logs and move on. + // If SPDM object doesn't exist, alert in logs and move on. + // This means we either never established the session, or have already torn down. // - NV_PRINTF(LEVEL_ERROR, "SPDM teardown did not occur, as SPDM object is null!\n"); + NV_PRINTF(LEVEL_INFO, "SPDM teardown did not occur, as SPDM object is null!\n"); return NV_OK; } @@ -319,26 +366,23 @@ _confComputeDeinitSpdmSession objDelete(pConfCompute->pSpdm); pConfCompute->pSpdm = NULL; - } + NV_PRINTF(LEVEL_INFO, "SPDM teardown successful.\n"); - return status; -} + // Deinitialize CCSL contexts. + ccslContextClear(pConfCompute->pRpcCcslCtx); + ccslContextClear(pConfCompute->pDmaCcslCtx); + ccslContextClear(pConfCompute->pReplayableFaultCcslCtx); + ccslContextClear(pConfCompute->pNonReplayableFaultCcslCtx); + pConfCompute->pRpcCcslCtx = NULL; + pConfCompute->pDmaCcslCtx = NULL; + pConfCompute->pReplayableFaultCcslCtx = NULL; + pConfCompute->pNonReplayableFaultCcslCtx = NULL; -/*! - * Perform any work that must be done before GPU initialization. - * - * @param[in] pGpu GPU object pointer - * @param[in] pConfCompute ConfidentialCompute pointer - */ -NV_STATUS -confComputeStatePreInitLocked_IMPL -( - OBJGPU *pGpu, - ConfidentialCompute *pConfCompute -) -{ - return confComputeEstablishSpdmSessionAndKeys_HAL(pGpu, pConfCompute); + confComputeKeyStoreDeinit_HAL(pConfCompute); + } + + return status; } /*! @@ -370,6 +414,31 @@ confComputeStatePostLoad_IMPL { NV_PRINTF(LEVEL_INFO, "Performing late SPDM initialization!\n"); status = confComputeEstablishSpdmSessionAndKeys_HAL(pGpu, pConfCompute); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ConfCompute : Failed initializing SPDM!"); + return status; + } + } + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + status = spdmSendInitRmDataCommand_HAL(pGpu, pConfCompute->pSpdm); + if (status != NV_OK) + { + return status; + } + + if (IS_GSP_CLIENT(pGpu) && (pConfCompute->heartbeatPeriodSec != 0)) + { + NV_PRINTF(LEVEL_INFO, "ConfCompute: Registering for SPDM heartbeats with period of 0x%x sec.\n", + pConfCompute->heartbeatPeriodSec); + status = spdmRegisterForHeartbeats(pGpu, pConfCompute->pSpdm, pConfCompute->heartbeatPeriodSec); + if (status != NV_OK) + { + return status; + } + } } return status; @@ -383,15 +452,29 @@ confComputeStatePostLoad_IMPL * @param[in] flags Optional flags describing state unload conditions */ NV_STATUS -confComputeStatePreUnload_IMPL +confComputeStatePreUnload_KERNEL ( OBJGPU *pGpu, ConfidentialCompute *pConfCompute, NvU32 flags ) { - NV_PRINTF(LEVEL_INFO, "Performing SPDM deinitialization in Pre Unload!\n"); - return _confComputeDeinitSpdmSession(pGpu, pConfCompute); + NV_STATUS status = NV_OK; + + if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + if (IS_GSP_CLIENT(pGpu) && (pConfCompute->heartbeatPeriodSec != 0)) + { + status = spdmUnregisterFromHeartbeats(pGpu, pConfCompute->pSpdm); + } + else if (!IS_GSP_CLIENT(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Performing SPDM deinitialization in Pre Unload!\n"); + status = _confComputeDeinitSpdmSessionAndKeys(pGpu, pConfCompute); + } + } + + return status; } NvBool @@ -436,160 +519,77 @@ confComputeStateInitLocked_IMPL return NV_OK; } -NV_STATUS -confComputeStartEncryption_KERNEL +/*! + * Sets fatal error state in ConfCompute session by setting GPU ready + * state to false and invalidating the SPDM session. + * + * @param[in] pGpu : OBJGPU Pointer + * @param[in] pConfCompute : ConfidentialCompute pointer + */ +void +confComputeSetErrorState_KERNEL ( OBJGPU *pGpu, ConfidentialCompute *pConfCompute ) { - NV_STATUS status = NV_OK; - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS params; - - if (!IS_GSP_CLIENT(pGpu)) - { - return NV_ERR_INVALID_STATE; - } - - if ((pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY) == NV_FALSE) && - (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED) == NV_FALSE)) - { - NV_PRINTF(LEVEL_INFO, "ConfCompute: Enabling encryption on Kernel-RM!\n"); - - pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY, NV_TRUE); - pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED, NV_TRUE); - - // - // GSP-RM has already initialized all its secrets successfully. - // We must initialize our own before we attempt to start encryption. - // - NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, - &pConfCompute->pRpcCcslCtx, - CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_LOCKED_RPC))); - NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, - &pConfCompute->pDmaCcslCtx, - CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_CPU_GSP_DMA))); - NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, - &pConfCompute->pReplayableFaultCcslCtx, - CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_REPLAYABLE_FAULT))); - NV_ASSERT_OK_OR_RETURN(ccslContextInitViaKeyId(pConfCompute, - &pConfCompute->pNonReplayableFaultCcslCtx, - CC_GKEYID_GEN(CC_KEYSPACE_GSP, CC_LKEYID_GSP_CPU_NON_REPLAYABLE_FAULT))); - - portMemSet(¶ms, 0, sizeof(params)); - params.bEncryptionControl = NV_TRUE; - - // Tell GSP-RM to start encrypting its responses. - NV_ASSERT_OK_OR_RETURN(status = pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL, - ¶ms, - sizeof(params))); - } - else + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NV_STATUS status = NV_OK; + RM_API *pRmApi = NULL; + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS params = {0}; + + NV_PRINTF(LEVEL_ERROR, "ConfCompute: Fatal error hit!\n"); + + // Set ready state to false + pConfCompute->bAcceptClientRequest = NV_FALSE; + pGpuMgr->ccCaps.bAcceptClientRequest = NV_FALSE; + pGpuMgr->ccCaps.bFatalFailure = NV_TRUE; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE, + ¶ms, + sizeof(params)); + + if (status != NV_OK) { - return NV_ERR_INVALID_STATE; + NV_PRINTF(LEVEL_ERROR, "ConfCompute: Failed setting GPU state to not ready!\n"); } - return NV_OK; -} - -NV_STATUS -confComputeStopEncryption_KERNEL -( - OBJGPU *pGpu, - ConfidentialCompute *pConfCompute -) -{ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL_PARAMS params; - NV_STATUS status = NV_OK; - - if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + // Invalidate SPDM session and all keys + status = _confComputeDeinitSpdmSessionAndKeys(pGpu, pConfCompute); + if (status != NV_OK) { - if (!IS_GSP_CLIENT(pGpu)) - { - return NV_ERR_INVALID_STATE; - } - - if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY)) - { - NV_PRINTF(LEVEL_INFO, "ConfCompute: Turning off receive encryption on Kernel-RM!\n"); - pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY, NV_FALSE); - } - - portMemSet(¶ms, 0, sizeof(params)); - params.bEncryptionControl = NV_FALSE; - - // - // Tell GSP-RM to stop encrypting its data. - // Always have GPU delete secrets, regardless of CPU-RM state. - // - status = pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_ENCRYPTION_CONTROL, - ¶ms, - sizeof(params)); - - // Regardless of response, be sure to disable and clear all encryption secrets from kernel side. - if (pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED)) - { - NV_PRINTF(LEVEL_INFO, "ConfCompute: Turning off send encryption on Kernel-RM!\n"); - pConfCompute->setProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED, NV_FALSE); - } - - // Deinitialize CCSL contexts. - ccslContextClear(pConfCompute->pRpcCcslCtx); - ccslContextClear(pConfCompute->pDmaCcslCtx); - ccslContextClear(pConfCompute->pReplayableFaultCcslCtx); - ccslContextClear(pConfCompute->pNonReplayableFaultCcslCtx); - - pConfCompute->pRpcCcslCtx = NULL; - pConfCompute->pDmaCcslCtx = NULL; - pConfCompute->pReplayableFaultCcslCtx = NULL; - pConfCompute->pNonReplayableFaultCcslCtx = NULL; + NV_PRINTF(LEVEL_ERROR, "ConfCompute: Failed tearing down SPDM!: 0x%x!\n", status); } - - return status; } /*! * Deinitialize all keys required for the Confidential Compute session. * - * Note: This assumes that Confidential Compute is the first object - * to be initialized in the GPU child order list, and therefore - * SPDM deinitialization is the last thing to happen. If another - * object precedes Confidential Compute - it will be deinitialized - * before SPDM. + * Note: Must occur in destructor, rather than confComputeStateDestroy + * as engine state is set to destroy before GSP-RM teardown. Since we + * still need encryption until after GSP-RM teardown, we wait until + * object destruction. * - * @param[in] pGpu GPU object pointer - * @param[in] pConfCompute ConfidentialCompute pointer + * @param[in] pConfCompute ConfidentialCompute pointer */ void -confComputeStateDestroy_IMPL +confComputeDestruct_KERNEL ( - OBJGPU *pGpu, ConfidentialCompute *pConfCompute ) { - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; + OBJGPU *pGpu = ENG_GET_GPU(pConfCompute); - status = _confComputeDeinitSpdmSession(pGpu, pConfCompute); - if (status != NV_OK) + status = _confComputeDeinitSpdmSessionAndKeys(pGpu, pConfCompute); + if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "ConfCompute: Failed deinitializing SPDM: 0x%x!\n", status); } - status = confComputeStopEncryption_HAL(pGpu, pConfCompute); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "ConfCompute: Failed disabling encryption: 0x%x!\n", status); - } - - confComputeKeyStoreDeinit_HAL(pConfCompute); - return; } diff --git a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c index 28396ce6d0..6e19de7d15 100644 --- a/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c +++ b/src/nvidia/src/kernel/gpu/conf_compute/conf_compute_api.c @@ -89,6 +89,7 @@ confComputeApiCtrlCmdSystemGetCapabilities_IMPL pParams->environment = NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_UNAVAILABLE; pParams->ccFeature = NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED; pParams->devToolsMode = NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_DISABLED; + pParams->multiGpuMode = NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_NONE; if (pCcCaps->bApmFeatureCapable) { @@ -111,14 +112,20 @@ confComputeApiCtrlCmdSystemGetCapabilities_IMPL } } + if (pParams->ccFeature != NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED) + { + pParams->environment = NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_PROD; + } + if (pCcCaps->bDevToolsModeEnabled) { pParams->devToolsMode = NV_CONF_COMPUTE_SYSTEM_DEVTOOLS_MODE_ENABLED; + pParams->environment = NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM; } - if (pParams->ccFeature != NV_CONF_COMPUTE_SYSTEM_FEATURE_DISABLED) + if (pCcCaps->bMultiGpuProtectedPcieModeEnabled) { - pParams->environment = NV_CONF_COMPUTE_SYSTEM_ENVIRONMENT_SIM; + pParams->multiGpuMode = NV_CONF_COMPUTE_SYSTEM_MULTI_GPU_MODE_PROTECTED_PCIE; } return NV_OK; @@ -145,11 +152,47 @@ confComputeApiCtrlCmdSystemSetGpusState_IMPL NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_SET_GPUS_STATE_PARAMS *pParams ) { + OBJGPU *pGpu; + NvU32 gpuMask; + NvU32 gpuInstance = 0; + RM_API *pRmApi = NULL; + NV_STATUS status = NV_OK; + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE_PARAMS params = {0}; + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - pConfComputeApi->pCcCaps->bAcceptClientRequest = pParams->bAcceptClientRequest; + // Make sure 'ready state' can't be set after being set to false once. + if (pConfComputeApi->pCcCaps->bFatalFailure) + return NV_ERR_INVALID_ARGUMENT; - return NV_OK; + if (pConfComputeApi->pCcCaps->bAcceptClientRequest && !pParams->bAcceptClientRequest) + { + pConfComputeApi->pCcCaps->bFatalFailure = NV_TRUE; + pConfComputeApi->pCcCaps->bAcceptClientRequest = NV_FALSE; + } + + params.bAcceptClientRequest = pParams->bAcceptClientRequest; + (void)gpumgrGetGpuAttachInfo(NULL, &gpuMask); + + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + if (IS_VIRTUAL(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_GPU_STATE, + ¶ms, + sizeof(params)); + if (status != NV_OK) + return status; + } + + pConfComputeApi->pCcCaps->bAcceptClientRequest = pParams->bAcceptClientRequest; + return status; } NV_STATUS @@ -226,6 +269,7 @@ confComputeApiCtrlCmdGetGpuCertificate_IMPL Subdevice *pSubdevice = NULL; OBJGPU *pGpu = NULL; ConfidentialCompute *pConfCompute = NULL; + NV_STATUS status = NV_OK; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); @@ -235,18 +279,26 @@ confComputeApiCtrlCmdGetGpuCertificate_IMPL pGpu = GPU_RES_GET_GPU(pSubdevice); pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); - if (pConfCompute != NULL) + if (pConfCompute != NULL && pConfCompute->pSpdm != NULL && + pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) { // Set max size of certificate buffers before calling SPDM. pParams->certChainSize = NV_CONF_COMPUTE_CERT_CHAIN_MAX_SIZE; pParams->attestationCertChainSize = NV_CONF_COMPUTE_ATTESTATION_CERT_CHAIN_MAX_SIZE; - return spdmGetCertChains_HAL(pGpu, - pConfCompute->pSpdm, - pParams->certChain, - &pParams->certChainSize, - pParams->attestationCertChain, - &pParams->attestationCertChainSize); + status = spdmGetCertChains_HAL(pGpu, + pConfCompute->pSpdm, + pParams->certChain, + &pParams->certChainSize, + pParams->attestationCertChain, + &pParams->attestationCertChainSize); + if (status != NV_OK) + { + // Attestation failure, tear down the CC system. + confComputeSetErrorState(pGpu, pConfCompute); + } + + return status; } return NV_ERR_OBJECT_NOT_FOUND; @@ -262,6 +314,7 @@ confComputeApiCtrlCmdGetGpuAttestationReport_IMPL Subdevice *pSubdevice = NULL; OBJGPU *pGpu = NULL; ConfidentialCompute *pConfCompute = NULL; + NV_STATUS status = NV_OK; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); @@ -271,20 +324,28 @@ confComputeApiCtrlCmdGetGpuAttestationReport_IMPL pGpu = GPU_RES_GET_GPU(pSubdevice); pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); - if (pConfCompute != NULL) + if (pConfCompute != NULL && pConfCompute->pSpdm != NULL && + pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) { // Set max size of report buffers before calling SPDM. pParams->attestationReportSize = NV_CONF_COMPUTE_GPU_ATTESTATION_REPORT_MAX_SIZE; pParams->cecAttestationReportSize = NV_CONF_COMPUTE_GPU_CEC_ATTESTATION_REPORT_MAX_SIZE; - return spdmGetAttestationReport(pGpu, - pConfCompute->pSpdm, - pParams->nonce, - pParams->attestationReport, - &pParams->attestationReportSize, - &pParams->isCecAttestationReportPresent, - pParams->cecAttestationReport, - &pParams->cecAttestationReportSize); + status = spdmGetAttestationReport(pGpu, + pConfCompute->pSpdm, + pParams->nonce, + pParams->attestationReport, + &pParams->attestationReportSize, + &pParams->isCecAttestationReportPresent, + pParams->cecAttestationReport, + &pParams->cecAttestationReportSize); + if (status != NV_OK) + { + // Attestation failure, tear down the CC system. + confComputeSetErrorState(pGpu, pConfCompute); + } + + return status; } return NV_ERR_OBJECT_NOT_FOUND; @@ -315,3 +376,24 @@ confComputeApiCtrlCmdGpuGetNumSecureChannels_IMPL return NV_OK; } + +NV_STATUS +confComputeApiCtrlCmdSystemGetSecurityPolicy_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_GET_SECURITY_POLICY_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS +confComputeApiCtrlCmdSystemSetSecurityPolicy_IMPL +( + ConfidentialComputeApi *pConfComputeApi, + NV_CONF_COMPUTE_CTRL_SET_SECURITY_POLICY_PARAMS *pParams +) +{ + return NV_ERR_NOT_SUPPORTED; +} + diff --git a/src/nvidia/src/kernel/gpu/deferred_api.c b/src/nvidia/src/kernel/gpu/deferred_api.c index 06351a008c..7ad206a827 100644 --- a/src/nvidia/src/kernel/gpu/deferred_api.c +++ b/src/nvidia/src/kernel/gpu/deferred_api.c @@ -644,7 +644,8 @@ _class5080DeferredApiV2 callContext.secInfo.pProcessToken = (void *)(NvU64) gfid; } - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(rmStatus, + resservSwapTlsCallContext(&pOldContext, &callContext), cleanup); rmStatus = serverControl_Prologue(&g_resServ, &rmCtrlParams, &access, &releaseFlags); @@ -664,7 +665,7 @@ _class5080DeferredApiV2 } } - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); rmStatus = serverControl_Epilogue(&g_resServ, &rmCtrlParams, access, &releaseFlags, rmStatus); } diff --git a/src/nvidia/src/kernel/gpu/device.c b/src/nvidia/src/kernel/gpu/device.c index 4a8ebe1e73..c1b1ff08b4 100644 --- a/src/nvidia/src/kernel/gpu/device.c +++ b/src/nvidia/src/kernel/gpu/device.c @@ -34,8 +34,10 @@ #include "resserv/rs_server.h" #include "resserv/rs_client.h" #include "resserv/rs_resource.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" +#include "platform/sli/sli.h" #include "class/cl0080.h" #include "core/locks.h" @@ -392,6 +394,26 @@ _deviceInit gpuresSetGpu(pGpuResource, pGpu, NV_TRUE); + // + // In case of a SR-IOV enabled guest we create a default client inside + // the guest whose handle can be used for VAS sharing. Setting hClientShare + // to 0 on baremetal causes any VA alloc made under this device to use the + // global vaspace. We do not support use of the global vaspace inside guest. + // The legacy paravirtualization config also makes use of a default client. + // But, in the legacy case, the client is created by the plugin and not guest + // RM . On SR-IOV, vaspace management has been pushed inside the guest. So, + // having a vaspace only on the plugin side won't help since RmMapMemoryDma + // calls will no longer be RPCed to host RM. + // + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && + gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) + { + if (hClientShare == NV01_NULL_OBJECT) + { + hClientShare = pGpu->hDefaultClientShare; + } + } + status = deviceSetClientShare(pDevice, hClientShare, vaSize, vaStartInternal, vaLimitInternal, allocFlags); if (NV_OK != status) diff --git a/src/nvidia/src/kernel/gpu/device_ctrl.c b/src/nvidia/src/kernel/gpu/device_ctrl.c index fb9a03ca87..89029b2616 100644 --- a/src/nvidia/src/kernel/gpu/device_ctrl.c +++ b/src/nvidia/src/kernel/gpu/device_ctrl.c @@ -34,8 +34,11 @@ #include "core/locks.h" #include "gpu/gpu.h" #include "gpu_mgr/gpu_mgr.h" +#include "platform/sli/sli.h" #include "kernel/gpu/rc/kernel_rc.h" #include "virtualization/hypervisor/hypervisor.h" +#include "kernel/virtualization/kernel_vgpu_mgr.h" +#include "vgpu/rpc.h" @@ -246,6 +249,34 @@ deviceCtrlCmdGpuGetVirtualizationMode_IMPL return NV_OK; } +/*! + * @brief This Command issues an RPC call to the host to switch the "backdoor + * VNC" view to the console. + * + * @return Returns NV_STATUS + * NV_ERR_NOT_SUPPORTED If GPU is not present under host hypervisor. + * NV_OK If GPU is present under host hypervisor. + * NV_ERR_INVALID_ARGUMENT If GPU is not present. + * + */ +NV_STATUS +deviceCtrlCmdGpuVirtualizationSwitchToVga_IMPL +( + Device *pDevice +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + NV_STATUS status = NV_OK; + + if (pGpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + NV_RM_RPC_SWITCH_TO_VGA(pGpu, status); + return status; +} + /*! * @brief This Command is used to get GPU SRIOV capabilities * @@ -291,6 +322,90 @@ deviceCtrlCmdGpuGetFindSubDeviceHandle_IMPL return status; } +NV_STATUS +deviceCtrlCmdGpuSetVgpuHeterogeneousMode_IMPL +( + Device *pDevice, + NV0080_CTRL_GPU_SET_VGPU_HETEROGENEOUS_MODE_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvU32 pgpuIndex; + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + NvU32 i; + VGPU_TYPE *pVgpuTypeInfo; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + + if (IS_MIG_ENABLED(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Call not supported with SMC enabled\n"); + return NV_ERR_NOT_SUPPORTED; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex)); + + pPgpuInfo = &pKernelVgpuMgr->pgpuInfo[pgpuIndex]; + + if (pPgpuInfo->heterogeneousTimesliceSizesSupported == NV_FALSE) + { + NV_PRINTF(LEVEL_ERROR, "GPU does not support heterogenenous vGPU mode\n"); + return NV_ERR_NOT_SUPPORTED; + } + + if (pPgpuInfo->numActiveVgpu != 0) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to set heterogeneous vGPU mode as vGPU instance is active\n"); + return NV_ERR_IN_USE; + } + + pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE, pParams->bHeterogeneousMode); + + if (pParams->bHeterogeneousMode) + { + for (i = 0; i < pPgpuInfo->numVgpuTypes; i++) + { + pVgpuTypeInfo = pPgpuInfo->vgpuTypes[i]; + + if (pVgpuTypeInfo == NULL) + continue; + + /* + * When heterogeneous vGPU mode is enabled, initially all + * supported placement IDs are creatable placement IDs + */ + portMemCopy(pPgpuInfo->creatablePlacementIds[i], + sizeof(pPgpuInfo->creatablePlacementIds[i]), + pVgpuTypeInfo->supportedPlacementIds, + sizeof(pVgpuTypeInfo->supportedPlacementIds)); + } + + /* No vGPU instances running, so placement region is empty. */ + bitVectorClrAll(&pPgpuInfo->usedPlacementRegionMap); + } + + return NV_OK; +} + +NV_STATUS +deviceCtrlCmdGpuGetVgpuHeterogeneousMode_IMPL +( + Device *pDevice, + NV0080_CTRL_GPU_GET_VGPU_HETEROGENEOUS_MODE_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu != NULL, NV_ERR_INVALID_ARGUMENT); + + pParams->bHeterogeneousMode = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE); + + return NV_OK; +} + /*! * @brief Get the GPU's sparse texture compute mode setting information. * @@ -384,7 +499,9 @@ deviceCtrlCmdGpuGetVgxCaps_IMPL NV0080_CTRL_GPU_GET_VGX_CAPS_PARAMS *pParams ) { - pParams->isVgx = NV_FALSE; + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + + pParams->isVgx = gpuIsVgxBranded(pGpu); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/device_share.c b/src/nvidia/src/kernel/gpu/device_share.c index b4722a3ce9..868ed37c84 100644 --- a/src/nvidia/src/kernel/gpu/device_share.c +++ b/src/nvidia/src/kernel/gpu/device_share.c @@ -32,7 +32,6 @@ #include "gpu/mem_mgr/vaspace_api.h" #include "rmapi/rs_utils.h" #include "gpu/device/device.h" -#include "gpu/subdevice/subdevice.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/virt_mem_allocator.h" diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c b/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c index 17627e87d7..fe4fcbbcca 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0207.c @@ -23,6 +23,7 @@ #define RM_STRICT_CONFIG_EMIT_DISP_ENGINE_DEFINITIONS 0 +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/disp/kern_disp.h" #include "gpu/disp/head/kernel_head.h" diff --git a/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c b/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c index 4505971c5e..36ec881ed5 100644 --- a/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c +++ b/src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c @@ -399,3 +399,30 @@ kheadGetLoadVCounter_v03_00 { return GPU_REG_RD32(pGpu, NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER(pKernelHead->PublicId)); } + +NvU32 +kdispGetPBTargetAperture_v03_00 +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay, + NvU32 memAddrSpace, + NvU32 cacheSnoop +) +{ + NvU32 pbTargetAperture = PHYS_NVM; + + if ((memAddrSpace == ADDR_SYSMEM) && (cacheSnoop != 0U)) + { + pbTargetAperture = PHYS_PCI_COHERENT; + } + else if (memAddrSpace == ADDR_SYSMEM) + { + pbTargetAperture = PHYS_PCI; + } + else + { + pbTargetAperture = PHYS_NVM; + } + + return pbTargetAperture; +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_channel.c b/src/nvidia/src/kernel/gpu/disp/disp_channel.c index 9a2afb11fe..ebe7492d94 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_channel.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_channel.c @@ -43,6 +43,7 @@ #include "gpu/mem_mgr/context_dma.h" #include "gpu/gpu.h" #include "gpu_mgr/gpu_mgr.h" +#include "platform/sli/sli.h" #include "vgpu/rpc.h" static void @@ -773,6 +774,10 @@ kdispSetPushBufferParamsToPhysical_IMPL // Generate PUSHBUFFER_ADDR. Shift the addr to get the size in 4KB pushBufferParams.physicalAddr = memdescGetPhysAddr(memdescGetMemDescFromGpu(pBufferContextDma->pMemDesc, pGpu), AT_GPU, 0); pushBufferParams.cacheSnoop= pBufferContextDma->CacheSnoop; + pushBufferParams.pbTargetAperture = kdispGetPBTargetAperture_HAL(pGpu, + pKernelDisplay, + pushBufferParams.addressSpace, + pushBufferParams.cacheSnoop); pushBufferParams.valid = NV_TRUE; } else diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c index e52e8a28d8..45a4a6917a 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c @@ -29,6 +29,7 @@ * (b) are ACPI feature related */ +#include "gpu_mgr/gpu_mgr.h" #include "gpu/disp/disp_objs.h" #include "mxm_spec.h" #include "nvacpitypes.h" @@ -787,3 +788,281 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL return status; } + +static NV_STATUS _dispDfpSwitchExternalMux +( + OBJGPU *pGpu, + NvU32 displayId, + NvBool bSwitchItoD +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJPFM *pPfm = SYS_GET_PFM(pSys); + NvU32 muxState = 0, acpiId = 0; + NV_STATUS status = NV_ERR_GENERIC; + + acpiId = pfmFindAcpiId(pPfm, pGpu, displayId); + if (acpiId != 0) + { + // Set the _MXDS acpi method input argument + muxState = FLD_SET_REF_NUM(MXDS_METHOD_MUX_OP, MXDS_METHOD_MUX_OP_SET, muxState); + if (bSwitchItoD) + { + muxState = FLD_SET_REF_NUM(MXDS_METHOD_MUX_SET_MODE, MXDS_METHOD_MUX_SET_MODE_DGPU, muxState); + } + else + { + muxState = FLD_SET_REF_NUM(MXDS_METHOD_MUX_SET_MODE, MXDS_METHOD_MUX_SET_MODE_IGPU, muxState); + } + + status = osCallACPI_MXDS(pGpu, acpiId, &muxState); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "osCallACPI_MXDS failed 0x%x\n", status); + } + } + + return status; +} + +static NV_STATUS _dispValidateDDSMuxSupport +( + OBJGPU *pGpu, + NvU32 displayId, + NvBool *pIsEmbeddedDisplayPort +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + + // Make sure there is one and only one display ID set + if (!ONEBITSET(displayId)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (!pKernelDisplay->pStaticInfo->bExternalMuxSupported && + !pKernelDisplay->pStaticInfo->bInternalMuxSupported) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (pKernelDisplay->pStaticInfo->embeddedDisplayPortMask & displayId) + { + *pIsEmbeddedDisplayPort = NV_TRUE; + } + + return NV_OK; +} + +/*! + * @brief Control call to switch dynamic display MUX between integrated + * and discrete GPU + * + * @Parameter pDispCommon [In] + * @Parameter pParams [In, Out] + * + * @return + * NV_OK + * The request successfully completed. + * NV_ERR_NOT_SUPPORTED + * The Feature is not supported. + * NV_ERR_INVALID_ARGUMENT + * Invalid argument is passed. + * + */ +NV_STATUS +dispcmnCtrlCmdDfpSwitchDispMux_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS *pParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); + KernelDisplay *pKernelDisplay = NULL; + NvBool bSwitchItoD = NV_TRUE; + NvBool bEmbeddedDisplayPort = NV_FALSE; + RM_API *pRmApi = NULL; + NV_STATUS status = NV_OK; + + // Get the right pGpu from subdevice instance given by client + status = dispapiSetUnicastAndSynchronize_HAL( + staticCast(pDispCommon, DisplayApi), + DISPAPI_GET_GPUGRP(pDispCommon), + &pGpu, + NULL, + pParams->subDeviceInstance); + if ((status != NV_OK) || (pGpu == NULL)) + { + return status; + } + + status = _dispValidateDDSMuxSupport(pGpu, pParams->displayId, &bEmbeddedDisplayPort); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Invalid arguments 0x%x\n", status); + return status; + } + + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + + if (FLD_TEST_DRF(0073_CTRL_DFP, _DISP_MUX, _SWITCH, _DGPU_TO_IGPU, pParams->flags)) + { + bSwitchItoD = NV_FALSE; + } + + // Check if current displayId belongs to external mux + if (pKernelDisplay->pStaticInfo->bExternalMuxSupported && !bEmbeddedDisplayPort) + { + status = _dispDfpSwitchExternalMux(pGpu, pParams->displayId, bSwitchItoD); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "external mux switch failed 0x%x\n", status); + } + } + else + { + // switch internal mux + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + status = pRmApi->Control(pRmApi, RES_GET_CLIENT_HANDLE(pDispCommon), + RES_GET_HANDLE(pDispCommon), + NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX, + pParams, sizeof(*pParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "internal mux switch failed 0x%x\n", status); + } + } + + return status; +} + +static NV_STATUS _dispDfpGetExternalMuxStatus +( + OBJGPU *pGpu, + NvU32 *pMuxStatus, + NvU32 displayId +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJPFM *pPfm = SYS_GET_PFM(pSys); + NvU32 acpiId = 0; + NvU32 muxState = 0; + NvU32 mode = 0; + NvU32 acpiidIndex = 0; + NV_STATUS status = NV_OK; + + acpiId = pfmFindAcpiId(pPfm, pGpu, displayId); + if (acpiId == 0) + { + NV_PRINTF(LEVEL_ERROR, "acpiId not found for displayId 0x%x\n", displayId); + return NV_ERR_GENERIC; + } + + // get mux state + status = osCallACPI_MXDS(pGpu, acpiId, &muxState); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ACPI call to get mux state failed.\n"); + return status; + } + + // get mux mode + status = NV_ERR_GENERIC; + for (acpiidIndex = 0; acpiidIndex < pGpu->acpiMethodData.muxMethodData.tableLen; acpiidIndex++) + { + if (pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].acpiId == acpiId) + { + mode = pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].mode; + status = pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable[acpiidIndex].status; + break; + } + } + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "ACPI lookup to get mux mode failed.\n"); + return status; + } + + *pMuxStatus = FLD_SET_DRF_NUM(0073_CTRL_DFP, _DISP_MUX, _STATE, + muxState, *pMuxStatus); + + *pMuxStatus = FLD_SET_DRF_NUM(0073_CTRL_DFP, _DISP_MUX, _MODE, + mode, *pMuxStatus); + + return status; +} + +/*! + * @brief Control call to query display MUX status + * + * @Parameter pDispCommon [In] + * @Parameter pParams [In, Out] + * + * @return + * NV_OK + * The request successfully completed. + * NV_ERR_NOT_SUPPORTED + * The Feature is not supported. + * NV_ERR_INVALID_ARGUMENT + * Invalid argument is passed. + * + */ +NV_STATUS +dispcmnCtrlCmdDfpGetDispMuxStatus_IMPL +( + DispCommon *pDispCommon, + NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS *pParams +) +{ + OBJGPU *pGpu; + KernelDisplay *pKernelDisplay = NULL; + NV_STATUS status = NV_OK; + NvBool bEmbeddedDisplayPort = NV_FALSE; + RM_API *pRmApi = NULL; + + // Get the right pGpu from subdevice instance given by client + status = dispapiSetUnicastAndSynchronize_HAL( + staticCast(pDispCommon, DisplayApi), + DISPAPI_GET_GPUGRP(pDispCommon), + &pGpu, + NULL, + pParams->subDeviceInstance); + if (status != NV_OK || pGpu == NULL) + { + return status; + } + + status = _dispValidateDDSMuxSupport(pGpu, pParams->displayId, &bEmbeddedDisplayPort); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Invalid arguments 0x%x\n", status); + return status; + } + + pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + + // Check if current displayId belongs to external mux + if (pKernelDisplay->pStaticInfo->bExternalMuxSupported && !bEmbeddedDisplayPort) + { + status = _dispDfpGetExternalMuxStatus(pGpu, &pParams->muxStatus, pParams->displayId); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to get external mux status\n"); + } + } + else + { + // get internal mux status + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + status = pRmApi->Control(pRmApi, RES_GET_CLIENT_HANDLE(pDispCommon), + RES_GET_HANDLE(pDispCommon), + NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS, + pParams, sizeof(*pParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to get internal mux status\n"); + } + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c b/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c index e3e2c7671f..a219006102 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c @@ -266,6 +266,26 @@ NV_STATUS dispcmnCtrlCmdVRRSetRgLineActive_IMPL return status; } +static NV_STATUS _kheadCheckVblankCountCallback +( + POBJGPU pGpu, + void *Object, + NvU32 param1, + NvV32 BuffNum, + NV_STATUS Status +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + KernelHead *pKernelHead = KDISP_GET_HEAD(pKernelDisplay, param1); + + if ((--pKernelHead->Vblank.VblankCountTimeout) == 0) + { + pKernelHead->Vblank.Callback.CheckVblankCount.Flags &= ~VBLANK_CALLBACK_FLAG_PERSISTENT; + } + + return NV_OK; +} + NV_STATUS dispcmnCtrlCmdSystemGetVblankCounter_IMPL ( @@ -276,16 +296,101 @@ dispcmnCtrlCmdSystemGetVblankCounter_IMPL OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); KernelHead *pKernelHead; + NvU32 flags = (VBLANK_CALLBACK_FLAG_SPECIFIED_VBLANK_NEXT | VBLANK_CALLBACK_FLAG_PERSISTENT); pKernelHead = KDISP_GET_HEAD(pKernelDisplay, pVBCounterParams->head); - if (pKernelHead == NULL) { NV_PRINTF(LEVEL_ERROR, "invalid head number!\n"); return NV_ERR_INVALID_ARGUMENT; } - pVBCounterParams->verticalBlankCounter = kheadGetLoadVCounter_HAL(pGpu, pKernelHead); + // TODO: make the behaviour same for monolithic and offload RM case + if (IS_GSP_CLIENT(pGpu)) + { + if (pKernelDisplay->pSharedData == NULL) + { + NV_PRINTF(LEVEL_ERROR, "no memory allocated for vblank count\n"); + return NV_ERR_NOT_SUPPORTED; + } + flags |= VBLANK_CALLBACK_FLAG_LOW_LATENCY; + } + + pKernelHead->Vblank.VblankCountTimeout = 60 * VBLANK_INFO_GATHER_KEEPALIVE_SECONDS; + + pKernelHead->Vblank.Callback.CheckVblankCount.Proc = _kheadCheckVblankCountCallback; + pKernelHead->Vblank.Callback.CheckVblankCount.pObject = NULL; + pKernelHead->Vblank.Callback.CheckVblankCount.bObjectIsChannelDescendant = NV_FALSE; + pKernelHead->Vblank.Callback.CheckVblankCount.Param1 = pKernelHead->PublicId; + pKernelHead->Vblank.Callback.CheckVblankCount.Param2 = 0; + pKernelHead->Vblank.Callback.CheckVblankCount.Status = NV_OK; + pKernelHead->Vblank.Callback.CheckVblankCount.bIsVblankNotifyEnable = NV_TRUE; + pKernelHead->Vblank.Callback.CheckVblankCount.Flags = flags; + + kheadAddVblankCallback(pGpu, pKernelHead, &pKernelHead->Vblank.Callback.CheckVblankCount); + + if (IS_GSP_CLIENT(pGpu)) + { + pVBCounterParams->verticalBlankCounter = pKernelDisplay->pSharedData->kHeadVblankCount[pKernelHead->PublicId]; + } + else + { + pVBCounterParams->verticalBlankCounter = kheadGetVblankNormLatencyCounter_HAL(pKernelHead); + } return NV_OK; } + +NV_STATUS dispcmnCtrlCmdVblankSemControl_IMPL( + DispCommon *pDispCommon, + NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS *pParams +) +{ + OBJGPU *pGpu = DISPAPI_GET_GPU(pDispCommon); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pDispCommon); + NvHandle hParent = RES_GET_PARENT_HANDLE(pDispCommon); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(DISPAPI_GET_GPU(pDispCommon)); + NV_STATUS status = NV_OK; + + // Get the right pGpu from subdevice instance given by client + status = dispapiSetUnicastAndSynchronize_HAL( + staticCast(pDispCommon, DisplayApi), + DISPAPI_GET_GPUGRP(pDispCommon), + &pGpu, + NULL, + pParams->subDeviceInstance); + + if (status != NV_OK) + { + return status; + } + + if (pParams->bEnable) + { + // Note: memdescRegisterToGSP() is a noop when either (a) we're not + // operating as a GSP client, or (b) the hMemory is already registered + // with GSP. + // + // Also, note that we don't explicitly unregister here in the + // !pParams->bEnable case: that could unregister the memory out from + // under other uses of this hMemory on GSP (e.g., other vblank semaphore + // controls). Instead, we rely on the hMemory getting unregistered when + // the memdesc is freed. + status = memdescRegisterToGSP(pGpu, hClient, hParent, pParams->hMemory); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memdescRegisterToGSP failed %d\n", status); + return status; + } + } + + // NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_PARAMS and + // NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_PARAMS are + // equivalent, so just pass pParams through. + return pRmApi->Control(pRmApi, + hClient, + RES_GET_HANDLE(pDispCommon), + NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL, + pParams, + sizeof(*pParams)); +} diff --git a/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c b/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c index 43f3030bfb..def5cf6c51 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c @@ -24,7 +24,6 @@ #define RM_STRICT_CONFIG_EMIT_DISP_ENGINE_DEFINITIONS 0 #include "class/cl5070.h" -#include "gpu/device/device.h" #include "gpu/disp/disp_objs.h" #include "gpu/disp/kern_disp.h" #include "gpu/gpu.h" diff --git a/src/nvidia/src/kernel/gpu/disp/disp_objs.c b/src/nvidia/src/kernel/gpu/disp/disp_objs.c index bbd728101a..a56a7db9fa 100644 --- a/src/nvidia/src/kernel/gpu/disp/disp_objs.c +++ b/src/nvidia/src/kernel/gpu/disp/disp_objs.c @@ -40,6 +40,7 @@ #include "gpu/disp/disp_channel.h" #include "gpu/disp/kern_disp.h" #include "gpu_mgr/gpu_mgr.h" +#include "platform/sli/sli.h" #include "kernel/gpu/intr/intr.h" diff --git a/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c b/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c index 903e4913e8..50e14fad90 100644 --- a/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c +++ b/src/nvidia/src/kernel/gpu/disp/head/kernel_head.c @@ -405,6 +405,7 @@ kheadWriteVblankIntrState_IMPL if (updatehw) { kheadWriteVblankIntrEnable_HAL(pGpu, pKernelHead, enablehw); + } } diff --git a/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c b/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c index 9d2042ba39..50fb48bbc5 100644 --- a/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c +++ b/src/nvidia/src/kernel/gpu/disp/inst_mem/arch/v03/disp_inst_mem_0300.c @@ -30,6 +30,7 @@ #define RM_STRICT_CONFIG_EMIT_DISP_ENGINE_DEFINITIONS 0 +#include "gpu_mgr/gpu_mgr.h" #include "gpu/disp/inst_mem/disp_inst_mem.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/context_dma.h" diff --git a/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c b/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c index 68d8372ef2..bced4562c7 100644 --- a/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c +++ b/src/nvidia/src/kernel/gpu/disp/inst_mem/disp_inst_mem.c @@ -32,6 +32,7 @@ #include "gpu/disp/kern_disp.h" #include "gpu/disp/disp_channel.h" #include "gpu/disp/inst_mem/disp_inst_mem.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/mem_mgr/context_dma.h" #include "gpu/mem_mgr/mem_mgr.h" #include "os/nv_memory_type.h" diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index 8ffcf73df0..617f9ed0dc 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,6 +47,7 @@ #include "ctrl/ctrl402c.h" #include "platform/acpi_common.h" #include "nvrm_registry.h" +#include "gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/intr/engine_idx.h" @@ -505,6 +506,110 @@ kdispStateDestroy_IMPL(OBJGPU *pGpu, kdispDestroyCommonHandle(pKernelDisplay); } +NV_STATUS +kdispAllocateSharedMem_IMPL +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay +) +{ + NV_STATUS rmStatus; + void *address = NULL; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_ADDRESS_SPACE addressSpace = ADDR_FBMEM; + struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS params = {0}; + NvBool bIsFbBroken = NV_FALSE; + + NV_ASSERT_OR_RETURN(pKernelDisplay->pSharedData == NULL, NV_ERR_INVALID_STATE); + + bIsFbBroken = pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM); + if (bIsFbBroken) + addressSpace = ADDR_SYSMEM; + + rmStatus = memdescCreate(&pKernelDisplay->pSharedMemDesc, + pGpu, + sizeof(KernelDisplaySharedMem), + RM_PAGE_SIZE, + NV_TRUE, + addressSpace, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to create memdesc from FB!\n"); + return rmStatus; + } + + rmStatus = memdescAlloc(pKernelDisplay->pSharedMemDesc); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to allocate memory from FB!\n"); + goto exit; + } + + address = memdescMapInternal(pGpu, pKernelDisplay->pSharedMemDesc, 0); + if (address == NULL) + { + NV_PRINTF(LEVEL_ERROR, "failed to map memory!\n"); + goto exit; + } + pKernelDisplay->pSharedData = (KernelDisplaySharedMem *)address; + + params.memDescInfo.base = memdescGetPhysAddr(pKernelDisplay->pSharedMemDesc, AT_GPU, 0); + params.memDescInfo.size = sizeof(KernelDisplaySharedMem); + params.memDescInfo.alignment = pKernelDisplay->pSharedMemDesc->Alignment; + params.memDescInfo.addressSpace = addressSpace; + params.memDescInfo.cpuCacheAttrib = NV_MEMORY_UNCACHED; + params.bMap = NV_TRUE; + rmStatus = pRmApi->Control(pRmApi, + kdispGetInternalClientHandle(pKernelDisplay), + kdispGetDispCommonHandle(pKernelDisplay), + NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA, + ¶ms, sizeof(params)); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA RM control failed!\n"); + goto exit; + } + + return rmStatus; + +exit: + kdispFreeSharedMem(pGpu, pKernelDisplay); + return rmStatus; +} + +void +kdispFreeSharedMem_IMPL +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay +) +{ + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);; + struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS params = {0}; + + if (pKernelDisplay->pSharedData != NULL) + { + params.bMap = NV_FALSE; + pRmApi->Control(pRmApi, kdispGetInternalClientHandle(pKernelDisplay), + kdispGetDispCommonHandle(pKernelDisplay), + NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA, + ¶ms, sizeof(params)); + + memdescUnmapInternal(pGpu, pKernelDisplay->pSharedMemDesc, 0); + pKernelDisplay->pSharedData = NULL; + } + + if (pKernelDisplay->pSharedMemDesc != NULL) + { + memdescFree(pKernelDisplay->pSharedMemDesc); + memdescDestroy(pKernelDisplay->pSharedMemDesc); + pKernelDisplay->pSharedMemDesc = NULL; + } +} + NV_STATUS kdispStateLoad_IMPL ( @@ -518,6 +623,8 @@ kdispStateLoad_IMPL if (pKernelDisplay->pInst != NULL) status = instmemStateLoad(pGpu, pKernelDisplay->pInst, flags); + kdispAllocateSharedMem_HAL(pGpu, pKernelDisplay); + return status; } @@ -534,6 +641,8 @@ kdispStateUnload_IMPL if (pKernelDisplay->pInst != NULL) status = instmemStateUnload(pGpu, pKernelDisplay->pInst, flags); + kdispFreeSharedMem_HAL(pGpu, pKernelDisplay); + return status; } @@ -640,6 +749,102 @@ kdispGetIntChnClsForHwCls_IMPL return NV_OK; } +void +kdispNotifyCommonEvent_IMPL +( + OBJGPU *pGpu, + KernelDisplay *pKernelDisplay, + NvU32 notifyIndex, + void *pNotifyParams +) +{ + PEVENTNOTIFICATION pEventNotifications; + NvU32 *pNotifyActions; + NvU32 disableCmd, singleCmd; + NvU32 subDeviceInst; + NOTIFICATION *pParams = (NOTIFICATION *)pNotifyParams; + RS_SHARE_ITERATOR it = serverutilShareIter(classId(NotifShare)); + + // search notifiers with events hooked up for this gpu + while (serverutilShareIterNext(&it)) + { + RsShared *pShared = it.pShared; + DispCommon *pDispCommon; + DisplayApi *pDisplayApi; + Device *pDevice; + INotifier *pNotifier; + NotifShare *pNotifierShare = dynamicCast(pShared, NotifShare); + + if ((pNotifierShare == NULL) || (pNotifierShare->pNotifier == NULL)) + continue; + + pNotifier = pNotifierShare->pNotifier; + pDispCommon = dynamicCast(pNotifier, DispCommon); + + // Only notify matching GPUs + if (pDispCommon == NULL) + continue; + + pDevice = dynamicCast(RES_GET_REF(pDispCommon)->pParentRef->pResource, Device); + if (GPU_RES_GET_GPU(pDevice) != pGpu) + continue; + pDisplayApi = staticCast(pDispCommon, DisplayApi); + + gpuSetThreadBcState(GPU_RES_GET_GPU(pDevice), pDisplayApi->bBcResource); + + disableCmd = NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; + singleCmd = NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE; + + // get notify actions list + subDeviceInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + pNotifyActions = pDisplayApi->pNotifyActions[subDeviceInst]; + if (pNotifyActions == NULL) + { + continue; + } + + // get event list + pEventNotifications = inotifyGetNotificationList(pNotifier); + if (pEventNotifications == NULL) + { + continue; + } + + // skip if client not "listening" to events of this type + if (pNotifyActions[notifyIndex] == disableCmd) + { + continue; + } + + if (pDisplayApi->hNotifierMemory != NV01_NULL_OBJECT && + pDisplayApi->pNotifierMemory != NULL) + { + NvV32 Info32 = 0; + NvV16 Info16 = 0; + + if (pParams != NULL) + { + Info32 = pParams->OtherInfo32; + Info16 = pParams->Info16Status.Info16Status_16.OtherInfo16; + } + + notifyFillNotifierMemory(pGpu, pDisplayApi->pNotifierMemory, Info32, Info16, + NV0073_NOTIFICATION_STATUS_DONE_SUCCESS, notifyIndex); + } + + // ping events bound to subdevice associated with pGpu + osEventNotification(pGpu, pEventNotifications, + (notifyIndex | OS_EVENT_NOTIFICATION_INDEX_MATCH_SUBDEV), + pParams, sizeof(*pParams)); + + // reset if single shot notify action + if (pNotifyActions[notifyIndex] == singleCmd) + { + pNotifyActions[notifyIndex] = disableCmd; + } + } +} + void kdispNotifyEvent_IMPL ( @@ -662,6 +867,7 @@ kdispNotifyEvent_IMPL while (serverutilShareIterNext(&it)) { RsShared *pShared = it.pShared; + DispObject *pDispObject; DisplayApi *pDisplayApi; INotifier *pNotifier; Device *pDevice; @@ -671,17 +877,19 @@ kdispNotifyEvent_IMPL continue; pNotifier = pNotifierShare->pNotifier; - pDisplayApi = dynamicCast(pNotifier, DisplayApi); + pDispObject = dynamicCast(pNotifier, DispObject); // Only notify matching GPUs - if (pDisplayApi == NULL) + if (pDispObject == NULL) continue; - pDevice = dynamicCast(RES_GET_REF(pDisplayApi)->pParentRef->pResource, Device); + pDevice = dynamicCast(RES_GET_REF(pDispObject)->pParentRef->pResource, Device); if (GPU_RES_GET_GPU(pDevice) != pGpu) continue; + pDisplayApi = staticCast(pDispObject, DisplayApi); + gpuSetThreadBcState(GPU_RES_GET_GPU(pDevice), pDisplayApi->bBcResource); disableCmd = NV5070_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; diff --git a/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c b/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c index a88042d639..ef6d0bb305 100644 --- a/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c +++ b/src/nvidia/src/kernel/gpu/disp/rg_line_callback/rg_line_callback.c @@ -25,7 +25,6 @@ #include "gpu/disp/rg_line_callback/rg_line_callback.h" #include "gpu/disp/kern_disp.h" -#include "gpu/device/device.h" #include "gpu/disp/disp_objs.h" #include "rmapi/client.h" #include "gpu/gpu.h" diff --git a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c index 27878fef93..167eb11ccd 100644 --- a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c +++ b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c @@ -261,6 +261,45 @@ kheadAddVblankCallback_IMPL } } +void +kheadPauseVblankCbNotifications_IMPL +( + OBJGPU *pGpu, + KernelHead *pKernelHead, + VBLANKCALLBACK *pCallback +) +{ + VBLANKCALLBACK *pList = NULL; + NvBool bShouldDisable = NV_TRUE; + + // Cache the requested queue and its current vblank count + if (pCallback->Flags & VBLANK_CALLBACK_FLAG_LOW_LATENCY) + { + pList = pKernelHead->Vblank.Callback.pListLL; + } + else + { + pList = pKernelHead->Vblank.Callback.pListNL; + } + + + VBLANKCALLBACK *pPrev = pList; + + while (pPrev) + { + if (pPrev->bIsVblankNotifyEnable == NV_TRUE) + { + bShouldDisable = NV_FALSE; + break; + } + pPrev = pPrev->Next; + } + + if(bShouldDisable) + { + kheadWriteVblankIntrState(pGpu, pKernelHead, NV_HEAD_VBLANK_INTR_AVAILABLE); + } +} void kheadDeleteVblankCallback_IMPL ( diff --git a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c index a2a784fc25..b340dc7451 100644 --- a/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c +++ b/src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank_callback.c @@ -131,17 +131,27 @@ vblcbCtrlSetVBlankNotification_IMPL KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); KernelHead *pKernelHead = KDISP_GET_HEAD(pKernelDisplay, pVblankCallback->LogicalHead); NV_STATUS status = NV_ERR_INVALID_ARGUMENT; + NvBool enabled = NV_FALSE; if (pVblankCallback->CallBack.Proc != NULL) { if (pParams->bSetVBlankNotifyEnable) { pVblankCallback->CallBack.bIsVblankNotifyEnable = NV_TRUE; - kheadAddVblankCallback(pGpu, pKernelHead, &pVblankCallback->CallBack); + + enabled = kheadReadVblankIntrEnable_HAL(pGpu, pKernelHead); + // + // We are assuming list is not empty as DD already done the registration for vsync + // So we can enable the _LAST_DATA in case if it is already disable. + // + if (!enabled) + { + kheadWriteVblankIntrState(pGpu, pKernelHead, NV_HEAD_VBLANK_INTR_ENABLED); + } } else { pVblankCallback->CallBack.bIsVblankNotifyEnable = NV_FALSE; - kheadDeleteVblankCallback(pGpu, pKernelHead, &pVblankCallback->CallBack); + kheadPauseVblankCbNotifications(pGpu, pKernelHead, &pVblankCallback->CallBack); } status = NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/eng_state.c b/src/nvidia/src/kernel/gpu/eng_state.c index 5bdfc2337c..82967db519 100644 --- a/src/nvidia/src/kernel/gpu/eng_state.c +++ b/src/nvidia/src/kernel/gpu/eng_state.c @@ -24,7 +24,6 @@ #include "gpu/gpu.h" #include "gpu/eng_state.h" #include "core/hal.h" -#include "core/info_block.h" #include "core/locks.h" #include "gpu/bus/kern_bus.h" diff --git a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c index f7d46c2144..d10a1b8803 100644 --- a/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c +++ b/src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c @@ -31,6 +31,7 @@ #include "rmapi/rmapi_utils.h" #include "class/cl402c.h" // NV40_I2C #include "kernel/gpu/i2c/i2c_api.h" +#include "platform/sli/sli.h" /* * statics */ @@ -5385,13 +5386,7 @@ isFirmwareRevMismatch DAC_EXTERNAL_DEVICE_REVS currentRev ) { - if (IsKEPLER(pGpu)) - { - return ((currentRev < NV_P2060_MIN_REV) || - (currentRev == DAC_EXTERNAL_DEVICE_REV_5) || - (currentRev == DAC_EXTERNAL_DEVICE_REV_6)); - } - else if (IsMAXWELL(pGpu)) + if (IsMAXWELL(pGpu)) { return (currentRev < NV_P2060_MIN_REV); } diff --git a/src/nvidia/src/kernel/gpu/external_device/gsync.c b/src/nvidia/src/kernel/gpu/external_device/gsync.c index 6bb8471863..b7ae2e81b4 100644 --- a/src/nvidia/src/kernel/gpu/external_device/gsync.c +++ b/src/nvidia/src/kernel/gpu/external_device/gsync.c @@ -35,6 +35,7 @@ #include "core/system.h" #include "core/locks.h" #include "gpu_mgr/gpu_mgr.h" +#include "platform/sli/sli.h" #include "gpu/external_device/gsync.h" #include "os/os.h" #include "rmapi/control.h" diff --git a/src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c b/src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c index db20a28c0a..b066503dce 100644 --- a/src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c +++ b/src/nvidia/src/kernel/gpu/falcon/arch/ampere/kernel_falcon_ga102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -53,6 +53,22 @@ kflcnIsRiscvActive_GA10X return FLD_TEST_DRF(_PRISCV, _RISCV_CPUCTL, _ACTIVE_STAT, _ACTIVE, val); } +/*! + * Reset falcon using secure reset, ready to run riscv. + */ +void +kflcnResetIntoRiscv_GA102 +( + OBJGPU *pGpu, + KernelFalcon *pKernelFlcn +) +{ + NV_ASSERT_OR_RETURN_VOID(kflcnPreResetWait_HAL(pGpu, pKernelFlcn) == NV_OK); + NV_ASSERT_OK(kflcnResetHw(pGpu, pKernelFlcn)); + kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn); + kflcnRiscvProgramBcr_HAL(pGpu, pKernelFlcn, NV_TRUE); +} + /*! * Program BCR register of RISCV * diff --git a/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c b/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c index 02b30e18df..0eecd8bd11 100644 --- a/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c +++ b/src/nvidia/src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c @@ -26,7 +26,6 @@ */ #include "gpu/falcon/kernel_falcon.h" -#include "gpu/mc/kernel_mc.h" #include "os/os.h" #include "published/turing/tu102/dev_riscv_pri.h" @@ -150,7 +149,8 @@ kflcnIsRiscvActive_TU102 } /*! - * Perform a reset of the Falcon. + * Reset falcon using secure reset. + * This leaves the falcon in falcon mode after reset. */ void kflcnReset_TU102 @@ -158,81 +158,30 @@ kflcnReset_TU102 OBJGPU *pGpu, KernelFalcon *pKernelFlcn ) -{ - kflcnEnable_HAL(pGpu, pKernelFlcn, NV_FALSE); - kflcnEnable_HAL(pGpu, pKernelFlcn, NV_TRUE); -} - -/*! - * Does a reset of the Falcon using secure reset and switches to Falcon mode. - */ -void -kflcnSecureReset_TU102 -( - OBJGPU *pGpu, - KernelFalcon *pKernelFlcn -) { NV_ASSERT_OR_RETURN_VOID(kflcnPreResetWait_HAL(pGpu, pKernelFlcn) == NV_OK); NV_ASSERT_OK(kflcnResetHw(pGpu, pKernelFlcn)); - kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn); - kflcnSwitchToFalcon_HAL(pGpu, pKernelFlcn); + kflcnRegWrite_HAL(pGpu, pKernelFlcn, NV_PFALCON_FALCON_RM, + pGpu->chipId0); } /*! - * Enable or disable the Falcon to FALCON mode. + * Reset falcon using secure reset, ready to run riscv. */ void -kflcnEnable_TU102 +kflcnResetIntoRiscv_TU102 ( OBJGPU *pGpu, - KernelFalcon *pKernelFlcn, - NvBool bEnable + KernelFalcon *pKernelFlcn ) { - KernelMc *pKernelMc = GPU_GET_KERNEL_MC(pGpu); - - if (!bEnable) - { - // Disable in PMC if engine is present in PMC - if (pKernelFlcn->pmcEnableMask > 0) - { - kmcWritePmcEnableReg_HAL(pGpu, pKernelMc, pKernelFlcn->pmcEnableMask, - NV_FALSE, pKernelFlcn->bIsPmcDeviceEngine); - // Read back to create enough of a delay - kmcReadPmcEnableReg_HAL(pGpu, pKernelMc, pKernelFlcn->bIsPmcDeviceEngine); - kmcReadPmcEnableReg_HAL(pGpu, pKernelMc, pKernelFlcn->bIsPmcDeviceEngine); - } - else - { - kflcnSecureReset_HAL(pGpu, pKernelFlcn); - } - } - else - { - // Enable in PMC if engine is present in PMC - if (pKernelFlcn->pmcEnableMask > 0) - { - kmcWritePmcEnableReg_HAL(pGpu, pKernelMc, pKernelFlcn->pmcEnableMask, - NV_TRUE, pKernelFlcn->bIsPmcDeviceEngine); - // Read back to create enough of a delay - kmcReadPmcEnableReg_HAL(pGpu, pKernelMc, pKernelFlcn->bIsPmcDeviceEngine); - kmcReadPmcEnableReg_HAL(pGpu, pKernelMc, pKernelFlcn->bIsPmcDeviceEngine); - } - else - { - kflcnSecureReset_HAL(pGpu, pKernelFlcn); - } - - kflcnSwitchToFalcon_HAL(pGpu, pKernelFlcn); - - kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn); - - kflcnRegWrite_HAL(pGpu, pKernelFlcn, NV_PFALCON_FALCON_RM, - pGpu->chipId0); - } + // + // Turing and GA100 do not have an explicit core switch, + // the core will be ready to run riscv after reset. + // + kflcnReset_TU102(pGpu, pKernelFlcn); } /*! diff --git a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c index e987a16516..879e0fb348 100644 --- a/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c +++ b/src/nvidia/src/kernel/gpu/falcon/kernel_falcon.c @@ -33,6 +33,7 @@ #include "gpu/device/device.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" +#include "gpu/video/kernel_video_engine.h" #include "mem_mgr/gpu_vaspace.h" #include "mem_mgr/ctx_buf_pool.h" #include "rmapi/rmapi.h" @@ -66,11 +67,17 @@ KernelFalcon *kflcnGetKernelFalconForEngine_IMPL(OBJGPU *pGpu, ENGDESCRIPTOR phy switch (physEngDesc) { // this list is mirrored in subdeviceCtrlCmdInternalGetConstructedFalconInfo_IMPL - case ENG_SEC2: return staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); + case ENG_SEC2: + { + KernelFalcon *pKernelSec2 = staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); + if (pKernelSec2 != NULL) + return pKernelSec2; + break; // If KernelSec2 does not exist on this chip, fall back to GKF list + } case ENG_GSP: return staticCast(GPU_GET_KERNEL_GSP(pGpu), KernelFalcon); - default: - return staticCast(gpuGetGenericKernelFalconForEngine(pGpu, physEngDesc), KernelFalcon); } + + return staticCast(gpuGetGenericKernelFalconForEngine(pGpu, physEngDesc), KernelFalcon); } @@ -349,10 +356,7 @@ void gkflcnRegisterIntrService_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenericK NV_PRINTF(LEVEL_INFO, "physEngDesc 0x%x\n", pKernelFalcon->physEngDesc); - if (!IS_NVDEC(pKernelFalcon->physEngDesc) && - !IS_OFA(pKernelFalcon->physEngDesc) && - !IS_NVJPEG(pKernelFalcon->physEngDesc) && - !IS_MSENC(pKernelFalcon->physEngDesc)) + if (!IS_VIDEO_ENGINE(pKernelFalcon->physEngDesc) && pKernelFalcon->physEngDesc != ENG_SEC2) return; // Register to handle nonstalling interrupts of the corresponding physical falcon in kernel rm @@ -364,7 +368,18 @@ void gkflcnRegisterIntrService_IMPL(OBJGPU *pGpu, GenericKernelFalcon *pGenericK ENGINE_INFO_TYPE_ENG_DESC, pKernelFalcon->physEngDesc, ENGINE_INFO_TYPE_MC, &mcIdx); - NV_ASSERT_OR_RETURN_VOID(status == NV_OK); + if (IS_VIRTUAL(pGpu) && (status == NV_ERR_OBJECT_NOT_FOUND)) + { + // + // In vGPU MIG, the GI does not own all possible engine instances, + // so engine list search returns NV_ERR_OBJECT_NOT_FOUND. + // + return; + } + else + { + NV_ASSERT_OR_RETURN_VOID(status == NV_OK); + } NV_PRINTF(LEVEL_INFO, "Registering 0x%x/0x%x to handle nonstall intr\n", pKernelFalcon->physEngDesc, mcIdx); @@ -405,6 +420,10 @@ NV_STATUS gkflcnServiceNotificationInterrupt_IMPL(OBJGPU *pGpu, GenericKernelFal NvU32 msencIdx = idxMc - MC_ENGINE_IDX_NVENCn(0); rmEngineType = RM_ENGINE_TYPE_NVENC(msencIdx); } + else if (idxMc == MC_ENGINE_IDX_SEC2) + { + rmEngineType = RM_ENGINE_TYPE_SEC2; + } NV_ASSERT_OR_RETURN(rmEngineType != RM_ENGINE_TYPE_NULL, NV_ERR_INVALID_STATE); diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/ada/kernel_fifo_ad102.c b/src/nvidia/src/kernel/gpu/fifo/arch/ada/kernel_fifo_ad102.c new file mode 100644 index 0000000000..c8f6cbce5b --- /dev/null +++ b/src/nvidia/src/kernel/gpu/fifo/arch/ada/kernel_fifo_ad102.c @@ -0,0 +1,194 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "gpu/mmu/kern_gmmu.h" + +#include "published/ada/ad102/dev_fault.h" + +/*! + * @brief Converts a mmu engine id (NV_PFAULT_MMU_ENG_ID_*) into a string. + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] engineID NV_PFAULT_MMU_ENG_ID_* + * + * @returns a string (always non-null) + */ +const char* +kfifoPrintInternalEngine_AD102 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 engineID +) +{ + NV_STATUS status = NV_OK; + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 pbdmaId; + NvU32 engTag; + + if (kfifoIsMmuFaultEngineIdPbdma(pGpu, pKernelFifo, engineID)) + { + NV_ASSERT_OR_RETURN(kfifoGetPbdmaIdFromMmuFaultId(pGpu, pKernelFifo, engineID, &pbdmaId) == NV_OK, "UNKNOWN"); + return kfifoPrintPbdmaId_HAL(pGpu, pKernelFifo, pbdmaId); + } + + if (kgmmuIsFaultEngineBar1_HAL(pKernelGmmu, engineID)) + { + return "BAR1"; + } + else if (kgmmuIsFaultEngineBar2_HAL(pKernelGmmu, engineID)) + { + return "BAR2"; + } + + switch (engineID) + { + case NV_PFAULT_MMU_ENG_ID_DISPLAY: + return "DISPLAY"; + case NV_PFAULT_MMU_ENG_ID_IFB: + return "IFB"; + case NV_PFAULT_MMU_ENG_ID_SEC: + return "SEC"; + case NV_PFAULT_MMU_ENG_ID_PERF: + return "PERF"; + case NV_PFAULT_MMU_ENG_ID_NVDEC0: + return "NVDEC0"; + case NV_PFAULT_MMU_ENG_ID_NVDEC1: + return "NVDEC1"; + case NV_PFAULT_MMU_ENG_ID_NVDEC2: + return "NVDEC2"; + case NV_PFAULT_MMU_ENG_ID_NVDEC3: + return "NVDEC3"; + case NV_PFAULT_MMU_ENG_ID_CE0: + return "CE0"; + case NV_PFAULT_MMU_ENG_ID_CE1: + return "CE1"; + case NV_PFAULT_MMU_ENG_ID_CE2: + return "CE2"; + case NV_PFAULT_MMU_ENG_ID_CE3: + return "CE3"; + case NV_PFAULT_MMU_ENG_ID_CE4: + return "CE4"; + case NV_PFAULT_MMU_ENG_ID_CE5: + return "CE5"; + case NV_PFAULT_MMU_ENG_ID_PWR_PMU: + return "PMU"; + case NV_PFAULT_MMU_ENG_ID_PTP: + return "PTP"; + case NV_PFAULT_MMU_ENG_ID_NVENC0: + return "NVENC0"; + case NV_PFAULT_MMU_ENG_ID_NVENC1: + return "NVENC1"; + case NV_PFAULT_MMU_ENG_ID_NVENC2: + return "NVENC2"; + case NV_PFAULT_MMU_ENG_ID_PHYSICAL: + return "PHYSICAL"; + case NV_PFAULT_MMU_ENG_ID_NVJPG0: + return "NVJPG0"; + case NV_PFAULT_MMU_ENG_ID_NVJPG1: + return "NVJPG1"; + case NV_PFAULT_MMU_ENG_ID_NVJPG2: + return "NVJPG2"; + case NV_PFAULT_MMU_ENG_ID_NVJPG3: + return "NVJPG3"; + case NV_PFAULT_MMU_ENG_ID_OFA0: + return "OFA"; + case NV_PFAULT_MMU_ENG_ID_FLA: + return "FLA"; + default: + { + const char *engine = + kfifoPrintInternalEngineCheck_HAL(pGpu, pKernelFifo, engineID); + if (engine != NULL) + { + return engine; + } + } + } + + status = kfifoEngineInfoXlate_HAL(pGpu, + pKernelFifo, + ENGINE_INFO_TYPE_MMU_FAULT_ID, + engineID, + ENGINE_INFO_TYPE_ENG_DESC, + &engTag); + if ((NV_OK == status) && IS_GR(engTag)) + { + switch (engTag) + { + case ENG_GR(0): + return "GRAPHICS"; + case ENG_GR(1): + return "GR1"; + case ENG_GR(2): + return "GR2"; + case ENG_GR(3): + return "GR3"; + case ENG_GR(4): + return "GR4"; + case ENG_GR(5): + return "GR5"; + case ENG_GR(6): + return "GR6"; + case ENG_GR(7): + return "GR7"; + } + } + + return "UNKNOWN"; +} + +/** + * @brief Converts a subid/clientid into a client string + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] pMmuExceptData + + * @returns a string (always non-null) + */ +const char* +kfifoGetClientIdString_AD102 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptInfo +) +{ + if (!pMmuExceptInfo->bGpc) + { + switch (pMmuExceptInfo->clientId) + { + case NV_PFAULT_CLIENT_HUB_NVJPG1: + return "HUBCLIENT_NVJPG1"; + case NV_PFAULT_CLIENT_HUB_NVJPG2: + return "HUBCLIENT_NVJPG2"; + case NV_PFAULT_CLIENT_HUB_NVJPG3: + return "HUBCLIENT_NVJPG3"; + } + } + // Fallback to GA100 HAL if above did not hit + return kfifoGetClientIdString_GA100(pGpu, pKernelFifo, pMmuExceptInfo); +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c index 8ade76e1b8..c4af0ef9db 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_MANAGER_H_PRIVATE_ACCESS_ALLOWED - #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/fifo/kernel_channel_group_api.h" #include "kernel/gpu/fifo/kernel_channel_group.h" @@ -33,6 +30,7 @@ #include "vgpu/vgpu_events.h" +#include "published/ampere/ga100/dev_fault.h" #include "published/ampere/ga100/dev_ram.h" #include "published/ampere/ga100/dev_ctrl.h" @@ -133,7 +131,7 @@ kfifoChannelGroupGetLocalMaxSubcontext_GA100 RM_ENGINE_TYPE_IS_GR(pKernelChannelGroup->engineType)) { NvU32 grIdx = RM_ENGINE_TYPE_GR_IDX(pKernelChannelGroup->engineType); - return nvPopCount64(pKernelGraphicsManager->grIdxVeidMask[grIdx]); + return nvPopCount64(kgrmgrGetGrIdxVeidMask(pGpu, pKernelGraphicsManager, grIdx)); } // In SMC-Legacy mode, revert to pre-Ampere behavior @@ -317,3 +315,597 @@ kfifoGetMaxCeChannelGroups_GA100 return maxCeChannels; } + +/*! + * @brief Provides PBDMA Fault IDs for requested engines + * + * @param[IN] pGpu Pointer to OBJGPU instance + * @param[IN] pKernelFifo Pointer to KernelFifo instance + * @param[IN] type Engine_info_type to determine if en engine need to be searched + * or not. + * @param[IN] val Engine value associated with the requested INFO_TYPE + * @param[OUT] ppPbdmaFaultIds Buffer to fill output PBDMA_FAULT_IDS + * @param[OUT] pNumPbdmas Number of PBDMAs or valid buffer entries in above buffer + * + */ +NV_STATUS +kfifoGetEnginePbdmaFaultIds_GA100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + ENGINE_INFO_TYPE type, + NvU32 val, + NvU32 **ppPbdmaFaultIds, + NvU32 *pNumPbdmas +) +{ + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + NvU32 i; + + *pNumPbdmas = 0; + + if (pEngineInfo == NULL) + { + NV_ASSERT_OK_OR_RETURN(kfifoConstructEngineList_HAL(pGpu, pKernelFifo)); + + pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + NV_ASSERT_OR_RETURN(pEngineInfo != NULL, NV_ERR_INVALID_STATE); + } + + if (type == ENGINE_INFO_TYPE_INVALID) + { + NV_ASSERT_OR_RETURN(val < pEngineInfo->engineInfoListSize, NV_ERR_INVALID_ARGUMENT); + *ppPbdmaFaultIds = pEngineInfo->engineInfoList[val].pbdmaFaultIds; + *pNumPbdmas = pEngineInfo->engineInfoList[val].numPbdmas; + return NV_OK; + } + + for (i = 0; i < pEngineInfo->engineInfoListSize; i++) + { + if (pEngineInfo->engineInfoList[i].engineData[type] == val) + { + *ppPbdmaFaultIds = pEngineInfo->engineInfoList[i].pbdmaFaultIds; + *pNumPbdmas = pEngineInfo->engineInfoList[i].numPbdmas; + return NV_OK; + } + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + +/** + * @brief Get the number of PBDMAs + * + * @param pGpu OBJGPU pointer + * @param pKernelFifo KernelFifo pointer + */ +NvU32 +kfifoGetNumPBDMAs_GA100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo +) +{ + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + + NV_PRINTF(LEVEL_INFO, "%d PBDMAs\n", pEngineInfo->maxNumPbdmas); + NV_ASSERT(pEngineInfo->maxNumPbdmas != 0); + + return pEngineInfo->maxNumPbdmas; +} + +/** +* @brief Convert PBDMA ID to string +* @param[in] pGpu +* @param[in] pKernelFifo +* @param[in] pbdmaId +* +* @return cont string +*/ +const char* +kfifoPrintPbdmaId_GA100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 pbdmaId +) +{ + NV_ASSERT_OR_RETURN(pbdmaId < kfifoGetNumPBDMAs_HAL(pGpu, pKernelFifo), "UNKNOWN"); + static const char* pbdmaIdString[64] = { "HOST0" , "HOST1" , "HOST2" , "HOST3" , "HOST4" , "HOST5" , "HOST6" , "HOST7" , + "HOST8" , "HOST9" , "HOST10", "HOST11", "HOST12", "HOST13", "HOST14", "HOST15", + "HOST16", "HOST17", "HOST18", "HOST19", "HOST20", "HOST21", "HOST22", "HOST23", + "HOST24", "HOST25", "HOST26", "HOST27", "HOST28", "HOST29", "HOST30", "HOST31", + "HOST32", "HOST33", "HOST34", "HOST35", "HOST36", "HOST37", "HOST38", "HOST39", + "HOST40", "HOST41", "HOST42", "HOST43", "HOST44", "HOST45", "HOST46", "HOST47", + "HOST48", "HOST49", "HOST50", "HOST51", "HOST52", "HOST53", "HOST54", "HOST55", + "HOST56", "HOST57", "HOST58", "HOST59", "HOST60", "HOST61", "HOST62", "HOST63"}; + + return pbdmaIdString[pbdmaId]; +} + +/*! + * @brief Converts a mmu engine id (NV_PFAULT_MMU_ENG_ID_*) into a string. + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] engineID NV_PFAULT_MMU_ENG_ID_* + * + * @returns a string (always non-null) + */ +const char* +kfifoPrintInternalEngine_GA100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 engineID +) +{ + NV_STATUS status = NV_OK; + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 pbdmaId; + NvU32 engTag; + + if (kfifoIsMmuFaultEngineIdPbdma(pGpu, pKernelFifo, engineID)) + { + NV_ASSERT_OR_RETURN(kfifoGetPbdmaIdFromMmuFaultId(pGpu, pKernelFifo, engineID, &pbdmaId) == NV_OK, "UNKNOWN"); + return kfifoPrintPbdmaId_HAL(pGpu, pKernelFifo, pbdmaId); + } + + if (kgmmuIsFaultEngineBar1_HAL(pKernelGmmu, engineID)) + { + return "BAR1"; + } + else if (kgmmuIsFaultEngineBar2_HAL(pKernelGmmu, engineID)) + { + return "BAR2"; + } + + switch (engineID) + { + case NV_PFAULT_MMU_ENG_ID_DISPLAY: + return "DISPLAY"; + case NV_PFAULT_MMU_ENG_ID_IFB: + return "IFB"; + case NV_PFAULT_MMU_ENG_ID_SEC: + return "SEC"; + case NV_PFAULT_MMU_ENG_ID_PERF: + return "PERF"; + case NV_PFAULT_MMU_ENG_ID_NVDEC0: + return "NVDEC0"; + case NV_PFAULT_MMU_ENG_ID_NVDEC1: + return "NVDEC1"; + case NV_PFAULT_MMU_ENG_ID_NVDEC2: + return "NVDEC2"; + case NV_PFAULT_MMU_ENG_ID_NVDEC3: + return "NVDEC3"; + case NV_PFAULT_MMU_ENG_ID_CE0: + return "CE0"; + case NV_PFAULT_MMU_ENG_ID_CE1: + return "CE1"; + case NV_PFAULT_MMU_ENG_ID_CE2: + return "CE2"; + case NV_PFAULT_MMU_ENG_ID_CE3: + return "CE3"; + case NV_PFAULT_MMU_ENG_ID_CE4: + return "CE4"; + case NV_PFAULT_MMU_ENG_ID_CE5: + return "CE5"; + case NV_PFAULT_MMU_ENG_ID_CE6: + return "CE6"; + case NV_PFAULT_MMU_ENG_ID_CE7: + return "CE7"; + case NV_PFAULT_MMU_ENG_ID_CE8: + return "CE8"; + case NV_PFAULT_MMU_ENG_ID_CE9: + return "CE9"; + case NV_PFAULT_MMU_ENG_ID_PWR_PMU: + return "PMU"; + case NV_PFAULT_MMU_ENG_ID_PTP: + return "PTP"; + case NV_PFAULT_MMU_ENG_ID_NVENC1: + return "NVENC1"; + case NV_PFAULT_MMU_ENG_ID_PHYSICAL: + return "PHYSICAL"; + case NV_PFAULT_MMU_ENG_ID_NVJPG0: + return "NVJPG"; + case NV_PFAULT_MMU_ENG_ID_OFA0: + return "OFA"; + case NV_PFAULT_MMU_ENG_ID_FLA: + return "FLA"; + default: + { + const char *engine = + kfifoPrintInternalEngineCheck_HAL(pGpu, pKernelFifo, engineID); + if (engine != NULL) + { + return engine; + } + } + } + + status = kfifoEngineInfoXlate_HAL(pGpu, + pKernelFifo, + ENGINE_INFO_TYPE_MMU_FAULT_ID, + engineID, + ENGINE_INFO_TYPE_ENG_DESC, + &engTag); + if ((NV_OK == status) && IS_GR(engTag)) + { + switch (engTag) + { + case ENG_GR(0): + return "GRAPHICS"; + case ENG_GR(1): + return "GR1"; + case ENG_GR(2): + return "GR2"; + case ENG_GR(3): + return "GR3"; + case ENG_GR(4): + return "GR4"; + case ENG_GR(5): + return "GR5"; + case ENG_GR(6): + return "GR6"; + case ENG_GR(7): + return "GR7"; + } + } + + return "UNKNOWN"; +} + +/*! + * @brief Converts a mmu engine id (NV_PFAULT_MMU_ENG_ID_*) into a string. + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] engineID NV_PFAULT_MMU_ENG_ID_* + * + * @returns a string + */ +const char* +kfifoPrintInternalEngineCheck_GA100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 engineID +) +{ + switch (engineID) + { + case NV_PFAULT_MMU_ENG_ID_NVDEC4: + return "NVDEC4"; + case NV_PFAULT_MMU_ENG_ID_NVENC0: + return "NVENC0"; + default: + return NULL; + } +} + +/** + * @brief Converts a subid/clientid into a client string + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] pMmuExceptData + + * @returns a string (always non-null) + */ +const char* +kfifoGetClientIdString_GA100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptInfo +) +{ + if (pMmuExceptInfo->bGpc) + { + switch (pMmuExceptInfo->clientId) + { + case NV_PFAULT_CLIENT_GPC_T1_0: + return "GPCCLIENT_T1_0"; + case NV_PFAULT_CLIENT_GPC_T1_1: + return "GPCCLIENT_T1_1"; + case NV_PFAULT_CLIENT_GPC_T1_2: + return "GPCCLIENT_T1_2"; + case NV_PFAULT_CLIENT_GPC_T1_3: + return "GPCCLIENT_T1_3"; + case NV_PFAULT_CLIENT_GPC_T1_4: + return "GPCCLIENT_T1_4"; + case NV_PFAULT_CLIENT_GPC_T1_5: + return "GPCCLIENT_T1_5"; + case NV_PFAULT_CLIENT_GPC_T1_6: + return "GPCCLIENT_T1_6"; + case NV_PFAULT_CLIENT_GPC_T1_7: + return "GPCCLIENT_T1_7"; + case NV_PFAULT_CLIENT_GPC_PE_0: + return "GPCCLIENT_PE_0"; + case NV_PFAULT_CLIENT_GPC_PE_1: + return "GPCCLIENT_PE_1"; + case NV_PFAULT_CLIENT_GPC_PE_2: + return "GPCCLIENT_PE_2"; + case NV_PFAULT_CLIENT_GPC_PE_3: + return "GPCCLIENT_PE_3"; + case NV_PFAULT_CLIENT_GPC_PE_4: + return "GPCCLIENT_PE_4"; + case NV_PFAULT_CLIENT_GPC_PE_5: + return "GPCCLIENT_PE_5"; + case NV_PFAULT_CLIENT_GPC_PE_6: + return "GPCCLIENT_PE_6"; + case NV_PFAULT_CLIENT_GPC_PE_7: + return "GPCCLIENT_PE_7"; + case NV_PFAULT_CLIENT_GPC_RAST: + return "GPCCLIENT_RAST"; + case NV_PFAULT_CLIENT_GPC_GCC: + return "GPCCLIENT_GCC"; + case NV_PFAULT_CLIENT_GPC_GPCCS: + return "GPCCLIENT_GPCCS"; + case NV_PFAULT_CLIENT_GPC_PROP_0: + return "GPCCLIENT_PROP_0"; + case NV_PFAULT_CLIENT_GPC_PROP_1: + return "GPCCLIENT_PROP_1"; + case NV_PFAULT_CLIENT_GPC_T1_8: + return "GPCCLIENT_T1_8"; + case NV_PFAULT_CLIENT_GPC_T1_9: + return "GPCCLIENT_T1_9"; + case NV_PFAULT_CLIENT_GPC_T1_10: + return "GPCCLIENT_T1_10"; + case NV_PFAULT_CLIENT_GPC_T1_11: + return "GPCCLIENT_T1_11"; + case NV_PFAULT_CLIENT_GPC_T1_12: + return "GPCCLIENT_T1_12"; + case NV_PFAULT_CLIENT_GPC_T1_13: + return "GPCCLIENT_T1_13"; + case NV_PFAULT_CLIENT_GPC_T1_14: + return "GPCCLIENT_T1_14"; + case NV_PFAULT_CLIENT_GPC_T1_15: + return "GPCCLIENT_T1_15"; + case NV_PFAULT_CLIENT_GPC_TPCCS_0: + return "GPCCLIENT_TPCCS_0"; + case NV_PFAULT_CLIENT_GPC_TPCCS_1: + return "GPCCLIENT_TPCCS_1"; + case NV_PFAULT_CLIENT_GPC_TPCCS_2: + return "GPCCLIENT_TPCCS_2"; + case NV_PFAULT_CLIENT_GPC_TPCCS_3: + return "GPCCLIENT_TPCCS_3"; + case NV_PFAULT_CLIENT_GPC_TPCCS_4: + return "GPCCLIENT_TPCCS_4"; + case NV_PFAULT_CLIENT_GPC_TPCCS_5: + return "GPCCLIENT_TPCCS_5"; + case NV_PFAULT_CLIENT_GPC_TPCCS_6: + return "GPCCLIENT_TPCCS_6"; + case NV_PFAULT_CLIENT_GPC_TPCCS_7: + return "GPCCLIENT_TPCCS_7"; + case NV_PFAULT_CLIENT_GPC_PE_8: + return "GPCCLIENT_PE_8"; + case NV_PFAULT_CLIENT_GPC_TPCCS_8: + return "GPCCLIENT_TPCCS_8"; + case NV_PFAULT_CLIENT_GPC_T1_16: + return "GPCCLIENT_T1_16"; + case NV_PFAULT_CLIENT_GPC_T1_17: + return "GPCCLIENT_T1_17"; + case NV_PFAULT_CLIENT_GPC_ROP_0: + return "GPCCLIENT_ROP_0"; + case NV_PFAULT_CLIENT_GPC_ROP_1: + return "GPCCLIENT_ROP_1"; + case NV_PFAULT_CLIENT_GPC_GPM: + return "GPCCLIENT_GPM"; + default: + return "UNRECOGNIZED_CLIENT"; + } + } + else + { + switch (pMmuExceptInfo->clientId) + { + case NV_PFAULT_CLIENT_HUB_VIP: + return "HUBCLIENT_VIP"; + case NV_PFAULT_CLIENT_HUB_CE0: + return "HUBCLIENT_CE0"; + case NV_PFAULT_CLIENT_HUB_CE1: + return "HUBCLIENT_CE1"; + case NV_PFAULT_CLIENT_HUB_DNISO: + return "HUBCLIENT_DNISO"; + case NV_PFAULT_CLIENT_HUB_FE: + return "HUBCLIENT_FE"; + case NV_PFAULT_CLIENT_HUB_FECS: + return "HUBCLIENT_FECS"; + case NV_PFAULT_CLIENT_HUB_HOST: + return "HUBCLIENT_HOST"; + case NV_PFAULT_CLIENT_HUB_HOST_CPU: + return "HUBCLIENT_HOST_CPU"; + case NV_PFAULT_CLIENT_HUB_HOST_CPU_NB: + return "HUBCLIENT_HOST_CPU_NB"; + case NV_PFAULT_CLIENT_HUB_ISO: + return "HUBCLIENT_ISO"; + case NV_PFAULT_CLIENT_HUB_MMU: + return "HUBCLIENT_MMU"; + case NV_PFAULT_CLIENT_HUB_NVDEC0: + return "HUBCLIENT_NVDEC0"; + case NV_PFAULT_CLIENT_HUB_NVENC1: + return "HUBCLIENT_NVENC1"; + case NV_PFAULT_CLIENT_HUB_NISO: + return "HUBCLIENT_NISO"; + case NV_PFAULT_CLIENT_HUB_P2P: + return "HUBCLIENT_P2P"; + case NV_PFAULT_CLIENT_HUB_PD: + return "HUBCLIENT_PD"; + case NV_PFAULT_CLIENT_HUB_PERF0: + return "HUBCLIENT_PERF"; + case NV_PFAULT_CLIENT_HUB_PMU: + return "HUBCLIENT_PMU"; + case NV_PFAULT_CLIENT_HUB_RASTERTWOD: + return "HUBCLIENT_RASTERTWOD"; + case NV_PFAULT_CLIENT_HUB_SCC: + return "HUBCLIENT_SCC"; + case NV_PFAULT_CLIENT_HUB_SCC_NB: + return "HUBCLIENT_SCC_NB"; + case NV_PFAULT_CLIENT_HUB_SEC: + return "HUBCLIENT_SEC"; + case NV_PFAULT_CLIENT_HUB_SSYNC: + return "HUBCLIENT_SSYNC"; + case NV_PFAULT_CLIENT_HUB_CE2: + return "HUBCLIENT_CE2"; + case NV_PFAULT_CLIENT_HUB_XV: + return "HUBCLIENT_XV"; + case NV_PFAULT_CLIENT_HUB_MMU_NB: + return "HUBCLIENT_MMU_NB"; + case NV_PFAULT_CLIENT_HUB_DFALCON: + return "HUBCLIENT_DFALCON"; + case NV_PFAULT_CLIENT_HUB_SKED: + return "HUBCLIENT_SKED"; + case NV_PFAULT_CLIENT_HUB_AFALCON: + return "HUBCLIENT_AFALCON"; + case NV_PFAULT_CLIENT_HUB_DONT_CARE: + return "HUBCLIENT_DONT_CARE"; + case NV_PFAULT_CLIENT_HUB_HSCE0: + return "HUBCLIENT_HSCE0"; + case NV_PFAULT_CLIENT_HUB_HSCE1: + return "HUBCLIENT_HSCE1"; + case NV_PFAULT_CLIENT_HUB_HSCE2: + return "HUBCLIENT_HSCE2"; + case NV_PFAULT_CLIENT_HUB_HSCE3: + return "HUBCLIENT_HSCE3"; + case NV_PFAULT_CLIENT_HUB_HSCE4: + return "HUBCLIENT_HSCE4"; + case NV_PFAULT_CLIENT_HUB_HSCE5: + return "HUBCLIENT_HSCE5"; + case NV_PFAULT_CLIENT_HUB_HSCE6: + return "HUBCLIENT_HSCE6"; + case NV_PFAULT_CLIENT_HUB_HSCE7: + return "HUBCLIENT_HSCE7"; + case NV_PFAULT_CLIENT_HUB_HSCE8: + return "HUBCLIENT_HSCE8"; + case NV_PFAULT_CLIENT_HUB_HSCE9: + return "HUBCLIENT_HSCE9"; + case NV_PFAULT_CLIENT_HUB_HSHUB: + return "HUBCLIENT_HSHUB"; + case NV_PFAULT_CLIENT_HUB_PTP_X0: + return "HUBCLIENT_PTP_X0"; + case NV_PFAULT_CLIENT_HUB_PTP_X1: + return "HUBCLIENT_PTP_X1"; + case NV_PFAULT_CLIENT_HUB_PTP_X2: + return "HUBCLIENT_PTP_X2"; + case NV_PFAULT_CLIENT_HUB_PTP_X3: + return "HUBCLIENT_PTP_X3"; + case NV_PFAULT_CLIENT_HUB_PTP_X4: + return "HUBCLIENT_PTP_X4"; + case NV_PFAULT_CLIENT_HUB_PTP_X5: + return "HUBCLIENT_PTP_X5"; + case NV_PFAULT_CLIENT_HUB_NVENC2: + return "HUBCLIENT_NVENC2"; + case NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0: + return "HUBCLIENT_VPR_SCRUBBER0"; + case NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1: + return "HUBCLIENT_VPR_SCRUBBER1"; + case NV_PFAULT_CLIENT_HUB_DWBIF: + return "HUBCLIENT_DWBIF"; + case NV_PFAULT_CLIENT_HUB_FBFALCON: + return "HUBCLIENT_FBFALCON"; + case NV_PFAULT_CLIENT_HUB_CE_SHIM: + return "HUBCLIENT_CE_SHIM"; + case NV_PFAULT_CLIENT_HUB_GSP: + return "HUBCLIENT_GSP"; + case NV_PFAULT_CLIENT_HUB_NVDEC1: + return "HUBCLIENT_NVDEC1"; + case NV_PFAULT_CLIENT_HUB_NVDEC2: + return "HUBCLIENT_NVDEC2"; + case NV_PFAULT_CLIENT_HUB_NVJPG0: + return "HUBCLIENT_NVJPG0"; + case NV_PFAULT_CLIENT_HUB_NVDEC3: + return "HUBCLIENT_NVDEC3"; + case NV_PFAULT_CLIENT_HUB_OFA0: + return "HUBCLIENT_OFA0"; + case NV_PFAULT_CLIENT_HUB_HSCE10: + return "HUBCLIENT_HSCE10"; + case NV_PFAULT_CLIENT_HUB_HSCE11: + return "HUBCLIENT_HSCE11"; + case NV_PFAULT_CLIENT_HUB_HSCE12: + return "HUBCLIENT_HSCE12"; + case NV_PFAULT_CLIENT_HUB_HSCE13: + return "HUBCLIENT_HSCE13"; + case NV_PFAULT_CLIENT_HUB_HSCE14: + return "HUBCLIENT_HSCE14"; + case NV_PFAULT_CLIENT_HUB_HSCE15: + return "HUBCLIENT_HSCE15"; + case NV_PFAULT_CLIENT_HUB_FE1: + return "HUBCLIENT_FE1"; + case NV_PFAULT_CLIENT_HUB_FE2: + return "HUBCLIENT_FE2"; + case NV_PFAULT_CLIENT_HUB_FE3: + return "HUBCLIENT_FE3"; + case NV_PFAULT_CLIENT_HUB_FE4: + return "HUBCLIENT_FE4"; + case NV_PFAULT_CLIENT_HUB_FE5: + return "HUBCLIENT_FE5"; + case NV_PFAULT_CLIENT_HUB_FE6: + return "HUBCLIENT_FE6"; + case NV_PFAULT_CLIENT_HUB_FE7: + return "HUBCLIENT_FE7"; + case NV_PFAULT_CLIENT_HUB_FECS1: + return "HUBCLIENT_FECS1"; + case NV_PFAULT_CLIENT_HUB_FECS2: + return "HUBCLIENT_FECS2"; + case NV_PFAULT_CLIENT_HUB_FECS3: + return "HUBCLIENT_FECS3"; + case NV_PFAULT_CLIENT_HUB_FECS4: + return "HUBCLIENT_FECS4"; + case NV_PFAULT_CLIENT_HUB_FECS5: + return "HUBCLIENT_FECS5"; + case NV_PFAULT_CLIENT_HUB_FECS6: + return "HUBCLIENT_FECS6"; + case NV_PFAULT_CLIENT_HUB_FECS7: + return "HUBCLIENT_FECS7"; + case NV_PFAULT_CLIENT_HUB_SKED1: + return "HUBCLIENT_SKED1"; + case NV_PFAULT_CLIENT_HUB_SKED2: + return "HUBCLIENT_SKED2"; + case NV_PFAULT_CLIENT_HUB_SKED3: + return "HUBCLIENT_SKED3"; + case NV_PFAULT_CLIENT_HUB_SKED4: + return "HUBCLIENT_SKED4"; + case NV_PFAULT_CLIENT_HUB_SKED5: + return "HUBCLIENT_SKED5"; + case NV_PFAULT_CLIENT_HUB_SKED6: + return "HUBCLIENT_SKED6"; + case NV_PFAULT_CLIENT_HUB_SKED7: + return "HUBCLIENT_SKED7"; + case NV_PFAULT_CLIENT_HUB_ESC: + return "HUBCLIENT_ESC"; + default: + return kfifoGetClientIdStringCheck_HAL(pGpu, pKernelFifo, pMmuExceptInfo->clientId); + } + } +} + + +/** + * @brief Converts a subid/clientid into a client string + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] clientId + + * @returns a string (always non-null) + */ +const char* +kfifoGetClientIdStringCheck_GA100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 clientId +) +{ + switch (clientId) + { + case NV_PFAULT_CLIENT_HUB_NVENC0: + return "HUBCLIENT_NVENC0"; + case NV_PFAULT_CLIENT_HUB_NVDEC4: + return "HUBCLIENT_NVDEC4"; + default: + return "UNRECOGNIZED_CLIENT"; + + } +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c index b53467d9e6..189386f014 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,10 +22,12 @@ */ #include "kernel/gpu/fifo/kernel_fifo.h" -#include "published/hopper/gh100/dev_vm.h" #include "kernel/gpu/mem_mgr/virt_mem_allocator.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "published/hopper/gh100/dev_fault.h" +#include "published/hopper/gh100/dev_vm.h" + /*! * Checks the USERD and GPFIFO/PushBuffer location attributes * to make sure that when USERD is in sysmem, GPFIFO or @@ -125,3 +127,431 @@ kfifoConstructUsermodeMemdescs_GH100 memdescDestroy(pKernelFifo->pBar1PrivVF); return status; } + +/*! + * @brief Converts an mmu engine id (NV_PFAULT_MMU_ENG_ID_*) into a string. + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] engineID NV_PFAULT_MMU_ENG_ID_* + * + * @returns a string (always non-null) + */ +const char* +kfifoPrintInternalEngine_GH100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 engineID +) +{ + NV_STATUS status = NV_OK; + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 pbdmaId; + NvU32 engTag; + + if (kfifoIsMmuFaultEngineIdPbdma(pGpu, pKernelFifo, engineID)) + { + NV_ASSERT_OR_RETURN(kfifoGetPbdmaIdFromMmuFaultId(pGpu, pKernelFifo, engineID, &pbdmaId) == NV_OK, "UNKNOWN"); + return kfifoPrintPbdmaId_HAL(pGpu, pKernelFifo, pbdmaId); + } + + if (kgmmuIsFaultEngineBar1_HAL(pKernelGmmu, engineID)) + { + return "BAR1"; + } + else if (kgmmuIsFaultEngineBar2_HAL(pKernelGmmu, engineID)) + { + return "BAR2"; + } + + switch (engineID) + { + case NV_PFAULT_MMU_ENG_ID_DISPLAY: + return "DISPLAY"; + case NV_PFAULT_MMU_ENG_ID_PERF: + return "PERF"; + case NV_PFAULT_MMU_ENG_ID_PWR_PMU: + return "PMU"; + case NV_PFAULT_MMU_ENG_ID_PTP: + return "PTP"; + case NV_PFAULT_MMU_ENG_ID_FLA: + return "FLA"; + case NV_PFAULT_MMU_ENG_ID_GSP: + return "GSP"; + case NV_PFAULT_MMU_ENG_ID_FSP: + return "FSP"; + default: + break; + } + + status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_MMU_FAULT_ID, + engineID, ENGINE_INFO_TYPE_ENG_DESC, &engTag); + if (status == NV_OK) + { + switch (engTag) + { + case ENG_GR(0): + return "GRAPHICS"; + default: + return kfifoGetEngineName_HAL(pKernelFifo, ENGINE_INFO_TYPE_ENG_DESC, engTag); + } + } + + return "UNKNOWN"; +} + +/** + * @brief Converts a subid/clientid into a client string. + * This common function may be used by subsequent chips + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] pMmuExceptData + + * @returns a string (always non-null) + */ +const char* +kfifoGetClientIdStringCommon_GH100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptInfo +) +{ + if (pMmuExceptInfo->bGpc) + { + switch (pMmuExceptInfo->clientId) + { + case NV_PFAULT_CLIENT_GPC_T1_0: + return "GPCCLIENT_T1_0"; + case NV_PFAULT_CLIENT_GPC_T1_1: + return "GPCCLIENT_T1_1"; + case NV_PFAULT_CLIENT_GPC_T1_2: + return "GPCCLIENT_T1_2"; + case NV_PFAULT_CLIENT_GPC_T1_3: + return "GPCCLIENT_T1_3"; + case NV_PFAULT_CLIENT_GPC_T1_4: + return "GPCCLIENT_T1_4"; + case NV_PFAULT_CLIENT_GPC_T1_5: + return "GPCCLIENT_T1_5"; + case NV_PFAULT_CLIENT_GPC_T1_6: + return "GPCCLIENT_T1_6"; + case NV_PFAULT_CLIENT_GPC_T1_7: + return "GPCCLIENT_T1_7"; + case NV_PFAULT_CLIENT_GPC_PE_0: + return "GPCCLIENT_PE_0"; + case NV_PFAULT_CLIENT_GPC_PE_1: + return "GPCCLIENT_PE_1"; + case NV_PFAULT_CLIENT_GPC_PE_2: + return "GPCCLIENT_PE_2"; + case NV_PFAULT_CLIENT_GPC_PE_3: + return "GPCCLIENT_PE_3"; + case NV_PFAULT_CLIENT_GPC_PE_4: + return "GPCCLIENT_PE_4"; + case NV_PFAULT_CLIENT_GPC_PE_5: + return "GPCCLIENT_PE_5"; + case NV_PFAULT_CLIENT_GPC_PE_6: + return "GPCCLIENT_PE_6"; + case NV_PFAULT_CLIENT_GPC_PE_7: + return "GPCCLIENT_PE_7"; + case NV_PFAULT_CLIENT_GPC_RAST: + return "GPCCLIENT_RAST"; + case NV_PFAULT_CLIENT_GPC_GCC: + return "GPCCLIENT_GCC"; + case NV_PFAULT_CLIENT_GPC_GPCCS: + return "GPCCLIENT_GPCCS"; + case NV_PFAULT_CLIENT_GPC_PROP_0: + return "GPCCLIENT_PROP_0"; + case NV_PFAULT_CLIENT_GPC_PROP_1: + return "GPCCLIENT_PROP_1"; + case NV_PFAULT_CLIENT_GPC_T1_8: + return "GPCCLIENT_T1_8"; + case NV_PFAULT_CLIENT_GPC_T1_9: + return "GPCCLIENT_T1_9"; + case NV_PFAULT_CLIENT_GPC_T1_10: + return "GPCCLIENT_T1_10"; + case NV_PFAULT_CLIENT_GPC_T1_11: + return "GPCCLIENT_T1_11"; + case NV_PFAULT_CLIENT_GPC_T1_12: + return "GPCCLIENT_T1_12"; + case NV_PFAULT_CLIENT_GPC_T1_13: + return "GPCCLIENT_T1_13"; + case NV_PFAULT_CLIENT_GPC_T1_14: + return "GPCCLIENT_T1_14"; + case NV_PFAULT_CLIENT_GPC_T1_15: + return "GPCCLIENT_T1_15"; + case NV_PFAULT_CLIENT_GPC_TPCCS_0: + return "GPCCLIENT_TPCCS_0"; + case NV_PFAULT_CLIENT_GPC_TPCCS_1: + return "GPCCLIENT_TPCCS_1"; + case NV_PFAULT_CLIENT_GPC_TPCCS_2: + return "GPCCLIENT_TPCCS_2"; + case NV_PFAULT_CLIENT_GPC_TPCCS_3: + return "GPCCLIENT_TPCCS_3"; + case NV_PFAULT_CLIENT_GPC_TPCCS_4: + return "GPCCLIENT_TPCCS_4"; + case NV_PFAULT_CLIENT_GPC_TPCCS_5: + return "GPCCLIENT_TPCCS_5"; + case NV_PFAULT_CLIENT_GPC_TPCCS_6: + return "GPCCLIENT_TPCCS_6"; + case NV_PFAULT_CLIENT_GPC_TPCCS_7: + return "GPCCLIENT_TPCCS_7"; + case NV_PFAULT_CLIENT_GPC_PE_8: + return "GPCCLIENT_PE_8"; + case NV_PFAULT_CLIENT_GPC_TPCCS_8: + return "GPCCLIENT_TPCCS_8"; + case NV_PFAULT_CLIENT_GPC_T1_16: + return "GPCCLIENT_T1_16"; + case NV_PFAULT_CLIENT_GPC_T1_17: + return "GPCCLIENT_T1_17"; + case NV_PFAULT_CLIENT_GPC_ROP_0: + return "GPCCLIENT_ROP_0"; + case NV_PFAULT_CLIENT_GPC_ROP_1: + return "GPCCLIENT_ROP_1"; + case NV_PFAULT_CLIENT_GPC_GPM: + return "GPCCLIENT_GPM"; + default: + return "UNRECOGNIZED_CLIENT"; + } + } + else + { + switch (pMmuExceptInfo->clientId) + { + case NV_PFAULT_CLIENT_HUB_VIP: + return "HUBCLIENT_VIP"; + case NV_PFAULT_CLIENT_HUB_CE0: + return "HUBCLIENT_CE0"; + case NV_PFAULT_CLIENT_HUB_CE1: + return "HUBCLIENT_CE1"; + case NV_PFAULT_CLIENT_HUB_CE2: + return "HUBCLIENT_CE2"; + case NV_PFAULT_CLIENT_HUB_CE3: + return "HUBCLIENT_CE3"; + case NV_PFAULT_CLIENT_HUB_DNISO: + return "HUBCLIENT_DNISO"; + case NV_PFAULT_CLIENT_HUB_FE: + return "HUBCLIENT_FE"; + case NV_PFAULT_CLIENT_HUB_FECS: + return "HUBCLIENT_FECS"; + case NV_PFAULT_CLIENT_HUB_HOST: + return "HUBCLIENT_HOST"; + case NV_PFAULT_CLIENT_HUB_HOST_CPU: + return "HUBCLIENT_HOST_CPU"; + case NV_PFAULT_CLIENT_HUB_HOST_CPU_NB: + return "HUBCLIENT_HOST_CPU_NB"; + case NV_PFAULT_CLIENT_HUB_ISO: + return "HUBCLIENT_ISO"; + case NV_PFAULT_CLIENT_HUB_MMU: + return "HUBCLIENT_MMU"; + case NV_PFAULT_CLIENT_HUB_NVDEC0: + return "HUBCLIENT_NVDEC0"; + case NV_PFAULT_CLIENT_HUB_NVENC1: + return "HUBCLIENT_NVENC1"; + case NV_PFAULT_CLIENT_HUB_NISO: + return "HUBCLIENT_NISO"; + case NV_PFAULT_CLIENT_HUB_P2P: + return "HUBCLIENT_P2P"; + case NV_PFAULT_CLIENT_HUB_PD: + return "HUBCLIENT_PD"; + case NV_PFAULT_CLIENT_HUB_PERF0: + return "HUBCLIENT_PERF"; + case NV_PFAULT_CLIENT_HUB_PMU: + return "HUBCLIENT_PMU"; + case NV_PFAULT_CLIENT_HUB_RASTERTWOD: + return "HUBCLIENT_RASTERTWOD"; + case NV_PFAULT_CLIENT_HUB_SCC: + return "HUBCLIENT_SCC"; + case NV_PFAULT_CLIENT_HUB_SCC_NB: + return "HUBCLIENT_SCC_NB"; + case NV_PFAULT_CLIENT_HUB_SEC: + return "HUBCLIENT_SEC"; + case NV_PFAULT_CLIENT_HUB_SSYNC: + return "HUBCLIENT_SSYNC"; + case NV_PFAULT_CLIENT_HUB_XV: + return "HUBCLIENT_XV"; + case NV_PFAULT_CLIENT_HUB_MMU_NB: + return "HUBCLIENT_MMU_NB"; + case NV_PFAULT_CLIENT_HUB_DFALCON: + return "HUBCLIENT_DFALCON"; + case NV_PFAULT_CLIENT_HUB_SKED: + return "HUBCLIENT_SKED"; + case NV_PFAULT_CLIENT_HUB_DONT_CARE: + return "HUBCLIENT_DONT_CARE"; + case NV_PFAULT_CLIENT_HUB_HSCE0: + return "HUBCLIENT_HSCE0"; + case NV_PFAULT_CLIENT_HUB_HSCE1: + return "HUBCLIENT_HSCE1"; + case NV_PFAULT_CLIENT_HUB_HSCE2: + return "HUBCLIENT_HSCE2"; + case NV_PFAULT_CLIENT_HUB_HSCE3: + return "HUBCLIENT_HSCE3"; + case NV_PFAULT_CLIENT_HUB_HSCE4: + return "HUBCLIENT_HSCE4"; + case NV_PFAULT_CLIENT_HUB_HSCE5: + return "HUBCLIENT_HSCE5"; + case NV_PFAULT_CLIENT_HUB_HSCE6: + return "HUBCLIENT_HSCE6"; + case NV_PFAULT_CLIENT_HUB_HSCE7: + return "HUBCLIENT_HSCE7"; + case NV_PFAULT_CLIENT_HUB_HSHUB: + return "HUBCLIENT_HSHUB"; + case NV_PFAULT_CLIENT_HUB_PTP_X0: + return "HUBCLIENT_PTP_X0"; + case NV_PFAULT_CLIENT_HUB_PTP_X1: + return "HUBCLIENT_PTP_X1"; + case NV_PFAULT_CLIENT_HUB_PTP_X2: + return "HUBCLIENT_PTP_X2"; + case NV_PFAULT_CLIENT_HUB_PTP_X3: + return "HUBCLIENT_PTP_X3"; + case NV_PFAULT_CLIENT_HUB_PTP_X4: + return "HUBCLIENT_PTP_X4"; + case NV_PFAULT_CLIENT_HUB_PTP_X5: + return "HUBCLIENT_PTP_X5"; + case NV_PFAULT_CLIENT_HUB_NVENC2: + return "HUBCLIENT_NVENC2"; + case NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0: + return "HUBCLIENT_VPR_SCRUBBER0"; + case NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1: + return "HUBCLIENT_VPR_SCRUBBER1"; + case NV_PFAULT_CLIENT_HUB_FBFALCON: + return "HUBCLIENT_FBFALCON"; + case NV_PFAULT_CLIENT_HUB_CE_SHIM: + return "HUBCLIENT_CE_SHIM"; + case NV_PFAULT_CLIENT_HUB_GSP: + return "HUBCLIENT_GSP"; + case NV_PFAULT_CLIENT_HUB_FSP: + return "HUBCLIENT_FSP"; + case NV_PFAULT_CLIENT_HUB_NVDEC1: + return "HUBCLIENT_NVDEC1"; + case NV_PFAULT_CLIENT_HUB_NVDEC2: + return "HUBCLIENT_NVDEC2"; + case NV_PFAULT_CLIENT_HUB_NVJPG0: + return "HUBCLIENT_NVJPG0"; + case NV_PFAULT_CLIENT_HUB_NVJPG1: + return "HUBCLIENT_NVJPG1"; + case NV_PFAULT_CLIENT_HUB_NVJPG2: + return "HUBCLIENT_NVJPG2"; + case NV_PFAULT_CLIENT_HUB_NVJPG3: + return "HUBCLIENT_NVJPG3"; + case NV_PFAULT_CLIENT_HUB_NVJPG4: + return "HUBCLIENT_NVJPG4"; + case NV_PFAULT_CLIENT_HUB_NVJPG5: + return "HUBCLIENT_NVJPG5"; + case NV_PFAULT_CLIENT_HUB_NVJPG6: + return "HUBCLIENT_NVJPG6"; + case NV_PFAULT_CLIENT_HUB_NVJPG7: + return "HUBCLIENT_NVJPG7"; + case NV_PFAULT_CLIENT_HUB_NVDEC3: + return "HUBCLIENT_NVDEC3"; + case NV_PFAULT_CLIENT_HUB_NVDEC4: + return "HUBCLIENT_NVDEC4"; + case NV_PFAULT_CLIENT_HUB_NVDEC5: + return "HUBCLIENT_NVDEC5"; + case NV_PFAULT_CLIENT_HUB_NVDEC6: + return "HUBCLIENT_NVDEC6"; + case NV_PFAULT_CLIENT_HUB_NVDEC7: + return "HUBCLIENT_NVDEC7"; + case NV_PFAULT_CLIENT_HUB_OFA0: + return "HUBCLIENT_OFA0"; + case NV_PFAULT_CLIENT_HUB_FE1: + return "HUBCLIENT_FE1"; + case NV_PFAULT_CLIENT_HUB_FE2: + return "HUBCLIENT_FE2"; + case NV_PFAULT_CLIENT_HUB_FE3: + return "HUBCLIENT_FE3"; + case NV_PFAULT_CLIENT_HUB_FE4: + return "HUBCLIENT_FE4"; + case NV_PFAULT_CLIENT_HUB_FE5: + return "HUBCLIENT_FE5"; + case NV_PFAULT_CLIENT_HUB_FE6: + return "HUBCLIENT_FE6"; + case NV_PFAULT_CLIENT_HUB_FE7: + return "HUBCLIENT_FE7"; + case NV_PFAULT_CLIENT_HUB_FECS1: + return "HUBCLIENT_FECS1"; + case NV_PFAULT_CLIENT_HUB_FECS2: + return "HUBCLIENT_FECS2"; + case NV_PFAULT_CLIENT_HUB_FECS3: + return "HUBCLIENT_FECS3"; + case NV_PFAULT_CLIENT_HUB_FECS4: + return "HUBCLIENT_FECS4"; + case NV_PFAULT_CLIENT_HUB_FECS5: + return "HUBCLIENT_FECS5"; + case NV_PFAULT_CLIENT_HUB_FECS6: + return "HUBCLIENT_FECS6"; + case NV_PFAULT_CLIENT_HUB_FECS7: + return "HUBCLIENT_FECS7"; + case NV_PFAULT_CLIENT_HUB_SKED1: + return "HUBCLIENT_SKED1"; + case NV_PFAULT_CLIENT_HUB_SKED2: + return "HUBCLIENT_SKED2"; + case NV_PFAULT_CLIENT_HUB_SKED3: + return "HUBCLIENT_SKED3"; + case NV_PFAULT_CLIENT_HUB_SKED4: + return "HUBCLIENT_SKED4"; + case NV_PFAULT_CLIENT_HUB_SKED5: + return "HUBCLIENT_SKED5"; + case NV_PFAULT_CLIENT_HUB_SKED6: + return "HUBCLIENT_SKED6"; + case NV_PFAULT_CLIENT_HUB_SKED7: + return "HUBCLIENT_SKED7"; + case NV_PFAULT_CLIENT_HUB_ESC: + return "HUBCLIENT_ESC"; + default: + return kfifoGetClientIdStringCheck_HAL(pGpu, pKernelFifo, pMmuExceptInfo->clientId); + } + } +} + +/** + * @brief Converts a subid/clientid into a client string + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] pMmuExceptData + * + * @returns a string (always non-null) + */ +const char* +kfifoGetClientIdString_GH100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionInfo +) +{ + if (pMmuExceptionInfo->bGpc) + { + return kfifoGetClientIdStringCommon_HAL(pGpu, pKernelFifo, pMmuExceptionInfo); + } + else + { + switch (pMmuExceptionInfo->clientId) + { + case NV_PFAULT_CLIENT_HUB_AFALCON: + return "HUBCLIENT_AFALCON"; + case NV_PFAULT_CLIENT_HUB_HSCE8: + return "HUBCLIENT_HSCE8"; + case NV_PFAULT_CLIENT_HUB_HSCE9: + return "HUBCLIENT_HSCE9"; + case NV_PFAULT_CLIENT_HUB_DWBIF: + return "HUBCLIENT_DWBIF"; + case NV_PFAULT_CLIENT_HUB_HSCE10: + return "HUBCLIENT_HSCE10"; + case NV_PFAULT_CLIENT_HUB_HSCE11: + return "HUBCLIENT_HSCE11"; + case NV_PFAULT_CLIENT_HUB_HSCE12: + return "HUBCLIENT_HSCE12"; + case NV_PFAULT_CLIENT_HUB_HSCE13: + return "HUBCLIENT_HSCE13"; + case NV_PFAULT_CLIENT_HUB_HSCE14: + return "HUBCLIENT_HSCE14"; + case NV_PFAULT_CLIENT_HUB_HSCE15: + return "HUBCLIENT_HSCE15"; + default: + return kfifoGetClientIdStringCommon_HAL(pGpu, pKernelFifo, pMmuExceptionInfo); + } + } +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c index 1c0983d5b1..86d4255191 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c @@ -28,6 +28,7 @@ #include "kernel/gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" +#include "platform/sli/sli.h" #include "class/cl906f.h" diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm200.c b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm200.c new file mode 100644 index 0000000000..f861c768db --- /dev/null +++ b/src/nvidia/src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm200.c @@ -0,0 +1,69 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "vgpu/rpc.h" + +#include "published/maxwell/gm200/dev_fifo.h" + +/** + * @brief + * + * @param pGpu + * @param pKernelFifo + * @param pbdmaCount + */ +NvU32 +kfifoGetNumPBDMAs_GM200 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo +) +{ + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + NvU32 numPbdmas; + + /*! + * If pEngineInfo is NULL, i.e. before fifoConstructEngineList, + * then read HW and return value, else return cached value + */ + if (pEngineInfo == NULL) + { + NV_ASSERT_OR_RETURN(!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu), 0); + + numPbdmas = GPU_REG_RD_DRF(pGpu, _PFIFO, _CFG0, _NUM_PBDMA); + + if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu)) + { + numPbdmas = 0; + } + + NV_PRINTF(LEVEL_INFO, "%d PBDMAs\n", numPbdmas); + } + else + { + numPbdmas = pEngineInfo->maxNumPbdmas; + } + + return numPbdmas; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/turing/kernel_fifo_tu102.c b/src/nvidia/src/kernel/gpu/fifo/arch/turing/kernel_fifo_tu102.c index da72304375..357cba6573 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/turing/kernel_fifo_tu102.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/turing/kernel_fifo_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,8 +28,10 @@ #include "gpu/gpu.h" #include "vgpu/vgpu_events.h" +#include "published/turing/tu102/dev_fault.h" #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/dev_ctrl.h" +#include "published/turing/tu102/hwproject.h" /*! * @brief Update the usermode doorbell register with work submit token to notify @@ -124,3 +126,348 @@ kfifoGenerateWorkSubmitToken_TU102 return NV_OK; } + +/** +* @brief Convert PBDMA ID to string +* @param[in] pGpu +* @param[in] pKernelFifo +* @param[in] pbdmaId +* +* @return cont string +*/ +const char* +kfifoPrintPbdmaId_TU102 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 pbdmaId +) +{ + NV_ASSERT_OR_RETURN(pbdmaId < NV_HOST_NUM_PBDMA, "UNKNOWN"); + static const char* pbdmaIdString[NV_HOST_NUM_PBDMA] = { "HOST0", + "HOST1", + "HOST2", + "HOST3", + "HOST4", + "HOST5", + "HOST6", + "HOST7", + "HOST8", + "HOST9", + "HOST10", + "HOST11", +#if NV_HOST_NUM_PBDMA > 12 +#error Uninitialized elements of static array. +#endif + }; + + return pbdmaIdString[pbdmaId]; +} + +/*! + * @brief Converts a mmu engine id (NV_PFAULT_MMU_ENG_ID_*) into a string. + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] engineID NV_PFAULT_MMU_ENG_ID_* + * + * @returns a string (always non-null) + */ +const char* +kfifoPrintInternalEngine_TU102 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 engineID +) +{ + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NvU32 pbdmaId; + + if (kfifoIsMmuFaultEngineIdPbdma(pGpu, pKernelFifo, engineID)) + { + NV_ASSERT_OR_RETURN(kfifoGetPbdmaIdFromMmuFaultId(pGpu, pKernelFifo, engineID, &pbdmaId) == NV_OK, "UNKNOWN"); + return kfifoPrintPbdmaId_HAL(pGpu, pKernelFifo, pbdmaId); + } + + if (kgmmuIsFaultEngineBar1_HAL(pKernelGmmu, engineID)) + { + return "BAR1"; + } + else if (kgmmuIsFaultEngineBar2_HAL(pKernelGmmu, engineID)) + { + return "BAR2"; + } + else + { + switch (engineID) + { + case NV_PFAULT_MMU_ENG_ID_DISPLAY: + return "DISPLAY"; + case NV_PFAULT_MMU_ENG_ID_IFB: + return "IFB"; + case NV_PFAULT_MMU_ENG_ID_SEC: + return "SEC"; + case NV_PFAULT_MMU_ENG_ID_PERF: + return "PERF"; + case NV_PFAULT_MMU_ENG_ID_NVDEC0: + return "NVDEC0"; + case NV_PFAULT_MMU_ENG_ID_NVDEC1: + return "NVDEC1"; + case NV_PFAULT_MMU_ENG_ID_NVDEC2: + return "NVDEC2"; + case NV_PFAULT_MMU_ENG_ID_CE0: + return "CE0"; + case NV_PFAULT_MMU_ENG_ID_CE1: + return "CE1"; + case NV_PFAULT_MMU_ENG_ID_CE2: + return "CE2"; + case NV_PFAULT_MMU_ENG_ID_CE3: + return "CE3"; + case NV_PFAULT_MMU_ENG_ID_CE4: + return "CE4"; + case NV_PFAULT_MMU_ENG_ID_CE5: + return "CE5"; + case NV_PFAULT_MMU_ENG_ID_CE6: + return "CE6"; + case NV_PFAULT_MMU_ENG_ID_CE7: + return "CE7"; + case NV_PFAULT_MMU_ENG_ID_CE8: + return "CE8"; + case NV_PFAULT_MMU_ENG_ID_PWR_PMU: + return "PMU"; + case NV_PFAULT_MMU_ENG_ID_PTP: + return "PTP"; + case NV_PFAULT_MMU_ENG_ID_NVENC0: + return "NVENC0"; + case NV_PFAULT_MMU_ENG_ID_NVENC1: + return "NVENC1"; + case NV_PFAULT_MMU_ENG_ID_PHYSICAL: + return "PHYSICAL"; + case NV_PFAULT_MMU_ENG_ID_NVJPG0: + return "NVJPG"; + default: + { + NV_STATUS status = NV_OK; + NvU32 engTag; + + status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_MMU_FAULT_ID, + engineID, ENGINE_INFO_TYPE_ENG_DESC, &engTag); + if ((status == NV_OK) && (IS_GR(engTag))) + { + return "GRAPHICS"; + } + + } + } + } + + return "UNKNOWN"; +} + +/*! + * @brief Converts a subid/clientid into a client string + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] pMmuExceptData + + * @returns a string (always non-null) + */ +const char* +kfifoGetClientIdString_TU102 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptInfo +) +{ + if (pMmuExceptInfo->bGpc) + { + switch (pMmuExceptInfo->clientId) + { + case NV_PFAULT_CLIENT_GPC_T1_0: + return "GPCCLIENT_T1_0"; + case NV_PFAULT_CLIENT_GPC_PE_0: + return "GPCCLIENT_PE_0"; + case NV_PFAULT_CLIENT_GPC_T1_1: + return "GPCCLIENT_T1_1"; + case NV_PFAULT_CLIENT_GPC_PE_1: + return "GPCCLIENT_PE_1"; + case NV_PFAULT_CLIENT_GPC_T1_2: + return "GPCCLIENT_T1_2"; + case NV_PFAULT_CLIENT_GPC_PE_2: + return "GPCCLIENT_PE_2"; + case NV_PFAULT_CLIENT_GPC_T1_3: + return "GPCCLIENT_T1_3"; + case NV_PFAULT_CLIENT_GPC_PE_3: + return "GPCCLIENT_PE_3"; + case NV_PFAULT_CLIENT_GPC_T1_4: + return "GPCCLIENT_T1_4"; + case NV_PFAULT_CLIENT_GPC_PE_4: + return "GPCCLIENT_PE_4"; + case NV_PFAULT_CLIENT_GPC_T1_5: + return "GPCCLIENT_T1_5"; + case NV_PFAULT_CLIENT_GPC_PE_5: + return "GPCCLIENT_PE_5"; + case NV_PFAULT_CLIENT_GPC_T1_6: + return "GPCCLIENT_T1_6"; + case NV_PFAULT_CLIENT_GPC_PE_6: + return "GPCCLIENT_PE_6"; + case NV_PFAULT_CLIENT_GPC_T1_7: + return "GPCCLIENT_T1_7"; + case NV_PFAULT_CLIENT_GPC_PE_7: + return "GPCCLIENT_PE_7"; + case NV_PFAULT_CLIENT_GPC_T1_8: + return "GPCCLIENT_T1_8"; + case NV_PFAULT_CLIENT_GPC_PE_8: + return "GPCCLIENT_PE_8"; + case NV_PFAULT_CLIENT_GPC_T1_9: + return "GPCCLIENT_T1_9"; + case NV_PFAULT_CLIENT_GPC_T1_10: + return "GPCCLIENT_T1_10"; + case NV_PFAULT_CLIENT_GPC_T1_11: + return "GPCCLIENT_T1_11"; + case NV_PFAULT_CLIENT_GPC_T1_12: + return "GPCCLIENT_T1_12"; + case NV_PFAULT_CLIENT_GPC_T1_13: + return "GPCCLIENT_T1_13"; + case NV_PFAULT_CLIENT_GPC_T1_14: + return "GPCCLIENT_T1_14"; + case NV_PFAULT_CLIENT_GPC_T1_15: + return "GPCCLIENT_T1_15"; + case NV_PFAULT_CLIENT_GPC_TPCCS_0: + return "GPCCLIENT_TPCCS_0"; + case NV_PFAULT_CLIENT_GPC_TPCCS_1: + return "GPCCLIENT_TPCCS_1"; + case NV_PFAULT_CLIENT_GPC_TPCCS_2: + return "GPCCLIENT_TPCCS_2"; + case NV_PFAULT_CLIENT_GPC_TPCCS_3: + return "GPCCLIENT_TPCCS_3"; + case NV_PFAULT_CLIENT_GPC_TPCCS_4: + return "GPCCLIENT_TPCCS_4"; + case NV_PFAULT_CLIENT_GPC_TPCCS_5: + return "GPCCLIENT_TPCCS_5"; + case NV_PFAULT_CLIENT_GPC_TPCCS_6: + return "GPCCLIENT_TPCCS_6"; + case NV_PFAULT_CLIENT_GPC_TPCCS_7: + return "GPCCLIENT_TPCCS_7"; + case NV_PFAULT_CLIENT_GPC_TPCCS_8: + return "GPCCLIENT_TPCCS_8"; + case NV_PFAULT_CLIENT_GPC_RAST: + return "GPCCLIENT_RAST"; + case NV_PFAULT_CLIENT_GPC_GCC: + return "GPCCLIENT_GCC"; + case NV_PFAULT_CLIENT_GPC_GPCCS: + return "GPCCLIENT_GPCCS"; + case NV_PFAULT_CLIENT_GPC_PROP_0: + return "GPCCLIENT_PROP_0"; + case NV_PFAULT_CLIENT_GPC_PROP_1: + return "GPCCLIENT_PROP_1"; + default: + return "UNRECOGNIZED_CLIENT"; + } + } + else + { + switch (pMmuExceptInfo->clientId) + { + case NV_PFAULT_CLIENT_HUB_CE0: + return "HUBCLIENT_CE0"; + case NV_PFAULT_CLIENT_HUB_HSCE0: + return "HUBCLIENT_HSCE0"; + case NV_PFAULT_CLIENT_HUB_CE1: + return "HUBCLIENT_CE1"; + case NV_PFAULT_CLIENT_HUB_HSCE1: + return "HUBCLIENT_HSCE1"; + case NV_PFAULT_CLIENT_HUB_CE2: + return "HUBCLIENT_CE2"; + case NV_PFAULT_CLIENT_HUB_HSCE2: + return "HUBCLIENT_HSCE2"; + case NV_PFAULT_CLIENT_HUB_HSCE3: + return "HUBCLIENT_HSCE3"; + case NV_PFAULT_CLIENT_HUB_HSCE4: + return "HUBCLIENT_HSCE4"; + case NV_PFAULT_CLIENT_HUB_HSCE5: + return "HUBCLIENT_HSCE5"; + case NV_PFAULT_CLIENT_HUB_HSCE6: + return "HUBCLIENT_HSCE6"; + case NV_PFAULT_CLIENT_HUB_HSCE7: + return "HUBCLIENT_HSCE7"; + case NV_PFAULT_CLIENT_HUB_HSCE8: + return "HUBCLIENT_HSCE8"; + case NV_PFAULT_CLIENT_HUB_HSCE9: + return "HUBCLIENT_HSCE9"; + case NV_PFAULT_CLIENT_HUB_DNISO: + return "HUBCLIENT_DNISO"; + case NV_PFAULT_CLIENT_HUB_FE: + return "HUBCLIENT_FE"; + case NV_PFAULT_CLIENT_HUB_FECS: + return "HUBCLIENT_FECS"; + case NV_PFAULT_CLIENT_HUB_HOST: + return "HUBCLIENT_HOST"; + case NV_PFAULT_CLIENT_HUB_HOST_CPU: + return "HUBCLIENT_HOST_CPU"; + case NV_PFAULT_CLIENT_HUB_HOST_CPU_NB: + return "HUBCLIENT_HOST_CPU_NB"; + case NV_PFAULT_CLIENT_HUB_ISO: + return "HUBCLIENT_ISO"; + case NV_PFAULT_CLIENT_HUB_MMU: + return "HUBCLIENT_MMU"; + case NV_PFAULT_CLIENT_HUB_NVDEC0: + return "HUBCLIENT_NVDEC0"; + case NV_PFAULT_CLIENT_HUB_NVDEC1: + return "HUBCLIENT_NVDEC1"; + case NV_PFAULT_CLIENT_HUB_NVDEC2: + return "HUBCLIENT_NVDEC2"; + case NV_PFAULT_CLIENT_HUB_NVENC0: + return "HUBCLIENT_NVENC0"; + case NV_PFAULT_CLIENT_HUB_NVENC1: + return "HUBCLIENT_NVENC1"; + case NV_PFAULT_CLIENT_HUB_NISO: + return "HUBCLIENT_NISO"; + case NV_PFAULT_CLIENT_HUB_P2P: + return "HUBCLIENT_P2P"; + case NV_PFAULT_CLIENT_HUB_PD: + return "HUBCLIENT_PD"; + case NV_PFAULT_CLIENT_HUB_PERF: + return "HUBCLIENT_PERF"; + case NV_PFAULT_CLIENT_HUB_PMU: + return "HUBCLIENT_PMU"; + case NV_PFAULT_CLIENT_HUB_RASTERTWOD: + return "HUBCLIENT_RASTERTWOD"; + case NV_PFAULT_CLIENT_HUB_SCC: + return "HUBCLIENT_SCC"; + case NV_PFAULT_CLIENT_HUB_SCC_NB: + return "HUBCLIENT_SCC_NB"; + case NV_PFAULT_CLIENT_HUB_SEC: + return "HUBCLIENT_SEC2"; + case NV_PFAULT_CLIENT_HUB_SSYNC: + return "HUBCLIENT_SSYNC"; + case NV_PFAULT_CLIENT_HUB_VIP: + return "HUBCLIENT_VIP"; + case NV_PFAULT_CLIENT_HUB_XV: + return "HUBCLIENT_XV"; + case NV_PFAULT_CLIENT_HUB_MMU_NB: + return "HUBCLIENT_MMU_NB"; + case NV_PFAULT_CLIENT_HUB_DFALCON: + return "HUBCLIENT_DFALCON"; + case NV_PFAULT_CLIENT_HUB_SKED: + return "HUBCLIENT_SKED"; + case NV_PFAULT_CLIENT_HUB_AFALCON: + return "HUBCLIENT_AFALCON"; + case NV_PFAULT_CLIENT_HUB_DONT_CARE: + return "HUBCLIENT_DONT_CARE"; + case NV_PFAULT_CLIENT_HUB_DWBIF: + return "HUBCLIENT_DWBIF"; + case NV_PFAULT_CLIENT_HUB_GSP: + return "HUBCLIENT_GSP"; + case NV_PFAULT_CLIENT_HUB_FBFALCON: + return "HUBCLIENT_FBFLCN"; + case NV_PFAULT_CLIENT_HUB_NVJPG0: + return "HUBCLIENT_NVJPG0"; + default: + return "UNRECOGNIZED_CLIENT"; + } + } +} diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c index f5e5473ae4..86616bc875 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_gv100.c @@ -24,6 +24,7 @@ #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/mem_mgr/mem.h" #include "kernel/gpu/mmu/kern_gmmu.h" +#include "platform/sli/sli.h" #include "published/volta/gv100/dev_pbdma.h" #include "rmapi/rs_utils.h" diff --git a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c index ba52fdd3df..5379783ef9 100644 --- a/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c +++ b/src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_fifo_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,6 +32,7 @@ #include "nvRmReg.h" +#include "published/volta/gv100/dev_fault.h" #include "published/volta/gv100/dev_ram.h" #include "ctrl/ctrlc36f.h" @@ -235,7 +236,7 @@ kfifoGetSubctxType_GV100 NV_ASSERT(pKernelChannel->subctxId != FIFO_PDB_IDX_BASE); KernelChannelGroup *pKernelChannelGroup = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup; - PEMEMBLOCK pBlock = pKernelChannelGroup->pSubctxIdHeap->eheapGetBlock( + EMEMBLOCK *pBlock = pKernelChannelGroup->pSubctxIdHeap->eheapGetBlock( pKernelChannelGroup->pSubctxIdHeap, pKernelChannel->subctxId, NV_FALSE); @@ -370,3 +371,43 @@ kfifoConstructUsermodeMemdescs_GV100 return NV_OK; } + +/** + * @brief Converts a MMU access type type (NV_PFAULT_ACCESS_TYPE_*) into a string. + * + * @param pGpu + * @param pKernelFifo + * @param faultId + * @returns a string (always non-null) + */ +const char* +kfifoGetFaultAccessTypeString_GV100 +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 accessType +) +{ + switch (accessType) + { + case NV_PFAULT_ACCESS_TYPE_VIRT_READ: + return "ACCESS_TYPE_VIRT_READ"; + case NV_PFAULT_ACCESS_TYPE_VIRT_WRITE: + return "ACCESS_TYPE_VIRT_WRITE"; + case NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG: + case NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK: + return "ACCESS_TYPE_VIRT_ATOMIC"; + case NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH: + return "ACCESS_TYPE_VIRT_PREFETCH"; + case NV_PFAULT_ACCESS_TYPE_PHYS_READ: + return "ACCESS_TYPE_PHYS_READ"; + case NV_PFAULT_ACCESS_TYPE_PHYS_WRITE: + return "ACCESS_TYPE_PHYS_WRITE"; + case NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC: + return "ACCESS_TYPE_PHYS_ATOMIC"; + case NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH: + return "ACCESS_TYPE_PHYS_PREFETCH"; + default: + return "UNRECOGNIZED_ACCESS_TYPE"; + } +} diff --git a/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c b/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c index 9dba975728..23db4fc2e8 100644 --- a/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c +++ b/src/nvidia/src/kernel/gpu/fifo/channel_descendant.c @@ -29,6 +29,7 @@ #include "kernel/gpu/fifo/channel_descendant.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "platform/sli/sli.h" NV_STATUS chandesConstruct_IMPL @@ -60,7 +61,7 @@ chandesConstruct_IMPL NV_ASSERT_OR_RETURN(pKernelChannel != NULL, NV_ERR_INVALID_OBJECT_PARENT); // Bad class creation can happen when GPU is in low power because class DB is invalid - NV_ASSERT(gpuIsGpuFullPower(pGpu)); + NV_ASSERT(IS_VIRTUAL(pGpu) || gpuIsGpuFullPower(pGpu)); NV_ASSERT(rmapiLockIsOwner() && rmGpuLockIsOwner()); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c index f2fe3ac93d..55d80525d2 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c @@ -21,8 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_CONTEXT_H_PRIVATE_ACCESS_ALLOWED #define NVOC_KERNEL_CHANNEL_H_PRIVATE_ACCESS_ALLOWED #include "kernel/gpu/fifo/kernel_channel.h" @@ -49,6 +47,7 @@ #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "objtmr.h" +#include "platform/sli/sli.h" #include "class/cl0090.h" // KERNEL_GRAPHICS_CONTEXT #include "class/cl906fsw.h" // GF100_GPFIFO @@ -1098,7 +1097,7 @@ kchannelDestruct_IMPL if ((kgrctxFromKernelChannel(pKernelChannel, &pKernelGraphicsContext) == NV_OK) && kgrctxIsValid(pGpu, pKernelGraphicsContext, pKernelChannel)) { - shrkgrctxDetach(pGpu, pKernelGraphicsContext->pShared, pKernelGraphicsContext, pKernelChannel); + shrkgrctxDetach(pGpu, kgrctxGetShared(pGpu, pKernelGraphicsContext), pKernelGraphicsContext, pKernelChannel); } } @@ -1131,6 +1130,7 @@ kchannelDestruct_IMPL } kchannelFreeHwID_HAL(pGpu, pKernelChannel); + kchannelFreeMmuExceptionInfo(pKernelChannel); NV_ASSERT(pKernelChannel->refCount == 1); } @@ -1745,7 +1745,6 @@ kchannelCtrlCmdStopChannel_IMPL if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { - NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, RES_GET_HANDLE(pKernelChannel), @@ -2829,6 +2828,42 @@ kchannelCtrlCmdGetClassEngineid_IMPL return status; } +NV_STATUS +kchannelCtrlCmdResetIsolatedChannel_IMPL +( + KernelChannel *pKernelChannel, + NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS *pResetIsolatedChannelParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + + // This ctrl sets bIsRcPending in the KernelChannel object. Because Kernel-RM is + // the source of truth on this, it's important that this ctrl is called from CPU-RM + NV_ASSERT_OR_RETURN(!RMCFG_FEATURE_PLATFORM_GSP, NV_ERR_INVALID_OPERATION); + + // Call internal RMCTRL on physical-RM, kchannelFwdToInternalCtrl() is not + // used because no conversion from KernelChannel to Channel is required + status = pRmApi->Control(pRmApi, + resservGetTlsCallContext()->pControlParams->hClient, + RES_GET_HANDLE(pKernelChannel), + NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL, + pResetIsolatedChannelParams, + sizeof(NV506F_CTRL_CMD_INTERNAL_RESET_ISOLATED_CHANNEL_PARAMS)); + + // If physical RM successfully reset the isolated channel, + // mark that the RC is no longer pending + if (status == NV_OK) + pKernelChannel->bIsRcPending[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] = NV_FALSE; + + return status; +} + +// This ctrl accesses bIsRcPending in the KernelChannel object to populate +// information required by physical RM. Because Kernel-RM is the source of +// truth on this, it's important that this ctrl be called originally from CPU-RM. NV_STATUS kchannelCtrlCmdResetChannel_IMPL ( @@ -2848,6 +2883,10 @@ kchannelCtrlCmdResetChannel_IMPL return NV_ERR_INVALID_PARAMETER; } + // Send physical RM info on if an RC is pending + pResetChannelParams->bIsRcPending = + pKernelChannel->bIsRcPending[gpumgrGetSubDeviceInstanceFromGpu(pGpu)]; + // // All real hardware management is done in the host. // Do an RPC to the host to do the hardware update and return. @@ -2934,7 +2973,6 @@ kchannelCtrlCmdGpFifoSchedule_IMPL // if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { - NV_RM_RPC_CONTROL(pGpu, RES_GET_CLIENT_HANDLE(pKernelChannel), RES_GET_HANDLE(pKernelChannel), @@ -4418,6 +4456,36 @@ kchannelCtrlCmdGetKmb_KERNEL portMemCopy((void*)(&pGetKmbParams->kmb), sizeof(CC_KMB), (const void*)(&pKernelChannel->clientKmb), sizeof(CC_KMB)); + if (pKernelChannel->pEncStatsBufMemDesc == NULL) + { + RsClient *pRsClient = NULL; + RsResourceRef *pResourceRef = NULL; + Memory *pMemory = NULL; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelChannel); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pKernelChannel); + + NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); + if (clientGetResourceRef(pRsClient, pGetKmbParams->hMemory, &pResourceRef) != NV_OK) + { + // TODO: Make this fatal once all cients move to using hMemory + return NV_OK; + } + pMemory = dynamicCast(pResourceRef->pResource, Memory); + pMemDesc = pMemory->pMemDesc; + NV_ASSERT_OR_RETURN(pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + pKernelChannel->pEncStatsBufMemDesc = pMemDesc; + + // Reset statistics to init the buffer + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + TRANSFER_SURFACE surf = {0}; + surf.pMemDesc = pMemory->pMemDesc; + surf.offset = 0; + CC_CRYPTOBUNDLE_STATS *pEncStats = (CC_CRYPTOBUNDLE_STATS*)memmgrMemBeginTransfer(pMemoryManager, &surf, + sizeof(CC_CRYPTOBUNDLE_STATS), TRANSFER_FLAGS_SHADOW_ALLOC); + portMemSet(pEncStats, 0, sizeof(CC_CRYPTOBUNDLE_STATS)); + memmgrMemEndTransfer(pMemoryManager, &surf, sizeof(CC_CRYPTOBUNDLE_STATS), 0); + } return NV_OK; return NV_ERR_NOT_SUPPORTED; } @@ -4530,3 +4598,122 @@ kchannelCtrlRotateSecureChannelIv_PHYSICAL return NV_OK; } + +/*! + * Fill in per-channel MMU exception data and allocate memory for this data if + * necessary + * + * @param[inout] pKernelChannel + * @param[in] pMmuExceptionData MMU exception data to be copied + */ +void +kchannelFillMmuExceptionInfo_IMPL +( + KernelChannel *pKernelChannel, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData +) +{ + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN_VOID(pKernelChannel); + + if (pKernelChannel->pMmuExceptionData == NULL) + { + pKernelChannel->pMmuExceptionData = portMemAllocNonPaged(sizeof(FIFO_MMU_EXCEPTION_DATA)); + if (pKernelChannel->pMmuExceptionData == NULL) + status = NV_ERR_NO_MEMORY; + } + + if (status == NV_OK) + { + portMemCopy(pKernelChannel->pMmuExceptionData, + sizeof(FIFO_MMU_EXCEPTION_DATA), + pMmuExceptionData, + sizeof(FIFO_MMU_EXCEPTION_DATA)); + } +} + +/*! + * Free per-channel MMU exception data if it exists + * + * @param[inout] pKernelChannel + */ +void +kchannelFreeMmuExceptionInfo_IMPL +( + KernelChannel *pKernelChannel +) +{ + portMemFree(pKernelChannel->pMmuExceptionData); + pKernelChannel->pMmuExceptionData = NULL; +} + +/*! + * Check if channel is disabled for key rotation + */ +NvBool kchannelIsDisabledForKeyRotation +( + OBJGPU *pGpu, + KernelChannel *pKernelChannel +) +{ + return !!(pKernelChannel->swState[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] & + KERNEL_CHANNEL_SW_STATE_DISABLED_FOR_KEY_ROTATION); +} + +/*! + * Mark channel disabled for key rotation + */ +void kchannelDisableForKeyRotation +( + OBJGPU *pGpu, + KernelChannel *pKernelChannel, + NvBool bDisable +) +{ + if (bDisable) + { + pKernelChannel->swState[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] |= + KERNEL_CHANNEL_SW_STATE_DISABLED_FOR_KEY_ROTATION; + } + else + { + pKernelChannel->swState[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] &= + ~KERNEL_CHANNEL_SW_STATE_DISABLED_FOR_KEY_ROTATION; + } +} + +/*! + * Check if channel needs to be enabled after key rotation + */ +NvBool kchannelIsEnableAfterKeyRotation +( + OBJGPU *pGpu, + KernelChannel *pKernelChannel +) +{ + return !!(pKernelChannel->swState[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] & + KERNEL_CHANNEL_SW_STATE_ENABLE_AFTER_KEY_ROTATION); +} + +/*! + * Mark channel to be re-enabled after key rotation completes + */ +void kchannelEnableAfterKeyRotation +( + OBJGPU *pGpu, + KernelChannel *pKernelChannel, + NvBool bEnable +) +{ + if (bEnable) + { + pKernelChannel->swState[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] |= + KERNEL_CHANNEL_SW_STATE_ENABLE_AFTER_KEY_ROTATION; + } + else + { + pKernelChannel->swState[gpumgrGetSubDeviceInstanceFromGpu(pGpu)] &= + ~KERNEL_CHANNEL_SW_STATE_ENABLE_AFTER_KEY_ROTATION; + } +} diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c index 3cbdd2a347..9f91cbcbab 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group.c @@ -23,6 +23,7 @@ #include "kernel/gpu/fifo/kernel_channel_group.h" #include "kernel/gpu/fifo/kernel_fifo.h" +#include "platform/sli/sli.h" #include "ctrl/ctrla06c.h" // NVA06C_CTRL_INTERLEAVE_LEVEL_* @@ -419,18 +420,21 @@ kchangrpDestroy_IMPL kfifoChannelListDestroy(pGpu, pKernelFifo, pKernelChannelGroup->pChanList); pKernelChannelGroup->pChanList= NULL; - // Remove this from the that we maintain in OBJFIFO - pKernelChannelGroupTemp = mapFind(pChidMgr->pChanGrpTree, pKernelChannelGroup->grpID); - if (pKernelChannelGroupTemp == NULL) + if (pChidMgr != NULL) { - NV_PRINTF(LEVEL_ERROR, "Could not find channel group %d\n", - pKernelChannelGroup->grpID); - return NV_ERR_OBJECT_NOT_FOUND; - } - mapRemove(pChidMgr->pChanGrpTree, pKernelChannelGroupTemp); + // Remove this from the that we maintain in OBJFIFO + pKernelChannelGroupTemp = mapFind(pChidMgr->pChanGrpTree, pKernelChannelGroup->grpID); + if (pKernelChannelGroupTemp == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Could not find channel group %d\n", + pKernelChannelGroup->grpID); + return NV_ERR_OBJECT_NOT_FOUND; + } + mapRemove(pChidMgr->pChanGrpTree, pKernelChannelGroupTemp); - // Release the free grpID - kfifoChidMgrFreeChannelGroupHwID(pGpu, pKernelFifo, pChidMgr, pKernelChannelGroup->grpID); + // Release the free grpID + kfifoChidMgrFreeChannelGroupHwID(pGpu, pKernelFifo, pChidMgr, pKernelChannelGroup->grpID); + } // // Free the method buffer if applicable diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c index ebf2b98fcc..37f275b466 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c @@ -28,6 +28,8 @@ #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/falcon/kernel_falcon.h" +#include "kernel/gpu/rc/kernel_rc.h" +#include "platform/sli/sli.h" #include "kernel/gpu/conf_compute/conf_compute.h" @@ -36,6 +38,7 @@ #include "libraries/utils/nvprintf.h" #include "gpu/gpu.h" +#include "gpu/device/device.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "gpu/mem_mgr/vaspace_api.h" #include "vgpu/rpc.h" @@ -242,13 +245,28 @@ kchangrpapiConstruct_IMPL if (!RMCFG_FEATURE_PLATFORM_GSP) { - NV_ASSERT_OK_OR_GOTO(rmStatus, - ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pCtxBufPool), - failed); + NvHandle hRcWatchdog; - NV_ASSERT_OK_OR_GOTO(rmStatus, - ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pChannelBufPool), - failed); + // + // WAR for 4217716 - Force allocations made on behalf of watchdog client to + // RM reserved heap. This avoids a constant memory allocation from appearing + // due to the ctxBufPool reservation out of PMA. + // + rmStatus = krcWatchdogGetClientHandle(GPU_GET_KERNEL_RC(pGpu), &hRcWatchdog); + if ((rmStatus != NV_OK) || (pParams->hClient != hRcWatchdog)) + { + NV_ASSERT_OK_OR_GOTO(rmStatus, + ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pCtxBufPool), + failed); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + ctxBufPoolInit(pGpu, pHeap, &pKernelChannelGroup->pChannelBufPool), + failed); + } + else + { + NV_PRINTF(LEVEL_INFO, "Skipping ctxBufPoolInit for RC watchdog\n"); + } } NV_ASSERT_OK_OR_GOTO(rmStatus, @@ -532,11 +550,18 @@ kchangrpapiConstruct_IMPL if (bLockAcquired) rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); - if (bReserveMem) + if ((rmStatus == NV_OK) && bReserveMem) { // GPU lock should not be held when reserving memory for ctxBufPool - NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + NV_CHECK_OK(rmStatus, LEVEL_ERROR, ctxBufPoolReserve(pGpu, pKernelChannelGroup->pCtxBufPool, bufInfoList, bufCount)); + if (rmStatus != NV_OK) + { + // Acquire the lock again for the cleanup path + NV_ASSERT_OK_OR_RETURN(rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_FIFO)); + bLockAcquired = NV_TRUE; + goto failed; + } } portMemFree(bufInfoList); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c b/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c index ae9f7bffdb..a95f88ceee 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_ctxshare.c @@ -33,6 +33,7 @@ #include "core/locks.h" #include "gpu/mem_mgr/vaspace_api.h" #include "rmapi/rs_utils.h" +#include "platform/sli/sli.h" #define SUBCTXID_EHEAP_OWNER NvU32_BUILD('n','v','r','m') @@ -369,7 +370,7 @@ kctxshareInitCommon_IMPL NvU32 heapFlag = 0; NvU64 offset = 0; NvU64 size = 1; - PEMEMBLOCK pBlock; + EMEMBLOCK *pBlock; KernelChannelGroup *pKernelChannelGroup; NV_ASSERT_OR_RETURN(pKernelChannelGroupApi != NULL, NV_ERR_INVALID_STATE); @@ -543,7 +544,7 @@ kctxshareDestroyCommon_IMPL continue; } - PEMEMBLOCK pBlock = pKernelChannelGroup->pSubctxIdHeap->eheapGetBlock( + EMEMBLOCK *pBlock = pKernelChannelGroup->pSubctxIdHeap->eheapGetBlock( pKernelChannelGroup->pSubctxIdHeap, i, NV_FALSE); @@ -597,7 +598,7 @@ kctxshareDestruct_IMPL // if(pKernelCtxShare->pKernelChannelGroup != NULL) { - PEMEMBLOCK pBlock = + EMEMBLOCK *pBlock = pKernelCtxShare->pKernelChannelGroup->pSubctxIdHeap->eheapGetBlock( pKernelCtxShare->pKernelChannelGroup->pSubctxIdHeap, pKernelCtxShare->subctxId, diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c index bbdb7089c7..27a169de02 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c @@ -29,6 +29,7 @@ #include "virtualization/kernel_vgpu_mgr.h" #include "rmapi/rs_utils.h" #include "rmapi/client.h" +#include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "kernel/core/locks.h" @@ -330,6 +331,15 @@ _kfifoChidMgrAllocChidHeaps RM_PAGE_SIZE / userdBar1Size); // Disable USERD allocation isolation for guest if disabled from vmioplugin + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if (pVSI != NULL) + { + subProcessIsolation = pVSI->subProcessIsolation; + } + } + else { // In this case subProcessIsolation is always 0 if (IS_GSP_CLIENT(pGpu)) @@ -823,11 +833,11 @@ kfifoChidMgrAllocChid_IMPL if (ChID < numChannels) { - PEMEMBLOCK pFifoDataBlock = pChidMgr->pFifoDataHeap->eheapGetBlock( + EMEMBLOCK *pFifoDataBlock = pChidMgr->pFifoDataHeap->eheapGetBlock( pChidMgr->pFifoDataHeap, ChID, NV_FALSE); - PEMEMBLOCK pIsolationIdBlock = pChidMgr->pGlobalChIDHeap->eheapGetBlock( + EMEMBLOCK *pIsolationIdBlock = pChidMgr->pGlobalChIDHeap->eheapGetBlock( pChidMgr->pGlobalChIDHeap, ChID, NV_FALSE); @@ -868,7 +878,7 @@ kfifoChidMgrRetainChid_IMPL ) { NvU32 gfid; - PEMEMBLOCK pFifoDataBlock = NULL; + EMEMBLOCK *pFifoDataBlock = NULL; NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); @@ -876,7 +886,7 @@ kfifoChidMgrRetainChid_IMPL { NV_ASSERT_OR_RETURN(pChidMgr->ppVirtualChIDHeap[gfid] != NULL, NV_ERR_INVALID_STATE); - PEMEMBLOCK pVirtChIdBlock = pChidMgr->ppVirtualChIDHeap[gfid]->eheapGetBlock( + EMEMBLOCK *pVirtChIdBlock = pChidMgr->ppVirtualChIDHeap[gfid]->eheapGetBlock( pChidMgr->ppVirtualChIDHeap[gfid], ChID, NV_FALSE); @@ -887,7 +897,7 @@ kfifoChidMgrRetainChid_IMPL else { NV_ASSERT_OR_RETURN(pChidMgr->pGlobalChIDHeap != NULL, NV_ERR_INVALID_STATE); - PEMEMBLOCK pChIdBlock = pChidMgr->pGlobalChIDHeap->eheapGetBlock( + EMEMBLOCK *pChIdBlock = pChidMgr->pGlobalChIDHeap->eheapGetBlock( pChidMgr->pGlobalChIDHeap, ChID, NV_FALSE); @@ -1015,6 +1025,7 @@ kfifoChidMgrReserveSystemChids_IMPL NvU32 flags, NvU32 gfid, NvU32 *pChidOffset, + NvU64 offset, NvU32 *pChannelCount, Device *pMigDevice, NvU32 engineFifoListNumEntries, @@ -1023,9 +1034,8 @@ kfifoChidMgrReserveSystemChids_IMPL { NV_STATUS status = NV_OK; NvU64 chSize; - NvU64 offset = 0; PFIFO_ISOLATIONID pIsolationID = NULL; - PEMEMBLOCK pIsolationIdBlock; + EMEMBLOCK *pIsolationIdBlock; NvU32 userdBar1Size; if (IS_VIRTUAL(pGpu)) @@ -1239,6 +1249,23 @@ kfifoRunlistQueryNumChannels_KERNEL NvU32 numChannels = 0; NvU32 status; + // For vgpu, read numChannels from VGPU_STATIC_INFO + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI; + pVSI = GPU_GET_STATIC_INFO(pGpu); + + if (pVSI) + { + numChannels = pVSI->vgpuStaticProperties.channelCount; + } + else + { + DBG_BREAKPOINT(); + return 0; + } + } + // Do internal control call and set numChannels if (IS_GSP_CLIENT(pGpu)) { @@ -2755,6 +2782,16 @@ void kfifoGetDeviceCaps_IMPL return; } +/** + * @brief Get the start offset of USERD BAR1 map region + */ +NvU64 +kfifoGetUserdBar1MapStartOffset_VF(OBJGPU *pGpu, KernelFifo *pKernelFifo) +{ + + return 0; +} + /*! * @brief Add handlers for scheduling enable and/or disable. * @@ -3397,7 +3434,7 @@ kfifoGetGuestEngineLookupTable_IMPL // To trap NV2080_ENGINE_TYPE expansions. // Please update the table guestEngineLookupTable if this assertion is triggered. // - ct_assert(NV2080_ENGINE_TYPE_LAST == 0x0000003f); + ct_assert(NV2080_ENGINE_TYPE_LAST == 0x00000040); *pEngLookupTblSize = NV_ARRAY_ELEMENTS(guestEngineLookupTable); @@ -3435,3 +3472,96 @@ kfifoGetMaxSecureChannels_KERNEL return NV_OK; } + +/** + * @brief Checking if the engine ID belongs to a PBDMA or not + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] engineId + * + * @return TRUE if engine ID belongs to a PBDMA + */ +NvBool +kfifoIsMmuFaultEngineIdPbdma_IMPL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 engineId +) +{ + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + + NV_ASSERT_OR_RETURN(pEngineInfo != NULL, NV_FALSE); + return bitVectorTest(&pEngineInfo->validEngineIdsForPbdmas, engineId); +} + +/** + * @brief Function to get PBDMA ID from the given MMU falut ID + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] mmuFaultId + * @param[out] pPbdmaId + */ +NV_STATUS +kfifoGetPbdmaIdFromMmuFaultId_IMPL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 mmuFaultId, + NvU32 *pPbdmaId +) +{ + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + NvU32 pbdmaFaultIdStart; + + NV_ASSERT_OR_RETURN(pEngineInfo != NULL, NV_ERR_INVALID_STATE); + + // + // HW guarantees mmu fault engine ids used for PBDMAs will be assigned in sequential order + // "PBDMA of MMU_ENGINE_ID = MMU_ENGINE_ID - BASE_PBDMA_FAULT_ID" relation holds for all assignments + // This is helping SW to derive the pbdma id using base pbdma fault id and mmu fault engine id + // + pbdmaFaultIdStart = bitVectorCountTrailingZeros(&pEngineInfo->validEngineIdsForPbdmas); + *pPbdmaId = mmuFaultId - pbdmaFaultIdStart; + + return NV_OK; +} + +/*! + * @brief Function to get RM engine type from the given pbdma falut id + * + * @param[in] pGpu + * @param[in] pKernelFifo + * @param[in] pbdmaFaultId + * @param[out] pRmEngineType + * + * @returns NV_OK when engine type found for given pbdma falut id + */ +NV_STATUS +kfifoGetEngineTypeFromPbdmaFaultId_IMPL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 pbdmaFaultId, + RM_ENGINE_TYPE *pRmEngineType +) +{ + const ENGINE_INFO *pEngineInfo = kfifoGetEngineInfo(pKernelFifo); + NvU32 i, j; + + for (i = 0; i < pEngineInfo->engineInfoListSize; i++) + { + for (j = 0; j < pEngineInfo->engineInfoList[i].numPbdmas; j++) + { + if (pbdmaFaultId == pEngineInfo->engineInfoList[i].pbdmaFaultIds[j]) + { + *pRmEngineType = pEngineInfo->engineInfoList[i].engineData[ENGINE_INFO_TYPE_RM_ENGINE_TYPE]; + return NV_OK; + } + } + } + + *pRmEngineType = RM_ENGINE_TYPE_NULL; + return NV_ERR_OBJECT_NOT_FOUND; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c index 3b4bb52b4a..aac84ba214 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_ctrl.c @@ -31,6 +31,7 @@ #include "kernel/virtualization/hypervisor/hypervisor.h" #include "kernel/core/locks.h" #include "lib/base_utils.h" +#include "platform/sli/sli.h" #include "vgpu/rpc.h" #include "vgpu/vgpu_events.h" @@ -763,3 +764,74 @@ subdeviceCtrlCmdFifoDisableChannels_IMPL return status; } + +/** + * @brief Disables and preempts the given channels and marks + * them disabled for key rotation. Conditionally also marks + * them for re-enablement. + */ +NV_STATUS +subdeviceCtrlCmdFifoDisableChannelsForKeyRotation_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS *pDisableChannelParams +) +{ + NV_STATUS status = NV_OK; + NV_STATUS tmpStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + NvU32 i; + + NV_CHECK_OR_RETURN(LEVEL_INFO, + pDisableChannelParams->numChannels <= NV_ARRAY_ELEMENTS(pDisableChannelParams->hChannelList), + NV_ERR_INVALID_ARGUMENT); + ct_assert(NV_ARRAY_ELEMENTS(pDisableChannelParams->hClientList) == \ + NV_ARRAY_ELEMENTS(pDisableChannelParams->hChannelList)); + + // Send RPC to handle message on Host-RM + if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) + { + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + } + // Send internal control call to actually disable channels and preempt channels + else + { + status = NV_ERR_NOT_SUPPORTED; + NV_ASSERT_OR_RETURN(status == NV_OK, status); + } + + // Loop through all the channels and mark them disabled + for (i = 0; i < pDisableChannelParams->numChannels; i++) + { + RsClient *pClient = NULL; + KernelChannel *pKernelChannel = NULL; + tmpStatus = serverGetClientUnderLock(&g_resServ, + pDisableChannelParams->hClientList[i], &pClient); + if (tmpStatus != NV_OK) + { + status = tmpStatus; + NV_PRINTF(LEVEL_ERROR, "Failed to get client with hClient = 0x%x status = 0x%x\n", pDisableChannelParams->hClientList[i], status); + continue; + } + tmpStatus = CliGetKernelChannel(pClient, + pDisableChannelParams->hChannelList[i], &pKernelChannel); + if (tmpStatus != NV_OK) + { + status = tmpStatus; + NV_PRINTF(LEVEL_ERROR, "Failed to get channel with hclient = 0x%x hChannel = 0x%x status = 0x%x\n", + pDisableChannelParams->hClientList[i], pDisableChannelParams->hChannelList[i], status); + continue; + } + kchannelDisableForKeyRotation(pGpu, pKernelChannel, NV_TRUE); + kchannelEnableAfterKeyRotation(pGpu, pKernelChannel, pDisableChannelParams->bEnableAfterKeyRotation); + } + return status; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c index bb97aaf36e..42a9ead0e0 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,6 +26,7 @@ #include "kernel/gpu/fifo/kernel_sched_mgr.h" #include "kernel/gpu/rc/kernel_rc.h" +#include "vgpu/rpc.h" #include "vgpu/vgpu_events.h" #include "nvRmReg.h" @@ -68,6 +69,56 @@ kfifoConstructEngine_IMPL return NV_OK; } +NV_STATUS +kfifoStateLoad_IMPL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 flags +) +{ + if (IS_VIRTUAL_WITH_FULL_SRIOV(pGpu) && (flags & GPU_STATE_FLAGS_PRESERVING)) + { + NV_STATUS rmStatus = NV_OK; + + NV_RM_RPC_DISABLE_CHANNELS(pGpu, NV_FALSE, rmStatus); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to enable all channels failed, status 0x%x\n", rmStatus); + DBG_BREAKPOINT(); + return rmStatus; + } + } + + return NV_OK; +} + +NV_STATUS +kfifoStateUnload_IMPL +( + OBJGPU *pGpu, + KernelFifo *pKernelFifo, + NvU32 flags +) +{ + if (IS_VIRTUAL_WITH_FULL_SRIOV(pGpu) && (flags & GPU_STATE_FLAGS_PRESERVING)) + { + NV_STATUS rmStatus = NV_OK; + + NV_RM_RPC_DISABLE_CHANNELS(pGpu, NV_TRUE, rmStatus); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to disable all channels failed, status 0x%x\n", rmStatus); + DBG_BREAKPOINT(); + return rmStatus; + } + } + + return NV_OK; +} + static void _kfifoPreConstructRegistryOverrides ( @@ -135,6 +186,14 @@ kfifoStateInitLocked_IMPL // only on host RM for SR-IOV capable SKUs (See gpuInitRegistryOverrides). // On MODS, the tests use the regkey to turn on SR-IOV // + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + pKernelFifo->bUsePerRunlistChram = pVSI->bPerRunlistChannelRamEnabled; + NV_PRINTF(LEVEL_INFO, "%s per runlist channel RAM in guest RM\n", + pVSI->bPerRunlistChannelRamEnabled ? "Enabling" : "Disabling"); + } + else { if (gpuIsSriovEnabled(pGpu)) { diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c b/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c index 38189cd8ea..3a94851ec6 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c @@ -24,7 +24,6 @@ #include "rmapi/rmapi.h" #include "core/locks.h" #include "gpu/device/device.h" -#include "gpu/subdevice/subdevice.h" #include "vgpu/rpc.h" #include "kernel/gpu/fifo/kernel_fifo.h" diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c b/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c index 99f3cd6c81..44fcc14ff3 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_sched_mgr.c @@ -54,15 +54,62 @@ _kschedmgrGetSchedulerPolicy ) { NvU32 schedPolicy = SCHED_POLICY_DEFAULT; + NvU32 regkey = 0; + + if (hypervisorIsVgxHyper() || (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu))) + { + // Disable OBJSCHED_SW_ENABLE when GPU is older than Pascal. + // This is true for WDDM and vGPU scheduling + if (!IsPASCALorBetter(pGpu)) + { + schedPolicy = SCHED_POLICY_DEFAULT; + } + else if (IS_MIG_ENABLED(pGpu)) + { + schedPolicy = SCHED_POLICY_DEFAULT; + portDbgPrintf("NVRM: Software Scheduler is not supported in MIG mode\n"); + } + // Check the PVMRL regkey + else if (osReadRegistryDword(pGpu, NV_REG_STR_RM_PVMRL, ®key) == NV_OK && + FLD_TEST_REF(NV_REG_STR_RM_PVMRL_ENABLE, _YES, regkey) ) + { + NvU32 configSchedPolicy = REF_VAL(NV_REG_STR_RM_PVMRL_SCHED_POLICY, regkey); + + switch (configSchedPolicy) + { + case NV_REG_STR_RM_PVMRL_SCHED_POLICY_VGPU_EQUAL_SHARE: + schedPolicy = SCHED_POLICY_VGPU_EQUAL_SHARE; + break; + case NV_REG_STR_RM_PVMRL_SCHED_POLICY_VGPU_FIXED_SHARE: + schedPolicy = SCHED_POLICY_VGPU_FIXED_SHARE; + break; + default: + NV_PRINTF(LEVEL_INFO, + "Invalid scheduling policy %d specified by regkey.\n", + configSchedPolicy); + break; + } + } + else + { + schedPolicy = SCHED_POLICY_BEST_EFFORT; + } + } *pSchedPolicy = schedPolicy; switch (schedPolicy) { + case SCHED_POLICY_BEST_EFFORT: + return MAKE_NV_PRINTF_STR("BEST_EFFORT"); + case SCHED_POLICY_VGPU_EQUAL_SHARE: + return MAKE_NV_PRINTF_STR("EQUAL_SHARE"); + case SCHED_POLICY_VGPU_FIXED_SHARE: + return MAKE_NV_PRINTF_STR("FIXED_SHARE"); case SCHED_POLICY_DEFAULT: default: // For baremetal and PT - return "NONE"; + return MAKE_NV_PRINTF_STR("NONE"); } } @@ -74,6 +121,25 @@ void kschedmgrSetConfigPolicyFromUser_IMPL ) { NvU32 schedSwPolicyLocal = SCHED_POLICY_DEFAULT; + switch (schedSwPolicy) + { + case NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_BEST_EFFORT: + schedSwPolicyLocal = SCHED_POLICY_BEST_EFFORT; + break; + case NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_EQUAL_SHARE: + schedSwPolicyLocal = SCHED_POLICY_VGPU_EQUAL_SHARE; + break; + case NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_FIXED_SHARE: + schedSwPolicyLocal = SCHED_POLICY_VGPU_FIXED_SHARE; + break; + case NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_OTHER: + schedSwPolicyLocal = SCHED_POLICY_DEFAULT; + break; + default: + NV_PRINTF(LEVEL_WARNING, "Unknown vGPU scheduler policy %u\n", schedSwPolicy); + schedSwPolicyLocal = SCHED_POLICY_DEFAULT; + break; + } pKernelSchedMgr->configSchedPolicy = schedSwPolicyLocal; pKernelSchedMgr->bIsSchedSwEnabled = (schedSwPolicyLocal != SCHED_POLICY_DEFAULT); } diff --git a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c index 3d4a8d85f3..9562a77290 100644 --- a/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c @@ -36,6 +36,8 @@ #include "published/hopper/gh100/dev_fsp_pri.h" #include "published/hopper/gh100/dev_fsp_addendum.h" #include "fsp/fsp_nvdm_format.h" +#include "published/hopper/gh100/dev_bus.h" +#include "published/hopper/gh100/dev_bus_addendum.h" #include "published/hopper/gh100/dev_gc6_island_addendum.h" #include "published/hopper/gh100/dev_falcon_v4.h" #include "published/hopper/gh100/dev_gsp.h" @@ -43,6 +45,7 @@ #include "published/hopper/gh100/dev_therm_addendum.h" #include "os/os.h" #include "nvRmReg.h" +#include "nverror.h" #include "gpu/conf_compute/conf_compute.h" @@ -624,9 +627,13 @@ kfspWaitForSecureBoot_GH100 status = gpuCheckTimeout(pGpu, &timeout); if (status == NV_ERR_TIMEOUT) { - NV_PRINTF(LEVEL_ERROR, - "Timout while polling for FSP boot complete I2CS_SCRATCH : %x\n", - GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE)); + NV_ERROR_LOG((void*) pGpu, GPU_INIT_ERROR, "Timeout while polling for FSP boot complete, " + "0x%x, 0x%x, 0x%x, 0x%x, 0x%x", + GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(2)), + GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(3))); break; } } @@ -672,7 +679,6 @@ kfspGetGspUcodeArchive { if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) { - NV_PRINTF(LEVEL_ERROR, "GSP-RM image for CC not found\n"); return NULL; } else @@ -1006,34 +1012,32 @@ kfspGspFmcIsEnforced_GH100 } /*! - * @brief Send GSP-FMC and FRTS info to FSP + * @brief Check if okay to send GSP-FMC and FRTS info to FSP * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelFsp KernelFsp pointer * - * @return NV_OK, or error if failed + * @return NV_OK + * Okay to send boot commands + * @return NV_WARN_NOTHING_TO_DO + * No need to send boot commands + * @return NV_ERR_NOT_SUPPORTED + * Should not send boot commands */ -NV_STATUS -kfspSendBootCommands_GH100 +static NV_STATUS +kfspSafeToSendBootCommands ( OBJGPU *pGpu, KernelFsp *pKernelFsp ) { - NV_STATUS status = NV_OK; - NV_STATUS statusBoot = NV_OK; - NvU32 frtsSize = 0; - NVDM_PAYLOAD_COT *pCotPayload = NULL; - NvP64 pVaKernel = NULL; - NvP64 pPrivKernel = NULL; - if (!IS_EMULATION(pGpu) && !IS_SILICON(pGpu)) { // // FSP managment partition is only enabled when secure boot is enabled // on silicon and certain emulation configs // - return NV_OK; + return NV_WARN_NOTHING_TO_DO; } if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_IS_MISSING)) @@ -1045,7 +1049,7 @@ kfspSendBootCommands_GH100 } NV_PRINTF(LEVEL_WARNING, "Secure boot is disabled due to missing FSP.\n"); - return NV_OK; + return NV_WARN_NOTHING_TO_DO; } if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK)) @@ -1054,15 +1058,6 @@ kfspSendBootCommands_GH100 return NV_ERR_NOT_SUPPORTED; } - // Confirm FSP secure boot partition is done - statusBoot = kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); - - if (statusBoot != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "FSP secure boot partition timed out.\n"); - return statusBoot; - } - // Enforce GSP-FMC can only be booted by FSP on silicon. if (IS_SILICON(pGpu) && kfspGspFmcIsEnforced_HAL(pGpu, pKernelFsp) && @@ -1078,18 +1073,64 @@ kfspSendBootCommands_GH100 { NV_PRINTF(LEVEL_WARNING, "Chain-of-trust is disabled via regkey\n"); pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK, NV_TRUE); - return NV_OK; + return NV_WARN_NOTHING_TO_DO; + } + + return NV_OK; +} + +/*! + * @brief Prepare GSP-FMC and FRTS info to send to FSP + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_OK + * GSP-FMC and FRTS info ready to send + * @return NV_WARN_NOTHING_TO_DO + * Skipped preparing boot commands + * @return Other error + * Error preparing GSP-FMC and FRTS info + */ +NV_STATUS +kfspPrepareBootCommands_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_STATUS status = NV_OK; + NV_STATUS statusBoot; + + NvU32 frtsSize = 0; + NvP64 pVaKernel = NULL; + NvP64 pPrivKernel = NULL; + + status = kfspSafeToSendBootCommands(pGpu, pKernelFsp); + if (status != NV_OK) + { + return status; + } + + statusBoot = kfspWaitForSecureBoot_HAL(pGpu, pKernelFsp); + + // Confirm FSP secure boot partition is done + if (statusBoot != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "FSP secure boot partition timed out.\n"); + status = statusBoot; + goto failed; } - pCotPayload = portMemAllocNonPaged(sizeof(NVDM_PAYLOAD_COT)); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pCotPayload != NULL, NV_ERR_NO_MEMORY); - portMemSet(pCotPayload, 0, sizeof(NVDM_PAYLOAD_COT)); + pKernelFsp->pCotPayload = portMemAllocNonPaged(sizeof(NVDM_PAYLOAD_COT)); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelFsp->pCotPayload != NULL, NV_ERR_NO_MEMORY); + portMemSet(pKernelFsp->pCotPayload, 0, sizeof(NVDM_PAYLOAD_COT)); frtsSize = NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K << 12; NV_ASSERT(frtsSize != 0); - pCotPayload->version = 1; - pCotPayload->size = sizeof(NVDM_PAYLOAD_COT); + pKernelFsp->pCotPayload->version = 1; + pKernelFsp->pCotPayload->size = sizeof(NVDM_PAYLOAD_COT); // Set up sysmem for FRTS copy if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM)) @@ -1119,8 +1160,12 @@ kfspSendBootCommands_GH100 memdescSetKernelMapping(pKernelFsp->pSysmemFrtsMemdesc, pVaKernel); memdescSetKernelMappingPriv(pKernelFsp->pSysmemFrtsMemdesc, pPrivKernel); - pCotPayload->frtsSysmemOffset = memdescGetPhysAddr(pKernelFsp->pSysmemFrtsMemdesc, AT_GPU, 0); - pCotPayload->frtsSysmemSize = frtsSize; + pKernelFsp->pCotPayload->frtsSysmemOffset = memdescGetPhysAddr(pKernelFsp->pSysmemFrtsMemdesc, AT_GPU, 0); + pKernelFsp->pCotPayload->frtsSysmemSize = frtsSize; + + NV_ASSERT_OK_OR_GOTO(status, + kfspFrtsSysmemLocationProgram_HAL(pGpu, pKernelFsp), + failed); } // Set up vidmem for FRTS copy @@ -1140,17 +1185,17 @@ kfspSendBootCommands_GH100 NvU32 FRTS_OFFSET_FROM_END = memmgrGetFBEndReserveSizeEstimate_HAL(pGpu, GPU_GET_MEMORY_MANAGER(pGpu)); - pCotPayload->frtsVidmemOffset = FRTS_OFFSET_FROM_END; - pCotPayload->frtsVidmemSize = frtsSize; + pKernelFsp->pCotPayload->frtsVidmemOffset = FRTS_OFFSET_FROM_END; + pKernelFsp->pCotPayload->frtsVidmemSize = frtsSize; } - pCotPayload->gspFmcSysmemOffset = (NvU64)-1; - pCotPayload->gspBootArgsSysmemOffset = (NvU64)-1; + pKernelFsp->pCotPayload->gspFmcSysmemOffset = (NvU64)-1; + pKernelFsp->pCotPayload->gspBootArgsSysmemOffset = (NvU64)-1; // Set up GSP-FMC for FSP to boot GSP if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) { - status = kfspSetupGspImages(pGpu, pKernelFsp, pCotPayload); + status = kfspSetupGspImages(pGpu, pKernelFsp, pKernelFsp->pCotPayload); if (status!= NV_OK) { NV_PRINTF(LEVEL_ERROR, "Ucode image preparation failed!\n"); @@ -1158,20 +1203,53 @@ kfspSendBootCommands_GH100 } } + return NV_OK; + +failed: + NV_PRINTF(LEVEL_ERROR, "Preparing FSP boot cmds failed. RM cannot boot.\n"); + + kfspCleanupBootState(pGpu, pKernelFsp); - status = kfspSendAndReadMessage(pGpu, pKernelFsp, (NvU8 *)pCotPayload, + return status; +} +/*! + * @brief Send GSP-FMC and FRTS info to FSP + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_OK + * GSP-FMC and FRTS info sent to FSP + * @return NV_WARN_NOTHING_TO_DO + * Skipped sending boot commands + * @return Other error + * Error sending GSP-FMC and FRTS info to FSP + */ +NV_STATUS +kfspSendBootCommands_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pKernelFsp->pCotPayload != NULL, NV_ERR_INVALID_STATE); + + status = kfspSendAndReadMessage(pGpu, pKernelFsp, (NvU8 *)pKernelFsp->pCotPayload, sizeof(NVDM_PAYLOAD_COT), NVDM_TYPE_COT, NULL, 0); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Sent following content to FSP: \n"); NV_PRINTF(LEVEL_ERROR, "version=0x%x, size=0x%x, gspFmcSysmemOffset=0x%llx\n", - pCotPayload->version, pCotPayload->size, pCotPayload->gspFmcSysmemOffset); + pKernelFsp->pCotPayload->version, pKernelFsp->pCotPayload->size, + pKernelFsp->pCotPayload->gspFmcSysmemOffset); NV_PRINTF(LEVEL_ERROR, "frtsSysmemOffset=0x%llx, frtsSysmemSize=0x%x\n", - pCotPayload->frtsSysmemOffset, pCotPayload->frtsSysmemSize); + pKernelFsp->pCotPayload->frtsSysmemOffset, pKernelFsp->pCotPayload->frtsSysmemSize); NV_PRINTF(LEVEL_ERROR, "frtsVidmemOffset=0x%llx, frtsVidmemSize=0x%x\n", - pCotPayload->frtsVidmemOffset, pCotPayload->frtsVidmemSize); + pKernelFsp->pCotPayload->frtsVidmemOffset, pKernelFsp->pCotPayload->frtsVidmemSize); NV_PRINTF(LEVEL_ERROR, "gspBootArgsSysmemOffset=0x%llx\n", - pCotPayload->gspBootArgsSysmemOffset); + pKernelFsp->pCotPayload->gspBootArgsSysmemOffset); goto failed; } @@ -1189,21 +1267,44 @@ kfspSendBootCommands_GH100 // Set property to indicate we only support secure boot at this point pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK, NV_TRUE); - pKernelFsp->pCotPayload = pCotPayload; return NV_OK; failed: NV_PRINTF(LEVEL_ERROR, "FSP boot cmds failed. RM cannot boot.\n"); kfspDumpDebugState_HAL(pGpu, pKernelFsp); - memdescDestroy(pKernelFsp->pSysmemFrtsMemdesc); - pKernelFsp->pSysmemFrtsMemdesc = NULL; - - portMemFree(pCotPayload); + kfspCleanupBootState(pGpu, pKernelFsp); return status; } +/*! + * @brief Prepare and send GSP-FMC and FRTS info to FSP + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelFsp KernelFsp pointer + * + * @return NV_OK + * GSP-FMC and FRTS info sent to FSP or determined okay to skip sending info + * @return Other error + * Error preparing or sending GSP-FMC and FRTS info to FSP + */ +NV_STATUS +kfspPrepareAndSendBootCommands_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_STATUS status; + status = kfspPrepareBootCommands_GH100(pGpu, pKernelFsp); + if (status != NV_OK) + { + return (status == NV_WARN_NOTHING_TO_DO) ? NV_OK : status; + } + return kfspSendBootCommands_GH100(pGpu, pKernelFsp); +} + NV_STATUS kfspErrorCode2NvStatusMap_GH100 ( @@ -1254,3 +1355,56 @@ kfspRequiresBug3957833WAR_GH100 const NvU32 fspUcodeVersion = GPU_REG_RD_DRF(pGpu, _GFW, _FSP_UCODE_VERSION, _FULL); return fspUcodeVersion < FSP_BUG_3957833_FIX_VERSION; } + +NV_STATUS +kfspFrtsSysmemLocationProgram_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + NV_STATUS status; + RmPhysAddr frtsSysmemAddr; + + NV_ASSERT_TRUE_OR_GOTO(status, + (pKernelFsp->pSysmemFrtsMemdesc != NULL), + NV_ERR_INVALID_STATE, + kfspFrtsSysmemLocationProgram_GH100_exit); + + frtsSysmemAddr = memdescGetPhysAddr( + pKernelFsp->pSysmemFrtsMemdesc, AT_GPU, 0U); + + GPU_REG_WR32( + pGpu, NV_PBUS_SW_FRTS_INSECURE_ADDR_LO32, NvU64_LO32(frtsSysmemAddr)); + GPU_REG_WR32( + pGpu, NV_PBUS_SW_FRTS_INSECURE_ADDR_HI32, NvU64_HI32(frtsSysmemAddr)); + GPU_REG_WR32( + pGpu, + NV_PBUS_SW_FRTS_INSECURE_CONFIG, + FLD_SET_DRF( + _PBUS, _SW_FRTS_INSECURE_CONFIG, _MEDIA_TYPE, _SYSMEM, + REF_NUM( + NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K, + (memdescGetSize(pKernelFsp->pSysmemFrtsMemdesc) >> + NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_SHIFT)))); + +kfspFrtsSysmemLocationProgram_GH100_exit: + return status; +} + +void +kfspFrtsSysmemLocationClear_GH100 +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + GPU_REG_WR32( + pGpu, + NV_PBUS_SW_FRTS_INSECURE_CONFIG, + REF_DEF(NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K, _INVALID)); + GPU_REG_WR32( + pGpu, NV_PBUS_SW_FRTS_INSECURE_ADDR_HI32, 0U); + GPU_REG_WR32( + pGpu, NV_PBUS_SW_FRTS_INSECURE_ADDR_LO32, 0U); +} diff --git a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c index 38b7f2370e..5258cef0b9 100644 --- a/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c +++ b/src/nvidia/src/kernel/gpu/fsp/kern_fsp.c @@ -136,15 +136,13 @@ kfspStateInitUnlocked_IMPL } /*! - * @brief Destroy FSP state + * @brief Clean up objects used when sending GSP-FMC and FRTS info to FSP * * @param[in] pGpu GPU object pointer * @param[in] pKernelFsp FSP object pointer - * - * @return 'NV_OK' if the FSP state was successfully destroyed */ void -kfspStateDestroy_IMPL +kfspCleanupBootState_IMPL ( OBJGPU *pGpu, KernelFsp *pKernelFsp @@ -155,6 +153,7 @@ kfspStateDestroy_IMPL if (pKernelFsp->pSysmemFrtsMemdesc != NULL) { + kfspFrtsSysmemLocationClear_HAL(pGpu, pKernelFsp); memdescUnmap(pKernelFsp->pSysmemFrtsMemdesc, NV_TRUE, 0, memdescGetKernelMapping(pKernelFsp->pSysmemFrtsMemdesc), memdescGetKernelMappingPriv(pKernelFsp->pSysmemFrtsMemdesc)); @@ -163,13 +162,6 @@ kfspStateDestroy_IMPL pKernelFsp->pSysmemFrtsMemdesc = NULL; } - if (pKernelFsp->pVidmemFrtsMemdesc != NULL) - { - memdescFree(pKernelFsp->pVidmemFrtsMemdesc); - memdescDestroy(pKernelFsp->pVidmemFrtsMemdesc); - pKernelFsp->pVidmemFrtsMemdesc = NULL; - } - if (pKernelFsp->pGspFmcMemdesc != NULL) { memdescFree(pKernelFsp->pGspFmcMemdesc); @@ -186,13 +178,34 @@ kfspStateDestroy_IMPL } +/*! + * @brief Destroy FSP state + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelFsp FSP object pointer + */ +void +kfspStateDestroy_IMPL +( + OBJGPU *pGpu, + KernelFsp *pKernelFsp +) +{ + kfspCleanupBootState(pGpu, pKernelFsp); + + if (pKernelFsp->pVidmemFrtsMemdesc != NULL) + { + memdescFree(pKernelFsp->pVidmemFrtsMemdesc); + memdescDestroy(pKernelFsp->pVidmemFrtsMemdesc); + pKernelFsp->pVidmemFrtsMemdesc = NULL; + } +} + /*! * @brief Override default behaviour of reset * * @param[in] pGpu GPU object pointer * @param[in] pKernelFsp FSP object pointer - * - * @return */ void kfspSecureReset_IMPL diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 0121aac252..7676c3f6e1 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -44,10 +44,14 @@ #include "diagnostics/journal.h" #include "rmapi/rs_utils.h" #include "rmapi/rmapi_utils.h" +#include "platform/sli/sli.h" #include "core/hal_mgr.h" #include "vgpu/rpc.h" #include "jt.h" +#include "ctrl/ctrl402c.h" // NV402C_CTRL_NUM_I2C_PORTS +#include "ctrl/ctrl5070/ctrl5070chnc.h" // NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE + #include "gpu/gpu_fabric_probe.h" #include "vgpu/vgpu_events.h" @@ -70,6 +74,8 @@ #include "nvop.h" +#include "nvdevid.h" // for NV_PCI_DEVID_DEVICE + #include "virtualization/hypervisor/hypervisor.h" #include "kernel/virtualization/kernel_vgpu_mgr.h" @@ -96,8 +102,6 @@ typedef struct GPUCHILDTYPE GPUCHILDTYPE; NvU32, WriteCount, sizeof(NvU32)); \ } -// Public interface functions - static NV_STATUS gpuRemoveMissingEngines(OBJGPU *); // local static function @@ -194,6 +198,15 @@ _gpuDetectNvswitchSupport pGpu->fabricProbeSlowdownThreshold = 1; pGpu->nvswitchSupport = NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED; + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = gpuGetStaticInfo(pGpu); + + pGpu->nvswitchSupport = pVSI->p2pCaps.bGpuSupportsFabricProbe ? + NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_SUPPORTED : + NV2080_CTRL_PMGR_MODULE_INFO_NVSWITCH_NOT_SUPPORTED; + } + else { NvU32 status = NV_OK; RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); @@ -210,15 +223,16 @@ _gpuDetectNvswitchSupport { pGpu->moduleId = moduleInfoParams.moduleId; pGpu->nvswitchSupport = moduleInfoParams.nvswitchSupport; - if (GPU_IS_NVSWITCH_DETECTED(pGpu)) - { - pGpu->fabricProbeRetryDelay = GPU_FABRIC_PROBE_DEFAULT_DELAY; - pGpu->fabricProbeSlowdownThreshold = - GPU_FABRIC_PROBE_DEFAULT_PROBE_SLOWDOWN_THRESHOLD; - } } } + if (GPU_IS_NVSWITCH_DETECTED(pGpu)) + { + pGpu->fabricProbeRetryDelay = GPU_FABRIC_PROBE_DEFAULT_DELAY; + pGpu->fabricProbeSlowdownThreshold = + GPU_FABRIC_PROBE_DEFAULT_PROBE_SLOWDOWN_THRESHOLD; + } + if (val != 0) { pGpu->fabricProbeSlowdownThreshold = \ @@ -263,6 +277,10 @@ NvU32 gpuGenerate32BitId(NvU32 domain, NvU8 bus, NvU8 device) // Include only the lower 16-bits to match the old gpuId scheme id |= (domain & 0xffff) << 16; + if ((domain >> 16) != 0) { + NV_ASSERT(hypervisorIsType(OS_HYPERVISOR_HYPERV)); + } + return id; } @@ -329,6 +347,7 @@ gpuPostConstruct_IMPL ) { NV_STATUS rmStatus; + NvU32 config = 0; gpumgrAddDeviceInstanceToGpus(NVBIT(pGpu->gpuInstance)); @@ -340,6 +359,19 @@ gpuPostConstruct_IMPL return rmStatus; } + + config = GPU_REG_RD32(pGpu, NV_PMC_BOOT_1); + if (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, config)) + { + pGpu->bIsVirtualWithSriov = NV_TRUE; + } + else + { + pGpu->bIsVirtualWithSriov = NV_FALSE; + } + + pGpu->sriovState.virtualRegPhysOffset = gpuGetVirtRegPhysOffset_HAL(pGpu); + gpuInitChipInfo(pGpu); // @@ -475,6 +507,39 @@ gpuPostConstruct_IMPL gpuDetermineSelfHostedMode_HAL(pGpu); } + if ( + IS_VIRTUAL(pGpu)) + { + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + +#if defined(NV_UNIX) + // For self hosted hopper, VF BAR2 is absent. So disable bUsePhysicalBar2InitPagetable + // in case of self hosted SRIOV guest + if (pAttachArg->instLength == 0) + pKernelBus->bUsePhysicalBar2InitPagetable = NV_FALSE; +#endif + + if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus)) + { + // setup BAR2 in physical mode + NV_ASSERT_OK_OR_RETURN(kbusBar2BootStrapInPhysicalMode_HAL(pGpu, pKernelBus)); + } + } + + rmStatus = vgpuCreateObject(pGpu); + if (rmStatus != NV_OK) + { + if (NV_ERR_LIB_RM_VERSION_MISMATCH == rmStatus) + { + nvErrorLog_va(pGpu, VGPU_START_ERROR, + "Guest driver is incompatible with host driver"); + } + return rmStatus; + } + } + gpuGetHwDefaults(pGpu); // Handle per-device core logic registry settings @@ -502,18 +567,44 @@ gpuPostConstruct_IMPL NV_STATUS gpuConstruct_IMPL ( OBJGPU *pGpu, - NvU32 gpuInstance + NvU32 gpuInstance, + NvU32 gpuId, + NvUuid *pGpuUuid ) { pGpu->gpuInstance = gpuInstance; + pGpu->gpuId = pGpu->boardId = gpuId; // boardId may be updated later pGpu->gspRmInitialized = NV_FALSE; + if (pGpuUuid != NULL) + { + portMemCopy(&pGpu->gpuUuid.uuid[0], sizeof(pGpu->gpuUuid.uuid), + &pGpuUuid->uuid[0], sizeof(pGpuUuid->uuid)); + pGpu->gpuUuid.isInitialized = NV_TRUE; + } + // allocate OS-specific GPU extension area osInitOSHwInfo(pGpu); + // Initialize NvFBC session count and list. + listInit(&(pGpu->nvfbcSessionList), portMemAllocatorGetGlobalNonPaged()); + + // Initialize NvENC session count and list. + listInit(&(pGpu->nvencSessionList), portMemAllocatorGetGlobalNonPaged()); + multimapInit(&pGpu->videoEventBufferBindingsUid, portMemAllocatorGetGlobalNonPaged()); + // Initialize the i2c port via which external devices will be connected. + pGpu->i2cPortForExtdev = NV402C_CTRL_NUM_I2C_PORTS; + + // Assume no SLI peer connection until later + for (NvU32 i = 0; i < DR_PINSET_COUNT; ++i) + { + pGpu->peer[i].pGpu = NULL; + pGpu->peer[i].pinset = NV5070_CTRL_CMD_GET_PINSET_PEER_PEER_PINSET_NONE; + } + return gpuConstructPhysical(pGpu); } @@ -630,7 +721,7 @@ static NV_STATUS _gpuRmApiControl callCtx.pControlParams = &rmCtrlParams; callCtx.pLockInfo = rmCtrlParams.pLockInfo; - resservSwapTlsCallContext(&oldCtx, &callCtx); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&oldCtx, &callCtx)); if (pEntry->paramSize == 0) { @@ -641,7 +732,7 @@ static NV_STATUS _gpuRmApiControl status = ((NV_STATUS(*)(void*,void*))pEntry->pFunc)(pGpu->pCachedSubdevice, pParams); } - resservRestoreTlsCallContext(oldCtx); + NV_ASSERT_OK(resservRestoreTlsCallContext(oldCtx)); } else { @@ -782,7 +873,7 @@ static NV_STATUS _gpuAllocateInternalObjects if (IS_GSP_CLIENT(pGpu)) { - if (IsT234DorBetter(pGpu)) + if (IS_DCE_CLIENT(pGpu)) { // // NOTE: We add +1 to the client base because DCE-RM will also @@ -1420,6 +1511,21 @@ gpuDestruct_IMPL gpushareddataDestroy(pGpu); } + // + // If device instance is unassigned, we haven't initialized far enough to + // do any accounting with it + // + if (gpuGetDeviceInstance(pGpu) != NV_MAX_DEVICES) + { + rmapiReportLeakedDevices(gpuGetGpuMask(pGpu)); + } + + if ( + IS_VIRTUAL(pGpu)) + { + vgpuDestructObject(pGpu); + } + // Free children in reverse order from construction for (typeNum = GPU_NUM_CHILD_TYPES - 1; typeNum >= 0; typeNum--) { @@ -1440,15 +1546,6 @@ gpuDestruct_IMPL } } - // - // If device instance is unassigned, we haven't initialized far enough to - // do any accounting with it - // - if (gpuGetDeviceInstance(pGpu) != NV_MAX_DEVICES) - { - rmapiReportLeakedDevices(gpuGetGpuMask(pGpu)); - } - _gpuFreeEngineOrderList(pGpu); portMemFree(pGpu->pUserRegisterAccessMap); @@ -1616,54 +1713,6 @@ gpuGetGpuMask_IMPL } } -static NV_STATUS gspSupportsEngine(OBJGPU *pGpu, ENGDESCRIPTOR engdesc, NvBool *supports) -{ - RM_ENGINE_TYPE clientEngineId = 0; - - if (!IS_GSP_CLIENT(pGpu)) - return NV_WARN_NOTHING_TO_DO; - - if (gpuXlateEngDescToClientEngineId(pGpu, engdesc, &clientEngineId) != NV_OK) - { - NV_PRINTF(LEVEL_INFO, "Failed to xlate engdesc 0x%x\n", engdesc); - return NV_WARN_NOTHING_TO_DO; - } - - if (pGpu->gspSupportedEngines == NULL) - { - pGpu->gspSupportedEngines = portMemAllocNonPaged(sizeof(*pGpu->gspSupportedEngines)); - NV_ASSERT_OR_RETURN(pGpu->gspSupportedEngines != NULL, NV_ERR_NO_MEMORY); - - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - - NV_STATUS status = pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_GPU_GET_ENGINES_V2, - pGpu->gspSupportedEngines, - sizeof(*pGpu->gspSupportedEngines)); - - if (status != NV_OK) - { - portMemFree(pGpu->gspSupportedEngines); - return status; - } - } - - NvU32 i; - for (i = 0; i < pGpu->gspSupportedEngines->engineCount; i++) - { - if (gpuGetRmEngineType(pGpu->gspSupportedEngines->engineList[i]) == clientEngineId) - { - *supports = NV_TRUE; - return NV_OK; - } - } - - *supports = NV_FALSE; - return NV_OK; -} - /*! * The engine removal protocol is as follows: * - engines returning an error code from ConstructEngine will be immediately @@ -1744,7 +1793,7 @@ gpuRemoveMissingEngines { const GPU_RESOURCE_DESC *const pCurDesc = &pGpu->engineOrder.pClassDescriptors[curClassDescIdx]; - NvBool bGspSupportsEngine; + NvBool bHostSupportsEngine = NV_FALSE; // // Skip any classes which: @@ -1761,24 +1810,20 @@ gpuRemoveMissingEngines } // - // If the engstate is NULL, the engine may still be supported on GSP. If + // If the engstate is NULL, the engine may still be supported on GSP or VGPU host. If // it is, we can skip removing it. // - // Note that if the function returns NV_WARN_NOTHING_TO_DO, this means - // GSP-RM is not running and thus the engine cannot be supported within - // GSP. - // - rmStatus = gspSupportsEngine(pGpu, pCurDesc->engDesc, &bGspSupportsEngine); - if (rmStatus == NV_WARN_NOTHING_TO_DO) + + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NV_ASSERT_OR_RETURN(pKernelBus != NULL, NV_ERR_INVALID_STATE); + + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu)) { - rmStatus = NV_OK; - bGspSupportsEngine = NV_FALSE; + bHostSupportsEngine = kbusCheckEngineWithOrderList_HAL(pGpu, pKernelBus, pCurDesc->engDesc, NV_FALSE); } - NV_ASSERT_OK_OR_RETURN(rmStatus); - if (bGspSupportsEngine) - { + + if (bHostSupportsEngine) continue; - } NV_ASSERT_OK_OR_RETURN( gpuDeleteClassFromClassDBByEngTag(pGpu, pCurDesc->engDesc)); @@ -1990,16 +2035,17 @@ gpuDeleteEngineOnPreInit_IMPL(OBJGPU *pGpu, NvU32 engDesc) NvU32 numEngDescriptors = gpuGetNumEngDescriptors(pGpu); ENGDESCRIPTOR engDescriptor = engDesc; NV_STATUS rmStatus = NV_OK; - NvBool bGspSupported = NV_FALSE; + NvBool bHostSupported = NV_FALSE; + + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - rmStatus = gspSupportsEngine(pGpu, engDesc, &bGspSupported); - if (rmStatus == NV_WARN_NOTHING_TO_DO) - rmStatus = NV_OK; + NV_ASSERT_OR_RETURN(pKernelBus != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OK_OR_RETURN(rmStatus); + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu)) + bHostSupported = kbusCheckEngineWithOrderList_HAL(pGpu, pKernelBus, engDesc, NV_FALSE); // remove Class tagged with engDesc from Class Database. - if (!bGspSupported) + if (!bHostSupported) gpuDeleteClassFromClassDBByEngTag(pGpu, engDesc); // Remove Load Engine Descriptors @@ -2022,7 +2068,7 @@ gpuDeleteEngineOnPreInit_IMPL(OBJGPU *pGpu, NvU32 engDesc) gpuMissingEngDescriptor(pEngDesc, numEngDescriptors, engDescriptor); - if (!bGspSupported) + if (!bHostSupported) { rmStatus = gpuUpdateEngineTable(pGpu); if (rmStatus != NV_OK) @@ -2061,7 +2107,7 @@ gpuStatePreInit_IMPL NV_STATUS rmStatus = NV_OK; // Quadro, Geforce SMB, Tesla, VGX, Titan GPU detection - gpuInitBranding(pGpu); + NV_ASSERT_OK_OR_RETURN(gpuInitBranding(pGpu)); // Set PDB properties as per data from GSP. gpuInitProperties(pGpu); @@ -2244,7 +2290,7 @@ gpuStateInit_IMPL { if ( IsdADA(pGpu) || - 0) + 0) { NvU32 data32 = NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DEFAULT; @@ -2369,6 +2415,18 @@ gpuStateLoad_IMPL _gpuDetectNvswitchSupport(pGpu); + if (IS_VIRTUAL_WITH_FULL_SRIOV(pGpu) && (flags & GPU_STATE_FLAGS_PRESERVING)) + { + rmStatus = vgpuReinitializeRpcInfraOnStateLoad(pGpu); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to re-init RPC infrastructure on resume, status 0x%x\n", rmStatus); + DBG_BREAKPOINT(); + return rmStatus; + } + } + // Initialize SRIOV specific members of OBJGPU status = gpuInitSriov_HAL(pGpu); if (status != NV_OK) @@ -2377,6 +2435,18 @@ gpuStateLoad_IMPL return status; } + if (IS_VIRTUAL_WITH_FULL_SRIOV(pGpu) && (flags & GPU_STATE_FLAGS_PRESERVING)) + { + NV_RM_RPC_RESTORE_HIBERNATION_DATA(pGpu, rmStatus); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to restore host hibernation data failed, status 0x%x\n", rmStatus); + DBG_BREAKPOINT(); + return rmStatus; + } + } + if (!(flags & GPU_STATE_FLAGS_PRESERVING)) { // It is a no-op on baremetal and inside non SRIOV guest. @@ -2465,11 +2535,14 @@ gpuStateLoad_IMPL // Video logging is not a required feature, don't override existing status NV_CHECK(LEVEL_ERROR, gpuInitVideoLogging(pGpu) == NV_OK); - rmStatus = gpuInitVmmuInfo(pGpu); - if (rmStatus != NV_OK) + if (!IS_VIRTUAL(pGpu)) { - NV_PRINTF(LEVEL_ERROR, "Error initializing VMMU info: 0x%0x\n", status); - goto gpuStateLoad_exit; + rmStatus = gpuInitVmmuInfo(pGpu); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error initializing VMMU info: 0x%0x\n", status); + goto gpuStateLoad_exit; + } } { @@ -2559,6 +2632,11 @@ _gpuRemoveP2pCapsFromPeerGpus RM_API *pPeerRmApi = GPU_GET_PHYSICAL_RMAPI(pPeerGpu); NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS removeP2PCapsParams = {0}; + if (!gpuIsStateLoaded(pPeerGpu)) + { + continue; + } + removeP2PCapsParams.peerGpuIdCount = 1; removeP2PCapsParams.peerGpuIds[0] = pGpu->gpuId; @@ -2618,6 +2696,11 @@ _gpuPropagateP2PCapsToAllGpus { RM_API *pPeerRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + if ((!gpuIsStateLoaded(pGpu)) && (pGpu != pAttachedGpu)) + { + continue; + } + portMemSet(pSetP2PCapsParams, 0, sizeof(*pSetP2PCapsParams)); // The newly attached GPU needs to be informed of all of the current GPUs caps, @@ -2630,6 +2713,11 @@ _gpuPropagateP2PCapsToAllGpus i = 0; while ((pPeerGpu = gpumgrGetNextGpu(attachMask, &peerGpuIndex)) != NULL) { + if ((!gpuIsStateLoaded(pPeerGpu)) && (pPeerGpu != pAttachedGpu)) + { + continue; + } + peerGpuIds[i] = pPeerGpu->gpuId; peerGpuInstances[i] = gpuGetInstance(pPeerGpu); i++; @@ -2660,7 +2748,8 @@ _gpuPropagateP2PCapsToAllGpus &pPeerInfo->p2pOptimalReadCEs, &pPeerInfo->p2pOptimalWriteCEs, pPeerInfo->p2pCapsStatus, - &pPeerInfo->busPeerId), + &pPeerInfo->busPeerId, + NULL), fail); } @@ -2684,6 +2773,11 @@ _gpuPropagateP2PCapsToAllGpus NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS removeP2PCapsParams = {0}; NV_STATUS ignoredStatus; + if ((!gpuIsStateLoaded(pGpu)) && (pGpu != pAttachedGpu)) + { + continue; + } + if (pGpu == pAttachedGpu) { NvU32 peerGpuIndex = 0; @@ -2691,6 +2785,11 @@ _gpuPropagateP2PCapsToAllGpus while ((pPeerGpu = gpumgrGetNextGpu(attachMask, &peerGpuIndex)) != NULL) { + if ((!gpuIsStateLoaded(pPeerGpu)) && (pPeerGpu != pAttachedGpu)) + { + continue; + } + removeP2PCapsParams.peerGpuIds[removeP2PCapsParams.peerGpuIdCount] = pPeerGpu->gpuId; removeP2PCapsParams.peerGpuIdCount++; } @@ -2827,10 +2926,13 @@ gpuStatePostLoad // Caching GID data, the GID is generated by PMU and passed to RM during PMU INIT message. //NV_ASSERT_OK(gpuGetGidInfo(pGpu, NULL, NULL, DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1))); - NV_CHECK_OK_OR_GOTO(rmStatus, - LEVEL_ERROR, - _gpuSetVgpuMgrConfig(pGpu), - gpuStatePostLoad_exit); + if (hypervisorIsVgxHyper()) + { + NV_CHECK_OK_OR_GOTO(rmStatus, + LEVEL_ERROR, + _gpuSetVgpuMgrConfig(pGpu), + gpuStatePostLoad_exit); + } if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_GSP_CLIENT(pGpu)) { @@ -2845,27 +2947,33 @@ gpuStatePostLoad gpuStatePostLoad_exit); } - pGpu->boardInfo = portMemAllocNonPaged(sizeof(*pGpu->boardInfo)); - if (pGpu->boardInfo) + if (!IS_VIRTUAL(pGpu)) { - // To avoid potential race of xid reporting with the control, zero it out - portMemSet(pGpu->boardInfo, '\0', sizeof(*pGpu->boardInfo)); + pGpu->boardInfo = portMemAllocNonPaged(sizeof(*pGpu->boardInfo)); + if (pGpu->boardInfo) + { + // To avoid potential race of xid reporting with the control, zero it out + portMemSet(pGpu->boardInfo, '\0', sizeof(*pGpu->boardInfo)); - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - if(pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO, - pGpu->boardInfo, - sizeof(*pGpu->boardInfo)) != NV_OK) - { - portMemFree(pGpu->boardInfo); - pGpu->boardInfo = NULL; + if(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO, + pGpu->boardInfo, + sizeof(*pGpu->boardInfo)) != NV_OK) + { + portMemFree(pGpu->boardInfo); + pGpu->boardInfo = NULL; + } } } - NV_ASSERT_OR_GOTO(gpuFabricProbeStart(pGpu, &pGpu->pGpuFabricProbeInfoKernel) == NV_OK, - gpuStatePostLoad_exit); + if (!hypervisorIsVgxHyper()) + { + NV_ASSERT_OR_GOTO(gpuFabricProbeStart(pGpu, &pGpu->pGpuFabricProbeInfoKernel) == NV_OK, + gpuStatePostLoad_exit); + } // terminate the load failure test if (rmStatus == NV_OK) @@ -2908,7 +3016,10 @@ gpuStatePreUnload rmapiControlCacheFreeAllCacheForGpu(pGpu->gpuInstance); - gpuFabricProbeStop(pGpu->pGpuFabricProbeInfoKernel); + if (!hypervisorIsVgxHyper()) + { + gpuFabricProbeStop(pGpu->pGpuFabricProbeInfoKernel); + } portMemFree(pGpu->boardInfo); pGpu->boardInfo = NULL; @@ -2972,6 +3083,17 @@ gpuEnterShutdown_IMPL "failed to unload the device with error 0x%x\n", rmStatus); } + if(IS_GSP_CLIENT(pGpu)) + { + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + + // this skips rmDestruct in GSP + NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, rmStatus, NV_FALSE, NV_FALSE, GPU_STATE_FLAGS_FAST_UNLOAD); + + kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp); + kgspDumpGspLogs(pKernelGsp, NV_FALSE); + } + return rmStatus; } @@ -3086,6 +3208,18 @@ gpuStateUnload_IMPL pGpu->bStateLoaded = NV_FALSE; } + if (IS_VIRTUAL_WITH_FULL_SRIOV(pGpu) && (flags & GPU_STATE_FLAGS_PRESERVING)) + { + NV_RM_RPC_SAVE_HIBERNATION_DATA(pGpu, rmStatus); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RPC to save host hibernation data failed, status 0x%x\n", rmStatus); + DBG_BREAKPOINT(); + return rmStatus; + } + } + if (fatalErrorStatus != NV_OK) { rmStatus = fatalErrorStatus; @@ -3195,7 +3329,8 @@ gpuStateDestroy_IMPL engDescriptorList = gpuGetDestroyEngineDescriptors(pGpu); numEngDescriptors = gpuGetNumEngDescriptors(pGpu); - NV_RM_RPC_SIM_FREE_INFRA(pGpu, rmStatus); + // remove all video event bind points before destroying gsp engine state below + videoRemoveAllBindpointsForGpu(pGpu); // Order is determined by gpuGetChildrenOrder_HAL pulling gpuChildOrderList array for (curEngDescIdx = 0; curEngDescIdx < numEngDescriptors; curEngDescIdx++) @@ -3246,9 +3381,6 @@ gpuStateDestroy_IMPL gpuDestroyKernelVideoEngineList(pGpu); - portMemFree(pGpu->gspSupportedEngines); - pGpu->gspSupportedEngines = NULL; - portMemFree(pGpu->pChipInfo); pGpu->pChipInfo = NULL; @@ -3479,6 +3611,8 @@ gpuDetermineVirtualMode OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); NvU32 gpuAttachMask, gpuInstance; NvBool bIsVirtual = NV_FALSE; + NvU32 config = 0; + NvBool bNoHostBridgeDetected = NV_TRUE; if (pGpu->bIsSOC || pGpu->getProperty(pGpu, PDB_PROP_GPU_TEGRA_SOC_NVDISPLAY)) { @@ -3492,6 +3626,26 @@ gpuDetermineVirtualMode gpumgrGetGpuAttachInfo(NULL, &gpuAttachMask); gpuInstance = 0; + config = GPU_REG_RD32(pGpu, NV_PMC_BOOT_1); + + if (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, config)) + { + bIsVirtual = NV_TRUE; + pGpu->bIsVirtualWithSriov = NV_TRUE; + pGpu->bPipelinedPteMemEnabled = NV_TRUE; + } + else + { + bNoHostBridgeDetected = NV_FALSE; + } + + _setPlatformNoHostbridgeDetect(bNoHostBridgeDetected); + + if (!pGpu->bSriovEnabled && !IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + pGpu->bWarBug200577889SriovHeavyEnabled = NV_FALSE; + } + gpuSetupVirtualGuestOwnedHW(pHypervisor, pGpu); // Checking if the VM is already vGPU enabled. @@ -4492,48 +4646,76 @@ gpuGetConstructedFalcon_IMPL NV_STATUS gpuBuildGenericKernelFalconList_IMPL(OBJGPU *pGpu) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + VGPU_STATIC_INFO *pVSI = gpuGetStaticInfo(pGpu); NV_STATUS status; - NvU32 i; + NvU32 srcFalconIdx, tgtFalconIdx; - NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams; + NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams = NULL; + NvBool bAllocatedParams = NV_FALSE; - pParams = portMemAllocNonPaged(sizeof(*pParams)); - NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_NO_MEMORY); + if (IS_VIRTUAL(pGpu)) + { + NV_ASSERT(pVSI != NULL); + pParams = &pVSI->constructedFalconInfo; + } + else + { + pParams = portMemAllocNonPaged(sizeof(*pParams)); + NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_NO_MEMORY); - portMemSet(pParams, 0, sizeof(*pParams)); + bAllocatedParams = NV_TRUE; - NV_ASSERT_OK_OR_GOTO(status, - pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO, - pParams, sizeof(*pParams)), - done); + portMemSet(pParams, 0, sizeof(*pParams)); + + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO, + pParams, sizeof(*pParams)), + done); + } NV_ASSERT_TRUE_OR_GOTO(status, pParams->numConstructedFalcons <= NV_ARRAY_ELEMENTS(pGpu->genericKernelFalcons), NV_ERR_BUFFER_TOO_SMALL, done); - for (i = 0; i < pParams->numConstructedFalcons; i++) + tgtFalconIdx = 0; + for (srcFalconIdx = 0; srcFalconIdx < pParams->numConstructedFalcons; srcFalconIdx++) { KernelFalconEngineConfig config = {0}; - config.physEngDesc = pParams->constructedFalconsTable[i].engDesc; - config.ctxAttr = pParams->constructedFalconsTable[i].ctxAttr; - config.ctxBufferSize = pParams->constructedFalconsTable[i].ctxBufferSize; - config.addrSpaceList = pParams->constructedFalconsTable[i].addrSpaceList; - config.registerBase = pParams->constructedFalconsTable[i].registerBase; + if (pParams->constructedFalconsTable[srcFalconIdx].engDesc == ENG_SEC2 && + GPU_GET_KERNEL_SEC2(pGpu) != NULL) + { + // + // Do not create a GenericKernelFalcon for SEC2 if a KernelSec2 instance exists. + // This is needed for pre-Turing VGPU guests as KernelSec2 is not supported there. + // + continue; + } + + config.physEngDesc = pParams->constructedFalconsTable[srcFalconIdx].engDesc; + config.ctxAttr = pParams->constructedFalconsTable[srcFalconIdx].ctxAttr; + config.ctxBufferSize = pParams->constructedFalconsTable[srcFalconIdx].ctxBufferSize; + config.addrSpaceList = pParams->constructedFalconsTable[srcFalconIdx].addrSpaceList; + config.registerBase = pParams->constructedFalconsTable[srcFalconIdx].registerBase; + + status = objCreate(&pGpu->genericKernelFalcons[tgtFalconIdx], pGpu, GenericKernelFalcon, pGpu, &config); + tgtFalconIdx++; - status = objCreate(&pGpu->genericKernelFalcons[i], pGpu, GenericKernelFalcon, pGpu, &config); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Failed to create a GenericKernelFalcon object %d\n", i); + NV_PRINTF(LEVEL_ERROR, "Failed to create a GenericKernelFalcon object with engdesc %u\n", + config.physEngDesc); goto done; } } - pGpu->numGenericKernelFalcons = pParams->numConstructedFalcons; + pGpu->numGenericKernelFalcons = tgtFalconIdx; done: - portMemFree(pParams); + if (bAllocatedParams) + portMemFree(pParams); + if (status != NV_OK) { gpuDestroyGenericKernelFalconList(pGpu); @@ -4557,8 +4739,14 @@ NV_STATUS gpuBuildKernelVideoEngineList_IMPL(OBJGPU *pGpu) RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status = NV_OK; NvU32 numKernelVideoEngines = 0; - NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams; + NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS *pParams; NvU32 i; + NvU32 data; + + // when regkey is not available, set default eventbuffer size to 32K + data = DRF_NUM(_REG_STR, _RM_VIDEO_EVENT_TRACE, _EVENT_BUFFER_SIZE_IN_4k, 0x8); + + osReadRegistryDword(pGpu, NV_REG_STR_RM_VIDEO_EVENT_TRACE, &data); pParams = portMemAllocNonPaged(sizeof(*pParams)); NV_ASSERT_OR_RETURN(pParams != NULL, NV_ERR_NO_MEMORY); @@ -4568,7 +4756,7 @@ NV_STATUS gpuBuildKernelVideoEngineList_IMPL(OBJGPU *pGpu) NV_ASSERT_OK_OR_GOTO( status, pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO, + NV2080_CTRL_CMD_GPU_GET_CONSTRUCTED_FALCON_INFO, pParams, sizeof(*pParams)), done); @@ -4588,6 +4776,8 @@ NV_STATUS gpuBuildKernelVideoEngineList_IMPL(OBJGPU *pGpu) status, objCreate(&pGpu->kernelVideoEngines[numKernelVideoEngines], pGpu, KernelVideoEngine, pGpu, physEngDesc), done); + + pGpu->kernelVideoEngines[numKernelVideoEngines]->videoTraceInfo.eventTraceRegkeyData = data; numKernelVideoEngines++; } @@ -4631,8 +4821,6 @@ void gpuDestroyKernelVideoEngineList_IMPL(OBJGPU *pGpu) { NvU32 i; - videoRemoveAllBindpointsForGpu(pGpu); - for (i = 0; i < NV_ARRAY_ELEMENTS(pGpu->kernelVideoEngines); i++) { objDelete(pGpu->kernelVideoEngines[i]); @@ -4775,11 +4963,13 @@ gpuGetNextInEngineOrderList(OBJGPU *pGpu, ENGLIST_ITER *pIt, PENGDESCRIPTOR pEng const GPUCHILDPRESENT *pCurChildPresent; const GPUCHILDORDER *pCurChildOrder; NvBool bAdvance = NV_FALSE; + NvBool bFirstIteration = NV_FALSE; pChildOrderList = gpuGetChildrenOrder_HAL(pGpu, &numChildOrder); if (!pIt->bStarted) { + bFirstIteration = NV_TRUE; pIt->bStarted = NV_TRUE; pIt->childOrderIndex = bReverse ? (NvS32)numChildOrder - 1 : 0; } @@ -4809,7 +4999,7 @@ gpuGetNextInEngineOrderList(OBJGPU *pGpu, ENGLIST_ITER *pIt, PENGDESCRIPTOR pEng continue; } - if (bAdvance) + if (bAdvance || bFirstIteration) { pIt->instanceID = bReverse ? pCurChildPresent->instances - 1 : 0; } @@ -4969,6 +5159,21 @@ gpuIsCCDevToolsModeEnabled_IMPL(OBJGPU *pGpu) return NV_FALSE; } +/*! + *@brief Check if protected PCIe is enabled + */ +NvBool +gpuIsCCMultiGpuProtectedPcieModeEnabled_IMPL(OBJGPU *pGpu) +{ + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + + if ((pCC != NULL) && gpuIsCCFeatureEnabled(pGpu)) + { + return pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_MULTI_GPU_PROTECTED_PCIE_MODE_ENABLED); + } + return NV_FALSE; +} + /*! * @brief: Initialize chip related info * This function fills up the chip info structure of OBJGPU. @@ -5027,6 +5232,11 @@ gpuGetDmaEndAddress_IMPL(OBJGPU *pGpu) VGPU_STATIC_INFO *gpuGetStaticInfo(OBJGPU *pGpu) { + if (IS_VIRTUAL(pGpu)) + { + NV_ASSERT_OR_RETURN(GPU_GET_VGPU(pGpu) != NULL, NULL); + return &GPU_GET_VGPU(pGpu)->_vgpuStaticInfo; + } return NULL; } @@ -5049,6 +5259,11 @@ OBJRPC *gpuGetGspClientRpc(OBJGPU *pGpu) OBJRPC *gpuGetVgpuRpc(OBJGPU *pGpu) { + if (IS_VIRTUAL(pGpu)) + { + NV_ASSERT_OR_RETURN(GPU_GET_VGPU(pGpu) != NULL, NULL); + return GPU_GET_VGPU(pGpu)->pRpc; + } return NULL; } @@ -5323,7 +5538,7 @@ NV_STATUS gpuSimEscapeReadBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, Nv // // Only supported with Windows, Debug or Develop driver, or with Release drivers instrumented builds. -// Instrumented build: add "RMCFG_FEATURE_ENABLED=RMTEST" to nvmake command line +// Instrumented build: add RMCFG_OPTIONS="--enable=RMTEST" to nvmake command line // Todo: add OpenRM/GSP support // #if defined(GPU_LOAD_FAILURE_TEST_SUPPORTED) @@ -5416,3 +5631,94 @@ gpuLoadFailurePathTest_IMPL return rmStatus; } #endif + +NvU32 +gpuGetLitterValues_KERNEL +( + OBJGPU *pGpu, + NvU32 index +) +{ + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + const NV2080_CTRL_INTERNAL_STATIC_GR_INFO *pGrInfo; + NvU32 i; + + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized, 0); + pGrInfo = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo; + NV_ASSERT_OR_RETURN(pGrInfo != NULL, 0); + + for (i = 0; i < NV_ARRAY_ELEMENTS(pGrInfo->infoList); i++) + { + if (pGrInfo->infoList[i].index == index) + return pGrInfo->infoList[i].data; + } + return 0; +} + +NV_STATUS gpuGetChipDetails_IMPL +( + OBJGPU *pGpu, + NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS *pParams +) +{ + NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS biosGetSKUInfoParams; + + NV_ASSERT_OK_OR_RETURN(gpuGetSkuInfo_HAL(pGpu, &biosGetSKUInfoParams)); + + // + // GPU chip name (PCI device ID) + // Upper half of pGpu->idInfo.PCIDeviceID is devid + // + pParams->pciDevId = (NvU16)DRF_VAL(_PCI, _SUBID, _DEVICE, pGpu->idInfo.PCIDeviceID); + + // GPU chip SKU + portStringCopy((char *) pParams->chipSku, + sizeof(pParams->chipSku), + (char *) biosGetSKUInfoParams.chipSKU, + sizeof(biosGetSKUInfoParams.chipSKU)); + + // GPU revision + pParams->chipMajor = gpuGetChipMajRev(pGpu); + pParams->chipMinor = gpuGetChipMinRev(pGpu); + + return NV_OK; +} + +BRANDING_TYPE +gpuDetectBranding_IMPL +( + OBJGPU *pGpu +) +{ + if (pGpu->bIsNvidiaNvs) + return BRANDING_TYPE_NVS_NVIDIA; + else if (pGpu->bIsQuadroAD) + return BRANDING_TYPE_QUADRO_AD; + else if (pGpu->bIsQuadro) + return BRANDING_TYPE_QUADRO_GENERIC; + + return BRANDING_TYPE_NONE; +} + +COMPUTE_BRANDING_TYPE +gpuDetectComputeBranding_IMPL(OBJGPU *pGpu) +{ + if (pGpu->bIsTesla) + return COMPUTE_BRANDING_TYPE_TESLA; + + return COMPUTE_BRANDING_TYPE_NONE; +} + +/*! + * @brief Determine the VGX brand of the board + * @returns the VGX brand + */ +BRANDING_TYPE +gpuDetectVgxBranding_IMPL(OBJGPU *pGpu) +{ + if (pGpu->bIsVgx) + return BRANDING_TYPE_VGX; + + return BRANDING_TYPE_NONE; +} + diff --git a/src/nvidia/src/kernel/gpu/gpu_access.c b/src/nvidia/src/kernel/gpu/gpu_access.c index bd1865110c..8c21882183 100644 --- a/src/nvidia/src/kernel/gpu/gpu_access.c +++ b/src/nvidia/src/kernel/gpu/gpu_access.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,9 +22,11 @@ */ #include "kernel/gpu/gpu.h" +#include "gpu_mgr/gpu_mgr.h" #include "kernel/diagnostics/journal.h" #include "core/thread_state.h" +#include "platform/sli/sli.h" #include "nv_ref.h" // Following enums are duplicated in 'apps/nvbucket/oca/ocarm.h'. @@ -1533,6 +1535,9 @@ gpuSanityCheckRegisterAccess_IMPL if ((status = gpuSanityCheckVirtRegAccess_HAL(pGpu, addr)) != NV_OK) { + NV_PRINTF(LEVEL_ERROR, "Invalid register access on VF, addr: 0x%x\n", addr); + osAssertFailed(); + // Return 0 to match with HW behavior retVal = 0; goto done; diff --git a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c index 970df3296e..6a6ef491fc 100644 --- a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c +++ b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c @@ -37,6 +37,10 @@ #include "kernel/mem_mgr/fabric_vaspace.h" #include "ctrl/ctrl2080/ctrl2080internal.h" +#include "compute/fabric.h" +#include "class/cl00f1.h" +#include "vgpu/rpc.h" + // Structure to hold gpu probe information typedef struct GPU_FABRIC_PROBE_INFO_KERNEL { @@ -263,6 +267,12 @@ gpuFabricProbeGetNumProbeReqs LOCK_ASSERT_AND_RETURN(rmDeviceGpuLockIsOwner( gpuGetInstance(pGpuFabricProbeInfoKernel->pGpu))); + if (IS_VIRTUAL(pGpu)) + { + *numProbes = 1; + return NV_OK; + } + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, pRmApi->Control(pRmApi, pGpu->hInternalClient, @@ -289,7 +299,27 @@ gpuFabricProbeGetFabricCliqueId NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); - *pFabricCliqueId = pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.cliqueId; + *pFabricCliqueId = + pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.cliqueId; + + return NV_OK; +} + +NV_STATUS +gpuFabricProbeGetFabricHealthStatus +( + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel, + NvU32 *pFabricHealthStatusMask +) +{ + NV_STATUS status; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); + + NV_CHECK_OR_RETURN(LEVEL_SILENT, status == NV_OK, status); + + *pFabricHealthStatusMask = + pGpuFabricProbeInfoKernel->probeResponseMsg.probeRsp.fabricHealthMask; return NV_OK; } @@ -390,16 +420,45 @@ _gpuFabricProbeSetupFlaRange gpuFabricProbeGetFlaAddressRange(pGpuFabricProbeInfoKernel, &flaSize) == NV_OK); + if (IS_VIRTUAL(pGpu)) + { + fabricvaspaceClearUCRange(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE)); + } + NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, fabricvaspaceInitUCRange(dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE), pGpu, flaBaseAddress, flaSize) == NV_OK); } } -static NV_STATUS -_gpuFabricProbeReceiveKernel +static void +_gpuFabricProbeSendCliqueIdChangeEvent +( + OBJGPU *pGpu, + NvU32 cliqueId +) +{ + NV_STATUS status; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV00F1_CTRL_FABRIC_EVENT event; + event.id = fabricGenerateEventId_IMPL(pFabric); + event.type = NV00F1_CTRL_FABRIC_EVENT_TYPE_CLIQUE_ID_CHANGE; + event.imexChannel = 0; + event.data.cliqueIdChange.gpuId = pGpu->gpuId; + event.data.cliqueIdChange.cliqueId = cliqueId; + status = fabricPostEventsV2(pFabric, &event, 1); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU%u Notifying cliqueId change failed\n", + gpuGetInstance(pGpu)); + } +} + +NV_STATUS +gpuFabricProbeReceiveKernelCallback ( NvU32 gpuInstance, + NvU64 *pNotifyGfidMask, NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams ) { @@ -457,6 +516,59 @@ _gpuFabricProbeReceiveKernel return NV_OK; } +NV_STATUS +gpuFabricProbeReceiveUpdateKernelCallback +( + NvU32 gpuInstance, + NvU64 *pNotifyGfidMask, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams +) +{ + OBJGPU *pGpu; + NvU32 gpuMaskUnused; + nvlink_inband_gpu_probe_update_req_msg_t *pProbeUpdateReqMsg; + nvlink_inband_gpu_probe_rsp_msg_t *pProbeRespMsg; + GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; + NV_STATUS status; + + if ((pGpu = gpumgrGetGpu(gpuInstance)) == NULL) + { + NV_ASSERT_FAILED("Invalid GPU instance"); + return NV_ERR_INVALID_ARGUMENT; + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pGpu->pGpuFabricProbeInfoKernel != NULL, NV_OK); + + NV_ASSERT(rmGpuGroupLockIsOwner(gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + &gpuMaskUnused)); + + NV_ASSERT(pInbandRcvParams != NULL); + + pGpuFabricProbeInfoKernel = pGpu->pGpuFabricProbeInfoKernel; + + status = _gpuFabricProbeFullSanityCheck(pGpuFabricProbeInfoKernel); + NV_CHECK_OR_RETURN(LEVEL_ERROR, status == NV_OK, status); + + pProbeRespMsg = &pGpuFabricProbeInfoKernel->probeResponseMsg; + + pProbeUpdateReqMsg = \ + (nvlink_inband_gpu_probe_update_req_msg_t *)&pInbandRcvParams->data[0]; + + pProbeRespMsg->probeRsp.fabricHealthMask = + pProbeUpdateReqMsg->probeUpdate.fabricHealthMask; + + if (pProbeRespMsg->probeRsp.cliqueId != + pProbeUpdateReqMsg->probeUpdate.cliqueId) + { + pProbeRespMsg->probeRsp.cliqueId = + pProbeUpdateReqMsg->probeUpdate.cliqueId; + _gpuFabricProbeSendCliqueIdChangeEvent(pGpu, + pProbeRespMsg->probeRsp.cliqueId); + } + + return NV_OK; +} + void gpuFabricProbeSuspend ( @@ -524,10 +636,8 @@ gpuFabricProbeStart GPU_FABRIC_PROBE_INFO_KERNEL **ppGpuFabricProbeInfoKernel ) { - NV_STATUS status; + NV_STATUS status = NV_OK; GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel; - NVLINK_INBAND_MSG_CALLBACK inbandMsgCbParams; - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS params = { 0 }; @@ -539,7 +649,8 @@ gpuFabricProbeStart return NV_OK; } - *ppGpuFabricProbeInfoKernel = portMemAllocNonPaged(sizeof(*pGpuFabricProbeInfoKernel)); + *ppGpuFabricProbeInfoKernel = + portMemAllocNonPaged(sizeof(*pGpuFabricProbeInfoKernel)); NV_ASSERT_OR_RETURN(*ppGpuFabricProbeInfoKernel != NULL, NV_ERR_NO_MEMORY); pGpuFabricProbeInfoKernel = *ppGpuFabricProbeInfoKernel; @@ -547,33 +658,31 @@ gpuFabricProbeStart portMemSet(pGpuFabricProbeInfoKernel, 0, sizeof(*pGpuFabricProbeInfoKernel)); pGpuFabricProbeInfoKernel->pGpu = pGpu; - - // Register the receive callback - inbandMsgCbParams.messageType = NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP; - inbandMsgCbParams.pCallback = _gpuFabricProbeReceiveKernel; - inbandMsgCbParams.wqItemFlags = (OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | - OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); - status = knvlinkRegisterInbandCallback(pGpu, - pKernelNvlink, - &inbandMsgCbParams); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "GPU%u Registering Inband Cb failed\n", - gpuGetInstance(pGpu)); - goto fail; - } - pGpuFabricProbeInfoKernel->bwMode = gpumgrGetGpuNvlinkBwMode(); params.bwMode = pGpuFabricProbeInfoKernel->bwMode; - // Send IOCTL to start probe - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE, - ¶ms, sizeof(params)), - fail); + + if (IS_VIRTUAL(pGpu)) + { + NV_RM_RPC_CONTROL(pGpu, NV01_NULL_OBJECT, NV01_NULL_OBJECT, + NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE, + ¶ms, sizeof(params), + status); + + if (status != NV_OK) + goto fail; + } + else + { + // Send IOCTL to start probe + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_START_FABRIC_PROBE, + ¶ms, sizeof(params)), + fail); + } return NV_OK; @@ -591,7 +700,6 @@ gpuFabricProbeStop ) { OBJGPU *pGpu; - KernelNvlink *pKernelNvlink; RM_API *pRmApi; if (pGpuFabricProbeInfoKernel == NULL) @@ -603,20 +711,24 @@ gpuFabricProbeStop NV_ASSERT_OR_RETURN_VOID(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - NV_ASSERT(pKernelNvlink != NULL); - - // Unregister the receive callback - NV_ASSERT_OK(knvlinkUnregisterInbandCallback(pGpu, pKernelNvlink, - NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP)); - - pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - - NV_ASSERT_OK(pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE, - NULL, 0)); + if (!IS_VIRTUAL(pGpu)) + { + // + // On VGPU, we have to stop the probe for guest driver unload as well as for guest clean/forced shutdown/reboot. + // An RPC from this point will not be triggered for forced shutdown/reboot. + // vmioplugin already has callbacks for guest driver unload, guest shutdown and guest reboot. + // Hence it is simpler to handle the probe stop directly from these callbacks in plugin instead of a separate + // RPC for this RM control. + // + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV_ASSERT_OK(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_STOP_FABRIC_PROBE, + NULL, 0)); + } portMemFree(pGpuFabricProbeInfoKernel); pGpu->pGpuFabricProbeInfoKernel = NULL; @@ -635,7 +747,7 @@ gpuFabricProbeIsSupported return NV_FALSE; } - if (GPU_GET_KERNEL_NVLINK(pGpu) == NULL) + if (!IS_VIRTUAL(pGpu) && (GPU_GET_KERNEL_NVLINK(pGpu) == NULL)) { return NV_FALSE; } diff --git a/src/nvidia/src/kernel/gpu/gpu_gspclient.c b/src/nvidia/src/kernel/gpu/gpu_gspclient.c index 85c7633dae..d3e1fa171d 100644 --- a/src/nvidia/src/kernel/gpu/gpu_gspclient.c +++ b/src/nvidia/src/kernel/gpu/gpu_gspclient.c @@ -22,17 +22,14 @@ */ /*! - * @file - * @brief GSP Client (CPU RM) specific GPU routines reside in this file. + * GSP Client (CPU RM) specific GPU routines reside in this file. */ #include "core/core.h" #include "gpu/gpu.h" #include "ctrl/ctrl2080.h" -#include "gpu/gr/kernel_graphics_manager.h" - -#include "gpu/gsp/kernel_gsp.h" +#include "gpu/gsp/gsp_static_config.h" // CORERM-3199 /*! * @brief Determines if the GPU has INTERNAL SKU FUSE parts by checking the GSP @@ -125,45 +122,20 @@ gpuCheckPageRetirementSupport_GSPCLIENT return pGSCI->bPageRetirementSupported; } -void gpuInitBranding_FWCLIENT(OBJGPU *pGpu) +NV_STATUS gpuInitBranding_FWCLIENT(OBJGPU *pGpu) { GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); pGpu->bIsQuadro = pGSCI->bIsQuadroAd || pGSCI->bIsQuadroGeneric; + pGpu->bIsQuadroAD = pGSCI->bIsQuadroAd; pGpu->bIsNvidiaNvs = pGSCI->bIsNvidiaNvs; pGpu->bIsVgx = pGSCI->bIsVgx; pGpu->bGeforceSmb = pGSCI->bGeforceSmb; pGpu->bIsTitan = pGSCI->bIsTitan; pGpu->bIsTesla = pGSCI->bIsTesla; + pGpu->bIsGeforce = !(pGpu->bIsQuadro || pGpu->bIsTesla || pGpu->bIsNvidiaNvs); - pGpu->bIsGeforce = !(pGpu->bIsQuadro || pGpu->bIsTesla || pGpu->bIsNvidiaNvs); -} - -BRANDING_TYPE gpuDetectBranding_FWCLIENT(OBJGPU *pGpu) -{ - GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); - - if (pGSCI->bIsQuadroGeneric) - return BRANDING_TYPE_QUADRO_GENERIC; - if (pGSCI->bIsQuadroAd) - return BRANDING_TYPE_QUADRO_AD; - if (pGSCI->bIsNvidiaNvs) - return BRANDING_TYPE_NVS_NVIDIA; - - return BRANDING_TYPE_NONE; -} - -COMPUTE_BRANDING_TYPE -gpuDetectComputeBranding_FWCLIENT(OBJGPU *pGpu) -{ - GspStaticConfigInfo *pGSCI = GPU_GET_GSP_STATIC_INFO(pGpu); - return pGSCI->computeBranding; -} - -BRANDING_TYPE -gpuDetectVgxBranding_FWCLIENT(OBJGPU *pGpu) -{ - return pGpu->bIsVgx ? BRANDING_TYPE_VGX : BRANDING_TYPE_NONE; + return NV_OK; } NV_STATUS @@ -182,7 +154,7 @@ gpuGenGidData_FWCLIENT if (portMemCmp(pGSCI->gidInfo.data, zeroGid, RM_SHA1_GID_SIZE) == 0) { - NV_PRINTF(LEVEL_ERROR, "GSP Static Info has not been initialized yet for UUID\n"); + NV_PRINTF(LEVEL_INFO, "GSP Static Info has not been initialized yet for UUID\n"); return NV_ERR_INVALID_STATE; } @@ -215,28 +187,6 @@ void gpuInitProperties_FWCLIENT(OBJGPU *pGpu) pGpu->setProperty(pGpu, PDB_PROP_GPU_LEGACY_GCOFF_SUPPORTED, pGSCI->bIsGcoffLegacyAllowed); } -/*! - * @brief These functions are used on CPU RM when pGpu is a GSP client. - * Data is fetched from GSP using subdeviceCtrlCmdInternalGetChipInfo and cached, - * then retrieved through the internal gpuGetChipInfo. - * - * Functions either return value directly, or through a second [out] param, depending - * on the underlying function. - * - * @param[in] pGpu - */ -NvU8 -gpuGetChipSubRev_FWCLIENT -( - OBJGPU *pGpu -) -{ - const NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *pChipInfo = gpuGetChipInfo(pGpu); - NV_ASSERT_OR_RETURN(pChipInfo != NULL, 0); - - return pChipInfo->chipSubRev; -} - NvU32 gpuGetEmulationRev1_FWCLIENT ( @@ -278,6 +228,9 @@ gpuConstructDeviceInfoTable_FWCLIENT if (pParams->numEntries == 0) goto done; + NV_ASSERT_OR_RETURN(pParams->numEntries <= NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES, + NV_ERR_INVALID_STATE); + pGpu->pDeviceInfoTable = portMemAllocNonPaged( pParams->numEntries * (sizeof *pGpu->pDeviceInfoTable)); NV_ASSERT_TRUE_OR_GOTO(status, @@ -296,29 +249,6 @@ gpuConstructDeviceInfoTable_FWCLIENT return status; } -NvU32 -gpuGetLitterValues_FWCLIENT -( - OBJGPU *pGpu, - NvU32 index -) -{ - KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); - const NV2080_CTRL_INTERNAL_STATIC_GR_INFO *pGrInfo; - NvU32 i; - - NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized, 0); - pGrInfo = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo; - NV_ASSERT_OR_RETURN(pGrInfo != NULL, 0); - - for (i = 0; i < NV_ARRAY_ELEMENTS(pGrInfo->infoList); i++) - { - if (pGrInfo->infoList[i].index == index) - return pGrInfo->infoList[i].data; - } - return 0; -} - NV_STATUS gpuGetRegBaseOffset_FWCLIENT ( @@ -340,8 +270,18 @@ gpuGetRegBaseOffset_FWCLIENT return NV_ERR_NOT_SUPPORTED; } -NvU32 -gpuReadBAR1Size_FWCLIENT +/*! + * @brief These functions are used on CPU RM when pGpu is a GSP client. + * Data is fetched from GSP using subdeviceCtrlCmdInternalGetChipInfo and cached, + * then retrieved through the internal gpuGetChipInfo. + * + * Functions either return value directly, or through a second [out] param, depending + * on the underlying function. + * + * @param[in] pGpu + */ +NvU8 +gpuGetChipSubRev_FWCLIENT ( OBJGPU *pGpu ) @@ -349,5 +289,5 @@ gpuReadBAR1Size_FWCLIENT const NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *pChipInfo = gpuGetChipInfo(pGpu); NV_ASSERT_OR_RETURN(pChipInfo != NULL, 0); - return pChipInfo->bar1Size; -} + return pChipInfo->chipSubRev; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/gpu_protobuf.c b/src/nvidia/src/kernel/gpu/gpu_protobuf.c index 0ef27fa113..6731b598f1 100644 --- a/src/nvidia/src/kernel/gpu/gpu_protobuf.c +++ b/src/nvidia/src/kernel/gpu/gpu_protobuf.c @@ -23,6 +23,7 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "platform/sli/sli.h" #include "diagnostics/nv_debug_dump.h" diff --git a/src/nvidia/src/kernel/gpu/gpu_register_access_map.c b/src/nvidia/src/kernel/gpu/gpu_register_access_map.c index d3bba1a525..f8c00da048 100644 --- a/src/nvidia/src/kernel/gpu/gpu_register_access_map.c +++ b/src/nvidia/src/kernel/gpu/gpu_register_access_map.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -214,6 +214,13 @@ gpuConstructUserRegisterAccessMap_IMPL(OBJGPU *pGpu) const NvU8 *compressedData = NULL; const NvU32 *profilingRangesArr = NULL; + if (IS_VIRTUAL(pGpu)) + { + // Usermode access maps unused in Guest RM. Initialize this boolean and leave. + pGpu->bRmProfilingPrivileged = _getIsProfilingPrivileged(pGpu); + return NV_OK; + } + NV_ASSERT(pGpu->userRegisterAccessMapSize == 0); { diff --git a/src/nvidia/src/kernel/gpu/gpu_registry.c b/src/nvidia/src/kernel/gpu/gpu_registry.c index 0937c77f83..933b83801d 100644 --- a/src/nvidia/src/kernel/gpu/gpu_registry.c +++ b/src/nvidia/src/kernel/gpu/gpu_registry.c @@ -135,6 +135,13 @@ gpuInitRegistryOverrides_KERNEL { pGpu->bVgpuGspPluginOffloadEnabled = NV_TRUE; } + // Do not enable VGPU-GSP plugin offload on guest for MODS, MODS doesn't support GSP + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + { + { + pGpu->bVgpuGspPluginOffloadEnabled = pGpu->getProperty(pGpu, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE); + } + } if (osReadRegistryDword(pGpu, NV_REG_STR_RM_CLIENT_RM_ALLOCATED_CTX_BUFFER, &data32) == NV_OK) { diff --git a/src/nvidia/src/kernel/gpu/gpu_resource.c b/src/nvidia/src/kernel/gpu/gpu_resource.c index 7244e67452..331bae9988 100644 --- a/src/nvidia/src/kernel/gpu/gpu_resource.c +++ b/src/nvidia/src/kernel/gpu/gpu_resource.c @@ -397,6 +397,7 @@ gpuresControl_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { + NV_ASSERT_OR_RETURN(pGpuResource->pGpu != NULL, NV_ERR_INVALID_STATE); gpuresControlSetup(pParams, pGpuResource); return resControl_IMPL(staticCast(pGpuResource, RsResource), diff --git a/src/nvidia/src/kernel/gpu/gpu_rmapi.c b/src/nvidia/src/kernel/gpu/gpu_rmapi.c index aa00aa6108..159bd9e089 100644 --- a/src/nvidia/src/kernel/gpu/gpu_rmapi.c +++ b/src/nvidia/src/kernel/gpu/gpu_rmapi.c @@ -36,7 +36,6 @@ #include "rmapi/client.h" #include "rmapi/resource_fwd_decls.h" #include "core/thread_state.h" -#include "virtualization/hypervisor/hypervisor.h" #include "virtualization/kernel_hostvgpudeviceapi.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_channel.h" @@ -894,14 +893,12 @@ _gpuCollectMemInfo // NVOS32_TYPE_UNUSED. if ((pResourceRef->externalClassId == NV01_MEMORY_LOCAL_USER || pResourceRef->externalClassId == NV01_MEMORY_LIST_FBMEM || - pResourceRef->externalClassId == NV01_MEMORY_LIST_OBJECT || - pResourceRef->externalClassId == NV01_MEMORY_HW_RESOURCES) && + pResourceRef->externalClassId == NV01_MEMORY_LIST_OBJECT ) && (pMemory->categoryClassId == NV01_MEMORY_LOCAL_USER) && (bGlobalInfo || (pMemory->pHeap == pTargetedHeap)) && (RES_GET_HANDLE(pMemory->pDevice) == hDevice) && (pMemory->pMemDesc != NULL) && - ((!bIsGuestProcess && (!memdescGetFlag(pMemory->pMemDesc, MEMDESC_FLAGS_LIST_MEMORY)) - && !(hypervisorIsVgxHyper() && (pResourceRef->externalClassId == NV01_MEMORY_HW_RESOURCES))) || + ((!bIsGuestProcess && (!memdescGetFlag(pMemory->pMemDesc, MEMDESC_FLAGS_LIST_MEMORY))) || (bIsGuestProcess && (memdescGetFlag(pMemory->pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED)) && (pMemory->Type != NVOS32_TYPE_UNUSED)))) { NvBool bIsMemProtected = NV_FALSE; @@ -1014,12 +1011,6 @@ gpuFindClientInfoWithPidIterator_IMPL continue; } - gpuInstanceId = clientRef.pKernelMIGGpuInstance->swizzId; - if (clientRef.pMIGComputeInstance != NULL) - { - computeInstanceId = clientRef.pMIGComputeInstance->id; - } - // Check instance subscription against requested instance reference if (!bGlobalInfo && !kmigmgrAreMIGReferencesSame(pRef, &clientRef)) @@ -1027,6 +1018,12 @@ gpuFindClientInfoWithPidIterator_IMPL continue; } + gpuInstanceId = clientRef.pKernelMIGGpuInstance->swizzId; + if (clientRef.pMIGComputeInstance != NULL) + { + computeInstanceId = clientRef.pMIGComputeInstance->id; + } + if (kmigmgrIsMIGReferenceValid(pRef)) { pHeap = pRef->pKernelMIGGpuInstance->pMemoryPartitionHeap; diff --git a/src/nvidia/src/kernel/gpu/gpu_suspend.c b/src/nvidia/src/kernel/gpu/gpu_suspend.c index 33203cecdb..967c7b06f5 100644 --- a/src/nvidia/src/kernel/gpu/gpu_suspend.c +++ b/src/nvidia/src/kernel/gpu/gpu_suspend.c @@ -57,6 +57,9 @@ gpuPowerManagementEnter(OBJGPU *pGpu, NvU32 newLevel, NvU32 flags) NV_STATUS status = NV_OK; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NV_ASSERT_OR_RETURN(!IS_VIRTUAL(pGpu) || !IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu), + NV_ERR_NOT_SUPPORTED); + // This is a no-op in CPU-RM NV_ASSERT_OK_OR_GOTO(status, gpuPowerManagementEnterPreUnloadPhysical(pGpu), done); @@ -79,7 +82,7 @@ gpuPowerManagementEnter(OBJGPU *pGpu, NvU32 newLevel, NvU32 flags) } KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - + KernelGspPreparedFwsecCmd preparedCmd; NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, status, NV_TRUE, IS_GPU_GC6_STATE_ENTERING(pGpu), newLevel); if (status != NV_OK) @@ -100,7 +103,14 @@ gpuPowerManagementEnter(OBJGPU *pGpu, NvU32 newLevel, NvU32 flags) } // Invoke FWSEC-SB to load back PreOsApps. - status = kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode); + status = kgspPrepareForFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode, &preparedCmd); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to prepare for FWSEC-SB for PreOsApps\n"); + goto done; + } + + status = kgspExecuteFwsec_HAL(pGpu, pKernelGsp, &preparedCmd); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC-SB for PreOsApps\n"); @@ -109,10 +119,8 @@ gpuPowerManagementEnter(OBJGPU *pGpu, NvU32 newLevel, NvU32 flags) kpmuFreeLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); - { - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp), done); - } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspSavePowerMgmtState_HAL(pGpu, pKernelGsp), done); } else { @@ -192,11 +200,8 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) if (!IS_GPU_GC6_STATE_EXITING(pGpu)) { - // Not called when kgspShouldBootWithBooter_HAL() is called and returns NV_FALSE - { - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp), done); - } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kgspRestorePowerMgmtState_HAL(pGpu, pKernelGsp), done); status = kpmuInitLibosLoggingStructures(pGpu, GPU_GET_KERNEL_PMU(pGpu)); if (status != NV_OK) @@ -230,7 +235,7 @@ gpuPowerManagementResume(OBJGPU *pGpu, NvU32 oldLevel, NvU32 flags) { pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_BOOT_COMMAND_OK, NV_FALSE); - status = kfspSendBootCommands_HAL(pGpu, pKernelFsp); + status = kfspPrepareAndSendBootCommands_HAL(pGpu, pKernelFsp); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "FSP boot command failed during resume.\n"); diff --git a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c index 475da9af1d..181f611770 100644 --- a/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c +++ b/src/nvidia/src/kernel/gpu/gpu_user_shared_data.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,7 +23,6 @@ #include "gpu/gpu_user_shared_data.h" #include "gpu/gpu.h" -#include "gpu/device/device.h" #include "os/os.h" #include "rmapi/client.h" #include "rmapi/rmapi.h" @@ -57,6 +56,13 @@ gpushareddataConstruct_IMPL return NV_ERR_NOT_SUPPORTED; } + // + // RUSD polling temporarily disabled on non-GSP due to collisions with VSYNC interrupt + // on high refresh rate monitors. See Bug 4432698. + // + if (!IS_GSP_CLIENT(pGpu) && (pAllocParams->polledDataMask != 0U)) + return NV_ERR_NOT_SUPPORTED; + if (RS_IS_COPY_CTOR(pParams)) { return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/gpu_vgpu.c b/src/nvidia/src/kernel/gpu/gpu_vgpu.c new file mode 100644 index 0000000000..be88f067ac --- /dev/null +++ b/src/nvidia/src/kernel/gpu/gpu_vgpu.c @@ -0,0 +1,330 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "objtmr.h" +#include "os/os.h" +#include "gpu/gpu.h" +#include "class/cl0080.h" +#include "vgpu/vgpu_util.h" + +/*! + * Generate GID data for vGPU. + * For SHA-1, we return uuid cached in the vGPU object + * We do not support SHA-256 + * + * @param [in] pGpu OBJGPU pointer + * @param [out] pGidData data array into which GID should be written + * @param [in] gidSize size of data array + * @param [in] gidFlags selects either the SHA-1 or SHA-256 GID + * + * @return NV_OK if the GID if SHA1 GID is requested + */ +NV_STATUS +gpuGenGidData_VGPUSTUB +( + OBJGPU *pGpu, + NvU8 *pGidData, + NvU32 gidSize, + NvU32 gidFlags +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + if (pVSI != NULL && FLD_TEST_DRF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1, gidFlags)) + { + portMemCopy(pGidData, RM_SHA1_GID_SIZE, pVSI->gidInfo.data, RM_SHA1_GID_SIZE); + return NV_OK; + } + return NV_ERR_NOT_SUPPORTED; +} + +/*! + * @brief Returns FBIO Floorsweeping Mask + * + * @param[in] pGpu OBJGPU pointer + * @returns FBIO Floorsweeping Mask - On is enabled + * + */ +NvU32 gpuGetActiveFBIOs_VGPUSTUB +( + OBJGPU *pGpu +) +{ + // Cache is not valid. + if (pGpu->activeFBIOs == 0) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if (pVSI) + pGpu->activeFBIOs = pVSI->fbioMask; + } + // Return the cached map of available FBIOs + return pGpu->activeFBIOs; +} + +NV_STATUS +gpuCreateDefaultClientShare_VGPUSTUB +( + OBJGPU *pGpu +) +{ + NvHandle hClient = NV01_NULL_OBJECT; + NvHandle hDevice = NV01_NULL_OBJECT; + NvHandle hSubDevice = NV01_NULL_OBJECT; + NV_STATUS status; + NV0080_ALLOC_PARAMETERS deviceAllocParams; + NV2080_ALLOC_PARAMETERS subdeviceAllocParams; + NvU32 deviceInstance; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_ASSERT_OK_OR_RETURN(pRmApi->AllocWithHandle(pRmApi, + hClient, + hClient, + hClient, + NV01_ROOT, + &hClient, + sizeof(hClient))); + + pGpu->hDefaultClientShare = hClient; + + // Which device are we? + deviceInstance = gpuGetDeviceInstance(pGpu); + + portMemSet(&deviceAllocParams, 0, sizeof(NV0080_ALLOC_PARAMETERS)); + deviceAllocParams.deviceId = deviceInstance; + deviceAllocParams.hClientShare = pGpu->hDefaultClientShare; + + // Add a device. + NV_ASSERT_OK_OR_GOTO(status, pRmApi->Alloc(pRmApi, + hClient, + hClient, + &hDevice, + NV01_DEVICE_0, + &deviceAllocParams, + sizeof(deviceAllocParams)), failed); + + pGpu->hDefaultClientShareDevice = hDevice; + + portMemSet(&subdeviceAllocParams, 0, sizeof(NV2080_ALLOC_PARAMETERS)); + subdeviceAllocParams.subDeviceId = 0; + + NV_ASSERT_OK_OR_GOTO(status, pRmApi->Alloc(pRmApi, + hClient, + hDevice, + &hSubDevice, + NV20_SUBDEVICE_0, + &subdeviceAllocParams, + sizeof(subdeviceAllocParams)), failed); + + pGpu->hDefaultClientShareSubDevice = hSubDevice; + + return NV_OK; + +failed: + pRmApi->Free(pRmApi, hClient, hClient); + pGpu->hDefaultClientShare = NV01_NULL_OBJECT; + + return status; +} + +void +gpuDestroyDefaultClientShare_VGPUSTUB +( + OBJGPU *pGpu +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + if (pGpu->hDefaultClientShare != NV01_NULL_OBJECT) + { + // Frees everything allocated under this client. + pRmApi->Free(pRmApi, pGpu->hDefaultClientShare, + pGpu->hDefaultClientShare); + } +} + +/*! + * Determines if the board/GPU supports page retirement i.e. removal of + * blacklisted pages from FB heap. For vGPU guest, it is only + * supported for vGPU types which have ECC enabled + * + * @param[in] pGpu GPU object pointer + * + * @return NV_TRUE + * If page retirement is supported. + * @return NV_FALSE + * If page retirement is not supported. + */ + +NvBool +gpuCheckPageRetirementSupport_VGPUSTUB +( + OBJGPU *pGpu +) +{ + NV_ASSERT_OR_RETURN(pGpu != NULL, NV_ERR_INVALID_POINTER); + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + return pVGpu->page_retirement_enabled; +} + +NV_STATUS +gpuInitSriov_VGPUSTUB +( + OBJGPU *pGpu +) +{ + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + pGpu->bSplitVasManagementServerClientRm = pVSI->bSplitVasBetweenServerClientRm; + } + + return NV_OK; +} + +NV_STATUS +gpuGetNameString_VGPUSTUB +( + OBJGPU *pGpu, + NvU32 type, + void *nameStringBuffer +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + if (type == NV2080_CTRL_GPU_GET_NAME_STRING_FLAGS_TYPE_ASCII) + { + portMemCopy(nameStringBuffer, sizeof(pVSI->adapterName), + pVSI->adapterName, sizeof(pVSI->adapterName)); + } + else + { + portMemCopy(nameStringBuffer, sizeof(pVSI->adapterName_Unicode), + pVSI->adapterName_Unicode, sizeof(pVSI->adapterName_Unicode)); + } + + return NV_OK; +} + +NV_STATUS +gpuGetShortNameString_VGPUSTUB +( + OBJGPU *pGpu, + NvU8 *nameStringBuffer +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + portMemCopy(nameStringBuffer, sizeof(pVSI->shortGpuNameString), + pVSI->shortGpuNameString, sizeof(pVSI->shortGpuNameString)); + + return NV_OK; +} + +NvBool +gpuIsGlobalPoisonFuseEnabled_VGPUSTUB +( + OBJGPU *pGpu +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + return pVSI->poisonFuseEnabled; +} + +NV_STATUS +gpuConstructDeviceInfoTable_VGPUSTUB +( + OBJGPU *pGpu +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + if (pGpu->pDeviceInfoTable) // already initialized + return NV_OK; + + if (pVSI->deviceInfoTable.numEntries == 0) + return NV_OK; + + NV_ASSERT_OR_RETURN(pVSI->deviceInfoTable.numEntries <= NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES, + NV_ERR_INVALID_STATE); + + pGpu->pDeviceInfoTable = portMemAllocNonPaged( + pVSI->deviceInfoTable.numEntries * (sizeof *pGpu->pDeviceInfoTable)); + + NV_ASSERT_OR_RETURN(pGpu->pDeviceInfoTable != NULL, NV_ERR_NO_MEMORY); + + pGpu->numDeviceInfoEntries = pVSI->deviceInfoTable.numEntries; + portMemCopy(pGpu->pDeviceInfoTable, + pGpu->numDeviceInfoEntries * (sizeof *pGpu->pDeviceInfoTable), + pVSI->deviceInfoTable.deviceInfoTable, + pVSI->deviceInfoTable.numEntries * (sizeof pVSI->deviceInfoTable.deviceInfoTable[0])); + + return NV_OK; +} + +/*! + * @brief Initialize GPU branding properties + */ +NV_STATUS gpuInitBranding_VGPUSTUB(OBJGPU *pGpu) +{ + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + + NV_ASSERT_OR_RETURN(pVGpu != NULL, NV_ERR_INVALID_STATE); + + pGpu->bIsQuadro = (pVGpu->vgpuConfigUsmType == NV_VGPU_CONFIG_USM_TYPE_QUADRO); + pGpu->bIsQuadroAD = NV_FALSE; + pGpu->bIsNvidiaNvs = (pVGpu->vgpuConfigUsmType == NV_VGPU_CONFIG_USM_TYPE_NVS); + pGpu->bIsVgx = NV_TRUE; + pGpu->bGeforceSmb = NV_FALSE; + pGpu->bIsTitan = NV_FALSE; + pGpu->bIsTesla = (pVGpu->vgpuConfigUsmType == NV_VGPU_CONFIG_USM_TYPE_COMPUTE); + pGpu->bIsGeforce = !(pGpu->bIsQuadro || pGpu->bIsTesla || pGpu->bIsNvidiaNvs); + + return NV_OK; +} + +NV_STATUS +gpuGetSkuInfo_VGPUSTUB +( + OBJGPU *pGpu, + NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pParams +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + portMemCopy(pParams, + sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS), + &pVSI->SKUInfo, + sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS)); + + return NV_OK; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/gpuvideo/videoeventlist.c b/src/nvidia/src/kernel/gpu/gpuvideo/videoeventlist.c index 3f645a4824..83acb9084e 100644 --- a/src/nvidia/src/kernel/gpu/gpuvideo/videoeventlist.c +++ b/src/nvidia/src/kernel/gpu/gpuvideo/videoeventlist.c @@ -34,6 +34,7 @@ #include "rmapi/event.h" #include "rmapi/event_buffer.h" #include "resserv/rs_server.h" +#include "gpu_mgr/gpu_mgr.h" #include "core/locks.h" #include "os/os.h" #include "gpuvideo/video_event.h" diff --git a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c index d92f833e41..81cc958f71 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c @@ -23,6 +23,7 @@ #define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED +#include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" diff --git a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c index b6e141c24a..f9fe175ff0 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/pascal/kgraphics_gp100.c @@ -72,7 +72,7 @@ kgraphicsInitFecsRegistryOverrides_GP100 // CTXSW logging is not supported when HCC prod settings are enabled. // However, the same is supported when HCC is enabled in devtools mode // - if (gpuIsCCFeatureEnabled(pGpu)) + if (gpuIsCCFeatureEnabled(pGpu) && !gpuIsCCDevToolsModeEnabled(pGpu)) { kgraphicsSetCtxswLoggingSupported(pGpu, pKernelGraphics, NV_FALSE); } @@ -248,6 +248,7 @@ kgraphicsServiceInterrupt_GP100 ) { NvU32 grIdx = pKernelGraphics->instance; + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NV_ASSERT_OR_RETURN(pParams != NULL, 0); NV_ASSERT_OR_RETURN(pParams->engineIdx == MC_ENGINE_IDX_GRn_FECS_LOG(grIdx), 0); @@ -259,7 +260,7 @@ kgraphicsServiceInterrupt_GP100 return 0; } - if ((pGpu->fecsCtxswLogConsumerCount > 0) && + if ((fecsGetCtxswLogConsumerCount(pGpu, pKernelGraphicsManager) > 0) && (kgraphicsIsIntrDrivenCtxswLoggingEnabled(pGpu, pKernelGraphics))) { if (fecsClearIntrPendingIfPending(pGpu, pKernelGraphics)) diff --git a/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c b/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c index 1ca621927a..e478624a58 100644 --- a/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c +++ b/src/nvidia/src/kernel/gpu/gr/arch/turing/kgraphics_tu102.c @@ -23,6 +23,7 @@ #define NVOC_KERNEL_GRAPHICS_H_PRIVATE_ACCESS_ALLOWED +#include "gpu_mgr/gpu_mgr.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" diff --git a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c index 4582901040..900041bc21 100644 --- a/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c +++ b/src/nvidia/src/kernel/gpu/gr/fecs_event_list.c @@ -46,6 +46,7 @@ #include "kernel/virtualization/hypervisor/hypervisor.h" #include "rmapi/client.h" #include "objtmr.h" +#include "vgpu/sdk-structures.h" #include "class/cl90cdtypes.h" #include "ctrl/ctrl90cd.h" @@ -96,6 +97,25 @@ struct KGRAPHICS_FECS_TRACE_INFO VGPU_FECS_TRACE_STAGING_BUFFER *pVgpuStaging; }; +/*! Private FECS event buffer data stored for the GPU as a whole */ +struct KGRMGR_FECS_GLOBAL_TRACE_INFO +{ + // map: { UserInfo* -> { pEventBuffer -> NV_EVENT_BUFFER_BIND_POINT* }} + FecsEventBufferBindMultiMap fecsEventBufferBindingsUid; + + // Timer event to periodically the processing callback + TMR_EVENT *pFecsTimerEvent; + + // Timer interval in nanoseconds + NvU32 fecsTimerInterval; + + // Atomic for scheduling the fecs callback in timer mode + NvU32 fecsCallbackScheduled; + + // Number of consumer clients + NvS16 fecsCtxswLogConsumerCount; +}; + /*! * @brief Function to populate client/subdevice/grRouteInfo from cached * information in order to make calls into the specific MIG GPU instance @@ -182,19 +202,21 @@ formatAndNotifyFecsRecord FECS_EVENT_RECORD *pRecord ) { - FECS_EVENT_NOTIFICATION_DATA notifRecord; - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - KernelChannel *pKernelChannel = NULL; - KernelChannel *pKernelChannelNew = NULL; - MIG_INSTANCE_REF *pChannelRef; - MIG_INSTANCE_REF *pNewChannelRef; - INST_BLOCK_DESC inst; - NvU32 timestampId; - NvU64 noisyTimestampStart = 0; - NvU64 noisyTimestampRange = 0; - NvU32 instSize; - NvU32 instShift; - NV_STATUS status; + FECS_EVENT_NOTIFICATION_DATA notifRecord; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + KernelChannel *pKernelChannel = NULL; + KernelChannel *pKernelChannelNew = NULL; + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + MIG_INSTANCE_REF *pChannelRef; + MIG_INSTANCE_REF *pNewChannelRef; + INST_BLOCK_DESC inst; + NvU32 timestampId; + NvU64 noisyTimestampStart = 0; + NvU64 noisyTimestampRange = 0; + NvU32 instSize; + NvU32 instShift; + NV_STATUS status; if (pRecord == NULL) { @@ -203,6 +225,8 @@ formatAndNotifyFecsRecord return; } + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo != NULL); + kfifoGetInstBlkSizeAlign_HAL(pKernelFifo, &instSize, &instShift); portMemSet(¬ifRecord, 0, sizeof(notifRecord)); @@ -356,12 +380,12 @@ formatAndNotifyFecsRecord if (notifRecord.userInfo != 0) { // Notify event buffers listening for the current UID - pSubmap = multimapFindSubmap(&pGpu->fecsEventBufferBindingsUid, notifRecord.userInfo); + pSubmap = multimapFindSubmap(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, notifRecord.userInfo); notifyEventBuffers(pGpu, pSubmap, ¬ifRecord); } // Notify event buffers listening for all UIDs - pSubmap = multimapFindSubmap(&pGpu->fecsEventBufferBindingsUid, 0); + pSubmap = multimapFindSubmap(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, 0); notifyEventBuffers(pGpu, pSubmap, ¬ifRecord); // Clear so we don't report drops for every event in this record @@ -444,11 +468,15 @@ notifyEventBuffers FECS_EVENT_NOTIFICATION_DATA const *pRecord ) { + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo != NULL); + if (pSubmap != NULL) { - FecsEventBufferBindMultiMapIter iter = multimapSubmapIterItems(&pGpu->fecsEventBufferBindingsUid, pSubmap); + FecsEventBufferBindMultiMapIter iter = multimapSubmapIterItems(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, pSubmap); while (multimapItemIterNext(&iter)) { @@ -637,11 +665,10 @@ fecsCtxswLoggingInit return NV_ERR_NO_MEMORY; portMemSet(pFecsTraceInfo, 0, sizeof(*pFecsTraceInfo)); - *ppFecsTraceInfo = pFecsTraceInfo; - osGetCurrentTick(&seed); pFecsTraceInfo->pFecsLogPrng = portCryptoPseudoRandomGeneratorCreate(seed); - multimapInit(&pGpu->fecsEventBufferBindingsUid, portMemAllocatorGetGlobalNonPaged()); + + *ppFecsTraceInfo = pFecsTraceInfo; kgraphicsInitFecsRegistryOverrides_HAL(pGpu, pKernelGraphics); @@ -659,13 +686,50 @@ fecsCtxswLoggingTeardown NV_ASSERT_OR_RETURN_VOID(pFecsTraceInfo != NULL); - multimapDestroy(&pGpu->fecsEventBufferBindingsUid); - portCryptoPseudoRandomGeneratorDestroy(pFecsTraceInfo->pFecsLogPrng); pFecsTraceInfo->pFecsLogPrng = NULL; portMemFree(pFecsTraceInfo); } +NV_STATUS +fecsGlobalLoggingInit +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager, + KGRMGR_FECS_GLOBAL_TRACE_INFO **ppFecsGlobalTraceInfo +) +{ + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo; + + pFecsGlobalTraceInfo = portMemAllocNonPaged(sizeof(*pFecsGlobalTraceInfo)); + NV_ASSERT_OR_RETURN(pFecsGlobalTraceInfo != NULL, NV_ERR_NO_MEMORY); + portMemSet(pFecsGlobalTraceInfo, 0, sizeof(*pFecsGlobalTraceInfo)); + + multimapInit(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, portMemAllocatorGetGlobalNonPaged()); + + *ppFecsGlobalTraceInfo = pFecsGlobalTraceInfo; + + pFecsGlobalTraceInfo->fecsTimerInterval = NV_FECS_TRACE_CALLBACK_TIME_NS; + + return NV_OK; +} + +void +fecsGlobalLoggingTeardown +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo != NULL); + + multimapDestroy(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid); + + portMemFree(pFecsGlobalTraceInfo); +} + /*! set num records to process per intr */ void fecsSetRecordsPerIntr ( @@ -712,6 +776,29 @@ fecsBufferChanged return NV_FALSE; } +static void +_fecsClearCallbackScheduled +( + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo +) +{ + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo != NULL); + portAtomicSetU32(&pFecsGlobalTraceInfo->fecsCallbackScheduled, 0); +} + +/*! + * @brief Atomically set fecs callback scheduled, return NV_TRUE if wasn't scheduled + */ +static NvBool +_fecsSignalCallbackScheduled +( + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo +) +{ + NV_ASSERT_OR_RETURN(pFecsGlobalTraceInfo != NULL, 0); + return portAtomicCompareAndSwapU32(&pFecsGlobalTraceInfo->fecsCallbackScheduled, 1, 0); +} + static void _fecsOsWorkItem ( @@ -721,12 +808,16 @@ _fecsOsWorkItem { OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); KernelGraphicsManager *pKernelGraphicsManager; + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo; NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, pGpu != NULL); pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo != NULL); nvEventBufferFecsCallback(pGpu, NULL); - kgrmgrClearFecsCallbackScheduled(pGpu, pKernelGraphicsManager); + _fecsClearCallbackScheduled(pFecsGlobalTraceInfo); } static NV_STATUS @@ -739,8 +830,11 @@ _fecsTimerCallback { NV_STATUS status = NV_OK; KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); NvU32 i; + NV_ASSERT_OR_RETURN(pFecsGlobalTraceInfo != NULL, NV_ERR_INVALID_STATE); + // If any Kgraphics have events, schedule work item for (i = 0; i < GPU_MAX_GRS; i++) { @@ -749,19 +843,21 @@ _fecsTimerCallback if (pKernelGraphics == NULL) continue; - if (fecsBufferChanged(pGpu, pKernelGraphics) && kgrmgrSignalFecsCallbackScheduled(pGpu, pKernelGraphicsManager)) + if (fecsBufferChanged(pGpu, pKernelGraphics) && _fecsSignalCallbackScheduled(pFecsGlobalTraceInfo)) { NV_CHECK_OK(status, LEVEL_ERROR, osQueueWorkItemWithFlags(pGpu, _fecsOsWorkItem, NULL, OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW)); if (status != NV_OK) - kgrmgrClearFecsCallbackScheduled(pGpu, pKernelGraphicsManager); + _fecsClearCallbackScheduled(pFecsGlobalTraceInfo); break; } } // TMR_FLAG_RECUR does not work, so reschedule it here. - NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, LEVEL_ERROR, tmrEventScheduleRel(pTmr, pTmrEvent, NV_FECS_TRACE_CALLBACK_TIME_NS)); + NV_CHECK_OK_OR_CAPTURE_FIRST_ERROR(status, + LEVEL_ERROR, + tmrEventScheduleRel(pTmr, pTmrEvent, pFecsGlobalTraceInfo->fecsTimerInterval)); return status; } @@ -773,16 +869,20 @@ _fecsTimerCreate ) { OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); NvU32 timerFlags = TMR_FLAG_RECUR; // Unix needs to use the OS timer to avoid corrupting records, but Windows doesn't have an OS timer implementation timerFlags |= TMR_FLAG_USE_OS_TIMER; + NV_ASSERT_OR_RETURN(pFecsGlobalTraceInfo != NULL, NV_ERR_INVALID_STATE); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - tmrEventCreate(pTmr, &pGpu->pFecsTimerEvent, _fecsTimerCallback, NULL, timerFlags)); + tmrEventCreate(pTmr, &pFecsGlobalTraceInfo->pFecsTimerEvent, _fecsTimerCallback, NULL, timerFlags)); // This won't be a true 30Hz timer as the callbacks are scheduled from the time they're called NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - tmrEventScheduleRel(pTmr, pGpu->pFecsTimerEvent, NV_FECS_TRACE_CALLBACK_TIME_NS)); + tmrEventScheduleRel(pTmr, pFecsGlobalTraceInfo->pFecsTimerEvent, pFecsGlobalTraceInfo->fecsTimerInterval)); return NV_OK; } @@ -793,13 +893,18 @@ _fecsTimerDestroy OBJGPU *pGpu ) { - if (pGpu->pFecsTimerEvent != NULL) + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo != NULL); + + if (pFecsGlobalTraceInfo->pFecsTimerEvent != NULL) { OBJTMR *pTmr = GPU_GET_TIMER(pGpu); - tmrEventCancel(pTmr, pGpu->pFecsTimerEvent); - tmrEventDestroy(pTmr, pGpu->pFecsTimerEvent); - pGpu->pFecsTimerEvent = NULL; + tmrEventCancel(pTmr, pFecsGlobalTraceInfo->pFecsTimerEvent); + tmrEventDestroy(pTmr, pFecsGlobalTraceInfo->pFecsTimerEvent); + pFecsGlobalTraceInfo->pFecsTimerEvent = NULL; } } @@ -813,26 +918,29 @@ nvEventBufferFecsCallback void *pArgs ) { - KernelGraphics *pKernelGraphics = (KernelGraphics*)pArgs; - NvU32 fecsReadOffset; - NvU32 fecsReadOffsetPrev; - NvU64 fecsBufferSize; - NvU32 fecsRecordSize; - NvU32 i, j; - NvU8 *pFecsBufferMapping; - MEMORY_DESCRIPTOR *pFecsMemDesc = NULL; - FECS_EVENT_RECORD *pPeekRecord; - NvU16 maxFecsRecordsPerIntr; - NV_STATUS status; - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NvU8 numIterations = (pArgs == NULL) - ? KGRMGR_MAX_GR - : 1; + KernelGraphics *pKernelGraphics = (KernelGraphics*)pArgs; + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + NvU32 fecsReadOffset; + NvU32 fecsReadOffsetPrev; + NvU64 fecsBufferSize; + NvU32 fecsRecordSize; + NvU32 i, j; + NvU8 *pFecsBufferMapping; + MEMORY_DESCRIPTOR *pFecsMemDesc = NULL; + FECS_EVENT_RECORD *pPeekRecord; + NvU16 maxFecsRecordsPerIntr; + NV_STATUS status; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU8 numIterations = (pArgs == NULL) + ? KGRMGR_MAX_GR + : 1; NV_ASSERT_OR_RETURN_VOID(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); - NV_ASSERT_OR_RETURN_VOID(pGpu->fecsCtxswLogConsumerCount >= 0); - if (pGpu->fecsCtxswLogConsumerCount <= 0) + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo != NULL); + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount >= 0); + if (pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount <= 0) return; for (j = 0; j < numIterations; j++) @@ -992,8 +1100,10 @@ fecsAddBindpoint NvBool bAdmin = osIsAdministrator(); NvU32 eventMask = 0; NvU64 targetUser; - NvS32 gpuConsumerCount = pGpu->fecsCtxswLogConsumerCount; - NvBool bFecsBindingActive = (pGpu->fecsCtxswLogConsumerCount > 0); + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + NvS32 gpuConsumerCount; + NvBool bFecsBindingActive; NvBool bIntrDriven = NV_FALSE; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); @@ -1005,6 +1115,10 @@ fecsAddBindpoint CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); NV_ASSERT_OR_RETURN(pCallContext != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pFecsGlobalTraceInfo != NULL, NV_ERR_INVALID_STATE); + + gpuConsumerCount = pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount; + bFecsBindingActive = (pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount > 0); bKernel = pCallContext->secInfo.privLevel >= RS_PRIV_LEVEL_KERNEL; @@ -1016,6 +1130,19 @@ fecsAddBindpoint LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + // Early bail-out if profiling capability is not enabled on vGPU + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if ((pVSI == NULL) || !pVSI->vgpuStaticProperties.bProfilingTracingEnabled) + { + if (pReasonCode != NULL) + *pReasonCode = NV2080_CTRL_GR_FECS_BIND_REASON_CODE_NEED_CAPABILITY; + + return NV_ERR_NOT_SUPPORTED; + } + } + // On a hypervisor or VM: bail-out early if admin is required if (IS_VIRTUAL(pGpu) || hypervisorIsVgxHyper()) { @@ -1083,12 +1210,12 @@ fecsAddBindpoint } pEventBuffer = dynamicCast(pEventBufferRef->pResource, EventBuffer); - if (NULL == pEventBuffer) + if (pEventBuffer == NULL) return NV_ERR_INVALID_ARGUMENT; - if (NULL == multimapFindSubmap(&pGpu->fecsEventBufferBindingsUid, targetUser)) + if (multimapFindSubmap(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, targetUser) == NULL) { - if (NULL == multimapInsertSubmap(&pGpu->fecsEventBufferBindingsUid, targetUser)) + if (multimapInsertSubmap(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, targetUser) == NULL) { NV_PRINTF(LEVEL_ERROR, "failed to add UID binding!\n"); return NV_ERR_INSUFFICIENT_RESOURCES; @@ -1096,13 +1223,13 @@ fecsAddBindpoint } // If the binding exists already, we're done - if (NULL != multimapFindItem(&pGpu->fecsEventBufferBindingsUid, targetUser, (NvU64)(NvUPtr)pEventBuffer)) + if (multimapFindItem(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, targetUser, (NvU64)(NvUPtr)pEventBuffer) != NULL) return NV_OK; - pBind = multimapInsertItemNew(&pGpu->fecsEventBufferBindingsUid, targetUser, (NvU64)(NvUPtr)pEventBuffer); + pBind = multimapInsertItemNew(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, targetUser, (NvU64)(NvUPtr)pEventBuffer); if (pBind == NULL) return NV_ERR_INVALID_ARGUMENT; - ++pGpu->fecsCtxswLogConsumerCount; + ++pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount; pBind->hClient = hClient; pBind->hNotifier = hNotifier; @@ -1187,7 +1314,7 @@ fecsAddBindpoint done: if (status != NV_OK) { - if (gpuConsumerCount != pGpu->fecsCtxswLogConsumerCount) + if (gpuConsumerCount != pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount) fecsRemoveBindpoint(pGpu, targetUser, pBind); _fecsTimerDestroy(pGpu); @@ -1205,8 +1332,12 @@ fecsRemoveBindpoint ) { EventBuffer *pEventBuffer = pBind->pEventBuffer; + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_ASSERT_OR_RETURN_VOID(pFecsGlobalTraceInfo != NULL); - --pGpu->fecsCtxswLogConsumerCount; + --pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount; unregisterEventNotificationWithData(&pEventBuffer->pListeners, pBind->hClient, @@ -1215,11 +1346,11 @@ fecsRemoveBindpoint NV_TRUE, pEventBuffer->producerInfo.notificationHandle); - multimapRemoveItemByKey(&pGpu->fecsEventBufferBindingsUid, + multimapRemoveItemByKey(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, uid, (NvU64)(NvUPtr)pEventBuffer); - if (pGpu->fecsCtxswLogConsumerCount == 0) + if (pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount == 0) { NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); NvU8 grIdx; @@ -1258,6 +1389,7 @@ fecsRemoveAllBindpoints OBJGPU *pGpu = NULL; NvU32 gpuMask = 0; NvU32 gpuIndex = 0; + KernelGraphicsManager *pKernelGraphicsManager; FecsEventBufferBindMultiMapSupermapIter uidBindIter; eventBufferSetEnable(&pEventBuffer->producerInfo, NV_FALSE); @@ -1265,14 +1397,19 @@ fecsRemoveAllBindpoints gpumgrGetGpuAttachInfo(NULL, &gpuMask); while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex)) != NULL) { - uidBindIter = multimapSubmapIterAll(&pGpu->fecsEventBufferBindingsUid); + pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_CHECK_OR_ELSE(LEVEL_ERROR, pFecsGlobalTraceInfo != NULL, continue;); + + uidBindIter = multimapSubmapIterAll(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid); while (multimapSubmapIterNext(&uidBindIter)) { FecsEventBufferBindMultiMapSubmap *pSubmap = uidBindIter.pValue; NV_EVENT_BUFFER_BIND_POINT_FECS *pBind = NULL; NvU64 uid = mapKey_IMPL(uidBindIter.iter.pMap, pSubmap); - while ((pBind = multimapFindItem(&pGpu->fecsEventBufferBindingsUid, + while ((pBind = multimapFindItem(&pFecsGlobalTraceInfo->fecsEventBufferBindingsUid, uid, (NvU64)(NvUPtr)pEventBuffer)) != NULL) { @@ -1306,10 +1443,10 @@ fecsBufferReset NV_ASSERT_OK_OR_ELSE( status, _fecsLoadInternalRoutingInfo(pGpu, - pKernelGraphics, - &hClient, - &hSubdevice, - &getHwEnableParams.grRouteInfo), + pKernelGraphics, + &hClient, + &hSubdevice, + &getHwEnableParams.grRouteInfo), return); NV_ASSERT_OK_OR_ELSE( @@ -1466,6 +1603,8 @@ fecsBufferMap NvU8 *pFecsBufferMapping = NULL; NV_STATUS status; KGRAPHICS_FECS_TRACE_INFO *pFecsTraceInfo = kgraphicsGetFecsTraceInfo(pGpu, pKernelGraphics); + TRANSFER_SURFACE surf = {0}; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_ASSERT_OR_RETURN(pFecsTraceInfo != NULL, NV_ERR_INVALID_STATE); @@ -1479,7 +1618,13 @@ fecsBufferMap if ((status != NV_OK) || (pFecsMemDesc == NULL)) return NV_ERR_INVALID_STATE; - pFecsBufferMapping = kbusMapRmAperture_HAL(pGpu, pFecsMemDesc); + surf.pMemDesc = pFecsMemDesc; + surf.offset = 0; + + pFecsBufferMapping = memmgrMemBeginTransfer(pMemoryManager, &surf, + memdescGetSize(pFecsMemDesc), + TRANSFER_FLAGS_PREFER_PROCESSOR | + TRANSFER_FLAGS_PERSISTENT_CPU_MAPPING); if (pFecsBufferMapping == NULL) return NV_ERR_INSUFFICIENT_RESOURCES; @@ -1498,6 +1643,8 @@ fecsBufferUnmap MEMORY_DESCRIPTOR *pFecsMemDesc = NULL; NV_STATUS status; KGRAPHICS_FECS_TRACE_INFO *pFecsTraceInfo = kgraphicsGetFecsTraceInfo(pGpu, pKernelGraphics); + TRANSFER_SURFACE surf = {0}; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); NV_ASSERT_OR_RETURN_VOID(pFecsTraceInfo != NULL); @@ -1505,10 +1652,21 @@ fecsBufferUnmap return; status = _getFecsMemDesc(pGpu, pKernelGraphics, &pFecsMemDesc); - if ((status == NV_OK) && (pFecsMemDesc != NULL) && (pFecsTraceInfo->pFecsBufferMapping != NULL)) - kbusUnmapRmAperture_HAL(pGpu, pFecsMemDesc, - &pFecsTraceInfo->pFecsBufferMapping, - NV_TRUE); + if ((status != NV_OK) || (pFecsMemDesc == NULL)) + return; + + surf.pMemDesc = pFecsMemDesc; + surf.offset = 0; + + if (pFecsTraceInfo->pFecsBufferMapping != NULL) + { + memmgrMemEndTransfer(pMemoryManager, &surf, + memdescGetSize(pFecsMemDesc), + TRANSFER_FLAGS_PREFER_PROCESSOR | + TRANSFER_FLAGS_PERSISTENT_CPU_MAPPING); + + pFecsTraceInfo->pFecsBufferMapping = NULL; + } } /*! Atomically set intr callback pending, return NV_TRUE if wasn't pending prior */ @@ -1555,6 +1713,52 @@ NvBool fecsIsIntrPending return portAtomicOrU32(&pFecsTraceInfo->fecsCtxswLogIntrPending, 0) != 0; } +NvS16 +fecsGetCtxswLogConsumerCount +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pFecsGlobalTraceInfo != NULL, 0); + + return pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount; +} + +NV_STATUS +fecsIncrementCtxswLogConsumerCount +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_ASSERT_OR_RETURN(pFecsGlobalTraceInfo != NULL, NV_ERR_INVALID_STATE); + + pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount++; + + return NV_OK; +} + +NV_STATUS +fecsDecrementCtxswLogConsumerCount +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_ASSERT_OR_RETURN(pFecsGlobalTraceInfo != NULL, NV_ERR_INVALID_STATE); + + pFecsGlobalTraceInfo->fecsCtxswLogConsumerCount--; + + return NV_OK; +} + /*! Retrieve the current VGPU staging buffer */ VGPU_FECS_TRACE_STAGING_BUFFER * fecsGetVgpuStagingBuffer @@ -1586,3 +1790,17 @@ fecsSetVgpuStagingBuffer pFecsTraceInfo->pVgpuStaging = pStagingBuffer; } +FecsEventBufferBindMultiMap * +fecsGetEventBufferBindMultiMap +( + OBJGPU *pGpu, + KernelGraphicsManager *pKernelGraphicsManager +) +{ + KGRMGR_FECS_GLOBAL_TRACE_INFO *pFecsGlobalTraceInfo = kgrmgrGetFecsGlobalTraceInfo(pGpu, pKernelGraphicsManager); + + NV_ASSERT_OR_RETURN(pFecsGlobalTraceInfo != NULL, NULL); + + return &pFecsGlobalTraceInfo->fecsEventBufferBindingsUid; +} + diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c index ca3672bac9..cb4507207b 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c @@ -41,6 +41,7 @@ #include "kernel/gpu/intr/engine_idx.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "gpu/mmu/kern_gmmu.h" +#include "platform/sli/sli.h" #include "rmapi/rs_utils.h" #include "rmapi/client.h" @@ -95,10 +96,6 @@ static NV_STATUS _kgraphicsMapGlobalCtxBuffer(OBJGPU *pGpu, KernelGraphics *pKer KernelGraphicsContext *, GR_GLOBALCTX_BUFFER, NvBool bIsReadOnly); static NV_STATUS _kgraphicsPostSchedulingEnableHandler(OBJGPU *, void *); -static void _kgraphicsInitProdRegistryOverrides(OBJGPU *pGpu, KernelGraphics *pKernelGraphics) -{ -} - NV_STATUS kgraphicsConstructEngine_IMPL ( @@ -136,7 +133,7 @@ kgraphicsConstructEngine_IMPL NvU32 override; } instlocOverrides[] = { - { GR_CTX_BUFFER_MAIN, DRF_VAL(_REG_STR_RM, _INST_LOC, _GRCTX, pGpu->instLocOverrides) }, + { GR_CTX_BUFFER_MAIN, DRF_VAL(_REG_STR_RM, _INST_LOC, _GRCTX, pGpu->instLocOverrides) }, { GR_CTX_BUFFER_PATCH, DRF_VAL(_REG_STR_RM, _INST_LOC_2, _CTX_PATCH, pGpu->instLocOverrides2) }, { GR_CTX_BUFFER_ZCULL, DRF_VAL(_REG_STR_RM, _INST_LOC_2, _ZCULLCTX, pGpu->instLocOverrides2) }, { GR_CTX_BUFFER_PM, DRF_VAL(_REG_STR_RM, _INST_LOC_2, _PMCTX, pGpu->instLocOverrides2) }, @@ -144,7 +141,8 @@ kgraphicsConstructEngine_IMPL { GR_CTX_BUFFER_BETA_CB, DRF_VAL(_REG_STR_RM, _INST_LOC_3, _GFXP_BETACB_BUFFER, pGpu->instLocOverrides3) }, { GR_CTX_BUFFER_PAGEPOOL, DRF_VAL(_REG_STR_RM, _INST_LOC_3, _GFXP_PAGEPOOL_BUFFER, pGpu->instLocOverrides3) }, { GR_CTX_BUFFER_SPILL, DRF_VAL(_REG_STR_RM, _INST_LOC_3, _GFXP_SPILL_BUFFER, pGpu->instLocOverrides3) }, - { GR_CTX_BUFFER_RTV_CB, DRF_VAL(_REG_STR_RM, _INST_LOC_3, _GFXP_RTVCB_BUFFER, pGpu->instLocOverrides3) } + { GR_CTX_BUFFER_RTV_CB, DRF_VAL(_REG_STR_RM, _INST_LOC_3, _GFXP_RTVCB_BUFFER, pGpu->instLocOverrides3) }, + { GR_CTX_BUFFER_SETUP, DRF_VAL(_REG_STR_RM, _INST_LOC_4, _GFXP_SETUP_BUFFER, pGpu->instLocOverrides4) } }; for (idx = 0; idx < NV_ARRAY_ELEMENTS(instlocOverrides); ++idx) @@ -217,7 +215,6 @@ kgraphicsConstructEngine_IMPL NV_ASSERT_OK_OR_RETURN(fecsCtxswLoggingInit(pGpu, pKernelGraphics, &pKernelGraphics->pFecsTraceInfo)); - _kgraphicsInitProdRegistryOverrides(pGpu, pKernelGraphics); return NV_OK; } @@ -338,7 +335,9 @@ kgraphicsStateLoad_IMPL NvU32 flags ) { - if (pGpu->fecsCtxswLogConsumerCount > 0) + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + + if (fecsGetCtxswLogConsumerCount(pGpu, pKernelGraphicsManager) > 0) { fecsBufferMap(pGpu, pKernelGraphics); fecsBufferReset(pGpu, pKernelGraphics); @@ -752,6 +751,266 @@ kgraphicsInitializeDeferredStaticData_IMPL return status; } +NV_STATUS +kgraphicsLoadStaticInfo_VGPUSTUB +( + OBJGPU *pGpu, + KernelGraphics *pKernelGraphics, + NvU32 swizzId +) +{ + KGRAPHICS_PRIVATE_DATA *pPrivate = pKernelGraphics->pPrivate; + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NvU32 grIdx = pKernelGraphics->instance; + NVOS_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pPrivate != NULL, NV_ERR_INVALID_STATE); + + if (pPrivate->bInitialized) + return status; + + if (IS_MIG_IN_USE(pGpu)) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + // + // Delay initialization to GPU instance configuration, unless MODS is using + // legacy VGPU mode, in which case the guest never receives a + // configuration call + // + if ((swizzId == KMIGMGR_SWIZZID_INVALID) && !kmigmgrUseLegacyVgpuPolicy(pGpu, pKernelMIGManager)) + return status; + + pPrivate->staticInfo.pGrInfo = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pGrInfo)); + if (pPrivate->staticInfo.pGrInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pGrInfo->infoList, + NV0080_CTRL_GR_INFO_MAX_SIZE * sizeof(*pPrivate->staticInfo.pGrInfo->infoList), + pVSI->grInfoParams.engineInfo[grIdx].infoList, + NV0080_CTRL_GR_INFO_MAX_SIZE * sizeof(*pVSI->grInfoParams.engineInfo[grIdx].infoList)); + + portMemCopy(&pPrivate->staticInfo.globalSmOrder, sizeof(pPrivate->staticInfo.globalSmOrder), + &pVSI->globalSmOrder.globalSmOrder[grIdx], sizeof(pVSI->globalSmOrder.globalSmOrder[grIdx])); + + // grCaps are the same for all GR and can be copied from VGPU static info + portMemCopy(pPrivate->staticInfo.grCaps.capsTbl, sizeof(pPrivate->staticInfo.grCaps.capsTbl), + pVSI->grCapsBits, sizeof(pVSI->grCapsBits)); + + // Initialize PDB properties synchronized with physical RM + pPrivate->staticInfo.pdbTable.bPerSubCtxheaderSupported = pVSI->bPerSubCtxheaderSupported; + kgraphicsSetPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics, pPrivate->staticInfo.pdbTable.bPerSubCtxheaderSupported); + + pPrivate->staticInfo.pSmIssueRateModifier = + portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pSmIssueRateModifier)); + if (pPrivate->staticInfo.pSmIssueRateModifier == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pSmIssueRateModifier, sizeof(*pPrivate->staticInfo.pSmIssueRateModifier), + &pVSI->smIssueRateModifier.smIssueRateModifier[grIdx], sizeof(pVSI->smIssueRateModifier.smIssueRateModifier[grIdx])); + + pPrivate->staticInfo.pPpcMasks = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pPpcMasks)); + if (pPrivate->staticInfo.pPpcMasks == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pPpcMasks, sizeof(*pPrivate->staticInfo.pPpcMasks), + &pVSI->ppcMaskParams.enginePpcMasks[grIdx], sizeof(pVSI->ppcMaskParams.enginePpcMasks[grIdx])); + + portMemCopy(&pPrivate->staticInfo.floorsweepingMasks, sizeof(pPrivate->staticInfo.floorsweepingMasks), + &pVSI->floorsweepMaskParams.floorsweepingMasks[grIdx], sizeof(pVSI->floorsweepMaskParams.floorsweepingMasks[grIdx])); + + pPrivate->staticInfo.pContextBuffersInfo = + portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pContextBuffersInfo)); + + if (pPrivate->staticInfo.pContextBuffersInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pContextBuffersInfo, + sizeof(*pPrivate->staticInfo.pContextBuffersInfo), + &pVSI->ctxBuffInfo.engineContextBuffersInfo[grIdx], + sizeof(pVSI->ctxBuffInfo.engineContextBuffersInfo[grIdx])); + + pPrivate->staticInfo.fecsRecordSize.fecsRecordSize = pVSI->fecsRecordSize.fecsRecordSize[grIdx].fecsRecordSize; + + pPrivate->staticInfo.pFecsTraceDefines = + portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pFecsTraceDefines)); + + if (pPrivate->staticInfo.pFecsTraceDefines == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pFecsTraceDefines, + sizeof(*pPrivate->staticInfo.pFecsTraceDefines), + &pVSI->fecsTraceDefines.fecsTraceDefines[grIdx], + sizeof(pVSI->fecsTraceDefines.fecsTraceDefines[grIdx])); + + portMemCopy(&pPrivate->staticInfo.pdbTable, sizeof(pPrivate->staticInfo.pdbTable), + &pVSI->pdbTableParams.pdbTable[grIdx], sizeof(pVSI->pdbTableParams.pdbTable[grIdx])); + } + else if (grIdx == 0) + { + portMemCopy(pPrivate->staticInfo.grCaps.capsTbl, sizeof(pPrivate->staticInfo.grCaps.capsTbl), + pVSI->grCapsBits, sizeof(pVSI->grCapsBits)); + + pPrivate->staticInfo.pGrInfo = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pGrInfo)); + if (pPrivate->staticInfo.pGrInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pGrInfo->infoList, + NV0080_CTRL_GR_INFO_MAX_SIZE * sizeof(*pPrivate->staticInfo.pGrInfo->infoList), + pVSI->grInfoParams.engineInfo[grIdx].infoList, + NV0080_CTRL_GR_INFO_MAX_SIZE * sizeof(*pVSI->grInfoParams.engineInfo[grIdx].infoList)); + + // Initialize PDB properties synchronized with physical RM + pPrivate->staticInfo.pdbTable.bPerSubCtxheaderSupported = pVSI->bPerSubCtxheaderSupported; + kgraphicsSetPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics, pPrivate->staticInfo.pdbTable.bPerSubCtxheaderSupported); + + portMemCopy(&pPrivate->staticInfo.globalSmOrder, sizeof(pPrivate->staticInfo.globalSmOrder), + &pVSI->globalSmOrder.globalSmOrder[grIdx], sizeof(pVSI->globalSmOrder.globalSmOrder[grIdx])); + + pPrivate->staticInfo.pSmIssueRateModifier = + portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pSmIssueRateModifier)); + if (pPrivate->staticInfo.pSmIssueRateModifier == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pSmIssueRateModifier, sizeof(*pPrivate->staticInfo.pSmIssueRateModifier), + &pVSI->smIssueRateModifier.smIssueRateModifier[grIdx], sizeof(pVSI->smIssueRateModifier.smIssueRateModifier[grIdx])); + + pPrivate->staticInfo.pPpcMasks = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pPpcMasks)); + if (pPrivate->staticInfo.pPpcMasks == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pPpcMasks, sizeof(*pPrivate->staticInfo.pPpcMasks), + &pVSI->ppcMaskParams.enginePpcMasks[grIdx], sizeof(pVSI->ppcMaskParams.enginePpcMasks[grIdx])); + + pPrivate->staticInfo.pContextBuffersInfo = + portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pContextBuffersInfo)); + + if (pPrivate->staticInfo.pContextBuffersInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pContextBuffersInfo, + sizeof(*pPrivate->staticInfo.pContextBuffersInfo), + &pVSI->ctxBuffInfo.engineContextBuffersInfo[grIdx], + sizeof(pVSI->ctxBuffInfo.engineContextBuffersInfo[grIdx])); + + portMemCopy(&pPrivate->staticInfo.floorsweepingMasks, sizeof(pPrivate->staticInfo.floorsweepingMasks), + &pVSI->floorsweepMaskParams.floorsweepingMasks[grIdx], sizeof(pVSI->floorsweepMaskParams.floorsweepingMasks[grIdx])); + + pPrivate->staticInfo.pRopInfo = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pRopInfo)); + if (pPrivate->staticInfo.pRopInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pRopInfo, sizeof(*pPrivate->staticInfo.pRopInfo), + &pVSI->ropInfoParams.engineRopInfo[grIdx], sizeof(pVSI->ropInfoParams.engineRopInfo[grIdx])); + + pPrivate->staticInfo.pZcullInfo = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pZcullInfo)); + if (pPrivate->staticInfo.pZcullInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pZcullInfo, sizeof(*pPrivate->staticInfo.pZcullInfo), + &pVSI->zcullInfoParams.engineZcullInfo[grIdx], sizeof(pVSI->zcullInfoParams.engineZcullInfo[grIdx])); + + pPrivate->staticInfo.fecsRecordSize.fecsRecordSize = pVSI->fecsRecordSize.fecsRecordSize[grIdx].fecsRecordSize; + + pPrivate->staticInfo.pFecsTraceDefines = + portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pFecsTraceDefines)); + if (pPrivate->staticInfo.pFecsTraceDefines == NULL) + { + status = NV_ERR_NO_MEMORY; + goto cleanup; + } + + portMemCopy(pPrivate->staticInfo.pFecsTraceDefines, + sizeof(*pPrivate->staticInfo.pFecsTraceDefines), + &pVSI->fecsTraceDefines.fecsTraceDefines[grIdx], + sizeof(pVSI->fecsTraceDefines.fecsTraceDefines[grIdx])); + + portMemCopy(&pPrivate->staticInfo.pdbTable, sizeof(pPrivate->staticInfo.pdbTable), + &pVSI->pdbTableParams.pdbTable[grIdx], sizeof(pVSI->pdbTableParams.pdbTable[grIdx])); + } + else + { + // if MIG disabled, only GR0 static data needs to be published + return status; + } + + if (status == NV_OK) + { + // Publish static configuration + pPrivate->bInitialized = NV_TRUE; + } + + if (!IS_MIG_IN_USE(pGpu) && (grIdx == 0)) + { + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + + // Cache legacy GR mask info (i.e. GR0 with MIG disabled) to pKernelGraphicsManager->legacyFsMaskState + kgrmgrSetLegacyKgraphicsStaticInfo(pGpu, pKernelGraphicsManager, pKernelGraphics); + } + +cleanup : + + if (status != NV_OK) + { + portMemFree(pPrivate->staticInfo.pGrInfo); + pPrivate->staticInfo.pGrInfo = NULL; + + portMemFree(pPrivate->staticInfo.pPpcMasks); + pPrivate->staticInfo.pPpcMasks = NULL; + + portMemFree(pPrivate->staticInfo.pZcullInfo); + pPrivate->staticInfo.pZcullInfo = NULL; + + portMemFree(pPrivate->staticInfo.pRopInfo); + pPrivate->staticInfo.pRopInfo = NULL; + + portMemFree(pPrivate->staticInfo.pContextBuffersInfo); + pPrivate->staticInfo.pContextBuffersInfo = NULL; + + portMemFree(pPrivate->staticInfo.pSmIssueRateModifier); + pPrivate->staticInfo.pSmIssueRateModifier = NULL; + + portMemFree(pPrivate->staticInfo.pFecsTraceDefines); + pPrivate->staticInfo.pFecsTraceDefines = NULL; + } + + return status; +} + NV_STATUS kgraphicsLoadStaticInfo_KERNEL ( @@ -1386,6 +1645,8 @@ kgraphicsAllocKgraphicsBuffers_KERNEL if (kgraphicsIsCtxswLoggingSupported(pGpu, pKernelGraphics) && (kgraphicsGetGlobalCtxBuffers(pGpu, pKernelGraphics, gfid)->memDesc[GR_GLOBALCTX_BUFFER_FECS_EVENT] != NULL)) { + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + if (!gvaspaceIsExternallyOwned(pGVAS) && !IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) { // @@ -1402,7 +1663,7 @@ kgraphicsAllocKgraphicsBuffers_KERNEL fecsBufferMap(pGpu, pKernelGraphics); } - if (pGpu->fecsCtxswLogConsumerCount > 0) + if (fecsGetCtxswLogConsumerCount(pGpu, pKernelGraphicsManager) > 0) fecsBufferReset(pGpu, pKernelGraphics); } @@ -2110,12 +2371,14 @@ void kgraphicsFreeGlobalCtxBuffers_IMPL pCtxBuffers = &pKernelGraphics->globalCtxBuffersInfo.pGlobalCtxBuffers[gfid]; + if (!pCtxBuffers->bAllocated) + return; + FOR_EACH_IN_ENUM(GR_GLOBALCTX_BUFFER, buff) { + if (pCtxBuffers->memDesc[buff] != NULL) { - - if (pCtxBuffers->memDesc[buff] != NULL) - bEvict = NV_TRUE; + bEvict = NV_TRUE; memdescFree(pCtxBuffers->memDesc[buff]); memdescDestroy(pCtxBuffers->memDesc[buff]); @@ -2331,9 +2594,8 @@ _kgraphicsCtrlCmdGrGetInfoV2 NV_STATUS status = NV_OK; KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NvU32 grInfoListSize = pParams->grInfoListSize; - KernelGraphics *pKernelGraphics; - const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NV2080_CTRL_INTERNAL_STATIC_GR_INFO *pGrInfo; NvU32 i; if (pKernelGraphicsManager == NULL) @@ -2350,31 +2612,30 @@ _kgraphicsCtrlCmdGrGetInfoV2 if (kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice)) { - NvU32 grIdx; - for (grIdx = 0; grIdx < GPU_MAX_GRS; grIdx++) - { - pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, grIdx); - if (pKernelGraphics != NULL) - break; - } - if (pKernelGraphics == NULL) - return NV_ERR_INVALID_STATE; + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo != NULL, NV_ERR_NOT_SUPPORTED); + + pGrInfo = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo; } else { + KernelGraphics *pKernelGraphics; + const KGRAPHICS_STATIC_INFO *pKernelGraphicsStaticInfo; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgrmgrCtrlRouteKGRWithDevice(pGpu, pKernelGraphicsManager, pDevice, &pParams->grRouteInfo, &pKernelGraphics)); - } - pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); - NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pGrInfo != NULL, NV_ERR_NOT_SUPPORTED); + pKernelGraphicsStaticInfo = kgraphicsGetStaticInfo(pGpu, pKernelGraphics); + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pKernelGraphicsStaticInfo->pGrInfo != NULL, NV_ERR_NOT_SUPPORTED); + + pGrInfo = pKernelGraphicsStaticInfo->pGrInfo; + } for (i = 0; i < grInfoListSize; i++) { NV_CHECK_OR_RETURN(LEVEL_ERROR, pParams->grInfoList[i].index < NV2080_CTRL_GR_INFO_MAX_SIZE, NV_ERR_INVALID_ARGUMENT); - pParams->grInfoList[i].data = - pKernelGraphicsStaticInfo->pGrInfo->infoList[pParams->grInfoList[i].index].data; + pParams->grInfoList[i].data = pGrInfo->infoList[pParams->grInfoList[i].index].data; } return status; diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c index e6ca6e807f..b4caf4767e 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_context.c @@ -35,10 +35,12 @@ #include "kernel/core/locks.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "vgpu/rpc.h" +#include "gpu/device/device.h" #include "kernel/gpu/subdevice/subdevice.h" #include "kernel/virtualization/hypervisor/hypervisor.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "gpu/mmu/kern_gmmu.h" +#include "platform/sli/sli.h" #include "rmapi/client.h" /*! @@ -288,6 +290,9 @@ kgrctxCtxBufferToFifoEngineId_IMPL case GR_CTX_BUFFER_PATCH: *pFifoEngineId = NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_PATCH; break; + case GR_CTX_BUFFER_SETUP: + *pFifoEngineId = NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_SETUP; + break; // No default case - Compiler enforces switch update if enum is changed } @@ -2388,24 +2393,21 @@ kgrctxUnmapAssociatedCtxBuffers_IMPL // channels could be using these mappings, and we must wait for both // channels to be detached before we remove them. // + if ((!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm) && + (pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->pChanList != NULL)) { - RS_ORDERED_ITERATOR it; - RsResourceRef *pScopeRef = RES_GET_REF(pKernelChannel); + CHANNEL_NODE *pChanNode; + CHANNEL_LIST *pChanList; - // Iterate over all channels in this TSG and check for duplicate VAS - if (!pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->bAllocatedByRm) - pScopeRef = RES_GET_REF(pKernelChannel->pKernelChannelGroupApi); + pChanList = pKernelChannel->pKernelChannelGroupApi->pKernelChannelGroup->pChanList; - it = kchannelGetIter(RES_GET_CLIENT(pKernelChannel), pScopeRef); - while (clientRefOrderedIterNext(it.pClient, &it)) + for (pChanNode = pChanList->pHead; pChanNode; pChanNode = pChanNode->pNext) { - KernelChannel *pLoopKernelChannel = dynamicCast(it.pResourceRef->pResource, KernelChannel); - NV_ASSERT_OR_RETURN_VOID(pLoopKernelChannel != NULL); - - if (pLoopKernelChannel == pKernelChannel) + // Skip the channel we are looking to unmap + if (kchannelGetDebugTag(pKernelChannel) == kchannelGetDebugTag(pChanNode->pKernelChannel)) continue; - NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, pLoopKernelChannel->pVAS != pKernelChannel->pVAS); + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, pChanNode->pKernelChannel->pVAS != pKernelChannel->pVAS); } } @@ -2560,6 +2562,20 @@ kgrctxShouldPreAllocPmBuffer_VF // created later with an rm ctrl. // 2. For full SRIOV vGPU guests with Profiling capability enabled // + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && !gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NvBool bProfilingEnabledVgpuGuest = NV_FALSE; + + if (pVSI != NULL) + { + bProfilingEnabledVgpuGuest = pVSI->vgpuStaticProperties.bProfilingTracingEnabled; + if (bProfilingEnabledVgpuGuest) + { + return NV_TRUE; + } + } + } return kgrctxShouldPreAllocPmBuffer_PF(pGpu, pKernelGraphicsContext, pKernelChannel); } diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c index e586341059..8420974b70 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c @@ -25,6 +25,7 @@ #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/gr/fecs_event_list.h" #include "kernel/gpu/device/device.h" #include "kernel/gpu/fifo/kernel_channel_group_api.h" @@ -171,6 +172,8 @@ kgrmgrIsCtxBufSupported_IMPL case GR_CTX_BUFFER_PAGEPOOL: // fall-through case GR_CTX_BUFFER_RTV_CB: + // fall-through + case GR_CTX_BUFFER_SETUP: bSupported = NV_FALSE; break; @@ -311,6 +314,8 @@ kgrmgrConstructEngine_IMPL { _kgrmgrInitRegistryOverrides(pGpu, pKernelGraphicsManager); + fecsGlobalLoggingInit(pGpu, pKernelGraphicsManager, &pKernelGraphicsManager->pFecsGlobalTraceInfo); + return NV_OK; } @@ -320,8 +325,12 @@ kgrmgrDestruct_IMPL KernelGraphicsManager *pKernelGraphicsManager ) { + OBJGPU *pGpu = ENG_GET_GPU(pKernelGraphicsManager); + + fecsGlobalLoggingTeardown(pGpu, pKernelGraphicsManager); + portMemSet(&pKernelGraphicsManager->legacyKgraphicsStaticInfo.floorsweepingMasks, 0, - sizeof(pKernelGraphicsManager->legacyKgraphicsStaticInfo.floorsweepingMasks)); + sizeof(pKernelGraphicsManager->legacyKgraphicsStaticInfo.floorsweepingMasks)); portMemFree(pKernelGraphicsManager->legacyKgraphicsStaticInfo.pPpcMasks); pKernelGraphicsManager->legacyKgraphicsStaticInfo.pPpcMasks = NULL; portMemFree(pKernelGraphicsManager->legacyKgraphicsStaticInfo.pGrInfo); @@ -1085,29 +1094,3 @@ kgrmgrCheckVeidsRequest_IMPL *pInUseMask |= veidMask; return NV_OK; } - -/*! - * @brief Atomically set fecs callback scheduled, return NV_TRUE if wasn't scheduled - */ -NvBool -kgrmgrSignalFecsCallbackScheduled_IMPL -( - OBJGPU *pGpu, - KernelGraphicsManager *pKernelGraphicsManager -) -{ - return portAtomicCompareAndSwapU32(&pKernelGraphicsManager->fecsCallbackScheduled, 1, 0); -} - -/*! - * @brief Atomically clear fecs callback scheduled - */ -void -kgrmgrClearFecsCallbackScheduled_IMPL -( - OBJGPU *pGpu, - KernelGraphicsManager *pKernelGraphicsManager -) -{ - portAtomicSetU32(&pKernelGraphicsManager->fecsCallbackScheduled, 0); -} diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c index 61ff7250db..344bb5a758 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics_object.c @@ -32,6 +32,7 @@ #include "kernel/gpu/mem_mgr/mem_mgr.h" #include "kernel/gpu/fifo/kernel_channel_group.h" #include "kernel/gpu/fifo/kernel_channel_group_api.h" +#include "platform/sli/sli.h" #include "class/cl0020.h" diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c index dd28f8b35e..18f046f0bf 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session.c @@ -23,9 +23,6 @@ #define NVOC_KERNEL_SM_DEBUGGER_SESSION_H_PRIVATE_ACCESS_ALLOWED -// FIXME XXX -#define NVOC_KERNEL_GRAPHICS_OBJECT_H_PRIVATE_ACCESS_ALLOWED - #include "kernel/os/os.h" #include "kernel/core/locks.h" #include "kernel/gpu/gr/kernel_sm_debugger_session.h" diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c index f98315161e..08bb00ac7a 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c @@ -188,7 +188,7 @@ _nv8deCtrlCmdReadWriteSurface end4kPage = (NvOffset_LO32(virtAddr + bufSize - 1) >> 12) & 0x1FFFF; curSize = RM_PAGE_SIZE - pageStartOffset; - virtAddr &= ~RM_PAGE_MASK; + virtAddr -= pageStartOffset; for (cur4kPage = start4kPage; cur4kPage <= end4kPage; ++cur4kPage) { @@ -220,7 +220,7 @@ _nv8deCtrlCmdReadWriteSurface if (traceArg.aperture == ADDR_SYSMEM) { NvP64 physAddr = NV_PTR_TO_NvP64(traceArg.pa); - NvU64 limit = (NvU64)(curSize - 1); + NvU64 limit = RM_PAGE_SIZE - 1; NvU32 os02Flags = DRF_DEF(OS02, _FLAGS, _LOCATION, _PCI) | DRF_DEF(OS02, _FLAGS, _MAPPING, _NO_MAP) | @@ -241,11 +241,11 @@ _nv8deCtrlCmdReadWriteSurface else if (traceArg.aperture == ADDR_FBMEM) { NV_ASSERT_OK_OR_ELSE(status, - memdescCreate(&pMemDesc, pGpu, curSize, 0, NV_TRUE, + memdescCreate(&pMemDesc, pGpu, RM_PAGE_SIZE, 0, NV_TRUE, traceArg.aperture, NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE), portMemFree(pKernBuffer); return status; ); - memdescDescribe(pMemDesc, traceArg.aperture, traceArg.pa, curSize); + memdescDescribe(pMemDesc, traceArg.aperture, traceArg.pa, RM_PAGE_SIZE); } surf.pMemDesc = pMemDesc; @@ -569,6 +569,13 @@ _nv83deCtrlCmdDebugAccessMemory flags = FLD_SET_DRF(OS33, _FLAGS, _MAPPING, _DIRECT, flags); } + // Allow the mapping to happen successfully on HCC devtools mode + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pTargetGpu)) && + gpuIsCCDevToolsModeEnabled(pTargetGpu)) + { + flags = FLD_SET_DRF(OS33, _FLAGS, _ALLOW_MAPPING_ON_HCC, _YES, flags); + } + // Map memory into the internal smdbg client rmStatus = _nv83deMapMemoryIntoGrdbgClient(pTargetGpu, pKernelSMDebuggerSession, @@ -708,7 +715,6 @@ NV_STATUS ksmdbgssnCtrlCmdDebugExecRegOps_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelSMDebuggerSession); - NV_STATUS status = NV_OK; NvBool isClientGspPlugin = NV_FALSE; NV_CHECK_OR_RETURN(LEVEL_ERROR, @@ -722,17 +728,16 @@ NV_STATUS ksmdbgssnCtrlCmdDebugExecRegOps_IMPL if (IS_GSP_CLIENT(pGpu)) { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); - return status; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + return pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); } return NV_ERR_NOT_SUPPORTED; diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c index 3409f3c481..eb350b323e 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c @@ -27,11 +27,10 @@ #include "gpu/gsp/kernel_gsp.h" -#include "gpu/bus/kern_bus.h" #include "gpu/conf_compute/conf_compute.h" +#include "gpu/mem_mgr/rm_page_size.h" #include "nverror.h" #include "rmgspseq.h" -#include "vgpu/rpc.h" #include "published/ampere/ga102/dev_falcon_v4.h" #include "published/ampere/ga102/dev_riscv_pri.h" @@ -63,13 +62,11 @@ kgspConfigureFalcon_GA102 falconConfig.bIsPmcDeviceEngine = NV_FALSE; falconConfig.physEngDesc = ENG_GSP; - ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); // // No CrashCat queue when CC is enabled, as it's not encrypted. - // Don't bother enabling the host-side decoding either, as CrashCat - // currently only supports sysmem queue reporting on GA10x+. + // Don't bother enabling the host-side decoding either. // if (pCC == NULL || !pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) { @@ -77,51 +74,11 @@ kgspConfigureFalcon_GA102 falconConfig.crashcatEngConfig.bEnable = NV_TRUE; falconConfig.crashcatEngConfig.pName = MAKE_NV_PRINTF_STR("GSP"); falconConfig.crashcatEngConfig.errorId = GSP_ERROR; - falconConfig.crashcatEngConfig.allocQueueSize = RM_PAGE_SIZE; } kflcnConfigureEngine(pGpu, staticCast(pKernelGsp, KernelFalcon), &falconConfig); } -/*! - * Reset RISCV using secure reset - * - * @return NV_OK if the RISCV reset was successful. - * Appropriate NV_ERR_xxx value otherwise. - */ -static NV_STATUS -_kgspResetIntoRiscv -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp -) -{ - KernelFalcon *pKernelFlcn = staticCast(pKernelGsp, KernelFalcon); - NV_ASSERT_OK_OR_RETURN(kflcnPreResetWait_HAL(pGpu, pKernelFlcn)); - - GPU_FLD_WR_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET, _TRUE); - - // Reg read cycles needed for signal propagation. - for (NvU32 i = 0; i < FLCN_RESET_PROPAGATION_DELAY_COUNT; i++) - { - GPU_REG_RD32(pGpu, NV_PGSP_FALCON_ENGINE); - } - - GPU_FLD_WR_DRF_DEF(pGpu, _PGSP, _FALCON_ENGINE, _RESET, _FALSE); - - // Reg read cycles needed for signal propagation. - for (NvU32 i = 0; i < FLCN_RESET_PROPAGATION_DELAY_COUNT; i++) - { - GPU_REG_RD32(pGpu, NV_PGSP_FALCON_ENGINE); - } - - NV_ASSERT_OK_OR_RETURN(kflcnWaitForResetToFinish_HAL(pGpu, pKernelFlcn)); - - kflcnRiscvProgramBcr_HAL(pGpu, pKernelFlcn, NV_TRUE); - - return NV_OK; -} - /*! * Determine if GSP reload via SEC2 is completed. */ @@ -139,145 +96,6 @@ _kgspIsReloadCompleted return FLD_TEST_DRF(_PGC6, _BSI_SECURE_SCRATCH_14, _BOOT_STAGE_3_HANDOFF, _VALUE_DONE, reg); } -/*! - * Boot GSP-RM. - * - * This routine handles the following: - * - prepares boot binary image - * - prepares RISCV core to run GSP-RM - * - prepares libos initialization args - * - prepares GSP-RM initialization message - * - starts the RISCV core and passes control to boot binary image - * - waits for GSP-RM to complete initialization - * - * Note that boot binary and GSP-RM images have already been placed - * in fbmem by kgspCalculateFbLayout_HAL(). - * - * Note that this routine is based on flcnBootstrapRiscvOS_GA102(). - * - * @param[in] pGpu GPU object pointer - * @param[in] pKernelGsp GSP object pointer - * @param[in] pGspFw GSP_FIRMWARE image pointer - * - * @return NV_OK if GSP-RM RISCV boot was successful. - * Appropriate NV_ERR_xxx value otherwise. - */ -NV_STATUS -kgspBootstrapRiscvOSEarly_GA102 -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp, - GSP_FIRMWARE *pGspFw -) -{ - KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); - NV_STATUS status = NV_OK; - - // Only for GSP client builds - if (!IS_GSP_CLIENT(pGpu)) - { - NV_PRINTF(LEVEL_ERROR, "IS_GSP_CLIENT is not set.\n"); - return NV_ERR_NOT_SUPPORTED; - } - - if (!kflcnIsRiscvCpuEnabled_HAL(pGpu, pKernelFalcon)) - { - NV_PRINTF(LEVEL_ERROR, "RISC-V core is not enabled.\n"); - return NV_ERR_NOT_SUPPORTED; - } - - kgspPopulateGspRmInitArgs(pGpu, pKernelGsp, NULL); - - { - // Execute FWSEC to setup FRTS if we have a FRTS region - if (kgspGetFrtsSize_HAL(pGpu, pKernelGsp) > 0) - { - kflcnReset_HAL(pGpu, pKernelFalcon); - - NV_ASSERT_OK_OR_GOTO(status, - kgspExecuteFwsecFrts_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode, - pKernelGsp->pWprMeta->frtsOffset), exit); - } - } - - NV_ASSERT_OK_OR_RETURN(_kgspResetIntoRiscv(pGpu, pKernelGsp)); - - // - // Stuff the message queue with async init messages that will be run - // before OBJGPU is created. - // - NV_RM_RPC_GSP_SET_SYSTEM_INFO(pGpu, status); - if (status != NV_OK) - { - NV_ASSERT_OK_FAILED("NV_RM_RPC_GSP_SET_SYSTEM_INFO", status); - goto exit; - } - - NV_RM_RPC_SET_REGISTRY(pGpu, status); - if (status != NV_OK) - { - NV_ASSERT_OK_FAILED("NV_RM_RPC_SET_REGISTRY", status); - goto exit; - } - - // First times setup of libos init args - kgspSetupLibosInitArgs(pGpu, pKernelGsp); - - // Fb configuration is done so setup libos arg list - kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); - - // Execute Scrubber if needed - if (pKernelGsp->pScrubberUcode != NULL) - { - NV_ASSERT_OK_OR_GOTO(status, - kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp), - exit); - } - - RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; - - { - status = kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, - memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Load (ucode for initial boot): 0x%x\n", status); - goto exit; - } - } - - // Program FALCON_OS - kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_OS, pRiscvDesc->appVersion); - - // Ensure the CPU is started - if (kflcnIsRiscvActive_HAL(pGpu, pKernelFalcon)) - { - NV_PRINTF(LEVEL_INFO, "GSP ucode loaded and RISCV started.\n"); - } - else - { - NV_ASSERT_FAILED("Failed to boot GSP"); - status = NV_ERR_NOT_READY; - goto exit; - } - - NV_PRINTF(LEVEL_INFO, "Waiting for GSP fw RM to be ready...\n"); - - // Link the status queue. - NV_ASSERT_OK_OR_GOTO(status, GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo), - exit); - - NV_ASSERT_OK_OR_GOTO(status, kgspWaitForRmInitDone(pGpu, pKernelGsp), - exit); - - NV_PRINTF(LEVEL_INFO, "GSP FW RM ready.\n"); - -exit: - NV_ASSERT(status == NV_OK); - - return status; -} - void kgspGetGspRmBootUcodeStorage_GA102 ( @@ -335,34 +153,32 @@ kgspExecuteSequencerCommand_GA102 NV_ASSERT_OR_RETURN(payloadSize == 0, NV_ERR_INVALID_ARGUMENT); - { - KernelFalcon *pKernelSec2Falcon = staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); - - pKernelGsp->bLibosLogsPollingEnabled = NV_FALSE; + KernelFalcon *pKernelSec2Falcon = staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); - NV_ASSERT_OK_OR_RETURN(_kgspResetIntoRiscv(pGpu, pKernelGsp)); - kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); + pKernelGsp->bLibosLogsPollingEnabled = NV_FALSE; - NV_PRINTF(LEVEL_INFO, "---------------Starting SEC2 to resume GSP-RM------------\n"); - // Start SEC2 in order to resume GSP-RM - kflcnStartCpu_HAL(pGpu, pKernelSec2Falcon); + kflcnResetIntoRiscv_HAL(pGpu, pKernelFalcon); + kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); - // Wait for reload to be completed. - status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); + NV_PRINTF(LEVEL_INFO, "---------------Starting SEC2 to resume GSP-RM------------\n"); + // Start SEC2 in order to resume GSP-RM + kflcnStartCpu_HAL(pGpu, pKernelSec2Falcon); - // Check SEC mailbox. - secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); + // Wait for reload to be completed. + status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); - if ((status != NV_OK) || (secMailbox0 != NV_OK)) - { - NV_PRINTF(LEVEL_ERROR, "Timeout waiting for SEC2-RTOS to resume GSP-RM. SEC2 Mailbox0 is : 0x%x\n", secMailbox0); - DBG_BREAKPOINT(); - return NV_ERR_TIMEOUT; - } + // Check SEC mailbox. + secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); - pKernelGsp->bLibosLogsPollingEnabled = NV_TRUE; + if ((status != NV_OK) || (secMailbox0 != NV_OK)) + { + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for SEC2-RTOS to resume GSP-RM. SEC2 Mailbox0 is : 0x%x\n", secMailbox0); + DBG_BREAKPOINT(); + return NV_ERR_TIMEOUT; } + pKernelGsp->bLibosLogsPollingEnabled = NV_TRUE; + // Program FALCON_OS kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_OS, pRiscvDesc->appVersion); diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c index ea701b3d9c..94e97172ed 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c @@ -27,15 +27,18 @@ #include "rmconfig.h" #include "gpu/conf_compute/conf_compute.h" +#include "spdm/rmspdmtransport.h" #include "gpu/fsp/kern_fsp.h" #include "gpu/gsp/kernel_gsp.h" #include "gpu/mem_sys/kern_mem_sys.h" #include "gsp/gspifpub.h" #include "vgpu/rpc.h" +#include "os/os.h" #include "published/hopper/gh100/dev_falcon_v4.h" #include "published/hopper/gh100/dev_gsp.h" #include "published/hopper/gh100/dev_riscv_pri.h" +#include "published/hopper/gh100/dev_vm.h" #define RISCV_BR_ADDR_ALIGNMENT (8) @@ -412,6 +415,32 @@ kgspSetupGspFmcArgs_GH100 pGspFmcBootParams->gspRmParams.bootArgsOffset = memdescGetPhysAddr(pKernelGsp->pLibosInitArgumentsDescriptor, AT_GPU, 0); pGspFmcBootParams->gspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pLibosInitArgumentsDescriptor); + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_SPDM_ENABLED)) + { + NV_STATUS status = NV_OK; + Spdm *pSpdm = pCC->pSpdm; + + // If SPDM is NULL, we failed to initialize + if (pCC->pSpdm == NULL) + { + return NV_ERR_INVALID_STATE; + } + + // Perform required pre-GSP-RM boot setup that could not be done on Spdm object creation. + status = spdmSetupCommunicationBuffers(pGpu, pSpdm); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failure when initializing SPDM messaging infrastructure. Status:0x%x\n", status); + return status; + } + + // Target will always be GSP_DMA_TARGET_COHERENT_SYSTEM + pGspFmcBootParams->gspSpdmParams.target = GSP_DMA_TARGET_COHERENT_SYSTEM; + pGspFmcBootParams->gspSpdmParams.payloadBufferOffset = memdescGetPhysAddr(pSpdm->pPayloadBufferMemDesc, + AT_GPU, 0); + pGspFmcBootParams->gspSpdmParams.payloadBufferSize = pSpdm->payloadBufferSize; + } + return NV_OK; } @@ -434,8 +463,113 @@ _kgspIsLockdownReleased _UNLOCK, reg); } +/*! + * Determine if SPDM partition has booted. + */ +static NvBool +_kgspHasSpdmBooted +( + OBJGPU *pGpu, + void *pVoid +) +{ + NvU32 spdmBootStatus = 0; + KernelFalcon *pKernelFalcon = (KernelFalcon *)pVoid; + + spdmBootStatus = kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0); + + return (spdmBootStatus == NV_SPDM_PARTITION_BOOT_SUCCESS); +} + +/*! + * Establish session with SPDM Responder on GSP in Confidential Compute scenario. + * GSP-RM boot is blocked until session establishment completes. + * + * NOTE: This function currently requires the API lock (for at least the async init + * RPCs and libspdm synchronization) and as such does NOT support parallel init. + */ +static NV_STATUS +_kgspEstablishSpdmSession +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + ConfidentialCompute *pConfCompute +) +{ + NV_STATUS status = NV_OK; + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + + // Ensure SPDM Responder has booted before attempting to establish session. + status = gpuTimeoutCondWait(pGpu, _kgspHasSpdmBooted, (void *)pKernelFalcon, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for SPDM Responder to initialize!\n"); + goto exit; + } + + status = confComputeEstablishSpdmSessionAndKeys_HAL(pGpu, pConfCompute); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM handshake with Responder failed.\n"); + goto exit; + } + + // + // Now we can send the async init messages that will be run before OBJGPU is created. + // SPDM will not continue with boot until we send ack after sending these RPCs, else + // we create a race condition where GSP-RM may skip these RPCs if not sent in time. + // + status = kgspQueueAsyncInitRpcs(pGpu, pKernelGsp); + if (status != NV_OK) + { + goto exit; + } + // Tell SPDM that it can continue with boot + kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0, NV_SPDM_REQUESTER_SECRETS_DERIVED); +exit: + if (status != NV_OK) + { + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + + NV_PRINTF(LEVEL_ERROR, "Failed to establish session with SPDM Responder!\n"); + if (pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM)) + { + kfspDumpDebugState_HAL(pGpu, pKernelFsp); + } + NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_MAILBOX0 = 0x%x\n", + kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0)); + NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_MAILBOX1 = 0x%x\n", + kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1)); + } + + return status; +} + +/*! + * Determine if GSP has performed CC partition cleanup. + * Success or failure will be determined by the value in Mailbox1 + */ +static NvBool +_kgspHasCcCleanupFinished +( + OBJGPU *pGpu, + void *pVoid +) +{ + NvU32 ccCleanupStatus = 0; + KernelFalcon *pKernelFalcon = (KernelFalcon *)pVoid; + + ccCleanupStatus = kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1); + + // + // To avoid a timing issue and issues with pre-existing values in Mailbox1 + // we check for explicit success or failure statuses. + // + return (ccCleanupStatus == NV_SPDM_SECRET_TEARDOWN_SUCCESS || + ccCleanupStatus == NV_SPDM_SECRET_TEARDOWN_FAILURE); +} static void _kgspBootstrapGspFmc_GH100 @@ -498,36 +632,30 @@ _kgspBootstrapGspFmc_GH100 } /*! - * Boot GSP-RM. + * Prepare to boot GSP-RM * - * This routine handles the following: - * - prepares RISCV core to run GSP-RM - * - prepares libos initialization args - * - prepares GSP-RM initialization message - * - starts the RISCV core and passes control to boot binary image - * - waits for GSP-RM to complete initialization - * - * Note that this routine is based on flcnBootstrapRiscvOS_GA102(). + * This routine handles the prequesites to booting GSP-RM that requires the API LOCK: + * - Clear ECC errors + * - Prepare GSP-FMC arguments + * - Prepare FSP boot commands * * @param[in] pGpu GPU object pointer * @param[in] pKernelGsp GSP object pointer * @param[in] pGspFw GSP_FIRMWARE image pointer * - * @return NV_OK if GSP-RM RISCV boot was successful. + * @return NV_OK if GSP-RM RISCV preparation to boot was successful. * Appropriate NV_ERR_xxx value otherwise. */ NV_STATUS -kgspBootstrapRiscvOSEarly_GH100 +kgspPrepareForBootstrap_GH100 ( OBJGPU *pGpu, KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw ) { - KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); - KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; // Only for GSP client builds if (!IS_GSP_CLIENT(pGpu)) @@ -537,50 +665,68 @@ kgspBootstrapRiscvOSEarly_GH100 } // Clear ECC errors before attempting to load GSP - status = kmemsysClearEccCounts_HAL(pGpu, pKernelMemorySystem); + status = gpuClearEccCounts_HAL(pGpu); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Issue clearing ECC counts! Status:0x%x\n", status); } // Setup the descriptors that GSP-FMC needs to boot GSP-RM - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw), exit); - - kgspSetupLibosInitArgs(pGpu, pKernelGsp); - - // Fill in the GSP-RM message queue init parameters - kgspPopulateGspRmInitArgs(pGpu, pKernelGsp, NULL); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw)); - // - // Stuff the message queue with async init messages that will be run - // before OBJGPU is created. - // - NV_RM_RPC_GSP_SET_SYSTEM_INFO(pGpu, status); - if (status != NV_OK) + if (pKernelFsp != NULL && !pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) { - NV_ASSERT_OK_FAILED("NV_RM_RPC_GSP_SET_SYSTEM_INFO", status); - goto exit; + pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM, NV_TRUE); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kfspPrepareBootCommands_HAL(pGpu, pKernelFsp)); } - - NV_RM_RPC_SET_REGISTRY(pGpu, status); - if (status != NV_OK) + else { - NV_ASSERT_OK_FAILED("NV_RM_RPC_SET_REGISTRY", status); - goto exit; + _kgspBootstrapGspFmc_GH100(pGpu, pKernelGsp); } + return NV_OK; +} + +/*! + * Boot GSP-RM. + * + * This routine handles the following: + * - sends FSP boot commands + * - waits for GSP-RM to complete initialization + * + * Note that this routine is based on flcnBootstrapRiscvOS_GA102(). + * + * Note that this routine can be called without the API lock for + * parllel initialization. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelGsp GSP object pointer + * @param[in] pGspFw GSP_FIRMWARE image pointer + * + * @return NV_OK if GSP-RM RISCV boot was successful. + * Appropriate NV_ERR_xxx value otherwise. + */ +NV_STATUS +kgspBootstrap_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw +) +{ + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu); + NV_STATUS status = NV_OK; + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pKernelFsp != NULL && !pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_GSPFMC)) { NV_PRINTF(LEVEL_NOTICE, "Starting to boot GSP via FSP.\n"); - pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM, NV_TRUE); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kfspSendBootCommands_HAL(pGpu, pKernelFsp), exit); } - else - { - _kgspBootstrapGspFmc_GH100(pGpu, pKernelGsp); - } // Wait for target mask to be released. if (pKernelFsp != NULL) @@ -602,6 +748,27 @@ kgspBootstrapRiscvOSEarly_GH100 } } + // + // In Confidential Compute, SPDM session will be established before GSP-RM boots. + // Wait until after target mask is released by ACR to minimize busy wait time. + // NOTE: This is incompatible with parallel initialization. See function + // description for more details. + // + if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + if (!rmapiLockIsOwner()) + { + NV_ASSERT(0); + status = NV_ERR_INVALID_LOCK_STATE; + goto exit; + } + status = _kgspEstablishSpdmSession(pGpu, pKernelGsp, pCC); + if (status != NV_OK) + { + goto exit; + } + } + // Wait for lockdown to be released. status = gpuTimeoutCondWait(pGpu, _kgspIsLockdownReleased, pKernelGsp, NULL); if (status != NV_OK) @@ -656,7 +823,12 @@ kgspBootstrapRiscvOSEarly_GH100 // If GSP fails to boot, check if there's any DED error. if (status != NV_OK) { - kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem); + if (pKernelFsp != NULL) + { + kfspCleanupBootState(pGpu, pKernelFsp); + } + + gpuCheckEccCounts_HAL(pGpu); } NV_ASSERT(status == NV_OK); @@ -693,3 +865,133 @@ kgspGetGspRmBootUcodeStorage_GH100 } kgspGetGspRmBootUcodeStorage_GA102(pGpu, pKernelGsp, ppBinStorageImage, ppBinStorageDesc); } + +NV_STATUS +kgspIssueNotifyOp_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + NvU32 opCode, + NvU32 *pArgs, + NvU32 argc +) +{ + NV_STATUS status = NV_OK; + NotifyOpSharedSurface *pNotifyOpSharedSurface; + volatile NvU32 *pInUse; + volatile NvU32 *pSeqAddr; + volatile NvU32 *pStatusAddr; + NvU32 *pOpCodeAddr; + NvU32 *pArgsAddr; + NvU32 *pArgcAddr; + + NvU32 seqValue; + NvU32 i; + RMTIMEOUT timeout; + + // 1. Validate the arguments. + NV_CHECK_OR_RETURN(LEVEL_ERROR, opCode < GSP_NOTIFY_OP_OPCODE_MAX, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, argc <= GSP_NOTIFY_OP_MAX_ARGUMENT_COUNT, NV_ERR_INVALID_ARGUMENT); + NV_CHECK_OR_RETURN(LEVEL_ERROR, (argc == 0 || pArgs != NULL), NV_ERR_INVALID_ARGUMENT); + + // 2. Set up ptrs to the shared memory. + NV_ASSERT_OR_RETURN(pKernelGsp->pNotifyOpSurf != NULL, NV_ERR_INVALID_STATE); + + pNotifyOpSharedSurface = pKernelGsp->pNotifyOpSurf; + + pInUse = (NvU32*) &(pNotifyOpSharedSurface->inUse); + pSeqAddr = (NvU32*) &(pNotifyOpSharedSurface->seqNum); + pOpCodeAddr = (NvU32*) &(pNotifyOpSharedSurface->opCode); + pStatusAddr = (NvU32*) &(pNotifyOpSharedSurface->status); + pArgcAddr = (NvU32*) &(pNotifyOpSharedSurface->argc); + pArgsAddr = (NvU32*) pNotifyOpSharedSurface->args; + + while (!portAtomicCompareAndSwapU32(pInUse, 1, 0)) + { + // We're not going to sleep, but safe to sleep also means safe to spin.. + NV_ASSERT_OR_RETURN(portSyncExSafeToSleep(), NV_ERR_INVALID_STATE); + osSpinLoop(); + } + + // 3. Read current sequence counter value. + seqValue = *pSeqAddr; + + // 4. Populate the opcode and arguments. + *pOpCodeAddr = opCode; + *pArgcAddr = argc; + for (i = 0; i < argc; i++) + { + pArgsAddr[i] = pArgs[i]; + } + + // + // Issue a store fence to ensure that the parameters have made it to memory + // before the interrupt is triggered. + // + portAtomicMemoryFenceStore(); + + // 5. Trigger notification interrupt to GSP. + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_DOORBELL, NV_DOORBELL_NOTIFY_LEAF_SERVICE_LOCKLESS_OP_HANDLE); + + // 6. Poll on the sequence number to ensure the op completed. + while (seqValue + 1 != *pSeqAddr) + { + status = gpuCheckTimeout(pGpu, &timeout); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "gpuCheckTimeout failed, status = 0x%x\n", status); + goto error_ret; + } + osSpinLoop(); + } + + status = *pStatusAddr; + +error_ret: + portAtomicSetU32(pInUse, 0); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); + return status; +} + +NV_STATUS +kgspCheckGspRmCcCleanup_GH100 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + NvU32 ccCleanupStatus = 0; + NV_STATUS status = NV_OK; + + // Wait for GSP to explicitly state we have completed CC cleanup. + status = gpuTimeoutCondWait(pGpu, _kgspHasCcCleanupFinished, (void *)pKernelFalcon, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "CC secret cleanup failed due to timeout!\n"); + goto exit; + } + + // Now, check whether or not CC cleanup was successful. + ccCleanupStatus = kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1); + if (ccCleanupStatus == NV_SPDM_SECRET_TEARDOWN_SUCCESS) + { + // FIPS: Make status clear to user. + NV_PRINTF(LEVEL_ERROR, "CC secret cleanup successful!\n"); + } + else + { + NV_PRINTF(LEVEL_ERROR, "CC secret cleanup failed! Status 0x%x\n", + ccCleanupStatus); + } + +exit: + + // Regardless of success or failure, write ack to GSP. + kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1, NV_SPDM_SECRET_TEARDOWN_ACK); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c index 484945bbff..646d06f4be 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c @@ -261,22 +261,24 @@ s_vbiosPatchInterfaceData } /*! - * Excecute a given FWSEC cmd and wait for completion. + * Prepare to execute a given FWSEC cmd. * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelGsp KernelGsp pointer * @param[in] pFwsecUcode KernelGspFlcnUcode structure of FWSEC ucode * @param[in] cmd FWSEC cmd (FRTS or SB) * @param[in] frtsOffset (if cmd is FRTS) desired FB offset of FRTS data + * @param[out] pPreparedCmd Prepared command state to pass to kgspExecuteFwsec_TU102 */ static NV_STATUS -s_executeFwsec_TU102 +s_prepareForFwsec_TU102 ( OBJGPU *pGpu, KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, const NvU32 cmd, - const NvU64 frtsOffset + const NvU64 frtsOffset, + KernelGspPreparedFwsecCmd *pPreparedCmd ) { NV_STATUS status; @@ -291,6 +293,7 @@ s_executeFwsec_TU102 NV_ASSERT_OR_RETURN(IS_GSP_CLIENT(pGpu), NV_ERR_NOT_SUPPORTED); NV_ASSERT_OR_RETURN(pFwsecUcode != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pPreparedCmd != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN((cmd != FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS) || (frtsOffset > 0), NV_ERR_INVALID_ARGUMENT); @@ -301,6 +304,10 @@ s_executeFwsec_TU102 return NV_ERR_INVALID_ARGUMENT; } + pPreparedCmd->pFwsecUcode = pFwsecUcode; + pPreparedCmd->cmd = cmd; + pPreparedCmd->frtsOffset = frtsOffset; + readVbiosDesc.version = 1; readVbiosDesc.size = sizeof(readVbiosDesc); readVbiosDesc.gfwImageOffset = 0; @@ -434,16 +441,49 @@ s_executeFwsec_TU102 return NV_ERR_NOT_SUPPORTED; } - status = kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, pFwsecUcode, +out: + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "(note: VBIOS version %s)\n", pKernelGsp->vbiosVersionStr); + } + + return status; +} + +/*! + * Execute a given FWSEC cmd and wait for completion. + * KernelGspPreparedFwsecCmd should be set by s_prepareForFwsec_TU102 and + * not filled in manually + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGsp KernelGsp pointer + * @param[in] pPreparedCmd Prepared command state from s_prepareForFwsec_TU102 + */ +NV_STATUS +kgspExecuteFwsec_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + KernelGspPreparedFwsecCmd *pPreparedCmd +) +{ + NV_STATUS status; + + NV_ASSERT_OR_RETURN(!IS_VIRTUAL(pGpu), NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN(IS_GSP_CLIENT(pGpu), NV_ERR_NOT_SUPPORTED); + + NV_ASSERT_OR_RETURN(pPreparedCmd != NULL, NV_ERR_INVALID_ARGUMENT); + + status = kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, pPreparedCmd->pFwsecUcode, staticCast(pKernelGsp, KernelFalcon), NULL, NULL); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC cmd 0x%x: status 0x%x\n", cmd, status); + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC cmd 0x%x: status 0x%x\n", pPreparedCmd->cmd, status); goto out; } - if (cmd == FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS) + if (pPreparedCmd->cmd == FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS) { NvU32 data; NvU32 frtsErrCode; @@ -471,7 +511,7 @@ s_executeFwsec_TU102 data = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_WPR2_ADDR_LO); wpr2LoVal = DRF_VAL(_PFB, _PRI_MMU_WPR2_ADDR_LO, _VAL, data); - expectedLoVal = (NvU32) (frtsOffset >> NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT); + expectedLoVal = (NvU32) (pPreparedCmd->frtsOffset >> NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT); if (wpr2LoVal != expectedLoVal) { NV_PRINTF(LEVEL_ERROR, @@ -522,41 +562,47 @@ s_executeFwsec_TU102 } /*! - * Excecute FWSEC for FRTS and wait for completion. + * Prepare to execute FWSEC FRTS ucode to setup FRTS * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelGsp KernelGsp pointer * @param[in] pFwsecUcode KernelGspFlcnUcode structure of FWSEC ucode * @param[in] frtsOffset Desired offset in FB of FRTS data and WPR2 + * @param[out] pPreparedCmd Prepared command state to pass to kgspExecuteFwsec_TU102 */ NV_STATUS -kgspExecuteFwsecFrts_TU102 +kgspPrepareForFwsecFrts_TU102 ( OBJGPU *pGpu, KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, - const NvU64 frtsOffset + const NvU64 frtsOffset, + KernelGspPreparedFwsecCmd *pPreparedCmd ) { - return s_executeFwsec_TU102(pGpu, pKernelGsp, pFwsecUcode, - FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS, frtsOffset); + return s_prepareForFwsec_TU102(pGpu, pKernelGsp, pFwsecUcode, + FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS, + frtsOffset, pPreparedCmd); } /*! - * Excecute FWSEC's SB command and wait for completion. + * Prepare to execute FWSEC SB ucode to setup FRTS * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelGsp KernelGsp pointer * @param[in] pFwsecUcode KernelGspFlcnUcode structure of FWSEC ucode + * @param[out] pPreparedCmd Prepared command state to pass to kgspExecuteFwsec_TU102 */ NV_STATUS -kgspExecuteFwsecSb_TU102 +kgspPrepareForFwsecSb_TU102 ( OBJGPU *pGpu, KernelGsp *pKernelGsp, - KernelGspFlcnUcode *pFwsecUcode + KernelGspFlcnUcode *pFwsecUcode, + KernelGspPreparedFwsecCmd *pPreparedCmd ) { - return s_executeFwsec_TU102(pGpu, pKernelGsp, pFwsecUcode, - FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB, 0); -} + return s_prepareForFwsec_TU102(pGpu, pKernelGsp, pFwsecUcode, + FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB, + 0, pPreparedCmd); +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c index bc43f498c9..7601ceef49 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c @@ -27,7 +27,6 @@ #include "gpu/gsp/kernel_gsp.h" -#include "gpu/bus/kern_bus.h" #include "gpu/disp/kern_disp.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_sys/kern_mem_sys.h" @@ -53,12 +52,6 @@ #include "gpu/sec2/kernel_sec2.h" -#define RPC_STRUCTURES -#define RPC_GENERIC_UNION -#include "g_rpc-structures.h" -#undef RPC_STRUCTURES -#undef RPC_GENERIC_UNION - void kgspConfigureFalcon_TU102 ( @@ -337,16 +330,35 @@ kgspProgramLibosBootArgsAddr_TU102 GPU_REG_WR32(pGpu, NV_PGSP_FALCON_MAILBOX1, NvU64_HI32(addr)); } +/*! + * Prepare to boot GSP-RM + * + * This routine handles the prerequisites to booting GSP-RM that requires the API LOCK: + * - prepares boot binary image + * - prepares RISCV core to run GSP-RM + * + * Note that boot binary and GSP-RM images have already been placed + * in fbmem by kgspCalculateFbLayout_HAL(). + * + * Note that this routine is based on flcnBootstrapRiscvOS_GA102(). + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelGsp GSP object pointer + * @param[in] pGspFw GSP_FIRMWARE image pointer + * + * @return NV_OK if GSP-RM RISCV boot was successful. + * Appropriate NV_ERR_xxx value otherwise. + */ NV_STATUS -kgspBootstrapRiscvOSEarly_TU102 +kgspPrepareForBootstrap_TU102 ( OBJGPU *pGpu, KernelGsp *pKernelGsp, GSP_FIRMWARE *pGspFw ) { - NV_STATUS status = NV_OK; - KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + NV_STATUS status; + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); // Only for GSP client builds if (!IS_GSP_CLIENT(pGpu)) @@ -361,49 +373,73 @@ kgspBootstrapRiscvOSEarly_TU102 return NV_ERR_NOT_SUPPORTED; } - // - // Setup for libos bootloader execution including reserving space in the - // fb for placement and bootloader args initialization. - // - kgspPopulateGspRmInitArgs(pGpu, pKernelGsp, NULL); - + // Prepare to execute FWSEC to setup FRTS if we have a FRTS region + if (kgspGetFrtsSize_HAL(pGpu, pKernelGsp) > 0) { - // Execute FWSEC to setup FRTS if we have a FRTS region - if (kgspGetFrtsSize_HAL(pGpu, pKernelGsp) > 0) + pKernelGsp->pPreparedFwsecCmd = portMemAllocNonPaged(sizeof(KernelGspPreparedFwsecCmd)); + status = kgspPrepareForFwsecFrts_HAL(pGpu, pKernelGsp, + pKernelGsp->pFwsecUcode, + pKernelGsp->pWprMeta->frtsOffset, + pKernelGsp->pPreparedFwsecCmd); + if (status != NV_OK) { - kflcnReset_HAL(pGpu, pKernelFalcon); - - NV_ASSERT_OK_OR_GOTO(status, - kgspExecuteFwsecFrts_HAL(pGpu, - pKernelGsp, - pKernelGsp->pFwsecUcode, - pKernelGsp->pWprMeta->frtsOffset), - exit); + portMemFree(pKernelGsp->pPreparedFwsecCmd); + pKernelGsp->pPreparedFwsecCmd = NULL; + return status; } } - kflcnReset_HAL(pGpu, pKernelFalcon); + return NV_OK; +} - // - // Stuff the message queue with async init messages that will be run - // before OBJGPU is created. - // - NV_RM_RPC_GSP_SET_SYSTEM_INFO(pGpu, status); - if (status != NV_OK) - { - NV_ASSERT_OK_FAILED("NV_RM_RPC_GSP_SET_SYSTEM_INFO", status); - goto exit; - } +/*! + * Boot GSP-RM. + * + * This routine handles the following: + * - starts the RISCV core and passes control to boot binary image + * - waits for GSP-RM to complete initialization + * + * Note that boot binary and GSP-RM images have already been placed + * in fbmem by kgspCalculateFbLayout_HAL(). + * + * Note that this routine is based on flcnBootstrapRiscvOS_GA102(). + * + * Note that this routine can be called without the API lock for + * parllel initialization. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelGsp GSP object pointer + * @param[in] pGspFw GSP_FIRMWARE image pointer + * + * @return NV_OK if GSP-RM RISCV boot was successful. + * Appropriate NV_ERR_xxx value otherwise. + */ +NV_STATUS +kgspBootstrap_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + GSP_FIRMWARE *pGspFw +) +{ + NV_STATUS status; + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); - NV_RM_RPC_SET_REGISTRY(pGpu, status); - if (status != NV_OK) + // Execute FWSEC to setup FRTS if we have a FRTS region + if (kgspGetFrtsSize_HAL(pGpu, pKernelGsp) > 0) { - NV_ASSERT_OK_FAILED("NV_RM_RPC_SET_REGISTRY", status); - goto exit; + NV_ASSERT_OR_RETURN(pKernelGsp->pPreparedFwsecCmd != NULL, NV_ERR_INVALID_STATE); + + kflcnReset_HAL(pGpu, pKernelFalcon); + + status = kgspExecuteFwsec_HAL(pGpu, pKernelGsp, pKernelGsp->pPreparedFwsecCmd); + portMemFree(pKernelGsp->pPreparedFwsecCmd); + pKernelGsp->pPreparedFwsecCmd = NULL; + + NV_ASSERT_OK_OR_RETURN(status); } - // Initialize libos init args list - kgspSetupLibosInitArgs(pGpu, pKernelGsp); + kflcnResetIntoRiscv_HAL(pGpu, pKernelFalcon); // Load init args into mailbox regs kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); @@ -411,21 +447,22 @@ kgspBootstrapRiscvOSEarly_TU102 // Execute Scrubber if needed if (pKernelGsp->pScrubberUcode != NULL) { - NV_ASSERT_OK_OR_GOTO(status, - kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp), - exit); + NV_ASSERT_OK_OR_RETURN(kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp)); } + // Execute Booter Load + status = kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, + memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0)); + if (status != NV_OK) { - status = kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, - memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0)); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Load (ucode for initial boot): 0x%x\n", status); - goto exit; - } + NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Load (ucode for initial boot): 0x%x\n", status); + return status; } + // Program FALCON_OS + RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; + kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_OS, pRiscvDesc->appVersion); + // Ensure the CPU is started if (kflcnIsRiscvActive_HAL(pGpu, pKernelFalcon)) { @@ -435,25 +472,19 @@ kgspBootstrapRiscvOSEarly_TU102 { NV_PRINTF(LEVEL_ERROR, "Failed to boot GSP.\n"); - status = NV_ERR_NOT_READY; - goto exit; + return NV_ERR_NOT_READY; } NV_PRINTF(LEVEL_INFO, "Waiting for GSP fw RM to be ready...\n"); // Link the status queue. - NV_ASSERT_OK_OR_GOTO(status, - GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo), - exit); + NV_ASSERT_OK_OR_RETURN(GspStatusQueueInit(pGpu, &pKernelGsp->pRpc->pMessageQueueInfo)); - NV_ASSERT_OK_OR_GOTO(status, - kgspWaitForRmInitDone(pGpu, pKernelGsp), - exit); + NV_ASSERT_OK_OR_RETURN(kgspWaitForRmInitDone(pGpu, pKernelGsp)); NV_PRINTF(LEVEL_INFO, "GSP FW RM ready.\n"); -exit: - return status; + return NV_OK; } void @@ -706,28 +737,26 @@ kgspExecuteSequencerCommand_TU102 { case GSP_SEQ_BUF_OPCODE_CORE_RESUME: { - { - KernelFalcon *pKernelSec2Falcon = staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); + KernelFalcon *pKernelSec2Falcon = staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); - kflcnSecureReset_HAL(pGpu, pKernelFalcon); - kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); + kflcnReset_HAL(pGpu, pKernelFalcon); + kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); - NV_PRINTF(LEVEL_INFO, "---------------Starting SEC2 to resume GSP-RM------------\n"); - // Start SEC2 in order to resume GSP-RM - kflcnStartCpu_HAL(pGpu, pKernelSec2Falcon); + NV_PRINTF(LEVEL_INFO, "---------------Starting SEC2 to resume GSP-RM------------\n"); + // Start SEC2 in order to resume GSP-RM + kflcnStartCpu_HAL(pGpu, pKernelSec2Falcon); - // Wait for reload to be completed. - status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); + // Wait for reload to be completed. + status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); - // Check SEC mailbox. - secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); + // Check SEC mailbox. + secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); - if ((status != NV_OK) || (secMailbox0 != NV_OK)) - { - NV_PRINTF(LEVEL_ERROR, "Timeout waiting for SEC2-RTOS to resume GSP-RM. SEC2 Mailbox0 is : 0x%x\n", secMailbox0); - DBG_BREAKPOINT(); - return NV_ERR_TIMEOUT; - } + if ((status != NV_OK) || (secMailbox0 != NV_OK)) + { + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for SEC2-RTOS to resume GSP-RM. SEC2 Mailbox0 is : 0x%x\n", secMailbox0); + DBG_BREAKPOINT(); + return NV_ERR_TIMEOUT; } // Ensure the CPU is started @@ -804,13 +833,9 @@ kgspHealthCheck_TU102 { bHealthy = NV_FALSE; - pKernelGsp->bFatalError = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, "****************************** GSP-CrashCat Report *******************************\n"); crashcatReportLog(pReport); - NV_PRINTF(LEVEL_ERROR, - "**********************************************************************************\n"); objDelete(pReport); } @@ -828,9 +853,8 @@ kgspHealthCheck_TU102 { NvU32 mb1 = GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(1)); NvU32 skipped = DRF_VAL(_GSP, _ERROR, _SKIPPED, mb0); - bHealthy = NV_FALSE; - pKernelGsp->bFatalError = NV_TRUE; + bHealthy = NV_FALSE; // Clear the mailbox GPU_REG_WR32(pGpu, NV_PGSP_MAILBOX(0), 0); @@ -838,14 +862,8 @@ kgspHealthCheck_TU102 NV_PRINTF(LEVEL_ERROR, "********************************* GSP Failure **********************************\n"); - nvErrorLog_va((void*)pGpu, GSP_ERROR, - "GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x. The GPU likely needs to be reset.", - DRF_VAL(_GSP, _ERROR, _TASK, mb0), - DRF_VAL(_GSP, _ERROR, _CODE, mb0), - DRF_VAL(_GSP, _ERROR, _REASON, mb0), - mb1); - NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, NV_PRINTF_ADD_PREFIX - ("GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x"), + NV_ERROR_LOG(pGpu, GSP_ERROR, + "GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x. The GPU likely needs to be reset.", DRF_VAL(_GSP, _ERROR, _TASK, mb0), DRF_VAL(_GSP, _ERROR, _CODE, mb0), DRF_VAL(_GSP, _ERROR, _REASON, mb0), @@ -856,16 +874,20 @@ kgspHealthCheck_TU102 { NV_PRINTF(LEVEL_ERROR, "%d more errors skipped\n", skipped); } - - NV_PRINTF(LEVEL_ERROR, - "********************************************************************************\n"); } exit_health_check: if (!bHealthy) { - KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem); + pKernelGsp->bFatalError = NV_TRUE; + + if (pKernelGsp->pRpc) + kgspLogRpcDebugInfo(pGpu, pKernelGsp->pRpc, GSP_ERROR, pKernelGsp->bPollingForRpcResponse); + + gpuCheckEccCounts_HAL(pGpu); + + NV_PRINTF(LEVEL_ERROR, + "**********************************************************************************\n"); } return bHealthy; } @@ -979,9 +1001,6 @@ kgspIsWpr2Up_TU102 return (wpr2HiVal != 0); } -#define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms -#define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s - NV_STATUS kgspWaitForGfwBootOk_TU102 ( @@ -989,51 +1008,16 @@ kgspWaitForGfwBootOk_TU102 KernelGsp *pKernelGsp ) { - NvU32 timeoutUs = FWSECLIC_PROG_START_TIMEOUT + FWSECLIC_PROG_COMPLETE_TIMEOUT; - RMTIMEOUT timeout; NV_STATUS status = NV_OK; - // Use the OS timer since the GPU timer is not ready yet - gpuSetTimeout(pGpu, gpuScaleTimeout(pGpu, timeoutUs), &timeout, - GPU_TIMEOUT_FLAGS_OSTIMER); - - while (status == NV_OK) + status = gpuWaitForGfwBootComplete_HAL(pGpu); + if (status != NV_OK) { - // - // Before reading the actual GFW_BOOT status register, - // we want to check that FWSEC has lowered its PLM first. - // If not then obviously it has not completed. - // - if (GPU_FLD_TEST_DRF_DEF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK, - _READ_PROTECTION_LEVEL0, - _ENABLE) - ) - { - if (GPU_FLD_TEST_DRF_DEF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, - _PROGRESS, - _COMPLETED) - ) - { - return NV_OK; - } - } - - status = gpuCheckTimeout(pGpu, &timeout); + NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW boot complete: 0x%x VBIOS version %s\n", + status, pKernelGsp->vbiosVersionStr); + NV_PRINTF(LEVEL_ERROR, "(the GPU may be in a bad state and may need to be reset)\n"); } - // The wait failed if we reach here (as above loop returns upon success). - NV_PRINTF(LEVEL_ERROR, "failed to wait for GFW_BOOT: 0x%x (progress 0x%x, VBIOS version %s)\n", - status, GPU_REG_RD_DRF(pGpu, - _PGC6, - _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, - _PROGRESS), - pKernelGsp->vbiosVersionStr); - NV_PRINTF(LEVEL_ERROR, "(the GPU may be in a bad state and may need to be reset)\n"); - return status; } @@ -1159,3 +1143,36 @@ kgspRestorePowerMgmtState_TU102 kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); return nvStatus; } + +void +kgspReadEmem_TU102 +( + KernelGsp *pKernelGsp, + NvU64 offset, + NvU64 size, + void *pBuf +) +{ + NvU32 ememMask = DRF_SHIFTMASK(NV_PGSP_EMEMC_OFFS) | DRF_SHIFTMASK(NV_PGSP_EMEMC_BLK); + OBJGPU *pGpu = ENG_GET_GPU(pKernelGsp); + NvU32 limit = size - NVBIT(DRF_SHIFT(NV_PGSP_EMEMC_OFFS)); + NvU32 *pBuffer = pBuf; + + portMemSet(pBuf, 0, size); + +#if defined(DEBUG) || defined(DEVELOP) + NV_ASSERT_OR_RETURN_VOID((offset & ~ememMask) == 0); + NV_ASSERT_OR_RETURN_VOID(limit <= ememMask); + NV_ASSERT_OR_RETURN_VOID(offset + limit <= ememMask); +#else + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, (offset & ~ememMask) == 0); + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, limit <= ememMask); + NV_CHECK_OR_RETURN_VOID(LEVEL_SILENT, offset + limit <= ememMask); +#endif + + GPU_REG_WR32(pGpu, NV_PGSP_EMEMC(pKernelGsp->ememPort), + offset | DRF_DEF(_PGSP, _EMEMC, _AINCR, _TRUE)); + + for (NvU32 idx = 0; idx < size / sizeof(NvU32); idx++) + pBuffer[idx] = GPU_REG_RD32(pGpu, NV_PGSP_EMEMD(pKernelGsp->ememPort)); +} diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index 3dc93c43d2..ba0a60b702 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -28,7 +28,9 @@ #include "kernel/core/thread_state.h" #include "kernel/core/locks.h" #include "kernel/diagnostics/gpu_acct.h" +#include "kernel/diagnostics/journal.h" #include "kernel/gpu/fifo/kernel_channel.h" +#include "kernel/gpu/gsp/gsp_trace_rats_macro.h" #include "kernel/gpu/intr/engine_idx.h" #include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" @@ -39,9 +41,11 @@ #include "virtualization/vgpuconfigapi.h" #include "kernel/gpu/disp/kern_disp.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/device/device.h" #include "gpu/external_device/external_device.h" #include "kernel/platform/platform_request_handler.h" #include "class/cl2080.h" // NV20_SUBDEVICE_0 +#include "ctrl/ctrl2080/ctrl2080nvd.h" #include "liblogdecode.h" #include "libelf.h" #include "nverror.h" @@ -60,6 +64,7 @@ #include "kernel/gpu/pmu/kern_pmu.h" #include "gpu/perf/kern_perf.h" #include "core/locks.h" +#include "kernel/gpu/intr/intr.h" #define RPC_STRUCTURES #define RPC_GENERIC_UNION @@ -109,12 +114,15 @@ static NV_STATUS _kgspConstructRpcObject(OBJGPU *, KernelGsp *, MESSAGE_QUEUE_IN static NV_STATUS _kgspRpcSendMessage(OBJGPU *, OBJRPC *); static NV_STATUS _kgspRpcRecvPoll(OBJGPU *, OBJRPC *, NvU32); -static NV_STATUS _kgspRpcDrainEvents(OBJGPU *, KernelGsp *, NvU32); +static NV_STATUS _kgspRpcDrainEvents(OBJGPU *, KernelGsp *, NvU32, KernelGspRpcEventHandlerContext); static void _kgspRpcIncrementTimeoutCountAndRateLimitPrints(OBJGPU *, OBJRPC *); static NV_STATUS _kgspAllocSimAccessBuffer(OBJGPU *pGpu, KernelGsp *pKernelGsp); static void _kgspFreeSimAccessBuffer(OBJGPU *pGpu, KernelGsp *pKernelGsp); +static NV_STATUS _kgspAllocNotifyOpSharedSurface(OBJGPU *pGpu, KernelGsp *pKernelGsp); +static void _kgspFreeNotifyOpSharedSurface(OBJGPU *pGpu, KernelGsp *pKernelGsp); + static void _kgspStopLogPolling(OBJGPU *pGpu, KernelGsp *pKernelGsp); static void _kgspFreeBootBinaryImage(OBJGPU *pGpu, KernelGsp *pKernelGsp); @@ -142,12 +150,13 @@ _kgspGetActiveRpcDebugData ( OBJRPC *pRpc, NvU32 function, - NvU32 *data0, - NvU32 *data1 + NvU64 *data0, + NvU64 *data1 ) { switch (function) { + // Functions (CPU -> GSP) case NV_VGPU_MSG_FUNCTION_GSP_RM_CONTROL: { RPC_PARAMS(gsp_rm_control, _v03_00); @@ -169,6 +178,36 @@ _kgspGetActiveRpcDebugData *data1 = rpc_params->params.hObjectParent; break; } + + // Events (CPU <- GSP) + case NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: + { + RPC_PARAMS(run_cpu_sequencer, _v17_00); + *data0 = rpc_params->cmdIndex; + *data1 = rpc_params->bufferSizeDWord; + break; + } + case NV_VGPU_MSG_EVENT_POST_EVENT: + { + RPC_PARAMS(post_event, _v17_00); + *data0 = rpc_params->notifyIndex; + *data1 = rpc_params->data; + break; + } + case NV_VGPU_MSG_EVENT_RC_TRIGGERED: + { + RPC_PARAMS(rc_triggered, _v17_02); + *data0 = rpc_params->nv2080EngineType; + *data1 = rpc_params->exceptType; + break; + } + case NV_VGPU_MSG_EVENT_VGPU_GSP_PLUGIN_TRIGGERED: + { + RPC_PARAMS(vgpu_gsp_plugin_triggered, _v17_00); + *data0 = rpc_params->gfid; + *data1 = rpc_params->notifyIndex; + break; + } case NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: { RPC_PARAMS(gsp_lockdown_notice, _v17_00); @@ -176,6 +215,16 @@ _kgspGetActiveRpcDebugData *data1 = 0; break; } + case NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD: + { + RPC_PARAMS(gsp_post_nocat_record, _v01_00); + const NV2080CtrlNocatJournalInsertRecord *pRecord = + (const NV2080CtrlNocatJournalInsertRecord *)&rpc_params->data; + *data0 = pRecord->recType; + *data1 = pRecord->errorCode; + break; + } + default: { *data0 = 0; @@ -186,42 +235,98 @@ _kgspGetActiveRpcDebugData } static NV_STATUS -_kgspRpcSanityCheck(OBJGPU *pGpu) +_kgspRpcSanityCheck(OBJGPU *pGpu, KernelGsp *pKernelGsp, OBJRPC *pRpc) { + if (pKernelGsp->bFatalError) + { + NV_PRINTF(LEVEL_INFO, "GSP crashed, skipping RPC\n"); + // + // In case of a fatal GSP error, if there was an outstanding RPC at the + // time, we should have already printed the error for that, so this is a + // new RPC call...from now on don't bother printing RPC errors anymore, + // as it can be too noisy and overrun logs. + // + pRpc->bQuietPrints = NV_TRUE; + return NV_ERR_RESET_REQUIRED; + } if (API_GPU_IN_RESET_SANITY_CHECK(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU in reset, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU in reset, skipping RPC\n"); return NV_ERR_GPU_IN_FULLCHIP_RESET; } if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu) || pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST)) { - NV_PRINTF(LEVEL_INFO, - "GPU lost, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU lost, skipping RPC\n"); return NV_ERR_GPU_IS_LOST; } if (osIsGpuShutdown(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU shutdown, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU shutdown, skipping RPC\n"); return NV_ERR_GPU_IS_LOST; } if (!gpuIsGpuFullPowerForPmResume(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU not full power, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU not full power, skipping RPC\n"); return NV_ERR_GPU_NOT_FULL_POWER; } if (!gpuCheckSysmemAccess(pGpu)) { - NV_PRINTF(LEVEL_INFO, - "GPU has no sysmem access, skipping RPC\n"); + NV_PRINTF(LEVEL_INFO, "GPU has no sysmem access, skipping RPC\n"); return NV_ERR_INVALID_ACCESS_TYPE; } return NV_OK; } +static void +_kgspAddRpcHistoryEntry +( + OBJRPC *pRpc, + RpcHistoryEntry *pHistory, + NvU32 *pCurrent +) +{ + NvU32 func = RPC_HDR->function; + NvU32 entry; + + entry = *pCurrent = (*pCurrent + 1) % RPC_HISTORY_DEPTH; + + portMemSet(&pHistory[entry], 0, sizeof(pHistory[0])); + pHistory[entry].function = func; + pHistory[entry].ts_start = osGetTimestamp(); + + _kgspGetActiveRpcDebugData(pRpc, func, + &pHistory[entry].data[0], + &pHistory[entry].data[1]); +} + +static void +_kgspCompleteRpcHistoryEntry +( + RpcHistoryEntry *pHistory, + NvU32 current +) +{ + NvU32 historyIndex; + NvU32 historyEntry; + + pHistory[current].ts_end = osGetTimestamp(); + + // + // Complete any previous entries that aren't marked complete yet, using the same timestamp + // (we may not have explicitly waited for them) + // + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (current + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + if (pHistory[historyEntry].ts_start != 0 && + pHistory[historyEntry].ts_end == 0) + { + pHistory[historyEntry].ts_end = pHistory[current].ts_end; + } + } +} + /*! * GSP client RM RPC send routine */ @@ -234,10 +339,11 @@ _kgspRpcSendMessage { NV_STATUS nvStatus; KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + NvU32 gpuMaskUnused; - NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + NV_ASSERT(rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskUnused)); - NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, _kgspRpcSanityCheck(pGpu)); + NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, _kgspRpcSanityCheck(pGpu, pKernelGsp, pRpc)); nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu); if (nvStatus != NV_OK) @@ -255,20 +361,7 @@ _kgspRpcSendMessage kgspSetCmdQueueHead_HAL(pGpu, pKernelGsp, pRpc->pMessageQueueInfo->queueIdx, 0); - // Add RPC history entry - { - NvU32 func = RPC_HDR->function; - NvU32 entry; - - entry = pRpc->rpcHistoryCurrent = (pRpc->rpcHistoryCurrent + 1) % RPC_HISTORY_DEPTH; - - portMemSet(&pRpc->rpcHistory[entry], 0, sizeof(pRpc->rpcHistory[0])); - pRpc->rpcHistory[entry].function = func; - - _kgspGetActiveRpcDebugData(pRpc, func, - &pRpc->rpcHistory[entry].data[0], - &pRpc->rpcHistory[entry].data[1]); - } + _kgspAddRpcHistoryEntry(pRpc, pRpc->rpcHistory, &pRpc->rpcHistoryCurrent); return NV_OK; } @@ -405,6 +498,18 @@ _kgspRpcRCTriggered // check if there's a PCI-E error pending either in device status or in AER krcCheckBusError_HAL(pGpu, pKernelRc); + // + // If we have received a special msg from GSP then ack back immediately + // that we are done writing notifiers since we would have already processed the + // other RC msgs that trigger notifier writes before this one. + // + if (rpc_params->exceptType == ROBUST_CHANNEL_FAST_PATH_ERROR) + { + NV_RM_RPC_ECC_NOTIFIER_WRITE_ACK(pGpu, status); + NV_ASSERT_OK(status); + return status; + } + status = kfifoGetChidMgrFromType(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32)rmEngineType, @@ -419,6 +524,64 @@ _kgspRpcRCTriggered pKernelChannel != NULL, NV_ERR_INVALID_CHANNEL); + // Add the RcDiag records we received from GSP-RM to our system wide journal + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + Journal *pRcDB = SYS_GET_RCDB(pSys); + RmClient *pClient; + + NvU32 recordSize = rcdbGetOcaRecordSizeWithHeader(pRcDB, RmRcDiagReport); + NvU32 rcDiagRecStart = pRcDB->RcErrRptNextIdx; + NvU32 rcDiagRecEnd; + NvU32 processId = 0; + NvU32 owner = RCDB_RCDIAG_DEFAULT_OWNER; + + pClient = dynamicCast(RES_GET_CLIENT(pKernelChannel), RmClient); + NV_ASSERT(pClient != NULL); + if (pClient != NULL) + processId = pClient->ProcID; + + for (NvU32 i = 0; i < rpc_params->rcJournalBufferSize / recordSize; i++) + { + RmRCCommonJournal_RECORD *pCommonRecord = + (RmRCCommonJournal_RECORD *)((NvU8*)&rpc_params->rcJournalBuffer + i * recordSize); + RmRcDiag_RECORD *pRcDiagRecord = + (RmRcDiag_RECORD *)&pCommonRecord[1]; + +#if defined(DEBUG) + NV_PRINTF(LEVEL_INFO, "%d: GPUTag=0x%x CPUTag=0x%llx timestamp=0x%llx stateMask=0x%llx\n", + i, pCommonRecord->GPUTag, pCommonRecord->CPUTag, pCommonRecord->timeStamp, + pCommonRecord->stateMask); + NV_PRINTF(LEVEL_INFO, " idx=%d timeStamp=0x%x type=0x%x flags=0x%x count=%d owner=0x%x processId=0x%x\n", + pRcDiagRecord->idx, pRcDiagRecord->timeStamp, pRcDiagRecord->type, pRcDiagRecord->flags, + pRcDiagRecord->count, pRcDiagRecord->owner, processId); + for (NvU32 j = 0; j < pRcDiagRecord->count; j++) + { + NV_PRINTF(LEVEL_INFO, " %d: offset=0x08%x tag=0x08%x value=0x08%x attribute=0x08%x\n", + j, pRcDiagRecord->data[j].offset, pRcDiagRecord->data[j].tag, + pRcDiagRecord->data[j].value, pRcDiagRecord->data[j].attribute); + } +#endif + if (rcdbAddRcDiagRecFromGsp(pGpu, pRcDB, pCommonRecord, pRcDiagRecord) == NULL) + { + NV_PRINTF(LEVEL_WARNING, "Lost RC diagnostic record coming from GPU%d GSP: type=0x%x stateMask=0x%llx\n", + gpuGetInstance(pGpu), pRcDiagRecord->type, pCommonRecord->stateMask); + } + } + + rcDiagRecEnd = pRcDB->RcErrRptNextIdx - 1; + + // Update records to have the correct PID associated with the channel + if (rcDiagRecStart != rcDiagRecEnd) + { + rcdbUpdateRcDiagRecContext(pRcDB, + rcDiagRecStart, + rcDiagRecEnd, + processId, + owner); + } + } + bIsCcEnabled = gpuIsCCFeatureEnabled(pGpu); // With CC enabled, CPU-RM needs to write error notifiers @@ -489,9 +652,9 @@ _kgspRpcGpuacctPerfmonUtilSamples OBJSYS *pSys = SYS_GET_INSTANCE(); GpuAccounting *pGpuAcct = SYS_GET_GPUACCT(pSys); GPUACCT_GPU_INSTANCE_INFO *pGpuInstanceInfo = &pGpuAcct->gpuInstanceInfo[pGpu->gpuInstance]; - RPC_PARAMS(gpuacct_perfmon_util_samples, _v17_00); + RPC_PARAMS(gpuacct_perfmon_util_samples, _v1F_0E); - NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v17_00 *src = &rpc_params->params; + NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E *src = &rpc_params->params; NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS *dest; NvU32 i; @@ -513,7 +676,7 @@ _kgspRpcGpuacctPerfmonUtilSamples dest->count = src->count; dest->tracker = src->tracker; - for (i = 0; i < NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL; i++) + for (i = 0; i < NV2080_CTRL_PERF_GPUMON_SAMPLE_COUNT_PERFMON_UTIL_v1F_0E; i++) { dest->samples[i].base.timeStamp = src->samples[i].timeStamp; @@ -685,6 +848,17 @@ _kgspRpcEventIsGpuDegradedCallback { } +static void +_kgspRpcNvlinkFatalErrorRecoveryCallback +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NV_ASSERT_OK(knvlinkFatalErrorRecovery(pGpu, pKernelNvlink)); +} + /*! * Receive MMU fault queue notification from GSP-RM. * @@ -887,7 +1061,8 @@ _kgspRpcGspExtdevIntrService return NV_OK; } -static void _kgspRpcMigCiConfigUpdateCallback +static void +_kgspRpcMigCiConfigUpdateCallback ( NvU32 gpuInstance, void *pArgs @@ -942,6 +1117,56 @@ _kgspRpcMigCiConfigUpdate return status; } +static void +_kgspRpcGspUpdateTrace +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ +#if KERNEL_GSP_TRACING_RATS_ENABLED + RPC_PARAMS(update_gsp_trace, _v01_00); + NvU32 i; + NV_RATS_GSP_TRACE_RECORD *GspTraceRecords = (NV_RATS_GSP_TRACE_RECORD*) (&rpc_params->data); + for (i = 0; i < rpc_params->records; i++) + { + gspTraceEventBufferLogRecord(pGpu, &GspTraceRecords[i]); + } +#endif +} + +static void +_kgspRpcGspPostNocatRecord +( + OBJGPU *pGpu, + OBJRPC *pRpc +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + Journal *pRcdb = SYS_GET_RCDB(pSys); + NOCAT_JOURNAL_PARAMS newEntry; + const NV2080CtrlNocatJournalInsertRecord *pRecord = NULL; + RPC_PARAMS(gsp_post_nocat_record, _v01_00); + + // make a pointer to the record. + pRecord = (const NV2080CtrlNocatJournalInsertRecord *)&rpc_params->data; + + portMemSet(&newEntry, 0, sizeof(newEntry)); + newEntry.timestamp = pRecord->timestamp; + newEntry.recType = pRecord->recType; + newEntry.bugcheck = pRecord->bugcheck; + newEntry.pSource = pRecord->source; + newEntry.subsystem = pRecord->subsystem; + newEntry.errorCode = pRecord->errorCode; + newEntry.diagBufferLen = pRecord->diagBufferLen; + newEntry.pDiagBuffer = pRecord->diagBuffer; + newEntry.pFaultingEngine = pRecord->faultingEngine; + newEntry.tdrReason = pRecord->tdrReason; + + (void)rcdbNocatInsertNocatError(pGpu, &newEntry); + pRcdb->nocatJournalDescriptor.nocatEventCounters[NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX]++; +} + static NV_STATUS _kgspRpcRgLineIntr ( @@ -1029,8 +1254,8 @@ const char *_getRpcName { static const char *rpcName[] = { - #define X(UNIT, a) #a, - #define E(a) #a, + #define X(UNIT, a, VAL) #a, + #define E(a, VAL) #a, #undef _RPC_GLOBAL_ENUMS_H_ #include "vgpu/rpc_global_enums.h" #undef X @@ -1053,20 +1278,46 @@ const char *_getRpcName /*! * GSP client process RPC events */ -static NV_STATUS +static void _kgspProcessRpcEvent ( OBJGPU *pGpu, - OBJRPC *pRpc + OBJRPC *pRpc, + KernelGspRpcEventHandlerContext rpcHandlerContext ) { rpc_message_header_v *pMsgHdr = RPC_HDR; NV_STATUS nvStatus = NV_OK; + NvU32 event = pMsgHdr->function; NV_PRINTF(LEVEL_INFO, "received event from GPU%d: 0x%x (%s) status: 0x%x size: %d\n", - gpuGetInstance(pGpu), pMsgHdr->function, _getRpcName(pMsgHdr->function), pMsgHdr->rpc_result, pMsgHdr->length); + gpuGetInstance(pGpu), event, _getRpcName(event), pMsgHdr->rpc_result, pMsgHdr->length); + + _kgspAddRpcHistoryEntry(pRpc, pRpc->rpcEventHistory, &pRpc->rpcEventHistoryCurrent); + + /* + * Shortlist of RPC's that have been manually screened to be safe without the API lock + * that are called during GSP bootup + */ + if ((rpcHandlerContext == KGSP_RPC_EVENT_HANDLER_CONTEXT_POLL_BOOTUP) && + (!rmapiLockIsOwner())) + { + switch(pMsgHdr->function) + { + case NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: + case NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT: + case NV_VGPU_MSG_EVENT_GSP_LOCKDOWN_NOTICE: + case NV_VGPU_MSG_EVENT_GSP_INIT_DONE: + break; + default: + NV_PRINTF(LEVEL_ERROR, "Attempted to process RPC event from GPU%d: 0x%x (%s) during bootup without API lock\n", + gpuGetInstance(pGpu), event, _getRpcName(event)); + NV_ASSERT(0); + goto done; + } + } - switch(pMsgHdr->function) + switch(event) { case NV_VGPU_MSG_EVENT_GSP_RUN_CPU_SEQUENCER: nvStatus = _kgspRpcRunCpuSequencer(pGpu, pRpc); @@ -1140,6 +1391,10 @@ _kgspProcessRpcEvent _kgspRpcNvlinkInbandReceivedData4096Callback(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_NVLINK_FATAL_ERROR_RECOVERY: + _kgspRpcNvlinkFatalErrorRecoveryCallback(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_NVLINK_IS_GPU_DEGRADED : _kgspRpcEventIsGpuDegradedCallback(pGpu, pRpc); break; @@ -1176,20 +1431,41 @@ _kgspProcessRpcEvent _kgspRpcGspLockdownNotice(pGpu, pRpc); break; + case NV_VGPU_MSG_EVENT_UPDATE_GSP_TRACE: + _kgspRpcGspUpdateTrace(pGpu, pRpc); + break; + + case NV_VGPU_MSG_EVENT_GSP_POST_NOCAT_RECORD: + _kgspRpcGspPostNocatRecord(pGpu, pRpc); + break; + case NV_VGPU_MSG_EVENT_GSP_INIT_DONE: // Handled by _kgspRpcRecvPoll. default: + // + // Log, but otherwise ignore unexpected events. // // We will get here if the previous RPC timed out. The response // eventually comes in as an unexpected event. The error handling - // for the timeout has already happened, and returning an error here - // causes subsequent messages to fail. So return NV_OK. + // for the timeout should have already happened. // NV_PRINTF(LEVEL_ERROR, "Unexpected RPC event from GPU%d: 0x%x (%s)\n", - gpuGetInstance(pGpu), pMsgHdr->function, _getRpcName(pMsgHdr->function)); + gpuGetInstance(pGpu), event, _getRpcName(event)); break; } - return nvStatus; + if (nvStatus != NV_OK) + { + // + // Failing to properly handle a specific event does not mean we should stop + // processing events/RPCs, so print the error and soldier on. + // + NV_PRINTF(LEVEL_ERROR, + "Failed to process received event 0x%x (%s) from GPU%d: status=0x%x\n", + event, _getRpcName(event), gpuGetInstance(pGpu), nvStatus); + } + +done: + _kgspCompleteRpcHistoryEntry(pRpc->rpcEventHistory, pRpc->rpcEventHistoryCurrent); } /*! @@ -1200,14 +1476,15 @@ _kgspProcessRpcEvent * NV_OK if the event is successfully handled. * NV_WARN_NOTHING_TO_DO if there are no events available. * NV_WARN_MORE_PROCESSING_REQUIRED if the event is expectedFunc: it is unhandled and in the staging area. - * (Another status) if event reading or processing fails. + * (Another status) if event reading fails. */ static NV_STATUS _kgspRpcDrainOneEvent ( OBJGPU *pGpu, OBJRPC *pRpc, - NvU32 expectedFunc + NvU32 expectedFunc, + KernelGspRpcEventHandlerContext rpcHandlerContext ) { NV_STATUS nvStatus; @@ -1222,20 +1499,15 @@ _kgspRpcDrainOneEvent if (nvStatus == NV_OK) { rpc_message_header_v *pMsgHdr = RPC_HDR; + if (pMsgHdr->function == expectedFunc) return NV_WARN_MORE_PROCESSING_REQUIRED; - nvStatus = _kgspProcessRpcEvent(pGpu, pRpc); - if (nvStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, - "Failed to process received event 0x%x (%s) from GPU%d: status=0x%x\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function), gpuGetInstance(pGpu), nvStatus); - } + _kgspProcessRpcEvent(pGpu, pRpc, rpcHandlerContext); } // - // We don't expect the NV_WARN_MORE_PROCESSING_REQUIRED from either called function. + // We don't expect NV_WARN_MORE_PROCESSING_REQUIRED here. // If we get it we need to suppress it to avoid confusing our caller, for whom it has special meaning. // NV_ASSERT_OR_ELSE(nvStatus != NV_WARN_MORE_PROCESSING_REQUIRED, @@ -1261,7 +1533,8 @@ _kgspRpcDrainEvents ( OBJGPU *pGpu, KernelGsp *pKernelGsp, - NvU32 expectedFunc + NvU32 expectedFunc, + KernelGspRpcEventHandlerContext rpcHandlerContext ) { NV_STATUS nvStatus = NV_OK; @@ -1269,11 +1542,11 @@ _kgspRpcDrainEvents while (nvStatus == NV_OK) { - nvStatus = _kgspRpcDrainOneEvent(pGpu, pRpc, expectedFunc); + nvStatus = _kgspRpcDrainOneEvent(pGpu, pRpc, expectedFunc, rpcHandlerContext); kgspDumpGspLogs(pKernelGsp, NV_FALSE); } - // If GSP-RM has died, + // If GSP-RM has died, the GPU will need to be reset if (!kgspHealthCheck_HAL(pGpu, pKernelGsp)) return NV_ERR_RESET_REQUIRED; @@ -1283,6 +1556,165 @@ _kgspRpcDrainEvents return nvStatus; } +static NvU64 +_tsDiffToDuration +( + NvU64 duration, + char *pDurationUnitsChar +) +{ + const NvU64 tsFreqUs = osGetTimestampFreq() / 1000000; + + *pDurationUnitsChar = 'u'; + + NV_ASSERT_OR_RETURN(tsFreqUs > 0, 0); + + duration /= tsFreqUs; + + // 999999us then 1000ms + if (duration >= 1000000) + { + duration /= 1000; + *pDurationUnitsChar = 'm'; + } + + // 9999ms then 10s + if (duration >= 10000) + { + duration /= 1000; + *pDurationUnitsChar = ' '; // so caller can always just append 's' + } + + return duration; +} + +static NvBool +_kgspIsTimestampDuringRecentRpc +( + OBJRPC *pRpc, + NvU64 timestamp, + NvBool bCheckIncompleteRpcsOnly +) +{ + NvU32 historyIndex; + NvU32 historyEntry; + + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + if (pRpc->rpcHistory[historyEntry].function != 0) + { + if ((timestamp >= pRpc->rpcHistory[historyEntry].ts_start) && + ((pRpc->rpcHistory[historyEntry].ts_end == 0) || + (!bCheckIncompleteRpcsOnly && (timestamp <= pRpc->rpcHistory[historyEntry].ts_end)))) + { + return NV_TRUE; + } + } + } + + return NV_FALSE; +} + +static void +_kgspLogRpcHistoryEntry +( + OBJGPU *pGpu, + NvU32 errorNum, + NvU32 historyIndex, + RpcHistoryEntry *pEntry, + NvBool lastColumnCondition +) +{ + NvU64 duration; + char durationUnitsChar; + + if (pEntry->function != 0) + { + duration = (pEntry->ts_end > pEntry->ts_start) ? (pEntry->ts_end - pEntry->ts_start) : 0; + if (duration) + { + duration = _tsDiffToDuration(duration, &durationUnitsChar); + + NV_ERROR_LOG_DATA(pGpu, errorNum, + " %c%-4d %-4d %-21.21s 0x%016llx 0x%016llx 0x%016llx 0x%016llx %6llu%cs %c\n", + ((historyIndex == 0) ? ' ' : '-'), + historyIndex, + pEntry->function, + _getRpcName(pEntry->function), + pEntry->data[0], + pEntry->data[1], + pEntry->ts_start, + pEntry->ts_end, + duration, durationUnitsChar, + (lastColumnCondition ? 'y' : ' ')); + } + else + { + NV_ERROR_LOG_DATA(pGpu, errorNum, + " %c%-4d %-4d %-21.21s 0x%016llx 0x%016llx 0x%016llx 0x%016llx %c\n", + ((historyIndex == 0) ? ' ' : '-'), + historyIndex, + pEntry->function, + _getRpcName(pEntry->function), + pEntry->data[0], + pEntry->data[1], + pEntry->ts_start, + pEntry->ts_end, + (lastColumnCondition ? 'y' : ' ')); + } + } +} + +void +kgspLogRpcDebugInfo +( + OBJGPU *pGpu, + OBJRPC *pRpc, + NvU32 errorNum, + NvBool bPollingForRpcResponse +) +{ + const rpc_message_header_v *pMsgHdr = RPC_HDR; + NvU32 historyIndex; + NvU32 historyEntry; + NvU64 activeData[2]; + + _kgspGetActiveRpcDebugData(pRpc, pMsgHdr->function, + &activeData[0], &activeData[1]); + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d GSP RPC buffer contains function %d (%s) and data 0x%016llx 0x%016llx.\n", + gpuGetInstance(pGpu), + pMsgHdr->function, _getRpcName(pMsgHdr->function), + activeData[0], activeData[1]); + + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d RPC history (CPU -> GSP):\n", + gpuGetInstance(pGpu)); + NV_ERROR_LOG_DATA(pGpu, errorNum, + " entry function data0 data1 ts_start ts_end duration actively_polling\n"); + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + _kgspLogRpcHistoryEntry(pGpu, errorNum, historyIndex, &pRpc->rpcHistory[historyEntry], + ((historyIndex == 0) && bPollingForRpcResponse)); + } + + NV_ERROR_LOG_DATA(pGpu, errorNum, + "GPU%d RPC event history (CPU <- GSP):\n", + gpuGetInstance(pGpu)); + NV_ERROR_LOG_DATA(pGpu, errorNum, + " entry function data0 data1 ts_start ts_end duration during_incomplete_rpc\n"); + for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) + { + historyEntry = (pRpc->rpcEventHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; + _kgspLogRpcHistoryEntry(pGpu, errorNum, historyIndex, &pRpc->rpcEventHistory[historyEntry], + _kgspIsTimestampDuringRecentRpc(pRpc, + pRpc->rpcEventHistory[historyEntry].ts_start, + NV_TRUE/*bCheckIncompleteRpcsOnly*/)); + } +} + /*! * Log Xid 119 - GSP RPC Timeout */ @@ -1294,65 +1726,36 @@ _kgspLogXid119 NvU32 expectedFunc ) { - NvU32 historyEntry = pRpc->rpcHistoryCurrent; + RpcHistoryEntry *pHistoryEntry = &pRpc->rpcHistory[pRpc->rpcHistoryCurrent]; + NvU64 ts_end = osGetTimestamp(); + NvU64 duration; + char durationUnitsChar; if (pRpc->timeoutCount == 1) { NV_PRINTF(LEVEL_ERROR, - "********************************* GSP Failure **********************************\n"); + "********************************* GSP Timeout **********************************\n"); + NV_PRINTF(LEVEL_ERROR, + "Note: Please also check logs above.\n"); } - NV_ASSERT(expectedFunc == pRpc->rpcHistory[historyEntry].function); + NV_ASSERT(expectedFunc == pHistoryEntry->function); - nvErrorLog_va((void*)pGpu, GSP_RPC_TIMEOUT, - "Timeout waiting for RPC from GSP%d! Expected function %d (%s) (0x%x 0x%x).", - gpuGetInstance(pGpu), - expectedFunc, - _getRpcName(expectedFunc), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, NV_PRINTF_ADD_PREFIX - ("Timeout waiting for RPC from GSP%d! Expected function %d (0x%x 0x%x)"), + NV_ASSERT(ts_end > pHistoryEntry->ts_start); + duration = _tsDiffToDuration(ts_end - pHistoryEntry->ts_start, &durationUnitsChar); + + NV_ERROR_LOG(pGpu, GSP_RPC_TIMEOUT, + "Timeout after %llus of waiting for RPC response from GPU%d GSP! Expected function %d (%s) (0x%x 0x%x).", + (durationUnitsChar == 'm' ? duration / 1000 : duration), gpuGetInstance(pGpu), expectedFunc, - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); + _getRpcName(expectedFunc), + pHistoryEntry->data[0], + pHistoryEntry->data[1]); if (pRpc->timeoutCount == 1) { - NvU32 activeData[2]; - NvU32 historyIndex; - rpc_message_header_v *pMsgHdr = RPC_HDR; - - _kgspGetActiveRpcDebugData(pRpc, pMsgHdr->function, - &activeData[0], &activeData[1]); - - if ((expectedFunc != pMsgHdr->function) || - (pRpc->rpcHistory[historyEntry].data[0] != activeData[0]) || - (pRpc->rpcHistory[historyEntry].data[1] != activeData[1])) - { - NV_PRINTF(LEVEL_ERROR, - "Current RPC function %d (%s) or data (0x%x 0x%x) does not match expected function %d (%s) or data (0x%x 0x%x).\n", - pMsgHdr->function, _getRpcName(pMsgHdr->function), - activeData[0], activeData[1], - expectedFunc, _getRpcName(expectedFunc), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - } - - NV_PRINTF(LEVEL_ERROR, "RPC history (CPU -> GSP%d):\n", gpuGetInstance(pGpu)); - NV_PRINTF(LEVEL_ERROR, "\tentry\tfunc\t\t\t\tdata\n"); - for (historyIndex = 0; historyIndex < RPC_HISTORY_DEPTH; historyIndex++) - { - historyEntry = (pRpc->rpcHistoryCurrent + RPC_HISTORY_DEPTH - historyIndex) % RPC_HISTORY_DEPTH; - NV_PRINTF(LEVEL_ERROR, "\t%c%-2d\t%2d %-22s\t0x%08x 0x%08x\n", - ((historyIndex == 0) ? ' ' : '-'), - historyIndex, - pRpc->rpcHistory[historyEntry].function, - _getRpcName(pRpc->rpcHistory[historyEntry].function), - pRpc->rpcHistory[historyEntry].data[0], - pRpc->rpcHistory[historyEntry].data[1]); - } + kgspLogRpcDebugInfo(pGpu, pRpc, GSP_RPC_TIMEOUT, NV_TRUE/*bPollingForRpcResponse*/); osAssertFailed(); @@ -1368,17 +1771,8 @@ _kgspRpcIncrementTimeoutCountAndRateLimitPrints OBJRPC *pRpc ) { - KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); - pRpc->timeoutCount++; - if (pKernelGsp->bFatalError) - { - // in case of a fatal GSP error, don't bother printing RPC errors at all - pRpc->bQuietPrints = NV_TRUE; - return; - } - if ((pRpc->timeoutCount == (RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH + 1)) && (RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP > 0)) { @@ -1419,7 +1813,14 @@ _kgspRpcRecvPoll NvU32 timeoutUs; NvU32 timeoutFlags; NvBool bSlowGspRpc = IS_EMULATION(pGpu) || IS_SIMULATION(pGpu); + NvU32 gpuMaskUnused; + KernelGspRpcEventHandlerContext rpcHandlerContext = KGSP_RPC_EVENT_HANDLER_CONTEXT_POLL; + if (expectedFunc == NV_VGPU_MSG_EVENT_GSP_INIT_DONE) + { + // special case for bootup path without API lock + rpcHandlerContext = KGSP_RPC_EVENT_HANDLER_CONTEXT_POLL_BOOTUP; + } // // We do not allow recursive polling. This can happen if e.g. // 1. CPU-RM issues RPC-A to GSP and polls waiting for it to finish @@ -1434,6 +1835,7 @@ _kgspRpcRecvPoll NV_ASSERT_OR_RETURN(!pKernelGsp->bPollingForRpcResponse, NV_ERR_INVALID_STATE); pKernelGsp->bPollingForRpcResponse = NV_TRUE; + // // GSP-RM init in emulation/simulation environment is extremely slow, // so need to increment timeout. // Apply the timeout extension to other RPCs as well, mostly so that @@ -1459,14 +1861,16 @@ _kgspRpcRecvPoll } else { + // // We should only ever timeout this when GSP is in really bad state, so if it just // happens to timeout on default timeout it should be OK for us to give it a little // more time - make this timeout 1.5 of the default to allow some leeway. + // timeoutUs = defaultus + defaultus / 2; } } - NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + NV_ASSERT(rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskUnused)); timeoutFlags = GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE; if (pRpc->bQuietPrints) @@ -1482,10 +1886,12 @@ _kgspRpcRecvPoll // timeoutStatus = gpuCheckTimeout(pGpu, &timeout); - rpcStatus = _kgspRpcDrainEvents(pGpu, pKernelGsp, expectedFunc); + rpcStatus = _kgspRpcDrainEvents(pGpu, pKernelGsp, expectedFunc, rpcHandlerContext); switch (rpcStatus) { case NV_WARN_MORE_PROCESSING_REQUIRED: + // The synchronous RPC response we were waiting for is here + _kgspCompleteRpcHistoryEntry(pRpc->rpcHistory, pRpc->rpcHistoryCurrent); rpcStatus = NV_OK; goto done; case NV_OK: @@ -1495,7 +1901,7 @@ _kgspRpcRecvPoll goto done; } - NV_CHECK_OK_OR_GOTO(rpcStatus, LEVEL_SILENT, _kgspRpcSanityCheck(pGpu), done); + NV_CHECK_OK_OR_GOTO(rpcStatus, LEVEL_SILENT, _kgspRpcSanityCheck(pGpu, pKernelGsp, pRpc), done); if (timeoutStatus == NV_ERR_TIMEOUT) { @@ -1616,7 +2022,10 @@ _kgspConstructRpcObject pRpc->pMessageQueueInfo = pMQI; portMemSet(&pRpc->rpcHistory, 0, sizeof(pRpc->rpcHistory)); - pRpc->rpcHistoryCurrent = RPC_HISTORY_DEPTH - 1; + pRpc->rpcHistoryCurrent = RPC_HISTORY_DEPTH - 1; + portMemSet(&pRpc->rpcEventHistory, 0, sizeof(pRpc->rpcEventHistory)); + pRpc->rpcEventHistoryCurrent = RPC_HISTORY_DEPTH - 1; + pRpc->message_buffer = (NvU32 *)pRpc->pMessageQueueInfo->pRpcMsgBuf; pRpc->maxRpcSize = GSP_MSG_QUEUE_RPC_SIZE_MAX; @@ -1785,7 +2194,8 @@ kgspInitVgpuPartitionLogging_IMPL return NV_ERR_INVALID_ARGUMENT; } - portSyncMutexAcquire(pKernelGsp->pNvlogFlushMtx); + if (pKernelGsp->pNvlogFlushMtx != NULL) + portSyncMutexAcquire(pKernelGsp->pNvlogFlushMtx); // Source name is used to generate a tag that is a unique identifier for nvlog buffers. // As the source name 'GSP' is already in use, we will need a custom source name. @@ -1848,7 +2258,8 @@ kgspInitVgpuPartitionLogging_IMPL pKernelGsp->bHasVgpuLogs = NV_TRUE; error_cleanup: - portSyncMutexRelease(pKernelGsp->pNvlogFlushMtx); + if (pKernelGsp->pNvlogFlushMtx != NULL) + portSyncMutexRelease(pKernelGsp->pNvlogFlushMtx); if (nvStatus != NV_OK) _kgspFreeLibosVgpuPartitionLoggingStructures(pGpu, pKernelGsp, gfid); @@ -1879,11 +2290,12 @@ _kgspFreeLibosLoggingStructures // Make sure there is no lingering debug output. kgspDumpGspLogs(pKernelGsp, NV_FALSE); + if (pKernelGsp->pLogElf == NULL) + nvlogDeregisterFlushCb(kgspNvlogFlushCb, pKernelGsp); + if (pKernelGsp->pNvlogFlushMtx != NULL) { - nvlogDeregisterFlushCb(kgspNvlogFlushCb, pKernelGsp); portSyncMutexDestroy(pKernelGsp->pNvlogFlushMtx); - pKernelGsp->pNvlogFlushMtx = NULL; } @@ -1952,11 +2364,15 @@ _kgspInitLibosLoggingStructures NvU8 idx; NvU64 flags = MEMDESC_FLAGS_NONE; - pKernelGsp->pNvlogFlushMtx = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); - if (pKernelGsp->pNvlogFlushMtx == NULL) + // Needed only on Unix where NV_ESC_RM_LOCKLESS_DIAGNOSTIC is supported + if (RMCFG_FEATURE_PLATFORM_UNIX) { - nvStatus = NV_ERR_INSUFFICIENT_RESOURCES; - goto error_cleanup; + pKernelGsp->pNvlogFlushMtx = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + if (pKernelGsp->pNvlogFlushMtx == NULL) + { + nvStatus = NV_ERR_INSUFFICIENT_RESOURCES; + goto error_cleanup; + } } libosLogCreate(&pKernelGsp->logDecode); @@ -1979,7 +2395,7 @@ _kgspInitLibosLoggingStructures flags), error_cleanup); - memdescTagAlloc(nvStatus, + memdescTagAlloc(nvStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_12, pLog->pTaskLogDescriptor); NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, error_cleanup); @@ -2087,7 +2503,7 @@ _kgspAllocSimAccessBuffer(OBJGPU *pGpu, KernelGsp *pKernelGsp) MEMDESC_FLAGS_NONE), error_cleanup); - memdescTagAlloc(nvStatus, + memdescTagAlloc(nvStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_13, pKernelGsp->pMemDesc_simAccessBuf); NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, error_cleanup); @@ -2129,6 +2545,67 @@ _kgspFreeSimAccessBuffer(OBJGPU *pGpu, KernelGsp *pKernelGsp) pKernelGsp->pSimAccessBufPriv = NULL; } +static NV_STATUS +_kgspAllocNotifyOpSharedSurface(OBJGPU *pGpu, KernelGsp *pKernelGsp) +{ + NvP64 pVa = NvP64_NULL; + NvP64 pPriv = NvP64_NULL; + NV_STATUS nvStatus; + NvU64 flags = MEMDESC_FLAGS_NONE; + + // + // On systems with SEV enabled, the fault buffer flush sequence memory should be allocated + // in unprotected sysmem as GSP will be writing to this location to let the guest + // know a the issued notify op has finished as well as the status of the operation. + // + flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescCreate(&pKernelGsp->pNotifyOpSurfMemDesc, + pGpu, + sizeof(NotifyOpSharedSurface), + RM_PAGE_SIZE, + NV_FALSE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, + flags), + error_cleanup); + + memdescTagAlloc(nvStatus, + NV_FB_ALLOC_RM_INTERNAL_OWNER_GSP_NOTIFY_OP_SURFACE, pKernelGsp->pNotifyOpSurfMemDesc); + NV_ASSERT_OK_OR_GOTO(nvStatus, nvStatus, error_cleanup); + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescMap(pKernelGsp->pNotifyOpSurfMemDesc, 0, + memdescGetSize(pKernelGsp->pNotifyOpSurfMemDesc), + NV_TRUE, NV_PROTECT_READ_WRITE, + &pVa, &pPriv), + error_cleanup); + + pKernelGsp->pNotifyOpSurf = (NotifyOpSharedSurface*)pVa; + pKernelGsp->pNotifyOpSurfPriv = pPriv; + + portMemSet(pKernelGsp->pNotifyOpSurf, 0, memdescGetSize(pKernelGsp->pNotifyOpSurfMemDesc)); + +error_cleanup: + if (nvStatus != NV_OK) + _kgspFreeNotifyOpSharedSurface(pGpu, pKernelGsp); + + return nvStatus; +} + +static void +_kgspFreeNotifyOpSharedSurface(OBJGPU *pGpu, KernelGsp *pKernelGsp) +{ + if (pKernelGsp->pNotifyOpSurfMemDesc != NULL) + { + memdescFree(pKernelGsp->pNotifyOpSurfMemDesc); + memdescDestroy(pKernelGsp->pNotifyOpSurfMemDesc); + } + + pKernelGsp->pNotifyOpSurfMemDesc = NULL; + pKernelGsp->pNotifyOpSurf = NULL; + pKernelGsp->pNotifyOpSurfPriv = NULL; +} + /*! * Create KernelGsp object and initialize RPC infrastructure */ @@ -2184,9 +2661,21 @@ kgspConstructEngine_IMPL } } + nvStatus = _kgspAllocNotifyOpSharedSurface(pGpu, pKernelGsp); + if (nvStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "notify operation shared surface alloc failed: 0x%x\n", nvStatus); + goto done; + } + +#if KERNEL_GSP_TRACING_RATS_ENABLED + multimapInit(&pGpu->gspTraceEventBufferBindingsUid, portMemAllocatorGetGlobalNonPaged()); +#endif + done: if (nvStatus != NV_OK) { + _kgspFreeSimAccessBuffer(pGpu, pKernelGsp); kgspFreeBootArgs_HAL(pGpu, pKernelGsp); _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); @@ -2215,6 +2704,95 @@ _kgspVbiosVersionToStr(NvU64 vbiosVersionCombined, char *pVbiosVersionStr, NvU32 (vbiosVersionCombined) & 0xff); } +/*! + * Prepare and place RPCs in message queue that GSP-RM will process + * in early boot before OBJGPU is created. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelGsp KernelGsp object pointer + * + * @return NV_OK if RPCs queued successfully. + * Appropriate NV_ERR_xxx value otherwise. + */ +NV_STATUS +kgspQueueAsyncInitRpcs_IMPL +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + NV_STATUS status = NV_OK; + + NV_RM_RPC_GSP_SET_SYSTEM_INFO(pGpu, status); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("NV_RM_RPC_GSP_SET_SYSTEM_INFO", status); + return status; + } + + NV_RM_RPC_SET_REGISTRY(pGpu, status); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("NV_RM_RPC_SET_REGISTRY", status); + return status; + } + + return NV_OK; +} + +static NvBool +_kgspShouldRelaxGspInitLocking +( + OBJGPU *pGpu +) +{ + NvU32 relaxGspInitLockingReg; + + if (!RMCFG_FEATURE_PLATFORM_UNIX) + { + return NV_FALSE; + } + + if (gpuIsCCFeatureEnabled(pGpu)) + { + return NV_FALSE; + } + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING, &relaxGspInitLockingReg) != NV_OK) + { + relaxGspInitLockingReg = NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DEFAULT; + } + + // Due to bug 4399629, restrict which platforms have parallel init enabled by default + if (relaxGspInitLockingReg == NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_DEFAULT) + { + NvU16 devId = (NvU16)(((pGpu->idInfo.PCIDeviceID) >> 16) & 0x0000FFFF); + NvU32 i; + + static const NvU16 defaultRelaxGspInitLockingGpus[] = { + 0x1EB8, // T4 + 0x1EB9, // T4 + }; + + if (IsHOPPER(pGpu) || IsADA(pGpu)) + { + return NV_TRUE; + } + + for (i = 0; i < NV_ARRAY_ELEMENTS(defaultRelaxGspInitLockingGpus); i++) + { + if (devId == defaultRelaxGspInitLockingGpus[i]) + { + return NV_TRUE; + } + } + return NV_FALSE; + } + + return (relaxGspInitLockingReg == NV_REG_STR_RM_RELAXED_GSP_INIT_LOCKING_ENABLE); + return NV_FALSE; +} + /*! * Initialize GSP-RM * @@ -2374,8 +2952,12 @@ kgspInitRm_IMPL NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, _kgspInitLibosLogDecoder(pGpu, pKernelGsp, pGspFw), done); - // If live decoding is enabled, do not register flush callback to avoid racing with ioctl - if (pKernelGsp->pLogElf == NULL) + // + // Do not register nvlog flush callback if: + // 1. Live decoding is enabled, as logs will be printed to dmesg. + // 2. NV_ESC_RM_LOCKLESS_DIAGNOSTIC is not supported on this platform, i.e. pNvlogFlushMtx=NULL. + // + if (pKernelGsp->pLogElf == NULL && pKernelGsp->pNvlogFlushMtx != NULL) NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, nvlogRegisterFlushCb(kgspNvlogFlushCb, pKernelGsp), done); // Reset thread state timeout and wait for GFW_BOOT OK status @@ -2427,12 +3009,106 @@ kgspInitRm_IMPL } } + // Initialize libos init args list + kgspSetupLibosInitArgs(pGpu, pKernelGsp); + + // Fill in the GSP-RM message queue init parameters + kgspPopulateGspRmInitArgs(pGpu, pKernelGsp, NULL); + + // + // If ConfCompute is enabled, all RPC traffic must be encrypted. Since we + // can't encrypt until GSP boots and session is established, we must send + // these messages later (kgspBootstrapRiscvOSEarly_HAL) in CC. + // + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + if (pCC == NULL || !pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_CC_FEATURE_ENABLED)) + { + // + // Stuff the message queue with async init messages that will be run + // before OBJGPU is created. + // + status = kgspQueueAsyncInitRpcs(pGpu, pKernelGsp); + if (status != NV_OK) + { + goto done; + } + } + // bring up ucode with RM offload task - status = kgspBootstrapRiscvOSEarly_HAL(pGpu, pKernelGsp, pGspFw); + status = kgspPrepareForBootstrap_HAL(pGpu, pKernelGsp, pGspFw); + if (status == NV_OK) + { + NV_STATUS statusBootstrap; + NvBool bReleaseApiLock = _kgspShouldRelaxGspInitLocking(pGpu); + if (bReleaseApiLock) + { + rmapiLockRelease(); + } + + statusBootstrap = kgspBootstrap_HAL(pGpu, pKernelGsp, pGspFw); + + // + // Reacquire locks even if GSP boot fails + // + // As this path doesn't go through resource server, no client locks should be held at this point. + // Note: we must not hold any client locks when re-acquiring the API per lock ordering + // + if (bReleaseApiLock) + { + // To follow lock order constraints, GPU lock needs to be released before acquiring API lock + rmGpuGroupLockRelease(gpusLockedMask, GPUS_LOCK_FLAGS_NONE); + gpusLockedMask = 0; + + status = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT); + if (status != NV_OK) + { + // + // rmapiLockAcquire should never fail on Linux if the API lock and GPU locks are not held. + // Failure to acquire the API lock means the cleanup sequence will skipped since it is + // unsafe without the lock. + // + NV_ASSERT_FAILED("Failed to reacquire API lock!"); + return NV_ERR_INVALID_LOCK_STATE; + } + + if (!gpumgrIsGpuPointerAttached(pGpu)) + { + // + // This should never happen on Linux due to locks in the Unix layer. + // This will need to be revisited when parallel init is enabled on + // other platforms. + // + NV_ASSERT(0); + status = NV_ERR_INVALID_DEVICE; + goto done; + } + + status = rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT, + &gpusLockedMask); + if (status != NV_OK) + { + gpusLockedMask = 0; + NV_ASSERT_FAILED("Failed to reacquire GPU lock!"); + goto done; + } + } + + status = statusBootstrap; + } + if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "cannot bootstrap riscv/gsp: 0x%x\n", status); + if (status == NV_ERR_INSUFFICIENT_POWER) + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + + pGpuMgr->powerDisconnectedGpuBus[pGpuMgr->powerDisconnectedGpuCount++] = gpuGetBus(pGpu); + } + // // Ignore return value - a crash report may have already been consumed, // this is just here as a last attempt to report boot issues that might @@ -2496,10 +3172,17 @@ kgspUnloadRm_IMPL { NV_STATUS rpcStatus = NV_OK; NV_STATUS status; + KernelGspPreparedFwsecCmd preparedCmd; NV_PRINTF(LEVEL_INFO, "unloading GSP-RM\n"); NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, rpcStatus, NV_FALSE, NV_FALSE, 0); + if (gpuIsCCFeatureEnabled(pGpu)) + { + // FIPS: If CC enabled, we need to confirm GSP-RM was able to teardown CC state. + kgspCheckGspRmCcCleanup_HAL(pGpu, pKernelGsp); + } + // Wait for GSP-RM processor to suspend kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp); @@ -2519,12 +3202,26 @@ kgspUnloadRm_IMPL } // Invoke FWSEC-SB to put back PreOsApps during driver unload - status = kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode); - if (status != NV_OK) + status = kgspPrepareForFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode, &preparedCmd); + if (status == NV_ERR_NOT_SUPPORTED) { - NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC-SB for PreOsApps during driver unload: 0x%x\n", status); + // skip FWSEC-SB during driver unload if unsupported (e.g. on Hopper+) + status = NV_OK; + } + else if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to prepare for FWSEC-SB for PreOsApps during driver unload: 0x%x\n", status); NV_ASSERT(0); } + else + { + status = kgspExecuteFwsec_HAL(pGpu, pKernelGsp, &preparedCmd); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC-SB for PreOsApps during driver unload: 0x%x\n", status); + NV_ASSERT(0); + } + } if (pKernelGsp->bPartitionedFmc) { @@ -2596,8 +3293,13 @@ kgspDestruct_IMPL _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); _kgspFreeBootBinaryImage(pGpu, pKernelGsp); _kgspFreeSimAccessBuffer(pGpu, pKernelGsp); + _kgspFreeNotifyOpSharedSurface(pGpu, pKernelGsp); kgspFreeSuspendResumeData_HAL(pGpu, pKernelGsp); + +#if KERNEL_GSP_TRACING_RATS_ENABLED + multimapDestroy(&pGpu->gspTraceEventBufferBindingsUid); +#endif } void @@ -2724,7 +3426,7 @@ kgspPrepareBootBinaryImage_IMPL BINDATA_STORAGE *pBinStorageDesc; NvU32 bufSize; NvU32 bufSizeAligned; - NvU8 *pDesc = NULL; + RM_RISCV_UCODE_DESC *pDesc = NULL; NvP64 pVa = NvP64_NULL; NvP64 pPriv = NvP64_NULL; NvU64 flags = MEMDESC_FLAGS_NONE; @@ -2750,7 +3452,7 @@ kgspPrepareBootBinaryImage_IMPL flags), fail); - memdescTagAlloc(status, + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_15, pKernelGsp->pGspRmBootUcodeMemdesc); NV_ASSERT_OK_OR_GOTO(status, status, fail); @@ -2771,21 +3473,11 @@ kgspPrepareBootBinaryImage_IMPL bufSize), fail); - // copy the image descriptor - bufSize = bindataGetBufferSize(pBinStorageDesc); - pDesc = portMemAllocNonPaged(bufSize); - if (pDesc == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Failed to allocate ucode desc buffer\n"); - status = NV_ERR_NO_MEMORY; - goto fail; - } - - pKernelGsp->pGspRmBootUcodeDesc = (RM_RISCV_UCODE_DESC*)pDesc; - + // get the image descriptor NV_ASSERT_OK_OR_GOTO(status, - bindataWriteToBuffer(pBinStorageDesc, pDesc, bufSize), + bindataStorageAcquireData(pBinStorageDesc, (const void**)&pDesc), fail); + pKernelGsp->pGspRmBootUcodeDesc = pDesc; return status; @@ -2801,7 +3493,7 @@ _kgspFreeBootBinaryImage KernelGsp *pKernelGsp ) { - portMemFree(pKernelGsp->pGspRmBootUcodeDesc); + bindataStorageReleaseData(pKernelGsp->pGspRmBootUcodeDesc); pKernelGsp->pGspRmBootUcodeDesc = NULL; if (pKernelGsp->pGspRmBootUcodeImage != NULL) @@ -2843,7 +3535,7 @@ _kgspCreateSignatureMemdesc NV_ALIGN_UP(pGspFw->signatureSize, 256), 256, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED, flags)); - memdescTagAlloc(status, + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_16, pKernelGsp->pSignatureMemdesc); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, status, fail_create); @@ -3105,7 +3797,7 @@ kgspCreateRadix3_IMPL flags), done); - memdescTagAlloc(status, + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_17, (*ppMemdescRadix3)); NV_ASSERT_OK_OR_GOTO(status, status, error_ret); @@ -3332,13 +4024,14 @@ kgspRpcRecvEvents_IMPL KernelGsp *pKernelGsp ) { - NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + NvU32 gpuMaskUnused; + NV_ASSERT(rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskUnused)); // // We should never have an event with code NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS. // If we do the assert will fail on NV_WARN_MORE_PROCESSING_REQUIRED, // in addition to general error codes. // - NV_ASSERT_OK(_kgspRpcDrainEvents(pGpu, pKernelGsp, NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS)); + NV_ASSERT_OK(_kgspRpcDrainEvents(pGpu, pKernelGsp, NV_VGPU_MSG_FUNCTION_NUM_FUNCTIONS, KGSP_RPC_EVENT_HANDLER_CONTEXT_INTERRUPT)); } /*! @@ -3560,11 +4253,16 @@ kgspStartLogPolling_IMPL NV_STATUS status = NV_OK; // - // Only enable the 1 Hz poll if we can live decode logs in dmesg. Else we'll flush it on demand - // by nvidia-debugdump. + // Only enable the 1 Hz poll if we can live decode logs in dmesg. Else we'll + // flush it on demand by nvidia-debugdump. // if (pKernelGsp->pLogElf != NULL) - status = osSchedule1SecondCallback(pGpu, _kgspLogPollingCallback, NULL, NV_OS_1HZ_REPEAT); + { + status = osSchedule1HzCallback(pGpu, + _kgspLogPollingCallback, + NULL, + NV_OS_1HZ_REPEAT); + } return status; } @@ -3576,7 +4274,9 @@ _kgspStopLogPolling ) { if (pKernelGsp->pLogElf != NULL) - osRemove1SecondRepeatingCallback(pGpu, _kgspLogPollingCallback, NULL); + { + osRemove1HzCallback(pGpu, _kgspLogPollingCallback, NULL); + } } #else // LIBOS_LOG_DECODE_ENABLE diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c index 5b3c987383..f851bb74a2 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c @@ -136,7 +136,7 @@ s_patchBooterUcodeSignature NvU8 *pImage, NvU32 sigDestOffset, NvU32 imageSize, - NvU32 *pSignatures, + const void *pSignatures, NvU32 signaturesTotalSize, NvU32 numSigs ) @@ -203,7 +203,7 @@ s_allocateUcodeFromBinArchive NvU32 patchSig; NvU32 numSigs; NvU32 signaturesTotalSize; - NvU32 *pSignatures = NULL; + const void *pSignatures = NULL; const BINDATA_STORAGE *pBinImage; const BINDATA_STORAGE *pBinHeader; @@ -302,15 +302,8 @@ s_allocateUcodeFromBinArchive goto out; } - pSignatures = portMemAllocNonPaged(signaturesTotalSize); - if (pSignatures == NULL) - { - status = NV_ERR_NO_MEMORY; - goto out; - } - NV_ASSERT_OK_OR_GOTO(status, - bindataWriteToBuffer(pBinSig, (NvU8 *) pSignatures, signaturesTotalSize), + bindataStorageAcquireData(pBinSig, &pSignatures), out); // Populate KernelGspFlcnUcode structure @@ -401,6 +394,9 @@ s_allocateUcodeFromBinArchive goto out; } + // We are not using zero copy api bindataStorageAcquireData here because s_patchBooterUcodeSignature + // writes to pUcode->pImage to patch the signatures. Since this path is taken once, the risk + // of accidentally overwriting original bindata buffer may not be worth the performance gains. // Copy in the whole image NV_ASSERT_OK_OR_GOTO(status, bindataWriteToBuffer(pBinImage, pUcode->pImage, pUcode->size), @@ -416,7 +412,7 @@ s_allocateUcodeFromBinArchive } out: - portMemFree(pSignatures); + bindataStorageReleaseData((void*)pSignatures); pSignatures = NULL; if (status == NV_OK) diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c index 525c785c8b..9b8584c703 100644 --- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c +++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c @@ -512,7 +512,6 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) NvU8 *pNextElement = NULL; int nRet; NvU32 i; - NvU32 nRetries; RMTIMEOUT timeout; NV_STATUS nvStatus = NV_OK; NvU32 uElementSize = GSP_MSG_QUEUE_ELEMENT_HDR_SIZE + @@ -535,12 +534,14 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) pCQE->elemCount = GSP_MSG_QUEUE_BYTES_TO_ELEMENTS(uElementSize); pCQE->checkSum = 0; - ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); - if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED)) + if (gpuIsCCFeatureEnabled(pGpu)) { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); + // Use sequence number as AAD. portMemCopy((NvU8*)pCQE->aadBuffer, sizeof(pCQE->aadBuffer), (NvU8 *)&pCQE->seqNum, sizeof(pCQE->seqNum)); + // We need to encrypt the full queue elements to obscure the data. nvStatus = ccslEncrypt(pCC->pRpcCcslCtx, (pCQE->elemCount * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN) - GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, pSrc + GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, @@ -549,15 +550,26 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) pSrc + GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, pCQE->authTagBuffer); - if(nvStatus != NV_OK) + if (nvStatus != NV_OK) { + // Do not re-try if encryption fails. NV_PRINTF(LEVEL_ERROR, "Encryption failed with status = 0x%x.\n", nvStatus); - // Do not re-try if decryption failed. + if (nvStatus == NV_ERR_INSUFFICIENT_RESOURCES) + { + // We hit potential IV overflow, this is fatal. + NV_PRINTF(LEVEL_ERROR, "Fatal error detected in RPC encrypt: IV overflow!\n"); + confComputeSetErrorState(pGpu, pCC); + } return nvStatus; } - } - pCQE->checkSum = _checkSum32(pSrc, pCQE->elemCount * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN); + // Now that encryption covers elements completely, include them in checksum. + pCQE->checkSum = _checkSum32(pSrc, pCQE->elemCount * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN); + } + else + { + pCQE->checkSum = _checkSum32(pSrc, uElementSize); + } for (i = 0; i < pCQE->elemCount; i++) { @@ -569,8 +581,8 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) // Set a timeout of 1 sec gpuSetTimeout(pGpu, 1000000, &timeout, timeoutFlags); - // Wait for space to put the next element. Retry for up to 10 ms. - for (nRetries = 0; ; nRetries++) + // Wait for space to put the next element. + while (NV_TRUE) { // Must get the buffers one at a time, since they could wrap. pNextElement = (NvU8 *)msgqTxGetWriteBuffer(pMQI->hQueue, i); @@ -589,7 +601,9 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) if (pNextElement == NULL) { pMQI->txBufferFull++; - NV_PRINTF_COND(pMQI->txBufferFull == 1, LEVEL_ERROR, LEVEL_INFO, "buffer is full\n"); + NV_PRINTF_COND(pMQI->txBufferFull == 1, LEVEL_ERROR, LEVEL_INFO, + "buffer is full (waiting for %d free elements, got %d)\n", + pCQE->elemCount, i); nvStatus = NV_ERR_BUSY_RETRY; goto done; } @@ -701,7 +715,17 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) continue; // Retry if checksum fails. - if (_checkSum32(pMQI->pCmdQueueElement, (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN)) != 0) + if (gpuIsCCFeatureEnabled(pGpu)) + { + // In Confidential Compute scenario, checksum includes complete element range. + if (_checkSum32(pMQI->pCmdQueueElement, (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN)) != 0) + { + NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n"); + nvStatus = NV_ERR_INVALID_DATA; + continue; + } + } else + if (_checkSum32(pMQI->pCmdQueueElement, uElementSize) != 0) { NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n"); nvStatus = NV_ERR_INVALID_DATA; @@ -754,9 +778,9 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) } } - ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); - if (pCC != NULL && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENCRYPT_READY)) + if (gpuIsCCFeatureEnabled(pGpu)) { + ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); nvStatus = ccslDecrypt(pCC->pRpcCcslCtx, (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN) - GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, ((NvU8*)pMQI->pCmdQueueElement) + GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, @@ -766,10 +790,11 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu) ((NvU8*)pMQI->pCmdQueueElement) + GSP_MSG_QUEUE_ELEMENT_HDR_SIZE, ((NvU8*)pMQI->pCmdQueueElement->authTagBuffer)); - if(nvStatus != NV_OK) + if (nvStatus != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Decryption failed with status = 0x%x.\n", nvStatus); - // Do not re-try if decryption failed. + // Do not re-try if decryption failed. Decryption failure is considered fatal. + NV_PRINTF(LEVEL_ERROR, "Fatal error detected in RPC decrypt: 0x%x!\n", nvStatus); + confComputeSetErrorState(pGpu, pCC); return nvStatus; } } diff --git a/src/nvidia/src/kernel/gpu/host_eng/host_eng.c b/src/nvidia/src/kernel/gpu/host_eng/host_eng.c index 6a0fe42d49..13570e5a9c 100644 --- a/src/nvidia/src/kernel/gpu/host_eng/host_eng.c +++ b/src/nvidia/src/kernel/gpu/host_eng/host_eng.c @@ -24,7 +24,6 @@ #include "core/prelude.h" #include "kernel/gpu/host_eng/host_eng.h" #include "core/hal.h" -#include "core/info_block.h" #include "os/os.h" /*! diff --git a/src/nvidia/src/kernel/gpu/hwpm/arch/hopper/kern_hwpm_gh100.c b/src/nvidia/src/kernel/gpu/hwpm/arch/hopper/kern_hwpm_gh100.c new file mode 100644 index 0000000000..1d1364fa95 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/hwpm/arch/hopper/kern_hwpm_gh100.c @@ -0,0 +1,48 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/hwpm/kern_hwpm.h" +#include "hopper/gh100/dev_perf.h" + +/*! + * @brief Get number of CBLOCKs per SYS chiplet and number of channels per CBLOCK + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelHwpm KernelHwpm pointer + * @param[out] pNumCblock The number of Cblocks per SYS chiplet + * @param[out] pNumChannels The number of Channels per Cblocks + */ +void +khwpmGetCblockInfo_GH100(OBJGPU *pGpu, KernelHwpm *pKernelHwpm, NvU32 *pNumCblock, NvU32 *pNumChannels) +{ + // In GH100, each channel has a bind point controller, so 1 channel/cblock => # cblock = # channel. + if (pNumCblock != NULL) + { + *pNumCblock = NV_PERF_PMMSYSROUTER_NUM_USER_STREAMING_CHANNELS; + } + + if (pNumChannels != NULL) + { + *pNumChannels = 1; + } +} diff --git a/src/nvidia/src/kernel/gpu/hwpm/arch/maxwell/kern_hwpm_gm107.c b/src/nvidia/src/kernel/gpu/hwpm/arch/maxwell/kern_hwpm_gm107.c new file mode 100644 index 0000000000..458734b481 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/hwpm/arch/maxwell/kern_hwpm_gm107.c @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/hwpm/kern_hwpm.h" + +/*! + * @brief Get number of CBLOCKs per SYS chiplet and number of channels per CBLOCK + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelHwpm KernelHwpm pointer + * @param[out] pNumCblock The number of Cblocks per SYS chiplet + * @param[out] pNumChannels The number of Channels per Cblocks + */ +void +khwpmGetCblockInfo_GM107(OBJGPU *pGpu, KernelHwpm *pKernelHwpm, NvU32 *pNumCblock, NvU32 *pNumChannels) +{ + // No Cblock concept, we can treat 1 channel/cblock/sys chiplet + if (pNumCblock != NULL) + { + *pNumCblock = 1; + } + + if (pNumChannels != NULL) + { + *pNumChannels = 1; + } +} diff --git a/src/nvidia/src/kernel/gpu/hwpm/kern_hwpm.c b/src/nvidia/src/kernel/gpu/hwpm/kern_hwpm.c new file mode 100644 index 0000000000..41af2edf0b --- /dev/null +++ b/src/nvidia/src/kernel/gpu/hwpm/kern_hwpm.c @@ -0,0 +1,268 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief Collection of interfaces for perf profiling + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "gpu/hwpm/kern_hwpm.h" +#include "ctrl/ctrlb0cc.h" + +/* ------------------------ Static Function Prototypes --------------------- */ +static RefcntStateChangeCallback _khwpmProfilerPmaVaSpaceAllocStateChange; + +/* ------------------------ Public Functions ------------------------------ */ + +static NV_STATUS +_khwpmProfilerPmaVaSpaceAllocStateChange +( + POBJREFCNT pRefcnt, + Dynamic *pDynamic, + REFCNT_STATE oldState, + REFCNT_STATE newState +) +{ + NV_STATUS status = NV_OK; + NvBool bCreateVaSpace = NV_FALSE; + KernelHwpm *pKernelHwpm = dynamicCast(pDynamic, KernelHwpm); + NvU32 bpcIdx; + POBJGPU pGpu; + + if (pRefcnt == NULL) + { + return NV_ERR_INVALID_STATE; + } + + if (pKernelHwpm == NULL) + { + return NV_ERR_INVALID_STATE; + } + + pGpu = ENG_GET_GPU(pKernelHwpm); + if (pGpu == NULL) + { + return NV_ERR_INVALID_STATE; + } + + bCreateVaSpace = (newState == REFCNT_STATE_ENABLED); + bpcIdx = pRefcnt->tag; + NV_ASSERT_OR_RETURN(bpcIdx < pKernelHwpm->maxCblocks, NV_ERR_INVALID_STATE); + + if (bCreateVaSpace) + { + if (pKernelHwpm->streamoutState[bpcIdx].bPmaVasRequested) + { + return NV_ERR_STATE_IN_USE; + } + + status = khwpmStreamoutCreatePmaVaSpace(pGpu, pKernelHwpm, bpcIdx); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate PMA VA space for CBLOCK ID 0x%x. Error 0x%x\n", bpcIdx, status); + return status; + } + + pKernelHwpm->streamoutState[bpcIdx].bPmaVasRequested = NV_TRUE; + } + else + { + if (!pKernelHwpm->streamoutState[bpcIdx].bPmaVasRequested) + { + return NV_ERR_INVALID_STATE; + } + + status = khwpmStreamoutFreePmaVaSpace(pGpu, pKernelHwpm, bpcIdx); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to free PMA VA space for CBLOCK ID 0x%x. Error 0x%x\n", bpcIdx, status); + return status; + } + + pKernelHwpm->streamoutState[bpcIdx].bPmaVasRequested = NV_FALSE; + } + + return status; +} + +/*! + * @brief Creates the refcount object for HWPM Pma VA space + * for a given PMA Channel ID + */ +static NV_STATUS +_khwpmProfilerPmaVaSpaceRefcntInit +( + POBJGPU pGpu, + KernelHwpm *pKernelHwpm, + NvU32 bpcIdx +) +{ + NV_STATUS status = NV_OK; + OBJREFCNT *pPmaVasRefcnt = NULL; + + status = objCreate(&pPmaVasRefcnt, pKernelHwpm, OBJREFCNT, + staticCast(pKernelHwpm, Dynamic), bpcIdx, &_khwpmProfilerPmaVaSpaceAllocStateChange, NULL); + if (status != NV_OK) + { + return status; + } + + pKernelHwpm->streamoutState[bpcIdx].pPmaVasRefcnt = pPmaVasRefcnt; + + return status; +} + +static NV_STATUS +_khwpmInitPmaStreamAttributes +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm +) +{ + pKernelHwpm->numPma = pKernelHwpm->getProperty(pKernelHwpm, PDB_PROP_KHWPM_MULTIPLE_PMA_SUPPORTED) ? 2 : 1; + NV_ASSERT_OR_RETURN(pKernelHwpm->numPma <= MAX_PMA_CREDIT_POOL, NV_ERR_INVALID_STATE); + + khwpmGetCblockInfo_HAL(pGpu, pKernelHwpm, &pKernelHwpm->maxCblocksPerPma, &pKernelHwpm->maxChannelPerCblock); + + pKernelHwpm->maxPmaChannels = + pKernelHwpm->maxCblocksPerPma * pKernelHwpm->maxChannelPerCblock * pKernelHwpm->numPma; + pKernelHwpm->maxCblocks = pKernelHwpm->numPma * pKernelHwpm->maxCblocksPerPma; + + return NV_OK; +} + +NV_STATUS +khwpmStateInitUnlocked_IMPL +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm +) +{ + NV_STATUS status = NV_OK; + NvU32 bpcIdx; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + _khwpmInitPmaStreamAttributes(pGpu, pKernelHwpm), khwpmStateInitUnlocked_exit); + + // Except full SRIOV, VA space creation is not required on vGPU guest + // It will happen on vGPU host + if (IS_VIRTUAL(pGpu) && !IS_SRIOV_FULL_GUEST(pGpu)) + { + goto khwpmStateInitUnlocked_exit; + } + + pKernelHwpm->vaSpaceBase = PERF_VASPACE_BASE; + + pKernelHwpm->vaSpaceSize = PERF_VASPACE_SIZE - PERF_VASPACE_BASE; + + pKernelHwpm->streamoutState = portMemAllocNonPaged(sizeof(HWPM_STREAMOUT_STATE) * pKernelHwpm->maxCblocks); + if (pKernelHwpm->streamoutState == NULL) + { + status = NV_ERR_NO_MEMORY; + goto khwpmStateInitUnlocked_exit; + } + + portMemSet(pKernelHwpm->streamoutState, 0, (sizeof(HWPM_STREAMOUT_STATE) * pKernelHwpm->maxCblocks)); + + for (bpcIdx = 0; bpcIdx < pKernelHwpm->maxCblocks; bpcIdx++) + { + status = _khwpmProfilerPmaVaSpaceRefcntInit(pGpu, pKernelHwpm, bpcIdx); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Initialization of VaSpace Refcnt objects failed!\n"); + goto khwpmStateInitUnlocked_exit; + } + } + +khwpmStateInitUnlocked_exit: + if (status != NV_OK) + { + khwpmStateDestroy(pGpu, pKernelHwpm); + } + return status; +} + +void +khwpmStateDestroy_IMPL +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm +) +{ + NvU32 bpcIdx; + + if (pKernelHwpm->streamoutState != NULL) + { + for (bpcIdx = 0; bpcIdx < pKernelHwpm->maxCblocks; bpcIdx++) + { + objDelete(pKernelHwpm->streamoutState[bpcIdx].pPmaVasRefcnt); + pKernelHwpm->streamoutState[bpcIdx].pPmaVasRefcnt = NULL; + } + portMemFree(pKernelHwpm->streamoutState); + } +} + +NV_STATUS +khwpmGetRequestCgStatusMask +( + NvU32 *pCgStatusMask, + HWPM_POWER_REQUEST_FEATURES_PARAMS *pParams +) +{ +#define HWPM_PROFILER_GET_REQUEST_CG_STATUS_MASKS(powerFeature) \ + do \ + { \ + NvU32 profilerCgStatus = 0; \ + NvU32 status = REF_VAL(HWPM_POWER_FEATURE_MASK_##powerFeature, pParams->statusMask); \ + switch (status) \ + { \ + case HWPM_POWER_FEATURE_REQUEST_FULFILLED: \ + profilerCgStatus = NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FULFILLED; \ + break; \ + case HWPM_POWER_FEATURE_REQUEST_REJECTED: \ + profilerCgStatus = NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_REJECTED; \ + break; \ + case HWPM_POWER_FEATURE_REQUEST_NOT_SUPPORTED: \ + profilerCgStatus = NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_NOT_SUPPORTED; \ + break; \ + case HWPM_POWER_FEATURE_REQUEST_FAILED: \ + profilerCgStatus = NVB0CC_CTRL_PROFILER_CG_CONTROL_REQUEST_FAILED; \ + break; \ + default: \ + return NV_ERR_INVALID_ARGUMENT; \ + } \ + *pCgStatusMask = FLD_SET_DRF_NUM(B0CC, _CTRL_PROFILER_CG_CONTROL_MASK, \ + _##powerFeature, profilerCgStatus, (*pCgStatusMask)); \ + } \ + while (0) + + HWPM_PROFILER_GET_REQUEST_CG_STATUS_MASKS(ELCG); + HWPM_PROFILER_GET_REQUEST_CG_STATUS_MASKS(BLCG); + HWPM_PROFILER_GET_REQUEST_CG_STATUS_MASKS(SLCG); + HWPM_PROFILER_GET_REQUEST_CG_STATUS_MASKS(ELPG); + HWPM_PROFILER_GET_REQUEST_CG_STATUS_MASKS(IDLE_SLOWDOWN); + +#undef HWPM_PROFILER_GET_REQUEST_CG_STATUS_MASKS + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/hwpm/kern_hwpm_streamout.c b/src/nvidia/src/kernel/gpu/hwpm/kern_hwpm_streamout.c new file mode 100644 index 0000000000..776f351b57 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/hwpm/kern_hwpm_streamout.c @@ -0,0 +1,587 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief Collection of interfaces for HWPM streamout + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "gpu/hwpm/kern_hwpm.h" +#include "lib/ref_count.h" +#include "gpu/gpu.h" +#include "gpu/mmu/kern_gmmu.h" +#include "mem_mgr/vaspace.h" +#include "mem_mgr/virt_mem_mgr.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/virt_mem_allocator.h" +#include "resserv/rs_client.h" +#include "vgpu/rpc.h" +#include "virtualization/hypervisor/hypervisor.h" +#include "gpu/bus/kern_bus.h" + +#include "ctrl/ctrl90cc.h" +#include "ctrl/ctrlb0cc.h" +#include "class/cl90f1.h" //FERMI_VASPACE_A +#include "rmapi/rs_utils.h" +#include "nvrm_registry.h" + +/* ------------------------ Macros ----------------------------------------- */ +#define PERF_PER_CTX_VASPACE_SIZE (4*1024*1024*1024ULL) + +/* ------------------------ Public Functions ------------------------------ */ + +static NV_STATUS +_hwpmStreamoutAllocPmaMapping +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm, + OBJVASPACE *pPmaVAS, + MEMORY_DESCRIPTOR *pMemDesc, + NvU64 virtualAddress +) +{ + VirtMemAllocator *pDma = GPU_GET_DMA(pGpu); + NvU32 flags = DRF_DEF(OS46, _FLAGS, _DMA_UNICAST_REUSE_ALLOC, _TRUE); + + if (RMCFG_FEATURE_PLATFORM_GSP || + (memdescGetCpuCacheAttrib(pMemDesc) == NV_MEMORY_CACHED)) + { + flags |= FLD_SET_DRF(OS46, _FLAGS, _CACHE_SNOOP, _ENABLE, flags); + } + + // Map it in PMA VA + return dmaAllocMapping_HAL(pGpu, pDma, pPmaVAS, pMemDesc, &virtualAddress, flags, NULL, KMIGMGR_SWIZZID_INVALID); +} + +static NV_STATUS +_hwpmStreamoutAllocCpuMapping +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm, + OBJVASPACE *pPmaVAS, + MEMORY_DESCRIPTOR *pMemDesc, + NvP64 *ppCpuAddr, + NvP64 *ppPriv +) +{ + NvP64 pAddr64 = NvP64_NULL; + NvU8 *pBuf = NULL; + NV_STATUS status = NV_OK; + + if (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) + { + pBuf = kbusMapRmAperture_HAL(pGpu, pMemDesc); + if (pBuf == NULL) + { + NV_PRINTF(LEVEL_ERROR, "busMapRmAperture_HAL failed\n"); + status = NV_ERR_GENERIC; + goto _hwpmStreamoutAllocCpuMapping_fail; + } + pAddr64 = NV_PTR_TO_NvP64(pBuf); + } + else + { + status = memdescMap(pMemDesc, 0, pMemDesc->Size, NV_TRUE, NV_PROTECT_READ_WRITE, + &pAddr64, ppPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "memdescMap failed: 0x%x\n", status); + goto _hwpmStreamoutAllocCpuMapping_fail; + } + } + + *ppCpuAddr = pAddr64; + + return NV_OK; + +_hwpmStreamoutAllocCpuMapping_fail: + NV_PRINTF(LEVEL_ERROR, "Error: 0x%x\n", status); + + return status; +} + +static void +_hwpmStreamoutFreeCpuMapping +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm, + OBJVASPACE *pPmaVAS, + MEMORY_DESCRIPTOR *pMemDesc, + NvP64 pCpuAddr, + NvP64 pPriv +) +{ + NvU8 *pCpuAddrTmp = NvP64_VALUE(pCpuAddr); + + if (pCpuAddrTmp != NULL) + { + if (memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) + { + kbusUnmapRmAperture_HAL(pGpu, pMemDesc, &pCpuAddrTmp, NV_TRUE); + } + else + { + memdescUnmap(pMemDesc, NV_TRUE, osGetCurrentProcess(), pCpuAddr, pPriv); + } + } +} + +/*! + * @brief: Allocates a PMA stream for HWPM to streamout records. + * + * Each PMA stream can have upto 4GB of VA space, and PMA stream can not straddle + * 4GB boundary. + * Caller needs to provide two memory buffers, one for streaming records, and other + * for streaming mem bytes (unread bytes). + */ +NV_STATUS +khwpmStreamoutAllocPmaStream_IMPL +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm, + NvU64 profilerId, + MEMORY_DESCRIPTOR *pRecordBufDesc, + MEMORY_DESCRIPTOR *pNumBytesBufDesc, + NvU32 pmaChIdx, + HWPM_PMA_STREAM *pPmaStream +) +{ + OBJVASPACE *pPmaVAS; + NvU64 virtSize; + NvU64 virtualAddress = 0; + NvU64 virtualAddress2 = 0; + NvU64 vaAlign; + NvU64 pageSize; + NvU64 vaSizeRequested; + VAS_ALLOC_FLAGS allocFlags = {0}; + NV_STATUS status = NV_OK; + NvP64 pCpuAddr = NvP64_NULL; + NvP64 pPriv = NvP64_NULL; + NvU32 gfid; + const NvU32 bpcIdx = pmaChIdx / pKernelHwpm->maxChannelPerCblock; + OBJREFCNT *pRefcnt; + NvBool bRefCnted = NV_FALSE; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, (bpcIdx < pKernelHwpm->maxCblocks), NV_ERR_INVALID_ARGUMENT); + + pRefcnt = pKernelHwpm->streamoutState[bpcIdx].pPmaVasRefcnt; + if (pRefcnt == NULL) + { + return NV_ERR_INVALID_STATE; + } + + NV_ASSERT_OK_OR_RETURN(refcntRequestReference(pRefcnt, profilerId, REFCNT_STATE_ENABLED, NV_FALSE)); + bRefCnted = NV_TRUE; + + pPmaVAS = pKernelHwpm->streamoutState[bpcIdx].pPmaVAS; + if (pPmaVAS == NULL) + { + status = NV_ERR_INVALID_STATE; + goto hwpmStreamoutAllocPmaStream_fail; + } + + if (pPmaStream->bValid) + { + status = NV_ERR_INVALID_STATE; + goto hwpmStreamoutAllocPmaStream_fail; + } + + pageSize = vaspaceGetBigPageSize(pPmaVAS); + vaSizeRequested = RM_ALIGN_UP(pRecordBufDesc->Size, pageSize) + RM_ALIGN_UP(pNumBytesBufDesc->Size, pageSize); + if (vaSizeRequested > PERF_PER_CTX_VASPACE_SIZE) + { + status = NV_ERR_INVALID_ARGUMENT; + goto hwpmStreamoutAllocPmaStream_fail; + } + + allocFlags.bLazy = NV_TRUE; + virtSize = PERF_PER_CTX_VASPACE_SIZE; + vaAlign = virtSize; + status = vaspaceAlloc(pPmaVAS, virtSize, vaAlign, + vaspaceGetVaStart(pPmaVAS), vaspaceGetVaLimit(pPmaVAS), + 0, allocFlags, &virtualAddress); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "vaspaceAlloc failed: 0x%08x\n", status); + goto hwpmStreamoutAllocPmaStream_fail; + } + + status = _hwpmStreamoutAllocPmaMapping(pGpu, pKernelHwpm, pPmaVAS, pRecordBufDesc, virtualAddress); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to map records buffer to pma vaspace: 0x%08x\n", + status); + goto hwpmStreamoutAllocPmaStream_fail; + } + + // memBytes va start right after record buffer va. + virtualAddress2 = virtualAddress + RM_ALIGN_UP(pRecordBufDesc->Size, pageSize); + status = _hwpmStreamoutAllocPmaMapping(pGpu, pKernelHwpm, pPmaVAS, pNumBytesBufDesc, virtualAddress2); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to map available bytes buffer to pma vaspace: 0x%08x\n", + status); + goto hwpmStreamoutAllocPmaStream_fail; + } + + pPmaStream->flags = 0; + + // CPU mapping of membytes buffer is not required on vGPU host, will be handled on guest + NV_ASSERT_OK_OR_GOTO(status, vgpuGetCallingContextGfid(pGpu, &gfid), + hwpmStreamoutAllocPmaStream_fail); + if (!(hypervisorIsVgxHyper() || (RMCFG_FEATURE_PLATFORM_GSP && IS_GFID_VF(gfid)))) + { + // If this is a WSL profiler using DMA remapping support, we already have + // the CPUVA in pNumBytesBufDesc->_pMemData + if (pNumBytesBufDesc->_pMemData) + { + pCpuAddr = pNumBytesBufDesc->_pMemData; + pPriv = pNumBytesBufDesc->_pMemData; + + // Set the _pMemData fields to NULL. Otherwise, osDestroyMemCreatedFromOsDescriptor() + // will interpret the _pMemData as a pointer to a SYS_MEM_INFO structure. + pRecordBufDesc->_pMemData = NvP64_NULL; + pNumBytesBufDesc->_pMemData = NvP64_NULL; + pPmaStream->flags |= NV_HWPM_STREAM_FLAGS_CPUVA_EXTERNAL; + status = NV_OK; + } + else + { + status = _hwpmStreamoutAllocCpuMapping(pGpu, pKernelHwpm, pPmaVAS, pNumBytesBufDesc, &pCpuAddr, &pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to map available bytes buffer to cpu vaspace: 0x%08x\n", + status); + goto hwpmStreamoutAllocPmaStream_fail; + } + } + } + + pPmaStream->pRecordBufDesc = pRecordBufDesc; + pPmaStream->pNumBytesBufDesc = pNumBytesBufDesc; + pPmaStream->pNumBytesCpuAddr = pCpuAddr; + pPmaStream->pNumBytesCpuAddrPriv = pPriv; + pPmaStream->vaddr = virtualAddress; + pPmaStream->vaddrRecordBuf = virtualAddress; + pPmaStream->vaddrNumBytesBuf = virtualAddress2; + pPmaStream->size = pRecordBufDesc->Size; + pPmaStream->pmaChannelIdx = pmaChIdx; + pPmaStream->bValid = NV_TRUE; + + return NV_OK; + +hwpmStreamoutAllocPmaStream_fail: + if (pCpuAddr != NvP64_NULL) + { + _hwpmStreamoutFreeCpuMapping(pGpu, pKernelHwpm, pPmaVAS, pNumBytesBufDesc, pCpuAddr, pPriv); + } + + if (virtualAddress != 0) + { + // free va allocations and mappings + vaspaceFree(pPmaVAS, virtualAddress); + } + + if (bRefCnted) + { + status = refcntReleaseReferences(pRefcnt, profilerId, NV_FALSE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Releasing pPmaVasRefcnt failed on pmChIdx-%d.\n", pmaChIdx); + } + } + + return status; +} + +/*! + * @brief: Frees a PMA stream. + */ +NV_STATUS +khwpmStreamoutFreePmaStream_IMPL +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm, + NvU64 profilerId, + HWPM_PMA_STREAM *pPmaStream, + NvU32 pmaChIdx +) +{ + NV_STATUS status = NV_OK; + OBJVASPACE *pPmaVAS; + const NvU32 bpcIdx = pmaChIdx / pKernelHwpm->maxChannelPerCblock; + OBJREFCNT *pRefcnt; + + NV_ASSERT_OR_RETURN(bpcIdx < pKernelHwpm->maxCblocks, NV_ERR_INVALID_ARGUMENT); + + pRefcnt = pKernelHwpm->streamoutState[bpcIdx].pPmaVasRefcnt; + if (pRefcnt == NULL) + { + return NV_ERR_INVALID_STATE; + } + + pPmaVAS = pKernelHwpm->streamoutState[bpcIdx].pPmaVAS; + if (pPmaVAS == NULL) + { + return NV_ERR_INVALID_STATE; + } + + if (!pPmaStream->bValid) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // If there is a CPU address and it was not allocated externally, free + // the internal CPU mapping. + if ((pPmaStream->pNumBytesCpuAddr != NvP64_NULL) && + (!(pPmaStream->flags & NV_HWPM_STREAM_FLAGS_CPUVA_EXTERNAL))) + { + _hwpmStreamoutFreeCpuMapping(pGpu, pKernelHwpm, pPmaVAS, pPmaStream->pNumBytesBufDesc, pPmaStream->pNumBytesCpuAddr, + pPmaStream->pNumBytesCpuAddrPriv); + } + pPmaStream->pNumBytesCpuAddr = NvP64_NULL; + pPmaStream->pNumBytesCpuAddrPriv = NvP64_NULL; + + if (pPmaStream->vaddr != 0) + { + vaspaceFree(pPmaVAS, pPmaStream->vaddr); + } + pPmaStream->vaddr = 0; + pPmaStream->size = 0; + + memdescDestroy(pPmaStream->pRecordBufDesc); + pPmaStream->pRecordBufDesc = NULL; + pPmaStream->vaddrRecordBuf = 0; + + memdescDestroy(pPmaStream->pNumBytesBufDesc); + pPmaStream->pNumBytesBufDesc = NULL; + pPmaStream->vaddrNumBytesBuf = 0; + + pPmaStream->pmaChannelIdx = INVALID_PMA_CHANNEL_IDX; + pPmaStream->bValid = NV_FALSE; + + status = refcntReleaseReferences(pRefcnt, profilerId, NV_FALSE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Releasing pPmaVasRefcnt failed on pmChIdx-%d.\n", pmaChIdx); + } + + return status; +} + +static NV_STATUS +khwpmInstBlkConstruct(OBJGPU *pGpu, KernelHwpm *pKernelHwpm, NvU32 bpcIdx) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NV_STATUS status; + NvU32 allocFlags = MEMDESC_FLAGS_NONE; + MEMORY_DESCRIPTOR *pInstBlkMemDesc = NULL; + NvU32 addrSpace = ADDR_FBMEM; + NvU32 attr = NV_MEMORY_WRITECOMBINED; + + memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_4, _HWPM_PMA, pGpu->instLocOverrides4), + "HWPM PMA instblk", &addrSpace, &attr); + + if ((status = memdescCreate(&pInstBlkMemDesc, pGpu, + GF100_BUS_INSTANCEBLOCK_SIZE, + GF100_BUS_INSTANCEBLOCK_SIZE, + NV_TRUE, + addrSpace, + attr, + allocFlags)) != NV_OK) + { + goto constructInstBlkMemDesc_fail; + } + + if ((memdescGetAddressSpace(pInstBlkMemDesc) == ADDR_SYSMEM) && + (gpuIsInstanceMemoryAlwaysCached(pGpu))) + { + memdescSetGpuCacheAttrib(pInstBlkMemDesc, NV_MEMORY_CACHED); + } + + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_59, + pInstBlkMemDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "couldn't allocate PERF instblk!\n"); + goto constructInstBlkMemDesc_fail; + } + + status = memmgrMemDescMemSet(pMemoryManager, pInstBlkMemDesc, 0, TRANSFER_FLAGS_NONE); + if (NV_OK != status) + { + goto constructInstBlkMemDesc_fail; + } + + pKernelHwpm->streamoutState[bpcIdx].pInstBlkMemDesc = pInstBlkMemDesc; + + return NV_OK; + +constructInstBlkMemDesc_fail: + if (pInstBlkMemDesc != NULL) + { + memdescFree(pInstBlkMemDesc); + memdescDestroy(pInstBlkMemDesc); + } + return status; +} + +static NV_STATUS +khwpmStreamoutInstBlkDestruct(OBJGPU *pGpu, KernelHwpm *pKernelHwpm, NvU32 bpcIdx) +{ + // Free the Instblk Surface resources + if (pKernelHwpm->streamoutState[bpcIdx].pInstBlkMemDesc != NULL) + { + memdescFree(pKernelHwpm->streamoutState[bpcIdx].pInstBlkMemDesc); + memdescDestroy(pKernelHwpm->streamoutState[bpcIdx].pInstBlkMemDesc); + pKernelHwpm->streamoutState[bpcIdx].pInstBlkMemDesc = NULL; + } + + return NV_OK; +} + +/*! + * @brief: Creates VA Space and Inst block corresponding to a + * given Channel ID (for full SRIOV guest) + */ +NV_STATUS +khwpmStreamoutCreatePmaVaSpace_IMPL +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm, + NvU32 bpcIdx +) +{ + OBJVMM *pVmm = SYS_GET_VMM(SYS_GET_INSTANCE()); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + OBJVASPACE *pVAS = NULL; + NvU64 vaSpaceStartAddr = pKernelHwpm->vaSpaceBase; + NvU64 vaRangeLimit = pKernelHwpm->vaSpaceBase + pKernelHwpm->vaSpaceSize - 1; + NvBool bRootPageDirPinned = NV_FALSE; + NvU32 flags; + NV_STATUS status; + INST_BLK_INIT_PARAMS params = {0}; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, (bpcIdx < pKernelHwpm->maxCblocks), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN((pKernelHwpm->streamoutState[bpcIdx].pPmaVAS == NULL), NV_ERR_INVALID_STATE); + + status = khwpmInstBlkConstruct(pGpu, pKernelHwpm, bpcIdx); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to construct PMA Instance block. Status 0x%x\n", + status); + goto khwpmStreamoutCreatePmaVaSpace_fail; + } + + // Initialize a heap for PERF VASpace + flags = DRF_DEF(_VASPACE, _FLAGS, _BIG_PAGE_SIZE, _DEFAULT) | + VASPACE_FLAGS_ENABLE_VMM | + VASPACE_FLAGS_HWPM; + + status = vmmCreateVaspace(pVmm, FERMI_VASPACE_A, 0, NVBIT(pGpu->gpuInstance), + vaSpaceStartAddr, vaRangeLimit, 0, 0, NULL, + flags, &pVAS); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Could not construct PMA vaspace object. Status 0x%x\n", + status); + pVAS = NULL; + goto khwpmStreamoutCreatePmaVaSpace_fail; + } + + status = vaspacePinRootPageDir(pVAS, pGpu); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Error Locking down VA space root.\n"); + goto khwpmStreamoutCreatePmaVaSpace_fail; + } + bRootPageDirPinned = NV_TRUE; + + status = kgmmuInstBlkInit(pKernelGmmu, pKernelHwpm->streamoutState[bpcIdx].pInstBlkMemDesc, + pVAS, FIFO_PDB_IDX_BASE, ¶ms); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error initializing HWPM PMA Instance Block.\n"); + goto khwpmStreamoutCreatePmaVaSpace_fail; + } + + pKernelHwpm->streamoutState[bpcIdx].pPmaVAS = pVAS; + + return NV_OK; + +khwpmStreamoutCreatePmaVaSpace_fail: + if (bRootPageDirPinned) + { + vaspaceUnpinRootPageDir(pVAS, pGpu); + } + if (pVAS != NULL) + { + vmmDestroyVaspace(pVmm, pVAS); + } + khwpmStreamoutInstBlkDestruct(pGpu, pKernelHwpm, bpcIdx); + pKernelHwpm->streamoutState[bpcIdx].pPmaVAS = NULL; + + return status; +} + +/*! + * @brief: Frees VA Space and Inst block (for full SRIOV guest) + */ +NV_STATUS +khwpmStreamoutFreePmaVaSpace_IMPL +( + OBJGPU *pGpu, + KernelHwpm *pKernelHwpm, + NvU32 bpcIdx +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJVMM *pVmm = SYS_GET_VMM(pSys); + OBJVASPACE *pVAS; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, (bpcIdx < pKernelHwpm->maxCblocks), NV_ERR_INVALID_ARGUMENT); + + pVAS = pKernelHwpm->streamoutState[bpcIdx].pPmaVAS; + if (pVAS != NULL) + { + vaspaceUnpinRootPageDir(pVAS, pGpu); + vmmDestroyVaspace(pVmm, pVAS); + khwpmStreamoutInstBlkDestruct(pGpu, pKernelHwpm, bpcIdx); + pKernelHwpm->streamoutState[bpcIdx].pPmaVAS = NULL; + } + + // Reset GFID in SRIOV mode + if (gpuIsSriovEnabled(pGpu)) + { + khwpmPmaStreamSriovSetGfid_HAL(pGpu, pKernelHwpm, bpcIdx, 0); + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c index f05271246b..dfb13b61d8 100644 --- a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c +++ b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c @@ -22,6 +22,7 @@ */ #include "gpu/hwpm/profiler_v2.h" +#include "gpu/hwpm/kern_hwpm.h" #include "vgpu/rpc.h" static NV_INLINE NvBool @@ -77,6 +78,22 @@ profilerBaseConstruct_IMPL return profilerBaseConstructState_HAL(pProf, pCallContext, pParams); } +NV_STATUS +profilerBaseConstructState_IMPL +( + ProfilerBase *pProf, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + RsClient *pRsClient = pCallContext->pClient; + + pProf->profilerId = NV_REQUESTER_CLIENT_OBJECT(pRsClient->hClient, pCallContext->pResourceRef->hResource); + pProf->bMmaBoostDisabled = NV_FALSE; + + return NV_OK; +} + void profilerBaseDestruct_IMPL ( @@ -86,6 +103,167 @@ profilerBaseDestruct_IMPL profilerBaseDestructState_HAL(pProf); } +static NV_STATUS +_profilerPollForUpdatedMembytes(ProfilerBase *pProfBase, OBJGPU *pGpu, KernelHwpm *pKernelHwpm, NvU32 pmaChIdx) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout = {0}; + volatile NvU32 *pMemBytesAddr = NvP64_VALUE(pProfBase->pPmaStreamList[pmaChIdx].pNumBytesCpuAddr); + + if (pMemBytesAddr == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid MEM_BYTES_ADDR.\n"); + return NV_ERR_INVALID_STATE; + } + + threadStateResetTimeout(pGpu); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + while (*pMemBytesAddr == NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE) + { + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, + "timeout occurred while waiting for PM streamout to idle.\n"); + break; + } + osSpinLoop(); + status = gpuCheckTimeout(pGpu, &timeout); + } + + NV_PRINTF(LEVEL_INFO, "status=0x%08x, *MEM_BYTES_ADDR=0x%08x.\n", status, + *pMemBytesAddr); + + return status; +} + +/* + * This function does the following: + * 1. Initialize membytes buffer on guest, ensuring no membytes streamout is in progress. + * 2. Issue RPC to vGPU host to idle PMA channel and trigger membytes streaming. + * 3. If required, wait on guest until updated membytes value is received + */ +NV_STATUS profilerBaseQuiesceStreamout_IMPL(ProfilerBase *pProf, OBJGPU *pGpu, KernelHwpm *pKernelHwpm, NvU32 pmaChIdx) +{ + NV_STATUS rmStatus = NV_OK; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS pmaIdleParams = {0}; + + if (pProf->pPmaStreamList == NULL) + return NV_ERR_INVALID_STATE; + + volatile NvU32 *pMemBytesAddr = NvP64_VALUE(pProf->pPmaStreamList[pmaChIdx].pNumBytesCpuAddr); + + if (pMemBytesAddr == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Invalid MEM_BYTES_ADDR.\n"); + return NV_ERR_INVALID_STATE; + } + + // Check if any membytes streamout is in progress + if (*pMemBytesAddr == NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE) + { + // Complete any pending membytes streamout + rmStatus = _profilerPollForUpdatedMembytes(pProf, pGpu, pKernelHwpm, pmaChIdx); + } + + *pMemBytesAddr = NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE; + + pmaIdleParams.pmaChannelIdx = pmaChIdx; + + // Issue RPC to quiesce PMA channel + NV_RM_RPC_CONTROL(pGpu, + pCallContext->pClient->hClient, + pCallContext->pResourceRef->hResource, + NVB0CC_CTRL_CMD_INTERNAL_QUIESCE_PMA_CHANNEL, + &pmaIdleParams, sizeof(NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS), + rmStatus); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Waiting for PMA to be idle failed with error 0x%x\n", + rmStatus); + return rmStatus; + } + + // If membytes streaming was triggered, wait on guest for it to complete + if (pmaIdleParams.bMembytesPollingRequired) + { + rmStatus = _profilerPollForUpdatedMembytes(pProf, pGpu, pKernelHwpm, pmaChIdx); + } + + return rmStatus; +} + +void +profilerBaseDestructState_VF +( + ProfilerBase *pProf +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProf); + KernelHwpm *pKernelHwpm = GPU_GET_KERNEL_HWPM(pGpu); + NvU32 pmaChIdx; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NV_STATUS rmStatus = NV_OK; + + if (pProf->pPmaStreamList == NULL) + return; + + // Handle quiesce streamout on guest, then issue RPC to free Profiler + // object on host, which will handle rest of the teardown + for (pmaChIdx = 0; pmaChIdx < pKernelHwpm->maxPmaChannels; pmaChIdx++) + { + if (!pProf->pPmaStreamList[pmaChIdx].bValid) + { + continue; + } + + rmStatus = profilerBaseQuiesceStreamout(pProf, pGpu, pKernelHwpm, pmaChIdx); + } + + // Issue RPC to vGPU host to free Profiler object allocated on host + NV_RM_RPC_FREE(pGpu, + pCallContext->pClient->hClient, + pCallContext->pResourceRef->pParentRef->hResource, + pCallContext->pResourceRef->hResource, + rmStatus); + + // Free membytes CPU mapping on guest + for (pmaChIdx = 0; pmaChIdx < pKernelHwpm->maxPmaChannels; pmaChIdx++) + { + if (!pProf->pPmaStreamList[pmaChIdx].bValid) + { + continue; + } + + if (IS_SRIOV_FULL_GUEST(pGpu)) + { + khwpmStreamoutFreePmaStream(pGpu, pKernelHwpm, pProf->profilerId, + &pProf->pPmaStreamList[pmaChIdx], pmaChIdx); + continue; + } + + if (pProf->pPmaStreamList[pmaChIdx].pNumBytesCpuAddr != NvP64_NULL ) + { + memdescUnmap(pProf->pPmaStreamList[pmaChIdx].pNumBytesBufDesc, NV_TRUE, osGetCurrentProcess(), + pProf->pPmaStreamList[pmaChIdx].pNumBytesCpuAddr, + pProf->pPmaStreamList[pmaChIdx].pNumBytesCpuAddrPriv); + } + + if (pProf->pPmaStreamList[pmaChIdx].pNumBytesBufDesc != NULL ) + { + memdescFree(pProf->pPmaStreamList[pmaChIdx].pNumBytesBufDesc); + memdescDestroy(pProf->pPmaStreamList[pmaChIdx].pNumBytesBufDesc); + } + + pProf->pPmaStreamList[pmaChIdx].bValid = NV_FALSE; + } + + portMemFree(pProf->pPmaStreamList); + portMemFree(pProf->pBindPointAllocated); +} + NV_STATUS profilerDevConstruct_IMPL ( @@ -117,7 +295,7 @@ profilerDevQueryCapabilities_IMPL OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); ProfilerBase *pProfBase = staticCast(pProfDev, ProfilerBase); API_SECURITY_INFO *pSecInfo = pParams->pSecInfo; - NvBool bAnyProfilingPermitted = NV_FALSE; + NvBool bAnyProfilingPermitted = NV_FALSE; pClientPermissions->bMemoryProfilingPermitted = _isMemoryProfilingPermitted(pGpu, pProfBase); @@ -140,6 +318,78 @@ profilerDevQueryCapabilities_IMPL return bAnyProfilingPermitted; } +/* + * To be called on vGPU guest only + * Profiler object will not be fully initialized on vGPU guest, + * this request will be passed on to vGPU host. + * Initialize pPmaStreamList on guest to store details PMA stream + */ +static NV_STATUS +_profilerDevConstructVgpuGuest +( + ProfilerBase *pProfBase, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfBase); + HWPM_PMA_STREAM *pPmaStreamList = NULL; + NvBool *pBindPointAllocated = NULL; + + // Allocate the pPmaStreamList to store info about memaddr buffer CPU mapping + pPmaStreamList = portMemAllocNonPaged(sizeof(HWPM_PMA_STREAM) * pGpu->pKernelHwpm->maxPmaChannels); + if (pPmaStreamList == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pPmaStreamList, 0, sizeof(HWPM_PMA_STREAM) * pGpu->pKernelHwpm->maxPmaChannels); + + pBindPointAllocated = portMemAllocNonPaged(sizeof(NvBool) * pGpu->pKernelHwpm->maxPmaChannels); + if (pBindPointAllocated == NULL) + { + portMemFree(pPmaStreamList); + return NV_ERR_NO_MEMORY; + } + + portMemSet(pBindPointAllocated, NV_FALSE, sizeof(NvBool) * pGpu->pKernelHwpm->maxPmaChannels); + + pProfBase->pPmaStreamList = pPmaStreamList; + pProfBase->pBindPointAllocated = pBindPointAllocated; + + return NV_OK; +} + +NV_STATUS +profilerDevConstructState_VF +( + ProfilerDev *pProfDev, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams, + PROFILER_CLIENT_PERMISSIONS clientPermissions +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); + ProfilerBase *pProfBase = staticCast(pProfDev, ProfilerBase); + NV_STATUS rmStatus = NV_OK; + + NV_ASSERT_OK_OR_GOTO(rmStatus, + _profilerDevConstructVgpuGuest(pProfBase, pParams), + profilerDevConstruct_VF_exit); + + // Issue RPC to allocate Profiler object on vGPU host as well + NV_RM_RPC_ALLOC_OBJECT(pGpu, + pCallContext->pClient->hClient, + pCallContext->pResourceRef->pParentRef->hResource, + pCallContext->pResourceRef->hResource, + MAXWELL_PROFILER_DEVICE, + pParams->pAllocParams, + pParams->paramsSize, + rmStatus); + +profilerDevConstruct_VF_exit: + return rmStatus; +} + NV_STATUS profilerDevConstructState_IMPL ( @@ -169,7 +419,7 @@ profilerDevConstructStatePrologue_FWCLIENT RS_RES_ALLOC_PARAMS_INTERNAL *pAllocParams ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfDev); NvHandle hParent = RES_GET_PARENT_HANDLE(pProfDev); NvHandle hObject = RES_GET_HANDLE(pProfDev); @@ -191,8 +441,8 @@ profilerDevConstructStateInterlude_IMPL PROFILER_CLIENT_PERMISSIONS clientPermissions ) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfDev); NvHandle hObject = RES_GET_HANDLE(pProfDev); @@ -224,13 +474,13 @@ profilerDevDestructState_FWCLIENT ProfilerDev *pProfDev ) { - NvHandle hClient; - NvHandle hParent; - NvHandle hObject; + NvHandle hClient; + NvHandle hParent; + NvHandle hObject; RS_RES_FREE_PARAMS_INTERNAL *pParams; CALL_CONTEXT *pCallContext; - OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); - NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfDev); + NV_STATUS status = NV_OK; resGetFreeParams(staticCast(pProfDev, RsResource), &pCallContext, &pParams); hClient = pCallContext->pClient->hClient; diff --git a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c index b9546c5453..a226065c60 100644 --- a/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c +++ b/src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c @@ -26,6 +26,8 @@ #include "nvstatuscodes.h" #include "rmapi/rs_utils.h" #include "gpu/hwpm/profiler_v2.h" +#include "gpu/hwpm/kern_hwpm.h" +#include "gpu/hwpm/kern_hwpm_power.h" #include "ctrl/ctrlb0cc/ctrlb0ccinternal.h" #include "ctrl/ctrlb0cc/ctrlb0ccprofiler.h" #include "mem_mgr/mem.h" @@ -55,7 +57,7 @@ profilerBaseCtrlCmdFreePmaStream_IMPL NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *pParams ) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(GPU_RES_GET_GPU(pProfiler)); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(GPU_RES_GET_GPU(pProfiler)); NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS internalParams; portMemSet(&internalParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS)); @@ -81,7 +83,7 @@ profilerBaseCtrlCmdFreePmaStream_IMPL pBufferRef = pProfiler->ppStreamBuffers[pParams->pmaChannelIdx]; pProfiler->ppStreamBuffers[pParams->pmaChannelIdx] = NULL; - if(pProfiler->pBoundCntBuf == pCountRef && pProfiler->pBoundPmaBuf == pBufferRef) + if (pProfiler->pBoundCntBuf == pCountRef && pProfiler->pBoundPmaBuf == pBufferRef) { Memory *pCntMem = dynamicCast(pCountRef->pResource, Memory); Memory *pBufMem = dynamicCast(pBufferRef->pResource, Memory); @@ -352,3 +354,451 @@ profilerBaseCtrlCmdAllocPmaStream_IMPL return status; } +/* + * To be called on vGPU guest only. + * Will issue RPC to vGPU host and map memBytes buffer to guest CPU VA + */ +static NV_STATUS +_profilerBaseCtrlCmdAllocPmaStreamVgpuGuest +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams, + Memory *pMemPmaAvailBytes, + Memory *pMemPmaBuffer +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + NvP64 pPriv = NvP64_NULL; + NvP64 pCpuAddr = NvP64_NULL; + KernelHwpm *pKernelHwpm = GPU_GET_KERNEL_HWPM(pGpu); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler); + NvHandle hObject = RES_GET_HANDLE(pProfiler); + MEMORY_DESCRIPTOR *pTgtMemDescPmaAvailBytes = NULL; + MEMORY_DESCRIPTOR *pTgtMemDescPmaBuffer = NULL; + NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS promoteParams; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + // vGPU only supports PMA buffers to be allocated in sysmem + NV_ASSERT_OR_RETURN((memdescGetAddressSpace(pMemPmaAvailBytes->pMemDesc) == ADDR_SYSMEM), + NV_ERR_NOT_SUPPORTED); + NV_ASSERT_OR_RETURN((memdescGetAddressSpace(pMemPmaBuffer->pMemDesc) == ADDR_SYSMEM), + NV_ERR_NOT_SUPPORTED); + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + NVB0CC_CTRL_CMD_ALLOC_PMA_STREAM, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to allocate PMA stream. Error 0x%x\n", status); + return status; + } + + // Map user-sent MEM_BYTES_ADDR buffer in CPU VA for guest RM to access the available bytes + status = memdescCreateSubMem(&pTgtMemDescPmaAvailBytes, + pMemPmaAvailBytes->pMemDesc, NULL, + pParams->pmaBytesAvailableOffset, + NVB0CC_PMA_BYTES_AVAILABLE_SIZE); + if (status != NV_OK) + { + goto _profilerBaseCtrlCmdAllocPmaStreamVgpuGuest_fail; + } + + status = memdescMap(pTgtMemDescPmaAvailBytes, 0, pTgtMemDescPmaAvailBytes->Size, NV_TRUE, + NV_PROTECT_READ_WRITE, &pCpuAddr, &pPriv); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Mapping of MEM_BYTES_ADDR buffer into CPU VA failed: 0x%x\n", status); + goto _profilerBaseCtrlCmdAllocPmaStreamVgpuGuest_fail; + } + + if (pProfiler->pPmaStreamList) + { + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pNumBytesBufDesc = pTgtMemDescPmaAvailBytes; + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pNumBytesCpuAddr = pCpuAddr; + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pNumBytesCpuAddrPriv = pPriv; + } + else + { + status = NV_ERR_INVALID_STATE; + goto _profilerBaseCtrlCmdAllocPmaStreamVgpuGuest_fail; + } + + // In full SRIOV, buffer VAs will be generated on guest, but they can be bound to PMA engine + // on host only. Thus, generate VAs and HWPM IB and convey them to host. + if (IS_SRIOV_FULL_GUEST(pGpu)) + { + status = memdescCreateSubMem(&pTgtMemDescPmaBuffer, + pMemPmaBuffer->pMemDesc, NULL, + pParams->pmaBufferOffset, + pParams->pmaBufferSize); + if (status != NV_OK) + { + goto _profilerBaseCtrlCmdAllocPmaStreamVgpuGuest_fail; + } + + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pRecordBufDesc = pTgtMemDescPmaBuffer; + + status = khwpmStreamoutAllocPmaStream(pGpu, pKernelHwpm, pProfiler->profilerId, + pTgtMemDescPmaBuffer, + pTgtMemDescPmaAvailBytes, + pParams->pmaChannelIdx, + &pProfiler->pPmaStreamList[pParams->pmaChannelIdx]); + if (status != NV_OK) + { + goto _profilerBaseCtrlCmdAllocPmaStreamVgpuGuest_fail; + } + + promoteParams.pmaChannelIdx = pParams->pmaChannelIdx; + + status = pRmApi->Control(pRmApi, + hClient, + hObject, + NVB0CC_CTRL_CMD_INTERNAL_SRIOV_PROMOTE_PMA_STREAM, + &promoteParams, sizeof(promoteParams)); + if (status != NV_OK) + { + goto _profilerBaseCtrlCmdAllocPmaStreamVgpuGuest_fail; + } + + pParams->pmaBufferVA = pProfiler->pPmaStreamList[pParams->pmaChannelIdx].vaddrRecordBuf; + } + + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].bValid = NV_TRUE; + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].bMemBytesBufferAccessAllowed = NV_TRUE; + + return NV_OK; + +_profilerBaseCtrlCmdAllocPmaStreamVgpuGuest_fail: + if (pCpuAddr != NvP64_NULL) + { + memdescUnmap(pTgtMemDescPmaAvailBytes, NV_TRUE, osGetCurrentProcess(), pCpuAddr, pPriv); + if (pProfiler->pPmaStreamList) + { + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pNumBytesCpuAddr = NvP64_NULL; + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pNumBytesCpuAddrPriv = NvP64_NULL; + } + } + if (pTgtMemDescPmaAvailBytes != NULL) + { + memdescFree(pTgtMemDescPmaAvailBytes); + memdescDestroy(pTgtMemDescPmaAvailBytes); + if (pProfiler->pPmaStreamList) + { + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pNumBytesBufDesc = NULL; + } + } + if (pTgtMemDescPmaBuffer != NULL) + { + memdescFree(pTgtMemDescPmaBuffer); + memdescDestroy(pTgtMemDescPmaBuffer); + if (pProfiler->pPmaStreamList) + { + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pRecordBufDesc = NULL; + } + } + + return status; +} + +static NV_STATUS +_profilerBaseCtrlCmdFreePmaStreamVgpuGuest +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + KernelHwpm *pKernelHwpm = GPU_GET_KERNEL_HWPM(pGpu); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + + // Handle quiesce streamout on guest, then issue RPC to host, which will handle + // freeing of PMA stream. + status = profilerBaseQuiesceStreamout(pProfiler, pGpu, pKernelHwpm, pParams->pmaChannelIdx); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to quiesce HWPM streamout. Error 0x%x\n", status); + return status; + } + + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + NVB0CC_CTRL_CMD_FREE_PMA_STREAM, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to free PMA stream. Error 0x%x\n", status); + return status; + } + + if (IS_SRIOV_FULL_GUEST(pGpu)) + { + khwpmStreamoutFreePmaStream(pGpu, pKernelHwpm, pProfiler->profilerId, + &pProfiler->pPmaStreamList[pParams->pmaChannelIdx], pParams->pmaChannelIdx); + } + + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].bValid = NV_FALSE; + pProfiler->pPmaStreamList[pParams->pmaChannelIdx].bMemBytesBufferAccessAllowed = NV_FALSE; + + return status; +} + +/* + * To be called on vGPU guest only. + * Will issue RPC to vGPU host and optionally, wait in guest to get updated available membytes + */ +static NV_STATUS +_profilerBaseCtrlCmdPmaStreamUpdateGetPutVgpuGuest +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + volatile NvU32 *pMemBytesAddr = NvP64_VALUE(pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pNumBytesCpuAddr); + + if (pParams->bUpdateAvailableBytes) + { + *pMemBytesAddr = NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE; + } + + status = _issueRpcToHost(pGpu); + if (status != NV_OK) + { + return status; + } + + // Wait on guest for PMA unit to streamout updated available membytes + if (pProfiler->pPmaStreamList[pParams->pmaChannelIdx].bMemBytesBufferAccessAllowed && + pParams->bUpdateAvailableBytes && pParams->bWait) + { + RMTIMEOUT timeout = {0}; + threadStateResetTimeout(pGpu); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + while (*pMemBytesAddr == NVB0CC_AVAILABLE_BYTES_DEFAULT_VALUE) + { + if (status == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "timeout occurred while waiting for PM streamout to idle.\n"); + break; + } + osSpinLoop(); + status = gpuCheckTimeout(pGpu, &timeout); + } + + pParams->bytesAvailable = *pMemBytesAddr; + + NV_PRINTF(LEVEL_INFO, "status=0x%08x, *MEM_BYTES_ADDR=0x%08x.\n", status, *pMemBytesAddr); + } + + return status; +} + +NV_STATUS +profilerBaseCtrlCmdInternalAllocPmaStream_VF +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS *pParams +) +{ + RsResourceRef *pMemoryPmaBufferRef = NULL; + RsResourceRef *pMemoryPmaAvailBytesRef = NULL; + Memory *pMemPmaBuffer = NULL; + Memory *pMemPmaAvailBytes = NULL; + NV_STATUS status = NV_OK; + NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler); + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + + if (IS_SILICON(pGpu)) + { + // bInputPmaChIdx is only allowed to set on emulation/simulation. + NV_CHECK_OR_RETURN(LEVEL_ERROR, pParams->bInputPmaChIdx == NV_FALSE, NV_ERR_INVALID_ARGUMENT); + } + + status = serverutilGetResourceRef(hClient, pParams->hMemPmaBuffer, &pMemoryPmaBufferRef); + if (status != NV_OK) + { + return status; + } + + pMemPmaBuffer = dynamicCast(pMemoryPmaBufferRef->pResource, Memory); + if (pMemPmaBuffer == NULL) + { + return NV_ERR_INVALID_OBJECT; + } + + status = serverutilGetResourceRef(hClient, pParams->hMemPmaBytesAvailable, + &pMemoryPmaAvailBytesRef); + if (status != NV_OK) + { + return status; + } + + pMemPmaAvailBytes = dynamicCast(pMemoryPmaAvailBytesRef->pResource, Memory); + if (pMemPmaAvailBytes == NULL) + { + return NV_ERR_INVALID_OBJECT; + } + + if ((pParams->pmaBufferSize > NVB0CC_PMA_BUFFER_SIZE_MAX) || + (pMemPmaBuffer->pMemDesc == NULL) || + (pMemPmaBuffer->pMemDesc->Size < (pParams->pmaBufferSize + pParams->pmaBufferOffset))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if ((pMemPmaAvailBytes->pMemDesc == NULL) || + (pMemPmaAvailBytes->pMemDesc->Size < (pParams->pmaBytesAvailableOffset + NVB0CC_PMA_BYTES_AVAILABLE_SIZE))) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Client must pass a RO buffer handle for available bytes buffer + if (!RMCFG_FEATURE_MODS_FEATURES && + !FLD_TEST_DRF(OS32, _ATTR2, _PROTECTION_USER, _READ_ONLY, pMemPmaAvailBytes->Attr2)) + { + NV_PRINTF(LEVEL_ERROR, + "failed: Memory 0x%x provided is not read only (Attr2: 0x%08x).\n", + pParams->hMemPmaBytesAvailable, pMemPmaAvailBytes->Attr2); + return NV_ERR_INVALID_ARGUMENT; + } + + return _profilerBaseCtrlCmdAllocPmaStreamVgpuGuest(pProfiler, pParams, pMemPmaAvailBytes, pMemPmaBuffer); +} + +NV_STATUS +profilerBaseCtrlCmdPmaStreamUpdateGetPut_VF +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + KernelHwpm *pKernelHwpm = GPU_GET_KERNEL_HWPM(pGpu); + + if (pParams->pmaChannelIdx > (pKernelHwpm->maxPmaChannels - 1)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return _profilerBaseCtrlCmdPmaStreamUpdateGetPutVgpuGuest(pProfiler, pParams); +} + +NV_STATUS +profilerBaseCtrlCmdInternalFreePmaStream_VF +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS *pNewParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + KernelHwpm *pKernelHwpm = GPU_GET_KERNEL_HWPM(pGpu); + NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS extParams, *pParams = &extParams; + + portMemSet(pParams, 0, sizeof(NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS)); + extParams.pmaChannelIdx = pNewParams->pmaChannelIdx; + + if (pParams->pmaChannelIdx > (pKernelHwpm->maxPmaChannels - 1)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return _profilerBaseCtrlCmdFreePmaStreamVgpuGuest(pProfiler, pParams); +} + +/* + * To be used on full SRIOV only. + * Promotes the PMA buffers and HWPM IB allocated on VF to PF context + */ +NV_STATUS +profilerBaseCtrlCmdInternalSriovPromotePmaStream_VF +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pProfiler); + KernelHwpm *pKernelHwpm = GPU_GET_KERNEL_HWPM(pGpu); + NvU32 vPmaChIdx = pParams->pmaChannelIdx; + NvU32 vBpcIdx = vPmaChIdx / pKernelHwpm->maxChannelPerCblock; + MEMORY_DESCRIPTOR *pInstBlkMemDesc = NULL; + + if (!IS_SRIOV_FULL_GUEST(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + pParams->pmaBufferVA = pProfiler->pPmaStreamList[vPmaChIdx].vaddrRecordBuf; + pParams->membytesVA = pProfiler->pPmaStreamList[vPmaChIdx].vaddrNumBytesBuf; + pParams->pmaBufferSize = pProfiler->pPmaStreamList[pParams->pmaChannelIdx].pRecordBufDesc->Size; + + pInstBlkMemDesc = pKernelHwpm->streamoutState[vBpcIdx].pInstBlkMemDesc; + + pParams->hwpmIBPA = memdescGetPhysAddr(pInstBlkMemDesc, AT_GPU, 0); + pParams->hwpmIBAperture = memdescGetAddressSpace(pInstBlkMemDesc); + + // vGPU only supports IBs allocation in FB memory + NV_ASSERT_OR_RETURN((pParams->hwpmIBAperture == ADDR_FBMEM), + NV_ERR_NOT_SUPPORTED); + + return _issueRpcToHost(pGpu); +} + +NV_STATUS +profilerBaseCtrlCmdInternalGetMaxPmas_IMPL +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS *pParams +) +{ + POBJGPU pGpu = GPU_RES_GET_GPU(pProfiler); + KernelHwpm *pKernelHwpm = GPU_GET_KERNEL_HWPM(pGpu); + + pParams->maxPmaChannels = pKernelHwpm->maxPmaChannels; + return NV_OK; +} + +/*! + * @brief Request a set of clock-gating controls on behalf of the calling + * profiler object. + * + * @param[in] pProfiler + * @param[in,out] pParams + */ +NV_STATUS +profilerBaseCtrlCmdRequestCgControls_VF +( + ProfilerBase *pProfiler, + NVB0CC_CTRL_POWER_REQUEST_FEATURES_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + HWPM_POWER_REQUEST_FEATURES_PARAMS requestParams; + + portMemSet(&requestParams, 0, sizeof(HWPM_POWER_REQUEST_FEATURES_PARAMS)); + + // Status for all power features will be set to 0 in statusMask only if + // HWPM_POWER_FEATURE_REQUEST_FULFILLED = 0. + ct_assert(HWPM_POWER_FEATURE_REQUEST_FULFILLED == 0); + requestParams.statusMask = HWPM_POWER_FEATURE_REQUEST_FULFILLED; + requestParams.globalStatus = NV_OK; + + // Copy output status. + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, khwpmGetRequestCgStatusMask(&pParams->statusMask, &requestParams)); + pParams->globalStatus = requestParams.globalStatus; + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c index dc5111da66..e60197f71a 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_cpu_ga102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -34,7 +34,7 @@ // NvU32 -intrReadRegTopEnSet_GA102 +intrReadRegTopEnSet_CPU_GA102 ( OBJGPU *pGpu, Intr *pIntr, @@ -54,7 +54,7 @@ intrReadRegTopEnSet_GA102 } void -intrWriteRegTopEnSet_GA102 +intrWriteRegTopEnSet_CPU_GA102 ( OBJGPU *pGpu, Intr *pIntr, @@ -76,7 +76,7 @@ intrWriteRegTopEnSet_GA102 } void -intrWriteRegTopEnClear_GA102 +intrWriteRegTopEnClear_CPU_GA102 ( OBJGPU *pGpu, Intr *pIntr, diff --git a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c index af187a198e..5c71db686c 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -57,7 +57,7 @@ intrGetUvmSharedLeafEnDisableMask_GA100 ) { NvU32 intrVectorNonReplayableFault; - NvU32 intrVectorTimerSwrl = NV_INTR_VECTOR_INVALID; + NvU32 intrVectorTimerSwrl; NvU64 mask = 0; NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; @@ -69,13 +69,9 @@ intrGetUvmSharedLeafEnDisableMask_GA100 } intrVectorNonReplayableFault = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_NON_REPLAYABLE_FAULT, NV_FALSE); + intrVectorTimerSwrl = NV_INTR_VECTOR_INVALID; - if (!IS_VIRTUAL(pGpu)) - { - intrVectorTimerSwrl = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_TMR_SWRL, NV_FALSE); - } - - if (intrVectorNonReplayableFault != NV_INTR_VECTOR_INVALID && intrVectorTimerSwrl != NV_INTR_VECTOR_INVALID) + if ((intrVectorNonReplayableFault != NV_INTR_VECTOR_INVALID) && (intrVectorTimerSwrl != NV_INTR_VECTOR_INVALID)) { // Ascertain that they're in the same subtree and same leaf NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(intrVectorNonReplayableFault) == diff --git a/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c b/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c index 9267b9c550..c2d266c59c 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/hopper/intr_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -57,6 +57,14 @@ intrInitSubtreeMap_GH100 pCategoryRunlistLocked->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; pCategoryRunlistLocked->subtreeEnd = NV_CPU_INTR_STALL_SUBTREE_LAST_SWRL; + // + // Don't reprogram NV_RUNLIST_INTR_TREE_LOCKLESS (runlist notification) + // vectors to a different subtree than their init values in Hopper unlike + // Ampere. INTR_TOP is covered with a "nonstall" mask corresponding to these + // leaf ranges. + // It is okay to reprogram the vectors for individual runlists within the + // same subtree. + // NV2080_INTR_CATEGORY_SUBTREE_MAP *pCategoryRunlistNotification = &pIntr->subtreeMap[NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION]; pCategoryRunlistNotification->subtreeStart = NV_CPU_INTR_STALL_SUBTREE_LAST; diff --git a/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c b/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c index 8dcab2ddfe..34d327125b 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/maxwell/intr_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -46,7 +46,8 @@ intrGetPendingStall_GM107 THREAD_STATE_NODE *pThreadState ) { - KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); NvU8 i; NV_ASSERT_OR_RETURN(pEngines != NULL, NV_ERR_INVALID_ARGUMENT); @@ -84,7 +85,7 @@ intrGetPendingStall_GM107 bitVectorSet(pEngines, MC_ENGINE_IDX_DISP); } - if (pGpu->fecsCtxswLogConsumerCount > 0) + if ((pKernelGraphicsManager != NULL) && (fecsGetCtxswLogConsumerCount(pGpu, pKernelGraphicsManager) > 0)) { // // WARNING: This loop must not call any GR HALs or diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c index ab0cb2ee36..c438776d4d 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_cpu_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -34,7 +34,7 @@ // NvU32 -intrReadRegLeafEnSet_TU102 +intrReadRegLeafEnSet_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, @@ -48,7 +48,7 @@ intrReadRegLeafEnSet_TU102 } NvU32 -intrReadRegLeaf_TU102 +intrReadRegLeaf_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, @@ -62,7 +62,7 @@ intrReadRegLeaf_TU102 } NvU32 -intrReadRegTopEnSet_TU102 +intrReadRegTopEnSet_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, @@ -82,7 +82,7 @@ intrReadRegTopEnSet_TU102 } NvU32 -intrReadRegTop_TU102 +intrReadRegTop_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, @@ -102,7 +102,7 @@ intrReadRegTop_TU102 } void -intrWriteRegLeafEnSet_TU102 +intrWriteRegLeafEnSet_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, @@ -118,7 +118,7 @@ intrWriteRegLeafEnSet_TU102 } void -intrWriteRegLeafEnClear_TU102 +intrWriteRegLeafEnClear_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, @@ -134,7 +134,7 @@ intrWriteRegLeafEnClear_TU102 } void -intrWriteRegLeaf_TU102 +intrWriteRegLeaf_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, @@ -150,7 +150,7 @@ intrWriteRegLeaf_TU102 } void -intrWriteRegTopEnSet_TU102 +intrWriteRegTopEnSet_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, @@ -172,7 +172,7 @@ intrWriteRegTopEnSet_TU102 } void -intrWriteRegTopEnClear_TU102 +intrWriteRegTopEnClear_CPU_TU102 ( OBJGPU *pGpu, Intr *pIntr, diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c index 5293f7fb71..42f1a6765a 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_nonstall_tu102.c @@ -48,15 +48,9 @@ intrGetNonStallEnable_TU102 NvU64 nonStallMask; NvU32 maskLo; NvU32 maskHi; - NvU32 isNonStallEnabled = 0; if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) { - if (vgpuShmIsNonStallEnabled(pGpu, &isNonStallEnabled) == NV_OK) - { - if (isNonStallEnabled) - return INTERRUPT_TYPE_MULTI; - } return INTERRUPT_TYPE_DISABLED; } @@ -104,6 +98,11 @@ intrEnableTopNonstall_TU102 { NvU64 nonStallMask; + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) + { + return; + } + nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); if (NvU64_LO32(nonStallMask) != 0) @@ -133,6 +132,11 @@ intrDisableTopNonstall_TU102 { NvU64 nonStallMask; + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) + { + return; + } + nonStallMask = intrGetIntrTopNonStallMask_HAL(pGpu, pIntr); if (NvU64_LO32(nonStallMask) != 0) @@ -165,6 +169,11 @@ intrRestoreNonStall_TU102 return; } + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) + { + return; + } + // // We only support enabling all non-stall interrupts or disabling all // non-stall interrupts in one go. We don't have a usecase to enable/disable @@ -223,7 +232,7 @@ intrGetPendingNonStall_TU102 if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) { - return vgpuIsNonStallPending(pGpu, pEngines); + return NV_ERR_NOT_SUPPORTED; } NV_ASSERT_OK_OR_RETURN(intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable)); @@ -269,6 +278,14 @@ intrGetPendingNonStall_TU102 if (intr & NVBIT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVector))) { bitVectorSet(pEngines, pEntry->mcEngine); + // + // Don't break here. We can have multiple non stall + // interrupts on the same vector in case of MIG + // partitioning. + // + // Although most of them will be GFID filtered to VFs, the + // PF also uses engines assigned to a partition. + // } } } @@ -420,9 +437,8 @@ intrServiceNonStall_TU102 if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) { - return vgpuServiceNonStall(pGpu, pEngines); + return NV_ERR_NOT_SUPPORTED; } - FOR_EACH_INDEX_IN_MASK(64, i, intrGetIntrTopNonStallMask_HAL(pGpu, pIntr)) { NvU32 j = NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(i); diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_swintr_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_swintr_tu102.c index 657accbb53..b3453e57b3 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_swintr_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_swintr_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,12 +59,9 @@ intrClearStallSWIntr_TU102 Intr *pIntr ) { - NvU32 leafReg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); - NvU32 leafBit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); - NvU32 clearSwIntr = NVBIT(leafBit); - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(leafReg), - clearSwIntr); + intrClearLeafVector_HAL(pGpu, pIntr, NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT, NULL); + return NV_OK; } @@ -78,13 +75,11 @@ intrEnableStallSWIntr_TU102 Intr *pIntr ) { - NvU32 leafReg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); - NvU32 leafBit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); NvU32 subtree = NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); NvU32 topIdx = NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(subtree); NvU32 topBit = NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(subtree); - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(leafReg), NVBIT(leafBit)); + intrEnableLeaf_HAL(pGpu, pIntr, NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(topIdx), NVBIT(topBit)); } @@ -101,13 +96,11 @@ intrDisableStallSWIntr_TU102 Intr *pIntr ) { - NvU32 leafReg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); - NvU32 leafBit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); NvU32 subtree = NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); NvU32 topIdx = NV_CTRL_INTR_SUBTREE_TO_TOP_IDX(subtree); NvU32 topBit = NV_CTRL_INTR_SUBTREE_TO_TOP_BIT(subtree); - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(leafReg), NVBIT(leafBit)); + intrDisableLeaf_HAL(pGpu, pIntr, NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(topIdx), NVBIT(topBit)); } @@ -131,20 +124,13 @@ intrGetStallInterruptMode_TU102 NvBool *pPending ) { - NvU32 reg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); - NvU32 bit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT); - NvU32 swPending = 0; - *pIntrmode = INTERRUPT_TYPE_SOFTWARE; // value put in to match with legacy + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu)) { - if (vgpuShmIsSwPending(pGpu, &swPending) == NV_OK) - *pPending = swPending; - else *pPending = NV_FALSE; return; } - swPending = intrReadRegLeaf_HAL(pGpu, pIntr, reg, NULL); - *pPending = (swPending & NVBIT(bit)) ? NV_TRUE : NV_FALSE; + *pPending = intrIsVectorPending_HAL(pGpu, pIntr, NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT, NULL); } diff --git a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c index e359edb5f2..ee04f8b43f 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/turing/intr_tu102.c @@ -38,35 +38,6 @@ #include "published/turing/tu102/dev_ctrl.h" #include "published/turing/tu102/dev_vm.h" #include "published/turing/tu102/dev_vm_addendum.h" -/*! - * @brief Get the base interrupt vector to use when indexing engine nonstall - * interrupts - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntr Intr pointer - * - * @returns the base interrupt vector for engine nonstall interrupts - */ -NvU32 -intrGetNonStallBaseVector_TU102 -( - OBJGPU *pGpu, - Intr *pIntr -) -{ - NvU32 base = 0; - - if (!IS_VIRTUAL(pGpu)) - { - base = GPU_REG_RD32(pGpu, NV_CTRL_LEGACY_ENGINE_NONSTALL_INTR_BASE_VECTORID); - } - else - { - NV_STATUS status = NV_OK; - NV_RM_RPC_VGPU_PF_REG_READ32(pGpu, NV_CTRL_LEGACY_ENGINE_NONSTALL_INTR_BASE_VECTORID, &base, status); - } - return base; -} // // Static interface functions @@ -208,32 +179,6 @@ intrCacheIntrFields_TU102 { NV_STATUS status = NV_OK; - { - NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; - NV_ASSERT_OK_OR_RETURN( - intrGetSubtreeRange(pIntr, - NV2080_INTR_CATEGORY_UVM_SHARED, - &uvmShared)); - // - // Assert to make sure we have only one client shared subtree. - // The below code assumes that. - // - NV_ASSERT_OR_RETURN(uvmShared.subtreeStart == uvmShared.subtreeEnd, - NV_ERR_INVALID_STATE); - - // Now cache the leaf enable mask for the subtree shared with the client - NvU32 leafEnHi = intrReadRegLeafEnSet_HAL(pGpu, pIntr, - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart), - NULL); - NvU32 leafEnLo = intrReadRegLeafEnSet_HAL(pGpu, pIntr, - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(uvmShared.subtreeStart), - NULL); - - pIntr->uvmSharedCpuLeafEn = ((NvU64)(leafEnHi) << 32) | leafEnLo; - pIntr->uvmSharedCpuLeafEnDisableMask = - intrGetUvmSharedLeafEnDisableMask_HAL(pGpu, pIntr); - } - // // Cache the CPU_INTR_TOP_EN mask to clear when disabling stall // interrupts (other interrupts are either not disabled or disabled @@ -244,7 +189,8 @@ intrCacheIntrFields_TU102 OBJDISP *pDisp = GPU_GET_DISP(pGpu); // Cache client owned, shared interrupt, and display vectors for ease of use later - pIntr->accessCntrIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_ACCESS_CNTR, NV_FALSE); + pIntr->accessCntrIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_ACCESS_CNTR, NV_FALSE); + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) { pIntr->replayableFaultIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT, NV_FALSE); @@ -253,9 +199,10 @@ intrCacheIntrFields_TU102 { pIntr->replayableFaultIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_REPLAYABLE_FAULT_CPU, NV_FALSE); } + if (pDisp != NULL) { - pIntr->displayIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_DISP, NV_FALSE); + pIntr->displayIntrVector = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_DISP, NV_FALSE); } else { @@ -306,6 +253,32 @@ intrCacheIntrFields_TU102 } } + { + NV2080_INTR_CATEGORY_SUBTREE_MAP uvmShared; + NV_ASSERT_OK_OR_RETURN( + intrGetSubtreeRange(pIntr, + NV2080_INTR_CATEGORY_UVM_SHARED, + &uvmShared)); + // + // Assert to make sure we have only one client shared subtree. + // The below code assumes that. + // + NV_ASSERT_OR_RETURN(uvmShared.subtreeStart == uvmShared.subtreeEnd, + NV_ERR_INVALID_STATE); + + // Now cache the leaf enable mask for the subtree shared with the client + NvU32 leafEnHi = intrReadRegLeafEnSet_HAL(pGpu, pIntr, + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(uvmShared.subtreeStart), + NULL); + NvU32 leafEnLo = intrReadRegLeafEnSet_HAL(pGpu, pIntr, + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(uvmShared.subtreeStart), + NULL); + + pIntr->uvmSharedCpuLeafEn = ((NvU64)(leafEnHi) << 32) | leafEnLo; + pIntr->uvmSharedCpuLeafEnDisableMask = + intrGetUvmSharedLeafEnDisableMask_HAL(pGpu, pIntr); + } + exit: return status; @@ -961,6 +934,35 @@ intrCheckAndServiceNonReplayableFault_TU102 ) { NV_STATUS status = NV_OK; + MC_ENGINE_BITVECTOR intrPending; + + intrGetPendingStall_HAL(pGpu, pIntr, &intrPending, pThreadState); + + if (bitVectorTest(&intrPending, MC_ENGINE_IDX_NON_REPLAYABLE_FAULT)) + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + // + // This interrupt was already cleared in the top half and "serviced" in + // the top half since copy from HW fault buffer always happens in the + // top half. This servicing is merely copying from the SW fault buffer, + // so doesn't need interrupt clearing. Also, we will only copy from the + // SW fault buffer if the fatalFaultIntrPending cache tells us that + // there is something to copy. Else, we'll just return early and rely + // on another interrupt to fire that will eventually update this state. + // In the top half, we will unconditionally write GET back, which will + // force HW to send us a new pulse as long as GET != PUT and we'd be + // eventually guaranteed to copy something into the SW fault buffer. + // + if (portAtomicCompareAndSwapS32(kgmmuGetFatalFaultIntrPendingState(pKernelGmmu, GPU_GFID_PF), 0, 1)) + { + status = kgmmuServiceNonReplayableFault_HAL(pGpu, pKernelGmmu); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("Failed to service MMU non-replayable fault", status); + } + } + } return status; } @@ -1297,7 +1299,7 @@ intrGetIntrTopNonStallMask_TU102 Intr *pIntr ) { - // TODO Bug 3823562 Remove these asserts + // TODO Bug 3823562 Remove these asserts // Compile-time assert against the highest set bit that will be returned #define NV_CPU_INTR_NOSTALL_SUBTREE_HIGHEST NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(0) diff --git a/src/nvidia/src/kernel/gpu/intr/intr.c b/src/nvidia/src/kernel/gpu/intr/intr.c index b158d96156..2f778a0f01 100644 --- a/src/nvidia/src/kernel/gpu/intr/intr.c +++ b/src/nvidia/src/kernel/gpu/intr/intr.c @@ -31,6 +31,7 @@ #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/intr/engine_idx.h" #include "kernel/gpu/intr/intr_service.h" +#include "kernel/gpu/gsp/gsp_trace_rats_macro.h" #include "gpu/mmu/kern_gmmu.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "os/os.h" @@ -38,6 +39,7 @@ #include "vgpu/rpc.h" #include "virtualization/hypervisor/hypervisor.h" #include "gpu/gsp/kernel_gsp.h" +#include "platform/sli/sli.h" #include "nv_ref.h" #include "nvRmReg.h" @@ -166,6 +168,16 @@ subdeviceCtrlCmdMcServiceInterrupts_IMPL RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; NV_STATUS status = NV_OK; + // + // Force kernel-RM to service interrupts from GSP-RM. This will allow + // kernel-RM to write notifiers and send an ack back to GSP. + // GSP waits for this ack before clearing fast path POSSIBLE_ERR interrupt. + // + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_FASTPATH_SEQ_ENABLED)) + { + intrServiceStallSingle_HAL(pGpu, pIntr, MC_ENGINE_IDX_GSP, NV_TRUE); + } + NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); if (status != NV_OK) @@ -524,23 +536,14 @@ intrServiceStallListDevice_IMPL SLI_LOOP_END; } -/*! - * @brief Get the interrupt vector for the given engine - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pIntr Intr pointer - * @param[in] mcEngineId Engine id (i.e. one of MC_ENGINE_IDX_* defines) - * @param[in] bNonStall NV_TRUE if non-stall, else NV_FALSE - * - * @returns the nonstall interrupt vector for that engine - */ -NvU32 -intrGetVectorFromEngineId_IMPL + +INTR_TABLE_ENTRY * +intrGetInterruptTableEntryFromEngineId_IMPL ( - OBJGPU *pGpu, - Intr *pIntr, - NvU16 mcEngineId, - NvBool bNonStall + OBJGPU *pGpu, + Intr *pIntr, + NvU16 mcEngineId, + NvBool bNonStall ) { InterruptTable *pIntrTable; @@ -551,7 +554,7 @@ intrGetVectorFromEngineId_IMPL if (status != NV_OK) { NV_ASSERT_OK_FAILED("Failed to get interrupt table", status); - return NV_INTR_VECTOR_INVALID; + return NULL; } for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) @@ -559,15 +562,46 @@ intrGetVectorFromEngineId_IMPL INTR_TABLE_ENTRY *pEntry = iter.pValue; if (pEntry->mcEngine == mcEngineId) { - return bNonStall ? pEntry->intrVectorNonStall : pEntry->intrVector; + return pEntry; } } - NV_PRINTF(LEVEL_ERROR, "Could not find the specified engine Id %u\n", mcEngineId); + NV_PRINTF(LEVEL_ERROR, + "Could not find the specified engine Id %u\n", + mcEngineId); DBG_BREAKPOINT(); - return NV_INTR_VECTOR_INVALID; + return NULL; } +/*! + * @brief Get the interrupt vector for the given engine + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pIntr Intr pointer + * @param[in] mcEngineId Engine id (i.e. one of MC_ENGINE_IDX_* defines) + * @param[in] bNonStall NV_TRUE if non-stall, else NV_FALSE + * + * @returns the nonstall interrupt vector for that engine + */ +NvU32 +intrGetVectorFromEngineId_IMPL +( + OBJGPU *pGpu, + Intr *pIntr, + NvU16 mcEngineId, + NvBool bNonStall +) +{ + INTR_TABLE_ENTRY *pEntry = intrGetInterruptTableEntryFromEngineId(pGpu, + pIntr, + mcEngineId, + bNonStall); + + NV_ASSERT_OR_RETURN(pEntry != NULL, NV_INTR_VECTOR_INVALID); + return bNonStall ? pEntry->intrVectorNonStall : pEntry->intrVector; +} + + /*! * @brief Convert a general MC_ENGINE_BITVECTOR to its corresponding hardware * interrupt mask in PMC. @@ -721,11 +755,15 @@ intrConstructEngine_IMPL pIntr->dpcQueue.pRear = NULL; pIntr->bDpcStarted = NV_FALSE; - if (!RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (!RMCFG_FEATURE_PLATFORM_WINDOWS) { pIntr->setProperty(pIntr, PDB_PROP_INTR_DISABLE_PER_INTR_DPC_QUEUEING, NV_TRUE); } + NV_ASSERT_OK_OR_RETURN(vectInit(&pIntr->intrTable, + portMemAllocatorGetGlobalNonPaged(), + 0 /* capacity */)); + return NV_OK; } @@ -746,6 +784,8 @@ intrDestruct_IMPL portMemFree(pNode); } + vectDestroy(&pIntr->intrTable); + } @@ -813,7 +853,7 @@ intrStateInitLocked_IMPL if (pIntr->getProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING)) { intrGetIntrMask_HAL(pGpu, pIntr, &pIntr->intrMask.engMaskOrig, NULL /* threadstate */); - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_WINDOWS) { MC_ENGINE_BITVECTOR engines; @@ -911,7 +951,7 @@ _intrInitRegistryOverrides } pIntr->setProperty(pIntr, PDB_PROP_INTR_USE_INTR_MASK_FOR_LOCKING, NV_FALSE); - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || hypervisorIsVgxHyper()) + if (RMCFG_FEATURE_PLATFORM_WINDOWS || hypervisorIsVgxHyper()) { // Enable IntrMask Locking by default if supported if (pIntr->getProperty(pIntr, PDB_PROP_INTR_MASK_SUPPORTED) && @@ -976,7 +1016,12 @@ intrInitInterruptTable_KERNEL NvU32 i; NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS *pParams; - NV_ASSERT_OR_RETURN(vectIsEmpty(&pIntr->intrTable), NV_ERR_INVALID_STATE); + // + // Unconditionally clear it. For _KERNEL, this function can be called to + // re-fetch the KernelRM interrupt table every time PhysicalRM updates it + // like after MIG partition configuration changes. + // + vectClear(&pIntr->intrTable); pParams = portMemAllocNonPaged(sizeof(*pParams)); NV_ASSERT_TRUE_OR_GOTO(status, pParams != NULL, NV_ERR_NO_MEMORY, exit); @@ -996,10 +1041,8 @@ intrInitInterruptTable_KERNEL exit); NV_ASSERT_OK_OR_GOTO(status, - vectInit(&pIntr->intrTable, - portMemAllocatorGetGlobalNonPaged(), - pParams->tableLen), - exit); + vectReserve(&pIntr->intrTable, pParams->tableLen), + exit); for (i = 0; i < pParams->tableLen; ++i) { INTR_TABLE_ENTRY entry = {0}; @@ -1049,7 +1092,7 @@ _intrInitServiceTable NvU32 intrServiceInterruptRecords_IMPL ( OBJGPU *pGpu, - Intr *pIntr, + Intr *pIntr, NvU16 engineIdx, NvBool *pServiced ) @@ -1078,7 +1121,10 @@ NvU32 intrServiceInterruptRecords_IMPL if (bShouldService) { + GSP_TRACE_RATS_ADD_RECORD(NV_RATS_GSP_TRACE_TYPE_INTR_INFO, pGpu, (NvU32) engineIdx); + GSP_TRACE_RATS_ADD_RECORD(NV_RATS_GSP_TRACE_TYPE_INTR_START, pGpu, 0); ret = intrservServiceInterrupt(pGpu, pIntrService, &serviceParams); + GSP_TRACE_RATS_ADD_RECORD(NV_RATS_GSP_TRACE_TYPE_INTR_END, pGpu, 0); } return ret; } @@ -1140,14 +1186,16 @@ NV_STATUS intrCheckFecsEventbufferPending_IMPL ) { NvU8 i; + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + NvS16 fecsCtxswLogConsumerCount= fecsGetCtxswLogConsumerCount(pGpu, pKernelGraphicsManager); NV_ASSERT_OR_RETURN(pbCtxswLog != NULL, NV_ERR_INVALID_ARGUMENT); *pbCtxswLog = NV_FALSE; - if (pGpu->fecsCtxswLogConsumerCount <= 0) + if (fecsCtxswLogConsumerCount <= 0) { - NV_ASSERT(pGpu->fecsCtxswLogConsumerCount == 0); + NV_ASSERT(fecsCtxswLogConsumerCount == 0); return NV_OK; } @@ -1180,14 +1228,16 @@ intrCheckAndServiceFecsEventbuffer_IMPL THREAD_STATE_NODE *pThreadState ) { + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + NvS16 fecsCtxswLogConsumerCount= fecsGetCtxswLogConsumerCount(pGpu, pKernelGraphicsManager); NvU8 i; if (bitVectorTestAllCleared(pIntrPending)) return NV_OK; - if (pGpu->fecsCtxswLogConsumerCount <= 0) + if (fecsCtxswLogConsumerCount <= 0) { - NV_ASSERT(pGpu->fecsCtxswLogConsumerCount == 0); + NV_ASSERT(fecsCtxswLogConsumerCount == 0); return NV_OK; } @@ -1235,7 +1285,8 @@ intrDestroyInterruptTable_IMPL pIntr->vectorToMcIdx[tree] = NULL; pIntr->vectorToMcIdxCounts[tree] = 0; } - vectDestroy(&pIntr->intrTable); + + vectClear(&pIntr->intrTable); return NV_OK; } @@ -1407,14 +1458,11 @@ _intrServiceStallExactList ) { NV_STATUS status; - NvU32 engineIdx; NvU32 intr; NvBool bHandled; NvBool bIntrStuck = NV_FALSE; NvBool bPending = NV_FALSE; - NvBool bRequiresPossibleErrorNotifier; - InterruptTable *pIntrTable; InterruptTableIter iter; @@ -1427,20 +1475,6 @@ _intrServiceStallExactList intrGetInterruptTable_HAL(pGpu, pIntr, &pIntrTable), return NV_FALSE); - bRequiresPossibleErrorNotifier = intrRequiresPossibleErrorNotifier_HAL(pGpu, pIntr, pEngines); - - if (bRequiresPossibleErrorNotifier) - { - // - // Notify CUDA there may be an error in ERR_CONT that they may miss because we're - // about to clear it out of the NV_CTRL tree backing ERR_CONT before the interrupt - // is serviced. - // - // info32 contains shadowed value of ERR_CONT - // - gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); - } - for (iter = vectIterAll(pIntrTable); vectIterNext(&iter);) { INTR_TABLE_ENTRY *pEntry = iter.pValue; @@ -1491,18 +1525,6 @@ _intrServiceStallExactList vgpuService(pGpu); } - if (bRequiresPossibleErrorNotifier) - { - // - // Notify CUDA there may be an error in ERR_CONT that they may miss because we're - // about to clear it out of the NV_CTRL tree backing ERR_CONT before the interrupt - // is serviced. - // - // info32 contains shadowed value of ERR_CONT - // - gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_POSSIBLE_ERROR, NULL, 0, intrReadErrCont_HAL(pGpu, pIntr), 0); - } - if (bIntrStuck) { NV_PRINTF(LEVEL_ERROR, @@ -1580,7 +1602,7 @@ intrServiceStallList_IMPL } } - resservSwapTlsCallContext(&pOldContext, NULL); + NV_ASSERT_OK_OR_ELSE(status, resservSwapTlsCallContext(&pOldContext, NULL), return); // prevent the isr from coming in _intrEnterCriticalSection(pGpu, pIntr, &intrMaskCtx); @@ -1609,7 +1631,7 @@ intrServiceStallList_IMPL // allow the isr to come in. _intrExitCriticalSection(pGpu, pIntr, &intrMaskCtx); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); } diff --git a/src/nvidia/src/kernel/gpu/intr/intr_vgpu.c b/src/nvidia/src/kernel/gpu/intr/intr_vgpu.c new file mode 100644 index 0000000000..5d6353e4ab --- /dev/null +++ b/src/nvidia/src/kernel/gpu/intr/intr_vgpu.c @@ -0,0 +1,276 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/fifo/kernel_fifo.h" +#include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" +#include "vgpu/rpc.h" + +/** + * @brief Gets the static interrupt table for a VF via RPC + * + * @param pGpu + * @param pIntr + * @param pTable The interrupt table to fill in + * @param pParams + */ +static NV_STATUS +_intrCopyVfStaticInterruptTable +( + OBJGPU *pGpu, + Intr *pIntr, + InterruptTable *pTable, + NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *pParams +) +{ + NvU32 i; + + // Fill in interrupt table with the matching NV2080 engine vectors + for (i = 0; i < pParams->numEntries; i++) + { + INTR_TABLE_ENTRY entry = {0}; + // + // Translate NV2080_INTR_TYPE back to local MC_ENGINE_IDX type + // for this driver version + // + switch (pParams->entries[i].nv2080IntrType) + { + case NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT: + entry.mcEngine = MC_ENGINE_IDX_NON_REPLAYABLE_FAULT; + break; + case NV2080_INTR_TYPE_NON_REPLAYABLE_FAULT_ERROR: + entry.mcEngine = MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR; + break; + case NV2080_INTR_TYPE_INFO_FAULT: + entry.mcEngine = MC_ENGINE_IDX_INFO_FAULT; + break; + case NV2080_INTR_TYPE_REPLAYABLE_FAULT: + entry.mcEngine = MC_ENGINE_IDX_REPLAYABLE_FAULT; + break; + case NV2080_INTR_TYPE_REPLAYABLE_FAULT_ERROR: + entry.mcEngine = MC_ENGINE_IDX_REPLAYABLE_FAULT_ERROR; + break; + case NV2080_INTR_TYPE_ACCESS_CNTR: + entry.mcEngine = MC_ENGINE_IDX_ACCESS_CNTR; + break; + case NV2080_INTR_TYPE_TMR: + entry.mcEngine = MC_ENGINE_IDX_TMR; + break; + case NV2080_INTR_TYPE_CPU_DOORBELL: + entry.mcEngine = MC_ENGINE_IDX_CPU_DOORBELL; + break; + case NV2080_INTR_TYPE_GR0_FECS_LOG: + entry.mcEngine = MC_ENGINE_IDX_GR0_FECS_LOG; + break; + case NV2080_INTR_TYPE_GR1_FECS_LOG: + entry.mcEngine = MC_ENGINE_IDX_GR1_FECS_LOG; + break; + case NV2080_INTR_TYPE_GR2_FECS_LOG: + entry.mcEngine = MC_ENGINE_IDX_GR2_FECS_LOG; + break; + case NV2080_INTR_TYPE_GR3_FECS_LOG: + entry.mcEngine = MC_ENGINE_IDX_GR3_FECS_LOG; + break; + case NV2080_INTR_TYPE_GR4_FECS_LOG: + entry.mcEngine = MC_ENGINE_IDX_GR4_FECS_LOG; + break; + case NV2080_INTR_TYPE_GR5_FECS_LOG: + entry.mcEngine = MC_ENGINE_IDX_GR5_FECS_LOG; + break; + case NV2080_INTR_TYPE_GR6_FECS_LOG: + entry.mcEngine = MC_ENGINE_IDX_GR6_FECS_LOG; + break; + case NV2080_INTR_TYPE_GR7_FECS_LOG: + entry.mcEngine = MC_ENGINE_IDX_GR7_FECS_LOG; + break; + default: + NV_PRINTF(LEVEL_ERROR, + "Unknown NV2080_INTR_TYPE 0x%x\n", + pParams->entries[i].nv2080IntrType); + NV_ASSERT_FAILED("Unknown NV2080_INTR_TYPE"); + return NV_ERR_INVALID_STATE; + } + + entry.pmcIntrMask = pParams->entries[i].pmcIntrMask; + entry.intrVector = pParams->entries[i].intrVectorStall; + entry.intrVectorNonStall = pParams->entries[i].intrVectorStall; + + NV_ASSERT_OR_RETURN(vectAppend(pTable, &entry) != NULL, + NV_ERR_NO_MEMORY); + } + return NV_OK; +} + +/** + * @brief Gets the dynamic interrupt table for a VF via RPC + * + * @param pGpu + * @param pIntr + * @param numEngines + * @param pTable The interrupt table to fill in, offset to empty entries. + * @param pParams + */ +static NV_STATUS +_intrCopyVfDynamicInterruptTable +( + OBJGPU *pGpu, + Intr *pIntr, + NvU32 numEngines, + InterruptTable *pTable, + NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS *pParams +) +{ + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NvU32 i; + + // Fill in interrupt table with the matching NV2080 engine vectors + for (i = 0; i < numEngines; i++) + { + INTR_TABLE_ENTRY entry = {0}; + NvU32 nv2080EngineType; + RM_ENGINE_TYPE rmEngineType; + NvU32 engineIdx; + NvU32 row; + + NV_ASSERT_OK_OR_RETURN( + kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_INVALID, i, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType)); + NV_ASSERT_OK_OR_RETURN( + kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_INVALID, i, + ENGINE_INFO_TYPE_MC, &engineIdx)); + + entry.mcEngine = engineIdx; + + // VF does not have any stalling interrupts + entry.intrVector = NV_INTR_VECTOR_INVALID; + + nv2080EngineType = gpuGetNv2080EngineType(rmEngineType); + + // Find the right row for this engine + for (row = 0; row < pParams->numEntries; row++) + { + if (pParams->entries[row].nv2080EngineType == nv2080EngineType) + { + break; + } + } + if (row >= pParams->numEntries) + { + // No matching engine received + return NV_ERR_GENERIC; + } + + entry.intrVectorNonStall = pParams->entries[row].notificationIntrVector; + + // Engines' nonstall vectors correspond 1 to 1 with their old pmcIntrMask bit + if ((!pIntr->getProperty(pIntr, PDB_PROP_INTR_HOST_DRIVEN_ENGINES_REMOVED_FROM_PMC)) && + (entry.intrVectorNonStall != NV_INTR_VECTOR_INVALID)) + { + entry.pmcIntrMask = NVBIT(entry.intrVectorNonStall); + } + else + { + entry.pmcIntrMask = NV_PMC_INTR_INVALID_MASK; + } + + NV_ASSERT_OR_RETURN(vectAppend(pTable, &entry) != NULL, + NV_ERR_NO_MEMORY); + } + + return NV_OK; +} + +NV_STATUS +intrInitInterruptTable_VIRTUAL +( + OBJGPU *pGpu, + Intr *pIntr +) +{ + NV_STATUS status = NV_OK; + NvHandle hClient = NV01_NULL_OBJECT; + NvHandle hObject = NV01_NULL_OBJECT; + NvU32 numEngines = kfifoGetNumEngines_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu)); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS *pStaticParams = NULL; + + NV_ASSERT_OR_RETURN(vectIsEmpty(&pIntr->intrTable), NV_ERR_INVALID_STATE); + + // Allocate params on the heap to avoid stack overflow + pStaticParams = portMemAllocNonPaged(sizeof *pStaticParams); + NV_ASSERT_TRUE_OR_GOTO(status, + pStaticParams != NULL, + NV_ERR_NO_MEMORY, + cleanup); + + NV_RM_RPC_CONTROL(pGpu, + hClient, + hObject, + NV2080_CTRL_CMD_MC_GET_STATIC_INTR_TABLE, + pStaticParams, + sizeof(*pStaticParams), + status); + NV_ASSERT_OR_GOTO(status == NV_OK, cleanup); + NV_ASSERT_TRUE_OR_GOTO(status, + pStaticParams->numEntries <= + NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_MAX, + NV_ERR_OUT_OF_RANGE, + cleanup); + + NV_ASSERT_TRUE_OR_GOTO(status, + pVSI->mcEngineNotificationIntrVectors.numEntries <= + NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_MAX_ENGINES, + NV_ERR_OUT_OF_RANGE, + cleanup); + + NV_ASSERT_OK_OR_GOTO(status, + vectReserve(&pIntr->intrTable, + pStaticParams->numEntries + pVSI->mcEngineNotificationIntrVectors.numEntries), + cleanup); + NV_ASSERT_OK_OR_GOTO(status, + _intrCopyVfStaticInterruptTable(pGpu, pIntr, + &pIntr->intrTable, + pStaticParams), + cleanup); + NV_ASSERT_OK_OR_GOTO(status, + _intrCopyVfDynamicInterruptTable(pGpu, pIntr, + numEngines, + &pIntr->intrTable, + &pVSI->mcEngineNotificationIntrVectors), + cleanup); + vectTrim(&pIntr->intrTable, 0); + + status = NV_OK; + + // Bug 3823562 TODO: Fetch this from Host RM + intrInitSubtreeMap_HAL(pGpu, pIntr); + +cleanup: + portMemFree(pStaticParams); + return status; +} diff --git a/src/nvidia/src/kernel/gpu/mc/arch/hopper/kernel_mc_gh100.c b/src/nvidia/src/kernel/gpu/mc/arch/hopper/kernel_mc_gh100.c new file mode 100644 index 0000000000..05f4927108 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mc/arch/hopper/kernel_mc_gh100.c @@ -0,0 +1,89 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "kernel/gpu/mc/kernel_mc.h" +#include "gpu/gpu.h" + +#include "published/hopper/gh100/dev_pmc.h" + +/*! + * @brief Updates PMC_ENABLE register whose pmcEnableMask is passed. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelMc + * @param[in] pmcEnableMask PMC Mask of engines to be reset. + * @param[in] bEnable If True, Enable the engine, else Reset the engines. + * @param[in] bIsPmcDeviceEngine NV_TRUE if it is PMC_DEVICE_ENABLE register + * else its PMC_ENABLE register. + * + * @return NV_OK + */ +NV_STATUS +kmcWritePmcEnableReg_GH100 +( + OBJGPU *pGpu, + KernelMc *pKernelMc, + NvU32 pmcEnableMask, + NvBool bEnable, + NvBool bIsPmcDeviceEngine +) +{ + if (bIsPmcDeviceEngine) + { + NV_ASSERT_FAILED("NV_PMC_DEVICE_ENABLE is not valid on Hopper+\n"); + return NV_ERR_INVALID_ARGUMENT; + } + + // No need for bIsPmcDeviceEngine, so just call GK104 + return kmcWritePmcEnableReg_GK104(pGpu, pKernelMc, pmcEnableMask, bEnable, NV_FALSE); +} + +/*! + * @brief Returns NV_PMC_ENABLE or NV_PMC_DEVICE_ENABLE register based on bIsPmcDeviceEngine. + * If bIsPmcDeviceEngine is NV_TRUE, then return NV_PMC_DEVICE_ENABLE (available from Ampere), + * If bIsPmcDeviceEngine is NV_FALSE, then return NV_PMC_ENABLE. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelMc + * @param[in] bIsPmcDeviceEngine if true return NV_PMC_DEVICE_ENABLE else return NV_PMC_ENABLE register. + * + * @return NvU32 containing register data + */ +NvU32 +kmcReadPmcEnableReg_GH100 +( + OBJGPU *pGpu, + KernelMc *pKernelMc, + NvBool bIsPmcDeviceEngine +) +{ + if (bIsPmcDeviceEngine) + { + NV_ASSERT_FAILED("NV_PMC_DEVICE_ENABLE is not valid on Hopper+\n"); + return 0; + } + + // No need for bIsPmcDeviceEngine, so just call GK104 + return kmcReadPmcEnableReg_GK104(pGpu, pKernelMc, NV_FALSE); +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c index f8cb53afe1..0578858b38 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c @@ -24,14 +24,6 @@ #include "core/core.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_mgr.h" -#include "gpu/mem_mgr/heap.h" -#include "gpu/mem_mgr/mem_desc.h" - -#include "nvRmReg.h" - -#include "kernel/gpu/intr/intr.h" -#include "gpu/subdevice/subdevice.h" -#include "vgpu/vgpu_events.h" /*! * Returns the max context size diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c index 71301acd53..cf06185327 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/fbsr_ga100.c @@ -56,7 +56,7 @@ fbsrSendMemsysProgramRawCompressionMode_GA100 NV_STATUS fbsrBegin_GA100(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op) { - if (op == FBSR_OP_RESTORE) + if (op == FBSR_OP_RESTORE && !IS_VIRTUAL(pGpu)) { const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); @@ -91,7 +91,7 @@ fbsrEnd_GA100(OBJGPU *pGpu, OBJFBSR *pFbsr) { NV_STATUS status = fbsrEnd_GM107(pGpu, pFbsr); - if (pFbsr->op == FBSR_OP_RESTORE && pFbsr->bRawModeWasEnabled) + if (pFbsr->op == FBSR_OP_RESTORE && pFbsr->bRawModeWasEnabled && !IS_VIRTUAL(pGpu)) { /* * Reenable raw mode if it was disabled by fbsrBegin_GA100. diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c index bb7f7c465d..ebebdc7212 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/ampere/mem_mgr_ga100.c @@ -25,14 +25,13 @@ #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_sys/kern_mem_sys.h" -#include "gpu/mem_mgr/heap.h" #include "gpu/mem_mgr/mem_desc.h" +#include "platform/sli/sli.h" #include "nvRmReg.h" #include "kernel/gpu/intr/intr.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" -#include "gpu/subdevice/subdevice.h" #include "vgpu/vgpu_events.h" #include "nvdevid.h" @@ -82,6 +81,15 @@ memmgrAllocDetermineAlignment_GA100 NvU64 hwAlignment ) { + const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = + kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + + // set the alignment to 256K if property is enabled and its a compressed surface + if (pMemorySystemConfig->bUseOneToFourComptagLineAllocation && + !FLD_TEST_DRF(OS32, _ATTR, _COMPR, _NONE, retAttr)) + { + hwAlignment = pMemorySystemConfig->comprPageSize - 1; + } return memmgrAllocDetermineAlignment_GM107(pGpu, pMemoryManager, pMemSize, pAlign, alignPad, allocFlags, retAttr, retAttr2, hwAlignment); @@ -275,7 +283,7 @@ memmgrGetMaxContextSize_GA100 // of GR buffers. Since GR buffers are not allocated inside guest RM // we are skipping reservation there // - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && + if (RMCFG_FEATURE_PLATFORM_WINDOWS && pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) { size += 32 * 1024 * 1024; @@ -493,22 +501,15 @@ memmgrInsertUnprotectedRegionAtBottomOfFb_GA100 } NvBool -memmgrIsApertureSupportedByFla_GA100 +memmgrIsMemDescSupportedByFla_GA100 ( OBJGPU *pGpu, MemoryManager *pMemoryManager, - NV_ADDRESS_SPACE aperture + MEMORY_DESCRIPTOR *pMemDesc ) { - // - // TODO: Bug 3802992: ADDR_EGM will be removed once the new design as part - // of bug 3802992 is implemented wherein EGM would be represented using - // ADDR_SYSMEM itself. - // - if ((aperture == ADDR_FBMEM) - || (aperture == ADDR_EGM) || - ((aperture == ADDR_SYSMEM) && - memmgrIsLocalEgmEnabled(pMemoryManager)) + if ((memdescGetAddressSpace(pMemDesc) == ADDR_FBMEM) + || memdescIsEgm(pMemDesc) ) { return NV_TRUE; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c index 1fa3ab543a..9b1e0bd2c8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/hopper/mem_utils_gh100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c index c92323d1e8..feb4d609c6 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/fbsr_gm107.c @@ -23,12 +23,14 @@ #include "core/core.h" #include "os/os.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/fbsr.h" #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/mem_desc.h" #include "published/maxwell/gm107/dev_ram.h" #include "core/thread_state.h" +#include "nvrm_registry.h" // // Implementation notes: @@ -341,16 +343,40 @@ NV_STATUS fbsrBegin_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op) { NV_STATUS status = NV_OK; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); pFbsr->op = op; pFbsr->bOperationFailed = NV_FALSE; if (op != FBSR_OP_SIZE_BUF && op != FBSR_OP_DESTROY) { - if (IS_GSP_CLIENT(pGpu)) + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu)) { pFbsr->pCe = NULL; } + // + // On guest, force re-initialize CeUtils with inst-in-sys. + // See bug 4414361 for details. + // + if (IS_VIRTUAL(pGpu)) + { + NvU32 instLocOverrides = pGpu->instLocOverrides; + NvU32 instLocOverrides4 = pGpu->instLocOverrides4; + + if (pMemoryManager->pCeUtils != NULL) + { + memmgrDestroyCeUtils(pMemoryManager, NV_FALSE); + } + + pGpu->instLocOverrides = FLD_SET_DRF(_REG_STR, _RM_INST_LOC, _USERD, _NCOH, pGpu->instLocOverrides); + pGpu->instLocOverrides4 = FLD_SET_DRF(_REG_STR_RM, _INST_LOC_4, _CHANNEL_PUSHBUFFER, _NCOH, pGpu->instLocOverrides4); + + NV_ASSERT_OK_OR_RETURN(memmgrInitCeUtils(pMemoryManager, NV_FALSE)); + + pGpu->instLocOverrides = instLocOverrides; + pGpu->instLocOverrides4 = instLocOverrides4; + } + NV_PRINTF(LEVEL_INFO, "%s %lld bytes of data\n", pFbsr->op == FBSR_OP_SAVE ? "saving" : "restoring", pFbsr->length); @@ -454,7 +480,7 @@ fbsrBegin_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op) break; } - if(bIommuEnabled) + if (bIommuEnabled) { status = osSrPinSysmem(pGpu->pOsGpuInfo, pFbsr->length, @@ -545,7 +571,7 @@ fbsrBegin_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, FBSR_OP_TYPE op) } // Initialize FBSR on GSP - if (IS_GSP_CLIENT(pGpu) && (pFbsr->pSysMemDesc != NULL)) + if ((status == NV_OK) && IS_GSP_CLIENT(pGpu) && (pFbsr->pSysMemDesc != NULL)) { NV_ASSERT_OK_OR_RETURN(_fbsrInitGsp(pGpu, pFbsr)); } @@ -659,9 +685,15 @@ fbsrEnd_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr) { NvBool bIommuEnabled = pGpu->getProperty(pGpu, PDB_PROP_GPU_ENABLE_IOMMU_SUPPORT); NV_STATUS status = NV_OK; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); if (pFbsr->op != FBSR_OP_SIZE_BUF && pFbsr->op != FBSR_OP_DESTROY) { + + if (IS_VIRTUAL(pGpu) && pMemoryManager->pCeUtils != NULL) + { + memmgrDestroyCeUtils(pMemoryManager, NV_FALSE); + } } if (pFbsr->op == FBSR_OP_RESTORE || pFbsr->bOperationFailed || pFbsr->op == FBSR_OP_DESTROY) @@ -1209,4 +1241,3 @@ fbsrCopyMemoryMemDesc_GM107(OBJGPU *pGpu, OBJFBSR *pFbsr, MEMORY_DESCRIPTOR *pVi #ifdef DEBUG #endif - diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c index 5d01e3e6b2..1e9c90205b 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c @@ -28,13 +28,17 @@ #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/heap.h" #include "gpu/mem_mgr/mem_desc.h" +#include "gpu/mem_mgr/fermi_dma.h" #include "gpu/mem_mgr/virt_mem_allocator.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/bus/kern_bus.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "platform/sli/sli.h" +#include "nvrm_registry.h" #include "gpu/bif/kernel_bif.h" +#include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "gpu/disp/inst_mem/disp_inst_mem.h" @@ -695,7 +699,7 @@ memmgrStateInitReservedMemory MemoryManager *pMemoryManager ) { - if (IS_GSP_CLIENT(pGpu)) + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu)) return; } @@ -712,6 +716,100 @@ memmgrStateInitAdjustReservedMemory ) { + if (!IS_GSP_CLIENT(pGpu)) + { + NV_STATUS status; + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 allocFlags = MEMDESC_FLAGS_NONE; + const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); + + // check for allocating VPR memory + if (pKernelBus->bInstProtectedMem) + allocFlags |= MEMDESC_ALLOC_FLAGS_PROTECTED; + + if ((status = memdescCreate(&pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc, pGpu, + GF100_BUS_INSTANCEBLOCK_SIZE, + GF100_BUS_INSTANCEBLOCK_SIZE, + NV_TRUE, + pKernelBus->InstBlkAperture, + pKernelBus->InstBlkAttr, + allocFlags)) != NV_OK) + { + return status; + } + + if ((memdescGetAddressSpace(pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc) == ADDR_SYSMEM) && + (gpuIsInstanceMemoryAlwaysCached(pGpu))) + { + memdescSetGpuCacheAttrib(pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc, NV_MEMORY_CACHED); + } + + if ((status = memdescCreate(&pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc, pGpu, + GF100_BUS_INSTANCEBLOCK_SIZE, + GF100_BUS_INSTANCEBLOCK_SIZE, + NV_TRUE, + pKernelBus->InstBlkAperture, + pKernelBus->InstBlkAttr, + allocFlags)) != NV_OK) + { + return status; + } + + if ((memdescGetAddressSpace(pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc) == ADDR_SYSMEM) && + (gpuIsInstanceMemoryAlwaysCached(pGpu))) + { + memdescSetGpuCacheAttrib(pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc, NV_MEMORY_CACHED); + } + + switch (pKernelBus->InstBlkAperture) + { + default: + case ADDR_FBMEM: + pKernelBus->bar1[GPU_GFID_PF].instBlockBase += pMemoryManager->rsvdMemoryBase; + memdescDescribe(pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc, + pKernelBus->InstBlkAperture, + pKernelBus->bar1[GPU_GFID_PF].instBlockBase, + GF100_BUS_INSTANCEBLOCK_SIZE); + pKernelBus->bar2[GPU_GFID_PF].instBlockBase += pMemoryManager->rsvdMemoryBase; + memdescDescribe(pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc, + pKernelBus->InstBlkAperture, + pKernelBus->bar2[GPU_GFID_PF].instBlockBase, + GF100_BUS_INSTANCEBLOCK_SIZE); + + // Pre-fill cache to prevent FB read accesses if in cache only mode and not doing one time pre-fill + if (gpuIsCacheOnlyModeEnabled(pGpu) && + !pMemorySystemConfig->bL2PreFill) + { + kmemsysPreFillCacheOnlyMemory_HAL(pGpu, pKernelMemorySystem, pKernelBus->bar1[GPU_GFID_PF].instBlockBase, GF100_BUS_INSTANCEBLOCK_SIZE); + kmemsysPreFillCacheOnlyMemory_HAL(pGpu, pKernelMemorySystem, pKernelBus->bar2[GPU_GFID_PF].instBlockBase, GF100_BUS_INSTANCEBLOCK_SIZE); + } + break; + + case ADDR_SYSMEM: + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_135, + (pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "couldn't allocate BAR1 instblk in sysmem\n"); + return status; + } + pKernelBus->bar1[GPU_GFID_PF].instBlockBase = memdescGetPhysAddr(pKernelBus->bar1[GPU_GFID_PF].pInstBlkMemDesc, AT_GPU, 0); + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_136, + (pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "couldn't allocate BAR2 instblk in sysmem\n"); + return status; + } + pKernelBus->bar2[GPU_GFID_PF].instBlockBase = memdescGetPhysAddr(pKernelBus->bar2[GPU_GFID_PF].pInstBlkMemDesc, AT_GPU, 0); + break; + } + } + return NV_OK; } @@ -754,8 +852,6 @@ memmgrInitReservedMemory_GM107 NvU64 rsvdTopOfMem = 0; NvU64 rsvdAlignment = 0; NvBool bMemoryProtectionEnabled = NV_FALSE; - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu)) { @@ -834,8 +930,16 @@ memmgrInitReservedMemory_GM107 // In L2 cache only mode, base this off the size of L2 cache // If reserved memory at top of FB, base this off the size of FB // - if (gpuIsCacheOnlyModeEnabled(pGpu) || !pMemorySystemConfig->bReservedMemAtBottom) + if (gpuIsCacheOnlyModeEnabled(pGpu) || !pMemoryManager->bReservedMemAtBottom) { + const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = + kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + + if (gpuIsCacheOnlyModeEnabled(pGpu)) + { + rsvdTopOfMem = pMemorySystemConfig->l2CacheSize; + } + else { rsvdTopOfMem = pMemoryManager->Ram.fbAddrSpaceSizeMb << 20; @@ -1251,11 +1355,12 @@ memmgrGetRsvdSizeForSr_GM107 MemoryManager *pMemoryManager ) { - if ((pMemoryManager->Ram.fbTotalMemSizeMb >> 10) > 32) + if (((pMemoryManager->Ram.fbTotalMemSizeMb >> 10) > 32) || IS_GSP_CLIENT(pGpu)) { // - // For SKUs with more than 32GB FB, need to reserve for more memory for S/R - // Bug Id:2468357 + // We need to reserve more memory for S/R if + // 1. FB size is > 32GB Bug Id: 2468357 + // 2. Or GSP is enabled Bug Id: 4312881 // return 512 * 1024 * 1024; } @@ -1547,15 +1652,13 @@ memmgrGetBlackListPagesForHeap_GM107 Heap *pHeap ) { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); BLACKLIST_ADDRESS *pBlAddrs; NvU32 idx; NV_STATUS status; NvU32 count; - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); - - count = pMemorySystemConfig->maximumBlacklistPages; + count = kmemsysGetMaximumBlacklistPages(pGpu, pKernelMemorySystem); pBlAddrs = portMemAllocNonPaged(sizeof(BLACKLIST_ADDRESS) * count); if (pBlAddrs == NULL) { @@ -1600,3 +1703,296 @@ memmgrGetFBEndReserveSizeEstimate_GM107 return ESTIMATED_RESERVE_FB; } + +/*! + * @brief Calculate the reserved memory requirement + * per FB region for mixed type/density + * + * @param[out] rsvdFastSize generic reserved RM memory needed in fast region + * @param[out] rsvdSlowSize generic reserved RM memory needed in slow region + * @param[out] rsvdISOSize ISO-specific reserved RM memory needed + * + * @returns void + * + */ +void +memmgrCalcReservedFbSpaceHal_GM107 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager, + NvU64 *rsvdFastSize, + NvU64 *rsvdSlowSize, + NvU64 *rsvdISOSize +) +{ + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, 0); + NvU64 smallPagePte = 0; + NvU64 bigPagePte = 0; + NvU32 attribBufferSize; + NvU64 maxContextSize = 0; + NvU64 userdReservedSize = 0; + NvU64 runlistEntriesReservedSize = 0; + NvU64 mmuFaultBufferSize = 0; + NvU64 faultMethodBufferSize = 0; + NV_STATUS status = NV_OK; + + // Initialize reserved block logging data structure + NV_FB_RSVD_BLOCK_LOG_INIT(pMemoryManager); + + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + // + // 4MB of reserved memory for vGPU. + // Mainly to satisfy KMD memory allocations. + // + *rsvdFastSize = 4 * 1024 * 1024; + *rsvdSlowSize = 0; + *rsvdISOSize = 0; + return; + } + +#if defined(NV_UNIX) + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && pMemoryManager->Ram.fbTotalMemSizeMb <= 1024) + { + // + // 88MB of reserved memory for vGPU guest with lower FB size(1GB) + // in full SRIOV mode. On lower vGPU profiles, available FB memory + // is already very less. To compensate for that, reducing the guest + // reserved FB memory. + // + *rsvdFastSize = 88 * 1024 * 1024; + *rsvdSlowSize = 0; + *rsvdISOSize = 0; + return; + } +#endif + + { + *rsvdFastSize = 0; + + // Allow reservation up to half of usable FB size + if (pMemoryManager->rsvdMemorySizeIncrement > (pMemoryManager->Ram.fbUsableMemSize / 2)) + { + pMemoryManager->rsvdMemorySizeIncrement = pMemoryManager->Ram.fbUsableMemSize / 2; + NV_PRINTF(LEVEL_ERROR, + "RM can only increase reserved heap by 0x%llx bytes\n", + pMemoryManager->rsvdMemorySizeIncrement); + } + NV_PRINTF(LEVEL_INFO, "RT::: incrementing the reserved size by: %llx\n", + pMemoryManager->rsvdMemorySizeIncrement); + *rsvdSlowSize = pMemoryManager->rsvdMemorySizeIncrement; + *rsvdISOSize = 0; + } + + if (RMCFG_FEATURE_PLATFORM_WINDOWS && pMemoryManager->bBug2301372IncreaseRmReserveMemoryWar) + { + *rsvdFastSize += 30 * 1024 * 1024; + } + + attribBufferSize = memmgrGetGrHeapReservationSize_HAL(pGpu, pMemoryManager); + + // Fast: Attribute buffer + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_ATTR_BUFFER, + attribBufferSize); + *rsvdFastSize += attribBufferSize; + + // Fast: Circular buffer & fudge + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_CIRCULAR_BUFFER, + 1 *1024 *1024); + *rsvdFastSize += 1 *1024 *1024; + + if (!RMCFG_FEATURE_PLATFORM_GSP) + { + // smallPagePte = FBSize /4k * 8 (Small page PTE for whole FB) + smallPagePte = NV_ROUNDUP((pMemoryManager->Ram.fbUsableMemSize / FERMI_SMALL_PAGESIZE) * 8, RM_PAGE_SIZE); + + // bigPagePte = FBSize /bigPageSize * 8 (Big page PTE for whole FB) + bigPagePte = NV_ROUNDUP((pMemoryManager->Ram.fbUsableMemSize / (kgmmuGetMaxBigPageSize_HAL(pKernelGmmu))) * 8, + RM_PAGE_SIZE); + + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_PAGE_PTE, + (smallPagePte + bigPagePte)); + } + + userdReservedSize = memmgrGetUserdReservedFbSpace_HAL(pGpu, pMemoryManager); + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_USERD_BUFFER, + userdReservedSize); + + runlistEntriesReservedSize = memmgrGetRunlistEntriesReservedFbSpace_HAL(pGpu, pMemoryManager); + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_RUNLIST_ENTRIES, + runlistEntriesReservedSize); + + maxContextSize = memmgrGetMaxContextSize_HAL(pGpu, pMemoryManager); + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_CONTEXT_BUFFER, + maxContextSize); + *rsvdSlowSize += + userdReservedSize + // Kepler USERD + runlistEntriesReservedSize + // Kepler Runlist entries + smallPagePte + // small page Pte + bigPagePte + // big page pte + maxContextSize; + + // Reserve FB for UVM on WDDM + memmgrCalcReservedFbSpaceForUVM_HAL(pGpu, pMemoryManager, rsvdSlowSize); + + // Reserve FB for MMU fault buffers + mmuFaultBufferSize = kgmmuGetFaultBufferReservedFbSpaceSize(pGpu, pKernelGmmu); + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_MMU_FAULT_BUFFER, + mmuFaultBufferSize); + *rsvdSlowSize += mmuFaultBufferSize; + + // Reserve FB for Fault method buffers + if (!RMCFG_FEATURE_PLATFORM_GSP) + { + faultMethodBufferSize = kfifoCalcTotalSizeOfFaultMethodBuffers_HAL(pGpu, pKernelFifo, NV_TRUE); + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_FAULT_METHOD, + faultMethodBufferSize); + *rsvdSlowSize += faultMethodBufferSize; + } + + // The access map is fairly large (512KB) so we account for it specifically + if (kgraphicsDoesUcodeSupportPrivAccessMap(pGpu, pKernelGraphics)) + { + *rsvdSlowSize += pGpu->userRegisterAccessMapSize; + NV_FB_RSVD_BLOCK_LOG_ENTRY_ADD(status, pMemoryManager, NV_FB_ALLOC_RM_INTERNAL_OWNER_ACCESS_MAP, + pGpu->userRegisterAccessMapSize); + } + + if (*rsvdFastSize + *rsvdSlowSize > pMemoryManager->Ram.fbUsableMemSize / 2) + { + NV_PRINTF(LEVEL_ERROR, + "Before capping: rsvdFastSize = 0x%llx bytes rsvdSlowSize = 0x%llx " + "bytes Usable FB = 0x%llx bytes\n", *rsvdFastSize, + *rsvdSlowSize, pMemoryManager->Ram.fbUsableMemSize); + if (pMemoryManager->rsvdMemorySizeIncrement > 0) + { + NV_PRINTF(LEVEL_ERROR, + "Fail the rsvd memory capping in case of user specified increase = %llx bytes\n", + pMemoryManager->rsvdMemorySizeIncrement); + *rsvdFastSize = 0; + *rsvdSlowSize = 0; + NV_ASSERT(0); + return; + } + // Scale down fast and slow proportionally + *rsvdFastSize = *rsvdFastSize * pMemoryManager->Ram.fbUsableMemSize / 2 + / (*rsvdFastSize + *rsvdSlowSize); + *rsvdSlowSize = pMemoryManager->Ram.fbUsableMemSize / 2 - *rsvdFastSize; + NV_PRINTF(LEVEL_ERROR, + "After capping: rsvdFastSize = 0x%llx bytes rsvdSlowSize = 0x%llx bytes\n", + *rsvdFastSize, *rsvdSlowSize); + } + + if (!pMemoryManager->bPreferSlowRegion) + { + *rsvdFastSize = *rsvdFastSize + *rsvdSlowSize; + *rsvdSlowSize = 0; + } + + // + // Memory should be blocked off with 64K granularity. This makes PMA and + // and VA space management more efficient. + // + *rsvdFastSize = NV_ROUNDUP(*rsvdFastSize, RM_PAGE_SIZE_64K); + *rsvdSlowSize = NV_ROUNDUP(*rsvdSlowSize, RM_PAGE_SIZE_64K); + *rsvdISOSize = NV_ROUNDUP(*rsvdISOSize, RM_PAGE_SIZE_64K); + + // If any of the reservation logging fails then print error message + if (status != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, "Error logging the FB reservation entries\n"); + } +} + +/*! + * Set up RM reserved memory space + */ +NV_STATUS +memmgrPreInitReservedMemory_GM107 +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU64 tmpAddr = 0; + NV_STATUS status = NV_OK; + NvU32 instBlkBarOverride = 0; + + // *************************************************************** + // Determine the size of reserved memory & tell the HW where it is + // Note that the order of these matters for optimum alignment & + // FB usage. The order must be highest alignment requirement to + // lowest alignment requirement, with the last item being the + // vbios image / workspace area + // *************************************************************** + + if (IS_GSP_CLIENT(pGpu) && pKernelDisplay != NULL) + { + // TODO: Determine the correct size of display instance memory + // via instmemGetSize_HAL(), as well as other parameters. + // I.e. refactor and leverage the code performing these tasks + // in memmgrPreInitReservedMemory_GM107() today. + tmpAddr += 0x10000; + } + + { + instBlkBarOverride = DRF_VAL(_REG_STR_RM, _INST_LOC, _INSTBLK, pGpu->instLocOverrides); + } + + pKernelBus->InstBlkAperture = ADDR_FBMEM; + pKernelBus->InstBlkAttr = NV_MEMORY_WRITECOMBINED; + + memdescOverrideInstLoc(instBlkBarOverride, "BAR instblk", + &pKernelBus->InstBlkAperture, + &pKernelBus->InstBlkAttr); + + if (pKernelBus->InstBlkAperture == ADDR_FBMEM) + { + // Reserve space for BAR1 and BAR2 instance blocks + tmpAddr = NV_ROUNDUP(tmpAddr, GF100_BUS_INSTANCEBLOCK_SIZE); + pKernelBus->bar1[GPU_GFID_PF].instBlockBase = tmpAddr; + tmpAddr += GF100_BUS_INSTANCEBLOCK_SIZE; + + tmpAddr = NV_ROUNDUP(tmpAddr, GF100_BUS_INSTANCEBLOCK_SIZE); + pKernelBus->bar2[GPU_GFID_PF].instBlockBase = tmpAddr; + tmpAddr += GF100_BUS_INSTANCEBLOCK_SIZE; + + NV_PRINTF(LEVEL_INFO, "Reserve space for Bar1 inst block offset = 0x%llx size = 0x%x\n", + pKernelBus->bar1[GPU_GFID_PF].instBlockBase, GF100_BUS_INSTANCEBLOCK_SIZE); + + NV_PRINTF(LEVEL_INFO, "Reserve space for Bar2 inst block offset = 0x%llx size = 0x%x\n", + pKernelBus->bar2[GPU_GFID_PF].instBlockBase, GF100_BUS_INSTANCEBLOCK_SIZE); + } + + if (gpuIsSelfHosted(pGpu) && !RMCFG_FEATURE_PLATFORM_GSP) + { + // + // Reserve space for the test buffer used in coherent link test + // that is run early when memory allocation is not ready yet. + // + pKernelBus->coherentLinkTestBufferBase = tmpAddr; + tmpAddr += BUS_COHERENT_LINK_TEST_BUFFER_SIZE; + } + + // + // This has to be the very *last* thing in reserved memory as it + // will may grow past the 1MB reserved memory window. We cannot + // size it until memsysStateInitLockedHal_GM107. + // + memmgrReserveBar2BackingStore(pGpu, pMemoryManager, &tmpAddr); + + // + // Store the size of rsvd memory excluding VBIOS space. Size finalized in memmgrStateInitReservedMemory. + // + NV_ASSERT(NvU64_LO32(tmpAddr) == tmpAddr); + pMemoryManager->rsvdMemorySize = NvU64_LO32(tmpAddr); + + NV_PRINTF(LEVEL_INFO, "Calculated size of reserved memory = 0x%x. Size finalized in StateInit.\n", pMemoryManager->rsvdMemorySize); + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c index 19a285d4a8..dc02c0eb70 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm200.c @@ -22,6 +22,7 @@ */ #include "core/core.h" +#include "platform/sli/sli.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" @@ -51,7 +52,7 @@ memmgrGetMaxContextSize_GM200 // spaces. // - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_WINDOWS) { if (pGpu->getProperty(pGpu, PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL)) { @@ -104,5 +105,9 @@ memmgrGetMaxContextSize_GM200 size = 0; } } + + // Reserve enough memory for CeUtils + size += (7*1024*1024); + return size; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c index fcc2fb9ea5..7c66e4f046 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_utils_gm107.c @@ -23,6 +23,7 @@ #include "core/core.h" #include "gpu/gpu.h" +#include "gpu/device/device.h" #include "os/os.h" #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/mem_mgr.h" @@ -37,10 +38,10 @@ #include "nvRmReg.h" #include "rmapi/rs_utils.h" #include "mem_mgr/ctx_buf_pool.h" -#include "gpu/subdevice/subdevice.h" #include "vgpu/rpc.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "platform/chipset/chipset.h" +#include "platform/sli/sli.h" #include "class/clc0b5sw.h" #include "class/cla06fsubch.h" // NVA06F_SUBCHANNEL_COPY_ENGINE @@ -228,6 +229,10 @@ _memUtilsChannelAllocatePB_GM107 DRF_DEF(OS32, _ATTR, _COHERENCY, _UNCACHED); flags = NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM; + if (!IS_MIG_IN_USE(pGpu)) + { + attr |= DRF_DEF(OS32, _ATTR, _ALLOCATE_FROM_RESERVED_HEAP, _YES); + } attrNotifier = attr; break; @@ -639,6 +644,11 @@ memmgrMemUtilsChannelInitialize_GM107 NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL | NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE; + if (!IS_MIG_IN_USE(pGpu)) + { + pVa->flags |= NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED; + } + if (rmDeviceGpuLockIsOwner(pGpu->gpuInstance)) { rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); @@ -1222,6 +1232,10 @@ _memUtilsAllocateUserD userdMemClass = NV01_MEMORY_LOCAL_USER; memAllocParams.attr = DRF_DEF(OS32, _ATTR, _LOCATION, _VIDMEM); memAllocParams.flags |= NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM; + if (!IS_MIG_IN_USE(pGpu)) + { + memAllocParams.attr |= DRF_DEF(OS32, _ATTR, _ALLOCATE_FROM_RESERVED_HEAP, _YES); + } break; } @@ -1683,7 +1697,6 @@ _ceChannelScheduleWork_GM107 RMTIMEOUT timeout; NvU32 spaceInPb; NvU32 numBytes; - NvU32 bytesPushed; NvU32 *ptr; NvU32 gpBase; NvU32 semaCount = 0; @@ -1723,7 +1736,6 @@ _ceChannelScheduleWork_GM107 ptr = (NvU32 *)(pChannel->pbCpuVA + pChannel->channelPutOffset); gpBase = 0; numBytes = 0; - bytesPushed = 0; // update the available space spaceInPb = _getSpaceInPb(pChannel); NV_PRINTF(LEVEL_INFO, "Wrapping PB around\n"); @@ -1755,7 +1767,7 @@ _ceChannelScheduleWork_GM107 } if(_checkSynchronization(pGpu, pMemoryManager, pChannel, BLOCK_INDEX_FROM_ADDR(dst, pChannel->blockShift))) { - bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, + NvU32 bytesPushed = _ceChannelPushMethodsBlock_GM107(pGpu, pMemoryManager, pChannel, src, srcAddressSpace, srcCpuCacheAttrib, // src parameters dst, dstAddressSpace, dstCpuCacheAttrib, // dst parameters blockSize, &ptr, NV_TRUE, (addNonStallIntr && !blocking), diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c index fc2857c58a..a5f5fca21a 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c @@ -120,6 +120,7 @@ #include "mem_mgr/vaspace.h" #include "mem_mgr/fabric_vaspace.h" #include "mem_mgr/virt_mem_mgr.h" +#include "platform/sli/sli.h" #include "mem_mgr/fla_mem.h" @@ -206,6 +207,7 @@ dmaAllocMapping_GM107 { NV_STATUS status = NV_OK; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); OBJEHEAP *pVASpaceHeap = NULL; KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); @@ -216,7 +218,7 @@ dmaAllocMapping_GM107 NvU32 gfid; NvBool bCallingContextPlugin; const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); OBJGVASPACE *pGVAS = NULL; struct @@ -266,6 +268,7 @@ dmaAllocMapping_GM107 NvU32 pageArrayGranularity; NvU8 pageShift; NvU64 physPageSize; + NvU64 pageArrayFlags; } *pLocals = portMemAllocNonPaged(sizeof(*pLocals)); // Heap Allocate to avoid stack overflow @@ -491,7 +494,7 @@ dmaAllocMapping_GM107 // Disable PLC Compression for FLA->PA Mapping because of the HW Bug: 3046774 if (pMemorySystemConfig->bUseRawModeComptaglineAllocation && - pMemorySystemConfig->bDisablePlcForCertainOffsetsBug3046774) + pKernelMemorySystem->bDisablePlcForCertainOffsetsBug3046774) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); @@ -885,7 +888,9 @@ dmaAllocMapping_GM107 // Commit the mapping update pLocals->pPteArray = memdescGetPteArray(pLocals->pTempMemDesc, addressTranslation); - dmaPageArrayInit(&pLocals->pageArray, pLocals->pPteArray, pLocals->pteCount); + + dmaPageArrayInitWithFlags(&pLocals->pageArray, pLocals->pPteArray, pLocals->pteCount, + pLocals->pageArrayFlags); // Get pLocals->aperture if (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FBMEM) @@ -1043,9 +1048,13 @@ dmaAllocMapping_GM107 // Fabric memory descriptors are pre-encoded with the fabric base address // use NVLINK_INVALID_FABRIC_ADDR to avoid encoding twice // + // Skip fabric base address for Local EGM as it uses peer aperture but + // doesn't require fabric address + // if (pLocals->bFlaImport || (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC_MC) || - (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC_V2)) + (memdescGetAddressSpace(pLocals->pTempMemDesc) == ADDR_FABRIC_V2) || + (memdescIsEgm(pLocals->pTempMemDesc) && (pGpu == pLocals->pSrcGpu))) { pLocals->fabricAddr = NVLINK_INVALID_FABRIC_ADDR; } @@ -1525,7 +1534,7 @@ _gmmuWalkCBMapNextEntries_Direct kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); if (pMemorySystemConfig->bUseRawModeComptaglineAllocation && - pMemorySystemConfig->bDisablePlcForCertainOffsetsBug3046774 && + pKernelMemorySystem->bDisablePlcForCertainOffsetsBug3046774 && !memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_DISALLOW_PLC, pIter->comprInfo.kind) && !kmemsysIsPagePLCable_HAL(pGpu, pKernelMemorySystem, (pIter->surfaceOffset + pIter->currIdx * pTarget->pageArrayGranularity), pageSize)) { @@ -1903,7 +1912,7 @@ dmaUpdateVASpace_GF100 kindNoCompression = kind; } - if (!RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && + if (!RMCFG_FEATURE_PLATFORM_WINDOWS && memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, pComprInfo->kind) && ((vAddr & (alignSize-1)) != 0) && !(flags & DMA_UPDATE_VASPACE_FLAGS_UNALIGNED_COMP)) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_gp100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_gp100.c index a78d83324d..8fdb3a9dbf 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_gp100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_gp100.c @@ -24,6 +24,7 @@ #include "core/core.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "platform/sli/sli.h" #include "published/pascal/gp100/dev_mmu.h" #include "class/cl906f.h" // GF100_CHANNEL_GPFIFO @@ -174,69 +175,6 @@ memmgrFinishHandleSizeOverrides_GP100 return rmStatus; } -/*! - * Inserts semaphore methods into the push buffer for one block" - * - * @param[in] subCh Subchannel Id - * @param[in] data Semaphore address. - * @param[in] payload size of copies. - * @param[in/out] **pPtr Pointer to location in pushbuffer. - */ -void -memmgrChannelPushSemaphoreMethodsBlock_GP100 -( - MemoryManager *pMemoryManager, - NvU32 subCh, - NvU64 data, - NvU32 payload, - NvU32 **pPtr -) -{ - NvU32 *ptr = *pPtr; - PUSH_PAIR(subCh, NVC0B5_SET_SEMAPHORE_A, DRF_NUM(C0B5, _SET_SEMAPHORE_A, - _UPPER, NvU64_HI32(data))); - PUSH_PAIR(subCh, NVC0B5_SET_SEMAPHORE_B, DRF_NUM(C0B5, _SET_SEMAPHORE_B, - _LOWER, NvU64_LO32(data))); - PUSH_PAIR(subCh, NVC0B5_SET_SEMAPHORE_PAYLOAD, payload); - *pPtr = ptr; -} - -/*! - * @brief Inserts address methods into the push buffer for one block - * - * @param[in] bSrc If true the address passed is for source - * @param[in] subCh Subchannel Id - * @param[in] addr Physical address of source/destination - * @param[in/out] **pPtr Pointer to location in pushbuffer. - */ -void -memmgrChannelPushAddressMethodsBlock_GP100 -( - MemoryManager *pMemoryManager, - NvBool bSrc, - NvU32 subCh, - RmPhysAddr addr, - NvU32 **pPtr -) -{ - NvU32 *ptr = *pPtr; - if (bSrc == NV_TRUE) - { - PUSH_PAIR(subCh, NVC0B5_OFFSET_IN_UPPER, DRF_NUM(C0B5, - _OFFSET_IN_UPPER, _UPPER, NvU64_HI32(addr))); - PUSH_PAIR(subCh, NVC0B5_OFFSET_IN_LOWER, DRF_NUM(C0B5, - _OFFSET_IN_LOWER, _VALUE, NvU64_LO32(addr))); - } - else - { - PUSH_PAIR(subCh, NVC0B5_OFFSET_OUT_UPPER, DRF_NUM(C0B5, - _OFFSET_OUT_UPPER, _UPPER, NvU64_HI32(addr))); - PUSH_PAIR(subCh, NVC0B5_OFFSET_OUT_LOWER, DRF_NUM(C0B5, - _OFFSET_OUT_LOWER, _VALUE, NvU64_LO32(addr))); - } - *pPtr = ptr; -} - /*! * Returns the max context size * @@ -278,7 +216,7 @@ memmgrGetMaxContextSize_GP100 // a new kmdtest (CreateNProcesses) should be used. - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_WINDOWS) { // Only needs increase in single GPU case as 400 process requirement is satisfied on SLI with the additional SLI reserve if (!IsSLIEnabled(pGpu) && pGpu->getProperty(pGpu, PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL)) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c index b9eb994adf..1100b70cd3 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/pascal/mem_mgr_scrub_gp100.c @@ -30,6 +30,7 @@ #include "gpu/mem_mgr/mem_desc.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_fifo.h" +#include "platform/sli/sli.h" /*! * Performs initialization that is dependant on work done in gpuStateLoad() such diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c index 42556840cf..efc0cd49ef 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102.c @@ -246,7 +246,7 @@ memmgrChooseKind_TU102 case NVOS32_TYPE_RESERVED: case NVOS32_TYPE_PMA: { - if (comprAttr == NVOS32_ATTR_COMPR_NONE) + if (comprAttr == NVOS32_ATTR_COMPR_NONE || pMemorySystemConfig->bDisableCompbitBacking) { kind = NV_MMU_PTE_KIND_GENERIC_MEMORY; } @@ -645,4 +645,4 @@ memmgrCalculateHeapOffsetWithGSP_TU102 } return NV_OK; -} \ No newline at end of file +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c b/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c index d8cd9564c1..3041a6f37c 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/arch/volta/mem_mgr_gv100.c @@ -98,7 +98,7 @@ memmgrGetMaxContextSize_GV100 NvU64 size = memmgrGetMaxContextSize_GP100(pGpu, pMemoryManager); // In Volta, the GR context buffer size increased by about 847 KB (doubled from Pascal) - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_WINDOWS) { // // We are increasing the reserved mem size by 10 MB. diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c index 42670f4bfc..c1abceef50 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/ce_utils.c @@ -34,8 +34,8 @@ #include "core/prelude.h" #include "core/locks.h" #include "gpu/mem_mgr/ce_utils.h" -#include "gpu/subdevice/subdevice.h" #include "kernel/gpu/mem_mgr/ce_utils_sizes.h" +#include "vgpu/rpc_headers.h" #include "class/clb0b5.h" // MAXWELL_DMA_COPY_A #include "class/clc0b5.h" // PASCAL_DMA_COPY_A @@ -98,8 +98,21 @@ ceutilsConstruct_IMPL status = serverGetClientUnderLock(&g_resServ, pChannel->hClient, &pChannel->pRsClient); NV_ASSERT_OR_GOTO(status == NV_OK, free_client); - status = clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U); - NV_ASSERT_OR_GOTO(status == NV_OK, free_client); + if (IS_VIRTUAL(pGpu)) + { + NV_ASSERT_OK_OR_GOTO( + status, + clientSetHandleGenerator(staticCast(pClient, RsClient), RS_UNIQUE_HANDLE_BASE, + RS_UNIQUE_HANDLE_RANGE/2 - VGPU_RESERVED_HANDLE_RANGE), + free_client); + } + else + { + NV_ASSERT_OK_OR_GOTO( + status, + clientSetHandleGenerator(staticCast(pClient, RsClient), 1U, ~0U - 1U), + free_client); + } pChannel->bClientAllocated = NV_TRUE; pChannel->pGpu = pGpu; @@ -129,7 +142,7 @@ ceutilsConstruct_IMPL } // For self-hosted Hopper, we can only use VA copy or faster scrubber - if (gpuIsSelfHosted(pGpu)) + if (pMemoryManager->bCePhysicalVidmemAccessNotSupported) { if (!pChannel->bUseVasForCeCopy && (pChannel->type != FAST_SCRUBBER_CHANNEL)) @@ -187,18 +200,6 @@ ceutilsDestruct_IMPL MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); - // Sanity checks - if ((pGpu == NULL) || (pChannel == NULL)) - { - NV_PRINTF(LEVEL_WARNING, "Possible double-free of CeUtils!\n"); - return; - } - else if (pGpu != pChannel->pGpu) - { - NV_PRINTF(LEVEL_ERROR, "Bad state during ceUtils teardown!\n"); - return; - } - if ((pChannel->bClientUserd) && (pChannel->pControlGPFifo != NULL)) { if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu))) @@ -273,7 +274,7 @@ ceutilsServiceInterrupts_IMPL(CeUtils *pCeUtils) static NvBool _ceUtilsFastScrubEnabled ( - POBJCHANNEL pChannel, + OBJCHANNEL *pChannel, CHANNEL_PB_INFO *pChannelPbInfo ) { @@ -311,7 +312,7 @@ _ceUtilsFastScrubEnabled static NV_STATUS _ceutilsSubmitPushBuffer ( - POBJCHANNEL pChannel, + OBJCHANNEL *pChannel, NvBool bPipelined, NvBool bInsertFinishPayload, CHANNEL_PB_INFO * pChannelPbInfo @@ -356,7 +357,7 @@ _ceutilsSubmitPushBuffer } else { - if (gpuIsSelfHosted(pChannel->pGpu)) + if (pMemoryManager->bCePhysicalVidmemAccessNotSupported) { // Self-hosted Hopper only supports VA copy or fast scrubber NV_ASSERT_OR_RETURN(pChannel->bUseVasForCeCopy, NV_ERR_NOT_SUPPORTED); @@ -659,7 +660,6 @@ ceutilsUpdateProgress_IMPL return swLastCompletedPayload; } -#if defined(DEBUG) || defined (DEVELOP) NV_STATUS ceutilsapiCtrlCmdCheckProgress_IMPL ( @@ -795,4 +795,3 @@ ceutilsapiCtrlCmdMemcopy_IMPL return status; } -#endif // defined(DEBUG) || defined (DEVELOP) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c index 73c0bb68c8..f56482e08a 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/channel_utils.c @@ -741,12 +741,6 @@ channelFillSec2Pb portMemCopy((void*)pBufScrub, SHA_256_HASH_SIZE_BYTE, (const void*)&hmacDigest[0], SHA_256_HASH_SIZE_BYTE); - if (methodIdx > SEC2_WL_METHOD_ARRAY_SIZE) - { - status = NV_ERR_INVALID_ARGUMENT; - goto cleanup; - } - for (NvU32 i = 0; i < methodIdx; i++) { NV_PUSH_INC_1U(RM_SUBCHANNEL, pMethods[i*2 + 0], pMethods[i*2 + 1]); @@ -774,12 +768,6 @@ channelFillSec2Pb portMemCopy((void*)pBufSema, SHA_256_HASH_SIZE_BYTE, (const void*)&hmacDigest[0], SHA_256_HASH_SIZE_BYTE); - if (methodIdx > SEC2_WL_METHOD_ARRAY_SIZE) - { - status = NV_ERR_INVALID_ARGUMENT; - goto cleanup; - } - for (NvU32 i = 0; i < methodIdx; i++) { NV_PUSH_INC_1U(RM_SUBCHANNEL, pMethods[i*2 + 0], pMethods[i*2 + 1]); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c b/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c index 62e1ed1a90..89c86d88a8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c @@ -44,6 +44,7 @@ #include "gpu/subdevice/subdevice.h" #include "rmapi/rs_utils.h" #include "rmapi/mapping_list.h" +#include "platform/sli/sli.h" #include "gpu/bus/kern_bus.h" diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/dma.c b/src/nvidia/src/kernel/gpu/mem_mgr/dma.c index f4fc03e261..1496f37623 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/dma.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/dma.c @@ -52,6 +52,7 @@ #include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "gpu/bus/kern_bus.h" +#include "platform/sli/sli.h" /*! * @brief Allocate mapping. @@ -1135,6 +1136,23 @@ dmaPageArrayInit pPageArray->count = pageCount; } +/*! + * Initialize an abstracted page array with opaque page array data. + * + * TODO: Deprecate dmaPageArrayInit once moving all the use cases. + */ +void +dmaPageArrayInitWithFlags +( + DMA_PAGE_ARRAY *pPageArray, //!< [out] Abstracted page array. + void *pPageData, //!< [in] Opaque page array data. + NvU32 pageCount, //!< [in] Number of pages represented + NvU64 pageArrayFlags //!< [in] Flags of type DMA_PAGE_ARRARY_FLAGS +) +{ + dmaPageArrayInit(pPageArray, pPageData, pageCount); +} + /*! * Initialize an abstracted page array from a memory descriptor. */ @@ -1184,7 +1202,9 @@ dmaPageArrayGetPhysAddr else { RmPhysAddr *pPteArray = pPageArray->pData; - addr = pPteArray[pPageArray->startIndex + pageIndex]; + { + addr = pPteArray[pPageArray->startIndex + pageIndex]; + } } addr |= pPageArray->orMask; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c index 42798e40a6..a5b4fe4499 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/heap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/heap.c @@ -41,10 +41,12 @@ #include "core/locks.h" #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER #include "vgpu/rpc.h" +#include "vgpu/vgpu_util.h" #include "gpu/mmu/kern_gmmu.h" #include "virtualization/hypervisor/hypervisor.h" #include "gpu/device/device.h" #include "kernel/gpu/intr/intr.h" +#include "platform/sli/sli.h" typedef enum { @@ -3051,6 +3053,14 @@ NV_STATUS heapHwAlloc_IMPL // if ((status == NV_OK) && IS_VIRTUAL(pGpu)) { + if (vgpuIsGuestManagedHwAlloc(pGpu) && + (FLD_TEST_DRF(OS32, _ATTR, _COMPR, _NONE, pFbAllocInfo->pageFormat->attr))) + { + status = memmgrAllocHwResources(pGpu, pMemoryManager, pFbAllocInfo); + pHwAlloc->hwResource.isVgpuHostAllocated = NV_FALSE; + NV_ASSERT(status == NV_OK); + } + else { NV_RM_RPC_MANAGE_HW_RESOURCE_ALLOC(pGpu, hClient, @@ -3180,6 +3190,11 @@ void heapHwFree_IMPL if (IS_VIRTUAL(pGpu)) { + if (vgpuIsGuestManagedHwAlloc(pGpu) && !pMemory->pHwResource->isVgpuHostAllocated) + { + memmgrFreeHwResources(pGpu, pMemoryManager, pFbAllocInfo); + } + else { NV_STATUS rmStatus = NV_OK; @@ -4191,6 +4206,7 @@ heapBlackListPages_IMPL ) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); PMA *pPma = &pHeap->pmaObject; NvU32 i = 0, j = 0; NV_STATUS status = NV_OK; @@ -4200,8 +4216,7 @@ heapBlackListPages_IMPL NvU32 staticBlacklistSize, dynamicBlacklistSize; NvU32 dynamicRmBlackListedCount; NvU32 staticRmBlackListedCount; - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + NvU16 maximumBlacklistPages = kmemsysGetMaximumBlacklistPages(pGpu, pKernelMemorySystem); if (NULL == pAddresses) { @@ -4218,14 +4233,14 @@ heapBlackListPages_IMPL // We may not be able to allocate all pages requested, but alloc enough // space anyway // - pBlackList->pBlacklistChunks = portMemAllocNonPaged(sizeof(BLACKLIST_CHUNK) * pMemorySystemConfig->maximumBlacklistPages); + pBlackList->pBlacklistChunks = portMemAllocNonPaged(sizeof(BLACKLIST_CHUNK) * maximumBlacklistPages); if (NULL == pBlackList->pBlacklistChunks) { NV_PRINTF(LEVEL_ERROR, "Could not allocate memory for blackList!\n"); return NV_ERR_NO_MEMORY; } - portMemSet(pBlackList->pBlacklistChunks, 0, sizeof(BLACKLIST_CHUNK) * pMemorySystemConfig->maximumBlacklistPages); + portMemSet(pBlackList->pBlacklistChunks, 0, sizeof(BLACKLIST_CHUNK) * maximumBlacklistPages); dynamicRmBlackListedCount = 0; staticRmBlackListedCount = 0; @@ -4401,6 +4416,7 @@ heapStorePendingBlackList_IMPL ) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NV_STATUS status = NV_OK; NvU64 physicalAddress; NvU64 pageNumber; @@ -4449,7 +4465,7 @@ heapStorePendingBlackList_IMPL if (pMemoryManager->bEnableDynamicPageOfflining) { // adding a new entry to heap managed blacklist - if (pBlacklist->count == pMemorySystemConfig->maximumBlacklistPages) + if (pBlacklist->count == kmemsysGetMaximumBlacklistPages(pGpu, pKernelMemorySystem)) { NV_PRINTF(LEVEL_ERROR, "We have blacklisted maximum number of pages possible. returning error \n"); return NV_ERR_INSUFFICIENT_RESOURCES; @@ -4525,18 +4541,18 @@ heapAddPageToBlackList_IMPL NvU32 type ) { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + NvU16 maximumBlacklistPages = kmemsysGetMaximumBlacklistPages(pGpu, pKernelMemorySystem); NvU32 index = pHeap->blackListAddresses.count; - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); - if (index == pMemorySystemConfig->maximumBlacklistPages) + if (index == maximumBlacklistPages) { return NV_ERR_INSUFFICIENT_RESOURCES; } if (pHeap->blackListAddresses.data == NULL) { - NvU64 listSize = sizeof(BLACKLIST_ADDRESS) * pMemorySystemConfig->maximumBlacklistPages; + NvU64 listSize = sizeof(BLACKLIST_ADDRESS) * maximumBlacklistPages; pHeap->blackListAddresses.data = portMemAllocNonPaged(listSize); if (pHeap->blackListAddresses.data == NULL) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c index 2ec8c99eb6..d992ade32b 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,16 +32,15 @@ #include "core/core.h" #include "os/os.h" #include "gpu/mem_sys/kern_mem_sys.h" -#include "gpu/mem_mgr/heap.h" #include "platform/platform.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "platform/sli/sli.h" #include "gpu/mem_mgr/mem_desc.h" #include "rmapi/client_resource.h" #include "rmapi/control.h" #include "gpu_mgr/gpu_mgr.h" #include "rmapi/rs_utils.h" -#include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "vgpu/rpc.h" @@ -59,17 +58,8 @@ memCtrlCmdGetSurfaceCompressionCoverageLvm_IMPL NvU32 _gpuCacheAttr, _gpuP2PCacheAttr; NV_STATUS status = NV_OK; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams->pLegacyParams; OBJGPU *pGpu = pMemory->pGpu; - if (IS_VIRTUAL(pGpu)) - { - NV_RM_RPC_CONTROL(pRmCtrlParams->pGpu, pRmCtrlParams->hClient, - pRmCtrlParams->hObject, pRmCtrlParams->cmd, - pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); - return status; - } - if (pParams->hSubDevice) { Subdevice *pSubDevice; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c index a5f21602a3..86bfdeae6e 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -37,6 +37,8 @@ #include "mem_mgr/io_vaspace.h" #include "mem_mgr/virt_mem_mgr.h" #include "core/system.h" +#include "vgpu/vgpu_util.h" +#include "platform/sli/sli.h" #include "gpu/mem_mgr/virt_mem_allocator.h" @@ -147,6 +149,8 @@ static NV_STATUS _memdescSetSubAllocatorFlag if (pHeap == NULL) pHeap = memmgrGetDeviceSuballocator(GPU_GET_MEMORY_MANAGER(pGpu), bForceSubheap); + NV_ASSERT_OR_RETURN(pHeap != NULL, NV_ERR_INVALID_STATE); + if (pHeap->heapType == HEAP_TYPE_PHYS_MEM_SUBALLOCATOR) { NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &pMemDesc->gfid)); @@ -713,16 +717,14 @@ _memdescAllocVprRegion * @brief Allocate and populate the EGM array based off of the already * populated _pteArray of the memdesc * - * @param[in] pMemDesc Memory descriptor to allocate EGM array in - * @param[in] pMemoryManager Memory manager for EGM base addr + * @param[in] pMemDesc Memory descriptor to allocate EGM array in * * @returns NV_OK on successful allocation. NV_ERR if not. */ static NV_INLINE NV_STATUS _memdescAllocEgmArray ( - MEMORY_DESCRIPTOR *pMemDesc, - MemoryManager *pMemoryManager + MEMORY_DESCRIPTOR *pMemDesc ) { // @@ -732,6 +734,16 @@ _memdescAllocEgmArray NvU64 i; NvU64 pageCount = pMemDesc->PageCount + 1; + // + // Get the root memory descriptor's memory manager to be able to get the + // EGM base of that GPU, instead of the mapping GPU in the case of this + // array being used in a submemdesc. The submemdesc should always have the + // mapping of the root since it's a submemdesc derived from the root, and + // not based on the mapping GPU. + // + MEMORY_DESCRIPTOR *pRootMemDesc = memdescGetRootMemDesc(pMemDesc, NULL); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pRootMemDesc->pGpu); + if (pMemDesc->_flags & MEMDESC_FLAGS_PHYSICALLY_CONTIGUOUS) { pageCount = 1; @@ -796,8 +808,7 @@ _memdescAllocInternal if (memdescIsEgm(pMemDesc)) { NV_ASSERT_OK_OR_GOTO(status, - _memdescAllocEgmArray(pMemDesc, - GPU_GET_MEMORY_MANAGER(pGpu)), + _memdescAllocEgmArray(pMemDesc), done); } @@ -876,8 +887,6 @@ _memdescAllocInternal MEMORY_ALLOCATION_REQUEST allocRequest = {0}; NV_MEMORY_ALLOCATION_PARAMS allocData = {0}; MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); NvU64 requestedSize = pMemDesc->Size; allocRequest.pUserParams = &allocData; @@ -896,7 +905,7 @@ _memdescAllocInternal allocData.flags = NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE; // remove the "grows_down" flag when bReservedMemAtBottom is set so as to move RM memory to the bottom. - if (pMemorySystemConfig != NULL && !pMemorySystemConfig->bReservedMemAtBottom) + if (!pMemoryManager->bReservedMemAtBottom) { allocData.flags |= NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN; } @@ -1361,6 +1370,19 @@ memdescAlloc gpumgrSetBcEnabledStatus(pGpu, bcState); } + if ((status == NV_OK) && + IS_VIRTUAL_WITH_SRIOV(pGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && + (pMemDesc->_addressSpace == ADDR_SYSMEM) && + !(pMemDesc->_flags & MEMDESC_FLAGS_CPU_ONLY)) + { + status = vgpuUpdateSysmemPfnBitMap(pGpu, pMemDesc, NV_TRUE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update sysmem PFN bitmap, error 0x%x\n", status); + } + } + return status; subdeviceAlloc_failed: @@ -1626,6 +1648,20 @@ memdescFree * For sysmem not allocated by RM but only registered to it, we * would need to update the shared sysmem pfn bitmap here */ + if (pMemDesc->pGpu && IS_VIRTUAL_WITH_SRIOV(pMemDesc->pGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pMemDesc->pGpu) && + !(pMemDesc->_flags & MEMDESC_FLAGS_CPU_ONLY)) + { + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM) && + (pMemDesc->_addressSpace == ADDR_SYSMEM)) + { + NV_STATUS status = vgpuUpdateSysmemPfnBitMap(pMemDesc->pGpu, pMemDesc, NV_FALSE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update sysmem PFN bitmap\n"); + } + } + } return; } pMemDesc->Allocated--; @@ -1646,6 +1682,16 @@ memdescFree if (pMemDesc->_addressSpace == ADDR_SYSMEM) { + if (pMemDesc->pGpu && IS_VIRTUAL_WITH_SRIOV(pMemDesc->pGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pMemDesc->pGpu) && + !(pMemDesc->_flags & MEMDESC_FLAGS_CPU_ONLY)) + { + NV_STATUS status = vgpuUpdateSysmemPfnBitMap(pMemDesc->pGpu, pMemDesc, NV_FALSE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update sysmem PFN bitmap\n"); + } + } // The memdesc is being freed so destroy all of its IOMMU mappings. _memdescFreeIommuMappings(pMemDesc); } @@ -2003,6 +2049,7 @@ memdescUnmap switch (pMemDesc->_addressSpace) { case ADDR_SYSMEM: + case ADDR_EGM: { osUnmapSystemMemory(pMemDesc, Kernel, ProcessId, Address, Priv); break; @@ -2670,8 +2717,7 @@ memdescCreateSubMem if (memdescIsEgm(pMemDesc)) { NV_ASSERT_OK_OR_GOTO(status, - _memdescAllocEgmArray(pMemDescNew, - GPU_GET_MEMORY_MANAGER(pGpu)), + _memdescAllocEgmArray(pMemDescNew), fail); } } @@ -2718,8 +2764,7 @@ memdescCreateSubMem if (memdescIsEgm(pMemDesc)) { NV_ASSERT_OK_OR_GOTO(status, - _memdescAllocEgmArray(pMemDescNew, - GPU_GET_MEMORY_MANAGER(pGpu)), + _memdescAllocEgmArray(pMemDescNew), fail); } } @@ -4618,7 +4663,14 @@ memdescOverridePhysicalAddressWidthWindowsWAR NvU32 addressWidth ) { - return; + if (RMCFG_FEATURE_PLATFORM_WINDOWS) + { + if (addressWidth < gpuGetPhysAddrWidth_HAL(pGpu, ADDR_SYSMEM)) + { + pMemDesc->_flags |= MEMDESC_FLAGS_OVERRIDE_SYSTEM_ADDRESS_LIMIT; + pMemDesc->_overridenAddressWidth = addressWidth; + } + } } /*! @@ -4980,15 +5032,28 @@ memdescIsEgm MEMORY_DESCRIPTOR *pMemDesc ) { - NV_ADDRESS_SPACE addrSpace = memdescGetAddressSpace(pMemDesc); - MemoryManager *pMemoryManager; + NV_ADDRESS_SPACE addrSpace; + MEMORY_DESCRIPTOR *pRootMemDesc; + MemoryManager *pMemoryManager; + // + // If memdesc is not device owned, we can't tell if local EGM is enabled + // due to lack of memory manager. + // if (pMemDesc->pGpu == NULL) { return NV_FALSE; } - pMemoryManager = GPU_GET_MEMORY_MANAGER(pMemDesc->pGpu); + addrSpace = memdescGetAddressSpace(pMemDesc); + pRootMemDesc = memdescGetRootMemDesc(pMemDesc, NULL); + + if ((pRootMemDesc == NULL) || (pRootMemDesc->pGpu == NULL)) + { + return NV_FALSE; + } + + pMemoryManager = GPU_GET_MEMORY_MANAGER(pRootMemDesc->pGpu); if (pMemoryManager == NULL) { return NV_FALSE; @@ -4997,7 +5062,7 @@ memdescIsEgm if ((addrSpace == ADDR_EGM) || (memmgrIsLocalEgmEnabled(pMemoryManager) && (addrSpace == ADDR_SYSMEM) && - (memdescGetNumaNode(pMemDesc) != NV0000_CTRL_NO_NUMA_NODE))) + (memdescGetNumaNode(pMemDesc) == pMemoryManager->localEgmNodeId))) { return NV_TRUE; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mapper.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mapper.c index 91b7e131de..db27d85e87 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mapper.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mapper.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,240 @@ #include "gpu/mem_mgr/mem_mapper.h" #include "gpu/gpu.h" #include "os/os.h" +#include "core/locks.h" +#include "gpu/subdevice/subdevice.h" +#include "gpu/device/device.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/sem_surf.h" +#include "mem_mgr/vaspace.h" +#include "gpu/mem_mgr/virt_mem_allocator.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "mem_mgr/virtual_mem.h" +#include "mem_mgr/mem.h" +#include "rmapi/rs_utils.h" +#include "rmapi/mapping_list.h" +#include "containers/btree.h" + +#include "class/cl0080.h" +#include "class/cl2080.h" + +static NV_STATUS +memmapperExecuteMap +( + MemoryMapper *pMemoryMapper, + NV00FE_CTRL_OPERATION_MAP *pMap, + RM_API *pRmApi +) +{ + RsClient *pClient = RES_GET_CLIENT(pMemoryMapper); + + RsResourceRef *pVirtualResourceRef; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, clientGetResourceRef(pClient, pMap->hVirtualMemory, &pVirtualResourceRef)); + VirtualMemory *pVirtualMemory = dynamicCast(pVirtualResourceRef->pResource, VirtualMemory); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pVirtualMemory != NULL, NV_ERR_INVALID_ARGUMENT); + NvU64 baseVirtAddr = memdescGetPhysAddr(staticCast(pVirtualMemory, Memory)->pMemDesc, AT_GPU_VA, 0); + + NV_PRINTF(LEVEL_INFO, "map virt:(0x%x:0x%llx) phys:(0x%x:0x%llx) size:0x%llx dmaFlags:0x%x\n", + pMap->hVirtualMemory, pMap->virtualOffset, pMap->hPhysicalMemory, pMap->physicalOffset, + pMap->size, pMap->dmaFlags); + + NvU64 dmaOffset = baseVirtAddr + pMap->virtualOffset; + NvU64 newDmaOffset = dmaOffset; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Map(pRmApi, + RES_GET_CLIENT_HANDLE(pMemoryMapper), + RES_GET_PARENT_HANDLE(pMemoryMapper->pSubdevice), + pMap->hVirtualMemory, + pMap->hPhysicalMemory, + pMap->physicalOffset, + pMap->size, + pMap->dmaFlags | DRF_DEF(OS46, _FLAGS, _DMA_OFFSET_FIXED, _TRUE), + &newDmaOffset)); + NV_ASSERT_OR_RETURN(newDmaOffset == dmaOffset, NV_ERR_INVALID_STATE); + + return NV_OK; +} + +static NV_STATUS +memmapperExecuteUnmap +( + MemoryMapper *pMemoryMapper, + NV00FE_CTRL_OPERATION_UNMAP *pUnmap, + RM_API *pRmApi +) +{ + RsClient *pClient = RES_GET_CLIENT(pMemoryMapper); + + RsResourceRef *pVirtualResourceRef; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, clientGetResourceRef(pClient, pUnmap->hVirtualMemory, &pVirtualResourceRef)); + VirtualMemory *pVirtualMemory = dynamicCast(pVirtualResourceRef->pResource, VirtualMemory); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pVirtualMemory != NULL, NV_ERR_INVALID_ARGUMENT); + NvU64 baseVirtAddr = memdescGetPhysAddr(staticCast(pVirtualMemory, Memory)->pMemDesc, AT_GPU_VA, 0); + + NV_PRINTF(LEVEL_INFO, "unmap virt:(0x%x:0x%llx) size:0x%llx dmaFlags:0x%x\n", + pUnmap->hVirtualMemory, pUnmap->virtualOffset, pUnmap->size, pUnmap->dmaFlags); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Unmap(pRmApi, + RES_GET_CLIENT_HANDLE(pMemoryMapper), + RES_GET_PARENT_HANDLE(pMemoryMapper->pSubdevice), + pUnmap->hVirtualMemory, + pUnmap->dmaFlags, + baseVirtAddr + pUnmap->virtualOffset, + pUnmap->size)); + + return NV_OK; +} + +static NV_STATUS +memmapperExecuteSemaphoreWait +( + MemoryMapper *pMemoryMapper, + NV00FE_CTRL_OPERATION_SEMAPHORE *pWait +) +{ + NvU64 semVal = semsurfGetValue(pMemoryMapper->pSemSurf, pWait->index); + + NV_PRINTF(LEVEL_INFO, "wait index:0x%x val:0x%llx cur_var:0x%llx\n", + pWait->index, pWait->value, semVal); + + return (semVal >= pWait->value) ? NV_OK : NV_ERR_BUSY_RETRY; +} + +static NV_STATUS +memmapperExecuteSemaphoreSignal +( + MemoryMapper *pMemoryMapper, + NV00FE_CTRL_OPERATION_SEMAPHORE *pSignal, + RM_API *pRmApi +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(GPU_RES_GET_GPU(pMemoryMapper)); + NV_SEMAPHORE_SURFACE_CTRL_SET_VALUE_PARAMS params = {0}; + + params.index = pSignal->index; + params.newValue = pSignal->value; + + NV_PRINTF(LEVEL_INFO, "signal index:0x%x val:0x%llx\n", + pSignal->index, pSignal->value); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pMemoryManager->hClient, + pMemoryMapper->hInternalSemaphoreSurface, + NV_SEMAPHORE_SURFACE_CTRL_CMD_SET_VALUE, + ¶ms, + sizeof params)); + return NV_OK; +} + +static void +memmapperProcessWork +( + MemoryMapper *pMemoryMapper +) +{ + NV_PRINTF(LEVEL_INFO, "processing MemoryMapper work\n"); + + if (pMemoryMapper->bError) + { + NV_PRINTF(LEVEL_INFO, "return from MemoryMapper worker (error)\n"); + return; + } + + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + while (pMemoryMapper->operationQueueGet != pMemoryMapper->operationQueuePut) + { + NV00FE_CTRL_OPERATION *pOperation = &pMemoryMapper->pOperationQueue[pMemoryMapper->operationQueueGet]; + NV_STATUS status = NV_OK; + + switch (pOperation->type) + { + case NV00FE_CTRL_OPERATION_TYPE_NOP: + break; + case NV00FE_CTRL_OPERATION_TYPE_MAP: + NV_CHECK_OK(status, LEVEL_ERROR, memmapperExecuteMap(pMemoryMapper, &pOperation->data.map, pRmApi)); + break; + case NV00FE_CTRL_OPERATION_TYPE_UNMAP: + NV_CHECK_OK(status, LEVEL_ERROR, memmapperExecuteUnmap(pMemoryMapper, &pOperation->data.unmap, pRmApi)); + break; + case NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_WAIT: + status = memmapperExecuteSemaphoreWait(pMemoryMapper, &pOperation->data.semaphore); + NV_CHECK(LEVEL_ERROR, (status == NV_OK) || (status == NV_ERR_BUSY_RETRY)); + break; + case NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_SIGNAL: + status = memmapperExecuteSemaphoreSignal(pMemoryMapper, &pOperation->data.semaphore, pRmApi); + break; + default: + NV_CHECK_OK(status, LEVEL_ERROR, NV_ERR_INVALID_ARGUMENT); + break; + } + + if (status != NV_OK) + { + if (status != NV_ERR_BUSY_RETRY) + pMemoryMapper->bError = NV_TRUE; + break; + } + + pMemoryMapper->operationQueueGet = (pMemoryMapper->operationQueueGet + 1) % pMemoryMapper->operationQueueLen; + } + + NV_PRINTF(LEVEL_INFO, "return from MemoryMapper worker\n"); +} + +static void +memoryMapperWorker +( + NvU32 gpuInstance, + void *pArg +) +{ + MemoryMapperWorkerParams *pWorkerParams = pArg; + MemoryMapper *pMemoryMapper = pWorkerParams->pMemoryMapper; + + if (pMemoryMapper != NULL) + { + memmapperProcessWork(pMemoryMapper); + } + + if (--pWorkerParams->numRefs == 0) + { + portMemFree(pWorkerParams); + } +} + +static void +memoryMapperQueueWork +( + MemoryMapper *pMemoryMapper +) +{ + pMemoryMapper->pWorkerParams->numRefs++; + + // Queue work at passive IRQL + NV_ASSERT_OK(osQueueWorkItemWithFlags(GPU_RES_GET_GPU(pMemoryMapper), + memoryMapperWorker, + pMemoryMapper->pWorkerParams, + OS_QUEUE_WORKITEM_FLAGS_DONT_FREE_PARAMS + | OS_QUEUE_WORKITEM_FLAGS_FALLBACK_TO_DPC + | OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW + | OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW)); +} + +static void +memmapperSemaphoreEventCallback +( + void *pArg, + void *pData, + NvHandle hEvent, + NvU32 data, + NvU32 status +) +{ + memoryMapperQueueWork(pArg); +} NV_STATUS memmapperConstruct_IMPL @@ -33,16 +267,181 @@ memmapperConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - // if (!GPU_GET_DMA(GPU_RES_GET_GPU(pMemoryMapper))->bMemoryMapperApiEnabled) - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pMemoryMapper); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + RsResourceRef *pResourceRef = pCallContext->pResourceRef; + RsResourceRef *pParentRef = pResourceRef->pParentRef; + NV_MEMORY_MAPPER_ALLOCATION_PARAMS *pAllocParams = pParams->pAllocParams; + NV_STATUS status; + + if (!GPU_GET_DMA(pGpu)->bMemoryMapperApiEnabled) + return NV_ERR_NOT_SUPPORTED; + + pMemoryMapper->pSubdevice = dynamicCast(pParentRef->pResource, Subdevice); + NV_ASSERT_OR_RETURN(pMemoryMapper->pSubdevice != NULL, NV_ERR_INVALID_ARGUMENT); + + NV_ASSERT_OR_RETURN(pAllocParams->maxQueueSize != 0, NV_ERR_INVALID_ARGUMENT); + pMemoryMapper->operationQueueLen = pAllocParams->maxQueueSize; + pMemoryMapper->pOperationQueue = + portMemAllocNonPaged(pMemoryMapper->operationQueueLen * sizeof(*pMemoryMapper->pOperationQueue)); + NV_CHECK_TRUE_OR_GOTO(status, LEVEL_ERROR, pMemoryMapper->pOperationQueue != NULL, NV_ERR_NO_MEMORY, failed); + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + pRmApi->DupObject(pRmApi, + pMemoryManager->hClient, + pMemoryManager->hSubdevice, + &pMemoryMapper->hInternalSemaphoreSurface, + RES_GET_CLIENT_HANDLE(pMemoryMapper), + pAllocParams->hSemaphoreSurface, + NV04_DUP_HANDLE_FLAGS_NONE), + failed); + + RmClient *pInternalClient = serverutilGetClientUnderLock(pMemoryManager->hClient); + NV_ASSERT_TRUE_OR_GOTO(status, pInternalClient != NULL, NV_ERR_INVALID_STATE, failed); + RsClient *pInternalRsClient = staticCast(pInternalClient, RsClient); + RsResourceRef *pSemSurfRef; + NV_ASSERT_OK_OR_GOTO(status, + clientGetResourceRef(pInternalRsClient, pMemoryMapper->hInternalSemaphoreSurface, &pSemSurfRef), + failed); + pMemoryMapper->pSemSurf = dynamicCast(pSemSurfRef->pResource, SemaphoreSurface); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pMemoryMapper->pSemSurf != NULL, NV_ERR_INVALID_ARGUMENT); + + pMemoryMapper->pWorkerParams = portMemAllocNonPaged(sizeof(*pMemoryMapper->pWorkerParams)); + pMemoryMapper->pWorkerParams->pMemoryMapper = pMemoryMapper; + pMemoryMapper->pWorkerParams->numRefs = 1; + NV_CHECK_TRUE_OR_GOTO(status, LEVEL_ERROR, pMemoryMapper->pWorkerParams != NULL, NV_ERR_NO_MEMORY, failed); + + pMemoryMapper->semaphoreCallback.func = memmapperSemaphoreEventCallback; + pMemoryMapper->semaphoreCallback.arg = pMemoryMapper; + +failed: + if (status != NV_OK) + { + if (pMemoryMapper->hInternalSemaphoreSurface != NV01_NULL_OBJECT) + { + pRmApi->Free(pRmApi, pMemoryManager->hClient, pMemoryMapper->hInternalSemaphoreSurface); + } + + portMemFree(pMemoryMapper->pOperationQueue); + portMemFree(pMemoryMapper->pWorkerParams); + } + + return status; +} + +void +memmapperDestruct_IMPL +( + MemoryMapper *pMemoryMapper +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(GPU_RES_GET_GPU(pMemoryMapper)); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + pRmApi->Free(pRmApi, pMemoryManager->hClient, pMemoryMapper->hInternalSemaphoreSurface); + portMemFree(pMemoryMapper->pOperationQueue); + + pMemoryMapper->pWorkerParams->pMemoryMapper = NULL; + + if (--pMemoryMapper->pWorkerParams->numRefs == 0) + { + portMemFree(pMemoryMapper->pWorkerParams); + } +} + +static NV_STATUS +memmapperSubmitSemaphoreWait +( + MemoryMapper *pMemoryMapper, + NV00FE_CTRL_OPERATION_SEMAPHORE *pSemaphoreWait +) +{ + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(GPU_RES_GET_GPU(pMemoryMapper)); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_SEMAPHORE_SURFACE_CTRL_REGISTER_WAITER_PARAMS params = {0}; + params.index = pSemaphoreWait->index; + params.waitValue = pSemaphoreWait->value; + params.notificationHandle = (NvU64)&pMemoryMapper->semaphoreCallback; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pMemoryManager->hClient, + pMemoryMapper->hInternalSemaphoreSurface, + NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER, + ¶ms, + sizeof params)); + + return NV_OK; } NV_STATUS -memmapperCtrlCmdSubmitPagingOperations_IMPL +memmapperCtrlCmdSubmitOperations_IMPL ( - MemoryMapper *pMemoryMapper, - NV00FE_CTRL_SUBMIT_PAGING_OPERATIONS_PARAMS *pParams + MemoryMapper *pMemoryMapper, + NV00FE_CTRL_SUBMIT_OPERATIONS_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + NV00FE_CTRL_OPERATION *pOperataionsParams = pParams->pOperations; + NV_STATUS status = NV_OK; + NvU32 i; + + for (i = 0; i < pParams->operationsCount; i++) + { + NV_CHECK_OR_RETURN(LEVEL_ERROR, !pMemoryMapper->bError, NV_ERR_INVALID_STATE); + + NvU32 nextOperationQueuePut = (pMemoryMapper->operationQueuePut + 1) % pMemoryMapper->operationQueueLen; + + if (nextOperationQueuePut == pMemoryMapper->operationQueueGet) + { + status = NV_ERR_NOT_READY; + break; + } + + NV00FE_CTRL_OPERATION *pOperation = &pMemoryMapper->pOperationQueue[pMemoryMapper->operationQueuePut]; + NV00FE_CTRL_OPERATION *pOperationParams = &pOperataionsParams[i]; + + *pOperation = *pOperationParams; + + switch (pOperationParams->type) + { + case NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_WAIT: + NV_CHECK_TRUE_OR_GOTO(status, LEVEL_ERROR, + semsurfValidateIndex(pMemoryMapper->pSemSurf, pOperation->data.semaphore.index), + NV_ERR_INVALID_ARGUMENT, op_failed); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + memmapperSubmitSemaphoreWait(pMemoryMapper, &pOperation->data.semaphore), + op_failed); + break; + case NV00FE_CTRL_OPERATION_TYPE_SEMAPHORE_SIGNAL: + NV_CHECK_TRUE_OR_GOTO(status, LEVEL_ERROR, + semsurfValidateIndex(pMemoryMapper->pSemSurf, pOperation->data.semaphore.index), + NV_ERR_INVALID_ARGUMENT, op_failed); + break; + case NV00FE_CTRL_OPERATION_TYPE_MAP: + case NV00FE_CTRL_OPERATION_TYPE_UNMAP: + break; + case NV00FE_CTRL_OPERATION_TYPE_NOP: + default: + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, NV_ERR_INVALID_ARGUMENT, op_failed); + break; + } + +op_failed: + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "MemoryMapper encountered an error, not processing more commands.\n"); + pMemoryMapper->bError = NV_TRUE; + break; + } + + pMemoryMapper->operationQueuePut = nextOperationQueuePut; + } + + pParams->operationsProcessedCount = i; + + memoryMapperQueueWork(pMemoryMapper); + + return status; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c index 6bfc5233b6..a97f1bd787 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c @@ -32,6 +32,7 @@ #include "gpu/bus/kern_bus.h" #include "gpu/bif/kernel_bif.h" #include "core/locks.h" +#include "vgpu/vgpu_util.h" #include "virtualization/kernel_vgpu_mgr.h" #include "vgpu/rpc.h" #include "core/thread_state.h" @@ -49,6 +50,7 @@ #include "os/os.h" #include "gpu/gsp/kernel_gsp.h" #include "gpu/conf_compute/conf_compute.h" +#include "platform/sli/sli.h" #include "class/cl0050.h" @@ -232,7 +234,7 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) } } - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) + if (RMCFG_FEATURE_PLATFORM_WINDOWS && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) { pMemoryManager->bFbsrWddmModeEnabled = NV_TRUE; } @@ -256,25 +258,13 @@ _memmgrInitRegistryOverrides(OBJGPU *pGpu, MemoryManager *pMemoryManager) } } - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_ENABLE_ADDRTREE, &data32) == NV_OK) - { - if (data32 == NV_REG_STR_RM_ENABLE_ADDRTREE_YES) - { - pMemoryManager->bPmaAddrTree = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, "Enabled address tree for PMA via regkey.\n"); - } - } - else if (RMCFG_FEATURE_PLATFORM_MODS) - { - pMemoryManager->bPmaAddrTree = NV_TRUE; - NV_PRINTF(LEVEL_ERROR, "Enabled address tree for PMA for MODS.\n"); - } - if (osReadRegistryDword(pGpu, NV_REG_STR_DISABLE_GLOBAL_CE_UTILS, &data32) == NV_OK && data32 == NV_REG_STR_DISABLE_GLOBAL_CE_UTILS_YES) { pMemoryManager->bDisableGlobalCeUtils = NV_TRUE; } + + pMemoryManager->bCePhysicalVidmemAccessNotSupported = gpuIsSelfHosted(pGpu); } NV_STATUS @@ -284,7 +274,7 @@ memmgrStatePreInitLocked_IMPL MemoryManager *pMemoryManager ) { - if (IS_GSP_CLIENT(pGpu)) + if (IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu)) { // // Temporary hack to get OpenRM working without breaking SLI @@ -375,7 +365,7 @@ memmgrInitInternalChannels_IMPL pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB) || gpuIsCacheOnlyModeEnabled(pGpu) || (IS_VIRTUAL(pGpu) && !IS_VIRTUAL_WITH_FULL_SRIOV(pGpu)) || - IS_SIMULATION(pGpu) || + !IS_SILICON(pGpu) || IsDFPGA(pGpu)) { NV_PRINTF(LEVEL_INFO, "Skipping global CeUtils creation (unsupported platform)\n"); @@ -386,12 +376,12 @@ memmgrInitInternalChannels_IMPL if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU) || !memmgrIsPmaInitialized(pMemoryManager) || RMCFG_FEATURE_PLATFORM_GSP || - RMCFG_FEATURE_PLATFORM_WINDOWS || IS_MIG_ENABLED(pGpu) || gpuIsCCorApmFeatureEnabled(pGpu) || IsSLIEnabled(pGpu) || - NVCPU_IS_PPC64LE || - NVCPU_IS_AARCH64) + IsUnlinkedSLIEnabled(pGpu) || + gpuIsSelfHosted(pGpu) || + NVCPU_IS_PPC64LE) { // BUG 4167899: Temporarily skip CeUtils creation on platforms where it fails NV_PRINTF(LEVEL_INFO, "Skipping global CeUtils creation\n"); @@ -671,13 +661,13 @@ memmgrStatePreUnload_IMPL NV_ASSERT((flags & GPU_STATE_FLAGS_PRESERVING) || pMemoryManager->zbcSurfaces == 0); - if (flags & GPU_STATE_FLAGS_PRESERVING) + if ((flags & GPU_STATE_FLAGS_PRESERVING)) { // // fifo won't send a PreSchedulingDisable callback on StateUnload // destroy the channel manually, so that a CeUtils lite instance can be created for FBSR // - memmgrDestroyCeUtils(pMemoryManager, NV_TRUE); + memmgrDestroyCeUtils(pMemoryManager, !IS_VIRTUAL(pGpu)); } if (memmgrIsPmaEnabled(pMemoryManager) && @@ -720,8 +710,8 @@ memmgrStateDestroy_IMPL ) { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - Heap *pHeap = MEMORY_MANAGER_GET_HEAP(pMemoryManager); - NvU32 i; + Heap *pHeap = MEMORY_MANAGER_GET_HEAP(pMemoryManager); + NvU32 i; _memmgrFreeInternalClientObjects(pMemoryManager); @@ -826,13 +816,11 @@ memmgrCreateHeap_IMPL NvU64 rsvdSize; NvU64 size; NV_STATUS status = NV_OK; - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); // If we're using FB regions then rsvd memory is already marked as a reserved region if ((pMemoryManager->Ram.numFBRegions == 0) || (IS_VIRTUAL_WITH_SRIOV(pGpu))) { - if (pMemorySystemConfig->bReservedMemAtBottom) + if (pMemoryManager->bReservedMemAtBottom) { // rsvd memory is already accounted for in heapStart rsvdSize = 0; @@ -1129,6 +1117,18 @@ memmgrAllocHwResources_IMPL return NV_ERR_NO_MEMORY; } + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // we can skip the resource allocation step. + // + + if (IS_VIRTUAL(pGpu) && !vgpuIsGuestManagedHwAlloc(pGpu)) + { + pFbAllocInfo->pageFormat->flags |= NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC; + } + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) { NV_STATUS tempStatus; @@ -1174,6 +1174,11 @@ memmgrFreeHwResources_IMPL gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + if (IS_VIRTUAL(pGpu) && !vgpuIsGuestManagedHwAlloc(pGpu)) + { + pFbAllocInfo->pageFormat->flags |= NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC; + } + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) { NV_STATUS tempStatus; @@ -1244,7 +1249,7 @@ memmgrComprSupported_IMPL // Compression is allowed on vidmem or unified aperture (vidmem/sysmem is same w.r.t HW) isSupported = (gpuIsUnifiedMemorySpaceEnabled(pGpu) && pMemoryManager->bSysmemCompressionSupportDef); - NV_PRINTF(LEVEL_ERROR, "isSupported=%s\n", + NV_PRINTF(LEVEL_INFO, "isSupported=%s\n", isSupported ? "NV_TRUE" : "NV_FALSE"); } else @@ -1590,7 +1595,7 @@ memmgrSetPlatformPmaSupport_IMPL // KMD in WDDM mode will not support pma managed client page tables as // in both cases client / OS manges it. // - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) + if (RMCFG_FEATURE_PLATFORM_WINDOWS && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_TCC_MODE)) { memmgrSetClientPageTablesPmaManaged(pMemoryManager, NV_FALSE); } @@ -1600,7 +1605,7 @@ memmgrSetPlatformPmaSupport_IMPL // if (RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_MODS - || RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + || RMCFG_FEATURE_PLATFORM_WINDOWS) { pMemoryManager->bPmaSupportedOnPlatform = NV_TRUE; } @@ -2940,17 +2945,12 @@ memmgrPmaInitialize_IMPL { NV_PRINTF(LEVEL_INFO, "Initializing PMA with NUMA flag.\n"); pmaInitFlags |= PMA_INIT_NUMA; - } - if (gpuIsSelfHosted(pGpu)) - { - NV_PRINTF(LEVEL_INFO, "Initializing PMA with NUMA_AUTO_ONLINE flag.\n"); - pmaInitFlags |= PMA_INIT_NUMA_AUTO_ONLINE; - } - - if (memmgrIsPmaAddrTree(pMemoryManager)) - { - pmaInitFlags |= PMA_INIT_ADDRTREE; + if (gpuIsSelfHosted(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Initializing PMA with NUMA_AUTO_ONLINE flag.\n"); + pmaInitFlags |= PMA_INIT_NUMA_AUTO_ONLINE; + } } status = pmaInitialize(pPma, pmaInitFlags); @@ -2997,10 +2997,28 @@ memmgrInitFbRegions_IMPL { NV_ASSERT_OR_RETURN(pMemoryManager->Ram.numFBRegions == 0, NV_ERR_INVALID_STATE); - // Dont setup regions if FB is broken and we aren't using L2 cache as "FB". + // Don't setup regions if FB is broken and we aren't using L2 cache as "FB". if ((pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) && !gpuIsCacheOnlyModeEnabled(pGpu))) + { + // + // Bug 594534: Don't read/write in the FBIO/FBPA space when FB is broken. + // Indicate 32MB FB Memory instead, which is a bit of a hack since zero + // would be more accurate, but zero breaks things. + // + + // When ZeroFB + L2Cache mode is enabled, we'll set fbAddrSpaceSizeMb + // appropriately in memmgrInitBaseFbRegions_HAL. + if (!gpuIsCacheOnlyModeEnabled(pGpu)) + { + pMemoryManager->Ram.mapRamSizeMb = pMemoryManager->Ram.fbAddrSpaceSizeMb = 32; + NV_PRINTF(LEVEL_ERROR, + "Bug 594534: HACK: Report 32MB of framebuffer instead of reading registers.\n"); + + } + return NV_OK; + } NV_ASSERT_OK_OR_RETURN(memmgrInitBaseFbRegions_HAL(pGpu, pMemoryManager)); @@ -3012,7 +3030,7 @@ memmgrInitFbRegions_IMPL // memmgrRegenerateFbRegionPriority(pGpu, pMemoryManager); - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_WINDOWS) { if (pGpu->getProperty(pGpu, PDB_PROP_GPU_EXTERNAL_HEAP_CONTROL)) { @@ -3062,10 +3080,8 @@ memmgrPmaRegisterRegions_IMPL NvU32 blPageIndex; NvU32 blackListCount; NvU64 base, size; - NvU64 pmaTotalMemorySize = 0; NV_STATUS status = NV_OK; - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); blackListCount = pHeap->blackListAddresses.count; base = pHeap->base; @@ -3155,7 +3171,6 @@ memmgrPmaRegisterRegions_IMPL } } - pmaTotalMemorySize += (pmaRegion.limit - pmaRegion.base + 1); NV_PRINTF(LEVEL_INFO, "Register FB region %llx..%llx of size %llx with PMA\n", pmaRegion.base, pmaRegion.limit, @@ -3181,18 +3196,6 @@ memmgrPmaRegisterRegions_IMPL pmaRegionIdx++; } - if (gpuIsSelfHosted(pGpu) && osNumaOnliningEnabled(pGpu->pOsGpuInfo)) - { - // - // NUMA onlined memory size should not exceed memory size assigned to PMA. - // TODO : Currently in selfhosted and P9+GV100 systems numaOnlined size is less - // than PMA Memory Size. Ideally both of them should be identical. Bug 4051320. - // - NvU64 numaTotalSize = 0; - NvU64 numaFreeSize = 0; - osGetNumaMemoryUsage(pPma->numaNodeId, &numaFreeSize, &numaTotalSize); - NV_ASSERT_OR_RETURN(pmaTotalMemorySize >= numaTotalSize, NV_ERR_INVALID_STATE); - } // // bug #200354346, make sure the RM reserved region(s) are // scrubbed during the region creation itself. Top Down scrubber, @@ -3205,9 +3208,9 @@ memmgrPmaRegisterRegions_IMPL _pmaInitFailed: portMemFree(pBlacklistPages); - if ((status == NV_OK) && (pMemsysConfig->fbOverrideStartKb != 0)) + if ((status == NV_OK) && (pKernelMemorySystem->fbOverrideStartKb != 0)) { - NvU64 allocSize = NV_ALIGN_UP(((NvU64)pMemsysConfig->fbOverrideStartKb << 10), PMA_GRANULARITY); + NvU64 allocSize = NV_ALIGN_UP(((NvU64)pKernelMemorySystem->fbOverrideStartKb << 10), PMA_GRANULARITY); NvU32 numPages = (NvU32)(allocSize >> PMA_PAGE_SHIFT); PMA_ALLOCATION_OPTIONS allocOptions = {0}; @@ -3632,6 +3635,7 @@ memmgrStatePostLoad_IMPL { if (kbusReserveP2PPeerIds_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), NVBIT(pMemoryManager->localEgmPeerId)) == NV_OK) { + if (!IS_VIRTUAL_WITH_SRIOV(pGpu)) { NV2080_CTRL_INTERNAL_HSHUB_EGM_CONFIG_PARAMS params = { 0 }; RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); @@ -3692,7 +3696,11 @@ memmgrInitCeUtils_IMPL return NV_OK; } - ceUtilsParams.flags = bFifoLite ? DRF_DEF(0050_CEUTILS, _FLAGS, _FIFO_LITE, _TRUE) : 0; + if (bFifoLite) + ceUtilsParams.flags |= DRF_DEF(0050_CEUTILS, _FLAGS, _FIFO_LITE, _TRUE); + + if (pMemoryManager->bCePhysicalVidmemAccessNotSupported) + ceUtilsParams.flags |= DRF_DEF(0050_CEUTILS, _FLAGS, _VIRTUAL_MODE, _TRUE); NV_ASSERT_OK_OR_RETURN(objCreate(&pMemoryManager->pCeUtils, pMemoryManager, CeUtils, ENG_GET_GPU(pMemoryManager), NULL, &ceUtilsParams)); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c index 40ebe4e52f..5ebacabdd0 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c @@ -35,6 +35,7 @@ #include "gpu/subdevice/subdevice_diag.h" #include "ctrl/ctrl0080/ctrl0080fb.h" #include "core/locks.h" +#include "platform/sli/sli.h" #include "rmapi/rs_utils.h" #include "rmapi/mapping_list.h" #include "platform/chipset/chipset.h" @@ -119,7 +120,7 @@ memmgrGetDeviceCaps RMCTRL_SET_CAP(tempCaps, NV0080_CTRL_FB_CAPS, _DISABLE_PLC_GLOBALLY); } - if (pMemorySystemConfig->bDisablePlcForCertainOffsetsBug3046774) + if (pKernelMemorySystem->bDisablePlcForCertainOffsetsBug3046774) { RMCTRL_SET_CAP(tempCaps, NV0080_CTRL_FB_CAPS, _PLC_BUG_3046774); } @@ -249,6 +250,44 @@ deviceCtrlCmdFbGetCapsV2_IMPL return rmStatus; } +// +// deviceCtrlCmdSetDefaultVidmemPhysicality +// +// Lock Requirements: +// Assert that API lock held on entry +// +NV_STATUS +deviceCtrlCmdSetDefaultVidmemPhysicality_IMPL +( + Device *pDevice, + NV0080_CTRL_FB_SET_DEFAULT_VIDMEM_PHYSICALITY_PARAMS *pParams +) +{ + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + NvU32 override; + + switch (pParams->value) + { + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_DEFAULT: + override = NVOS32_ATTR_PHYSICALITY_DEFAULT; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_CONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_CONTIGUOUS; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_NONCONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS; + break; + case NV0080_CTRL_FB_DEFAULT_VIDMEM_PHYSICALITY_ALLOW_NONCONTIGUOUS: + override = NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS; + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + pDevice->defaultVidmemPhysicalityOverride = override; + + return NV_OK; +} + // // subdeviceCtrlCmdFbGetBar1Offset // diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c index ef879b0237..a565726df1 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c @@ -128,125 +128,3 @@ memmgrInitBaseFbRegions_FWCLIENT return NV_OK; } - -/*! - * @brief Set up CPU RM reserved memory space for physical carveout. - */ -NV_STATUS -memmgrPreInitReservedMemory_FWCLIENT -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager -) -{ - KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); - KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); - NvU64 tmpAddr = 0; - - if (pKernelDisplay) - { - // TODO: Determine the correct size of display instance memory - // via instmemGetSize_HAL(), as well as other parameters. - // I.e. refactor and leverage the code performing these tasks - // in memmgrPreInitReservedMemory_GM107() today. - tmpAddr += 0x10000; - } - - if (gpuIsSelfHosted(pGpu)) - { - // - // Reserve space for the test buffer used in coherent link test - // that is run early when memory allocation is not ready yet. - // - // if Self-Hosted is running in PCIe mode then this space will - // will not be used, this should not cause any issue - // - pKernelBus->coherentLinkTestBufferBase = tmpAddr; - tmpAddr += BUS_COHERENT_LINK_TEST_BUFFER_SIZE; - } - - // - // This has to be the very *last* thing in reserved memory as it - // will may grow past the 1MB reserved memory window. We cannot - // size it until memsysStateInitLockedHal_GK104. - // - memmgrReserveBar2BackingStore(pGpu, pMemoryManager, &tmpAddr); - - NV_ASSERT(NvU64_LO32(tmpAddr) == tmpAddr); - pMemoryManager->rsvdMemorySize = NvU64_LO32(tmpAddr); - - return NV_OK; -} - -/*! - * @brief Calculate the FB reserved memory requirement. - * - * @param[out] rsvdFastSize generic reserved RM memory needed in fast region - * @param[out] rsvdSlowSize generic reserved RM memory needed in slow region - * @param[out] rsvdISOSize ISO-specific reserved RM memory needed - */ -void -memmgrCalcReservedFbSpaceHal_FWCLIENT -( - OBJGPU *pGpu, - MemoryManager *pMemoryManager, - NvU64 *rsvdFastSize, - NvU64 *rsvdSlowSize, - NvU64 *rsvdISOSize -) -{ - KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); - KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - NvU64 rsvdSizeBytes; - NvU64 smallPagePte = 0; - NvU64 bigPagePte = 0; - - // - // Minimum reserved memory for driver internal memdescAlloc() calls. - // DO NOT increase this hard-coded memory to account for more reserved - // FB memory, instead add individual calculations below. - // - rsvdSizeBytes = 5 * 1024 * 1024; - - // Add in USERD reservation - rsvdSizeBytes += memmgrGetUserdReservedFbSpace_HAL(pGpu, pMemoryManager); - - // Reserve FB for Fault method buffers - rsvdSizeBytes += kfifoCalcTotalSizeOfFaultMethodBuffers_HAL(pGpu, pKernelFifo, NV_TRUE); - - // smallPagePte = FBSize /4k * 8 (Small page PTE for whole FB) - smallPagePte = NV_ROUNDUP((pMemoryManager->Ram.fbUsableMemSize / FERMI_SMALL_PAGESIZE) * 8, RM_PAGE_SIZE); - - // bigPagePte = FBSize /bigPageSize * 8 (Big page PTE for whole FB) - bigPagePte = NV_ROUNDUP((pMemoryManager->Ram.fbUsableMemSize/ (kgmmuGetMaxBigPageSize_HAL(pKernelGmmu))) * 8, - RM_PAGE_SIZE); - - rsvdSizeBytes += smallPagePte; - rsvdSizeBytes += bigPagePte; - - if (gpuIsClientRmAllocatedCtxBufferEnabled(pGpu)) - { - rsvdSizeBytes += memmgrGetMaxContextSize_HAL(pGpu, pMemoryManager); - } - - // Add in NV_REG_STR_RM_INCREASE_RSVD_MEMORY_SIZE_MB if applicable - if (pMemoryManager->rsvdMemorySizeIncrement != 0) - { - // Allow reservation up to half of usable FB size - if (pMemoryManager->rsvdMemorySizeIncrement > (pMemoryManager->Ram.fbUsableMemSize / 2)) - { - pMemoryManager->rsvdMemorySizeIncrement = pMemoryManager->Ram.fbUsableMemSize / 2; - NV_PRINTF(LEVEL_ERROR, - "RM can only increase reserved heap by 0x%llx bytes\n", - pMemoryManager->rsvdMemorySizeIncrement); - } - rsvdSizeBytes += pMemoryManager->rsvdMemorySizeIncrement; - } - - rsvdSizeBytes = NV_ROUNDUP(rsvdSizeBytes, RM_PAGE_SIZE_64K); - - // mixed memory type/density only existed in pre-Pascal chips - *rsvdFastSize = rsvdSizeBytes; - *rsvdSlowSize = 0; - *rsvdISOSize = 0; -} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c index 5928ccf507..fd1f84e129 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c @@ -374,7 +374,6 @@ _memmgrAllocFbsrReservedRanges ADDR_FBMEM, pKernelGsp->pWprMeta->vgaWorkspaceOffset, pKernelGsp->pWprMeta->vgaWorkspaceSize); - } // Allocate Vid Mem descriptor for RM INSTANCE memory, specific to VGA i.e. after BAR2PTE to end. else @@ -664,25 +663,19 @@ memmgrAddMemNodes_IMPL // content of memory descriptor, remove MEMDESC_FLAGS_LOST_ON_SUSPEND // flag. // - if (pAllocMemDesc != NULL) + if (block->owner != NVOS32_BLOCK_TYPE_FREE && pAllocMemDesc != NULL) { - // - // Save RM_RESERVED_REGION if it is not GSP managed FB region and - // - bSaveRmAllocations true or - // - MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND is set + if (memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND)) + { + bSaveNode = NV_TRUE; + } // TODO: Use LOST_ON_SUSPEND flag to skip GSP managed FB regions - // - if ((block->owner == HEAP_OWNER_RM_RESERVED_REGION) && + else if ((block->owner == HEAP_OWNER_RM_RESERVED_REGION) && !memmgrIsGspOwnedMemory_HAL(pGpu, pMemoryManager, pAllocMemDesc)) { - if (bSaveAllRmAllocations || memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND)) + if (bSaveAllRmAllocations) bSaveNode = NV_TRUE; } - // - // Save RM_CHANNEL_CTX_BUFFER or RM_KERNEL_CLIENT regions if - // - bSaveRmAllocations true or - // - MEMDESC_FLAGS_PRESERVE_LOST_ON_SUSPEND is not set - // else if ((block->owner == HEAP_OWNER_RM_CHANNEL_CTX_BUFFER) || (block->owner == HEAP_OWNER_RM_KERNEL_CLIENT)) { if (bSaveAllRmAllocations || (!memdescGetFlag(pAllocMemDesc, MEMDESC_FLAGS_LOST_ON_SUSPEND))) diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c index b47f84b894..f1520f214d 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_regions.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ +#include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/heap.h" @@ -407,6 +408,27 @@ memmgrRegionSetupCommon_IMPL for (i = 0; i < pMemoryManager->Ram.numFBRegions; i++) { + // + // In NUMA systems unreserved FB memory Block is onlined to the + // kernel after aligning to memblock size. If we have leftover + // memory after the alignment this memory will just be unused. + // Hence adding this memory to the reserved heap to avoid + // assigning unused memory later to PMA and to keep both the + // NUMA size and the PMA size same. + // + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo) && + (pMemoryManager->Ram.fbRegion[i].bRsvdRegion == NV_FALSE) && + (pMemoryManager->Ram.fbRegion[i].bInternalHeap == NV_FALSE)) + { + NvU64 unusedBlockSize = 0; + NvU64 memblockSize = 0; + NvU64 regionSize = pMemoryManager->Ram.fbRegion[i].limit - pMemoryManager->Ram.fbRegion[i].base + 1; + NvU64 usableBlockSize = regionSize - pMemoryManager->Ram.fbRegion[i].rsvdSize; + + NV_ASSERT_OR_RETURN_VOID(osNumaMemblockSize(&memblockSize) == NV_OK); + unusedBlockSize = usableBlockSize - NV_ALIGN_DOWN64(usableBlockSize, memblockSize); + pMemoryManager->Ram.fbRegion[i].rsvdSize += unusedBlockSize; + } // // if the region has an RM reserved block and is not already reserved, subdivide it. // diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_vgpu.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_vgpu.c new file mode 100644 index 0000000000..8d68ac22e8 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr_vgpu.c @@ -0,0 +1,135 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/gpu.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "vgpu/vgpu_events.h" + +/*! + * @@brief get FB tax size + * + * @returns fb tax size + */ +NvU64 +memmgrGetFbTaxSize_VGPUSTUB +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + NvU64 ret = 0; + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + if (pVSI) + ret = pVSI->fbTaxLength; + + return ret; +} + +/*! + * @brief Fill in FB region information. + */ +NV_STATUS +memmgrInitBaseFbRegions_VGPUSTUB +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + if (pVSI->fbRegionInfoParams.numFBRegions == 0) + { + NV_PRINTF(LEVEL_ERROR, "Invalid number of FB regions (%d)\n", + pVSI->fbRegionInfoParams.numFBRegions); + NV_ASSERT(0); + return NV_ERR_INVALID_PARAMETER; + } + + if (pVSI->fbRegionInfoParams.numFBRegions > 1) + { + // mixed density FB mem is not yet supported on vGPU + NV_ASSERT(0); + NV_PRINTF(LEVEL_ERROR, + "Mixed density FB regions not supported (%d)\n", + pVSI->fbRegionInfoParams.numFBRegions); + + return NV_ERR_INVALID_PARAMETER; + } + + pMemoryManager->Ram.fbRegion[0].base = 0; + pMemoryManager->Ram.fbRegion[0].limit = pVSI->fbLength - 1; + pMemoryManager->Ram.fbRegion[0].rsvdSize = 0; + pMemoryManager->Ram.fbRegion[0].bRsvdRegion = NV_FALSE; + pMemoryManager->Ram.fbRegion[0].performance = pVSI->fbRegionInfoParams.fbRegion[0].performance; + pMemoryManager->Ram.fbRegion[0].bSupportCompressed = pVSI->fbRegionInfoParams.fbRegion[0].supportCompressed; + pMemoryManager->Ram.fbRegion[0].bSupportISO = pVSI->fbRegionInfoParams.fbRegion[0].supportISO; + pMemoryManager->Ram.fbRegion[0].bProtected = pVSI->fbRegionInfoParams.fbRegion[0].bProtected; + + pMemoryManager->Ram.fbUsableMemSize = pMemoryManager->Ram.fbRegion[0].limit - pMemoryManager->Ram.fbRegion[0].base + 1; + + NV_PRINTF(LEVEL_INFO, + "FB Region 0 : %x'%08x - %x'%08x perf = %d rsvd = %s ISO = %s internal = %s\n", + NvU64_HI32(pMemoryManager->Ram.fbRegion[0].base), + NvU64_LO32(pMemoryManager->Ram.fbRegion[0].base), + NvU64_HI32(pMemoryManager->Ram.fbRegion[0].limit), + NvU64_LO32(pMemoryManager->Ram.fbRegion[0].limit), + pMemoryManager->Ram.fbRegion[0].performance, + pMemoryManager->Ram.fbRegion[0].bRsvdRegion ? "NV_TRUE" : "NV_FALSE", + pMemoryManager->Ram.fbRegion[0].bSupportISO ? "NV_TRUE" : "NV_FALSE", + pMemoryManager->Ram.fbRegion[0].bInternalHeap ? "NV_TRUE" : "NV_FALSE"); + + pMemoryManager->Ram.numFBRegions = pVSI->fbRegionInfoParams.numFBRegions; + pMemoryManager->Ram.fbTotalMemSizeMb = (pMemoryManager->Ram.fbUsableMemSize) >> 20; + pMemoryManager->Ram.fbAddrSpaceSizeMb = (pMemoryManager->Ram.fbRegion[pMemoryManager->Ram.numFBRegions - 1].limit + 1) >> 20; + + NV_PRINTF(LEVEL_INFO, + "FB Reserved Memory = %x'%08x FB Usable Memory = %x'%08x FB Address " + "Space (MB) = %x'%08x\n", + NvU64_HI32(pMemoryManager->Ram.reservedMemSize), + NvU64_LO32(pMemoryManager->Ram.reservedMemSize), + NvU64_HI32(pMemoryManager->Ram.fbUsableMemSize), + NvU64_LO32(pMemoryManager->Ram.fbUsableMemSize), + NvU64_HI32(pMemoryManager->Ram.fbAddrSpaceSizeMb), + NvU64_LO32(pMemoryManager->Ram.fbAddrSpaceSizeMb)); + + return NV_OK; +} + +/*! + * @brief Get the required heap space for GR module + */ +NvU32 +memmgrGetGrHeapReservationSize_VGPUSTUB +( + OBJGPU *pGpu, + MemoryManager *pMemoryManager +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN((pVSI != NULL), 0); + + return pVSI->grBufferSize[RPC_GR_BUFFER_TYPE_GRAPHICS_ATTRIBUTE_CB]; +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c index 0ec5ec1268..441ea3dcbf 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_scrub.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c index dedb7d16e8..243895df4f 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c @@ -94,7 +94,8 @@ memmgrGetMemTransferType // transferType = TRANSFER_TYPE_PROCESSOR; } - else if (kbusIsBarAccessBlocked(pKernelBus)) + else if (kbusIsBarAccessBlocked(pKernelBus) && + (!gpuIsCCDevToolsModeEnabled(pGpu) || !(flags & TRANSFER_FLAGS_PREFER_PROCESSOR))) { transferType = TRANSFER_TYPE_GSP_DMA; } @@ -102,6 +103,22 @@ memmgrGetMemTransferType return transferType; } +static NV_STATUS +memmgrCheckSurfaceBounds +( + TRANSFER_SURFACE *pSurface, + NvU64 size +) +{ + NV_ASSERT_OR_RETURN(pSurface != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pSurface->pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(size != 0, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pSurface->offset <= pSurface->pMemDesc->Size, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pSurface->offset + size <= pSurface->pMemDesc->Size, NV_ERR_INVALID_ARGUMENT); + + return NV_OK; +} + static NV_STATUS _memmgrAllocAndMapSurface ( @@ -125,7 +142,7 @@ _memmgrAllocAndMapSurface memdescCreate(ppMemDesc, pGpu, size, RM_PAGE_SIZE, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED, flags)); - memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_77, + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_77, (*ppMemDesc)); NV_ASSERT_OK_OR_GOTO(status, status, failed); @@ -189,12 +206,6 @@ _memmgrMemReadOrWriteWithGsp void *pStagingBufPriv = NULL; RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); - if (gpuIsCCFeatureEnabled(pGpu)) - { - NV_ASSERT_OR_RETURN(pConfCompute->getProperty(pCC, - PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED), - NV_ERR_INVALID_STATE); - } // Do not expect GSP to be used for reading/writing from/to sysmem if (memdescGetAddressSpace(pDst->pMemDesc) == ADDR_SYSMEM) @@ -213,10 +224,18 @@ _memmgrMemReadOrWriteWithGsp { if (gpuIsCCFeatureEnabled(pGpu)) { - NV_ASSERT_OK_OR_GOTO(status, - ccslEncrypt_HAL(pConfCompute->pDmaCcslCtx, size, pBuf, NULL, 0, - pStagingBufMap, gspParams.authTag), - failed); + status = ccslEncrypt_HAL(pConfCompute->pDmaCcslCtx, size, pBuf, NULL, 0, + pStagingBufMap, gspParams.authTag); + if (status != NV_OK) + { + if (status == NV_ERR_INSUFFICIENT_RESOURCES) + { + // We hit potential IV overflow, this is fatal. + NV_PRINTF(LEVEL_ERROR, "Fatal error detected in GSP-DMA encrypt: IV Overflow!\n"); + confComputeSetErrorState(pGpu, pConfCompute); + } + goto failed; + } } else { @@ -275,10 +294,15 @@ _memmgrMemReadOrWriteWithGsp { if (gpuIsCCFeatureEnabled(pGpu)) { - NV_ASSERT_OK_OR_GOTO(status, - ccslDecrypt_HAL(pConfCompute->pDmaCcslCtx, size, pStagingBufMap, - NULL, NULL, 0, pBuf, gspParams.authTag), - failed); + status = ccslDecrypt_HAL(pConfCompute->pDmaCcslCtx, size, pStagingBufMap, + NULL, NULL, 0, pBuf, gspParams.authTag); + if (status != NV_OK) + { + // Failure in GSP-DMA decrypt is considered fatal. + NV_PRINTF(LEVEL_ERROR, "Fatal error detected in GSP-DMA decrypt: 0x%x!\n", status); + confComputeSetErrorState(pGpu, pConfCompute); + goto failed; + } } else { @@ -316,6 +340,7 @@ _memmgrMemcpyWithGsp NvU8 *pMap = NULL; void *pPriv = NULL; RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); // // Do not expect GSP to be used for copying data b/w two surfaces @@ -347,10 +372,29 @@ _memmgrMemcpyWithGsp NV_PROTECT_READ_WRITE, (void**)&pMap, &pPriv), failed); - // Copy to staging buffer - portMemCopy(pStagingBufMap, size, pMap + pSrc->offset, size); + // Copy to staging buffer, encrypting first if CC mode + if (gpuIsCCFeatureEnabled(pGpu)) + { + status = ccslEncrypt_HAL(pConfCompute->pDmaCcslCtx, size, pMap + pSrc->offset, + NULL, 0, pStagingBufMap, gspParams.authTag); + if (status == NV_ERR_INSUFFICIENT_RESOURCES) + { + // + // We hit potential IV overflow, this is fatal. + // Status is checked below, make sure we unmap memory first. + // + NV_PRINTF(LEVEL_ERROR, "Fatal error detected in GSP-DMA encrypt: IV Overflow!\n"); + confComputeSetErrorState(pGpu, pConfCompute); + } + } + else + { + portMemCopy(pStagingBufMap, size, pMap + pSrc->offset, size); + } + // Be sure to unmap memory before potentially taking cleanup path memdescUnmapOld(pSrc->pMemDesc, NV_TRUE, 0, (void*)pMap, pPriv); + NV_ASSERT_OK_OR_GOTO(status, status, failed); // Source surface in unprotected sysmem gspParams.src.baseAddr = memdescGetPhysAddr(pStagingBuf, AT_GPU, 0); @@ -413,9 +457,29 @@ _memmgrMemcpyWithGsp NV_PROTECT_READ_WRITE, (void**)&pMap, &pPriv), failed); - portMemCopy(pMap + pDst->offset, size, pStagingBufMap, size); + if (gpuIsCCFeatureEnabled(pGpu)) + { + status = ccslDecrypt_HAL(pConfCompute->pDmaCcslCtx, size, pStagingBufMap, + NULL, NULL, 0, pMap + pDst->offset, gspParams.authTag); + if (status != NV_OK) + { + // + // Failure in GSP-DMA decrypt is considered fatal. + // Just print and set fatal state here, status is checked below after + // unmappin memory. + // + NV_PRINTF(LEVEL_ERROR, "Fatal error detected in GSP-DMA decrypt: 0x%x!\n", status); + confComputeSetErrorState(pGpu, pConfCompute); + } + } + else + { + portMemCopy(pMap + pDst->offset, size, pStagingBufMap, size); + } + // Be sure to unmap memory before potentially taking cleanup path memdescUnmapOld(pDst->pMemDesc, NV_TRUE, 0, (void*)pMap, pPriv); + NV_ASSERT_OK_OR_GOTO(status, status, failed); } failed: @@ -489,10 +553,8 @@ memmgrMemCopyWithTransferType NvU8 *pDst; // Sanitize the input - NV_ASSERT_OR_RETURN(pDstInfo != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pSrcInfo != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pDstInfo->pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pSrcInfo->pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(memmgrCheckSurfaceBounds(pDstInfo, size)); + NV_ASSERT_OK_OR_RETURN(memmgrCheckSurfaceBounds(pSrcInfo, size)); NV_ASSERT_OR_RETURN(!memdescDescIsEqual(pDstInfo->pMemDesc, pSrcInfo->pMemDesc), NV_ERR_INVALID_ARGUMENT); @@ -618,10 +680,7 @@ memmgrMemSetWithTransferType NvU8 *pDst; // Sanitize the input - NV_ASSERT_OR_RETURN(pDstInfo != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pDstInfo->pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(size > 0, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pDstInfo->offset + size <= pDstInfo->pMemDesc->Size, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(memmgrCheckSurfaceBounds(pDstInfo, size)); switch (transferType) { @@ -779,11 +838,8 @@ memmgrMemWriteWithTransferType OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); // Sanitize the input - NV_ASSERT_OR_RETURN(pDstInfo != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pDstInfo->pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(memmgrCheckSurfaceBounds(pDstInfo, size)); NV_ASSERT_OR_RETURN(pBuf != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(size > 0, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pDstInfo->offset + size <= pDstInfo->pMemDesc->Size, NV_ERR_INVALID_ARGUMENT); if (pMapping != NULL) { @@ -854,11 +910,8 @@ memmgrMemReadWithTransferType // Sanitize the input - NV_ASSERT_OR_RETURN(pSrcInfo != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pSrcInfo->pMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OK_OR_RETURN(memmgrCheckSurfaceBounds(pSrcInfo, size)); NV_ASSERT_OR_RETURN(pBuf != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(size > 0, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pSrcInfo->offset + size <= pSrcInfo->pMemDesc->Size, NV_ERR_INVALID_ARGUMENT); if (pMapping != NULL) { @@ -1173,14 +1226,11 @@ memmgrMemBeginTransfer_IMPL NvU64 offset = pTransferInfo->offset; OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); NvU8 *pPtr = NULL; - NvU64 memSz = 0; + NvU64 memSz = shadowBufSize; - NV_ASSERT_OR_RETURN(pMemDesc != NULL, NULL); - NV_ASSERT_OR_RETURN((memSz = memdescGetSize(pMemDesc)) >= shadowBufSize, NULL); + NV_ASSERT_OR_RETURN(memmgrCheckSurfaceBounds(pTransferInfo, memSz) == NV_OK, NULL); NV_ASSERT_OR_RETURN(memdescGetKernelMapping(pMemDesc) == NULL, NULL); - memSz = shadowBufSize == 0 ? memSz : shadowBufSize; - switch (transferType) { case TRANSFER_TYPE_PROCESSOR: @@ -1246,16 +1296,13 @@ memmgrMemEndTransfer_IMPL TRANSFER_TYPE transferType = memmgrGetMemTransferType(pMemoryManager, pTransferInfo, NULL, flags); MEMORY_DESCRIPTOR *pMemDesc = pTransferInfo->pMemDesc; - NvU64 offset = pTransferInfo->offset; OBJGPU *pGpu = ENG_GET_GPU(pMemoryManager); - NvU64 memSz = 0; NvU8 *pMapping = NULL; + NvU64 memSz = shadowBufSize; - NV_ASSERT_OR_RETURN_VOID(pMemDesc != NULL); - pMapping = memdescGetKernelMapping(pMemDesc); + NV_ASSERT_OR_RETURN_VOID(memmgrCheckSurfaceBounds(pTransferInfo, memSz) == NV_OK); - NV_ASSERT_OR_RETURN_VOID((memSz = memdescGetSize(pMemDesc)) >= (shadowBufSize + offset) ); - memSz = shadowBufSize == 0 ? memSz : shadowBufSize; + pMapping = memdescGetKernelMapping(pMemDesc); memdescSetKernelMapping(pMemDesc, NULL); @@ -1553,6 +1600,11 @@ memUtilsAllocMemDesc { NvU64 memDescFlags = MEMDESC_FLAGS_SKIP_RESOURCE_COMPUTE; + if (FLD_TEST_DRF(OS32, _ATTR2, _USE_EGM, _TRUE, pFbAllocInfo->retAttr2)) + { + memDescFlags |= MEMDESC_FLAGS_ALLOC_FROM_EGM; + } + // // Allocate a contig vidmem descriptor now; if needed we'll // allocate a new noncontig memdesc later diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c index e4db3fe971..372952c544 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/method_notification.c @@ -38,6 +38,7 @@ #include "gpu/device/device.h" #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/mem_mgr.h" +#include "platform/sli/sli.h" //--------------------------------------------------------------------------- // diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c deleted file mode 100644 index 56e59e825a..0000000000 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c +++ /dev/null @@ -1,2181 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/*! - * @file addrtree.c - */ - -#include "gpu/mem_mgr/phys_mem_allocator/addrtree.h" -#include "gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h" -#include "utils/nvprintf.h" -#include "utils/nvassert.h" -#include "nvport/nvport.h" -#include "nvmisc.h" - -// Returns if (x, x+y-1) contains (u, u+v-1) in one dimention -#define RANGE_CONTAINS(x, y, u, v) ((x <= u) && ((x + y - 1) >= (u + v - 1))) - -static PMA_PAGESTATUS pmaAddrtreeReadLevel(void *pMap, NvU32 levelNum, NvU64 frameNum, NvBool bReadAttrib); -static void _addrtreeUpdateAncestors(PMA_ADDRTREE *pTree, ADDRTREE_NODE *pNode, PMA_PAGESTATUS newStateMask); -static void _addrtreeConvertLevelFrameToNodeIndex(PMA_ADDRTREE *pTree, NvU32 levelNum, NvU64 frameNum, - ADDRTREE_NODE **ppNode, NvU32 *pIndex); -PMA_PAGESTATUS _pmaAddrtreeReadLevelAndSkipUnavailable(void *pMap, NvU32 levelNum, NvU64 frameNum, - PMA_PAGESTATUS searchState, NvBool bAllowFree, - NvU64 *pNumFramesToSkip, NvBool bReverse); - -static NvU64 alignUpToMod(NvU64 frame, NvU64 alignment, NvU64 mod) -{ - if ((frame & (alignment - 1)) <= mod) - return NV_ALIGN_DOWN(frame, alignment) + mod; - else - return NV_ALIGN_UP(frame, alignment) + mod; -} - -static NvU32 -addrtreeGetTreeLevel(NvU64 pageSize) -{ - NvU32 level = 0; - switch (pageSize) - { - case _PMA_64KB: level = 5; break; - // 128KB is supported in wrapper routines - case _PMA_2MB: level = 4; break; - case _PMA_512MB: level = 2; break; - default: break; - } - - NV_ASSERT(level != 0); - return level; -} - -static void -pmaAddrtreePrintLevel(ADDRTREE_LEVEL *pLevel) -{ - NvU32 i; - NvU32 mapIndex = MAP_IDX_ALLOC_PIN; - ADDRTREE_NODE *pNode = NULL; - - for (i = 0; i < pLevel->nodeCount; i++) - { - pNode = &pLevel->pNodeList[i]; - NV_PRINTF(LEVEL_INFO, "S[%d]=0x%llx A[%d]=0x%llx\n", i, - pNode->seeChild[mapIndex], i, pNode->state[mapIndex]); - - // In case compiler complains when the above print is compiled out - (void)pNode; - (void)mapIndex; - } -} - -void pmaAddrtreePrintTree(void *pMap, const char* str) -{ - NvU32 i; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - NV_PRINTF(LEVEL_INFO, "%s ==== \n", str); - - for (i = 0; i < pTree->levelCount - 1; i++) - { - NV_PRINTF(LEVEL_INFO, "Level [%d]\n", i); - pmaAddrtreePrintLevel(&pTree->levels[i]); - } - NV_PRINTF(LEVEL_INFO, "END printing Tree ==== \n"); -} - -static NvU64 -_makeMaskUpToIndex(NvU32 index) -{ - NV_ASSERT(index <= 64); - if (index == 64) - { - return NV_U64_MAX; - } - else - { - return (1ULL << index) - 1; - } -} - -void * -pmaAddrtreeInit -( - NvU64 numFrames, - NvU64 addrBase, - PMA_STATS *pPmaStats, - NvBool bProtected -) -{ - // - // Hardcoding this for now to get things started - // TODO: use more flexible configs - // - NvU32 levelSizes[] = {_TREE_2TB, _TREE_32GB, _TREE_512MB, _TREE_128MB, _TREE_2MB, _TREE_64KB}; - NvU32 levelCount = sizeof(levelSizes) / sizeof(levelSizes[0]); - //NV_PRINTF(LEVEL_INFO, "numFrames: 0x%llx, addrBase 0x%llx \n", numFrames, addrBase); - - NvU64 totalNodeCount, num2mbPages; - NvU32 i; - PMA_ADDRTREE *newTree; - NvU64 numFramesToAllocate; - - // PMA already ensures this - NV_ASSERT(NV_IS_ALIGNED(addrBase, PMA_GRANULARITY)); - - newTree = (PMA_ADDRTREE*)portMemAllocNonPaged((NvLength)sizeof(struct pma_addrtree)); - if (newTree == NULL) - { - return NULL; - } - portMemSet(newTree, 0, (NvLength)sizeof(*newTree)); - newTree->levels = NULL; - newTree->root = NULL; - - // Allocate the levels - newTree->levels = (ADDRTREE_LEVEL *)portMemAllocNonPaged((NvLength)(levelCount * sizeof(ADDRTREE_LEVEL))); - if (newTree->levels == NULL) - { - goto error; - } - portMemSet(newTree->levels, 0, (NvLength)(levelCount * sizeof(ADDRTREE_LEVEL))); - - newTree->levelCount = levelCount; - newTree->totalFrames = numFrames; - num2mbPages = numFrames / (_PMA_2MB >> PMA_PAGE_SHIFT); - - pPmaStats->numFreeFrames += newTree->totalFrames; - pPmaStats->num2mbPages += num2mbPages; - pPmaStats->numFree2mbPages += num2mbPages; - - if (bProtected) - { - pPmaStats->numFreeFramesProtected += newTree->totalFrames; - pPmaStats->num2mbPagesProtected += num2mbPages; - pPmaStats->numFree2mbPagesProtected += num2mbPages; - } - - newTree->bProtected = bProtected; - newTree->pPmaStats = pPmaStats; - - // - // Now pad the beginning of addrtree, and round down to the largest - // single page allocation supported so that its level will be aligned. - // The biggest single page is 512 MB currently. - // - newTree->numPaddingFrames = (addrBase - NV_ALIGN_DOWN64(addrBase, _PMA_512MB)) >> PMA_PAGE_SHIFT; - numFramesToAllocate = newTree->totalFrames + newTree->numPaddingFrames; - - // Allocate each level and calculate number of nodes needed - totalNodeCount = 0; - for (i = 0; i < levelCount; i++) - { - ADDRTREE_LEVEL *cur = &newTree->levels[i]; - cur->nodeCount = numFramesToAllocate >> (levelSizes[i] - PMA_PAGE_SHIFT); - cur->pageSizeShift = levelSizes[i]; - - // To be a tree, there needs to be one root node - if (i == 0 && cur->nodeCount != 0) - { - NV_PRINTF(LEVEL_ERROR, "Total memory is > 2TB. PMA Address Tree cannot account for this much.\n"); - goto error; - } - - // The 64KB level is a placeholder level which doesn't need to be allocated - if (i == levelCount - 1) - { - break; - } - - // Always allocate at least 1 node for each level and account for non-full nodes - if ((cur->nodeCount == 0) || (numFramesToAllocate % (1ULL << (levelSizes[i] - PMA_PAGE_SHIFT)) != 0)) - cur->nodeCount++; - - totalNodeCount += cur->nodeCount; - - //NV_PRINTF(LEVEL_INFO, "Level %d: nodeCount: %d, totalNodeCount: %d\n", i, cur->nodeCount, totalNodeCount); - } - - // Allocate all the nodes needed in a linear array - newTree->root = (ADDRTREE_NODE *)portMemAllocNonPaged((NvLength)(totalNodeCount * sizeof(ADDRTREE_NODE))); - if (newTree->root == NULL) - { - goto error; - } - portMemSet(newTree->root, 0, (NvLength)(totalNodeCount * sizeof(ADDRTREE_NODE))); - newTree->root->parent = NULL; - - NvU32 curIdx = 0; - - // Skip the last level because we don't really need to allocate 64K level - for (i = 0; i < levelCount - 1; i++) - { - NvU64 nextLevelStart = curIdx + newTree->levels[i].nodeCount; - // - // The maxChildren a node can have is a factor of - // the difference in page sizes between levels - // - NvU32 maxChildren = 1U<<(levelSizes[i] - levelSizes[i + 1]); - newTree->levels[i].maxFramesPerNode = maxChildren; - - //NV_PRINTF(LEVEL_INFO, "Level %d: maxChildren per node: %d\n", i, maxChildren); - - NvU32 j; - for (j = 0; j < newTree->levels[i].nodeCount; j++) - { - ADDRTREE_NODE *curNode = &newTree->root[curIdx]; - - // Register first node in the level structure - if (j == 0) - { - newTree->levels[i].pNodeList = curNode; - } - - // Populate curNode - curNode->level = i; - curNode->frame = maxChildren * j; - - // All nodes before this node must have maxChildren - NvU64 childrenNodeIdx = nextLevelStart + j * maxChildren; - curNode->children = &newTree->root[childrenNodeIdx]; - - // The last node may not have maxChildren, calculate how many it does have - // OK to just cast because we know numChildren must be at most 64 - NvU32 lastNodeNumValidChildren = (NvU32)(newTree->levels[i+1].nodeCount - (j * maxChildren)); - NvU32 numValidChildren = 0; - - // - // If this is not the last node in a level, - // then it must have maxChildren. - // Otherwise calculate how many it does have. - // - if (j != newTree->levels[i].nodeCount - 1) - { - curNode->numChildren = maxChildren; - numValidChildren = maxChildren; - } - else - { - curNode->numChildren = maxChildren; - numValidChildren = lastNodeNumValidChildren; - - // - // Mark invalid children as allocated so that reads of partial nodes - // do not return that they are available - // - NvU64 invalidChildrenMask = _makeMaskUpToIndex(maxChildren) & ~_makeMaskUpToIndex(lastNodeNumValidChildren); - curNode->state[MAP_IDX_ALLOC_PIN] = invalidChildrenMask; - _addrtreeUpdateAncestors(newTree, curNode, STATE_PIN); - } - - // Populate curNode->children[*]->parent, except for the last level - if (i != levelCount - 2) - { - NvU32 k; - - for (k = 0; k < numValidChildren; k++) - { - ADDRTREE_NODE *curChild = &curNode->children[k]; - curChild->parent = curNode; - } - } - - curIdx++; - } - } - - return (void *)newTree; - -error: - pmaAddrtreeDestroy(newTree); - return NULL; -} - -void pmaAddrtreeDestroy(void *pMap) -{ - NvU64 num2mbPages; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - NV_ASSERT_OR_RETURN_VOID(pTree != NULL); - - num2mbPages = pTree->totalFrames / (_PMA_2MB >> PMA_PAGE_SHIFT); - pTree->pPmaStats->numFreeFrames -= pTree->totalFrames; - pTree->pPmaStats->numFree2mbPages -= num2mbPages; - - if (pTree->bProtected) - { - pTree->pPmaStats->numFreeFramesProtected -= pTree->totalFrames; - pTree->pPmaStats->numFree2mbPagesProtected -= num2mbPages; - } - - portMemFree(pTree->root); - portMemFree(pTree->levels); - - portMemFree(pTree); -} - -static void -_addrtreeConvertFrame(PMA_ADDRTREE *pTree, NvU32 sourceLevel, NvU64 sourceFrame, NvU32 targetLevel, NvU64 *pTargetFrame) -{ - // Converting up the tree, frame number goes down - if (sourceLevel > targetLevel) - { - *pTargetFrame = sourceFrame >> (pTree->levels[targetLevel+1].pageSizeShift - pTree->levels[sourceLevel+1].pageSizeShift); - } - else - { - *pTargetFrame = sourceFrame << (pTree->levels[sourceLevel+1].pageSizeShift - pTree->levels[targetLevel+1].pageSizeShift); - } -} - -// -// Given a node and index into its children array, whether this node is -// on the target level, the current accumulated status, and the current -// valid status mask, read the status of this node index and return -// - The remaining mask of children that will still need to be -// read to determine the state at a lower level of the tree in -// pStatusMask -// - The accumulated status combined with this node index's status -// -// To read the effective value of a node, callers must start with their -// desired status mask, call getNodeIndexStatus, and use the returned -// status mask to know what states still need to be read at the -// next level down in the tree. -// -// If statusMask is 0 upon return, reading children will give no more information -// That is, shouldCheckChildren == (*pStatusMask != 0) -// -// If the caller wants to keep reading status downwards in the tree, it must -// call getNodeIndexStatus with bIsTargetLevel = NV_FALSE. Here is pseudocode -// for reading a node: -// *pCumulativeStatus = 0; -// *pStatusMask = MAP_MASK; -// while (!targetLevel) { -// getNodeIndexStatus(node, index, NV_FALSE, pStatusMask, pCumulativeStatus); -// // increment while condition, typically the following: -// if (!shouldCheckChildren(stateMask)) -// { -// // do logic -// goto exit; -// } -// } -// -// // At target level -// getNodeIndexStatus(node, index, NV_TRUE, pStatusMask, pCumulativeStatus); -// -static void -getNodeIndexStatus -( - ADDRTREE_NODE *node, - NvU32 index, - NvBool bIsTargetLevel, - PMA_PAGESTATUS *pStatusMask, - PMA_PAGESTATUS *pCumulativeStatus -) -{ - PMA_PAGESTATUS curStatusMask = *pStatusMask; - PMA_PAGESTATUS nextStatusMask = 0; - NvU64 state = 0; - NvU32 i; - - NV_ASSERT(index < node->numChildren); - - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - if (curStatusMask & (NVBIT(i))) - { - if (node->seeChild[i] & NVBIT64(index)) - { - nextStatusMask |= NVBIT64(i); - } - - // Assert that either state or seeChild is set, not both - NV_ASSERT(((node->seeChild[i] & node->state[i]) & (NVBIT64(index))) == 0); - - // - // But state does need to be accurate and returned as PMA_PAGESTATUS - // seeChild must be checked to get an accurate state - // - if ((node->state[i] | node->seeChild[i]) & (NVBIT64(index))) - { - state |= NVBIT64(i); - } - } - } - - //NV_PRINTF(LEVEL_ERROR, "curStatusMask=0x%llx, nextStatusMask=0x%llx, index=0x%x, state=0x%llx\n", - // (NvU64)curStatusMask, nextStatusMask, index, state); - - *pStatusMask = nextStatusMask; - - if (bIsTargetLevel) - { - *pCumulativeStatus |= state; - } - else - { - *pCumulativeStatus |= state & ~nextStatusMask; - } -} - -static NvBool -shouldCheckChildren(PMA_PAGESTATUS statusMask) -{ - return statusMask != 0; -} - -// This function returns if the current node holds valid information. -// If not, returns the effective state of this node -static NvBool -_addrtreeNodeValid -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *node, - PMA_PAGESTATUS *pFoundState -) -{ - ADDRTREE_NODE *n = pTree->root; - NvU64 newFrame = 0; - NvU32 newIndex = 0; - *pFoundState = STATE_FREE; - PMA_PAGESTATUS stateMask = MAP_MASK; // check all states TODO - - //NV_PRINTF(LEVEL_INFO, "Source level=%d frame=0x%llx.\n", - // node->level, node->frame); - - while(n->level != node->level) - { - _addrtreeConvertFrame(pTree, node->level, node->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - getNodeIndexStatus(n, newIndex, NV_FALSE, &stateMask, pFoundState); - - if (!shouldCheckChildren(stateMask)) - { - return NV_FALSE; - } - - // Go to the right children to continue walking down - n = &n->children[newIndex]; - } - - return NV_TRUE; - -} - -static NvU64 -_addrtreeComputeMask(ADDRTREE_NODE *node, NvU64 frameStart, NvU64 numFrames) -{ - NV_ASSERT(node->numChildren <= 64); - - NvU64 mask = _makeMaskUpToIndex(node->numChildren); - - // If node is contained within the range, return a full mask - if (RANGE_CONTAINS(frameStart, numFrames, node->frame, node->numChildren)) - { - //NV_PRINTF(LEVEL_ERRORS, "frameStart=0x%llx, numFrames=0x%llx, node: start=0x%llx, num=0x%x, mask=0x%llx\n", - // frameStart, numFrames, node->frame, node->numChildren, mask); - return mask; - } - else - { - // If the node doesn't cover the start, unset the beginning bits - if (frameStart > node->frame) - { - mask &= (~_makeMaskUpToIndex((NvU32)(frameStart - node->frame))); - } - - // If the node doesn't cover the end, unset the last bits - if (frameStart + numFrames < node->frame + node->numChildren) - { - mask &= (_makeMaskUpToIndex((NvU32)(frameStart + numFrames - node->frame))); - } - } - return mask; -} - -// -// For the given state, for the mask of a node's children, -// the function returns -// -// NV_TRUE if the mask is available -// NV_FALSE if the mask is not available -// and the last child index which does not satisfy the given state -// -static NvBool -_addrtreeNodeMaskAvailable( - ADDRTREE_NODE *node, - NvU64 mask, - PMA_PAGESTATUS state, - NvBool bReverse, - NvU64 *pDiff -) -{ - NvU64 allocated = 0; - NvU32 i; - - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - // - // allocated tracks which pages are not available. - // We are looking for pages in free or state status. - // Pages in state status are available, so exclude them. - // - if ((NVBIT(i) & state) == 0) - { - // Note that once we see a seeChild being set, we would - // count that as allocated because some children are allocated - allocated |= node->seeChild[i]; - allocated |= node->state[i]; - } - } - - allocated &= mask; - - if (!bReverse) - { - // - // Skip past all unavailable and return last child index - // which does not satisfy the given state - // This will underflow for allocated == 0, but in that case, - // *pDiff should not be read anyway - // - *pDiff = 64 - portUtilCountLeadingZeros64(allocated) - 1; - } - else - { - // Return the first child index that doesn't satisfy given state - *pDiff = portUtilCountTrailingZeros64(allocated); - } - - return (allocated == 0); -} - -// This function returns the node on a specific level that contains the frame -// The node may or may not contain valid information. That is handled later. -static NvU64 -_addrtreeGetNodeIdx(PMA_ADDRTREE *pTree, NvU32 level, NvU64 frame) -{ - ADDRTREE_LEVEL *treeLevel = &pTree->levels[level]; - - // Current level's frame number should be the same as next level's node number - NV_ASSERT(frame < pTree->levels[level+1].nodeCount); - - return (frame / (treeLevel->maxFramesPerNode)); -} - -// -// Optimization: enable scanning functions to skip over fully allocated -// parent nodes with _pmaAddrtreeReadLevelAndSkipUnavailable -// -// For a given level and startFrame, return the number of frames to skip on the -// given level based on the parent's allocation state. -// Add this number to skip to the startFrame to get the next node which is not -// fully allocated. -// -PMA_PAGESTATUS -_pmaAddrtreeReadLevelAndSkipUnavailable -( - void *pMap, - NvU32 levelNum, - NvU64 frameNum, - PMA_PAGESTATUS searchState, - NvBool bAllowFree, - NvU64 *pNumFramesToSkip, - NvBool bReverse -) -{ - NvU32 index; - ADDRTREE_NODE *pNode; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - ADDRTREE_NODE *n = pTree->root; - NvU64 newFrame = 0; - NvU32 newIndex; - PMA_PAGESTATUS status = STATE_FREE; - PMA_PAGESTATUS stateMask = MAP_MASK; - - _addrtreeConvertLevelFrameToNodeIndex(pTree, levelNum, frameNum, &pNode, &index); - - while (n->level != pNode->level) - { - _addrtreeConvertFrame(pTree, pNode->level, pNode->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - getNodeIndexStatus(n, newIndex, NV_FALSE, &stateMask, &status); - - if (!shouldCheckChildren(stateMask)) - { - // - // There's no need to scan further down. - // Return the number of frames to skip over on the target level - // in order to skip over this n->level ancestor. - // - - NvBool bWrongState = (status != searchState) && !(bAllowFree && (status == STATE_FREE)); - - if (bWrongState) - { - // - // This node is fully allocated. - // Return the number of frames of the target level we should skip. - // - NvU64 targetFrameStartForThisNode; - NvU64 numTargetFramesPerAncestor; - - _addrtreeConvertFrame(pTree, n->level, newFrame, levelNum, &targetFrameStartForThisNode); - _addrtreeConvertFrame(pTree, n->level, 1ULL, levelNum, &numTargetFramesPerAncestor); - - if (!bReverse) - *pNumFramesToSkip = numTargetFramesPerAncestor - (frameNum - targetFrameStartForThisNode); - else - *pNumFramesToSkip = frameNum - targetFrameStartForThisNode + 1; - } else { - // - // This node is in a state we're searching for. - // The caller will store off one frame of the target level - // - *pNumFramesToSkip = 1; - } - - goto exit; - } - - // Go to the right children to continue walking down - n = &n->children[newIndex]; - } - - *pNumFramesToSkip = 1; - - // Extract the final value from this pNode - getNodeIndexStatus(pNode, index, NV_TRUE, &stateMask, &status); - -exit: - NV_ASSERT(*pNumFramesToSkip > 0); - return status; -} - -// -// For the given state, between frameStart and (frameStart + numFrames - 1) -// for a given level, this function returns -// -// NV_TRUE if the range is available -// NV_FALSE if the range is not available -// and the frame number of the last frame which does not -// satisfy the given state in the variable pDiff -// -// XXX: Caution! This will not properly pick up nodes only in state `state` -// If it were used for discontig scanning, it would be wrong! -// -static NvBool -_pmaAddrtreeAvailable -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 frameStart, - NvU64 numFrames, - NvU64 *pDiff -) -{ - NvU64 i, startIdx, endIdx, childrenMask; - PMA_PAGESTATUS foundState; - NvU64 nodeIndexDiff; - ADDRTREE_NODE *node; - - NV_ASSERT(level != 0); // TODO handle the root node case - //NV_PRINTF(LEVEL_INFO, "level=%d, frameStart=0x%llx, numFrames=%llx\n", - // level, frameStart, numFrames); - - startIdx = _addrtreeGetNodeIdx(pTree, level, frameStart); - endIdx = _addrtreeGetNodeIdx(pTree, level, (frameStart + numFrames - 1)); - - //NV_PRINTF(LEVEL_INFO, "startIdx = %llx, endIdx = 0x%llx\n", startIdx, endIdx); - - // Begin checking from the end so that we can skip the most frames in the overall search - for (i = endIdx; i >= startIdx; i--) - { - // Protect against underflow - if (i == (NvU64)-1) break; - - //NV_PRINTF(LEVEL_INFO, "IN LOOP: i=0x%llx, startIdx=%llx\n", i, startIdx); - node = &(pTree->levels[level].pNodeList[i]); - if (_addrtreeNodeValid(pTree, node, &foundState)) - { - childrenMask = _addrtreeComputeMask(node, frameStart, numFrames); - - if (!_addrtreeNodeMaskAvailable(node, childrenMask, state, NV_FALSE, &nodeIndexDiff)) - { - *pDiff = node->frame + nodeIndexDiff; - return NV_FALSE; - } - } - else - { - //NV_PRINTF(LEVEL_INFO, "IN LOOP: Node is INVALID. allocated?-%d\n", - // (NvU32)state); - if ((foundState != STATE_FREE) && (foundState != state)) - { - // This node is completely allocated. - // Return the frame number of the last frame in this node - *pDiff = node->frame + node->numChildren - 1; - return NV_FALSE; - } - else - { - // - // This node is completely free or in a state we're looking for, - // continue checking - // - continue; - } - } - } - - return NV_TRUE; -} - -// -// For the given state, between frameStart and (frameStart + numFrames - 1) -// for a given level, this function returns -// -// NV_TRUE if the range is available -// NV_FALSE if the range is not available -// and the frame number of the first frame which does not -// satisfy the given state in the variable pDiff -// -// XXX: Caution! This will not properly pick up nodes only in state `state` -// If it were used for discontig scanning, it would be wrong! -// -static NvBool -_pmaAddrtreeAvailableReverse -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 frameStart, - NvU64 numFrames, - NvU64 *pDiff -) -{ - NvU64 i, startIdx, endIdx, childrenMask; - PMA_PAGESTATUS foundState; - NvU64 nodeIndexDiff; - ADDRTREE_NODE *node; - - NV_ASSERT(level != 0); // TODO handle the root node case - - startIdx = _addrtreeGetNodeIdx(pTree, level, frameStart); - endIdx = _addrtreeGetNodeIdx(pTree, level, (frameStart + numFrames - 1)); - - // For reverse alloc, begin checking from the start so that we can skip the most frames in the overall search - for (i = startIdx; i <= endIdx; i++) - { - node = &(pTree->levels[level].pNodeList[i]); - if (_addrtreeNodeValid(pTree, node, &foundState)) - { - childrenMask = _addrtreeComputeMask(node, frameStart, numFrames); - - if (!_addrtreeNodeMaskAvailable(node, childrenMask, state, NV_TRUE, &nodeIndexDiff)) - { - *pDiff = node->frame + nodeIndexDiff; - return NV_FALSE; - } - } - else - { - if ((foundState != STATE_FREE) && (foundState != state)) - { - // This node is completely allocated. - // Return the frame number of the first frame in this node - *pDiff = node->frame; - return NV_FALSE; - } - else - { - // - // This node is completely free or in a state we're looking for, - // continue checking - // - continue; - } - } - } - - return NV_TRUE; -} - -static NvBool -_pmaAddrtreeContigSearchLoop -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 addrBase, - NvU64 localStart, - NvU64 localEnd, - NvU64 numFrames, - NvU64 frameAlignment, - NvU64 *freeList -) -{ - NvBool found = NV_FALSE; - NvU64 freeStart; - NvU64 diff; - PMA_PAGESTATUS startStatus, endStatus; - - if ((state != STATE_FREE) && (state != STATE_UNPIN)) - { - NV_PRINTF(LEVEL_INFO, "Scanning for state %d is not supported\n", state); - return found; - } - - freeStart = localStart; - while (!found) - { - NvU64 endFrame = freeStart + numFrames - 1; - NvU64 framesToSkip = 0; - - if (endFrame > localEnd) - { - // freeStart + numFrames too close to local search end. Re-starting search - break; - } - - // - // Read endStatus first so we don't have to waste time traversing the - // tree again to read startStatus if endStatus is not even usable - // - endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, endFrame, state, NV_TRUE, &framesToSkip, NV_FALSE); - - if (framesToSkip > 1) { - freeStart = NV_ALIGN_UP(endFrame + framesToSkip, frameAlignment); - NV_ASSERT(freeStart != 0); - continue; - } - - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_TRUE, &framesToSkip, NV_FALSE); - - if (framesToSkip > 1) { - freeStart += NV_ALIGN_UP(framesToSkip, frameAlignment); - NV_ASSERT(freeStart != 0); - continue; - } - - if ((endStatus == STATE_FREE) || (endStatus == state)) - { - if ((startStatus == STATE_FREE) || (startStatus == state)) - { - if (_pmaAddrtreeAvailable(pTree, level, state, freeStart, numFrames, &diff)) - { - found = NV_TRUE; - // Substract off padding when returning - *freeList = addrBase + ((freeStart << pTree->levels[level+1].pageSizeShift) - - (pTree->numPaddingFrames << PMA_PAGE_SHIFT)); - //NV_PRINTF(LEVEL_INFO, "found! 0x%llx\n", freeStart); - } - else - { - //NV_PRINTF(LEVEL_INFO, "Frame number of allocated frame = 0x%llx\n", - // diff); - // - // Find the next aligned free frame and set it as the start - // frame for next iteration's scan. - // - freeStart = NV_ALIGN_UP(diff + 1, frameAlignment); - NV_ASSERT(freeStart != 0); - } - } - else - { - // Start point isn't free, so bump to check the next aligned frame - freeStart += frameAlignment; - } - } - else - { - // - // End point isn't usable, so jump to after the end to check again - // However, align the new start point properly before next iteration. - // - freeStart += NV_ALIGN_UP(numFrames, frameAlignment); - } - } - - return found; -} - -static NvBool -_pmaAddrtreeContigSearchLoopReverse -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 addrBase, - NvU64 localStart, - NvU64 localEnd, - NvU64 numFrames, - NvU64 frameAlignment, - NvU64 *freeList -) -{ - NvBool found = NV_FALSE; - NvU64 freeStart; - NvU64 diff; - PMA_PAGESTATUS startStatus, endStatus; - - if ((state != STATE_FREE) && (state != STATE_UNPIN)) - { - NV_PRINTF(LEVEL_INFO, "Scanning for state %d is not supported\n", state); - return found; - } - - freeStart = localEnd + 1 - numFrames; // First frame from end able to accommodate num_frames allocation. - freeStart = NV_ALIGN_DOWN(freeStart, frameAlignment); - while (!found) - { - NvU64 framesToSkip = 0; - - if (freeStart < localStart || (NvS64)freeStart < 0) // Account for underflow - { - // freeStart too close to local search start. Re-starting search - break; - } - - // - // For reverse allocation, read startStatus first so we don't have to waste time - // traversing the tree again to read endStatus if startStatus is not even usable - // - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_TRUE, &framesToSkip, NV_TRUE); - if (framesToSkip > 1) { - NvU64 newEndFrame = freeStart - framesToSkip; - freeStart = newEndFrame + 1 - numFrames; - freeStart = NV_ALIGN_DOWN(freeStart, frameAlignment); - continue; - } - - endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart + numFrames - 1, state, NV_TRUE, &framesToSkip, NV_TRUE); - if (framesToSkip > 1) { - freeStart -= NV_ALIGN_UP(framesToSkip, frameAlignment); - continue; - } - - if ((startStatus == STATE_FREE) || (startStatus == state)) - { - if ((endStatus == STATE_FREE) || (endStatus == state)) - { - if (_pmaAddrtreeAvailableReverse(pTree, level, state, freeStart, numFrames, &diff)) - { - found = NV_TRUE; - // Subtract off padding when returning - *freeList = addrBase + ((freeStart << pTree->levels[level+1].pageSizeShift) - - (pTree->numPaddingFrames << PMA_PAGE_SHIFT)); - //NV_PRINTF(LEVEL_INFO, "found! 0x%llx\n", freeStart); - } - else - { - //NV_PRINTF(LEVEL_INFO, "Frame number of allocated frame = 0x%llx\n", - // diff); - // - // Find the next aligned free frame and set it as the end - // frame for next iteration's scan. - // - freeStart = NV_ALIGN_DOWN(diff - numFrames, frameAlignment); - } - } - else - { - // Start point isn't free, so bump to check the next aligned frame - freeStart -= frameAlignment; - } - } - else - { - // - // End point isn't usable, so jump to after the end to check again - // However, align the new start point properly before next iteration. - // - freeStart -= NV_ALIGN_UP(numFrames, frameAlignment); - } - } - - return found; -} - -static NV_STATUS -_pmaAddrtreeScanContiguous -( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU64 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict, - NvBool bReverseAlloc -) -{ - NvU64 localStart, localEnd, frameAlignment; - NvBool found; - NvU32 level; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - // This requirement is ensured in PMA - NV_ASSERT(alignment >= pageSize && portUtilIsPowerOfTwo(alignment)); - - *numPagesAlloc = 0; - - // Only focus on the level above the pageSize level. Children are ignored. - level = addrtreeGetTreeLevel(pageSize); - if (level == 0) - { - NV_PRINTF(LEVEL_ERROR, "address tree cannot handle page size 0x%llx\n", - pageSize); - return NV_ERR_INVALID_ARGUMENT; - } - - frameAlignment = alignment / pageSize; - - // Handle restricted allocations - if (rangeStart != 0 || rangeEnd != 0) - { - rangeStart += (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - rangeEnd += (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - localStart = NV_ALIGN_UP64(rangeStart, alignment) >> pTree->levels[level].pageSizeShift; - localEnd = NV_MIN(rangeEnd >> pTree->levels[level].pageSizeShift, pTree->levels[level].nodeCount - 1); - } - else - { - localStart = NV_ALIGN_UP64(pTree->numPaddingFrames << PMA_PAGE_SHIFT, alignment) >> pTree->levels[level].pageSizeShift; - localEnd = pTree->levels[level].nodeCount - 1; - } - - //NV_PRINTF(LEVEL_INFO, "Scanning level %d with addrBase 0x%llx in frame range 0x%llx..0x%llx, " - // "pages to allocate 0x%llx (pageSize=0x%x, alignment=0x%x)\n", - // (level - 1), addrBase, localStart, localEnd, numPages, pageSize, alignment); - if (!bReverseAlloc) - { - found = _pmaAddrtreeContigSearchLoop(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); - } - else - { - found = _pmaAddrtreeContigSearchLoopReverse(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); - } - - if (found) - { - *numPagesAlloc = numPages; - return NV_OK; - } - - if (bSkipEvict) - { - return NV_ERR_NO_MEMORY; - } - - // Loop back to the beginning and continue searching for evictable pages - if (!bReverseAlloc) - { - found = _pmaAddrtreeContigSearchLoop(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); - } - else - { - found = _pmaAddrtreeContigSearchLoopReverse(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); - } - if (found) - return NV_ERR_IN_USE; - else - return NV_ERR_NO_MEMORY; -} - -// -// This function wraps the real _pmaAddrtreeScanContiguous -// to allow addrtree to scan for 128KB page size -// -NV_STATUS -pmaAddrtreeScanContiguous -( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU64 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict, - NvBool bReverseAlloc -) -{ - if (NV_UNLIKELY(pageSize == _PMA_128KB)) { - // - // Call the contig function with twice as many 64KB frames, - // and cut in half the number of allocated frames. - // Contig allocations are all or nothing so the number of - // allocated frames cannot be odd. - // - NV_STATUS status; - - status = _pmaAddrtreeScanContiguous( - pMap, - addrBase, - rangeStart, - rangeEnd, - numPages * 2, - freeList, - _PMA_64KB, - alignment, - numPagesAlloc, - bSkipEvict, - bReverseAlloc); - - *numPagesAlloc /= 2; - - return status; - } - else - { - return _pmaAddrtreeScanContiguous( - pMap, - addrBase, - rangeStart, - rangeEnd, - numPages, - freeList, - pageSize, - alignment, - numPagesAlloc, - bSkipEvict, - bReverseAlloc); - } -} - -static NvU64 -_pmaAddrtreeDiscontigSearchLoop -( - PMA_ADDRTREE *pTree, - NvU32 level, - PMA_PAGESTATUS state, - NvU64 addrBase, - NvU64 localStart, - NvU64 localEnd, - NvU64 numFrames, - NvU64 frameAlignment, - NvU64 *freeList, - NvBool bReverseAlloc -) -{ - NvU64 found = 0; - NvU64 freeStart; - PMA_PAGESTATUS startStatus; - - if ((state != STATE_FREE) && (state != STATE_UNPIN)) - { - NV_PRINTF(LEVEL_INFO, "Scanning for state %d is not supported\n", state); - return found; - } - - freeStart = !bReverseAlloc ? localStart : localEnd; - - // - // We only need one frame at a time on this level, - // so we can skip much of the frame logic - // - while (found != numFrames) - { - NvU64 framesToSkip = 0; - - if (freeStart > localEnd || freeStart < localStart || (NvS64)freeStart < 0) break; - - // - // For discontig, we MUST only pick up the exact state. - // Otherwise we give away pages for eviction that we already stored off to be allocated. - // - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_FALSE, &framesToSkip, bReverseAlloc); - - if (startStatus == state) - { - // Substract off padding when returning - freeList[found++] = addrBase + ((freeStart << pTree->levels[level+1].pageSizeShift) - - (pTree->numPaddingFrames << PMA_PAGE_SHIFT)); - } - freeStart = !bReverseAlloc ? (freeStart + framesToSkip) : (freeStart - framesToSkip); - } - - return found; -} - -static NV_STATUS -_pmaAddrtreeScanDiscontiguous -( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU64 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict, - NvBool bReverseAlloc -) -{ - NvU64 localStart, localEnd; - NvU64 foundFree; - NvU64 foundEvictable; - NvU32 level; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - // This requirement is ensured in PMA - NV_ASSERT(alignment == pageSize); - - // Only focus on the level above the pageSize level. Children are ignored. - level = addrtreeGetTreeLevel(pageSize); - if (level == 0) - { - NV_PRINTF(LEVEL_ERROR, "address tree cannot handle page size 0x%llx\n", - pageSize); - return NV_ERR_INVALID_ARGUMENT; - } - - // Handle restricted allocations - if (rangeStart != 0 || rangeEnd != 0) - { - // Embedded % requires special handling. - NV_ASSERT_OR_ELSE_STR(rangeStart % pageSize == 0, - "rangeStart %% pageSize == 0", /*do nothing*/); - NV_ASSERT_OR_ELSE_STR((rangeEnd + 1) % pageSize == 0, - "(rangeEnd + 1) %% pageSize == 0", /*do nothing*/); - - rangeStart += (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - rangeEnd += (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - localStart = NV_ALIGN_UP(rangeStart, alignment) >> pTree->levels[level].pageSizeShift; - localEnd = NV_MIN(rangeEnd >> pTree->levels[level].pageSizeShift, pTree->levels[level].nodeCount - 1); - } - else - { - localStart = NV_ALIGN_UP64(pTree->numPaddingFrames << PMA_PAGE_SHIFT, alignment) >> pTree->levels[level].pageSizeShift; - localEnd = pTree->levels[level].nodeCount - 1; - } - - //NV_PRINTF(LEVEL_INFO, "Scanning level %d with addrBase 0x%llx in frame range 0x%llx..0x%llx, " - // "pages to allocate 0x%llx (pageSize=0x%x, alignment=0x%x)\n", - // (level - 1), addrBase, localStart, localEnd, numPages, pageSize, alignment); - - foundFree = _pmaAddrtreeDiscontigSearchLoop(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, - numPages, alignment, freeList, bReverseAlloc); - - - // numPagesAlloc must be set for partial allocations - *numPagesAlloc = foundFree; - - if (foundFree == numPages) - { - return NV_OK; - } - else if (bSkipEvict) - { - return NV_ERR_NO_MEMORY; - } - - // - // Loop back to the beginning and continue searching for evictable pages - // This next search picks up only evictable pages and not free pages - // - foundEvictable = _pmaAddrtreeDiscontigSearchLoop(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, - (numPages - foundFree), alignment, (freeList + foundFree), bReverseAlloc); - - if ((foundFree + foundEvictable) == numPages) - return NV_ERR_IN_USE; - else - return NV_ERR_NO_MEMORY; -} - -// -// This function wraps the real _pmaAddrtreeScanDiscontiguous -// to allow addrtree to scan for 128KB page size -// -NV_STATUS -pmaAddrtreeScanDiscontiguous -( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU64 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict, - NvBool bReverseAlloc -) -{ - if (NV_UNLIKELY(pageSize == _PMA_128KB)) { - NV_STATUS status = NV_OK; - NvU64 i; - NvU64 localNumPagesAlloc; - *numPagesAlloc = 0; - - if (rangeEnd == 0) { - NV_ASSERT(rangeStart == 0); - rangeEnd = ((PMA_ADDRTREE *)pMap)->totalFrames << PMA_PAGE_SHIFT; - } - - for (i = 0; i < numPages; i++) { - // - // Only call the contig function because we need the two frames to be - // contiguous. - // Alignment only needs to be aligned to 64KB and power of 2, - // so it is ok to pass through even if it is 128KB - // - status = _pmaAddrtreeScanContiguous( - pMap, - addrBase, - rangeStart, - rangeEnd, - 2, - freeList + i, - _PMA_64KB, - alignment, - &localNumPagesAlloc, - bSkipEvict, - bReverseAlloc); - - // Give back the first of every two 64KB frames - *numPagesAlloc += localNumPagesAlloc / 2; - - if (status != NV_OK) - { - return status; - } - - if (!bReverseAlloc) - rangeStart = freeList[i] + _PMA_128KB; - else - { - rangeEnd = freeList[i] - 1; - if (rangeEnd < rangeStart || (NvS64)rangeEnd < 0) - { - // Extended the current implementation to reverse alloc here but - // isn't this logic incorrect for tryEvict case? As we are closing - // off the region for tryEvict case after an allocation is made. - // Also we don't check evictable for remaining pages after the - // first NV_ERR_IN_USE is returned. - if (i < numPages - 1) return NV_ERR_NO_MEMORY; - } - } - } - - return status; - } - else - { - return _pmaAddrtreeScanDiscontiguous( - pMap, - addrBase, - rangeStart, - rangeEnd, - numPages, - freeList, - pageSize, - alignment, - numPagesAlloc, - bSkipEvict, - bReverseAlloc); - } -} - -// Either set or clear a specified bit in old and return the result -static NvU64 -replaceBit(NvU64 old, NvU32 bit, NvBool bIsSet) -{ - NV_ASSERT(bit < 64); - NvU64 mask = NVBIT64(bit); - return bIsSet ? (old | mask) : (old & ~mask); -} - -static void -_addrtreeUpdateAncestors -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *pNode, - PMA_PAGESTATUS newStateMask -) -{ - ADDRTREE_NODE *pParent; - NvU32 i; - NvU64 newFrame; - NvU32 newIndex; - PMA_PAGESTATUS stateMask; - NvU64 fillPattern; - - pParent = pNode->parent; - - while (pParent != NULL) - { - //NV_PRINTF(LEVEL_INFO, "Current level %d Maybe updating parent at level %d newStateMask=%x\n", - // pNode->level, pNode->level - 1, newStateMask); - - if (newStateMask == 0) - break; - - fillPattern = _makeMaskUpToIndex(pNode->numChildren); - _addrtreeConvertFrame(pTree, pNode->level, pNode->frame, pParent->level, &newFrame); - newIndex = (NvU32)(newFrame - pParent->frame); - - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - stateMask = NVBIT(i); - - if (stateMask & newStateMask) - { - NvBool bSeeChild; - NvBool bSetState; - NvU64 newSeeChild; - NvU64 newState; - - // Calculate what this node should look like to the parent - bSetState = NV_FALSE; - bSeeChild = NV_TRUE; - if (pNode->seeChild[i] == 0) - { - if (pNode->state[i] == fillPattern) - { - bSetState = NV_TRUE; - bSeeChild = NV_FALSE; - } - else if (pNode->state[i] == 0) - { - bSeeChild = NV_FALSE; - } - } - - newSeeChild = replaceBit(pParent->seeChild[i], newIndex, bSeeChild); - newState = replaceBit(pParent->state[i], newIndex, bSetState); - - //NV_PRINTF(LEVEL_INFO, "bSetState %d bSeeChild %d newSeeChild=0x%llx newState=0x%llx \n", - // bSetState, bSeeChild, newSeeChild, newState); - - // - // If the parent won't change from this update, do not do any further - // checking on this state: remove it from the mask - // - if (pParent->seeChild[i] == newSeeChild && pParent->state[i] == newState) - { - newStateMask &= ~stateMask; - continue; - } - - //NV_PRINTF(LEVEL_INFO, "update parent\n"); - - pParent->seeChild[i] = newSeeChild; - pParent->state[i] = newState; - - } - } - - pNode = pParent; - pParent = pNode->parent; - } - -} - -// -// This function traverses the tree and changes the state of the frame at `index` -// in `node` to the desired states and change all its ancestors to set seeChild. -// Note that this function also makes `node` a valid node unconditionally. -// -static void -_addrtreeSetState -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *pNode, - NvU32 index, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask -) -{ - ADDRTREE_NODE *n = pTree->root; - ADDRTREE_NODE *pChildNode; - NvU32 i; - NvU64 newFrame = 0; - NvU32 newIndex; - NvU64 stateMask; - NvU64 childMask = 0; - - //NV_PRINTF(LEVEL_INFO, "Source level=%d frame=0x%llx.\n", - // pNode->level, pNode->frame); - NV_ASSERT(index < pNode->numChildren); - - // Walk down from root and update all its ancestors - while(n->level != pNode->level) - { - _addrtreeConvertFrame(pTree, pNode->level, pNode->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - //NV_PRINTF(LEVEL_INFO, "Going to traverse level=%d newFrame=0x%x newIndex=0x%x \n", - // n->level, newFrame, newIndex); - - childMask = NVBIT64(newIndex); - pChildNode = &n->children[newIndex]; - - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - stateMask = NVBIT64(i); - - if (stateMask & newStateMask) - { - // - // If entire node has some state, update children to contain the same state - // Only update child state if this node's seeChild is 0 - // - if ((childMask & n->seeChild[i]) == 0) - { - if ((n->state[i] & childMask) != 0) - { - // - // Note that we may overwrite the pinned state of the edge cases here, - // but they will still be in the correct state since they cannot be the - // ones being freed. - // - pChildNode->state[i] = _makeMaskUpToIndex(pChildNode->numChildren); - } - else - { - // - // There is no risk of overwriting the ALLOC_PIN frames set to - // protect the end-of-region edge case. If seeChild == 0, these nodes - // and all ancestors must be in the set state, not the clear state - // because addrtree will not give out frames that are out of bounds - // - pChildNode->state[i] = 0; - } - - // Set the child's seeChild to 0 so we force update it next iteration - pChildNode->seeChild[i] = 0; - } - n->seeChild[i] |= childMask; - } - } - // Go to the right children to continue walking down - n = pChildNode; - } - - - //NV_PRINTF(LEVEL_INFO, "Setting pNode level=%d frame=0x%llx index=0x%x to state=0x%llx mask=0x%llx\n", - // pNode->level, pNode->frame, index, newState, newStateMask); - - // - // Important loop to actually set the state bits now. - // Do not refactor this unless you know what you are doing! - // Update the node, then go update the ancestors. - // - for (i = 0; i < PMA_BITS_PER_PAGE; i++) - { - stateMask = NVBIT64(i); - - if (stateMask & newStateMask) - { - // Set the current node index as valid since we are changing its states - pNode->seeChild[i] &= ~NVBIT64(index); - - if (stateMask & newStateMask & newState) - { - pNode->state[i] |= NVBIT64(index); - } - else - { - pNode->state[i] &= ~NVBIT64(index); - } - } - } - - _addrtreeUpdateAncestors(pTree, pNode, newStateMask); -} - -static PMA_PAGESTATUS -_addrtreeGetState -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *node, - NvU32 index, - NvBool bReadAttrib -) -{ - ADDRTREE_NODE *n = pTree->root; - - NvU64 newFrame = 0; - NvU32 newIndex; - PMA_PAGESTATUS status = STATE_FREE; - PMA_PAGESTATUS stateMask = bReadAttrib ? MAP_MASK : STATE_MASK; - - while(n->level != node->level) - { - _addrtreeConvertFrame(pTree, node->level, node->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - //NV_PRINTF(LEVEL_INFO, "n->level=0x%x, node->level=0x%x\n", n->level, node->level); - - getNodeIndexStatus(n, newIndex, NV_FALSE, &stateMask, &status); - - if (!shouldCheckChildren(stateMask)) - { - return status; - } - - // Go to the right children to continue walking down - n = &n->children[newIndex]; - } - - // Extract the final value from this node - getNodeIndexStatus(node, index, NV_TRUE, &stateMask, &status); - - return status; -} - -// TODO: this is pretty similar to _addrtreeConvertFrame: maybe combine - -static void -_addrtreeConvertLevelFrameToNodeIndex -( - PMA_ADDRTREE *pTree, - NvU32 levelNum, - NvU64 frameNum, - ADDRTREE_NODE **ppNode, - NvU32 *pIndex -) -{ - NvU32 nodeIdx; - ADDRTREE_LEVEL *pLevel; - NvU32 framesPerNode; - - pLevel = &pTree->levels[levelNum]; - framesPerNode = pLevel->maxFramesPerNode; - - nodeIdx = (NvU32)(frameNum / framesPerNode); - *pIndex = (NvU32)(frameNum % framesPerNode); - *ppNode = &pLevel->pNodeList[nodeIdx]; - - NV_ASSERT(*pIndex < (*ppNode)->numChildren); -} - -//frameNum is a levelNum frame -static PMA_PAGESTATUS -pmaAddrtreeReadLevel -( - void *pMap, - NvU32 levelNum, - NvU64 frameNum, - NvBool bReadAttrib -) -{ - NvU32 index; - ADDRTREE_NODE *pNode; - PMA_PAGESTATUS state; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - _addrtreeConvertLevelFrameToNodeIndex(pTree, levelNum, - frameNum, &pNode, &index); - - state = _addrtreeGetState(pTree, pNode, index, bReadAttrib); - return state; -} - -// -// This function returns if the node pointed to by pNode index -// has any seeChild bits set for those seeChild bits that are valid for this node. -// It also returns the value of the pNode index in pState -// This is very similar to _addrtreeNodeValid, but requires some tweaked logic -// This is necessary for a very specific check in _pmaAddrtreeChangePageStateAttribEx -// This node must have at least one more level beneath it! -// -static NvBool -_addrtreeNodeIndexHasSeeChildSet -( - PMA_ADDRTREE *pTree, - ADDRTREE_NODE *pNode, - NvU32 index, - PMA_PAGESTATUS *pState -) -{ - ADDRTREE_NODE *n = pTree->root; - NvU64 newFrame = 0; - NvU32 newIndex = 0; - *pState = STATE_FREE; - - // TODO: try this for only STATE_MASK, because stats will only - // get corrupted if the STATE_MASK values differ. - PMA_PAGESTATUS stateMask = MAP_MASK; // check all states TODO - - while(n->level != pNode->level) - { - _addrtreeConvertFrame(pTree, pNode->level, pNode->frame, n->level, &newFrame); - newIndex = (NvU32)(newFrame - n->frame); - - getNodeIndexStatus(n, newIndex, NV_FALSE, &stateMask, pState); - - if (!shouldCheckChildren(stateMask)) - { - // State is fully realized in an ancestor above the parent - return NV_FALSE; - } - - // Go to the right children to continue walking down - n = &n->children[newIndex]; - } - - // Extract the value from this pNode - getNodeIndexStatus(pNode, index, NV_FALSE, &stateMask, pState); - - // Now check if the final child has any seeChild set - if (shouldCheckChildren(stateMask)) - { - // Target child is different from parent - return NV_TRUE; - } - else - { - // State is fully realized in parent - return NV_FALSE; - } -} - -// frameNumStart is the 64k frameNum to start with -static void -__pmaAddrtreeChangePageStateAttribEx -( - void *pMap, - NvU64 frameNumStart, - NvU64 pageSize, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask -) -{ - NvU32 index; - ADDRTREE_NODE *pNode; - NvU32 targetLevelNum = addrtreeGetTreeLevel(pageSize) - 1; - NvU64 targetFrameNum; - NvU32 levelNum = addrtreeGetTreeLevel(_PMA_64KB) - 1; - NvU32 levelNum2mb = addrtreeGetTreeLevel(_PMA_2MB) - 1; - PMA_PAGESTATUS oldState, updatedState, oldState2mb, updatedState2mb; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - PMA_PAGESTATUS targetFoundState; - ADDRTREE_NODE *pTargetNode; - NvU32 targetIndex; - - frameNumStart += pTree->numPaddingFrames; - newStateMask &= MAP_MASK; - - _addrtreeConvertFrame(pTree, levelNum, frameNumStart, targetLevelNum, &targetFrameNum); - - _addrtreeConvertLevelFrameToNodeIndex(pTree, targetLevelNum, targetFrameNum, &pTargetNode, &targetIndex); - - // - // In address tree, if a node is partially allocated, any node above that node is considered fully - // allocated because you cannot allocate a node-aligned block at the higher level. - // Because of address tree structure, we don't get an accurate count of the number of frames - // that were allocated beforehand if we're overwriting some state. - // e.g. if a node is half allocated and then we allocate the rest of it at a higher level, - // then there's no way to know how many frames were allocated before without going downwards and reading them. - // Until something better is implemented, implement a heuristic wherein we only do the optimized case - // when the current node has no seeChild bits are set for thoese seeChild bits that are valid for this node. - // Also, we won't get any optimization out of doing this for 64KB, so skip it and avoid wasting time - // reading state. - // Since stats only care about free/unpin/pin states,.we could perhaps relax this restriction - // - - if ((pageSize >= _PMA_2MB) && - !_addrtreeNodeIndexHasSeeChildSet(pTree, pTargetNode, targetIndex, &targetFoundState)) - { - // Do optimized case - - // Figure out how many 64KB frames and how many 2MB frames we're going to touch - NvU64 numFramesTouched = pageSize >> PMA_PAGE_SHIFT; - NvU64 num2mbFramesTouched = pageSize >> _TREE_2MB; - - updatedState = (targetFoundState & ~newStateMask) | (newState & newStateMask); - - _addrtreeSetState(pTree, pTargetNode, targetIndex, newState, newStateMask); - - // In this case, the states at the 2MB and 64KB levels are the same because we're changing at - // least a 2MB node that had no valid children - pmaStatsUpdateState(&pTree->pPmaStats->numFreeFrames, - numFramesTouched, targetFoundState, updatedState); - pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPages, - num2mbFramesTouched, targetFoundState, updatedState); - - if (pTree->bProtected) - { - pmaStatsUpdateState(&pTree->pPmaStats->numFreeFramesProtected, - numFramesTouched, targetFoundState, updatedState); - pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPagesProtected, - num2mbFramesTouched, targetFoundState, updatedState); - } - } - else - { - // Do unoptimized case - NvU32 framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); - NvU32 j; - - for (j = 0; j < framesPerPage; j++) - { - NvU64 frameNum2mb; - NvU64 frameNum = frameNumStart + j; - - _addrtreeConvertFrame(pTree, levelNum, frameNum, levelNum2mb, &frameNum2mb); - oldState2mb = pmaAddrtreeReadLevel(pTree, levelNum2mb, frameNum2mb, NV_TRUE); - - _addrtreeConvertLevelFrameToNodeIndex(pTree, levelNum, frameNum, &pNode, &index); - - // The read is done only to update the stats tracking - oldState = pmaAddrtreeReadLevel(pTree, levelNum, frameNum, NV_TRUE); - _addrtreeSetState(pTree, pNode, index, newState, newStateMask); - - // Calculate what the new state will be - updatedState = (oldState & ~newStateMask) | (newState & newStateMask); - - pmaStatsUpdateState(&pTree->pPmaStats->numFreeFrames, 1, oldState, updatedState); - - if (pTree->bProtected) - { - pmaStatsUpdateState(&pTree->pPmaStats->numFreeFramesProtected, - 1, oldState, updatedState); - } - - updatedState2mb = pmaAddrtreeReadLevel(pTree, levelNum2mb, frameNum2mb, NV_TRUE); - - if (updatedState2mb != oldState2mb) - { - pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPages, 1, - oldState2mb, updatedState2mb); - - if (pTree->bProtected) - { - pmaStatsUpdateState(&pTree->pPmaStats->numFree2mbPagesProtected, 1, - oldState2mb, updatedState2mb); - } - } - } - - } -} - -// -// This function wraps the real __pmaAddrtreeChangePageStateAttribEx -// to allow addrtree to set 128KB page size -// -void -pmaAddrtreeChangePageStateAttribEx -( - void *pMap, - NvU64 frameNumStart, - NvU64 pageSize, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask -) -{ - if (NV_UNLIKELY(pageSize == _PMA_128KB)) { - NvU64 i; - for (i = 0; i < 2; i++) { - __pmaAddrtreeChangePageStateAttribEx( - pMap, - frameNumStart + i, - _PMA_64KB, - newState, - newStateMask); - } - } - else - { - __pmaAddrtreeChangePageStateAttribEx( - pMap, - frameNumStart, - pageSize, - newState, - newStateMask); - } -} - -// -// These accessor functions can be made more efficient. TODO improve this. -// We have page size information in the alloc path, but in general, we don't use -// _pmaAddrtreeChangePageStateAttribEx to its fullest extent for all other cases where -// we change the state of the tree. -// If we had the page size information, we won't need to walk the tree for every frame. -// For now, pmaAddrtreeChangeState and pmaAddrtreeRead only operate on 64K level frameNums -// -void -pmaAddrtreeChangeStateAttribEx -( - void *pMap, - NvU64 frameNum, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS newStateMask -) -{ - pmaAddrtreeChangePageStateAttribEx(pMap, frameNum, _PMA_64KB, newState, newStateMask); -} - -void -pmaAddrtreeChangeBlockStateAttrib -( - void *pMap, - NvU64 frame, - NvU64 len, - PMA_PAGESTATUS newState, - PMA_PAGESTATUS writeMask -) -{ - while (len != 0) - { - len--; - pmaAddrtreeChangeStateAttribEx(pMap, frame + len, newState, writeMask); - } -} - -PMA_PAGESTATUS pmaAddrtreeRead -( - void *pMap, - NvU64 frameNum, - NvBool bReadAttrib -) -{ - NvU32 index; - ADDRTREE_NODE *pNode; - NvU32 levelNum = addrtreeGetTreeLevel(_PMA_64KB) - 1; - PMA_PAGESTATUS state; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - frameNum += pTree->numPaddingFrames; - - _addrtreeConvertLevelFrameToNodeIndex(pTree, levelNum, - frameNum, &pNode, &index); - - state = _addrtreeGetState(pTree, pNode, index, bReadAttrib); - return state; -} - - -void pmaAddrtreeGetSize -( - void *pMap, - NvU64 *pBytesTotal -) -{ - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - *pBytesTotal = (pTree->totalFrames << PMA_PAGE_SHIFT); -} - -// -// The algorithm here is very simplistic. But maybe that's OK because this call -// is not used a whole lot. We can optimize it but might not worth the effort. -// -void pmaAddrtreeGetLargestFree -( - void *pMap, - NvU64 *pLargestFree -) -{ - NvU64 i, length = 0, largestLength = 0; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - for (i = 0; i < pTree->totalFrames; i++) - { - if (pmaAddrtreeRead(pTree, i, NV_FALSE) != STATE_FREE) - { - largestLength = NV_MAX(length, largestLength); - length = 0; - } - else - { - length++; - } - } - - largestLength = NV_MAX(length, largestLength); - *pLargestFree = (largestLength << PMA_PAGE_SHIFT); -} - -// -// Check whether the specified frame range is available completely for eviction -// -// Returns: -// - -1 if the whole range is evictable -// -// - Index of the last unevictable frame number -// -// For now, just do a dumb scan frame by frame -static NvS64 -_pmaAddrtreeScanNumaUnevictable -( - PMA_ADDRTREE *pTree, - NvU64 frameBegin, - NvU64 frameEnd -) -{ - NvU64 frame; - PMA_PAGESTATUS frameStatus; - - for(frame = frameEnd; frame >= frameBegin; frame--) - { - frameStatus = pmaAddrtreeRead((void*)pTree, frame, NV_TRUE); - if (frameStatus != STATE_UNPIN) - { - return frame; - } - } - return -1; -} - -// -// Determine a contiguous evictable range of size actualSize -// -// Returns: -// - NV_ERR_NO_MEMORY if eviction is not possible for this size -// -// - NV_OK if there is a valid contiguous evictable range -// starting and ending at address stored at evictStart and evictEnd -// -// - -NV_STATUS pmaAddrtreeScanContiguousNumaEviction -( - void *pMap, - NvU64 addrBase, - NvLength actualSize, - NvU64 pageSize, - NvU64 *evictStart, - NvU64 *evictEnd -) -{ - NV_STATUS status = NV_ERR_NO_MEMORY; - PMA_ADDRTREE *pTree = (PMA_ADDRTREE *)pMap; - - NvU64 alignedAddrBase; - NvU64 frameNum; - NvU64 endFrame, frameStart; - NvU64 alignment = pageSize; - NvU64 frameAlignment, frameAlignmentPadding; - NvU64 numFrames = actualSize >> PMA_PAGE_SHIFT; - NvU64 framesToSkip; - NvU32 level = addrtreeGetTreeLevel(_PMA_64KB) - 1; - PMA_PAGESTATUS startStatus, endStatus; - - endFrame = pTree->totalFrames - 1; - - if (pTree->totalFrames < numFrames) - return status; - - // Copied from _pmaAddrtreeContigSearchLoop, pmaRegmapScanContiguous - // We need to do this one the 64K frame level because addrtree will currently - // qualify a 2MB node that is half unpin and half free as entirely - // unpin, which doesn't work in NUMA mode because PMA cannot ask - // UVM to evict free pages in NUMA mode - - frameAlignment = alignment >> PMA_PAGE_SHIFT; - alignedAddrBase = NV_ALIGN_UP(addrBase, alignment); - // May need to modify to work with internal address tree padding - frameAlignmentPadding = (alignedAddrBase - addrBase) >> PMA_PAGE_SHIFT; - frameStart = alignUpToMod(0, frameAlignment, frameAlignmentPadding); - - for (frameNum = frameStart; frameNum <= endFrame; ) - { - NvS64 firstUnevictableFrame; - NvU64 endFrame = frameNum + numFrames - 1; - - // - // Read endStatus first so we don't have to waste time traversing the - // tree again to read startStatus if endStatus is not even usable - // - endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, endFrame, STATE_UNPIN, NV_FALSE, &framesToSkip, NV_FALSE); - - if (framesToSkip > 1) { - frameNum = NV_ALIGN_UP(endFrame + framesToSkip, frameAlignment); - NV_ASSERT(frameNum != 0); - continue; - } - - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, frameNum, STATE_UNPIN, NV_FALSE, &framesToSkip, NV_FALSE); - - if (framesToSkip > 1) { - frameNum += NV_ALIGN_UP(framesToSkip, frameAlignment); - NV_ASSERT(frameNum != 0); - continue; - } - - // Check against the whole state since we've already ready that in addrtree - if (endStatus != STATE_UNPIN) - { - // end is not available jump from start to after numFrames - frameNum += numFrames; - frameNum = alignUpToMod(frameNum, frameAlignment, frameAlignmentPadding); - continue; - } - - if (startStatus != STATE_UNPIN) - { - // startFrame is unavailable, jump to next aligned frame - frameNum += frameAlignment; - continue; - } - - // First occurrence of 0 in STATE_UNPIN from frameNum to frameNum + numFrames - 1 - firstUnevictableFrame = _pmaAddrtreeScanNumaUnevictable(pMap, frameNum, frameNum + numFrames - 1); - - if (firstUnevictableFrame == -1) - { - NV_PRINTF(LEVEL_INFO, " %s evictable frame = %lld evictstart = %llx evictEnd = %llx\n", - __FUNCTION__, frameNum, addrBase + (frameNum << PMA_PAGE_SHIFT), - (addrBase + (frameNum << PMA_PAGE_SHIFT) + actualSize - 1)); - - // Subtract off padding when returning - *evictStart = addrBase + (frameNum << PMA_PAGE_SHIFT) - (pTree->numPaddingFrames << PMA_PAGE_SHIFT); - *evictEnd = *evictStart + actualSize - 1; - status = NV_OK; - break; - } - else - { - // get the next aligned frame after the unevictable frame. - frameNum = alignUpToMod(firstUnevictableFrame + 1, frameAlignment, frameAlignmentPadding); - } - } - - return status; - -} - -NvU64 pmaAddrtreeGetEvictingFrames(void *pMap) -{ - return ((PMA_ADDRTREE *)pMap)->frameEvictionsInProcess; -} - -void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess) -{ - ((PMA_ADDRTREE *)pMap)->frameEvictionsInProcess = frameEvictionsInProcess; -} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c index 97e8495128..f087d8ee46 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c @@ -651,7 +651,7 @@ NV_STATUS pmaNumaAllocate status = NV_ERR_NO_MEMORY; break; } - pPma->pMapInfo->pmaMapChangeStateAttribEx(pMap, frameOffset, allocOption, MAP_MASK); + pPma->pMapInfo->pmaMapChangeStateAttrib(pMap, frameOffset, allocOption, MAP_MASK); } if (status != NV_OK) break; @@ -743,14 +743,14 @@ void pmaNumaFreeInternal // if (currentStatus & STATE_UNPIN) { - pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), - ATTRIB_NUMA_REUSE, ATTRIB_NUMA_REUSE); + pPma->pMapInfo->pmaMapChangeStateAttrib(pPma->pRegions[regId], (frameNum + j), + ATTRIB_NUMA_REUSE, ATTRIB_NUMA_REUSE); } continue; } sysPagePhysAddr = sysPhysAddr + (j << PMA_PAGE_SHIFT); osAllocReleasePage(sysPagePhysAddr, 1 << (PMA_PAGE_SHIFT - osPageShift)); - pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), newStatus, ~ATTRIB_EVICTING); + pPma->pMapInfo->pmaMapChangeStateAttrib(pPma->pRegions[regId], (frameNum + j), newStatus, ~ATTRIB_EVICTING); } } } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c index 7f9de3982d..e5c8ccc73f 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c @@ -97,7 +97,7 @@ _pmaRollback for (j = 0; j < framesPerPage; j++) { - pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), oldState, STATE_MASK); + pPma->pMapInfo->pmaMapChangeStateAttrib(pPma->pRegions[regId], (frameNum + j), oldState, STATE_MASK); } } } @@ -110,7 +110,7 @@ _pmaRollback frameNum = PMA_ADDR2FRAME(pPages[failCount], addrBase); for(i = 0; i < failFrame; i++) { - pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + i), oldState, STATE_MASK); + pPma->pMapInfo->pmaMapChangeStateAttrib(pPma->pRegions[regId], (frameNum + i), oldState, STATE_MASK); } } } @@ -208,8 +208,8 @@ pmaInitialize(PMA *pPma, NvU32 initFlags) // pMapInfo->pmaMapInit = pmaRegmapInit; pMapInfo->pmaMapDestroy = pmaRegmapDestroy; - pMapInfo->pmaMapChangeStateAttribEx = pmaRegmapChangeStateAttribEx; - pMapInfo->pmaMapChangePageStateAttribEx = pmaRegmapChangePageStateAttribEx; + pMapInfo->pmaMapChangeStateAttrib = pmaRegmapChangeStateAttrib; + pMapInfo->pmaMapChangePageStateAttrib = pmaRegmapChangePageStateAttrib; pMapInfo->pmaMapChangeBlockStateAttrib = pmaRegmapChangeBlockStateAttrib; pMapInfo->pmaMapRead = pmaRegmapRead; pMapInfo->pmaMapScanContiguous = pmaRegmapScanContiguous; @@ -239,25 +239,6 @@ pmaInitialize(PMA *pPma, NvU32 initFlags) pPma->bNuma = !!(initFlags & PMA_INIT_NUMA); pPma->bNumaAutoOnline = !!(initFlags & PMA_INIT_NUMA_AUTO_ONLINE); - - // If we want to run with address tree instead of regmap - if (initFlags & PMA_INIT_ADDRTREE) - { - pMapInfo->pmaMapInit = pmaAddrtreeInit; - pMapInfo->pmaMapDestroy = pmaAddrtreeDestroy; - pMapInfo->pmaMapChangeStateAttribEx = pmaAddrtreeChangeStateAttribEx; - pMapInfo->pmaMapChangePageStateAttribEx = pmaAddrtreeChangePageStateAttribEx; - pMapInfo->pmaMapChangeBlockStateAttrib = pmaAddrtreeChangeBlockStateAttrib; - pMapInfo->pmaMapRead = pmaAddrtreeRead; - pMapInfo->pmaMapScanContiguous = pmaAddrtreeScanContiguous; - pMapInfo->pmaMapScanDiscontiguous = pmaAddrtreeScanDiscontiguous; - pMapInfo->pmaMapGetSize = pmaAddrtreeGetSize; - pMapInfo->pmaMapGetLargestFree = pmaAddrtreeGetLargestFree; - pMapInfo->pmaMapScanContiguousNumaEviction = pmaAddrtreeScanContiguousNumaEviction; - pMapInfo->pmaMapGetEvictingFrames = pmaAddrtreeGetEvictingFrames; - pMapInfo->pmaMapSetEvictingFrames = pmaAddrtreeSetEvictingFrames; - NV_PRINTF(LEVEL_WARNING, "Going to use addrtree for PMA init!!\n"); - } } pPma->pMapInfo = pMapInfo; @@ -834,15 +815,6 @@ pmaAllocatePages curPages += numPagesAllocatedThisTime; numPagesLeftToAllocate -= numPagesAllocatedThisTime; - // - // PMA must currently catch addrtree shortcomings and fail the request - // Just follow the no memory path for now to properly release locks - // - if (status == NV_ERR_INVALID_ARGUMENT) - { - status = NV_ERR_NO_MEMORY; - } - if (status == NV_ERR_IN_USE && !tryEvict) { // @@ -1097,12 +1069,14 @@ pmaAllocatePages } else { - NvU64 frameRangeStart = 0; - NvU64 lastFrameRangeEnd = 0; + NvU64 frameRangeStart = 0; + NvU64 nextExpectedFrame = 0; + NvU32 frameRangeRegId = 0; NvU64 frameBase = 0; (void)frameRangeStart; //Silence the compiler - (void)lastFrameRangeEnd; + (void)nextExpectedFrame; + (void)frameRangeRegId; NV_PRINTF(LEVEL_INFO, "Successfully allocated frames:\n"); @@ -1117,25 +1091,30 @@ pmaAllocatePages if (i == 0) { frameRangeStart = frameBase; + frameRangeRegId = regId; } - else if ((lastFrameRangeEnd + 1) != frameBase) + else if ((frameRangeRegId != regId) || (nextExpectedFrame != frameBase)) { // Break in frame range detected - NV_PRINTF(LEVEL_INFO, "0x%llx through 0x%llx \n", - frameRangeStart, - lastFrameRangeEnd); + NV_PRINTF(LEVEL_INFO, "0x%llx through 0x%llx region %d \n", + reverseFlag ? nextExpectedFrame + framesPerPage : frameRangeStart, + reverseFlag ? frameRangeStart + framesPerPage - 1 : nextExpectedFrame - 1, + frameRangeRegId); frameRangeStart = frameBase; + frameRangeRegId = regId; } - lastFrameRangeEnd = frameBase + framesPerPage - 1; + nextExpectedFrame = reverseFlag ? frameBase - framesPerPage : frameBase + framesPerPage; - pPma->pMapInfo->pmaMapChangePageStateAttribEx(pMap, PMA_ADDR2FRAME(pPages[i], addrBase), + pPma->pMapInfo->pmaMapChangePageStateAttrib(pMap, PMA_ADDR2FRAME(pPages[i], addrBase), pageSize, pinOption, MAP_MASK); } - NV_PRINTF(LEVEL_INFO, "0x%llx through 0x%llx \n", - frameRangeStart, - frameBase + framesPerPage - 1); + // Break in frame range detected + NV_PRINTF(LEVEL_INFO, "0x%llx through 0x%llx region %d \n", + reverseFlag ? nextExpectedFrame + framesPerPage : frameRangeStart, + reverseFlag ? frameRangeStart + framesPerPage - 1 : nextExpectedFrame - 1, + frameRangeRegId); } } @@ -1262,7 +1241,7 @@ pmaPinPages } else { - pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), STATE_PIN, STATE_MASK); + pPma->pMapInfo->pmaMapChangeStateAttrib(pPma->pRegions[regId], (frameNum + j), STATE_PIN, STATE_MASK); } } } @@ -1273,59 +1252,6 @@ pmaPinPages return status; } - -NV_STATUS -pmaUnpinPages -( - PMA *pPma, - NvU64 *pPages, - NvLength pageCount, - NvU64 pageSize -) -{ - NvU32 framesPerPage, regId, i, j; - NvU64 frameNum, addrBase; - PMA_PAGESTATUS state; - framesPerPage = (NvU32)(pageSize >> PMA_PAGE_SHIFT); - - if (pPma == NULL || pageCount == 0 || pPages == NULL - || (pageSize != _PMA_64KB && pageSize != _PMA_128KB && pageSize != _PMA_2MB && pageSize != _PMA_512MB)) - { - return NV_ERR_INVALID_ARGUMENT; - } - - portSyncSpinlockAcquire(pPma->pPmaLock); - - for(i = 0; i < pageCount; i++) - { - regId = findRegionID(pPma, pPages[i]); - addrBase = pPma->pRegDescriptors[regId]->base; - frameNum = PMA_ADDR2FRAME(pPages[i], addrBase); - - for (j = 0; j < framesPerPage; j++) - { - state = pPma->pMapInfo->pmaMapRead(pPma->pRegions[regId], (frameNum + j), NV_FALSE); - if (state != STATE_PIN) - { - NV_PRINTF(LEVEL_ERROR, "Unpin failed at %dth page %dth frame\n", - i, j); - _pmaRollback(pPma, pPages, i, j, pageSize, STATE_PIN); - portSyncSpinlockRelease(pPma->pPmaLock); - return NV_ERR_INVALID_STATE; - } - else - { - pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), STATE_UNPIN, STATE_MASK); - } - } - } - - portSyncSpinlockRelease(pPma->pPmaLock); - - return NV_OK; -} - - void pmaFreePages ( @@ -1407,7 +1333,7 @@ pmaFreePages // Reset everything except for the (ATTRIB_EVICTING and ATTRIB_BLACKLIST) state to support memory being freed // after being picked for eviction. // - pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + j), newStatus, ~(ATTRIB_EVICTING | ATTRIB_BLACKLIST)); + pPma->pMapInfo->pmaMapChangeStateAttrib(pPma->pRegions[regId], (frameNum + j), newStatus, ~(ATTRIB_EVICTING | ATTRIB_BLACKLIST)); } } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c index bd6fddecf0..793be0b9f0 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c @@ -278,7 +278,7 @@ pmaSetBlockStateAttribUnderPmaLock for (i = 0; i < numFrames; i++) { - pPma->pMapInfo->pmaMapChangeStateAttribEx(pMap, (baseFrame + i), pmaState, pmaStateWriteMask); + pPma->pMapInfo->pmaMapChangeStateAttrib(pMap, (baseFrame + i), pmaState, pmaStateWriteMask); } } @@ -419,8 +419,8 @@ _pmaCleanupNumaReusePages if (currentStatus & ATTRIB_NUMA_REUSE) { osAllocReleasePage(sysPagePhysAddr, 1 << (PMA_PAGE_SHIFT - osPageShift)); - pPma->pMapInfo->pmaMapChangeStateAttribEx(pPma->pRegions[regId], (frameNum + i), - STATE_FREE, (STATE_MASK | ATTRIB_NUMA_REUSE)); + pPma->pMapInfo->pmaMapChangeStateAttrib(pPma->pRegions[regId], (frameNum + i), + STATE_FREE, (STATE_MASK | ATTRIB_NUMA_REUSE)); } } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c index 0c1043404f..c9e6846387 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c @@ -463,7 +463,7 @@ pmaRegmapDestroy(void *pMap) // STATE_MASK, ATTRIB_MASK // void -pmaRegmapChangeStateAttribEx +pmaRegmapChangeStateAttrib ( void *pMap, NvU64 frameNum, @@ -475,7 +475,7 @@ pmaRegmapChangeStateAttribEx } void -pmaRegmapChangePageStateAttribEx +pmaRegmapChangePageStateAttrib ( void * pMap, NvU64 startFrame, diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c b/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c index a84a866b36..84ee780212 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/sec2_utils.c @@ -30,7 +30,6 @@ #include "core/prelude.h" #include "core/locks.h" #include "gpu/mem_mgr/sec2_utils.h" -#include "gpu/subdevice/subdevice.h" #include "kernel/gpu/mem_mgr/ce_utils_sizes.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "nvrm_registry.h" @@ -287,8 +286,8 @@ sec2utilsDestruct_IMPL { OBJCHANNEL *pChannel = pSec2Utils->pChannel; OBJGPU *pGpu = pSec2Utils->pGpu; - MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + MemoryManager *pMemoryManager = NULL; + RM_API *pRmApi = NULL; // Sanity checks if ((pGpu == NULL) || (pChannel == NULL)) @@ -302,6 +301,9 @@ sec2utilsDestruct_IMPL return; } + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + ccslContextClear(pSec2Utils->pCcslCtx); if ((pChannel->bClientUserd) && (pChannel->pControlGPFifo != NULL)) @@ -591,7 +593,7 @@ sec2utilsMemset_IMPL do { NvU64 maxContigSize = bContiguous ? memsetLength : (pageGranularity - offset % pageGranularity); - NvU32 memsetSizeContig = (NvU32)NV_MIN(NV_MIN(memsetLength, maxContigSize), NVCBA2_DECRYPT_COPY_SIZE_MAX_BYTES); + NvU32 memsetSizeContig = (NvU32)NV_MIN(NV_MIN(memsetLength, maxContigSize), NVCBA2_DECRYPT_SCRUB_SIZE_MAX_BYTES); channelPbInfo.dstAddr = memdescGetPhysAddr(pMemDesc, AT_GPU, offset); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c b/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c index be0b05467f..e1a8008409 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/sem_surf.c @@ -24,6 +24,7 @@ #include "gpu/mem_mgr/sem_surf.h" #include "os/os.h" // NV_MEMORY_NONCONTIGUOUS, osEventNotification #include "gpu/device/device.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_desc.h" #include "gpu/gpu.h" @@ -63,16 +64,20 @@ _semsurfUnregisterCallback ) { RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvU32 i; - if ((pShared->hClient != NV01_NULL_OBJECT) && - (pShared->hEvent != NV01_NULL_OBJECT)) + if ((pShared->hClient != NV01_NULL_OBJECT) && (pShared->phEvents != NULL)) { - pRmApi->Free(pRmApi, - pShared->hClient, - pShared->hEvent); + for (i = 0; i < pShared->numEvents; i++) + { + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->phEvents[i]); + } } - pShared->hEvent = NV01_NULL_OBJECT; + portMemFree(pShared->phEvents); + pShared->phEvents = NULL; } static NvU64 @@ -323,7 +328,7 @@ _semsurfEventCallback NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Got a callback\n", pShared->hClient, pShared->hSemaphoreMem); NV_PRINTF(LEVEL_INFO, " hEvent: 0x%08x surf event: 0x%08x, data 0x%08x, status 0x%08x\n", - hEvent, pShared->hEvent, data, status); + hEvent, hEvent, data, status); while (valuesChanged) { @@ -538,28 +543,105 @@ _semsurfRegisterCallback SEM_SHARED_DATA *pShared = pSemSurf->pShared; NV0005_ALLOC_PARAMETERS nv0005AllocParams; RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + static const NvU32 eventNotifiers[] = + { + NV2080_NOTIFIERS_GR0, // NV2080_NOTIFIERS_GRAPHICS + NV2080_NOTIFIERS_GR1, + NV2080_NOTIFIERS_GR2, + NV2080_NOTIFIERS_GR3, + NV2080_NOTIFIERS_GR4, + NV2080_NOTIFIERS_GR5, + NV2080_NOTIFIERS_GR6, + NV2080_NOTIFIERS_GR7, + NV2080_NOTIFIERS_PPP, + NV2080_NOTIFIERS_VLD, + NV2080_NOTIFIERS_NVDEC0, + NV2080_NOTIFIERS_NVDEC1, + NV2080_NOTIFIERS_NVDEC2, + NV2080_NOTIFIERS_NVDEC3, + NV2080_NOTIFIERS_NVDEC4, + NV2080_NOTIFIERS_NVDEC5, + NV2080_NOTIFIERS_NVDEC6, + NV2080_NOTIFIERS_NVDEC7, + NV2080_NOTIFIERS_PDEC, + NV2080_NOTIFIERS_CE0, + NV2080_NOTIFIERS_CE1, + NV2080_NOTIFIERS_CE2, + NV2080_NOTIFIERS_CE3, + NV2080_NOTIFIERS_CE4, + NV2080_NOTIFIERS_CE5, + NV2080_NOTIFIERS_CE6, + NV2080_NOTIFIERS_CE7, + NV2080_NOTIFIERS_CE8, + NV2080_NOTIFIERS_CE9, + NV2080_NOTIFIERS_MSENC, + NV2080_NOTIFIERS_NVENC0, + NV2080_NOTIFIERS_NVENC1, + NV2080_NOTIFIERS_NVENC2, + NV2080_NOTIFIERS_SEC2, + NV2080_NOTIFIERS_NVJPEG0, // NV2080_NOTIFIERS_NVJPG + NV2080_NOTIFIERS_NVJPEG1, + NV2080_NOTIFIERS_NVJPEG2, + NV2080_NOTIFIERS_NVJPEG3, + NV2080_NOTIFIERS_NVJPEG4, + NV2080_NOTIFIERS_NVJPEG5, + NV2080_NOTIFIERS_NVJPEG6, + NV2080_NOTIFIERS_NVJPEG7, + NV2080_NOTIFIERS_OFA0, // NV2080_NOTIFIERS_OFA + NV2080_NOTIFIERS_FIFO_EVENT_MTHD, + }; + NV_STATUS status = NV_OK; + NvU32 i; + NvU32 j; + + pShared->numEvents = NV_ARRAY_ELEMENTS(eventNotifiers); + pShared->phEvents = portMemAllocNonPaged(pShared->numEvents * + sizeof(*pShared->phEvents)); + NV_ASSERT_OR_RETURN(pShared->phEvents != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pShared->phEvents, 0, sizeof(*pShared->phEvents) * pShared->numEvents); pShared->callback.func = _semsurfEventCallback; pShared->callback.arg = pShared; portMemSet(&nv0005AllocParams, 0, sizeof(nv0005AllocParams)); nv0005AllocParams.hParentClient = pShared->hClient; nv0005AllocParams.hClass = NV01_EVENT_KERNEL_CALLBACK_EX; - nv0005AllocParams.notifyIndex = NV2080_NOTIFIERS_FIFO_EVENT_MTHD | - NV01_EVENT_NONSTALL_INTR | - NV01_EVENT_WITHOUT_EVENT_DATA | - NV01_EVENT_SUBDEVICE_SPECIFIC | - DRF_NUM(0005, _NOTIFY_INDEX, _SUBDEVICE, - gpumgrGetSubDeviceInstanceFromGpu(GPU_RES_GET_GPU(pSemSurf))); nv0005AllocParams.data = NV_PTR_TO_NvP64(&pShared->callback); + for (i = 0; i < pShared->numEvents; i++) + { + nv0005AllocParams.notifyIndex = eventNotifiers[i] | + NV01_EVENT_NONSTALL_INTR | + NV01_EVENT_WITHOUT_EVENT_DATA | + NV01_EVENT_SUBDEVICE_SPECIFIC | + DRF_NUM(0005, _NOTIFY_INDEX, _SUBDEVICE, + gpumgrGetSubDeviceInstanceFromGpu(GPU_RES_GET_GPU(pSemSurf))); + + status = pRmApi->Alloc(pRmApi, + pShared->hClient, + pShared->hSubDevice, + &pShared->phEvents[i], + NV01_EVENT_KERNEL_CALLBACK_EX, + &nv0005AllocParams, + sizeof(nv0005AllocParams)); + + NV_ASSERT_OR_GOTO(status == NV_OK, eventAllocFailed); + } - return pRmApi->Alloc(pRmApi, - pShared->hClient, - pShared->hSubDevice, - &pShared->hEvent, - NV01_EVENT_KERNEL_CALLBACK_EX, - &nv0005AllocParams, - sizeof(nv0005AllocParams)); + return status; + +eventAllocFailed: + for (j = 0; j < i; j++) + { + pRmApi->Free(pRmApi, + pShared->hClient, + pShared->phEvents[j]); + } + + portMemFree(pShared->phEvents); + pShared->phEvents = NULL; + + return status; } static NV_STATUS @@ -650,9 +732,7 @@ _semsurfValidateIndex NvU64 index ) { - const NvU64 slotSize = pShared->layout.size; - - if (((index * slotSize) + slotSize) <= pShared->pSemaphoreMem->pMemDesc->Size) + if (index < pShared->slotCount) return NV_TRUE; else return NV_FALSE; @@ -745,6 +825,8 @@ semsurfConstruct_IMPL 0), ctorFailed); + pShared->slotCount = pShared->pSemaphoreMem->pMemDesc->Size / pShared->layout.size; + pShared->pSem = KERNEL_POINTER_FROM_NvP64(NvU8 *, pShared->semKernAddr); if (!pShared->bIs64Bit) @@ -773,6 +855,9 @@ semsurfConstruct_IMPL 0), ctorFailed); + pShared->slotCount = + NV_MIN(pShared->slotCount, pShared->pMaxSubmittedMem->pMemDesc->Size / pShared->layout.size); + pShared->pMaxSubmitted = KERNEL_POINTER_FROM_NvP64(NvU8 *, pShared->maxSubmittedKernAddr); } @@ -1159,6 +1244,9 @@ _semsurfAddWaiter return NV_ERR_INVALID_STATE; } + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Entering spinlock\n", + pSemSurf->pShared->hClient, + pSemSurf->pShared->hSemaphoreMem); portSyncSpinlockAcquire(pSemSurf->pShared->pSpinlock); pIndexListeners = mapFind(&pSemSurf->pShared->listenerMap, index); @@ -1379,14 +1467,16 @@ _semsurfAddWaiter } portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); NV_PRINTF(LEVEL_INFO, "SemSurf(0x%08x, 0x%08x): " "Registered semaphore surface value listener at index %" NvU64_fmtu ", value %" NvU64_fmtu " current value %" NvU64_fmtu - " post-wait value %" NvU64_fmtu " notification: %" NvU64_fmtx "\n", + " post-wait value %" NvU64_fmtu " notification: " NvP64_fmt "\n", hClient, hSemaphoreSurf, index, waitValue, semValue, newValue, - (NvU64)notificationHandle); + notificationHandle); return rmStatus; @@ -1412,6 +1502,8 @@ _semsurfAddWaiter } portSyncSpinlockRelease(pSemSurf->pShared->pSpinlock); + NV_PRINTF(LEVEL_INFO, "SemMem(0x%08x, 0x%08x): Exited spinlock\n", + pSemSurf->pShared->hClient, pSemSurf->pShared->hSemaphoreMem); // There's no point of going through the trouble of notifying the waiter in // this case, but it is worth immediately running the auto-update code here @@ -1639,3 +1731,24 @@ semsurfCtrlCmdUnregisterWaiter_IMPL return rmStatus; } + +NvU64 +semsurfGetValue_IMPL +( + SemaphoreSurface *pSemSurf, + NvU64 index +) +{ + NV_ASSERT_OR_RETURN(_semsurfValidateIndex(pSemSurf->pShared, index), 0); + return _semsurfGetValue(pSemSurf->pShared, index); +} + +NvBool +semsurfValidateIndex_IMPL +( + SemaphoreSurface *pSemSurf, + NvU64 index +) +{ + return _semsurfValidateIndex(pSemSurf->pShared, index); +} diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c index 9b96cc81f4..c41c5bb690 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c @@ -41,7 +41,8 @@ #include "vgpu/rpc.h" /* ------------------ static and helper functions prototypes------------------*/ -static NvU32 translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *translatedFlags); +static NvU32 translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *translatedFlags, + NvBool bKernelClient, NvU32 gfid); static NvU32 translatePageSizeToVASpaceFlags(NV_VASPACE_ALLOCATION_PARAMETERS *pNvVASpaceAllocParams); static NV_STATUS _vaspaceapiManagePageLevelsForSplitVaSpace(OBJGPU *pGpu, Device *pDevice, NvU32 gpuMask, NvU32 flags, VASPACEAPI_MANAGE_PAGE_LEVELS_ACTION action); @@ -80,6 +81,7 @@ vaspaceapiConstruct_IMPL KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvU64 originalVaBase; NvU64 originalVaSize; + NvU32 gfid = 0; if (RS_IS_COPY_CTOR(pParams)) { @@ -96,6 +98,9 @@ vaspaceapiConstruct_IMPL return status; } + if (gpuIsSriovEnabled(pGpu)) + NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); + pNvVASpaceAllocParams = pParams->pAllocParams; allocFlags = pNvVASpaceAllocParams->flags; @@ -104,7 +109,10 @@ vaspaceapiConstruct_IMPL originalVaSize = pNvVASpaceAllocParams->vaSize; // Translate & validate flags - NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, translateAllocFlagsToVASpaceFlags(allocFlags, &flags)); + NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, + translateAllocFlagsToVASpaceFlags(allocFlags, &flags, + (pCallContext->secInfo.privLevel >= + RS_PRIV_LEVEL_KERNEL), gfid)); // // Make sure this GPU is not already locked by this thread @@ -306,7 +314,8 @@ vaspaceapiConstruct_IMPL memmgrIsPmaInitialized(pMemoryManager) && memmgrAreClientPageTablesPmaManaged(pMemoryManager) && !(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED) && - !(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_FLA)) + !(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_IS_FLA) && + !(allocFlags & NV_VASPACE_ALLOCATION_FLAGS_PTETABLE_HEAP_MANAGED)) { flags |= VASPACE_FLAGS_PTETABLE_PMA_MANAGED; } @@ -539,7 +548,8 @@ vaspaceapiDestruct_IMPL(VaSpaceApi *pVaspaceApi) * @param[in] allocFlags Client handle * @param[out] translatedFlags The translated internal flags. **/ -static NV_STATUS translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *translatedFlags) +static NV_STATUS translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *translatedFlags, + NvBool bKernelClient, NvU32 gfid) { NV_STATUS status = NV_OK; NvU32 flags = 0; @@ -605,11 +615,21 @@ static NV_STATUS translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *tran (flags & VASPACE_FLAGS_SET_MIRRORED)), NV_ERR_INVALID_ARGUMENT); - // MODs environment requires ATS to be enabled but RM to continue to own - // page table management + // + // MODS environment requires ATS to be enabled but RM to continue to own + // page table management with PASID coming from the MODS OS layer. + // + // For production driver, PASID comes from UVM via NV0080_CTRL_DMA_SET_PAGE_DIRECTORY + // and so only VASPACE_FLAGS_IS_EXTERNALLY_OWNED or VASPACE_FLAGS_SHARED_MANAGEMENT is + // supported which is where NV0080_CTRL_DMA_SET_PAGE_DIRECTORY happens. + // ATS on VASPACE_FLAGS_SHARED_MANAGEMENT is allowed only when it is from + // kernel client(UVM) or for VF context (where vaspace is allocated in the host for a + // kernel client created vaspace within the VF's VM). + // NV_CHECK_OR_RETURN(LEVEL_WARNING, !((flags & VASPACE_FLAGS_ENABLE_ATS) && - !(flags & VASPACE_FLAGS_IS_EXTERNALLY_OWNED)), + !((flags & VASPACE_FLAGS_IS_EXTERNALLY_OWNED) || + ((flags & VASPACE_FLAGS_SHARED_MANAGEMENT) && (bKernelClient || IS_GFID_VF(gfid))))), NV_ERR_INVALID_ARGUMENT); // // 1766112: Prevent channels in fault-capable VAS from running unless bound @@ -721,7 +741,7 @@ _vaspaceapiManagePageLevelsForSplitVaSpace } else if (action == VASPACEAPI_MANAGE_PAGE_LEVELS_TRIM) { - rmMemPoolTrim(pMemPool, 0, flags); + rmMemPoolTrim(pMemPool, 1, flags); } } FOR_EACH_GPU_IN_MASK_UC_END diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator.c b/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator.c index 096f212e32..72181f78c7 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,7 +29,6 @@ #include "core/core.h" #include "core/hal.h" -#include "core/info_block.h" #include "nvrm_registry.h" #include "os/os.h" #include "vgpu/rpc.h" @@ -74,6 +73,9 @@ dmaInitRegistryOverrides(OBJGPU *pGpu, VirtMemAllocator *pDma) NV_STATUS rmStatus = NV_OK; NvU32 data32; +#if defined(DEBUG) || defined (DEVELOP) + pDma->bMemoryMapperApiEnabled = NV_TRUE; +#endif if (osReadRegistryDword(pGpu, NV_REG_ENABLE_MEMORY_MAPPER_API, &data32) == NV_OK && data32 == NV_REG_ENABLE_MEMORY_MAPPER_API_TRUE) { diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator_vgpu.c b/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator_vgpu.c index 07bc73bc79..c5f7c9ab81 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator_vgpu.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/virt_mem_allocator_vgpu.c @@ -30,9 +30,28 @@ #include "core/core.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/virt_mem_allocator.h" +#include "vgpu/rpc.h" +#include "gpu/device/device.h" NV_STATUS dmaConstructHal_VGPUSTUB(OBJGPU *pGpu, VirtMemAllocator *pDma) { return NV_OK; } + +// +// deviceCtrlCmdDmaFlush_VF +// +// Lock Requirements: +// Assert that API lock and GPUs lock held on entry +// +NV_STATUS +deviceCtrlCmdDmaFlush_VF +( + Device *pDevice, + NV0080_CTRL_DMA_FLUSH_PARAMS *flushParams +) +{ + NV_STATUS status = NV_OK; + return status; +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c index cbc9919de8..a8127110f9 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/ampere/kern_mem_sys_ga100.c @@ -26,10 +26,11 @@ #include "os/os.h" #include "kernel/gpu/mem_sys/kern_mem_sys.h" #include "kernel/gpu/mem_mgr/mem_mgr.h" -#include "kernel/gpu/subdevice/subdevice.h" #include "gpu/mem_mgr/mem_desc.h" +#include "ctrl/ctrl2080/ctrl2080fb.h" #include "published/ampere/ga100/dev_fb.h" +#include "published/ampere/ga100/hwproject.h" /*! * @brief Write the sysmemFlushBuffer val into the NV_PFB_NISO_FLUSH_SYSMEM_ADDR register @@ -186,9 +187,8 @@ kmemsysInitMIGMemoryPartitionTable_GA100 ) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); - if (!pMemorySystemConfig->bDisablePlcForCertainOffsetsBug3046774) + if (!pKernelMemorySystem->bDisablePlcForCertainOffsetsBug3046774) return NV_OK; NV_ASSERT_OK_OR_RETURN( @@ -441,3 +441,23 @@ kmemsysIsPagePLCable_GA100 return NV_TRUE; } } + +NvU16 +kmemsysGetMaximumBlacklistPages_GA100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV2080_CTRL_FB_DYNAMIC_BLACKLIST_MAX_PAGES; +} + +NvU32 +kmemsysGetMaxFbpas_GA100 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_SCAL_LITTER_NUM_FBPAS; +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c index f87dc9f9b2..4e8ecf781b 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/hopper/kern_mem_sys_gh100.c @@ -32,7 +32,6 @@ #include "nverror.h" #include "published/hopper/gh100/dev_fb.h" -#include "published/hopper/gh100/dev_ltc.h" #include "published/hopper/gh100/dev_fbpa.h" #include "published/hopper/gh100/dev_vm.h" #include "published/hopper/gh100/pri_nv_xal_ep.h" @@ -70,6 +69,20 @@ kmemsysDoCacheOp_GH100 return rmStatus; } + if (IS_VIRTUAL(pGpu)) + { + switch (reg) + { + case NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE: + case NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE: + break; + case NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY: + return NV_OK; + default: + return NV_ERR_NOT_SUPPORTED; + } + } + switch (reg) { case NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY: @@ -279,6 +292,10 @@ kmemsysCacheOp_GH100 break; case FB_CACHE_VIDEO_MEMORY: + // Fbmem cache ops are not supported from VF -- force NV_OK for MODS + if (IS_VIRTUAL(pGpu)) + return NV_OK; + if (cacheOp == FB_CACHE_EVICT) { NvU32 flags = NV2080_CTRL_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT_FLAGS_ALL | @@ -499,7 +516,7 @@ kmemsysNumaRemoveMemory_GH100 pKernelMemorySystem->memPartitionNumaInfo[swizzId].size = 0; pKernelMemorySystem->memPartitionNumaInfo[swizzId].numaNodeId = NV_U32_MAX; - NV_PRINTF(LEVEL_INFO, "NVRM: memory partition: %u removed successfully!\n", + NV_PRINTF(LEVEL_INFO, "memory partition: %u removed successfully!\n", swizzId); return; } @@ -593,169 +610,24 @@ kmemsysAssertFbAckTimeoutPending_GH100 #endif } - -/*! - * Utility function used to read registers and ignore PRI errors - */ -static NvU32 -_kmemsysReadRegAndMaskPriError +NvU32 +kmemsysGetEccDedCountSize_GH100 ( - OBJGPU *pGpu, - NvU32 regAddr -) -{ - NvU32 regVal; - - regVal = osGpuReadReg032(pGpu, regAddr); - if ((regVal & GPU_READ_PRI_ERROR_MASK) == GPU_READ_PRI_ERROR_CODE) - { - return 0; - } - - return regVal; -} -/* - * @brief Function that checks if ECC error occurred by reading various count - * registers/interrupt registers. This function is not floorsweeping-aware so - * PRI errors are ignored - */ -void -kmemsysCheckEccCounts_GH100 -( - OBJGPU *pGpu, + OBJGPU *pGpu, KernelMemorySystem *pKernelMemorySystem ) { - NvU32 dramCount = 0; - NvU32 mmuCount = 0; - NvU32 ltcCount = 0; - NvU32 pcieCount = 0; - NvU32 regVal; - for (NvU32 i = 0; i < NV_SCAL_LITTER_NUM_FBPAS; i++) - { - for (NvU32 j = 0; j < NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; j++) - { - // DRAM count read - dramCount += _kmemsysReadRegAndMaskPriError(pGpu, NV_PFB_FBPA_0_ECC_DED_COUNT(j) + (i * NV_FBPA_PRI_STRIDE)); - - // LTC count read - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + - (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE)); - ltcCount += DRF_VAL(_PLTCG_LTC0_LTS0, _L2_CACHE_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - } - } - - // L2TLB - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT); - mmuCount += DRF_VAL(_PFB_PRI_MMU, _L2TLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // HUBTLB - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT); - mmuCount += DRF_VAL(_PFB_PRI_MMU, _HUBTLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // FILLUNIT - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT); - mmuCount += DRF_VAL(_PFB_PRI_MMU, _FILLUNIT_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // PCIE RBUF - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_RBUF); - pcieCount += DRF_VAL(_XPL_DL, _ERR_COUNT_RBUF, _UNCORR_ERR, regVal); - - // PCIE SEQ_LUT - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_COUNT_SEQ_LUT); - pcieCount += DRF_VAL(_XPL_DL, _ERR_COUNT_SEQ_LUT, _UNCORR_ERR, regVal); - - // PCIE RE ORDER - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT); - pcieCount += DRF_VAL(_XAL_EP, _REORDER_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // PCIE P2PREQ - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT); - pcieCount += DRF_VAL(_XAL_EP, _P2PREQ_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); - - // PCIE XTL - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS); - if (regVal != 0) - { - pcieCount += 1; - } - - // PCIE XTL - regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS); - if (regVal != 0) - { - pcieCount += 1; - } - - // If counts > 0 or if poison interrupt pending, ECC error has occurred. - if (((dramCount + ltcCount + mmuCount + pcieCount) != 0) || - intrIsVectorPending_HAL(pGpu, GPU_GET_INTR(pGpu), NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT, NULL)) - { - nvErrorLog_va((void *)pGpu, UNRECOVERABLE_ECC_ERROR_ESCAPE, - "An uncorrectable ECC error detected " - "(possible firmware handling failure) " - "DRAM:%d, LTC:%d, MMU:%d, PCIE:%d", dramCount, ltcCount, mmuCount, pcieCount); - } + return NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; } -/* - * @brief Function that clears ECC error count registers. - */ -NV_STATUS -kmemsysClearEccCounts_GH100 +NvU32 +kmemsysGetEccDedCountRegAddr_GH100 ( - OBJGPU *pGpu, - KernelMemorySystem *pKernelMemorySystem + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 fbpa, + NvU32 subp ) { - NvU32 regVal = 0; - RMTIMEOUT timeout; - NV_STATUS status = NV_OK; - - gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu); - - for (NvU32 i = 0; i < NV_SCAL_LITTER_NUM_FBPAS; i++) - { - for (NvU32 j = 0; j < NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; j++) - { - osGpuWriteReg032(pGpu, NV_PFB_FBPA_0_ECC_DED_COUNT(j) + (i * NV_FBPA_PRI_STRIDE), 0); - osGpuWriteReg032(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE), 0); - } - } - - // Reset MMU counts - osGpuWriteReg032(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT, 0); - osGpuWriteReg032(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT, 0); - osGpuWriteReg032(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT, 0); - - // Reset XAL-EP counts - osGpuWriteReg032(pGpu, NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT, 0); - osGpuWriteReg032(pGpu, NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT, 0); - - // Reset XTL-EP status registers - osGpuWriteReg032(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_DED_ERROR_STATUS, ~0); - osGpuWriteReg032(pGpu, NV_XTL_BASE_ADDRESS + NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS, ~0); - - // Reset XPL-EP error counters - regVal = DRF_DEF(_XPL, _DL_ERR_RESET, _RBUF_UNCORR_ERR_COUNT, _PENDING) | - DRF_DEF(_XPL, _DL_ERR_RESET, _SEQ_LUT_UNCORR_ERR_COUNT, _PENDING); - osGpuWriteReg032(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_RESET, regVal); - - // Wait for the error counter reset to complete - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - for (;;) - { - status = gpuCheckTimeout(pGpu, &timeout); - - regVal = osGpuReadReg032(pGpu, NV_XPL_BASE_ADDRESS + NV_XPL_DL_ERR_RESET); - - if (FLD_TEST_DRF(_XPL, _DL_ERR_RESET, _RBUF_UNCORR_ERR_COUNT, _DONE, regVal) && - FLD_TEST_DRF(_XPL, _DL_ERR_RESET, _SEQ_LUT_UNCORR_ERR_COUNT, _DONE, regVal)) - break; - - if (status != NV_OK) - return status; - } - - return NV_OK; + return NV_PFB_FBPA_0_ECC_DED_COUNT(fbpa) + (subp * NV_FBPA_PRI_STRIDE); } diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c index c2b6d43de4..a41c80b945 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm107.c @@ -26,12 +26,12 @@ #include "os/os.h" #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/mem_mgr/mem_desc.h" - -#include "gpu/device/device.h" +#include "ctrl/ctrl2080/ctrl2080fb.h" #include "published/maxwell/gm107/dev_fb.h" #include "published/maxwell/gm107/dev_bus.h" #include "published/maxwell/gm107/dev_flush.h" +#include "published/maxwell/gm107/dev_fifo.h" // Based on busFlushSingle_GM107 @@ -51,6 +51,20 @@ kmemsysDoCacheOp_GM107 NV_STATUS timeoutStatus = NV_OK; NvU32 regValueRead = 0; + if (IS_VIRTUAL(pGpu)) + { + switch (reg) + { + case NV_UFLUSH_L2_PEERMEM_INVALIDATE: + case NV_UFLUSH_L2_SYSMEM_INVALIDATE: + break; + case NV_UFLUSH_L2_FLUSH_DIRTY: + return NV_OK; + default: + return NV_ERR_NOT_SUPPORTED; + } + } + if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu)) { // @@ -63,7 +77,7 @@ kmemsysDoCacheOp_GM107 // We don't want this breakpoint when a debug build is being used by special test // equipment (e.g. ATE) that expects to hit this situation. Bug 672073 #ifdef DEBUG - if (!(API_GPU_IN_RESET_SANITY_CHECK(pGpu))) + if (!(API_GPU_IN_RESET_SANITY_CHECK(pGpu)) && !IS_VIRTUAL(pGpu)) { NV_ASSERT(GPU_REG_RD32(pGpu, NV_UFLUSH_FB_FLUSH) == 0); NV_ASSERT(kmemsysReadL2SysmemInvalidateReg_HAL(pGpu, pKernelMemorySystem) == 0); @@ -132,7 +146,7 @@ kmemsysDoCacheOp_GM107 } #ifdef DEBUG - if (cnt > 1) + if (cnt > 1 && !IS_VIRTUAL(pGpu)) { NvU32 intr0 = 0; intr0 = GPU_REG_RD32(pGpu, NV_PBUS_INTR_0); @@ -353,7 +367,7 @@ kmemsysInitFlushSysmemBuffer_GM107 // non-fatal till a proper WAR is implemented. Bug 2423129 had // this issue. // - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_WINDOWS) { bMakeItFatal = NV_FALSE; } @@ -426,3 +440,34 @@ kmemsysGetFlushSysmemBufferAddrShift_GM107 { return NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT; } + +NvU16 +kmemsysGetMaximumBlacklistPages_GM107 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES; +} + +/*! + * @brief Do any operations to get ready for a XVE sw reset. + * + * Set the PFIFO_FB_IFACE to DISABLE + * + * @return NV_OK + */ +NV_STATUS +kmemsysPrepareForXVEReset_GM107 +( + POBJGPU pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + GPU_REG_WR32(pGpu, NV_PFIFO_FB_IFACE, + DRF_DEF(_PFIFO, _FB_IFACE, _CONTROL, _DISABLE) | + DRF_DEF(_PFIFO, _FB_IFACE, _STATUS, _DISABLED)); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm200.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm200.c index ccaed118f8..acc0708564 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm200.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/maxwell/kern_mem_sys_gm200.c @@ -113,6 +113,10 @@ kmemsysCacheOp_GM200 } break; case FB_CACHE_VIDEO_MEMORY: + // Fbmem cache ops are not supported from VF -- force NV_OK for MODS + if (IS_VIRTUAL(pGpu)) + return NV_OK; + if (cacheOp == FB_CACHE_EVICT) { status = kmemsysSendL2InvalidateEvict(pGpu, pKernelMemorySystem, diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c index ad3938bfa1..5bdc3550c1 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -22,10 +22,18 @@ */ #include "core/core.h" +#include "g_kern_mem_sys_nvoc.h" #include "gpu/gpu.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/bif/kernel_bif.h" +#include "nvtypes.h" #include "published/turing/tu102/dev_vm.h" +#include "published/turing/tu102/hwproject.h" +#include "published/turing/tu102/dev_fbpa.h" +#include "published/turing/tu102/dev_fb.h" +#include "published/turing/tu102/dev_ltc.h" void kmemsysWriteL2SysmemInvalidateReg_TU102 @@ -68,3 +76,114 @@ kmemsysReadL2PeermemInvalidateReg_TU102 { return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_L2_PEERMEM_INVALIDATE); } + +NvU32 +kmemsysGetMaxFbpas_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_SCAL_LITTER_NUM_FBPAS; +} + +NvU32 kmemsysGetEccDedCountSize_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1; +} + +NvU32 kmemsysGetEccDedCountRegAddr_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 fbpa, + NvU32 subp +) +{ + return NV_PFB_FBPA_0_ECC_DED_COUNT(fbpa) + (subp * NV_FBPA_PRI_STRIDE); +} + +/*! + * Utility function used to read registers and ignore PRI errors + */ +static NvU32 +_kmemsysReadRegAndMaskPriError +( + OBJGPU *pGpu, + NvU32 regAddr +) +{ + NvU32 regVal; + + regVal = osGpuReadReg032(pGpu, regAddr); + if ((regVal & GPU_READ_PRI_ERROR_MASK) == GPU_READ_PRI_ERROR_CODE) + { + return 0; + } + + return regVal; +} + +void +kmemsysGetEccCounts_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem, + NvU32 *dramCount, + NvU32 *ltcCount +) +{ + NvU32 maxFbpas = kmemsysGetMaxFbpas_HAL(pGpu, pKernelMemorySystem); + NvU32 dedCountSize = kmemsysGetEccDedCountSize_HAL(pGpu, pKernelMemorySystem); + NvU32 fbpaDedCountRegAddr = 0; + NvU32 regVal; + + if (dramCount == NULL || ltcCount == NULL) + { + return; + } + + *dramCount = 0; + *ltcCount = 0; + + for (NvU32 i = 0; i < maxFbpas; i++) + { + for (NvU32 j = 0; j < dedCountSize; j++) + { + // DRAM count read + fbpaDedCountRegAddr = kmemsysGetEccDedCountRegAddr_HAL(pGpu, pKernelMemorySystem, i, j); + *dramCount += _kmemsysReadRegAndMaskPriError(pGpu, fbpaDedCountRegAddr); + + // LTC count read + regVal = _kmemsysReadRegAndMaskPriError(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + + (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE)); + *ltcCount += DRF_VAL(_PLTCG_LTC0_LTS0, _L2_CACHE_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + } + } +} + +void +kmemsysClearEccCounts_TU102 +( + OBJGPU *pGpu, + KernelMemorySystem *pKernelMemorySystem +) +{ + NvU32 maxFbpas = kmemsysGetMaxFbpas_HAL(pGpu, pKernelMemorySystem); + NvU32 dedCountSize = kmemsysGetEccDedCountSize_HAL(pGpu, pKernelMemorySystem); + NvU32 fbpaDedCountRegAddr = 0; + + for (NvU32 i = 0; i < maxFbpas; i++) + { + for (NvU32 j = 0; j < dedCountSize; j++) + { + fbpaDedCountRegAddr = kmemsysGetEccDedCountRegAddr_HAL(pGpu, pKernelMemorySystem, i, j); + osGpuWriteReg032(pGpu, fbpaDedCountRegAddr, 0); + osGpuWriteReg032(pGpu, NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT + (i * NV_LTC_PRI_STRIDE) + (j * NV_LTS_PRI_STRIDE), 0); + } + } +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c b/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c index 7288ac3632..f3e7ac077c 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -48,12 +48,13 @@ kmemsysGetFbNumaInfo_GV100 OBJGPU *pGpu, KernelMemorySystem *pKernelMemorySystem, NvU64 *physAddr, + NvU64 *rsvdPhysAddr, NvS32 *numaNodeId ) { NV_STATUS status; - status = osGetFbNumaInfo(pGpu, physAddr, numaNodeId); + status = osGetFbNumaInfo(pGpu, physAddr, rsvdPhysAddr, numaNodeId); if (status == NV_OK) { NV_PRINTF(LEVEL_INFO, "NUMA FB Physical address: 0x%llx Node ID: 0x%x\n", @@ -343,7 +344,7 @@ kmemsysSetupAllAtsPeers_GV100 NvU32 gpuAttachCnt, gpuAttachMask, gpuInstance = 0; NV_STATUS status = NV_OK; - POBJGPU pRemoteGpu = NULL; + OBJGPU *pRemoteGpu = NULL; NV_CHECK_OR_RETURN(LEVEL_WARNING, pKernelNvlink != NULL, status); @@ -384,7 +385,7 @@ kmemsysRemoveAllAtsPeers_GV100 NvU32 gpuAttachCnt, gpuAttachMask, gpuInstance = 0; NV_STATUS status = NV_OK; - POBJGPU pRemoteGpu = NULL; + OBJGPU *pRemoteGpu = NULL; // loop over all possible GPU pairs and remove the ATS config gpumgrGetGpuAttachInfo(&gpuAttachCnt, &gpuAttachMask); diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c index 18903cebe2..9ba9072ef4 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c @@ -30,6 +30,7 @@ #include "gpu/bif/kernel_bif.h" #include "gpu/bus/kern_bus.h" #include "os/os.h" +#include "platform/sli/sli.h" #include "nvRmReg.h" #include "gpu/gsp/gsp_static_config.h" @@ -50,6 +51,13 @@ kmemsysInitRegistryOverrides if (data32 == NV_REG_STR_RM_L2_CLEAN_FB_PULL_DISABLED) pKernelMemorySystem->bL2CleanFbPull = NV_FALSE; } + + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_OVERRIDE_TO_GMK, &data32) == NV_OK) && + (data32 != NV_REG_STR_RM_OVERRIDE_TO_GMK_DISABLED)) + { + pKernelMemorySystem->overrideToGMK = data32; + } + } NV_STATUS @@ -71,6 +79,7 @@ kmemsysConstructEngine_IMPL // resetting GPU FALCONs and in particular resetting the PMU as part of VBIOS // init. NV_ASSERT_OK_OR_RETURN(kmemsysInitFlushSysmemBuffer_HAL(pGpu, pKernelMemorySystem)); + } return NV_OK; @@ -159,6 +168,17 @@ NV_STATUS kmemsysStateInitLocked_IMPL NV_ASSERT_OK_OR_GOTO(status, kmemsysSetupCoherentCpuLink(pGpu, pKernelMemorySystem, NV_FALSE), fail); } + { + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + // + // Ask GMMU to set the large page size after we have initialized + // memory and before we initialize BAR2. + // + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kgmmuCheckAndDecideBigPageSize_HAL(pGpu, pKernelGmmu)); + } + fail: if (status != NV_OK) { @@ -385,12 +405,10 @@ kmemsysInitStaticConfig_KERNEL ) { RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_STATUS status; - status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG, - pConfig, sizeof(*pConfig)); - return status; + return pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_STATIC_CONFIG, + pConfig, sizeof(*pConfig)); } /*! @@ -574,9 +592,18 @@ kmemsysGetMIGGPUInstanceMemInfo_IMPL // Some FB memory is wasted here if it is not already aligned. // alignedStartAddr = NV_ALIGN_UP64(startAddr, memblockSize); - partitionSize -= (alignedStartAddr - startAddr); - startAddr = alignedStartAddr; + + if(pKernelMemorySystem->bNumaMigPartitionSizeEnumerated) + { + partitionSize = pKernelMemorySystem->numaMigPartitionSize[swizzId]; + } + else + { + partitionSize -= (alignedStartAddr - startAddr); + } + partitionSize = NV_ALIGN_DOWN64(partitionSize, memblockSize); + startAddr = alignedStartAddr; } endAddr = startAddr + partitionSize - 1; @@ -586,6 +613,40 @@ kmemsysGetMIGGPUInstanceMemInfo_IMPL return NV_OK; } +/** + * @brief Modifies numaMigPartitionSize array such that memory size of + all the mig partitions with swizzId between startSwizzId and + endSwizzId is assigned the minimum value among all partition's + memory size. + * + * @param[IN] pKernelMemorySystem + * @param[IN] startSwizzId + * @param[IN] endSwizzId + * + */ +static void +_kmemsysSetNumaMigPartitionSizeSubArrayToMinimumValue +( + KernelMemorySystem *pKernelMemorySystem, + NvU64 startSwizzId, + NvU64 endSwizzId +) +{ + NvU64 minPartitionSize = pKernelMemorySystem->numaMigPartitionSize[startSwizzId]; + NvU64 index; + + for (index = startSwizzId; index <= endSwizzId; index++) + { + if(pKernelMemorySystem->numaMigPartitionSize[index] < minPartitionSize) + minPartitionSize = pKernelMemorySystem->numaMigPartitionSize[index]; + } + + for (index = startSwizzId; index <= endSwizzId; index++) + { + pKernelMemorySystem->numaMigPartitionSize[index] = minPartitionSize; + } +} + /*! * @brief Function to populate static GPU instance memory config which will be * utilized for GPU instance memory query and memory allocation @@ -639,6 +700,30 @@ kmemsysPopulateMIGGPUInstanceMemConfig_KERNEL kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments)); } + if (osNumaOnliningEnabled(pGpu->pOsGpuInfo)) + { + NV_RANGE addrRange = NV_RANGE_EMPTY; + NvU32 memSize; + + for(swizzId = 0; swizzId < KMIGMGR_MAX_GPU_SWIZZID; swizzId++) + { + kmemsysGetMIGGPUInstanceMemInfo(pGpu, pKernelMemorySystem, swizzId, &addrRange); + pKernelMemorySystem->numaMigPartitionSize[swizzId] = addrRange.hi - addrRange.lo + 1; + } + + // + // In GH180 for all the swizzId's for a given memory profile (FULL, HALF, QUARTER + // and EIGHTH partitions) might not be same. Modify numaMigPartitionSize array + // for the partition size to be constant for a given profile. BUG 4284299. + // + for (memSize = NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL; memSize < NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE__SIZE; memSize++) + { + NV_RANGE swizzRange = kmigmgrMemSizeFlagToSwizzIdRange(pGpu, pKernelMIGManager, + DRF_NUM(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, memSize)); + _kmemsysSetNumaMigPartitionSizeSubArrayToMinimumValue(pKernelMemorySystem, swizzRange.lo, swizzRange.hi); + } + pKernelMemorySystem->bNumaMigPartitionSizeEnumerated = NV_TRUE; + } return NV_OK; } @@ -655,6 +740,13 @@ kmemsysGetMIGGPUInstanceMemConfigFromSwizzId_IMPL ) { NV_ASSERT_OR_RETURN(swizzId < KMIGMGR_MAX_GPU_SWIZZID, NV_ERR_INVALID_ARGUMENT); + + if (IS_VIRTUAL(pGpu)) + { + // VMMU Segment details are populated on Host and not Guest. + return NV_ERR_NOT_SUPPORTED; + } + // MODS makes a control call to describe GPU instances before this is populated. Return invalid data anyways NV_ASSERT_OR_RETURN(pKernelMemorySystem->gpuInstanceMemConfig[swizzId].bInitialized, NV_ERR_INVALID_STATE); @@ -752,6 +844,7 @@ kmemsysSetupCoherentCpuLink_IMPL { NV_ASSERT_OK_OR_RETURN(kmemsysGetFbNumaInfo_HAL(pGpu, pKernelMemorySystem, &pKernelMemorySystem->coherentCpuFbBase, + &pKernelMemorySystem->coherentRsvdFbBase, &numaNodeId)); if (pKernelMemorySystem->coherentCpuFbBase != 0) { @@ -825,6 +918,10 @@ kmemsysSetupCoherentCpuLink_IMPL totalRsvdBytes += (rsvdFastSize + rsvdSlowSize + rsvdISOSize); totalRsvdBytes += pMemoryManager->Ram.reservedMemSize; + // For SRIOV guest, take into account FB tax paid on host side for each VF + // This FB tax is non zero only for SRIOV guest RM environment. + totalRsvdBytes += memmgrGetFbTaxSize_HAL(pGpu, pMemoryManager); + // // TODO: make sure the onlineable memory is aligned to memblockSize // Currently, if we have leftover memory, it'll just be wasted because no @@ -833,6 +930,24 @@ kmemsysSetupCoherentCpuLink_IMPL // numaOnlineSize = NV_ALIGN_DOWN64(fbSize - totalRsvdBytes, memblockSize); + if (IS_PASSTHRU(pGpu) && pKernelMemorySystem->bBug3656943WAR) + { + // For passthrough case, reserved memory size is fixed as 1GB + NvU64 rsvdSize = 1 * 1024 * 1024 * 1024; + + NV_ASSERT_OR_RETURN(rsvdSize >= totalRsvdBytes, NV_ERR_INVALID_STATE); + totalRsvdBytes = rsvdSize; + // + // Aligning to hardcoded 512MB size as both host and guest need to use + // the same alignment irrespective of the kernel page size. 512MB size + // works for both 4K and 64K page size kernels but more memory is + // wasted being part of non onlined region which can't be avoided + // per the design. + // + numaOnlineSize = NV_ALIGN_DOWN64(fbSize - totalRsvdBytes, 512 * 1024 * 1024); + } + + NV_PRINTF(LEVEL_INFO, "fbSize: 0x%llx NUMA reserved memory size: 0x%llx online memory size: 0x%llx\n", fbSize, totalRsvdBytes, numaOnlineSize); @@ -930,3 +1045,44 @@ kmemsysGetUsableFbSize_KERNEL return kmemsysReadUsableFbSize_HAL(pGpu, pKernelMemorySystem, pFbSize); } +NV_STATUS +kmemsysStateLoad_VF(OBJGPU *pGpu, KernelMemorySystem *pKernelMemorySystem, NvU32 flags) +{ + NV_STATUS status = NV_OK; + + if (flags & GPU_STATE_FLAGS_PRESERVING) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + NV_ASSERT(!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)); + + status = memmgrRestorePowerMgmtState(pGpu, pMemoryManager); + if (status != NV_OK) + memmgrFreeFbsrMemory(pGpu, pMemoryManager); + + NV_ASSERT_OK(status); + } + + return status; +} + +NV_STATUS +kmemsysStateUnload_VF(OBJGPU *pGpu, KernelMemorySystem *pKernelMemorySystem, NvU32 flags) +{ + NV_STATUS status = NV_OK; + + if (flags & GPU_STATE_FLAGS_PRESERVING) + { + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + NV_ASSERT(!(flags & GPU_STATE_FLAGS_GC6_TRANSITION)); + + status = memmgrSavePowerMgmtState(pGpu, pMemoryManager); + if (status != NV_OK) + memmgrFreeFbsrMemory(pGpu, pMemoryManager); + + NV_ASSERT_OK(status); + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c index 35069b98aa..7710b0ab65 100644 --- a/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c @@ -38,11 +38,97 @@ #include "core/locks.h" #include "vgpu/rpc.h" #include "rmapi/client.h" +#include "platform/sli/sli.h" +NV_STATUS +kmemsysGetFbInfos_VF(OBJGPU *pGpu, KernelMemorySystem *pKernelMemorySystem, RsClient *pClient, Device *pDevice, NvHandle hObject, + NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams, NvU64 *pFbInfoListIndicesUnset) +{ + NV2080_CTRL_FB_INFO *pFbInfos = pParams->fbInfoList; + NvU32 data = 0; + NvU32 i = 0; + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + FOR_EACH_INDEX_IN_MASK(64, i, *pFbInfoListIndicesUnset) + { + switch (pFbInfos[i].index) + { + case NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT: + { + data = nvPopCount64(pVSI->fbioMask); + break; + } + case NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK: + { + data = pVSI->fbioMask; + break; + } + case NV2080_CTRL_FB_INFO_INDEX_FBP_MASK: + { + data = pVSI->fbpMask; + break; + } + case NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH: + { + data = pVSI->fbBusWidth; + break; + } + case NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT: + { + data = nvPopCount64(pVSI->fbpMask); + break; + } + case NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT: + { + data = nvPopCount64(pVSI->ltcMask); + break; + } + case NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT: + { + data = pVSI->ltsCount; + break; + } + case NV2080_CTRL_FB_INFO_INDEX_LTC_MASK: + { + data = pVSI->ltcMask; + break; + } + case NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE: + { + data = pVSI->sizeL2Cache; + break; + } + + // Indices unknown to this function are handled downstream, so do not modify them. + default: + { + continue; + } + } + + // save off data value + pFbInfos[i].data = data; + *pFbInfoListIndicesUnset &= ~NVBIT64(i); + } + FOR_EACH_INDEX_IN_MASK_END; + + return NV_OK; +} + +// Common logic for all runtimes to populate NV2080_CTRL_FB_INFO array static NV_STATUS -_fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject, NV2080_CTRL_FB_INFO *pFbInfos, NvU32 fbInfoListSize) +_kmemsysGetFbInfos +( + OBJGPU *pGpu, + RsClient *pClient, + Device *pDevice, + NvHandle hObject, + NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams +) { + NV2080_CTRL_FB_INFO *pFbInfos = pParams->fbInfoList; KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); Heap *pHeap = GPU_GET_HEAP(pGpu); @@ -58,12 +144,9 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject NvU64 heapBase; NvU64 largestOffset; NvU64 largestFree; - NvU64 val; - NvU64 routeToPhysicalIdxMask = 0; NvBool bIsClientMIGMonitor = NV_FALSE; NvBool bIsClientMIGProfiler = NV_FALSE; - - ct_assert(NV2080_CTRL_FB_INFO_INDEX_MAX < NV_NBITS_IN_TYPE(routeToPhysicalIdxMask)); + NvU64 fbInfoListIndicesUnset = 0; if (!RMCFG_FEATURE_PMA) return NV_ERR_NOT_SUPPORTED; @@ -74,12 +157,21 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject bIsClientMIGProfiler = kmigmgrIsDeviceUsingDeviceProfiling(pGpu, pKernelMIGManager, pDevice); } + ct_assert(NV2080_CTRL_FB_INFO_INDEX_MAX <= NV_NBITS_IN_TYPE(fbInfoListIndicesUnset)); + + // Construct mask of width fbInfoListSize to track which indices have been handled + fbInfoListIndicesUnset = NV_U64_MAX >> (NV_NBITS_IN_TYPE(fbInfoListIndicesUnset) - pParams->fbInfoListSize); + // - // Most MIG queries require GPU instance info that is only kept in the Physical RM. Flag - // the indices that will need to be fulfilled by the GSP when in offload mode, and - // also load the per-GPU instance heap for others. + // Populate indices with runtime-specific logic + // Return early if this computed all requested indices // - for (i = 0; i < fbInfoListSize; i++) + status = kmemsysGetFbInfos_HAL(pGpu, pKernelMemorySystem, pClient, pDevice, hObject, pParams, &fbInfoListIndicesUnset); + if (status == NV_OK && nvPopCount64(fbInfoListIndicesUnset) == 0) + return NV_OK; + + // Load the per-GPU instance heap if MIG is enabled. + FOR_EACH_INDEX_IN_MASK(64, i, fbInfoListIndicesUnset) { switch (pFbInfos[i].index) { @@ -104,35 +196,8 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject case NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_SIZE: case NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_ALIGNMENT: case NV2080_CTRL_FB_INFO_INDEX_P2P_MAILBOX_BAR1_MAX_OFFSET_64KB: - { continue; - } - case NV2080_CTRL_FB_INFO_INDEX_BUS_WIDTH: - case NV2080_CTRL_FB_INFO_INDEX_PARTITION_COUNT: - case NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK: - case NV2080_CTRL_FB_INFO_INDEX_FBP_MASK: - case NV2080_CTRL_FB_INFO_INDEX_FBP_COUNT: - case NV2080_CTRL_FB_INFO_INDEX_L2CACHE_SIZE: - case NV2080_CTRL_FB_INFO_INDEX_LTC_COUNT: - case NV2080_CTRL_FB_INFO_INDEX_LTS_COUNT: - case NV2080_CTRL_FB_INFO_INDEX_LTC_MASK: - case NV2080_CTRL_FB_INFO_INDEX_MEMORYINFO_VENDOR_ID: - case NV2080_CTRL_FB_INFO_INDEX_TRAINIG_2T: - case NV2080_CTRL_FB_INFO_INDEX_PSEUDO_CHANNEL_MODE: - case NV2080_CTRL_FB_INFO_INDEX_COMPRESSION_SIZE: - case NV2080_CTRL_FB_INFO_INDEX_DRAM_PAGE_STRIDE: - case NV2080_CTRL_FB_INFO_INDEX_RAM_CFG: - case NV2080_CTRL_FB_INFO_INDEX_RAM_TYPE: - case NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE: - { - // This info is only known by the Physical RM. Redirect it there. - if (IS_GSP_CLIENT(pGpu)) - { - routeToPhysicalIdxMask |= BIT64(i); - } - break; - } case NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE: case NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE: { @@ -184,49 +249,10 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject } } } + FOR_EACH_INDEX_IN_MASK_END; - // If we have any infos that need to be populated by Physical RM, query now - if (routeToPhysicalIdxMask != 0) + FOR_EACH_INDEX_IN_MASK(64, i, fbInfoListIndicesUnset) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pParams = - portMemAllocNonPaged(sizeof(NV2080_CTRL_FB_GET_INFO_V2_PARAMS)); - NvU32 physIdx = 0; - - portMemSet(pParams, 0, sizeof(*pParams)); - FOR_EACH_INDEX_IN_MASK(64, i, routeToPhysicalIdxMask) - { - pParams->fbInfoList[physIdx++].index = pFbInfos[i].index; - } - FOR_EACH_INDEX_IN_MASK_END; - - pParams->fbInfoListSize = physIdx; - - NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - pRmApi->Control(pRmApi, pClient->hClient, hObject, - NV2080_CTRL_CMD_FB_GET_INFO_V2, - pParams, sizeof(*pParams)), - portMemFree(pParams); - return status; - ); - - physIdx = 0; - FOR_EACH_INDEX_IN_MASK(64, i, routeToPhysicalIdxMask) - { - NV_ASSERT(pFbInfos[i].index == pParams->fbInfoList[physIdx].index); - pFbInfos[i].data = pParams->fbInfoList[physIdx++].data; - } - FOR_EACH_INDEX_IN_MASK_END; - - portMemFree(pParams); - } - - for (i = 0; i < fbInfoListSize; i++) - { - // Skip info already populated by Physical RM - if ((routeToPhysicalIdxMask & BIT64(i)) != 0) - continue; - switch (pFbInfos[i].index) { case NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT: @@ -286,6 +312,14 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject } case NV2080_CTRL_FB_INFO_INDEX_TOTAL_RAM_SIZE: { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + { + data = 0; + NV_PRINTF(LEVEL_INFO, + "[zero-FB, No local RAM] TOTAL_RAM_SIZE = 0\n"); + break; + } + if (pMemoryPartitionHeap != NULL) { NvU32 heapSizeKb; @@ -308,28 +342,23 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject } else { - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) - { - data = 0; - NV_PRINTF(LEVEL_INFO, - "[zero-FB, No local RAM] TOTAL_RAM_SIZE = 0\n"); - } - else - { - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); - NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), - (pMemoryManager->Ram.fbOverrideSizeMb << 10)) - - pMemsysConfig->fbOverrideStartKb); - } + NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pKernelMemorySystem->fbOverrideStartKb); break; } } case NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE: { - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) + { + data = 0; + NV_PRINTF(LEVEL_INFO, + "[zero-FB, No local RAM] RAM_SIZE = 0\n"); + break; + } + if (pMemoryPartitionHeap != NULL) { NvU32 heapSizeKb; @@ -350,25 +379,22 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject data = heapSizeKb; break; } + NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pKernelMemorySystem->fbOverrideStartKb); + break; + } + case NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE: + { if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) { data = 0; NV_PRINTF(LEVEL_INFO, - "[zero-FB, No local RAM] RAM_SIZE = 0\n"); - } - else - { - NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), - (pMemoryManager->Ram.fbOverrideSizeMb << 10)) - - pMemsysConfig->fbOverrideStartKb); + "[zero-FB, No local RAM] USABLE_RAM_SIZE = 0\n"); + break; } - break; - } - case NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE: - { - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); + if (pMemoryPartitionHeap != NULL) { NvU32 heapSizeKb; @@ -389,25 +415,14 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject data = heapSizeKb; break; } - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB)) - { - data = 0; - NV_PRINTF(LEVEL_INFO, - "[zero-FB, No local RAM] USABLE_RAM_SIZE = 0\n"); - } - else - { - NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbUsableMemSize >> 10)); - data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbUsableMemSize >> 10 ), - (pMemoryManager->Ram.fbOverrideSizeMb << 10)) - - pMemsysConfig->fbOverrideStartKb); - } + NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbUsableMemSize >> 10)); + data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbUsableMemSize >> 10 ), + (pMemoryManager->Ram.fbOverrideSizeMb << 10)) + - pKernelMemorySystem->fbOverrideStartKb); break; } case NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE: { - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); if (bIsPmaEnabled) { pmaGetTotalMemory(&pHeap->pmaObject, &bytesTotal); @@ -430,7 +445,7 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject NV_ASSERT(NvU64_HI32(size >> 10) == 0); data = NvU64_LO32(size >> 10); } - data -= pMemsysConfig->fbOverrideStartKb; + data -= pKernelMemorySystem->fbOverrideStartKb; break; } case NV2080_CTRL_FB_INFO_INDEX_HEAP_START: @@ -458,12 +473,10 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject // in hardware, then heapGetBase() will give the correct // value and it just needs to be converted to kbytes. // It will be zero unless VGA display memory is reserved - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); - if (pMemsysConfig->fbOverrideStartKb != 0) + if (pKernelMemorySystem->fbOverrideStartKb != 0) { - data = NvU64_LO32(pMemsysConfig->fbOverrideStartKb); - NV_ASSERT(((NvU64) data << 10ULL) == pMemsysConfig->fbOverrideStartKb); + data = NvU64_LO32(pKernelMemorySystem->fbOverrideStartKb); + NV_ASSERT(((NvU64) data << 10ULL) == pKernelMemorySystem->fbOverrideStartKb); } else { @@ -484,6 +497,7 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject { if (bIsClientMIGMonitor || bIsClientMIGProfiler) { + NvU64 val = 0; bytesFree = 0; if (bIsPmaEnabled) @@ -580,8 +594,6 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject case NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE: { - const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); if (bIsPmaEnabled) { NvU32 heapSizeKb; @@ -607,7 +619,7 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject if (data > heapSizeKb) data = heapSizeKb; } - data -= pMemsysConfig->fbOverrideStartKb; + data -= pKernelMemorySystem->fbOverrideStartKb; break; } case NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT: @@ -831,50 +843,75 @@ _fbGetFbInfos(OBJGPU *pGpu, RsClient *pClient, Device *pDevice, NvHandle hObject } break; } + default: { - data = 0; - status = NV_ERR_INVALID_ARGUMENT; - break; + if (status != NV_OK) + break; + + continue; } } if (status != NV_OK) break; + // save off data value pFbInfos[i].data = data; + fbInfoListIndicesUnset &= ~NVBIT64(i); } + FOR_EACH_INDEX_IN_MASK_END; - return status; -} + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, status); -// -// subdeviceCtrlCmdFbGetInfo -// -// Lock Requirements: -// Assert that API and Gpus lock held on entry -// -NV_STATUS -subdeviceCtrlCmdFbGetInfo_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_FB_GET_INFO_PARAMS *pFbInfoParams -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - RsClient *pClient = RES_GET_CLIENT(pSubdevice); - NvHandle hObject = RES_GET_HANDLE(pSubdevice); - Device *pDevice = GPU_RES_GET_DEVICE(pSubdevice); + // RPC to host to populate indices that could not be yet computed + if ((IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) && + (nvPopCount64(fbInfoListIndicesUnset) > 0)) + { + NvU32 physIdx = 0; + NV2080_CTRL_FB_GET_INFO_V2_PARAMS *pRpcParams = + portMemAllocNonPaged(sizeof(NV2080_CTRL_FB_GET_INFO_V2_PARAMS)); - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(pGpu->gpuInstance)); + portMemSet(pRpcParams, 0, sizeof(*pRpcParams)); + FOR_EACH_INDEX_IN_MASK(64, i, fbInfoListIndicesUnset) + { + pRpcParams->fbInfoList[physIdx++].index = pFbInfos[i].index; + } + FOR_EACH_INDEX_IN_MASK_END; - if ((pFbInfoParams->fbInfoListSize == 0) || - (NvP64_VALUE(pFbInfoParams->fbInfoList) == NULL)) - { - return NV_ERR_INVALID_ARGUMENT; + pRpcParams->fbInfoListSize = physIdx; + + NV_RM_RPC_CONTROL(pGpu, + pClient->hClient, + hObject, + NV2080_CTRL_CMD_FB_GET_INFO_V2, + pRpcParams, + sizeof(*pRpcParams), + status); + + physIdx = 0; + FOR_EACH_INDEX_IN_MASK(64, i, fbInfoListIndicesUnset) + { + NV_ASSERT(pFbInfos[i].index == pRpcParams->fbInfoList[physIdx].index); + + pFbInfos[i].data = pRpcParams->fbInfoList[physIdx].data; + + // + // Assume that the RPC could handle unknown indices. Actual errors will be signaled by + // returning status. + // + fbInfoListIndicesUnset &= ~NVBIT64(i); + + physIdx++; + } + FOR_EACH_INDEX_IN_MASK_END; + + portMemFree(pRpcParams); } - return _fbGetFbInfos(pGpu, pClient, pDevice, hObject, NvP64_VALUE(pFbInfoParams->fbInfoList), pFbInfoParams->fbInfoListSize); + NV_CHECK(LEVEL_INFO, nvPopCount64(fbInfoListIndicesUnset) == 0); + + return status; } // @@ -903,7 +940,7 @@ subdeviceCtrlCmdFbGetInfoV2_IMPL return NV_ERR_INVALID_ARGUMENT; } - return _fbGetFbInfos(pGpu, pClient, pDevice, hObject, pFbInfoParams->fbInfoList, pFbInfoParams->fbInfoListSize); + return _kmemsysGetFbInfos(pGpu, pClient, pDevice, hObject, pFbInfoParams); } // @@ -1155,8 +1192,6 @@ subdeviceCtrlCmdFbGetNumaInfo_IMPL NvU32 count; NvU64 numaMemOffset = 0; NvU64 numaMemSize = 0; - const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = - kmemsysGetStaticConfig(pGpu, pKernelMemorySystem); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); @@ -1210,7 +1245,7 @@ subdeviceCtrlCmdFbGetNumaInfo_IMPL return NV_OK; } - count = pMemorySystemConfig->maximumBlacklistPages; + count = kmemsysGetMaximumBlacklistPages(pGpu, pKernelMemorySystem); pBlAddrs = portMemAllocNonPaged(sizeof(BLACKLIST_ADDRESS) * count); if (pBlAddrs == NULL) { @@ -1427,3 +1462,92 @@ subdeviceCtrlCmdFbFlushGpuCache_IMPL return status; } + +// +// subdeviceCtrlCmdFbGetGpuCacheInfo +// +// Lock Requirements: +// Assert that API and GPUs lock held on entry +// +NV_STATUS +subdeviceCtrlCmdFbGetGpuCacheInfo_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS *pGpuCacheParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NV_STATUS status = NV_OK; + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + FB_CACHE_WRITE_MODE writeMode = pKernelMemorySystem->l2WriteMode; + FB_CACHE_BYPASS_MODE bypassMode = FB_CACHE_BYPASS_MODE_DISABLED; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + switch (writeMode) + { + case FB_CACHE_WRITE_MODE_WRITETHROUGH: + pGpuCacheParams->writeMode = NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITETHROUGH; + break; + case FB_CACHE_WRITE_MODE_WRITEBACK: + pGpuCacheParams->writeMode = NV2080_CTRL_FB_GET_GPU_CACHE_INFO_WRITE_MODE_WRITEBACK; + break; + default: + status = NV_ERR_INVALID_STATE; + NV_PRINTF(LEVEL_ERROR, "Invalid write mode : %d\n", writeMode); + break; + } + + switch (bypassMode) + { + case FB_CACHE_BYPASS_MODE_DISABLED: + pGpuCacheParams->bypassMode = NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_DISABLED; + break; + case FB_CACHE_BYPASS_MODE_ENABLED: + pGpuCacheParams->bypassMode = NV2080_CTRL_FB_GET_GPU_CACHE_INFO_BYPASS_MODE_ENABLED; + break; + default: + status = NV_ERR_INVALID_STATE; + NV_PRINTF(LEVEL_ERROR, "Invalid bypass mode : %d\n", + bypassMode); + break; + } + + pGpuCacheParams->powerState = NV2080_CTRL_FB_GET_GPU_CACHE_INFO_POWER_STATE_ENABLED; + pGpuCacheParams->rcmState = NV2080_CTRL_FB_GET_GPU_CACHE_INFO_RCM_STATE_FULL; + + return status; +} + +NV_STATUS subdeviceCtrlCmdMemSysGetStaticConfig_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + const MEMORY_SYSTEM_STATIC_CONFIG *pConfig = + kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pConfig != NULL, NV_ERR_INVALID_STATE); + portMemCopy(pParams, sizeof(*pParams), pConfig, sizeof(*pConfig)); + + return NV_OK; +} + +NV_STATUS subdeviceCtrlCmdMemSysGetStaticConfig_VGPUSTUB +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + portMemCopy(pParams, sizeof(*pParams), + &pVSI->memsysStaticConfig, sizeof(pVSI->memsysStaticConfig)); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mem_sys/zbc_api.c b/src/nvidia/src/kernel/gpu/mem_sys/zbc_api.c new file mode 100644 index 0000000000..f3b23fb600 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mem_sys/zbc_api.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "kernel/gpu/mem_sys/zbc_api.h" +#include "vgpu/rpc.h" + +NV_STATUS +zbcapiCtrlCmdGetZbcClearTableSize_VF +( + ZbcApi *pZbcApi, + NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS *pGetZBCClearTableSizeParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pZbcApi); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + if (pGetZBCClearTableSizeParams->tableType >= NV9096_CTRL_ZBC_CLEAR_TABLE_TYPE_COUNT) + return NV_ERR_INVALID_PARAMETER; + + pGetZBCClearTableSizeParams->indexStart = pVSI->zbcTableSizes[pGetZBCClearTableSizeParams->tableType].indexStart; + pGetZBCClearTableSizeParams->indexEnd = pVSI->zbcTableSizes[pGetZBCClearTableSizeParams->tableType].indexEnd; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c b/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c index e4278e4295..98d5938dd8 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c @@ -367,3 +367,91 @@ kmigmgrIsMemoryPartitioningNeeded_GA100 // Memory partitioning is needed for non-zero swizzIds return (swizzId != 0); } + +/*! + * @brief Returns the span covered by the swizzId + */ +NV_RANGE +kmigmgrSwizzIdToSpan_GA100 +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 swizzId +) +{ + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + NV_RANGE ret; + NvU8 spanLen; + NvU32 maxValidSwizzId; + + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized, NV_RANGE_EMPTY); + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo != NULL, NV_RANGE_EMPTY); + + if (kmigmgrIsA100ReducedConfig(pGpu, pKernelMIGManager)) + spanLen = 4; + else + spanLen = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS].data; + + switch (swizzId) + { + case 0: + ret = rangeMake(0, spanLen - 1); + break; + case 1: + ret = rangeMake(0, (spanLen/2) - 1); + break; + case 2: + ret = rangeMake(spanLen/2, spanLen - 1); + break; + case 3: + ret = rangeMake(0, (spanLen/4) - 1); + break; + case 4: + ret = rangeMake((spanLen/4), (spanLen/2) - 1); + break; + case 5: + ret = rangeMake((spanLen/2), (3*(spanLen/4)) - 1); + break; + case 6: + ret = rangeMake((3*(spanLen/4)), spanLen - 1); + break; + case 7: + ret = rangeMake(0, 0); + break; + case 8: + ret = rangeMake(1, 1); + break; + case 9: + ret = rangeMake(2, 2); + break; + case 10: + ret = rangeMake(3, 3); + break; + case 11: + ret = rangeMake(4, 4); + break; + case 12: + ret = rangeMake(5, 5); + break; + case 13: + ret = rangeMake(6, 6); + break; + case 14: + ret = rangeMake(7, 7); + break; + default: + NV_PRINTF(LEVEL_ERROR, "Unsupported swizzid 0x%x\n", swizzId); + DBG_BREAKPOINT(); + ret = NV_RANGE_EMPTY; + break; + } + + maxValidSwizzId = (spanLen * 2) - 2; + + if (swizzId > maxValidSwizzId) + { + ret = NV_RANGE_EMPTY; + } + + return ret; +} diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c b/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c index c6058bf5f9..00a36cad11 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c @@ -24,7 +24,6 @@ #define NVOC_KERNEL_MIG_MANAGER_H_PRIVATE_ACCESS_ALLOWED #include "kernel/gpu/mem_mgr/mem_mgr.h" -#include "kernel/gpu/mem_mgr/heap.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_fifo.h" @@ -94,16 +93,21 @@ kmigmgrIsGPUInstanceCombinationValid_GH100 { NvU32 memSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, gpuInstanceFlag); NvU32 computeSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, gpuInstanceFlag); + NvU32 smallestComputeSizeFlag; if (!kmigmgrIsGPUInstanceFlagValid_HAL(pGpu, pKernelMIGManager, gpuInstanceFlag)) { return NV_FALSE; } + NV_CHECK_OR_RETURN(LEVEL_ERROR, + kmigmgrGetSmallestGpuInstanceSize(pGpu, pKernelMIGManager, &smallestComputeSizeFlag) == NV_OK, + NV_FALSE); + // JPG_OFA profile is only available on the smallest partition if (FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA, _ENABLE, gpuInstanceFlag)) { - if (computeSizeFlag != NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH) + if (computeSizeFlag != smallestComputeSizeFlag) { return NV_FALSE; } diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c b/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c index cf43fa5145..511ad1337a 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/compute_instance_subscription.c @@ -34,7 +34,6 @@ #include "gpu/gpu.h" #include "core/system.h" #include "os/os.h" -#include "gpu/subdevice/subdevice.h" #include "kernel/gpu/mig_mgr/gpu_instance_subscription.h" #include "kernel/gpu/mig_mgr/compute_instance_subscription.h" diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c index 85c1140012..2080c24d01 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c @@ -798,17 +798,14 @@ gisubscriptionCtrlCmdExecPartitionsExport_IMPL { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - NV_STATUS status = NV_OK; - - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); - - return status; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + return pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); } if (pParams->id >= NV_ARRAY_ELEMENTS(pGPUInstance->MIGComputeInstance)) @@ -876,14 +873,14 @@ gisubscriptionCtrlCmdExecPartitionsImport_IMPL { CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); + status = pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); if (status != NV_OK) return status; @@ -1210,3 +1207,24 @@ gisubscriptionCtrlCmdExecPartitionsGetProfileCapacity_IMPL return NV_OK; } + +NV_STATUS +gisubscriptionCtrlCmdGetUuid_IMPL +( + GPUInstanceSubscription *pGPUInstanceSubscription, + NVC637_CTRL_GET_UUID_PARAMS *pParams +) +{ + NV_CHECK_OR_RETURN(LEVEL_ERROR, !pGPUInstanceSubscription->bDeviceProfiling, + NV_ERR_NOT_SUPPORTED); + + portMemCopy(pParams->uuid, sizeof(pParams->uuid), + pGPUInstanceSubscription->pKernelMIGGpuInstance->uuid.uuid, + sizeof(pGPUInstanceSubscription->pKernelMIGGpuInstance->uuid.uuid)); + + nvGetSmcUuidString((void*)pParams->uuid, pParams->uuidStr); + pParams->uuidStr[1] = 'G'; + pParams->uuidStr[2] = 'I'; + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c index 8a16bcae92..f09bf5c6ce 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -26,6 +26,7 @@ #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" #include "kernel/gpu/rc/kernel_rc.h" +#include "kernel/gpu/device/device.h" #include "kernel/gpu/subdevice/subdevice.h" #include "kernel/gpu/mig_mgr/compute_instance_subscription.h" #include "kernel/gpu/mig_mgr/gpu_instance_subscription.h" @@ -47,9 +48,11 @@ #include "virtualization/hypervisor/hypervisor.h" #include "kernel/gpu/gr/kernel_graphics_manager.h" #include "kernel/gpu/gr/kernel_graphics.h" +#include "kernel/gpu/intr/intr.h" #include "kernel/core/locks.h" #include "class/cl503b.h" #include "nv_ref.h" +#include "platform/sli/sli.h" #include "nvRmReg.h" #include "kernel/gpu/ccu/kernel_ccu.h" @@ -738,6 +741,26 @@ _kmigmgrHandlePostSchedulingEnableCallback NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, memmgrSetPartitionableMem_HAL(pGpu, pMemoryManager)); + if (IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu)) + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_GPU_GET_SMC_MODE_PARAMS params; + + portMemSet(¶ms, 0x0, sizeof(params)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GPU_GET_SMC_MODE, + ¶ms, + sizeof(params))); + + if (params.smcMode == NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_MIG_SUPPORTED, NV_FALSE); + } + } + if ((pKernelMIGManager == NULL) || !kmigmgrIsMIGSupported(pGpu, pKernelMIGManager)) { NV_PRINTF(LEVEL_INFO, "MIG not supported on this GPU.\n"); @@ -765,8 +788,15 @@ _kmigmgrHandlePostSchedulingEnableCallback kmigmgrSetPartitioningMode(pGpu, pKernelMIGManager)); } - if (IS_MIG_ENABLED(pGpu)) + gpumgrCacheSetMIGEnabled(pGpu, pKernelMIGManager->bMIGEnabled); + + // Populate static info collection even if MIG is not enabled. + if ((!pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) && IS_SILICON(pGpu)) || + (IS_VIRTUAL(pGpu) && IS_MIG_ENABLED(pGpu))) { + // Initialize static info derived from physical RM + NV_ASSERT_OK_OR_RETURN(kmigmgrLoadStaticInfo_HAL(pGpu, pKernelMIGManager)); + // // Populate static GPU instance memory config which will be used to manage // GPU instance memory @@ -774,9 +804,6 @@ _kmigmgrHandlePostSchedulingEnableCallback KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NV_ASSERT_OK_OR_RETURN(kmemsysPopulateMIGGPUInstanceMemConfig_HAL(pGpu, pKernelMemorySystem)); - // Initialize static info derived from physical RM - NV_ASSERT_OK_OR_RETURN(kmigmgrLoadStaticInfo_HAL(pGpu, pKernelMIGManager)); - // KERNEL_ONLY variants require static info to detect reduced configs kmigmgrDetectReducedConfig_HAL(pGpu, pKernelMIGManager); } @@ -929,10 +956,20 @@ kmigmgrStateInitLocked_IMPL if (kmigmgrIsDevinitMIGBitSet_HAL(pGpu, pKernelMIGManager)) pKernelMIGManager->bMIGEnabled = NV_TRUE; - gpumgrCacheSetMIGEnabled(pGpu, pKernelMIGManager->bMIGEnabled); - NV_CHECK_OR_RETURN(LEVEL_SILENT, kmigmgrIsMIGSupported(pGpu, pKernelMIGManager), NV_OK); + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_RESETLESS_MIG_SUPPORTED)) + { + NvU32 data32; + if (NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE, &data32)) + { + if (NV_REG_STR_RM_SET_MIG_AUTO_ONLINE_MODE_ENABLED == data32) + { + pKernelMIGManager->bMIGAutoOnlineEnabled = NV_TRUE; + } + } + } + // Setup a callback to initialize state at the very end of GPU post load NV_ASSERT_OK( kfifoAddSchedulingHandler(pGpu, GPU_GET_KERNEL_FIFO(pGpu), @@ -973,8 +1010,19 @@ kmigmgrInitRegistryOverrides_IMPL { NvU32 data32; - // Read boot config feature flags regkey - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, &data32) != NV_OK) + // + // Try reading boot config feature flags regkey from NvGlobal regkeys first. + // If the NvGlobal regkey is not found, try reading from per-GPU regkeys. + // + if (osGetNvGlobalRegistryDword(pGpu, NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, &data32) == NV_OK) + { + pKernelMIGManager->bGlobalBootConfigUsed = NV_TRUE; + } + else if (osReadRegistryDword(pGpu, NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, &data32) == NV_OK) + { + // Do nothing + } + else { data32 = DRF_DEF(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, _SUPPORTED, _DEFAULT) | DRF_DEF(_REG_STR_RM, _MIG_BOOT_CONFIGURATION_FEATURE_FLAGS, _AUTO_UPDATE, _DEFAULT); @@ -1104,6 +1152,143 @@ kmigmgrGetStaticInfo_IMPL return ((pPrivate != NULL) && pPrivate->bInitialized) ? &pPrivate->staticInfo : NULL; } +/*! Initialize static information sourced from VGPU static info */ +NV_STATUS +kmigmgrLoadStaticInfo_VF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager +) +{ + NV_STATUS status = NV_OK; + KERNEL_MIG_MANAGER_PRIVATE_DATA *pPrivate = (KERNEL_MIG_MANAGER_PRIVATE_DATA *)pKernelMIGManager->pPrivate; + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pPrivate != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + if (pPrivate->bInitialized) + return NV_OK; + + pPrivate->staticInfo.pProfiles = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pProfiles)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pPrivate->staticInfo.pProfiles != NULL, + status = NV_ERR_NO_MEMORY; + goto failed;); + portMemSet(pPrivate->staticInfo.pProfiles, 0x0, sizeof(*pPrivate->staticInfo.pProfiles)); + // In VGPU only one profile is visible describing all resources available + { + NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO *pPartitionDesc = &pPrivate->staticInfo.pProfiles->table[0]; + + pPartitionDesc->partitionFlag = (DRF_DEF(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, _FULL) | + DRF_DEF(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, _FULL)); + + pPartitionDesc->grCount = pVSI->gpuPartitionInfo.grEngCount; + pPartitionDesc->gpcCount = pVSI->gpuPartitionInfo.gpcCount; + pPartitionDesc->virtualGpcCount = pVSI->gpuPartitionInfo.virtualGpcCount; + pPartitionDesc->gfxGpcCount = pVSI->gpuPartitionInfo.gfxGpcCount; + pPartitionDesc->veidCount = pVSI->gpuPartitionInfo.veidCount; + pPartitionDesc->smCount = pVSI->gpuPartitionInfo.smCount; + pPartitionDesc->ceCount = pVSI->gpuPartitionInfo.ceCount; + pPartitionDesc->nvEncCount = pVSI->gpuPartitionInfo.nvEncCount; + pPartitionDesc->nvDecCount = pVSI->gpuPartitionInfo.nvDecCount; + pPartitionDesc->nvJpgCount = pVSI->gpuPartitionInfo.nvJpgCount; + pPartitionDesc->nvOfaCount = pVSI->gpuPartitionInfo.nvOfaCount; + pPartitionDesc->validCTSIdMask = pVSI->gpuPartitionInfo.validCTSIdMask; + pPrivate->staticInfo.pProfiles->count = 1; + } + + bitVectorClrAll(&pPrivate->staticInfo.partitionableEngines); + + // Use the engine info list to populate the partitionable engines in guest + { + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + const NvU32 numEngines = kfifoGetNumEschedDrivenEngines(pKernelFifo); + NvU32 engine; + + NV_ASSERT_OK(gpuUpdateEngineTable(pGpu)); + for (engine = 0; engine < numEngines; ++engine) + { + RM_ENGINE_TYPE rmEngineType; + + NV_ASSERT_OK_OR_RETURN( + kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_INVALID, engine, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType)); + + // Skip invalid engine type values + if (!RM_ENGINE_TYPE_IS_VALID(rmEngineType)) + { + NV_ASSERT(0); + continue; + } + + // Skip engines which are not partitionable + if (!kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, rmEngineType)) + continue; + + bitVectorSet(&pPrivate->staticInfo.partitionableEngines, rmEngineType); + } + } + + pPrivate->staticInfo.pCIProfiles = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pCIProfiles)); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + pPrivate->staticInfo.pCIProfiles != NULL, + status = NV_ERR_NO_MEMORY; + goto failed;); + portMemSet(pPrivate->staticInfo.pCIProfiles, 0x0, sizeof(*pPrivate->staticInfo.pCIProfiles)); + { + NvU32 entryCount = 0; + NvU32 i; + + NV_ASSERT(pVSI->ciProfiles.profileCount <= NV_ARRAY_ELEMENTS(pPrivate->staticInfo.pCIProfiles->profiles)); + + for (i = 0; i < pVSI->ciProfiles.profileCount; i++) + { + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pCIProfile; + + // Filter any profiles which would not have fit on the VGPU's instance anyway + if (pVSI->ciProfiles.profiles[i].smCount > pVSI->gpuPartitionInfo.smCount) + continue; + + pCIProfile = &pPrivate->staticInfo.pCIProfiles->profiles[entryCount]; + pCIProfile->gfxGpcCount = pVSI->ciProfiles.profiles[i].gfxGpcCount; + pCIProfile->computeSize = pVSI->ciProfiles.profiles[i].computeSize; + pCIProfile->gpcCount = pVSI->ciProfiles.profiles[i].gpcCount; + pCIProfile->physicalSlots = pVSI->ciProfiles.profiles[i].gpcCount; + pCIProfile->veidCount = pVSI->ciProfiles.profiles[i].veidCount; + pCIProfile->smCount = pVSI->ciProfiles.profiles[i].smCount; + + entryCount++; + } + pPrivate->staticInfo.pCIProfiles->profileCount = entryCount; + } + + // Not used by VGPU + pPrivate->staticInfo.pSwizzIdFbMemPageRanges = NULL; + + // Support to be added for skylines on vgpu as part of bug 3424046 + pPrivate->staticInfo.pSkylineInfo = NULL; + + // Publish static data + pPrivate->bInitialized = NV_TRUE; + + // Load fake static info for VGPU + kmigmgrSetStaticInfo_HAL(pGpu, pKernelMIGManager); + + return NV_OK; + +failed: + portMemFree(pPrivate->staticInfo.pProfiles); + pPrivate->staticInfo.pProfiles = NULL; + portMemFree(pPrivate->staticInfo.pSwizzIdFbMemPageRanges); + pPrivate->staticInfo.pSwizzIdFbMemPageRanges = NULL; + portMemFree(pPrivate->staticInfo.pCIProfiles); + pPrivate->staticInfo.pCIProfiles = NULL; + + return status; +} + /*! Initialize static information queried from Physical RM */ NV_STATUS kmigmgrLoadStaticInfo_KERNEL @@ -1116,7 +1301,8 @@ kmigmgrLoadStaticInfo_KERNEL RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status; NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS params = {0}; - NvU32 nv2080EngineMask[NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX]; + ENGTYPE_BIT_VECTOR partitionableNv2080Engines; + NvU32 nv2080EngineType; NV_ASSERT_OR_RETURN(pPrivate != NULL, NV_ERR_INVALID_STATE); @@ -1130,7 +1316,12 @@ kmigmgrLoadStaticInfo_KERNEL // pPrivate->bInitialized = NV_TRUE; - portMemSet(pPrivate->staticInfo.partitionableEngineMask, 0x0, sizeof(pPrivate->staticInfo.partitionableEngineMask)); + bitVectorClrAll(&pPrivate->staticInfo.partitionableEngines); + + if (IS_GSP_CLIENT(pGpu)) + { + NV_CHECK(LEVEL_ERROR, kmigmgrEnableAllLCEs(pGpu, pKernelMIGManager, NV_TRUE) == NV_OK); + } NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, pRmApi->Control(pRmApi, @@ -1141,16 +1332,20 @@ kmigmgrLoadStaticInfo_KERNEL sizeof(params)), failed); - ct_assert(NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX == 2); - - nv2080EngineMask[0] = NvU64_LO32(params.engineMask); - nv2080EngineMask[1] = NvU64_HI32(params.engineMask); + // + // Copy over the engineMask and save it in the staticInfo for later use. + // In staticInfo, we use RMEngineTypes, so convert the nv2080 types before saving. + // + bitVectorFromRaw(&partitionableNv2080Engines, + params.engineMask, + sizeof(params.engineMask)); + FOR_EACH_IN_BITVECTOR(&partitionableNv2080Engines, nv2080EngineType) + { + bitVectorSet(&pPrivate->staticInfo.partitionableEngines, + gpuGetRmEngineType(nv2080EngineType)); + } + FOR_EACH_IN_BITVECTOR_END(); - NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - gpuGetRmEngineTypeCapMask(nv2080EngineMask, - NVGPU_ENGINE_CAPS_MASK_ARRAY_MAX, - pPrivate->staticInfo.partitionableEngineMask), - failed); pPrivate->staticInfo.pSkylineInfo = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pSkylineInfo)); NV_CHECK_OR_ELSE(LEVEL_ERROR, @@ -1200,6 +1395,11 @@ kmigmgrLoadStaticInfo_KERNEL sizeof(*pPrivate->staticInfo.pProfiles)), failed); + if (IS_GSP_CLIENT(pGpu)) + { + NV_CHECK(LEVEL_ERROR, kmigmgrEnableAllLCEs(pGpu, pKernelMIGManager, NV_FALSE) == NV_OK); + } + pPrivate->staticInfo.pSwizzIdFbMemPageRanges = portMemAllocNonPaged(sizeof(*pPrivate->staticInfo.pSwizzIdFbMemPageRanges)); NV_CHECK_OR_ELSE(LEVEL_ERROR, pPrivate->staticInfo.pSwizzIdFbMemPageRanges != NULL, @@ -1271,6 +1471,315 @@ kmigmgrClearStaticInfo_VF } } +/*! + * @brief Save MIG topology from VGPU static info to persistence, if available. + */ +NV_STATUS +kmigmgrSaveToPersistenceFromVgpuStaticInfo_VF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY *pTopologySave; + GPUMGR_SAVE_GPU_INSTANCE *pGPUInstanceSave; + ENGTYPE_BIT_VECTOR engines; + NvBool bTopologyValid; + NvU32 GIIdx; + NvU32 CIIdx; + NvU32 savedCIIdx; + NvU32 assignableGrMask; + NvU32 i; + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_ARGUMENT); + + NV_CHECK_OR_RETURN(LEVEL_SILENT, + gpumgrGetSystemMIGInstanceTopo(gpuGetDBDF(pGpu), &pTopologySave), + NV_OK); + + // check VSI to see whether we've restored from it before. + NV_CHECK_OR_RETURN(LEVEL_SILENT, !pTopologySave->bVgpuRestoredFromStaticInfo, NV_OK); + + // Check to see whether there is anything already saved + for (GIIdx = 0; GIIdx < NV_ARRAY_ELEMENTS(pTopologySave->saveGI); ++GIIdx) + { + pGPUInstanceSave = &pTopologySave->saveGI[GIIdx]; + if (pGPUInstanceSave->bValid) + break; + } + + bTopologyValid = (GIIdx < NV_ARRAY_ELEMENTS(pTopologySave->saveGI)); + NV_CHECK_OR_RETURN(LEVEL_SILENT, !bTopologyValid, NV_OK); + + // There can only be one saved GPU instance in VGPU + pGPUInstanceSave = &pTopologySave->saveGI[0]; + + pGPUInstanceSave->bValid = NV_TRUE; + pGPUInstanceSave->swizzId = 0; + pGPUInstanceSave->giInfo.partitionFlags = (DRF_DEF(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, _FULL) | + DRF_DEF(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, _FULL) ); + + gpumgrCacheCreateGpuInstance(pGpu, pGPUInstanceSave->swizzId); + + bitVectorClrAll(&engines); + + if (pVSI->gpuPartitionInfo.grEngCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_GR(0), + RM_ENGINE_TYPE_GR(pVSI->gpuPartitionInfo.grEngCount - 1))); + + if (pVSI->gpuPartitionInfo.ceCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_COPY(0), + RM_ENGINE_TYPE_COPY(pVSI->gpuPartitionInfo.ceCount - 1))); + + if (pVSI->gpuPartitionInfo.nvDecCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_NVDEC(0), + RM_ENGINE_TYPE_NVDEC(pVSI->gpuPartitionInfo.nvDecCount - 1))); + + if (pVSI->gpuPartitionInfo.nvEncCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_NVENC(0), + RM_ENGINE_TYPE_NVENC(pVSI->gpuPartitionInfo.nvEncCount - 1))); + + if (pVSI->gpuPartitionInfo.nvJpgCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_NVJPEG(0), + RM_ENGINE_TYPE_NVJPEG(pVSI->gpuPartitionInfo.nvJpgCount - 1))); + + if (pVSI->gpuPartitionInfo.nvOfaCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_OFA(0), + RM_ENGINE_TYPE_OFA(pVSI->gpuPartitionInfo.nvOfaCount - 1))); + + bitVectorToRaw(&engines, + pGPUInstanceSave->giInfo.enginesMask, + sizeof(pGPUInstanceSave->giInfo.enginesMask)); + + // Create a mask of GR IDs to later use in restoring + assignableGrMask = 0x0; + for (i = 0; i < pVSI->gpuPartitionInfo.grEngCount; i++) + if (pVSI->gpuPartitionInfo.gpcsPerGr[i] != 0) + assignableGrMask |= NVBIT32(i); + + NV_ASSERT_OR_RETURN(nvPopCount32(assignableGrMask) <= pVSI->execPartitionInfo.execPartCount, NV_ERR_INSUFFICIENT_RESOURCES); + + pGPUInstanceSave->giInfo.veidOffset = 0; + pGPUInstanceSave->giInfo.veidCount = pVSI->gpuPartitionInfo.veidCount; + pGPUInstanceSave->giInfo.gpcMask = DRF_MASK(pVSI->gpuPartitionInfo.gpcCount - 1 : 0); + pGPUInstanceSave->giInfo.virtualGpcCount = pVSI->gpuPartitionInfo.virtualGpcCount; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + osRmCapRegisterSmcPartition(pGpu->pOsRmCaps, &pGPUInstanceSave->pOsRmCaps, pGPUInstanceSave->swizzId)); + + savedCIIdx = 0; + for (CIIdx = 0; CIIdx < pVSI->execPartitionInfo.execPartCount; ++CIIdx) + { + GPUMGR_SAVE_COMPUTE_INSTANCE *pComputeInstanceSave = &pGPUInstanceSave->saveCI[savedCIIdx]; + NVC637_CTRL_EXEC_PARTITIONS_INFO *pExecPartInfo = &pVSI->execPartitionInfo.execPartInfo[CIIdx]; + NvU32 grIdx = portUtilCountTrailingZeros32(assignableGrMask); + ENGTYPE_BIT_VECTOR engines; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, grIdx < RM_ENGINE_TYPE_GR_SIZE, NV_ERR_INVALID_STATE); + + pComputeInstanceSave->bValid = NV_TRUE; + pComputeInstanceSave->ciInfo.sharedEngFlags = pExecPartInfo->sharedEngFlag; + pComputeInstanceSave->id = pVSI->execPartitionInfo.execPartId[CIIdx]; + + // + // This association is not strictly enforced when allocating compute instances + // however, the ordering RM expects here is that the local GR index per GI + // matches with the execPartId that it was created to. Simply perform a non-fatal + // check for logging purposes. + // + NV_CHECK(LEVEL_WARNING, pComputeInstanceSave->id == grIdx); + + bitVectorClrAll(&engines); + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_GR(grIdx), + RM_ENGINE_TYPE_GR(grIdx))); + assignableGrMask &= ~(NVBIT32(grIdx)); + + if (pExecPartInfo->ceCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_COPY(0), + RM_ENGINE_TYPE_COPY(pExecPartInfo->ceCount - 1))); + + if (pExecPartInfo->nvDecCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_NVDEC(0), + RM_ENGINE_TYPE_NVDEC(pExecPartInfo->nvDecCount - 1))); + + if (pExecPartInfo->nvEncCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_NVENC(0), + RM_ENGINE_TYPE_NVENC(pExecPartInfo->nvEncCount - 1))); + + if (pExecPartInfo->nvJpgCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_NVJPEG(0), + RM_ENGINE_TYPE_NVJPEG(pExecPartInfo->nvJpgCount - 1))); + + if (pExecPartInfo->ofaCount > 0) + bitVectorSetRange(&engines, + rangeMake(RM_ENGINE_TYPE_OFA(0), + RM_ENGINE_TYPE_OFA(pExecPartInfo->ofaCount - 1))); + + bitVectorToRaw(&engines, + pComputeInstanceSave->ciInfo.enginesMask, + sizeof(pComputeInstanceSave->ciInfo.enginesMask)); + + pComputeInstanceSave->ciInfo.gpcMask = DRF_MASK(pExecPartInfo->gpcCount - 1 : 0); + pComputeInstanceSave->ciInfo.gfxGpcCount = pExecPartInfo->gfxGpcCount; + pComputeInstanceSave->ciInfo.spanStart = pExecPartInfo->spanStart; + pComputeInstanceSave->ciInfo.smCount = pExecPartInfo->smCount; + pComputeInstanceSave->ciInfo.computeSize = pExecPartInfo->computeSize; + pComputeInstanceSave->ciInfo.veidCount = pExecPartInfo->veidCount; + pComputeInstanceSave->ciInfo.veidOffset = pExecPartInfo->veidStartOffset; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + osRmCapRegisterSmcExecutionPartition(pGPUInstanceSave->pOsRmCaps, + &(pComputeInstanceSave->pOsRmCaps), + pComputeInstanceSave->id)); + + ++savedCIIdx; + } + + // + // Make sure that we never try to restore from static info again, to allow + // guest to change the topology themselves. + // + pTopologySave->bVgpuRestoredFromStaticInfo = NV_TRUE; + + return NV_OK; +} + +/*! + * @brief Sets static KernelMIGManager, KernelGraphicsManager, and partitionInfo inside a vGPU + */ +NV_STATUS +kmigmgrSetStaticInfo_VF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager +) +{ + const KERNEL_MIG_MANAGER_STATIC_INFO *pStaticInfo; + VGPU_STATIC_INFO *pVSI; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + MIG_RESOURCE_ALLOCATION *pResourceAllocation; + NvU32 veidOffset = 0; + NvU32 grIdx; + NV_RANGE memoryRange; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + + pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_OBJECT_NOT_FOUND); + + // If MIG isn't enabled for this VM, nothing to do + NV_CHECK_OR_RETURN(LEVEL_SILENT, IS_MIG_ENABLED(pGpu), NV_OK); + + pStaticInfo = kmigmgrGetStaticInfo(pGpu, pKernelMIGManager); + NV_ASSERT_OR_RETURN(pStaticInfo != NULL, NV_ERR_INVALID_STATE); + + // + // Fill required GPU instance info and create state needed in + // KernelMIGManager/KernelGraphicsManager For legacy MIG vgpu policy, there + // is only one GPU instance with no compute instances, so we statically + // setup its resources taken from plugin and assign swizzID-0 to it inside + // vGPU. For production vgpu policy, guest is responsible for requesting GPU + // instance and compute instance creation, so we initialize RM with the + // correct resource counts and let the rest of the instancing APIs work as + // in host RM. + // + + if (kmigmgrUseLegacyVgpuPolicy(pGpu, pKernelMIGManager)) + { + // + // In legacy flow, mark swizzid 0 as in use, as the GPU instance is + // pre-populated + // + NV_ASSERT_OK_OR_RETURN(kmigmgrSetSwizzIdInUse(pGpu, pKernelMIGManager, 0)); + } + else + { + // + // In Prod flow, copy any GPU instance info retrieved from vpgu static info + // into persistent storage on first driver boot. + // + NV_ASSERT_OK(kmigmgrSaveToPersistenceFromVgpuStaticInfo_HAL(pGpu, pKernelMIGManager)); + } + + if (kmigmgrUseLegacyVgpuPolicy(pGpu, pKernelMIGManager)) + { + // In legacy flow, engines are pre-configured. VEIDs are marked as in-use + kgrmgrSetVeidInUseMask(pGpu, pKernelGraphicsManager, DRF_MASK64(pVSI->gpuPartitionInfo.veidCount - 1 : 0)); + NV_PRINTF(LEVEL_INFO, "VF VEID in use mask: 0x%llX\n", kgrmgrGetVeidInUseMask(pGpu, pKernelGraphicsManager)); + } + + NV_ASSERT_OK_OR_RETURN(memmgrDiscoverMIGPartitionableMemoryRange_HAL(pGpu, pMemoryManager, &memoryRange)); + + memmgrSetMIGPartitionableMemoryRange(pGpu, pMemoryManager, memoryRange); + + if (kmigmgrUseLegacyVgpuPolicy(pGpu, pKernelMIGManager)) + { + GPUMGR_SAVE_GPU_INSTANCE save = { 0 }; + KMIGMGR_CREATE_GPU_INSTANCE_PARAMS params = + { + .type = KMIGMGR_CREATE_GPU_INSTANCE_PARAMS_TYPE_RESTORE, + .inst.restore.pGPUInstanceSave = &save + }; + NvU32 grCount; + NvUuid uuid; + + save.bValid = NV_TRUE; + save.swizzId = 0; + save.giInfo.partitionFlags = (DRF_DEF(2080_CTRL_GPU, _PARTITION_FLAG, _MEMORY_SIZE, _FULL) | + DRF_DEF(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, _FULL) ); + + bitVectorToRaw(&pStaticInfo->partitionableEngines, + save.giInfo.enginesMask, + sizeof(save.giInfo.enginesMask)); + + save.giInfo.veidOffset = 0; + save.giInfo.veidCount = pVSI->gpuPartitionInfo.veidCount; + save.giInfo.gpcMask = DRF_MASK(pVSI->gpuPartitionInfo.gpcCount - 1 : 0); + + NV_ASSERT_OK_OR_RETURN(kmigmgrGenerateGPUInstanceUuid_HAL(pGpu, pKernelMIGManager, 0, &uuid)); + + // Create static GPU instance for legacy vgpu flow + NV_ASSERT_OK_OR_RETURN(kmigmgrSetGPUInstanceInfo(pGpu, pKernelMIGManager, 0/*SwizzID-0*/, uuid.uuid, params)); + NV_ASSERT_OK_OR_RETURN(kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, 0, &pKernelMIGGpuInstance)); + + gpumgrCacheCreateGpuInstance(pGpu, 0); + + pResourceAllocation = &pKernelMIGGpuInstance->resourceAllocation; + pResourceAllocation->virtualGpcCount = pVSI->gpuPartitionInfo.virtualGpcCount; + pResourceAllocation->gfxGpcCount = pVSI->gpuPartitionInfo.gfxGpcCount; + + grCount = kmigmgrCountEnginesOfType(&pResourceAllocation->engines, RM_ENGINE_TYPE_GR(0)); + for (grIdx = 0; grIdx < grCount; ++grIdx) + { + // set VEID mask for grIdx + kgrmgrSetGrIdxVeidMask(pGpu, pKernelGraphicsManager, grIdx, DRF_MASK64(pVSI->gpuPartitionInfo.veidsPerGr[grIdx] - 1:0) << veidOffset); + veidOffset += pVSI->gpuPartitionInfo.veidsPerGr[grIdx]; + + if (pVSI->gpuPartitionInfo.gpcsPerGr[grIdx] != 0) + { + KernelGraphics *pKernelGraphics = GPU_GET_KERNEL_GRAPHICS(pGpu, grIdx); + + kgraphicsInvalidateStaticInfo(pGpu, pKernelGraphics); + NV_ASSERT_OK(kgraphicsLoadStaticInfo_HAL(pGpu, pKernelGraphics, 0)); + } + } + } + + return NV_OK; +} + /*! * @brief Disable RC Watchdog */ @@ -1540,10 +2049,38 @@ kmigmgrIsEngineInInstance_IMPL MIG_INSTANCE_REF ref ) { - RM_ENGINE_TYPE unused; return kmigmgrGetGlobalToLocalEngineType(pGpu, pKernelMIGManager, ref, - globalRmEngType, - &unused) == NV_OK; + globalRmEngType, NULL) == NV_OK; +} + +/*! + * @brief Function to determine whether local RM_ENGINE_TYPE belongs to given + * gpu/compute instance. + * + * @return NV_TRUE if this engine falls within the given instance. NV_FALSE + * otherwise. Non-partitioned engines fall within all instances. + */ +NvBool +kmigmgrIsLocalEngineInInstance_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + RM_ENGINE_TYPE localRmEngType, + MIG_INSTANCE_REF ref +) +{ + ENGTYPE_BIT_VECTOR *pLocalEngines; + + if (!kmigmgrIsEnginePartitionable(pGpu, pKernelMIGManager, localRmEngType)) + { + return NV_TRUE; + } + + pLocalEngines = (ref.pMIGComputeInstance != NULL) ? + &ref.pMIGComputeInstance->resourceAllocation.localEngines : + &ref.pKernelMIGGpuInstance->resourceAllocation.localEngines; + + return bitVectorTest(pLocalEngines, localRmEngType); } /*! @@ -1999,14 +2536,19 @@ kmigmgrRestoreFromPersistence_VF .type = KMIGMGR_CREATE_GPU_INSTANCE_PARAMS_TYPE_RESTORE, .inst.restore.pGPUInstanceSave = pGPUInstanceSave }; - NvU32 swizzId; + NvU32 swizzId = pGPUInstanceSave->swizzId; + NvUuid uuid; if (!pGPUInstanceSave->bValid) continue; + NV_ASSERT_OK_OR_GOTO(status, + kmigmgrGenerateGPUInstanceUuid_HAL(pGpu, pKernelMIGManager, swizzId, &uuid), + fail); + // Create a GPU instance using the saved data NV_CHECK_OK_OR_GOTO(status, LEVEL_WARNING, - kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, &swizzId, restore, NV_TRUE, NV_FALSE), + kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, swizzId, uuid.uuid, restore, NV_TRUE, NV_FALSE), fail); NV_ASSERT_OK_OR_GOTO(status, @@ -2110,6 +2652,24 @@ kmigmgrInitGPUInstanceInfo_IMPL portMemSet(&pKernelMIGGpuInstance->resourceAllocation, 0x0, sizeof(pKernelMIGGpuInstance->resourceAllocation)); } +/*! + * @brief Checks Devinit owned scratch bit to see if MIG is enabled or not + * + * @return NV_TRUE if there is valid GPU instance in VGPU static info + */ +NvBool +kmigmgrIsDevinitMIGBitSet_VF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_FALSE); + + return pVSI->gpuPartitionInfo.swizzId != KMIGMGR_SWIZZID_INVALID; +} + /*! * @brief Function to set device profiling in use */ @@ -2459,14 +3019,24 @@ kmigmgrPrintGPUInstanceInfo_IMPL "Size in VMMU Seg."); NV_PRINTF(LEVEL_INFO, "%s\n", PADDING_STR); - NV_ASSERT_OK_OR_ELSE(status, - kmemsysGetMIGGPUInstanceMemConfigFromSwizzId(pGpu, pKernelMemorySystem, pKernelMIGGpuInstance->swizzId, &pGPUInstanceMemConfig), - return;); - NV_PRINTF(LEVEL_INFO, "| %18llx | %18llx | %18llx |\n", - pGPUInstanceMemConfig->startingVmmuSegment, - (pGPUInstanceMemConfig->startingVmmuSegment + - pGPUInstanceMemConfig->memSizeInVmmuSegment) - 1, - pGPUInstanceMemConfig->memSizeInVmmuSegment); + status = kmemsysGetMIGGPUInstanceMemConfigFromSwizzId(pGpu, pKernelMemorySystem, + pKernelMIGGpuInstance->swizzId, + &pGPUInstanceMemConfig); + if (status == NV_ERR_NOT_SUPPORTED) + { + // Guest does not populate VMMU segment details. + NV_ASSERT_OR_RETURN_VOID(IS_VIRTUAL(pGpu)); + NV_PRINTF(LEVEL_INFO, "| %18s | %18s | %18s |\n", "N/A", "N/A", "N/A"); + } + else + { + NV_ASSERT_OR_RETURN_VOID(status == NV_OK); + NV_PRINTF(LEVEL_INFO, "| %18llx | %18llx | %18llx |\n", + pGPUInstanceMemConfig->startingVmmuSegment, + (pGPUInstanceMemConfig->startingVmmuSegment + + pGPUInstanceMemConfig->memSizeInVmmuSegment) - 1, + pGPUInstanceMemConfig->memSizeInVmmuSegment); + } NV_PRINTF(LEVEL_INFO, "%s\n", PADDING_STR); #undef PADDING_STR #endif // NV_PRINTF_LEVEL_ENABLED(LEVEL_INFO) @@ -2481,6 +3051,7 @@ kmigmgrSetGPUInstanceInfo_IMPL OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, NvU32 swizzId, + NvU8 *pUuid, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS params ) { @@ -2519,6 +3090,31 @@ kmigmgrSetGPUInstanceInfo_IMPL pKernelMIGGpuInstance->memRange = addrRange; pKernelMIGGpuInstance->pMemoryPartitionHeap = pMemoryPartitionHeap; pKernelMIGGpuInstance->partitionFlag = partitionFlag; + portMemCopy(pKernelMIGGpuInstance->uuid.uuid, sizeof(pKernelMIGGpuInstance->uuid.uuid), + pUuid, NVC637_UUID_LEN); + + // + // Offloading of VGPU to GSP requires that the memRange in KERNEL_MIG_GPU_INSTANCE + // be populated, as the plugin will query only within GSP for GPU INSTANCE information. + // CPU-RM is the entity which actually calculates and allocates memory, so with + // VGPU offloaded, GSP-RM must be updated with the memRange info. + // + if (IS_GSP_CLIENT(pGpu) && !IS_VIRTUAL(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS memParams; + + memParams.swizzId = pKernelMIGGpuInstance->swizzId; + memParams.memAddrRange.lo = pKernelMIGGpuInstance->memRange.lo; + memParams.memAddrRange.hi = pKernelMIGGpuInstance->memRange.hi; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_KMIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE, + &memParams, + sizeof(memParams))); + } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kmigmgrGetProfileByPartitionFlag(pGpu, pKernelMIGManager, partitionFlag, &pKernelMIGGpuInstance->pProfile)); @@ -2623,9 +3219,9 @@ kmigmgrGetLocalToGlobalEngineType_IMPL &ref.pMIGComputeInstance->resourceAllocation.engines, &localEngType) != NV_OK) { NV_PRINTF(LEVEL_INFO, - "Compute instance Local Engine type 0x%x is not allocated to Compute instance\n", - localEngType); - return NV_ERR_INVALID_ARGUMENT; + "Compute instance Local Engine type 0x%x is not allocated to Compute instance\n", + localEngType); + return NV_ERR_INVALID_ARGUMENT; } } @@ -2633,10 +3229,10 @@ kmigmgrGetLocalToGlobalEngineType_IMPL if (kmigmgrEngineTypeXlate(&ref.pKernelMIGGpuInstance->resourceAllocation.localEngines, localEngType, &ref.pKernelMIGGpuInstance->resourceAllocation.engines, &localEngType) != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "GPU instance Local Engine type 0x%x is not allocated to GPU instance\n", - localEngType); - return NV_ERR_INVALID_ARGUMENT; + NV_PRINTF(LEVEL_INFO, + "GPU instance Local Engine type 0x%x is not allocated to GPU instance\n", + localEngType); + return NV_ERR_INVALID_ARGUMENT; } *pGlobalEngType = localEngType; @@ -2668,7 +3264,10 @@ kmigmgrGetGlobalToLocalEngineType_IMPL // Return same engineId as global if called for non-partitioned // rm engine types like host engines, PMU SEC etc. // - *pLocalEngType = globalEngType; + if (pLocalEngType != NULL) + { + *pLocalEngType = globalEngType; + } return NV_OK; } @@ -2676,10 +3275,13 @@ kmigmgrGetGlobalToLocalEngineType_IMPL if (kmigmgrEngineTypeXlate(&ref.pKernelMIGGpuInstance->resourceAllocation.engines, globalEngType, &ref.pKernelMIGGpuInstance->resourceAllocation.localEngines, &globalEngType) != NV_OK) { - NV_PRINTF(LEVEL_INFO, - "Global Engine type 0x%x is not allocated to GPU instance\n", - globalEngType); - return NV_ERR_INVALID_ARGUMENT; + if (pLocalEngType != NULL) + { + NV_PRINTF(LEVEL_INFO, + "Global Engine type 0x%x is not allocated to GPU instance\n", + globalEngType); + } + return NV_ERR_INVALID_ARGUMENT; } if (ref.pMIGComputeInstance != NULL) @@ -2688,14 +3290,20 @@ kmigmgrGetGlobalToLocalEngineType_IMPL if (kmigmgrEngineTypeXlate(&ref.pMIGComputeInstance->resourceAllocation.engines, globalEngType, &ref.pMIGComputeInstance->resourceAllocation.localEngines, &globalEngType) != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "GPU instance Local Engine type 0x%x is not allocated to compute instance\n", - globalEngType); - return NV_ERR_INVALID_ARGUMENT; + if (pLocalEngType != NULL) + { + NV_PRINTF(LEVEL_ERROR, + "GPU instance Local Engine type 0x%x is not allocated to compute instance\n", + globalEngType); + } + return NV_ERR_INVALID_ARGUMENT; } } - *pLocalEngType = globalEngType; + if (pLocalEngType != NULL) + { + *pLocalEngType = globalEngType; + } return NV_OK; } @@ -3132,6 +3740,13 @@ kmigmgrDescribeGPUInstances_IMPL entryCount = 0; for (i = 0; i < pStaticInfo->pProfiles->count; ++i) { + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + pParams->partitionDescs[entryCount].memorySize = pVSI->gpuPartitionInfo.memSize; + } + else { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); NV_RANGE addrRange = NV_RANGE_EMPTY; @@ -3352,24 +3967,83 @@ kmigmgrAllocComputeInstanceHandles_IMPL failed); } - { - NVC638_ALLOCATION_PARAMETERS params; - portMemSet(¶ms, 0, sizeof(params)); - params.execPartitionId = pMIGComputeInstance->id; - NV_ASSERT_OK_OR_GOTO(status, - pRmApi->Alloc(pRmApi, hClient, hGPUInstanceSubscription, &hComputeInstanceSubscription, AMPERE_SMC_EXEC_PARTITION_REF, ¶ms, sizeof(params)), - failed); - } + { + NVC638_ALLOCATION_PARAMETERS params; + portMemSet(¶ms, 0, sizeof(params)); + params.execPartitionId = pMIGComputeInstance->id; + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Alloc(pRmApi, hClient, hGPUInstanceSubscription, &hComputeInstanceSubscription, AMPERE_SMC_EXEC_PARTITION_REF, ¶ms, sizeof(params)), + failed); + } + + pMIGComputeInstance->instanceHandles.hClient = hClient; + pMIGComputeInstance->instanceHandles.hSubdevice = hSubdevice; + pMIGComputeInstance->instanceHandles.hSubscription = hComputeInstanceSubscription; + + return NV_OK; + +failed: + pRmApi->Free(pRmApi, hClient, hClient); + return status; +} + +/*! + * @brief Get Compute Instance UUID + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] swizzId GPU instance swizz ID + * @param[IN] globalGrIdx physical syspipe ID + * @param[OUT] pUuid Compute Instance UUID + */ +NV_STATUS +kmigmgrGenerateComputeInstanceUuid_VF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 swizzId, + NvU32 globalGrIdx, + NvUuid *pUuid +) +{ + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NvU16 chipId = DRF_VAL(_PMC, _BOOT_42, _CHIP_ID, pGpu->chipId1); + NvU64 gid; + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); - pMIGComputeInstance->instanceHandles.hClient = hClient; - pMIGComputeInstance->instanceHandles.hSubdevice = hSubdevice; - pMIGComputeInstance->instanceHandles.hSubscription = hComputeInstanceSubscription; + portMemCopy(&gid, sizeof(gid), pVSI->gidInfo.data, sizeof(gid)); + + // + // We can't use PDI for the vGPU use-case. We need a unique ID per VM. + // So, for vGPU, read the first 64-bits from the host generated UUID. + // These bits represent a timestamp, which should be unique per VM. + // + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + nvGenerateSmcUuid(chipId, gid, swizzId, globalGrIdx, pUuid)); return NV_OK; +} -failed: - pRmApi->Free(pRmApi, hClient, hClient); - return status; +/*! + * @brief Get GPU Instance UUID + * + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] swizzId GPU instance swizz ID + * @param[OUT] pUuid GPU Instance UUID + */ +NV_STATUS +kmigmgrGenerateGPUInstanceUuid_VF +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 swizzId, + NvUuid *pUuid +) +{ + return kmigmgrGenerateComputeInstanceUuid_HAL( + pGpu, pKernelMIGManager, swizzId, GR_INDEX_INVALID, pUuid); } /*! @@ -3526,8 +4200,7 @@ kmigmgrCreateComputeInstances_VF pConfigRequestPerCi[CIIdx].veidSpanStart = spanStart; pCIProfile = &pConfigRequestPerCi[CIIdx].profile; ctsId = KMIGMGR_CTSID_INVALID; - if ((kmigmgrGetComputeProfileFromSmCount(pGpu, pKernelMIGManager, smCount, pCIProfile) == NV_OK) || - (kmigmgrGetComputeProfileFromGpcCount_HAL(pGpu, pKernelMIGManager, gpcCount, pCIProfile) == NV_OK)) + if (kmigmgrGetComputeProfileForRequest(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, smCount, gpcCount, pCIProfile) == NV_OK) { // CTS and Span allocation is done early to help prevent spurious requests if (bIsCTSRequired) @@ -3547,8 +4220,6 @@ kmigmgrCreateComputeInstances_VF shadowCTSInUseMask, ctsId), status = NV_ERR_STATE_IN_USE; goto done; ); - - shadowCTSInUseMask |= NVBIT64(ctsId); } else { @@ -3565,6 +4236,9 @@ kmigmgrCreateComputeInstances_VF done); } + NV_CHECK_OR_ELSE(LEVEL_ERROR, ctsId < KMIGMGR_MAX_GPU_CTSID, + status = NV_ERR_INVALID_STATE; goto done; ); + pConfigRequestPerCi[CIIdx].veidSpanStart = kmigmgrGetSpanStartFromCTSId(pGpu, pKernelMIGManager, ctsId); shadowCTSInUseMask |= NVBIT64(ctsId); } @@ -5060,6 +5734,28 @@ kmigmgrInvalidateGPUInstance_IMPL // Initialize gpu instance info to initial value kmigmgrInitGPUInstanceInfo(pGpu, pKernelMIGManager, pKernelMIGGpuInstance); + // + // Only partitions in which VGPU guests are booted require changing + // engine interrupt vectors to deterministic values for migration. + // + if (IS_GSP_CLIENT(pGpu) && gpuIsSriovEnabled(pGpu)) + { + Intr *pIntr = GPU_GET_INTR(pGpu); + + // + // When running in GSP offload mode, KernelRM must re-fetch the + // interrupt table on every change to the MIG partitioning layout. + // + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + intrStateUnload_HAL(pGpu, pIntr, GPU_STATE_FLAGS_PRESERVING)); + + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + intrInitInterruptTable_HAL(pGpu, pIntr)); + + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + intrStateLoad_HAL(pGpu, pIntr, GPU_STATE_FLAGS_PRESERVING)); + } + return rmStatus; } @@ -5499,7 +6195,7 @@ kmigmgrSetMIGState_FWCLIENT // Disable ctx buf pool after freeing any resources that uses it. // Leave enabled on platforms that support it outside MIG. // - pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, + pGpu->setProperty(pGpu, PDB_PROP_GPU_MOVE_CTX_BUFFERS_TO_PMA, gpuIsCtxBufAllocInPmaSupported_HAL(pGpu)); // @@ -5575,19 +6271,21 @@ kmigmgrSetMIGState_FWCLIENT /*! * @brief Function to create or destroy GPU instance * - * @param[IN] pGpu - * @param[IN] pKernelMIGManager - * @param[OUT] pSwizzId Output swizzId allocated for this gpu instance - * @param[IN] params Gpu instance creation parameters - * @param[IN] bValid Flag stating if gpu instance is created or destroyed - * @param[IN] bCreateCap Flag stating if MIG capabilities needs to be created + * @param[IN] pGpu + * @param[IN] pKernelMIGManager + * @param[IN] swizzId SwizzId allocated for this gpu instance + * @param[IN] pUuid UUID of the GPU instance + * @param[IN] params Gpu instance creation parameters + * @param[IN] bValid Flag stating if gpu instance is created or destroyed + * @param[IN] bCreateCap Flag stating if MIG capabilities needs to be created */ NV_STATUS kmigmgrCreateGPUInstance_IMPL ( OBJGPU *pGpu, KernelMIGManager *pKernelMIGManager, - NvU32 *pSwizzId, + NvU32 swizzId, + NvU8 *pUuid, KMIGMGR_CREATE_GPU_INSTANCE_PARAMS params, NvBool bValid, NvBool bCreateCap @@ -5608,10 +6306,8 @@ kmigmgrCreateGPUInstance_IMPL // if (params.type == KMIGMGR_CREATE_GPU_INSTANCE_PARAMS_TYPE_RESTORE) { - NvU32 swizzId = params.inst.restore.pGPUInstanceSave->swizzId; NV_ASSERT_OR_RETURN(!kmigmgrIsSwizzIdInUse(pGpu, pKernelMIGManager, swizzId), NV_ERR_INVALID_STATE); - *pSwizzId = swizzId; } // @@ -5626,17 +6322,17 @@ kmigmgrCreateGPUInstance_IMPL } NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrSetGPUInstanceInfo(pGpu, pKernelMIGManager, *pSwizzId, params), invalidate); + kmigmgrSetGPUInstanceInfo(pGpu, pKernelMIGManager, swizzId, pUuid, params), invalidate); // Mark swizzId as "in-use" in cached mask NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrSetSwizzIdInUse(pGpu, pKernelMIGManager, *pSwizzId), invalidate); + kmigmgrSetSwizzIdInUse(pGpu, pKernelMIGManager, swizzId), invalidate); NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, *pSwizzId, &pKernelMIGGpuInstance), invalidate); + kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, swizzId, &pKernelMIGGpuInstance), invalidate); NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, - kmigmgrAllocGPUInstanceHandles(pGpu, *pSwizzId, pKernelMIGGpuInstance), invalidate); + kmigmgrAllocGPUInstanceHandles(pGpu, swizzId, pKernelMIGGpuInstance), invalidate); NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, kmigmgrInitGPUInstanceBufPools(pGpu, pKernelMIGManager, pKernelMIGGpuInstance), invalidate); @@ -5683,6 +6379,43 @@ kmigmgrCreateGPUInstance_IMPL NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, kmigmgrInitGPUInstanceScrubber(pGpu, pKernelMIGManager, pKernelMIGGpuInstance), invalidate); + // + // Only partitions in which VGPU guests are booted require changing + // engine interrupt vectors to deterministic values for migration. + // + if (IS_GSP_CLIENT(pGpu) && gpuIsSriovEnabled(pGpu)) + { + Intr *pIntr = GPU_GET_INTR(pGpu); + + // + // Making changes to MIG partition structure reassigns engine interrupts + // of the engines assigned to a partition. This is done so that a guest + // VM sees the same vectors across a migration (suspend/resume / cloning + // / resuming from a snapshot, etc.). + // + // Physical RM will update the interrupt table to reflect the actual + // changes made to engine interrupts. + // + // When running in GSP offload mode, KernelRM must re-fetch the + // interrupt table on every change to the MIG partitioning layout. + // + // The changes to partitions as well as preparing an existing partition + // to boot a VM are done together on Physical RM in + // NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK. + // + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, + intrStateUnload_HAL(pGpu, pIntr, GPU_STATE_FLAGS_PRESERVING), + invalidate); + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, + intrInitInterruptTable_HAL(pGpu, pIntr), + invalidate); + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, + intrStateLoad_HAL(pGpu, pIntr, GPU_STATE_FLAGS_PRESERVING), + invalidate); + } + // // Register gpu instance with the capability framework only if it explicitly // requested. Otherwise, we rely on the persistent state. @@ -5696,16 +6429,16 @@ kmigmgrCreateGPUInstance_IMPL } else { - NV_PRINTF(LEVEL_INFO, "Invalidating swizzId - %d.\n", *pSwizzId); + NV_PRINTF(LEVEL_INFO, "Invalidating swizzId - %d.\n", swizzId); NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, - kmigmgrInvalidateGPUInstance(pGpu, pKernelMIGManager, *pSwizzId, NV_FALSE)); + kmigmgrInvalidateGPUInstance(pGpu, pKernelMIGManager, swizzId, NV_FALSE)); } return rmStatus; invalidate: - kmigmgrInvalidateGPUInstance(pGpu, pKernelMIGManager, *pSwizzId, NV_FALSE); + kmigmgrInvalidateGPUInstance(pGpu, pKernelMIGManager, swizzId, NV_FALSE); return rmStatus; } @@ -6054,7 +6787,107 @@ kmigmgrUpdateCiConfigForVgpu_IMPL NvBool bDelete ) { - return NV_ERR_NOT_SUPPORTED; + NvU32 i; + NV_STATUS status = NV_OK; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + RsClient *pRsClient; + GPUInstanceSubscription *pGPUInstanceSubscription; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + Subdevice *pSubdevice; + + if (!(IS_GSP_CLIENT(pGpu) && IS_MIG_IN_USE(pGpu) && + IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu))) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_ASSERT_OR_RETURN(execPartCount <= NVC637_CTRL_MAX_EXEC_PARTITIONS, + NV_ERR_INVALID_ARGUMENT); + + // Get hostVgpuDevice from provided GFID and validate the subscription + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kvgpumgrGetHostVgpuDeviceFromGfid(pGpu->gpuId, gfid, + &pKernelHostVgpuDevice)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, serverGetClientUnderLock(&g_resServ, pKernelHostVgpuDevice->hMigClient, + &pRsClient)); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, subdeviceGetByInstance(pRsClient, pKernelHostVgpuDevice->hMigDevice, 0, + &pSubdevice)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + gisubscriptionGetGPUInstanceSubscription(pRsClient, RES_GET_HANDLE(pSubdevice), + &pGPUInstanceSubscription)); + + pKernelMIGGpuInstance = gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription); + + if (!bDelete) + { + NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS execPartExportParams; + + // Create the execution partition state on CPU + for (i = 0; i < execPartCount; i++) + { + GPUMGR_SAVE_COMPUTE_INSTANCE save; + KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS restore = + { + .type = KMIGMGR_CREATE_COMPUTE_INSTANCE_PARAMS_TYPE_RESTORE, + .inst.restore.pComputeInstanceSave = &save, + }; + + portMemSet(&execPartExportParams, 0, sizeof(execPartExportParams)); + execPartExportParams.id = pExecPartId[i]; + + // Retrieve the CI state created by GSP-RM, then restore it to CPU-RM + NV_ASSERT_OK_OR_GOTO(status, + pRmApi->Control(pRmApi, + pKernelMIGGpuInstance->instanceHandles.hClient, + pKernelMIGGpuInstance->instanceHandles.hSubscription, + NVC637_CTRL_CMD_EXEC_PARTITIONS_EXPORT, + &execPartExportParams, + sizeof(execPartExportParams)), + failed); + + portMemSet(&save, 0, sizeof(save)); + save.bValid = NV_TRUE; + save.id = pExecPartId[i]; + save.ciInfo = execPartExportParams.info; + + NV_ASSERT_OK_OR_GOTO(status, + kmigmgrCreateComputeInstances_HAL(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, + NV_FALSE, restore, &pExecPartId[i], NV_TRUE), + failed); + } + } + else + { + for (i = 0; i < execPartCount; i++) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kmigmgrDeleteComputeInstance(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, + pExecPartId[i], NV_FALSE)); + } + } + + // Generate a CPU event to notify CPU clients of updated config + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_SMC_CONFIG_UPDATE, NULL, + 0, 0, 0); + return NV_OK; + +failed: + // Send an RPC to GSP-RM to cleanup the state as we failed the call + if (!bDelete) + { + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS params; + portMemSet(¶ms, 0, sizeof(params)); + params.execPartCount = 1; + params.execPartId[0] = pExecPartId[i]; + NV_RM_RPC_CONTROL(pGpu, pKernelMIGGpuInstance->instanceHandles.hClient, + pKernelMIGGpuInstance->instanceHandles.hSubscription, + NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE, ¶ms, + sizeof(params), status); + } + + return status; } // Control call for getting active gpu instance Ids @@ -6123,7 +6956,7 @@ subdeviceCtrlCmdGpuGetPartitionCapacity_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - NV_CHECK_OR_RETURN(LEVEL_INFO, IS_MIG_ENABLED(pGpu), NV_ERR_NOT_SUPPORTED); + NV_CHECK_OR_RETURN(LEVEL_INFO, kmigmgrIsMIGSupported(pGpu, pKernelMIGManager), NV_ERR_NOT_SUPPORTED); if (IS_VIRTUAL(pGpu)) { @@ -6212,11 +7045,6 @@ subdeviceCtrlCmdGpuDescribePartitions_IMPL return NV_ERR_NOT_SUPPORTED; } - if (!IS_MIG_ENABLED(pGpu)) - { - NV_PRINTF(LEVEL_ERROR, "Entered MIG API with MIG disabled.\n"); - } - return kmigmgrDescribeGPUInstances(pGpu, pKernelMIGManager, pParams); } @@ -6317,6 +7145,8 @@ _kmigmgrProcessGPUInstanceEntry sizeof(*pParams)), cleanup_smc_state); pEntry->swizzId = pParams->partitionInfo[0].swizzId; + portMemCopy(&pEntry->uuid, sizeof(pEntry->uuid), + &pParams->partitionInfo[0].uuid, sizeof(pParams->partitionInfo[0].uuid)); } if (IS_GSP_CLIENT(pGpu)) @@ -6335,8 +7165,8 @@ _kmigmgrProcessGPUInstanceEntry // Step 3, 4, 5, 6: Create / delete gpu instance NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, &pEntry->swizzId, request, pEntry->bValid, - NV_TRUE /* create MIG capabilities */), + kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, pEntry->swizzId, pEntry->uuid, + request, pEntry->bValid, NV_TRUE /* create MIG capabilities */), cleanup_rpc); } @@ -6631,6 +7461,35 @@ subdeviceCtrlCmdGpuGetPartitions_IMPL pParams->queryPartitionInfo[i].validGfxCTSIdMask = ref.pKernelMIGGpuInstance->pProfile->validGfxCTSIdMask; pParams->queryPartitionInfo[i].bValid = NV_TRUE; + if (IS_VIRTUAL(pGpu)) + { + NV_RANGE span = NV_RANGE_EMPTY; + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_ELSE(pVSI != NULL, + rmStatus = NV_ERR_OBJECT_NOT_FOUND; goto done); + + // VGPU doesn't support this + pParams->queryPartitionInfo[i].bPartitionError = NV_FALSE; + pParams->queryPartitionInfo[i].span.lo = span.lo; + pParams->queryPartitionInfo[i].span.hi = span.hi; + + // Fill GPCs associated with every GR + j = 0; + FOR_EACH_IN_BITVECTOR(&pResourceAllocation->engines, rmEngineType) + { + if (!RM_ENGINE_TYPE_IS_GR(rmEngineType)) + continue; + + pParams->queryPartitionInfo[i].gpcsPerGr[j] = pVSI->gpuPartitionInfo.gpcsPerGr[j]; + pParams->queryPartitionInfo[i].veidsPerGr[j] = pVSI->gpuPartitionInfo.veidsPerGr[j]; + pParams->queryPartitionInfo[i].virtualGpcsPerGr[j] = pVSI->gpuPartitionInfo.virtualGpcsPerGr[j]; + pParams->queryPartitionInfo[i].gfxGpcPerGr[j] = pVSI->gpuPartitionInfo.gfxGpcPerGr[j]; + + j++; + } + FOR_EACH_IN_BITVECTOR_END(); + } + else { NV_ASSERT_OR_ELSE(pRpcParams->queryPartitionInfo[i].bValid, rmStatus = NV_ERR_INVALID_STATE; goto done); @@ -6781,7 +7640,8 @@ subdeviceCtrlCmdInternalKMIGmgrImportGPUInstance_IMPL pSave->pOsRmCaps = NULL; portMemCopy(&(pSave->giInfo), sizeof(pSave->giInfo), &pParams->info, sizeof(pParams->info)); - status = kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, &pParams->swizzId, restore, NV_TRUE, NV_FALSE); + status = kmigmgrCreateGPUInstance(pGpu, pKernelMIGManager, pParams->swizzId, pParams->uuid, + restore, NV_TRUE, NV_FALSE); portMemFree(pSave); NV_CHECK_OR_GOTO(LEVEL_ERROR, status == NV_OK, cleanup_rpc); @@ -7234,6 +8094,92 @@ kmigmgrComputeProfileSizeToCTSIdRange_IMPL } } +/*! + * @brief Returns the span covered by the CTS ID + */ +NV_RANGE +kmigmgrCtsIdToSpan_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 ctsId +) +{ + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + NvU32 spanLen; + NV_RANGE ret; + + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized, NV_RANGE_EMPTY); + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo != NULL, NV_RANGE_EMPTY); + + spanLen = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS].data; + + if (kmigmgrIsA100ReducedConfig(pGpu, pKernelMIGManager)) + spanLen /= 2; + + switch (ctsId) + { + case 0: + ret = rangeMake(0, spanLen - 1); + break; + case 1: + case 3: + ret = rangeMake(0, (spanLen/2) - 1); + break; + case 2: + case 4: + ret = rangeMake(spanLen/2, spanLen - 1); + break; + case 5: + case 9: + ret = rangeMake(0, (spanLen/4) - 1); + break; + case 6: + case 10: + ret = rangeMake((spanLen/4), (spanLen/2) - 1); + break; + case 7: + case 11: + ret = rangeMake((spanLen/2), (3*(spanLen/4)) - 1); + break; + case 8: + case 12: + ret = rangeMake((3*(spanLen/4)), spanLen - 1); + break; + case 13: + ret = rangeMake(0, 0); + break; + case 14: + ret = rangeMake(1, 1); + break; + case 15: + ret = rangeMake(2, 2); + break; + case 16: + ret = rangeMake(3, 3); + break; + case 17: + ret = rangeMake(4, 4); + break; + case 18: + ret = rangeMake(5, 5); + break; + case 19: + ret = rangeMake(6, 6); + break; + case 20: + ret = rangeMake(7, 7); + break; + default: + NV_PRINTF(LEVEL_ERROR, "Unsupported CTS ID 0x%x\n", ctsId); + DBG_BREAKPOINT(); + ret = NV_RANGE_EMPTY; + break; + } + + return ret; +} + /*! * @brief Function to get next free CTS ID * @@ -7613,6 +8559,11 @@ kmigmgrIsCTSIdAvailable_IMPL return !!((ctsIdValidMask & ~invalidMask) & NVBIT64(ctsId)); } +#define _kmigmgrReadRegistryDword(pGpu, pKernelMIGManager, pRegParmStr, pData) \ + ((pKernelMIGManager)->bGlobalBootConfigUsed \ + ? osGetNvGlobalRegistryDword((pGpu), (pRegParmStr), (pData)) \ + : osReadRegistryDword((pGpu), (pRegParmStr), (pData))) + /*! * @brief Read MIG boot config from the registry * @@ -7640,7 +8591,7 @@ _kmigmgrReadBootConfig char regStr[sizeof(NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI(0))]; nvDbgSnprintf(regStr, sizeof(regStr), NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_GI(%u), i); - if (osReadRegistryDword(pGpu, regStr, &data32) != NV_OK) + if (_kmigmgrReadRegistryDword(pGpu, pKernelMIGManager, regStr, &data32) != NV_OK) { // Do not break here, so we could later check if there are any holes in the config continue; @@ -7675,7 +8626,7 @@ _kmigmgrReadBootConfig } // Read compute instance assignment regkey - if (osReadRegistryDword(pGpu, NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT, &data32) == NV_OK) + if (_kmigmgrReadRegistryDword(pGpu, pKernelMIGManager, NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT, &data32) == NV_OK) { NV_PRINTF(LEVEL_INFO, "Found a CI assignment regkey '" NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI_ASSIGNMENT "': value=%x", data32); @@ -7693,7 +8644,7 @@ _kmigmgrReadBootConfig char regStr[sizeof(NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI(0))]; nvDbgSnprintf(regStr, sizeof(regStr), NV_REG_STR_RM_MIG_BOOT_CONFIGURATION_CI(%u), i); - if (osReadRegistryDword(pGpu, regStr, &data32) != NV_OK) + if (_kmigmgrReadRegistryDword(pGpu, pKernelMIGManager, regStr, &data32) != NV_OK) { // If the CI entry is not specified, its assignment should be 0 if (pBootConfig->CIs[i].GIIdx != 0) @@ -7897,3 +8848,154 @@ kmigmgrRestoreFromBootConfig_PF return status; } + +/*! + * Returns the Smallest Compute size (NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_*) + * that is supported on this GPU. + * + * @param[in] pGpu - OBJGPU + * @param[in] pKernelMIGManager - KernelMIGManager Object + * @param[out] pSmallestComputeSize - NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_* flag for the smallest supported size. + * This should be used only for MIG Supported GPUs. + * + * @return NV_OK on success, + * NV_ERR_NOT_SUPPORTED when the MaxMIG count is unsupported + * NV_ERR_INVALID_STATE When this is called before the internal data is initialized + */ +NV_STATUS +kmigmgrGetSmallestGpuInstanceSize_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + NvU32 *pSmallestComputeSize +) +{ + NvU32 maxMIG; + KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu); + + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->bInitialized, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo != NULL, NV_ERR_INVALID_STATE); + + maxMIG = kgrmgrGetLegacyKGraphicsStaticInfo(pGpu, pKernelGraphicsManager)->pGrInfo->infoList[NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES].data; + switch (maxMIG) + { + case 8: + *pSmallestComputeSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_EIGHTH; + break; + case 1: + *pSmallestComputeSize = NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL; + break; + default: + NV_PRINTF(LEVEL_ERROR, "maxMIG(%d) is unsupported\n", maxMIG); + return NV_ERR_NOT_SUPPORTED; + break; + } + + return NV_OK; +} +/*! + * @brief Function to lookup a compute profile for a sm or gpc count. This function + * has the caller provide a KERNEL_MIG_GPU_INSTANCE object, to catch requests + * which lie outside the normal bounds of the GPU instance. + * If the request is not at (or above) the GPU instances limit, then the CI + * profile will be selected by using the smCountRequest first, and only use + * gpcCount if the SM count look-up fails. + * + * @param[in] pGpu + * @param[in] pKernelMIGManager + * @param[in] pKernelMIGGpuInstance GPU instance for which the request was made + * @param[in] smCountRequest SM Count to look up the associated compute profile + * @param[in] gpcCountRequest GPC Count to look up the associated compute profile if SM lookup fails + * @param[out] pProfile Pointer to NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE struct filled with + * a copy of the compute profile info associated with the requested SM or GPC count. + */ +NV_STATUS +kmigmgrGetComputeProfileForRequest_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance, + NvU32 smCountRequest, + NvU32 gpcCountRequest, + NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE *pProfile +) +{ + NvU32 computeSize; + NV_ASSERT_OR_RETURN(pProfile != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_ERR_INVALID_ARGUMENT); + + // If SM Count is >= the GI's total size, use GI's computeSize as CI profile + computeSize = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG, _COMPUTE_SIZE, pKernelMIGGpuInstance->partitionFlag); + if (!IS_SILICON(pGpu) && + (pKernelMIGGpuInstance->resourceAllocation.smCount <= smCountRequest)) + { + NV_PRINTF(LEVEL_INFO, "CI request is at GPU instance's limit. Using GPU instance's size: %d\n", computeSize); + if (kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, computeSize, pProfile) == NV_OK) + return NV_OK; + } + + if (kmigmgrGetComputeProfileFromSmCount(pGpu, pKernelMIGManager, smCountRequest, pProfile) == NV_OK) + { + return NV_OK; + } + + if (!IS_SILICON(pGpu) && (pKernelMIGGpuInstance->resourceAllocation.gpcCount == gpcCountRequest)) + { + NV_PRINTF(LEVEL_INFO, "CI request is at GPU instance's limit. Using GPU instance's size: %d\n", computeSize); + if (kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, computeSize, pProfile) == NV_OK) + return NV_OK; + } + + // Do basic GPC look-up as last resort if all the above failed + return kmigmgrGetComputeProfileFromGpcCount_HAL(pGpu, pKernelMIGManager, gpcCountRequest, pProfile); +} + +/*! + * @brief Returns if all allocated VEIDs in a GPU instance are contiguous and + * have no holes + */ +NvBool +kmigmgrIsPartitionVeidAllocationContiguous_IMPL +( + OBJGPU *pGpu, + KernelMIGManager *pKernelMIGManager, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance +) +{ + NvU32 ciIdx; + NvU64 instanceVeidMask = 0x0; + NvU64 tempMask; + NvU64 shift; + + // Sanity checks + NV_ASSERT_OR_RETURN(pKernelMIGGpuInstance != NULL, NV_FALSE); + + for (ciIdx = 0; ciIdx < NV_ARRAY_ELEMENTS(pKernelMIGGpuInstance->MIGComputeInstance); ++ciIdx) + { + NvU32 veidStart; + NvU32 veidEnd; + MIG_COMPUTE_INSTANCE *pMIGComputeInstance = &pKernelMIGGpuInstance->MIGComputeInstance[ciIdx]; + + // Skip invalid compute instances + if (!pMIGComputeInstance->bValid) + continue; + + veidStart = pMIGComputeInstance->resourceAllocation.veidOffset; + veidEnd = veidStart + pMIGComputeInstance->resourceAllocation.veidCount - 1; + instanceVeidMask |= DRF_SHIFTMASK64(veidEnd:veidStart); + } + + // If mask is fully populated or empty, no need to check + if ((instanceVeidMask == 0) || (instanceVeidMask == NV_U64_MAX)) + return NV_TRUE; + + // Count the zeros at the end to align mask to always start with "1" + shift = portUtilCountTrailingZeros64(instanceVeidMask); + tempMask = (instanceVeidMask >> shift); + + // + // If the above mask is contiguous "1s", an addition will result in next + // pow-2, so simply check if we have only one-bit set or multiple. + // + return ONEBITSET(tempMask + 1); +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/ada/kern_gmmu_ad102.c b/src/nvidia/src/kernel/gpu/mmu/arch/ada/kern_gmmu_ad102.c new file mode 100644 index 0000000000..e9aaadad1c --- /dev/null +++ b/src/nvidia/src/kernel/gpu/mmu/arch/ada/kern_gmmu_ad102.c @@ -0,0 +1,44 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gpu/mmu/kern_gmmu.h" + +#include "published/ada/ad102/dev_fault.h" + +/*! + * @brief Get the engine ID associated with the max CE + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * + * return engine ID of the max CE + */ +NvU32 +kgmmuGetMaxCeEngineId_AD102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + return NV_PFAULT_MMU_ENG_ID_CE5; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c index be80941184..a13c31d540 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c @@ -28,9 +28,12 @@ #include "gpu/mem_mgr/mem_utils.h" #include "gpu/bus/kern_bus.h" #include "gpu/nvlink/kernel_nvlink.h" +#include "nverror.h" +#include "published/ampere/ga100/dev_fault.h" #include "published/ampere/ga100/dev_vm.h" + /*! * @brief Sets the Invalidation scope field in the register * @@ -343,3 +346,101 @@ kgmmuSetupWarForBug2720120_GA100 } return status; } + +/*! + * @brief Get the engine ID associated with the max CE + * + * @param[in] pGpu GPU object + * @param[in] pKernelGmmu KernelGmmu object + * + * return engine ID of the max CE + */ +NvU32 +kgmmuGetMaxCeEngineId_GA100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + return NV_PFAULT_MMU_ENG_ID_CE9; +} + +/** + * @brief Determine if the fault is P2P unbound Instance Fault + * + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] faultType NvU32 identifier for Fault + * @param[in] faultClientId NvU32 identifier for Client Id + * + * @returns True, if it satisfies the following conditions + * -- FLA engine is not bound + -- Destination side GFID mismatch in P2P/FLA incoming NvLink packets + * False, otherwise + */ +NvBool +kgmmuIsP2PUnboundInstFault_GA100 +( + KernelGmmu *pKernelGmmu, + NvU32 faultType, + NvU32 faultClientId +) +{ + if ((faultType == NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK) && + ((faultClientId >= NV_PFAULT_CLIENT_HUB_PTP_X0 && faultClientId <= NV_PFAULT_CLIENT_HUB_PTP_X5))) + { + return NV_TRUE; + } + + return NV_FALSE; +} + +/** + * @brief handles an engine or PBDMA MMU fault + * + * "engine" is defined as an engine that is downstream of host (graphics, ce, + * etc...). + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] pParsedFaultEntry Parsed Fault entry + * @param[in] pMmuExceptionData FIFO exception packet used + * for printing fault info. + * + * @returns + */ +NV_STATUS +kgmmuServiceMmuFault_GA100 +( + POBJGPU pGpu, + KernelGmmu *pKernelGmmu, + NvP64 pParsedFaultInfo, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData +) +{ + MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry = KERNEL_POINTER_FROM_NvP64(MMU_FAULT_BUFFER_ENTRY *, pParsedFaultInfo); + + // If FLA fault do not reset channel + if (pParsedFaultEntry->mmuFaultEngineId == NV_PFAULT_MMU_ENG_ID_FLA) + { + if (pKernelGmmu->bReportFlaTranslationXid) + { + nvErrorLog_va((void *)pGpu, + DESTINATION_FLA_TRANSLATION_ERROR, + "FLA Fault: inst:0x%x dev:0x%x subdev:0x%x, faulted @ 0x%x_%08x. Fault is of type %s %s", + gpuGetInstance(pGpu), + gpuGetDeviceInstance(pGpu), + pGpu->subdeviceInstance, + pMmuExceptionData->addrHi, + pMmuExceptionData->addrLo, + kgmmuGetFaultTypeString_HAL(pKernelGmmu, pMmuExceptionData->faultType), + kfifoGetFaultAccessTypeString_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), + pMmuExceptionData->accessType)); + } + + return NV_OK; + } + else + { + return kgmmuServiceMmuFault_GV100(pGpu, pKernelGmmu, pParsedFaultInfo, pMmuExceptionData); + } +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c index fd239cb644..91bc1b7ce4 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c @@ -114,7 +114,7 @@ void kgmmuFmtInitLevels_GH10X(KernelGmmu *pKernelGmmu, pLevels[6].virtAddrBitLo = 12; pLevels[6].entrySize = NV_MMU_VER3_PTE__SIZE; pLevels[6].bPageTable = NV_TRUE; - pLevels[5].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PT_4K; + pLevels[6].pageLevelIdTag = MMU_FMT_PT_SURF_ID_PT_4K; } void kgmmuFmtInitPdeMulti_GH10X(KernelGmmu *pKernelGmmu, diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c index 8c79e9c0da..63123e5054 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/hopper/kern_gmmu_gh100.c @@ -28,6 +28,8 @@ #include "vgpu/vgpu_events.h" #include "nv_sriov_defines.h" #include "kernel/gpu/intr/intr.h" +#include "kernel/gpu/gsp/kernel_gsp.h" +#include "kernel/gpu/conf_compute/ccsl.h" #include "mmu/gmmu_fmt.h" #include "published/hopper/gh100/dev_mmu.h" @@ -425,8 +427,6 @@ kgmmuGetFaultRegisterMappings_GH100 *pFaultBufferGet = (NvU32*) &(pFaultBufSharedMem->swGetIndex); *pFaultBufferPut = NvP64_PLUS_OFFSET(bar0Mapping, GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI)); - *pPrefetchCtrl = NvP64_PLUS_OFFSET(bar0Mapping, - GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL)); } else if (index == NON_REPLAYABLE_FAULT_BUFFER) { @@ -472,8 +472,7 @@ kgmmuFaultBufferAllocSharedMemory_GH100 // // On systems with SEV enabled, the fault buffer flush sequence memory should be allocated - // in unprotected sysmem as GSP will be writing to this location to let the guest - // know a flush has finished. + // in unprotected sysmem as GSP will be reading this location to check whether the Replayable buffer is full. // flags |= MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; @@ -562,43 +561,41 @@ kgmmuIssueReplayableFaultBufferFlush_GH100 KernelGmmu *pKernelGmmu ) { - GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuffer; - FAULT_BUFFER_SHARED_MEMORY *pFaultBufSharedMem; - NvU32 gfid; - volatile NvU32 *pFlushSeqAddr; - NvU32 replayableFlushSeqValue; - NV_STATUS status; - RMTIMEOUT timeout; + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu) || !IS_GSP_CLIENT(pGpu)) { - return NV_OK; + return NV_ERR_NOT_SUPPORTED; } - NV_ASSERT_OK_OR_RETURN(vgpuGetCallingContextGfid(pGpu, &gfid)); - - pClientShadowFaultBuffer = &pKernelGmmu->mmuFaultBuffer[gfid].clientShadowFaultBuffer[REPLAYABLE_FAULT_BUFFER]; - pFaultBufSharedMem = KERNEL_POINTER_FROM_NvP64(FAULT_BUFFER_SHARED_MEMORY *, - pClientShadowFaultBuffer->pFaultBufferSharedMemoryAddress); - pFlushSeqAddr = (NvU32*) &(pFaultBufSharedMem->flushBufferSeqNum); - replayableFlushSeqValue = *pFlushSeqAddr; + return kgspIssueNotifyOp_HAL(pGpu, pKernelGsp, GSP_NOTIFY_OP_FLUSH_REPLAYABLE_FAULT_BUFFER_OPCODE, NULL, 0); +} - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_DOORBELL, NV_DOORBELL_NOTIFY_LEAF_SERVICE_REPLAYABLE_FAULT_FLUSH_HANDLE); +/* + * @brief The GSP client can use this function to toggle the prefetch ctrl register state. + * The write of the register will be performed by GSP. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] bEnable Enable/Disable fault on prefetch. + */ +NV_STATUS +kgmmuToggleFaultOnPrefetch_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvBool bEnable +) +{ + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + NvU32 arg = !!bEnable; - while (replayableFlushSeqValue + 1 != *pFlushSeqAddr) + if (!IS_GSP_CLIENT(pGpu)) { - status = gpuCheckTimeout(pGpu, &timeout); - - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "gpuCheckTimeout failed, status = 0x%x\n", status); - return status; - } - osSpinLoop(); + return NV_ERR_NOT_SUPPORTED; } - return NV_OK; + return kgspIssueNotifyOp_HAL(pGpu, pKernelGsp, GSP_NOTIFY_OP_TOGGLE_FAULT_ON_PREFETCH_OPCODE, &arg, 1 /* argc */); } /* @@ -632,3 +629,359 @@ kgmmuReadShadowBufPutIndex_GH100 } return val; } + +/*! + * @brief Check if the given engineID is BAR1 + * + * @param[in] pKernelGmmu KernelGmmu object + * @param[in] engineID Engine ID + * + * @return True if BAR1 + */ +NvBool +kgmmuIsFaultEngineBar1_GH100 +( + KernelGmmu *pKernelGmmu, + NvU32 engineID +) +{ + return (engineID == NV_PFAULT_MMU_ENG_ID_BAR1); +} + +/*! + * @brief Check if the given engineID is BAR2 + * + * @param[in] pKernelGmmu KernelGmmu object + * @param[in] engineID Engine ID + * + * @return True if BAR2 + */ +NvBool +kgmmuIsFaultEngineBar2_GH100 +( + KernelGmmu *pKernelGmmu, + NvU32 engineID +) +{ + return (engineID == NV_PFAULT_MMU_ENG_ID_BAR2); +} + +/*! + * @brief Check if the given engineID is PHYSICAL + * + * @param[in] pKernelGmmu KernelGmmu object + * @param[in] engineID Engine ID + * + * @return True if PHYSICAL + */ +NvBool +kgmmuIsFaultEnginePhysical_GH100 +( + KernelGmmu *pKernelGmmu, + NvU32 engineID +) +{ + return (engineID == NV_PFAULT_MMU_ENG_ID_PHYSICAL); +} + +NvU32 +kgmmuReadClientShadowBufPutIndex_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 gfid, + FAULT_BUFFER_TYPE type +) +{ + return 0; +} + +void +kgmmuWriteClientShadowBufPutIndex_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 gfid, + FAULT_BUFFER_TYPE type, + NvU32 putIndex +) +{ +} + +/* + * @brief Copies a single fault packet from the replayable/non-replayable + * HW fault buffer to the corresponding client shadow buffer + * + * @param[in] pFaultBuffer Pointer to GMMU_FAULT_BUFFER + * @param[in] type Replayable/Non-replayable fault type + * @param[in] getIndex Get pointer of the HW fault buffer + * @param[in] shadowBufPutIndex Put pointer of the shadow buffer + * @param[in] maxBufferEntries Maximum possible entries in the HW buffer + * @param[in] pThreadState Pointer to THREAD_STATE_NODE + * @param[out] pFaultsCopied Number of fault packets copied by the function + * + * @returns NV_STATUS + */ +NV_STATUS +kgmmuCopyFaultPacketToClientShadowBuffer_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + struct GMMU_FAULT_BUFFER *pFaultBuffer, + FAULT_BUFFER_TYPE type, + NvU32 getIndex, + NvU32 shadowBufPutIndex, + NvU32 maxBufferEntries, + THREAD_STATE_NODE *pThreadState, + NvU32 *pFaultsCopied +) +{ + struct HW_FAULT_BUFFER *pHwFaultBuffer = NULL; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuf = NULL; + GMMU_FAULT_PACKET faultPacket; + NvU32 faultPacketsPerPage; + NvU32 faultPacketPageIndex; + NvU32 faultPacketPageOffset; + void *pSrc; + NvU8 *pDst; + NV_STATUS status; + NvU8 *pDstMetadata; + NvU32 metadataStartIndex; + NvU32 metadataPerPage; + NvU32 metadataPageIndex; + NvU32 metadataPageOffset; + NvU8 validBit = 1; + void *pCslCtx = NULL; + + if (!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + return kgmmuCopyFaultPacketToClientShadowBuffer_GV100(pGpu, pKernelGmmu, + pFaultBuffer, + type, + getIndex, + shadowBufPutIndex, + maxBufferEntries, + pThreadState, + pFaultsCopied); + } + + *pFaultsCopied = 0; + + pHwFaultBuffer = &pFaultBuffer->hwFaultBuffers[type]; + pClientShadowFaultBuf = pFaultBuffer->pClientShadowFaultBuffer[type]; + + // Read the fault packet from HW buffer + pSrc = kgmmuFaultBufferGetFault_HAL(pGpu, pKernelGmmu, pHwFaultBuffer, getIndex); + portMemCopy(&faultPacket, sizeof(GMMU_FAULT_PACKET), pSrc, sizeof(GMMU_FAULT_PACKET)); + + // + // The following is the sequence to be followed for replayable faults + // as per production design when Hopper CC is enabled + // + if (type == REPLAYABLE_FAULT_BUFFER) + { + NvU32 nextGetIndex; + + kgmmuFaultBufferClearPackets_HAL(pGpu, pKernelGmmu, pHwFaultBuffer, getIndex, 1); + + // + // Ensure all writes to the current entry are completed before updating the + // GET pointer. + // + portAtomicMemoryFenceStore(); + + nextGetIndex = (getIndex + 1) % maxBufferEntries; + + // Update cached GET to a valid value. + pHwFaultBuffer->cachedGetIndex = nextGetIndex; + + // Increment the GET pointer to enable HW to write new fault packets + kgmmuWriteFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, type, pHwFaultBuffer->cachedGetIndex, pThreadState); + + // Check if there is space in the shadow buffer + if (kgmmuIsReplayableShadowFaultBufferFull_HAL(pGpu, pKernelGmmu, + pClientShadowFaultBuf, + shadowBufPutIndex, + maxBufferEntries)) + { + // The design allows the SW Repalyable shadow fault buffer to overflow. + return NV_OK; + } + } + + faultPacketsPerPage = RM_PAGE_SIZE / sizeof(GMMU_FAULT_PACKET); + faultPacketPageIndex = shadowBufPutIndex / faultPacketsPerPage; + faultPacketPageOffset = shadowBufPutIndex % faultPacketsPerPage; + + pDst = KERNEL_POINTER_FROM_NvP64(NvU8 *, + pClientShadowFaultBuf->pBufferPages[faultPacketPageIndex].pAddress); + pDst += (faultPacketPageOffset * sizeof(GMMU_FAULT_PACKET)); + + // + // Metadata is packed at the end of the buffer. + // Calculate the page index and offset at which RM needs to fill the metadata + // and copy it over. + // + metadataStartIndex = pClientShadowFaultBuf->metadataStartIndex; + metadataPerPage = RM_PAGE_SIZE / sizeof(GMMU_FAULT_PACKET_METADATA); + metadataPageIndex = shadowBufPutIndex / metadataPerPage; + metadataPageOffset = shadowBufPutIndex % faultPacketsPerPage; + + pDstMetadata = KERNEL_POINTER_FROM_NvP64(NvU8 *, + pClientShadowFaultBuf->pBufferPages[metadataStartIndex + metadataPageIndex].pAddress); + pDstMetadata += (metadataPageOffset * sizeof(GMMU_FAULT_PACKET_METADATA)); + + // Sanity check client reset the Valid bit. + if (pDstMetadata[GMMU_FAULT_PACKET_METADATA_VALID_IDX] != 0) + { + NV_PRINTF(LEVEL_ERROR, "Plaintext valid bit not reset by client.\n"); + return NV_ERR_INVALID_STATE; + } + + pCslCtx = kgmmuGetShadowFaultBufferCslContext(pGpu, pKernelGmmu, type); + if (pCslCtx == NULL) + { + NV_PRINTF(LEVEL_ERROR, "CSL context for type 0x%x unexpectedtly NULL\n", type); + return NV_ERR_INVALID_STATE; + } + + status = ccslEncrypt(pCslCtx, + sizeof(GMMU_FAULT_PACKET), + (NvU8*) &faultPacket, + &validBit, + GMMU_FAULT_PACKET_METADATA_VALID_SIZE, + pDst, + &pDstMetadata[GMMU_FAULT_PACKET_METADATA_AUTHTAG_IDX]); + if (status != NV_OK) + { + if (status == NV_ERR_INSUFFICIENT_RESOURCES) + { + // IV overflow is considered fatal. + NV_PRINTF(LEVEL_ERROR, "Fatal error detected in fault buffer packet encryption: IV overflow!\n"); + confComputeSetErrorState(pGpu, GPU_GET_CONF_COMPUTE(pGpu)); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Error detected in fault buffer packet encryption: 0x%x\n", status); + } + return status; + } + + // + // Ensure that the encrypted packet and authTag have reached point of coherence + // before writing the plaintext valid bit. + // + portAtomicMemoryFenceStore(); + + // Write the valid bit and increment the number of faults copied. + portMemCopy((void*)&pDstMetadata[GMMU_FAULT_PACKET_METADATA_VALID_IDX], + GMMU_FAULT_PACKET_METADATA_VALID_SIZE, + &validBit, + GMMU_FAULT_PACKET_METADATA_VALID_SIZE); + + *pFaultsCopied = 1; + + return NV_OK; +} + +/* + * @brief Checks if the client shadow buffer has space + * + * @param[in] pClientShadowFaultBuf Pointer to the shadow buffer + * @param[in] shadowBufPutIndex Put index inside shadow buffer + * @param[in] maxBufferEntries Maximum possible entries in the HW buffer + * + * @returns NV_TRUE/NV_FALSE + */ +NvBool +kgmmuIsReplayableShadowFaultBufferFull_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuf, + NvU32 shadowBufPutIndex, + NvU32 maxBufferEntries +) +{ + FAULT_BUFFER_SHARED_MEMORY *pFaultBufSharedMem; + + pFaultBufSharedMem = + KERNEL_POINTER_FROM_NvP64(FAULT_BUFFER_SHARED_MEMORY *, + pClientShadowFaultBuf->pFaultBufferSharedMemoryAddress); + + return (pFaultBufSharedMem->swGetIndex == + ((shadowBufPutIndex + 1) % maxBufferEntries)) ? NV_TRUE : NV_FALSE; +} + +/*! + * @brief Get the engine ID associated with the min CE + * + * @param[in] pKenrelGmmu KernelGmmu object + * + * return engine ID of the min CE + */ +NvU32 +kgmmuGetMinCeEngineId_GH100 +( + KernelGmmu *pKernelGmmu +) +{ + return NV_PFAULT_MMU_ENG_ID_CE0; +} + +/*! + * @brief Get the engine ID associated with the max CE + * + * @param[in] pGpu OBJGPU object + * @param[in] pKenrelGmmu KernelGmmu object + * + * return engine ID of the max CE + */ +NvU32 +kgmmuGetMaxCeEngineId_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + return NV_PFAULT_MMU_ENG_ID_CE9; +} + +/** + * @brief Sign extend a fault address to a supported width as per UVM requirements + */ +void +kgmmuSignExtendFaultAddress_GH100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU64 *pMmuFaultAddress +) +{ + NvU32 cpuAddrShift = osGetCpuVaAddrShift(); + NvU32 gpuVaAddrShift = portUtilCountTrailingZeros64(pKernelGmmu->maxVASize); + + // Sign extend VA to ensure it's in canonical form if required + if (gpuVaAddrShift >= cpuAddrShift) + { + switch (pGpu->busInfo.oorArch) + { + case OOR_ARCH_X86_64: + case OOR_ARCH_ARM: + case OOR_ARCH_AARCH64: + *pMmuFaultAddress = (NvU64)(((NvS64)*pMmuFaultAddress << (64 - 57)) >> + (64 - 57)); + break; + case OOR_ARCH_PPC64LE: + break; + case OOR_ARCH_NONE: + NV_ASSERT_FAILED("Invalid oor address mode type."); + break; + } + } + else + { + NV_PRINTF(LEVEL_ERROR, "UVM has not defined what to do here, doing nothing\n"); + NV_ASSERT(0); + } +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c index b53805218f..9bf53b3755 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/maxwell/kern_gmmu_gm107.c @@ -80,6 +80,7 @@ kgmmuInvalidateTlb_GM107 TLB_INVALIDATE_PARAMS params; NvU32 flushCount = 0; NvBool bDoVgpuRpc = NV_FALSE; + OBJVGPU *pVgpu = NULL; // // Bail out early if @@ -107,6 +108,18 @@ kgmmuInvalidateTlb_GM107 return; } + pVgpu = GPU_GET_VGPU(pGpu); + if (pVgpu && pVgpu->bGspBuffersInitialized) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + if (pVSI && + FLD_TEST_DRF(A080, _CTRL_CMD_VGPU_GET_CONFIG, + _PARAMS_VGPU_DEV_CAPS_VF_INVALIDATE_TLB_TRAP_ENABLED, + _TRUE, pVSI->vgpuConfig.vgpuDeviceCapsBits)) + bDoVgpuRpc = NV_TRUE; + } + if (!bDoVgpuRpc) { // @@ -185,6 +198,11 @@ kgmmuInvalidateTlb_GM107 if (bDoVgpuRpc) { + NV_RM_RPC_INVALIDATE_TLB(pGpu, status, params.pdbAddress, params.regVal); + if (status != NV_OK) + { + return; + } } else { diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c b/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c index e50bc0bb81..8a9fe9e4ad 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/pascal/kern_gmmu_gp100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -28,6 +28,7 @@ #include "gpu/mem_mgr/fermi_dma.h" +#include "published/pascal/gp100/dev_fb.h" #include "published/pascal/gp100/dev_ram.h" #include "published/pascal/gp100/dev_fault.h" @@ -231,3 +232,90 @@ kgmmuGetFaultTypeString_GP100(KernelGmmu *pGmmu, NvU32 faultType) return "UNRECOGNIZED_FAULT"; } } + +NV_STATUS +kgmmuFaultCancelIssueInvalidate_GP100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + GMMU_FAULT_CANCEL_INFO *pCancelInfo, + TLB_INVALIDATE_PARAMS *pParams, + NvBool bGlobal +) +{ + NvU32 data32 = 0; + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _ALL_VA, + NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _ALL_PDB, + NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _HUBTLB_ONLY, + NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _SYS_MEMBAR, + NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _ACK, + NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _CACHE_LEVEL, + NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _TRIGGER, + NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE, data32); + + if (bGlobal) + { + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _REPLAY, + NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL, data32); + } + else + { + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _REPLAY, + NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _CANCEL_CLIENT_ID, + pCancelInfo->clientId, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _CANCEL_GPC_ID, + pCancelInfo->gpcId, data32); + + data32 = FLD_SET_DRF_NUM(_PFB, _PRI_MMU_INVALIDATE, _CANCEL_CLIENT_TYPE, + NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC, data32); + } + + pParams->regVal = data32; + + NV_ASSERT_OK_OR_RETURN(kgmmuCheckPendingInvalidates_HAL(pGpu, pKernelGmmu, &pParams->timeout, pParams->gfid)); + + NV_ASSERT_OK_OR_RETURN(kgmmuCommitTlbInvalidate_HAL(pGpu, pKernelGmmu, pParams)); + + return NV_OK; +} + +/*! + * On Pascal+, the big page size is 64KB. The function checks and captures + * incorrect registry overriding. + * + * @param[in] pGpu + * @param[in] pGmmu + * + */ +NV_STATUS +kgmmuCheckAndDecideBigPageSize_GP100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NvU64 bigPageSizeOverride = kgmmuGetBigPageSizeOverride(pKernelGmmu); + + if (bigPageSizeOverride) + { + // Pascal+ does not support 128kB page size + NV_ASSERT_OR_RETURN(bigPageSizeOverride == RM_PAGE_SIZE_64K, NV_ERR_NOT_SUPPORTED); + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c index baa40ff382..cd39f4c41e 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c @@ -26,12 +26,15 @@ * @brief TURING specific HAL MMU routines reside in this file */ +#include "nvtypes.h" #define NVOC_KERN_GMMU_H_PRIVATE_ACCESS_ALLOWED #include "gpu/mmu/kern_gmmu.h" #include "gpu/gpu.h" #include "kernel/gpu/intr/intr.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "published/turing/tu102/dev_fault.h" #include "published/turing/tu102/dev_fb.h" #include "published/turing/tu102/dev_vm.h" @@ -60,6 +63,8 @@ kgmmuCheckPendingInvalidates_TU102 NvU32 regVal; { + NV_ASSERT(IS_GFID_PF(gfid)); + regVal = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE); } @@ -104,6 +109,8 @@ kgmmuCommitTlbInvalidate_TU102 } { + NV_ASSERT(IS_GFID_PF(pParams->gfid)); + if (IS_VIRTUAL(pGpu)) { // Prevent VF from updating INVALIDATE_ALL_PDB, bug 3356599 @@ -136,6 +143,8 @@ kgmmuSetPdbToInvalidate_TU102 ) { { + NV_ASSERT(IS_GFID_PF(pParams->gfid)); + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB, DRF_NUM(_VIRTUAL_FUNCTION_PRIV, _MMU_INVALIDATE_PDB, _ADDR, NvU64_LO32(pParams->pdbAddress >> @@ -321,6 +330,8 @@ kgmmuReadMmuFaultStatus_TU102 ) { { + NV_ASSERT(IS_GFID_PF(gfid)); + return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS); } } @@ -346,6 +357,8 @@ kgmmuReadMmuFaultBufferSize_TU102 ) { { + NV_ASSERT(IS_GFID_PF(gfid)); + return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE(index)); } } @@ -369,6 +382,52 @@ kgmmuReadFaultBufferGetPtr_TU102 return NV_OK; } +NV_STATUS +kgmmuWriteFaultBufferGetPtr_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvU32 getValue, + THREAD_STATE_NODE *pThreadState +) +{ + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + + if (index == REPLAYABLE_FAULT_BUFFER) + { + // + // If HW has detected an overflow condition (PUT == GET - 1 and a fault has + // arrived, which is dropped due to no more space in the fault buffer), it will + // not deliver any more faults into the buffer until the overflow condition has + // been cleared. The overflow condition is cleared by updating the GET index to + // indicate space in the buffer and writing 1 to the OVERFLOW bit in GET. + // Unfortunately, this can not be done in the same write because it can collide + // with an arriving fault on the same cycle, resulting in the overflow condition + // being instantly reasserted. + // However, if the index is updated first and then the OVERFLOW bit is cleared + // such a collision will not cause a reassertion of the overflow condition. + // + GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET(index), getValue, pThreadState); + getValue = FLD_SET_DRF(_VIRTUAL_FUNCTION_PRIV, _MMU_FAULT_BUFFER_GET, _OVERFLOW, _CLEAR, getValue); + getValue = FLD_SET_DRF(_VIRTUAL_FUNCTION_PRIV, _MMU_FAULT_BUFFER_GET, _GETPTR_CORRUPTED, _CLEAR, getValue); + } + else + { + // + // Mask off the _OVERFLOW and _GETPTR_CORRUPTED bits. Writing 0 should + // have no effect, but they're write 1 to clear so make sure we're not + // trying to clear an overflow or the corrupted bit. + // + getValue = FLD_SET_DRF(_VIRTUAL_FUNCTION_PRIV, _MMU_FAULT_BUFFER_GET, _OVERFLOW, _NO, getValue); + getValue = FLD_SET_DRF(_VIRTUAL_FUNCTION_PRIV, _MMU_FAULT_BUFFER_GET, _GETPTR_CORRUPTED, _NO, getValue); + } + + GPU_VREG_WR32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET(index), getValue, pThreadState); + + return NV_OK; +} + NV_STATUS kgmmuReadFaultBufferPutPtr_TU102 ( @@ -447,3 +506,221 @@ kgmmuClearReplayableFaultIntr_TU102 Intr *pIntr = GPU_GET_INTR(pGpu); intrClearLeafVector_HAL(pGpu, pIntr, NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE, pThreadState); } + +/** + * @brief Print information about a MMU fault + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] mmuFaultEngineId Engine ID of the faulted engine + * @param[in] pMmuExceptionData FIFO exception packet used + * for printing fault info + * @returns + */ +void +kgmmuPrintFaultInfo_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 mmuFaultEngineId, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData +) +{ + if (kmemsysCbcIsSafe_HAL(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)) == NV_FALSE) + { + NV_PRINTF(LEVEL_ERROR, + "MMU Fault: CBC Backingstore unsafe, this can be reported as " + "UNSUPPORTED_KIND error\n"); + } + + void kgmmuPrintFaultInfo_GV100(OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NvU32, FIFO_MMU_EXCEPTION_DATA*); + kgmmuPrintFaultInfo_GV100(pGpu, pKernelGmmu, mmuFaultEngineId, pMmuExceptionData); +} + +/*! + * @brief Check if the given engineID is BAR1 + * + * @param[in] pKernelGmmu KernelGmmu object + * @param[in] engineID Engine ID + * + * @return True if BAR1 + */ +NvBool +kgmmuIsFaultEngineBar1_TU102 +( + KernelGmmu *pKernelGmmu, + NvU32 engineID +) +{ + return (engineID == NV_PFAULT_MMU_ENG_ID_BAR1); +} + +/*! + * @brief Check if the given engineID is BAR2 + * + * @param[in] pKernelGmmu KernelGmmu object + * @param[in] engineID Engine ID + * + * @return True if BAR2 + */ + +NvBool +kgmmuIsFaultEngineBar2_TU102 +( + KernelGmmu *pKernelGmmu, + NvU32 engineID +) +{ + return (engineID == NV_PFAULT_MMU_ENG_ID_BAR2); +} + +/*! + * @brief Returns the HW default size of MMU fault buffers (replayable + * or non replayable buffers). + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] index Fault buffer index + * + * @returns size of MMU fault buffers + */ +NvU32 +kgmmuSetAndGetDefaultFaultBufferSize_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE index, + NvU32 gfid +) +{ + NvU32 faultBufferSize; + { + { + NV_ASSERT(IS_GFID_PF(gfid)); + + GPU_VREG_FLD_IDX_WR_DRF_DEF(pGpu, _VIRTUAL_FUNCTION_PRIV, _MMU_FAULT_BUFFER_SIZE, index, _SET_DEFAULT, _YES); + faultBufferSize = GPU_VREG_IDX_RD_DRF(pGpu, _VIRTUAL_FUNCTION_PRIV, _MMU_FAULT_BUFFER_SIZE, index, _VAL) * NVC369_BUF_SIZE; + } + } + + return faultBufferSize; +} + +void +kgmmuWriteMmuFaultBufferSize_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvU32 value, + NvU32 gfid +) +{ + { + NV_ASSERT(IS_GFID_PF(gfid)); + + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE(index), value); + } + + // Align the HW/SW _GET_PTR if _FAULT_BUFFER_SIZE_ENABLE is _FALSE which will be 0 + if (FLD_TEST_DRF(_PFB_PRI, _MMU_FAULT_BUFFER_SIZE, _ENABLE, _FALSE, value)) + { + pKernelGmmu->mmuFaultBuffer[gfid].hwFaultBuffers[index].cachedGetIndex = 0; + } +} + +void +kgmmuWriteMmuFaultBufferHiLo_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvU32 loValue, + NvU32 hiValue, + NvU32 gfid +) +{ + { + NV_ASSERT(IS_GFID_PF(gfid)); + + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI(index), hiValue); + GPU_VREG_WR32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(index), loValue); + } +} + +void +kgmmuReadMmuFaultInstHiLo_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 *pHiVal, + NvU32 *pLoVal +) +{ + NV_ASSERT(pHiVal != NULL); + NV_ASSERT(pLoVal != NULL); + *pLoVal = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO); + *pHiVal = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI); +} + +void +kgmmuReadMmuFaultAddrHiLo_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 *pHiVal, + NvU32 *pLoVal +) +{ + NV_ASSERT(pHiVal != NULL); + NV_ASSERT(pLoVal != NULL); + *pLoVal = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO); + *pHiVal = GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI); +} + +NvU32 +kgmmuReadMmuFaultInfo_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + return GPU_VREG_RD32(pGpu, NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO); +} + +NvU32 +kgmmuGetEccCounts_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NvU32 mmuCount = 0; + NvU32 regVal; + + // L2TLB + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _L2TLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // HUBTLB + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _HUBTLB_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + // FILLUNIT + regVal = GPU_REG_RD32(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT); + mmuCount += DRF_VAL(_PFB_PRI_MMU, _FILLUNIT_ECC, _UNCORRECTED_ERR_COUNT_UNIQUE, regVal); + + return mmuCount; +} + +void +kgmmuClearEccCounts_TU102 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + GPU_REG_WR32(pGpu, NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT, 0); + GPU_REG_WR32(pGpu, NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT, 0); + GPU_REG_WR32(pGpu, NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT, 0); +} diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c index fbe7c6ab88..6b7a050094 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,12 +25,29 @@ #include "gpu/mmu/kern_gmmu.h" #include "gpu/gpu.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/intr/intr.h" +#include "gpu/device/device.h" +#include "gpu/subdevice/subdevice.h" +#include "gpu/uvm/uvm.h" +#include "vgpu/vgpu_events.h" +#include "vgpu/rpc.h" #include "kernel/gpu/rc/kernel_rc.h" +#include "nverror.h" #include "published/volta/gv100/dev_fb.h" #include "published/volta/gv100/dev_ram.h" #include "published/volta/gv100/dev_fault.h" +// Static function Definition +static NV_STATUS _kgmmuCreateExceptionDataFromPriv_GV100(OBJGPU *pGpu, KernelGmmu *pKernelGmmu, + MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData); +static NvU32 _kgmmuResetFaultBufferError_GV100(NvU32 faultBufType); +static NV_STATUS _kgmmuServiceBar2Faults_GV100(OBJGPU *pGpu, KernelGmmu *pKernelGmmu, NvU32 faultStatus, NvU32 mmuFaultClientId); +static NV_STATUS _kgmmuHandleReplayablePrivFault_GV100(OBJGPU *pGpu, KernelGmmu *pKernelGmmu, + MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry); + /** * @brief Initialize the supported GMMU HW format structures. * @details GV100+ supports ATS NV4K 64K PTE encoding @@ -531,3 +548,2066 @@ kgmmuEnableNvlinkComputePeerAddressing_GV100(KernelGmmu *pKernelGmmu) return NV_OK; } + +/** + * @brief Print information about a MMU fault + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] mmuFaultEngineId Engine ID of the faulted engine + * @param[in] pMmuExceptionData FIFO exception packet used + * for printing fault info + * @returns + */ +void +kgmmuPrintFaultInfo_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 mmuFaultEngineId, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData +) +{ + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + + NV_PRINTF(LEVEL_ERROR, "MMU Fault: inst:0x%x dev:0x%x subdev:0x%x\n", + gpuGetInstance(pGpu), gpuGetDeviceInstance(pGpu), + pGpu->subdeviceInstance); + + NV_PRINTF(LEVEL_ERROR, + "MMU Fault: ENGINE 0x%x (%s %s) faulted @ 0x%x_%08x. Fault is of type 0x%x (%s). Access type is 0x%x (%s)", + mmuFaultEngineId, + kfifoPrintInternalEngine_HAL(pGpu, pKernelFifo, mmuFaultEngineId), + kfifoGetClientIdString_HAL(pGpu, pKernelFifo, pMmuExceptionData), + pMmuExceptionData->addrHi, + pMmuExceptionData->addrLo, + pMmuExceptionData->faultType, + kgmmuGetFaultTypeString_HAL(GPU_GET_KERNEL_GMMU(pGpu), + pMmuExceptionData->faultType), + pMmuExceptionData->accessType, + kfifoGetFaultAccessTypeString_HAL(pGpu, pKernelFifo, + pMmuExceptionData->accessType)); + + MODS_ARCH_ERROR_PRINTF("MMU Fault : ENGINE_%s %s %s %s", + kfifoPrintInternalEngine_HAL(pGpu, pKernelFifo, mmuFaultEngineId), + kgmmuGetFaultTypeString_HAL(GPU_GET_KERNEL_GMMU(pGpu), + pMmuExceptionData->faultType), + kfifoGetClientIdString_HAL(pGpu, pKernelFifo, pMmuExceptionData), + kfifoGetFaultAccessTypeString_HAL(pGpu, pKernelFifo, + pMmuExceptionData->accessType)); + + { + NvU32 engTag; + NV_STATUS status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_MMU_FAULT_ID, + mmuFaultEngineId, ENGINE_INFO_TYPE_ENG_DESC, &engTag); + + if ((status == NV_OK) && (IS_GR(engTag))) + { + NvU32 baseFaultId; + + if (pMmuExceptionData->bGpc) + { + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_ERROR, " on GPC %d", pMmuExceptionData->gpcId); + } + + status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_ENG_DESC, + engTag, ENGINE_INFO_TYPE_MMU_FAULT_ID, &baseFaultId); + if (status == NV_OK) + { + NvU32 subctxId = (mmuFaultEngineId - baseFaultId); + + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_ERROR, " on VEID %d", subctxId); + + } + else + { + DBG_BREAKPOINT(); + } + } + } + + NV_PRINTF_EX(NV_PRINTF_MODULE, LEVEL_ERROR, "\n"); + MODS_ARCH_ERROR_PRINTF("\n"); +} + +static NvBool +_kgmmuFaultBufferHasMapping(struct HW_FAULT_BUFFER *pFaultBuffer) +{ + return (pFaultBuffer->kernelVaddr || pFaultBuffer->pBufferPages) ? NV_TRUE : NV_FALSE; +} + +static void +_kgmmuFaultEntryRmServiceable_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + KernelFifo *pKernelFifo, + struct HW_FAULT_BUFFER *pFaultBuffer, + NvU32 entryIndex, + NvU32 hwBufferPut, + NvBool bClientBufEnabled, + NvBool *bRmServiceable, + NvBool *bFaultValid, + FAULT_BUFFER_TYPE type +) +{ + NvU32 faultEntry; + NvBool bUvmHandledNonFatal, bEngineCE, bPbdmaFault; + NvU32 engineId; + NvU32 mwValid, mwUvmHandledNonFatal, mwEngineId; + NvBool bUvmHandledReplayable; + + *bRmServiceable = NV_FALSE; + + // Get MW which contains Valid, replayable and Client Type + mwValid = DRF_WORD_MW(NVC369_BUF_ENTRY_VALID); + mwUvmHandledNonFatal = DRF_WORD_MW(NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN); + mwEngineId = DRF_WORD_MW(NVC369_BUF_ENTRY_ENGINE_ID); + + // + // Currently they all are in same DWORD, so we will read only one DWORD + // Add assert for future HW changes + // + NV_ASSERT(mwValid == mwUvmHandledNonFatal); + + if (type == REPLAYABLE_FAULT_BUFFER) + { + RMTIMEOUT timeout; + NV_STATUS status; + + // + // For the replayable buffer we read HW put. + // If the GET value equals PUT, we know there are no more faults to process. + // + if (entryIndex == hwBufferPut) + { + *bFaultValid = NV_FALSE; + return; + } + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + do + { + faultEntry = MEM_RD32(((NvU32 *)kgmmuFaultBufferGetFault_HAL(pGpu, pKernelGmmu, pFaultBuffer, entryIndex) + mwValid)); + *bFaultValid = !!(NVBIT32(DRF_EXTENT_MW(NVC369_BUF_ENTRY_VALID)) & faultEntry); + + status = gpuCheckTimeout(pGpu, &timeout); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Timed out while waiting for valid bit.\n"); + gpuMarkDeviceForReset(pGpu); + break; + } + } while (*bFaultValid != NV_TRUE); + } + else + { + faultEntry = MEM_RD32(((NvU32 *)kgmmuFaultBufferGetFault_HAL(pGpu, pKernelGmmu, pFaultBuffer, entryIndex) + mwValid)); + *bFaultValid = !!(NVBIT32(DRF_EXTENT_MW(NVC369_BUF_ENTRY_VALID)) & faultEntry); + } + + bUvmHandledNonFatal = !!(NVBIT32(DRF_EXTENT_MW(NVC369_BUF_ENTRY_REPLAYABLE_FAULT_EN)) & faultEntry); + bUvmHandledReplayable = !!(NVBIT32(DRF_EXTENT_MW(NVC369_BUF_ENTRY_REPLAYABLE_FAULT)) & faultEntry); + + // + // Check engine Id. RM doesn't service CE faults with replayable_en bit set. Such faults are serviced by + // clients. In case client wants to cancel such faults, it would need to make a RM control call for RCing + // the channel. + // + if (*bFaultValid) + { + // + // GPU is now done writing to this fault entry. A read memory barrier + // here ensures that fault entry values are not read before the valid + // bit is set. It is needed on architectures like PowerPC and ARM where + // read instructions can be reordered. + // + portAtomicMemoryFenceLoad(); + + faultEntry = MEM_RD32(((NvU32 *)kgmmuFaultBufferGetFault_HAL(pGpu, pKernelGmmu, pFaultBuffer, entryIndex) + mwEngineId)); + engineId = (faultEntry >> DRF_SHIFT_MW(NVC369_BUF_ENTRY_ENGINE_ID)) + & DRF_MASK_MW(NVC369_BUF_ENTRY_ENGINE_ID); + + bEngineCE = ((engineId >= kgmmuGetMinCeEngineId_HAL(pKernelGmmu)) && (engineId <= kgmmuGetMaxCeEngineId_HAL(pGpu, pKernelGmmu))); + bPbdmaFault = kfifoIsMmuFaultEngineIdPbdma(pGpu, pKernelFifo, engineId); + + *bRmServiceable = (!bClientBufEnabled || !bUvmHandledNonFatal || !(bEngineCE || bPbdmaFault)); + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + *bRmServiceable &= !bUvmHandledReplayable; + } + + } +} + +static inline NV_STATUS +_kgmmuCopyFaultPktInShadowBuf_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + FAULT_BUFFER_TYPE type, + struct GMMU_FAULT_BUFFER *pFaultBuffer, + NvU32 getIndex, + NvU32 entriesToCopy, + NvU32 maxBufferEntries, + NvBool bRmServiceable, + THREAD_STATE_NODE *pThreadState +) +{ + GMMU_SHADOW_FAULT_BUF *pRmShadowFaultBuf = NULL; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuf = NULL; + NvU32 copiedCount = 0; + NvU32 copyIndex = 0; + NvU32 origShadowBufPutIndex = 0; + NvU32 shadowBufPutIndex = 0; + struct HW_FAULT_BUFFER *pHwFaultBuffer; + NV_STATUS status = NV_OK; + + pHwFaultBuffer = &pFaultBuffer->hwFaultBuffers[type]; + + if (entriesToCopy == 0) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (bRmServiceable) + { + pRmShadowFaultBuf = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, pFaultBuffer->pRmShadowFaultBuffer); + } + else + { + pClientShadowFaultBuf = pFaultBuffer->pClientShadowFaultBuffer[type]; + // Fetch the current put index for the appropriate shadow buffer + shadowBufPutIndex = kgmmuReadClientShadowBufPutIndex_HAL(pGpu, pKernelGmmu, + GPU_GFID_PF, type); + origShadowBufPutIndex = shadowBufPutIndex; + } + + if ((bRmServiceable && pRmShadowFaultBuf == NULL) || + (!bRmServiceable && pClientShadowFaultBuf == NULL)) + { + return NV_ERR_INVALID_POINTER; + } + + copyIndex = getIndex; + + while (entriesToCopy > 0) + { + if (bRmServiceable) + { + copiedCount = queuePush(pRmShadowFaultBuf, + kgmmuFaultBufferGetFault_HAL(pGpu, pKernelGmmu, pHwFaultBuffer, copyIndex), 1); + if (copiedCount != 1) + { + return NV_ERR_NO_MEMORY; + } + } + else + { + status = kgmmuCopyFaultPacketToClientShadowBuffer_HAL(pGpu, pKernelGmmu, + pFaultBuffer, + type, + copyIndex, + shadowBufPutIndex, + maxBufferEntries, + pThreadState, + &copiedCount); + if (status != NV_OK) + { + return status; + } + + // If nothing was copied, but the status is NV_OK check if PUT needs to be updated. + if (copiedCount == 0) + { + // + // Assert we only end up here in case of Replayable faults. + // Non-Replayable copies always need to succeed. + // + NV_ASSERT_OR_RETURN(type == REPLAYABLE_FAULT_BUFFER, NV_ERR_INVALID_STATE); + if (shadowBufPutIndex != origShadowBufPutIndex) + { + goto update_client_put; + } + + // Signal the caller that no copies have taken place. + return NV_WARN_NOTHING_TO_DO; + } + + shadowBufPutIndex = (shadowBufPutIndex + 1) % maxBufferEntries; + } + + entriesToCopy--; + copyIndex++; + if (copyIndex == maxBufferEntries) + { + copyIndex = 0; + } + } + +update_client_put: + // Update the put index for CPU driver + if (!bRmServiceable) + { + // Make sure the packet reaches memory before writing the PUT. + portAtomicMemoryFenceStore(); + kgmmuWriteClientShadowBufPutIndex_HAL(pGpu, pKernelGmmu, GPU_GFID_PF, + type, shadowBufPutIndex); + } + + return status; +} + +/*! + * @brief Copy fault packets from RM owned HW fault buffer to Shadow faultBuffers + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] faultBufferType Fault buffer Type [Replayable/Non-Replyabale] + * @param[in] pShadowFaultBuf Shadow fault buffer pointer + * @param[out] entriesCopied Number of fault packets copied into shadow buffer + * @param[in] type Replayable or non-replayable fault buffer + * + * @returns + */ +NV_STATUS +kgmmuCopyMmuFaults_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + THREAD_STATE_NODE *pThreadState, + NvU32 *entriesCopied, + FAULT_BUFFER_TYPE type +) +{ + NV_STATUS rmStatus = NV_OK; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + Intr *pIntr = GPU_GET_INTR(pGpu); + GMMU_SHADOW_FAULT_BUF *pRmShadowFaultBuf = NULL; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuf = NULL; + NvU32 nextGetIndex = 0, curGetIndex = 0; + NvU32 totalCount = 0, curCount = 0, rmPktCount = 0; + NvU32 maxBufferEntries = 0; + NvBool bRmServiceable = NV_FALSE, bPrevRmServiceable = NV_FALSE; + NvBool bFaultValid = NV_FALSE; + struct HW_FAULT_BUFFER *pHwFaultBuffer; + struct GMMU_FAULT_BUFFER *pFaultBuffer; + NvU32 hwBufferPut = 0; + + ct_assert(NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER == NON_REPLAYABLE_FAULT_BUFFER); + ct_assert(NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER == REPLAYABLE_FAULT_BUFFER); + + NV_ASSERT_OR_RETURN(type == REPLAYABLE_FAULT_BUFFER || + type == NON_REPLAYABLE_FAULT_BUFFER, + NV_ERR_INVALID_ARGUMENT); + + *entriesCopied = 0; + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF]; + pHwFaultBuffer = &pFaultBuffer->hwFaultBuffers[type]; + + // + // Sanity checks to see if SW is ready to handle interrupts. If interrupts are + // not enabled in SW return fine as we don't want to error out top half. + // + if ((pIntr == NULL) || (intrGetIntrEn(pIntr) == INTERRUPT_TYPE_DISABLED) || + pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED) || + !pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pShadowFaultBufLock) + { + return NV_OK; + } + + if ((!gpuIsCCFeatureEnabled(pGpu) || !gpuIsGspOwnedFaultBuffersEnabled(pGpu)) && + (type == REPLAYABLE_FAULT_BUFFER)) + { + return NV_OK; + } + + // If there is no replayable buffer registered, then there is no work to be done. + if (type == REPLAYABLE_FAULT_BUFFER && + !pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE)) + { + // RM still needs to clear the interrupt to avoid an interrupt storm. + kgmmuClearReplayableFaultIntr_HAL(pGpu, pKernelGmmu, pThreadState); + return NV_OK; + } + + portSyncSpinlockAcquire(pFaultBuffer->pShadowFaultBufLock); + + pRmShadowFaultBuf = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, pFaultBuffer->pRmShadowFaultBuffer); + pClientShadowFaultBuf = KERNEL_POINTER_FROM_NvP64(GMMU_CLIENT_SHADOW_FAULT_BUFFER *, + pFaultBuffer->pClientShadowFaultBuffer[type]); + + // Max entries exposed in register takes care of 1 entry used for Full detection + NV_ASSERT(pHwFaultBuffer->faultBufferSize); + maxBufferEntries = (pHwFaultBuffer->faultBufferSize / NVC369_BUF_SIZE); + + if (!_kgmmuFaultBufferHasMapping(pHwFaultBuffer)) + { + NV_PRINTF(LEVEL_ERROR, + "GPU %d HW's fault buffer doesn't have kernel mappings\n", + pGpu->gpuInstance); + rmStatus = NV_ERR_INVALID_STATE; + goto done; + } + + if (pRmShadowFaultBuf == NULL) + { + NV_PRINTF(LEVEL_ERROR, "GPU %d RM's shadow buffer should be setup\n", + pGpu->gpuInstance); + rmStatus = NV_ERR_INVALID_STATE; + goto done; + } + + // + // For SRIOV vGPU, GET and PUT reg gets reset to zero during migration. + // This results in wrong fault buffer entry referenced by RM after migration + // for next fault entry read. So for SRIOV vgpu setup, instead of using RM cached value + // always read NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET(index) reg in order to + // identify next fault entry to read. + // + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + kgmmuReadFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, type, + &pHwFaultBuffer->cachedGetIndex, pThreadState); + } + + nextGetIndex = curGetIndex = pHwFaultBuffer->cachedGetIndex; + + if (type == NON_REPLAYABLE_FAULT_BUFFER) + { + // Clear non replayable fault pulse interrupt + kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, pThreadState); + } + else + { + // Clear replayable fault pulse interrupt + kgmmuClearReplayableFaultIntr_HAL(pGpu, pKernelGmmu, pThreadState); + kgmmuReadFaultBufferPutPtr_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER, + &hwBufferPut, pThreadState); + } + + // + // Check how many entries are valid and serviceable by one driver in HW fault buffer. + // We copy everything in one go to optimize copy performance + // + while (totalCount < maxBufferEntries) + { + _kgmmuFaultEntryRmServiceable_GV100(pGpu, pKernelGmmu, pKernelFifo, + pHwFaultBuffer, nextGetIndex, hwBufferPut, (pClientShadowFaultBuf != NULL), + &bRmServiceable, &bFaultValid, type); + + if (!bFaultValid) + break; + + // Non replayable fault copy path. + if (type == NON_REPLAYABLE_FAULT_BUFFER) + { + // Check if servicing entity has changed + if ((bPrevRmServiceable != bRmServiceable) && (curCount > 0)) + { + rmStatus = _kgmmuCopyFaultPktInShadowBuf_GV100(pGpu, pKernelGmmu, + type, + pFaultBuffer, + curGetIndex, + curCount, + maxBufferEntries, + bPrevRmServiceable, + pThreadState); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to copy faults into GPU %d's %s shadow buffer\n", + pGpu->gpuInstance, + (bPrevRmServiceable ? "RM" : "Client")); + gpuMarkDeviceForReset(pGpu); + goto done; + } + + curGetIndex = (curGetIndex + curCount) % maxBufferEntries; + curCount = 0; + } + } + + // + // A Replayable fault is never RM servicable. + // As a result, we will never perform the fault copy within this loop, + // but only count the number of entries. + // + // The number of entries is used outside of the loop to + // determine the number of packets to copy. + // + if (type == REPLAYABLE_FAULT_BUFFER) + { + NV_ASSERT_OR_RETURN(!bRmServiceable, NV_ERR_INVALID_STATE); + } + + if (curCount == 0) + { + bPrevRmServiceable = bRmServiceable; + } + + if (bRmServiceable) + { + rmPktCount++; + } + + curCount++; + totalCount++; + nextGetIndex++; + if (nextGetIndex == maxBufferEntries) + { + nextGetIndex = 0; + if (type == NON_REPLAYABLE_FAULT_BUFFER) + { + pFaultBuffer->faultBufferGenerationCounter++; + } + } + } + + // Nothing to copy + if (totalCount == 0) + { + // + // Writing to GET will cause the GET != PUT condition to get reevaluated + // and the interrupt signal will be sent again if they are not equal. + // This is necessary because the non replayable fault interrupt was cleared + // earlier. Once the packet is ready and it is copied, GET == PUT and the + // interrupt will not be retriggered. + // + + NvU32 val; + val = pHwFaultBuffer->cachedGetIndex; + + kgmmuWriteFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, type, + val, pThreadState); + goto done; + } + + // Copy all remaining entries + if (curCount > 0) + { + rmStatus = _kgmmuCopyFaultPktInShadowBuf_GV100(pGpu, pKernelGmmu, + type, + pFaultBuffer, + curGetIndex, + curCount, + maxBufferEntries, + bPrevRmServiceable, + pThreadState); + // + // NV_WARN_NOTHING_TO_DO signals that no faults have been copied + // in the replayable fault handling case. There is no need to notify the client. + // + if (rmStatus == NV_WARN_NOTHING_TO_DO) + { + rmStatus = NV_OK; + goto done; + } + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to copy faults into GPU %d's %s shadow buffer\n", + pGpu->gpuInstance, + (bPrevRmServiceable ? "RM" : "Client")); + gpuMarkDeviceForReset(pGpu); + goto done; + } + } + + // + // Reset the valid bit in all these fault packets. It's easy to zero down the overall packets rather than writing + // INVALID to one packet at a time + // + curGetIndex = pHwFaultBuffer->cachedGetIndex; + curCount = totalCount; + + if ((curGetIndex + curCount) > maxBufferEntries) + { + kgmmuFaultBufferClearPackets_HAL(pGpu, pKernelGmmu, pHwFaultBuffer, curGetIndex, maxBufferEntries - curGetIndex); + curCount = totalCount - (maxBufferEntries - curGetIndex); + curGetIndex = 0; + } + + kgmmuFaultBufferClearPackets_HAL(pGpu, pKernelGmmu, pHwFaultBuffer, curGetIndex, curCount); + + // + // Ensure fatalFaultIntrPending is set only after fault buffer entries have been + // copied into shadow buffer. + // + portAtomicMemoryFenceStore(); + + // + // Set the SW flag needed for interrupt processing. This should be set before we write GET pointer as moving + // GET ptr can disable top level interrupt and we should not have a window where an interrupt pending state is lost + // As we don't mask these interrupts, top level interrupts will be reset as soon as GET == PUT after copy. McService + // in RM's bottom_half relies on top level interrupts for servicing, hence we need a SW flag to state that there is + // an intr pending for servicing. + // + portAtomicSetS32(&pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].fatalFaultIntrPending, 1); + + // + // Ensure all writes to the current entry are completed before updating the + // GET pointer. + // + portAtomicMemoryFenceStore(); + + // Increment the GET pointer to enable HW to write new fault packets + kgmmuWriteFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, type, nextGetIndex, pThreadState); + + *entriesCopied = rmPktCount; + pHwFaultBuffer->cachedGetIndex = nextGetIndex; + +done: + portSyncSpinlockRelease(pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pShadowFaultBufLock); + return rmStatus; +} + +void +kgmmuFaultBufferClearPackets_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + struct HW_FAULT_BUFFER *pFaultBuffer, + NvU32 beginIdx, + NvU32 numFaultPackets +) +{ + if (pFaultBuffer->kernelVaddr) + { + void *bufferAddr = (void *)(NvUPtr)(KERNEL_POINTER_FROM_NvP64(NvU64, pFaultBuffer->kernelVaddr) + + (NvU64)(beginIdx * sizeof(GMMU_FAULT_PACKET))); + portMemSet(bufferAddr, 0, sizeof(GMMU_FAULT_PACKET) * numFaultPackets); + } + else + { + NvU32 pktPerPage = RM_PAGE_SIZE / sizeof(GMMU_FAULT_PACKET); + + NvU32 pageNumber = beginIdx * sizeof(GMMU_FAULT_PACKET) / RM_PAGE_SIZE; + NvU32 fstPktInPage = beginIdx % (RM_PAGE_SIZE / sizeof(GMMU_FAULT_PACKET)); + NvU32 clearInThisPage = NV_MIN(numFaultPackets, pktPerPage - fstPktInPage); + + while (numFaultPackets > 0) + { + NvP64 pAddress = pFaultBuffer->pBufferPages[pageNumber].pAddress; + + void *bufferAddr = (void *)(NvUPtr)(KERNEL_POINTER_FROM_NvP64(NvU64, pAddress) + fstPktInPage * sizeof(GMMU_FAULT_PACKET)); + + portMemSet(bufferAddr, 0, clearInThisPage * sizeof(GMMU_FAULT_PACKET)); + + pageNumber++; + fstPktInPage = 0; + numFaultPackets -= clearInThisPage; + clearInThisPage = NV_MIN(pktPerPage, numFaultPackets); + } + } +} + +GMMU_FAULT_PACKET * +kgmmuFaultBufferGetFault_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + struct HW_FAULT_BUFFER *pFaultBuffer, + NvU32 idx) +{ + if (pFaultBuffer->kernelVaddr) + { + void *pFault = (void *)(NvUPtr)(KERNEL_POINTER_FROM_NvP64(NvU64, pFaultBuffer->kernelVaddr) + + (NvU64)(idx * sizeof(GMMU_FAULT_PACKET))); + return pFault; + } + else + { + NvU32 pageNumber = idx * sizeof(GMMU_FAULT_PACKET) / RM_PAGE_SIZE; + NvP64 pAddress = pFaultBuffer->pBufferPages[pageNumber].pAddress; + NvU32 inPageIdx = idx % (RM_PAGE_SIZE / sizeof(GMMU_FAULT_PACKET)); + void *pFault = (void *)(NvUPtr)(KERNEL_POINTER_FROM_NvP64(NvU64, pAddress) + + inPageIdx * sizeof(GMMU_FAULT_PACKET)); + + return pFault; + } +} + +/* + * @brief Copies a single fault packet from the replayable/non-replayable + * HW fault buffer to the corresponding client shadow buffer + * + * @param[in] pFaultBuffer Pointer to GMMU_FAULT_BUFFER + * @param[in] type Replayable/Non-replayable fault type + * @param[in] getIndex Get pointer of the HW fault buffer + * @param[in] shadowBufPutIndex Put pointer of the shadow buffer + * @param[in] maxBufferEntries Maximum possible entries in the HW buffer + * @param[in] pThreadState Pointer to THREAD_STATE_NODE + * @param[out] pFaultsCopied Number of fault packets copied by the function + * + * @returns NV_STATUS + */ +NvU32 +kgmmuCopyFaultPacketToClientShadowBuffer_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + struct GMMU_FAULT_BUFFER *pFaultBuffer, + FAULT_BUFFER_TYPE type, + NvU32 getIndex, + NvU32 shadowBufPutIndex, + NvU32 maxBufferEntries, + THREAD_STATE_NODE *pThreadState, + NvU32 *pFaultsCopied +) +{ + GMMU_SHADOW_FAULT_BUF *pQueue = NULL; + struct HW_FAULT_BUFFER *pHwFaultBuffer = NULL; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowFaultBuf = NULL; + + pHwFaultBuffer = &pFaultBuffer->hwFaultBuffers[type]; + pClientShadowFaultBuf = pFaultBuffer->pClientShadowFaultBuffer[type]; + + pQueue = (GMMU_SHADOW_FAULT_BUF *) pClientShadowFaultBuf->pQueueAddress; + + *pFaultsCopied = queuePushNonManaged(pQueue, &pClientShadowFaultBuf->queueContext, + kgmmuFaultBufferGetFault_HAL(pGpu, pKernelGmmu, + pHwFaultBuffer, + getIndex), + 1); + if (*pFaultsCopied == 0) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + + return NV_OK; +} + +/*! + * @brief Get the engine ID associated with the min CE + * + * @param[in] pKernelGmmu KernelGmmu object + * + * return engine ID of the min CE + */ +NvU32 +kgmmuGetMinCeEngineId_GV100 +( + KernelGmmu *pKernelGmmu +) +{ + return NV_PFAULT_MMU_ENG_ID_CE0; +} + +/*! + * @brief Get the engine ID associated with the max CE + * + * @param[in] pGpu OBJGPU object + * @param[in] pKernelGmmu KernelGmmu object + * + * return engine ID of the max CE + */ +NvU32 +kgmmuGetMaxCeEngineId_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + return NV_PFAULT_MMU_ENG_ID_CE8; +} + +/*! + * @brief Creates shadow fault buffer for RM fatal fault handling + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * + * @returns + */ +static NV_STATUS +_kgmmuAllocShadowFaultBuffer_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NV_STATUS rmStatus = NV_OK; + GMMU_SHADOW_FAULT_BUF *gmmuShadowFaultBuf = NULL; + NvU32 queueMaxEntries = 0; + struct HW_FAULT_BUFFER *pFaultBuffer; + + // NvPort should be initialized in RM before these calls are made + if (!portIsInitialized()) + { + NV_PRINTF(LEVEL_ERROR, "NvPort needed but not initaiized\n"); + NV_ASSERT(0); + } + + if (pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + NV_PRINTF(LEVEL_ERROR, "Fault-Buffer is disabled. ShadowBuffer cannot be created\n"); + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hwFaultBuffers[NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER]; + NV_ASSERT_OR_RETURN(pFaultBuffer->faultBufferSize != 0, NV_ERR_INVALID_ARGUMENT); + + // Allocate memory for queue dataStructure and initialize queue + gmmuShadowFaultBuf = portMemAllocNonPaged(sizeof(GMMU_SHADOW_FAULT_BUF)); + NV_ASSERT_OR_RETURN(gmmuShadowFaultBuf != NULL, NV_ERR_NO_MEMORY); + + queueMaxEntries = (pFaultBuffer->faultBufferSize / NVC369_BUF_SIZE); + rmStatus = queueInit(gmmuShadowFaultBuf, portMemAllocatorGetGlobalNonPaged(), queueMaxEntries); + if (rmStatus != NV_OK) + goto error; + + // + // SpinLock needed to protect shadow buffer setup as it gets accessed + // from top half and clientShadowBuffer can get setup/destroy later + // + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pShadowFaultBufLock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); + if (!pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pShadowFaultBufLock) + { + rmStatus = NV_ERR_INSUFFICIENT_RESOURCES; + goto error; + } + + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pRmShadowFaultBuffer = NV_PTR_TO_NvP64(gmmuShadowFaultBuf); + return NV_OK; + +error: + portMemFree(gmmuShadowFaultBuf); + return rmStatus; +} + +NV_STATUS +kgmmuFaultBufferInit_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NV_STATUS status; + NvU32 faultBufferSize; + + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + return NV_OK; + + ct_assert(NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER == REPLAYABLE_FAULT_BUFFER); + ct_assert(NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER == NON_REPLAYABLE_FAULT_BUFFER); + + faultBufferSize = kgmmuSetAndGetDefaultFaultBufferSize_HAL(pGpu, pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER, + GPU_GFID_PF); + status = kgmmuFaultBufferAlloc(pGpu, pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER, + faultBufferSize); + if (status != NV_OK) + { + return status; + } + + // Allocate shadow fault buffer for fatal fault handling inside RM + status = _kgmmuAllocShadowFaultBuffer_GV100(pGpu, pKernelGmmu); + if (status != NV_OK) + { + (void) kgmmuFaultBufferFree(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); + return status; + } + + return NV_OK; +} + +NV_STATUS +kgmmuFaultBufferLoad_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvU32 gfid +) +{ + NV_STATUS status; + + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + return NV_OK; + + // Skip the map if this is a GC6 cycle as FB is preserved. + if (!IS_GPU_GC6_STATE_EXITING(pGpu)) + { + status = kgmmuFaultBufferMap(pGpu, pKernelGmmu, index, gfid); + if (status != NV_OK) + { + return status; + } + // Init the PUT pointer PRI before use. Applicable only to Hopper CC + kgmmuWriteClientShadowBufPutIndex_HAL(pGpu, pKernelGmmu, gfid, index, 0); + } + + status = kgmmuEnableFaultBuffer_HAL(pGpu, pKernelGmmu, index, NV_FALSE, gfid); + if (status != NV_OK) + { + (void) kgmmuFaultBufferUnmap(pGpu, pKernelGmmu, index, gfid); + return status; + } + + return NV_OK; +} + +NV_STATUS +kgmmuEnableFaultBuffer_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvBool bIsErrorRecovery, + NvU32 gfid +) +{ + NvU32 faultBufferHi; + NvU32 faultBufferLo; + NvU32 regVal; + struct HW_FAULT_BUFFER *pFaultBuffer; + + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) || + pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + return NV_OK; + } + + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[gfid].hwFaultBuffers[index]; + + faultBufferHi = NvU64_HI32(pFaultBuffer->bar2FaultBufferAddr); + faultBufferLo = NvU64_LO32(pFaultBuffer->bar2FaultBufferAddr); + kgmmuWriteMmuFaultBufferHiLo_HAL(pGpu, pKernelGmmu, index, faultBufferLo, faultBufferHi, gfid); + + kgmmuSetAndGetDefaultFaultBufferSize_HAL(pGpu, pKernelGmmu, index, gfid); + + regVal = kgmmuReadMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, index, gfid); + regVal = FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_BUFFER_SIZE, _ENABLE, _TRUE, regVal); + + if (index == NON_REPLAYABLE_FAULT_BUFFER) + { + // + // Non-Replayable Fault buffer needs overflow interrupt reporting + // as overflow is considered fatal due to fault packet loss. Also + // this interrupt will disable non_replayable interrupt when raised. + // + regVal = FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_BUFFER_SIZE, _OVERFLOW_INTR, _ENABLE, regVal); + } + else + { + // + // Replayable Fault buffer does not need overflow interrupt reporting + // as overflow is not considered fatal. There is no fault packet loss + // due to replays. + // + regVal = FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_BUFFER_SIZE, _OVERFLOW_INTR, _DISABLE, regVal); + } + + kgmmuWriteMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, index, regVal, gfid); + // Don't touch interrupts if called in error recovery path + if (!bIsErrorRecovery) + { + kgmmuEnableMmuFaultInterrupts_HAL(pGpu, pKernelGmmu, index); + kgmmuEnableMmuFaultOverflowIntr_HAL(pGpu, pKernelGmmu, index); + } + return NV_OK; +} + +NV_STATUS +kgmmuDisableFaultBuffer_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvBool bIsErrorRecovery, + NvU32 gfid +) +{ + NV_STATUS rmStatus = NV_OK; + NvU32 faultBufferSize; + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + + if (pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED) || + (IS_VIRTUAL(pGpu) && gpuIsWarBug200577889SriovHeavyEnabled(pGpu))) + { + return NV_OK; + } + + rmStatus = gpuSanityCheckRegisterAccess(pGpu, 0, NULL); + if (rmStatus != NV_OK) + return rmStatus; + + // + // Before disabling fault buffer make sure that no packets are pending in pipe. + // The status register here provides status for all fault buffers(replayable/non-replayable) + // and ideally we should have separate status register for these buffers. This is tracked in + // Bug 1848948 + // + if (!bIsErrorRecovery) + { + RMTIMEOUT timeout; + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + while (FLD_TEST_DRF(_PFB_PRI, _MMU_FAULT_STATUS, _BUSY, _TRUE, + kgmmuReadMmuFaultStatus_HAL(pGpu, pKernelGmmu, gfid))) + { + rmStatus = gpuCheckTimeout(pGpu, &timeout); + if (rmStatus == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "HW couldn't flush %s buffer.\n", + (index == REPLAYABLE_FAULT_BUFFER) ? "REPLAYABLE_FAULT_BUFFER" : "NON_REPLAYABLE_FAULT_BUFFER"); + DBG_BREAKPOINT(); + break; + } + } + } + + faultBufferSize = kgmmuReadMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, index, gfid); + faultBufferSize = FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_BUFFER_SIZE, _ENABLE, _FALSE, + faultBufferSize); + kgmmuWriteMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, index, faultBufferSize, gfid); + + return rmStatus; +} + +NV_STATUS +kgmmuFaultBufferDestroy_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NV_STATUS status; + + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + return NV_OK; + + status = kgmmuClientShadowFaultBufferFree_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); + if (status != NV_OK) + return status; + + // Free RM shadow fault buffer created for fatal fault handling + if (pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pRmShadowFaultBuffer) + { + queueDestroy(KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pRmShadowFaultBuffer)); + portMemFree(NvP64_VALUE(pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pRmShadowFaultBuffer)); + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pRmShadowFaultBuffer = NvP64_NULL; + } + + if (pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pShadowFaultBufLock) + { + portSyncSpinlockDestroy(pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pShadowFaultBufLock); + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pShadowFaultBufLock = NULL; + } + + (void) kgmmuFaultBufferFree(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER); + + return NV_OK; +} + +NV_STATUS +kgmmuFaultBufferUnload_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvU32 gfid +) +{ + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + return NV_OK; + + kgmmuDisableFaultBuffer_HAL(pGpu, pKernelGmmu, index, NV_FALSE, gfid); + + // Skip the unmap if this is a GC6 cycle as FB is preserved. + if (!IS_GPU_GC6_STATE_ENTERING(pGpu)) + kgmmuFaultBufferUnmap(pGpu, pKernelGmmu, index, gfid); + + return NV_OK; +} + +/** + * @brief Sign extend a fault address to a supported width as per UVM requirements + */ +void +kgmmuSignExtendFaultAddress_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU64 *pMmuFaultAddress +) +{ + NvU32 cpuAddrShift = osGetCpuVaAddrShift(); + NvU32 gpuVaAddrShift = portUtilCountTrailingZeros64(pKernelGmmu->maxVASize); + + // Sign extend VA to ensure it's in canonical form if required + if (gpuVaAddrShift >= cpuAddrShift) + { + switch (pGpu->busInfo.oorArch) + { + case OOR_ARCH_X86_64: + case OOR_ARCH_ARM: + case OOR_ARCH_AARCH64: + *pMmuFaultAddress = (NvU64)(((NvS64)*pMmuFaultAddress << (64 - cpuAddrShift)) >> + (64 - cpuAddrShift)); + break; + case OOR_ARCH_PPC64LE: + break; + case OOR_ARCH_NONE: + NV_ASSERT_FAILED("Invalid oor address mode type."); + break; + } + } + else + { + switch (pGpu->busInfo.oorArch) + { + case OOR_ARCH_X86_64: + *pMmuFaultAddress = (NvU64)(((NvS64)*pMmuFaultAddress << (64 - 48)) >> + (64 - 48)); + break; + case OOR_ARCH_ARM: + case OOR_ARCH_AARCH64: + *pMmuFaultAddress = (NvU64)(((NvS64)*pMmuFaultAddress << (64 - 49)) >> + (64 - 49)); + break; + case OOR_ARCH_PPC64LE: + break; + case OOR_ARCH_NONE: + NV_ASSERT_FAILED("Invalid oor address mode type."); + break; + } + } +} + +/*! + * @brief Parses Faultbuffer entry and returns Fault Type + * + * @param[in] fault Fault Value + * @param[out] pMmuFaultType Fault Type + * + * @returns + */ +NV_STATUS +kgmmuGetFaultType_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 fault, + FAULT_TYPE *pMmuFaultType +) +{ + NV_ASSERT_OR_RETURN(pMmuFaultType != NULL, NV_ERR_INVALID_POINTER); + switch (fault) + { + case NV_PFAULT_FAULT_TYPE_PDE: + *pMmuFaultType = fault_invalidPde; + break; + + case NV_PFAULT_FAULT_TYPE_PDE_SIZE: + *pMmuFaultType = fault_invalidPdeSize; + break; + + case NV_PFAULT_FAULT_TYPE_PTE: + *pMmuFaultType = fault_invalidPte; + break; + + case NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION: + *pMmuFaultType = fault_limitViolation; + break; + + case NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK: + *pMmuFaultType = fault_unboundInstBlock; + break; + + case NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION: + *pMmuFaultType = fault_privViolation; + break; + + case NV_PFAULT_FAULT_TYPE_RO_VIOLATION: + *pMmuFaultType = fault_write; + break; + + case NV_PFAULT_FAULT_TYPE_WO_VIOLATION: + *pMmuFaultType = fault_read; + break; + + case NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION: + *pMmuFaultType = fault_pitchMaskViolation; + break; + + case NV_PFAULT_FAULT_TYPE_WORK_CREATION: + *pMmuFaultType = fault_workCreation; + break; + + case NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE: + *pMmuFaultType = fault_unsupportedAperture; + break; + + case NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE: + *pMmuFaultType = fault_compressionFailure; + break; + + case NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND: + *pMmuFaultType = fault_unsupportedKind; + break; + + case NV_PFAULT_FAULT_TYPE_REGION_VIOLATION: + *pMmuFaultType = fault_regionViolation; + break; + + case NV_PFAULT_FAULT_TYPE_POISONED: + *pMmuFaultType = fault_poison; + break; + + case NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION: + *pMmuFaultType = fault_atomic; + break; + + default: + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + +/*! + * @brief Check if the given engineID is PHYSICAL + * + * @param[in] pKernelGmmu KernelGmmu object + * @param[in] engineID Engine ID + * + * @return True if PHYSICAL + */ +NvBool +kgmmuIsFaultEnginePhysical_GV100 +( + KernelGmmu *pKernelGmmu, + NvU32 engineID +) +{ + return (engineID == NV_PFAULT_MMU_ENG_ID_PHYSICAL); +} + +/*! + * @brief Parse fault Buffer Packet + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] pFaultPacket Raw Fault Packet data + * @param[out] pParsedFaultEntry Parsed Fault entry + * + * @returns + */ +NV_STATUS +kgmmuParseFaultPacket_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvP64 pFaultPacket, + NvP64 pParsedFaultEntry +) +{ + NV_STATUS rmStatus = NV_OK; + NvU32 *faultEntry = KERNEL_POINTER_FROM_NvP64(NvU32 *, pFaultPacket); + MMU_FAULT_BUFFER_ENTRY * pParsedEntry = KERNEL_POINTER_FROM_NvP64(MMU_FAULT_BUFFER_ENTRY *, pParsedFaultEntry); + NvU64 addrHi, addrLo; + NvU64 timestampLo, timestampHi; + NvU32 tmp; + + addrLo = DRF_VAL_MW(C369, _BUF_ENTRY, _INST_LO, faultEntry); + addrHi = DRF_VAL_MW(C369, _BUF_ENTRY, _INST_HI, faultEntry); + pParsedEntry->mmuFaultInstBlock.address = addrLo + (addrHi << DRF_SIZE_MW(NVC369_BUF_ENTRY_INST_LO)); + pParsedEntry->mmuFaultInstBlock.address <<= 12; + + tmp = DRF_VAL_MW(C369, _BUF_ENTRY, _INST_APERTURE, faultEntry); + pParsedEntry->mmuFaultInstBlock.aperture = tmp; + pParsedEntry->mmuFaultInstBlock.gfid = GPU_GFID_PF; + + VERIFY_INST_BLOCK_APERTURE(NVC369_BUF_ENTRY_INST_APERTURE_VID_MEM, + NVC369_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT, + NVC369_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT); + + addrLo = DRF_VAL_MW(C369, _BUF_ENTRY, _ADDR_LO, faultEntry); + addrHi = DRF_VAL_MW(C369, _BUF_ENTRY, _ADDR_HI, faultEntry); + pParsedEntry->mmuFaultAddress = (addrLo + (addrHi << DRF_SIZE_MW(NVC369_BUF_ENTRY_ADDR_LO))) << + (DRF_BASE_MW(NVC369_BUF_ENTRY_ADDR_LO)); + + kgmmuSignExtendFaultAddress_HAL(pGpu, pKernelGmmu, &pParsedEntry->mmuFaultAddress); + + timestampLo = DRF_VAL_MW(C369, _BUF_ENTRY, _TIMESTAMP_LO, faultEntry); + timestampHi = DRF_VAL_MW(C369, _BUF_ENTRY, _TIMESTAMP_HI, faultEntry); + pParsedEntry->mmuFaultTimestamp = timestampLo + (timestampHi << DRF_SIZE_MW(NVC369_BUF_ENTRY_TIMESTAMP_LO)); + + tmp = DRF_VAL_MW(C369, _BUF_ENTRY, _FAULT_TYPE, faultEntry); + rmStatus = kgmmuGetFaultType_HAL(pGpu, pKernelGmmu, tmp, &pParsedEntry->mmuFaultType); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, rmStatus); + + pParsedEntry->mmuFaultAccessType = DRF_VAL_MW(C369, _BUF_ENTRY, _ACCESS_TYPE, faultEntry); + + pParsedEntry->mmuFaultEngineId = DRF_VAL_MW(C369, _BUF_ENTRY, _ENGINE_ID, faultEntry); + pParsedEntry->mmuFaultClientId = DRF_VAL_MW(C369, _BUF_ENTRY, _CLIENT, faultEntry); + pParsedEntry->mmuFaultClientType = DRF_VAL_MW(C369, _BUF_ENTRY, _MMU_CLIENT_TYPE, faultEntry); + pParsedEntry->mmuFaultGpcId = DRF_VAL_MW(C369, _BUF_ENTRY, _GPC_ID, faultEntry); + pParsedEntry->bFaultEntryValid = DRF_VAL_MW(C369, _BUF_ENTRY, _VALID, faultEntry); + pParsedEntry->bFaultInProtectedMode = DRF_VAL_MW(C369, _BUF_ENTRY, _PROTECTED_MODE, faultEntry); + pParsedEntry->bFaultTypeReplayable = DRF_VAL_MW(C369, _BUF_ENTRY, _REPLAYABLE_FAULT, faultEntry); + pParsedEntry->bReplayableFaultEn = DRF_VAL_MW(C369, _BUF_ENTRY, _REPLAYABLE_FAULT_EN, faultEntry); + return rmStatus; +} + +/*! + * @brief Handles the nonreplayable fault based on a fault packet + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] pFaultPacket Raw Fault Packet data + * + * @returns + * NV_ERR_INVALID_DATA if fault packet data is not valid. + */ +NV_STATUS +kgmmuHandleNonReplayableFaultPacket_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + GMMU_FAULT_PACKET *pFaultPacket +) +{ + NV_STATUS rmStatus = NV_OK; + MMU_FAULT_BUFFER_ENTRY parsedFaultEntry; + FIFO_MMU_EXCEPTION_DATA MmuExceptionData = {0}; + + // Parse the fault packet. RM fault buffer will have only RM serviceable packets + rmStatus = kgmmuParseFaultPacket_HAL(pGpu, pKernelGmmu, NV_PTR_TO_NvP64(pFaultPacket), + NV_PTR_TO_NvP64(&parsedFaultEntry)); + if (rmStatus != NV_OK) + return NV_ERR_INVALID_DATA; + + // Let's create the exception data just for printing purposes + MmuExceptionData.addrLo = (NvU32)(parsedFaultEntry.mmuFaultAddress & 0xFFFFFFFFUL); + MmuExceptionData.addrHi = (NvU32)(parsedFaultEntry.mmuFaultAddress >> 32); + MmuExceptionData.faultType = parsedFaultEntry.mmuFaultType; + MmuExceptionData.clientId = parsedFaultEntry.mmuFaultClientId; + if (parsedFaultEntry.mmuFaultClientType == NV_PFAULT_MMU_CLIENT_TYPE_GPC) + { + MmuExceptionData.bGpc = NV_TRUE; + MmuExceptionData.gpcId = parsedFaultEntry.mmuFaultGpcId; + } + else + { + MmuExceptionData.bGpc = NV_FALSE; + MmuExceptionData.gpcId = 0; + } + MmuExceptionData.accessType = parsedFaultEntry.mmuFaultAccessType; + MmuExceptionData.faultEngineId = parsedFaultEntry.mmuFaultEngineId; + + kgmmuPrintFaultInfo_HAL(pGpu, pKernelGmmu, parsedFaultEntry.mmuFaultEngineId, &MmuExceptionData); + + rmStatus = kgmmuServiceMmuFault_HAL(pGpu, pKernelGmmu, NV_PTR_TO_NvP64(&parsedFaultEntry), + &MmuExceptionData); + NV_ASSERT(rmStatus == NV_OK); + + // Send event notifier in response to MMU Poison Fault. + if ((parsedFaultEntry.mmuFaultType == fault_poison) && + gpuIsGlobalPoisonFuseEnabled(pGpu)) + { + NV_ERROR_CONT_LOCATION loc = {0}; + + // Error containment location information + loc.locType = NV_ERROR_CONT_LOCATION_TYPE_NONE; + + // Generate Error Containment Xid, send NV2080_NOTIFIER*, mark device for Reset or Drain And Reset + NV_ASSERT_OK_OR_RETURN( + gpuUpdateErrorContainmentState_HAL(pGpu, + NV_ERROR_CONT_ERR_ID_E13_MMU_POISON, // Error type + loc, // Loc + NULL)); // RC Error Code + } + + return rmStatus; +} + +NV_STATUS +kgmmuNotifyNonReplayableFault_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvBool bNotifyClient +) +{ + NV_STATUS rmStatus = NV_OK; + PEVENTNOTIFICATION *ppEventNotification = NULL; + GMMU_CLIENT_SHADOW_FAULT_BUFFER *pClientShadowBuffer = NULL; + + // + // We call clients unconditionally as clients should be walking thru their shadow buffer and filter all + // redundant faults if any + // + if (CliGetEventNotificationList(pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferClient, + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferObject, NULL, &ppEventNotification) == NV_OK && + ppEventNotification != NULL) + { + // + // Check if client has registered for shadow buffer. If not, we will call client only if RM has + // serviced a fault packet. This reduces the duplicate notifications and enhances test speeds. + // + pClientShadowBuffer = + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pClientShadowFaultBuffer[NON_REPLAYABLE_FAULT_BUFFER]; + + if (pClientShadowBuffer != NULL || bNotifyClient) + { + rmStatus = notifyEvents(pGpu, *ppEventNotification, NVC369_NOTIFIER_MMU_FAULT_NON_REPLAYABLE, + 0, 0, NV_OK, NV_OS_WRITE_THEN_AWAKEN); + NV_ASSERT(rmStatus == NV_OK); + } + } + + return rmStatus; +} + +NV_STATUS +kgmmuServiceNonReplayableFault_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NV_STATUS rmStatus = NV_OK; + GMMU_SHADOW_FAULT_BUF *pShadowFaultBuf; + GMMU_FAULT_PACKET faultPacket; + NvBool bNotifyClient = NV_FALSE; + + pShadowFaultBuf = KERNEL_POINTER_FROM_NvP64(GMMU_SHADOW_FAULT_BUF *, pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].pRmShadowFaultBuffer); + NV_ASSERT_OR_RETURN(pShadowFaultBuf != NULL, NV_ERR_INVALID_POINTER); + + // + // We don't disable Non-Replayable interrupts as we have copied all data from HW buffers and interrupts + // should be enabled if new fault is generated + // Walk thru the fault packets in shadow fault buffer and see if RM need to service anything + // + while (!queueIsEmpty(pShadowFaultBuf)) + { + + portMemSet((void *)&faultPacket, 0, sizeof(GMMU_FAULT_PACKET)); + queuePopAndCopy(pShadowFaultBuf, (void *)&faultPacket); + + rmStatus = kgmmuHandleNonReplayableFaultPacket_HAL(pGpu, pKernelGmmu, &faultPacket); + if (rmStatus != NV_OK) + return rmStatus; + + bNotifyClient = NV_TRUE; + } + + rmStatus = kgmmuNotifyNonReplayableFault_HAL(pGpu, pKernelGmmu, bNotifyClient); + return rmStatus; +} + +/** + * @brief handles an engine or PBDMA MMU fault + * + * "engine" is defined as an engine that is downstream of host (graphics, ce, + * etc...). + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * @param[in] pParsedFaultEntry Parsed Fault entry + * @param[in] pMmuExceptionData FIFO exception packet used + * for printing fault info. + * + * @returns + */ +NV_STATUS +kgmmuServiceMmuFault_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvP64 pParsedFaultInfo, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData +) +{ + NV_STATUS rmStatus = NV_OK; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + KernelChannel *pKernelChannel = NULL; + MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry = KERNEL_POINTER_FROM_NvP64(MMU_FAULT_BUFFER_ENTRY *, pParsedFaultInfo); + + // Find channel ID from instance pointer + rmStatus = kfifoConvertInstToKernelChannel_HAL(pGpu, pKernelFifo, &pParsedFaultEntry->mmuFaultInstBlock, &pKernelChannel); + + if (rmStatus != NV_OK || pKernelChannel == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Could not get chid from inst addr\n"); + DBG_BREAKPOINT(); + return rmStatus; + } + + // Reset channel + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + NvBool bIsMmuDebugModeEnabled = NV_FALSE; + NvU32 engDesc; + + rmStatus = kchannelGetEngine_HAL(pGpu, pKernelChannel, &engDesc); + if ((rmStatus == NV_OK) && IS_GR(engDesc)) + { + NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS params; + + portMemSet(¶ms, 0, sizeof(params)); + NV_RM_RPC_CONTROL(pGpu, + RES_GET_CLIENT_HANDLE(pKernelChannel), + RES_GET_HANDLE(pKernelChannel), + NV0090_CTRL_CMD_GET_MMU_DEBUG_MODE, + ¶ms, + sizeof(params), + rmStatus); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RM control call to read MMU debug mode failed, rmStatus 0x%x\n", + rmStatus); + DBG_BREAKPOINT(); + } + else + { + bIsMmuDebugModeEnabled = params.bMode; + } + } + + NV_PRINTF(LEVEL_INFO, "bIsMmuDebugModeEnabled: %s\n", + bIsMmuDebugModeEnabled ? "TRUE" : "FALSE"); + + if (!bIsMmuDebugModeEnabled) + { + RmCtrlParams rmCtrlParams = {0}; + NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS resetChannelParams = {0}; + RsClient *pClient = RES_GET_CLIENT(pKernelChannel); + Device *pDevice = GPU_RES_GET_DEVICE(pKernelChannel); + NvU32 subdeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu); + Subdevice *pSubDevice; + RM_ENGINE_TYPE rmEngineType; + + rmStatus = subdeviceGetByInstance(pClient, RES_GET_HANDLE(pDevice), + subdeviceInstance, &pSubDevice); + if (rmStatus != NV_OK) + return rmStatus; + + GPU_RES_SET_THREAD_BC_STATE(pSubDevice); + + rmCtrlParams.hClient = RES_GET_CLIENT_HANDLE(pKernelChannel); + rmCtrlParams.hObject = RES_GET_HANDLE(pKernelChannel); + rmCtrlParams.cmd = NV906F_CTRL_CMD_RESET_CHANNEL; + rmCtrlParams.pParams = &resetChannelParams; + rmCtrlParams.paramsSize = sizeof(NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS); + + if (kfifoIsMmuFaultEngineIdPbdma(pGpu, pKernelFifo, pParsedFaultEntry->mmuFaultEngineId)) + { + rmEngineType = RM_ENGINE_TYPE_HOST; + } + else + { + rmStatus = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_MMU_FAULT_ID, pParsedFaultEntry->mmuFaultEngineId, + ENGINE_INFO_TYPE_RM_ENGINE_TYPE, (NvU32 *)&rmEngineType); + NV_ASSERT(rmStatus == NV_OK); + } + + resetChannelParams.engineID = gpuGetNv2080EngineType(rmEngineType); + resetChannelParams.subdeviceInstance = pSubDevice->subDeviceInst; + resetChannelParams.resetReason = NV906F_CTRL_CMD_RESET_CHANNEL_REASON_MMU_FLT; + + // Update the per-channel error notifier before performing the RC + rmStatus = krcErrorSetNotifier(pGpu, GPU_GET_KERNEL_RC(pGpu), + pKernelChannel, + ROBUST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT, + rmEngineType, + RC_NOTIFIER_SCOPE_TSG); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to set error notifier, rmStatus 0x%x\n", + rmStatus); + DBG_BREAKPOINT(); + } + + // + // Reset rmStatus before calling reset channel RPC as we should return + // status of this RPC which actually performs channel reset. + // + rmStatus = NV_OK; + + NV_RM_RPC_CONTROL(pGpu, + rmCtrlParams.hClient, + rmCtrlParams.hObject, + rmCtrlParams.cmd, + rmCtrlParams.pParams, + rmCtrlParams.paramsSize, + rmStatus + ); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "RM control call to reset channel failed, rmStatus 0x%x\n", + rmStatus); + DBG_BREAKPOINT(); + } + } + + // + // Fill exception info in FifoData. + // Also mark this exception as notified to prevent duplication notification + // in vgpuService when PF has done its RC. + // + kchannelFillMmuExceptionInfo(pKernelChannel, pMmuExceptionData); + + if (IS_GR(engDesc) && pMmuExceptionData->bGpc) + { + KernelGraphicsContext *pKernelGraphicsContext; + + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(rmStatus, + kgrctxFromKernelChannel(pKernelChannel, + &pKernelGraphicsContext)); + if (rmStatus == NV_OK) + { + kgrctxRecordMmuFault(pGpu, pKernelGraphicsContext, + kgmmuGetFaultInfoFromFaultPckt_HAL(pKernelGmmu, pParsedFaultEntry), + pParsedFaultEntry->mmuFaultAddress, + pParsedFaultEntry->mmuFaultType, + pParsedFaultEntry->mmuFaultAccessType); + } + } + + return rmStatus; + } + + rmStatus = kgmmuServiceChannelMmuFault_HAL(pGpu, pKernelGmmu, pParsedFaultEntry, + pMmuExceptionData, pKernelChannel); + if (NV_OK != rmStatus) + { + NV_PRINTF(LEVEL_ERROR, "Could not service MMU fault for chid %x\n", + kchannelGetDebugTag(pKernelChannel)); + } + + return rmStatus; +} + +NvU32 +kgmmuGetFaultInfoFromFaultPckt_GV100 +( + KernelGmmu *pKernelGmmu, + MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry +) +{ + NvU32 faultInfo = 0; + + if (pParsedFaultEntry == NULL) + return 0; + + // + // This is a bit insane. We don't have any protection against changing bit position. + // Still copying the bits and relying on fact that MMU_FAULT_INFO will always keep info consistent + // + faultInfo = FLD_SET_DRF_NUM(_PFB_PRI, _MMU_FAULT_INFO, _FAULT_TYPE, pParsedFaultEntry->mmuFaultType, faultInfo); + faultInfo = FLD_SET_DRF_NUM(_PFB_PRI, _MMU_FAULT_INFO, _CLIENT, pParsedFaultEntry->mmuFaultClientId, faultInfo); + faultInfo = FLD_SET_DRF_NUM(_PFB_PRI, _MMU_FAULT_INFO, _ACCESS_TYPE, pParsedFaultEntry->mmuFaultAccessType, faultInfo); + faultInfo = FLD_SET_DRF_NUM(_PFB_PRI, _MMU_FAULT_INFO, _CLIENT_TYPE, pParsedFaultEntry->mmuFaultClientType, faultInfo); + faultInfo = FLD_SET_DRF_NUM(_PFB_PRI, _MMU_FAULT_INFO, _GPC_ID, pParsedFaultEntry->mmuFaultGpcId, faultInfo); + faultInfo = FLD_SET_DRF_NUM(_PFB_PRI, _MMU_FAULT_INFO, _PROTECTED_MODE, pParsedFaultEntry->bFaultInProtectedMode, faultInfo); + faultInfo = FLD_SET_DRF_NUM(_PFB_PRI, _MMU_FAULT_INFO, _REPLAYABLE_FAULT, pParsedFaultEntry->bFaultTypeReplayable, faultInfo); + faultInfo = FLD_SET_DRF_NUM(_PFB_PRI, _MMU_FAULT_INFO, _VALID, pParsedFaultEntry->bFaultEntryValid, faultInfo); + + return faultInfo; +} + +static NV_STATUS +_kgmmuCreateExceptionDataFromPriv_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry, + FIFO_MMU_EXCEPTION_DATA *pMmuExceptionData +) +{ + NV_STATUS rmStatus = NV_OK; + NvU32 regDataLo, regDataHi; + NvU64 tempLo = 0; + NvU64 tempHi = 0; + NV_ASSERT_OR_RETURN(pParsedFaultEntry != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(pMmuExceptionData != NULL, NV_ERR_INVALID_ARGUMENT); + + // FaultInstPtr + { + kgmmuReadMmuFaultInstHiLo_HAL(pGpu, pKernelGmmu, ®DataHi, ®DataLo); + + tempLo = DRF_VAL(_PFB_PRI, _MMU_FAULT_INST_LO, _ADDR, regDataLo); + tempHi = DRF_VAL(_PFB_PRI, _MMU_FAULT_INST_HI, _ADDR, regDataHi); + pParsedFaultEntry->mmuFaultInstBlock.address = tempLo + (tempHi << DRF_SIZE(NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR)); + pParsedFaultEntry->mmuFaultInstBlock.address <<= DRF_BASE(NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR); + pParsedFaultEntry->mmuFaultInstBlock.aperture = DRF_VAL(_PFB_PRI, _MMU_FAULT_INST_LO, _APERTURE, regDataLo); + pParsedFaultEntry->mmuFaultInstBlock.gfid = GPU_GFID_PF; + pParsedFaultEntry->mmuFaultEngineId = DRF_VAL(_PFB_PRI, _MMU_FAULT_INST_LO, _ENGINE_ID, regDataLo); + } + + // Fault Addr + { + kgmmuReadMmuFaultAddrHiLo_HAL(pGpu, pKernelGmmu, ®DataHi, ®DataLo); + + tempLo = DRF_VAL(_PFB_PRI, _MMU_FAULT_ADDR_LO, _ADDR, regDataLo); + tempHi = DRF_VAL(_PFB_PRI, _MMU_FAULT_ADDR_HI, _ADDR, regDataHi); + + pParsedFaultEntry->mmuFaultAddress = (tempLo + (tempHi << DRF_SIZE(NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR))) << + (DRF_BASE(NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR)); + + kgmmuSignExtendFaultAddress_HAL(pGpu, pKernelGmmu, &pParsedFaultEntry->mmuFaultAddress); + } + + // FaultInfo + { + regDataLo = kgmmuReadMmuFaultInfo_HAL(pGpu, pKernelGmmu); + + rmStatus = kgmmuGetFaultType_HAL(pGpu, pKernelGmmu, DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _FAULT_TYPE, regDataLo), + &pParsedFaultEntry->mmuFaultType); + NV_ASSERT_OR_RETURN(rmStatus == NV_OK, rmStatus); + pParsedFaultEntry->mmuFaultAccessType = DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _ACCESS_TYPE, regDataLo); + pParsedFaultEntry->mmuFaultClientId = DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _CLIENT, regDataLo); + pParsedFaultEntry->mmuFaultClientType = DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _CLIENT_TYPE, regDataLo); + pParsedFaultEntry->mmuFaultGpcId = DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _GPC_ID, regDataLo); + pParsedFaultEntry->bFaultEntryValid = DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _VALID, regDataLo); + pParsedFaultEntry->bFaultInProtectedMode = DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _PROTECTED_MODE, regDataLo); + pParsedFaultEntry->bFaultTypeReplayable = DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _REPLAYABLE_FAULT, regDataLo); + pParsedFaultEntry->bReplayableFaultEn = DRF_VAL(_PFB_PRI, _MMU_FAULT_INFO, _REPLAYABLE_FAULT_EN, regDataLo); + } + + pMmuExceptionData->addrLo = (NvU32)(pParsedFaultEntry->mmuFaultAddress & 0xFFFFFFFFUL); + pMmuExceptionData->addrHi = (NvU32)(pParsedFaultEntry->mmuFaultAddress >> 32); + pMmuExceptionData->faultType = pParsedFaultEntry->mmuFaultType; + pMmuExceptionData->clientId = pParsedFaultEntry->mmuFaultClientId; + if (pParsedFaultEntry->mmuFaultClientType == NV_PFAULT_MMU_CLIENT_TYPE_GPC) + { + pMmuExceptionData->bGpc = NV_TRUE; + pMmuExceptionData->gpcId = pParsedFaultEntry->mmuFaultGpcId; + } + else + { + pMmuExceptionData->bGpc = NV_FALSE; + pMmuExceptionData->gpcId = 0; + } + pMmuExceptionData->accessType = pParsedFaultEntry->mmuFaultAccessType; + pMmuExceptionData->faultEngineId = pParsedFaultEntry->mmuFaultEngineId; + + return rmStatus; +} + +/** + * @brief Resets REPLAYABLE/NON_REPLAYABLE FAULT error status + * + * @param[in] faultBufType FaultBuffer type + * + * @returns - Value resetting corresponding status fields + */ + +static inline NvU32 +_kgmmuResetFaultBufferError_GV100 +( + NvU32 faultBufType +) +{ + NvU32 faultBufStatus = 0; + NV_ASSERT_OR_RETURN((faultBufType < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + + if (faultBufType == REPLAYABLE_FAULT_BUFFER) + return FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_STATUS, _REPLAYABLE_ERROR, _RESET, faultBufStatus); + else + return FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_STATUS, _NON_REPLAYABLE_ERROR, _RESET, faultBufStatus); +} + +/** + * @brief Handles all BAR2 faults including fault buffer and + * access counter BAR2 errors. + * + */ +static NV_STATUS +_kgmmuServiceBar2Faults_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 faultStatus, + NvU32 mmuFaultClientId +) +{ + NV_STATUS rmStatus = NV_OK; + OBJUVM *pUvm = GPU_GET_UVM(pGpu); + NvU32 i; + + NvBool replayableFaultError = FLD_TEST_DRF(_PFB_PRI, _MMU_FAULT_STATUS, + _REPLAYABLE_ERROR, _SET, faultStatus); + NvBool nonReplayableFaultError = FLD_TEST_DRF(_PFB_PRI, _MMU_FAULT_STATUS, + _NON_REPLAYABLE_ERROR, _SET, faultStatus); + NvBool accessCntrError = kgmmuTestAccessCounterWriteNak_HAL(pGpu, pKernelGmmu); + + NvBool bVidmemAccessBitBufError = kgmmuTestVidmemAccessBitBufferError_HAL(pGpu, pKernelGmmu, faultStatus); + + // + // If it's a MMU Fault buffer BAR2 error, disable and re-enable fault buffers after BAR2 rebind. + // In case of BAR2 fault on both fault buffers, RM should see two error interrupts. + // So, just handle one buffer here and next buffer can be reset with next incoming interrupt + // + NvU32 faultBufType = replayableFaultError ? REPLAYABLE_FAULT_BUFFER : + NON_REPLAYABLE_FAULT_BUFFER; + if (replayableFaultError || nonReplayableFaultError) + { + rmStatus = kgmmuDisableFaultBuffer_HAL(pGpu, pKernelGmmu, faultBufType, NV_TRUE, GPU_GFID_PF); + if (rmStatus != NV_OK) + return rmStatus; + } + + // Access counter Bar2 fault handling + if (accessCntrError) + { + for (i = 0; i < pUvm->accessCounterBufferCount; i++) + { + rmStatus = uvmDisableAccessCntr_HAL(pGpu, pUvm, i, NV_TRUE); + if (rmStatus != NV_OK) + return rmStatus; + } + } + + // vidmem access bit buffer BAR2 fault handling + if (bVidmemAccessBitBufError) + { + kgmmuDisableVidmemAccessBitBuf_HAL(pGpu, pKernelGmmu); + } + + // do a rebind of bar2 + kbusBindBar2_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), BAR2_MODE_VIRTUAL); + + kgmmuServiceMthdBuffFaultInBar2Fault(pGpu, pKernelGmmu); + + if (replayableFaultError || nonReplayableFaultError) + { + rmStatus = kgmmuEnableFaultBuffer_HAL(pGpu, pKernelGmmu, faultBufType, NV_TRUE, GPU_GFID_PF); + if (rmStatus != NV_OK) + return rmStatus; + + faultStatus |= _kgmmuResetFaultBufferError_GV100(faultBufType); + } + + if (accessCntrError) + { + for (i = 0; i < pUvm->accessCounterBufferCount; i++) + { + rmStatus = uvmEnableAccessCntr_HAL(pGpu, pUvm, i, NV_TRUE); + if (rmStatus != NV_OK) + return rmStatus; + } + + kgmmuClearAccessCounterWriteNak_HAL(pGpu, pKernelGmmu); + } + + if (bVidmemAccessBitBufError) + { + rmStatus = kgmmuEnableVidmemAccessBitBuf_HAL(pGpu, pKernelGmmu); + if (rmStatus != NV_OK) + return rmStatus; + } + + return rmStatus; +} + +static NV_STATUS +_kgmmuHandleReplayablePrivFault_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + MMU_FAULT_BUFFER_ENTRY *pParsedFaultEntry +) +{ + GMMU_FAULT_CANCEL_INFO cancelInfo; + NvU32 faultStatus; + + // Fill in the structure used by cancel routine to cancel fault + cancelInfo.clientId = pParsedFaultEntry->mmuFaultClientId; + cancelInfo.gpcId = pParsedFaultEntry->mmuFaultGpcId; + cancelInfo.instBlock = pParsedFaultEntry->mmuFaultInstBlock; + + // + // Clear the VALID bit to ensure non_replayable fault shows up when replayable + // fault is canceled + // + faultStatus = kgmmuReadMmuFaultStatus_HAL(pGpu, pKernelGmmu, GPU_GFID_PF); + faultStatus = FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_STATUS, _VALID, _CLEAR, faultStatus); + kgmmuWriteMmuFaultStatus_HAL(pGpu, pKernelGmmu, faultStatus); + + return kgmmuFaultCancelTargeted_HAL(pGpu, pKernelGmmu, &cancelInfo); +} + +/** + * @brief Handles PRI MMU faults + * PRI MMU faults are used for BAR1/BAR2, Physical faults and + * capturing faults in the event fault buffers are disabled. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGmmu KernelGmmu pointer + * + * @returns + */ +NV_STATUS +kgmmuServicePriFaults_GV100 +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NV_STATUS rmStatus = NV_OK; + KernelRc *pKernelRC = GPU_GET_KERNEL_RC(pGpu); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvU32 faultStatus = kgmmuReadMmuFaultStatus_HAL(pGpu, pKernelGmmu, GPU_GFID_PF); + PEVENTNOTIFICATION *ppEventNotification = NULL; + MMU_FAULT_BUFFER_ENTRY parsedFaultEntry = {{0}, 0}; + FIFO_MMU_EXCEPTION_DATA mmuExceptionData = {0}; + NvBool bBarFault = NV_FALSE; + NvU32 vfFaultType = NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID; + + if (FLD_TEST_DRF(_PFB_PRI, _MMU_FAULT_STATUS, _VALID, _SET, faultStatus)) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kgmmuCreateExceptionDataFromPriv_GV100(pGpu, pKernelGmmu, &parsedFaultEntry, &mmuExceptionData)); + + // + // BAR faults mean incorrect BAR mappings. These are usually fatal with + // fullchip reset that follows this. + // + if (kgmmuIsFaultEngineBar1_HAL(pKernelGmmu, parsedFaultEntry.mmuFaultEngineId)) + { + vfFaultType = NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR1; + + // do a rebind of bar1 + kbusBar1InstBlkBind_HAL(pGpu, pKernelBus); + NV_PRINTF(LEVEL_ERROR, "BAR1 MMU Fault\n"); + kgmmuPrintFaultInfo_HAL(pGpu, pKernelGmmu, parsedFaultEntry.mmuFaultEngineId, &mmuExceptionData); + krcBreakpoint(GPU_GET_KERNEL_RC(pGpu)); + } + else if (kgmmuIsFaultEngineBar2_HAL(pKernelGmmu, parsedFaultEntry.mmuFaultEngineId) && + !kgmmuIsP2PUnboundInstFault_HAL(pKernelGmmu, parsedFaultEntry.mmuFaultType, parsedFaultEntry.mmuFaultClientId)) + { + vfFaultType = NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_BAR2; + + NV_PRINTF(LEVEL_ERROR, "BAR2 MMU Fault\n"); + kgmmuPrintFaultInfo_HAL(pGpu, pKernelGmmu, parsedFaultEntry.mmuFaultEngineId, &mmuExceptionData); + rmStatus = _kgmmuServiceBar2Faults_GV100(pGpu, pKernelGmmu, faultStatus, parsedFaultEntry.mmuFaultClientId); + NV_ASSERT(rmStatus == NV_OK); + krcBreakpoint(GPU_GET_KERNEL_RC(pGpu)); + + bBarFault = NV_TRUE; + } + else if (kgmmuIsFaultEnginePhysical_HAL(pKernelGmmu, parsedFaultEntry.mmuFaultEngineId)) + { + vfFaultType = NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_PHYSICAL; + // + // This fault usually means VPR or out of bounds physical accesses. + // Nothing much we can do except notify clients and wait for a TDR + // + NV_PRINTF(LEVEL_ERROR, "Physical MMU fault\n"); + kgmmuPrintFaultInfo_HAL(pGpu, pKernelGmmu, parsedFaultEntry.mmuFaultEngineId, &mmuExceptionData); + krcBreakpoint(GPU_GET_KERNEL_RC(pGpu)); + + gpuNotifySubDeviceEvent(pGpu, + NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT, NULL, 0, 0, 0); + } + else if (mmuExceptionData.faultType == NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK) + { + NV_PRINTF(LEVEL_ERROR, "Unbound Instance MMU fault\n"); + kgmmuPrintFaultInfo_HAL(pGpu, pKernelGmmu, parsedFaultEntry.mmuFaultEngineId, &mmuExceptionData); + krcBreakpoint(GPU_GET_KERNEL_RC(pGpu)); + vfFaultType = NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_UNBOUND_INSTANCE; + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgmmuServiceUnboundInstBlockFault_HAL(pGpu, pKernelGmmu, NV_PTR_TO_NvP64(&parsedFaultEntry), + &mmuExceptionData)); + } + else + { + // + // Check if any fault buffer is disabled. If yes, then service the fault + // snapped in priv register. + // Non-Replayable Faults - These faults are serviced as fault buffer faults i.e channel + // will be RCed. + // Replayable Faults - These faults will be cancelled as RM doesn't support replaying such + // faults. Cancelling these faults will bring them back as non-replayable faults. + // + NvBool bReplayableBufDis = FLD_TEST_DRF(_PFB_PRI, _MMU_FAULT_BUFFER_SIZE,_ENABLE, _FALSE, + kgmmuReadMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF)); + NvBool bNonReplayBufDis = FLD_TEST_DRF(_PFB_PRI, _MMU_FAULT_BUFFER_SIZE,_ENABLE, _FALSE, + kgmmuReadMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF)); + if (bReplayableBufDis || bNonReplayBufDis) + { + if (parsedFaultEntry.bFaultEntryValid) + { + // Replayable faults snapped in privs are handled differently, so check if replayable + if (parsedFaultEntry.bFaultTypeReplayable) + { + NV_PRINTF(LEVEL_ERROR, + "MMU Fault : Replayable fault with fault-buffer disabled. Initiating cancel\n"); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _kgmmuHandleReplayablePrivFault_GV100(pGpu, pKernelGmmu, &parsedFaultEntry)); + } + else + { + kgmmuPrintFaultInfo_HAL(pGpu, pKernelGmmu, parsedFaultEntry.mmuFaultEngineId, + &mmuExceptionData); + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kgmmuServiceMmuFault_HAL(pGpu, pKernelGmmu, NV_PTR_TO_NvP64(&parsedFaultEntry), + &mmuExceptionData)); + } + } + } + else + { + kgmmuPrintFaultInfo_HAL(pGpu, pKernelGmmu, parsedFaultEntry.mmuFaultEngineId, &mmuExceptionData); + krcBreakpoint(GPU_GET_KERNEL_RC(pGpu)); + } + } + + // In case of SR-IOV vgpu, the fault needs to be cleared from the host side. + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && (vfFaultType != NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID)) + rmStatus = kgmmuServiceVfPriFaults(pGpu, pKernelGmmu, vfFaultType); + + // Clear the VALID bit to indicate we have seen this. + faultStatus = FLD_SET_DRF(_PFB_PRI, _MMU_FAULT_STATUS, _VALID, _CLEAR, faultStatus); + kgmmuWriteMmuFaultStatus_HAL(pGpu, pKernelGmmu, faultStatus); + + if (bBarFault && pKernelRC != NULL && pKernelRC->bRcOnBar2Fault) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_IN_FATAL_ERROR, NV_TRUE); + (void)kfifoRecoverAllChannels_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu), GPU_GFID_PF); + } + + if ((NV_OK == CliGetEventNotificationList(pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferClient, + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferObject, NULL, &ppEventNotification)) && ppEventNotification != NULL) + { + rmStatus = notifyEvents(pGpu, *ppEventNotification, NVC369_NOTIFIER_MMU_FAULT_NON_REPLAYABLE_IN_PRIV, + 0, 0, NV_OK, NV_OS_WRITE_THEN_AWAKEN); + } + + // Send event notifier in response to MMU Poison Fault. + if ((parsedFaultEntry.mmuFaultType == fault_poison) && + gpuIsGlobalPoisonFuseEnabled(pGpu)) + { + NV_ERROR_CONT_LOCATION loc = {0}; + + // Error containment location information + loc.locType = NV_ERROR_CONT_LOCATION_TYPE_NONE; + + // Generate Error Containment Xid, send NV2080_NOTIFIER*, mark device for Reset or Drain And Reset + NV_ASSERT_OK_OR_RETURN( + gpuUpdateErrorContainmentState_HAL(pGpu, + NV_ERROR_CONT_ERR_ID_E13_MMU_POISON, // Error type + loc, // Loc + NULL)); // RC Error Code + } + } + return rmStatus; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c index 26d524d60a..d505a39e10 100644 --- a/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c +++ b/src/nvidia/src/kernel/gpu/mmu/bar2_walk.c @@ -566,6 +566,7 @@ _bar2WalkCBLevelAlloc { NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu) || kbusIsBarAccessBlocked(pKernelBus)); pdeBase = pKernelBus->bar2[gfid].pdeBase; pteBase = pKernelBus->bar2[gfid].pteBase; @@ -648,6 +649,7 @@ _bar2WalkCBLevelAlloc { NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu) || kbusIsBarAccessBlocked(pKernelBus)); pKernelBus->bar2[gfid].pdeBase = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); pKernelBus->bar2[gfid].pPDEMemDesc = pMemDesc; @@ -733,6 +735,7 @@ _bar2WalkCBLevelAlloc { NV_ASSERT(pKernelBus->bar2[gfid].bBootstrap || IS_GFID_VF(gfid) || KBUS_BAR0_PRAMIN_DISABLED(pGpu) || + KBUS_CPU_VISIBLE_BAR12_DISABLED(pGpu) || kbusIsBarAccessBlocked(pKernelBus)); pKernelBus->bar2[gfid].pteBase = memdescGetPhysAddr(pMemDesc, AT_GPU, 0); diff --git a/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c b/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c index 919e655cef..8cb8bac95c 100644 --- a/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c +++ b/src/nvidia/src/kernel/gpu/mmu/fault_buffer_ctrl.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c index 06f0c98933..f4d3c94244 100644 --- a/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c +++ b/src/nvidia/src/kernel/gpu/mmu/kern_gmmu.c @@ -38,6 +38,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "vgpu/vgpu_events.h" #include "gpu/mem_mgr/mem_desc.h" +#include "gpu/subdevice/subdevice.h" #include "os/os.h" #include "rmapi/rmapi.h" #include "gpu/gpu.h" @@ -130,7 +131,7 @@ _kgmmuInitStaticInfo KernelGmmu *pKernelGmmu ) { - NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status; // @@ -144,20 +145,19 @@ _kgmmuInitStaticInfo NV_ASSERT_OK_OR_RETURN(kgmmuFmtFamiliesInit_HAL(pGpu, pKernelGmmu)); } - pStaticInfo = portMemAllocNonPaged(sizeof(*pStaticInfo)); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_INSUFFICIENT_RESOURCES); - portMemSet(pStaticInfo, 0, sizeof(*pStaticInfo)); + pKernelGmmu->pStaticInfo = portMemAllocNonPaged(sizeof(*pKernelGmmu->pStaticInfo)); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelGmmu->pStaticInfo != NULL, NV_ERR_INSUFFICIENT_RESOURCES); + portMemSet(pKernelGmmu->pStaticInfo, 0, sizeof(*pKernelGmmu->pStaticInfo)); NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, - kgmmuInitStaticInfo_HAL(pGpu, pKernelGmmu, pStaticInfo), - fail); - - pKernelGmmu->pStaticInfo = pStaticInfo; + pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO, + pKernelGmmu->pStaticInfo, sizeof(*pKernelGmmu->pStaticInfo)), fail); fail: if (status != NV_OK) { - portMemFree(pStaticInfo); + portMemFree(pKernelGmmu->pStaticInfo); } return status; @@ -190,6 +190,18 @@ NV_STATUS kgmmuStateInitLocked_IMPL return status; } + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + pGpu->setProperty(pGpu, PDB_PROP_GPU_ATS_SUPPORTED, pVSI->bAtsSupported); + } + + // Setup Fault buffer if enabled + if (!pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + NV_ASSERT_OK_OR_RETURN(kgmmuFaultBufferInit_HAL(pGpu, pKernelGmmu)); + } + return status; } @@ -326,6 +338,8 @@ NV_STATUS kgmmuStatePostLoad_IMPL return status; } + NV_ASSERT_OK_OR_RETURN(kgmmuInitCeMmuFaultIdRange_HAL(pGpu, pKernelGmmu)); + return status; } @@ -400,6 +414,81 @@ kgmmuStateDestroy_IMPL(OBJGPU *pGpu, KernelGmmu *pKernelGmmu) memdescDestroy(pKernelGmmu->pWarPageDirectory0); pKernelGmmu->pWarPageDirectory0 = NULL; } + + // Only if faultBuffer is enabled + if (!pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + (void)kgmmuFaultBufferDestroy_HAL(pGpu, pKernelGmmu); + } +} + +NV_STATUS +kgmmuStateLoad_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 flags +) +{ + NV_STATUS status = NV_OK; + + // Only if faultBuffer is enabled + if (!pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + status = kgmmuFaultBufferLoad_HAL(pGpu, pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); + NV_ASSERT_OK_OR_RETURN(status); + + // + // Note1: We check both enablement of replayable fault buffer as well + // as PM codepath because replayable fault buffer is client controlled + // and it may be or may not be enabled at the time of S3 entry / exit. + // Also, the state of the replayable fault buffer needs to be + // disabled / enabled during S3 entry / exit since the client is + // unaware of its state being lost during S3 entry. + // + if ((pKernelGmmu->getProperty(pKernelGmmu, + PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE)) && + (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH))) + { + status = kgmmuFaultBufferLoad_HAL(pGpu, pKernelGmmu, + REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); + } + return status; + } + + return NV_OK; +} + +NV_STATUS +kgmmuStateUnload_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 flags +) +{ + NV_STATUS status = NV_OK; + + // Only if faultBuffer is enabled + if (!pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + status = kgmmuFaultBufferUnload_HAL(pGpu, pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); + NV_ASSERT_OK_OR_RETURN(status); + + // See Note1: + if ((pKernelGmmu->getProperty(pKernelGmmu, + PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE)) && + (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_CODEPATH))) + { + status = kgmmuFaultBufferUnload_HAL(pGpu, pKernelGmmu, + REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); + } + return status; + } + + return NV_OK; } /*! @@ -610,31 +699,6 @@ kgmmuGetStaticInfo_IMPL return pKernelGmmu->pStaticInfo; } -/*! - * @brief Initializes static info data from the Physical side. - * - * @param pGpu - * @param pKernelGmmu - * @param[out] pStaticInfo pointer to the static info init on Physical driver. - */ -NV_STATUS -kgmmuInitStaticInfo_KERNEL -( - OBJGPU *pGpu, - KernelGmmu *pKernelGmmu, - NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pStaticInfo -) -{ - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_STATUS status; - - status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_GMMU_GET_STATIC_INFO, - pStaticInfo, sizeof(*pStaticInfo)); - - return status; -} - /*! * Retrieve GMMU format based on version and big page size. */ @@ -1205,6 +1269,21 @@ kgmmuFaultBufferReplayableAllocate_IMPL return status; } } + else + { + status = kgmmuFaultBufferLoad_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); + + if (status != NV_OK) + { + kgmmuFaultBufferFree(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER); + return status; + } + + // for non-gsp builds, set the pdb property here. + pKernelGmmu->setProperty(pKernelGmmu, + PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE, + NV_TRUE); + } pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferClient = hClient; pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferObject = hObject; @@ -1253,6 +1332,23 @@ kgmmuFaultBufferReplayableDestroy_IMPL status); } } + else + { + status = kgmmuFaultBufferUnload_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unloading Replayable Fault buffer failed (status=0x%08x), proceeding...\n", + status); + } + else + { + // for non-gsp builds, reset the pdb property here. + pKernelGmmu->setProperty(pKernelGmmu, + PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE, + NV_FALSE); + } + } if (RMCFG_FEATURE_PLATFORM_GSP) { @@ -1960,8 +2056,9 @@ kgmmuInstBlkInit_IMPL NvU32 dirBaseHiData; NvU32 dirBaseLoOffset; NvU32 dirBaseLoData; - NvU32 atsOffset; - NvU32 atsData; + NvU32 atsOffset = 0; + NvU32 atsData = 0; + NvU32 pasid; NvU32 magicValueOffset; NvU32 magicValueData; NV_STATUS status = NV_OK; @@ -1977,16 +2074,25 @@ kgmmuInstBlkInit_IMPL pVAS, pInstBlkParams, subctxId, &dirBaseLoOffset, &dirBaseLoData, &dirBaseHiOffset, &dirBaseHiData)); + // + // Enable ATS in instance block only when both ATS is enabled in the + // vaspace and a valid PASID is provisioned through + // NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY. + // if ((pVAS != NULL) && vaspaceIsAtsEnabled(pVAS)) { - // Coherent link ATS parameters are only set on the new VMM path. - status = kgmmuInstBlkAtsGet_HAL(pKernelGmmu, pVAS, subctxId, &atsOffset, &atsData); - NV_ASSERT_OR_RETURN((status == NV_OK), status); - } - else - { - atsOffset = 0; - atsData = 0; + if ((status = vaspaceGetPasid(pVAS, &pasid)) == NV_OK) + { + // Coherent link ATS parameters are only set on the new VMM path. + status = kgmmuInstBlkAtsGet_HAL(pKernelGmmu, pVAS, subctxId, + &atsOffset, &atsData); + NV_ASSERT_OR_RETURN((status == NV_OK), status); + } + else + { + // Proceed with ATS disabled in instance block if PASID is not yet provisioned + NV_ASSERT_OR_RETURN((status == NV_ERR_NOT_READY), status); + } } status = kgmmuInstBlkMagicValueGet_HAL(pKernelGmmu, &magicValueOffset, &magicValueData); @@ -2156,6 +2262,57 @@ kgmmuRegisterIntrService_IMPL NV_ASSERT(pRecords[engineIdx].pInterruptService == NULL); pRecords[engineIdx].pInterruptService = staticCast(pKernelGmmu, IntrService); } + + if (!IS_GSP_CLIENT(pGpu)) + { + engineIdx = MC_ENGINE_IDX_GMMU; + NV_ASSERT(pRecords[engineIdx].pInterruptService == NULL); + pRecords[engineIdx].pInterruptService = staticCast(pKernelGmmu, IntrService); + + NV_ASSERT(pRecords[engineIdx].pNotificationService == NULL); + pRecords[engineIdx].bFifoWaiveNotify = NV_FALSE; + pRecords[engineIdx].pNotificationService = staticCast(pKernelGmmu, IntrService); + + static NvU16 physicalEngineIdxList[] = { + MC_ENGINE_IDX_NON_REPLAYABLE_FAULT, + MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR, + MC_ENGINE_IDX_INFO_FAULT + }; + + for (NvU32 tableIdx = 0; tableIdx < NV_ARRAY_ELEMENTS(physicalEngineIdxList); tableIdx++) + { + engineIdx = physicalEngineIdxList[tableIdx]; + NV_ASSERT(pRecords[engineIdx].pInterruptService == NULL); + pRecords[engineIdx].pInterruptService = staticCast(pKernelGmmu, IntrService); + } + } +} + +/** + * @brief Clears the stall interrupt leaf vector and return whether to call ServiceInterrupt. + * @details Normally there's no need to override this function as its default is used by almost all handlers, + * but MC_ENGINE_IDX_NON_REPLAYABLE_FAULT is cleared in the top half. + * + * @returns NV_TRUE indicating that the interrupt should be handled. + */ +NvBool +kgmmuClearInterrupt_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + IntrServiceClearInterruptArguments *pParams) +{ + NV_ASSERT_OR_RETURN(pParams != NULL, 0); + if (pParams->engineIdx == MC_ENGINE_IDX_NON_REPLAYABLE_FAULT) + { + // Skip clearing the interrupt; just return success. + return NV_TRUE; + } + else + { + // Fallthrough to default handler, which will clear the interrupt. + return intrservClearInterrupt_IMPL(pGpu, staticCast(pKernelGmmu, IntrService), pParams); + } } /** @@ -2178,6 +2335,50 @@ kgmmuServiceInterrupt_IMPL switch (pParams->engineIdx) { + case MC_ENGINE_IDX_GMMU: + { + return kgmmuService_HAL(pGpu, pKernelGmmu); + } + case MC_ENGINE_IDX_NON_REPLAYABLE_FAULT: + { + + // + // This interrupt was already cleared in the top half and "serviced" + // in the top half since copy from HW fault buffer always happens + // in the top half. This servicing is merely copying from the SW + // fault buffer, so doesn't need interrupt clearing. Also, we will + // only copy from the SW fault buffer if the fatalFaultIntrPending + // cache tells us that there is something to copy. Else, we'll just + // return early and rely on another interrupt to fire that will + // eventually update this state. In the top half, we will + // unconditionally write GET back, which will force HW to send us a + // new pulse as long as GET != PUT and we'd be eventually guaranteed + // to copy something into the SW fault buffer. + // + if (portAtomicCompareAndSwapS32(&pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].fatalFaultIntrPending, 0, 1)) + { + status = kgmmuServiceNonReplayableFault_HAL(pGpu, pKernelGmmu); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED( + "Failed to service non-replayable MMU fault error", + status); + } + } + + break; + } + case MC_ENGINE_IDX_NON_REPLAYABLE_FAULT_ERROR: + { + status = kgmmuReportFaultBufferOverflow_HAL(pGpu, pKernelGmmu); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED( + "Failed to report non-replayable MMU fault buffer overflow error", + status); + } + break; + } case MC_ENGINE_IDX_REPLAYABLE_FAULT: { NV_STATUS status = kgmmuServiceReplayableFault_HAL(pGpu, pKernelGmmu); @@ -2216,6 +2417,15 @@ kgmmuServiceInterrupt_IMPL status = NV_ERR_INVALID_STATE; break; } + case MC_ENGINE_IDX_INFO_FAULT: + { + status = kgmmuServicePriFaults_HAL(pGpu, pKernelGmmu); + if (status != NV_OK) + { + NV_ASSERT_OK_FAILED("Failed to service PRI fault error", status); + } + break; + } default: { NV_ASSERT_FAILED("Invalid engineIdx"); @@ -2473,10 +2683,6 @@ kgmmuGetShadowFaultBufferCslContext_IMPL return NULL; } - NV_ASSERT_OR_RETURN( - pConfCompute->getProperty(pConfCompute, PDB_PROP_CONFCOMPUTE_ENCRYPT_ENABLED), - NULL); - switch (type) { case NON_REPLAYABLE_FAULT_BUFFER: @@ -2489,3 +2695,465 @@ kgmmuGetShadowFaultBufferCslContext_IMPL return NULL; } + +NV_STATUS +kgmmuFaultBufferMap_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvU32 gfid +) +{ + MEMORY_DESCRIPTOR *pMemDesc; + struct HW_FAULT_BUFFER *pFaultBuffer; + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + NvU64 vaddr; + NV_STATUS status = NV_OK; + + // Return early if fault buffer is disabled + if (pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + return NV_OK; + + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(!IS_GSP_CLIENT(pGpu), NV_ERR_INVALID_STATE); + + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[gfid].hwFaultBuffers[index]; + pMemDesc = pFaultBuffer->pFaultBufferMemDesc; + + memmgrSetMemDescPageSize_HAL(pGpu, pMemoryManager, pMemDesc, AT_GPU, RM_ATTR_PAGE_SIZE_4KB); + + { + status = kbusMapCpuInvisibleBar2Aperture_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), pMemDesc, + &vaddr, pMemDesc->Size, 0, gfid); + if (status != NV_OK) + { + return status; + } + + NV_ASSERT(pFaultBuffer->bar2FaultBufferAddr == 0); + pFaultBuffer->bar2FaultBufferAddr = vaddr; + } + + if (IS_GFID_PF(gfid)) + { + if (pMemDesc->_addressSpace == ADDR_FBMEM && !RMCFG_FEATURE_PLATFORM_GSP) + { + // + // For Mods and testing, buffer can be allocated in FB. In such cases map it on BAR2 as + // only RM will be the owner of this buffer. BAR1 mappings need code-refactoring as BAR1 vaSpace is + // allocated lazily + // + pFaultBuffer->kernelVaddr = NV_PTR_TO_NvP64(kbusMapRmAperture_HAL(pGpu, pMemDesc)); + if (!pFaultBuffer->kernelVaddr) + { + NV_ASSERT(0); + return NV_ERR_INVALID_ADDRESS; + } + } + else + { + if (memdescGetContiguity(pMemDesc, AT_GPU)) + { + status = memdescMap(pMemDesc, 0, pMemDesc->Size, NV_TRUE, NV_PROTECT_READ_WRITE, + &pFaultBuffer->kernelVaddr, &pFaultBuffer->hCpuFaultBuffer); + if (status != NV_OK) + { + return status; + } + } + else + { + NvU32 i, j; + NvU32 numPages = NV_ROUNDUP(pMemDesc->Size, RM_PAGE_SIZE) / RM_PAGE_SIZE; + GMMU_FAULT_BUFFER_PAGE *pBufferPage; + + pFaultBuffer->pBufferPages = portMemAllocNonPaged(numPages * sizeof(GMMU_FAULT_BUFFER_PAGE)); + if (pFaultBuffer->pBufferPages == NULL) + { + return NV_ERR_NO_MEMORY; + } + + for (i = 0; i < numPages; i++) + { + pBufferPage = &pFaultBuffer->pBufferPages[i]; + + status = memdescMap(pMemDesc, i * RM_PAGE_SIZE, RM_PAGE_SIZE, 1, NV_PROTECT_READ_WRITE, + &pBufferPage->pAddress, &pBufferPage->pPriv); + if (status != NV_OK) + { + break; + } + } + + if (status != NV_OK) + { + for (j = 0; j < i; j++) + { + pBufferPage = &pFaultBuffer->pBufferPages[j]; + + memdescUnmap(pMemDesc, NV_TRUE, osGetCurrentProcess(), + pBufferPage->pAddress, pBufferPage->pPriv); + } + + portMemFree(pFaultBuffer->pBufferPages); + + return status; + } + } + } + + if (memdescGetContiguity(pMemDesc, AT_GPU)) + { + portMemSet(NvP64_VALUE(pFaultBuffer->kernelVaddr), 0, (NvLength)pMemDesc->Size); + } + else + { + NvU32 i; + for (i = 0; i * RM_PAGE_SIZE < pMemDesc->Size; i++) + { + GMMU_FAULT_BUFFER_PAGE *page = &pFaultBuffer->pBufferPages[i]; + portMemSet(NvP64_VALUE(page->pAddress), 0, RM_PAGE_SIZE); + } + } + } + + return status; +} + +NV_STATUS +kgmmuFaultBufferUnmap_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvU32 gfid +) +{ + struct HW_FAULT_BUFFER *pFaultBuffer; + + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + + // Return early if fault buffer is disabled + if (pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + return NV_OK; + + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[gfid].hwFaultBuffers[index]; + + if (pFaultBuffer == NULL) + { + return NV_OK; + } + + if (pFaultBuffer->pFaultBufferMemDesc != NULL) + { + if (IS_GFID_PF(gfid)) + { + // kbusUnmapRmAperture cannot handle discontiguous allocations on GSP-RM + if (pFaultBuffer->pFaultBufferMemDesc->_addressSpace == ADDR_FBMEM && + !RMCFG_FEATURE_PLATFORM_GSP) + { + kbusUnmapRmAperture_HAL(pGpu, + pFaultBuffer->pFaultBufferMemDesc, + (NvU8 **)&pFaultBuffer->kernelVaddr, + NV_TRUE); + } + else + { + if (memdescGetContiguity(pFaultBuffer->pFaultBufferMemDesc, AT_GPU)) + { + memdescUnmap(pFaultBuffer->pFaultBufferMemDesc, NV_TRUE, osGetCurrentProcess(), + pFaultBuffer->kernelVaddr, pFaultBuffer->hCpuFaultBuffer); + } + else + { + if (pFaultBuffer->pBufferPages != NULL) + { + NvU32 i; + NvU32 numPages = NV_ROUNDUP(pFaultBuffer->pFaultBufferMemDesc->Size, RM_PAGE_SIZE) / RM_PAGE_SIZE; + + for (i = 0; i < numPages; i++) + { + GMMU_FAULT_BUFFER_PAGE *pBufferPage; + + pBufferPage = &pFaultBuffer->pBufferPages[i]; + + memdescUnmap(pFaultBuffer->pFaultBufferMemDesc, NV_TRUE, osGetCurrentProcess(), + pBufferPage->pAddress, pBufferPage->pPriv); + } + + portMemFree(pFaultBuffer->pBufferPages); + } + } + } + } + + { + kbusUnmapCpuInvisibleBar2Aperture_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu), + pFaultBuffer->pFaultBufferMemDesc, pFaultBuffer->bar2FaultBufferAddr, gfid); + } + } + + pFaultBuffer->pBufferPages = NULL; + pFaultBuffer->kernelVaddr = NvP64_NULL; + pFaultBuffer->bar2FaultBufferAddr = 0; + return NV_OK; +} + +NV_STATUS +kgmmuServiceVfPriFaults_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 faultType +) +{ + NV_STATUS status = NV_OK; + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS params; + + NV_ASSERT_OR_RETURN(IS_VIRTUAL_WITH_SRIOV(pGpu), NV_ERR_INVALID_ARGUMENT); + + if (faultType == NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_TYPE_INVALID) + return NV_ERR_INVALID_PARAMETER; + + portMemSet(¶ms, 0, sizeof(params)); + params.faultType = faultType; + + NV_RM_RPC_CONTROL(pGpu, pGpu->hDefaultClientShare, pGpu->hDefaultClientShareSubDevice, + NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT, ¶ms, sizeof(params), status); + + return status; +} + +NV_STATUS +kgmmuFaultCancelTargeted_VF +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + GMMU_FAULT_CANCEL_INFO *pCancelInfo +) +{ + TLB_INVALIDATE_PARAMS params; + + // Clear struct before use. + portMemSet(¶ms, 0, sizeof(TLB_INVALIDATE_PARAMS)); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, ¶ms.timeout, 0); + + params.gfid = GPU_GFID_PF; + + // Bug 2029506 fix will remove kgmmuFaultCancelIssueInvalidate call here + return kgmmuFaultCancelIssueInvalidate_HAL(pGpu, pKernelGmmu, pCancelInfo, + ¶ms, NV_FALSE); +} + +NvU32 +kgmmuGetFaultBufferReservedFbSpaceSize_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu +) +{ + NvU32 reservedBytes = 0; + NvU32 faultBufferAddrSpace; + NvU32 faultBufferSize; + NvU32 i; + NV_STATUS status; + + if (pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + return 0; + + for (i = 0; i < NUM_FAULT_BUFFERS; i++) + { + status = kgmmuFaultBufferGetAddressSpace(pGpu, pKernelGmmu, i, + &faultBufferAddrSpace, NULL); + NV_ASSERT(status == NV_OK); + if (status != NV_OK || faultBufferAddrSpace != ADDR_FBMEM) + { + continue; + } + + faultBufferSize = kgmmuSetAndGetDefaultFaultBufferSize_HAL(pGpu, pKernelGmmu, i, GPU_GFID_PF); + reservedBytes += RM_PAGE_ALIGN_UP(faultBufferSize); + } + + return reservedBytes; +} + +NV_STATUS +subdeviceCtrlCmdGmmuGetStaticInfo_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + pParams->replayableFaultBufferSize = kgmmuSetAndGetDefaultFaultBufferSize_HAL(pGpu, pKernelGmmu, + REPLAYABLE_FAULT_BUFFER, + GPU_GFID_PF); + pParams->nonReplayableFaultBufferSize = kgmmuSetAndGetDefaultFaultBufferSize_HAL(pGpu, pKernelGmmu, + NON_REPLAYABLE_FAULT_BUFFER, + GPU_GFID_PF); + + if (gpuIsCCFeatureEnabled(pGpu) && gpuIsGspOwnedFaultBuffersEnabled(pGpu)) + { + NvU32 maxNumPacketsReplayable = pParams->replayableFaultBufferSize / sizeof(struct GMMU_FAULT_PACKET); + NvU32 maxNumPacketsNonReplayable = pParams->nonReplayableFaultBufferSize / sizeof(struct GMMU_FAULT_PACKET); + + pParams->replayableShadowFaultBufferMetadataSize = sizeof(struct GMMU_FAULT_PACKET_METADATA) * maxNumPacketsReplayable; + pParams->nonReplayableShadowFaultBufferMetadataSize = sizeof(struct GMMU_FAULT_PACKET_METADATA) * maxNumPacketsNonReplayable; + } + + return NV_OK; +} + +static NV_STATUS +_kgmmuFaultBufferDescribe +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvU32 index, + NvU64 *pFaultBufferPages, + NvU32 faultBufferSize +) +{ + NV_STATUS status; + MEMORY_DESCRIPTOR *pMemDesc = NULL; + struct HW_FAULT_BUFFER *pFaultBuffer; + NvU32 faultBufferAddrSpace = ADDR_UNKNOWN; + + NV_ASSERT_OR_RETURN((index < NUM_FAULT_BUFFERS), NV_ERR_INVALID_ARGUMENT); + + status = kgmmuFaultBufferCreateMemDesc(pGpu, pKernelGmmu, index, faultBufferSize, + (MEMDESC_FLAGS_GUEST_ALLOCATED | + MEMDESC_FLAGS_EXT_PAGE_ARRAY_MEM), + &pMemDesc); + if (status != NV_OK) + { + return status; + } + + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hwFaultBuffers[index]; + + pFaultBuffer->faultBufferSize = faultBufferSize; + pFaultBuffer->pFaultBufferMemDesc = NULL; + + { + NvBool bIsContiguous = memdescGetContiguity(pMemDesc, AT_GPU); + + if (bIsContiguous) + { + status = kgmmuFaultBufferGetAddressSpace(pGpu, pKernelGmmu, index, &faultBufferAddrSpace, NULL); + if (status != NV_OK) + { + memdescDestroy(pMemDesc); + return status; + } + + memdescDescribe(pMemDesc, faultBufferAddrSpace, + pFaultBufferPages[0], faultBufferSize); + } + else + { + memdescFillPages(pMemDesc, 0, pFaultBufferPages, + RM_PAGE_ALIGN_UP(faultBufferSize)/RM_PAGE_SIZE, + RM_PAGE_SIZE); + } + } + + pFaultBuffer->pFaultBufferMemDesc = pMemDesc; + + return NV_OK; +} + +NV_STATUS +kgmmuFaultBufferReplayableSetup_IMPL +( + OBJGPU *pGpu, + KernelGmmu *pKernelGmmu, + NvHandle hClient, + NvHandle hObject, + NvU32 faultBufferSize, + NvU64 *pFaultBufferPages +) +{ + NV_STATUS status; + struct HW_FAULT_BUFFER *pFaultBuffer; + + if (IS_VIRTUAL_WITHOUT_SRIOV(pGpu) || + pKernelGmmu->getProperty(pKernelGmmu, PDB_PROP_KGMMU_FAULT_BUFFER_DISABLED)) + { + return NV_OK; + } + + pFaultBuffer = &pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hwFaultBuffers[REPLAYABLE_FAULT_BUFFER]; + if (pFaultBuffer->pFaultBufferMemDesc != NULL) + { + return NV_ERR_NOT_SUPPORTED; + } + + status = _kgmmuFaultBufferDescribe(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER, + pFaultBufferPages, faultBufferSize); + + if (status != NV_OK) + { + return status; + } + + status = kgmmuFaultBufferLoad_HAL(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); + if (status != NV_OK) + { + kgmmuFaultBufferUnregister(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER); + return status; + } + + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferClient = hClient; + pKernelGmmu->mmuFaultBuffer[GPU_GFID_PF].hFaultBufferObject = hObject; + + pKernelGmmu->setProperty(pKernelGmmu, + PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE, + NV_TRUE); + + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdInternalGmmuRegisterFaultBuffer_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + + NV_PRINTF(LEVEL_INFO, "GMMU_REGISTER_FAULT_BUFFER\n"); + return kgmmuFaultBufferReplayableSetup(pGpu, pKernelGmmu, + pParams->hClient, + pParams->hObject, + pParams->faultBufferSize, + pParams->faultBufferPteArray); +} + +NV_STATUS +subdeviceCtrlCmdInternalGmmuUnregisterFaultBuffer_IMPL +( + Subdevice *pSubdevice +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + NV_STATUS status; + + NV_PRINTF(LEVEL_INFO, "GMMU_UNREGISTER_FAULT_BUFFER\n"); + status = kgmmuFaultBufferReplayableDestroy(pGpu, pKernelGmmu); + if (status == NV_OK) + { + pKernelGmmu->setProperty(pKernelGmmu, + PDB_PROP_KGMMU_REPLAYABLE_FAULT_BUFFER_IN_USE, + NV_FALSE); + } + return status; +} diff --git a/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c b/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c index a42f8c6340..28f1bfeb34 100644 --- a/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c +++ b/src/nvidia/src/kernel/gpu/mmu/vidmem_access_bit_buffer_v2.c @@ -24,7 +24,6 @@ #include "core/core.h" #include "os/os.h" #include "gpu/mmu/vidmem_access_bit_buffer.h" -#include "gpu/device/device.h" #include "gpu/gpu.h" NV_STATUS @@ -37,4 +36,4 @@ vidmemAccessBitBufConstructHelper_KERNEL { OBJGPU *pGpu = GPU_RES_GET_GPU(pVidmemAccessBitBuffer); return IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu)? NV_OK : NV_ERR_NOT_SUPPORTED; -} \ No newline at end of file +} diff --git a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_ctx.c b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_ctx.c index b0ec21757a..f8a662596a 100644 --- a/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_ctx.c +++ b/src/nvidia/src/kernel/gpu/nvdec/kernel_nvdec_ctx.c @@ -21,11 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ -#include "os/os.h" +#include "kernel/gpu/device/device.h" #include "kernel/gpu/falcon/kernel_falcon.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/nvdec/kernel_nvdec_ctx.h" +#include "os/os.h" +#include "vgpu/sdk-structures.h" + +#include "ctrl/ctrl0080/ctrl0080bsp.h" NV_STATUS nvdecctxConstructHal_KERNEL @@ -40,6 +44,9 @@ nvdecctxConstructHal_KERNEL KernelFalcon *pKernelFalcon = kflcnGetKernelFalconForEngine(pGpu, pChannelDescendant->resourceDesc.engDesc); KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; + if (pKernelFalcon == NULL) + return NV_ERR_INVALID_STATE; + NV_PRINTF(LEVEL_INFO, "nvdecctxConstruct for 0x%x\n", pChannelDescendant->resourceDesc.engDesc); return kflcnAllocContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant)); @@ -59,3 +66,29 @@ void nvdecctxDestructHal_KERNEL NV_ASSERT_OK(kflcnFreeContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant))); } + +NV_STATUS deviceCtrlCmdBspGetCapsV2_VF +( + Device *pDevice, + NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2 *pBspCapParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + // Sanity check for correct instance Id of NVDEC + if (pBspCapParams->instanceId >= GPU_MAX_NVDECS) + { + NV_PRINTF(LEVEL_ERROR, + "Requested NVDEC Id 0x%x is not present. Hence, returning capabilities of NVDEC0\n", + pBspCapParams->instanceId); + // Set default instance Id to zero if it's not set already. + pBspCapParams->instanceId = 0; + } + + portMemCopy(pBspCapParams->capsTbl, sizeof(pBspCapParams->capsTbl), + pVSI->vgpuBspCaps[pBspCapParams->instanceId].capsTbl, + NV0080_CTRL_BSP_CAPS_TBL_SIZE); + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_ctx.c b/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_ctx.c index 1bd8bc5389..d80ad30652 100644 --- a/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_ctx.c +++ b/src/nvidia/src/kernel/gpu/nvenc/kernel_nvenc_ctx.c @@ -21,11 +21,14 @@ * DEALINGS IN THE SOFTWARE. */ +#include "gpu/falcon/kernel_falcon.h" #include "gpu/nvenc/kernel_nvenc_ctx.h" #include "kernel/gpu/device/device.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "os/os.h" -#include "gpu/falcon/kernel_falcon.h" +#include "vgpu/sdk-structures.h" + +#include "ctrl/ctrl0080/ctrl0080msenc.h" NV_STATUS msencctxConstructHal_KERNEL @@ -40,6 +43,9 @@ msencctxConstructHal_KERNEL KernelFalcon *pKernelFalcon = kflcnGetKernelFalconForEngine(pGpu, pChannelDescendant->resourceDesc.engDesc); KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; + if (pKernelFalcon == NULL) + return NV_ERR_INVALID_STATE; + NV_PRINTF(LEVEL_INFO, "msencctxConstruct for 0x%x\n", pChannelDescendant->resourceDesc.engDesc); return kflcnAllocContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant)); @@ -60,45 +66,17 @@ void msencctxDestructHal_KERNEL NV_ASSERT_OK(kflcnFreeContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant))); } -// -// Query subdevice caps, and return caps for nvenc0 -// This version does not support SLI -// -NV_STATUS -deviceCtrlCmdMsencGetCaps_IMPL +NV_STATUS deviceCtrlCmdMsencGetCapsV2_VF ( Device *pDevice, - NV0080_CTRL_MSENC_GET_CAPS_PARAMS *pMsencCapsParams + NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS *pMsencCapsParams ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS params; - - // sanity check array size - if (pMsencCapsParams->capsTblSize != NV0080_CTRL_MSENC_CAPS_TBL_SIZE) - { - NV_PRINTF(LEVEL_ERROR, "size mismatch: client 0x%x rm 0x%x\n", - pMsencCapsParams->capsTblSize, - NV0080_CTRL_MSENC_CAPS_TBL_SIZE); - return NV_ERR_INVALID_ARGUMENT; - } - - ct_assert(NV0080_CTRL_MSENC_CAPS_TBL_SIZE == - sizeof(params.caps[0].capsTbl) / sizeof(*params.caps[0].capsTbl)); - - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_MSENC_GET_CAPS, - ¶ms, - sizeof(params))); - - NV_ASSERT_OR_RETURN(params.valid[0], NV_ERR_INVALID_STATE); - portMemCopy(pMsencCapsParams->capsTbl, - NV0080_CTRL_MSENC_CAPS_TBL_SIZE, - ¶ms.caps[0].capsTbl, - sizeof(params.caps[0].capsTbl)); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + portMemCopy(pMsencCapsParams, sizeof(*pMsencCapsParams), &pVSI->nvencCaps, + sizeof(pVSI->nvencCaps)); return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/nvenc/nvencsession.c b/src/nvidia/src/kernel/gpu/nvenc/nvencsession.c new file mode 100644 index 0000000000..2e5bd27708 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/nvenc/nvencsession.c @@ -0,0 +1,418 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" + +#include "os/os.h" +#include "gpu_mgr/gpu_mgr.h" +#include "virtualization/hypervisor/hypervisor.h" + +#include "vgpu/rpc.h" +#include "gpu/nvenc/nvencsession.h" +#include "rmapi/rs_utils.h" +#include "core/locks.h" + +static NvU32 sessionCounter = 0x01; + +static void _gpuNvEncSessionDataProcessingCallback(POBJGPU pGpu, void *data); + +NV_STATUS +nvencsessionConstruct_IMPL +( + NvencSession *pNvencSession, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NVA0BC_ALLOC_PARAMETERS *pNvA0BCAllocParams = pParams->pAllocParams; + NvHandle hNvencSessionHandle = pCallContext->pResourceRef->hResource; + PNVENC_SESSION_LIST_ITEM pNvencSessionListItem = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pNvencSession); + RsClient *pRsClient = pCallContext->pClient; + NvHandle hClient = pRsClient->hClient; + RmClient *pClient = dynamicCast(pRsClient, RmClient); + NV_STATUS status = NV_OK; + + if (listCount(&(pGpu->nvencSessionList)) >= NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES) + { + NV_PRINTF(LEVEL_WARNING, + "Creating NVENC session above max copyout limit.\n"); + } + + if (pClient == NULL) + { + return NV_ERR_INVALID_CLIENT; + } + + if (IS_VIRTUAL(pGpu)) + { + NV_RM_RPC_ALLOC_OBJECT(pGpu, + pParams->hClient, + pParams->hParent, + pParams->hResource, + pParams->externalClassId, + pNvA0BCAllocParams, + sizeof(*pNvA0BCAllocParams), + status); + + if (status != NV_OK) + { + return status; + } + } + + if (pNvA0BCAllocParams->version == NVA0BC_ALLOC_PARAMS_VER_1) + { + pNvencSession->version = NVA0BC_ALLOC_PARAMS_VER_1; + } + else + { + pNvencSession->version = NVA0BC_ALLOC_PARAMS_VER_0; + } + + if ((pNvencSession->version == NVA0BC_ALLOC_PARAMS_VER_1) && + (!hypervisorIsVgxHyper())) + { + status = memGetByHandle(pRsClient, pNvA0BCAllocParams->hMem, &(pNvencSession->pMemory)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Unable to find mem corresponding to handle : 0x%0x.\n", + pNvA0BCAllocParams->hMem); + pNvencSession->pMemory = NULL; + return status; + } + + status = memdescMap(pNvencSession->pMemory->pMemDesc, // Descriptor + 0, // Offset + NVENC_SESSION_INFO_SIZE_V1, // Length + NV_TRUE, // Kernel + NV_PROTECT_READABLE, // Protect + &(pNvencSession->pSessionStatsBuffer), // pAddress + &(pNvencSession->pPriv)); // pPriv + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Error mapping memory to CPU VA space, error : 0x%0x.\n", + status); + pNvencSession->pMemory = NULL; + return status; + } + } + else + { + pNvencSession->pMemory = NULL; + pNvencSession->pSessionStatsBuffer = NvP64_NULL; + pNvencSession->pPriv = NvP64_NULL; + } + + pNvencSessionListItem = listAppendNew(&(pGpu->nvencSessionList)); + + if (pNvencSessionListItem == NULL) + { + return NV_ERR_NO_MEMORY; + } + + portMemSet(pNvencSessionListItem, 0, sizeof(NVENC_SESSION_LIST_ITEM)); + + /* + * When this class is allocated for NMOS or vGPU VM, subProcessId is 0x00. + * However when allocated for host vGPU NVRM, processId represents plugin + * and subProcessId represent NVENC session process Id within that VM. + */ + + pNvencSession->handle = hNvencSessionHandle; + pNvencSession->nvencSessionEntry.sessionId = sessionCounter++; + pNvencSession->nvencSessionEntry.processId = pClient->ProcID; + pNvencSession->nvencSessionEntry.subProcessId = pClient->SubProcessID; + pNvencSession->nvencSessionEntry.codecType = pNvA0BCAllocParams->codecType; + pNvencSession->nvencSessionEntry.hResolution = pNvA0BCAllocParams->hResolution; + pNvencSession->nvencSessionEntry.vResolution = pNvA0BCAllocParams->vResolution; + pNvencSession->nvencSessionEntry.averageEncodeFps = 0; + pNvencSession->nvencSessionEntry.averageEncodeLatency = 0; + + pNvencSessionListItem->hClient = hClient; + pNvencSessionListItem->sessionPtr = pNvencSession; + + if ((pNvencSession->version == NVA0BC_ALLOC_PARAMS_VER_1) && + (!hypervisorIsVgxHyper()) && + (listCount(&(pGpu->nvencSessionList)) == 1)) + { + // Register 1Hz timer callback for this GPU. + status = osSchedule1HzCallback(pGpu, + _gpuNvEncSessionDataProcessingCallback, + NULL, + NV_OS_1HZ_REPEAT); + } + + return NV_OK; +} + +void +nvencsessionDestruct_IMPL +( + NvencSession *pNvencSession +) +{ + RS_RES_FREE_PARAMS_INTERNAL *pParams; + PNVENC_SESSION_LIST_ITEM pNvencSessionListItem; + PNVENC_SESSION_LIST_ITEM pNvencSessionListItemNext; + OBJGPU *pGpu = GPU_RES_GET_GPU(pNvencSession); + CALL_CONTEXT *pCallContext; + RsClient *pRsClient; + NvHandle hClient; + NvHandle hParent; + NvHandle hNvencSessionHandle; + NV_STATUS status = NV_OK; + + resGetFreeParams(staticCast(pNvencSession, RsResource), &pCallContext, &pParams); + + pRsClient = pCallContext->pClient; + hClient = pRsClient->hClient; + hParent = pCallContext->pResourceRef->pParentRef->hResource; + hNvencSessionHandle = pCallContext->pResourceRef->hResource; + + if (pNvencSession->pMemory) + { + memdescUnmap(pNvencSession->pMemory->pMemDesc, + NV_TRUE, + osGetCurrentProcess(), + pNvencSession->pSessionStatsBuffer, + pNvencSession->pPriv); + } + + if (IS_VIRTUAL(pGpu)) + { + NV_RM_RPC_FREE(pGpu, hClient, hParent, hNvencSessionHandle, status); + NV_ASSERT(NV_OK == status); + } + + for (pNvencSessionListItem = listHead(&(pGpu->nvencSessionList)); + pNvencSessionListItem != NULL; + pNvencSessionListItem = pNvencSessionListItemNext) + { + pNvencSessionListItemNext = listNext(&(pGpu->nvencSessionList), pNvencSessionListItem); + + if (pNvencSessionListItem != NULL && (pNvencSessionListItem->sessionPtr == pNvencSession)) + { + listRemove(&(pGpu->nvencSessionList), pNvencSessionListItem); + } + } + + if ((pNvencSession->version == NVA0BC_ALLOC_PARAMS_VER_1) && + (!hypervisorIsVgxHyper()) && + (listCount(&(pGpu->nvencSessionList)) == 0)) + { + // Stop 1Hz callback for this GPU. + osRemove1HzCallback(pGpu, _gpuNvEncSessionDataProcessingCallback, NULL); + } + + pParams->status = status; +} + +static void +_gpuNvEncSessionProcessBuffer(POBJGPU pGpu, NvencSession *pNvencSession) +{ + NvU32 frameCount; + NvU32 currIndex; + NvU32 latestFrameIndex; + NvU32 latestFrameId; + NvU64 latestFrameEndTS; + NvU64 processedFrameCount; + NvU64 timeTakenToEncodeNs; + NVENC_SESSION_INFO_V1 *pSessionInfoBuffer; + NVENC_SESSION_INFO_V1 *pLocalSessionInfoBuffer; + NVENC_SESSION_INFO_ENTRY_V1 *pSubmissionTSEntry; + NVENC_SESSION_INFO_ENTRY_V1 *pStartTSEntry; + NVENC_SESSION_INFO_ENTRY_V1 *pEndTSEntry; + NVENC_SESSION_INFO_REGION_1_ENTRY_V1 *pRegion1; + + pSessionInfoBuffer = (NVENC_SESSION_INFO_V1 *)NvP64_VALUE(pNvencSession->pSessionStatsBuffer); + if (pSessionInfoBuffer == NULL) + { + NV_PRINTF(LEVEL_INFO, "GPU : 0x%0x, NvEnc session stats buffer pointer is null.\n", pGpu->gpuId); + return; + } + + pLocalSessionInfoBuffer = portMemAllocNonPaged(sizeof(NVENC_SESSION_INFO_V1)); + if (pLocalSessionInfoBuffer == NULL) + { + NV_PRINTF(LEVEL_INFO, "GPU : 0x%0x, Failed to allocate memory for local stats buffer.\n", pGpu->gpuId); + return; + } + + // Reset local buffer. + portMemSet(pLocalSessionInfoBuffer, 0, sizeof(NVENC_SESSION_INFO_V1)); + + // Copy all the frame data from memory allocated by UMD to local buffer. + portMemCopy(pLocalSessionInfoBuffer, sizeof(NVENC_SESSION_INFO_V1), pSessionInfoBuffer, sizeof(NVENC_SESSION_INFO_V1)); + + pRegion1 = pLocalSessionInfoBuffer->region1.frameInfo; + + // Detect if UMD has not written all NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 entries. + // If yes, then pick the index next to last processed index from previous callback. + // If not, then we need to find lowest frame no from where we should start reading the timestamp data. + if (pRegion1[pNvencSession->lastProcessedIndex].submissionTSEntry.frameId == pNvencSession->lastProcessedFrameId) + { + currIndex = (pNvencSession->lastProcessedIndex + 1) % NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1; + } + else + { + NvU32 oldestIndex = NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1 - 1; + NvU32 minFrameId = pRegion1[oldestIndex].submissionTSEntry.frameId; + + while (oldestIndex > 0) + { + oldestIndex--; + if (minFrameId > pRegion1[oldestIndex].submissionTSEntry.frameId) + { + minFrameId = pRegion1[oldestIndex].submissionTSEntry.frameId; + } + else + { + oldestIndex++; + break; + } + } + currIndex = oldestIndex; + } + + timeTakenToEncodeNs = 0; + processedFrameCount = 0; + latestFrameIndex = currIndex; + if (pNvencSession->lastProcessedFrameTS == 0) + { + pNvencSession->lastProcessedFrameTS = pLocalSessionInfoBuffer->region2.frameInfo[currIndex].startTSEntry.timestamp; + } + + // Loop through all entries, find correct ones and use them for calculating average FPS and latency. + for (frameCount = 0; + frameCount < NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1; + frameCount++, (currIndex = (currIndex + 1) % NVENC_SESSION_INFO_REGION_1_MAX_ENTRIES_COUNT_V1)) + { + pSubmissionTSEntry = &(pLocalSessionInfoBuffer->region1.frameInfo[currIndex].submissionTSEntry); + pStartTSEntry = &(pLocalSessionInfoBuffer->region2.frameInfo[currIndex].startTSEntry); + pEndTSEntry = &(pLocalSessionInfoBuffer->region2.frameInfo[currIndex].endTSEntry); + + // Validation : Check if last processed frame id is less than current frame id. + if (pRegion1[latestFrameIndex].submissionTSEntry.frameId > pSubmissionTSEntry->frameId) + { + break; + } + + // Update latest processed frame index. + latestFrameIndex = currIndex; + + // Validation : Check if submission-start-end frame ids match. + if ((pSubmissionTSEntry->frameId != pStartTSEntry->frameId) || (pStartTSEntry->frameId != pEndTSEntry->frameId)) + { + continue; + } + // Validation : Check if submission-start-end timestamps are in incrementing order. + if ((pSubmissionTSEntry->timestamp > pStartTSEntry->timestamp) || (pStartTSEntry->timestamp > pEndTSEntry->timestamp)) + { + continue; + } + + // Add the difference of end timestamp and submission timestamp to total time taken. + timeTakenToEncodeNs += (pEndTSEntry->timestamp - pSubmissionTSEntry->timestamp); + processedFrameCount++; + } + + if (processedFrameCount > 0) + { + latestFrameId = pLocalSessionInfoBuffer->region1.frameInfo[latestFrameIndex].submissionTSEntry.frameId; + latestFrameEndTS = pLocalSessionInfoBuffer->region2.frameInfo[latestFrameIndex].endTSEntry.timestamp; + + // Calculate average latency. + timeTakenToEncodeNs /= processedFrameCount; + // averageEncodeLatency is in micro second. + pNvencSession->nvencSessionEntry.averageEncodeLatency = + ((timeTakenToEncodeNs / 1000) < 0xFFFFFFFF) ? (timeTakenToEncodeNs / 1000) : 0xFFFFFFFF; + + // Calculate average FPS. + // Find time difference between latest processed frame end TS and last processed frame end TS in last callback. + // Same is done for findng processed frame count. + // This would provide a better average FPS value. + timeTakenToEncodeNs = latestFrameEndTS - pNvencSession->lastProcessedFrameTS; + if (timeTakenToEncodeNs > 0) + { + processedFrameCount = latestFrameId - pNvencSession->lastProcessedFrameId; + pNvencSession->nvencSessionEntry.averageEncodeFps = ((processedFrameCount * 1000 * 1000 * 1000) / timeTakenToEncodeNs); + } + else + { + pNvencSession->nvencSessionEntry.averageEncodeLatency = 0; + pNvencSession->nvencSessionEntry.averageEncodeFps = 0; + } + + pNvencSession->lastProcessedIndex = latestFrameIndex; + pNvencSession->lastProcessedFrameId = latestFrameId; + pNvencSession->lastProcessedFrameTS = latestFrameEndTS; + } + else + { + pNvencSession->nvencSessionEntry.averageEncodeLatency = 0; + pNvencSession->nvencSessionEntry.averageEncodeFps = 0; + } + + portMemFree(pLocalSessionInfoBuffer); +} + +static void +_gpuNvEncSessionDataProcessingCallback(POBJGPU pGpu, void *data) +{ + PNVENC_SESSION_LIST_ITEM pNvencSessionListItem; + PNVENC_SESSION_LIST_ITEM pNvencSessionListItemNext; + NV_STATUS status = NV_OK; + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS rpcParams = {0}; + + // Loop through all sessions. + for (pNvencSessionListItem = listHead(&(pGpu->nvencSessionList)); + pNvencSessionListItem != NULL; + pNvencSessionListItem = pNvencSessionListItemNext) + { + pNvencSessionListItemNext = listNext(&(pGpu->nvencSessionList), pNvencSessionListItem); + if (pNvencSessionListItem != NULL && pNvencSessionListItem->sessionPtr) + { + _gpuNvEncSessionProcessBuffer(pGpu, pNvencSessionListItem->sessionPtr); + + if (IS_VIRTUAL(pGpu) && (pGpu->encSessionStatsReportingState == NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED)) + { + rpcParams.hResolution = pNvencSessionListItem->sessionPtr->nvencSessionEntry.hResolution; + rpcParams.vResolution = pNvencSessionListItem->sessionPtr->nvencSessionEntry.vResolution; + rpcParams.averageEncodeLatency = pNvencSessionListItem->sessionPtr->nvencSessionEntry.averageEncodeLatency; + rpcParams.averageEncodeFps = pNvencSessionListItem->sessionPtr->nvencSessionEntry.averageEncodeFps; + rpcParams.timestampBufferSize = 0; + + NV_RM_RPC_CONTROL(pGpu, + pNvencSessionListItem->hClient, + pNvencSessionListItem->sessionPtr->handle, + NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO, + &rpcParams, + sizeof(NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS), + status); + } + } + } +} diff --git a/src/nvidia/src/kernel/gpu/nvenc/nvencsessionctrl.c b/src/nvidia/src/kernel/gpu/nvenc/nvencsessionctrl.c new file mode 100644 index 0000000000..489324a6b6 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/nvenc/nvencsessionctrl.c @@ -0,0 +1,189 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2007-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "vgpu/rpc.h" +#include "os/os.h" +#include "rmapi/control.h" +#include "ctrl/ctrla0bc.h" +#include "gpu/nvenc/nvencsession.h" +#include "virtualization/hypervisor/hypervisor.h" + +NV_STATUS +_nvencsessionCtrlCmdNvencSwSessionUpdateInfo +( + OBJGPU *pGpu, + NvU32 hResolution, + NvU32 vResolution, + NvU32 averageEncodeLatency, + NvU32 averageEncodeFps, + NvU32 timeStampBufferSize, + NVA0BC_CTRL_NVENC_TIMESTAMP *timeStampBuffer, + NvencSession *pNvencSession +) +{ + NvU32 i, tempTimestampBufferSize; + NvU64 timeToEncodeBuffer = 0; + NV_STATUS status = NV_OK; + + NV_PRINTF(LEVEL_INFO, "\n"); + + pNvencSession->nvencSessionEntry.hResolution = hResolution; + pNvencSession->nvencSessionEntry.vResolution = vResolution; + + if (pNvencSession->version == NVA0BC_ALLOC_PARAMS_VER_0) + { + if (timeStampBufferSize != 0 && timeStampBuffer != NULL) + { + tempTimestampBufferSize = timeStampBufferSize; + + for (i = 0; i < tempTimestampBufferSize; i++) + { + if (timeStampBuffer[i].startTime > timeStampBuffer[i].endTime) + { + timeToEncodeBuffer += ((0xFFFFFFFFFFFFFFFFULL - timeStampBuffer[i].startTime ) + timeStampBuffer[i].endTime); + } + else + { + timeToEncodeBuffer += timeStampBuffer[i].endTime - timeStampBuffer[i].startTime; + } + } + + // Mask with 0xFFFFFFFF since it should not be greater than 32bit range. + pNvencSession->nvencSessionEntry.averageEncodeLatency = (timeToEncodeBuffer / tempTimestampBufferSize) & 0xFFFFFFFF; + + if (timeStampBuffer[tempTimestampBufferSize - 1].endTime > timeStampBuffer[0].startTime) + { + timeToEncodeBuffer = timeStampBuffer[tempTimestampBufferSize - 1].endTime - timeStampBuffer[0].startTime; + } + else + { + timeToEncodeBuffer = (0xFFFFFFFFFFFFFFFFULL - timeStampBuffer[0].startTime) + timeStampBuffer[tempTimestampBufferSize - 1].endTime; + } + + if (timeToEncodeBuffer) + { + pNvencSession->nvencSessionEntry.averageEncodeFps = ((tempTimestampBufferSize * 1000 * 1000) / timeToEncodeBuffer) & 0xFFFFFFFF; + } + } + else + { + pNvencSession->nvencSessionEntry.averageEncodeLatency = averageEncodeLatency; + pNvencSession->nvencSessionEntry.averageEncodeFps = averageEncodeFps; + } + + if (IS_VIRTUAL(pGpu) && + (pGpu->encSessionStatsReportingState == NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED)) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS rpcParams = {0}; + + rpcParams.hResolution = hResolution; + rpcParams.vResolution = vResolution; + rpcParams.averageEncodeLatency = pNvencSession->nvencSessionEntry.averageEncodeLatency; + rpcParams.averageEncodeFps = pNvencSession->nvencSessionEntry.averageEncodeFps; + rpcParams.timestampBufferSize = 0; + + NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, + &rpcParams, pRmCtrlParams->paramsSize, status); + } + } + else if (pNvencSession->version == NVA0BC_ALLOC_PARAMS_VER_1) + { + if (hypervisorIsVgxHyper()) + { + pNvencSession->nvencSessionEntry.averageEncodeLatency = averageEncodeLatency; + pNvencSession->nvencSessionEntry.averageEncodeFps = averageEncodeFps; + } + } + + return status; +} + +NV_STATUS +nvencsessionCtrlCmdNvencSwSessionUpdateInfo_IMPL +( + NvencSession *pNvencSession, + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS *pParams +) +{ + NVA0BC_CTRL_NVENC_TIMESTAMP *pTimeStampBuffer = NULL; + POBJGPU pGpu = GPU_RES_GET_GPU(pNvencSession); + NV_STATUS status = NV_OK; + + NV_PRINTF(LEVEL_INFO, "\n"); + + NV_ASSERT_OR_RETURN((pParams != NULL), NV_ERR_INVALID_POINTER); + if (pParams->timestampBufferSize > NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pNvencSession->version == NVA0BC_ALLOC_PARAMS_VER_0) + { + if (pParams->timestampBufferSize != 0) + { + pTimeStampBuffer = NvP64_VALUE(pParams->timestampBuffer); + } + } + + status = _nvencsessionCtrlCmdNvencSwSessionUpdateInfo(pGpu, pParams->hResolution, pParams->vResolution, pParams->averageEncodeLatency, pParams->averageEncodeFps, pParams->timestampBufferSize, pTimeStampBuffer, pNvencSession); + if (status != NV_OK) + return status; + + return status; +} + +NV_STATUS +nvencsessionCtrlCmdNvencSwSessionUpdateInfoV2_IMPL +( + NvencSession *pNvencSession, + NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_V2_PARAMS *pParams +) +{ + NVA0BC_CTRL_NVENC_TIMESTAMP *pTimeStampBuffer = NULL; + POBJGPU pGpu = GPU_RES_GET_GPU(pNvencSession); + NV_STATUS status = NV_OK; + + NV_PRINTF(LEVEL_INFO, "\n"); + + NV_ASSERT_OR_RETURN((pParams != NULL), NV_ERR_INVALID_POINTER); + if (pParams->timestampBufferSize > NVA0BC_CTRL_CMD_NVENC_MAX_BUFFER_ENTRIES) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (pNvencSession->version == NVA0BC_ALLOC_PARAMS_VER_0) + { + if (pParams->timestampBufferSize != 0) + { + pTimeStampBuffer = pParams->timestampBuffer; + } + } + + status = _nvencsessionCtrlCmdNvencSwSessionUpdateInfo(pGpu, pParams->hResolution, pParams->vResolution, pParams->averageEncodeLatency, pParams->averageEncodeFps, pParams->timestampBufferSize, pTimeStampBuffer, pNvencSession); + if (status != NV_OK) + return status; + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_ctx.c b/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_ctx.c index 1d28c41267..3088112d1e 100644 --- a/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_ctx.c +++ b/src/nvidia/src/kernel/gpu/nvjpg/kernel_nvjpg_ctx.c @@ -21,11 +21,15 @@ * DEALINGS IN THE SOFTWARE. */ -#include "os/os.h" +#include "kernel/gpu/device/device.h" #include "kernel/gpu/falcon/kernel_falcon.h" #include "kernel/gpu/fifo/kernel_channel.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/nvjpg/kernel_nvjpg_ctx.h" +#include "os/os.h" +#include "vgpu/sdk-structures.h" + +#include "ctrl/ctrl0080/ctrl0080nvjpg.h" NV_STATUS nvjpgctxConstructHal_KERNEL @@ -40,6 +44,9 @@ nvjpgctxConstructHal_KERNEL KernelFalcon *pKernelFalcon = kflcnGetKernelFalconForEngine(pGpu, pChannelDescendant->resourceDesc.engDesc); KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; + if (pKernelFalcon == NULL) + return NV_ERR_INVALID_STATE; + NV_PRINTF(LEVEL_INFO, "nvjpgctxConstruct for 0x%x\n", pChannelDescendant->resourceDesc.engDesc); return kflcnAllocContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant)); @@ -59,3 +66,18 @@ void nvjpgctxDestructHal_KERNEL NV_ASSERT_OK(kflcnFreeContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant))); } + +NV_STATUS deviceCtrlCmdNvjpgGetCapsV2_VF +( + Device *pDevice, + NV0080_CTRL_NVJPG_GET_CAPS_V2_PARAMS *pNvjpgCapsParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + portMemCopy(pNvjpgCapsParams->capsTbl, sizeof(pNvjpgCapsParams->capsTbl), + pVSI->jpegCaps, sizeof(pVSI->jpegCaps)); + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c index e8e5492e54..9247fb5494 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c @@ -32,6 +32,7 @@ #include "objtmr.h" #include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu_fabric_probe.h" +#include "platform/sli/sli.h" /*! * @brief Check if ALI is supported for the given device diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c index 330b6d1b2e..1c0b05c833 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_minion_gv100.c @@ -23,9 +23,6 @@ #define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED -// FIXME XXX -#define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED - #include "os/os.h" #include "nvRmReg.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" @@ -60,15 +57,17 @@ kioctrlMinionConstruct_GV100 "NVLink MINION is not supported on this platform, disabling.\n"); } + NvU32 minionControl = knvlinkGetMinionControl(pGpu, pKernelNvlink); + // Read in any MINION registry overrides. if (NV_OK == osReadRegistryDword(pGpu, - NV_REG_STR_RM_NVLINK_MINION_CONTROL, &pKernelNvlink->minionControl)) + NV_REG_STR_RM_NVLINK_MINION_CONTROL, &minionControl)) { NV_PRINTF(LEVEL_INFO, "%s: 0x%x\n", - NV_REG_STR_RM_NVLINK_MINION_CONTROL, pKernelNvlink->minionControl); + NV_REG_STR_RM_NVLINK_MINION_CONTROL, minionControl); // Select requested enable state - switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _ENABLE, pKernelNvlink->minionControl)) + switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _ENABLE, minionControl)) { case NV_REG_STR_RM_NVLINK_MINION_CONTROL_ENABLE_FORCE_ON: NV_PRINTF(LEVEL_INFO, @@ -85,7 +84,7 @@ kioctrlMinionConstruct_GV100 break; } - switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _CACHE_SEEDS, pKernelNvlink->minionControl)) + switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _CACHE_SEEDS, minionControl)) { case NV_REG_STR_RM_NVLINK_MINION_CONTROL_CACHE_SEEDS_ENABLE: { @@ -103,7 +102,7 @@ kioctrlMinionConstruct_GV100 } } - switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _ALI_TRAINING, pKernelNvlink->minionControl)) + switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _ALI_TRAINING, minionControl)) { case NV_REG_STR_RM_NVLINK_MINION_CONTROL_ALI_TRAINING_ENABLE: { @@ -129,7 +128,7 @@ kioctrlMinionConstruct_GV100 } } - switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _GFW_BOOT_DISABLE, pKernelNvlink->minionControl)) + switch (DRF_VAL(_REG_STR_RM, _NVLINK_MINION_CONTROL, _GFW_BOOT_DISABLE, minionControl)) { case NV_REG_STR_RM_NVLINK_MINION_CONTROL_GFW_BOOT_DISABLE_DISABLE: { diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c index c5213a9a46..fdf8131b88 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/volta/kernel_nvlink_gv100.c @@ -29,6 +29,7 @@ #include "kernel/gpu/mmu/kern_gmmu.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "core/thread_state.h" +#include "platform/sli/sli.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_mgr.h" diff --git a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c index eb5e88eb5c..a317c7bd0d 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c @@ -203,23 +203,6 @@ nvlinkCtrlCmdBusGetNvlinkCaps KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bMIGNvLinkP2PSupported = ((pKernelMIGManager != NULL) && kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); - // - // vGPU: - // - // Since vGPU does all real hardware management in the - // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), - // do an RPC to the host to get blacklist information from host RM - // - if (IS_VIRTUAL(pGpu)) - { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - NV_STATUS status = NV_OK; - - NV_RM_RPC_CONTROL(pGpu, pRmCtrlParams->hClient, pRmCtrlParams->hObject, pRmCtrlParams->cmd, - pRmCtrlParams->pParams, pRmCtrlParams->paramsSize, status); - return status; - } // Initialize link masks to 0 pParams->enabledLinkMask = 0; @@ -633,6 +616,8 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL FOR_EACH_INDEX_IN_MASK(32, i, pParams->enabledLinkMask) { NV2080_CTRL_NVLINK_DEVICE_INFO *pDeviceInfo = &pParams->linkInfo[i].remoteDeviceInfo; + if (pDeviceInfo->deviceType == NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH) + continue; OBJGPU *pLoopGpu = gpumgrGetGpuFromUuid(pDeviceInfo->deviceUUID, DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY)); diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c index ca8e4349e9..c101c52045 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c @@ -28,14 +28,19 @@ #include "os/os.h" #include "core/hal.h" -#include "core/info_block.h" #include "core/locks.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mmu/kern_gmmu.h" #include "gpu/ce/kernel_ce.h" +#include "platform/sli/sli.h" +#include "gpu/gpu_fabric_probe.h" +#include "compute/imex_session_api.h" +#include "compute/fabric.h" +#include "mem_mgr/mem_multicast_fabric.h" /*! * @brief Is NVLINK topology forced? NVLink topology is considered @@ -608,66 +613,29 @@ knvlinkUpdateCurrentConfig_IMPL return status; } -/*! - * @brief Clients to register their callback functions for inband data - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelNvlink KernelNvlink pointer - * @param[in] params callback functions - */ -NV_STATUS -knvlinkRegisterInbandCallback_IMPL -( - OBJGPU *pGpu, - KernelNvlink *pKernelNvlink, - NVLINK_INBAND_MSG_CALLBACK *params -) +const static NVLINK_INBAND_MSG_CALLBACK nvlink_inband_callbacks[] = { - if (params->messageType >= NVLINK_INBAND_MSG_TYPE_MAX) { - NV_PRINTF(LEVEL_ERROR, "Wrong msgType. Not registering\n"); - return NV_ERR_INVALID_PARAMETER; - } + .messageType = NVLINK_INBAND_MSG_TYPE_GPU_PROBE_RSP, + .pCallback = gpuFabricProbeReceiveKernelCallback, + .wqItemFlags = OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW + }, - if (pKernelNvlink->inbandCallback[params->messageType].pCallback != NULL) { - NV_PRINTF(LEVEL_ERROR, "Callback has been already registered" - "for msgType %d\n", params->messageType); - return NV_ERR_IN_USE; - } - - pKernelNvlink->inbandCallback[params->messageType].pCallback = params->pCallback; - pKernelNvlink->inbandCallback[params->messageType].wqItemFlags = params->wqItemFlags; + .messageType = NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP, + .pCallback = memorymulticastfabricTeamSetupResponseCallback, + .wqItemFlags = OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW + }, - return NV_OK; -} - -/*! - * @brief Clients to unregister their callback functions for inband data - * - * @param[in] pGpu OBJGPU pointer - * @param[in] pKernelNvlink KernelNvlink pointer - * @param[in] msgType Inband Message type - */ -NV_STATUS -knvlinkUnregisterInbandCallback_IMPL -( - OBJGPU *pGpu, - KernelNvlink *pKernelNvlink, - NvU16 msgType -) -{ - if (msgType >= NVLINK_INBAND_MSG_TYPE_MAX) { - NV_PRINTF(LEVEL_ERROR, "Wrong msgType. Not unregistering\n"); - return NV_ERR_INVALID_PARAMETER; + .messageType = NVLINK_INBAND_MSG_TYPE_GPU_PROBE_UPDATE_REQ, + .pCallback = gpuFabricProbeReceiveUpdateKernelCallback, + .wqItemFlags = OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW } - - pKernelNvlink->inbandCallback[msgType].pCallback = NULL; - pKernelNvlink->inbandCallback[msgType].wqItemFlags = 0; - - return NV_OK; -} +}; void knvlinkInbandMsgCallbackDispatcher_WORKITEM @@ -676,29 +644,26 @@ knvlinkInbandMsgCallbackDispatcher_WORKITEM void *pData ) { - OBJGPU *pGpu = NULL; nvlink_inband_msg_header_t *pHeader; - KernelNvlink *pKernelNvlink; NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pMessage = pData; - NvU8 *pRsvd = NULL; + NvU8 i; + const NVLINK_INBAND_MSG_CALLBACK *pCb = NULL; - pGpu = gpumgrGetGpu(gpuInstance); - if (pGpu == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Invalid GPU\n"); - return; - } + // Dispatcher may not be called under GPU lock, so don't access pGpu. - pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - if (pKernelNvlink == NULL) + pHeader = (nvlink_inband_msg_header_t *)pMessage->data; + + for (i = 0; i < NV_ARRAY_ELEMENTS(nvlink_inband_callbacks); i++) { - NV_PRINTF(LEVEL_ERROR, "Invalid NVLink state\n"); - return; + if ((nvlink_inband_callbacks[i].messageType == pHeader->type) && + (nvlink_inband_callbacks[i].pCallback != NULL)) + { + pCb = &nvlink_inband_callbacks[i]; + break; + } } - pHeader = (nvlink_inband_msg_header_t *)pMessage->data; - - if (pKernelNvlink->inbandCallback[pHeader->type].pCallback == NULL) + if (pCb == NULL) { NV_PRINTF(LEVEL_ERROR, "No Callback Registered for type %d. Dropping the msg\n", @@ -706,12 +671,18 @@ knvlinkInbandMsgCallbackDispatcher_WORKITEM return; } - // Assert reserved in msgHdr are zero - pRsvd = &pHeader->reserved[0]; - NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, - sizeof(pHeader->reserved) - 1) == 0); +#if defined(DEBUG) || defined(DEVELOP) + { + NvU8 *pRsvd = NULL; + + // Assert reserved in msgHdr are zero + pRsvd = &pHeader->reserved[0]; + NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, + sizeof(pHeader->reserved) - 1) == 0); + } +#endif - (void)pKernelNvlink->inbandCallback[pHeader->type].pCallback(gpuInstance, pData); + (void)pCb->pCallback(gpuInstance, NULL, pData); } NV_STATUS @@ -725,8 +696,9 @@ knvlinkInbandMsgCallbackDispatcher_IMPL { NV_STATUS status; nvlink_inband_msg_header_t *pHeader; - NVLINK_INBAND_MSG_CALLBACK *pParams; NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pData = NULL; + const NVLINK_INBAND_MSG_CALLBACK *pCb = NULL; + NvU8 i; pHeader = (nvlink_inband_msg_header_t *)pMessage; @@ -736,10 +708,21 @@ knvlinkInbandMsgCallbackDispatcher_IMPL return NV_ERR_INVALID_REQUEST; } - pParams = &pKernelNvlink->inbandCallback[pHeader->type]; - if (pParams->pCallback == NULL) + for (i = 0; i < NV_ARRAY_ELEMENTS(nvlink_inband_callbacks); i++) { - NV_PRINTF(LEVEL_ERROR, "Callback not registered for the message type %d\n", pHeader->type); + if ((nvlink_inband_callbacks[i].messageType == pHeader->type) && + (nvlink_inband_callbacks[i].pCallback != NULL)) + { + pCb = &nvlink_inband_callbacks[i]; + break; + } + } + + if (pCb == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "No Callback Registered for type %d. Dropping the msg\n", + pHeader->type); return NV_ERR_INVALID_REQUEST; } @@ -754,7 +737,7 @@ knvlinkInbandMsgCallbackDispatcher_IMPL portMemCopy(pData->data, pData->dataSize, pMessage, dataSize); status = osQueueWorkItemWithFlags(pGpu, knvlinkInbandMsgCallbackDispatcher_WORKITEM, pData, - pParams->wqItemFlags); + pCb->wqItemFlags); if (status != NV_OK) { portMemFree(pData); @@ -1248,7 +1231,7 @@ knvlinkSetPowerFeatures_IMPL case NVLINK_VERSION_22: { // NVLink L2 is supported only on MODS and Windows LDDM - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || RMCFG_FEATURE_MODS_FEATURES) + if (RMCFG_FEATURE_PLATFORM_WINDOWS || RMCFG_FEATURE_MODS_FEATURES) { pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_L2_POWER_STATE_ENABLED, (pKernelNvlink->bDisableL2Mode ? NV_FALSE : NV_TRUE)); @@ -2058,6 +2041,34 @@ knvlinkProcessInitDisabledLinks_IMPL return NV_OK; } +void +knvlinkFatalErrorRecovery_WORKITEM +( + NvU32 gpuInstance, + void *pArgs +) +{ + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + rcAndDisableOutstandingClientsWithImportedMemory(pGpu, NV_FABRIC_INVALID_NODE_ID); +} + +NV_STATUS +knvlinkFatalErrorRecovery_IMPL +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink +) +{ + NV_STATUS status; + + status = osQueueWorkItemWithFlags(pGpu, knvlinkFatalErrorRecovery_WORKITEM, NULL, + (OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA | + OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW | + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW)); + + return status; +} + // Grab GPU locks before RPCing into GSP-RM for NVLink RPCs NV_STATUS knvlinkExecGspRmRpc_IMPL diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c index 5a031f8b8d..57b574a17e 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkapi.c @@ -25,7 +25,6 @@ #include "os/os.h" #include "core/hal.h" -#include "core/info_block.h" #include "core/locks.h" #include "gpu/gpu.h" #include "gpu/subdevice/subdevice.h" diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c index 992169bf5d..5606fc31fa 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelib.c @@ -25,8 +25,8 @@ #include "os/os.h" #include "core/hal.h" -#include "core/info_block.h" #include "core/locks.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c index 262a02ae33..3a6d5683a4 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibcallback.c @@ -23,14 +23,11 @@ #define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED -// FIXME XXX -#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED - #include "os/os.h" #include "core/hal.h" -#include "core/info_block.h" #include "core/locks.h" #include "core/thread_state.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" @@ -1494,6 +1491,16 @@ knvlinkCoreTrainingCompleteCallback } } +NvlStatus +knvlinkCoreGetCciLinkModeCallback +( + nvlink_link *link, + NvU64 *mode +) +{ + return NVL_SUCCESS; +} + /* * @brief nvlinkCoreGetUphyLoadCallback send ALI training on the specified link * diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c index 611fe5cbaa..669a7a287c 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c @@ -25,10 +25,11 @@ #include "os/os.h" #include "core/hal.h" -#include "core/info_block.h" #include "core/locks.h" #include "core/thread_state.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" +#include "platform/sli/sli.h" #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" @@ -1680,7 +1681,7 @@ _knvlinkActivateDiscoveredP2pConn { pGpu1 = gpumgrGetGpu(gpuInst); - if (pGpu1 && + if (pGpu1 && (gpuIsStateLoaded(pGpu1) || gpuIsStateLoading(pGpu1)) && // Just rely on PCIe DBDF values for detecting the remote (pKernelNvlink0->nvlinkLinks[linkId].remoteEndInfo.domain == gpuGetDomain(pGpu1)) && (pKernelNvlink0->nvlinkLinks[linkId].remoteEndInfo.bus == gpuGetBus(pGpu1)) && @@ -2267,6 +2268,11 @@ _knvlinkUpdateSwitchLinkMasks continue; } + if (!(gpuIsStateLoaded(pGpu1) || gpuIsStateLoading(pGpu1))) + { + continue; + } + pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); if (!pKernelNvlink1) @@ -2341,6 +2347,11 @@ _knvlinkUpdateSwitchLinkMasksGpuDegraded continue; } + if (!(gpuIsStateLoaded(pGpu1) || gpuIsStateLoading(pGpu1))) + { + continue; + } + pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); if (!pKernelNvlink1) diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c index e3945c4ed4..f3c0437d45 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c @@ -23,9 +23,6 @@ #define NVOC_KERNEL_NVLINK_H_PRIVATE_ACCESS_ALLOWED -// FIXME XXX -#define NVOC_KERNEL_IOCTRL_H_PRIVATE_ACCESS_ALLOWED - #include "kernel/gpu/nvlink/kernel_nvlink.h" #include "kernel/gpu/nvlink/kernel_ioctrl.h" #include "kernel/gpu/mem_sys/kern_mem_sys.h" @@ -135,13 +132,15 @@ _knvlinkFilterIoctrls continue; } - pKernelIoctrl->localDiscoveredLinks &= - KIOCTRL_LINK_GLOBAL_TO_LOCAL_MASK(pKernelNvlink->discoveredLinks); + NvU32 localDiscoveredLinks = kioctrlGetLocalDiscoveredLinks(pGpu, pKernelIoctrl); + + localDiscoveredLinks &= + kioctrlGetGlobalToLocalMask(pGpu, pKernelIoctrl, pKernelNvlink->discoveredLinks); // No need to handle the IOCTRL if no links are being enabled - if (pKernelIoctrl->localDiscoveredLinks == 0x0) + if (localDiscoveredLinks == 0x0) { - pKernelNvlink->ioctrlMask &= ~(NVBIT(pKernelIoctrl->PublicId)); + pKernelNvlink->ioctrlMask &= ~(NVBIT(kioctrlGetPublicId(pGpu, pKernelIoctrl))); } } FOR_EACH_INDEX_IN_MASK_END; @@ -253,8 +252,8 @@ knvlinkIsPresent_IMPL { NV_STATUS status = NV_OK; - // Mark NVLINK as absent when HCC is enabled - if (gpuIsCCFeatureEnabled(pGpu)) + // Mark NVLINK as absent when HCC SPT is enabled + if (gpuIsCCFeatureEnabled(pGpu) && !gpuIsCCMultiGpuProtectedPcieModeEnabled(pGpu)) return NV_FALSE; // On GSP clients, retrieve all device discovery info from GSP through RPC @@ -770,7 +769,10 @@ knvlinkStatePostLoad_IMPL gpuInstance = 0; while ((pRemoteGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) { - knvlinkTrainP2pLinksToActive(pGpu, pRemoteGpu, pKernelNvlink); + if (gpuIsStateLoaded(pRemoteGpu) || gpuIsStateLoading(pRemoteGpu)) + { + knvlinkTrainP2pLinksToActive(pGpu, pRemoteGpu, pKernelNvlink); + } } } } diff --git a/src/nvidia/src/kernel/gpu/ofa/kernel_ofa_ctx.c b/src/nvidia/src/kernel/gpu/ofa/kernel_ofa_ctx.c index 12981c12d4..e3cb23be17 100644 --- a/src/nvidia/src/kernel/gpu/ofa/kernel_ofa_ctx.c +++ b/src/nvidia/src/kernel/gpu/ofa/kernel_ofa_ctx.c @@ -39,6 +39,9 @@ ofactxConstructHal_KERNEL KernelFalcon *pKernelFalcon = kflcnGetKernelFalconForEngine(pGpu, pChannelDescendant->resourceDesc.engDesc); KernelChannel *pKernelChannel = pChannelDescendant->pKernelChannel; + if (pKernelFalcon == NULL) + return NV_ERR_GENERIC; + NV_PRINTF(LEVEL_INFO, "ofactxConstruct for 0x%x\n", pChannelDescendant->resourceDesc.engDesc); return kflcnAllocContext(pGpu, pKernelFalcon, pKernelChannel, RES_GET_EXT_CLASS_ID(pChannelDescendant)); diff --git a/src/nvidia/src/kernel/gpu/perf/kern_cuda_limit.c b/src/nvidia/src/kernel/gpu/perf/kern_cuda_limit.c index 88ade0b851..8a607aa469 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_cuda_limit.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_cuda_limit.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -24,6 +24,7 @@ /*! * @brief All functions related to the Cuda Safe feature. */ +#include "gpu/device/device.h" #include "gpu/perf/kern_cuda_limit.h" #include "rmapi/rmapi.h" #include "gpu/gpu.h" @@ -53,6 +54,11 @@ deviceKPerfCudaLimitCliDisable RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); NV_STATUS status = NV_OK; + if (IS_VIRTUAL(pGpu)) + { + return NV_OK; + } + if (pDevice->nCudaLimitRefCnt > 0) { status = pRmApi->Control(pRmApi, @@ -98,6 +104,10 @@ deviceCtrlCmdKPerfCudaLimitSetControl_IMPL NvBool bCudaLimitAfter; NV_STATUS status = NV_OK; + if (IS_VIRTUAL(pGpu)) + { + return NV_OK; + } // Obtain current Cuda limit activation setting. NV_ASSERT_OK_OR_RETURN(kperfCudaLimitCliGet(pDevice, &bCudaLimitBefore)); diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c index 8d1f0ff69d..b8a51c5ee2 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_boost.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -52,7 +52,7 @@ subdeviceCtrlCmdKPerfBoost_IMPL NV_CHECK_OR_RETURN(LEVEL_INFO, (pKernelPerf != NULL), NV_ERR_NOT_SUPPORTED); - status = kperfBoostSet_HAL(pKernelPerf, pSubdevice, pBoostParams); + status = kperfBoostSet(pKernelPerf, pSubdevice, pBoostParams); return status; } @@ -60,7 +60,7 @@ subdeviceCtrlCmdKPerfBoost_IMPL * @copydoc kperfBoostSet */ NV_STATUS -kperfBoostSet_3x +kperfBoostSet_IMPL ( KernelPerf *pKernelPerf, Subdevice *pSubdevice, diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_ctrl.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_ctrl.c new file mode 100644 index 0000000000..52bb4f984e --- /dev/null +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_ctrl.c @@ -0,0 +1,287 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* ------------------------ Includes --------------------------------------- */ +#include "ctrl/ctrl2080/ctrl2080clk.h" +#include "ctrl/ctrl2080/ctrl2080perf.h" +#include "os/os.h" +#include "gpu/subdevice/subdevice.h" +#include "rmapi/rmapi.h" +#include "rmapi/rs_utils.h" +#include "vgpu/rpc.h" +#include "gpu/gpu.h" + +/* ------------------------ Global Variables ------------------------------- */ +/* ------------------------ Static Function Prototypes --------------------- */ +/* ------------------------ Macros ----------------------------------------- */ +/* ------------------------ Public Functions ------------------------------- */ +/*! + * @copydoc NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES + * + * @params[in] pSubdevice + * @params[in/out] pParams + * + * @return NV_OK + * + * @return Other error + * Encountered un-expected error. + */ +NV_STATUS +subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamples_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_PARAM *pParams +) +{ + NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE *pSamples = NvP64_VALUE(pParams->pSamples); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvU32 bufSize = pParams->bufSize; + NV_STATUS status = NV_OK; + + if (IS_MIG_ENABLED(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Call not supported with SMC Enabled\n"); + return NV_ERR_NOT_SUPPORTED; + } + + NV_ASSERT_OR_RETURN(pSamples != NULL, NV_ERR_INVALID_ARGUMENT); + + NV_RM_RPC_GET_ENGINE_UTILIZATION(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pSamples, + bufSize, + status); + + return status; +} + +/*! + * @copydoc NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2 + * + * @params[in] pSubdevice + * @params[in/out] pParams + * + * @return NV_OK + * + * @return Other error + * Encountered un-expected error. + */ +NV_STATUS +subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS *pParams +) +{ + + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NV_STATUS status = NV_OK; + + if (IS_MIG_ENABLED(pGpu)) + { + NV_PRINTF(LEVEL_INFO, "Call not supported with SMC Enabled\n"); + return NV_ERR_NOT_SUPPORTED; + } + + if (pParams->bufSize != NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_BUFFER_SIZE) + return NV_ERR_INVALID_ARGUMENT; + + NV_RM_RPC_GET_ENGINE_UTILIZATION(pRmCtrlParams->pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pParams->samples, + pParams->bufSize, + status); + + return status; +} + +/* + * We are using the V1 structure here so as to use the old + * RPC call, without changing function signature of RPC + * (since it still uses V1 structure). Allocated, used and + * freed only if vGPU is in effect. + * + * The old structure's pointer, where normally would point + * to some userspace buffer, now points to the V2 structure's + * static array. + * + * V1 structure is allocated from heap rather than on + * stack out of concern for limits on kernel stack usage. + * (3 pages on Windows) + */ +NV_STATUS +subdeviceCtrlCmdPerfGetLevelInfo_V2_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_PERF_GET_LEVEL_INFO_V2_PARAMS *pLevelInfoParams +) +{ + NV2080_CTRL_PERF_GET_CLK_INFO *pPerfClkInfos = (NV2080_CTRL_PERF_GET_CLK_INFO *) + &(pLevelInfoParams->perfGetClkInfoList); + NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS *pOldLevelInfoParams = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NV_STATUS status = NV_OK; + NvHandle hObject = RES_GET_HANDLE(pSubdevice); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + + // get flags for the level + pLevelInfoParams->flags = 0; + + pOldLevelInfoParams = portMemAllocNonPaged(sizeof(NV2080_CTRL_PERF_GET_LEVEL_INFO_PARAMS)); + if (pOldLevelInfoParams == NULL) + { + return NV_ERR_NO_MEMORY; + } + + pOldLevelInfoParams->level = pLevelInfoParams->level; + pOldLevelInfoParams->flags = pLevelInfoParams->flags; + pOldLevelInfoParams->perfGetClkInfoListSize = pLevelInfoParams->perfGetClkInfoListSize; + pOldLevelInfoParams->perfGetClkInfoList = NV_PTR_TO_NvP64(&(pLevelInfoParams->perfGetClkInfoList)); + + NV_RM_RPC_PERF_GET_LEVEL_INFO(pGpu, + hClient, + hObject, + pOldLevelInfoParams, + pPerfClkInfos, + status); + + pLevelInfoParams->level = pOldLevelInfoParams->level; + pLevelInfoParams->flags = pOldLevelInfoParams->flags; + pLevelInfoParams->perfGetClkInfoListSize = pOldLevelInfoParams->perfGetClkInfoListSize; + portMemFree(pOldLevelInfoParams); + + return status; +} + +/*! + * @copydoc NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE + * + * @params[in] pSubdevice + * @params[in/out] pParams + * + * @return NV_OK + * + * @return Other error + * Encountered un-expected error. + */ +NV_STATUS +subdeviceCtrlCmdPerfGetVideoEnginePerfmonSample_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS *pSampleParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + NV_STATUS status = NV_OK; + + if (IS_MIG_ENABLED(pGpu)) + { + NV_PRINTF(LEVEL_ERROR, "Call not supported with SMC Enabled\n"); + return NV_ERR_NOT_SUPPORTED; + } + + // + // Skipping the VID_ENG_NVJPG and VID_ENG_NVOFA engine calls for vGPU Guest. + // Support to be added via. bug 4020549 + // + if ((pSampleParams->engineType == NV2080_CTRL_CMD_PERF_VID_ENG_NVJPG) || + (pSampleParams->engineType == NV2080_CTRL_CMD_PERF_VID_ENG_NVOFA)) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_RM_RPC_GET_ENGINE_UTILIZATION(pRmCtrlParams->pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pSampleParams, + sizeof(NV2080_CTRL_PERF_GET_VID_ENG_PERFMON_SAMPLE_PARAMS), + status); + + return status; +} + +/*! + * @copydoc NV2080_CTRL_CMD_PERF_GET_POWERSTATE + * + * @params[in] pSubdevice + * @params[out] pParams + * + * @return NV_OK + * + * @return Other error + * Encountered un-expected error. + */ +NV_STATUS +subdeviceCtrlCmdPerfGetPowerstate_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_PERF_GET_POWERSTATE_PARAMS *powerInfoParams +) +{ + NV_STATUS status = NV_OK; + + // + // vGPU: + // + // We need to set the power state value to AC as we do not initialize perf engine for guest. + // Return the power state from guest RM instead of RPC call. + // + powerInfoParams->powerStateInfo.powerState = NV2080_CTRL_PERF_POWER_SOURCE_AC; + + return status; +} + +/*! + * @copydoc NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE + * + * @params[in] pSubdevice + * @params[out] pParams + * + * @return NV_OK + * + * @return Other error + * Encountered un-expected error. + */ +NV_STATUS +subdeviceCtrlCmdPerfGetCurrentPstate_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_PERF_GET_CURRENT_PSTATE_PARAMS *pInfoParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + return RmRpcPerfGetCurrentPstate(pGpu, pInfoParams); +} +/* ------------------------- Private Functions ------------------------------ */ diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c index 2c919b4d66..79ca39e5fb 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_gpuboostsync.c @@ -21,10 +21,12 @@ * DEALINGS IN THE SOFTWARE. */ +#include "gpu/device/device.h" #include "gpu/perf/kern_perf.h" #include "core/locks.h" #include "vgpu/rpc.h" #include "nvRmReg.h" +#include "platform/sli/sli.h" /* ------------------------ Macros ----------------------------------------- */ /* ------------------------ Public Class Interfaces ------------------------ */ diff --git a/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c b/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c index da022fde8b..18110094b0 100644 --- a/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c +++ b/src/nvidia/src/kernel/gpu/perf/kern_perf_pm.c @@ -26,6 +26,7 @@ #include "gpu/subdevice/subdevice.h" #include "rmapi/rmapi.h" #include "rmapi/rs_utils.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/perf/kern_perf_pm.h" diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c index f852184e4a..ede69454c6 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc.c @@ -23,6 +23,7 @@ #include "kernel/gpu/rc/kernel_rc.h" +#include "kernel/core/locks.h" #include "kernel/core/system.h" #include "kernel/gpu/bif/kernel_bif.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" @@ -184,7 +185,7 @@ _krcInitRegistryOverrides { pKernelRc->watchdog.flags |= WATCHDOG_FLAGS_DISABLED; } - else if (gpuIsCCFeatureEnabled(pGpu) && !gpuIsCCDevToolsModeEnabled(pGpu)) + else if (gpuIsCCFeatureEnabled(pGpu)) { pKernelRc->watchdog.flags |= WATCHDOG_FLAGS_DISABLED; } @@ -303,7 +304,10 @@ krcReportXid_IMPL // Get PID of channel creator if available, or get the current PID for // exception types that never have an associated channel // - if (pKernelChannel != NULL) + // Check for API lock since this can be called from parallel init + // path without API lock, and RES_GET_CLIENT requires API lock + // + if (rmapiLockIsOwner() && (pKernelChannel != NULL)) { RsClient *pClient = RES_GET_CLIENT(pKernelChannel); RmClient *pRmClient = dynamicCast(pClient, RmClient); diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c index 2ff2610882..4664b0b0d4 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c @@ -30,6 +30,7 @@ #include "kernel/gpu/rc/kernel_rc.h" #include "kernel/gpu/bif/kernel_bif.h" #include "kernel/os/os.h" +#include "platform/sli/sli.h" #include "class/cl0000.h" // NV01_NULL_OBJECT #include "class/cl0002.h" // NV01_CONTEXT_DMA @@ -53,7 +54,6 @@ #include "deprecated/rmapi_deprecated.h" #include "nvRmReg.h" - // // Watchdog object ids // @@ -108,7 +108,6 @@ #define SUBDEVICE_MASK_ALL DRF_MASK(NV906F_DMA_SET_SUBDEVICE_MASK_VALUE) - NV_STATUS krcWatchdogChangeState_IMPL ( @@ -392,9 +391,7 @@ krcWatchdogShutdown_IMPL return NV_OK; krcWatchdogDisable(pKernelRc); - osRemove1SecondRepeatingCallback(pGpu, - krcWatchdogTimerProc, - NULL /* pData */); + osRemove1HzCallback(pGpu, krcWatchdogTimerProc, NULL /* pData */); // This should free the client and all associated resources pRmApi->Free(pRmApi, @@ -403,7 +400,7 @@ krcWatchdogShutdown_IMPL // // Make sure to clear any old watchdog data this also clears - // WATCHDOG_FLAGS_INITIALIZED + // WATCHDOG_FLAGS_INITIALIZED, bHandleValid, and hClient // portMemSet(&pKernelRc->watchdog, 0, sizeof pKernelRc->watchdog); portMemSet(&pKernelRc->watchdogChannelInfo, 0, @@ -480,11 +477,23 @@ krcWatchdogInit_IMPL if (bClientUserd) { - Heap *pHeap = GPU_GET_HEAP(pGpu); - if (pHeap->pmaObject.bNuma) + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + if (memmgrIsPmaInitialized(pMemoryManager)) { - // PMA can't be used until it's onlined - bClientUserd = NV_FALSE; + Heap *pHeap = GPU_GET_HEAP(pGpu); + NvU32 pmaConfig = PMA_QUERY_NUMA_ENABLED | PMA_QUERY_NUMA_ONLINED; + + if (pmaQueryConfigs(&pHeap->pmaObject, &pmaConfig) == NV_OK) + { + // PMA can't be used until it's onlined + if (pmaConfig & PMA_QUERY_NUMA_ENABLED) + { + // PMA can't be used until it's onlined + if (!(pmaConfig & PMA_QUERY_NUMA_ONLINED)) + bClientUserd = NV_FALSE; + } + } } } @@ -520,6 +529,8 @@ krcWatchdogInit_IMPL status = NV_ERR_NO_MEMORY; goto error; } + pKernelRc->watchdog.hClient = hClient; + pKernelRc->watchdog.bHandleValid = NV_TRUE; } if (bAcquireLock) @@ -1165,10 +1176,10 @@ krcWatchdogInit_IMPL pKernelRc->watchdog.flags |= WATCHDOG_FLAGS_INITIALIZED; // Hook into the 1 Hz OS timer - osSchedule1SecondCallback(pGpu, - krcWatchdogTimerProc, - NULL /* pData */, - NV_OS_1HZ_REPEAT); + osSchedule1HzCallback(pGpu, + krcWatchdogTimerProc, + NULL /* pData */, + NV_OS_1HZ_REPEAT); // Schedule next interval to run immediately pKernelRc->watchdogPersistent.nextRunTime = 0; @@ -1179,6 +1190,7 @@ krcWatchdogInit_IMPL if (status != NV_OK) { pRmApi->Free(pRmApi, hClient, hClient); + pKernelRc->watchdog.bHandleValid = NV_FALSE; } portMemFree(pParams); @@ -1418,4 +1430,11 @@ krcWatchdogWriteNotifierToGpfifo_IMPL SLI_LOOP_END; } +NV_STATUS krcWatchdogGetClientHandle(KernelRc *pKernelRc, NvHandle *phClient) +{ + if (!pKernelRc->watchdog.bHandleValid) + return NV_ERR_INVALID_STATE; + *phClient = pKernelRc->watchdog.hClient; + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c index e503c6617f..aa5d203b86 100644 --- a/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c +++ b/src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog_callback.c @@ -29,6 +29,7 @@ #include "kernel/gpu/fifo/kernel_fifo.h" #include "kernel/gpu/gpu.h" #include "kernel/gpu_mgr/gpu_mgr.h" +#include "platform/sli/sli.h" #include "ctrl/ctrl906f.h" diff --git a/src/nvidia/src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga100.c b/src/nvidia/src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga100.c index ef346be1b6..9a19eeeae6 100644 --- a/src/nvidia/src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga100.c +++ b/src/nvidia/src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga100.c @@ -32,7 +32,7 @@ #include "published/ampere/ga100/dev_sec_pri.h" #include "published/ampere/ga100/dev_sec_addendum.h" -void +NV_STATUS ksec2ConfigureFalcon_GA100 ( OBJGPU *pGpu, @@ -55,6 +55,7 @@ ksec2ConfigureFalcon_GA100 falconConfig.addrSpaceList = memdescAddrSpaceListToU32(ADDRLIST_FBMEM_PREFERRED); kflcnConfigureEngine(pGpu, staticCast(pKernelSec2, KernelFalcon), &falconConfig); + return NV_OK; } /*! diff --git a/src/nvidia/src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga102.c b/src/nvidia/src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga102.c index 1a3268187e..3330dd6d95 100644 --- a/src/nvidia/src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga102.c +++ b/src/nvidia/src/kernel/gpu/sec2/arch/ampere/kernel_sec2_ga102.c @@ -32,7 +32,7 @@ #include "published/ampere/ga102/dev_sec_pri.h" #include "published/ampere/ga102/dev_sec_addendum.h" -void +NV_STATUS ksec2ConfigureFalcon_GA102 ( OBJGPU *pGpu, @@ -55,4 +55,5 @@ ksec2ConfigureFalcon_GA102 falconConfig.addrSpaceList = memdescAddrSpaceListToU32(ADDRLIST_FBMEM_PREFERRED); kflcnConfigureEngine(pGpu, staticCast(pKernelSec2, KernelFalcon), &falconConfig); + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c b/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c index 7d5d23458f..6b1d2b4e60 100644 --- a/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c +++ b/src/nvidia/src/kernel/gpu/sec2/arch/turing/kernel_sec2_tu102.c @@ -34,7 +34,7 @@ #include "rmflcnbl.h" -void +NV_STATUS ksec2ConfigureFalcon_TU102 ( OBJGPU *pGpu, @@ -57,6 +57,7 @@ ksec2ConfigureFalcon_TU102 falconConfig.addrSpaceList = memdescAddrSpaceListToU32(ADDRLIST_FBMEM_PREFERRED); kflcnConfigureEngine(pGpu, staticCast(pKernelSec2, KernelFalcon), &falconConfig); + return NV_OK; } NV_STATUS diff --git a/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c b/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c index e7269bd44a..94e948e269 100644 --- a/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c +++ b/src/nvidia/src/kernel/gpu/sec2/kernel_sec2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -38,8 +38,7 @@ ksec2ConstructEngine_IMPL ENGDESCRIPTOR engDesc ) { - ksec2ConfigureFalcon_HAL(pGpu, pKernelSec2); - return NV_OK; + return ksec2ConfigureFalcon_HAL(pGpu, pKernelSec2); } void @@ -92,4 +91,5 @@ ksec2ServiceNotificationInterrupt_IMPL // Wake up channels waiting on this event engineNonStallIntrNotify(pGpu, RM_ENGINE_TYPE_SEC2); return NV_OK; -} \ No newline at end of file +} + diff --git a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c index 34a09f1d2f..aa0d483b37 100644 --- a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c +++ b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_certs_gh100.c @@ -219,6 +219,51 @@ const static NvU8 SPDM_L3_CERTIFICATE_DER[686] = 0xe9, 0x59, 0x4b, 0x59, 0x36, 0x3f, 0x08, 0xcf, 0xab, 0x7a, 0xc8, 0xe3, 0xab, 0x14, }; +// +//TODO : Need to generate individual encapsulated certification chain. +// + +NvU8 SPDM_REQ_ENCAP_CERTIFICATE_DER[NV_SPDM_ENCAP_CERT_SIZE_IN_BYTE] = +{ + 0x30, 0x82, 0x02, 0x3e, 0x30, 0x82, 0x01, 0xc4, 0xa0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x09, 0x00, + 0xff, 0xe0, 0xbc, 0xe4, 0x95, 0xe5, 0x9e, 0xe2, 0x30, 0x0a, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, + 0x3d, 0x04, 0x03, 0x03, 0x30, 0x5d, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, + 0x02, 0x55, 0x53, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c, 0x02, 0x43, 0x41, + 0x31, 0x14, 0x30, 0x12, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0c, 0x0b, 0x53, 0x61, 0x6e, 0x74, 0x61, + 0x20, 0x43, 0x6c, 0x61, 0x72, 0x61, 0x31, 0x15, 0x30, 0x13, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, + 0x0c, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x43, 0x6f, 0x72, 0x70, 0x2e, 0x31, 0x14, 0x30, + 0x12, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x0b, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x43, + 0x6f, 0x72, 0x70, 0x30, 0x1e, 0x17, 0x0d, 0x32, 0x33, 0x30, 0x38, 0x32, 0x35, 0x32, 0x33, 0x31, + 0x33, 0x30, 0x32, 0x5a, 0x17, 0x0d, 0x32, 0x34, 0x30, 0x38, 0x31, 0x39, 0x32, 0x33, 0x31, 0x33, + 0x30, 0x32, 0x5a, 0x30, 0x5d, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02, + 0x55, 0x53, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c, 0x02, 0x43, 0x41, 0x31, + 0x14, 0x30, 0x12, 0x06, 0x03, 0x55, 0x04, 0x07, 0x0c, 0x0b, 0x53, 0x61, 0x6e, 0x74, 0x61, 0x20, + 0x43, 0x6c, 0x61, 0x72, 0x61, 0x31, 0x15, 0x30, 0x13, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x0c, + 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x43, 0x6f, 0x72, 0x70, 0x2e, 0x31, 0x14, 0x30, 0x12, + 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x0b, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0x20, 0x43, 0x6f, + 0x72, 0x70, 0x30, 0x76, 0x30, 0x10, 0x06, 0x07, 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, + 0x05, 0x2b, 0x81, 0x04, 0x00, 0x22, 0x03, 0x62, 0x00, 0x04, 0x70, 0x6b, 0x5a, 0x92, 0xed, 0x0a, + 0x9c, 0x5a, 0x55, 0xc0, 0x58, 0xf9, 0x81, 0x86, 0xa5, 0x64, 0x3f, 0x44, 0x00, 0xe2, 0x18, 0x4e, + 0x99, 0xc0, 0x4c, 0xd7, 0x31, 0x73, 0x24, 0x23, 0xf4, 0x0a, 0x39, 0x0e, 0x91, 0x52, 0x32, 0x2f, + 0x50, 0x58, 0xe9, 0xc0, 0x83, 0xf4, 0x6d, 0x3c, 0x93, 0x5c, 0x98, 0x18, 0x14, 0x47, 0xc1, 0x0d, + 0x27, 0xa8, 0x36, 0xe8, 0x06, 0xcb, 0xe5, 0x3d, 0x08, 0x85, 0x08, 0x1b, 0x52, 0xcf, 0xa3, 0x82, + 0x42, 0xe8, 0xa7, 0xe7, 0x8b, 0x28, 0x0c, 0xff, 0xb1, 0xc8, 0x8f, 0x55, 0x85, 0xdf, 0x28, 0x5a, + 0xf3, 0xfc, 0x58, 0xed, 0xa6, 0x7a, 0xec, 0x14, 0xff, 0xc8, 0xa3, 0x50, 0x30, 0x4e, 0x30, 0x1d, + 0x06, 0x03, 0x55, 0x1d, 0x0e, 0x04, 0x16, 0x04, 0x14, 0xa9, 0xa5, 0x22, 0xdc, 0x5d, 0xfa, 0x59, + 0xb0, 0xcb, 0x52, 0xad, 0xb1, 0xfa, 0x85, 0x29, 0x88, 0x57, 0xd8, 0xdb, 0x5a, 0x30, 0x1f, 0x06, + 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, 0x16, 0x80, 0x14, 0xa9, 0xa5, 0x22, 0xdc, 0x5d, 0xfa, + 0x59, 0xb0, 0xcb, 0x52, 0xad, 0xb1, 0xfa, 0x85, 0x29, 0x88, 0x57, 0xd8, 0xdb, 0x5a, 0x30, 0x0c, + 0x06, 0x03, 0x55, 0x1d, 0x13, 0x04, 0x05, 0x30, 0x03, 0x01, 0x01, 0xff, 0x30, 0x0a, 0x06, 0x08, + 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x04, 0x03, 0x03, 0x03, 0x68, 0x00, 0x30, 0x65, 0x02, 0x31, 0x00, + 0x84, 0x63, 0x87, 0x79, 0x88, 0x73, 0x70, 0xe9, 0x95, 0x15, 0x55, 0xd1, 0xc6, 0x51, 0x3c, 0xcf, + 0x76, 0x6a, 0x20, 0x60, 0xc4, 0x73, 0xe4, 0xb8, 0xc1, 0x98, 0xc8, 0xf5, 0x08, 0xea, 0x10, 0xe8, + 0xb5, 0xd4, 0x08, 0xda, 0x10, 0xfd, 0x17, 0x75, 0xc4, 0xf5, 0x90, 0xcf, 0x11, 0x5f, 0x53, 0x87, + 0x02, 0x30, 0x07, 0xed, 0x77, 0x63, 0xcf, 0xdd, 0xfb, 0x29, 0x3a, 0xec, 0xf3, 0x3b, 0x00, 0x8e, + 0xbc, 0xdf, 0x9c, 0xc3, 0x64, 0xab, 0x3c, 0x29, 0x7a, 0x32, 0x50, 0xd7, 0xb0, 0x78, 0x74, 0xe4, + 0xd1, 0xea, 0x43, 0xdb, 0xc8, 0x9d, 0xd0, 0xc2, 0xa5, 0x5e, 0x8f, 0x90, 0x4d, 0xb5, 0x1c, 0xe7, + 0xd2, 0x38 +}; + /* ------------------------ Static Functions ------------------------------- */ /*! @param pCert : The pointer to certification chain start @@ -654,9 +699,10 @@ spdmGetCertificates_GH100 return NV_ERR_INVALID_ARGUMENT; } - if (pSpdm->pLibspdmContext == NULL) + // Don't allow certificate retrieval after session is established. + if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId != INVALID_SESSION_ID) { - return NV_ERR_NOT_READY; + return NV_ERR_INVALID_STATE; } // Allocate buffer for certificates. @@ -679,7 +725,8 @@ spdmGetCertificates_GH100 portMemSet(pSpdm->pAttestationCertChain, 0, pSpdm->attestationCertChainSize); // We fetch Attestation cert chain only on Hopper. - CHECK_SPDM_STATUS(libspdm_get_certificate(pSpdm->pLibspdmContext, SPDM_CERT_DEFAULT_SLOT_ID, + CHECK_SPDM_STATUS(libspdm_get_certificate(pSpdm->pLibspdmContext, NULL, + SPDM_CERT_DEFAULT_SLOT_ID, &gpuCertsSize, pGpuCerts)); // Now, append the root certificates to create the entire chain. @@ -736,8 +783,8 @@ spdmGetCertificates_GH100 if (derCertChainSize != totalSize) { - NV_PRINTF(LEVEL_ERROR, " %s: derCertChainSize(%lu) != totalSize(0x%x) !! \n", - __FUNCTION__, derCertChainSize, totalSize); + NV_PRINTF(LEVEL_ERROR, " %s: derCertChainSize(%llu) != totalSize(0x%x) !! \n", + __FUNCTION__, ((NvU64)derCertChainSize), totalSize); // Something has gone quite wrong with our calculations. status = NV_ERR_BUFFER_TOO_SMALL; @@ -827,3 +874,31 @@ spdmGetCertChains_GH100 return NV_OK; } + +/*! + @param pGpu : The pointer to GPU object + @param pSpdm : The pointer to SPDM object + @parsm pEncapCertChain : The pointer to store return certification address + @param pEncapCertChainSize : The pointer to store rrtun certification size + + @return Return NV-OK if no error. +*/ +NV_STATUS +spdmGetReqEncapCertificates_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU8 **pEncapCertChain, + NvU32 *pEncapCertChainSize +) +{ + if (pEncapCertChain == NULL || pEncapCertChainSize == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + *pEncapCertChain = (NvU8 *)SPDM_REQ_ENCAP_CERTIFICATE_DER; + *pEncapCertChainSize = sizeof(SPDM_REQ_ENCAP_CERTIFICATE_DER); + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c index 80235bb10f..86e8c76dac 100644 --- a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c +++ b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c @@ -32,6 +32,7 @@ #include "spdm/rmspdmtransport.h" #include "spdm/rmspdmvendordef.h" #include "objtmr.h" +#include "gpu/gsp/kernel_gsp.h" #include "gpu/bus/kern_bus.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/spdm/libspdm_includes.h" @@ -39,10 +40,17 @@ #include "ctrl/ctrl2080/ctrl2080spdm.h" #include "flcnretval.h" #include "gpu/conf_compute/conf_compute.h" +#include "platform/sli/sli.h" +#include "nvspdm_rmconfig.h" +#include "published/hopper/gh100/dev_falcon_v4.h" +#include "gpu/conf_compute/conf_compute.h" /* ------------------------ Macros ----------------------------------------- */ -#define SPDM_MESSAGE_BUFFER_ADDRESS_ALIGNMENT (256) - +// +// List expected capabilties to receive from Responder. +// Regardless of whether Requester is configured to support these, +// we only expect Responder to provide these capabilities. +// #define SPDM_CAPABILITIES_FLAGS_GH100 \ SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP | \ SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG | \ @@ -50,91 +58,30 @@ SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP | \ SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MAC_CAP | \ SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP | \ - SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP - -/* ------------------------ Types Definitions ------------------------------ */ -/*! - * Define context structure which tracks all state required for IO between - * RM and GSP. They communicate via a shared memory surface in which SPDM - * payloads are stored, and use the RM<->GSP command queue to alert of payloads. - */ -typedef struct _SPDM_GSP_IO_CONTEXT -{ - /*! - * Buffer to store SPDM response read from memory surface. Required since - * libspdm splits send and receive message across two message calls. - */ - NV_DECLARE_ALIGNED(NvU8 *pResponse, 8); - - /*! The memory descriptor that describes the memory surface */ - NV_DECLARE_ALIGNED(MEMORY_DESCRIPTOR *pMemDesc, 8); - - /*! - * The size of the surface. This information is also contained in - * the surfaces's memory descriptor but is still required since - * surface structures will be allocated and populated before the - * underlying surfaces are allocated themselves (time at which the - * memory descriptors will allocated and populated). - */ - NvU32 surfaceSizeInByte; - - /*! - * Represents the amount by which the actual size of the surface will - * aligned when the surface is allocated. - */ - NvU32 alignSize; - - /*! - * Stores the address that the GSP will use when accessing the surface. - */ - NvU64 dmaAddr; - - /*! - * Address space for memory surface (sysmem or FB). - */ - NvU32 addrSpace; - - /*! - * Sequence number for the memory surface. - */ - NvU32 seqNum; - - /*! - * Region ID for the payload (i.e. unprotected, protected). - */ - NvU32 regionId; - - /*! - * Size allocated for the SPDM message decription header, which - * describes the payload contained in the surface. - */ - NvU32 descHdrSizeInByte; - - /*! - * Size of the surface available to RM for storing SPDM messages. - */ - NvU32 rmBufferSizeInByte; - - /*! - * Size of the above response buffer. - */ - NvU32 responseSize; - -} SPDM_GSP_IO_CONTEXT; + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCAP_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MUT_AUTH_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HBEAT_CAP; /* ------------------------ Static Variables ------------------------------- */ // -// For transport functionality, we require access to the GPU and Spdm objects. -// However, libspdm transport layer currently does not support passing any custom -// parameters, meaning we must use static variables to access these objects. -// If we ever require multiple instances of the Spdm object, this will be an issue. +// For transport functionality, we require access to the GPU and Spdm objects, +// as well as additional state (temporary response buffer). // -static OBJGPU *g_pGpu = NULL; -static Spdm *g_pSpdm = NULL; +// However, libspdm transport layer is implemented via callbacks which currently +// do not support passing any custom parameters, meaning we must use static variables +// to access these objects. If we ever require multiple instances of the Spdm object, +// this will be an issue. +// +static OBJGPU *g_pGpu = NULL; +static Spdm *g_pSpdm = NULL; +static NvU8 *g_pTransportBuffer = NULL; +static NvU32 g_transportBufferSize = 0; +static NvU32 g_pendingResponseSize = 0; static SPDM_ALGO_CHECK_ENTRY g_SpdmAlgoCheckTable_GH100[] = { - { LIBSPDM_DATA_MEASUREMENT_SPEC, SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF }, + { LIBSPDM_DATA_MEASUREMENT_SPEC, SPDM_MEASUREMENT_SPECIFICATION_DMTF }, { LIBSPDM_DATA_MEASUREMENT_HASH_ALGO, SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 }, { LIBSPDM_DATA_BASE_ASYM_ALGO, SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 }, { LIBSPDM_DATA_BASE_HASH_ALGO, SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 }, @@ -142,23 +89,26 @@ static SPDM_ALGO_CHECK_ENTRY g_SpdmAlgoCheckTable_GH100[] = { LIBSPDM_DATA_AEAD_CIPHER_SUITE, SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM }, { LIBSPDM_DATA_KEY_SCHEDULE, SPDM_ALGORITHMS_KEY_SCHEDULE_HMAC_HASH }, { LIBSPDM_DATA_OTHER_PARAMS_SUPPORT, 0 }, - { LIBSPDM_DATA_REQ_BASE_ASYM_ALG, 0 } +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + { LIBSPDM_DATA_REQ_BASE_ASYM_ALG, SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 } +#endif }; /* ------------------------ Static Function Prototypes --------------------- */ -static void _spdmReleaseSurfaceGsp(Spdm *pSpdm); - -static NV_STATUS _spdmErrorCheck(RM_GSP_SPDM_MSG *pSpdmMsg, - NvU32 guestIdChk, - NvU32 endpointIdChk, - NvU32 cmdType); +static void _spdmSendHeartbeat(NvU32 gpuInstance, void *pArgs); +static NV_STATUS _spdmTriggerHeartbeat(OBJGPU *pGpu, OBJTMR *pTmr, PTMR_EVENT pTmrEvent); // // Static transport layer functions which we pass to libspdm as function pointers. // The libspdm library will then use these functions to send and receive SPDM messages. // Function parameters and types must match those expected by libspdm. // -static uint32_t _spdmGetTransportHeaderSizeGsp(void *spdm_context); +static spdm_version_number_t _spdmGetSecuredMessageVersionGsp(spdm_version_number_t secured_message_version); + +static uint8_t _spdmGetSecuredMessageSequenceNumberGsp(uint64_t sequence_number, + uint8_t *sequence_number_buffer); + +static uint32_t _spdmGetSecuredMessageMaxRandomNumberCountGsp(void); static libspdm_return_t _spdmEncodeMessageGsp(void *spdm_context, const uint32_t *session_id, bool is_app_message, bool is_requester, @@ -175,102 +125,138 @@ static libspdm_return_t _spdmSendMessageGsp(void *spdm_context, size_t message_s const void *message, uint64_t timeout); static libspdm_return_t _spdmReceiveMessageGsp(void *spdm_context, size_t *message_size, - void **message, uint64_t timeout); + void **message, uint64_t timeout); -static NV_STATUS _spdmSendInitRmDataCommand(OBJGPU *pGpu, Spdm *pSpdm); /* ------------------------ Static Functions ------------------------------- */ +// +// Hardcoding check for libspdm secured message callbacks version. +// If libspdm bumps this in a version update, we must update as well. +// +ct_assert(LIBSPDM_SECURED_MESSAGE_CALLBACKS_VERSION == 2); + /*! - * Frees all memory and state associated with the GSP SPDM-message surface. - */ -void -_spdmReleaseSurfaceGsp + * Callback to convert secured_message_version to DSP0277 version. + * In our case, secured_message_version will always be DSP0277 version. + */ +spdm_version_number_t +_spdmGetSecuredMessageVersionGsp ( - Spdm *pSpdm + spdm_version_number_t secured_message_version ) { - SPDM_GSP_IO_CONTEXT *pIOContext = NULL; - - if (pSpdm == NULL || pSpdm->pDeviceIOContext == NULL) - { - NV_PRINTF(LEVEL_ERROR, "SPDM: Attempting to release NULL MemDesc, this is BUG!\n"); - DBG_BREAKPOINT(); - return; - } - - pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; - memdescFree(pIOContext->pMemDesc); - memdescDestroy(pIOContext->pMemDesc); - portMemFree(pIOContext->pResponse); - portMemSet(pIOContext, 0, sizeof(SPDM_GSP_IO_CONTEXT)); - portMemFree(pIOContext); - - // Ensure we clear object context pointer. - pSpdm->pDeviceIOContext = NULL; + return secured_message_version; } /*! - * Performs validation of received RPC SPDM message and - * by comparing the message against expected values. Used - * to detect mismatch between attributes of request sent - * and attributes of response received. + * @brief Work function scheduled by heartbeat callback in order to actually + * send the heartbeat to GSP-RM. Checks to ensure whether KEY_UPDATE + * is required before sending heartbeat. * - * @param[in] pSpdmMsg Pointer to SPDM Message structure. - * @param[in] guestIdChk Expected guest ID. - * @param[in] endpointIdChk Expected endpoint ID. - * @param[in] cmdType SPDM command type. + * @param[in] gpuInstance : Instance number of the specific GPU + * @param[in] pArgs : Opaque pointer to the SPDM object */ -NV_STATUS -_spdmErrorCheck +static void +_spdmSendHeartbeat ( - RM_GSP_SPDM_MSG *pSpdmMsg, - NvU32 guestIdChk, - NvU32 endpointIdChk, - NvU32 cmdType + NvU32 gpuInstance, + void *pArgs ) { - // Perform validation of received RPC SPDM message. - if (pSpdmMsg->status != FLCN_OK) + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); + OBJTMR *pTmr = NULL; + Spdm *pSpdm = NULL; + NV_STATUS status = NV_OK; + + if (pGpu == NULL || pArgs == NULL) { - NV_PRINTF(LEVEL_ERROR, "SPDM: RPC message error : status = 0x%x.\n", - pSpdmMsg->status); + status = NV_ERR_INVALID_ARGUMENT; + goto ErrorExit; + } - DBG_BREAKPOINT(); - return NV_ERR_GENERIC; + pTmr = GPU_GET_TIMER(pGpu); + pSpdm = (Spdm *)pArgs; + if (pSpdm == NULL || pSpdm->pLibspdmContext == NULL || + pSpdm->sessionId == INVALID_SESSION_ID) + { + status = NV_ERR_NOT_READY; + goto ErrorExit; } - // Perform validation of received SPDM message description header only if SPDM RPC message status is FLCN_OK. - if (pSpdmMsg->version != NV_SPDM_DESC_HEADER_VERSION_CURRENT) + // + // Check to see if KEY_UPDATE is required before using. As timer resets on + // every message sent, sending KEY_UPDATE shouldn't incur any timeout risk. + // + status = spdmCheckAndExecuteKeyUpdate(pGpu, pSpdm, NV_KEY_UPDATE_TRIGGER_ID_HEARTBEAT); + if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "SPDM: Version mismatch: [Check] version = 0x%x, [SpdmRet] version = 0x%x\n", - NV_SPDM_DESC_HEADER_VERSION_CURRENT, pSpdmMsg->version); - DBG_BREAKPOINT(); - return NV_ERR_GENERIC; + goto ErrorExit; } - if (pSpdmMsg->guestId != guestIdChk) + CHECK_SPDM_STATUS(libspdm_heartbeat(pSpdm->pLibspdmContext, pSpdm->sessionId)); + + // Reschedule heartbeat only if successful + status = tmrEventScheduleRelSec(pTmr, pSpdm->pHeartbeatEvent, pSpdm->heartbeatPeriodSec); + +ErrorExit: + if (status != NV_OK && pGpu != NULL) { - NV_PRINTF(LEVEL_ERROR, - "SPDM: Guest ID mismatch: [Check] guestId = 0x%x, [SpdmRet] guestId = 0x%x\n", - guestIdChk, pSpdmMsg->guestId); - DBG_BREAKPOINT(); - return NV_ERR_GENERIC; + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + // + // Set GPU Ready State to false. This will destroy the SPDM session as well. + // Ideally we don't have dependency on Confidential Compute object here, + // but that's the best we can do without unnecessary code duplication. + // + confComputeSetErrorState(pGpu, pConfCompute); } +} - if (cmdType != RM_GSP_SPDM_CMD_ID_CC_INIT) +/*! + * @brief Callback function scheduled when HEARTBEAT is enabled. + * Function will queue a work item to actually send the heartbeat, + * since we cannot do so in the callback interrupt context. + * Upon successful queueing of work item, schedules another heartbeat callback. + * + * @param[in] pGpu : OBJGPU pointer + * @param[in] pTmr : OBJTMR pointer + * @param[in] pTmrEvent : Pointer to the specific heartbeat timer event. + * + * @return NV_STATUS representing success or relevant failure. + */ +static NV_STATUS +_spdmTriggerHeartbeat +( + OBJGPU *pGpu, + OBJTMR *pTmr, + PTMR_EVENT pTmrEvent +) +{ + NV_STATUS status = NV_OK; + + if (pGpu == NULL || pTmr == NULL || pTmrEvent == NULL) { - if (pSpdmMsg->endpointId != endpointIdChk) - { - NV_PRINTF(LEVEL_ERROR, - "SPDM: Endpoint ID mismatch: [Check] endpointId = 0x%x, [SpdmRet] endpointId = 0x%x\n", - endpointIdChk, pSpdmMsg->endpointId); - DBG_BREAKPOINT(); - return NV_ERR_GENERIC; - } + status = NV_ERR_INVALID_ARGUMENT; + goto ErrorExit; } - return NV_OK; + // Some RM APIs call SPDM, ensure we do not conflict with them + status = osQueueWorkItemWithFlags(pGpu, _spdmSendHeartbeat, pTmrEvent->pUserData, + OS_QUEUE_WORKITEM_FLAGS_DONT_FREE_PARAMS | + OS_QUEUE_WORKITEM_FLAGS_LOCK_API_RW | + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW); + + ErrorExit: + if (status != NV_OK && pGpu != NULL) + { + ConfidentialCompute *pConfCompute = GPU_GET_CONF_COMPUTE(pGpu); + // + // Set GPU Ready State to false. This will destroy the SPDM session as well. + // Ideally we don't have dependency on Confidential Compute object here, + // but that's the best we can do without unnecessary code duplication. + // + confComputeSetErrorState(pGpu, pConfCompute); + } + return status; } /*! @@ -279,7 +265,7 @@ _spdmErrorCheck * Currently, requester(RM) and responder(GSP-SPDM) doesn't support sequence number. */ uint8_t -_spdmGetSequenceNumberGsp +_spdmGetSecuredMessageSequenceNumberGsp ( uint64_t sequence_number, uint8_t *sequence_number_buffer @@ -294,7 +280,7 @@ _spdmGetSequenceNumberGsp * The random number size is for secured message format only and defined in DMTF DSP0277. */ uint32_t -_spdmGetMaxRandomNumberCountGsp +_spdmGetSecuredMessageMaxRandomNumberCountGsp ( void ) @@ -302,19 +288,6 @@ _spdmGetMaxRandomNumberCountGsp return NV_SPDM_MAX_RANDOM_MSG_BYTES; } -/*! - * Callback to get allocated space for transport header that is pre-pended - * to the SPDM message. Return the size of the NV_SPDM_MESSAGE_HEADER we prepend. - */ -uint32_t -_spdmGetTransportHeaderSizeGsp -( - void *spdm_context -) -{ - return sizeof(NV_SPDM_DESC_HEADER); -} - /*! * Static function libspdm uses as hook to RM<->GSP transport layer. * If secured, encodes message into SPDM Secured Message format. @@ -338,14 +311,11 @@ _spdmEncodeMessageGsp void *pSecuredMessageContext = NULL; NV_SPDM_DESC_HEADER *pNvSpdmDescHdr = NULL; NvU32 payloadSize = 0; - SPDM_GSP_IO_CONTEXT *pIOContext = NULL; - - pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; // Check libspdm parameters. if (spdm_context == NULL || message == NULL || message_size == 0 || transport_message == NULL || *transport_message == NULL || - transport_message_size == NULL || pIOContext == NULL) + transport_message_size == NULL) { return LIBSPDM_STATUS_INVALID_PARAMETER; } @@ -365,6 +335,7 @@ _spdmEncodeMessageGsp // Initialize descriptor header. pNvSpdmDescHdr = (NV_SPDM_DESC_HEADER *)*transport_message; portMemSet(pNvSpdmDescHdr, 0, sizeof(NV_SPDM_DESC_HEADER)); + pNvSpdmDescHdr->version = NV_SPDM_DESC_HEADER_VERSION_CURRENT; // Determine whether message is secured. if (session_id != NULL) @@ -385,9 +356,10 @@ _spdmEncodeMessageGsp // Initialize secured message attributes. portMemSet(&securedMessageInfo, 0, sizeof(securedMessageInfo)); - securedMessageInfo.version = SPDM_SECURED_MESSAGE_CALLBACKS_VERSION; - securedMessageInfo.get_sequence_number = _spdmGetSequenceNumberGsp; - securedMessageInfo.get_max_random_number_count = _spdmGetMaxRandomNumberCountGsp; + securedMessageInfo.version = LIBSPDM_SECURED_MESSAGE_CALLBACKS_VERSION; + securedMessageInfo.get_sequence_number = _spdmGetSecuredMessageSequenceNumberGsp; + securedMessageInfo.get_max_random_number_count = _spdmGetSecuredMessageMaxRandomNumberCountGsp; + securedMessageInfo.get_secured_spdm_version = _spdmGetSecuredMessageVersionGsp; // Encode secured message into output buffer. status = libspdm_encode_secured_message(pSecuredMessageContext, *session_id, is_requester, @@ -429,21 +401,11 @@ _spdmEncodeMessageGsp } // Check final encrypted message size. - if (*transport_message_size > NV_SPDM_RM_SURFACE_SIZE_IN_BYTE) + if (*transport_message_size > g_pSpdm->payloadBufferSize) { return LIBSPDM_STATUS_BUFFER_TOO_SMALL; } - // Record the message in the last exchange transcript. - if (message_size > SPDM_MAX_EXCHANGE_BUFFER_SIZE) - { - return LIBSPDM_STATUS_INVALID_PARAMETER; - } - - portMemCopy(g_pSpdm->pLastExchange, SPDM_MAX_EXCHANGE_BUFFER_SIZE, - message, message_size); - g_pSpdm->lastExchangeSize = message_size; - return LIBSPDM_STATUS_SUCCESS; } @@ -469,7 +431,6 @@ _spdmDecodeMessageGsp NvU32 payloadSize = 0; void *pSecuredMessageContext = NULL; libspdm_return_t status = LIBSPDM_STATUS_SUCCESS; - NvU32 lastExchangeSizeLeft = 0; spdm_secured_message_a_data_header1_t *pSpdmSecuredMsgHdr = NULL; // Check libspdm parameters. @@ -489,12 +450,21 @@ _spdmDecodeMessageGsp // Retrieve NV-header from message, and perform basic validation. pNvSpdmDescHdr = (NV_SPDM_DESC_HEADER *)transport_message; if (transport_message_size < sizeof(NV_SPDM_DESC_HEADER) || - transport_message_size > NV_SPDM_RM_SURFACE_SIZE_IN_BYTE) + transport_message_size > g_pSpdm->payloadBufferSize) { return LIBSPDM_STATUS_INVALID_MSG_FIELD; } - payloadSize = NV_SPDM_DESC_HEADER_SIZE_IN_BYTE + pNvSpdmDescHdr->msgSizeByte; + if (pNvSpdmDescHdr->version != NV_SPDM_DESC_HEADER_VERSION_CURRENT) + { + NV_PRINTF(LEVEL_ERROR, + "SPDM: Version mismatch: [Check] version = 0x%x, [SpdmRet] version = 0x%x\n", + NV_SPDM_DESC_HEADER_VERSION_CURRENT, pNvSpdmDescHdr->version); + DBG_BREAKPOINT(); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + + payloadSize = sizeof(NV_SPDM_DESC_HEADER) + pNvSpdmDescHdr->msgSizeByte; if (transport_message_size != payloadSize) { @@ -530,15 +500,16 @@ _spdmDecodeMessageGsp // Initialize secured message attributes. portMemSet(&securedMessageInfo, 0, sizeof(securedMessageInfo)); - securedMessageInfo.version = SPDM_SECURED_MESSAGE_CALLBACKS_VERSION; - securedMessageInfo.get_sequence_number = _spdmGetSequenceNumberGsp; - securedMessageInfo.get_max_random_number_count = _spdmGetMaxRandomNumberCountGsp; + securedMessageInfo.version = LIBSPDM_SECURED_MESSAGE_CALLBACKS_VERSION; + securedMessageInfo.get_sequence_number = _spdmGetSecuredMessageSequenceNumberGsp; + securedMessageInfo.get_max_random_number_count = _spdmGetSecuredMessageMaxRandomNumberCountGsp; + securedMessageInfo.get_secured_spdm_version = _spdmGetSecuredMessageVersionGsp; // Decode and retrieve application payload from secured message. // We must copy the message to the scratch buffer. status = libspdm_decode_secured_message(pSecuredMessageContext, **session_id, is_requester, - transport_message_size - NV_SPDM_DESC_HEADER_SIZE_IN_BYTE, + transport_message_size - sizeof(NV_SPDM_DESC_HEADER), (pNvSpdmDescHdr + 1), message_size, message, &securedMessageInfo); if (status != LIBSPDM_STATUS_SUCCESS) @@ -578,17 +549,6 @@ _spdmDecodeMessageGsp // We don't expect app message for any scenario. *is_app_message = NV_FALSE; - // Record the message in the last exchange transcript. - lastExchangeSizeLeft = SPDM_MAX_EXCHANGE_BUFFER_SIZE - g_pSpdm->lastExchangeSize; - if (*message_size > lastExchangeSizeLeft || SPDM_MAX_EXCHANGE_BUFFER_SIZE < g_pSpdm->lastExchangeSize) - { - return LIBSPDM_STATUS_INVALID_PARAMETER; - } - - portMemCopy((NvU8 *)g_pSpdm->pLastExchange + g_pSpdm->lastExchangeSize, - lastExchangeSizeLeft, *message, *message_size); - g_pSpdm->lastExchangeSize += *message_size; - return LIBSPDM_STATUS_SUCCESS; } @@ -606,11 +566,11 @@ _spdmSendMessageGsp uint64_t timeout ) { - NvU8 *pRequest = NULL; - NvU32 requestSize = 0; - NV_STATUS nvStatus = NV_OK; - libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS; - SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + NV_STATUS nvStatus = NV_OK; + libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS; + + // Ensure size is cleared to indicate no response pending in buffer yet + g_pendingResponseSize = 0; // Check libspdm parameters. if (message_size == 0 || message == NULL) @@ -618,43 +578,32 @@ _spdmSendMessageGsp return LIBSPDM_STATUS_INVALID_PARAMETER; } - if (g_pGpu == NULL || g_pSpdm == NULL || g_pSpdm->pDeviceIOContext == NULL) + if (g_pGpu == NULL || g_pSpdm == NULL) { return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } - pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; - - // Initialize space for SPDM request and response buffers. - requestSize = message_size; - pRequest = (NvU8 *)portMemAllocNonPaged(requestSize); - pIOContext->responseSize = LIBSPDM_MAX_MESSAGE_BUFFER_SIZE; - pIOContext->pResponse = (NvU8 *)portMemAllocNonPaged(pIOContext->responseSize); - - if (pRequest == NULL || pIOContext->pResponse == NULL) + if (g_transportBufferSize < message_size) { - spdmStatus = LIBSPDM_STATUS_BUFFER_FULL; - goto ErrorExit; + return LIBSPDM_STATUS_BUFFER_TOO_SMALL; } - portMemSet(pRequest, 0, requestSize); - portMemSet(pIOContext->pResponse, 0, pIOContext->responseSize); - portMemCopy(pRequest, requestSize, message, message_size); + // Fill transport buffer with message and send + g_pendingResponseSize = g_transportBufferSize; + portMemCopy(g_pTransportBuffer, g_transportBufferSize, message, message_size); nvStatus = spdmMessageProcess_HAL(g_pGpu, g_pSpdm, - pRequest, requestSize, - pIOContext->pResponse, - &pIOContext->responseSize); - -ErrorExit: + g_pTransportBuffer, message_size, + g_pTransportBuffer, &g_pendingResponseSize); + if (nvStatus != NV_OK) + { + spdmStatus = LIBSPDM_STATUS_SEND_FAIL; + } - portMemFree(pRequest); - if (spdmStatus != LIBSPDM_STATUS_SUCCESS || nvStatus != NV_OK) + if (spdmStatus != LIBSPDM_STATUS_SUCCESS) { - portMemFree(pIOContext->pResponse); - pIOContext->pResponse = NULL; - pIOContext->responseSize = 0; - spdmStatus = LIBSPDM_STATUS_SEND_FAIL; + // If message failed, size is cleared to indicate no response pending + g_pendingResponseSize = 0; } return spdmStatus; @@ -674,8 +623,7 @@ _spdmReceiveMessageGsp uint64_t timeout ) { - libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS; - SPDM_GSP_IO_CONTEXT *pIOContext = NULL; + libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS; // Check libspdm parameters. if (message_size == NULL || message == NULL || *message == NULL) @@ -683,79 +631,29 @@ _spdmReceiveMessageGsp return LIBSPDM_STATUS_INVALID_PARAMETER; } - if (g_pGpu == NULL || g_pSpdm == NULL || g_pSpdm->pDeviceIOContext == NULL) + if (g_pGpu == NULL || g_pSpdm == NULL) { return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } // Basic validation to ensure we have a real response. - pIOContext = (SPDM_GSP_IO_CONTEXT *)g_pSpdm->pDeviceIOContext; - if (pIOContext->pResponse == NULL || pIOContext->responseSize == 0) + if (g_pendingResponseSize == 0 || g_pendingResponseSize > *message_size) { spdmStatus = LIBSPDM_STATUS_RECEIVE_FAIL; goto ErrorExit; } - if (pIOContext->responseSize > *message_size) - { - spdmStatus = LIBSPDM_STATUS_BUFFER_TOO_SMALL; - goto ErrorExit; - } - - portMemCopy(*message, *message_size, pIOContext->pResponse, pIOContext->responseSize); - *message_size = pIOContext->responseSize; + portMemCopy(*message, *message_size, g_pTransportBuffer, g_pendingResponseSize); + *message_size = g_pendingResponseSize; ErrorExit: - // Invalidate response message, regardless of success or failure. - portMemFree(pIOContext->pResponse); - pIOContext->pResponse = NULL; - pIOContext->responseSize = 0; + // Ensure size is cleared to indicate no response pending in buffer + g_pendingResponseSize = 0; return spdmStatus; } -/*! -* Static function that sends the opaque data from RM to GSP. -*/ -NV_STATUS -_spdmSendInitRmDataCommand -( - OBJGPU *pGpu, - Spdm *pSpdm -) -{ - NV_STATUS status = NV_OK; - RMTIMEOUT timeout; - NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; - - if (pGpu == NULL || pSpdm == NULL) - { - return NV_ERR_INVALID_ARGUMENT; - } - - portMemSet(¶ms, 0, sizeof(params)); - params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA; - - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - - status = spdmCtrlSpdmPartition(pGpu, ¶ms); - if (status != NV_OK) - { - return NV_ERR_FLCN_ERROR; - } - - // Perform basic validation of header returned, ensuring it matches expected values. - status = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "SPDM: _spdmErrorCheck() failed in INIT_RM_DATA command \n"); - DBG_BREAKPOINT(); - return status; - } - - return NV_OK; -} /* ------------------------ Public Functions ------------------------------- */ /*! @@ -770,172 +668,45 @@ spdmDeviceInit_GH100 Spdm *pSpdm ) { - NV_STATUS status = NV_OK; - NV_STATUS descHdrStatus = NV_OK; - SPDM_GSP_IO_CONTEXT *pIOContext = NULL; - RmPhysAddr physAddr = 0; - NvU64 memDescFlags = MEMDESC_FLAGS_NONE; - NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; - RMTIMEOUT timeout; - TRANSFER_SURFACE surf = {0}; - MemoryManager *pMemoryManager = NULL; - if (pGpu == NULL || pSpdm == NULL || pSpdm->pLibspdmContext == NULL) { return NV_ERR_INVALID_ARGUMENT; } - g_pGpu = pGpu; - g_pSpdm = pSpdm; - - // Register transport layer functionality with library. - libspdm_register_transport_layer_func(pSpdm->pLibspdmContext, - _spdmEncodeMessageGsp, - _spdmDecodeMessageGsp, - _spdmGetTransportHeaderSizeGsp); - - libspdm_register_device_io_func(pSpdm->pLibspdmContext, - _spdmSendMessageGsp, - _spdmReceiveMessageGsp); - - - pSpdm->pDeviceIOContext = portMemAllocNonPaged(sizeof(SPDM_GSP_IO_CONTEXT)); - if (pSpdm->pDeviceIOContext == NULL) - { - return NV_ERR_INSUFFICIENT_RESOURCES; - } - - pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; - portMemSet(pIOContext, 0, sizeof(SPDM_GSP_IO_CONTEXT)); + g_pGpu = pGpu; + g_pSpdm = pSpdm; + g_pendingResponseSize = 0; + g_pTransportBuffer = portMemAllocNonPaged(pSpdm->payloadBufferSize); - // - // Set default values for IO context. - // TODO CONFCOMP-1463: Generalize command structures. - // - pIOContext->surfaceSizeInByte = NV_SPDM_RM_SURFACE_SIZE_IN_BYTE; - pIOContext->descHdrSizeInByte = NV_SPDM_DESC_HEADER_SIZE_IN_BYTE; - pIOContext->rmBufferSizeInByte = NV_RM_BUFFER_SIZE_IN_BYTE; - pIOContext->alignSize = SPDM_MESSAGE_BUFFER_ADDRESS_ALIGNMENT; - pIOContext->addrSpace = NV_SPDM_DMA_ADDR_SPACE_DEFAULT; - pIOContext->regionId = NV_SPDM_DMA_REGION_ID_DEFAULT; - pIOContext->pResponse = NULL; - pIOContext->responseSize = 0; - - // Be sure to allocate in unprotected memory, so GPU can read. - memDescFlags = MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY; - - // Create memory descriptor. - status = memdescCreate(&pIOContext->pMemDesc, pGpu, - pIOContext->surfaceSizeInByte, - pIOContext->alignSize, - NV_TRUE, pIOContext->addrSpace, - NV_MEMORY_UNCACHED, - memDescFlags); - if (status != NV_OK || pIOContext->pMemDesc == NULL) - { - portMemFree(pIOContext); - pSpdm->pDeviceIOContext = NULL; - return NV_ERR_INSUFFICIENT_RESOURCES; - } - - memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_82, - pIOContext->pMemDesc); - if (status != NV_OK) + if (g_pTransportBuffer == NULL) { - NV_PRINTF(LEVEL_ERROR, "SPDM: Cannot allocate SPDM surface!\n"); - memdescDestroy(pIOContext->pMemDesc); - portMemFree(pIOContext); - pSpdm->pDeviceIOContext = NULL; - return status; + g_transportBufferSize = 0; + return NV_ERR_NO_MEMORY; } - // Physical mode with GSP. - if ((pIOContext->addrSpace == ADDR_SYSMEM) || (pIOContext->addrSpace == ADDR_FBMEM)) - { - physAddr = memdescGetPhysAddr(pIOContext->pMemDesc, AT_GPU, 0); - } - else - { - NV_PRINTF(LEVEL_ERROR, "SPDM: Message surface addr space is invalid: (0x%x)\n", - pIOContext->addrSpace); - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto ErrorExit; - } - - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) - - pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - - surf.pMemDesc = pIOContext->pMemDesc; - surf.offset = 0; - - // Scrub surface - NV_ASSERT_OK_OR_GOTO(status, - memmgrMemSet(pMemoryManager, &surf, 0, pIOContext->surfaceSizeInByte, - TRANSFER_FLAGS_NONE), - ErrorExit); - - pIOContext->dmaAddr = (NvU64)physAddr; - - // Prepare GSP-CMD and send to GSP-SPDM partition. - portMemSet(¶ms, 0, sizeof(params)); + g_transportBufferSize = pSpdm->payloadBufferSize; - params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_INIT; - - RM_GSP_SPDM_CMD_CC_INIT *pCcInit = ¶ms.cmd.ccInit; - RM_GSP_SPDM_CC_INIT_CTX *pCcInitCtx = &pCcInit->ccInitCtx; - - // Ucode is responsible for setting DMA index. - pCcInitCtx->guestId = pSpdm->guestId; - pCcInitCtx->rmBufferSizeInByte = NV_RM_BUFFER_SIZE_IN_BYTE; - NvU64_ALIGN32_PACK(&pCcInitCtx->dmaAddr, &pIOContext->dmaAddr); - - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - - status = spdmCtrlSpdmPartition(pGpu, ¶ms); - - // - // If successful, copy status received from GSP-SPDM. In case of failure, we will - // unmap memory first before breaking to error handling routine. - // - if (status == NV_OK) - { - descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_INIT); - } - - // Now we check for command success. - if (status != NV_OK || descHdrStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "SPDM: gspCommandPostBlocking() failed in INIT command, status = 0x%x, descHdrStatus = 0x%x \n", - status, descHdrStatus); - DBG_BREAKPOINT(); - - status = (status == NV_OK ? descHdrStatus : status); - goto ErrorExit; - } - - // If successful, save returned endpoint ID to context. - pSpdm->endpointId = params.msg.endpointId; - - // Sending Rm data for opaque data to GSP. - status = _spdmSendInitRmDataCommand(pGpu, pSpdm); + // Register transport layer functionality with library. + libspdm_register_transport_layer_func(pSpdm->pLibspdmContext, + NV_SPDM_MAX_SPDM_PAYLOAD_SIZE, + sizeof(NV_SPDM_DESC_HEADER), + 0, + _spdmEncodeMessageGsp, + _spdmDecodeMessageGsp); - SLI_LOOP_END + libspdm_register_device_io_func(pSpdm->pLibspdmContext, + _spdmSendMessageGsp, + _spdmReceiveMessageGsp); -ErrorExit: - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "SPDM: INIT command failed: status 0x%x\n", status); - _spdmReleaseSurfaceGsp(pSpdm); - } + pSpdm->bUsePolling = IS_GSP_CLIENT(pGpu); - return status; + return NV_OK; } /*! * To deinitialize the GSP SPDM Responder, we need to release the surface for - * SPDM communcation, and send deinitialization command to GSP-SPDM. + * SPDM communication. GSP-RM will handle the rest. */ NV_STATUS spdmDeviceDeinit_GH100 @@ -945,72 +716,13 @@ spdmDeviceDeinit_GH100 NvBool bForceClear ) { - NV_STATUS status = NV_OK; - NV_STATUS descHdrStatus = NV_OK; - RM_GSP_SPDM_CMD_CC_DEINIT *pCcDeinit = NULL; - RM_GSP_SPDM_CC_DEINIT_CTX *pCcDeinitCtx = NULL; - NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; - RMTIMEOUT timeout; - - if (pGpu == NULL || pSpdm == NULL || pSpdm->pDeviceIOContext == NULL) - { - return NV_ERR_INVALID_ARGUMENT; - } - - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) - - // Prepare GSP-CMD and send to GSP-SPDM partition. - portMemSet(¶ms, 0, sizeof(params)); - - params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_DEINIT; - - // TODO CONFCOMP-1463: Generalize command structures. - pCcDeinit = ¶ms.cmd.ccDeinit; - pCcDeinitCtx = &pCcDeinit->ccDeinitCtx; - pCcDeinitCtx->guestId = pSpdm->guestId; - pCcDeinitCtx->endpointId = pSpdm->endpointId; - - if (bForceClear) - { - pCcDeinitCtx->flags |= DEINIT_FLAGS_FORCE_CLEAR; - } - - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); - - status = spdmCtrlSpdmPartition(pGpu, ¶ms); - - // - // If successful, copy status received from GSP-SPDM. In case of failure, we will - // unmap memory first before breaking to error handling routine. - // - if (status == NV_OK) - { - descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_DEINIT); - } - - SLI_LOOP_END - - if (status != NV_OK || descHdrStatus != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "SPDM: DEINIT command failed: status = 0x%x, descHdrStatus = 0x%x\n", - status, descHdrStatus); - DBG_BREAKPOINT(); - - status = (status == NV_OK ? descHdrStatus : status); - goto ErrorExit; - } - - // Only release surface on success, as we may want to retry deinit on failure. - _spdmReleaseSurfaceGsp(pSpdm); - -ErrorExit: + // Just-in-case, portMemFree handles NULL. + portMemFree(g_pTransportBuffer); + g_pTransportBuffer = NULL; + g_transportBufferSize = 0; + g_pendingResponseSize = 0; - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "SPDM: DEINIT command failed: status 0x%x\n", status); - } - - return status; + return NV_OK; } NV_STATUS @@ -1024,103 +736,131 @@ spdmMessageProcess_GH100 NvU32 *pResponseSize ) { - NV_STATUS status = NV_OK; - NV_STATUS descHdrStatus = NV_OK; - NvU8 *pMapMem = NULL; - NvU32 transportResponseSize = 0; - SPDM_GSP_IO_CONTEXT *pIOContext = NULL; - RM_GSP_SPDM_CMD_CC_CTRL *pCcCtrl = NULL; - RM_GSP_SPDM_CC_CTRL_CTX *pCcCtrlCtx = NULL; - NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; - RMTIMEOUT timeout; - MemoryManager *pMemoryManager = NULL; - TRANSFER_SURFACE surf = {0}; - NvBool bFreeShadowBuf = NV_FALSE; - - if (pGpu == NULL || pSpdm == NULL || pSpdm->pDeviceIOContext == NULL || - pRequest == NULL || pResponse == NULL || pResponseSize == NULL) + NV_STATUS status = NV_OK; + NvU8 *pMapMem = NULL; + NvU32 messagePending = 0; + NvU8 *pPayloadBuffer = NULL; + NvU32 transportResponseSize = 0; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + MemoryManager *pMemoryManager = NULL; + TRANSFER_SURFACE surf = {0}; + NvBool bFreeShadowBuf = NV_FALSE; + + if (pGpu == NULL || pSpdm == NULL ||pRequest == NULL || + pResponse == NULL || pResponseSize == NULL) { return NV_ERR_INVALID_ARGUMENT; } - pIOContext = (SPDM_GSP_IO_CONTEXT *)pSpdm->pDeviceIOContext; - if (requestSize > pIOContext->rmBufferSizeInByte) + if (requestSize > pSpdm->payloadBufferSize) { return NV_ERR_INSUFFICIENT_RESOURCES; } - // - // Map memory for CPU access to copy SPDM message - ensure we unmap - // before returning for any reason. - // SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + // Offset is zero for all transfers + surf.offset = 0; pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); - pMapMem = memmgrMemDescBeginTransfer(pMemoryManager, pIOContext->pMemDesc, - TRANSFER_FLAGS_SHADOW_ALLOC); - if (pMapMem == NULL) + if (pSpdm->bUsePolling) { - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto ErrorExit; - } - - // Copy entire SPDM message to shared memory. - portMemCopy(pMapMem, requestSize, pRequest, requestSize); + // + // If we haven't established the session yet, we need to utilize polling + // based communication with GSP-SPDM partition, as GSP-RM RPC is not available. + // Note that there is a short window where session is established but GSP-RM RPC is + // not active - we don't expect any SPDM messages in this window. + // + RMTIMEOUT timeout; + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); - memmgrMemDescEndTransfer(pMemoryManager, pIOContext->pMemDesc, - TRANSFER_FLAGS_SHADOW_ALLOC); + pPayloadBuffer = memmgrMemDescBeginTransfer(pMemoryManager, pSpdm->pPayloadBufferMemDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); + if (pPayloadBuffer == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto ErrorExit; + } - // Prepare GSP-CMD and send to GSP-SPDM partition - portMemSet(¶ms, 0, sizeof(params)); - params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_CTRL; - pCcCtrl = ¶ms.cmd.ccCtrl; - pCcCtrlCtx = &pCcCtrl->ccCtrlCtx; - pCcCtrlCtx->version = NV_SPDM_DESC_HEADER_VERSION_CURRENT; - pCcCtrlCtx->guestId = pSpdm->guestId; - pCcCtrlCtx->endpointId = pSpdm->endpointId; + // First copy payload to shared buffer + portMemCopy(pPayloadBuffer, requestSize, pRequest, requestSize); + memdescFlushCpuCaches(pGpu, pSpdm->pPayloadBufferMemDesc); - gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + // Trigger message pending value, then poll for response from GSP + kflcnRegWrite_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0, NV_SPDM_REQUESTER_MESSAGE_PENDING_TOKEN); - status = spdmCtrlSpdmPartition(pGpu, ¶ms); + messagePending = kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0); + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + while (messagePending != NV_SPDM_RESPONDER_MESSAGE_PENDING_TOKEN) + { + if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT) + { + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for response from SPDM Responder!\n"); + DBG_BREAKPOINT(); + status = NV_ERR_TIMEOUT; + goto ErrorExit; + } - // Retrieve descriptor header and response message, checking header to ensure valid response. - if (status == NV_OK) + messagePending = kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0); + } + } + else { - surf.pMemDesc = pIOContext->pMemDesc; - surf.offset = 0; - - pMapMem = portMemAllocNonPaged(pIOContext->surfaceSizeInByte); + // + // At this point, we have abandoned polling and now rely on GSP-RM RPCs. + // - if (pMapMem == NULL) + // Copy entire SPDM message to shared memory. + surf.pMemDesc = pSpdm->pPayloadBufferMemDesc; + status = memmgrMemWrite(pMemoryManager, &surf, pRequest, requestSize, TRANSFER_FLAGS_NONE); + if (status != NV_OK) { - status = NV_ERR_INSUFFICIENT_RESOURCES; goto ErrorExit; } - bFreeShadowBuf = NV_TRUE; + // Prepare GSP-CMD and send to GSP-SPDM partition + portMemSet(¶ms, 0, sizeof(params)); + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_CTRL; - NV_ASSERT_OK_OR_GOTO(status, - memmgrMemRead(pMemoryManager, &surf, pMapMem, - pIOContext->surfaceSizeInByte, - TRANSFER_FLAGS_NONE), - ErrorExit); - - descHdrStatus = _spdmErrorCheck(¶ms.msg, pSpdm->guestId, pSpdm->endpointId, RM_GSP_SPDM_CMD_ID_CC_CTRL); + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + if (params.msg.status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: RPC failed! RPC status = 0x%x\n", + params.msg.status); + status = params.msg.status; + DBG_BREAKPOINT(); + goto ErrorExit; + } } - if (status != NV_OK || descHdrStatus != NV_OK) + if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "SPDM: Process message failed: status = 0x%x, descHdrStatus = 0x%x\n", - status, descHdrStatus); + NV_PRINTF(LEVEL_ERROR, "SPDM: Send/receive failed! status = 0x%x\n", status); DBG_BREAKPOINT(); + goto ErrorExit; + } - status = (status == NV_OK ? descHdrStatus : status); + // Retrieve descriptor header and response message, checking header to ensure valid response. + surf.pMemDesc = pSpdm->pPayloadBufferMemDesc; + pMapMem = portMemAllocNonPaged(pSpdm->payloadBufferSize); + if (pMapMem == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; goto ErrorExit; } - transportResponseSize = (((NV_SPDM_DESC_HEADER *)pMapMem)->msgSizeByte + NV_SPDM_DESC_HEADER_SIZE_IN_BYTE); + bFreeShadowBuf = NV_TRUE; + status = memmgrMemRead(pMemoryManager, &surf, pMapMem, + pSpdm->payloadBufferSize, + TRANSFER_FLAGS_NONE); + if (status != NV_OK) + { + goto ErrorExit; + } + + transportResponseSize = (((NV_SPDM_DESC_HEADER *)pMapMem)->msgSizeByte + sizeof(NV_SPDM_DESC_HEADER)); if (transportResponseSize > *pResponseSize) { status = NV_ERR_INSUFFICIENT_RESOURCES; @@ -1133,14 +873,21 @@ spdmMessageProcess_GH100 portMemCopy(pResponse, *pResponseSize, pMapMem, transportResponseSize); *pResponseSize = transportResponseSize; +ErrorExit: + if (pPayloadBuffer != NULL) + { + memmgrMemDescEndTransfer(pMemoryManager, pSpdm->pPayloadBufferMemDesc, + TRANSFER_FLAGS_SHADOW_ALLOC); + } + SLI_LOOP_END -ErrorExit: if (bFreeShadowBuf) { portMemFree(pMapMem); bFreeShadowBuf = NV_FALSE; } + return status; } @@ -1151,7 +898,6 @@ spdmDeviceSecuredSessionSupported_GH100 Spdm *pSpdm ) { - return NV_OK; } @@ -1208,7 +954,7 @@ spdmCheckConnection_GH100 ret = libspdm_get_data(pContext, LIBSPDM_DATA_CAPABILITY_CT_EXPONENT, &dataParam, &ctExponent, &dataSize); - if (ret != LIBSPDM_STATUS_SUCCESS || ctExponent != SPDM_CAPABILITIES_CT_EXPONENT_MAX) + if (ret != LIBSPDM_STATUS_SUCCESS || ctExponent != LIBSPDM_MAX_CT_EXPONENT) { NV_PRINTF(LEVEL_ERROR, "SPDM: Invalid Responder CT exponent.\n"); return NV_ERR_INVALID_STATE; @@ -1275,25 +1021,31 @@ spdmGetAttestationReport_GH100 } // Ensure we have a valid session, and have retrieved the certificates. - if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId == INVALID_SESSION_ID) + if (pSpdm->pLibspdmContext == NULL || !pSpdm->bSessionEstablished) { return NV_ERR_NOT_READY; } + // Check to see if KEY_UPDATE is required before using. + status = spdmCheckAndExecuteKeyUpdate(pGpu, pSpdm, NV_KEY_UPDATE_TRIGGER_ID_GET_MEASUREMENTS); + if (status != NV_OK) + { + return status; + } + // Retrieve Attestation Report, if requested. if (pAttestationReport != NULL && pAttestationReportSize != NULL) { - // Guarantees the latest transcript will fit inside the Attestation Report buffer. - if (*pAttestationReportSize < SPDM_MAX_EXCHANGE_BUFFER_SIZE) - { - return NV_ERR_BUFFER_TOO_SMALL; - } + // Reset the libspdm message log to ensure it only contains the request and response from this call. + libspdm_reset_msg_log(pSpdm->pLibspdmContext); + libspdm_set_msg_log_mode(pSpdm->pLibspdmContext, LIBSPDM_MSG_LOG_MODE_ENABLE); - numBlocks = LIBSPDM_MAX_MEASUREMENT_BLOCK_COUNT; + numBlocks = SPDM_MAX_MEASUREMENT_BLOCK_COUNT; // // Use Attestation Report buffer temporarily to store measurements, we will replace - // with the full Attestation Report from message transcripts. + // with the full Attestation Report from message transcripts. If the Attestation Report + // buffer is too small to get the measurements, it won't be large enough for the report. // pMeasurementBuffer = pAttestationReport; measurementSize = *pAttestationReportSize; @@ -1303,7 +1055,7 @@ spdmGetAttestationReport_GH100 SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_GENERATE_SIGNATURE, SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS, SPDM_CERT_DEFAULT_SLOT_ID, NULL, &numBlocks, - &measurementSize, pMeasurementBuffer, pNonce, NULL, NULL)); + &measurementSize, pMeasurementBuffer, pNonce, NULL, NULL, NULL, NULL)); if (!nvspdm_check_and_clear_libspdm_assert()) { @@ -1315,13 +1067,17 @@ spdmGetAttestationReport_GH100 } // - // Last exchange buffer will hold Attestation Report, which is comprised of + // Message log buffer will hold Attestation Report, which is comprised of // the GET_MEASUREMENTS request concatenated with the MEASUREMENTS response. - // By definition, must be larger than the measurements written above. // + if (*pAttestationReportSize < libspdm_get_msg_log_size(pSpdm->pLibspdmContext)) + { + return NV_ERR_BUFFER_TOO_SMALL; + } + portMemCopy(pAttestationReport, *pAttestationReportSize, - pSpdm->pLastExchange, pSpdm->lastExchangeSize); - *pAttestationReportSize = pSpdm->lastExchangeSize; + pSpdm->pMsgLog, libspdm_get_msg_log_size(pSpdm->pLibspdmContext)); + *pAttestationReportSize = libspdm_get_msg_log_size(pSpdm->pLibspdmContext); } // Retrieve CEC Attestation Report, if requested. @@ -1331,6 +1087,236 @@ spdmGetAttestationReport_GH100 } ErrorExit: + // Regardless of what happens, reset the message log so we don't track anything past this. + libspdm_reset_msg_log(pSpdm->pLibspdmContext); + + return status; +} + +/*! +* Function that sends the opaque data from RM to GSP. +*/ +NV_STATUS +spdmSendInitRmDataCommand_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + RMTIMEOUT timeout; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + + if (pGpu == NULL || pSpdm == NULL || !pSpdm->bSessionEstablished) + { + return NV_ERR_INVALID_ARGUMENT; + } + + portMemSet(¶ms, 0, sizeof(params)); + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Send/receive error in INIT_RM_DATA command\n"); + return NV_ERR_FLCN_ERROR; + } + + // Perform basic validation of header returned. + status = params.msg.status; + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: RPC returned failure in INIT_RM_DATA command! status = 0x%0x\n", + status); + DBG_BREAKPOINT(); + return status; + } + + return NV_OK; +} + +/*! + * @brief spdmCheckAndExecuteKeyUpdate_GH100 + * This function is used check scenario and perform key_exchange process if needed. + * + * @param[in] pGpu : OBJGPU Pointer + * @param[in] pSpdm : SPDM pointer + * @param[in] keyUpdateTriggerId : The id to identify the client, which trigger key update. + * + * @return NV_OK : Return NV_OK if no error + * + */ +NV_STATUS +spdmCheckAndExecuteKeyUpdate_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU32 keyUpdateTriggerId +) +{ + libspdm_return_t ret; + bool bSingleDirection = false; + + if (pGpu == NULL || pSpdm == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Ensure we have a valid session, and have retrieved the certificates. + if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId == INVALID_SESSION_ID) + { + return NV_ERR_NOT_READY; + } + + if (keyUpdateTriggerId == NV_KEY_UPDATE_TRIGGER_ID_GET_MEASUREMENTS || + keyUpdateTriggerId == NV_KEY_UPDATE_TRIGGER_ID_HEARTBEAT) + { + pSpdm->sessionMsgCount++; + if (pSpdm->sessionMsgCount >= NV_KEY_UPDATE_TRIGGER_THRESHOLD) + { + ret = libspdm_key_update(pSpdm->pLibspdmContext, pSpdm->sessionId, + bSingleDirection); + + if (ret != LIBSPDM_STATUS_SUCCESS) + { + NV_PRINTF(LEVEL_ERROR, "Key Update (single direction(0x%x)) failed, ret(0x%x), triggerId = (0x%x).\n", + bSingleDirection, ret, keyUpdateTriggerId); + return NV_ERR_GENERIC; + } + + if (!nvspdm_check_and_clear_libspdm_assert()) + { + // libspdm detects assert/error in key update process, need to return error. + NV_PRINTF(LEVEL_ERROR, "SPDM: spdmCheckAndExecuteKeyUpdate() assert !! \n"); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_STATE; + } + + NV_PRINTF(LEVEL_INFO, "SPDM: Key update successfully, triggerId = (0x%x)!\n", keyUpdateTriggerId); + pSpdm->sessionMsgCount = 0; + } + } + else + { + return NV_ERR_INVALID_ARGUMENT; + } + + + return NV_OK; +} + +NV_STATUS +spdmRegisterForHeartbeats_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm, + NvU32 heartbeatPeriodSec +) +{ + NV_STATUS status = NV_OK; + OBJTMR *pTmr; + RMTIMEOUT timeout; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + + // Basic parameter validation, make sure we are in a session + if (pGpu == NULL || pSpdm == NULL || pSpdm->sessionId == INVALID_SESSION_ID) + { + return NV_ERR_NOT_READY; + } + // Set minimum value to ensure we don't trigger unexpected behavior with small timer values. + else if (heartbeatPeriodSec < SPDM_DEFAULT_HEARTBEAT_PERIOD_IN_SEC) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pTmr = GPU_GET_TIMER(pGpu); + + // Create the timer event and schedule the first heartbeat callback + status = tmrEventCreate(pTmr, &pSpdm->pHeartbeatEvent, _spdmTriggerHeartbeat, pSpdm, TMR_FLAGS_NONE); + if (status != NV_OK) + { + return status; + } + + pSpdm->heartbeatPeriodSec = heartbeatPeriodSec; + status = tmrEventScheduleRelSec(pTmr, pSpdm->pHeartbeatEvent, pSpdm->heartbeatPeriodSec); + + // Tell GSP-RM to start expecting heartbeats. + portMemSet(¶ms, 0, sizeof(params)); + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL; + params.cmd.ccHeartbeatCtrl.bEnable = NV_TRUE; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Send/receive error in CC_HEARTBEAT_CTRL command! Status = 0x%0x\n", status); + return status; + } + + // Perform basic validation of header returned. + status = params.msg.status; + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: RPC returned failure in CC_HEARTBEAT_CTRL command! status = 0x%0x\n", + status); + DBG_BREAKPOINT(); + return status; + } + + return status; +} + +NV_STATUS +spdmUnregisterFromHeartbeats_GH100 +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + NV_STATUS status = NV_OK; + + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + RMTIMEOUT timeout; + NV2080_CTRL_INTERNAL_SPDM_PARTITION_PARAMS params; + + if (pSpdm->pHeartbeatEvent == NULL) + { + // No timer exists, we never started sending heartbeats. + return NV_OK; + } + + // Tell GSP-RM to stop expecting heartbeats. + portMemSet(¶ms, 0, sizeof(params)); + params.cmd.cmdType = RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL; + params.cmd.ccHeartbeatCtrl.bEnable = NV_FALSE; + + gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, 0); + status = spdmCtrlSpdmPartition(pGpu, ¶ms); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: Send/receive error in CC_HEARTBEAT_CTRL command! Status = 0x%0x\n", status); + goto ErrorExit; + } + + // Perform basic validation of header returned. + status = params.msg.status; + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "SPDM: RPC returned failure in CC_HEARTBEAT_CTRL command! status = 0x%0x\n", + status); + DBG_BREAKPOINT(); + goto ErrorExit; + } + +ErrorExit: + // In any case, cancel any further heartbeats that might occur. Handles NULL gracefully. + tmrEventCancel(pTmr, pSpdm->pHeartbeatEvent); + tmrEventDestroy(pTmr, pSpdm->pHeartbeatEvent); + pSpdm->pHeartbeatEvent = NULL; + pSpdm->heartbeatPeriodSec = 0; return status; } diff --git a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c index 3bca07a0d2..803f2b7fc6 100644 --- a/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c +++ b/src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_module.c @@ -32,6 +32,8 @@ #include "rmapi/client_resource.h" #include "gpu/conf_compute/ccsl.h" #include "gpu/conf_compute/conf_compute.h" +#include "spdm/rmspdmvendordef.h" +#include "objtmr.h" /* ------------------------- Macros and Defines ----------------------------- */ /* ------------------------- Static Functions ------------------------------ */ diff --git a/src/nvidia/src/kernel/gpu/spdm/spdm.c b/src/nvidia/src/kernel/gpu/spdm/spdm.c index fa2ebacba3..35f2632577 100644 --- a/src/nvidia/src/kernel/gpu/spdm/spdm.c +++ b/src/nvidia/src/kernel/gpu/spdm/spdm.c @@ -33,6 +33,12 @@ #include "spdm/rmspdmvendordef.h" #include "gpu/gpu.h" #include "gpu/gpu_resource.h" +#include "nvspdm_rmconfig.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "platform/sli/sli.h" +#include "rmapi/client_resource.h" +#include "gpu/bus/kern_bus.h" +#include "os/os.h" // // Libspdm only supported on certain builds, @@ -42,7 +48,7 @@ /* ------------------------ Static Function Prototypes --------------------- */ static void _spdmClearContext(Spdm *pSpdm); -libspdm_return_t _spdmAcquireTransportBuffer(void *context, size_t *max_msg_size, void **msg_buf_ptr); +libspdm_return_t _spdmAcquireTransportBuffer(void *context, void **msg_buf_ptr); void _spdmReleaseTransportBuffer(void *context, const void *msg_buf_ptr); bool _spdmVerifyCertChain(void *spdm_context, uint8_t slot_id, size_t cert_chain_size, const void *cert_chain, const void **trust_anchor, size_t *trust_anchor_size); @@ -57,8 +63,6 @@ _spdmClearContext Spdm *pSpdm ) { - NvU32 index = 0; - if (pSpdm == NULL) { return; @@ -71,18 +75,6 @@ _spdmClearContext // if (pSpdm->pLibspdmContext != NULL) { - - libspdm_reset_message_b(pSpdm->pLibspdmContext); - libspdm_reset_message_c(pSpdm->pLibspdmContext); - libspdm_reset_message_mut_b(pSpdm->pLibspdmContext); - libspdm_reset_message_mut_c(pSpdm->pLibspdmContext); - - libspdm_reset_message_m(pSpdm->pLibspdmContext, NULL); - for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) - { - libspdm_reset_message_m(pSpdm->pLibspdmContext, &(((libspdm_context_t *)pSpdm->pLibspdmContext)->session_info[index])); - } - libspdm_deinit_context(pSpdm->pLibspdmContext); libspdm_reset_context(pSpdm->pLibspdmContext); portMemSet((NvU8 *)pSpdm->pLibspdmContext, 0, pSpdm->libspdmContextSize); @@ -93,27 +85,34 @@ _spdmClearContext portMemSet((NvU8 *)pSpdm->pLibspdmScratch, 0, pSpdm->libspdmScratchSize); } + // memdescFree and memdescDestroy handle NULL gracefully. + memdescFree(pSpdm->pPayloadBufferMemDesc); + memdescDestroy(pSpdm->pPayloadBufferMemDesc); + + pSpdm->pPayloadBufferMemDesc = NULL; + pSpdm->payloadBufferSize = 0; + // portMemFree handles NULL pointers gracefully. portMemFree(pSpdm->pLibspdmContext); portMemFree(pSpdm->pLibspdmScratch); portMemFree(pSpdm->pAttestationCertChain); portMemFree(pSpdm->pDeviceIOContext); - portMemFree(pSpdm->pLastExchange); + portMemFree(pSpdm->pMsgLog); pSpdm->pLibspdmContext = NULL; pSpdm->pLibspdmScratch = NULL; pSpdm->pAttestationCertChain = NULL; pSpdm->pDeviceIOContext = NULL; - pSpdm->pLastExchange = NULL; + pSpdm->pMsgLog = NULL; pSpdm->libspdmContextSize = 0; pSpdm->libspdmScratchSize = 0; pSpdm->attestationCertChainSize = 0; - pSpdm->lastExchangeSize = 0; + pSpdm->msgLogMaxSize = 0; - pSpdm->guestId = 0; pSpdm->sessionId = INVALID_SESSION_ID; - pSpdm->endpointId = 0; + pSpdm->bSessionEstablished = NV_FALSE; + pSpdm->bUsePolling = NV_FALSE; } /* @@ -123,23 +122,20 @@ libspdm_return_t _spdmAcquireTransportBuffer ( void *context, - size_t *max_msg_size, void **msg_buf_ptr ) { - if (context == NULL || max_msg_size == NULL || msg_buf_ptr == NULL) + if (context == NULL || msg_buf_ptr == NULL) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - *msg_buf_ptr = portMemAllocNonPaged(LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + *msg_buf_ptr = portMemAllocNonPaged(NV_SPDM_SYSMEM_SURFACE_SIZE_IN_BYTES); if (*msg_buf_ptr == NULL) { return LIBSPDM_STATUS_BUFFER_FULL; } - *max_msg_size = LIBSPDM_MAX_MESSAGE_BUFFER_SIZE; - return LIBSPDM_STATUS_SUCCESS; } @@ -187,19 +183,24 @@ spdmConstruct_IMPL pSpdm->pLibspdmScratch = NULL; pSpdm->pAttestationCertChain = NULL; pSpdm->pDeviceIOContext = NULL; - pSpdm->pLastExchange = NULL; + pSpdm->pMsgLog = NULL; pSpdm->libspdmContextSize = 0; pSpdm->libspdmScratchSize = 0; pSpdm->attestationCertChainSize = 0; - pSpdm->lastExchangeSize = 0; + pSpdm->msgLogMaxSize = 0; - pSpdm->guestId = 0; pSpdm->sessionId = INVALID_SESSION_ID; - pSpdm->endpointId = 0; - + pSpdm->bSessionEstablished = NV_FALSE; + pSpdm->bUsePolling = NV_FALSE; pSpdm->bExportSecretCleared = NV_FALSE; + pSpdm->pPayloadBufferMemDesc = NULL; + pSpdm->payloadBufferSize = 0; + + pSpdm->pHeartbeatEvent = NULL; + pSpdm->heartbeatPeriodSec = 0; + return NV_OK; } @@ -215,6 +216,60 @@ spdmDestruct_IMPL _spdmClearContext(pSpdm); } +NV_STATUS +spdmSetupCommunicationBuffers_IMPL +( + OBJGPU *pGpu, + Spdm *pSpdm +) +{ + MemoryManager *pMemoryManager = NULL; + TRANSFER_SURFACE surf = {0}; + NV_STATUS status = NV_OK; + + // Create memory descriptor for payload buffer + status = memdescCreate(&pSpdm->pPayloadBufferMemDesc, pGpu, NV_SPDM_SYSMEM_SURFACE_SIZE_PAGE_ALIGNED, + NV_SPDM_SYSMEM_SURFACE_ALIGNMENT_IN_BYTES, NV_TRUE, ADDR_SYSMEM, + NV_MEMORY_CACHED, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY); + if (status != NV_OK || pSpdm->pPayloadBufferMemDesc == NULL) + { + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto ErrorExit; + } + + memdescTagAlloc(status, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_82, pSpdm->pPayloadBufferMemDesc); + if (status != NV_OK) + { + goto ErrorExit; + } + + // We over-allocate since we must allocate page-aligned. Set size only to what we will use. + pSpdm->payloadBufferSize = NV_SPDM_SYSMEM_SURFACE_SIZE_IN_BYTES; + + // Scrub surface + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) + pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + surf.offset = 0; + + surf.pMemDesc = pSpdm->pPayloadBufferMemDesc; + status = memmgrMemSet(pMemoryManager, &surf, 0, pSpdm->payloadBufferSize, TRANSFER_FLAGS_NONE); + if (status != NV_OK) + { + SLI_LOOP_GOTO(ErrorExit); + } + + SLI_LOOP_END + +ErrorExit: + + if (status != NV_OK) + { + _spdmClearContext(pSpdm); + } + + return status; +} + NV_STATUS spdmContextInit_IMPL ( @@ -232,6 +287,14 @@ spdmContextInit_IMPL uint16_t dheGroup; uint16_t aeadSuite; uint16_t keySched; + uint32_t maxSessionCount; + uint8_t maxRetries; + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + uint16_t reqAsymAlgo; + NvU8 *pEncapCertChain; + NvU32 encapCertChainSize; +#endif if (pGpu == NULL || pSpdm == NULL) { @@ -251,29 +314,28 @@ spdmContextInit_IMPL portMemSet(pSpdm->pLibspdmContext, 0, pSpdm->libspdmContextSize); libspdm_init_context(pSpdm->pLibspdmContext); - // Allocate scratch space required for libspdm processing. - pSpdm->libspdmScratchSize = libspdm_get_sizeof_required_scratch_buffer(pSpdm->pLibspdmContext); - pSpdm->pLibspdmScratch = portMemAllocNonPaged(pSpdm->libspdmScratchSize); - if (pSpdm->libspdmScratchSize == 0 || pSpdm->pLibspdmScratch == NULL) + // Allocate message transcript recording buffer. + pSpdm->pMsgLog = portMemAllocNonPaged(NV_SPDM_MAX_TRANSCRIPT_BUFFER_SIZE); + pSpdm->msgLogMaxSize = NV_SPDM_MAX_TRANSCRIPT_BUFFER_SIZE; + + if (pSpdm->pMsgLog == NULL) { - status = NV_ERR_NO_MEMORY; + pSpdm->msgLogMaxSize = 0; + status = NV_ERR_NO_MEMORY; goto ErrorExit; } - portMemSet(pSpdm->pLibspdmScratch, 0, pSpdm->libspdmScratchSize); - libspdm_set_scratch_buffer(pSpdm->pLibspdmContext, pSpdm->pLibspdmScratch, - pSpdm->libspdmScratchSize); - - // Allocate message transcript recording buffer. - pSpdm->pLastExchange = portMemAllocNonPaged(SPDM_MAX_EXCHANGE_BUFFER_SIZE); - pSpdm->lastExchangeSize = 0; +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + // Get requester cert chain for mutual authentication process. + status = spdmGetReqEncapCertificates_HAL(pGpu, pSpdm, &pEncapCertChain, &encapCertChainSize); - if (pSpdm->pLastExchange == NULL) + if (status != NV_OK) { - status = NV_ERR_NO_MEMORY; + status = NV_ERR_NOT_SUPPORTED; goto ErrorExit; } +#endif // // Eventually, owner of Spdm object may want to set their own @@ -283,20 +345,32 @@ spdmContextInit_IMPL parameter.location = LIBSPDM_DATA_LOCATION_LOCAL; // Requester will not check Responder's timing, set to maximum value. - ctExponent = SPDM_CAPABILITIES_CT_EXPONENT_MAX; + ctExponent = LIBSPDM_MAX_CT_EXPONENT; CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_CAPABILITY_CT_EXPONENT, ¶meter, &ctExponent, sizeof(ctExponent))); +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + capFlags = SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCAP_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MUT_AUTH_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HBEAT_CAP; +#else capFlags = SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP | SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP | SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP | - SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP; + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP | + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HBEAT_CAP; +#endif CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_CAPABILITY_FLAGS, ¶meter, &capFlags, sizeof(capFlags))); - measSpec = SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF; + measSpec = SPDM_MEASUREMENT_SPECIFICATION_DMTF; CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_MEASUREMENT_SPEC, ¶meter, &measSpec, sizeof(measSpec))); @@ -323,7 +397,38 @@ spdmContextInit_IMPL CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_KEY_SCHEDULE, ¶meter, &keySched, sizeof(keySched))); - pSpdm->guestId = 0x01; +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + reqAsymAlgo = SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_REQ_BASE_ASYM_ALG, + ¶meter, &reqAsymAlgo, + sizeof(reqAsymAlgo))); + + // + // Set certification for encapsulated command process. + // Specify certificate location, passing slot number as well. + // + parameter.additional_data[0] = SPDM_CERT_DEFAULT_SLOT_ID; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN, + ¶meter, pEncapCertChain, + encapCertChainSize)); +#endif + + // Ensure that we set only DHE sessions as allowed, not PSK sessions. + maxSessionCount = 1; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_MAX_DHE_SESSION_COUNT, + ¶meter, &maxSessionCount, sizeof(maxSessionCount))); + + maxSessionCount = 0; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_MAX_PSK_SESSION_COUNT, + ¶meter, &maxSessionCount, sizeof(maxSessionCount))); + + + // We don't allow SPDM message retries. + maxRetries = 0; + CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_REQUEST_RETRY_TIMES, + ¶meter, &maxRetries, sizeof(maxRetries))); + + libspdm_init_msg_log(pSpdm->pLibspdmContext, pSpdm->pMsgLog, pSpdm->msgLogMaxSize); // // Perform any device-specific initialization. spdmDeviceInit is also @@ -336,15 +441,36 @@ spdmContextInit_IMPL } libspdm_register_device_buffer_func(pSpdm->pLibspdmContext, + NV_SPDM_SYSMEM_SURFACE_SIZE_IN_BYTES, NV_SPDM_SYSMEM_SURFACE_SIZE_IN_BYTES, _spdmAcquireTransportBuffer, _spdmReleaseTransportBuffer, _spdmAcquireTransportBuffer, _spdmReleaseTransportBuffer); + // + // Allocate scratch space required for libspdm processing. + // We need to wait for transport layer initialization (i.e. after device init) + // in order to properly calculate the required scratch size. + // + pSpdm->libspdmScratchSize = libspdm_get_sizeof_required_scratch_buffer(pSpdm->pLibspdmContext); + pSpdm->pLibspdmScratch = portMemAllocNonPaged(pSpdm->libspdmScratchSize); + if (pSpdm->libspdmScratchSize == 0 || pSpdm->pLibspdmScratch == NULL) + { + status = NV_ERR_NO_MEMORY; + goto ErrorExit; + } + + portMemSet(pSpdm->pLibspdmScratch, 0, pSpdm->libspdmScratchSize); + libspdm_set_scratch_buffer(pSpdm->pLibspdmContext, pSpdm->pLibspdmScratch, + pSpdm->libspdmScratchSize); + // // Verifier is responsible for verifying the certificate chain. To avoid concerns // with libspdm compatibility, override certificate validation function with stub. // libspdm_register_verify_spdm_cert_chain_func(pSpdm->pLibspdmContext, _spdmVerifyCertChain); + // Initialize session message count to zero. + pSpdm->sessionMsgCount = 0; + ErrorExit: // Clear all SPDM state on failure. @@ -364,7 +490,7 @@ spdmContextDeinit_IMPL NvBool bForceClear ) { - NV_STATUS status = NV_OK; + NV_STATUS status = NV_OK; if (pGpu == NULL || pSpdm == NULL) { @@ -378,6 +504,13 @@ spdmContextDeinit_IMPL return NV_OK; } + // + // Make sure to unregister heartbeats in case we didn't + // hit normal teardown path. Best effort attempt. + // + status = spdmUnregisterFromHeartbeats(pGpu, pSpdm); + NV_ASSERT_OK(status); + // // End the session by deinitializing the Responder. // We don't send END_SESSION as Responder will handle teardown. @@ -452,23 +585,35 @@ spdmStart_IMPL // if (spdmDeviceSecuredSessionSupported_HAL(pGpu, pSpdm) == NV_OK) { + NvU8 heartbeatPeriodInSec = 0; + NV_PRINTF(LEVEL_INFO, "SPDM: Attempting to establish SPDM session.\n"); - CHECK_SPDM_STATUS(libspdm_start_session(pSpdm->pLibspdmContext, NV_FALSE, + CHECK_SPDM_STATUS(libspdm_start_session(pSpdm->pLibspdmContext, NV_FALSE, NULL, 0, SPDM_KEY_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH, - SPDM_CERT_DEFAULT_SLOT_ID, 0, &pSpdm->sessionId, NULL, NULL)); - - + SPDM_CERT_DEFAULT_SLOT_ID, 0, &pSpdm->sessionId, + &heartbeatPeriodInSec, NULL)); if (!nvspdm_check_and_clear_libspdm_assert()) { NV_PRINTF(LEVEL_ERROR, "SPDM: libspdm_start_session() assert hit !!!.\n"); - status = NV_ERR_GENERIC; + status = NV_ERR_GENERIC; goto ErrorExit; } - else + else if (heartbeatPeriodInSec != SPDM_DEFAULT_HEARTBEAT_PERIOD_IN_SEC) { - NV_PRINTF(LEVEL_INFO, "SPDM: Session establishment successful: sessionId 0x%x.\n", - pSpdm->sessionId); + // + // Do a basic check to make sure the SPDM heartbeat period agreed between + // Requester and Responder is expected, even if it is overridden via regkey. + // + NV_PRINTF(LEVEL_ERROR, "SPDM: Responder returned unexpected heartbeat 0x%x\n", + heartbeatPeriodInSec); + status = NV_ERR_NOT_SUPPORTED; + goto ErrorExit; } + + NV_PRINTF(LEVEL_INFO, "SPDM: Session establishment successful: sessionId 0x%x.\n", + pSpdm->sessionId); + pSpdm->bSessionEstablished = NV_TRUE; + pSpdm->bUsePolling = NV_FALSE; } ErrorExit: @@ -479,7 +624,8 @@ spdmStart_IMPL // if (status != NV_OK) { - pSpdm->sessionId = INVALID_SESSION_ID; + pSpdm->sessionId = INVALID_SESSION_ID; + pSpdm->bSessionEstablished = NV_FALSE; NV_PRINTF(LEVEL_ERROR, "SPDM: Session establishment failed!\n"); DBG_BREAKPOINT(); } @@ -506,8 +652,7 @@ spdmRetrieveExportSecret_IMPL } // Ensure we are in valid state. Note that export master secret can only be retrieved once. - if (pSpdm->pLibspdmContext == NULL || pSpdm->sessionId == INVALID_SESSION_ID || - pSpdm->bExportSecretCleared) + if (pSpdm->pLibspdmContext == NULL || !pSpdm->bSessionEstablished || pSpdm->bExportSecretCleared) { return NV_ERR_NOT_READY; } @@ -535,4 +680,3 @@ spdmRetrieveExportSecret_IMPL return NV_OK; } - diff --git a/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c b/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c index c186920639..84a9d0c5ae 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c +++ b/src/nvidia/src/kernel/gpu/subdevice/generic_engine.c @@ -25,7 +25,6 @@ #include "os/os.h" #include "gpu/gpu.h" #include "gpu/subdevice/generic_engine.h" -#include "gpu/subdevice/subdevice.h" #include "rmapi/client.h" #include diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c index 91aed43984..d8b6305f88 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c @@ -34,6 +34,7 @@ #include "resserv/rs_resource.h" #include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" +#include "gpu_mgr/gpu_mgr.h" #include "vgpu/rpc.h" #include "core/locks.h" @@ -195,6 +196,9 @@ subdeviceDestruct_IMPL subdeviceRestoreLockedClock(pSubdevice, pCallContext); + // Decrement the reference count for VF if previously incremented. + subdeviceRestoreVF(pSubdevice, pCallContext); + // Restore GR tick frequency to default. subdeviceRestoreGrTickFreq(pSubdevice, pCallContext); @@ -247,6 +251,54 @@ subdeviceControlFilter_IMPL(Subdevice *pSubdevice, CALL_CONTEXT *pCallContext, RS_RES_CONTROL_PARAMS_INTERNAL *pParams) { + RmCtrlParams *pRmCtrlParams = pParams->pLegacyParams; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + if (IS_VIRTUAL(pGpu)) + { + // For vGPU proceed with RM ctrls supported on host OS. + switch (DRF_VAL(XXXX, _CTRL_CMD, _CATEGORY, pRmCtrlParams->cmd)) + { + case NV2080_CTRL_ACR: + case NV2080_CTRL_LPWR: + case NV2080_CTRL_SPI: + case NV2080_CTRL_VOLT: + case NV2080_CTRL_POWER: + case NV2080_CTRL_PMGR: + return NV_ERR_NOT_SUPPORTED; + break; + case NV2080_CTRL_NVLINK: + switch (pRmCtrlParams->cmd) + { + case NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS: + case NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS: + break; + + default: + return NV_ERR_NOT_SUPPORTED; + break; + } + break; + case NV2080_CTRL_PERF: + switch (pRmCtrlParams->cmd) + { + case NV2080_CTRL_CMD_PERF_BOOST: + case NV2080_CTRL_CMD_PERF_NOTIFY_VIDEOEVENT: + case NV2080_CTRL_CMD_PERF_GET_CURRENT_PSTATE: + case NV2080_CTRL_CMD_PERF_GET_LEVEL_INFO: + case NV2080_CTRL_CMD_PERF_GET_VID_ENG_PERFMON_SAMPLE: + case NV2080_CTRL_CMD_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2: + case NV2080_CTRL_CMD_PERF_GET_POWERSTATE: + case NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL: + break; + + default: + return NV_ERR_NOT_SUPPORTED; + break; + } + break; + } + } return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c index f6f4c8f3e9..d71c2e1464 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c @@ -38,6 +38,7 @@ #include "rmapi/rs_utils.h" #include "mem_mgr/mem.h" #include "gpu/mem_mgr/virt_mem_allocator_common.h" +#include "gpu/gsp/gsp_trace_rats_macro.h" // // EVENT RM SubDevice Controls @@ -307,3 +308,36 @@ subdeviceCtrlCmdEventVideoBindEvtbuf_IMPL pParams->eventFilter); return status; } + + +NV_STATUS +subdeviceCtrlCmdEventGspTraceRatsBindEvtbuf_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_EVENT_RATS_GSP_TRACE_BIND_EVTBUF_PARAMS *pParams +) +{ + NV_STATUS status = NV_ERR_NOT_SUPPORTED; +#if KERNEL_GSP_TRACING_RATS_ENABLED + RsClient *pClient = RES_GET_CLIENT(pSubdevice); + RsResourceRef *pEventBufferRef = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + NvHandle hNotifier = RES_GET_HANDLE(pSubdevice); + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + NV_ASSERT_OK_OR_RETURN(serverutilGetResourceRefWithType(hClient, + pParams->hEventBuffer, + classId(EventBuffer), + &pEventBufferRef)); + status = gspTraceAddBindpoint(pGpu, + pClient, + pEventBufferRef, + hNotifier, + pParams->tracepointMask, + pParams->gspLoggingBufferSize, + pParams->gspLoggingBufferWatermark); +#endif + return status; +} diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c index c7e5294639..fef50a4cbc 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_fla.c @@ -250,7 +250,21 @@ subdeviceCtrlCmdFlaGetRange_IMPL NV2080_CTRL_FLA_GET_RANGE_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelBus *pKernelBus = GPU_GET_KERNEL_BUS(pGpu); + NvBool bIsConntectedToNvswitch; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pKernelNvlink != NULL, NV_ERR_NOT_SUPPORTED); + bIsConntectedToNvswitch = knvlinkIsGpuConnectedToNvswitch(pGpu, pKernelNvlink); + } + + NV_CHECK_OR_RETURN(LEVEL_ERROR, kbusIsFlaSupported(pKernelBus), NV_ERR_NOT_SUPPORTED); + + return kbusGetFlaRange_HAL(pGpu, pKernelBus, &pParams->base, &pParams->size, bIsConntectedToNvswitch); } NV_STATUS diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index f1f4930e5e..c3b753cb72 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -39,6 +39,7 @@ #include "gpu/bif/kernel_bif.h" #include "gpu/bus/kern_bus.h" #include "gpu/disp/kern_disp.h" +#include "disp/nvfbc_session.h" #include "gpu/mmu/kern_gmmu.h" #include "kernel/gpu/intr/intr.h" #include "kernel/gpu/mc/kernel_mc.h" @@ -53,6 +54,7 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/nvenc/nvencsession.h" #include "kernel/gpu/fifo/kernel_fifo.h" #include "rmapi/resource_fwd_decls.h" @@ -62,17 +64,17 @@ +// bit to set when telling physical to fill in an info entry +#define INDEX_FORWARD_TO_PHYSICAL 0x80000000 + static NV_STATUS getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, NvBool bCanAccessHw) { - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NV_STATUS status = NV_OK; - NvU32 i = 0; - NvU32 data = 0; - NvBool bGspForward = NV_FALSE; - - // bit to set when telling GSP to fill in an info entry - const NvU32 indexForwardToGsp = 0x80000000; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NV_STATUS status = NV_OK; + NvU32 i = 0; + NvU32 data = 0; + NvBool bPhysicalForward = NV_FALSE; if ((pParams->gpuInfoListSize > NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE) || (pParams->gpuInfoListSize == 0)) @@ -189,9 +191,18 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, if (IS_VIRTUAL(pGpu)) { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + if ((pKernelMIGManager == NULL) || !kmigmgrIsMIGSupported(pGpu, pKernelMIGManager)) + { + data = NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_UNSUPPORTED; + break; + } + data = IS_MIG_ENABLED(pGpu) ? NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED : NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLED; + break; } @@ -263,7 +274,27 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } case NV2080_CTRL_GPU_INFO_INDEX_NVENC_STATS_REPORTING_STATE: { - data = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED; + if (IS_VIRTUAL(pGpu)) + { + // On vGPU, if encoding is supported then we need to keep the NvEnc stats reporting state enabled + // all the time so that NvEnc UMD keeps pushing the raw timestamp data. + // This is to handle the migration case where on source host the NvEnc stats reporting was disabled, + // but on target host the NvEnc stats reporting is enabled. If UMD doesn't keep pushing raw data + // even if stats reporting was disabled on source host, we won't be able to report NvEnc stats on + // target host data reporting is enabled. + if (pGpu->encSessionStatsReportingState == NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED) + { + data = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED; + } + else + { + data = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED; + } + } + else + { + data = pGpu->encSessionStatsReportingState; + } break; } case NV2080_CTRL_GPU_INFO_INDEX_4K_PAGE_ISOLATION_REQUIRED: @@ -304,6 +335,21 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } case NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY: { + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if (pVSI) + { + data = pVSI->vgpuStaticProperties.bProfilingTracingEnabled ? + NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED : + NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED; + } + else + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_DISABLED; + } + } + else { // Always return ENABLED for Baremetal/Host data = NV2080_CTRL_GPU_INFO_INDEX_GPU_PROFILING_CAPABILITY_ENABLED; @@ -312,6 +358,21 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } case NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY: { + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if (pVSI) + { + data = pVSI->vgpuStaticProperties.bDebuggingEnabled ? + NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED : + NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED; + } + else + { + data = NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_DISABLED; + } + } + else { // Always return ENABLED for Baremetal/Host data = NV2080_CTRL_GPU_INFO_INDEX_GPU_DEBUGGING_CAPABILITY_ENABLED; @@ -384,11 +445,11 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } default: { - // Only forward to GSP if we're in the HW-access-enabled control - if (IS_GSP_CLIENT(pGpu) && bCanAccessHw) + // Only forward to physical if we're in the HW-access-enabled control + if ((IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu)) && bCanAccessHw) { - pParams->gpuInfoList[i].index |= indexForwardToGsp; - bGspForward = NV_TRUE; + pParams->gpuInfoList[i].index |= INDEX_FORWARD_TO_PHYSICAL; + bPhysicalForward = NV_TRUE; } else { @@ -399,24 +460,29 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } } + if (status != NV_OK) + { + break; + } + // save off data value pParams->gpuInfoList[i].data = data; } - if (IS_GSP_CLIENT(pGpu) && bGspForward && (status == NV_OK)) + if ((IS_GSP_CLIENT(pGpu) || IS_VIRTUAL(pGpu)) && bPhysicalForward && (status == NV_OK)) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - - return pRmApi->Control(pRmApi, - RES_GET_CLIENT_HANDLE(pSubdevice), - RES_GET_HANDLE(pSubdevice), - NV2080_CTRL_CMD_GPU_GET_INFO_V2, - pParams, sizeof(*pParams)); + NV_RM_RPC_CONTROL(pGpu, + RES_GET_CLIENT_HANDLE(pSubdevice), + RES_GET_HANDLE(pSubdevice), + NV2080_CTRL_CMD_GPU_GET_INFO_V2, + pParams, sizeof(*pParams), status); } return status; } +#undef INDEX_FORWARD_TO_PHYSICAL + NV_STATUS subdeviceCtrlCmdGpuGetInfoV2_IMPL ( @@ -727,6 +793,8 @@ subdeviceCtrlCmdGpuGetEncoderCapacity_IMPL { NV_STATUS rmStatus = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + NvHandle hObject = RES_GET_HANDLE(pSubdevice); LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); @@ -745,6 +813,19 @@ subdeviceCtrlCmdGpuGetEncoderCapacity_IMPL pEncoderCapacityParams->encoderCapacity = NV_ENC_CAPACITY_MAX_VALUE; + // + // vGPU: Since vGPU does all real hardware management + // in the host, there is nothing to do at this point in + // the guest OS (where IS_VIRTUAL(pGpu) is true). + // + if (IS_VIRTUAL(pGpu)) // Otherwise default for vGPU host/baremetal/NMOS/GSP_CLIENT + { + NV_RM_RPC_GET_ENCODER_CAPACITY(pGpu, + hClient, + hObject, + &pEncoderCapacityParams->encoderCapacity, + rmStatus); + } return rmStatus; } @@ -761,9 +842,57 @@ subdeviceCtrlCmdGpuGetNvencSwSessionStats_IMPL NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_STATS_PARAMS *pParams ) { - pParams->encoderSessionCount = 0; - pParams->averageEncodeFps = 0; - pParams->averageEncodeLatency = 0; + + NvU32 averageEncodeFps = 0, averageEncodeLatency = 0; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvencSession *pNvencSession = NULL; + PNVENC_SESSION_LIST_ITEM pNvencSessionListItem = NULL; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + // + // For GSP vGPU host, get the data from GSP RM for CPU RM and it's client + // + if (IS_GSP_CLIENT(pGpu) && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + return pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); + } + + if (listCount(&(pGpu->nvencSessionList)) == 0) + { + pParams->encoderSessionCount = 0; + pParams->averageEncodeFps = 0; + pParams->averageEncodeLatency = 0; + return NV_OK; + } + + pParams->encoderSessionCount = listCount(&(pGpu->nvencSessionList)); + + for (pNvencSessionListItem = listHead(&(pGpu->nvencSessionList)); + pNvencSessionListItem != NULL; + pNvencSessionListItem = listNext(&(pGpu->nvencSessionList), pNvencSessionListItem)) + { + if (pNvencSessionListItem->sessionPtr) + { + pNvencSession = pNvencSessionListItem->sessionPtr; + + averageEncodeFps += pNvencSession->nvencSessionEntry.averageEncodeFps; + averageEncodeLatency += pNvencSession->nvencSessionEntry.averageEncodeLatency; + } + } + + // average FPS and latency over all active sessions on this GPU. + pParams->averageEncodeFps = averageEncodeFps / listCount(&(pGpu->nvencSessionList)); + pParams->averageEncodeLatency = averageEncodeLatency / listCount(&(pGpu->nvencSessionList)); return NV_OK; } @@ -778,6 +907,51 @@ _subdeviceCtrlCmdGpuGetNvencSwSessionInfo ) { + NvencSession *pNvencSession = NULL; + PNVENC_SESSION_LIST_ITEM pNvencSessionListItem = NULL; + NvU32 i = 0; + NV2080_CTRL_NVENC_SW_SESSION_INFO *pSession; + + NV_ASSERT_OR_RETURN(sessionInfoTblEntry == + NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES, + NV_ERR_INVALID_ARGUMENT); + + portMemSet(pSessionInfo, 0, sizeof(NV2080_CTRL_NVENC_SW_SESSION_INFO) * sessionInfoTblEntry); + + for (pNvencSessionListItem = listHead(&(pGpu->nvencSessionList)); + pNvencSessionListItem != NULL; + pNvencSessionListItem = listNext(&(pGpu->nvencSessionList), pNvencSessionListItem)) + { + if (pNvencSessionListItem->sessionPtr) + { + pNvencSession = pNvencSessionListItem->sessionPtr; + pSession = &pSessionInfo[i]; + + pSession->sessionId = pNvencSession->nvencSessionEntry.sessionId; + pSession->processId = pNvencSession->nvencSessionEntry.processId; + pSession->subProcessId = pNvencSession->nvencSessionEntry.subProcessId; + pSession->codecType = pNvencSession->nvencSessionEntry.codecType; + pSession->hResolution = pNvencSession->nvencSessionEntry.hResolution; + pSession->vResolution = pNvencSession->nvencSessionEntry.vResolution; + pSession->averageEncodeFps = pNvencSession->nvencSessionEntry.averageEncodeFps; + pSession->averageEncodeLatency = pNvencSession->nvencSessionEntry.averageEncodeLatency; + + i++; + + if (i == NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES) + { + // Stop copying beyond max size otherwise we might corrupt other kernel data + break; + } + } + } + + // + // Copy the data only if sessionInfoTbl entry is equals or greater + // than current active sessions i.e. listCount(&(pGpu->nvencSessionList)) + // + *entryCount = i; + return NV_OK; } @@ -796,7 +970,29 @@ subdeviceCtrlCmdGpuGetNvencSwSessionInfo_IMPL ) { NV_STATUS status = NV_OK; - pParams->sessionInfoTblEntry = 0; + NV2080_CTRL_NVENC_SW_SESSION_INFO *pSessionInfo = NvP64_VALUE(pParams->sessionInfoTbl); + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvU32 entryCount = 0; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + if ((!IS_VIRTUAL(pGpu)) && (pGpu->encSessionStatsReportingState != NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED)) + { + pParams->sessionInfoTblEntry = 0; + return status; + } + + if (pParams->sessionInfoTbl == NvP64_NULL || listCount(&(pGpu->nvencSessionList)) == 0) + { + pParams->sessionInfoTblEntry = listCount(&(pGpu->nvencSessionList)); + return status; + } + + status = _subdeviceCtrlCmdGpuGetNvencSwSessionInfo(pGpu, pParams->sessionInfoTblEntry, pSessionInfo, &entryCount); + if (status != NV_OK) + return status; + + pParams->sessionInfoTblEntry = entryCount; return status; } @@ -809,7 +1005,29 @@ subdeviceCtrlCmdGpuGetNvencSwSessionInfoV2_IMPL ) { NV_STATUS status = NV_OK; - pParams->sessionInfoTblEntry = 0; + NV2080_CTRL_NVENC_SW_SESSION_INFO *pSessionInfo = pParams->sessionInfoTbl; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvU32 entryCount = 0; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + if ((!IS_VIRTUAL(pGpu)) && (pGpu->encSessionStatsReportingState != NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED)) + { + pParams->sessionInfoTblEntry = 0; + return status; + } + + if (pParams->sessionInfoTblEntry == 0 || listCount(&(pGpu->nvencSessionList)) == 0) + { + pParams->sessionInfoTblEntry = listCount(&(pGpu->nvencSessionList)); + return status; + } + + status = _subdeviceCtrlCmdGpuGetNvencSwSessionInfo(pGpu, pParams->sessionInfoTblEntry, pSessionInfo, &entryCount); + if (status != NV_OK) + return status; + + pParams->sessionInfoTblEntry = entryCount; return status; } @@ -827,9 +1045,42 @@ subdeviceCtrlCmdGpuGetNvfbcSwSessionStats_IMPL NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_STATS_PARAMS *pParams ) { - pParams->sessionCount = 0; - pParams->averageFPS = 0; - pParams->averageLatency = 0; + + NvU32 averageFPS = 0, averageLatency = 0, localSessionCount = 0; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvfbcSession *pNvfbcSession = NULL; + PNVFBC_SESSION_LIST_ITEM pNvfbcSessionListItem = NULL; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + if (listCount(&(pGpu->nvfbcSessionList)) == 0) + { + pParams->sessionCount = 0; + pParams->averageFPS = 0; + pParams->averageLatency = 0; + return NV_OK; + } + + for (pNvfbcSessionListItem = listHead(&(pGpu->nvfbcSessionList)); + pNvfbcSessionListItem != NULL; + pNvfbcSessionListItem = listNext(&(pGpu->nvfbcSessionList), pNvfbcSessionListItem)) + { + if (pNvfbcSessionListItem->sessionPtr) + { + pNvfbcSession = pNvfbcSessionListItem->sessionPtr; + + averageFPS += pNvfbcSession->nvfbcSessionEntry.averageFPS; + averageLatency += pNvfbcSession->nvfbcSessionEntry.averageLatency; + + localSessionCount++; + } + } + + // average FPS and latency over all active sessions on this GPU. + pParams->averageFPS = localSessionCount == 0 ? 0 : (averageFPS / localSessionCount); + pParams->averageLatency = localSessionCount == 0 ? 0 : (averageLatency / localSessionCount); + + pParams->sessionCount = localSessionCount; return NV_OK; } @@ -848,7 +1099,68 @@ subdeviceCtrlCmdGpuGetNvfbcSwSessionInfo_IMPL NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS *pParams ) { - pParams->sessionInfoCount = 0; + + NV2080_CTRL_NVFBC_SW_SESSION_INFO *pSession, *pSessionInfo = pParams->sessionInfoTbl; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvU32 i = 0; + NvfbcSession *pNvfbcSession = NULL; + PNVFBC_SESSION_LIST_ITEM pNvfbcSessionListItem = NULL; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + portMemSet(pParams, 0, sizeof(NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS)); + + for (pNvfbcSessionListItem = listHead(&(pGpu->nvfbcSessionList)); + pNvfbcSessionListItem != NULL; + pNvfbcSessionListItem = listNext(&(pGpu->nvfbcSessionList), pNvfbcSessionListItem)) + { + if (pNvfbcSessionListItem->sessionPtr) + { + pNvfbcSession = pNvfbcSessionListItem->sessionPtr; + pSession = &pSessionInfo[i]; + + pSession->processId = pNvfbcSession->nvfbcSessionEntry.processId; + pSession->vgpuInstanceId = pNvfbcSession->nvfbcSessionEntry.vgpuInstanceId; + pSession->sessionId = pNvfbcSession->nvfbcSessionEntry.sessionId; + pSession->displayOrdinal = pNvfbcSession->nvfbcSessionEntry.displayOrdinal; + pSession->sessionType = pNvfbcSession->nvfbcSessionEntry.sessionType; + pSession->sessionFlags = pNvfbcSession->nvfbcSessionEntry.sessionFlags; + pSession->hMaxResolution = pNvfbcSession->nvfbcSessionEntry.hMaxResolution; + pSession->vMaxResolution = pNvfbcSession->nvfbcSessionEntry.vMaxResolution; + + // All the following fields are dynamic fields. + // We will return these as 0 if these are stale values. + if (nvfbcIsSessionDataStale(pNvfbcSession->nvfbcSessionEntry.lastUpdateTimeStamp)) + { + pSession->hResolution = 0; + pSession->vResolution = 0; + pSession->averageFPS = 0; + pSession->averageLatency = 0; + } + else + { + pSession->hResolution = pNvfbcSession->nvfbcSessionEntry.hResolution; + pSession->vResolution = pNvfbcSession->nvfbcSessionEntry.vResolution; + pSession->averageFPS = pNvfbcSession->nvfbcSessionEntry.averageFPS; + pSession->averageLatency = pNvfbcSession->nvfbcSessionEntry.averageLatency; + } + + i++; + + if (i == NV2080_GPU_NVFBC_MAX_SESSION_COUNT) + { + NV_ASSERT(0); + NV_PRINTF(LEVEL_ERROR, + "more entries in pGpu->nvencSessionList than " + "NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES\n"); + + // Stop copying beyond max size otherwise we might corrupt other kernel data. + break; + } + } + } + + pParams->sessionInfoCount = i; return NV_OK; } @@ -1526,23 +1838,20 @@ subdeviceCtrlCmdGpuSetComputeModeRules_IMPL if (IS_GSP_CLIENT(pGpu)) { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); RmCtrlParams *pRmCtrlParams = pCallContext->pControlParams; - NV_STATUS status = NV_OK; - - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); // // Client RM still needs to set its value and update the registry, // so don't return unless there was an error. // - NV_ASSERT_OK_OR_RETURN(status); + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize)); } //TODO Bug 2718406 will extend compute mode support for MIG @@ -1551,6 +1860,15 @@ subdeviceCtrlCmdGpuSetComputeModeRules_IMPL return NV_ERR_NOT_SUPPORTED; } + // Setting compute mode for cuda non supported vGPU profiles + // is not supported. + // Exclude GSP environment for that rule. + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if (pVSI && !IS_GSP_CLIENT(pGpu) && pVSI->vgpuConfig.cudaEnabled == 0) + { + return NV_ERR_NOT_SUPPORTED; + } + switch(pSetRulesParams->rules) { case NV2080_CTRL_GPU_COMPUTE_MODE_RULES_NONE: @@ -1601,6 +1919,17 @@ subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + // + // vGPU specific check to assign compute mode as 'Prohibited' + // for cuda non supported vGPU profiles. + // Exclude GSP environment for that rule. + // + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if ((pVSI != NULL) && !IS_GSP_CLIENT(pGpu) && (pVSI->vgpuConfig.cudaEnabled == 0)) + { + pQueryRulesParams->rules = NV2080_CTRL_GPU_COMPUTE_MODE_RULES_COMPUTE_PROHIBITED; + } + else { pQueryRulesParams->rules = pGpu->computeModeRules; } @@ -2058,6 +2387,15 @@ subdeviceCtrlCmdGpuGetMaxSupportedPageSize_IMPL // Default to minimal page size (4k) pParams->maxSupportedPageSize = RM_PAGE_SIZE; + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + pParams->maxSupportedPageSize = pVSI->maxSupportedPageSize; + + return status; + } + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); if (kgmmuIsPageSize512mbSupported(pKernelGmmu)) @@ -2477,14 +2815,13 @@ subdeviceCtrlCmdGpuGetGfid_IMPL * NV_ERR_IN_USE If MAX_NUM_P2P_GFIDS have already been enabled for P2P */ NV_STATUS -subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL +gpuUpdateGfidP2pCapability ( - Subdevice *pSubdevice, + OBJGPU *pGpu, NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS *pParams ) { OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); PSRIOV_P2P_INFO pP2PInfo = pGpu->sriovState.pP2PInfo; NvBool bSetP2PAccess = NV_FALSE; NvU32 idx; @@ -2554,6 +2891,15 @@ subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL return NV_OK; } +NV_STATUS +subdeviceCtrlCmdUpdateGfidP2pCapability_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_GPU_UPDATE_GFID_P2P_CAPABILITY_PARAMS *pParams +) +{ + return gpuUpdateGfidP2pCapability(GPU_RES_GET_GPU(pSubdevice), pParams); +} /* * Set the EGM fabric base address */ @@ -2671,6 +3017,10 @@ _convertGpuFabricProbeInfoCaps case NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2: { fabricCaps |= NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_SUPPORTED; +#ifdef NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED + fabricCaps |= + NV2080_CTRL_GPU_FABRIC_PROBE_CAP_MC_MUTLINODE_SUPPORTED; +#endif break; } default: @@ -2696,16 +3046,26 @@ subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL NvU64 numProbeReqs = 0; NvU64 fmCaps = 0; NvUuid *pClusterUuid = (NvUuid*) pParams->clusterUuid; + NvU32 mask = 0, healthMask = 0; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - if (pGpu->pGpuFabricProbeInfoKernel == NULL) + // Probe is not supported - Ex - Direct connected etc. + if (!gpuFabricProbeIsSupported(pGpu)) { pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_UNSUPPORTED; return NV_OK; } + // Probe is not supported - Ex - GPU is degraded etc. + if (pGpu->pGpuFabricProbeInfoKernel == NULL) + { + pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE; + pParams->status = NV_ERR_NOT_SUPPORTED; // Due to degradation etc. + return NV_OK; + } + status = gpuFabricProbeGetNumProbeReqs(pGpu->pGpuFabricProbeInfoKernel, &numProbeReqs); if (status != NV_OK) @@ -2718,31 +3078,217 @@ subdeviceCtrlCmdGetGpuFabricProbeInfo_IMPL NV2080_CTRL_GPU_FABRIC_PROBE_STATE_NOT_STARTED : NV2080_CTRL_GPU_FABRIC_PROBE_STATE_IN_PROGRESS; - if (gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfoKernel)) + if (!gpuFabricProbeIsReceived(pGpu->pGpuFabricProbeInfoKernel)) { - pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE; - pParams->status = gpuFabricProbeGetFmStatus(pGpu->pGpuFabricProbeInfoKernel); - if (pParams->status != NV_OK) + return NV_OK; + } + + pParams->state = NV2080_CTRL_GPU_FABRIC_PROBE_STATE_COMPLETE; + pParams->status = gpuFabricProbeGetFmStatus(pGpu->pGpuFabricProbeInfoKernel); + if (pParams->status != NV_OK) + { + // Nothing needs to be done as probe response status is not success + return NV_OK; + } + + ct_assert(NV2080_GPU_FABRIC_CLUSTER_UUID_LEN == NV_UUID_LEN); + + status = gpuFabricProbeGetClusterUuid(pGpu->pGpuFabricProbeInfoKernel, pClusterUuid); + NV_ASSERT_OK_OR_RETURN(status); + + status = gpuFabricProbeGetFabricPartitionId(pGpu->pGpuFabricProbeInfoKernel, + &pParams->fabricPartitionId); + NV_ASSERT_OK_OR_RETURN(status); + + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps); + NV_ASSERT_OK_OR_RETURN(status); + + pParams->fabricCaps = _convertGpuFabricProbeInfoCaps(fmCaps); + + status = gpuFabricProbeGetFabricCliqueId(pGpu->pGpuFabricProbeInfoKernel, + &pParams->fabricCliqueId); + NV_ASSERT_OK_OR_RETURN(status); + + status = gpuFabricProbeGetFabricHealthStatus(pGpu->pGpuFabricProbeInfoKernel, + &mask); + NV_ASSERT_OK_OR_RETURN(status); + + if (FLD_TEST_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK, _DEGRADED_BW, _TRUE, mask)) + { + healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK, + _DEGRADED_BW, _TRUE, healthMask); + } + else if (FLD_TEST_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK, _DEGRADED_BW, + _FALSE, mask)) + { + healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK, + _DEGRADED_BW, _FALSE, healthMask); + } + else if (FLD_TEST_DRF(LINK, _INBAND_FABRIC_HEALTH_MASK, _DEGRADED_BW, + _NOT_SUPPORTED, mask)) + { + healthMask |= FLD_SET_DRF(2080, _CTRL_GPU_FABRIC_HEALTH_MASK, + _DEGRADED_BW, _NOT_SUPPORTED, healthMask); + } + + pParams->fabricHealthMask = healthMask; + + return NV_OK; +} + +/*! + * @brief This command is used to determine which GSP features are + * supported on this GPU. + * + * @param[in] pSubdevice + * @param[in,out] pGspFeaturesParams + * + * @return Returns NV_STATUS + * NV_OK Success + */ +NV_STATUS +subdeviceCtrlCmdGspGetFeatures_KERNEL +( + Subdevice *pSubdevice, + NV2080_CTRL_GSP_GET_FEATURES_PARAMS *pGspFeaturesParams +) +{ + pGspFeaturesParams->bValid = NV_FALSE; + return NV_OK; +} + +// +// Lock Requirements: +// Assert that API lock and GPUs lock held on entry +// +NV_STATUS +subdeviceCtrlCmdGpuGetNameString_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS *pNameStringParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + return gpuGetNameString(pGpu, + pNameStringParams->gpuNameStringFlags, + (void *)&pNameStringParams->gpuNameString); +} + +// +// subdeviceCtrlCmdGpuGetShortNameString +// +// Lock Requirements: +// Assert that API lock and GPUs lock held on entry +// +NV_STATUS +subdeviceCtrlCmdGpuGetShortNameString_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_GET_SHORT_NAME_STRING_PARAMS *pShortNameStringParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + return gpuGetShortNameString(pGpu, (void *)&pShortNameStringParams->gpuShortNameString); +} + +// +// subdeviceCtrlCmdGpuGetGidInfo +// +// Lock Requirements: +// Assert that API lock held on entry +// +NV_STATUS +subdeviceCtrlCmdGpuGetGidInfo_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_GET_GID_INFO_PARAMS *pGidInfoParams +) +{ + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvU8 *pGidString; + NvU32 flags = pGidInfoParams->flags; + NvU32 gidStrlen; + + rmStatus = gpuGetGidInfo(pGpu, &pGidString, &gidStrlen, flags); + if (rmStatus == NV_OK) + { + if (sizeof(pGidInfoParams->data) >= gidStrlen) { - // Nothing needs to be done as probe response status is not success - return NV_OK; + portMemCopy(pGidInfoParams->data, gidStrlen, pGidString, gidStrlen); + pGidInfoParams->length = gidStrlen; + } + else + { + rmStatus = NV_ERR_INSUFFICIENT_RESOURCES; } - ct_assert(NV2080_GPU_FABRIC_CLUSTER_UUID_LEN == NV_UUID_LEN); + portMemFree(pGidString); + } - NV_ASSERT_OK(gpuFabricProbeGetClusterUuid(pGpu->pGpuFabricProbeInfoKernel, - pClusterUuid)); + return rmStatus; +} - NV_ASSERT_OK(gpuFabricProbeGetFabricPartitionId(pGpu->pGpuFabricProbeInfoKernel, - &pParams->fabricPartitionId)); +// Control call to report a nonreplayable fault from UVM +NV_STATUS +subdeviceCtrlCmdGpuReportNonReplayableFault_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); + GMMU_FAULT_PACKET *pFaultPacket = (GMMU_FAULT_PACKET *)(NvUPtr)&pParams->faultPacket.data; - NV_ASSERT_OK(gpuFabricProbeGetFabricCliqueId(pGpu->pGpuFabricProbeInfoKernel, - &pParams->fabricCliqueId)); + ct_assert(sizeof(GMMU_FAULT_PACKET) == NV2080_CTRL_GPU_FAULT_PACKET_SIZE); - NV_ASSERT_OK(gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, &fmCaps)); + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - pParams->fabricCaps = _convertGpuFabricProbeInfoCaps(fmCaps); - } + status = kgmmuHandleNonReplayableFaultPacket_HAL(pGpu, pKernelGmmu, pFaultPacket); + + return status; +} + +NV_STATUS +subdeviceCtrlCmdGpuGetChipDetails_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + return gpuGetChipDetails(pGpu, pParams); +} + +/*! + * @brief This Command is used to report if the specified logo illumination attribute + * is supported + * + * @param[in,out] pConfigParams + * attribute: The attribute whose support is to be determined. + * bSupported: indicator if the specified attribute is supported. + * + * @return Returns NV_STATUS + * NV_OK Success + * + */ +NV_STATUS +subdeviceCtrlCmdGpuQueryIllumSupport_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS *pConfigParams +) +{ + pConfigParams->bSupported = NV_FALSE; return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c index 6828ebaa76..1d5735212e 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c @@ -150,6 +150,41 @@ subdeviceCtrlCmdGpuExecRegOps_cmn // used by the migratable ops function. // bUseMigratableOps = (pOpSmIds != NULL); + // + // If in a VM, do RPC to the host that has hw access. + // + // In case of SRIOV, vGPU guest UMD such as CUDA driver read/write + // PF registers through this RMCtrl. Since, it is a PF register the + // validation is to be performed by host RM only. Hence, we need to + // call RPC early and skip any validation check in Guest RM. + // + if (IS_VIRTUAL(pGpu)) + { + // + // If this function is being used by a MIGRATABLE call, + // we route the GSP call to normal DMA controller + // + if (bUseMigratableOps) + { + NV_RM_RPC_CONTROL(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize, + status); + } + else + { + NV_RM_RPC_GPU_EXEC_REG_OPS(pGpu, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->pParams, + pRegOps, + status); + } + return status; + } // init once, only in monolithic-rm or the cpu-rm, or gsp-rm if the call // is from the gsp plugin @@ -173,13 +208,14 @@ subdeviceCtrlCmdGpuExecRegOps_cmn // if (bUseMigratableOps) { - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); } else { diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_internal_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_internal_kernel.c new file mode 100644 index 0000000000..1156a4e132 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_internal_kernel.c @@ -0,0 +1,60 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * @file + * @brief This module contains the gpu control interfaces for the + * subdevice (NV20_SUBDEVICE_0) class. Subdevice-level control calls + * are directed unicast to the associated GPU. + * File contains ctrls related to general GPU + */ + +#include "gpu/gpu.h" +#include "gpu/subdevice/subdevice.h" +#include "ctrl/ctrl2080/ctrl2080internal.h" + +NV_STATUS +subdeviceCtrlCmdInternalGetChipInfo_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *pParams +) +{ + NvU32 i; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + pParams->chipSubRev = gpuGetChipSubRev_HAL(pGpu); + pParams->isCmpSku = gpuGetIsCmpSku_HAL(pGpu); + pParams->pciDeviceId = pGpu->idInfo.PCIDeviceID; + pParams->pciSubDeviceId = pGpu->idInfo.PCISubDeviceID; + pParams->pciRevisionId = pGpu->idInfo.PCIRevisionID; + + for (i = 0; i < NV_ARRAY_ELEMENTS(pParams->regBases); i++) + { + if (gpuGetRegBaseOffset_HAL(pGpu, i, &pParams->regBases[i]) != NV_OK) + pParams->regBases[i] = 0xFFFFFFFF; + } + + + return NV_OK; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_vgpu.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_vgpu.c new file mode 100644 index 0000000000..c20ad74533 --- /dev/null +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_vgpu.c @@ -0,0 +1,185 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "core/core.h" +#include "gpu/subdevice/subdevice.h" + +#include "nvrm_registry.h" +#include "os/os.h" +#include "vgpu/rpc.h" + +NV_STATUS +subdeviceCtrlCmdBiosGetSKUInfo_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS *pBiosGetSKUInfoParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + NV_ASSERT_OR_RETURN(pVSI != NULL, NV_ERR_INVALID_STATE); + + portMemCopy(pBiosGetSKUInfoParams, sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS), &pVSI->SKUInfo, sizeof(NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS)); + + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdGpuQueryEccConfiguration_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS *pConfig +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + NvU32 eccState = 0; + + NV_ASSERT_OR_RETURN((pVGpu != NULL) && pVGpu->bECCSupported, NV_ERR_NOT_SUPPORTED); + + if (osReadRegistryDword(pGpu, NV_REG_STR_RM_GUEST_ECC_STATE, &eccState) == NV_OK) + { + pConfig->currentConfiguration = eccState; + } + else + { + pConfig->currentConfiguration = pVGpu->bECCEnabled; + } + + // If ECC supported on vGPU, default ECC state is enabled. + pConfig->defaultConfiguration = NV_REG_STR_RM_GUEST_ECC_STATE_DEFAULT; + + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdGpuSetEccConfiguration_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_SET_ECC_CONFIGURATION_PARAMS *pConfig +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NV_STATUS rmStatus = NV_OK; + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + NvU32 eccState; + + NV_ASSERT_OR_RETURN((pVGpu != NULL) && pVGpu->bECCSupported, NV_ERR_NOT_SUPPORTED); + + eccState = !!pConfig->newConfiguration; + + rmStatus = osWriteRegistryDword(pGpu, NV_REG_STR_RM_GUEST_ECC_STATE, eccState); + + return rmStatus; +} + +/*! + * @brief Returns the status of the HW scrubber - running/idle. + * If the scrubber is running, it also returns the range + * that is being scrubbed. + */ +NV_STATUS +subdeviceCtrlCmdGpuQueryScrubberStatus_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_PARAMS *pParams +) +{ + pParams->scrubberStatus = NV2080_CTRL_GPU_QUERY_SCRUBBER_STATUS_SCRUBBER_IDLE; + + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdBiosGetPostTime_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS *pBiosPostTime +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + + pBiosPostTime->vbiosPostTime = pGpu->gpuVbiosPostTime; + + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdGpuResetEccErrorStatus_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_RESET_ECC_ERROR_STATUS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NvU32 i; + + if ((pVGpu == NULL) || (!pVGpu->bECCSupported) || + (pParams->statuses & NV2080_CTRL_GPU_ECC_ERROR_STATUS_AGGREGATE)) + { + return NV_ERR_NOT_SUPPORTED; + } + + for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT; i++) + { + if (pVSI->eccStatus.units[i].supported) + { + pVSI->eccStatus.units[i].sbe.count = 0; + pVSI->eccStatus.units[i].dbe.count = 0; + } + } + + return NV_OK; +} + +NV_STATUS +subdeviceCtrlCmdGpuQueryEccStatus_VF +( + Subdevice *pSubdevice, + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + OBJVGPU *pVGpu = GPU_GET_VGPU(pGpu); + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + NV_STATUS status = NV_OK; + + if ((pVGpu == NULL) || !pVGpu->bECCSupported) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (pVGpu->bECCEnabled) + { + portMemCopy(pParams, sizeof(*pParams), &pVSI->eccStatus, sizeof(pVSI->eccStatus)); + } + else + { + portMemSet(pParams, 0, sizeof(*pParams)); + } + + return status; +} diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_diag.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_diag.c index 0b2bfeecd9..a404080c93 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_diag.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_diag.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -27,7 +27,6 @@ #include "rmapi/rs_utils.h" #include "gpu/subdevice/subdevice_diag.h" -#include "gpu/subdevice/subdevice.h" #include "class/cl208f.h" // NV208F_NOTIFIERS_MAXCOUNT #include "ctrl/ctrl208f/ctrl208fevent.h" // NV208F_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE @@ -85,6 +84,25 @@ diagapiControlFilter_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { + OBJGPU *pGpu = GPU_RES_GET_GPU(pDiagApi); + RmCtrlParams *pRmCtrlParams = pParams->pLegacyParams; + + if (IS_VIRTUAL(pGpu)) + { + switch (pRmCtrlParams->cmd) + { + // For Guest OS, only below RM controls are supported. + case NV208F_CTRL_CMD_FIFO_ENABLE_VIRTUAL_CONTEXT: + case NV208F_CTRL_CMD_FIFO_CHECK_ENGINE_CONTEXT: + case NV208F_CTRL_CMD_DMA_GET_VAS_BLOCK_DETAILS: + break; + + // Fall though for unsupported CTRL + default: + return NV_ERR_NOT_SUPPORTED; + } + } + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c b/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c index a1b7f144fb..f8d4cc21b6 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/ampere/timer_ga100.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -47,6 +47,12 @@ tmrGetGpuPtimerOffset_GA100 NvU32 *pGpuTimestampOffsetHi ) { + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + *pGpuTimestampOffsetLo = NV_VIRTUAL_FUNCTION_TIME_0; + *pGpuTimestampOffsetHi = NV_VIRTUAL_FUNCTION_TIME_1; + } + else { *pGpuTimestampOffsetLo = GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_TIME_0); *pGpuTimestampOffsetHi = GPU_GET_VREG_OFFSET(pGpu, NV_VIRTUAL_FUNCTION_TIME_1); @@ -54,3 +60,49 @@ tmrGetGpuPtimerOffset_GA100 return NV_OK; } + +/** + * @brief Services the stall interrupt. + * + * @param[in] pGpu + * @param[in] pTmr + * @param[in] pParams + * + * @returns Zero, or any implementation-chosen nonzero value. If the same nonzero value is returned enough + * times the interrupt is considered stuck. + */ +NvU32 +tmrServiceInterrupt_GA100 +( + OBJGPU *pGpu, + OBJTMR *pTmr, + IntrServiceServiceInterruptArguments *pParams +) +{ + NV_ASSERT_OR_RETURN(pParams != NULL, 0); + + switch (pParams->engineIdx) + { + case MC_ENGINE_IDX_TMR: + { + MODS_ARCH_REPORT(NV_ARCH_EVENT_PTIMER, "%s", "processing ptimer interrupt\n"); + + // Service countdown timer interrupts + (void)tmrCallExpiredCallbacks(pGpu, pTmr); + + break; + } + case MC_ENGINE_IDX_TMR_SWRL: + { + tmrServiceSwrlCallbacks(pGpu, pTmr, NULL); + break; + } + default: + { + NV_ASSERT_FAILED("Invalid engineIdx"); + break; + } + } + + return 0; +} diff --git a/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c b/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c index d092bbb568..f49ee2396e 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/maxwell/timer_gm107.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -276,3 +276,91 @@ tmrGetTimeEx_GM107 return Time; } + +// +// For functions that only need a short delta of time elapsed (~ 4.29 seconds) +// NOTE: Since it wraps around every 4.29 seconds, for general GetTime purposes, +// it's better to use tmrGetTime(). +// +NvU32 +tmrGetTimeLo_GM107 +( + OBJGPU *pGpu, + OBJTMR *pTmr +) +{ + NvU32 lo = 0; + + // read TIME_0 + lo = tmrReadTimeLoReg_HAL(pGpu, pTmr, NULL); + // + // check if it's a stable TIME_0, otherwise, we just call a regular + // tmrGetTime to handle all error book-keeping, resetting timer, etc. + // + if ((lo & ~DRF_SHIFTMASK(NV_PTIMER_TIME_0_NSEC)) != 0) + { + // let tmrGetTime() handle all the mess.. + NV_PRINTF(LEVEL_WARNING, + "NVRM-RC: Bad TimeLo value %x, Let's see if it happens again.\n", + lo); + DBG_BREAKPOINT(); + + return (NvU32) (tmrGetTime_HAL(pGpu, pTmr) & 0xffffffff); + } + return lo; +} + +NvU64 +tmrGetTime_GM107 +( + OBJGPU *pGpu, + OBJTMR *pTmr +) +{ + return tmrGetTimeEx_HAL(pGpu, pTmr, NULL); +} + +/** + * @brief Services the stall interrupt. + * + * @param[in] pGpu + * @param[in] pTmr + * @param[in] pParams + * + * @returns Zero, or any implementation-chosen nonzero value. If the same nonzero value is returned enough + * times the interrupt is considered stuck. + */ +NvU32 +tmrServiceInterrupt_GM107 +( + OBJGPU *pGpu, + OBJTMR *pTmr, + IntrServiceServiceInterruptArguments *pParams +) +{ + NvU32 retVal = 0; + NV_ASSERT_OR_RETURN(pParams != NULL, 0); + + // Service the countdown timer interrupt. + tmrServiceSwrlCallbacksPmcTree(pGpu, pTmr, NULL); + + // Service the timer alarm interrupt. + if (tmrGetCallbackInterruptPending(pGpu, pTmr)) + { + tmrResetCallbackInterrupt(pGpu, pTmr); + + // service both normal and self-rescheduling lists + (void)tmrCallExpiredCallbacks(pGpu, pTmr); + + // If there are no remaining callbacks then disable the PTIMER interrupt. + if (pTmr->pRmActiveEventList == NULL) + { + // Last one is gone. Disable PTIMER interrupt. + tmrRmCallbackIntrDisable(pTmr, pGpu); + } + } + + tmrGetIntrStatus_HAL(pGpu, pTmr, &retVal, NULL); + + return retVal; +} diff --git a/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c b/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c index d8be48ea36..f5e80c0768 100644 --- a/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c +++ b/src/nvidia/src/kernel/gpu/timer/arch/turing/timer_tu102.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -158,3 +158,32 @@ tmrReadTimeHiReg_TU102 { return GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_TIME_1, pThreadState); } + +/** + * @brief Services the stall interrupt. + * + * @param[in] pGpu + * @param[in] pTmr + * @param[in] pParams + * + * @returns Zero, or any implementation-chosen nonzero value. If the same nonzero value is returned enough + * times the interrupt is considered stuck. + */ +NvU32 +tmrServiceInterrupt_TU102 +( + OBJGPU *pGpu, + OBJTMR *pTmr, + IntrServiceServiceInterruptArguments *pParams +) +{ + extern NvU32 tmrServiceInterrupt_GM107(OBJGPU *pGpu, OBJTMR *pTmr, IntrServiceServiceInterruptArguments *pParams); + NV_ASSERT_OR_RETURN(pParams != NULL, 0); + MODS_ARCH_REPORT(NV_ARCH_EVENT_PTIMER, "%s", "processing ptimer interrupt\n"); + + // Service countdown timer interrupts + (void)tmrCallExpiredCallbacks(pGpu, pTmr); + + // Call the legacy timer service routine to service alarm interrupts + return tmrServiceInterrupt_GM107(pGpu, pTmr, pParams); +} diff --git a/src/nvidia/src/kernel/gpu/video/kernel_video_engine.c b/src/nvidia/src/kernel/gpu/video/kernel_video_engine.c index 638162cbac..69e39fa4eb 100644 --- a/src/nvidia/src/kernel/gpu/video/kernel_video_engine.c +++ b/src/nvidia/src/kernel/gpu/video/kernel_video_engine.c @@ -51,7 +51,12 @@ kvidengIsVideoTraceLogSupported_IMPL OBJGPU *pGpu ) { - return !IS_VIRTUAL(pGpu) && !RMCFG_FEATURE_PLATFORM_MODS && !IS_SIMULATION(pGpu); + NvBool bSupported = !IS_VIRTUAL(pGpu) && !RMCFG_FEATURE_PLATFORM_MODS && + !IS_SIMULATION(pGpu); + + bSupported &= !gpuIsCCFeatureEnabled(pGpu); + + return bSupported; } NV_STATUS kvidengConstruct_IMPL @@ -73,121 +78,117 @@ NV_STATUS kvidengInitLogging_KERNEL ) { NV_STATUS status; - NvU32 data = NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED; + NvU32 eventBufferSize; + VIDEO_TRACE_RING_BUFFER *pTraceBuf; + NvU64 seed; + NvBool bIsFbBroken = NV_FALSE; + NV_ADDRESS_SPACE addressSpace = ADDR_FBMEM; NvBool bAlwaysLogging; + NvU32 data; - if (!kvidengIsVideoTraceLogSupported(pGpu)) - return NV_OK; + NV_CHECK_OR_RETURN(LEVEL_INFO, kvidengIsVideoTraceLogSupported(pGpu), NV_OK); - status = osReadRegistryDword(pGpu, NV_REG_STR_RM_VIDEO_EVENT_TRACE, &data); - if (status != NV_OK) - { - // When GLOBAL_FEATURE_GR2069_VIDEO_EVENT is enabled and the registry is not set, - // default eventbuffer size to 32K and staging buffer to 4K. - data = DRF_NUM(_REG_STR, _RM_VIDEO_EVENT_TRACE, _STAGING_BUFFER_SIZE_IN_4k, 1) | - DRF_NUM(_REG_STR, _RM_VIDEO_EVENT_TRACE, _EVENT_BUFFER_SIZE_IN_4k, 0x8); - } + data = pKernelVideoEngine->videoTraceInfo.eventTraceRegkeyData; + + NV_CHECK_OR_RETURN(LEVEL_INFO, (data != NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED), NV_OK); bAlwaysLogging = DRF_VAL(_REG_STR, _RM_VIDEO_EVENT_TRACE, _ALWAYS_LOG, (data)) == NV_REG_STR_RM_VIDEO_EVENT_TRACE_ALWAYS_LOG_ENABLED; - if (data != NV_REG_STR_RM_VIDEO_EVENT_TRACE_DISABLED) + eventBufferSize = DRF_VAL(_REG_STR, _RM_VIDEO_EVENT_TRACE, _EVENT_BUFFER_SIZE_IN_4k, (data)) * 0x1000; + + bIsFbBroken = pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM); + + if (bIsFbBroken) + addressSpace = ADDR_SYSMEM; + + // Allocate the staging buffer + NV_ASSERT_OK_OR_GOTO( + status, + memdescCreate(&pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc, + pGpu, + eventBufferSize, + 0, + NV_TRUE, + addressSpace, + NV_MEMORY_UNCACHED, + MEMDESC_FLAGS_NONE), + exit); + + NV_ASSERT_OK_OR_GOTO( + status, + memdescAlloc(pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc), + exit); + + pTraceBuf = (VIDEO_TRACE_RING_BUFFER *)kbusMapRmAperture_HAL(pGpu, + pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc); + + NV_ASSERT_OR_ELSE(pTraceBuf != NULL, + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto exit;); + + // clear trace buffer + portMemSet(pTraceBuf, 0, eventBufferSize); + pTraceBuf->bufferSize = eventBufferSize - sizeof(VIDEO_TRACE_RING_BUFFER); + pTraceBuf->readPtr = 0; + pTraceBuf->writePtr = 0; + pTraceBuf->flags = bAlwaysLogging ? VIDEO_TRACE_FLAG__LOGGING_ENABLED : 0; + + pKernelVideoEngine->videoTraceInfo.pTraceBufferEngine = pTraceBuf; + + if (IS_GSP_CLIENT(pGpu)) { - NvU32 eventBufferSize; - VIDEO_TRACE_RING_BUFFER *pTraceBuf; - NvU64 seed; - NvBool bIsFbBroken = NV_FALSE; - NV_ADDRESS_SPACE addressSpace = ADDR_FBMEM; - - eventBufferSize = DRF_VAL(_REG_STR, _RM_VIDEO_EVENT_TRACE, _EVENT_BUFFER_SIZE_IN_4k, (data)) * 0x1000; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS params = {0}; - bIsFbBroken = pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) || - pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM); + params.memDescInfo.base = memdescGetPhysAddr(pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc, + AT_GPU, + 0); + params.memDescInfo.size = pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc->ActualSize; + params.memDescInfo.alignment = pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc->Alignment; + params.memDescInfo.addressSpace = addressSpace; + params.memDescInfo.cpuCacheAttrib = NV_MEMORY_UNCACHED; - if (bIsFbBroken) - addressSpace = ADDR_SYSMEM; + params.engDesc = pKernelVideoEngine->physEngDesc; - // Allocate the staging buffer NV_ASSERT_OK_OR_GOTO( status, - memdescCreate(&pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc, - pGpu, - eventBufferSize, - 0, - NV_TRUE, - addressSpace, - NV_MEMORY_UNCACHED, - MEMDESC_FLAGS_NONE), + pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY, + ¶ms, + sizeof(params)), exit); - NV_ASSERT_OK_OR_GOTO( - status, - memdescAlloc(pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc), - exit); - - pTraceBuf = (VIDEO_TRACE_RING_BUFFER *)kbusMapRmAperture_HAL(pGpu, pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc); - - NV_ASSERT_OR_ELSE(pTraceBuf != NULL, - status = NV_ERR_INSUFFICIENT_RESOURCES; - goto exit;); - - // clear trace buffer - portMemSet(pTraceBuf, 0, eventBufferSize); - pTraceBuf->bufferSize = eventBufferSize - sizeof(VIDEO_TRACE_RING_BUFFER); - pTraceBuf->readPtr = 0; - pTraceBuf->writePtr = 0; - pTraceBuf->flags = bAlwaysLogging ? VIDEO_TRACE_FLAG__LOGGING_ENABLED : 0; - - pKernelVideoEngine->videoTraceInfo.pTraceBufferEngine = pTraceBuf; - - if (IS_GSP_CLIENT(pGpu)) - { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV2080_CTRL_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY_PARAMS params = {0}; - - params.memDescInfo.base = memdescGetPhysAddr(pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc, AT_GPU, 0); - params.memDescInfo.size = pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc->ActualSize; - params.memDescInfo.alignment = pKernelVideoEngine->videoTraceInfo.pTraceBufferEngineMemDesc->Alignment; - params.memDescInfo.addressSpace = addressSpace; - params.memDescInfo.cpuCacheAttrib = NV_MEMORY_UNCACHED; - - params.engDesc = pKernelVideoEngine->physEngDesc; - - NV_ASSERT_OK_OR_GOTO( - status, - pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_INTERNAL_FLCN_SET_VIDEO_EVENT_BUFFER_MEMORY, - ¶ms, - sizeof(params)), - exit); - - if (!params.bEngineFound) - { - kvidengFreeLogging(pGpu, pKernelVideoEngine); - goto exit; - } - } - - // Allocate allocate scratch pad for variable data - pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData = portMemAllocNonPaged(RM_VIDEO_TRACE_MAX_VARIABLE_DATA_SIZE); - - if (pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData == NULL) + if (!params.bEngineFound) { - status = NV_ERR_NO_MEMORY; + kvidengFreeLogging(pGpu, pKernelVideoEngine); goto exit; } - portMemSet(pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData, 0x00, RM_VIDEO_TRACE_MAX_VARIABLE_DATA_SIZE); + } - /*! - * Random number generator used for generate noisy timestamp - */ - osGetCurrentTick(&seed); - pKernelVideoEngine->videoTraceInfo.pVideoLogPrng = portCryptoPseudoRandomGeneratorCreate(seed); + // Allocate allocate scratch pad for variable data + pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData = + portMemAllocNonPaged(RM_VIDEO_TRACE_MAX_VARIABLE_DATA_SIZE); - pKernelVideoEngine->bVideoTraceEnabled = NV_TRUE; + if (pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData == NULL) + { + status = NV_ERR_NO_MEMORY; + goto exit; } + portMemSet(pKernelVideoEngine->videoTraceInfo.pTraceBufferVariableData, + 0x00, + RM_VIDEO_TRACE_MAX_VARIABLE_DATA_SIZE); + + /*! + * Random number generator used for generate noisy timestamp + */ + osGetCurrentTick(&seed); + pKernelVideoEngine->videoTraceInfo.pVideoLogPrng = portCryptoPseudoRandomGeneratorCreate(seed); + + pKernelVideoEngine->bVideoTraceEnabled = NV_TRUE; exit: if (status != NV_OK) diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index 4404085cdd..52ffeaed30 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -29,6 +29,7 @@ #include "core/system.h" #include "core/locks.h" +#include "platform/sli/sli.h" #include "gpu_mgr/gpu_mgr.h" #include "gpu/device/device.h" #include "gpu/gpu.h" @@ -39,6 +40,7 @@ #include "nv-firmware-registry.h" #include "kernel/gpu/intr/intr.h" +#include "vgpu/sdk-structures.h" #include "virtualization/hypervisor/hypervisor.h" #include "platform/chipset/chipset.h" #include "published/pcie_switch/pcie_switch_ref.h" @@ -46,6 +48,7 @@ #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/conf_compute/conf_compute.h" #include "gpu/gpu_fabric_probe.h" +#include "gpu/mig_mgr/gpu_instance_subscription.h" // local static funcs static void gpumgrSetAttachInfo(OBJGPU *, GPUATTACHARG *); @@ -145,6 +148,7 @@ _gpumgrDetermineConfComputeCapabilities pGpuMgr->ccCaps.bHccFeatureCapable = pGpu->getProperty(pGpu, PDB_PROP_GPU_CC_FEATURE_CAPABLE); pGpuMgr->ccCaps.bCCFeatureEnabled = bCCFeatureEnabled; pGpuMgr->ccCaps.bDevToolsModeEnabled = gpuIsCCDevToolsModeEnabled(pGpu); + pGpuMgr->ccCaps.bMultiGpuProtectedPcieModeEnabled = gpuIsCCMultiGpuProtectedPcieModeEnabled(pGpu); if (pGpuMgr->ccCaps.bDevToolsModeEnabled) { @@ -175,6 +179,10 @@ _gpumgrDetermineConfComputeCapabilities NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bDevToolsModeEnabled == gpuIsCCDevToolsModeEnabled(pGpu), NV_ERR_INVALID_STATE); + + NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bMultiGpuProtectedPcieModeEnabled == + gpuIsCCMultiGpuProtectedPcieModeEnabled(pGpu), + NV_ERR_INVALID_STATE); } return NV_OK; @@ -263,6 +271,54 @@ gpumgrDestruct_IMPL(OBJGPUMGR *pGpuMgr) gpumgrDestroyPcieP2PCapsCache(pGpuMgr); } +static NvBool +_gpumgrThreadHasExpandedGpuVisibilityInTls(void) +{ + NvP64 entry = tlsEntryGet(TLS_ENTRY_ID_GPUMGR_EXPANDED_GPU_VISIBILITY); + return (entry != NvP64_NULL) && (entry == ((NvP64) 1)); +} + +NvBool +gpumgrThreadHasExpandedGpuVisibility(void) +{ + if (RMCFG_FEATURE_PLATFORM_UNIX) + { + return _gpumgrThreadHasExpandedGpuVisibilityInTls(); + } + else + { + // + // Bug 4376209 + // Non-UNIX platforms have expanded GPU visibility by default for now + // (this is OK as they do not have parallel init yet). + // + return NV_TRUE; + } +} + +NV_STATUS +gpumgrThreadEnableExpandedGpuVisibility(void) +{ + NvP64 *pEntry = tlsEntryAcquire(TLS_ENTRY_ID_GPUMGR_EXPANDED_GPU_VISIBILITY); + if (pEntry == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + *pEntry = (NvP64) 1; + return NV_OK; +} + +void +gpumgrThreadDisableExpandedGpuVisibility(void) +{ + if (_gpumgrThreadHasExpandedGpuVisibilityInTls()) + { + NvU32 refCount = tlsEntryRelease(TLS_ENTRY_ID_GPUMGR_EXPANDED_GPU_VISIBILITY); + NV_ASSERT(refCount == 0); + } +} + // // gpumgrAllocGpuInstance // @@ -366,9 +422,20 @@ gpumgrGetGpu(NvU32 gpuInstance) NvU32 i; for (i = 0; i < pGpuMgr->numGpuHandles; i++) + { if (pGpuMgr->gpuHandleIDList[i].gpuInstance == gpuInstance) - if (pGpuMgr->gpuHandleIDList[i].pGpu) - return pGpuMgr->gpuHandleIDList[i].pGpu; + { + OBJGPU *pGpu = pGpuMgr->gpuHandleIDList[i].pGpu; + if (pGpu != NULL) + { + if (gpumgrThreadHasExpandedGpuVisibility() || + pGpu->getProperty(pGpu, PDB_PROP_GPU_STATE_INITIALIZED)) + { + return pGpu; + } + } + } + } return NULL; } @@ -439,9 +506,30 @@ gpumgrGetGpuAttachInfo(NvU32 *pGpuCnt, NvU32 *pGpuMask) OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NvU32 outCount = 0; + NvU32 outMask = 0; + + NvU32 gpuMask = pGpuMgr->gpuAttachMask; + NvU32 gpuInstance = 0; + + while (gpuInstance != NV_MAX_DEVICES) + { + OBJGPU *pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance); + if (pGpu == NULL) + continue; + + if (gpumgrThreadHasExpandedGpuVisibility() || + pGpu->getProperty(pGpu, PDB_PROP_GPU_STATE_INITIALIZED)) + { + // adjust gpuInstance down one as gpumgrGetNextGpu increments one + outMask |= NVBIT(gpuInstance - 1); + outCount++; + } + } + // caller can pass in NULL for outparams that it doesn't need. - if (pGpuCnt) *pGpuCnt = pGpuMgr->gpuAttachCount; - if (pGpuMask) *pGpuMask = pGpuMgr->gpuAttachMask; + if (pGpuCnt != NULL) *pGpuCnt = outCount; + if (pGpuMask != NULL) *pGpuMask = outMask; return NV_OK; } @@ -790,10 +878,63 @@ gpumgrGetGpuUuidInfo(NvU32 gpuId, NvU8 **ppUuidStr, NvU32 *pUuidStrLen, NvU32 uu return status; } +static NV_STATUS +gpumgrGetRegisteredIds +( + NvU64 gpuDomainBusDevice, + NvU32 *pGpuId, + NvUuid *pUuid, + NvBool *pbUuidValid +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NV_STATUS status = NV_ERR_OBJECT_NOT_FOUND; + + portSyncMutexAcquire(pGpuMgr->probedGpusLock); + + for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(pGpuMgr->probedGpus); i++) + { + PROBEDGPU *pProbedGpu = &pGpuMgr->probedGpus[i]; + if (pProbedGpu->gpuId == NV0000_CTRL_GPU_INVALID_ID) + continue; + + if (pProbedGpu->gpuDomainBusDevice == gpuDomainBusDevice) + { + *pGpuId = pProbedGpu->gpuId; + *pbUuidValid = pProbedGpu->bUuidValid; + if (pProbedGpu->bUuidValid) + portMemCopy(pUuid->uuid, sizeof(pUuid->uuid), + pProbedGpu->uuid, sizeof(pProbedGpu->uuid)); + + status = NV_OK; + break; + } + } + + portSyncMutexRelease(pGpuMgr->probedGpusLock); + return status; +} + static void gpumgrGetGpuHalFactorOfVirtual(NvBool *pIsVirtual, GPUATTACHARG *pAttachArg) { + DEVICE_MAPPING gpuDevMapping = {0}; + NvU32 pmcBoot1; + + gpuDevMapping.gpuNvAddr = pAttachArg->regBaseAddr; + gpuDevMapping.gpuNvLength = pAttachArg->regLength; + *pIsVirtual = NV_FALSE; + + // Check register NV_PMC_BOOT_1 + pmcBoot1 = osDevReadReg032(/*pGpu=*/ NULL, &gpuDevMapping, NV_PMC_BOOT_1); + + // VGPU with SRIOV + if (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmcBoot1)) + { + *pIsVirtual = NV_TRUE; + } } NvBool gpumgrGetRmFirmwareLogsEnabled @@ -802,14 +943,16 @@ NvBool gpumgrGetRmFirmwareLogsEnabled ) { // Check for logs - if ((enableFirmwareLogsRegVal == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE) + if (enableFirmwareLogsRegVal == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE) + { + return NV_TRUE; + } #if defined(DEBUG) || defined(DEVELOP) - || (enableFirmwareLogsRegVal == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG) -#endif // defined(DEBUG) || defined(DEVELOP) - ) + if (enableFirmwareLogsRegVal == NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG) { return NV_TRUE; } +#endif // defined(DEBUG) || defined(DEVELOP) return NV_FALSE; } @@ -848,26 +991,25 @@ static NvBool _gpumgrIsRmFirmwareCapableChip(NvU32 pmcBoot42) return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) >= NV_PMC_BOOT_42_ARCHITECTURE_TU100); } -static NvBool _gpumgrIsVgxRmFirmwareCapableChip(NvU32 pmcBoot42) +NvBool gpumgrIsVgxRmFirmwareCapableChip(NvU32 pmcBoot42) { - return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) >= NV_PMC_BOOT_42_ARCHITECTURE_GA100) && - (DRF_VAL(_PMC, _BOOT_42, _CHIP_ID, pmcBoot42) > NV_PMC_BOOT_42_CHIP_ID_GA100); + if (FLD_TEST_DRF(_PMC, _BOOT_42, _ARCHITECTURE, _GH100, pmcBoot42)) + return NV_TRUE; + + if (FLD_TEST_DRF(_PMC, _BOOT_42, _ARCHITECTURE, _AD100, pmcBoot42)) + return NV_TRUE; + + return NV_FALSE; } static NvBool _gpumgrIsRmFirmwareDefaultChip(NvU32 pmcBoot42) { - return (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_GH100); + return FLD_TEST_DRF(_PMC, _BOOT_42, _ARCHITECTURE, _GH100, pmcBoot42); } static NvBool _gpumgrIsVgxRmFirmwareDefaultChip(NvU32 pmcBoot42) { - if (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_GH100) - return NV_TRUE; - - if (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_AD100) - return NV_TRUE; - - return NV_FALSE; + return gpumgrIsVgxRmFirmwareCapableChip(pmcBoot42); } NvBool gpumgrIsDeviceRmFirmwareCapable @@ -890,7 +1032,7 @@ NvBool gpumgrIsDeviceRmFirmwareCapable bFirmwareCapable = NV_FALSE; goto finish; } - else if (hypervisorIsVgxHyper() && !_gpumgrIsVgxRmFirmwareCapableChip(pmcBoot42)) + else if (hypervisorIsVgxHyper() && !gpumgrIsVgxRmFirmwareCapableChip(pmcBoot42)) { bFirmwareCapable = NV_FALSE; goto finish; @@ -1111,6 +1253,9 @@ _gpumgrCreateGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) NvU32 chipId1; // 32-bit chipId (pmcBoot42 on GPU) NvU32 socChipId0; // 32-bit SOC chipId NvU32 hidrev, majorRev; + NvU32 gpuId; + NvUuid gpuUuid; + NvBool bGpuUuidValid = NV_FALSE; gpumgrGetGpuHalFactor(&chipId0, &chipId1, &socChipId0, &rmVariant, &tegraType, pAttachArg); @@ -1125,6 +1270,14 @@ _gpumgrCreateGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) hidrev = (hidrev << 4) | majorRev; + // + // The OS layer must have previously registered the GPU ID, and may have already registered + // the UUID. Pull out the registered IDs for this device from the probed GPU info to pass to + // the OBJGPU constructor. + // + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, gpumgrGetRegisteredIds(pAttachArg->nvDomainBusDeviceFunc, + &gpuId, &gpuUuid, &bGpuUuidValid)); + // create OBJGPU with halspec factor initialization value status = objCreate(&pGpu, pSys, OBJGPU, /* ChipHal_arch = */ DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, chipId1), @@ -1133,7 +1286,9 @@ _gpumgrCreateGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) /* RmVariantHal_rmVariant = */ rmVariant, /* TegraChipHal_tegraType = */ tegraType, /* DispIpHal_ipver = */ 0, // initialized later - /* ctor.gpuInstance = */ gpuInstance); + /* ctor.gpuInstance = */ gpuInstance, + /* ctor.gpuId = */ gpuId, + /* ctor.pUuid = */ bGpuUuidValid ? &gpuUuid : NULL); if (status != NV_OK) { return status; @@ -1163,6 +1318,59 @@ _gpumgrCreateGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg) static void _gpumgrGetEncSessionStatsReportingState(OBJGPU *pGpu) { + NvU32 numClasses = 0; + + // Set NvEnc Session Stats reporting state flag to 'not supported' on GPUs with no encoder engine. + NV_STATUS nvStatus = gpuGetClassList(pGpu, &numClasses, NULL, MKENGDESC(classId(OBJMSENC), 0)); + if ((nvStatus != NV_OK) || (numClasses == 0)) + { + pGpu->encSessionStatsReportingState = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_NOT_SUPPORTED; + return; + } + + pGpu->encSessionStatsReportingState = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED; + +#if defined(NVCPU_AARCH64) + pGpu->encSessionStatsReportingState = NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_DISABLED; +#else + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + if (IS_VIRTUAL(pGpu)) + { + if (pVSI) + { + pGpu->encSessionStatsReportingState = pVSI->vgpuStaticProperties.encSessionStatsReportingState; + } + else + { + pGpu->encSessionStatsReportingState = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED; + } + } + else + { + NvU32 encSessionStatsReportingState = NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_DISABLED;; + + // Encoder Sessions Stats report is enabled by default + pGpu->encSessionStatsReportingState = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED; + + // Override the value with the value specified in registry. + if (osReadRegistryDword(pGpu, + NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE, + &encSessionStatsReportingState) == NV_OK) + { + switch(encSessionStatsReportingState) + { + case NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_DISABLED: + pGpu->encSessionStatsReportingState = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_DISABLED; + break; + case NV_REG_STR_RM_NVENC_SESSION_STATS_REPORTING_STATE_ENABLED: + pGpu->encSessionStatsReportingState = NV2080_CTRL_GPU_INFO_NVENC_STATS_REPORTING_STATE_ENABLED; + break; + default: + break; + } + } + } +#endif // defined(NVCPU_AARCH64) } // @@ -1525,8 +1733,6 @@ gpumgrGetSubDeviceMaxValuePlus1(OBJGPU *pGpu) static void gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) { - NvU32 gpuId = NV0000_CTRL_GPU_INVALID_ID; - if (pAttachArg->socDeviceArgs.specified) { NvU32 idx; @@ -1602,6 +1808,7 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) pGpu->fbLength = pAttachArg->fbLength; pGpu->busInfo.IntLine = pAttachArg->intLine; pGpu->gpuDeviceMapCount = 1; + pGpu->cpuNumaNodeId = pAttachArg->cpuNumaNodeId; if ( ! pAttachArg->instBaseAddr ) { @@ -1628,16 +1835,6 @@ gpumgrSetAttachInfo(OBJGPU *pGpu, GPUATTACHARG *pAttachArg) pGpu->instLength = pAttachArg->instLength; } } - - // Generate GPU ID using end-point address for PCIe devices, otherwise use MMIO address - gpuId = (!RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM || !pGpu->bIsSOC) - ? gpuGenerate32BitId(gpuGetDomain(pGpu), gpuGetBus(pGpu), gpuGetDevice(pGpu)) - : gpuGenerate32BitIdFromPhysAddr(pAttachArg->socDeviceArgs.deviceMapping[DEVICE_INDEX_GPU].gpuNvPAddr); - - if (gpuId != NV0000_CTRL_GPU_INVALID_ID) - { - gpumgrSetGpuId(pGpu, gpuId); - } } // @@ -1756,7 +1953,7 @@ gpumgrGetNextGpu(NvU32 subDeviceMask, NvU32 *pStartIndex) // -// gpumgrIsGpuPointerValid - Validates pGpu without dereferencing it. +// gpumgrIsGpuPointerValid - Validates pGpu is initialized without dereferencing it. // NvBool gpumgrIsGpuPointerValid(OBJGPU *pGpu) @@ -1785,6 +1982,33 @@ gpumgrIsGpuPointerValid(OBJGPU *pGpu) return NV_FALSE; } +// +// gpumgrIsGpuPointerAttached - Validates pGpu is attached without dereferencing it. +// +NvBool +gpumgrIsGpuPointerAttached(OBJGPU *pGpu) +{ + OBJGPU *pTempGpu = NULL; + NvU32 gpuMask = 0; + NvU32 gpuCount = 0; + NvU32 gpuIndex = 0; + + gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); + pTempGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + + while(pTempGpu) + { + if (pTempGpu == pGpu) + { + return NV_TRUE; + } + pTempGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); + } + + return NV_FALSE; +} + + NvBool gpumgrIsGpuDisplayParent(OBJGPU *pGpu) { OBJGPUGRP *pGpuGrp = gpumgrGetGpuGrpFromGpu(pGpu); @@ -2140,20 +2364,38 @@ gpumgrGetGpuIdInfoV2(NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS *pGpuInfo) if (gpuIsSelfHosted(pGpu) && IS_MIG_IN_USE(pGpu)) { - CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); - KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); - MIG_INSTANCE_REF ref; - NvU32 swizzId; - Device *pDevice; - - if ((deviceGetByGpu(pCallContext->pClient, pGpu, NV_TRUE, &pDevice) == NV_OK) && - (kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref) == NV_OK)) + // + // We do not have enough information here to route to correct MIG instance. + // There may even not be enough state to do this lookup at all as this is a 0x0000 control + // but we need to get to Subdevice child. Try extra hard to preserve originally + // implemented behavior. See bug 4251227. + // + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RS_ITERATOR it = clientRefIter(pCallContext->pClient, NULL, classId(GPUInstanceSubscription), + RS_ITERATE_DESCENDANTS, NV_TRUE); + + while (clientRefIterNext(it.pClient, &it)) { - swizzId = ref.pKernelMIGGpuInstance->swizzId; + NvU32 swizzId; + GPUInstanceSubscription *pGPUInstanceSubscription = + dynamicCast(it.pResourceRef->pResource, GPUInstanceSubscription); + + if (GPU_RES_GET_GPU(pGPUInstanceSubscription) != pGpu) + { + continue; + } + + swizzId = gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription)->swizzId; + + if (swizzId == NVC637_DEVICE_PROFILING_SWIZZID) + { + continue; + } if (GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->memPartitionNumaInfo[swizzId].bInUse) { pGpuInfo->numaId = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)->memPartitionNumaInfo[swizzId].numaNodeId; } + break; } } else @@ -2626,7 +2868,7 @@ RmPhysAddr gpumgrGetGpuPhysFbAddr(OBJGPU *pGpu) physFbAddr = pGpu->busInfo.gpuPhysFbAddr; - NV_ASSERT(physFbAddr); + NV_ASSERT(pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB) || physFbAddr); return physFbAddr; } @@ -2717,7 +2959,7 @@ gpumgrAddDeviceInstanceToGpus(NvU32 gpuMask) * @return GPUGRP pointer on success, NULL on error * */ -POBJGPUGRP +OBJGPUGRP * gpumgrGetGpuGrpFromInstance ( NvU32 gpugrpInstance @@ -2737,7 +2979,7 @@ gpumgrGetGpuGrpFromInstance * @return OBJGPUGRP pointer on success, NULL on error * */ -POBJGPUGRP +OBJGPUGRP * gpumgrGetGpuGrpFromGpu ( OBJGPU *pGpu @@ -3820,6 +4062,10 @@ gpumgrCacheSetMIGEnabled_IMPL(OBJGPU *pGpu, NvBool bMIGEnabled) NV_ASSERT_OR_GOTO(pMIGInfo != NULL, done); pMIGInfo->bMIGEnabled = bMIGEnabled; + if (!bMIGEnabled) + { + portMemSet(&pMIGInfo->gpuInstances, 0x0, sizeof(pMIGInfo->gpuInstances)); + } done: portSyncRwLockReleaseWrite(pGpuMgr->cachedMIGInfoLock); @@ -3877,7 +4123,7 @@ gpumgrCacheGetActiveDeviceIds_IMPL { NvU32 ciIdx; NvU32 swizzId = pGpuInstances[giIdx].swizzId; - NvBool *pbValidComputeInstances = + NvBool *pbValidComputeInstances = pGpuInstances[giIdx].bValidComputeInstances; if (!pGpuInstances[giIdx].bValid) @@ -3911,7 +4157,7 @@ gpumgrCacheGetActiveDeviceIds_IMPL total++; } } - + *pNumDevices = total; done: @@ -4233,3 +4479,41 @@ NvBool gpumgrIsSafeToReadGpuInfo(void) // return rmapiLockIsOwner() || (rmGpuLocksGetOwnedMask() != 0); } + +// +// Workaround for Bug 3809777. This is a HW bug happening in Ampere and +// Ada GPU's. For these GPU's, after device reset, CRS (Configuration Request +// Retry Status) is being released without waiting for GFW boot completion. +// MSI-X capability in the config space may be inconsistent when GFW boot +// is in progress, so this function checks if MSI-X is allowed. +// For Hopper and above, the CRS will be released after +// GFW boot completion, so the WAR is not needed. +// The bug will be exposed only when GPU is running inside guest in +// pass-through mode. +// +NvBool gpumgrIsDeviceMsixAllowed +( + RmPhysAddr bar0BaseAddr, + NvU32 pmcBoot1, + NvU32 pmcBoot42 +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + NvU32 chipArch; + + if ((hypervisorGetHypervisorType(pHypervisor) == OS_HYPERVISOR_UNKNOWN) || + !FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _REAL, pmcBoot1)) + { + return NV_TRUE; + } + + chipArch = DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42); + if ((chipArch != NV_PMC_BOOT_42_ARCHITECTURE_AD100) && + (chipArch != NV_PMC_BOOT_42_ARCHITECTURE_GA100)) + { + return NV_TRUE; + } + + return gpuIsMsixAllowed_TU102(bar0BaseAddr); +} diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c index 39e435b7ad..23c484c8d2 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr_sli.c @@ -37,6 +37,7 @@ #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "gpu/disp/kern_disp.h" #include "gpu/mem_mgr/mem_desc.h" +#include "gpu/mem_mgr/heap.h" #include "platform/sli/sli.h" #include "nvpcie.h" #include "nvhybridacpi.h" @@ -52,7 +53,26 @@ #include "ctrl/ctrl0000/ctrl0000gpu.h" #include "nvlimits.h" -static NV_STATUS gpumgrStateInitialized(void); +// +// gpumgrAreGpusInitialized +// +// Returns NV_TRUE if all GPUS in the given mask have been initialized. +// +NvBool gpumgrAreGpusInitialized(NvU32 gpuMask) +{ + NvU32 idx1 = 0; + OBJGPU *pGpu; + + while ( (pGpu = gpumgrGetNextGpu(gpuMask, &idx1)) != NULL ) + { + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_STATE_INITIALIZED)) + { + return NV_FALSE; + } + } + + return NV_TRUE; +} void gpumgrDetectSliLinkFromGpus @@ -82,7 +102,7 @@ gpumgrDetectSliLinkFromGpus *pSliLinkTestDone = *pSliLinkOutputMask = *pSliLinkEndsMask = 0; // Bail out early if all GPU'S haven't been loaded. - if (gpumgrStateInitialized() != NV_OK) + if (!gpumgrAreGpusInitialized(gpuMask)) { NV_PRINTF(LEVEL_WARNING, "All GPUs do not have state initialized\n"); @@ -238,40 +258,6 @@ gpumgrDetectSliLinkFromGpus *pVidLinkCount = vidLinkCount; } - -// -// Return a status indicating whether all GPU's have been initialized via StateInit(). -// -static NV_STATUS gpumgrStateInitialized(void) -{ - OBJGPU *pGpu = NULL; - NvU32 gpuMask = 0; - NvU32 gpuCount = 0; - NvU32 gpuIndex = 0; - NV_STATUS status = NV_OK; - - gpumgrGetGpuAttachInfo(&gpuCount, &gpuMask); - - pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); - if (pGpu == NULL) - { - return NV_ERR_INVALID_POINTER; - } - - do - { - if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_STATE_INITIALIZED)) - { - status = NV_ERR_INVALID_STATE; - } - - pGpu = gpumgrGetNextGpu(gpuMask, &gpuIndex); - - } while (pGpu); - - return (status); -} - /*! * @brief Updates the GPU routing information for the * 2 specified GPUs using the 2 Pinset Indices specified. @@ -400,7 +386,7 @@ gpumgrDetectHighSpeedVideoBridges(NvU32 linkOutputMask) pKernelDisp = GPU_GET_KERNEL_DISPLAY(pGpu); if ( - (pKernelDisp == NULL)) + pKernelDisp == NULL) { NV_ASSERT(pKernelDisp != NULL); // This should not happen continue; diff --git a/src/nvidia/src/kernel/mem_mgr/egm_mem.c b/src/nvidia/src/kernel/mem_mgr/egm_mem.c index 8b0d52a14e..a1abbd530c 100644 --- a/src/nvidia/src/kernel/mem_mgr/egm_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/egm_mem.c @@ -51,6 +51,7 @@ egmmemConstruct_IMPL NV_STATUS rmStatus = NV_OK; FB_ALLOC_INFO *pFbAllocInfo = NULL; FB_ALLOC_PAGE_FORMAT *pFbAllocPageFormat = NULL; + RM_ATTR_PAGE_SIZE pageSizeAttr; MEMORY_DESCRIPTOR *pMemDesc; HWRESOURCE_INFO hwResource; NvU64 sizeOut; @@ -171,6 +172,12 @@ egmmemConstruct_IMPL memdescSetGpuCacheAttrib(pMemDesc, gpuCacheAttrib); + + pageSizeAttr = dmaNvos32ToPageSizeAttr(pAllocData->attr, pAllocData->attr2); + NV_ASSERT_OK_OR_GOTO(rmStatus, memmgrSetMemDescPageSize_HAL(pGpu, GPU_GET_MEMORY_MANAGER(pGpu), pMemDesc, + AT_GPU, pageSizeAttr), + mem_construct_failed); + memdescTagAlloc(rmStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_45, pMemDesc); NV_ASSERT_OK_OR_GOTO(rmStatus, rmStatus, mem_construct_failed); @@ -248,6 +255,10 @@ egmmemValidateParams NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, stdmemValidateParams(pGpu, hClient, pAllocData)); + NV_CHECK_OR_RETURN(LEVEL_ERROR, + FLD_TEST_DRF(OS32, _ATTR2, _USE_EGM, _TRUE, pAllocData->attr2), + NV_ERR_INVALID_ARGUMENT); + // Make sure EGM memory is not requested if local EGM is not supported if (!memmgrIsLocalEgmEnabled(pMemoryManager)) { diff --git a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c index faa76f99e1..1197849633 100644 --- a/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/fabric_vaspace.c @@ -44,8 +44,6 @@ #include "class/cl00fc.h" // FABRIC_VASPACE_A #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER #include "class/cl0080.h" // NV01_DEVICE_0 -#include "gpu/device/device.h" -#include "gpu/subdevice/subdevice.h" #include "deprecated/rmapi_deprecated.h" #include "rmapi/rs_utils.h" #include "vgpu/vgpu_events.h" @@ -983,6 +981,7 @@ fabricvaspaceUnmapPhysMemdesc_IMPL NvU64 mapLength; FABRIC_VASPACE_MAPPING_REGIONS regions; NvU32 numRegions; + RmPhysAddr *pFabricPteArray; fabricPageSize = memdescGetPageSize(pFabricMemDesc, AT_GPU); @@ -993,6 +992,8 @@ fabricvaspaceUnmapPhysMemdesc_IMPL ®ions, &numRegions); NV_ASSERT_OR_RETURN_VOID(numRegions != 0); + pFabricPteArray = memdescGetPteArray(pFabricMemDesc, AT_GPU); + for (i = 0; i < numRegions; i++) { fabricPageCount = @@ -1008,12 +1009,12 @@ fabricvaspaceUnmapPhysMemdesc_IMPL { if (fabricPageCount == 1) { - fabricAddr = pFabricMemDesc->_pteArray[0] + fabricOffset; + fabricAddr = pFabricPteArray[0] + fabricOffset; } else { - fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / - pFabricMemDesc->pageArrayGranularity]; + fabricAddr = pFabricPteArray[fabricOffset / + pFabricMemDesc->pageArrayGranularity]; } vaspaceUnmap(pFabricVAS->pGVAS, pPhysMemDesc->pGpu, fabricAddr, @@ -1060,6 +1061,8 @@ fabricvaspaceMapPhysMemdesc_IMPL MEMORY_DESCRIPTOR *pTempMemdesc; NvU32 aperture; NvU32 peerNumber = BUS_INVALID_PEER; + RmPhysAddr *pFabricPteArray; + RmPhysAddr *pPhysPteArray; NV_ASSERT_OR_RETURN(pFabricMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(pPhysMemDesc != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1123,6 +1126,9 @@ fabricvaspaceMapPhysMemdesc_IMPL ®ions, &numRegions); NV_ASSERT_OR_RETURN(numRegions != 0, NV_ERR_INVALID_ARGUMENT); + pFabricPteArray = memdescGetPteArray(pFabricMemDesc, AT_GPU); + pPhysPteArray = memdescGetPteArray(pPhysMemDesc, AT_GPU); + for (i = 0; i < numRegions; i++) { fabricPageCount = ((memdescGetPteArraySize(pFabricMemDesc, AT_GPU) == 1) || @@ -1139,23 +1145,23 @@ fabricvaspaceMapPhysMemdesc_IMPL { if (fabricPageCount == 1) { - fabricAddr = pFabricMemDesc->_pteArray[0] + fabricOffset; + fabricAddr = pFabricPteArray[0] + fabricOffset; } else { - fabricAddr = pFabricMemDesc->_pteArray[fabricOffset / - pFabricMemDesc->pageArrayGranularity]; + fabricAddr = pFabricPteArray[fabricOffset / + pFabricMemDesc->pageArrayGranularity]; } if (pageArray.count == 1) { - physAddr = pPhysMemDesc->_pteArray[0] + physOffset; + physAddr = pPhysPteArray[0] + physOffset; pageArray.pData = &physAddr; } else { - pageArray.pData = &pPhysMemDesc->_pteArray[physOffset / - pPhysMemDesc->pageArrayGranularity]; + pageArray.pData = &pPhysPteArray[physOffset / + pPhysMemDesc->pageArrayGranularity]; } // @@ -1232,6 +1238,14 @@ fabricvaspaceInitUCRange_IMPL pFabricVAS->ucFabricLimit = fabricBase + fabricSize - 1; pFabricVAS->ucFabricInUseSize = 0; pFabricVAS->ucFabricFreeSize = fabricSize; + + if (IS_VIRTUAL(pGpu)) + { + VGPU_STATIC_INFO *pVSI = GPU_GET_STATIC_INFO(pGpu); + + pVSI->flaInfo.base = fabricBase; + pVSI->flaInfo.size = fabricSize; + } } return NV_OK; diff --git a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c index 0d42361fe4..790604f085 100644 --- a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c @@ -54,6 +54,7 @@ #include "deprecated/rmapi_deprecated.h" #include "rmapi/rs_utils.h" #include "gpu/mem_mgr/vaspace_api.h" +#include "platform/sli/sli.h" @@ -120,7 +121,7 @@ _gvaspaceFreeVASBlock ( OBJEHEAP *pHeap, void *pEnv, - PEMEMBLOCK pMemBlock, + EMEMBLOCK *pMemBlock, NvU32 *pContinue, NvU32 *pInvalCursor ); @@ -1980,7 +1981,7 @@ gvaspaceIncAllocRefCnt_IMPL return NV_OK; } -POBJEHEAP +OBJEHEAP * gvaspaceGetHeap_IMPL(OBJGVASPACE *pGVAS) { return pGVAS->pHeap; @@ -2075,7 +2076,11 @@ gvaspaceGetPasid_IMPL(OBJGVASPACE *pGVAS, NvU32 *pPasid) pGVAS->bIsAtsEnabled, pGVAS->processAddrSpaceId); NV_ASSERT_OR_RETURN(pGVAS->bIsAtsEnabled, NV_ERR_INVALID_STATE); - NV_ASSERT_OR_RETURN(pGVAS->processAddrSpaceId != NV_U32_MAX, NV_ERR_INVALID_STATE); + if (pGVAS->processAddrSpaceId == NV_U32_MAX) + { + return NV_ERR_NOT_READY; + } + *pPasid = pGVAS->processAddrSpaceId; return NV_OK; } @@ -4628,7 +4633,7 @@ _gvaspacePinLazyPageTables ) { NV_STATUS status = NV_OK; - PEMEMBLOCK pMemBlock; + EMEMBLOCK *pMemBlock; PGVAS_BLOCK pVASBlock; // Search for the VA block, abort if not found. @@ -4699,7 +4704,7 @@ _gvaspaceFreeVASBlock ( OBJEHEAP *pHeap, void *pEnv, - PEMEMBLOCK pMemBlock, + EMEMBLOCK *pMemBlock, NvU32 *pContinue, NvU32 *pInvalCursor ) @@ -4824,6 +4829,12 @@ _gvaspaceMappingRemove NV_STATUS status = NV_OK; GVAS_MAPPING *pMapNode = NULL; const NvU32 gpuMask = NVBIT(pGpu->gpuInstance); + NvU64 nodeVaLo; + NvU64 nodeVaHi; + const VAS_MAP_FLAGS flags = { 0 }; + NvBool bPartialUnmap = NV_FALSE; + NvBool bLoEntryAdded = NV_FALSE; + NvBool bHiEntryAdded = NV_FALSE; // Search for existing mapping. status = btreeSearch(vaLo, (NODE**)&pMapNode, &pVASBlock->pMapTree->node); @@ -4831,19 +4842,79 @@ _gvaspaceMappingRemove // Check for consistency. NV_ASSERT_OR_RETURN(gpuMask == (pMapNode->gpuMask & gpuMask), NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pMapNode->node.keyStart == vaLo, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(pMapNode->node.keyEnd == vaHi, NV_ERR_INVALID_ARGUMENT); + if (pMapNode->node.keyStart != vaLo || + pMapNode->node.keyEnd != vaHi) + { + // check the entire range falls within the existing mapping + NV_ASSERT_OR_RETURN(pMapNode->node.keyStart <= vaLo && + pMapNode->node.keyEnd >= vaHi, NV_ERR_INVALID_ARGUMENT); + // Allow partial unmap only when the mapping is not shared + NV_ASSERT_OR_RETURN(pMapNode->gpuMask == gpuMask, + NV_ERR_INVALID_ARGUMENT); + NV_PRINTF(LEVEL_INFO, "Partial unmap: Removing vaLo: 0x%llx vaHi: 0x%llx.\n", + vaLo, vaHi); + bPartialUnmap = NV_TRUE; + } // Remove GPU from mapping mask. pMapNode->gpuMask &= ~gpuMask; + nodeVaLo = pMapNode->node.keyStart; + nodeVaHi = pMapNode->node.keyEnd; // Remove mapping if unused. if (0 == pMapNode->gpuMask) { btreeUnlink(&pMapNode->node, (NODE**)&pVASBlock->pMapTree); - portMemFree(pMapNode); } + if (nodeVaLo < vaLo) + { + status = _gvaspaceMappingInsert(pGVAS, pGpu, pVASBlock, nodeVaLo, vaLo - 1, flags); + NV_ASSERT_OR_GOTO(NV_OK == status, done); + NV_PRINTF(LEVEL_INFO, "Partial unmap: Inserting partial vaLo: 0x%llx " + "vaHi: 0x%llx. status: 0x%x\n", nodeVaLo, vaLo - 1, status); + bLoEntryAdded = NV_TRUE; + } + if (nodeVaHi > vaHi) + { + status = _gvaspaceMappingInsert(pGVAS, pGpu, pVASBlock, vaHi + 1, nodeVaHi, flags); + NV_ASSERT_OR_GOTO(NV_OK == status, done); + NV_PRINTF(LEVEL_INFO, "Partial unmap: Inserting partial vaLo: 0x%llx " + "vaHi: 0x%llx. status: 0x%x\n", + vaHi + 1, nodeVaHi, status); + bHiEntryAdded = NV_TRUE; + } + +done: + if (bPartialUnmap && + (status != NV_OK)) + { + if (bLoEntryAdded) + { + NV_ASSERT_OK(_gvaspaceMappingRemove(pGVAS, pGpu, pVASBlock, + nodeVaLo, vaLo - 1)); + } + if (bHiEntryAdded) + { + NV_ASSERT_OK(_gvaspaceMappingRemove(pGVAS, pGpu, pVASBlock, + vaHi + 1, nodeVaHi)); + } + + // Add the original mapping back + portMemSet(pMapNode, 0, sizeof(*pMapNode)); + pMapNode->node.keyStart = nodeVaLo; + pMapNode->node.keyEnd = nodeVaHi; + pMapNode->gpuMask = gpuMask; + NV_ASSERT_OK(btreeInsert(&pMapNode->node, (NODE**)&pVASBlock->pMapTree)); + + return status; + } + + // Free if unused. + if (0 == pMapNode->gpuMask) + { + portMemFree(pMapNode); + } return status; } diff --git a/src/nvidia/src/kernel/mem_mgr/hw_resources.c b/src/nvidia/src/kernel/mem_mgr/hw_resources.c index c2df1fc71e..6bd7e20529 100644 --- a/src/nvidia/src/kernel/mem_mgr/hw_resources.c +++ b/src/nvidia/src/kernel/mem_mgr/hw_resources.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,6 +25,7 @@ #include "mem_mgr_internal.h" #include "mem_mgr/hw_resources.h" #include "gpu/mem_mgr/mem_desc.h" +#include "vgpu/vgpu_util.h" #include "mem_mgr/mem.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/heap.h" @@ -32,7 +33,6 @@ #include "rmapi/client.h" #include "mmu/gmmu_fmt.h" #include "gpu/device/device.h" -#include "gpu/subdevice/subdevice.h" #include "class/cl0041.h" // NV04_MEMORY #include "class/cl003e.h" // NV01_MEMORY_SYSTEM @@ -134,6 +134,22 @@ hwresConstruct_IMPL pMemory->osDeviceHandle = pAllocData->osDeviceHandle; + if (IS_VIRTUAL(pGpu) && vgpuIsGuestManagedHwAlloc(pGpu)) + { + pAllocData->compPageShift = pMemorySystemConfig->comprPageShift; + pAllocData->compressedKind = pAllocData->kind; + + if (memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_COMPRESSIBLE, pAllocData->kind)) + { + pAllocData->uncompressedKind = memmgrGetUncompressedKind_HAL(pGpu, pMemoryManager, + pAllocData->kind, NV_FALSE); + } + else + { + pAllocData->uncompressedKind = pAllocData->kind; + } + } + if (!IS_VIRTUAL(pGpu) && !IS_GSP_CLIENT(pGpu)) { NvU32 compressedKind; diff --git a/src/nvidia/src/kernel/mem_mgr/mem.c b/src/nvidia/src/kernel/mem_mgr/mem.c index 7a2decd3c8..78fef97d90 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem.c +++ b/src/nvidia/src/kernel/mem_mgr/mem.c @@ -25,6 +25,7 @@ #include "mem_mgr/fla_mem.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/disp/disp_objs.h" @@ -34,6 +35,7 @@ #include "gpu/device/device.h" #include "gpu/subdevice/subdevice.h" #include "vgpu/rpc.h" +#include "platform/sli/sli.h" #include "class/cl0041.h" // NV04_MEMORY #include "class/cl003e.h" // NV01_MEMORY_SYSTEM @@ -737,15 +739,25 @@ memGetByHandleAndGroupedGpu_IMPL Memory **ppMemory ) { - Device *pDevice; + Memory *pMemory; NV_STATUS status; + Device *pDevice; - // Get device handle - status = deviceGetByInstance(pClient, gpuGetDeviceInstance(pGpu), &pDevice); + status = memGetByHandle(pClient, hMemory, &pMemory); if (status != NV_OK) - return NV_ERR_INVALID_OBJECT_HANDLE; + return status; + + pDevice = pMemory->pDevice; + + if ((pDevice == NULL) || + (gpumgrGetParentGPU(pGpu) != GPU_RES_GET_GPU(pDevice))) + { + *ppMemory = NULL; + return NV_ERR_OBJECT_NOT_FOUND; + } - return memGetByHandleAndDevice(pClient, hMemory, RES_GET_HANDLE(pDevice), ppMemory); + *ppMemory = pMemory; + return NV_OK; } NV_STATUS @@ -1017,19 +1029,6 @@ memGetMemInterMapParams_IMPL // gpumgrSetBcEnabledStatus(pGpu, bcState); - // - // Mapping Guest allocated memory in PF is not supported - // - if (pSrcMemDesc->pGpu != pGpu && gpuIsSriovEnabled(pGpu) && - !(memdescGetFlag(pSrcMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED))) - { - // - // Memory allocated by pSrcMemDesc->pGpu needs to be - // remapped for pGpu as requested by client. - // - pParams->bDmaMapNeeded = NV_TRUE; - } - pParams->pSrcMemDesc = pSrcMemDesc; pFlaMemory = dynamicCast(pMemoryRef->pResource, FlaMemory); diff --git a/src/nvidia/src/kernel/mem_mgr/mem_export.c b/src/nvidia/src/kernel/mem_mgr/mem_export.c new file mode 100644 index 0000000000..f61136bf2f --- /dev/null +++ b/src/nvidia/src/kernel/mem_mgr/mem_export.c @@ -0,0 +1,1234 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions managing memory export class + * + *****************************************************************************/ + +#define NVOC_MEM_EXPORT_H_PRIVATE_ACCESS_ALLOWED + +/* + * Lock ordering + * + * RMAPI Lock (can be removed once RM-core allows it, for now RO-only) + * |_External Client Lock (e.g. CUDA client) + * |_Export Module Lock + * |_Export Descriptor Lock + * |_GPU(s) Lock as needed + */ + +#include "os/os.h" +#include "core/locks.h" +#include "os/capability.h" +#include "core/system.h" +#include "core/thread_state.h" +#include "mem_mgr/mem_export.h" +#include "resserv/rs_resource.h" +#include "compute/fabric.h" +#include "kernel/gpu/mem_mgr/mem_mgr.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "gpu/device/device.h" +#include "gpu/subdevice/subdevice.h" +#include "containers/list.h" + +typedef struct mem_export_uuid +{ + NvU64 expId; + NvU16 nodeId; + NvU8 unused[6]; +} MEM_EXPORT_UUID; + +typedef struct attached_parent_info +{ + void *pGpuOsInfo; + OBJGPU *pGpu; + NvU64 refCount; + NvHandle hClient; + NvHandle hParent; // hDevice or hSubdevice + + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; +} ATTACHED_PARENT_INFO; + +MAKE_LIST(ATTACHED_PARENT_INFO_LIST, ATTACHED_PARENT_INFO); + +typedef struct attached_mem_info +{ + ATTACHED_PARENT_INFO *pParentInfo; + + NvHandle hDupedMem; + NvU8 addressSpace; +} ATTACHED_MEM_INFO; + +typedef struct mem_export_info +{ + NV00E0_ALLOCATION_PARAMETERS cachedParams; + + NvU64 refCount; + MEM_EXPORT_UUID uuid; + + struct + { + NvU32 gpu; + NvU32 migGi[KMIGMGR_MAX_GPU_SWIZZID]; + } attachedUsageCount[NV_MAX_DEVICES]; + + ATTACHED_PARENT_INFO_LIST parentInfoList; + + // Temp stash before committing the change. + ATTACHED_MEM_INFO stashMemInfos[NV00E0_MAX_EXPORT_HANDLES]; + + // + // The lock protects MEM_EXPORT_INFO, the mem export descriptor. + // + // The lock should be taken only if a mem export descriptor is safe + // to access i.e., holding the module lock or the accessing thread + // has the mem export descriptor refcounted. + // + PORT_RWLOCK *pLock; + + // Should be last + ATTACHED_MEM_INFO memInfos[0]; +} MEM_EXPORT_INFO; + +NvU16 +memoryExportGetNodeId +( + NV_EXPORT_MEM_PACKET *pExportPacket +) +{ + ct_assert(sizeof(MEM_EXPORT_UUID) == sizeof(pExportPacket->uuid)); + + MEM_EXPORT_UUID *pExportUuid = (MEM_EXPORT_UUID*)pExportPacket->uuid; + + return pExportUuid->nodeId; +} + +static NV_STATUS +_memoryexportDup +( + MemoryExport *pMemoryExport, + NV00E0_ALLOCATION_PARAMETERS *pAllocParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + SysMemExportCacheEntry *pEntry; + MEM_EXPORT_INFO *pExportInfo; + MEM_EXPORT_UUID uuid; + + // TODO: Perform checks to make sure the client is allowed to dup. + + ct_assert(sizeof(NV_EXPORT_MEM_PACKET) == NV_MEM_EXPORT_PACKET_LEN); + ct_assert(sizeof(MEM_EXPORT_UUID) == NV_MEM_EXPORT_UUID_LEN); + + portMemCopy(&uuid, NV_MEM_EXPORT_UUID_LEN, + pAllocParams->packet.uuid, NV_MEM_EXPORT_UUID_LEN); + + // + // Keep the module lock throughout so that the destructor can't delete + // pExportInfo underneath us until we refcount it. + // + portSyncRwLockAcquireRead(pSys->pSysMemExportModuleLock); + + pEntry = multimapFindItem(&pSys->sysMemExportCache, uuid.nodeId, + uuid.expId); + if (pEntry == NULL) + { + portSyncRwLockReleaseRead(pSys->pSysMemExportModuleLock); + return NV_ERR_OBJECT_NOT_FOUND; + } + + pExportInfo = pEntry->pData; + + portSyncRwLockAcquireWrite(pExportInfo->pLock); + + *pAllocParams = pExportInfo->cachedParams; + + pExportInfo->refCount++; + + portSyncRwLockReleaseWrite(pExportInfo->pLock); + + portSyncRwLockReleaseRead(pSys->pSysMemExportModuleLock); + + pMemoryExport->pExportInfo = pExportInfo; + + return NV_OK; +} + +static void +_memoryexportGenerateUuid +( + MEM_EXPORT_UUID *pUuid +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + Fabric *pFabric = SYS_GET_FABRIC(pSys); + + ct_assert(sizeof(MEM_EXPORT_UUID) == NV_MEM_EXPORT_UUID_LEN); + + pUuid->nodeId = fabricGetNodeId(pFabric); + pUuid->expId = portAtomicExIncrementU64(&pSys->sysExportObjectCounter); +} + +static NV_STATUS +_memoryexportConstruct +( + MemoryExport *pMemoryExport, + NV00E0_ALLOCATION_PARAMETERS *pAllocParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + MEM_EXPORT_INFO *pExportInfo; + NvU64 size; + NV_STATUS status; + SysMemExportCacheEntry *pEntry; + SYS_MEM_EXPORT_CACHESubmap *pSubmap = NULL; + + if (!pSys->bSysUuidBasedMemExportSupport) + return NV_ERR_NOT_SUPPORTED; + + if (pAllocParams->numMaxHandles == 0) + return NV_ERR_INVALID_ARGUMENT; + + size = sizeof(*pExportInfo) + (pAllocParams->numMaxHandles * + sizeof(pExportInfo->memInfos[0])); + + pExportInfo = portMemAllocNonPaged(size); + if (pExportInfo == NULL) + return NV_ERR_NO_MEMORY; + + portMemSet(pExportInfo, 0, size); + + _memoryexportGenerateUuid(&pExportInfo->uuid); + + pExportInfo->pLock = portSyncRwLockCreate( + portMemAllocatorGetGlobalNonPaged()); + if (pExportInfo->pLock == NULL) + { + status = NV_ERR_NO_MEMORY; + goto free_mem; + } + + portMemCopy(pAllocParams->packet.uuid, NV_MEM_EXPORT_UUID_LEN, + &pExportInfo->uuid, NV_MEM_EXPORT_UUID_LEN); + + pExportInfo->cachedParams.packet = pAllocParams->packet; + pExportInfo->cachedParams.numMaxHandles = pAllocParams->numMaxHandles; + pExportInfo->cachedParams.flags = pAllocParams->flags; + + portMemCopy(pExportInfo->cachedParams.metadata, + NV_MEM_EXPORT_METADATA_LEN, + pAllocParams->metadata, + NV_MEM_EXPORT_METADATA_LEN); + + listInit(&pExportInfo->parentInfoList, portMemAllocatorGetGlobalNonPaged()); + + pExportInfo->refCount = 1; + + pMemoryExport->pExportInfo = pExportInfo; + + // Cache entry now... + portSyncRwLockAcquireWrite(pSys->pSysMemExportModuleLock); + + if (multimapFindSubmap(&pSys->sysMemExportCache, + pExportInfo->uuid.nodeId) == NULL) + { + if ((pSubmap = multimapInsertSubmap(&pSys->sysMemExportCache, + pExportInfo->uuid.nodeId)) == NULL) + { + status = NV_ERR_NO_MEMORY; + goto fail; + } + } + + pEntry = multimapInsertItemNew(&pSys->sysMemExportCache, + pExportInfo->uuid.nodeId, + pExportInfo->uuid.expId); + if (pEntry == NULL) + { + status = NV_ERR_INSERT_DUPLICATE_NAME; + goto fail; + } + + pEntry->pData = pExportInfo; + + portSyncRwLockReleaseWrite(pSys->pSysMemExportModuleLock); + + return NV_OK; + +fail: + listDestroy(&pExportInfo->parentInfoList); + + if (pSubmap != NULL) + multimapRemoveSubmap(&pSys->sysMemExportCache, pSubmap); + + portSyncRwLockReleaseWrite(pSys->pSysMemExportModuleLock); + + portSyncRwLockDestroy(pExportInfo->pLock); + pExportInfo->pLock = NULL; + +free_mem: + portMemFree(pExportInfo); + + return status; +} + +NV_STATUS +memoryexportConstruct_IMPL +( + MemoryExport *pMemoryExport, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV_STATUS status; + NV00E0_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; + + if (pAllocParams->flags & NV_MEM_EXPORT_FLAGS_DUP_BY_UUID) + status = _memoryexportDup(pMemoryExport, pAllocParams); + else + status = _memoryexportConstruct(pMemoryExport, pAllocParams); + + return status; +} + +static void +_memoryexportDetachParent +( + MEM_EXPORT_INFO *pExportInfo, + ATTACHED_PARENT_INFO *pParentInfo +) +{ + THREAD_STATE_NODE *pThreadNode; + THREAD_STATE_FREE_CALLBACK freeCallback; + NvU32 deviceInstance; + + NV_ASSERT_OR_RETURN_VOID(pParentInfo->refCount == 0); + + if (pParentInfo->pGpuOsInfo != NULL) + { + deviceInstance = gpuGetDeviceInstance(pParentInfo->pGpu); + + if (pParentInfo->pKernelMIGGpuInstance != NULL) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance = pParentInfo->pKernelMIGGpuInstance; + NvU32 swizzId = pKernelMIGGpuInstance->swizzId; + + pExportInfo->attachedUsageCount[deviceInstance].migGi[swizzId]--; + + // Update giIdMasks if the MIG instance is no more used.. + if (pExportInfo->attachedUsageCount[deviceInstance].migGi[swizzId] == 0) + pExportInfo->cachedParams.giIdMasks[deviceInstance] &= !NVBIT(swizzId); + + // Drop refcount on GPU instance.. + NV_ASSERT_OK(kmigmgrDecRefCount(pKernelMIGGpuInstance->pShare)); + } + + // Drop refcount on GPU + NV_ASSERT_OR_RETURN_VOID(threadStateGetCurrent(&pThreadNode, + NULL) == NV_OK); + + freeCallback.pCb = osReleaseGpuOsInfo; + freeCallback.pCbData = (void *)pParentInfo->pGpuOsInfo; + + NV_ASSERT_OK(threadStateEnqueueCallbackOnFree(pThreadNode, + &freeCallback)); + + pExportInfo->attachedUsageCount[deviceInstance].gpu--; + + // Update deviceInstanceMask if the GPU is no more used.. + if (pExportInfo->attachedUsageCount[deviceInstance].gpu == 0) + pExportInfo->cachedParams.deviceInstanceMask &= !NVBIT(deviceInstance); + } + + listRemove(&pExportInfo->parentInfoList, pParentInfo); +} + +static void +_memoryexportUndupMem +( + ATTACHED_PARENT_INFO *pParentInfo, + ATTACHED_MEM_INFO *pMemInfo +) +{ + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_ASSERT_OK(pRmApi->Free(pRmApi, pParentInfo->hClient, + pMemInfo->hDupedMem)); + + pMemInfo->hDupedMem = 0; +} + +static void +_memoryexportDetachMemAndParent +( + MEM_EXPORT_INFO *pExportInfo, + ATTACHED_MEM_INFO *pMemInfo +) +{ + ATTACHED_PARENT_INFO *pParentInfo = pMemInfo->pParentInfo; + + _memoryexportUndupMem(pParentInfo, pMemInfo); + + pParentInfo->refCount--; + pMemInfo->pParentInfo = NULL; + + pExportInfo->cachedParams.numCurHandles--; + + // If parent info is unused, drop it. + if (pParentInfo->refCount == 0) + _memoryexportDetachParent(pExportInfo, pParentInfo); +} + +void +memoryexportDestruct_IMPL +( + MemoryExport *pMemoryExport +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + MEM_EXPORT_INFO *pExportInfo = pMemoryExport->pExportInfo; + SYS_MEM_EXPORT_CACHESubmap *pSubmap; + NvU16 i, j; + NvU32 gpuMask = GPUS_LOCK_ALL; + + if (pExportInfo == NULL) + return; + + pMemoryExport->pExportInfo = NULL; + + // + // Take pSysMemExportModuleLock to synchronize with _memoryexportDup(). + // We don't want to delete pExportInfo under it. + // + portSyncRwLockAcquireWrite(pSys->pSysMemExportModuleLock); + portSyncRwLockAcquireWrite(pExportInfo->pLock); + + pExportInfo->refCount--; + + if (pExportInfo->refCount > 0) + { + portSyncRwLockReleaseWrite(pExportInfo->pLock); + portSyncRwLockReleaseWrite(pSys->pSysMemExportModuleLock); + + return; + } + + // + // Continue to hold pSysMemExportModuleLock to update the + // sysMemExportCache and may undup/detach memory from + // hSysMemExportClient + // + + // Empty caches so new calls to _memoryexportDup() fail. + multimapRemoveItemByKey(&pSys->sysMemExportCache, + pExportInfo->uuid.nodeId, + pExportInfo->uuid.expId); + + pSubmap = multimapFindSubmap(&pSys->sysMemExportCache, + pExportInfo->uuid.nodeId); + if ((pSubmap != NULL) && + (multimapCountSubmapItems(&pSys->sysMemExportCache, pSubmap) == 0)) + multimapRemoveSubmap(&pSys->sysMemExportCache, pSubmap); + + // Now I am the only one holding the pExportInfo, drop the lock. + portSyncRwLockReleaseWrite(pExportInfo->pLock); + + NV_ASSERT_OK(rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM, + &gpuMask)); + + for (i = 0; i < pExportInfo->cachedParams.numMaxHandles; i++) + { + if (pExportInfo->memInfos[i].hDupedMem != 0) + { + _memoryexportDetachMemAndParent(pExportInfo, + &pExportInfo->memInfos[i]); + } + } + + // Drop rest of the locks as memory undup/detach is done.. + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + + portSyncRwLockReleaseWrite(pSys->pSysMemExportModuleLock); + + for (j = 0; j < NV_MAX_DEVICES; j++) + { + NV_ASSERT(pExportInfo->attachedUsageCount[j].gpu == 0); + + for (i = 0; i < KMIGMGR_MAX_GPU_SWIZZID; i++) + NV_ASSERT(pExportInfo->attachedUsageCount[j].migGi[i] == 0); + NV_ASSERT(pExportInfo->cachedParams.giIdMasks[j] == 0); + } + + NV_ASSERT(pExportInfo->cachedParams.numCurHandles == 0); + NV_ASSERT(pExportInfo->cachedParams.deviceInstanceMask == 0); + + NV_ASSERT(listCount(&pExportInfo->parentInfoList) == 0); + listDestroy(&pExportInfo->parentInfoList); + + portSyncRwLockDestroy(pExportInfo->pLock); + pExportInfo->pLock = NULL; + + portMemFree(pExportInfo); + pMemoryExport->pExportInfo = NULL; +} + +NvBool +memoryexportCanCopy_IMPL +( + MemoryExport *pMemoryExport +) +{ + return NV_FALSE; +} + +static NV_STATUS +_memoryexportVerifyMem +( + OBJGPU *pGpu, + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance, + RsClient *pClient, + NvHandle hSrcHandle, + NvU8 *pAddrSpace +) +{ + NV_STATUS status; + RsResourceRef *pSrcMemoryRef; + Memory *pSrcMemory; + MEMORY_DESCRIPTOR *pMemDesc; + CALL_CONTEXT callContext; + NvU32 addrSpace; + NvU32 mapFlags; + + // + // Don't not use memGetByHandle() or access pSrcMemory->pMemDesc here. + // There are certain memory types like MCFLA which might not be ready + // at the time of attachment, and hence could cause memGetByHandle() + // fail with NV_ERR_NOT_READY, which we don't want in this case. + // + status = clientGetResourceRef(pClient, hSrcHandle, &pSrcMemoryRef); + if (status != NV_OK) + return status; + + pSrcMemory = dynamicCast(pSrcMemoryRef->pResource, Memory); + if (pSrcMemory == NULL) + return NV_ERR_INVALID_OBJECT_HANDLE; + + if (!memIsExportAllowed(pSrcMemory)) + return NV_ERR_NOT_SUPPORTED; + + portMemSet(&callContext, 0, sizeof(callContext)); + callContext.pClient = pClient; + callContext.pResourceRef = pSrcMemoryRef; + + // + // rmApiGetEffectiveAddrSpace expect mapping flags to be set as DIRECT for + // GPU cacheable Sysmem for Pre-Ampere chips. We are not doing any mapping + // here, so passing this as workaround to get the expected address space. + // + mapFlags = FLD_SET_DRF(OS33, _FLAGS, _MAPPING, _DIRECT, 0); + + status = memGetMapAddrSpace(pSrcMemory, &callContext, mapFlags, &addrSpace); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to query address space: 0x%x\n", status); + return status; + } + + switch(addrSpace) + { + case ADDR_SYSMEM: + *pAddrSpace = NV00E0_ADDR_SPACE_TYPE_SYSMEM; + break; + case ADDR_FBMEM: + *pAddrSpace = NV00E0_ADDR_SPACE_TYPE_VIDMEM; + break; + case ADDR_FABRIC_V2: + *pAddrSpace = NV00E0_ADDR_SPACE_TYPE_FABRIC; + break; + case ADDR_FABRIC_MC: + *pAddrSpace = NV00E0_ADDR_SPACE_TYPE_FABRIC_MC; + break; + default: + return NV_ERR_NOT_SUPPORTED; + } + + // No need to inspect parent GPU if a deviceless object + if (pGpu == NULL) + return NV_OK; + + if (pKernelMIGGpuInstance != NULL) + { + if ((pKernelMIGGpuInstance->pMemoryPartitionHeap != pSrcMemory->pHeap)) + return NV_ERR_INVALID_OBJECT_PARENT; + } + + // Check if hMemory belongs to the same pGpu + pMemDesc = pSrcMemory->pMemDesc; + if ((pSrcMemory->pGpu != pGpu) && (pMemDesc->pGpu != pGpu)) + return NV_ERR_INVALID_OBJECT_PARENT; + + return NV_OK; +} + +static NV_STATUS +_memoryexportValidateAndDupMem +( + RsClient *pSrcClient, + NvHandle hSrcMem, + ATTACHED_PARENT_INFO *pDestParentInfo, + ATTACHED_MEM_INFO *pMemInfo +) +{ + NV_STATUS status; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + status = _memoryexportVerifyMem(pDestParentInfo->pGpu, + pDestParentInfo->pKernelMIGGpuInstance, + pSrcClient, hSrcMem, + &pMemInfo->addressSpace); + if (status != NV_OK) + return status; + + status = pRmApi->DupObject(pRmApi, pDestParentInfo->hClient, + pDestParentInfo->hParent, + &pMemInfo->hDupedMem, + pSrcClient->hClient, hSrcMem, 0); + if (status != NV_OK) + return status; + + return NV_OK; +} + +// +// This function is called without holding GPU lock, so don't access GPU until +// validated. +// +static NV_STATUS +_memoryexportValidateParent +( + NV00E0_CTRL_EXPORT_MEM_PARAMS *pExportParams, + void **ppGpuOsInfo, + OBJGPU **ppGpu, + Device **ppDevice, + Subdevice **ppSubdevice +) +{ + NV_STATUS status; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + RS_RES_CONTROL_PARAMS_INTERNAL *pParams = pCallContext->pControlParams; + RsClient *pClient = pCallContext->pClient; + + *ppGpuOsInfo = NULL; + *ppGpu = NULL; + *ppDevice = NULL; + *ppSubdevice = NULL; + + // Non-device parent, nothing to do.. + if (pClient->hClient == pExportParams->hParent) + return NV_OK; + + // + // Validate the parent subdevice/device is same as that of ref-counted by + // the OS layer. + // + status = deviceGetByHandle(pClient, pExportParams->hParent, ppDevice); + if (status != NV_OK) + { + status = subdeviceGetByHandle(pClient, pExportParams->hParent, + ppSubdevice); + if (status != NV_OK) + return status; + + *ppGpu = GPU_RES_GET_GPU(*ppSubdevice); + } + else + { + *ppGpu = GPU_RES_GET_GPU(*ppDevice); + } + + if(!osMatchGpuOsInfo(*ppGpu, pParams->secInfo.gpuOsInfo)) + return NV_ERR_INVALID_DEVICE; + + *ppGpuOsInfo = pParams->secInfo.gpuOsInfo; + + return NV_OK; +} + +static NV_STATUS +_memoryexportGetParentHandles +( + OBJGPU *pGpu, + Device *pDevice, + Subdevice *pSubdevice, + KERNEL_MIG_GPU_INSTANCE **ppKernelMIGGpuInstance, + NvHandle *phParentClient, + NvHandle *phParentObject +) +{ + NV_STATUS status; + OBJSYS *pSys = SYS_GET_INSTANCE(); + + *phParentClient = pSys->hSysMemExportClient; + *phParentObject = pSys->hSysMemExportClient; + *ppKernelMIGGpuInstance = NULL; + + // Non-device parent, nothing to do.. + if (pGpu == NULL) + return NV_OK; + + if (IS_MIG_ENABLED(pGpu)) + { + MIG_INSTANCE_REF ref; + Device *pTempDevice = (pSubdevice != NULL) ? GPU_RES_GET_DEVICE(pSubdevice) : pDevice; + + status = kmigmgrGetInstanceRefFromDevice(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu), + pTempDevice, &ref); + if (status != NV_OK) + return status; + + if (!kmigmgrIsMIGReferenceValid(&ref)) + return NV_ERR_INVALID_STATE; + + status = kmigmgrIncRefCount(ref.pKernelMIGGpuInstance->pShare); + if (status != NV_OK) + return status; + + *ppKernelMIGGpuInstance = ref.pKernelMIGGpuInstance; + + if (pSubdevice != NULL) + { + *phParentClient = ref.pKernelMIGGpuInstance->instanceHandles.hClient; + *phParentObject = ref.pKernelMIGGpuInstance->instanceHandles.hSubdevice; + } + else + { + *phParentClient = ref.pKernelMIGGpuInstance->instanceHandles.hClient; + *phParentObject = ref.pKernelMIGGpuInstance->instanceHandles.hDevice; + } + } + else + { + if (pSubdevice != NULL) + { + *phParentClient = GPU_GET_MEMORY_MANAGER(pGpu)->hClient; + *phParentObject = GPU_GET_MEMORY_MANAGER(pGpu)->hSubdevice; + } + else + { + *phParentClient = GPU_GET_MEMORY_MANAGER(pGpu)->hClient; + *phParentObject = GPU_GET_MEMORY_MANAGER(pGpu)->hDevice; + } + } + + return NV_OK; +} + +NV_STATUS +memoryexportCtrlExportMem_IMPL +( + MemoryExport *pMemoryExport, + NV00E0_CTRL_EXPORT_MEM_PARAMS *pParams +) +{ + NV_STATUS status; + NvU16 result; + NvU16 i = 0, j; + MEM_EXPORT_INFO *pExportInfo = pMemoryExport->pExportInfo; + ATTACHED_PARENT_INFO *pParentInfo; + ATTACHED_MEM_INFO *pMemInfo; + OBJGPU *pGpu; + void *pGpuOsInfo; + Device *pDevice; + Subdevice *pSubdevice; + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU32 gpuMask = GPUS_LOCK_ALL; + NvBool bModuleLockAcquired = NV_FALSE; + NvBool bAllGpuLockAcquired = NV_FALSE; + + if ((pParams->numHandles == 0) || + (pParams->numHandles > NV00E0_MAX_EXPORT_HANDLES)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // + // pExportInfo->cachedParams.numMaxHandles is an immutable attribute, + // can be queried outside of the locks. + // + if ((!portSafeAddU16(pParams->index, pParams->numHandles, &result)) || + (result > pExportInfo->cachedParams.numMaxHandles)) + { + return NV_ERR_OUT_OF_RANGE; + } + + status = _memoryexportValidateParent(pParams, &pGpuOsInfo, &pGpu, &pDevice, &pSubdevice); + if (status != NV_OK) + { + return status; + } + + // + // During device-less memory dup, take module lock to protect + // pSys->hSysMemExportClient. RM-core expects client locking to + // be managed by the caller in this case, rather than relying + // on dual client locking. + // + if (pGpu == NULL) + { + portSyncRwLockAcquireWrite(pSys->pSysMemExportModuleLock); + bModuleLockAcquired = NV_TRUE; + } + + portSyncRwLockAcquireWrite(pExportInfo->pLock); + + pParentInfo = listAppendNew(&pExportInfo->parentInfoList); + if (pParentInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + pParentInfo->pGpuOsInfo = pGpuOsInfo; + pParentInfo->pGpu = pGpu; + pParentInfo->refCount = 0; + pParentInfo->hClient = 0; + pParentInfo->hParent = 0; + pParentInfo->pKernelMIGGpuInstance = NULL; + + status = rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM, + &gpuMask); + if (status != NV_OK) + { + NV_ASSERT(0); + goto fail; + } + + bAllGpuLockAcquired = NV_TRUE; + + status = _memoryexportGetParentHandles(pGpu, pDevice, pSubdevice, + &pParentInfo->pKernelMIGGpuInstance, + &pParentInfo->hClient, + &pParentInfo->hParent); + if (status != NV_OK) + goto fail; + + // Duped memory and store it in the stash + for (i = 0; i < pParams->numHandles; i++) + { + if (pParams->handles[i] == 0) + continue; + + pMemInfo = &pExportInfo->stashMemInfos[i]; + + status = _memoryexportValidateAndDupMem(RES_GET_CLIENT(pMemoryExport), + pParams->handles[i], + pParentInfo, pMemInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to duping 0x%x\n", status); + goto fail; + } + } + + // Start committing now. + + // !!! Don't expect any failures from this point onward !!! + + for (i = 0; i < pParams->numHandles; i++) + { + pMemInfo = &pExportInfo->memInfos[i + pParams->index]; + + // If the handle already exists in this position, detach it + if (pMemInfo->hDupedMem != 0) + { + _memoryexportDetachMemAndParent(pExportInfo, pMemInfo); + + NV_ASSERT(pMemInfo->hDupedMem == 0); + } + + // Nothing to attach, continue.. + if (pExportInfo->stashMemInfos[i].hDupedMem == 0) + continue; + + // Attach successful + *pMemInfo = pExportInfo->stashMemInfos[i]; + + // Ref-count parent and cache for future use. + pParentInfo->refCount++; + pMemInfo->pParentInfo = pParentInfo; + + pExportInfo->cachedParams.numCurHandles++; + + // Clear stash + pExportInfo->stashMemInfos[i].hDupedMem = 0; + } + + // Attach GPU if applicable... + if (pGpu != NULL) + { + NvU32 deviceInstance = gpuGetDeviceInstance(pGpu); + + pExportInfo->attachedUsageCount[deviceInstance].gpu++; + pExportInfo->cachedParams.deviceInstanceMask |= NVBIT(deviceInstance); + + if (pParentInfo->pKernelMIGGpuInstance != NULL) + { + NvU32 swizzId = pParentInfo->pKernelMIGGpuInstance->swizzId; + + pExportInfo->attachedUsageCount[deviceInstance].migGi[swizzId]++; + pExportInfo->cachedParams.giIdMasks[deviceInstance] |= NVBIT(swizzId); + } + } + + // + // If this was mem detach only call, detach the new parent info which is + // unused. + // + if (pParentInfo->refCount == 0) + _memoryexportDetachParent(pExportInfo, pParentInfo); + + goto done; + +fail: + for (j = 0; j < i; j++) + { + pMemInfo = &pExportInfo->stashMemInfos[j]; + if (pMemInfo->hDupedMem != 0) + _memoryexportUndupMem(pParentInfo, pMemInfo); + } + + if (pParentInfo->pKernelMIGGpuInstance != NULL) + NV_ASSERT_OK(kmigmgrDecRefCount(pParentInfo->pKernelMIGGpuInstance->pShare)); + + listRemove(&pExportInfo->parentInfoList, pParentInfo); + +done: + if (bAllGpuLockAcquired) + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + + portSyncRwLockReleaseWrite(pExportInfo->pLock); + + if (bModuleLockAcquired) + portSyncRwLockReleaseWrite(pSys->pSysMemExportModuleLock); + + return status; +} + +static NV_STATUS +_memoryexportFindImporterMIGParent +( + RsClient *pImpClient, + ATTACHED_PARENT_INFO *pSrcParentInfo, + NvHandle *pImpParentHandle +) +{ + NV_STATUS status; + OBJGPU *pSrcGpu; + KERNEL_MIG_GPU_INSTANCE *pSrcKernelMIGGpuInstance; + NvBool bDevice; + RS_ITERATOR it; + + pSrcGpu = pSrcParentInfo->pGpu; + NV_ASSERT_OR_RETURN(pSrcGpu != NULL, NV_ERR_INVALID_STATE); + + pSrcKernelMIGGpuInstance = pSrcParentInfo->pKernelMIGGpuInstance; + NV_ASSERT_OR_RETURN(pSrcKernelMIGGpuInstance != NULL, NV_ERR_INVALID_STATE); + + *pImpParentHandle = 0; + + bDevice = (pSrcKernelMIGGpuInstance->instanceHandles.hDevice == pSrcParentInfo->hParent); + + // In MIG, multiple devices of same the device instance are feasible. + it = clientRefIter(pImpClient, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); + + while (clientRefIterNext(pImpClient, &it)) + { + Device *pImpDevice = dynamicCast(it.pResourceRef->pResource, Device); + Subdevice *pImpSubdevice; + MIG_INSTANCE_REF impRef; + + if (pImpDevice == NULL) + continue; + + status = kmigmgrGetInstanceRefFromDevice(pSrcGpu, GPU_GET_KERNEL_MIG_MANAGER(pSrcGpu), + pImpDevice, &impRef); + if (status != NV_OK) + continue; + + if (pSrcKernelMIGGpuInstance != impRef.pKernelMIGGpuInstance) + continue; + + if (bDevice) + { + *pImpParentHandle = RES_GET_HANDLE(pImpDevice); + } + else + { + status = subdeviceGetByDeviceAndGpu(pImpClient, pImpDevice, pSrcGpu, &pImpSubdevice); + if (status != NV_OK) + continue; + + *pImpParentHandle = RES_GET_HANDLE(pImpSubdevice); + } + + break; + } + + return (*pImpParentHandle == 0) ? NV_ERR_OBJECT_NOT_FOUND : NV_OK; +} + +static NV_STATUS +_memoryexportFindImporterParent +( + RsClient *pImpClient, + ATTACHED_PARENT_INFO *pSrcParentInfo, + NvHandle *pImpParentHandle +) +{ + NV_STATUS status; + OBJGPU *pSrcGpu = pSrcParentInfo->pGpu; + NvBool bDevice; + Device *pImpDevice; + Subdevice *pImpSubdevice; + + // If device-less memory, use client as importer parent + if (pSrcGpu == NULL) + { + *pImpParentHandle = pImpClient->hClient; + return NV_OK; + } + + if (IS_MIG_ENABLED(pSrcGpu)) + { + return _memoryexportFindImporterMIGParent(pImpClient, pSrcParentInfo, + pImpParentHandle); + } + + // If source is device, then return device as parent + bDevice = (GPU_GET_MEMORY_MANAGER(pSrcGpu)->hDevice == pSrcParentInfo->hParent); + + status = deviceGetByGpu(pImpClient, pSrcGpu, NV_TRUE, &pImpDevice); + if (status != NV_OK) + return status; + + if (bDevice) + { + *pImpParentHandle = RES_GET_HANDLE(pImpDevice); + return NV_OK; + } + + status = subdeviceGetByDeviceAndGpu(pImpClient, pImpDevice, pSrcGpu, &pImpSubdevice); + if (status != NV_OK) + return status; + + *pImpParentHandle = RES_GET_HANDLE(pImpSubdevice); + + return NV_OK; +} + +NV_STATUS +memoryexportCtrlImportMem_IMPL +( + MemoryExport *pMemoryExport, + NV00E0_CTRL_IMPORT_MEM_PARAMS *pParams +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + NV_STATUS status; + NvU16 result; + NvU16 i = 0, j; + MEM_EXPORT_INFO *pExportInfo = pMemoryExport->pExportInfo; + ATTACHED_MEM_INFO *pMemInfo; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + NvHandle hDstParent; + NvHandle hDstClient = RES_GET_CLIENT(pMemoryExport)->hClient; + NvU32 gpuMask = GPUS_LOCK_ALL; + NvBool bAllGpuLockAcquired = NV_FALSE; + + if ((pParams->numHandles == 0) || + (pParams->numHandles > NV00E0_MAX_IMPORT_HANDLES)) + return NV_ERR_INVALID_ARGUMENT; + + // + // pExportInfo->cachedParams.numMaxHandles is an immutable attribute, + // can be queried outside of the locks. + // + if ((!portSafeAddU16(pParams->index, pParams->numHandles, &result)) || + (result > pExportInfo->cachedParams.numMaxHandles)) + return NV_ERR_OUT_OF_RANGE; + + // + // During import we might read (dup) the hSysMemExportClient's client + // database to dup from it. So, during device-less memory dup, take module + // lock to protect pSys->hSysMemExportClient. RM-core expects client + // locking to be managed by the caller in this case, rather than relying + // on dual client locking (as there could be a lock inversion issue to + // lock another client, if one client is already locked). + // + portSyncRwLockAcquireRead(pSys->pSysMemExportModuleLock); + + portSyncRwLockAcquireWrite(pExportInfo->pLock); + + status = rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM, + &gpuMask); + if (status != NV_OK) + { + NV_ASSERT(0); + goto done; + } + + bAllGpuLockAcquired = NV_TRUE; + + for (i = 0; i < pParams->numHandles; i++) + { + pMemInfo = &pExportInfo->memInfos[i + pParams->index]; + + // Nothing to import + if (pMemInfo->hDupedMem == 0) + { + portMemSet(&pParams->memInfos[i], 0, sizeof(pParams->memInfos[0])); + continue; + } + + if (pParams->handles[i] == 0) + { + NV_PRINTF(LEVEL_ERROR, "Invalid handle\n"); + status = NV_ERR_INVALID_OBJECT_HANDLE; + goto fail; + } + + status = _memoryexportFindImporterParent(RES_GET_CLIENT(pMemoryExport), + pMemInfo->pParentInfo, + &hDstParent); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to find parent: 0x%x\n", status); + goto fail; + } + + status = pRmApi->DupObject(pRmApi, + hDstClient, + hDstParent, + &pParams->handles[i], + pMemInfo->pParentInfo->hClient, + pMemInfo->hDupedMem, 0); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to duping 0x%x\n", status); + goto fail; + } + + pParams->memInfos[i].addrSpace = pMemInfo->addressSpace; + pParams->memInfos[i].hParent = hDstParent; + } + + goto done; + +fail: + for (j = 0; j < i; j++) + { + if (pParams->memInfos[j].hParent != 0) + pRmApi->Free(pRmApi, hDstClient, pParams->handles[j]); + } + +done: + if (bAllGpuLockAcquired) + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + + portSyncRwLockReleaseWrite(pExportInfo->pLock); + + portSyncRwLockReleaseRead(pSys->pSysMemExportModuleLock); + + return status; +} + +NV_STATUS +memoryexportCtrlGetInfo_IMPL +( + MemoryExport *pMemoryExport, + NV00E0_CTRL_GET_INFO_PARAMS *pParams +) +{ + MEM_EXPORT_INFO *pExportInfo = pMemoryExport->pExportInfo; + + portSyncRwLockAcquireRead(pExportInfo->pLock); + + pParams->info = pMemoryExport->pExportInfo->cachedParams; + + portSyncRwLockReleaseRead(pExportInfo->pLock); + + return NV_OK; +} + +NV_STATUS +memoryexportControl_IMPL +( + MemoryExport *pMemoryExport, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + // + // Note: GPU lock(s) is required for some control calls. Thus, it is + // incorrect to take the leaf lock here. resControl_IMPL() attempts to + // acquire the GPU locks before it calls the control call body. + // + return resControl_IMPL(staticCast(pMemoryExport, RsResource), + pCallContext, pParams); +} + +void +memoryexportClearCache +( + NvU16 nodeId +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + SYS_MEM_EXPORT_CACHESubmap *pSubmap; + + portSyncRwLockAcquireWrite(pSys->pSysMemExportModuleLock); + + pSubmap = multimapFindSubmap(&pSys->sysMemExportCache, nodeId); + + if (pSubmap != NULL) + { + SYS_MEM_EXPORT_CACHEIter it = + multimapSubmapIterItems(&pSys->sysMemExportCache, pSubmap); + + while (multimapItemIterNext(&it) != 0) + multimapRemoveItem(&pSys->sysMemExportCache, it.pValue); + + multimapRemoveSubmap(&pSys->sysMemExportCache, pSubmap); + } + + portSyncRwLockReleaseWrite(pSys->pSysMemExportModuleLock); +} diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c index f2844a37ff..2d1154a600 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric.c @@ -39,9 +39,7 @@ #include "mem_mgr/vaspace.h" #include "gpu/mem_mgr/mem_mgr.h" #include "gpu/mem_mgr/mem_utils.h" -#include "gpu/mem_mgr/heap.h" #include "gpu/device/device.h" -#include "gpu/subdevice/subdevice.h" #include "os/os.h" #include "compute/fabric.h" #include "gpu/mem_mgr/mem_desc.h" @@ -83,52 +81,31 @@ _memoryfabricMemDescGetNumAddr static NV_STATUS _memoryfabricValidatePhysMem ( - NvHandle hClient, + RsClient *pRsClient, NvHandle hPhysMem, OBJGPU *pOwnerGpu, MEMORY_DESCRIPTOR **ppPhysMemDesc ) { MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pOwnerGpu); - RsResourceRef *pPhysmemRef; MEMORY_DESCRIPTOR *pPhysMemDesc; NvU64 physPageSize; NV_STATUS status; Memory *pMemory; - if (hPhysMem == 0) - { - NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle\n"); - - return NV_ERR_INVALID_ARGUMENT; - } - - status = serverutilGetResourceRef(hClient, hPhysMem, &pPhysmemRef); + status = memGetByHandle(pRsClient, hPhysMem, &pMemory); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "Failed to get resource in resserv for physmem handle\n"); - + NV_PRINTF(LEVEL_ERROR, "Invalid object handle passed\n"); return status; } - pMemory = dynamicCast(pPhysmemRef->pResource, Memory); - if (pMemory == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); - return NV_ERR_INVALID_OBJECT_HANDLE; - } - pPhysMemDesc = pMemory->pMemDesc; - if (pPhysMemDesc == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); - return NV_ERR_INVALID_OBJECT_HANDLE; - } if ((pOwnerGpu != pPhysMemDesc->pGpu) || - !memmgrIsApertureSupportedByFla_HAL(pOwnerGpu, pMemoryManager, - memdescGetAddressSpace(pPhysMemDesc))) + !memmgrIsMemDescSupportedByFla_HAL(pOwnerGpu, + pMemoryManager, + pPhysMemDesc)) { NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle passed\n"); @@ -245,7 +222,7 @@ _memoryFabricAttachMem return NV_ERR_NOT_SUPPORTED; } - status = _memoryfabricValidatePhysMem(RES_GET_CLIENT_HANDLE(pMemory), + status = _memoryfabricValidatePhysMem(RES_GET_CLIENT(pMemory), pAttachInfo->hMemory, pGpu, &pPhysMemDesc); @@ -632,7 +609,7 @@ memoryfabricConstruct_IMPL } else if (!bFlexible) { - status = _memoryfabricValidatePhysMem(pCallContext->pClient->hClient, + status = _memoryfabricValidatePhysMem(pCallContext->pClient, hPhysMem, pGpu, &pPhysMemDesc); if (status != NV_OK) return status; @@ -762,7 +739,7 @@ memoryfabricConstruct_IMPL NV0041_CTRL_GET_SURFACE_INFO_PARAMS surfaceInfoParam = {0}; surfaceInfo[0].index = NV0041_CTRL_SURFACE_INFO_INDEX_ADDR_SPACE_TYPE; - surfaceInfo[1].index = NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE; + surfaceInfo[1].index = NV0041_CTRL_SURFACE_INFO_INDEX_ATTRS; surfaceInfoParam.surfaceInfoListSize = 2; surfaceInfoParam.surfaceInfoList = NvP64_VALUE(&surfaceInfo); @@ -779,7 +756,14 @@ memoryfabricConstruct_IMPL } pMemdescData->physAttrs.addressSpace = surfaceInfo[0].data; - pMemdescData->physAttrs.compressionCoverage = surfaceInfo[1].data; + // + // TODO: Bug 4322867: use NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR + // instead of NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE. + // NV0041_CTRL_SURFACE_INFO_INDEX_COMPR_COVERAGE is buggy and + // will be removed soon. + // + pMemdescData->physAttrs.compressionCoverage = + (surfaceInfo[1].data & NV0041_CTRL_SURFACE_INFO_ATTRS_COMPR) ? 0x1 : 0x0; mapFlags |= bReadOnly ? FABRIC_VASPACE_MAP_FLAGS_READ_ONLY : 0; @@ -953,6 +937,7 @@ memoryfabricCtrlCmdDescribe_IMPL OBJGPU *pGpu; if ( + !rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_FABRIC_IMEX_MGMT) && !rmclientIsAdminByHandle(hClient, pCallContext->secInfo.privLevel)) { return NV_ERR_INSUFFICIENT_PERMISSIONS; diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c new file mode 100644 index 0000000000..4b072d4e5f --- /dev/null +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_ref.c @@ -0,0 +1,272 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions managing the ref-counted imported + * fabric memory + * + *****************************************************************************/ + +#define NVOC_MEM_FABRIC_IMPORT_REF_H_PRIVATE_ACCESS_ALLOWED + +#include "core/core.h" +#include "os/os.h" +#include "rmapi/client.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "mem_mgr/mem_fabric_import_ref.h" +#include "mem_mgr/mem_fabric_import_v2.h" +#include "gpu/mem_mgr/virt_mem_allocator_common.h" + +#include "class/cl00fb.h" + +NV_STATUS +memoryfabricimportedrefConstruct_IMPL +( + MemoryFabricImportedRef *pMemoryFabricImportedRef, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + NV00FB_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; + NvHandle hClient = pParams->hClient; + + NV_ASSERT_OR_RETURN(RMCFG_FEATURE_KERNEL_RM, NV_ERR_NOT_SUPPORTED); + + if (!rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_FABRIC_IMEX_MGMT) && + !rmclientIsCapableByHandle(hClient, NV_RM_CAP_EXT_FABRIC_MGMT)) + return NV_ERR_INSUFFICIENT_PERMISSIONS; + + if (pAllocParams->flags != 0) + return NV_ERR_INVALID_ARGUMENT; + + pMemoryFabricImportedRef->pFabricImportDesc = + importDescriptorGetUnused((const NvUuid*) pAllocParams->exportUuid, + pAllocParams->index, pAllocParams->id); + if (pMemoryFabricImportedRef->pFabricImportDesc == NULL) + return NV_WARN_NOTHING_TO_DO; + + return NV_OK; +} + +void +memoryfabricimportedrefDestruct_IMPL +( + MemoryFabricImportedRef *pMemoryFabricImportedRef +) +{ + memdescDestroy(pMemoryFabricImportedRef->pTempMemDesc); + + importDescriptorPutNonBlocking(pMemoryFabricImportedRef->pFabricImportDesc); +} + +NvBool +memoryfabricimportedrefCanCopy_IMPL +( + MemoryFabricImportedRef *pMemoryFabricImportedRef +) +{ + return NV_FALSE; +} + +static void +_memoryfabricImportMemDescDestroyCallback +( + OBJGPU *pUnused, + void *pObject, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + FABRIC_IMPORT_MEMDESC_DATA *pMemdescData = + (FABRIC_IMPORT_MEMDESC_DATA *)memdescGetMemData(pMemDesc); + + if (pMemdescData != NULL) + { + portMemFree(pMemDesc->_pMemData); + pMemDesc->_pMemData = NULL; + } + + portMemFree(pObject); +} + +MEMORY_DESCRIPTOR* +_createTempMemDesc +( + NV_FABRIC_MEMORY_ATTRS *pAttrs, + NV_PHYSICAL_MEMORY_ATTRS *pPhysAttrs, + NvU32 memFlags, + NvBool bConting +) +{ + MEMORY_DESCRIPTOR *pMemDesc; + FABRIC_IMPORT_MEMDESC_DATA *pMemdescData = NULL; + MEM_DESC_DESTROY_CALLBACK *pCallback = NULL; + NV_STATUS status; + + status = memdescCreate(&pMemDesc, NULL, pAttrs->size, 0, + bConting, ADDR_FABRIC_V2, + NV_MEMORY_UNCACHED, MEMDESC_FLAGS_NONE); + if (status != NV_OK) + return NULL; + + memdescSetPageSize(pMemDesc, AT_GPU, pAttrs->pageSize); + + pMemDesc->_pteKind = pAttrs->kind; + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SET_KIND, NV_TRUE); + + // Allocate memory for memory fabric memdesc private data. + pMemdescData = portMemAllocNonPaged(sizeof(FABRIC_IMPORT_MEMDESC_DATA)); + if (pMemdescData == NULL) + goto freeMemDesc; + + portMemSet(pMemdescData, 0, sizeof(FABRIC_IMPORT_MEMDESC_DATA)); + + pMemdescData->physAttrs = *pPhysAttrs; + pMemdescData->memFlags = memFlags; + pMemdescData->cliqueId = pAttrs->cliqueId; + + // Associate the memdesc data release callback function. + memdescSetMemData(pMemDesc, (void *)pMemdescData, NULL); + + // Allocate memory for the memory descriptor destroy callback. + pCallback = portMemAllocNonPaged(sizeof(MEM_DESC_DESTROY_CALLBACK)); + if (pCallback == NULL) + goto freeMemdescMemData; + + portMemSet(pCallback, 0, sizeof(MEM_DESC_DESTROY_CALLBACK)); + + // Associate the memdescDestroy callback function. + pCallback->pObject = (void *)pCallback; + pCallback->destroyCallback = + (MemDescDestroyCallBack*) &_memoryfabricImportMemDescDestroyCallback; + + memdescAddDestroyCallback(pMemDesc, pCallback); + + return pMemDesc; + +freeMemdescMemData: + portMemFree(pMemdescData); + +freeMemDesc: + memdescDestroy(pMemDesc); + + return NULL; +} + +NV_STATUS +memoryfabricimportedrefCtrlValidate_IMPL +( + MemoryFabricImportedRef *pMemoryFabricImportedRef, + NV00FB_CTRL_VALIDATE_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + NvU64 i; + NvU64 *pPfnArray = NULL; + MEMORY_DESCRIPTOR *pTempMemDesc = pMemoryFabricImportedRef->pTempMemDesc; + NvU64 result; + + pParams->bDone = NV_FALSE; + + if (pParams->flags & NV00FB_CTRL_FLAGS_IMPORT_FAILED) + { + pTempMemDesc = NULL; + goto install; + } + + if ((pParams->totalPfns == 0) || + (pMemoryFabricImportedRef->numUpdatedPfns >= pParams->totalPfns)) + return NV_ERR_INVALID_ARGUMENT; + + if (!portSafeAddU64(pParams->offset, pParams->numPfns, &result) || + (result > pParams->totalPfns)) + return NV_ERR_OUT_OF_RANGE; + + if ((pParams->attrs.pageSize != RM_PAGE_SIZE_HUGE) && + (pParams->attrs.pageSize != RM_PAGE_SIZE_512M)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if ((pParams->attrs.size == 0) || + !NV_IS_ALIGNED64(pParams->attrs.size, pParams->attrs.pageSize)) + return NV_ERR_INVALID_ARGUMENT; + + pPfnArray = portMemAllocNonPaged(sizeof(NvU64) * pParams->numPfns); + if (pPfnArray == NULL) + return NV_ERR_NO_MEMORY; + + for (i = 0; i < pParams->numPfns; i++) + pPfnArray[i] = ((NvU64)pParams->pfnArray[i]) << RM_PAGE_SHIFT_HUGE; + + if (pTempMemDesc == NULL) + { + pTempMemDesc = _createTempMemDesc(&pParams->attrs, + &pParams->physAttrs, + pParams->memFlags, + (pParams->totalPfns == 1)); + if (pTempMemDesc == NULL) + { + status = NV_ERR_NO_MEMORY; + goto out; + } + + pMemoryFabricImportedRef->pTempMemDesc = pTempMemDesc; + } + + if (pParams->totalPfns == 1) + { + memdescSetPte(pTempMemDesc, AT_GPU, 0, pPfnArray[0]); + } + else + { + memdescFillPages(pTempMemDesc, pParams->offset, pPfnArray, + pParams->numPfns, pParams->attrs.pageSize); + } + + pMemoryFabricImportedRef->numUpdatedPfns += pParams->numPfns; + + pParams->bDone = (pMemoryFabricImportedRef->numUpdatedPfns == \ + pParams->totalPfns); + + if (!pParams->bDone) + goto out; + +install: + status = importDescriptorInstallMemDesc( + pMemoryFabricImportedRef->pFabricImportDesc, pTempMemDesc); + + // + // Reset pTempMemDesc so that memoryfabricimportedrefDestruct_IMPL won't + // destroy it. The ref-counting would be properly handled when + // importDescriptorPutNonBlocking is called. + // + if ((status == NV_OK) && (pTempMemDesc != NULL)) + pMemoryFabricImportedRef->pTempMemDesc = NULL; + +out: + portMemFree(pPfnArray); + + return status; +} diff --git a/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_v2.c b/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_v2.c new file mode 100644 index 0000000000..17b7da7d4e --- /dev/null +++ b/src/nvidia/src/kernel/mem_mgr/mem_fabric_import_v2.c @@ -0,0 +1,903 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/****************************************************************************** + * + * Description: + * This file contains the functions managing the memory fabric import + * + *****************************************************************************/ + +#define NVOC_MEM_FABRIC_IMPORT_V2_H_PRIVATE_ACCESS_ALLOWED + +/* + * Lock ordering + * + * RMAPI Lock + * |_Client Lock + * |_GPU(s) Lock (Should not be needed for this device-less class) + * |_Fabric Import Module Lock + * |_Fabric Import Descriptor Lock + */ + +#include "core/core.h" +#include "core/system.h" +#include "compute/fabric.h" +#include "rmapi/resource.h" +#include "mem_mgr/mem_fabric_import_v2.h" +#include "mem_mgr/mem_export.h" +#include "gpu/mem_mgr/mem_desc.h" +#include "gpu_mgr/gpu_mgr.h" +#include "gpu/bus/kern_bus.h" +#include "gpu/nvlink/kernel_nvlink.h" +#include "kernel/gpu/gpu_fabric_probe.h" + +#include "class/cl00f9.h" + +typedef struct mem_fabric_importer_info +{ + void *pOsEvent; + Memory *pMemory; +} MEM_FABRIC_IMPORTER_INFO; + +MAKE_LIST(MemFabricImporterInfoList, MEM_FABRIC_IMPORTER_INFO); + +typedef struct mem_fabric_import_descriptor +{ + // Ref-count to keep this descriptor alive + NvU64 refCount; + + // The list of importers waiting on this object to get ready. + MemFabricImporterInfoList waitingImportersList; + + // + // Incremented by importDescriptorGetUnused() and decremented by + // importDescriptorPutNonBlocking(). + // + NvU64 extUsageCount; + + // Unique import event ID + NvU64 importEventId; + + // Export object information associated with this import descriptor. + NvU16 exportNodeId; + NvU16 index; + NvU64 id; + NvU64 key; + + // Same as packet.uuid, but uses NvUuid type. + NvUuid uuid; + + // Set when pMemDesc is installed. + NvBool bMemdescInstalled; + + // A memdesc that is ready to use, where NULL is a valid value. + MEMORY_DESCRIPTOR *pMemDesc; + + // Set when unimported. + NvBool bUnimported; + + // + // The lock protects MEM_FABRIC_IMPORT_DESCRIPTOR. + // + // The lock should be taken only if the descriptor is safe to access i.e., + // holding the module lock or the accessing thread has the descriptor + // refcounted. + // + PORT_RWLOCK *pLock; +} MEM_FABRIC_IMPORT_DESCRIPTOR; + +// +// Must be called with the pFabricImportModuleLock RW taken. +// The call returns with pFabricImportDesc->pLock RW acquired if found. +// +static MEM_FABRIC_IMPORT_DESCRIPTOR* +_importDescriptorGetAndLockAcquireWrite +( + const NvUuid *pExportUuid, + NvU16 index, + NvU64 id, + NvU64 *pKey +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc = NULL; + NvU64 key = (id << NV00F9_IMPORT_ID_SHIFT) | index; + + if (pKey != NULL) + *pKey = key; + + pFabricImportDesc = fabricImportCacheGet(pFabric, pExportUuid, key); + if (pFabricImportDesc == NULL) + return NULL; + + portSyncRwLockAcquireWrite(pFabricImportDesc->pLock); + + pFabricImportDesc->refCount++; + + return pFabricImportDesc; +} + +static void +_initImportFabricEvent +( + NvU16 exportNodeId, + NvUuid *pExportUuid, + NvU16 index, + NvU64 id, + NV00F1_CTRL_FABRIC_EVENT *pEvent +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + + pEvent->imexChannel = 0; + pEvent->type = NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_IMPORT; + pEvent->id = fabricGenerateEventId_IMPL(pFabric); + pEvent->data.import.exportNodeId = exportNodeId; + pEvent->data.import.index = index; + pEvent->data.import.id = id; + portMemCopy(pEvent->data.import.exportUuid, NV_MEM_EXPORT_UUID_LEN, + pExportUuid->uuid, NV_MEM_EXPORT_UUID_LEN); +} + +static void +_initUnimportFabricEvent +( + NvU64 importEventId, + NvU16 exportNodeId, + NV00F1_CTRL_FABRIC_EVENT *pEvent +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + + pEvent->imexChannel = 0; + pEvent->type = NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_UNIMPORT; + pEvent->id = fabricGenerateEventId_IMPL(pFabric); + pEvent->data.unimport.exportNodeId = exportNodeId; + pEvent->data.unimport.importEventId = importEventId; +} + +static void +_importDescriptorCleanup +( + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc +) +{ + if (pFabricImportDesc == NULL) + return; + + if (pFabricImportDesc->pLock != NULL) + portSyncRwLockDestroy(pFabricImportDesc->pLock); + + listDestroy(&pFabricImportDesc->waitingImportersList); + + memdescDestroy(pFabricImportDesc->pMemDesc); + pFabricImportDesc->pMemDesc = NULL; + + portMemFree(pFabricImportDesc); +} + +// +// Must be called with the pFabricImportModuleLock RO or RW taken. +// +// pFabricImportModuleLock is needed to synchronize with +// _importDescriptorGetAndLockAcquireWrite(). We don't want to delete +// pFabricImportDesc under while it is being refcounted for the first +// time. +// +// The call returns with pFabricImportDesc->pLock released if found. +// +static void +_importDescriptorPutAndLockReleaseWrite +( + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc, + NvBool bUnimportEvent +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV00F1_CTRL_FABRIC_EVENT unimportEvent; + + if (pFabricImportDesc == NULL) + return; + + pFabricImportDesc->refCount--; + + // Cleanup when all the non-FM references are gone (unimport). + if (!pFabricImportDesc->bUnimported && + (pFabricImportDesc->refCount == pFabricImportDesc->extUsageCount)) + { + // + // Generate unimport event in the following cases: + // + // 1. Import sequence was successful. + // 2. Import sequence is in progress. This is because, FM must have + // ref-counted the fabric memory object already. After import + // sequence is successful, an unimport event is needed for FM to + // drop ref-count on the fabric memory object. However, there is a + // possibility that import sequence could fail in between, and FM + // drops ref-count on the fabric memory object already. In such a + // case, FM should still complete unimport sequence to unblock the + // waiting process. + // + // Do not generate unimport event in the following cases: + // + // 1. Import was unsuccessful and FM has notified RM about it. This is + // because FM must have dropped ref-count on the fabric memory object + // already when import failed. + // + if (bUnimportEvent && + !(pFabricImportDesc->bMemdescInstalled && + pFabricImportDesc->pMemDesc == NULL)) + { + _initUnimportFabricEvent(pFabricImportDesc->importEventId, + pFabricImportDesc->exportNodeId, + &unimportEvent); + NV_CHECK(LEVEL_WARNING, + fabricPostEventsV2(pFabric, &unimportEvent, 1) == NV_OK); + } + + fabricImportCacheDelete(pFabric, &pFabricImportDesc->uuid, + pFabricImportDesc->key); + + pFabricImportDesc->bUnimported = NV_TRUE; + } + + if (pFabricImportDesc->refCount != 0) + { + portSyncRwLockReleaseWrite(pFabricImportDesc->pLock); + return; + } + + // At this point no one is using pFabricImportDesc, drop the locks... + portSyncRwLockReleaseWrite(pFabricImportDesc->pLock); + + NV_ASSERT(listCount(&pFabricImportDesc->waitingImportersList) == 0); + NV_ASSERT(pFabricImportDesc->extUsageCount == 0); + _importDescriptorCleanup(pFabricImportDesc); +} + +MEM_FABRIC_IMPORT_DESCRIPTOR* +importDescriptorGetUnused +( + const NvUuid *pExportUuid, + NvU16 index, + NvU64 id +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc = NULL; + + portSyncRwLockAcquireWrite(pFabric->pFabricImportModuleLock); + + pFabricImportDesc = _importDescriptorGetAndLockAcquireWrite(pExportUuid, + index, id, NULL); + if (pFabricImportDesc == NULL) + goto done; + + // + // bMemdescInstalled is also checked because the installed pMemDesc + // could be in use by RM clients. + // + if (pFabricImportDesc->bMemdescInstalled || + (pFabricImportDesc->extUsageCount > 0)) + { + _importDescriptorPutAndLockReleaseWrite(pFabricImportDesc, NV_FALSE); + pFabricImportDesc = NULL; + goto done; + } + + pFabricImportDesc->extUsageCount++; + NV_ASSERT(pFabricImportDesc->extUsageCount == 1); + + portSyncRwLockReleaseWrite(pFabricImportDesc->pLock); + +done: + portSyncRwLockReleaseWrite(pFabric->pFabricImportModuleLock); + + return pFabricImportDesc; +} + +void +importDescriptorPutNonBlocking +( + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + + portSyncRwLockAcquireRead(pFabric->pFabricImportModuleLock); + + portSyncRwLockAcquireWrite(pFabricImportDesc->pLock); + + NV_ASSERT(pFabricImportDesc->extUsageCount > 0); + + pFabricImportDesc->extUsageCount--; + + _importDescriptorPutAndLockReleaseWrite(pFabricImportDesc, NV_FALSE); + + portSyncRwLockReleaseRead(pFabric->pFabricImportModuleLock); +} + +static void +_importDescriptorFlushImporters +( + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc +) +{ + MEM_FABRIC_IMPORTER_INFO *pNode; + + if (!pFabricImportDesc->bMemdescInstalled) + return; + + while ((pNode = listHead(&pFabricImportDesc->waitingImportersList)) != NULL) + { + if (pFabricImportDesc->pMemDesc != NULL) + { + // + // This function only initializes pNode->pMemory so it + // should never fail. + // + NV_ASSERT_OK(memConstructCommon(pNode->pMemory, + NV_MEMORY_FABRIC_IMPORT_V2, + 0, pFabricImportDesc->pMemDesc, + 0, NULL, 0, 0, 0, 0, + NVOS32_MEM_TAG_NONE, NULL)); + } + + if (pNode->pOsEvent != NULL) + { + osSetEvent(NULL, pNode->pOsEvent); + NV_ASSERT_OK(osDereferenceObjectCount(pNode->pOsEvent)); + } + + listRemove(&pFabricImportDesc->waitingImportersList, pNode); + } + + return; +} + +NV_STATUS +importDescriptorInstallMemDesc +( + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc, + MEMORY_DESCRIPTOR *pMemDesc +) +{ + NV_STATUS status; + + if (pFabricImportDesc == NULL) + return NV_ERR_INVALID_ARGUMENT; + + portSyncRwLockAcquireWrite(pFabricImportDesc->pLock); + + if (pFabricImportDesc->bMemdescInstalled) + { + status = NV_ERR_IN_USE; + goto done; + } + + pFabricImportDesc->pMemDesc = pMemDesc; + pFabricImportDesc->bMemdescInstalled = NV_TRUE; + + _importDescriptorFlushImporters(pFabricImportDesc); + + status = NV_OK; + +done: + portSyncRwLockReleaseWrite(pFabricImportDesc->pLock); + + return status; +} + +static void +_importDescriptorDequeueWait +( + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc, + Memory *pMemory +) +{ + MEM_FABRIC_IMPORTER_INFO *pNode; + + for (pNode = listHead(&pFabricImportDesc->waitingImportersList); + pNode != NULL; + pNode = listNext(&pFabricImportDesc->waitingImportersList, pNode)) + { + if (pNode->pMemory == pMemory) + { + if (pNode->pOsEvent != NULL) + NV_ASSERT_OK(osDereferenceObjectCount(pNode->pOsEvent)); + + listRemove(&pFabricImportDesc->waitingImportersList, pNode); + + break; + } + } +} + +static NV_STATUS +_importDescriptorEnqueueWait +( + NvHandle hClient, + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc, + NvP64 pOsEvent, + Memory *pMemory +) +{ + MEM_FABRIC_IMPORTER_INFO *pNode; + NV_STATUS status; + NvP64 pValidatedOsEvent = NULL; + + if (pOsEvent != NULL) + { + status = osUserHandleToKernelPtr(hClient, pOsEvent, &pValidatedOsEvent); + if (status != NV_OK) + { + goto fail; + } + } + + pNode = listAppendNew(&pFabricImportDesc->waitingImportersList); + if (pNode == NULL) + { + osDereferenceObjectCount(pValidatedOsEvent); + status = NV_ERR_NO_MEMORY; + goto fail; + } + + pNode->pOsEvent = pValidatedOsEvent; + pNode->pMemory = pMemory; + + // In case the memdesc is ready, get unblocked + _importDescriptorFlushImporters(pFabricImportDesc); + + return NV_OK; + +fail: + _importDescriptorDequeueWait(pFabricImportDesc, pMemory); + + return status; +} + +// +// Returns with pFabricImportModuleLock and pFabricImportDesc->pLock taken in +// RW mode. The caller must drop the locks. +// +static MEM_FABRIC_IMPORT_DESCRIPTOR* +_importDescriptorAlloc +( + NvU8 *pUuid, + NvU16 exportNodeId, + NvU16 index, + NvU64 id +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV_STATUS status; + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc; + NvUuid uuid; + NvU64 key; + + ct_assert(NV_MEM_EXPORT_UUID_LEN == NV_UUID_LEN); + portMemCopy(uuid.uuid, NV_UUID_LEN,pUuid, NV_MEM_EXPORT_UUID_LEN); + + // + // Take pFabricImportModuleLock to synchronize multiple constructors + // to share the cached pFabricImportDesc. Without this lock, two or + // more constructors may see the import cache empty at the same time. + // + // We want the following sequence happen atomically: + // + // pFabricImportDesc = _importDescriptorGetAndLockAcquireWrite(..); + // if (pFabricImportDesc == NULL) + // { + // pFabricImportDesc = alloc(); + // fabricImportCacheInsert(pFabricImportDesc); + // ... + // } + // + // Also, it is important to synchronize the constructor with the destructor. + // _importDescriptorGetAndLockAcquireWrite() looks up and refcounts + // pFabricImportDesc non-atomically. Thus, pFabricImportDesc may be + // destroyed before it could be refcounted. + // + portSyncRwLockAcquireWrite(pFabric->pFabricImportModuleLock); + + // Nothing to do... + pFabricImportDesc = _importDescriptorGetAndLockAcquireWrite(&uuid, index, + id, &key); + if (pFabricImportDesc != NULL) + return pFabricImportDesc; + + pFabricImportDesc = + portMemAllocNonPaged(sizeof(MEM_FABRIC_IMPORT_DESCRIPTOR)); + if (pFabricImportDesc == NULL) + goto fail; + + portMemSet(pFabricImportDesc, 0, sizeof(MEM_FABRIC_IMPORT_DESCRIPTOR)); + + pFabricImportDesc->refCount = 1; + + pFabricImportDesc->index = index; + pFabricImportDesc->exportNodeId = exportNodeId; + pFabricImportDesc->uuid = uuid; + pFabricImportDesc->id = id; + pFabricImportDesc->key = key; + + listInit(&pFabricImportDesc->waitingImportersList, + portMemAllocatorGetGlobalNonPaged()); + + pFabricImportDesc->pLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + if (pFabricImportDesc->pLock == NULL) + goto fail; + + status = fabricImportCacheInsert(pFabric, &pFabricImportDesc->uuid, key, + pFabricImportDesc); + if (status != NV_OK) + goto fail; + + portSyncRwLockAcquireWrite(pFabricImportDesc->pLock); + + return pFabricImportDesc; + +fail: + _importDescriptorCleanup(pFabricImportDesc); + + portSyncRwLockReleaseWrite(pFabric->pFabricImportModuleLock); + + return NULL; +} + +static NV_STATUS +_memoryfabricimportv2Construct +( + MemoryFabricImportV2 *pMemoryFabricImportV2, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV00F9_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; + Memory *pMemory = staticCast(pMemoryFabricImportV2, Memory); + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc; + NV_EXPORT_MEM_PACKET *pExportPacket = &pAllocParams->expPacket; + NV_STATUS status; + NvU16 exportNodeId = memoryExportGetNodeId(pExportPacket); + NvU8 *pUuid = pExportPacket->uuid; + NV00F1_CTRL_FABRIC_EVENT importEvent; + + // If this a single-node UUID? + if (exportNodeId == NV_FABRIC_INVALID_NODE_ID) + return NV_ERR_NOT_SUPPORTED; + + // + // NV00F9_IMPORT_ID_MAX is reserved for MCFLA case. See + // mem_multicast_fabric.c + // + if (pAllocParams->id >= NV00F9_IMPORT_ID_MAX) + return NV_ERR_INVALID_ARGUMENT; + + pFabricImportDesc = _importDescriptorAlloc(pUuid, + exportNodeId, + pAllocParams->index, + pAllocParams->id); + if (pFabricImportDesc == NULL) + return NV_ERR_NO_MEMORY; + + // + // At this point the pFabricImportDesc is refcounted, locked and is + // safe to access. + // + + pMemoryFabricImportV2->pFabricImportDesc = pFabricImportDesc; + pMemoryFabricImportV2->expNodeId = exportNodeId; + + status = _importDescriptorEnqueueWait(pParams->hClient, + pFabricImportDesc, + pAllocParams->pOsEvent, + pMemory); + if (status != NV_OK) + goto fail; + + if (pFabricImportDesc->refCount > 1) + goto unlock; + + _initImportFabricEvent(exportNodeId, &pFabricImportDesc->uuid, + pAllocParams->index, pAllocParams->id, + &importEvent); + + pFabricImportDesc->importEventId = importEvent.id; + + status = fabricPostEventsV2(pFabric, &importEvent, 1); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to notify IMEX daemon of import event\n"); + goto fail; + } + + // + // DO NOT FAIL after the call to fabricPostEventsV2. + // This function is used to signal that the + // MemoryFabricImportV2 has been successfully constructed. + // It is important that we do not fail the constructor + // after the event has been posted. + // + +unlock: + portSyncRwLockReleaseWrite(pFabricImportDesc->pLock); + portSyncRwLockReleaseWrite(pFabric->pFabricImportModuleLock); + + return NV_OK; + +fail: + _importDescriptorDequeueWait(pFabricImportDesc, pMemory); + + _importDescriptorPutAndLockReleaseWrite(pFabricImportDesc, NV_FALSE); + + portSyncRwLockReleaseWrite(pFabric->pFabricImportModuleLock); + + pMemoryFabricImportV2->pFabricImportDesc = NULL; + + return status; +} + +NV_STATUS +memoryfabricimportv2Construct_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + if (RS_IS_COPY_CTOR(pParams)) + { + return memoryfabricimportv2CopyConstruct_IMPL(pMemoryFabricImportV2, + pCallContext, + pParams); + } + + return _memoryfabricimportv2Construct(pMemoryFabricImportV2, + pCallContext, pParams); + + // + // DO NOT ADD ANY CODE HERE. + // See _memoryfabricimportv2Construct for details. + // +} + +void +memoryfabricimportv2Destruct_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2 +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + Memory *pMemory = staticCast(pMemoryFabricImportV2, Memory); + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc = + pMemoryFabricImportV2->pFabricImportDesc; + + portSyncRwLockAcquireRead(pFabric->pFabricImportModuleLock); + + // + // Destruct pMemory here, under pFabricImportDesc->pLock. We want to skip + // the default memory destructor as it calls memdescDestroy(), which + // we don't want. + // + portSyncRwLockAcquireWrite(pFabricImportDesc->pLock); + + memDestructCommon(pMemory); + + _importDescriptorDequeueWait(pFabricImportDesc, pMemory); + + _importDescriptorPutAndLockReleaseWrite(pFabricImportDesc, NV_TRUE); + + portSyncRwLockReleaseRead(pFabric->pFabricImportModuleLock); +} + +NvBool +memoryfabricimportv2CanCopy_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2 +) +{ + return NV_TRUE; +} + +NV_STATUS +memoryfabricimportv2IsReady_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2, + NvBool bCopyConstructorContext +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc = + pMemoryFabricImportV2->pFabricImportDesc; + NV_STATUS status; + + // If the IMEX daemon is down, bail out. + if (fabricGetNodeId(pFabric) == NV_FABRIC_INVALID_NODE_ID) + return NV_ERR_INVALID_STATE; + + portSyncRwLockAcquireRead(pFabricImportDesc->pLock); + + if (!pFabricImportDesc->bMemdescInstalled) + status = NV_ERR_NOT_READY; + else if (pFabricImportDesc->pMemDesc == NULL) + status = NV_ERR_INVALID_OBJECT; + else + status = NV_OK; + + portSyncRwLockReleaseRead(pFabricImportDesc->pLock); + + return status; +} + +NV_STATUS +memoryfabricimportv2CopyConstruct_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2, + CALL_CONTEXT *pCallContext, + RS_RES_ALLOC_PARAMS_INTERNAL *pParams +) +{ + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc; + Memory *pMemory = staticCast(pMemoryFabricImportV2, Memory); + NV_STATUS status; + + MemoryFabricImportV2 *pSourceMemoryFabricImportV2 = + dynamicCast(pParams->pSrcRef->pResource, MemoryFabricImportV2); + + pFabricImportDesc = pSourceMemoryFabricImportV2->pFabricImportDesc; + + portSyncRwLockAcquireWrite(pFabricImportDesc->pLock); + + status = _importDescriptorEnqueueWait(pParams->hClient, + pFabricImportDesc, + NULL, + pMemory); + if (status == NV_OK) + { + pFabricImportDesc->refCount++; + pMemoryFabricImportV2->pFabricImportDesc = pFabricImportDesc; + pMemoryFabricImportV2->expNodeId = pFabricImportDesc->exportNodeId; + } + + portSyncRwLockReleaseWrite(pFabricImportDesc->pLock); + + return status; +} + +NV_STATUS +memoryfabricimportv2Control_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2, + CALL_CONTEXT *pCallContext, + RS_RES_CONTROL_PARAMS_INTERNAL *pParams +) +{ + NV_CHECK_OK_OR_RETURN(LEVEL_INFO, + memoryfabricimportv2IsReady(pMemoryFabricImportV2, NV_FALSE)); + + return resControl_IMPL(staticCast(pMemoryFabricImportV2, RsResource), + pCallContext, pParams); +} + +NV_STATUS +memoryfabricimportv2CtrlGetInfo_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2, + NV00F9_CTRL_GET_INFO_PARAMS *pParams +) +{ + FABRIC_IMPORT_MEMDESC_DATA *pMemdescData; + Memory *pMemory = staticCast(pMemoryFabricImportV2, Memory); + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc; + + pFabricImportDesc = pMemoryFabricImportV2->pFabricImportDesc; + + portSyncRwLockAcquireRead(pFabricImportDesc->pLock); + + pMemdescData = + (FABRIC_IMPORT_MEMDESC_DATA *)memdescGetMemData(pMemory->pMemDesc); + + pParams->memFlags = pMemdescData->memFlags; + pParams->physAttrs = pMemdescData->physAttrs; + pParams->size = memdescGetSize(pMemory->pMemDesc); + pParams->pageSize = memdescGetPageSize(pMemory->pMemDesc, AT_GPU); + + portSyncRwLockReleaseRead(pFabricImportDesc->pLock); + + return NV_OK; +} + +NV_STATUS +memoryfabricimportv2GetMapAddrSpace_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2, + CALL_CONTEXT *pCallContext, + NvU32 mapFlags, + NV_ADDRESS_SPACE *pAddrSpace +) +{ + *pAddrSpace = ADDR_FABRIC_V2; + return NV_OK; +} + +void +memoryfabricimportv2RemoveFromCache_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2 +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_FABRIC_IMPORT_DESCRIPTOR *pFabricImportDesc; + + pFabricImportDesc = pMemoryFabricImportV2->pFabricImportDesc; + + portSyncRwLockAcquireRead(pFabricImportDesc->pLock); + + fabricImportCacheDelete(pFabric, &pFabricImportDesc->uuid, + pFabricImportDesc->key); + + portSyncRwLockReleaseRead(pFabricImportDesc->pLock); +} + +NvBool +memoryfabricimportv2IsExportAllowed_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2 +) +{ + return NV_FALSE; +} + +NvBool +memoryfabricimportv2IsGpuMapAllowed_IMPL +( + MemoryFabricImportV2 *pMemoryFabricImportV2, + OBJGPU *pGpu +) +{ + Memory *pMemory = staticCast(pMemoryFabricImportV2, Memory); + FABRIC_IMPORT_MEMDESC_DATA *pMemdescData; + NvU32 cliqueId; + NV_STATUS status; + + if (!gpuFabricProbeIsSupported(pGpu)) + return NV_TRUE; + + pMemdescData = + (FABRIC_IMPORT_MEMDESC_DATA *)memdescGetMemData(pMemory->pMemDesc); + + status = gpuFabricProbeGetFabricCliqueId(pGpu->pGpuFabricProbeInfoKernel, + &cliqueId); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "unable to query cliqueId 0x%x\n", status); + return NV_FALSE; + } + + return (cliqueId == pMemdescData->cliqueId); +} diff --git a/src/nvidia/src/kernel/mem_mgr/mem_list.c b/src/nvidia/src/kernel/mem_mgr/mem_list.c index 83ea04975f..d95c6aadcf 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_list.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_list.c @@ -263,11 +263,7 @@ memlistConstruct_IMPL { NvU32 attr2 = 0; - if ((src_pMemDesc != NULL) || bContig) - { - NV_ASSERT(0); - return NV_ERR_NOT_SUPPORTED; - } + NV_CHECK_OR_RETURN(LEVEL_ERROR, src_pMemDesc == NULL, NV_ERR_NOT_SUPPORTED); status = memdescCreate(&pMemDesc, pGpu, memSize, 0, bContig, addressSpace, Cache, diff --git a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c index ce602cf394..fa79209478 100644 --- a/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c +++ b/src/nvidia/src/kernel/mem_mgr/mem_multicast_fabric.c @@ -29,6 +29,16 @@ *****************************************************************************/ #define NVOC_MEM_MULTICAST_FABRIC_H_PRIVATE_ACCESS_ALLOWED +/* + * Lock ordering + * + * RMAPI Lock + * |_Client Lock + * |_GPU(s) Lock + * |_MCFLA Module Lock + * |_MCFLA Descriptor Lock + */ + #include "os/os.h" #include "core/locks.h" #include "nvport/nvport.h" @@ -45,6 +55,9 @@ #include "mem_mgr/mem_multicast_fabric.h" #include "published/hopper/gh100/dev_mmu.h" +#include "class/cl00f9.h" +#include "mem_mgr/mem_export.h" + #include "gpu/gpu_fabric_probe.h" typedef struct mem_multicast_fabric_attach_mem_info_node @@ -69,10 +82,29 @@ typedef struct mem_multicast_fabric_gpu_info NvU32 cliqueId; NvBool bMcflaAlloc; + // + // Unique import event ID. Valid only if the GPU was remotely attached to + // the prime MCFLA object + // + NvU64 attachEventId; + + // // Tracks memory attached using NV00FD_CTRL_CMD_ATTACH_MEM + // + // GPU lock must be taken to protect this tree. + // PNODE pAttachMemInfoTree; } MEM_MULTICAST_FABRIC_GPU_INFO; +typedef struct mem_multicast_fabric_remote_gpu_info +{ + NvU32 cliqueId; + NvU64 key; +} MEM_MULTICAST_FABRIC_REMOTE_GPU_INFO; + +MAKE_MULTIMAP(MemMulticastFabricRemoteGpuInfoMap, + MEM_MULTICAST_FABRIC_REMOTE_GPU_INFO); + MAKE_LIST(MemMulticastFabricClientInfoList, MEM_MULTICAST_FABRIC_CLIENT_INFO); MAKE_LIST(MemMulticastFabricGpuInfoList, MEM_MULTICAST_FABRIC_GPU_INFO); @@ -139,6 +171,27 @@ typedef struct mem_multicast_fabric_descriptor // No. of unique GPUs currently attached to the multicast object NvU32 numAttachedGpus; + // Export object information associated with this import descriptor. + NvU16 exportNodeId; + NvU16 index; + + // Same as packet.uuid, but uses NvUuid type. + NvUuid expUuid; + + // Import cache key + NvU64 cacheKey; + + // Map of attached remote GPU info + MemMulticastFabricRemoteGpuInfoMap remoteGpuInfoMap; + + // + // The lock protects MEM_MULTICAST_FABRIC_DESCRIPTOR, the MCFLA descriptor. + // + // The lock should be taken only if an MCFLA descriptor is safe + // to access i.e., holding the module lock or the accessing thread + // has the MCFLA descriptor refcounted. + // + PORT_RWLOCK *pLock; } MEM_MULTICAST_FABRIC_DESCRIPTOR; static NvBool @@ -149,9 +202,63 @@ _memMulticastFabricIsPrime { NvBool bPrime = NV_TRUE; +#ifdef NV_MEMORY_MULTICAST_FABRIC_ALLOC_FLAGS_USE_EXPORT_PACKET + // + // If an MCFLA object is allocated using export packet (UUID), then it + // is a non-prime (imported) object. Such objects are just extension + // of the prime (exported) MCFLA objects. + // + bPrime = !(allocFlags & + NV_MEMORY_MULTICAST_FABRIC_ALLOC_FLAGS_USE_EXPORT_PACKET); +#endif + return bPrime; } +static void +_memMulticastFabricInitAttachEvent +( + NvU64 gpuFabricProbeHandle, + NvU64 key, + NvU32 cliqueId, + NvU16 exportNodeId, + NvU16 index, + NvUuid *pExportUuid, + NV00F1_CTRL_FABRIC_EVENT *pEvent +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + + pEvent->imexChannel = 0; + pEvent->type = NV00F1_CTRL_FABRIC_EVENT_TYPE_REMOTE_GPU_ATTACH; + pEvent->id = fabricGenerateEventId(pFabric); + + pEvent->data.attach.gpuFabricProbeHandle = gpuFabricProbeHandle; + pEvent->data.attach.key = key; + pEvent->data.attach.cliqueId = cliqueId; + pEvent->data.attach.index = index; + pEvent->data.attach.exportNodeId = exportNodeId; + portMemCopy(pEvent->data.attach.exportUuid, NV_MEM_EXPORT_UUID_LEN, + pExportUuid->uuid, NV_MEM_EXPORT_UUID_LEN); +} + +static void +_memMulticastFabricInitUnimportEvent +( + NvU64 attachEventId, + NvU16 exportNodeId, + NV00F1_CTRL_FABRIC_EVENT *pEvent +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + + pEvent->imexChannel = 0; + pEvent->type = NV00F1_CTRL_FABRIC_EVENT_TYPE_MEM_UNIMPORT; + pEvent->id = fabricGenerateEventId(pFabric); + pEvent->data.unimport.exportNodeId = exportNodeId; + pEvent->data.unimport.importEventId = attachEventId; +} + static NV_STATUS _memMulticastFabricValidateAllocParams @@ -198,15 +305,45 @@ _memMulticastFabricValidateAllocParams return NV_OK; } +static void +_memMulticastFabricDescriptorCleanup +( + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc +) +{ + if (pMulticastFabricDesc == NULL) + return; + + NV_ASSERT(listCount(&pMulticastFabricDesc->gpuInfoList) == 0); + listDestroy(&pMulticastFabricDesc->gpuInfoList); + + multimapDestroy(&pMulticastFabricDesc->remoteGpuInfoMap); + + NV_ASSERT(pMulticastFabricDesc->numAttachedGpus == 0); + NV_ASSERT(pMulticastFabricDesc->localAttachedGpusMask == 0); + + NV_ASSERT(listCount(&pMulticastFabricDesc->waitingClientsList) == 0); + listDestroy(&pMulticastFabricDesc->waitingClientsList); + + memdescDestroy(pMulticastFabricDesc->pMemDesc); + + if (pMulticastFabricDesc->pLock != NULL) + portSyncRwLockDestroy(pMulticastFabricDesc->pLock); + + portMemFree(pMulticastFabricDesc); +} + static MEM_MULTICAST_FABRIC_DESCRIPTOR* -_memMulticastFabricDescriptorAllocUnderLock +_memMulticastFabricDescriptorAlloc ( MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_ALLOCATION_PARAMETERS *pAllocParams ) { + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + NV_STATUS status; pMulticastFabricDesc = portMemAllocNonPaged( sizeof(MEM_MULTICAST_FABRIC_DESCRIPTOR)); @@ -232,11 +369,34 @@ _memMulticastFabricDescriptorAllocUnderLock pMulticastFabricDesc->numMaxGpus = pAllocParams->numGpus; pMulticastFabricDesc->inbandReqId = osGetTimestamp(); + multimapInit(&pMulticastFabricDesc->remoteGpuInfoMap, + portMemAllocatorGetGlobalNonPaged()); + pMulticastFabricDesc->exportNodeId = NV_FABRIC_INVALID_NODE_ID; + + pMulticastFabricDesc->pLock = + portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged()); + if (pMulticastFabricDesc->pLock == NULL) + goto fail; + + status = fabricMulticastSetupCacheInsert(pFabric, + pMulticastFabricDesc->inbandReqId, + pMulticastFabricDesc); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to track memdesc 0x%x", status); + goto fail; + } + return pMulticastFabricDesc; + +fail: + _memMulticastFabricDescriptorCleanup(pMulticastFabricDesc); + + return NULL; } static void -_memMulticastFabricDescriptorFlushClientsUnderLock +_memMulticastFabricDescriptorFlushClients ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc ) @@ -259,7 +419,7 @@ _memMulticastFabricDescriptorFlushClientsUnderLock } static NV_STATUS -_memMulticastFabricDescriptorEnqueueWaitUnderLock +_memMulticastFabricDescriptorEnqueueWait ( NvHandle hClient, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, @@ -297,15 +457,14 @@ _memMulticastFabricDescriptorEnqueueWaitUnderLock // if (pMulticastFabricDesc->bMemdescInstalled) { - _memMulticastFabricDescriptorFlushClientsUnderLock( - pMulticastFabricDesc); + _memMulticastFabricDescriptorFlushClients(pMulticastFabricDesc); } return NV_OK; } static void -_memMulticastFabricDescriptorDequeueWaitUnderLock +_memMulticastFabricDescriptorDequeueWait ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, Memory *pMemory @@ -334,7 +493,7 @@ _memMulticastFabricDescriptorDequeueWaitUnderLock } static NV_STATUS -_memMulticastFabricGpuInfoAddUnderLock +_memMulticastFabricGpuInfoAdd ( MemoryMulticastFabric *pMemoryMulticastFabric, RS_RES_CONTROL_PARAMS_INTERNAL *pParams @@ -382,7 +541,7 @@ _memMulticastFabricGpuInfoAddUnderLock } static void -_memMulticastFabricGpuInfoRemoveUnderLock +_memMulticastFabricGpuInfoRemove ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc ) @@ -395,6 +554,22 @@ _memMulticastFabricGpuInfoRemoveUnderLock while ((pNode = listHead(&pMulticastFabricDesc->gpuInfoList)) != NULL) { + // + // Enqueue unimport event before the callback to release GPU. + // This ordering is important. + // + if (!_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags)) + { + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV00F1_CTRL_FABRIC_EVENT unimportEvent; + + _memMulticastFabricInitUnimportEvent(pNode->attachEventId, + pMulticastFabricDesc->exportNodeId, + &unimportEvent); + + NV_CHECK(LEVEL_WARNING, + fabricPostEventsV2(pFabric, &unimportEvent, 1) == NV_OK); + } freeCallback.pCb = osReleaseGpuOsInfo; freeCallback.pCbData = (void *)pNode->pGpuOsInfo; @@ -409,7 +584,7 @@ _memMulticastFabricGpuInfoRemoveUnderLock } NV_STATUS -_memMulticastFabricSendInbandTeamSetupRequestV2UnderLock +_memMulticastFabricSendInbandTeamSetupRequestV2 ( OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc @@ -424,6 +599,7 @@ _memMulticastFabricSendInbandTeamSetupRequestV2UnderLock NvU32 sendDataSize; NV_STATUS status = NV_OK; NvU16 numKeys = 1; + MemMulticastFabricRemoteGpuInfoMapSupermapIter smIter; sendDataParams = (NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *) @@ -438,6 +614,12 @@ _memMulticastFabricSendInbandTeamSetupRequestV2UnderLock pMcTeamSetupReq = (nvlink_inband_mc_team_setup_req_v2_t *)&pMcTeamSetupReqMsg->mcTeamSetupReq; + // + // Submap of remoteGpuInfoMap represent a node. As there is a key/node, + // count submap to calculate numKeys. + // + numKeys += multimapCountSubmaps(&pMulticastFabricDesc->remoteGpuInfoMap); + payloadSize = (NvU32)(sizeof(nvlink_inband_mc_team_setup_req_v2_t) + (sizeof(pMcTeamSetupReq->gpuHandlesAndKeys[0]) * (pMulticastFabricDesc->numMaxGpus + numKeys))); @@ -463,9 +645,48 @@ _memMulticastFabricSendInbandTeamSetupRequestV2UnderLock pNode = listNext(&pMulticastFabricDesc->gpuInfoList, pNode)) pMcTeamSetupReq->gpuHandlesAndKeys[idx++] = pNode->gpuProbeHandle; + // Fill remote GPUs probe handles per submap (i.e per node) + smIter = multimapSubmapIterAll(&pMulticastFabricDesc->remoteGpuInfoMap); + + while (multimapSubmapIterNext(&smIter)) + { + MemMulticastFabricRemoteGpuInfoMapSubmap *pSubmap = smIter.pValue; + MemMulticastFabricRemoteGpuInfoMapIter iter; + + iter = multimapSubmapIterItems(&pMulticastFabricDesc->remoteGpuInfoMap, + pSubmap); + + while (multimapItemIterNext(&iter)) + { + // Item key is the GPU probe handle + pMcTeamSetupReq->gpuHandlesAndKeys[idx++] = + multimapItemKey(&pMulticastFabricDesc->remoteGpuInfoMap, + iter.pValue); + } + } + // Fill local key pMcTeamSetupReq->gpuHandlesAndKeys[idx++] = pMulticastFabricDesc->inbandReqId; + // Fill remote keys per submap (i.e per node) + smIter = multimapSubmapIterAll(&pMulticastFabricDesc->remoteGpuInfoMap); + + while (multimapSubmapIterNext(&smIter)) + { + MemMulticastFabricRemoteGpuInfoMapSubmap *pSubmap = smIter.pValue; + MEM_MULTICAST_FABRIC_REMOTE_GPU_INFO *pRemoteNode = NULL; + MemMulticastFabricRemoteGpuInfoMapIter iter; + + iter = multimapSubmapIterItems(&pMulticastFabricDesc->remoteGpuInfoMap, + pSubmap); + + if (multimapItemIterNext(&iter)) + { + pRemoteNode = iter.pValue; + pMcTeamSetupReq->gpuHandlesAndKeys[idx++] = pRemoteNode->key; + } + } + if (idx != (pMcTeamSetupReq->numGpuHandles + numKeys)) { NV_ASSERT(0); @@ -493,7 +714,7 @@ _memMulticastFabricSendInbandTeamSetupRequestV2UnderLock } NV_STATUS -_memMulticastFabricSendInbandTeamSetupRequestV1UnderLock +_memMulticastFabricSendInbandTeamSetupRequestV1 ( OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc @@ -561,7 +782,7 @@ _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock } NV_STATUS -_memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock +_memMulticastFabricSendInbandTeamReleaseRequestV1 ( OBJGPU *pGpu, NvU64 mcTeamHandle @@ -609,7 +830,7 @@ _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock } NV_STATUS -_memMulticastFabricSendInbandTeamSetupRequestUnderlock +_memMulticastFabricSendInbandTeamSetupRequest ( OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc @@ -625,12 +846,12 @@ _memMulticastFabricSendInbandTeamSetupRequestUnderlock if (fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2) { - return _memMulticastFabricSendInbandTeamSetupRequestV2UnderLock(pGpu, + return _memMulticastFabricSendInbandTeamSetupRequestV2(pGpu, pMulticastFabricDesc); } else if (fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V1) { - return _memMulticastFabricSendInbandTeamSetupRequestV1UnderLock(pGpu, + return _memMulticastFabricSendInbandTeamSetupRequestV1(pGpu, pMulticastFabricDesc); } else @@ -640,7 +861,7 @@ _memMulticastFabricSendInbandTeamSetupRequestUnderlock } NV_STATUS -_memMulticastFabricSendInbandTeamReleaseRequestUnderLock +_memMulticastFabricSendInbandTeamReleaseRequest ( OBJGPU *pGpu, NvU64 mcTeamHandle @@ -661,12 +882,12 @@ _memMulticastFabricSendInbandTeamReleaseRequestUnderLock if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_RELEASE_V1)) return NV_ERR_NOT_SUPPORTED; - return _memMulticastFabricSendInbandTeamReleaseRequestV1UnderLock(pGpu, - mcTeamHandle); + return _memMulticastFabricSendInbandTeamReleaseRequestV1(pGpu, + mcTeamHandle); } -NV_STATUS -_memMulticastFabricSendInbandRequestUnderLock +static NV_STATUS +_memMulticastFabricSendInbandRequest ( OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, @@ -674,26 +895,26 @@ _memMulticastFabricSendInbandRequestUnderLock ) { NV_STATUS status = NV_OK; + NvU32 gpuMask; - // If pGpu is NULL, pick the first one attached to the object. if (pGpu == NULL) - pGpu = listHead(&pMulticastFabricDesc->gpuInfoList)->pGpu; + return NV_ERR_NOT_SUPPORTED; - // If nothing is attached locally... - if (pGpu == NULL) + gpuMask = NVBIT(gpuGetInstance(pGpu)); + if (!rmGpuGroupLockIsOwner(0, GPU_LOCK_GRP_MASK, &gpuMask)) { - NV_PRINTF(LEVEL_ERROR, "No locally attached GPU found\n"); + NV_ASSERT(0); return NV_ERR_INVALID_STATE; } switch (requestType) { case MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST: - status = _memMulticastFabricSendInbandTeamSetupRequestUnderlock(pGpu, + status = _memMulticastFabricSendInbandTeamSetupRequest(pGpu, pMulticastFabricDesc); break; case MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST: - status = _memMulticastFabricSendInbandTeamReleaseRequestUnderLock(pGpu, + status = _memMulticastFabricSendInbandTeamReleaseRequest(pGpu, pMulticastFabricDesc->mcTeamHandle); break; default: @@ -704,6 +925,10 @@ _memMulticastFabricSendInbandRequestUnderLock return status; } +// +// This function may be called with RO pMulticastFabricDesc->pLock. Don't modify +// pMulticastFabricDesc. +// static void _memorymulticastfabricDetachMem ( @@ -716,7 +941,7 @@ _memorymulticastfabricDetachMem MEMORY_DESCRIPTOR *pPhysMemDesc; MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *pAttachMemInfoNode; - pAttachMemInfoNode = \ + pAttachMemInfoNode = (MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *)pMemNode->Data; pPhysMemDesc = pAttachMemInfoNode->pPhysMemDesc; @@ -739,6 +964,8 @@ _memorymulticastfabricBatchDetachMem MEM_MULTICAST_FABRIC_GPU_INFO *pGpuNode; NODE *pMemNode; FABRIC_VASPACE *pFabricVAS; + NvU32 gpuMask; + OBJGPU *pGpu; pFabricMemDesc = pMulticastFabricDesc->pMemDesc; NV_ASSERT_OR_RETURN_VOID(pFabricMemDesc != NULL); @@ -747,7 +974,12 @@ _memorymulticastfabricBatchDetachMem pGpuNode != NULL; pGpuNode = listNext(&pMulticastFabricDesc->gpuInfoList, pGpuNode)) { - pFabricVAS = dynamicCast(pGpuNode->pGpu->pFabricVAS, FABRIC_VASPACE); + pGpu = pGpuNode->pGpu; + gpuMask = NVBIT(gpuGetInstance(pGpu)); + + NV_ASSERT(rmGpuGroupLockIsOwner(0, GPU_LOCK_GRP_MASK, &gpuMask)); + + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); if (pFabricVAS == NULL) { NV_ASSERT(0); @@ -777,45 +1009,97 @@ _memorymulticastfabricBatchDetachMem } static void -_memMulticastFabricDescriptorFreeUnderLock +_memMulticastFabricDescriptorFree ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc ) { Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NvU32 allocFlags; + NvU32 gpuMask; + NvBool bGpuLockTaken = NV_FALSE; if (pMulticastFabricDesc == NULL) return; + // + // Take pMulticastFabricModuleLock to synchronize with + // memorymulticastfabricTeamSetupResponseCallback() and + // _memMulticastFabricDescriptorAllocUsingExpPacket(). + // We don't want to delete pMulticastFabricDesc under them. + // + portSyncRwLockAcquireWrite(pFabric->pMulticastFabricModuleLock); + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); + pMulticastFabricDesc->refCount--; if (pMulticastFabricDesc->refCount != 0) + { + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + portSyncRwLockReleaseWrite(pFabric->pMulticastFabricModuleLock); + return; + } allocFlags = pMulticastFabricDesc->allocFlags; + // + // Empty caches so new calls to + // memorymulticastfabricTeamSetupResponseCallback() and + // _memMulticastFabricDescriptorAllocUsingExpPacket() fail. + // + if (!_memMulticastFabricIsPrime(allocFlags)) + { + NV_ASSERT(pMulticastFabricDesc->cacheKey != 0); + fabricImportCacheDelete(pFabric, &pMulticastFabricDesc->expUuid, + pMulticastFabricDesc->cacheKey); + } + + fabricMulticastSetupCacheDelete(pFabric, + pMulticastFabricDesc->inbandReqId); + + // Now I am the only one holding the pMulticastFabricDesc, drop the locks. + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + portSyncRwLockReleaseWrite(pFabric->pMulticastFabricModuleLock); + + // + // TODO: Make this a per-GPU lock in future. For now both dup() and free() + // forces all GPU lock. + // + + if (!rmGpuLockIsOwner()) + { + gpuMask = GPUS_LOCK_ALL; + + if (rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM, &gpuMask) == NV_OK) + { + bGpuLockTaken = NV_TRUE; + } + else + { + NV_ASSERT(0); + } + } + if (pMulticastFabricDesc->pMemDesc != NULL) { + MEM_MULTICAST_FABRIC_GPU_INFO *pNode = + listHead(&pMulticastFabricDesc->gpuInfoList); + NV_ASSERT(pMulticastFabricDesc->bMemdescInstalled); + NV_ASSERT(pNode != NULL); _memorymulticastfabricBatchDetachMem(pMulticastFabricDesc); if (_memMulticastFabricIsPrime(allocFlags)) { - _memMulticastFabricSendInbandRequestUnderLock( - NULL, pMulticastFabricDesc, + _memMulticastFabricSendInbandRequest(pNode->pGpu, + pMulticastFabricDesc, MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); } } - if (!_memMulticastFabricIsPrime(allocFlags)) - { - } - - fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, - pMulticastFabricDesc->inbandReqId); - if (pMulticastFabricDesc->bInbandReqInProgress) { OS_WAIT_QUEUE *pWq; @@ -826,8 +1110,7 @@ _memMulticastFabricDescriptorFreeUnderLock if (pWq != NULL) { - NV_ASSERT_OK(fabricMulticastCleanupCacheInsertUnderLock_IMPL( - pFabric, + NV_ASSERT_OK(fabricMulticastCleanupCacheInsert(pFabric, pMulticastFabricDesc->inbandReqId, pWq)); @@ -841,79 +1124,213 @@ _memMulticastFabricDescriptorFreeUnderLock } } - _memMulticastFabricGpuInfoRemoveUnderLock(pMulticastFabricDesc); + _memMulticastFabricGpuInfoRemove(pMulticastFabricDesc); - NV_ASSERT(listCount(&pMulticastFabricDesc->gpuInfoList) == 0); - listDestroy(&pMulticastFabricDesc->gpuInfoList); + if (bGpuLockTaken) + { + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + bGpuLockTaken = NV_FALSE; + } - NV_ASSERT(pMulticastFabricDesc->numAttachedGpus == 0); - NV_ASSERT(pMulticastFabricDesc->localAttachedGpusMask == 0); + _memMulticastFabricDescriptorCleanup(pMulticastFabricDesc); +} - NV_ASSERT(listCount(&pMulticastFabricDesc->waitingClientsList) == 0); - listDestroy(&pMulticastFabricDesc->waitingClientsList); +static +MEM_MULTICAST_FABRIC_DESCRIPTOR* +_memMulticastFabricDescriptorAllocUsingExpPacket +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_ALLOCATION_PARAMETERS *pAllocParams +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + NvU64 cacheKey; + NvUuid expUuid; + NV_EXPORT_MEM_PACKET *pExportPacket = &pAllocParams->expPacket; + NV_STATUS status = NV_OK; - memdescDestroy(pMulticastFabricDesc->pMemDesc); + ct_assert(NV_MEM_EXPORT_UUID_LEN == NV_UUID_LEN); + portMemCopy(expUuid.uuid, NV_UUID_LEN, pExportPacket->uuid, + NV_MEM_EXPORT_UUID_LEN); - portMemFree(pMulticastFabricDesc); + // + // To reuse import cache with the UCFLA class (0xf9), we create + // unique import cache keys for MCFLA using NV00F9_IMPORT_ID_MAX, which + // are never used by UCFLA. + // + cacheKey = + (NV00F9_IMPORT_ID_MAX << NV00F9_IMPORT_ID_SHIFT) | pAllocParams->index; + + // + // Take pMulticastFabricModuleLock to synchronize multiple constructors + // to share the cached pMulticastFabricDesc. Without this lock, two or + // more constructors may see the import cache empty at the same time. + // + // We want the following sequence happen atomically: + // + // pMulticastFabricDesc = fabricImportCacheGet(..); + // if (pMulticastFabricDesc == NULL) + // { + // pMulticastFabricDesc = alloc(); + // fabricImportCacheInsert(pMulticastFabricDesc); + // ... + // } + // + // Also, it is important to synchronize the constructor with the destructor. + // The constructor looks up and refcounts pMulticastFabricDesc + // non-atomically. Thus, pMulticastFabricDesc may be destroyed before + // it could be refcounted. + // + // pMulticastFabricDesc = fabricImportCacheGet(..); + // if (pMulticastFabricDesc != NULL) + // { + // pMulticastFabricDesc->lock(); + // pMulticastFabricDesc->refCount++; + // ... + // } + // + + portSyncRwLockAcquireWrite(pFabric->pMulticastFabricModuleLock); + + pMulticastFabricDesc = fabricImportCacheGet(pFabric, &expUuid, cacheKey); + if (pMulticastFabricDesc != NULL) + { + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); + + NV_ASSERT(!_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags)); + + pMulticastFabricDesc->refCount++; + + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + + goto done; + } + + pMulticastFabricDesc = + _memMulticastFabricDescriptorAlloc(pMemoryMulticastFabric, + pAllocParams); + + if (pMulticastFabricDesc == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + // + // For the imported object, set numMaxGpus to NV_U32_MAX for two reasons. + // a. It doesn't track how many GPUs the team should have. That's tracked + // by the exporter. + // b. This object should never send MCFLA team setup request to the FM. + // Setting numMaxGpus to NV_U32_MAX, makes sure that implicitly. + // + pMulticastFabricDesc->numMaxGpus = NV_U32_MAX; + + // + // allocSize is set to zero. GFM will provide that in the team setup + // response. + // + pMulticastFabricDesc->allocSize = 0; + + // + // For now only pageSize support is 512MB. This needs to be revisited + // in case we support more pagesizes. + // + pMulticastFabricDesc->pageSize = NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M; + pMulticastFabricDesc->alignment = NV_MEMORY_MULTICAST_FABRIC_PAGE_SIZE_512M; + + pMulticastFabricDesc->exportNodeId = memoryExportGetNodeId(pExportPacket); + pMulticastFabricDesc->expUuid = expUuid; + pMulticastFabricDesc->cacheKey = cacheKey; + pMulticastFabricDesc->index = pAllocParams->index; + + // insert into cache once ready... + status = fabricImportCacheInsert(pFabric, &expUuid, cacheKey, + pMulticastFabricDesc); + +done: + portSyncRwLockReleaseWrite(pFabric->pMulticastFabricModuleLock); + + if (status != NV_OK) + { + _memMulticastFabricDescriptorFree(pMulticastFabricDesc); + pMulticastFabricDesc = NULL; + } + + return pMulticastFabricDesc; } NV_STATUS -_memMulticastFabricConstructUnderLock +_memMulticastFabricConstruct ( MemoryMulticastFabric *pMemoryMulticastFabric, CALL_CONTEXT *pCallContext, RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; NV_STATUS status = NV_OK; + if (!_memMulticastFabricIsPrime(pAllocParams->allocFlags)) { + NV_EXPORT_MEM_PACKET *pExportPacket = &pAllocParams->expPacket; + + // If this a single-node UUID? + if (memoryExportGetNodeId(pExportPacket) == NV_FABRIC_INVALID_NODE_ID) + return NV_ERR_NOT_SUPPORTED; + pMulticastFabricDesc = - _memMulticastFabricDescriptorAllocUnderLock( + _memMulticastFabricDescriptorAllocUsingExpPacket( pMemoryMulticastFabric, pAllocParams); } + else + { + pMulticastFabricDesc = + _memMulticastFabricDescriptorAlloc(pMemoryMulticastFabric, + pAllocParams); + } if (pMulticastFabricDesc == NULL) return NV_ERR_NO_MEMORY; - // Track pMulticastFabricDesc if freshly allocated... - if (pMulticastFabricDesc->refCount == 1) - { - status = fabricMulticastSetupCacheInsertUnderLock_IMPL(pFabric, - pMulticastFabricDesc->inbandReqId, - pMulticastFabricDesc); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Failed to track memdesc 0x%x", status); - goto fail; - } - } + // + // At this point the pMulticastFabricDesc can be fresh or in-use, but will + // be refcounted for safe access. If in-use, it can get modified before + // pMulticastFabricDesc->pLock() is acquired. + // + + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); - status = _memMulticastFabricDescriptorEnqueueWaitUnderLock( - pParams->hClient, - pMulticastFabricDesc, - pAllocParams->pOsEvent, - pMemory); + status = _memMulticastFabricDescriptorEnqueueWait(pParams->hClient, + pMulticastFabricDesc, + pAllocParams->pOsEvent, + pMemory); if (status != NV_OK) goto fail; pMemoryMulticastFabric->pMulticastFabricDesc = pMulticastFabricDesc; + pMemoryMulticastFabric->expNodeId = pMulticastFabricDesc->exportNodeId; + pMemoryMulticastFabric->bImported = + !_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags); + + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + return NV_OK; fail: - _memMulticastFabricDescriptorFreeUnderLock(pMulticastFabricDesc); + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + + _memMulticastFabricDescriptorFree(pMulticastFabricDesc); return status; } NV_STATUS -_memMulticastFabricCreateMemDescUnderLock +_memMulticastFabricCreateMemDesc ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, NvU64 mcAddressBase, @@ -952,7 +1369,7 @@ _memMulticastFabricCreateMemDescUnderLock } void -_memMulticastFabricInstallMemDescUnderLock +_memMulticastFabricInstallMemDesc ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, MEMORY_DESCRIPTOR *pMemDesc, @@ -967,11 +1384,11 @@ _memMulticastFabricInstallMemDescUnderLock pMulticastFabricDesc->mcTeamHandle = mcTeamHandle; pMulticastFabricDesc->mcTeamStatus = status; - _memMulticastFabricDescriptorFlushClientsUnderLock(pMulticastFabricDesc); + _memMulticastFabricDescriptorFlushClients(pMulticastFabricDesc); } static NV_STATUS -_memorymulticastFabricAllocVasUnderLock +_memorymulticastFabricAllocVas ( MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, MEMORY_DESCRIPTOR *pFabricMemDesc @@ -988,6 +1405,14 @@ _memorymulticastFabricAllocVasUnderLock pGpuInfo = listNext(&pMulticastFabricDesc->gpuInfoList, pGpuInfo)) { OBJGPU *pGpu = pGpuInfo->pGpu; + NvU32 gpuMask = NVBIT(gpuGetInstance(pGpu)); + + if (!rmGpuGroupLockIsOwner(0, GPU_LOCK_GRP_MASK, &gpuMask)) + { + NV_ASSERT(0); + status = NV_ERR_INVALID_STATE; + goto cleanup; + } pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); if (pFabricVAS == NULL) @@ -1047,7 +1472,7 @@ _memorymulticastFabricAllocVasUnderLock } static void -_memMulticastFabricAttachGpuPostProcessorUnderLock +_memMulticastFabricAttachGpuPostProcessor ( OBJGPU *pGpu, MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc, @@ -1066,6 +1491,13 @@ _memMulticastFabricAttachGpuPostProcessorUnderLock // NV_ASSERT(mcTeamStatus != NV_ERR_NOT_READY); + // + // There is a failure case on multinode systems, where a buggy client + // may cause an error the prime object (e.g. attaching a GPU even after all + // the required GPUs were attached) after MCFLA team request is sent to the + // GFM. This should never happen under normal case, but in case it happens, + // fail loudly. + // // Initial value is not NV_ERR_NOT_READY, means a failure was observed. if (pMulticastFabricDesc->mcTeamStatus != NV_ERR_NOT_READY) { @@ -1097,16 +1529,15 @@ _memMulticastFabricAttachGpuPostProcessorUnderLock goto installMemDesc; } - status = _memMulticastFabricCreateMemDescUnderLock(pMulticastFabricDesc, - mcAddressBase, &pMemDesc); + status = _memMulticastFabricCreateMemDesc(pMulticastFabricDesc, + mcAddressBase, &pMemDesc); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Failed to allocate fabric memdesc\n"); goto installMemDesc; } - status = _memorymulticastFabricAllocVasUnderLock(pMulticastFabricDesc, - pMemDesc); + status = _memorymulticastFabricAllocVas(pMulticastFabricDesc, pMemDesc); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Failed to allocate fabric VAS\n"); @@ -1116,41 +1547,20 @@ _memMulticastFabricAttachGpuPostProcessorUnderLock } installMemDesc: - _memMulticastFabricInstallMemDescUnderLock(pMulticastFabricDesc, - pMemDesc, - mcTeamHandle, - status); + _memMulticastFabricInstallMemDesc(pMulticastFabricDesc, pMemDesc, + mcTeamHandle, status); if ((status != NV_OK) && (mcTeamStatus == NV_OK)) - _memMulticastFabricSendInbandRequestUnderLock(pGpu, - pMulticastFabricDesc, + _memMulticastFabricSendInbandRequest(pGpu, pMulticastFabricDesc, MEM_MULTICAST_FABRIC_TEAM_RELEASE_REQUEST); } -void -_memorymulticastfabricDestructUnderLock +NV_STATUS +memorymulticastfabricTeamSetupResponseCallback ( - MemoryMulticastFabric *pMemoryMulticastFabric -) -{ - Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); - - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ - pMemoryMulticastFabric->pMulticastFabricDesc; - - memDestructCommon(pMemory); - - _memMulticastFabricDescriptorDequeueWaitUnderLock(pMulticastFabricDesc, - pMemory); - - _memMulticastFabricDescriptorFreeUnderLock(pMulticastFabricDesc); -} - -NV_STATUS -memorymulticastfabricTeamSetupResponseCallback -( - NvU32 gpuInstance, - NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams + NvU32 gpuInstance, + NvU64 *pNotifyGfidMask, + NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams ) { Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); @@ -1162,7 +1572,6 @@ memorymulticastfabricTeamSetupResponseCallback NvU64 mcTeamHandle = 0; NvU64 mcAddressBase = 0; NvU64 mcAddressSize = 0; - NvU8 *pRsvd = NULL; OBJGPU *pGpu; NV_ASSERT(pInbandRcvParams != NULL); @@ -1174,10 +1583,10 @@ memorymulticastfabricTeamSetupResponseCallback return NV_ERR_INVALID_ARGUMENT; } - pMcTeamSetupRspMsg = \ + pMcTeamSetupRspMsg = (nvlink_inband_mc_team_setup_rsp_msg_t *)&pInbandRcvParams->data[0]; - pMcTeamSetupRsp = \ + pMcTeamSetupRsp = (nvlink_inband_mc_team_setup_rsp_t *)&pMcTeamSetupRspMsg->mcTeamSetupRsp; requestId = pMcTeamSetupRspMsg->msgHdr.requestId; @@ -1190,39 +1599,66 @@ memorymulticastfabricTeamSetupResponseCallback mcAddressBase = pMcTeamSetupRsp->mcAddressBase; mcAddressSize = pMcTeamSetupRsp->mcAddressSize; - // Make sure that the reserved fields are initialized to 0 - pRsvd = &pMcTeamSetupRsp->reserved[0]; +#if defined(DEBUG) || defined(DEVELOP) + { + // Make sure that the reserved fields are initialized to 0 + NvU8 *pRsvd = &pMcTeamSetupRsp->reserved[0]; - NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, - (sizeof(pMcTeamSetupRsp->reserved) - 1)) == 0); + NV_ASSERT((pRsvd[0] == 0) && portMemCmp(pRsvd, pRsvd + 1, + (sizeof(pMcTeamSetupRsp->reserved) - 1)) == 0); + } +#endif } - fabricMulticastFabricOpsMutexAcquire(pFabric); + // + // Acquire pMulticastFabricModuleLock here, to make sure + // pMulticastFabricDesc is not removed underneath us. + // The thread doesn't hold refcount on pMulticastFabricDesc. + // + portSyncRwLockAcquireWrite(pFabric->pMulticastFabricModuleLock); - pMulticastFabricDesc = \ - fabricMulticastSetupCacheGetUnderLock_IMPL(pFabric, requestId); + pMulticastFabricDesc = fabricMulticastSetupCacheGet(pFabric, requestId); if (pMulticastFabricDesc != NULL) { + fabricMulticastSetupCacheDelete(pFabric, requestId); + + // + // We have now safely acquired pMulticastFabricDesc->lock, which + // should block the destructor from removing pMulticastFabricDesc + // under us even if pMulticastFabricModuleLock is dropped. + // + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); + + // + // Drop pMulticastFabricModuleLock here as out of order, now we + // shouldn't need it ever. + // + portSyncRwLockReleaseWrite(pFabric->pMulticastFabricModuleLock); + pMulticastFabricDesc->bInbandReqInProgress = NV_FALSE; - fabricMulticastSetupCacheDeleteUnderLock_IMPL(pFabric, requestId); + _memMulticastFabricAttachGpuPostProcessor(pGpu, + pMulticastFabricDesc, + mcTeamStatus, + mcTeamHandle, + mcAddressBase, + mcAddressSize); - _memMulticastFabricAttachGpuPostProcessorUnderLock(pGpu, - pMulticastFabricDesc, - mcTeamStatus, - mcTeamHandle, - mcAddressBase, - mcAddressSize); + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); } else { - OS_WAIT_QUEUE *pWq; + // + // As pMulticastFabricDesc is not found, drop the lock right + // away. GPU locks are already taken to submit the team release + // request. + // + portSyncRwLockReleaseWrite(pFabric->pMulticastFabricModuleLock); if (mcTeamStatus == NV_OK) - (void)_memMulticastFabricSendInbandTeamReleaseRequestUnderLock( - pGpu, - mcTeamHandle); + (void)_memMulticastFabricSendInbandTeamReleaseRequest(pGpu, + mcTeamHandle); // // Check if there is any thread waiting for team release and @@ -1236,17 +1672,10 @@ memorymulticastfabricTeamSetupResponseCallback // descriptor is put to sleep until the team setup response // is received and a subsequent team release request is sent. // - - pWq = (OS_WAIT_QUEUE *)fabricMulticastCleanupCacheGetUnderLock_IMPL( - pFabric, - requestId); - - if (pWq != NULL) - osWakeUp(pWq); + fabricMulticastCleanupCacheInvokeCallback(pFabric, requestId, + fabricWakeUpThreadCallback); } - fabricMulticastFabricOpsMutexRelease(pFabric); - return NV_OK; } @@ -1258,45 +1687,40 @@ memorymulticastfabricConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV00FD_ALLOCATION_PARAMETERS *pAllocParams = pParams->pAllocParams; - NV_STATUS status = NV_OK; if (RS_IS_COPY_CTOR(pParams)) { - return memorymulticastfabricCopyConstruct_IMPL(pMemoryMulticastFabric, - pCallContext, - pParams); + return memorymulticastfabricCopyConstruct(pMemoryMulticastFabric, + pCallContext, pParams); } NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, _memMulticastFabricValidateAllocParams(pAllocParams)); - fabricMulticastFabricOpsMutexAcquire(pFabric); - - status = _memMulticastFabricConstructUnderLock(pMemoryMulticastFabric, - pCallContext, - pParams); - - fabricMulticastFabricOpsMutexRelease(pFabric); - - return status; + return _memMulticastFabricConstruct(pMemoryMulticastFabric, + pCallContext, pParams); } +// +// Note this function is not always called with the GPU lock. Be careful +// while accessing GPU state. +// static NV_STATUS _memorymulticastfabricCtrlAttachGpu ( + OBJGPU *pGpu, MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams ) { MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; - NV_STATUS status = NV_OK; - Subdevice *pSubdevice; - OBJGPU *pGpu; + NV_STATUS status; FABRIC_VASPACE *pFabricVAS; MEM_MULTICAST_FABRIC_GPU_INFO *pNode; + MEM_MULTICAST_FABRIC_GPU_INFO *pHead; + MEM_MULTICAST_FABRIC_REMOTE_GPU_INFO *pRemoteHead; CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); if (pParams->flags != 0) @@ -1319,16 +1743,6 @@ _memorymulticastfabricCtrlAttachGpu return NV_ERR_STATE_IN_USE; } - status = subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), - pParams->hSubdevice, &pSubdevice); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "Unable to query subdevice\n"); - return status; - } - - pGpu = GPU_RES_GET_GPU(pSubdevice); - if (RMCFG_FEATURE_PLATFORM_WINDOWS || gpuIsCCFeatureEnabled(pGpu) || IS_VIRTUAL(pGpu)) @@ -1338,8 +1752,8 @@ _memorymulticastfabricCtrlAttachGpu return NV_ERR_NOT_SUPPORTED; } - status = _memMulticastFabricGpuInfoAddUnderLock(pMemoryMulticastFabric, - pCallContext->pControlParams); + status = _memMulticastFabricGpuInfoAdd(pMemoryMulticastFabric, + pCallContext->pControlParams); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "Failed to populate GPU info\n"); @@ -1358,7 +1772,7 @@ _memorymulticastfabricCtrlAttachGpu } status = gpuFabricProbeGetFabricCliqueId(pGpu->pGpuFabricProbeInfoKernel, - &pNode->cliqueId); + &pNode->cliqueId); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, @@ -1366,6 +1780,23 @@ _memorymulticastfabricCtrlAttachGpu goto fail; } + pHead = listHead(&pMulticastFabricDesc->gpuInfoList); + pRemoteHead = multimapFirstItem(&pMulticastFabricDesc->remoteGpuInfoMap); + + if ((pHead != NULL) && (pHead->cliqueId != pNode->cliqueId)) + { + NV_PRINTF(LEVEL_ERROR, "Clique ID mismatch\n"); + status = NV_ERR_INVALID_DEVICE; + goto fail; + } + + if ((pRemoteHead != NULL) && (pRemoteHead->cliqueId != pNode->cliqueId)) + { + NV_PRINTF(LEVEL_ERROR, "Clique ID mismatch\n"); + status = NV_ERR_INVALID_DEVICE; + goto fail; + } + pFabricVAS = dynamicCast(pGpu->pFabricVAS, FABRIC_VASPACE); if (pFabricVAS == NULL) { @@ -1379,7 +1810,9 @@ _memorymulticastfabricCtrlAttachGpu if ((pMulticastFabricDesc->numAttachedGpus + 1) == pMulticastFabricDesc->numMaxGpus) { - status = _memMulticastFabricSendInbandRequestUnderLock(NULL, + NV_ASSERT(_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags)); + + status = _memMulticastFabricSendInbandRequest(pGpu, pMulticastFabricDesc, MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); if (status != NV_OK) @@ -1389,6 +1822,56 @@ _memorymulticastfabricCtrlAttachGpu goto fail; } } + // Invoke remote GPU attach event.. + else if (!_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags)) + { + NvU64 fmCaps; + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + NV00F1_CTRL_FABRIC_EVENT event; + + status = gpuFabricProbeGetfmCaps(pGpu->pGpuFabricProbeInfoKernel, + &fmCaps); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to query IMEX FM caps\n"); + goto fail; + } + + if (!(fmCaps & NVLINK_INBAND_FM_CAPS_MC_TEAM_SETUP_V2)) + { + NV_PRINTF(LEVEL_ERROR, "Remote attach is supported from V2+\n"); + status = NV_ERR_NOT_SUPPORTED; + goto fail; + } + + _memMulticastFabricInitAttachEvent(pNode->gpuProbeHandle, + pMulticastFabricDesc->inbandReqId, + pNode->cliqueId, + pMulticastFabricDesc->exportNodeId, + pMulticastFabricDesc->index, + &pMulticastFabricDesc->expUuid, + &event); + + pNode->attachEventId = event.id; + + status = fabricPostEventsV2(pFabric, &event, 1); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to notify IMEX daemon of import event\n"); + goto fail; + } + } + + // + // DO NOT FAIL after the call to fabricPostEventsV2 or + // _memMulticastFabricSendInbandRequest(). + // + // These functions are used to communicate with the external + // entities like FM/IMEX daemons. It is recommended that we + // do not fail the control call after these to avoid + // complicated cleanups. + // pMulticastFabricDesc->numAttachedGpus++; pMulticastFabricDesc->localAttachedGpusMask |= NVBIT32(pGpu->gpuInstance); @@ -1409,36 +1892,401 @@ memorymulticastfabricCtrlAttachGpu_IMPL NV00FD_CTRL_ATTACH_GPU_PARAMS *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); - NV_STATUS status = NV_OK; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + NV_STATUS status; + NvBool bLastAttach; + NvBool bLastAttachRecheck; + NvBool bGpuLockTaken = NV_FALSE; + Subdevice *pSubdevice; + OBJGPU *pGpu; + NvU32 gpuMask; + + status = subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + pParams->hSubdevice, &pSubdevice); + if (status == NV_ERR_OBJECT_NOT_FOUND) + status = NV_ERR_INVALID_DEVICE; + + if (status != NV_OK) + return status; + + pGpu = GPU_RES_GET_GPU(pSubdevice); + gpuMask = NVBIT(gpuGetInstance(pGpu)); + +retry: + // + // Find if I am the last attach. If yes, take a GPU lock to submit + // inband request. Otherwise, skip taking GPU lock. + // + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); + + bLastAttach = ((pMulticastFabricDesc->numMaxGpus - + pMulticastFabricDesc->numAttachedGpus) == 1); - fabricMulticastFabricOpsMutexAcquire(pFabric); + // Drop the lock to avoid lock inversion with the GPU lock... + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); - status = _memorymulticastfabricCtrlAttachGpu(pMemoryMulticastFabric, + if (bLastAttach && (gpuMask != 0)) + { + status = rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM, &gpuMask); + if (status != NV_OK) + { + NV_ASSERT(0); + return status; + } + + bGpuLockTaken = NV_TRUE; + } + + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); + + // + // Recheck to avoid TOCTOU, make sure bLastAttach state didn't change.. + // + // This is a deterministic check as once the GPU is attached to + // this object it can't be detached unless the object is destroyed. + // + bLastAttachRecheck = ((pMulticastFabricDesc->numMaxGpus - + pMulticastFabricDesc->numAttachedGpus) == 1); + + if (bLastAttachRecheck != bLastAttach) + { + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + + if (bGpuLockTaken) + { + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + bGpuLockTaken = NV_FALSE; + } + + goto retry; + } + + status = _memorymulticastfabricCtrlAttachGpu(pGpu, pMemoryMulticastFabric, pParams); - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + + if (bGpuLockTaken) + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + + return status; +} + +#ifdef NV00FD_CTRL_CMD_SET_FAILURE +static NV_STATUS +_memorymulticastfabricCtrlSetFailure +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_SET_FAILURE_PARAMS *pParams +) +{ + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvHandle hClient = pCallContext->pClient->hClient; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + + if (!rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_FABRIC_IMEX_MGMT) && + !rmclientIsAdminByHandle(hClient, pCallContext->secInfo.privLevel)) + return NV_ERR_INSUFFICIENT_PERMISSIONS; + + if (!_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags)) + { + NV_PRINTF(LEVEL_ERROR, "Only supported on prime MCLFA object\n"); + return NV_ERR_NOT_SUPPORTED; + } + + if ((pParams->status == NV_OK) || (pParams->status == NV_ERR_NOT_READY)) + return NV_ERR_INVALID_ARGUMENT; + + pMulticastFabricDesc->mcTeamStatus = pParams->status; + + // Notify the callers about the failure. + _memMulticastFabricDescriptorFlushClients(pMulticastFabricDesc); + + return NV_OK; +} + +NV_STATUS memorymulticastfabricCtrlSetFailure_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_SET_FAILURE_PARAMS *pParams +) +{ + NV_STATUS status; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); + + status = _memorymulticastfabricCtrlSetFailure(pMemoryMulticastFabric, + pParams); + + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + + return status; +} +#endif + +#ifdef NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU +// +// Note this function is not always called with the GPU lock. Be careful +// while accessing GPU state. +// +static NV_STATUS +_memorymulticastfabricCtrlAttachRemoteGpu +( + OBJGPU *pGpu, + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_GPU_INFO *pHead = + listHead(&pMulticastFabricDesc->gpuInfoList); + MEM_MULTICAST_FABRIC_REMOTE_GPU_INFO *pRemoteHead = + multimapFirstItem(&pMulticastFabricDesc->remoteGpuInfoMap); + MEM_MULTICAST_FABRIC_REMOTE_GPU_INFO *pNode; + MEM_MULTICAST_FABRIC_GPU_INFO *pIter; + MemMulticastFabricRemoteGpuInfoMapSubmap *pSubmap = NULL; + CALL_CONTEXT *pCallContext = resservGetTlsCallContext(); + NvHandle hClient = pCallContext->pClient->hClient; + NV00FD_CTRL_SET_FAILURE_PARAMS params; + NV_STATUS status; + + if (!rmclientIsCapableByHandle(hClient, NV_RM_CAP_SYS_FABRIC_IMEX_MGMT) && + !rmclientIsAdminByHandle(hClient, pCallContext->secInfo.privLevel)) + { + // Don't set failure as non-priv client can hit this failure too. + return NV_ERR_INSUFFICIENT_PERMISSIONS; + } + + if (!_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags)) + { + NV_PRINTF(LEVEL_ERROR, "Only supported on prime MCLFA object\n"); + status = NV_ERR_NOT_SUPPORTED; + goto fail; + } + + // Check if the Multicast FLA object has any additional slots for GPUs + if (pMulticastFabricDesc->numAttachedGpus == + pMulticastFabricDesc->numMaxGpus) + { + NV_PRINTF(LEVEL_ERROR, "Max no. of GPUs have already attached!\n"); + status = NV_ERR_INVALID_OPERATION; + goto fail; + } + + if ((pHead != NULL) && (pHead->cliqueId != pParams->cliqueId)) + { + NV_PRINTF(LEVEL_ERROR, "Clique ID mismatch\n"); + status = NV_ERR_INVALID_DEVICE; + goto fail; + } + + if ((pRemoteHead != NULL) && (pRemoteHead->cliqueId != pParams->cliqueId)) + { + NV_PRINTF(LEVEL_ERROR, "Clique ID mismatch\n"); + status = NV_ERR_INVALID_DEVICE; + goto fail; + } + + if (pParams->nodeId == NV_FABRIC_INVALID_NODE_ID) + { + NV_PRINTF(LEVEL_ERROR, "Invalid node ID\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto fail; + } + + for (pIter = listHead(&pMulticastFabricDesc->gpuInfoList); + pIter != NULL; + pIter = listNext(&pMulticastFabricDesc->gpuInfoList, pIter)) + { + if (pIter->gpuProbeHandle == pParams->gpuFabricProbeHandle) + { + NV_PRINTF(LEVEL_ERROR, "GPU is already attached\n"); + status = NV_ERR_INSERT_DUPLICATE_NAME; + goto fail; + } + } + + if (multimapFindSubmap(&pMulticastFabricDesc->remoteGpuInfoMap, + pParams->nodeId) == NULL) + { + pSubmap = multimapInsertSubmap(&pMulticastFabricDesc->remoteGpuInfoMap, + pParams->nodeId); + if (pSubmap == NULL) + { + status = NV_ERR_NO_MEMORY; + goto fail; + } + } + + pNode = multimapInsertItemNew(&pMulticastFabricDesc->remoteGpuInfoMap, + pParams->nodeId, + pParams->gpuFabricProbeHandle); + if (pNode == NULL) + { + // This could also fail due to NO_MEMORY error.. + NV_PRINTF(LEVEL_ERROR, "Failed to track remote GPU info\n"); + status = NV_ERR_INSERT_DUPLICATE_NAME; + goto cleanup_submap; + } + + portMemSet(pNode, 0, sizeof(*pNode)); + + pNode->key = pParams->key; + pNode->cliqueId = pParams->cliqueId; + + if ((pMulticastFabricDesc->numAttachedGpus + 1) + == pMulticastFabricDesc->numMaxGpus) + { + status = _memMulticastFabricSendInbandRequest(pGpu, + pMulticastFabricDesc, + MEM_MULTICAST_FABRIC_TEAM_SETUP_REQUEST); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Inband request Multicast Team Setup failed!\n"); + goto unlink_node; + } + } + + // + // DO NOT FAIL after the call to _memMulticastFabricSendInbandRequest(). + // + // This function is used to communicate with the external + // entities like FM daemon. It is recommended that we do not + // fail the control call after this to avoid complicated state + // cleanups. + // + + pMulticastFabricDesc->numAttachedGpus++; + + return NV_OK; + +unlink_node: + multimapRemoveItemByKey(&pMulticastFabricDesc->remoteGpuInfoMap, + pParams->nodeId, pParams->gpuFabricProbeHandle); + +cleanup_submap: + if (pSubmap != NULL) + multimapRemoveSubmap(&pMulticastFabricDesc->remoteGpuInfoMap, pSubmap); + +fail: + // + // NV_ERR_NOT_READY means the object is not ready, which is the initial + // state. Thus, in case any API returns NV_ERR_NOT_READY, overwrite it. + // + if (status == NV_ERR_NOT_READY) + status = NV_ERR_GENERIC; + + params.status = status; + + NV_ASSERT_OK(_memorymulticastfabricCtrlSetFailure(pMemoryMulticastFabric, + ¶ms)); + + return status; +} + +NV_STATUS +memorymulticastfabricCtrlAttachRemoteGpu_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric, + NV00FD_CTRL_ATTACH_REMOTE_GPU_PARAMS *pParams +) +{ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + NV_STATUS status; + OBJGPU *pGpu; + MEM_MULTICAST_FABRIC_GPU_INFO *pNode; + NvU32 gpuMask; + NvBool bLastAttach; + NvBool bLastAttachRecheck; + NvBool bGpuLockTaken = NV_FALSE; + +retry: + // + // Find if I am the last attach. If yes, take a GPU lock to submit + // inband request. Otherwise, skip taking GPU lock. + // + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); + + bLastAttach = ((pMulticastFabricDesc->numMaxGpus - + pMulticastFabricDesc->numAttachedGpus) == 1); + + pNode = listHead(&pMulticastFabricDesc->gpuInfoList); + pGpu = (pNode != NULL) ? pNode->pGpu : NULL; + gpuMask = (pGpu != NULL) ? NVBIT(gpuGetInstance(pGpu)) : 0; + + // Drop the lock to avoid lock inversion with the GPU lock... + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); + + if (bLastAttach && (gpuMask != 0)) + { + status = rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM, &gpuMask); + if (status != NV_OK) + { + NV_ASSERT(0); + return status; + } + + bGpuLockTaken = NV_TRUE; + } + + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); + + // + // Recheck to avoid TOCTOU, make sure bLastAttach state didn't change.. + // + // This is a deterministic check as once the GPU is attached to + // this object it can't be detached unless the object is destroyed. + // + bLastAttachRecheck = ((pMulticastFabricDesc->numMaxGpus - + pMulticastFabricDesc->numAttachedGpus) == 1); + + if (bLastAttachRecheck != bLastAttach) + { + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + + if (bGpuLockTaken) + { + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); + bGpuLockTaken = NV_FALSE; + } + + goto retry; + } + + status = _memorymulticastfabricCtrlAttachRemoteGpu(pGpu, + pMemoryMulticastFabric, + pParams); + + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); + + if (bGpuLockTaken) + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); return status; } +#endif static MEM_MULTICAST_FABRIC_GPU_INFO* _memorymulticastfabricGetAttchedGpuInfo ( MemoryMulticastFabric *pMemoryMulticastFabric, - NvHandle hSubdevice + Subdevice *pSubdevice ) { - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; MEM_MULTICAST_FABRIC_GPU_INFO *pNodeItr; - Subdevice *pSubdevice = NULL; - NV_STATUS status; - - status = subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), - hSubdevice, &pSubdevice); - if (status != NV_OK) - return NULL; for (pNodeItr = listHead(&pMulticastFabricDesc->gpuInfoList); pNodeItr != NULL; @@ -1451,29 +2299,42 @@ _memorymulticastfabricGetAttchedGpuInfo return NULL; } +// +// This function is called with RO pMulticastFabricDesc->pLock. Don't modify +// pMulticastFabricDesc. +// static NV_STATUS _memorymulticastfabricCtrlDetachMem ( + Subdevice *pSubdevice, MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_DETACH_MEM_PARAMS *pParams ) { - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; MEM_MULTICAST_FABRIC_GPU_INFO *pGpuInfo; NODE *pNode; MEMORY_DESCRIPTOR *pFabricMemDesc; FABRIC_VASPACE *pFabricVAS; NV_STATUS status; + OBJGPU *pGpu; + NvU32 gpuMask; if (pParams->flags != 0) return NV_ERR_INVALID_ARGUMENT; pGpuInfo = _memorymulticastfabricGetAttchedGpuInfo(pMemoryMulticastFabric, - pParams->hSubdevice); + pSubdevice); if (pGpuInfo == NULL) return NV_ERR_INVALID_DEVICE; + pGpu = pGpuInfo->pGpu; + gpuMask = NVBIT(gpuGetInstance(pGpu)); + + if (!rmGpuGroupLockIsOwner(0, GPU_LOCK_GRP_MASK, &gpuMask)) + return NV_ERR_INVALID_LOCK_STATE; + status = btreeSearch(pParams->offset, &pNode, pGpuInfo->pAttachMemInfoTree); if (status != NV_OK) return status; @@ -1499,15 +2360,51 @@ memorymulticastfabricCtrlDetachMem_IMPL NV00FD_CTRL_DETACH_MEM_PARAMS *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); - NV_STATUS status = NV_OK; + NV_STATUS status; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + Subdevice *pSubdevice; + NvU32 gpuMask; + + status = subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + pParams->hSubdevice, &pSubdevice); + if (status == NV_ERR_OBJECT_NOT_FOUND) + status = NV_ERR_INVALID_DEVICE; + + if (status != NV_OK) + return status; - fabricMulticastFabricOpsMutexAcquire(pFabric); + // + // TODO: Make this a per-GPU lock in future. For now both dup() and free() + // forces all GPU lock. + // + gpuMask = GPUS_LOCK_ALL; + + // + // Take per-GPU lock as we ensure source and destination devices are the + // same. + // + status = rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM, &gpuMask); + if (status != NV_OK) + { + NV_ASSERT(0); + return status; + } - status = _memorymulticastfabricCtrlDetachMem(pMemoryMulticastFabric, + // + // pMulticastFabricDesc->pLock read locking is sufficient as rest of the + // state in being modified is per-GPU, which is protected by the GPU lock. + // + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); + + status = _memorymulticastfabricCtrlDetachMem(pSubdevice, + pMemoryMulticastFabric, pParams); - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); + + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); return status; } @@ -1521,39 +2418,25 @@ _memorymulticastfabricValidatePhysMem MEMORY_DESCRIPTOR **ppPhysMemDesc ) { - RsResourceRef *pPhysmemRef; MEMORY_DESCRIPTOR *pPhysMemDesc; NvU64 physPageSize; NV_STATUS status; Memory *pMemory; - status = serverutilGetResourceRef( - RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric), - hPhysMem, &pPhysmemRef); + status = memGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + hPhysMem, &pMemory); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, - "Failed to get resource in resserv for physmem handle\n"); - + NV_PRINTF(LEVEL_ERROR, "Invalid object handle passed\n"); return status; } - pMemory = dynamicCast(pPhysmemRef->pResource, Memory); - if (pMemory == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); - return NV_ERR_INVALID_OBJECT_HANDLE; - } - pPhysMemDesc = pMemory->pMemDesc; - if (pPhysMemDesc == NULL) - { - NV_PRINTF(LEVEL_ERROR, "Invalid memory handle\n"); - return NV_ERR_INVALID_OBJECT_HANDLE; - } - if (memdescGetAddressSpace(pPhysMemDesc) != ADDR_FBMEM || - (pAttachedGpu != pPhysMemDesc->pGpu)) + if ((pAttachedGpu != pPhysMemDesc->pGpu) || + !memmgrIsMemDescSupportedByFla_HAL(pAttachedGpu, + GPU_GET_MEMORY_MANAGER(pAttachedGpu), + pPhysMemDesc)) { NV_PRINTF(LEVEL_ERROR, "Invalid physmem handle passed\n"); @@ -1574,14 +2457,19 @@ _memorymulticastfabricValidatePhysMem return NV_OK; } +// +// This function is called with RO pMulticastFabricDesc->pLock. Don't modify +// pMulticastFabricDesc. +// static NV_STATUS _memorymulticastfabricCtrlAttachMem ( + Subdevice *pSubdevice, MemoryMulticastFabric *pMemoryMulticastFabric, NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams ) { - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = \ + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; MEM_MULTICAST_FABRIC_GPU_INFO *pGpuInfo; NV_STATUS status; @@ -1591,15 +2479,23 @@ _memorymulticastfabricCtrlAttachMem RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); FABRIC_VASPACE *pFabricVAS; MEM_MULTICAST_FABRIC_ATTACH_MEM_INFO_NODE *pNode; + OBJGPU *pGpu; + NvU32 gpuMask; if (pParams->flags != 0) return NV_ERR_INVALID_ARGUMENT; pGpuInfo = _memorymulticastfabricGetAttchedGpuInfo(pMemoryMulticastFabric, - pParams->hSubdevice); + pSubdevice); if (pGpuInfo == NULL) return NV_ERR_INVALID_DEVICE; + pGpu = pGpuInfo->pGpu; + gpuMask = NVBIT(gpuGetInstance(pGpu)); + + if (!rmGpuGroupLockIsOwner(0, GPU_LOCK_GRP_MASK, &gpuMask)) + return NV_ERR_INVALID_LOCK_STATE; + status = _memorymulticastfabricValidatePhysMem(pMemoryMulticastFabric, pParams->hMemory, pGpuInfo->pGpu, @@ -1686,15 +2582,51 @@ memorymulticastfabricCtrlAttachMem_IMPL NV00FD_CTRL_ATTACH_MEM_PARAMS *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); - NV_STATUS status = NV_OK; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + NV_STATUS status; + Subdevice *pSubdevice; + NvU32 gpuMask; + + status = subdeviceGetByHandle(RES_GET_CLIENT(pMemoryMulticastFabric), + pParams->hSubdevice, &pSubdevice); + if (status == NV_ERR_OBJECT_NOT_FOUND) + status = NV_ERR_INVALID_DEVICE; + + if (status != NV_OK) + return status; - fabricMulticastFabricOpsMutexAcquire(pFabric); + // + // TODO: Make this a per-GPU lock in future. For now both dup() and free() + // forces all GPU lock. + // + gpuMask = GPUS_LOCK_ALL; + + // + // Take per-GPU lock as we ensure source and destination devices are the + // same. + // + status = rmGpuGroupLockAcquire(0, GPU_LOCK_GRP_MASK, GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_MEM, &gpuMask); + if (status != NV_OK) + { + NV_ASSERT(0); + return status; + } + + // + // pMulticastFabricDesc->pLock read locking is sufficient as rest of the + // state in being modified is per-GPU, which is protected by the GPU lock. + // + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); - status = _memorymulticastfabricCtrlAttachMem(pMemoryMulticastFabric, + status = _memorymulticastfabricCtrlAttachMem(pSubdevice, + pMemoryMulticastFabric, pParams); - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); + + rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE); return status; } @@ -1705,13 +2637,19 @@ memorymulticastfabricDestruct_IMPL MemoryMulticastFabric *pMemoryMulticastFabric ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); + + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); + + memDestructCommon(pMemory); - fabricMulticastFabricOpsMutexAcquire(pFabric); + _memMulticastFabricDescriptorDequeueWait(pMulticastFabricDesc, pMemory); - _memorymulticastfabricDestructUnderLock(pMemoryMulticastFabric); + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); - fabricMulticastFabricOpsMutexRelease(pFabric); + _memMulticastFabricDescriptorFree(pMulticastFabricDesc); } NvBool @@ -1732,20 +2670,23 @@ memorymulticastfabricCopyConstruct_IMPL ) { MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); - - fabricMulticastFabricOpsMutexAcquire(pFabric); MemoryMulticastFabric *pSourceMemoryMulticastFabric = dynamicCast(pParams->pSrcRef->pResource, MemoryMulticastFabric); pMulticastFabricDesc = pSourceMemoryMulticastFabric->pMulticastFabricDesc; + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); + pMulticastFabricDesc->refCount++; pMemoryMulticastFabric->pMulticastFabricDesc = pMulticastFabricDesc; - fabricMulticastFabricOpsMutexRelease(pFabric); + pMemoryMulticastFabric->expNodeId = pMulticastFabricDesc->exportNodeId; + pMemoryMulticastFabric->bImported = + !_memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags); + + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); return NV_OK; } @@ -1777,15 +2718,17 @@ memorymulticastfabricCtrlGetInfo_IMPL NV00FD_CTRL_GET_INFO_PARAMS *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); NV_STATUS status = NV_OK; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; - fabricMulticastFabricOpsMutexAcquire(pFabric); + pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); status = _memorymulticastfabricCtrlGetInfo(pMemoryMulticastFabric, pParams); - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); return status; } @@ -1797,19 +2740,18 @@ memorymulticastfabricIsReady_IMPL NvBool bCopyConstructorContext ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; NV_STATUS mcTeamStatus; - fabricMulticastFabricOpsMutexAcquire(pFabric); + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); - pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; mcTeamStatus = pMulticastFabricDesc->mcTeamStatus; if (bCopyConstructorContext && (mcTeamStatus == NV_ERR_NOT_READY)) { - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); return NV_OK; } @@ -1823,7 +2765,7 @@ memorymulticastfabricIsReady_IMPL NVOS32_MEM_TAG_NONE, NULL)); } - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); return mcTeamStatus; } @@ -1838,11 +2780,12 @@ _memorymulticastfabricCtrlRegisterEvent Memory *pMemory = staticCast(pMemoryMulticastFabric, Memory); NvHandle hClient = RES_GET_CLIENT_HANDLE(pMemoryMulticastFabric); - return _memMulticastFabricDescriptorEnqueueWaitUnderLock(hClient, - pMemoryMulticastFabric->pMulticastFabricDesc, - pParams->pOsEvent, pMemory); + return _memMulticastFabricDescriptorEnqueueWait(hClient, + pMemoryMulticastFabric->pMulticastFabricDesc, + pParams->pOsEvent, pMemory); } + NV_STATUS memorymulticastfabricCtrlRegisterEvent_IMPL ( @@ -1850,15 +2793,16 @@ memorymulticastfabricCtrlRegisterEvent_IMPL NV00FD_CTRL_REGISTER_EVENT_PARAMS *pParams ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); - NV_STATUS status = NV_OK; + NV_STATUS status; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; - fabricMulticastFabricOpsMutexAcquire(pFabric); + portSyncRwLockAcquireWrite(pMulticastFabricDesc->pLock); status = _memorymulticastfabricCtrlRegisterEvent(pMemoryMulticastFabric, pParams); - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseWrite(pMulticastFabricDesc->pLock); return status; } @@ -1874,6 +2818,12 @@ memorymulticastfabricControl_IMPL NV_STATUS status = NV_OK; if ( +#ifdef NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU + (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_REMOTE_GPU) && +#endif +#ifdef NV00FD_CTRL_CMD_SET_FAILURE + (pParams->cmd != NV00FD_CTRL_CMD_SET_FAILURE) && +#endif (pParams->cmd != NV00FD_CTRL_CMD_ATTACH_GPU)) { status = memorymulticastfabricIsReady(pMemoryMulticastFabric, @@ -1920,18 +2870,15 @@ memorymulticastfabricIsExportAllowed_IMPL MemoryMulticastFabric *pMemoryMulticastFabric ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; NvBool bAllowed; - fabricMulticastFabricOpsMutexAcquire(pFabric); + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); - pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; - - bAllowed = (pMulticastFabricDesc != NULL) && - _memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags); + bAllowed = _memMulticastFabricIsPrime(pMulticastFabricDesc->allocFlags); - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); return bAllowed; } @@ -1943,17 +2890,15 @@ memorymulticastfabricIsGpuMapAllowed_IMPL OBJGPU *pGpu ) { - Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); - MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc; NvU32 localAttachedGpusMask; + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; - fabricMulticastFabricOpsMutexAcquire(pFabric); - - pMulticastFabricDesc = pMemoryMulticastFabric->pMulticastFabricDesc; + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); localAttachedGpusMask = pMulticastFabricDesc->localAttachedGpusMask; - fabricMulticastFabricOpsMutexRelease(pFabric); + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); return ((localAttachedGpusMask & NVBIT32(pGpu->gpuInstance)) != 0U); } @@ -1971,3 +2916,23 @@ memorymulticastfabricGetMapAddrSpace_IMPL return NV_OK; } +void +memorymulticastfabricRemoveFromCache_IMPL +( + MemoryMulticastFabric *pMemoryMulticastFabric +) +{ + Fabric *pFabric = SYS_GET_FABRIC(SYS_GET_INSTANCE()); + MEM_MULTICAST_FABRIC_DESCRIPTOR *pMulticastFabricDesc = + pMemoryMulticastFabric->pMulticastFabricDesc; + + if (!pMemoryMulticastFabric->bImported) + return; + + portSyncRwLockAcquireRead(pMulticastFabricDesc->pLock); + + fabricImportCacheDelete(pFabric, &pMulticastFabricDesc->expUuid, + pMulticastFabricDesc->cacheKey); + + portSyncRwLockReleaseRead(pMulticastFabricDesc->pLock); +} diff --git a/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c b/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c index 90283638d0..593543dce6 100644 --- a/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/os_desc_mem.c @@ -27,11 +27,11 @@ #include "rmapi/mapping_list.h" #include "gpu/mem_mgr/mem_desc.h" #include "os/os.h" -#include "gpu/device/device.h" #include "vgpu/rpc.h" #include "mem_mgr/mem.h" #include "gpu/mem_mgr/mem_mgr.h" #include "deprecated/rmapi_deprecated.h" +#include "vgpu/vgpu_util.h" #include "class/cl0071.h" // NV01_MEMORY_SYSTEM_OS_DESCRIPTOR @@ -171,6 +171,17 @@ osdescConstruct_IMPL if (status == NV_OK) pMemory->bRpcAlloc = NV_TRUE; + if (IS_VIRTUAL_WITH_SRIOV(pGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pGpu) && + (pMemDesc->_addressSpace == ADDR_SYSMEM) && + !(pMemDesc->_flags & MEMDESC_FLAGS_CPU_ONLY)) + { + status = vgpuUpdateSysmemPfnBitMap(pGpu, pMemDesc, NV_TRUE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_INFO, "Failed to update sysmem PFN bitmap\n"); + } + } } } diff --git a/src/nvidia/src/kernel/mem_mgr/phys_mem.c b/src/nvidia/src/kernel/mem_mgr/phys_mem.c index 0bec14b984..64abe3899e 100644 --- a/src/nvidia/src/kernel/mem_mgr/phys_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/phys_mem.c @@ -32,7 +32,6 @@ #include "gpu/mem_mgr/heap.h" #include "gpu/mem_sys/kern_mem_sys.h" #include "gpu/bus/kern_bus.h" -#include "gpu/device/device.h" #include "rmapi/client.h" #include "virtualization/hypervisor/hypervisor.h" diff --git a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c index 93133ab73e..321037d20b 100644 --- a/src/nvidia/src/kernel/mem_mgr/pool_alloc.c +++ b/src/nvidia/src/kernel/mem_mgr/pool_alloc.c @@ -1,4 +1,4 @@ -/* + /* * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * @@ -193,7 +193,7 @@ struct RM_POOL_ALLOC_MEM_RESERVE_INFO * pool. * * @param[in] pCtx Context for upstream allocator. - * @param[in] pageSize Only for debugging. + * @param[in] pageSize Page size to use when allocating from PMA * @param[in] pPage Output page handle from upstream. * * @return NV_STATUS @@ -203,20 +203,20 @@ allocUpstreamTopPool ( void *pCtx, NvU64 pageSize, + NvU64 numPages, POOLALLOC_HANDLE *pPage ) { PMA_ALLOCATION_OPTIONS allocOptions = {0}; RM_POOL_ALLOC_MEM_RESERVE_INFO *pMemReserveInfo; - NV_STATUS status; + NvU64 i, pageBegin; + NV_STATUS status; NV_ASSERT_OR_RETURN(NULL != pCtx, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(NULL != pPage, NV_ERR_INVALID_ARGUMENT); - // TODO: Replace the direct call to PMA with function pointer. pMemReserveInfo = (RM_POOL_ALLOC_MEM_RESERVE_INFO *)pCtx; - allocOptions.flags = PMA_ALLOCATE_PINNED | PMA_ALLOCATE_PERSISTENT | - PMA_ALLOCATE_CONTIGUOUS; + allocOptions.flags = PMA_ALLOCATE_PINNED | PMA_ALLOCATE_PERSISTENT; if (pMemReserveInfo->bSkipScrub) { @@ -228,18 +228,54 @@ allocUpstreamTopPool allocOptions.flags |= PMA_ALLOCATE_PROTECTED_REGION; } - status = pmaAllocatePages(pMemReserveInfo->pPma, - pMemReserveInfo->pmaChunkSize/PMA_CHUNK_SIZE_64K, - PMA_CHUNK_SIZE_64K, - &allocOptions, - &pPage->address); - if (status != NV_OK) + // + // Some tests fail page table and directory allocation when close to all FB is allocated if we allocate contiguously. + // For now, we're special-casing this supported pageSize and allocating the 64K pages discontigously. + // TODO: Unify the codepaths so that all pages allocated discontiguously (not currently supported by PMA) + // + if (pageSize == PMA_CHUNK_SIZE_64K) { + NvU64 *pPageStore = portMemAllocNonPaged(sizeof(NvU64) * numPages); + NV_STATUS status = NV_OK; + NV_ASSERT_OK_OR_GOTO(status, + pmaAllocatePages(pMemReserveInfo->pPma, + numPages, + pageSize, + &allocOptions, + pPageStore), + free_mem); + + for (i = 0; i < numPages; i++) + { + pPage[i].address = pPageStore[i]; + pPage[i].pMetadata = NULL; + } +free_mem: + portMemFree(pPageStore); return status; } - pPage->pMetadata = NULL; + allocOptions.flags |= PMA_ALLOCATE_CONTIGUOUS; + + for (i = 0; i < numPages; i++) + { + NV_ASSERT_OK_OR_GOTO(status, pmaAllocatePages(pMemReserveInfo->pPma, + pageSize / PMA_CHUNK_SIZE_64K, + PMA_CHUNK_SIZE_64K, + &allocOptions, + &pageBegin), err); + pPage[i].address = pageBegin; + pPage[i].pMetadata = NULL; + } + return NV_OK; +err: + for (;i > 0; i--) + { + NvU32 flags = pMemReserveInfo->bSkipScrub ? PMA_FREE_SKIP_SCRUB : 0; + pmaFreePages(pMemReserveInfo->pPma, &pPage[i - 1].address, 1, + pageSize, flags); + } return status; } @@ -258,17 +294,28 @@ allocUpstreamLowerPools ( void *pCtx, NvU64 pageSize, + NvU64 numPages, POOLALLOC_HANDLE *pPage ) { NV_STATUS status; + NvU64 i; NV_ASSERT_OR_RETURN(NULL != pCtx, NV_ERR_INVALID_ARGUMENT); NV_ASSERT_OR_RETURN(NULL != pPage, NV_ERR_INVALID_ARGUMENT); - status = poolAllocate((POOLALLOC *)pCtx, pPage); - NV_ASSERT_OR_RETURN(status == NV_OK, status); - + for(i = 0; i < numPages; i++) + { + NV_ASSERT_OK_OR_GOTO(status, + poolAllocate((POOLALLOC *)pCtx, &pPage[i]), + cleanup); + } + return NV_OK; +cleanup: + for(;i > 0; i--) + { + poolFree((POOLALLOC *)pCtx, &pPage[i-1]); + } return status; } @@ -441,7 +488,7 @@ rmMemPoolSetup // of reserving memory for page tables required for mapping GR context buffers // in the channel vaspace. See bug 200590870 and 200614517. // - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM) + if (RMCFG_FEATURE_PLATFORM_WINDOWS) { flags = FLD_SET_DRF(_RMPOOL, _FLAGS, _AUTO_POPULATE, _ENABLE, flags); } diff --git a/src/nvidia/src/kernel/mem_mgr/standard_mem.c b/src/nvidia/src/kernel/mem_mgr/standard_mem.c index cca4241c94..9ec50bb564 100644 --- a/src/nvidia/src/kernel/mem_mgr/standard_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/standard_mem.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -26,7 +26,6 @@ #include "vgpu/rpc.h" #include "rmapi/client.h" #include "gpu/mem_mgr/mem_mgr.h" -#include "gpu/device/device.h" #include "virtualization/hypervisor/hypervisor.h" #include "resserv/rs_server.h" #include "rmapi/rs_utils.h" diff --git a/src/nvidia/src/kernel/mem_mgr/system_mem.c b/src/nvidia/src/kernel/mem_mgr/system_mem.c index 956cc98af3..a9009f0e84 100644 --- a/src/nvidia/src/kernel/mem_mgr/system_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/system_mem.c @@ -32,6 +32,7 @@ #include "deprecated/rmapi_deprecated.h" #include "gpu/mem_mgr/mem_utils.h" #include "core/system.h" +#include "ctrl/ctrl0000/ctrl0000gpu.h" #include "gpu/mem_sys/kern_mem_sys.h" @@ -222,18 +223,24 @@ sysmemConstruct_IMPL if (FLD_TEST_DRF(OS32, _ATTR2, _FIXED_NUMA_NODE_ID, _YES, pAllocData->attr2)) { - // - // TODO: Add validation of NUMA Node ID. Bug: 3802992 - // Invalid ID criteria: - // * NUMA is not supported on this platform - // * NUMA Node ID is of GPU - // * When memory is protected, if requested in unprotected memory - // - // Allow kernel to validate the following: - // * NUMA Node ID is not in range of [0,MAX_NUMANODES) - // * NUMA Node has no memory present - // * NUMA Node has no free memory - // + + if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_IN_UNPROTECTED_MEMORY)) + { + NV_PRINTF(LEVEL_ERROR, "Cannot specify NUMA node in unprotected memory.\n"); + memdescDestroy(pMemDesc); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto failed; + } + + if ((pGpu->cpuNumaNodeId != NV0000_CTRL_NO_NUMA_NODE) && + (pAllocData->numaNode != pGpu->cpuNumaNodeId)) + { + NV_PRINTF(LEVEL_ERROR, "NUMA node mismatch. Requested node: %u CPU node: %u\n", + pAllocData->numaNode, pGpu->cpuNumaNodeId); + memdescDestroy(pMemDesc); + rmStatus = NV_ERR_INVALID_ARGUMENT; + goto failed; + } memdescSetNumaNode(pMemDesc, pAllocData->numaNode); // diff --git a/src/nvidia/src/kernel/mem_mgr/video_mem.c b/src/nvidia/src/kernel/mem_mgr/video_mem.c index 047474d2a6..476498cd1f 100644 --- a/src/nvidia/src/kernel/mem_mgr/video_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/video_mem.c @@ -32,9 +32,11 @@ #include "core/locks.h" #include "kernel/gpu/rc/kernel_rc.h" #include "diagnostics/gpu_acct.h" +#include "gpu/device/device.h" #include "Nvcm.h" #include "gpu/bus/third_party_p2p.h" #include "gpu/bus/kern_bus.h" +#include "platform/sli/sli.h" #include "class/cl0040.h" // NV01_MEMORY_LOCAL_USER @@ -159,11 +161,6 @@ _vidmemPmaAllocate pAllocData->attr); } - // LOCK: acquire device lock - status = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_MEM_PMA); - NV_ASSERT_OR_RETURN(status == NV_OK, status); - NV_PRINTF(LEVEL_INFO, "PMA input\n"); NV_PRINTF(LEVEL_INFO, " Owner: 0x%x\n", pAllocData->owner); NV_PRINTF(LEVEL_INFO, " hMemory: 0x%x\n", pAllocRequest->hMemory); @@ -208,16 +205,11 @@ _vidmemPmaAllocate // Bug:2451834, gpuCheckPageRetirementSupport should not be called outside // RM lock. // - if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT) && - gpuCheckPageRetirementSupport_HAL(pGpu) && - FLD_TEST_DRF(OS32, _ATTR2, _BLACKLIST, _OFF, pAllocData->attr2)) + if (FLD_TEST_DRF(OS32, _ATTR2, _BLACKLIST, _OFF, pAllocData->attr2)) { allocOptions.flags |= PMA_ALLOCATE_TURN_BLACKLIST_OFF; } - // UNLOCK: release device lock - rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL); - NV_ASSERT_OR_RETURN(NV_OK == status, status); // RM allocations are always pinned. @@ -567,6 +559,14 @@ vidmemConstruct_IMPL bUpdatePteKind = NV_TRUE; } + if (FLD_TEST_DRF(OS32, _ATTR, _PHYSICALITY, _DEFAULT, pAllocData->attr)) + { + pAllocData->attr = + FLD_SET_DRF_NUM(OS32, _ATTR, _PHYSICALITY, + pDevice->defaultVidmemPhysicalityOverride, + pAllocData->attr); + } + NV_CHECK_OK_OR_RETURN(LEVEL_WARNING, stdmemValidateParams(pGpu, hClient, pAllocData)); NV_CHECK_OR_RETURN(LEVEL_WARNING, DRF_VAL(OS32, _ATTR, _LOCATION, pAllocData->attr) == NVOS32_ATTR_LOCATION_VIDMEM && @@ -584,6 +584,9 @@ vidmemConstruct_IMPL pHeap = vidmemGetHeap(pGpu, pDevice, bSubheap, bRsvdHeap); NV_CHECK_OR_RETURN(LEVEL_INFO, pHeap != NULL, NV_ERR_INVALID_STATE); + attr = pAllocData->attr; + attr2 = pAllocData->attr2; + if (gpuIsCCorApmFeatureEnabled(pGpu) && !FLD_TEST_DRF(OS32, _ATTR2, _MEMORY_PROTECTION, _UNPROTECTED, pAllocData->attr2)) { @@ -626,7 +629,7 @@ vidmemConstruct_IMPL // Scrub-on-free is not supported by heap. Make sure clients don't get unscrubbed allocations NV_CHECK_OR_RETURN(LEVEL_WARNING, - !memmgrIsScrubOnFreeEnabled(pMemoryManager) || bIsPmaAlloc || bSubheap, + !memmgrIsScrubOnFreeEnabled(pMemoryManager) || bIsPmaAlloc || bSubheap || bRsvdHeap, NV_ERR_INVALID_STATE); // Get the allocation from PMA if enabled. @@ -903,6 +906,13 @@ vidmemConstruct_IMPL // XXX: This is a hack for now. No Hw resources are assumed to be used in the call. // The host is only requested to make an alias to the allocated heap. + // + // Heap alloc may allocate non-contiguous pages when it is not able to + // find contiguous pages. Replace this field before passing to RPC. + // + attr = (pAllocData->attr & DRF_SHIFTMASK(NVOS32_ATTR_PHYSICALITY)) | + (attr & ~DRF_SHIFTMASK(NVOS32_ATTR_PHYSICALITY)); + if (!IS_GSP_CLIENT(pGpu)) { NV_RM_RPC_ALLOC_VIDMEM(pGpu, @@ -1293,6 +1303,11 @@ vidmemAllocResources } bAllocedMemory = NV_TRUE; + + if (pVidHeapAlloc->flags & NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM) + { + memdescSetFlag(pMemDesc, MEMDESC_FLAGS_PRESERVE_CONTENT_ON_SUSPEND, NV_TRUE); + } } if (!bIsPmaOwned && (pVidHeapAlloc->type != NVOS32_TYPE_PMA)) diff --git a/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c b/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c index 6fed7cfa53..7d02f01159 100644 --- a/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c +++ b/src/nvidia/src/kernel/mem_mgr/virt_mem_range.c @@ -25,7 +25,6 @@ #include "mem_mgr/virt_mem_range.h" #include "os/os.h" #include "vgpu/rpc.h" -#include "gpu/device/device.h" #include "gpu/mem_mgr/vaspace_api.h" #include "gpu/mmu/kern_gmmu.h" #include "class/cl0070.h" diff --git a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c index 8c5c52cb17..ca178c9ce1 100644 --- a/src/nvidia/src/kernel/mem_mgr/virtual_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/virtual_mem.c @@ -31,12 +31,14 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "core/locks.h" #include "kernel/gpu/rc/kernel_rc.h" +#include "gpu/device/device.h" #include "Nvcm.h" #include "gpu/mem_mgr/vaspace_api.h" #include "gpu/mem_mgr/mem_utils.h" #include "gpu/bus/kern_bus.h" #include "gpu/bus/p2p_api.h" #include "mem_mgr/gpu_vaspace.h" +#include "platform/sli/sli.h" #include "class/cl0070.h" // NV01_MEMORY_VIRTUAL #include "class/cl50a0.h" // NV50_MEMORY_VIRTUAL @@ -350,6 +352,9 @@ virtmemConstruct_IMPL stdmemDumpInputAllocParams(pAllocData, pCallContext); + attr = pAllocData->attr; + attr2 = pAllocData->attr2; + pAllocRequest->classNum = NV50_MEMORY_VIRTUAL; pAllocRequest->pUserParams = pAllocData; pAllocRequest->hMemory = pResourceRef->hResource; @@ -1222,9 +1227,6 @@ virtmemMapTo_IMPL Memory *pSrcMemory = dynamicCast(pMemoryRef->pResource, Memory); NvU32 tgtAddressSpace = ADDR_UNKNOWN; - - NvBool bDmaMapNeeded = pParams->bDmaMapNeeded; - NvBool bDmaMapped = NV_FALSE; NvBool bDmaMappingRegistered = NV_FALSE; NvBool bFlaMapping = pParams->bFlaMapping; NvBool bIsIndirectPeer = NV_FALSE; @@ -1234,6 +1236,7 @@ virtmemMapTo_IMPL GPU_GET_KERNEL_BUS(pGpu), pSrcGpu, GPU_GET_KERNEL_BUS(pSrcGpu))); + NvBool bKernelMappingRequired = FLD_TEST_DRF(OS46, _FLAGS, _KERNEL_MAPPING, _ENABLE, flags); // // Allow unicast on NV01_MEMORY_VIRTUAL object, but maintain the broadcast @@ -1298,57 +1301,49 @@ virtmemMapTo_IMPL if (gpumgrCheckIndirectPeer(pGpu, pSrcGpu)) bIsIndirectPeer = NV_TRUE; - - // IOMMU mapping not needed for GPU P2P accesses on FB pages. - bDmaMapNeeded = NV_FALSE; - } - - if ( - (tgtAddressSpace == ADDR_FABRIC_MC) || - (tgtAddressSpace == ADDR_FABRIC_V2)) - { - // IOMMU mapping not needed for GPU P2P accesses on FB pages. - bDmaMapNeeded = NV_FALSE; } // Different cases for vidmem & system memory/fabric memory. bIsSysmem = (tgtAddressSpace == ADDR_SYSMEM); bIsSysmem = bIsSysmem || (tgtAddressSpace == ADDR_EGM); - if (bIsSysmem || - (tgtAddressSpace == ADDR_FABRIC_MC) || - (tgtAddressSpace == ADDR_FABRIC_V2)) + // + // Create a MEMORY_DESCRIPTOR describing this region of the memory + // alloc in question + // + status = memdescCreateSubMem(&pDmaMappingInfo->pMemDesc, pSrcMemDesc, pGpu, offset, length); + if (status != NV_OK) + goto done; + + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) + memdescSetFlag(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu), + MEMDESC_FLAGS_ENCRYPTED, + bEncrypted); + SLI_LOOP_END + + if (FLD_TEST_DRF(OS46, _FLAGS, _PAGE_KIND, _VIRTUAL, flags)) { - // - // Create a MEMORY_DESCRIPTOR describing this region of the memory - // alloc in question - // - status = memdescCreateSubMem(&pDmaMappingInfo->pMemDesc, pSrcMemDesc, pGpu, offset, length); - if (status != NV_OK) - goto done; - *pParams->ppMemDesc = pDmaMappingInfo->pMemDesc; + NvU32 kind = memdescGetPteKind(pMemory->pMemDesc); - // - // If system memory does not support compression, the virtual kind is compressible, - // and being mapped into system memory fallback to using the uncompressed kind. - // - if (FLD_TEST_DRF(OS46, _FLAGS, _PAGE_KIND, _VIRTUAL, flags) && - (tgtAddressSpace == ADDR_SYSMEM) && - (!memmgrComprSupported(pMemoryManager, ADDR_SYSMEM))) - { - NvU32 kind = memdescGetPteKind(pMemory->pMemDesc); - NvU32 updatedKind = memmgrGetUncompressedKind_HAL(pGpu, pMemoryManager, kind, 0); - NvU32 dmaKind = memdescGetPteKind(pDmaMappingInfo->pMemDesc); + NV_ASSERT(memdescGetFlag(pMemory->pMemDesc, MEMDESC_FLAGS_SET_KIND)); - if (dmaKind != updatedKind) - { - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY); - NV_ASSERT(memdescGetFlag(memdescGetMemDescFromGpu(pMemory->pMemDesc, pGpu), MEMDESC_FLAGS_SET_KIND)); - memdescSetPteKind(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu), updatedKind); - SLI_LOOP_END; - } + SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY); + if (tgtAddressSpace == ADDR_SYSMEM && !memmgrComprSupported(pMemoryManager, ADDR_SYSMEM)) + { + // + // If system memory does not support compression, the virtual kind is compressible, + // and being mapped into system memory fallback to using the uncompressed kind. + // + kind = memmgrGetUncompressedKind_HAL(pGpu, pMemoryManager, kind, 0); } + memdescSetPteKind(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu), kind); + SLI_LOOP_END; + } + if (bIsSysmem || + (tgtAddressSpace == ADDR_FABRIC_MC) || + (tgtAddressSpace == ADDR_FABRIC_V2)) + { // if GPUs are indirect peers, create TCE mappings if (bIsIndirectPeer) { @@ -1365,28 +1360,6 @@ virtmemMapTo_IMPL goto done; } } - else if (bDmaMapNeeded) - { - status = osDmaMapPages(pGpu->pOsGpuInfo, pDmaMappingInfo->pMemDesc); - if ((status != NV_OK) && (status != NV_ERR_NOT_SUPPORTED)) - { - NV_PRINTF(LEVEL_ERROR, "DMA map pages failed for requested GPU!\n"); - goto done; - } - // - // Some operating systems return NV_ERR_NOT_SUPPORTED. Assign NV_OK to - // status since we return status from this function and NV_ERR_NOT_SUPPORTED - // may be considered as failure in calling function. - // - status = NV_OK; - bDmaMapped = NV_TRUE; - } - - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY) - memdescSetFlag(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu), - MEMDESC_FLAGS_ENCRYPTED, - bEncrypted); - SLI_LOOP_END // Monolithic CPU RM or SPLIT_VAS_MGMT if (!pMemory->bRpcAlloc || gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) @@ -1410,7 +1383,7 @@ virtmemMapTo_IMPL bDmaMappingRegistered = NV_TRUE; // If a kernel mapping has been requested, create one - if (DRF_VAL(OS46, _FLAGS, _KERNEL_MAPPING, flags) == NVOS46_FLAGS_KERNEL_MAPPING_ENABLE) + if (bKernelMappingRequired) { status = memdescMapOld(pDmaMappingInfo->pMemDesc, 0, @@ -1428,33 +1401,6 @@ virtmemMapTo_IMPL } else if (tgtAddressSpace == ADDR_FBMEM) { - // - // Create a MEMORY_DESCRIPTOR describing this region of the memory alloc - // in question - // - status = memdescCreateSubMem(&pDmaMappingInfo->pMemDesc, pSrcMemDesc, pGpu, offset, length); - if (status != NV_OK) - goto done; - *pParams->ppMemDesc = pDmaMappingInfo->pMemDesc; - - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY); - memdescSetFlag(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu), - MEMDESC_FLAGS_ENCRYPTED, - bEncrypted); - SLI_LOOP_END; - - if (FLD_TEST_DRF(OS46, _FLAGS, _PAGE_KIND, _VIRTUAL, flags)) - { - // - // Want to make sure that the virtual kind was set beforehand - // - SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY | SLI_LOOP_FLAGS_IGNORE_REENTRANCY); - NV_ASSERT(memdescGetFlag(memdescGetMemDescFromGpu(pMemory->pMemDesc, pGpu), MEMDESC_FLAGS_SET_KIND)); - memdescSetPteKind(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu), - memdescGetPteKind(pMemory->pMemDesc)); - SLI_LOOP_END; - } - pDmaMappingInfo->DmaOffset = *pDmaOffset; // in case this is 'in' // Monolithic CPU RM or SPLIT_VAS_MGMT @@ -1478,7 +1424,7 @@ virtmemMapTo_IMPL bDmaMappingRegistered = NV_TRUE; - if (DRF_VAL(OS46, _FLAGS, _KERNEL_MAPPING, flags) == NVOS46_FLAGS_KERNEL_MAPPING_ENABLE) + if (bKernelMappingRequired) { status = _virtmemAllocKernelMapping(pGpu, pVas, pDmaMappingInfo, offset, length, pSrcMemory); if (status != NV_OK) @@ -1546,7 +1492,7 @@ virtmemMapTo_IMPL if (tgtAddressSpace == ADDR_SYSMEM) { // If a kernel mapping has been requested, create one - if (DRF_VAL(OS46, _FLAGS, _KERNEL_MAPPING, flags) == NVOS46_FLAGS_KERNEL_MAPPING_ENABLE) + if (bKernelMappingRequired) { status = memdescMapOld(pDmaMappingInfo->pMemDesc, 0, @@ -1566,8 +1512,7 @@ virtmemMapTo_IMPL { if (pDmaMappingInfo != NULL) { - if ((pDmaMappingInfo->pMemDesc != NULL) && - FLD_TEST_DRF(OS46, _FLAGS, _KERNEL_MAPPING, _ENABLE, flags)) + if ((pDmaMappingInfo->pMemDesc != NULL) && bKernelMappingRequired) { // // if Kernel cookie exists and mapping is in sysmem, free sysmem mapping @@ -1587,23 +1532,9 @@ virtmemMapTo_IMPL } } - if (pDmaMappingInfo->pMemDesc != NULL) + if (pDmaMappingInfo->pMemDesc != NULL && bIsIndirectPeer) { - NV_STATUS status; - - if (bIsIndirectPeer) - { - memdescUnmapIommu(pDmaMappingInfo->pMemDesc, pGpu->busInfo.iovaspaceId); - } - else if (bDmaMapped) - { - // Unmap the DMA mapped pages in failure case if any. - status = osDmaUnmapPages(pGpu->pOsGpuInfo, pDmaMappingInfo->pMemDesc); - if (!(status == NV_OK || status == NV_ERR_NOT_SUPPORTED)) - { - NV_PRINTF(LEVEL_ERROR, "DMA unmap pages failed for requested GPU!\n"); - } - } + memdescUnmapIommu(pDmaMappingInfo->pMemDesc, pGpu->busInfo.iovaspaceId); } dmaFreeBar1P2PMapping_HAL(pDma, pDmaMappingInfo); @@ -1648,6 +1579,11 @@ virtmemUnmapFrom_IMPL OBJVASPACE *pVas = NULL; NV_STATUS status = NV_OK; NvBool bIsIndirectPeer = NV_FALSE; + CLI_DMA_MAPPING_INFO *pDmaMappingInfoLeft = NULL; + NvBool bDmaMappingInfoLeftRegistered = NV_FALSE; + CLI_DMA_MAPPING_INFO *pDmaMappingInfoRight = NULL; + NvBool bDmaMappingInfoRightRegistered = NV_FALSE; + CLI_DMA_MAPPING_INFO *pDmaMappingInfoUnmap = NULL; CLI_DMA_MAPPING_INFO *pDmaMappingInfo = NULL; @@ -1686,55 +1622,105 @@ virtmemUnmapFrom_IMPL // Get DMA mapping info. pDmaMappingInfo = intermapGetDmaMapping(pVirtualMemory, dmaOffset, gpuMask); NV_ASSERT_OR_RETURN(pDmaMappingInfo != NULL, NV_ERR_INVALID_OBJECT_HANDLE); + NvBool bPartialUnmap = dmaOffset != pDmaMappingInfo->DmaOffset || pParams->size != pDmaMappingInfo->pMemDesc->Size; + NV_ASSERT_OR_RETURN(!bPartialUnmap || (gpuMask & (gpuMask - 1)) == 0, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(!bPartialUnmap || !bIsIndirectPeer, NV_ERR_INVALID_ARGUMENT); - // - // if Kernel cookie exists and mapping is in sysmem, free sysmem mapping - // for ADDR_FBMEM function determines whether mapping was created itself - // - if ((pDmaMappingInfo->KernelPriv != NULL) && - (memdescGetAddressSpace(pDmaMappingInfo->pMemDesc) == ADDR_SYSMEM)) + if (FLD_TEST_DRF(OS46, _FLAGS, _KERNEL_MAPPING, _ENABLE, pDmaMappingInfo->Flags)) { - memdescUnmapOld(pDmaMappingInfo->pMemDesc, NV_TRUE, 0, - pDmaMappingInfo->KernelVAddr[gpumgrGetSubDeviceInstanceFromGpu(gpumgrGetParentGPU(pGpu))], - pDmaMappingInfo->KernelPriv); - pDmaMappingInfo->KernelPriv = NULL; - } - else if (memdescGetAddressSpace(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu)) == ADDR_FBMEM) - { - _virtmemFreeKernelMapping(pGpu, pDmaMappingInfo); + NV_ASSERT_OR_RETURN(!bPartialUnmap, NV_ERR_INVALID_ARGUMENT); + + // + // if Kernel cookie exists and mapping is in sysmem, free sysmem mapping + // for ADDR_FBMEM function determines whether mapping was created itself + // + if ((pDmaMappingInfo->KernelPriv != NULL) && + (memdescGetAddressSpace(pDmaMappingInfo->pMemDesc) == ADDR_SYSMEM)) + { + memdescUnmapOld(pDmaMappingInfo->pMemDesc, NV_TRUE, 0, + pDmaMappingInfo->KernelVAddr[gpumgrGetSubDeviceInstanceFromGpu(gpumgrGetParentGPU(pGpu))], + pDmaMappingInfo->KernelPriv); + pDmaMappingInfo->KernelPriv = NULL; + } + else if (memdescGetAddressSpace(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu)) == ADDR_FBMEM) + { + _virtmemFreeKernelMapping(pGpu, pDmaMappingInfo); + } } // if this was peer mapped context dma, remove it from P2P object if (RMCFG_CLASS_NV50_P2P && pDmaMappingInfo->bP2P) { + NV_ASSERT_OR_RETURN(!bPartialUnmap, NV_ERR_INVALID_ARGUMENT); dmaFreeBar1P2PMapping_HAL(GPU_GET_DMA(pGpu), pDmaMappingInfo); } + if (dmaOffset > pDmaMappingInfo->DmaOffset) + { + NV_ASSERT_OK_OR_GOTO(status, + intermapCreateDmaMapping(pClient, pVirtualMemory, &pDmaMappingInfoLeft, pDmaMappingInfo->Flags), + failed); + + pDmaMappingInfoLeft->DmaOffset = pDmaMappingInfo->DmaOffset; + pDmaMappingInfoLeft->bP2P = pDmaMappingInfo->bP2P; + pDmaMappingInfoLeft->addressTranslation = pDmaMappingInfo->addressTranslation; + pDmaMappingInfoLeft->mapPageSize = pDmaMappingInfo->mapPageSize; + + NV_ASSERT_OK_OR_GOTO(status, + memdescCreateSubMem(&pDmaMappingInfoLeft->pMemDesc, pDmaMappingInfo->pMemDesc, pGpu, + pDmaMappingInfoLeft->DmaOffset - pDmaMappingInfo->DmaOffset, + dmaOffset - pDmaMappingInfoLeft->DmaOffset), + failed); + } + + if (dmaOffset + pParams->size < pDmaMappingInfo->DmaOffset + pDmaMappingInfo->pMemDesc->Size) + { + NV_ASSERT_OK_OR_GOTO(status, + intermapCreateDmaMapping(pClient, pVirtualMemory, &pDmaMappingInfoRight, pDmaMappingInfo->Flags), + failed); + + pDmaMappingInfoRight->DmaOffset = dmaOffset + pParams->size; + pDmaMappingInfoRight->bP2P = pDmaMappingInfo->bP2P; + pDmaMappingInfoRight->addressTranslation = pDmaMappingInfo->addressTranslation; + pDmaMappingInfoRight->mapPageSize = pDmaMappingInfo->mapPageSize; + + NV_ASSERT_OK_OR_GOTO(status, + memdescCreateSubMem(&pDmaMappingInfoRight->pMemDesc, pDmaMappingInfo->pMemDesc, pGpu, + pDmaMappingInfoRight->DmaOffset - pDmaMappingInfo->DmaOffset, + pDmaMappingInfo->DmaOffset + pDmaMappingInfo->pMemDesc->Size - pDmaMappingInfoRight->DmaOffset), + failed); + } + + pDmaMappingInfoUnmap = pDmaMappingInfo; + if (pDmaMappingInfoLeft != NULL || pDmaMappingInfoRight != NULL) + { + NV_ASSERT_OK_OR_GOTO(status, + intermapCreateDmaMapping(pClient, pVirtualMemory, &pDmaMappingInfoUnmap, pDmaMappingInfo->Flags), + failed); + + pDmaMappingInfoUnmap->DmaOffset = dmaOffset; + pDmaMappingInfoUnmap->bP2P = pDmaMappingInfo->bP2P; + pDmaMappingInfoUnmap->addressTranslation = pDmaMappingInfo->addressTranslation; + pDmaMappingInfoUnmap->mapPageSize = pDmaMappingInfo->mapPageSize; + pDmaMappingInfoUnmap->gpuMask = pDmaMappingInfo->gpuMask; + + NV_ASSERT_OK_OR_GOTO(status, + memdescCreateSubMem(&pDmaMappingInfoUnmap->pMemDesc, pDmaMappingInfo->pMemDesc, pGpu, + pDmaMappingInfoUnmap->DmaOffset - pDmaMappingInfo->DmaOffset, + pParams->size), + failed); + } + if (!pMemory->bRpcAlloc || gpuIsSplitVasManagementServerClientRmEnabled(pGpu)) { // free mapping in context dma - dmaFreeMap(pGpu, GPU_GET_DMA(pGpu), pVas, pVirtualMemory, pDmaMappingInfo, pParams->flags); + dmaFreeMap(pGpu, GPU_GET_DMA(pGpu), pVas, pVirtualMemory, pDmaMappingInfoUnmap, pParams->flags); if ((memdescGetAddressSpace(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu)) == ADDR_FBMEM) && bIsIndirectPeer) { memdescUnmapIommu(pDmaMappingInfo->pMemDesc, pGpu->busInfo.iovaspaceId); } - else if ((memdescGetAddressSpace(memdescGetMemDescFromGpu(pDmaMappingInfo->pMemDesc, pGpu)) == ADDR_SYSMEM) && - (pDmaMappingInfo->pMemDesc->pGpu != pGpu)) - { - status = osDmaUnmapPages(pGpu->pOsGpuInfo, pDmaMappingInfo->pMemDesc); - if (!(status == NV_OK || status == NV_ERR_NOT_SUPPORTED)) - { - NV_PRINTF(LEVEL_ERROR, "DMA unmap pages failed for requested GPU!\n"); - } - // - // Some operating systems return NV_ERR_NOT_SUPPORTED. Assign NV_OK to - // status since we return status from this function and NV_ERR_NOT_SUPPORTED - // may be considered as failure in calling function. - // - status = NV_OK; - } } // free memory descriptor @@ -1743,8 +1729,53 @@ virtmemUnmapFrom_IMPL pDmaMappingInfo->pMemDesc = NULL; // delete client dma mapping - intermapDelDmaMapping(pClient, pVirtualMemory, dmaOffset, gpuMask); + intermapDelDmaMapping(pClient, pVirtualMemory, pDmaMappingInfo->DmaOffset, gpuMask); + + if (pDmaMappingInfoLeft != NULL) + { + NV_ASSERT_OK_OR_GOTO(status, + intermapRegisterDmaMapping(pClient, pVirtualMemory, pDmaMappingInfoLeft, + pDmaMappingInfoLeft->DmaOffset, gpuMask), + failed); + bDmaMappingInfoLeftRegistered = NV_TRUE; + } + + if (pDmaMappingInfoRight != NULL) + { + NV_ASSERT_OK_OR_GOTO(status, + intermapRegisterDmaMapping(pClient, pVirtualMemory, pDmaMappingInfoRight, + pDmaMappingInfoRight->DmaOffset, gpuMask), + failed); + bDmaMappingInfoRightRegistered = NV_TRUE; + } + +failed: + if (pDmaMappingInfoUnmap != NULL && pDmaMappingInfoUnmap != pDmaMappingInfo) + { + memdescFree(pDmaMappingInfoUnmap->pMemDesc); + memdescDestroy(pDmaMappingInfoUnmap->pMemDesc); + intermapFreeDmaMapping(pDmaMappingInfoUnmap); + } + + if (status != NV_OK) + { + if (pDmaMappingInfoLeft != NULL) + { + if (bDmaMappingInfoLeftRegistered) + intermapDelDmaMapping(pClient, pVirtualMemory, pDmaMappingInfoLeft->DmaOffset, gpuMask); + else + intermapFreeDmaMapping(pDmaMappingInfoLeft); + } + + if (pDmaMappingInfoRight != NULL) + { + if (bDmaMappingInfoRightRegistered) + intermapDelDmaMapping(pClient, pVirtualMemory, pDmaMappingInfoRight->DmaOffset, gpuMask); + else + intermapFreeDmaMapping(pDmaMappingInfoRight); + } + } // // vGPU: // diff --git a/src/nvidia/src/kernel/os/os_init.c b/src/nvidia/src/kernel/os/os_init.c index 1e88278de7..d58a6f4210 100644 --- a/src/nvidia/src/kernel/os/os_init.c +++ b/src/nvidia/src/kernel/os/os_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -300,6 +300,11 @@ void vgpuDevWriteReg032( NV_ASSERT_OK(kbifGetPciConfigSpacePriMirror_HAL(pGpu, GPU_GET_KERNEL_BIF(pGpu), &configSpaceMirrorBase, &configSpaceMirrorSize)); + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + configSpaceSize = configSpaceMirrorSize; + } + else { configSpaceSize = NV_CONFIG_PCI_NV_12; } @@ -371,6 +376,11 @@ NvU32 vgpuDevReadReg032( NV_ASSERT_OK(kbifGetPciConfigSpacePriMirror_HAL(pGpu, GPU_GET_KERNEL_BIF(pGpu), &configSpaceMirrorBase, &configSpaceMirrorSize)); + if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + configSpaceSize = configSpaceMirrorSize; + } + else { configSpaceSize = NV_CONFIG_PCI_NV_12; } diff --git a/src/nvidia/src/kernel/os/os_sanity.c b/src/nvidia/src/kernel/os/os_sanity.c index 127def6e5a..f5ef3f170a 100644 --- a/src/nvidia/src/kernel/os/os_sanity.c +++ b/src/nvidia/src/kernel/os/os_sanity.c @@ -236,8 +236,8 @@ static NV_STATUS _osVerifyInterrupts( while (!interrupt_triggered) { #if defined(NV_UNIX) && !defined(NV_MODS) - osDelay(50); - Bailout += 50 * 1000; + osDelayNs(5 * 1000); + Bailout += 5; #else OBJTMR *pTmr = GPU_GET_TIMER(pGpu); tmrDelay(pTmr, 5 * 1000); diff --git a/src/nvidia/src/kernel/os/os_stubs.c b/src/nvidia/src/kernel/os/os_stubs.c index 6119ed826e..2ce3fc7731 100644 --- a/src/nvidia/src/kernel/os/os_stubs.c +++ b/src/nvidia/src/kernel/os/os_stubs.c @@ -122,16 +122,6 @@ NV_STATUS osCallACPI_BCL(OBJGPU *pGpu, NvU32 acpiId, NvU32 *pOut, NvU16 *size) return NV_ERR_NOT_SUPPORTED; } -NV_STATUS osCallACPI_ON(OBJGPU *pGpu, NvU32 uAcpiId) -{ - return NV_ERR_NOT_SUPPORTED; -} - -NV_STATUS osCallACPI_OFF(OBJGPU *pGpu, NvU32 uAcpiId) -{ - return NV_ERR_NOT_SUPPORTED; -} - NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *pGpu) { return NV_ERR_NOT_SUPPORTED; @@ -429,6 +419,28 @@ osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo) { return NV_TRUE; } + +NvBool +osTegraSocIsSimNetlistNet07 +( + OS_GPU_INFO *pOsGpuInfo +) +{ + return NV_FALSE; +} + +void +osTegraGetDispSMMUStreamIds +( + OS_GPU_INFO *pOsGpuInfo, + NvU32 *dispIsoStreamId, + NvU32 *dispNisoStreamId +) +{ + /* NV_U32_MAX is used to indicate that the platform does not support SMMU */ + *dispIsoStreamId = NV_U32_MAX; + *dispNisoStreamId = NV_U32_MAX; +} #endif NV_STATUS diff --git a/src/nvidia/src/kernel/os/os_timer.c b/src/nvidia/src/kernel/os/os_timer.c index 5a06144375..bfb3ff7499 100644 --- a/src/nvidia/src/kernel/os/os_timer.c +++ b/src/nvidia/src/kernel/os/os_timer.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2002-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2002-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -109,7 +109,7 @@ osDestroy1HzCallbacks * @return NV_ERR_INVALID_REQUEST The callback has not been added */ NV_STATUS -osSchedule1SecondCallback +osSchedule1HzCallback ( OBJGPU *pGpu, OS1HZPROC callback, @@ -161,7 +161,7 @@ osSchedule1SecondCallback * @param[in] pData Unique identifier for the callback */ void -osRemove1SecondRepeatingCallback +osRemove1HzCallback ( OBJGPU *pGpu, OS1HZPROC callback, diff --git a/src/nvidia/src/kernel/platform/acpi_common.c b/src/nvidia/src/kernel/platform/acpi_common.c index 1459d86383..0c8c311042 100644 --- a/src/nvidia/src/kernel/platform/acpi_common.c +++ b/src/nvidia/src/kernel/platform/acpi_common.c @@ -1110,7 +1110,7 @@ _acpiCacheMethodData NV_STATUS status; NvU32 inOut = 0; NvU16 rtnSize = sizeof(inOut); - NvU32 tableLen = 0, acpiidIndex = 0, mode = 0, muxPartId = 0; + NvU32 tableLen = 0, acpiidIndex = 0, mode = 0, muxPartId = 0, state = 0; // This bit is used for checking if pGpu::acpiMethodData need to be used or not. pGpu->acpiMethodData.bValid = NV_TRUE; @@ -1133,6 +1133,7 @@ _acpiCacheMethodData // Fill in the MUX Method Data. portMemSet(pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable, 0, sizeof(pGpu->acpiMethodData.muxMethodData.acpiIdMuxModeTable)); portMemSet(pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable, 0, sizeof(pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable)); + portMemSet(pGpu->acpiMethodData.muxMethodData.acpiIdMuxStateTable, 0, sizeof(pGpu->acpiMethodData.muxMethodData.acpiIdMuxStateTable)); if (pGpu->acpiMethodData.dodMethodData.status == NV_OK) { tableLen = pGpu->acpiMethodData.dodMethodData.acpiIdListLen / sizeof(NvU32); @@ -1148,7 +1149,12 @@ _acpiCacheMethodData pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex]; pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].mode = muxPartId; pGpu->acpiMethodData.muxMethodData.acpiIdMuxPartTable[acpiidIndex].status = status; - mode = muxPartId = 0; + + status = osCallACPI_MXDS(pGpu, pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex], &state); + pGpu->acpiMethodData.muxMethodData.acpiIdMuxStateTable[acpiidIndex].acpiId = pGpu->acpiMethodData.dodMethodData.acpiIdList[acpiidIndex]; + pGpu->acpiMethodData.muxMethodData.acpiIdMuxStateTable[acpiidIndex].mode = state; + pGpu->acpiMethodData.muxMethodData.acpiIdMuxStateTable[acpiidIndex].status = status; + mode = muxPartId = state = 0; } } diff --git a/src/nvidia/src/kernel/platform/chipset/chipset.c b/src/nvidia/src/kernel/platform/chipset/chipset.c index e998220700..c4f6cf4504 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -80,6 +80,12 @@ clInitPropertiesFromRegistry_IMPL(OBJGPU *pGpu, OBJCL *pCl) } } + if ((osReadRegistryDword(pGpu, NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC, &data32) == NV_OK) + && (data32 == NV_REG_STR_RM_FORCE_DISABLE_IOMAP_WC_YES)) + { + pCl->setProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC, NV_TRUE); + } + osQADbgRegistryInit(); } diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_info.c b/src/nvidia/src/kernel/platform/chipset/chipset_info.c index 2e1fed4658..574eb11baf 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_info.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_info.c @@ -1292,6 +1292,40 @@ Arm_NeoverseN1_setupFunc return NV_OK; } +static NV_STATUS +Riscv_generic_setupFunc +( + OBJCL *pCl +) +{ + pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); + return NV_OK; +} + +static NV_STATUS +PLDA_XpressRichAXI_setupFunc +( + OBJCL *pCl +) +{ +#if NVCPU_IS_RISCV64 + pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); +#endif + return NV_OK; +} + +// Ampere AmpereOne Setup Function +static NV_STATUS +Ampere_AmpereOne_setupFunc +( + OBJCL *pCl +) +{ + // TODO Need to check if any more PDB properties should be set + pCl->setProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT, NV_TRUE); + return NV_OK; +} + void csGetInfoStrings ( diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c index 1b5817f5e2..2fc50d5fa1 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c @@ -36,16 +36,15 @@ #include "platform/chipset/chipset.h" #include "platform/chipset/chipset_info.h" #include "nvpcie.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "objtmr.h" #include "gpu/bif/kernel_bif.h" -#include "gpu/gpu.h" #include "gpu/gsp/gsp_static_config.h" #include "virtualization/hypervisor/hypervisor.h" #include "gpu/mem_mgr/virt_mem_allocator_common.h" #include "ctrl/ctrl2080/ctrl2080bus.h" // NV2080_CTRL_BUS_INFO_PCIE_LINK_ERRORS_* #include "core/thread_state.h" -#include "nveGPUConfig.h" #include "Nvcm.h" #include "nvdevid.h" @@ -73,7 +72,6 @@ static void objClGpuMapEnhCfgSpace(OBJGPU *, OBJCL *); static void objClGpuUnmapEnhCfgSpace(OBJGPU *); static NV_STATUS objClGpuIs3DController(OBJGPU *); static void objClLoadPcieVirtualP2PApproval(OBJGPU *); -static void objClCheckForExternalGpu(OBJGPU *, OBJCL *); static void _objClAdjustTcVcMap(OBJGPU *, OBJCL *, PORTDATA *); static void _objClGetDownstreamAtomicsEnabledMask(void *, NvU32, NvU32 *); static void _objClGetUpstreamAtomicRoutingCap(void *, NvU32, NvBool *); @@ -1104,9 +1102,6 @@ NV_STATUS clInitPcie_IMPL /* enable chipset-specific overrides */ clUpdatePcieConfig(pGpu, pCl); - // Bug 200370149 tracks normalizing KMD detection with RM. - objClCheckForExternalGpu(pGpu, pCl); - return NV_OK; } @@ -4331,84 +4326,6 @@ objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu) gpuGetInstance(pGpu), pGpu->pciePeerClique.id); } -/*! - * @brief Traverse bus topology till Gpu's root port. - * If any of the intermediate bridge has TB3 supported vendorId and hotplug - * capability(not necessarily same bridge), mark the Gpu as External Gpu. - * - * @params[in] pGpu OBJGPU pointer - * @params[in] pCl OBJCL pointer - * - */ -void -objClCheckForExternalGpu -( - OBJGPU *pGpu, - OBJCL *pCl -) -{ - NvU8 bus; - NvU32 domain; - void *handleUp; - NvU8 busUp, devUp, funcUp; - NvU16 vendorIdUp, deviceIdUp; - NvU32 portCaps, pciCaps, slotCaps; - NvU32 PCIECapPtr; - NvBool bTb3Bridge = NV_FALSE, bSlotHotPlugSupport = NV_FALSE; - - domain = gpuGetDomain(pGpu); - bus = gpuGetBus(pGpu); - - do - { - // Find the upstream bridge - handleUp = clFindP2PBrdg(pCl, domain, bus, &busUp, &devUp, &funcUp, &vendorIdUp, &deviceIdUp); - if (!handleUp) - { - return; - } - - if (vendorIdUp == PCI_VENDOR_ID_INTEL) - { - // Check for the supported TB3(ThunderBolt 3) bridges. - bTb3Bridge = isTB3DeviceID(deviceIdUp); - } - - if (NV_OK != clSetPortPcieCapOffset(pCl, handleUp, &PCIECapPtr)) - { - // PCIE bridge but no cap pointer. - return; - } - - // Get the PCIE capabilities. - pciCaps = osPciReadDword(handleUp, CL_PCIE_CAP - CL_PCIE_BEGIN + PCIECapPtr); - if (CL_PCIE_CAP_SLOT & pciCaps) - { - // Get the slot capabilities. - slotCaps = osPciReadDword(handleUp, CL_PCIE_SLOT_CAP - CL_PCIE_BEGIN + PCIECapPtr); - - if ((CL_PCIE_SLOT_CAP_HOTPLUG_CAPABLE & slotCaps) && - (CL_PCIE_SLOT_CAP_HOTPLUG_SURPRISE & slotCaps)) - { - bSlotHotPlugSupport = NV_TRUE; - } - } - - if (bTb3Bridge && bSlotHotPlugSupport) - { - pCl->setProperty(pCl, PDB_PROP_CL_IS_EXTERNAL_GPU, NV_TRUE); - break; - } - - bus = busUp; - - // Get port caps to check if PCIE bridge is the root port - portCaps = osPciReadDword(handleUp, CL_PCIE_CAP - CL_PCIE_BEGIN + PCIECapPtr); - - } while (!CL_IS_ROOT_PORT(portCaps)); -} - - /*! * @brief : Enable L0s and L1 support for GPU's upstream port * Refer Section 7.8.7. Link Control Register of PCIE Spec 3. diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index 7b04f58641..eb37a4a4a1 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -186,6 +186,7 @@ void RmInitCpuInfo(void) break; case AARCH64_VENDOR_PART(ARM, NEOVERSE_N2): case AARCH64_VENDOR_PART(ARM, NEOVERSE_V2): + case AARCH64_VENDOR_PART(AMPERE_2, AMPEREONE): pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC; break; default: diff --git a/src/nvidia/src/kernel/platform/cpu_arm_def.h b/src/nvidia/src/kernel/platform/cpu_arm_def.h index 185777505d..3f658e771a 100644 --- a/src/nvidia/src/kernel/platform/cpu_arm_def.h +++ b/src/nvidia/src/kernel/platform/cpu_arm_def.h @@ -57,6 +57,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_IMPLEMENTER_FUJITSU 0x46 #define CP_MIDR_IMPLEMENTER_PHYTIUM 0x70 #define CP_MIDR_IMPLEMENTER_AMPERE 0x81 +#define CP_MIDR_IMPLEMENTER_AMPERE_2 0XC0 #define CP_CSSELR_DATA_CACHE 0 #define CP_CSSELR_INSTRUCTION_CACHE 1 @@ -91,6 +92,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1 #define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49 +#define CP_MIDR_PRIMARY_PART_NUM_AMPEREONE 0xac3 // Cache Size Identification Register #define CP_CCSIDR "ccsidr_el1" diff --git a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c index 3a3408b3cc..763f5a8ddb 100644 --- a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c +++ b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c @@ -28,6 +28,7 @@ #include "kernel/gpu/bif/kernel_bif.h" #include "gpu/subdevice/subdevice.h" #include "gpu/gpu.h" +#include "virtualization/hypervisor/hypervisor.h" #include "vgpu/rpc.h" #include "vgpu/vgpu_events.h" #include "platform/chipset/chipset.h" @@ -96,7 +97,7 @@ p2pGetCaps // The classes like NV50_P2P, NV50_THIRD_PARTY_P2P depends on direct P2P // connectivity, hence the check. // - if (!((connectivity == P2P_CONNECTIVITY_PCIE) || + if (!((connectivity == P2P_CONNECTIVITY_PCIE_PROPRIETARY) || (connectivity == P2P_CONNECTIVITY_PCIE_BAR1) || (connectivity == P2P_CONNECTIVITY_NVLINK) || (connectivity == P2P_CONNECTIVITY_C2C))) @@ -345,6 +346,7 @@ _kp2pCapsGetStatusOverPcie NvU8 gpuP2PWriteCapsStatus = NV0000_P2P_CAPS_STATUS_OK; NvU32 lockedGpuMask = 0; NV_STATUS status = NV_OK; + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); // Check if any overrides are enabled. if (_kp2pCapsCheckStatusOverridesForPcie(gpuMask, pP2PWriteCapStatus, @@ -362,6 +364,16 @@ _kp2pCapsGetStatusOverPcie } } + // Check for hypervisor oriented PCIe P2P overrides + if (pHypervisor && + pHypervisor->bDetected && + hypervisorPcieP2pDetection(pHypervisor, gpuMask)) + { + *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_OK; + *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_OK; + goto done; + } + // PCI-E topology checks gpuInstance = 0; while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) @@ -760,7 +772,7 @@ p2pGetCapsStatus NvU8 bar1P2PWriteCapStatus = *pP2PWriteCapStatus; NvU8 bar1P2PReadCapStatus = *pP2PReadCapStatus; - *pConnectivity = P2P_CONNECTIVITY_PCIE; + *pConnectivity = P2P_CONNECTIVITY_PCIE_PROPRIETARY; if (_kp2pCapsGetStatusOverPcieBar1(gpuMask, &bar1P2PWriteCapStatus, &bar1P2PReadCapStatus, bCommonSwitchFound) == NV_OK) diff --git a/src/nvidia/src/kernel/platform/platform_request_handler.c b/src/nvidia/src/kernel/platform/platform_request_handler.c index 1008e0dab1..8d3a18629f 100644 --- a/src/nvidia/src/kernel/platform/platform_request_handler.c +++ b/src/nvidia/src/kernel/platform/platform_request_handler.c @@ -25,6 +25,7 @@ #include "nvRmReg.h" #include "objtmr.h" #include "platform/platform_request_handler.h" +#include "gpu_mgr/gpu_mgr.h" #include "core/locks.h" #include "diagnostics/tracer.h" #include "gps.h" diff --git a/src/nvidia/src/kernel/platform/sli/sli.c b/src/nvidia/src/kernel/platform/sli/sli.c index 536965bcad..e2214adf23 100644 --- a/src/nvidia/src/kernel/platform/sli/sli.c +++ b/src/nvidia/src/kernel/platform/sli/sli.c @@ -125,8 +125,14 @@ rmSliSearchForSliCombination(OBJGPU *pGpu, NvU32 nWay, NvU32 numFoundValidConfig do { + gpuMask = NVBIT(pGpu->gpuInstance) | mask; + + // // Look for a mask contained in the GPU mask, - if ((mask & gpuAttachMask) != mask) + // and check that GPUs are initialized + // + if (((mask & gpuAttachMask) != mask) || + (!gpumgrAreGpusInitialized(gpuMask))) { // Last mask. Exit loop. if (mask == largestMask) @@ -138,8 +144,6 @@ rmSliSearchForSliCombination(OBJGPU *pGpu, NvU32 nWay, NvU32 numFoundValidConfig continue; } - gpuMask = NVBIT(pGpu->gpuInstance) | mask; - // Do Sli link detection gpumgrDetectSliLinkFromGpus(NV_TRUE, nWay, gpuMask, &sliLinkTestDone, diff --git a/src/nvidia/src/kernel/power/gpu_boost_mgr.c b/src/nvidia/src/kernel/power/gpu_boost_mgr.c index a3dcb1ab31..c9d9b35379 100644 --- a/src/nvidia/src/kernel/power/gpu_boost_mgr.c +++ b/src/nvidia/src/kernel/power/gpu_boost_mgr.c @@ -39,6 +39,7 @@ #include "vgpu/vgpu_events.h" #include "gpu/perf/kern_perf_gpuboostsync.h" #include "nvdevid.h" +#include "platform/sli/sli.h" /*-----------------------Static Private Method Prototypes---------------------*/ static NV_STATUS _gpuboostmgrApplyPolicyFilters(NV0000_SYNC_GPU_BOOST_GROUP_CONFIG *); diff --git a/src/nvidia/src/kernel/rmapi/alloc_free.c b/src/nvidia/src/kernel/rmapi/alloc_free.c index 4d4e0ef3c2..7d30414496 100644 --- a/src/nvidia/src/kernel/rmapi/alloc_free.c +++ b/src/nvidia/src/kernel/rmapi/alloc_free.c @@ -22,6 +22,7 @@ */ #include "rmapi/rmapi.h" +#include "rmapi/rmapi_specific.h" #include "rmapi/client.h" #include "entry_points.h" #include "core/locks.h" @@ -32,13 +33,13 @@ #include "gpu/disp/disp_channel.h" #include "nvsecurityinfo.h" #include "virtualization/hypervisor/hypervisor.h" +#include "gpu_mgr/gpu_mgr.h" +#include "platform/sli/sli.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "gpu/device/device.h" - -#include "class/cl0005.h" // NV01_EVENT -#include "class/clc574.h" // UVM_CHANNEL_RETAINER +#include "class/cl0080.h" #include "class/cl83de.h" // GT200_DEBUGGER #include "gpu/gr/kernel_sm_debugger_session.h" @@ -215,35 +216,6 @@ serverAllocApiCopyOut return status; } -NvHandle -serverAllocLookupSecondClient -( - NvU32 externalClassId, - void *pAllocParams -) -{ - if (pAllocParams != NULL) - { - switch (externalClassId) - { - case GT200_DEBUGGER: - { - return ((NV83DE_ALLOC_PARAMETERS *) pAllocParams)->hAppClient; - break; - } - case UVM_CHANNEL_RETAINER: - { - return ((NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS *) pAllocParams)->hClient; - break; - } - default: - break; - } - } - - return NV01_NULL_OBJECT; -} - NV_STATUS serverTopLock_Prologue ( @@ -575,46 +547,6 @@ _rmAlloc } -static -NV_STATUS -_fixupAllocParams -( - RS_RESOURCE_DESC **ppResDesc, - RS_RES_ALLOC_PARAMS_INTERNAL *pRmAllocParams -) -{ - RS_RESOURCE_DESC *pResDesc = *ppResDesc; - - if ((pResDesc->pClassInfo != NULL) && (pResDesc->pClassInfo->classId == classId(Event))) - { - NV0005_ALLOC_PARAMETERS *pNv0005Params = pRmAllocParams->pAllocParams; - - // - // This field isn't filled out consistently by clients. Some clients specify NV01_EVENT as the class - // and then override it using the subclass in the event parameters, while other clients specify the - // same subclass in both the RmAllocParams and event params. NV01_EVENT isn't a valid class to allocate - // so overwrite it with the subclass from the event params. - // - if (pRmAllocParams->externalClassId == NV01_EVENT) - pRmAllocParams->externalClassId = pNv0005Params->hClass; - - pNv0005Params->hSrcResource = pRmAllocParams->hParent; - - // No support for event and src resource that reside under different clients - if (pNv0005Params->hParentClient != pRmAllocParams->hClient) - pRmAllocParams->hParent = pRmAllocParams->hClient; - - // class id may have changed so refresh the resource descriptor, but make sure it is still an Event - pResDesc = RsResInfoByExternalClassId(pRmAllocParams->externalClassId); - if (pResDesc == NULL || pResDesc->pClassInfo == NULL || pResDesc->pClassInfo->classId != classId(Event)) - return NV_ERR_INVALID_CLASS; - - *ppResDesc = pResDesc; - } - - return NV_OK; -} - static NV_STATUS _serverAlloc_ValidateVgpu ( @@ -628,7 +560,7 @@ _serverAlloc_ValidateVgpu // // Get any GPU to check environmental properties // Assume: In multi-vGPU systems, no mix and matching SRIOV and non-SRIOV GPUs. - // Assume: This POBJGPU will only used to read system properties. + // Assume: This OBJGPU will only used to read system properties. // OBJGPU *pGpu = gpumgrGetSomeGpu(); @@ -756,7 +688,7 @@ serverAllocResourceUnderLock return NV_ERR_INVALID_CLASS; } - NV_ASSERT_OK_OR_RETURN(_fixupAllocParams(&pResDesc, pRmAllocParams)); + NV_ASSERT_OK_OR_RETURN(rmapiFixupAllocParams(&pResDesc, pRmAllocParams)); rmapiResourceDescToLegacyFlags(pResDesc, &pLockInfo->flags, NULL); status = _serverAllocValidatePrivilege(pServer, pResDesc, pRmAllocParams); @@ -957,7 +889,8 @@ serverAllocResourceUnderLock callContext.pLockInfo = pRmAllocParams->pLockInfo; callContext.secInfo = *pRmAllocParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); NV_RM_RPC_ALLOC_OBJECT(pGpu, pRmAllocParams->hClient, pRmAllocParams->hParent, @@ -966,7 +899,7 @@ serverAllocResourceUnderLock pRmAllocParams->pAllocParams, pRmAllocParams->paramsSize, status); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; @@ -1031,6 +964,49 @@ serverFreeResourceRpcUnderLock pResourceRef->pParentRef->hResource, pResourceRef->hResource, status); + NvBool clientInUse = NV_FALSE; + if ( IS_VIRTUAL(pGpu) && (pResourceRef->externalClassId == GT200_DEBUGGER)) + { + RS_ITERATOR it; + + it = clientRefIter(pResourceRef->pClient, NULL, classId(Device), RS_ITERATE_CHILDREN, NV_TRUE); + while (clientRefIterNext(it.pClient, &it)) + { + Device *pDeviceTest = dynamicCast(it.pResourceRef->pResource, Device); + // In VGPU-GSP mode each plugin only handles it's own GPU, + // so we need to check if Device has the same OBJGPU. + if (pDeviceTest != NULL && (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) || GPU_RES_GET_GPU(pDeviceTest) == pGpu)) + { + clientInUse = NV_TRUE; + break; + } + } + + it = clientRefIter(pResourceRef->pClient, NULL, classId(KernelSMDebuggerSession), RS_ITERATE_CHILDREN, NV_TRUE); + while (clientRefIterNext(it.pClient, &it)) + { + KernelSMDebuggerSession *pKernelSMDebuggerSession = dynamicCast(it.pResourceRef->pResource, KernelSMDebuggerSession); + if ((dynamicCast(pResourceRef->pResource, KernelSMDebuggerSession) != pKernelSMDebuggerSession) && pKernelSMDebuggerSession != NULL && + (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) || GPU_RES_GET_GPU(pKernelSMDebuggerSession) == pGpu)) + { + clientInUse = NV_TRUE; + break; + } + } + // If neither any devices nor KernelSMDebuggerSession are in use, free up the client on host. + if (!clientInUse) + { + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to do the hardware update. + // + NV_RM_RPC_FREE(pGpu, pResourceRef->pClient->hClient, NV01_NULL_OBJECT, pResourceRef->pClient->hClient, status); + } + } + rpc_done: return status; } @@ -1217,8 +1193,11 @@ rmapiAllocWithSecInfo if (pSecInfo->paramLocation == PARAM_LOCATION_KERNEL) { - hSecondClient = serverAllocLookupSecondClient(hClass, - NvP64_VALUE(pAllocParams)); + status = serverAllocLookupSecondClient(hClass, + NvP64_VALUE(pAllocParams), + &hSecondClient); + if (status != NV_OK) + goto done; } portMemSet(pLockInfo, 0, sizeof(*pLockInfo)); @@ -1354,6 +1333,25 @@ resservResourceFactory } } + if (pResDesc->internalClassId == classId(Device)) + { + if (pParams == NULL || pParams->pAllocParams == NULL) + return NV_ERR_INVALID_ARGUMENT; + + NV0080_ALLOC_PARAMETERS *pNv0080AllocParams = pParams->pAllocParams; + NvU32 deviceInst = pNv0080AllocParams->deviceId; + + if (deviceInst >= NV_MAX_DEVICES) + return NV_ERR_INVALID_ARGUMENT; + + NvU32 gpuInst = gpumgrGetPrimaryForDevice(deviceInst); + + if ((pGpu = gpumgrGetGpu(gpuInst)) == NULL) + { + return NV_ERR_INVALID_STATE; + } + } + status = objCreateDynamicWithFlags(&pDynamic, (Object*)pGpu, pResDesc->pClassInfo, diff --git a/src/nvidia/src/kernel/rmapi/binary_api.c b/src/nvidia/src/kernel/rmapi/binary_api.c index eb91a42420..9a7eb4b5be 100644 --- a/src/nvidia/src/kernel/rmapi/binary_api.c +++ b/src/nvidia/src/kernel/rmapi/binary_api.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -32,7 +32,8 @@ #include "gpu/gpu_resource.h" #include "gpu/gpu.h" #include "core/locks.h" - +#include "vgpu/rpc.h" +#include "rmapi/rmapi_utils.h" NV_STATUS binapiConstruct_IMPL @@ -64,9 +65,10 @@ binapiControl_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { - NV_STATUS status; + NV_STATUS status = NV_OK; OBJGPU *pGpu = GPU_RES_GET_GPU(pResource); GPU_MASK gpuMaskRelease = 0; + RM_API *pRmApi; // check if CMD is NULL, return early if (RMCTRL_IS_NULL_CMD(pParams->cmd)) @@ -75,23 +77,51 @@ binapiControl_IMPL if (pGpu == NULL) return NV_ERR_INVALID_ARGUMENT; - NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, - GPU_LOCK_GRP_SUBDEVICE, - GPUS_LOCK_FLAGS_NONE, - RM_LOCK_MODULES_RPC, - &gpuMaskRelease)); - - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - status = pRmApi->Control(pRmApi, - pParams->hClient, - pParams->hObject, - pParams->cmd, - pParams->pParams, - pParams->paramsSize); - if (gpuMaskRelease != 0) + if (IS_VIRTUAL(pGpu)) { - rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + { + NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuMaskRelease)); + + NV_RM_RPC_API_CONTROL(pGpu, + pParams->hClient, + pParams->hObject, + pParams->cmd, + pParams->pParams, + pParams->paramsSize, + status); + + if (gpuMaskRelease != 0) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + } } + else if (IS_GSP_CLIENT(pGpu)) + { + NV_ASSERT_OK_OR_RETURN(rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuMaskRelease)); + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + status = pRmApi->Control(pRmApi, + pParams->hClient, + pParams->hObject, + pParams->cmd, + pParams->pParams, + pParams->paramsSize); + + if (gpuMaskRelease != 0) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + } + return status; } @@ -103,18 +133,29 @@ binapiprivControl_IMPL RS_RES_CONTROL_PARAMS_INTERNAL *pParams ) { + NV_STATUS status = NV_OK; + // check if CMD is NULL, return early if (RMCTRL_IS_NULL_CMD(pParams->cmd)) return NV_OK; + { + if (pParams->secInfo.privLevel >= RS_PRIV_LEVEL_USER_ROOT) + { + status = NV_OK; + } + else + { + status = NV_ERR_INSUFFICIENT_PERMISSIONS; + } + } - // Add check if privileged client - if (pParams->secInfo.privLevel >= RS_PRIV_LEVEL_USER_ROOT) + if (status == NV_OK) { return binapiControl_IMPL(staticCast(pResource, BinaryApi), pCallContext, pParams); } else { - return NV_ERR_INSUFFICIENT_PERMISSIONS; + return status; } } diff --git a/src/nvidia/src/kernel/rmapi/client.c b/src/nvidia/src/kernel/rmapi/client.c index 2fbbe988a2..94f2ccb508 100644 --- a/src/nvidia/src/kernel/rmapi/client.c +++ b/src/nvidia/src/kernel/rmapi/client.c @@ -30,7 +30,6 @@ #include "rmapi/resource_fwd_decls.h" #include "core/locks.h" #include "core/system.h" -#include "gpu/device/device.h" #include "resource_desc.h" #include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" @@ -315,13 +314,12 @@ rmclientInterMap_IMPL mapToParams.hMemoryDevice = pPrivate->hMemoryDevice; mapToParams.gpuMask = pPrivate->gpuMask; mapToParams.bSubdeviceHandleProvided = pPrivate->bSubdeviceHandleProvided; - mapToParams.bDmaMapNeeded = pPrivate->bDmaMapNeeded; mapToParams.bFlaMapping = pPrivate->bFlaMapping; return resMapTo(pMapperRef->pResource, &mapToParams); } -void +NV_STATUS rmclientInterUnmap_IMPL ( RmClient *pClient, @@ -339,13 +337,14 @@ rmclientInterUnmap_IMPL unmapFromParams.hMemory = pParams->hMappable; unmapFromParams.flags = pParams->flags; unmapFromParams.dmaOffset = pParams->dmaOffset; + unmapFromParams.size = pParams->size; unmapFromParams.pGpu = pPrivate->pGpu; unmapFromParams.hBroadcastDevice = pPrivate->hBroadcastDevice; unmapFromParams.gpuMask = pPrivate->gpuMask; unmapFromParams.bSubdeviceHandleProvided = pPrivate->bSubdeviceHandleProvided; - resUnmapFrom(pMapperRef->pResource, &unmapFromParams); + return resUnmapFrom(pMapperRef->pResource, &unmapFromParams); } RS_PRIV_LEVEL @@ -800,6 +799,11 @@ static NvBool _rmclientIsCapable internalClassId = classId(FmSessionApi); break; } + case NV_RM_CAP_SYS_FABRIC_IMEX_MGMT: + { + internalClassId = classId(ImexSessionApi); + break; + } case NV_RM_CAP_SYS_SMC_MONITOR: { internalClassId = classId(MIGMonitorSession); diff --git a/src/nvidia/src/kernel/rmapi/client_resource.c b/src/nvidia/src/kernel/rmapi/client_resource.c index dc898ca791..ce7599ac25 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource.c +++ b/src/nvidia/src/kernel/rmapi/client_resource.c @@ -1,4 +1,3 @@ - /* * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT @@ -44,6 +43,7 @@ #include "nvsecurityinfo.h" #include "kernel/gpu/rc/kernel_rc.h" #include "resource_desc.h" +#include "platform/sli/sli.h" #include "mem_mgr/fla_mem.h" @@ -90,6 +90,27 @@ #define NVPCF0100_CTRL_CONTROLLER_FILTER_TYPE_EMWA (0) #define NVPCF0100_CTRL_CONTROLLER_FILTER_TYPE_MOVING_MAX (1) +ct_assert(NV_GPU_UUID_LEN == VM_UUID_SIZE); + +static NV_STATUS +CliGetSystemP2pCaps_GSPCLIENT +( + NvU32 *gpuIds, + NvU32 gpuCount, + NvU32 *p2pCaps, + NvU32 *p2pOptimalReadCEs, + NvU32 *p2pOptimalWriteCEs, + NvU8 *p2pCapsStatus, + NvU32 *busPeerIds +); + +static +NV_STATUS +CliGetSystemP2pCapsMatrix_GSPCLIENT +( + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *pP2PParams +); + NV_STATUS cliresConstruct_IMPL ( @@ -344,7 +365,8 @@ CliGetSystemP2pCaps NvU32 *p2pOptimalReadCEs, NvU32 *p2pOptimalWriteCEs, NvU8 *p2pCapsStatus, - NvU32 *pBusPeerIds + NvU32 *pBusPeerIds, + NvU32 *pBusEgmPeerIds ) { OBJGPU *pGpuLocal = NULL; @@ -412,6 +434,11 @@ CliGetSystemP2pCaps pBusPeerIds[(localGpuIndex * gpuCount) + peerGpuIndex] = kbusGetPeerId_HAL(pGpuLocalLoop, GPU_GET_KERNEL_BUS(pGpuLocalLoop), pGpuPeer); } + if (pBusEgmPeerIds != NULL) + { + pBusEgmPeerIds[(localGpuIndex * gpuCount) + peerGpuIndex] = + kbusGetEgmPeerId_HAL(pGpuLocalLoop, GPU_GET_KERNEL_BUS(pGpuLocalLoop), pGpuPeer); + } } } @@ -473,7 +500,8 @@ CliGetSystemP2pCaps p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK] = NV0000_P2P_CAPS_STATUS_OK; } } - else if ((connectivity == P2P_CONNECTIVITY_PCIE_BAR1) || (connectivity == P2P_CONNECTIVITY_PCIE)) + else if ((connectivity == P2P_CONNECTIVITY_PCIE_BAR1) || + (connectivity == P2P_CONNECTIVITY_PCIE_PROPRIETARY)) { if (p2pCaps != NULL) { @@ -481,7 +509,7 @@ CliGetSystemP2pCaps REF_DEF(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED, _TRUE) : 0; *p2pCaps |= (p2pWriteCapStatus == NV0000_P2P_CAPS_STATUS_OK) ? REF_DEF(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED, _TRUE) : 0; - *p2pCaps |= REF_DEF(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED, _TRUE); + *p2pCaps |= REF_DEF(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED, _TRUE); if (connectivity == P2P_CONNECTIVITY_PCIE_BAR1) { @@ -489,13 +517,13 @@ CliGetSystemP2pCaps } else { - *p2pCaps |= REF_DEF(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED, _TRUE); + *p2pCaps |= REF_DEF(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED, _TRUE); } } if (p2pCapsStatus != NULL) { - p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_PROP] = NV0000_P2P_CAPS_STATUS_OK; + p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_PCI] = NV0000_P2P_CAPS_STATUS_OK; if (connectivity == P2P_CONNECTIVITY_PCIE_BAR1) { @@ -503,11 +531,11 @@ CliGetSystemP2pCaps } else { - p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_PCI] = NV0000_P2P_CAPS_STATUS_OK; + p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_PROP] = NV0000_P2P_CAPS_STATUS_OK; } } - if ((gpuCount == 1) && (connectivity == P2P_CONNECTIVITY_PCIE)) + if ((gpuCount == 1) && (connectivity == P2P_CONNECTIVITY_PCIE_PROPRIETARY)) { if (p2pCaps != NULL) { @@ -784,6 +812,12 @@ cliresCtrlCmdSystemGetFeatures_IMPL _IS_EFI_INIT, _TRUE, featuresMask); } + if (pSys->bSysUuidBasedMemExportSupport) + { + featuresMask = FLD_SET_DRF(0000, _CTRL_SYSTEM_GET_FEATURES, + _UUID_BASED_MEM_SHARING, _TRUE, featuresMask); + } + pFeaturesParams->featuresMask = featuresMask; return NV_OK; @@ -1011,7 +1045,7 @@ cliresCtrlCmdSystemGetCpuInfo_IMPL pCpuInfoParams->family = pSys->cpuInfo.family; pCpuInfoParams->model = pSys->cpuInfo.model; pCpuInfoParams->stepping = pSys->cpuInfo.stepping; - pCpuInfoParams->bSEVEnabled = (sysGetStaticConfig(pSys))->bOsCCEnabled; + pCpuInfoParams->bCCEnabled = (sysGetStaticConfig(pSys))->bOsCCEnabled; portMemCopy(pCpuInfoParams->name, sizeof (pCpuInfoParams->name), pSys->cpuInfo.name, sizeof (pCpuInfoParams->name)); @@ -1091,31 +1125,6 @@ cliresCtrlCmdSystemGetChipsetInfo_IMPL return NV_OK; } -// -// cliresCtrlCmdSystemSetMemorySize -// -// Set system memory size in pages. -// -// Lock Requirements: -// Assert that API and GPUs locks held on entry -// -NV_STATUS -cliresCtrlCmdSystemSetMemorySize_IMPL -( - RmClientResource *pRmCliRes, - NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS *pParams -) -{ - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJOS *pOS = SYS_GET_OS(pSys); - - LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); - - pOS->SystemMemorySize = pParams->memorySize; - - return NV_OK; -} - // // cliresCtrlCmdSystemGetLockTimes // @@ -1501,6 +1510,32 @@ cliresCtrlCmdGpuGetProbedIds_IMPL return gpumgrGetProbedGpuIds(pGpuProbedIds); } +// +// _cliresValidateGpuIdAgainstProbed +// +// Lock Requirements: none (only operates on arguments) +// +static NV_STATUS +_cliresValidateGpuIdAgainstProbed +( + NvU32 gpuId, + const NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *pGpuProbedIds +) +{ + NvU32 j; + + for (j = 0; j < NV0000_CTRL_GPU_MAX_PROBED_GPUS; j++) + { + if (pGpuProbedIds->gpuIds[j] == NV0000_CTRL_GPU_INVALID_ID) + break; + + if (gpuId == pGpuProbedIds->gpuIds[j]) + return NV_OK; + } + + return NV_ERR_INVALID_ARGUMENT; +} + // // cliresCtrlCmdGpuAttachIds // @@ -1516,7 +1551,7 @@ cliresCtrlCmdGpuAttachIds_IMPL ) { NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *pGpuProbedIds = NULL; - NvU32 i, j; + NvU32 i; NV_STATUS status = NV_OK; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -1544,19 +1579,10 @@ cliresCtrlCmdGpuAttachIds_IMPL for (i = 0; (i < NV0000_CTRL_GPU_MAX_PROBED_GPUS) && (pGpuAttachIds->gpuIds[i] != NV0000_CTRL_GPU_INVALID_ID); i++) { - for (j = 0; (j < NV0000_CTRL_GPU_MAX_PROBED_GPUS) && - (pGpuProbedIds->gpuIds[j] != NV0000_CTRL_GPU_INVALID_ID); j++) - { - if (pGpuAttachIds->gpuIds[i] == pGpuProbedIds->gpuIds[j]) - break; - } - - if ((j == NV0000_CTRL_GPU_MAX_PROBED_GPUS) || - (pGpuProbedIds->gpuIds[j] == NV0000_CTRL_GPU_INVALID_ID)) - { - status = NV_ERR_INVALID_ARGUMENT; + status = _cliresValidateGpuIdAgainstProbed(pGpuAttachIds->gpuIds[i], + pGpuProbedIds); + if (status != NV_OK) break; - } } // XXX add callback to attach logic on Windows @@ -1565,6 +1591,83 @@ cliresCtrlCmdGpuAttachIds_IMPL return status; } +// +// cliresCtrlCmdGpuAsyncAttachId +// +// Lock Requirements: +// Assert that API lock held on entry +// No GPUs lock +// +NV_STATUS +cliresCtrlCmdGpuAsyncAttachId_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS *pAsyncAttachIdParams +) +{ + // + // Similar to non-async attach, async attach is mostly handled by + // libnvrmapi in userspace. Here, Core RM just does validation. + // + + NV_STATUS status = NV_OK; + NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS *pGpuProbedIds = NULL; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); + + pGpuProbedIds = portMemAllocNonPaged(sizeof(*pGpuProbedIds)); + if (pGpuProbedIds == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + status = gpumgrGetProbedGpuIds(pGpuProbedIds); + if (status != NV_OK) + { + goto done; + } + + status = _cliresValidateGpuIdAgainstProbed(pAsyncAttachIdParams->gpuId, + pGpuProbedIds); + if (status != NV_OK) + { + goto done; + } + +done: + portMemFree(pGpuProbedIds); + return status; +} + +// +// cliresCtrlCmdGpuWaitAttachId +// +// Lock Requirements: none +// +NV_STATUS +cliresCtrlCmdGpuWaitAttachId_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS *pWaitAttachIdParams +) +{ + // + // Similar to non-async attach, async attach is mostly handled by + // libnvrmapi in userspace. That includes the logic for waiting for + // background attach operations to complete. + // + // Since background attach operations are not tracked by Core RM + // (that is the responsibility of libnvrmapi and the kernel interface + // layer), there is nothing to do here. + // + // Note: libnvrmapi on UNIX skips calling into Core RM entirely for this + // command, so this path (and the unneeded API lock acquire) is not taken. + // + + return NV_OK; +} + // // cliresCtrlCmdGpuDetachIds // @@ -1715,6 +1818,7 @@ cliresCtrlCmdGpuAcctGetProcAccountingInfo_IMPL NV_STATUS status = NV_OK; CALL_CONTEXT *pCallContext; RmCtrlParams *pRmCtrlParams; + RM_API *pRmApi; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -1743,15 +1847,14 @@ cliresCtrlCmdGpuAcctGetProcAccountingInfo_IMPL { pCallContext = resservGetTlsCallContext(); pRmCtrlParams = pCallContext->pControlParams; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); - return status; + return pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); } return gpuacctGetProcAcctInfo(pGpuAcct, pAcctInfoParams); @@ -1768,6 +1871,7 @@ cliresCtrlCmdGpuAcctSetAccountingState_IMPL NV_STATUS status = NV_OK; CALL_CONTEXT *pCallContext; RmCtrlParams *pRmCtrlParams; + RM_API *pRmApi; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -1798,14 +1902,15 @@ cliresCtrlCmdGpuAcctSetAccountingState_IMPL { pCallContext = resservGetTlsCallContext(); pRmCtrlParams = pCallContext->pControlParams; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + status = pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); if (status != NV_OK) return status; } @@ -1841,6 +1946,7 @@ cliresCtrlCmdGpuAcctClearAccountingData_IMPL CALL_CONTEXT *pCallContext; RmCtrlParams *pRmCtrlParams; NV_STATUS status = NV_OK; + RM_API *pRmApi; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -1868,15 +1974,14 @@ cliresCtrlCmdGpuAcctClearAccountingData_IMPL { pCallContext = resservGetTlsCallContext(); pRmCtrlParams = pCallContext->pControlParams; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); - return status; + return pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); } return gpuacctClearAccountingData(pGpuAcct, pGpu->gpuInstance, pParams); @@ -1895,6 +2000,7 @@ cliresCtrlCmdGpuAcctGetAccountingState_IMPL CALL_CONTEXT *pCallContext; RmCtrlParams *pRmCtrlParams; NV_STATUS status = NV_OK; + RM_API *pRmApi; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -1922,15 +2028,14 @@ cliresCtrlCmdGpuAcctGetAccountingState_IMPL { pCallContext = resservGetTlsCallContext(); pRmCtrlParams = pCallContext->pControlParams; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); - return status; + return pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); } return gpuacctGetAccountingMode(pGpuAcct, pGpu->gpuInstance, pParams); @@ -1949,6 +2054,7 @@ cliresCtrlCmdGpuAcctGetAccountingPids_IMPL CALL_CONTEXT *pCallContext; RmCtrlParams *pRmCtrlParams; NV_STATUS status = NV_OK; + RM_API *pRmApi; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -1977,15 +2083,14 @@ cliresCtrlCmdGpuAcctGetAccountingPids_IMPL { pCallContext = resservGetTlsCallContext(); pRmCtrlParams = pCallContext->pControlParams; + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_RM_RPC_CONTROL(pGpu, - pRmCtrlParams->hClient, - pRmCtrlParams->hObject, - pRmCtrlParams->cmd, - pRmCtrlParams->pParams, - pRmCtrlParams->paramsSize, - status); - return status; + return pRmApi->Control(pRmApi, + pRmCtrlParams->hClient, + pRmCtrlParams->hObject, + pRmCtrlParams->cmd, + pRmCtrlParams->pParams, + pRmCtrlParams->paramsSize); } return gpuacctGetAcctPids(pGpuAcct, pAcctPidsParams); @@ -1998,7 +2103,7 @@ cliresCtrlCmdSystemPfmreqhndlrControl_IMPL NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CONTROL_PARAMS *controlParams ) { - OBJSYS *pSys = NULL; + OBJSYS *pSys = NULL; PlatformRequestHandler *pPlatformRequestHandler = NULL; NV_STATUS ret = NV_OK; NvU32 data = 0; @@ -2353,8 +2458,8 @@ _controllerParseStaticTable_v20 { _controllerBuildConfig_StaticTable_v20(&entry, pParams); _controllerBuildQboostConfig_StaticTable_v20(&entry, pParams); - break; - } + break; + } case NVPCF_CONTROLLER_STATIC_TABLE_ENTRY_V20_FLAGS0_CLASS_CTGP: { _controllerBuildCtgpConfig_StaticTable_2x(pParams); @@ -2506,10 +2611,10 @@ _sysDeviceParseStaticTable_2x NV_STATUS status = NV_OK; NvU32 deviceTableOffset = 0; SYSDEV_STATIC_TABLE_HEADER_2X sysdevHeader = { 0 }; - SYSDEV_STATIC_TABLE_COMMON_2X common = { 0 }; + SYSDEV_STATIC_TABLE_COMMON_2X common = { 0 }; const char *pSzSysDevHeaderFmt = NVPCF_SYSDEV_STATIC_TABLE_HEADER_2X_FMT_SIZE_03; - const char *pSzCommonFmt = + const char *pSzCommonFmt = NVPCF_SYSDEV_STATIC_TABLE_COMMON_2X_FMT_SIZE_01; // Unpack the table header @@ -2535,7 +2640,7 @@ _sysDeviceParseStaticTable_2x deviceTableOffset + sysdevHeader.headerSize, pSzCommonFmt); - pParams->cpuType = (DRF_VAL(PCF_SYSDEV_STATIC_TABLE_COMMON_2X, _PARAM0, _CPU_TYPE, + pParams->cpuType = (DRF_VAL(PCF_SYSDEV_STATIC_TABLE_COMMON_2X, _PARAM0, _CPU_TYPE, common.param0)); pParams->gpuType = (DRF_VAL(PCF_SYSDEV_STATIC_TABLE_COMMON_2X, _PARAM0, _GPU_TYPE, @@ -2687,10 +2792,6 @@ cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL switch (pParams->subFunc) { - case NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED_CASE: - acpiDsmFunction = ACPI_DSM_FUNCTION_NVPCF; - acpiDsmSubFunction = NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_SUPPORTED; - /* fallthrough */ case NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED_CASE: { NvU32 supportedFuncs; @@ -2723,40 +2824,6 @@ cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL } - case NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_CASE: - { - CONTROLLER_DYNAMIC_TABLE_1X_ACPI dynamicTable_1x; - portMemSet(&dynamicTable_1x, 0, sizeof(dynamicTable_1x)); - - dynamicTable_1x.header.version = NVPCF0100_CTRL_DYNAMIC_TABLE_1X_VERSION; - dynamicTable_1x.header.size = sizeof(NVPCF0100_CTRL_DYNAMIC_TABLE_1X_HEADER); - dynamicTable_1x.header.entryCnt = 2; - dynamicTable_1x.header.reserved = 0; - - dynamicTable_1x.entries[0] = NVPCF0100_CTRL_DYNAMIC_TABLE_1X_INPUT_CMD_GET_TPP; - dsmDataSize = sizeof(dynamicTable_1x); - - if ((rc = osCallACPI_DSM(pGpu, - ACPI_DSM_FUNCTION_NVPCF, - NVPCF0100_CTRL_CONFIG_DSM_1X_FUNC_GET_DYNAMIC_PARAMS, - (NvU32*)(&dynamicTable_1x), - &dsmDataSize)) != NV_OK) - { - NV_PRINTF(LEVEL_WARNING, - "Unable to retrieve NVPCF dynamic data. Possibly not supported by SBIOS " - "rc = %x\n", rc); - status = NV_ERR_NOT_SUPPORTED; - } - else - { - // bit [0:15] is TPP, bit [16:31] is rated TGP - pParams->tpp = dynamicTable_1x.entries[1] & 0xFFFF; - pParams->ratedTgp = (dynamicTable_1x.entries[1] & 0xFFFF0000) >> 16; - } - - break; - } - case NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_DYNAMIC_CASE: { NvU8 *pData = NULL; @@ -3288,6 +3355,408 @@ cliresCtrlCmdNvdGetNvlog_IMPL return status; } +static NV_STATUS +CliGetSystemP2pCaps_GSPCLIENT +( + NvU32 *gpuIds, + NvU32 gpuCount, + NvU32 *p2pCaps, + NvU32 *p2pOptimalReadCEs, + NvU32 *p2pOptimalWriteCEs, + NvU8 *p2pCapsStatus, + NvU32 *busPeerIds +) +{ + NV_STATUS status = NV_OK; + NvU32 i; + NV2080_CTRL_GET_P2P_CAPS_PARAMS *pGetParams = NULL; + + if ((gpuIds == NULL) || + (gpuCount == 0) || + (gpuCount > NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS) || + (p2pOptimalReadCEs == NULL) || + (p2pOptimalWriteCEs == NULL)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pGetParams = portMemAllocNonPaged(sizeof *pGetParams); + NV_CHECK_OR_RETURN(LEVEL_INFO, pGetParams != NULL, NV_ERR_NO_MEMORY); + + // Initialize caps to empty + *p2pOptimalReadCEs = 0; + *p2pOptimalWriteCEs = 0; + if (p2pCaps != NULL) + { + *p2pCaps = 0; + } + + if (p2pCapsStatus != NULL) + { + for (i = 0; i < NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE; i++) + { + p2pCapsStatus[i] = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; + } + } + + if (busPeerIds != NULL) + { + for (i = 0; i < (gpuCount * gpuCount); i++) + { + busPeerIds[i] = NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER; + } + } + + // Initialize internal call params + pGetParams->bAllCaps = NV_FALSE; + pGetParams->bUseUuid = NV_TRUE; + pGetParams->peerGpuCount = gpuCount; + for (i = 0; i < gpuCount; i++) + { + OBJGPU *pGpu = gpumgrGetGpuFromId(gpuIds[i]); + + NV_CHECK_OR_ELSE(LEVEL_INFO, pGpu != NULL, + status = NV_ERR_INVALID_ARGUMENT; goto done); + + portMemCopy(pGetParams->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE, + pGpu->gpuUuid.uuid, + NV_GPU_UUID_LEN); + } + + // Retrieve caps and peer IDs + for (i = 0; i < gpuCount; i++) + { + NvU32 j; + NvU32 gpuMaskRelease = 0; + NvBool bLockAcquired = NV_FALSE; + OBJGPU *pGpu = gpumgrGetGpuFromId(gpuIds[i]); + + NV_CHECK_OR_ELSE(LEVEL_INFO, pGpu != NULL, + status = NV_ERR_INVALID_ARGUMENT; goto done); + + if (!rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskRelease)) + { + // Acquire lock + NV_ASSERT_OK_OR_GOTO(status, + rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuMaskRelease), + done); + + bLockAcquired = NV_TRUE; + } + + NV_RM_RPC_CONTROL(pGpu, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_GET_P2P_CAPS, + pGetParams, + sizeof *pGetParams, + status); + + // Release lock + if (bLockAcquired && gpuMaskRelease != 0) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + + if (status != NV_OK) + goto done; + + // + // Populate caps only once and according to local gpu's view. + // If gpuCount == 1, retrieve gpu caps of local gpu (allows read of loopback cap). + // When gpuCount > 1, retrieve gpu caps of one other remote: + // Don't use caps of local gpu as it may contain loopback cap. + // All local-to-remote pairs have identical caps except CEs data. + // + if (i == 0) + { + NvU32 ref = gpuCount > 1 ? 1 : 0; + NV2080_CTRL_GPU_P2P_PEER_CAPS_PEER_INFO localGpuCaps = pGetParams->peerGpuCaps[ref]; + + if (p2pCaps != NULL) + { + *p2pCaps = localGpuCaps.p2pCaps; + } + + // Retrieve CEs only for a pair of GPUs (local to itself or to a remote) + if (gpuCount <= 2) + { + *p2pOptimalReadCEs = localGpuCaps.p2pOptimalReadCEs; + *p2pOptimalWriteCEs = localGpuCaps.p2pOptimalWriteCEs; + } + + if (p2pCapsStatus != NULL) + { + portMemCopy(p2pCapsStatus, + NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE * sizeof(p2pCapsStatus[0]), + &localGpuCaps.p2pCapsStatus, + NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE * sizeof(localGpuCaps.p2pCapsStatus[0])); + } + } + + // Fill out gpu peerId matrix + if (busPeerIds != NULL) + { + for (j = 0; j < gpuCount; ++j) + busPeerIds[i * gpuCount + j] = pGetParams->peerGpuCaps[j].busPeerId; + } + } + +done: + portMemFree(pGetParams); + + return status; +} + +static NV_STATUS +CliGetSystemP2pCapsMatrix_GSPCLIENT +( + NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS *pP2PParams +) +{ + NV_STATUS status = NV_OK; + NvU32 i; + NvBool bReflexive = NV_FALSE; + NV2080_CTRL_GET_P2P_CAPS_PARAMS *pGetParams = NULL; + + if ((pP2PParams == NULL) || + (pP2PParams->grpACount == 0) || + (pP2PParams->grpACount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS) || + (pP2PParams->grpBCount > NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + pGetParams = portMemAllocNonPaged(sizeof *pGetParams); + NV_CHECK_OR_RETURN(LEVEL_INFO, pGetParams != NULL, NV_ERR_NO_MEMORY); + + if (pP2PParams->grpBCount == 0) + { + bReflexive = NV_TRUE; + } + + // Initialize output to empty + portMemSet(&pP2PParams->p2pCaps, 0, sizeof(pP2PParams->p2pCaps)); + portMemSet(&pP2PParams->a2bOptimalReadCes, 0, sizeof(pP2PParams->a2bOptimalReadCes)); + portMemSet(&pP2PParams->a2bOptimalWriteCes, 0, sizeof(pP2PParams->a2bOptimalWriteCes)); + portMemSet(&pP2PParams->b2aOptimalReadCes, 0, sizeof(pP2PParams->b2aOptimalReadCes)); + portMemSet(&pP2PParams->b2aOptimalWriteCes, 0, sizeof(pP2PParams->b2aOptimalWriteCes)); + + // Initialize internal call params for group A + pGetParams->bAllCaps = NV_FALSE; + pGetParams->bUseUuid = NV_TRUE; + for (i = 0; bReflexive ? i < (pP2PParams->grpACount) : (i < pP2PParams->grpBCount); i++) + { + if (bReflexive) + { + OBJGPU *pGpu = gpumgrGetGpuFromId(pP2PParams->gpuIdGrpA[i]); + + NV_CHECK_OR_ELSE(LEVEL_INFO, pGpu != NULL, + status = NV_ERR_INVALID_ARGUMENT; goto done); + + portMemCopy(pGetParams->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE, + pGpu->gpuUuid.uuid, + NV_GPU_UUID_LEN); + } + else + { + OBJGPU *pGpu = gpumgrGetGpuFromId(pP2PParams->gpuIdGrpB[i]); + + NV_CHECK_OR_ELSE(LEVEL_INFO, pGpu != NULL, + status = NV_ERR_INVALID_ARGUMENT; goto done); + + portMemCopy(pGetParams->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE, + pGpu->gpuUuid.uuid, + NV_GPU_UUID_LEN); + } + } + + // Cycle through group A to set caps and A2B CEs + for (i = 0; i < pP2PParams->grpACount; i++) + { + NvU32 b; + NvU32 gpuMaskRelease = 0; + NvBool bLockAcquired = NV_FALSE; + OBJGPU *pGpu; + + if (bReflexive) + { + // Set gpuCount equal to (i + 1) to get # GPUs up to and including matrix diag + pGetParams->peerGpuCount = i + 1; + } + else + { + pGetParams->peerGpuCount = pP2PParams->grpBCount; + } + + pGpu = gpumgrGetGpuFromId(pP2PParams->gpuIdGrpA[i]); + + NV_CHECK_OR_ELSE(LEVEL_INFO, pGpu != NULL, + status = NV_ERR_INVALID_ARGUMENT; goto done); + + if (!rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskRelease)) + { + // Acquire lock + NV_ASSERT_OK_OR_GOTO(status, + rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuMaskRelease), + done); + + bLockAcquired = NV_TRUE; + } + + NV_RM_RPC_CONTROL(pGpu, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_GET_P2P_CAPS, + pGetParams, + sizeof *pGetParams, + status); + + // Release lock + if (bLockAcquired && gpuMaskRelease != 0) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + + if (status != NV_OK) + goto done; + + // Set Caps and A2B CEs for this row of the matrix + for (b = 0; b < pGetParams->peerGpuCount; ++b) + { + pP2PParams->p2pCaps[i][b] = pGetParams->peerGpuCaps[b].p2pCaps; + pP2PParams->a2bOptimalReadCes[i][b] = pGetParams->peerGpuCaps[b].p2pOptimalReadCEs; + pP2PParams->a2bOptimalWriteCes[i][b] = pGetParams->peerGpuCaps[b].p2pOptimalWriteCEs; + + // If reflexive (including identity) mirror A2B results to B2A + if (bReflexive) + { + pP2PParams->p2pCaps[b][i] = pP2PParams->p2pCaps[i][b]; + pP2PParams->b2aOptimalReadCes[b][i] = pP2PParams->a2bOptimalReadCes[i][b]; + pP2PParams->b2aOptimalWriteCes[b][i] = pP2PParams->a2bOptimalWriteCes[i][b]; + } + } + } + + // + // Initialize internal call params for group B. + // Regardless of bReflexive, logically always should use grpACount and gpuIdGrpA here. + // + portMemSet(pGetParams, 0, sizeof *pGetParams); + pGetParams->bAllCaps = NV_FALSE; + pGetParams->bUseUuid = NV_TRUE; + for (i = 0; i < pP2PParams->grpACount; i++) + { + OBJGPU *pGpu = gpumgrGetGpuFromId(pP2PParams->gpuIdGrpA[i]); + + NV_CHECK_OR_ELSE(LEVEL_INFO, pGpu != NULL, + status = NV_ERR_INVALID_ARGUMENT; goto done); + + portMemCopy(pGetParams->peerGpuCaps[i].gpuUuid, + VM_UUID_SIZE, + pGpu->gpuUuid.uuid, + NV_GPU_UUID_LEN); + } + + // Cycle through group B and set B2A CEs + for (i = 0; bReflexive ? (i < pP2PParams->grpACount) : (i < pP2PParams->grpBCount); i++) + { + NvU32 a; + NvU32 gpuMaskRelease = 0; + NvBool bLockAcquired = NV_FALSE; + OBJGPU *pGpu; + + if (bReflexive) + { + // set count to number of elems up to and including diagonal. + pGetParams->peerGpuCount = i + 1; + pGpu = gpumgrGetGpuFromId(pP2PParams->gpuIdGrpA[i]); + } + else + { + pGetParams->peerGpuCount = pP2PParams->grpACount; + pGpu = gpumgrGetGpuFromId(pP2PParams->gpuIdGrpB[i]); + } + + NV_CHECK_OR_ELSE(LEVEL_INFO, pGpu != NULL, + status = NV_ERR_INVALID_ARGUMENT; goto done); + + if (!rmGpuGroupLockIsOwner(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE, &gpuMaskRelease)) + { + // Acquire lock + NV_ASSERT_OK_OR_GOTO(status, + rmGpuGroupLockAcquire(pGpu->gpuInstance, + GPU_LOCK_GRP_SUBDEVICE, + GPUS_LOCK_FLAGS_NONE, + RM_LOCK_MODULES_RPC, + &gpuMaskRelease), + done); + + bLockAcquired = NV_TRUE; + } + + // Retrieve B2A optimal CEs + NV_RM_RPC_CONTROL(pGpu, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_GET_P2P_CAPS, + pGetParams, + sizeof *pGetParams, + status); + + // Release lock + if (bLockAcquired && gpuMaskRelease != 0) + { + rmGpuGroupLockRelease(gpuMaskRelease, GPUS_LOCK_FLAGS_NONE); + } + + if (status != NV_OK) + goto done; + + // Set B2A CEs + for (a = 0; a < pGetParams->peerGpuCount; ++a) + { + if (bReflexive) + { + if (a == i) + { + // Identity work all done in A loop. + continue; + } + + // Set B->A CEs (which are a2bOptimal*Ces for GPU i in group B) + pP2PParams->a2bOptimalReadCes[a][i] = pGetParams->peerGpuCaps[a].p2pOptimalReadCEs; + pP2PParams->a2bOptimalWriteCes[a][i] = pGetParams->peerGpuCaps[a].p2pOptimalWriteCEs; + + // Set A->B CEs (which are b2aOptimal*Ces for GPU i in group A) + pP2PParams->b2aOptimalReadCes[i][a] = pP2PParams->a2bOptimalReadCes[a][i]; + pP2PParams->b2aOptimalWriteCes[i][a] = pP2PParams->a2bOptimalWriteCes[a][i]; + } + else + { + pP2PParams->b2aOptimalReadCes[a][i] = pGetParams->peerGpuCaps[a].p2pOptimalReadCEs; + pP2PParams->b2aOptimalWriteCes[a][i] = pGetParams->peerGpuCaps[a].p2pOptimalWriteCEs; + } + } + } + +done: + portMemFree(pGetParams); + + return status; +} + NV_STATUS cliresCtrlCmdSystemGetP2pCaps_IMPL ( @@ -3315,13 +3784,35 @@ cliresCtrlCmdSystemGetP2pCaps_IMPL return NV_ERR_INVALID_ARGUMENT; } + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to get blacklist information from host RM + // + if (IS_VIRTUAL(pGpu)) + { + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + return CliGetSystemP2pCaps_GSPCLIENT(pP2PParams->gpuIds, + pP2PParams->gpuCount, + &pP2PParams->p2pCaps, + &pP2PParams->p2pOptimalReadCEs, + &pP2PParams->p2pOptimalWriteCEs, + pP2PParams->p2pCapsStatus, + pP2PParams->busPeerIds); + } + } + return CliGetSystemP2pCaps(pP2PParams->gpuIds, pP2PParams->gpuCount, &pP2PParams->p2pCaps, &pP2PParams->p2pOptimalReadCEs, &pP2PParams->p2pOptimalWriteCEs, NvP64_VALUE(pP2PParams->p2pCapsStatus), - NvP64_VALUE(pP2PParams->busPeerIds)); + NvP64_VALUE(pP2PParams->busPeerIds), + NvP64_VALUE(pP2PParams->busEgmPeerIds)); } NV_STATUS @@ -3352,13 +3843,39 @@ cliresCtrlCmdSystemGetP2pCapsV2_IMPL return NV_ERR_INVALID_ARGUMENT; } + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to get blacklist information from host RM + // + if (IS_VIRTUAL(pGpu)) + { + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + // + // NOTE: If in the future we'd like to enable this path for baremetal, + // the guest GPU ID to UUID conversion needs to be extracted to here. + // + return CliGetSystemP2pCaps_GSPCLIENT(pP2PParams->gpuIds, + pP2PParams->gpuCount, + &pP2PParams->p2pCaps, + &pP2PParams->p2pOptimalReadCEs, + &pP2PParams->p2pOptimalWriteCEs, + pP2PParams->p2pCapsStatus, + pP2PParams->busPeerIds); + } + } + return CliGetSystemP2pCaps(pP2PParams->gpuIds, bLoopback ? 1 : pP2PParams->gpuCount, &pP2PParams->p2pCaps, &pP2PParams->p2pOptimalReadCEs, &pP2PParams->p2pOptimalWriteCEs, NvP64_VALUE(pP2PParams->p2pCapsStatus), - NvP64_VALUE(pP2PParams->busPeerIds)); + NvP64_VALUE(pP2PParams->busPeerIds), + NvP64_VALUE(pP2PParams->busEgmPeerIds)); } NV_STATUS @@ -3394,6 +3911,21 @@ cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL return NV_ERR_INVALID_ARGUMENT; } + // + // vGPU: + // + // Since vGPU does all real hardware management in the + // host, if we are in guest OS (where IS_VIRTUAL(pGpu) is true), + // do an RPC to the host to get blacklist information from host RM + // + if (IS_VIRTUAL(pGpu)) + { + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + return CliGetSystemP2pCapsMatrix_GSPCLIENT(pP2PParams); + } + } + groupA = pP2PParams->gpuIdGrpA; groupB = pP2PParams->gpuIdGrpB; @@ -3430,6 +3962,7 @@ cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL &pP2PParams->a2bOptimalReadCes[grpAIdx][grpBIdx], &pP2PParams->a2bOptimalWriteCes[grpAIdx][grpBIdx], NULL, + NULL, NULL); if (status != NV_OK) { @@ -3454,6 +3987,7 @@ cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL &pP2PParams->b2aOptimalReadCes[grpAIdx][grpBIdx], &pP2PParams->b2aOptimalWriteCes[grpAIdx][grpBIdx], NULL, + NULL, NULL); if (status != NV_OK) { @@ -3479,6 +4013,37 @@ cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL return status; } +NV_STATUS +cliresCtrlCmdSystemGetVgxSystemInfo_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS *pParams +) +{ + NV_STATUS status = NV_OK; + OBJGPU *pGpu = NULL; + VGPU_STATIC_INFO *pVSI; + + // Get the pGpu object + pGpu = gpumgrGetSomeGpu(); + if (pGpu == NULL) + { + return NV_ERR_INVALID_REQUEST; + } + + pVSI = GPU_GET_STATIC_INFO(pGpu); + if (pVSI) + { + portMemCopy(pParams, sizeof(pVSI->vgxSystemInfo), &pVSI->vgxSystemInfo, sizeof(pVSI->vgxSystemInfo)); + } + else + { + status = NV_ERR_NOT_SUPPORTED; + } + + return status; +} + /*! * @brief get the GPUs Power status. * @@ -3492,36 +4057,16 @@ cliresCtrlCmdSystemGetGpusPowerStatus_IMPL NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS *pGpusPowerStatus ) { - NV_STATUS status = NV_OK; - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); - OBJGPU *pGpu = NULL; - NvU32 gpuAttachCnt = 0, gpuAttachMask = 0, i = 0; - NvU32 gpuIndex = 0; - RM_API *pRmApi; - NV0080_CTRL_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT_PARAMS params = {0}; - - - pGpu = gpumgrGetSomeGpu(); - - if (pGpu == NULL) - { - return NV_ERR_INVALID_REQUEST; - } - - pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_CHECK_OK_OR_RETURN( - LEVEL_INFO, - pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalDevice, - NV0080_CTRL_CMD_INTERNAL_PERF_GET_UNDERPOWERED_GPU_COUNT, - ¶ms, - sizeof(params))); + NV_STATUS status = NV_OK; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + OBJGPU *pGpu = NULL; + NvU32 gpuAttachCnt = 0; + NvU32 gpuAttachMask = 0; + NvU32 i = 0; + NvU32 gpuIndex = 0; - pGpuMgr->powerDisconnectedGpuCount = params.powerDisconnectedGpuCount; - portMemCopy(pGpuMgr->powerDisconnectedGpuBus, sizeof(*pGpuMgr->powerDisconnectedGpuBus) * NV_MAX_DEVICES, - ¶ms.powerDisconnectedGpuBus, sizeof(*params.powerDisconnectedGpuBus) * NV_MAX_DEVICES); + portMemSet(pGpusPowerStatus, 0, sizeof(*pGpusPowerStatus)); // Loop though the GPUs with power disconnected for (gpuIndex = 0; gpuIndex < pGpuMgr->powerDisconnectedGpuCount; gpuIndex++) @@ -4196,9 +4741,10 @@ cliresCtrlCmdClientShareObject_IMPL callContext.pResourceRef = pObjectRef; callContext.secInfo = pCallContext->secInfo; - resservSwapTlsCallContext(&pOldCallContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldCallContext, &callContext)); + status = clientShareResource(pClient, pObjectRef, pSharePolicy, &callContext); - resservRestoreTlsCallContext(pOldCallContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldCallContext)); if (status != NV_OK) return status; @@ -4274,6 +4820,22 @@ cliresCtrlCmdObjectsAreDuplicates_IMPL return NV_OK; } +NV_STATUS +cliresCtrlCmdClientSubscribeToImexChannel_IMPL +( + RmClientResource *pRmCliRes, + NV0000_CTRL_CLIENT_SUBSCRIBE_TO_IMEX_CHANNEL_PARAMS *pParams +) +{ + // + // TODO: Implement channel validation. For now, return success to keep + // userspace happy. + // + pParams->channel = 0; + + return NV_OK; +} + NV_STATUS cliresCtrlCmdGpuGetMemOpEnable_IMPL ( @@ -4362,7 +4924,6 @@ cliresCtrlCmdNvdGetRcerrRpt_IMPL NvU32 gpuAttachCount = 0; NvU32 gpuIdx = 0; OBJGPU *pGpu = NULL; - NvU32 processId = osGetCurrentProcess(); NV_ASSERT_OK_OR_RETURN(gpumgrGetGpuAttachInfo(&gpuAttachCount, &gpuMask)); @@ -4377,7 +4938,7 @@ cliresCtrlCmdNvdGetRcerrRpt_IMPL pParams->flags = 0; if (!RMCFG_FEATURE_PLATFORM_GSP) { - pParams->processId = processId; + pParams->processId = osGetCurrentProcess(); } if ((status = krcCliresCtrlNvdGetRcerrRptCheckPermissions_HAL( @@ -4388,75 +4949,66 @@ cliresCtrlCmdNvdGetRcerrRpt_IMPL return status; } - if (IS_GSP_CLIENT(pGpu)) { - NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS *pLocalParams = - portMemAllocNonPaged(sizeof *pLocalParams); + Journal *pRcDB = SYS_GET_RCDB(SYS_GET_INSTANCE()); + RmRCCommonJournal_RECORD *pCommon; - NV_CHECK_OR_RETURN(LEVEL_INFO, pLocalParams != NULL, NV_ERR_NO_MEMORY); + status = rcdbGetRcDiagRecBoundaries(pRcDB, + &pParams->startIdx, + &pParams->endIdx, + pParams->owner, + pParams->processId); + if (status != NV_OK) + { + return status; + } + + pParams->flags |= NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_RANGE_VALID; - // - // Pre-GSP, RcDiagRec from all GPUs were stored in kernel sysmem in a - // single RING_BUFFER_LOG. - // - // With GSP, each GPU its own separate RING_BUFFER_LOG. We need to - // search in all of them. - // - // However, we will always return only the first matching record in all - // cases (similar to pre-GSP behavior) - // - for (; pGpu != NULL ; pGpu = gpumgrGetNextGpu(gpuMask, &gpuIdx)) { - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - portMemSet(pLocalParams, 0, sizeof(*pLocalParams)); - pLocalParams->reqIdx = pParams->reqIdx; - pLocalParams->owner = pParams->owner; - pLocalParams->processId = pParams->processId; - - status = pRmApi->Control(pRmApi, - RES_GET_CLIENT_HANDLE(pRmCliRes), - RES_GET_HANDLE(pRmCliRes), - NV0000_CTRL_CMD_NVD_GET_RCERR_RPT, - pLocalParams, - sizeof *pLocalParams); - if (status == NV_OK && - (pLocalParams->flags & - NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID)) + NV_STATUS localStatus = rcdbGetRcDiagRec(pRcDB, + pParams->reqIdx, + &pCommon, + pParams->owner, + pParams->processId); + switch (localStatus) { - // - // Each RING_BUFFER_LOG can contain MAX_RCDB_RCDIAG_WRAP_BUFF - // RmRcDiag_RECORD. We will multiply indices returned to the - // client by this value so the GPU can be uniquely identified - // (in addition to GPUTag) from - // NV0000_CTRL_CMD_NVD_GET_RCERR_RPT_PARAMS.rptIdx - // - // Note that this will result in clients receivinga rptIdx value - // larger than MAX_RCDB_RCDIAG_WRAP_BUFF. - // - NvU16 indexOffset = pGpu->gpuInstance * MAX_RCDB_RCDIAG_WRAP_BUFF; - - *pParams = *pLocalParams; - pParams->startIdx += indexOffset; - pParams->endIdx += indexOffset; - pParams->rptIdx += indexOffset; - - break; + case NV_OK: + break; + case NV_ERR_BUSY_RETRY: + return localStatus; + default: + return status; } + } - if (status == NV_ERR_BUSY_RETRY) + if (pCommon != NULL) + { + NvU32 i = 0; + RmRcDiag_RECORD *pRecord = (RmRcDiag_RECORD *)&pCommon[1]; + + pParams->GPUTag = pCommon->GPUTag; + pParams->rptIdx = pRecord->idx; + pParams->rptTime = pRecord->timeStamp; + pParams->rptType = pRecord->type; + pParams->rptCount = pRecord->count; + pParams->flags |= pRecord->flags; + + for (i = 0; i < pRecord->count; ++i) { - // - // To avoid the case where we silently fail to find a record - // because we skipped over to the next Gpu on getting a - // BUSY_RETRY on one of the Gpus (which might have contained the - // record). - // - break; + pParams->report[i].tag = pRecord->data[i].tag; + pParams->report[i].value = pRecord->data[i].value; + pParams->report[i].attribute = pRecord->data[i].attribute; } + for (; i < NV0000_CTRL_CMD_NVD_RCERR_RPT_MAX_ENTRIES; ++i) + { + pParams->report[i].tag = + NV0000_CTRL_CMD_NVD_RCERR_RPT_REG_EMPTY; + pParams->report[i].value = 0; + pParams->report[i].attribute = 0; + } + pParams->flags |= NV0000_CTRL_CMD_NVD_RCERR_RPT_FLAGS_DATA_VALID; } - - portMemFree(pLocalParams); - pLocalParams = NULL; } return status; diff --git a/src/nvidia/src/kernel/rmapi/client_resource_sli.c b/src/nvidia/src/kernel/rmapi/client_resource_sli.c index d2b573d07a..bec666ab8f 100644 --- a/src/nvidia/src/kernel/rmapi/client_resource_sli.c +++ b/src/nvidia/src/kernel/rmapi/client_resource_sli.c @@ -26,6 +26,7 @@ #include "rmapi/client_resource.h" #include "platform/sli/sli.h" +#include "gpu_mgr/gpu_mgr.h" #include "resserv/rs_client.h" #include "resserv/rs_server.h" #include "resserv/rs_access_map.h" diff --git a/src/nvidia/src/kernel/rmapi/control.c b/src/nvidia/src/kernel/rmapi/control.c index f7989fe822..13e57bd1f3 100644 --- a/src/nvidia/src/kernel/rmapi/control.c +++ b/src/nvidia/src/kernel/rmapi/control.c @@ -33,22 +33,13 @@ #include "entry_points.h" #include "resserv/rs_access_map.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" -#include "gpu/subdevice/subdevice.h" +#include "rmapi/rmapi_specific.h" #include "rmapi/rmapi_utils.h" -#include "ctrl/ctrl0000/ctrl0000client.h" // NV0000_CTRL_CMD_CLIENT_* -#include "ctrl/ctrl0000/ctrl0000gpu.h" // NV0000_CTRL_CMD_GPU_* -#include "ctrl/ctrl0000/ctrl0000system.h" // NV0000_CTRL_CMD_SYSTEM_* -#include "ctrl/ctrl0000/ctrl0000syncgpuboost.h" // NV0000_CTRL_CMD_SYNC_GPU_BOOST_* -#include "ctrl/ctrl0000/ctrl0000nvd.h" // NV0000_CTRL_CMD_NVD_* -#include "ctrl/ctrl2080/ctrl2080rc.h" // NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM -#include "ctrl/ctrl0002.h" // N09002_CTRL_CMD_*_CONTEXTDMA -#include "ctrl/ctrl906f.h" // NV906F_CTRL_CMD_GET_MMU_FAULT_INFO -#include "ctrl/ctrlc370/ctrlc370chnc.h" // NVC370_CTRL_CMD_* -#include "ctrl/ctrl9010.h" //NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION -#include "ctrl/ctrl2080/ctrl2080tmr.h" // NV2080_CTRL_CMD_TIMER_* #include "ctrl/ctrl0000/ctrl0000gpuacct.h" // NV0000_CTRL_CMD_GPUACCT_* +#include "ctrl/ctrl2080/ctrl2080tmr.h" // NV2080_CTRL_CMD_TIMER_SCHEDULE static NV_STATUS releaseDeferRmCtrlBuffer(RmCtrlDeferredCmd* pRmCtrlDeferredCmd) @@ -274,7 +265,9 @@ serverControlApiCopyIn rmStatus = embeddedParamCopyIn(pEmbeddedParamCopies, pRmCtrlParams); if (rmStatus != NV_OK) + { return rmStatus; + } pCookie->bFreeEmbeddedCopy = NV_TRUE; return NV_OK; @@ -349,43 +342,6 @@ serverControlApiCopyOut return rmStatus; } -static NvBool _rmapiRmControlCanBeRaisedIrql(NvU32 cmd) -{ - switch (cmd) - { - case NV2080_CTRL_CMD_TIMER_SCHEDULE: - case NV2080_CTRL_CMD_TIMER_GET_TIME: - // Below 2 control calls are used for flip canceling (HW Flip Queue) - // We use TRASH/ABORT mode to discard queued hw commands in the push buffer (bug 200644346) - case NVC370_CTRL_CMD_SET_ACCL: - case NVC370_CTRL_CMD_GET_CHANNEL_INFO: - case NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION: - return NV_TRUE; - default: - return NV_FALSE; - } -} - -static NvBool _rmapiRmControlCanBeBypassLock(NvU32 cmd) -{ - switch (cmd) - { - case NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM: - case NV2080_CTRL_CMD_TIMER_GET_TIME: - case NV906F_CTRL_CMD_GET_MMU_FAULT_INFO: - // Below 2 control calls are used for flip canceling (HW Flip Queue) - // We use TRASH/ABORT mode to discard queued hw commands in the push buffer (bug 200644346) - case NVC370_CTRL_CMD_SET_ACCL: - case NVC370_CTRL_CMD_GET_CHANNEL_INFO: - case NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS: - case NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION: - case NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA: - return NV_TRUE; - default: - return NV_FALSE; - } -} - static NV_STATUS _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams, NvU32 paramsSize, NvU32 flags, RM_API *pRmApi, API_SECURITY_INFO *pSecInfo) { @@ -433,7 +389,7 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams if (bIsRaisedIrqlCmd) { // Check that we support this control call at raised IRQL - if (!_rmapiRmControlCanBeRaisedIrql(cmd)) + if (!rmapiRmControlCanBeRaisedIrql(cmd)) { NV_PRINTF(LEVEL_WARNING, "rmControl: cmd 0x%x cannot be called at raised irq level\n", cmd); @@ -457,7 +413,7 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams if (!bInternalRequest) { // Check that we support bypassing locks with this control call - if (!_rmapiRmControlCanBeBypassLock(cmd)) + if (!rmapiRmControlCanBeBypassLock(cmd)) { NV_PRINTF(LEVEL_WARNING, "rmControl: cmd 0x%x cannot bypass locks\n", cmd); @@ -487,8 +443,9 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams } // error check parameters - if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) || - ((paramsSize == 0) && (pUserParams != (NvP64) 0))) + if (((paramsSize != 0) && (pUserParams == (NvP64) 0)) || + ((paramsSize == 0) && (pUserParams != (NvP64) 0)) + ) { NV_PRINTF(LEVEL_WARNING, "bad params: ptr " NvP64_fmt " size: 0x%x\n", pUserParams, paramsSize); @@ -530,6 +487,8 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams rmCtrlParams.pCookie->apiCopyFlags |= RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER; } + rmCtrlParams.pCookie->ctrlFlags = ctrlFlags; + // // Three separate rmctrl command modes: // @@ -628,7 +587,18 @@ _rmapiRmControl(NvHandle hClient, NvHandle hObject, NvU32 cmd, NvP64 pUserParams // if (bInternalRequest && resservGetTlsCallContext() != NULL) { - rmStatus = rmapiInitLockInfo(pRmApi, hClient, NV01_NULL_OBJECT, &lockInfo); + NvHandle hSecondClient = NV01_NULL_OBJECT; + + if (pSecInfo->paramLocation == PARAM_LOCATION_KERNEL) + { + rmStatus = serverControlLookupSecondClient(cmd, + NvP64_VALUE(pUserParams), rmCtrlParams.pCookie, &hSecondClient); + + if (rmStatus != NV_OK) + goto epilogue; + } + + rmStatus = rmapiInitLockInfo(pRmApi, hClient, hSecondClient, &lockInfo); if (rmStatus != NV_OK) goto epilogue; @@ -753,6 +723,18 @@ NV_STATUS serverControl_ValidateCookie } } + if (pRmCtrlParams->pGpu != NULL && IS_VIRTUAL(pRmCtrlParams->pGpu) && + (pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) && + !(pRmCtrlExecuteCookie->ctrlFlags & (RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST | RMCTRL_FLAGS_PHYSICAL_IMPLEMENTED_ON_VGPU_GUEST))) + { + if (!rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(pRmCtrlParams->cmd)) + { + NV_PRINTF(LEVEL_ERROR, "Unsupported ROUTE_TO_PHYSICAL control 0x%x was called on vGPU guest\n", pRmCtrlParams->cmd); + } + + return NV_ERR_NOT_SUPPORTED; + } + if ((pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_INTERNAL)) { NvBool bInternalCall = pRmCtrlParams->bInternal; @@ -868,6 +850,8 @@ serverControlLookupLockFlags "rmapiutilGetControlInfo(cmd=0x%x, out flags=0x%x, NULL) = status=0x%x\n", pRmCtrlParams->cmd, controlFlags, status); } + + pRmCtrlExecuteCookie->ctrlFlags = controlFlags; } NvBool areAllGpusInOffloadMode = gpumgrAreAllGpusInOffloadMode(); diff --git a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c index 53cb82f1ff..347268f017 100644 --- a/src/nvidia/src/kernel/rmapi/embedded_param_copy.c +++ b/src/nvidia/src/kernel/rmapi/embedded_param_copy.c @@ -50,6 +50,7 @@ #include "ctrl/ctrl208f/ctrl208fgpu.h" #include "ctrl/ctrl402c.h" #include "ctrl/ctrl0073.h" +#include "ctrl/ctrla0bc.h" #include "ctrl/ctrlb06f.h" #include "ctrl/ctrl83de.h" #ifdef USE_AMAPLIB @@ -212,8 +213,7 @@ static NV_STATUS i2cTransactionCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlPara */ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCtrlParams) { - NV_STATUS status = NV_OK; - NV_STATUS statusCleanUp = NV_OK; + NV_STATUS status = NV_OK; void* pParams = pRmCtrlParams->pParams; NvU32 paramsCnt = 1; NvU32 i, j = 0; @@ -226,6 +226,19 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt switch (pRmCtrlParams->cmd) { + case NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS); + + RMAPI_PARAM_COPY_INIT(paramCopies[0], + ((NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS*)pParams)->sessionInfoTbl, + ((NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS*)pParams)->sessionInfoTbl, + ((NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_PARAMS*)pParams)->sessionInfoTblEntry, + sizeof(NV2080_CTRL_NVENC_SW_SESSION_INFO)); + paramCopies[0].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN; + + break; + } case NV2080_CTRL_CMD_GPU_GET_ENGINES: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV2080_CTRL_GPU_GET_ENGINES_PARAMS); @@ -454,6 +467,17 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt break; } + case NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS); + + RMAPI_PARAM_COPY_INIT(paramCopies[0], + ((NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS*)pParams)->timestampBuffer, + ((NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS*)pParams)->timestampBuffer, + ((NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS*)pParams)->timestampBufferSize, + sizeof(NVA0BC_CTRL_NVENC_TIMESTAMP)); + break; + } case NV83DE_CTRL_CMD_DEBUG_READ_MEMORY: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV83DE_CTRL_DEBUG_READ_MEMORY_PARAMS); @@ -754,11 +778,11 @@ NV_STATUS embeddedParamCopyIn(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCt for (j = 0; j <= i; j++) { paramCopies[j].flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT; - statusCleanUp = rmapiParamsRelease(¶mCopies[j]); + rmapiParamsRelease(¶mCopies[j]); } } - return (status == NV_OK) ? statusCleanUp : status; + return status; } NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmCtrlParams) @@ -978,6 +1002,14 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *paramCopies, RmCtrlParams *pRmC ((NV0080_CTRL_FIFO_GET_CAPS_PARAMS*)pParams)->capsTbl = paramCopies[0].pUserParams; break; } + case NVA0BC_CTRL_CMD_NVENC_SW_SESSION_UPDATE_INFO: + { + CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS); + + status = rmapiParamsRelease(¶mCopies[0]); + ((NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS*)pParams)->timestampBuffer = paramCopies[0].pUserParams; + break; + } case NV402C_CTRL_CMD_I2C_INDEXED: { CHECK_PARAMS_OR_RETURN(pRmCtrlParams, NV402C_CTRL_I2C_INDEXED_PARAMS); diff --git a/src/nvidia/src/kernel/rmapi/entry_points.c b/src/nvidia/src/kernel/rmapi/entry_points.c index decf23a53f..a44b6d7eb3 100644 --- a/src/nvidia/src/kernel/rmapi/entry_points.c +++ b/src/nvidia/src/kernel/rmapi/entry_points.c @@ -470,7 +470,7 @@ static void _nv04UnmapMemoryDma XlateUserModeArgsToSecInfo(bUserModeArgs, NV_FALSE, &secInfo); pArgs->status = pRmApi->UnmapWithSecInfo(pRmApi, pArgs->hClient, pArgs->hDevice, pArgs->hDma, - pArgs->hMemory, pArgs->flags, pArgs->dmaOffset, &secInfo); + pArgs->flags, pArgs->dmaOffset, pArgs->size, &secInfo); } // end of Nv04UnmapMemoryDma() static void _nv04UnmapMemoryDmaWithSecInfo @@ -483,7 +483,7 @@ static void _nv04UnmapMemoryDmaWithSecInfo RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL); pArgs->status = pRmApi->UnmapWithSecInfo(pRmApi, pArgs->hClient, pArgs->hDevice, pArgs->hDma, - pArgs->hMemory, pArgs->flags, pArgs->dmaOffset, &secInfo); + pArgs->flags, pArgs->dmaOffset, pArgs->size, &secInfo); } /* diff --git a/src/nvidia/src/kernel/rmapi/entry_points.h b/src/nvidia/src/kernel/rmapi/entry_points.h index 9cf33a5f55..0ab2b55402 100644 --- a/src/nvidia/src/kernel/rmapi/entry_points.h +++ b/src/nvidia/src/kernel/rmapi/entry_points.h @@ -397,9 +397,9 @@ rmapiUnmap NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, - NvHandle hMemory, NvU32 flags, - NvU64 dmaOffset + NvU64 dmaOffset, + NvU64 size ); NV_STATUS @@ -409,9 +409,9 @@ rmapiUnmapWithSecInfo NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, - NvHandle hMemory, NvU32 flags, NvU64 dmaOffset, + NvU64 size, API_SECURITY_INFO *pSecInfo ); @@ -422,9 +422,9 @@ rmapiUnmapWithSecInfoTls NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, - NvHandle hMemory, NvU32 flags, NvU64 dmaOffset, + NvU64 size, API_SECURITY_INFO *pSecInfo ); diff --git a/src/nvidia/src/kernel/rmapi/event.c b/src/nvidia/src/kernel/rmapi/event.c index 0592fbe4e6..f4b0254a1c 100644 --- a/src/nvidia/src/kernel/rmapi/event.c +++ b/src/nvidia/src/kernel/rmapi/event.c @@ -38,9 +38,7 @@ #include "ctrl/ctrl0000/ctrl0000event.h" // NV0000_CTRL_EVENT_SET_NOTIFICATION_ACTION_* -#if (!NV_RM_STUB_RPC) static NV_STATUS _eventRpcForType(NvHandle hClient, NvHandle hObject); -#endif NV_STATUS eventConstruct_IMPL @@ -89,7 +87,6 @@ eventConstruct_IMPL } } -#if (!NV_RM_STUB_RPC) if (_eventRpcForType(hParentClient, pNv0050AllocParams->hSrcResource)) { RsResourceRef *pSrcRef; @@ -112,7 +109,6 @@ eventConstruct_IMPL } } } -#endif NV_ASSERT_OK_OR_RETURN(clientGetResourceRef(pRsClient, pRsClient->hClient, &pClientRef)); @@ -264,7 +260,6 @@ NV_STATUS notifyUnregisterEvent_IMPL if (*ppEventNotification != NULL) { -#if (!NV_RM_STUB_RPC) if (_eventRpcForType(hNotifierClient, hNotifierResource)) { OBJGPU *pGpu = CliGetGpuFromHandle(hNotifierClient, hNotifierResource, NULL); @@ -309,7 +304,6 @@ NV_STATUS notifyUnregisterEvent_IMPL hNotifierClient, hNotifierResource); } } -#endif unregisterEventNotification(ppEventNotification, hEventClient, @@ -643,7 +637,6 @@ void CliAddSystemEvent( return; } -#if (!NV_RM_STUB_RPC) static NV_STATUS _eventRpcForType(NvHandle hClient, NvHandle hObject) { @@ -670,4 +663,50 @@ _eventRpcForType(NvHandle hClient, NvHandle hObject) return NV_FALSE; } -#endif + +NV_STATUS +eventGetByHandle_IMPL +( + RsClient *pClient, + NvHandle hEvent, + NvU32 *pNotifyIndex +) +{ + RsResourceRef *pEventResourceRef; + NV_STATUS status; + Event *pEvent; + NotifShare *pNotifierShare; + PEVENTNOTIFICATION pEventNotification; + + *pNotifyIndex = NV2080_NOTIFIERS_MAXCOUNT; + + status = clientGetResourceRef(pClient, hEvent, &pEventResourceRef); + if (status != NV_OK) + return status; + + pEvent = dynamicCast(pEventResourceRef->pResource, Event); + if (pEvent == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Event is null \n"); + return NV_ERR_INVALID_ARGUMENT; + } + + // TODO: Check existing notifiers in that event + pNotifierShare = pEvent->pNotifierShare; + if ((pNotifierShare == NULL) || (pNotifierShare->pNotifier == NULL)) + { + NV_PRINTF(LEVEL_ERROR, "pNotifierShare or pNotifier is NULL \n"); + return NV_ERR_INVALID_ARGUMENT; + } + + pEventNotification = inotifyGetNotificationList(pNotifierShare->pNotifier); + if (pEventNotification == NULL) + { + NV_PRINTF(LEVEL_ERROR, "pEventNotification is NULL \n"); + return NV_ERR_INVALID_ARGUMENT; + } + + *pNotifyIndex = pEventNotification->NotifyIndex; + + return status; +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/rmapi/event_buffer.c b/src/nvidia/src/kernel/rmapi/event_buffer.c index 5675c45028..f623eb30a6 100644 --- a/src/nvidia/src/kernel/rmapi/event_buffer.c +++ b/src/nvidia/src/kernel/rmapi/event_buffer.c @@ -34,9 +34,11 @@ #include "rmapi/rs_utils.h" #include "rmapi/rmapi_utils.h" #include "kernel/gpu/gr/fecs_event_list.h" +#include "gpu/bus/kern_bus.h" #include "mem_mgr/no_device_mem.h" #include "class/cl90ce.h" #include "class/cl0040.h" +#include "gpu/gsp/gsp_trace_rats_macro.h" static NV_STATUS _allocAndMapMemory(CALL_CONTEXT *pCallContext, NvP64 pAddress, MEMORY_DESCRIPTOR** ppMemDesc, NvU64 size, NvBool bKernel, NvP64* pKernelAddr, NvP64* pKernelPriv, NvP64* pUserAddr, NvP64* pUserPriv); @@ -136,7 +138,7 @@ eventbufferConstruct_IMPL pEventBuffer->hClient = pCallContext->pClient->hClient; pEventBuffer->hSubDevice = pAllocParams->hSubDevice; - if (pEventBuffer->hSubDevice) + if (pEventBuffer->hSubDevice != 0) { status = subdeviceGetByHandle(pCallContext->pClient, pEventBuffer->hSubDevice, &pSubdevice); if (status != NV_OK) @@ -185,6 +187,23 @@ eventbufferConstruct_IMPL { Memory *pMemory; NvBool bRequireReadOnly = bUsingVgpuStagingBuffer || !bKernel; + NvU32 flags = 0; + + // Allow the mapping to succeed when HCC is enabled in devtools mode + if (kbusIsBarAccessBlocked(GPU_GET_KERNEL_BUS(pGpu)) && + gpuIsCCDevToolsModeEnabled(pGpu)) + { + flags = FLD_SET_DRF(OS33, _FLAGS, _ALLOW_MAPPING_ON_HCC, _YES, flags); + } + + if (bUsingVgpuStagingBuffer) + { + flags = FLD_SET_DRF(OS33, _FLAGS, _ACCESS, _READ_ONLY, flags); + } + else + { + flags = FLD_SET_DRF(OS33, _FLAGS, _ACCESS, _READ_WRITE, flags); + } // // Buffer header @@ -208,7 +227,8 @@ eventbufferConstruct_IMPL RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if ((!bKernel) && bUsingVgpuStagingBuffer) + // Dup memory object under CPU-RM's hClient + if (!bKernel) { status = pRmApi->DupObject(pRmApi, hMapperClient, @@ -229,9 +249,7 @@ eventbufferConstruct_IMPL 0, pMemory->Length, &pKernelMap->headerAddr, - bUsingVgpuStagingBuffer - ? DRF_DEF(OS33, _FLAGS, _ACCESS, _READ_ONLY) - : DRF_DEF(OS33, _FLAGS, _ACCESS, _READ_WRITE)); + flags); if (status != NV_OK) { @@ -269,7 +287,8 @@ eventbufferConstruct_IMPL RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if ((!bKernel) && bUsingVgpuStagingBuffer) + // Dup memory object under CPU-RM's hClient + if (!bKernel) { status = pRmApi->DupObject(pRmApi, hMapperClient, @@ -290,9 +309,7 @@ eventbufferConstruct_IMPL 0, pMemory->Length, &pKernelMap->recordBuffAddr, - bUsingVgpuStagingBuffer - ? DRF_DEF(OS33, _FLAGS, _ACCESS, _READ_ONLY) - : DRF_DEF(OS33, _FLAGS, _ACCESS, _READ_WRITE)); + flags); if (status != NV_OK) { goto cleanup; @@ -330,7 +347,8 @@ eventbufferConstruct_IMPL RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); NvHandle hMemory = RES_GET_HANDLE(pMemory); - if ((!bKernel) && bUsingVgpuStagingBuffer) + // Dup memory object under CPU-RM's hClient + if (!bKernel) { status = pRmApi->DupObject(pRmApi, hMapperClient, @@ -351,9 +369,7 @@ eventbufferConstruct_IMPL 0, pMemory->Length, &pKernelMap->recordBuffAddr, - bUsingVgpuStagingBuffer - ? DRF_DEF(OS33, _FLAGS, _ACCESS, _READ_ONLY) - : DRF_DEF(OS33, _FLAGS, _ACCESS, _READ_WRITE)); + flags); if (status != NV_OK) { goto cleanup; @@ -478,6 +494,9 @@ eventbufferDestruct_IMPL // Clean-up all bind points videoRemoveAllBindpoints(pEventBuffer); fecsRemoveAllBindpoints(pEventBuffer); +#if KERNEL_GSP_TRACING_RATS_ENABLED + gspTraceRemoveAllBindpoints(pEventBuffer); +#endif _unmapAndFreeMemory(pEventBuffer->pHeaderDesc, bKernel, pKernelMap->headerAddr, pKernelMap->headerPriv, pClientMap->headerAddr, pClientMap->headerPriv); diff --git a/src/nvidia/src/kernel/rmapi/event_notification.c b/src/nvidia/src/kernel/rmapi/event_notification.c index 97187e0705..9081228746 100644 --- a/src/nvidia/src/kernel/rmapi/event_notification.c +++ b/src/nvidia/src/kernel/rmapi/event_notification.c @@ -29,6 +29,7 @@ ****************************************************************************/ #include "core/core.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_desc.h" #include "class/cl0000.h" @@ -38,6 +39,7 @@ #include "rmapi/rs_utils.h" #include "mem_mgr/mem.h" #include "kernel/gpu/gpu_engine_type.h" +#include "platform/sli/sli.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" diff --git a/src/nvidia/src/kernel/rmapi/mapping.c b/src/nvidia/src/kernel/rmapi/mapping.c index 0ebeb5ff62..a4564051a6 100644 --- a/src/nvidia/src/kernel/rmapi/mapping.c +++ b/src/nvidia/src/kernel/rmapi/mapping.c @@ -31,6 +31,7 @@ #include "rmapi/rs_utils.h" #include "entry_points.h" +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_desc.h" #include "gpu/mem_mgr/mem_mgr.h" @@ -152,7 +153,6 @@ serverInterMap_Prologue pPrivate->pSrcGpu = memInterMapParams.pSrcGpu; pPrivate->hMemoryDevice = memInterMapParams.hMemoryDevice; - pPrivate->bDmaMapNeeded = memInterMapParams.bDmaMapNeeded; pPrivate->bFlaMapping = memInterMapParams.bFlaMapping; // Check length for overflow and against the physical memory size. @@ -284,39 +284,31 @@ _rmapiRmUnmapMemoryDma NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, - NvHandle hMemory, NvU32 flags, NvU64 dmaOffset, + NvU64 size, RS_LOCK_INFO *pLockInfo, API_SECURITY_INFO *pSecInfo ) { RsClient *pRsClient = NULL; - MEMORY_DESCRIPTOR *pMemDesc = NULL; - Memory *pMemory = NULL; RS_INTER_UNMAP_PARAMS params; RS_INTER_UNMAP_PRIVATE private; NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hClient, &pRsClient)); - // Translate hMemory to pMemDesc - if (memGetByHandle(pRsClient, hMemory, &pMemory) == NV_OK) - { - pMemDesc = pMemory->pMemDesc; - } - portMemSet(¶ms, 0, sizeof(params)); params.hClient = hClient; params.hMapper = hMemCtx; params.hDevice = hDevice; - params.hMappable = hMemory; params.flags = flags; params.dmaOffset = dmaOffset; - params.pMemDesc = pMemDesc; params.pLockInfo = pLockInfo; params.pSecInfo = pSecInfo; + params.size = size; + portMemSet(&private, 0, sizeof(private)); params.pPrivate = &private; @@ -463,16 +455,16 @@ rmapiUnmap NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, - NvHandle hMemory, NvU32 flags, - NvU64 dmaOffset + NvU64 dmaOffset, + NvU64 size ) { if (!pRmApi->bHasDefaultSecInfo) return NV_ERR_NOT_SUPPORTED; - return pRmApi->UnmapWithSecInfo(pRmApi, hClient, hDevice, hMemCtx, hMemory, - flags, dmaOffset, &pRmApi->defaultSecInfo); + return pRmApi->UnmapWithSecInfo(pRmApi, hClient, hDevice, hMemCtx, + flags, dmaOffset, size, &pRmApi->defaultSecInfo); } NV_STATUS @@ -482,9 +474,9 @@ rmapiUnmapWithSecInfo NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, - NvHandle hMemory, NvU32 flags, NvU64 dmaOffset, + NvU64 size, API_SECURITY_INFO *pSecInfo ) { @@ -493,10 +485,10 @@ rmapiUnmapWithSecInfo RS_LOCK_INFO lockInfo; NV_PRINTF(LEVEL_INFO, - "Nv04Unmap: client:0x%x device:0x%x context:0x%x memory:0x%x\n", - hClient, hDevice, hMemCtx, hMemory); - NV_PRINTF(LEVEL_INFO, "Nv04Unmap: flags:0x%x dmaOffset:0x%08llx\n", - flags, dmaOffset); + "Nv04Unmap: client:0x%x device:0x%x context:0x%x\n", + hClient, hDevice, hMemCtx); + NV_PRINTF(LEVEL_INFO, "Nv04Unmap: flags:0x%x dmaOffset:0x%08llx size:0x%llx\n", + flags, dmaOffset, size); status = rmapiPrologue(pRmApi, &rmApiContext); if (status != NV_OK) @@ -515,8 +507,8 @@ rmapiUnmapWithSecInfo LOCK_METER_DATA(UNMAPMEM_DMA, flags, 0, 0); // Unmap DMA memory - status = _rmapiRmUnmapMemoryDma(hClient, hDevice, hMemCtx, hMemory, flags, - dmaOffset, &lockInfo, pSecInfo); + status = _rmapiRmUnmapMemoryDma(hClient, hDevice, hMemCtx, flags, + dmaOffset, size, &lockInfo, pSecInfo); rmapiEpilogue(pRmApi, &rmApiContext); @@ -541,9 +533,9 @@ rmapiUnmapWithSecInfoTls NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, - NvHandle hMemory, NvU32 flags, NvU64 dmaOffset, + NvU64 size, API_SECURITY_INFO *pSecInfo ) { @@ -552,7 +544,7 @@ rmapiUnmapWithSecInfoTls threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - status = rmapiUnmapWithSecInfo(pRmApi, hClient, hDevice, hMemCtx, hMemory, flags, dmaOffset, pSecInfo); + status = rmapiUnmapWithSecInfo(pRmApi, hClient, hDevice, hMemCtx, flags, dmaOffset, size, pSecInfo); threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); diff --git a/src/nvidia/src/kernel/rmapi/mapping_cpu.c b/src/nvidia/src/kernel/rmapi/mapping_cpu.c index e7bfb85a5f..e863629930 100644 --- a/src/nvidia/src/kernel/rmapi/mapping_cpu.c +++ b/src/nvidia/src/kernel/rmapi/mapping_cpu.c @@ -242,17 +242,27 @@ memMap_IMPL } } - if ((pGpu != NULL) && (pMemoryInfo->Flags & NVOS32_ALLOC_FLAGS_PROTECTED)) + if ((pGpu != NULL) && gpuIsCCFeatureEnabled(pGpu) && + (pMemoryInfo->Flags & NVOS32_ALLOC_FLAGS_PROTECTED)) { ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu); // // If neither BAR1 nor PCIE as a whole is trusted, fail the mapping // for allocations in CPR region. Mapping should still succeed for // allocations in non-CPR region + // Deny BAR1 access to CPU-RM by default irrespective of prod or devtools + // mode. Some mappings made by CPU-RM may be allowed to go thorough in + // devtools mode. + // However, allow the mapping to go through on platforms where GSP-DMA + // is not present e.g. MODS. User may have also set a regkey to force + // BAR accesses. // - if ((pCC != NULL) && !pCC->ccStaticInfo.bIsBar1Trusted && - !pCC->ccStaticInfo.bIsPcieTrusted) + if (((pCC != NULL) && !pCC->ccStaticInfo.bIsBar1Trusted && + !pCC->ccStaticInfo.bIsPcieTrusted) || + (IS_GSP_CLIENT(pGpu) && pMapParams->bKernel && !pKernelBus->bForceBarAccessOnHcc && + FLD_TEST_DRF(OS33, _FLAGS, _ALLOW_MAPPING_ON_HCC, _NO, pMapParams->flags))) { + NV_PRINTF(LEVEL_ERROR, "BAR1 mapping to CPR vidmem not supported\n"); NV_ASSERT(0); return NV_ERR_NOT_SUPPORTED; } @@ -482,7 +492,7 @@ memMap_IMPL pMemDesc = memdescGetMemDescFromGpu(pMemDesc, pGpu); // WAR for Bug 3564398, need to allocate doorbell for windows differently - if (RMCFG_FEATURE_PLATFORM_WINDOWS_LDDM && + if (RMCFG_FEATURE_PLATFORM_WINDOWS && memdescGetFlag(pMemDesc, MEMDESC_FLAGS_MAP_SYSCOH_OVER_BAR1)) { busMapFbFlags |= BUS_MAP_FB_FLAGS_MAP_DOWNWARDS; diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c index a1d816aa77..ecec3adda2 100644 --- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c +++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c @@ -21,9 +21,6 @@ * DEALINGS IN THE SOFTWARE. */ -// FIXME XXX -#define NVOC_GPU_INSTANCE_SUBSCRIPTION_H_PRIVATE_ACCESS_ALLOWED - #include "core/prelude.h" @@ -38,6 +35,7 @@ #include #include // KEPLER_CHANNEL_GROUP_A #include +#include #include #include #include @@ -87,6 +85,7 @@ #include #include #include +#include #include #include #include @@ -129,6 +128,7 @@ #include #include #include +#include #include #include @@ -365,6 +365,9 @@ struct systemP2PCaps // peerId[i] contains gpu[i]'s peer id of gpu[1 - i] NvU32 peerIds[2]; + // egmPeerId[i] contains gpu[i]'s peer id of gpu[1 - i] + NvU32 egmPeerIds[2]; + // true if the two GPUs are direct NvLink or PCIe peers NvU32 accessSupported : 1; @@ -1278,7 +1281,7 @@ static NV_STATUS getSwizzIdFromSmcPartHandle(RM_API *pRmApi, if (!pGPUInstanceSubscription) return NV_ERR_INVALID_OBJECT; - *swizzId = pGPUInstanceSubscription->pKernelMIGGpuInstance->swizzId; + *swizzId = gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription)->swizzId; return NV_OK; } @@ -1421,9 +1424,9 @@ static NV_STATUS nvGpuOpsRmSmcPartitionCreate(struct gpuDevice *device, const gp pGPUInstanceSubscription = dynamicCast(pSmcResourceRef->pResource, GPUInstanceSubscription); NV_ASSERT(pGPUInstanceSubscription != NULL); - NV_ASSERT(pGPUInstanceSubscription->pKernelMIGGpuInstance->swizzId == pGpuInfo->smcSwizzId); + NV_ASSERT(gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription)->swizzId == pGpuInfo->smcSwizzId); - rmSubDevice->smcPartition.info = pGPUInstanceSubscription->pKernelMIGGpuInstance; + rmSubDevice->smcPartition.info = gisubscriptionGetMIGGPUInstance(pGPUInstanceSubscription); return NV_OK; @@ -1564,38 +1567,29 @@ static UVM_LINK_TYPE rmControlToUvmNvlinkVersion(NvU32 nvlinkVersion) static NV_STATUS queryFbInfo(struct gpuDevice *device) { NV_STATUS nvStatus = NV_OK; - NV2080_CTRL_FB_GET_INFO_PARAMS fbInfoParams; + NV2080_CTRL_FB_GET_INFO_V2_PARAMS fbInfoParams; NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS *fbRegionInfoParams; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); NvU32 i; - struct fbInputParams - { - NV2080_CTRL_FB_INFO heapSize; - NV2080_CTRL_FB_INFO reservedHeapSize; - NV2080_CTRL_FB_INFO zeroFb; - } fbParams; - fbRegionInfoParams = portMemAllocNonPaged(sizeof(*fbRegionInfoParams)); if (fbRegionInfoParams == NULL) return NV_ERR_NO_MEMORY; portMemSet(fbRegionInfoParams, 0, sizeof(*fbRegionInfoParams)); portMemSet(&fbInfoParams, 0, sizeof(fbInfoParams)); - portMemSet(&fbParams, 0, sizeof(fbParams)); // Set up the list of parameters we are looking to extract - fbParams.heapSize.index = NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE; - fbParams.reservedHeapSize.index = NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE; - fbParams.zeroFb.index = NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN; + fbInfoParams.fbInfoList[0].index = NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE; + fbInfoParams.fbInfoList[1].index = NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE; + fbInfoParams.fbInfoList[2].index = NV2080_CTRL_FB_INFO_INDEX_FB_IS_BROKEN; - fbInfoParams.fbInfoListSize = sizeof(fbParams) / sizeof(fbParams.heapSize); - fbInfoParams.fbInfoList = NV_PTR_TO_NvP64(&fbParams); + fbInfoParams.fbInfoListSize = 3; nvStatus = pRmApi->Control(pRmApi, device->session->handle, device->subhandle, - NV2080_CTRL_CMD_FB_GET_INFO, + NV2080_CTRL_CMD_FB_GET_INFO_V2, &fbInfoParams, sizeof(fbInfoParams)); if (nvStatus != NV_OK) @@ -1610,9 +1604,9 @@ static NV_STATUS queryFbInfo(struct gpuDevice *device) if (nvStatus != NV_OK) goto out; - device->fbInfo.heapSize = fbParams.heapSize.data; - device->fbInfo.reservedHeapSize = fbParams.reservedHeapSize.data; - device->fbInfo.bZeroFb = (NvBool)fbParams.zeroFb.data; + device->fbInfo.heapSize = fbInfoParams.fbInfoList[0].data; + device->fbInfo.reservedHeapSize = fbInfoParams.fbInfoList[1].data; + device->fbInfo.bZeroFb = (NvBool)fbInfoParams.fbInfoList[2].data; device->fbInfo.maxAllocatableAddress = 0; @@ -2007,6 +2001,7 @@ static NV_STATUS getAddressSpaceInfo(struct gpuAddressSpace *vaSpace, NV_STATUS nvGpuOpsAddressSpaceCreate(struct gpuDevice *device, NvU64 vaBase, NvU64 vaSize, + NvBool enableAts, struct gpuAddressSpace **vaSpace, UvmGpuAddressSpaceInfo *vaSpaceInfo) { @@ -2033,12 +2028,16 @@ NV_STATUS nvGpuOpsAddressSpaceCreate(struct gpuDevice *device, portMemSet(vaSpaceInfo, 0, sizeof(*vaSpaceInfo)); // Create a new vaSpace object - vaParams.index= NV_VASPACE_ALLOCATION_INDEX_GPU_NEW; + vaParams.index = NV_VASPACE_ALLOCATION_INDEX_GPU_NEW; vaParams.vaBase = gpuVaSpace->vaBase; vaParams.vaSize = gpuVaSpace->vaSize; vaParams.flags = gpuVaSpace->vaSize ? NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT : NV_VASPACE_ALLOCATION_FLAGS_NONE; + if (enableAts) { + NV_ASSERT_OR_RETURN(vaParams.flags != NV_VASPACE_ALLOCATION_FLAGS_NONE, NV_ERR_INVALID_ARGUMENT); + vaParams.flags |= NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS; + } // TODO: Acquired because CliSetGpuContext expects RMAPI lock. Necessary? status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); @@ -2520,6 +2519,8 @@ static NV_STATUS getSystemP2PCaps(struct gpuDevice *device1, portMemSet(p2pCaps, 0, sizeof(*p2pCaps)); p2pCaps->peerIds[0] = p2pCapsParams->busPeerIds[0 * 2 + 1]; p2pCaps->peerIds[1] = p2pCapsParams->busPeerIds[1 * 2 + 0]; + p2pCaps->egmPeerIds[0] = p2pCapsParams->busEgmPeerIds[0 * 2 + 1]; + p2pCaps->egmPeerIds[1] = p2pCapsParams->busEgmPeerIds[1 * 2 + 0]; p2pCaps->nvlinkSupported = !!REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED, p2pCapsParams->p2pCaps); p2pCaps->atomicSupported = !!REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED, p2pCapsParams->p2pCaps); p2pCaps->indirectAccessSupported = !!REF_VAL(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED, @@ -2677,6 +2678,8 @@ NV_STATUS nvGpuOpsGetP2PCaps(struct gpuDevice *device1, portMemSet(p2pCapsParams, 0, sizeof(*p2pCapsParams)); p2pCapsParams->peerIds[0] = (NvU32)-1; p2pCapsParams->peerIds[1] = (NvU32)-1; + p2pCapsParams->egmPeerIds[0] = (NvU32)-1; + p2pCapsParams->egmPeerIds[1] = (NvU32)-1; p2pCapsParams->p2pLink = UVM_LINK_TYPE_NONE; p2pCapsParams->indirectAccess = NV_FALSE; @@ -2714,6 +2717,8 @@ NV_STATUS nvGpuOpsGetP2PCaps(struct gpuDevice *device1, { p2pCapsParams->peerIds[0] = p2pCaps.peerIds[0]; p2pCapsParams->peerIds[1] = p2pCaps.peerIds[1]; + p2pCapsParams->egmPeerIds[0] = p2pCaps.egmPeerIds[0]; + p2pCapsParams->egmPeerIds[1] = p2pCaps.egmPeerIds[1]; if (p2pCaps.nvlinkSupported) { @@ -3252,14 +3257,19 @@ nvGpuOpsBuildExternalAllocPtes FlaMemory* pFlaMemory = dynamicCast(pMemory, FlaMemory); nvFieldSet32(&pPteFmt->fldPeerIndex, peerId, pte.v8); + // + // Any fabric memory descriptors are pre-encoded with the fabric base address + // use NVLINK_INVALID_FABRIC_ADDR to avoid encoding twice + // + // Skip fabric base address for Local EGM as it uses peer aperture but + // doesn't require fabric address + // if ( (memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_MC) || - (memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_V2) || pFlaMemory) + (memdescGetAddressSpace(pMemDesc) == ADDR_FABRIC_V2) || + (pFlaMemory != NULL) || + (memdescIsEgm(pMemDesc) && (pMappingGpu == pMemDesc->pGpu))) { - // - // Any fabric memory descriptors are pre-encoded with the fabric base address - // use NVLINK_INVALID_FABRIC_ADDR to avoid encoding twice - // fabricBaseAddress = NVLINK_INVALID_FABRIC_ADDR; } else @@ -3365,7 +3375,7 @@ nvGpuOpsBuildExternalAllocPtes nvFieldSet32(&pPteFmt->fldCompTagSubIndex, 0, pte.v8); if (pMemorySystemConfig->bUseRawModeComptaglineAllocation && - pMemorySystemConfig->bDisablePlcForCertainOffsetsBug3046774 && + pKernelMemorySystem->bDisablePlcForCertainOffsetsBug3046774 && !memmgrIsKind_HAL(pMemoryManager, FB_IS_KIND_DISALLOW_PLC, comprInfo.kind)) { NvBool bEnablePlc = NV_TRUE; @@ -3503,8 +3513,6 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_MC) || (memdescGetAddressSpace(pAdjustedMemDesc) == ADDR_FABRIC_V2)) { - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); - isPeerSupported = NV_TRUE; pPeerGpu = pAdjustedMemDesc->pGpu; peerId = BUS_INVALID_PEER; @@ -3519,10 +3527,21 @@ NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace, if (pPeerGpu != NULL) { - if ((pKernelNvlink != NULL) && - knvlinkIsNvlinkP2pSupported(pMappingGpu, pKernelNvlink, pPeerGpu)) + if (IS_VIRTUAL_WITH_SRIOV(pMappingGpu) && + !gpuIsWarBug200577889SriovHeavyEnabled(pMappingGpu)) { - peerId = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); + peerId = kbusGetNvlinkPeerId_HAL(pMappingGpu, + GPU_GET_KERNEL_BUS(pMappingGpu), + pPeerGpu); + } + else + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pMappingGpu); + if ((pKernelNvlink != NULL) && + knvlinkIsNvlinkP2pSupported(pMappingGpu, pKernelNvlink, pPeerGpu)) + { + peerId = kbusGetPeerId_HAL(pMappingGpu, GPU_GET_KERNEL_BUS(pMappingGpu), pPeerGpu); + } } } else @@ -4049,9 +4068,9 @@ static void nvGpuOpsUnmapGpuMemory(struct gpuAddressSpace *vaSpace, vaSpace->device->session->handle, vaSpace->device->handle, memDescVa->handle, - memDescVa->childHandle, NV04_MAP_MEMORY_FLAGS_NONE, - gpuOffset)); + gpuOffset, + 0)); return; } @@ -4279,25 +4298,6 @@ NV_STATUS nvGpuOpsPmaPinPages(void *pPma, return status; } -NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma, - NvU64 *pPages, - NvLength pageCount, - NvU64 pageSize) -{ - NV_STATUS status; - THREAD_STATE_NODE threadState; - threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE); - - if (!pPma || !pPages) - return NV_ERR_INVALID_ARGUMENT; - - // Invoke PMA module to Unpin pages. - status = pmaUnpinPages((PMA *)pPma, pPages, pageCount, pageSize); - - threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE); - return status; -} - // // When this API is called from UVM as part of PMA eviction, the thread state // should have been initialized already and recursive re-init needs to be @@ -4604,6 +4604,7 @@ static NV_STATUS channelAllocate(const gpuTsgHandle tsg, NvLength gpFifoSize, errorNotifierSize; RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); RsClient *pClient; + RM_ENGINE_TYPE globalRmEngineId; if (params->numGpFifoEntries == 0) return NV_ERR_INVALID_ARGUMENT; @@ -4881,12 +4882,38 @@ static NV_STATUS channelAllocate(const gpuTsgHandle tsg, goto cleanup_free_virtual; } + if (IS_MIG_IN_USE(pGpu)) + { + // + // If we are running on a MIG instance, the engineID need to be translated to + // Global Engine ID before we look for the HW Runlist ID + // + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + Device *pDevice = NULL; + + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + deviceGetByHandle(pClient, device->handle, &pDevice), + cleanup_free_channel); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref), + cleanup_free_channel); + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, + kmigmgrGetLocalToGlobalEngineType(pGpu, pKernelMIGManager, ref, + (NvU32)tsgEngineType(channel->tsg), &globalRmEngineId), + cleanup_free_channel); + } + else + { + globalRmEngineId = tsgEngineType(channel->tsg); + } + // Query runlist ID pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); status = kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, ENGINE_INFO_TYPE_RM_ENGINE_TYPE, - (NvU32)tsgEngineType(channel->tsg), + (NvU32)globalRmEngineId, ENGINE_INFO_TYPE_RUNLIST, &channel->hwRunlistId); if (status != NV_OK) @@ -5099,7 +5126,6 @@ NV_STATUS nvGpuOpsChannelAllocate(const gpuTsgHandle tsg, nvGpuOpsChannelDestroy(*channelHandle); *channelHandle = NULL; return status; - } void nvGpuOpsChannelDestroy(struct gpuChannel *channel) @@ -5751,6 +5777,58 @@ static NV_STATUS queryVirtMode(NvHandle hClient, NvHandle hDevice, NvU32 *virtMo { NV_STATUS status = NV_OK; *virtMode = UVM_VIRT_MODE_NONE; + RM_API *pRmApi = rmapiGetInterface(RMAPI_EXTERNAL_KERNEL); + NVA080_CTRL_VGPU_GET_CONFIG_PARAMS cparams = {0}; + NV0080_CTRL_GPU_GET_VIRTUALIZATION_MODE_PARAMS params = {0}; + NvHandle vgpuHandle = NV01_NULL_OBJECT; + + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + hClient, + hDevice, + NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE, + ¶ms, + sizeof(params))); + + if (params.virtualizationMode != NV0080_CTRL_GPU_VIRTUALIZATION_MODE_VGX) + return status; + + NV_ASSERT_OK_OR_RETURN(pRmApi->Alloc(pRmApi, + hClient, + hDevice, + &vgpuHandle, + KEPLER_DEVICE_VGPU, + NULL, + 0)); + + NV_ASSERT_OK_OR_GOTO(status, pRmApi->Control(pRmApi, + hClient, + vgpuHandle, + NVA080_CTRL_CMD_VGPU_GET_CONFIG, + &cparams, + sizeof(cparams)), cleanup_handle); + + if (FLD_TEST_DRF(A080, + _CTRL_CMD_VGPU_GET_CONFIG, + _PARAMS_VGPU_DEV_CAPS_SRIOV_ENABLED, + _TRUE, + cparams.vgpuDeviceCapsBits)) + { + if (FLD_TEST_DRF(A080, + _CTRL_CMD_VGPU_GET_CONFIG, + _PARAMS_VGPU_DEV_CAPS_SRIOV_HEAVY_ENABLED, + _TRUE, + cparams.vgpuDeviceCapsBits)) + *virtMode = UVM_VIRT_MODE_SRIOV_HEAVY; + else + *virtMode = UVM_VIRT_MODE_SRIOV_STANDARD; + } + else + { + *virtMode = UVM_VIRT_MODE_LEGACY; + } + +cleanup_handle: + pRmApi->Free(pRmApi, hClient, vgpuHandle); return status; } @@ -5897,7 +5975,8 @@ static NV_STATUS getSysmemLinkInfo(NvHandle hClient, return NV_OK; } -static NV_STATUS getEgmInfo(NvHandle hClient, +static NV_STATUS getEgmInfo(OBJGPU *pGpu, + NvHandle hClient, NvHandle hSubDevice, gpuInfo *pGpuInfo) { @@ -5930,9 +6009,12 @@ static NV_STATUS getEgmInfo(NvHandle hClient, ((egmInfo & 0x1) == NV2080_CTRL_GPU_INFO_INDEX_GPU_LOCAL_EGM_CAPABILITY_YES); pGpuInfo->egmPeerId = DRF_VAL(2080_CTRL_GPU_INFO, _INDEX_GPU_LOCAL_EGM, _PEERID, egmInfo); + pGpuInfo->egmBaseAddr = memmgrLocalEgmBaseAddress(GPU_GET_MEMORY_MANAGER(pGpu)); - NV_PRINTF(LEVEL_INFO, "EGM enabled: %u peerId: %u\n", pGpuInfo->egmEnabled, - pGpuInfo->egmPeerId); + NV_PRINTF(LEVEL_INFO, "EGM enabled: %u peerId: %u BaseAddr: 0x%llx\n", + pGpuInfo->egmEnabled, + pGpuInfo->egmPeerId, + pGpuInfo->egmBaseAddr); return NV_OK; } @@ -6142,6 +6224,7 @@ NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, if (IS_MIG_IN_USE(pGpu)) { NvU32 swizzId; + NVC637_CTRL_GET_UUID_PARAMS getGIUuidParams = {0}; NV_ASSERT(pGpuInfo->subdeviceCount == 1); @@ -6158,6 +6241,18 @@ NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, pGpuInfo->smcSwizzId = swizzId; pGpuInfo->smcUserClientInfo.hClient = pGpuClientInfo->hClient; pGpuInfo->smcUserClientInfo.hSmcPartRef = pGpuClientInfo->hSmcPartRef; + + status = pRmApi->Control(pRmApi, + pGpuClientInfo->hClient, + pGpuClientInfo->hSmcPartRef, + NVC637_CTRL_CMD_GET_UUID, + &getGIUuidParams, + sizeof(getGIUuidParams)); + if (status != NV_OK) + goto cleanup; + + portMemCopy(&pGpuInfo->uuid, sizeof(*pUuid), getGIUuidParams.uuid, + sizeof(getGIUuidParams.uuid)); } status = pRmApi->Control(pRmApi, @@ -6189,7 +6284,7 @@ NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *pUuid, if (status != NV_OK) goto cleanup; - status = getEgmInfo(clientHandle, subDeviceHandle, pGpuInfo); + status = getEgmInfo(pGpu, clientHandle, subDeviceHandle, pGpuInfo); if (status != NV_OK) goto cleanup; @@ -6345,9 +6440,30 @@ NV_STATUS nvGpuOpsCheckEccErrorSlowpath(struct gpuChannel *channel, return status; } +static NV_STATUS fillMIGGiUUID(gpuMemoryInfo *pGpuMemoryInfo, Device *pDevice) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + MIG_INSTANCE_REF ref; + NV_STATUS status; + + if (!pGpuMemoryInfo->deviceDescendant) + return NV_ERR_INVALID_DEVICE; + + status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager, pDevice, &ref); + if (status == NV_OK) + { + portMemCopy(pGpuMemoryInfo->uuid.uuid, sizeof(pGpuMemoryInfo->uuid.uuid), + ref.pKernelMIGGpuInstance->uuid.uuid, sizeof(ref.pKernelMIGGpuInstance->uuid.uuid)); + } + + return status; +} + static NV_STATUS nvGpuOpsFillGpuMemoryInfo(PMEMORY_DESCRIPTOR pMemDesc, OBJGPU *pMappingGpu, - gpuMemoryInfo *pGpuMemoryInfo) + gpuMemoryInfo *pGpuMemoryInfo, + Device *pDevice) { NV_STATUS status; PMEMORY_DESCRIPTOR pRootMemDesc = memdescGetRootMemDesc(pMemDesc, NULL); @@ -6390,6 +6506,9 @@ static NV_STATUS nvGpuOpsFillGpuMemoryInfo(PMEMORY_DESCRIPTOR pMemDesc, flags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) | DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY); + if (fillMIGGiUUID(pGpuMemoryInfo, pDevice) == NV_OK) + return NV_OK; + // on success, allocates memory for uuid status = gpuGetGidInfo(pGpu, &uuid, &uuidLength, flags); if (status != NV_OK) @@ -6420,6 +6539,30 @@ static NvBool memdescRequiresIommuMapping(PMEMORY_DESCRIPTOR pMemDesc) static void _disablePeerAccess(struct gpuDevice *device, NvU32 addressSpace) { + subDeviceDesc *rmSubDevice = device->rmSubDevice; + + NV_ASSERT(rmapiLockIsOwner() && !rmGpuLockIsOwner()); + + if (!(isDeviceHopperPlus(device) && + device->info.connectedToSwitch)) + { + return; + } + + if ( + (addressSpace != ADDR_FABRIC_MC) && + (addressSpace != ADDR_FABRIC_V2)) + { + return; + } + + if (portAtomicExDecrementU64(&rmSubDevice->p2pObjectRef) == 0) + { + _nvGpuOpsP2pObjectDestroy(device->session, + rmSubDevice->hP2pObject, + RMAPI_API_LOCK_INTERNAL); + rmSubDevice->hP2pObject = 0; + } } // @@ -6430,6 +6573,41 @@ static void _disablePeerAccess(struct gpuDevice *device, static NV_STATUS _enablePeerAccess(struct gpuDevice *device, NvU32 addressSpace) { + NV_STATUS status; + + subDeviceDesc *rmSubDevice = device->rmSubDevice; + + LOCK_ASSERT_AND_RETURN(rmapiLockIsWriteOwner() && rmGpuLockIsOwner()); + + if (!(isDeviceHopperPlus(device) && + device->info.connectedToSwitch)) + { + return NV_OK; + } + + // + // This change is needed to enable inter-node P2P, especially on single-GPU + // multi-node systems as there is no external trigger to enable P2P. We + // only support FLA address space for inter-node P2P, so skip otherwise. + // + if ( + (addressSpace != ADDR_FABRIC_MC) && + (addressSpace != ADDR_FABRIC_V2)) + { + return NV_OK; + } + + if (portAtomicExIncrementU64(&rmSubDevice->p2pObjectRef) > 1) + return NV_OK; + + status = _nvGpuOpsP2pObjectCreate(device, device, + &rmSubDevice->hP2pObject, + RMAPI_GPU_LOCK_INTERNAL); + if (status != NV_OK) + { + portAtomicExSetU64(&rmSubDevice->p2pObjectRef, 0); + return status; + } return NV_OK; } @@ -6540,7 +6718,7 @@ static NV_STATUS dupMemory(struct gpuDevice *device, if (status != NV_OK) goto freeGpaMemdesc; - status = nvGpuOpsFillGpuMemoryInfo(pAdjustedMemDesc, pMappingGpu, pGpuMemoryInfo); + status = nvGpuOpsFillGpuMemoryInfo(pAdjustedMemDesc, pMappingGpu, pGpuMemoryInfo, GPU_RES_GET_DEVICE(pSubdevice)); if (status != NV_OK) goto freeGpaMemdesc; } @@ -7613,7 +7791,6 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, { KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - pFaultInfo->replayable.bUvmOwnsHwFaultBuffer = NV_FALSE; pFaultInfo->replayable.cslCtx.ctx = (struct ccslContext_t *) kgmmuGetShadowFaultBufferCslContext(pGpu, pKernelGmmu, REPLAYABLE_FAULT_BUFFER); if (pFaultInfo->replayable.cslCtx.ctx == NULL) { @@ -7621,10 +7798,6 @@ NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, goto cleanup_fault_buffer; } } - else - { - pFaultInfo->replayable.bUvmOwnsHwFaultBuffer = NV_TRUE; - } return NV_OK; @@ -8031,7 +8204,8 @@ NV_STATUS nvGpuOpsGetNonReplayableFaults(gpuFaultInfo *pFaultInfo, metadata.authTag); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "Fault buffer packet decryption failed with status = 0x%x\n", status); + NV_PRINTF(LEVEL_ERROR, "Fatal error detected in fault buffer packet decryption: 0x%x\n", status); + confComputeSetErrorState(pGpu, GPU_GET_CONF_COMPUTE(pGpu)); return status; } @@ -8092,6 +8266,18 @@ NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device) return kgmmuIssueReplayableFaultBufferFlush_HAL(pGpu, pKernelGmmu); } +NV_STATUS nvGpuOpsTogglePrefetchFaults(gpuFaultInfo *pFaultInfo, + NvBool bEnable) +{ + OBJGPU *pGpu; + + if (pFaultInfo->pDevice == NULL) + return NV_ERR_INVALID_ARGUMENT; + + pGpu = GPU_RES_GET_GPU(pFaultInfo->pDevice); + return kgmmuToggleFaultOnPrefetch_HAL(pGpu, GPU_GET_KERNEL_GMMU(pGpu), bEnable); +} + static NV_STATUS nvGpuOpsVerifyChannel(struct gpuAddressSpace *vaSpace, RsClient *pClient, NvHandle hKernelChannel, @@ -8955,8 +9141,11 @@ static NV_STATUS _nvGpuOpsRetainChannelResources(struct gpuDevice *device, pGpuMemoryInfo->sysmem = pFlcnParams->aperture == ADDR_SYSMEM; pGpuMemoryInfo->deviceDescendant = pFlcnParams->bDeviceDescendant; - portMemCopy(pGpuMemoryInfo->uuid.uuid, sizeof(pGpuMemoryInfo->uuid.uuid), - pFlcnParams->uuid, sizeof(pFlcnParams->uuid)); + if (fillMIGGiUUID(pGpuMemoryInfo, GPU_RES_GET_DEVICE(pKernelChannel)) != NV_OK) + { + portMemCopy(pGpuMemoryInfo->uuid.uuid, sizeof(pGpuMemoryInfo->uuid.uuid), + pFlcnParams->uuid, sizeof(pFlcnParams->uuid)); + } status = _shadowMemdescCreateFlcn(retainedChannel, pFlcnParams, &pMemDesc); if (status != NV_OK) @@ -9011,8 +9200,11 @@ static NV_STATUS _nvGpuOpsRetainChannelResources(struct gpuDevice *device, pGpuMemoryInfo->sysmem = pCtxBufferInfo->aperture == ADDR_SYSMEM; pGpuMemoryInfo->deviceDescendant = pCtxBufferInfo->bDeviceDescendant; - portMemCopy(pGpuMemoryInfo->uuid.uuid, sizeof(pGpuMemoryInfo->uuid.uuid), - pCtxBufferInfo->uuid, sizeof(pCtxBufferInfo->uuid)); + if (fillMIGGiUUID(pGpuMemoryInfo, GPU_RES_GET_DEVICE(pKernelChannel)) != NV_OK) + { + portMemCopy(pGpuMemoryInfo->uuid.uuid, sizeof(pGpuMemoryInfo->uuid.uuid), + pCtxBufferInfo->uuid, sizeof(pCtxBufferInfo->uuid)); + } status = _shadowMemdescCreate(retainedChannel, pCtxBufferInfo, &pMemDesc); if (status != NV_OK) @@ -9872,6 +10064,16 @@ NV_STATUS nvGpuOpsCcslContextClear(struct ccslContext_t *ctx) return NV_OK; } +NV_STATUS nvGpuOpsCcslContextUpdate(struct ccslContext_t *ctx) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslContextUpdate(ctx); +} + NV_STATUS nvGpuOpsCcslRotateIv(struct ccslContext_t *ctx, NvU8 direction) { if (ctx == NULL) @@ -9983,3 +10185,14 @@ NV_STATUS nvGpuOpsIncrementIv(struct ccslContext_t *ctx, return NV_ERR_INVALID_ARGUMENT; } } + +NV_STATUS nvGpuOpsLogDeviceEncryption(struct ccslContext_t *ctx, + NvU32 bufferSize) +{ + if (ctx == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + return ccslLogDeviceEncryption(ctx, bufferSize); +} diff --git a/src/nvidia/src/kernel/rmapi/resource.c b/src/nvidia/src/kernel/rmapi/resource.c index a2accf5d81..06bd25e19b 100644 --- a/src/nvidia/src/kernel/rmapi/resource.c +++ b/src/nvidia/src/kernel/rmapi/resource.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -25,10 +25,12 @@ #include "rmapi/client.h" #include "rmapi/resource.h" #include "rmapi/rmapi.h" +#include "rmapi/rmapi_utils.h" #include "rmapi/control.h" #include "ctrl/ctrlxxxx.h" #include "gpu/gpu_resource.h" #include "gpu/gpu.h" +#include "gpu_mgr/gpu_mgr.h" #include "vgpu/rpc.h" #include "core/locks.h" @@ -173,27 +175,6 @@ void serverControl_InitCookie = exportedEntry->accessRight; } -// -// This routine searches through the Resource's NVOC exported methods for an entry -// that matches the specified command. -// -// Same logic as rmControlCmdLookup() in legacy RMCTRL path -// -NV_STATUS rmresControlLookup_IMPL -( - RmResource *pResource, - RS_RES_CONTROL_PARAMS_INTERNAL *pRsParams, - const struct NVOC_EXPORTED_METHOD_DEF **ppEntry -) -{ - NvU32 cmd = pRsParams->cmd; - - if (RMCTRL_IS_NULL_CMD(cmd)) - return NV_WARN_NOTHING_TO_DO; - - return resControlLookup_IMPL(staticCast(pResource, RsResource), pRsParams, ppEntry); -} - NV_STATUS rmresGetMemInterMapParams_IMPL ( diff --git a/src/nvidia/src/kernel/rmapi/resource_desc_flags.h b/src/nvidia/src/kernel/rmapi/resource_desc_flags.h index 6f4574dde8..b6a1c896c4 100644 --- a/src/nvidia/src/kernel/rmapi/resource_desc_flags.h +++ b/src/nvidia/src/kernel/rmapi/resource_desc_flags.h @@ -75,4 +75,6 @@ #define RS_FLAGS_ALLOC_ALL_VGPU_PLUGINS (RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_VGPU_GSP | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_SRIOV | RS_FLAGS_ALLOC_CPU_PLUGIN_FOR_LEGACY | RS_FLAGS_ALLOC_GSP_PLUGIN_FOR_VGPU_GSP) +#define RS_FLAGS_DUAL_CLIENT_LOCK NVBIT(15) ///< Class needs to lock two clients when being allocated, must update serverAllocLookupSecondClient in order to use + #endif // _RESOURCE_DESC_FLAGS_H_ diff --git a/src/nvidia/src/kernel/rmapi/resource_list.h b/src/nvidia/src/kernel/rmapi/resource_list.h index 43de0b1e7e..f0600a0056 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list.h +++ b/src/nvidia/src/kernel/rmapi/resource_list.h @@ -110,6 +110,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV_IMEX_SESSION, + /* Internal Class */ ImexSessionApi, + /* Multi-Instance */ NV_FALSE, + /* Parents */ RS_LIST(classId(RmClientResource)), + /* Alloc Param Info */ RS_REQUIRED(NV00F1_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV0020_GPU_MANAGEMENT, /* Internal Class */ GpuManagementApi, @@ -177,7 +187,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device)), /* Alloc Param Info */ RS_REQUIRED(NV83DE_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_DUAL_CLIENT_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -220,6 +230,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ KEPLER_DEVICE_VGPU, + /* Internal Class */ VgpuApi, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Device)), + /* Alloc Param Info */ RS_NONE, + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ GF100_HDACODEC, /* Internal Class */ Hdacodec, @@ -329,7 +349,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Device), classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_HIGH, - /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ALLOC_ALL_VGPU_PLUGINS | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_KERNEL_PRIVILEGED | RS_FLAGS_ALLOC_ALL_VGPU_PLUGINS | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_DUAL_CLIENT_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -339,7 +359,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannelGroupApi)), /* Alloc Param Info */ RS_REQUIRED(NV_CTXSHARE_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -369,7 +389,9 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV2081_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | + RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM | + RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -379,7 +401,9 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_OPTIONAL(NV2082_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM, + /* Flags */ RS_FLAGS_ALLOC_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | + RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_PHYS_RM | + RS_FLAGS_ALLOC_RPC_TO_VGPU_HOST | RS_FLAGS_ALLOC_GSP_PLUGIN_FOR_VGPU_GSP, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -465,11 +489,11 @@ RS_ENTRY( RS_ENTRY( /* External Class */ NV_MEMORY_MAPPER, /* Internal Class */ MemoryMapper, - /* Multi-Instance */ NV_FALSE, + /* Multi-Instance */ NV_TRUE, /* Parents */ RS_LIST(classId(Subdevice)), /* Alloc Param Info */ RS_REQUIRED(NV_MEMORY_MAPPER_ALLOCATION_PARAMS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -552,6 +576,26 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV_MEMORY_EXPORT, + /* Internal Class */ MemoryExport, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(RmClientResource)), + /* Alloc Param Info */ RS_REQUIRED(NV00E0_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NV_MEMORY_FABRIC_IMPORT_V2, + /* Internal Class */ MemoryFabricImportV2, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(RmClientResource)), + /* Alloc Param Info */ RS_REQUIRED(NV00F9_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NV_MEMORY_FABRIC, /* Internal Class */ MemoryFabric, @@ -562,6 +606,16 @@ RS_ENTRY( /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) +RS_ENTRY( + /* External Class */ NV_MEMORY_FABRIC_IMPORTED_REF, + /* Internal Class */ MemoryFabricImportedRef, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(RmClientResource)), + /* Alloc Param Info */ RS_REQUIRED(NV00FB_ALLOCATION_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ FERMI_VASPACE_A, /* Internal Class */ VaSpaceApi, @@ -579,10 +633,30 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(RmClientResource)), /* Alloc Param Info */ RS_REQUIRED(NV00FD_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK_ON_FREE | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC, /* Required Access Rights */ RS_ACCESS_NONE ) /* Subdevice Children: */ +RS_ENTRY( + /* External Class */ NVENC_SW_SESSION, + /* Internal Class */ NvencSession, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NVA0BC_ALLOC_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) +RS_ENTRY( + /* External Class */ NVFBC_SW_SESSION, + /* Internal Class */ NvfbcSession, + /* Multi-Instance */ NV_TRUE, + /* Parents */ RS_LIST(classId(Subdevice)), + /* Alloc Param Info */ RS_REQUIRED(NVA0BD_ALLOC_PARAMETERS), + /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Required Access Rights */ RS_ACCESS_NONE +) RS_ENTRY( /* External Class */ NVA081_VGPU_CONFIG, /* Internal Class */ VgpuConfigApi, @@ -1042,7 +1116,7 @@ RS_ENTRY( /* Parents */ RS_LIST(classId(KernelChannel)), /* Alloc Param Info */ RS_REQUIRED(NV9072_ALLOCATION_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_CHANNEL_DESCENDANT_COMMON | RS_FLAGS_ALLOC_RPC_TO_ALL, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPU_GROUP_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_ALLOC_RPC_TO_ALL, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1452,7 +1526,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_DUAL_CLIENT_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1462,7 +1536,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_DUAL_CLIENT_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1472,7 +1546,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_DUAL_CLIENT_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( @@ -1482,7 +1556,7 @@ RS_ENTRY( /* Parents */ RS_ANY_PARENT, /* Alloc Param Info */ RS_REQUIRED(NV0005_ALLOC_PARAMETERS), /* Resource Free Priority */ RS_FREE_PRIORITY_DEFAULT, - /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK, + /* Flags */ RS_FLAGS_ALLOC_NON_PRIVILEGED | RS_FLAGS_ACQUIRE_GPUS_LOCK | RS_FLAGS_ACQUIRE_RO_API_LOCK_ON_ALLOC | RS_FLAGS_DUAL_CLIENT_LOCK, /* Required Access Rights */ RS_ACCESS_NONE ) RS_ENTRY( diff --git a/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h b/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h index 2703e8a275..0a010cf153 100644 --- a/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h +++ b/src/nvidia/src/kernel/rmapi/resource_list_required_includes.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a diff --git a/src/nvidia/src/kernel/rmapi/rmapi_cache.c b/src/nvidia/src/kernel/rmapi/rmapi_cache.c index 6746e87432..de51fc4233 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_cache.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_cache.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -946,7 +946,7 @@ NV_STATUS rmapiControlCacheGet ) { NV_STATUS status = NV_OK; - NvU32 flags = 0; + NvU32 flags; if (RmapiControlCache.mode == NV0000_CTRL_SYSTEM_RMCTRL_CACHE_MODE_CTRL_MODE_VERIFY_ONLY) return NV_ERR_OBJECT_NOT_FOUND; @@ -984,7 +984,7 @@ NV_STATUS rmapiControlCacheSet ) { NV_STATUS status = NV_OK; - NvU32 flags = 0; + NvU32 flags; status = rmapiutilGetControlInfo(cmd, &flags, NULL); if (status != NV_OK) diff --git a/src/nvidia/src/kernel/rmapi/rmapi_finn.c b/src/nvidia/src/kernel/rmapi/rmapi_finn.c index f2df6c6288..6fa3b79c06 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_finn.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_finn.c @@ -83,7 +83,7 @@ serverSerializeCtrlDown { NV_PRINTF(LEVEL_ERROR, "Serialization failed for cmd 0x%06x with status %s (0x%02x)\n", - cmd, nvAssertStatusToString(status), status); + cmd, nvstatusToString(status), status); portMemFree(pCallContext->pSerializedParams); pCallContext->pSerializedParams = NULL; return status; @@ -162,7 +162,7 @@ serverDeserializeCtrlDown { NV_PRINTF(LEVEL_ERROR, "Deserialization failed for cmd 0x%06x with status %s (0x%02x)\n", - cmd, nvAssertStatusToString(status), status); + cmd, nvstatusToString(status), status); portMemFree(pCallContext->pDeserializedParams); pCallContext->pDeserializedParams = NULL; return status; @@ -240,7 +240,7 @@ serverSerializeCtrlUp { NV_PRINTF(LEVEL_ERROR, "Serialization failed for cmd 0x%06x with status %s (0x%02x)\n", - cmd, nvAssertStatusToString(status), status); + cmd, nvstatusToString(status), status); return status; } @@ -317,7 +317,7 @@ serverDeserializeCtrlUp { NV_PRINTF(LEVEL_ERROR, "Deserialization failed for cmd 0x%06x with status %s (0x%02x)\n", - cmd, nvAssertStatusToString(status), status); + cmd, nvstatusToString(status), status); return status; } @@ -376,7 +376,7 @@ serverSerializeAllocDown { NV_PRINTF(LEVEL_ERROR, "Serialization failed for classId 0x%06x with status %s (0x%02x)\n", - classId, nvAssertStatusToString(status), status); + classId, nvstatusToString(status), status); portMemFree(pCallContext->pSerializedParams); pCallContext->pSerializedParams = NULL; return status; @@ -445,7 +445,7 @@ serverDeserializeAllocDown { NV_PRINTF(LEVEL_ERROR, "Deserialization failed for classId 0x%06x with status %s (0x%02x)\n", - classId, nvAssertStatusToString(status), status); + classId, nvstatusToString(status), status); portMemFree(pCallContext->pDeserializedParams); pCallContext->pDeserializedParams = NULL; return status; @@ -513,7 +513,7 @@ serverSerializeAllocUp { NV_PRINTF(LEVEL_ERROR, "Serialization failed for classId 0x%06x with status %s (0x%02x)\n", - classId, nvAssertStatusToString(status), status); + classId, nvstatusToString(status), status); return status; } @@ -578,7 +578,7 @@ serverDeserializeAllocUp { NV_PRINTF(LEVEL_ERROR, "Deserialization failed for classId 0x%06x with status %s (0x%02x)\n", - classId, nvAssertStatusToString(status), status); + classId, nvstatusToString(status), status); return status; } diff --git a/src/nvidia/src/kernel/rmapi/rmapi_specific.c b/src/nvidia/src/kernel/rmapi/rmapi_specific.c new file mode 100644 index 0000000000..a651c0e938 --- /dev/null +++ b/src/nvidia/src/kernel/rmapi/rmapi_specific.c @@ -0,0 +1,200 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "rmconfig.h" +#include "g_rmconfig_private.h" +#include "rmapi/rmapi_specific.h" +#include "rmapi/event.h" +#include "resource_desc.h" +#include "resserv/rs_server.h" + +#include "class/cl0005.h" // NV01_EVENT +#include "class/clc574.h" // UVM_CHANNEL_RETAINER + +#include "class/cl83de.h" // GT200_DEBUGGER + +#include "ctrl/ctrl0002.h" // NV0002_CTRL_CMD_*_CONTEXTDMA + +#include "ctrl/ctrl2080/ctrl2080bus.h" // NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS +#include "ctrl/ctrl2080/ctrl2080fb.h" // NV2080_CTRL_CMD_FB_FLUSH_GPU_CACHE_IRQL +#include "ctrl/ctrl2080/ctrl2080rc.h" // NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM +#include "ctrl/ctrl2080/ctrl2080nvd.h" // NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA +#include "ctrl/ctrl2080/ctrl2080tmr.h" // NV2080_CTRL_CMD_TIMER_* +#include "ctrl/ctrl9010.h" //NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION +#include "ctrl/ctrl906f.h" // NV906F_CTRL_CMD_GET_MMU_FAULT_INFO +#include "ctrl/ctrlc370/ctrlc370chnc.h" // NVC370_CTRL_CMD_* + +#include "ctrl/ctrl2080/ctrl2080gr.h" // NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND +#include "ctrl/ctrl2080/ctrl2080internal.h" // NV2080_CTRL_CMD_INTERNAL_GR_CTXSW_ZCULL_BIND + +NV_STATUS +rmapiFixupAllocParams +( + RS_RESOURCE_DESC **ppResDesc, + RS_RES_ALLOC_PARAMS_INTERNAL *pRmAllocParams +) +{ + RS_RESOURCE_DESC *pResDesc = *ppResDesc; + + if ((pResDesc->pClassInfo != NULL) && (pResDesc->pClassInfo->classId == classId(Event))) + { + NV0005_ALLOC_PARAMETERS *pNv0005Params = pRmAllocParams->pAllocParams; + + // + // This field isn't filled out consistently by clients. Some clients specify NV01_EVENT as the class + // and then override it using the subclass in the event parameters, while other clients specify the + // same subclass in both the RmAllocParams and event params. NV01_EVENT isn't a valid class to allocate + // so overwrite it with the subclass from the event params. + // + if (pRmAllocParams->externalClassId == NV01_EVENT) + pRmAllocParams->externalClassId = pNv0005Params->hClass; + + pNv0005Params->hSrcResource = pRmAllocParams->hParent; + + // No support for event and src resource that reside under different clients + if (pNv0005Params->hParentClient != pRmAllocParams->hClient) + pRmAllocParams->hParent = pRmAllocParams->hClient; + + // class id may have changed so refresh the resource descriptor, but make sure it is still an Event + pResDesc = RsResInfoByExternalClassId(pRmAllocParams->externalClassId); + if (pResDesc == NULL || pResDesc->pClassInfo == NULL || pResDesc->pClassInfo->classId != classId(Event)) + return NV_ERR_INVALID_CLASS; + + *ppResDesc = pResDesc; + } + + return NV_OK; +} + +NV_STATUS +serverAllocLookupSecondClient +( + NvU32 externalClassId, + void *pAllocParams, + NvHandle *phSecondClient +) +{ + RS_RESOURCE_DESC *pResDesc = RsResInfoByExternalClassId(externalClassId); + + *phSecondClient = NV01_NULL_OBJECT; + + if ((pAllocParams != NULL) && (pResDesc != NULL) && + (pResDesc->flags & RS_FLAGS_DUAL_CLIENT_LOCK)) + { + switch (externalClassId) + { + case GT200_DEBUGGER: + { + *phSecondClient = ((NV83DE_ALLOC_PARAMETERS *) pAllocParams)->hAppClient; + break; + } + case UVM_CHANNEL_RETAINER: + { + *phSecondClient = ((NV_UVM_CHANNEL_RETAINER_ALLOC_PARAMS *) pAllocParams)->hClient; + break; + } + case NV01_EVENT: + case NV01_EVENT_OS_EVENT: + case NV01_EVENT_KERNEL_CALLBACK: + case NV01_EVENT_KERNEL_CALLBACK_EX: + { + *phSecondClient = ((NV0005_ALLOC_PARAMETERS *) pAllocParams)->hParentClient; + break; + } + default: + { + // RS_FLAGS_DUAL_CLIENT_LOCK flag requires adding a case statement here. + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + } + } + + return NV_OK; +} + +NV_STATUS +serverControlLookupSecondClient +( + NvU32 cmd, + void *pControlParams, + RS_CONTROL_COOKIE *pCookie, + NvHandle *phSecondClient +) +{ + *phSecondClient = NV01_NULL_OBJECT; + + if ((pControlParams != NULL) && (pCookie->ctrlFlags & RMCTRL_FLAGS_DUAL_CLIENT_LOCK)) + { + switch (cmd) + { + case NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND: + { + *phSecondClient = ((NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS *) pControlParams)->hClient; + break; + } + default: + // RMCTRL_FLAGS_DUAL_CLIENT_LOCK flag requires adding a case statement here. + NV_ASSERT_OR_RETURN(0, NV_ERR_INVALID_STATE); + } + } + + return NV_OK; +} + +NvBool +rmapiRmControlCanBeRaisedIrql(NvU32 cmd) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_TIMER_SCHEDULE: + case NV2080_CTRL_CMD_TIMER_GET_TIME: + // Below 2 control calls are used for flip canceling (HW Flip Queue) + // We use TRASH/ABORT mode to discard queued hw commands in the push buffer (bug 200644346) + case NVC370_CTRL_CMD_SET_ACCL: + case NVC370_CTRL_CMD_GET_CHANNEL_INFO: + case NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION: + return NV_TRUE; + default: + return NV_FALSE; + } +} + +NvBool +rmapiRmControlCanBeBypassLock(NvU32 cmd) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_RC_READ_VIRTUAL_MEM: + case NV2080_CTRL_CMD_TIMER_GET_TIME: + case NV906F_CTRL_CMD_GET_MMU_FAULT_INFO: + // Below 2 control calls are used for flip canceling (HW Flip Queue) + // We use TRASH/ABORT mode to discard queued hw commands in the push buffer (bug 200644346) + case NVC370_CTRL_CMD_SET_ACCL: + case NVC370_CTRL_CMD_GET_CHANNEL_INFO: + case NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS: + case NV9010_CTRL_CMD_SET_VBLANK_NOTIFICATION: + case NV2080_CTRL_CMD_NVD_SET_NOCAT_JOURNAL_DATA: + return NV_TRUE; + default: + return NV_FALSE; + } +} diff --git a/src/nvidia/src/kernel/rmapi/rmapi_stubs.c b/src/nvidia/src/kernel/rmapi/rmapi_stubs.c index 240ffa8f80..82cbcbbe6a 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_stubs.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_stubs.c @@ -142,14 +142,14 @@ static NV_STATUS _rmapiMapWithSecInfo_STUB(RM_API *pRmApi, NvHandle hClient, NvH return NV_ERR_NOT_SUPPORTED; } -static NV_STATUS _rmapiUnmap_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, NvHandle hMemory, - NvU32 flags, NvU64 dmaOffset) +static NV_STATUS _rmapiUnmap_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, + NvU32 flags, NvU64 dmaOffset, NvU64 size) { return NV_ERR_NOT_SUPPORTED; } -static NV_STATUS _rmapiUnmapWithSecInfo_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, NvHandle hMemory, - NvU32 flags, NvU64 dmaOffset, API_SECURITY_INFO *pSecInfo) +static NV_STATUS _rmapiUnmapWithSecInfo_STUB(RM_API *pRmApi, NvHandle hClient, NvHandle hDevice, NvHandle hMemCtx, + NvU32 flags, NvU64 dmaOffset, NvU64 size, API_SECURITY_INFO *pSecInfo) { return NV_ERR_NOT_SUPPORTED; } diff --git a/src/nvidia/src/kernel/rmapi/rmapi_utils.c b/src/nvidia/src/kernel/rmapi/rmapi_utils.c index 8eda73e617..35c075de28 100644 --- a/src/nvidia/src/kernel/rmapi/rmapi_utils.c +++ b/src/nvidia/src/kernel/rmapi/rmapi_utils.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -31,6 +31,8 @@ #include "class/cl0080.h" #include "class/cl2080.h" +#include "ctrl/ctrl2080.h" + NV_STATUS rmapiutilAllocClientAndDeviceHandles ( @@ -183,3 +185,25 @@ rmapiutilGetControlInfo return NV_ERR_OBJECT_NOT_FOUND; } + +NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(NvU32 cmd) +{ + switch (cmd) + { + case NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO: + case NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION: + case NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION: + case NV2080_CTRL_CMD_GPU_GET_RESET_STATUS: + case NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS: + case NV2080_CTRL_CMD_BUS_GET_PEX_COUNTERS: + case NV2080_CTRL_CMD_FB_GET_OFFLINED_PAGES: + case NV2080_CTRL_CMD_FB_GET_REMAPPED_ROWS: + case NV2080_CTRL_CMD_ECC_GET_VOLATILE_COUNTS: + case NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT: + return NV_TRUE; + + default: + return NV_FALSE; + } +} + diff --git a/src/nvidia/src/kernel/rmapi/rpc_common.c b/src/nvidia/src/kernel/rmapi/rpc_common.c index 6d337004ee..a1fefd949a 100644 --- a/src/nvidia/src/kernel/rmapi/rpc_common.c +++ b/src/nvidia/src/kernel/rmapi/rpc_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -29,6 +29,7 @@ //****************************************************************************** #include "gpu/gpu.h" +#include "gpu/device/device.h" #include "vgpu/rpc.h" #include "os/os.h" @@ -94,6 +95,17 @@ OBJRPC *initRpcObject(OBJGPU *pGpu) rpcRmApiSetup(pGpu); + if ( + !IS_GSP_CLIENT(pGpu)) + { + if (NV_OK != rpcConstruct(pGpu, pRpc)) + { + NV_PRINTF(LEVEL_ERROR, "rpcConstruct failed\n"); + portMemFree(pRpc); + return NULL; + } + } + return pRpc; } @@ -109,7 +121,10 @@ NV_STATUS rpcWriteCommonHeader(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 func, NvU32 par return NV_ERR_INVALID_STATE; } - portMemSet(pRpc->message_buffer, 0, pRpc->maxRpcSize); + if (func == NV_VGPU_MSG_FUNCTION_RM_API_CONTROL) + portMemSet(pRpc->message_buffer, 0, pRpc->largeRpcSize); + else + portMemSet(pRpc->message_buffer, 0, pRpc->maxRpcSize); vgpu_rpc_message_header_v->header_version = DRF_DEF(_VGPU, _MSG_HEADER_VERSION, _MAJOR, _TOT) | DRF_DEF(_VGPU, _MSG_HEADER_VERSION, _MINOR, _TOT); diff --git a/src/nvidia/src/kernel/rmapi/sharing.c b/src/nvidia/src/kernel/rmapi/sharing.c index fbf729c03d..0719d3577c 100644 --- a/src/nvidia/src/kernel/rmapi/sharing.c +++ b/src/nvidia/src/kernel/rmapi/sharing.c @@ -28,9 +28,6 @@ #include "resource_desc.h" #include "class/cl0071.h" -#include "gpu/device/device.h" -#include "gpu/subdevice/subdevice.h" - static NV_STATUS _RmDupObject ( diff --git a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c index 32bf7028cf..0618040733 100644 --- a/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c +++ b/src/nvidia/src/kernel/virtualization/common_vgpu_mgr.c @@ -22,13 +22,101 @@ */ #include "virtualization/common_vgpu_mgr.h" +#include "virtualization/kernel_vgpu_mgr.h" #include "virtualization/hypervisor/hypervisor.h" #include "ctrl/ctrl2080/ctrl2080gpu.h" +// Get vGPU license product name from license info +static char * getGridLicenseProductName(const char* licenseInfo) +{ + if (licenseInfo == NULL) + { + return NULL; + } + + if (portStringCompare(licenseInfo, NV_GRID_LICENSE_FEATURE_VPC_EDITION, (portStringLength(NV_GRID_LICENSE_FEATURE_VPC_EDITION) + 1)) == 0) + { + return (char *)NV_GRID_LICENSED_PRODUCT_VPC; + } + else if (portStringCompare(licenseInfo, NV_GRID_LICENSE_FEATURE_VAPPS_EDITION, (portStringLength(NV_GRID_LICENSE_FEATURE_VAPPS_EDITION) + 1)) == 0) + { + return (char *)NV_GRID_LICENSED_PRODUCT_VAPPS; + } + else if (portStringCompare(licenseInfo, NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION, (portStringLength(NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION) + 1)) == 0) + { + return (char *)NV_GRID_LICENSED_PRODUCT_VWS; + } + else if (portStringCompare(licenseInfo, NV_GRID_LICENSE_FEATURE_GAMING_EDITION, (portStringLength(NV_GRID_LICENSE_FEATURE_GAMING_EDITION) + 1)) == 0) + { + return (char *)NV_GRID_LICENSED_PRODUCT_GAMING; + } + else if (portStringCompare(licenseInfo, NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION, (portStringLength(NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION) + 1)) == 0) + { + return (char *)NV_GRID_LICENSED_PRODUCT_COMPUTE; + } + else + { + return NULL; + } +} + void vgpuMgrFillVgpuType(NVA081_CTRL_VGPU_INFO *pVgpuInfo, VGPU_TYPE *pVgpuTypeNode) { + char *licenseProductNameBuffer = NULL; + + portMemSet(pVgpuTypeNode, 0, sizeof(VGPU_TYPE)); + + pVgpuTypeNode->vgpuTypeId = pVgpuInfo->vgpuType; + pVgpuTypeNode->maxInstance = pVgpuInfo->maxInstance; + pVgpuTypeNode->numHeads = pVgpuInfo->numHeads; + pVgpuTypeNode->maxResolutionX = pVgpuInfo->maxResolutionX; + pVgpuTypeNode->maxResolutionY = pVgpuInfo->maxResolutionY; + pVgpuTypeNode->maxPixels = pVgpuInfo->maxPixels; + pVgpuTypeNode->frlConfig = pVgpuInfo->frlConfig; + pVgpuTypeNode->cudaEnabled = pVgpuInfo->cudaEnabled; + pVgpuTypeNode->eccSupported = pVgpuInfo->eccSupported; + pVgpuTypeNode->gpuInstanceSize = pVgpuInfo->gpuInstanceSize; + pVgpuTypeNode->multiVgpuSupported = pVgpuInfo->multiVgpuSupported; + pVgpuTypeNode->vdevId = pVgpuInfo->vdevId; + pVgpuTypeNode->pdevId = pVgpuInfo->pdevId; + pVgpuTypeNode->profileSize = pVgpuInfo->profileSize; + pVgpuTypeNode->fbLength = pVgpuInfo->fbLength; + pVgpuTypeNode->gspHeapSize = pVgpuInfo->gspHeapSize; + pVgpuTypeNode->fbReservation = pVgpuInfo->fbReservation; + pVgpuTypeNode->mappableVideoSize = pVgpuInfo->mappableVideoSize; + pVgpuTypeNode->encoderCapacity = pVgpuInfo->encoderCapacity; + pVgpuTypeNode->bar1Length = pVgpuInfo->bar1Length; + pVgpuTypeNode->gpuDirectSupported = pVgpuInfo->gpuDirectSupported; + pVgpuTypeNode->nvlinkP2PSupported = pVgpuInfo->nvlinkP2PSupported; + pVgpuTypeNode->multiVgpuExclusive = pVgpuInfo->multiVgpuExclusive; + pVgpuTypeNode->frlEnable = pVgpuInfo->frlEnable; + + portStringCopy( + (char *) pVgpuTypeNode->vgpuName, sizeof(pVgpuTypeNode->vgpuName), + (char *) pVgpuInfo->vgpuName, sizeof(pVgpuInfo->vgpuName)); + portStringCopy( + (char *) pVgpuTypeNode->vgpuClass, sizeof(pVgpuTypeNode->vgpuClass), + (char *) pVgpuInfo->vgpuClass, sizeof(pVgpuInfo->vgpuClass)); + portStringCopy( + (char *) pVgpuTypeNode->license, sizeof(pVgpuTypeNode->license), + (char *) pVgpuInfo->license, sizeof(pVgpuInfo->license)); + portStringCopy( + (char *) pVgpuTypeNode->vgpuExtraParams, sizeof(pVgpuTypeNode->vgpuExtraParams), + (char *) pVgpuInfo->vgpuExtraParams, sizeof(pVgpuInfo->vgpuExtraParams)); + portMemCopy( + (char *) pVgpuTypeNode->vgpuSignature, sizeof(pVgpuTypeNode->vgpuSignature), + (char *) pVgpuInfo->vgpuSignature, sizeof(pVgpuInfo->vgpuSignature)); + + // Fetch vGPU license product name from license info + licenseProductNameBuffer = getGridLicenseProductName((const char *)pVgpuInfo->license); + if (licenseProductNameBuffer != NULL) + { + portStringCopy( + (char *)pVgpuTypeNode->licensedProductName, sizeof(pVgpuTypeNode->licensedProductName), + (char *)licenseProductNameBuffer, (portStringLength((char *)licenseProductNameBuffer) + 1)); + } } NV_STATUS @@ -41,11 +129,100 @@ vgpuMgrReserveSystemChannelIDs NvU32 *pChannelCount, Device *pMigDevice, NvU32 numChannels, + NvU16 placementId, NvU32 engineFifoListNumEntries, FIFO_ENGINE_LIST *engineFifoList ) { - return NV_ERR_NOT_SUPPORTED; + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NvU64 mask = 0; + NvU32 i; + NvU32 flags = NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN; // allocate from the end + NvU64 heapOffset = 0; + + NV_ASSERT_OR_RETURN(engineFifoListNumEntries != 0, NV_ERR_INVALID_STATE); + + // If we are running with plugin-offload mode and are in GSP-RM, we + // need to use fixed offset allocation for channel reserve + if (RMCFG_FEATURE_PLATFORM_GSP && IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + flags |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; + + if (!RMCFG_FEATURE_PLATFORM_GSP && + pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE) && + (placementId != NVA081_PLACEMENT_ID_INVALID)) + { + /* + * If heterogeneous mode is enabled, query chidOffset based on placement ID + * and vGPU typeId. + */ + NV_ASSERT_OK_OR_RETURN(kvgpumgrHeterogeneousGetChidOffset(vgpuTypeInfo->vgpuTypeId, + placementId, + numChannels, + &heapOffset)); + + flags |= NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE; + } + + // Last entry is ENG_SW. Don't include that + for (i = 0; i < engineFifoListNumEntries - 1; i++) + { + NvU32 runlistId; + CHID_MGR *pChidMgr; + NvU32 currentNumChannels = numChannels; + + // + // This code needs the physical runlist ID. ENGINE_INFO_TYPE_FIFO_TAG is not virtualized currently, + // and hence we can use a trick to translate it to the physical runlist ID using the host's device table. + // In the future, if we virtualize all of the data in engineData, we'll need a translation from virtual to physical IDs + // + NV_ASSERT_OK_OR_RETURN(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_FIFO_TAG, + engineFifoList[i].engineData[ENGINE_INFO_TYPE_FIFO_TAG], + ENGINE_INFO_TYPE_RUNLIST, + &runlistId)); + pChidMgr = kfifoGetChidMgr(pGpu, pKernelFifo, runlistId); + + // + // numChannels received as input argument is prevPow2(maxPhysicalChannels/vgpuTypeInfo->maxInstance) + // So, if vgpuTypeInfo->maxInstance is not pow2, then numChannels is already reduced. + if (hypervisorIsType(OS_HYPERVISOR_HYPERV) && + (RM_ENGINE_TYPE_IS_COPY(engineFifoList[i].engineData[ENGINE_INFO_TYPE_RM_ENGINE_TYPE])) && + ONEBITSET(vgpuTypeInfo->maxInstance)) + { + // + // On hyperv host, KMD/OS uses a CE channel for some paging oprations. + // so, we need to reduce the number of channels for guest to prev + // power of 2 and then reserve the channels. + // + currentNumChannels /= 2; + } + + // + // Some engines (like GR and GRCE) may share a single runlist. + // So, don't process any runlist twice. + // + if (mask & NVBIT64(runlistId)) + continue; + + NV_ASSERT_OK_OR_RETURN(kfifoChidMgrReserveSystemChids(pGpu, pKernelFifo, + pChidMgr, currentNumChannels, flags, + gfid, + pChidOffset, + heapOffset, + pChannelCount, + pMigDevice, + engineFifoListNumEntries, + engineFifoList)); + + // Mark as processed + mask |= NVBIT64(runlistId); + + // Stop looping in case per runlist chidmgr is not enabled + if (pKernelFifo->numChidMgrs == 1) + break; + } + + return NV_OK; } void @@ -60,4 +237,53 @@ vgpuMgrFreeSystemChannelIDs FIFO_ENGINE_LIST *engineFifoList ) { + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + NvU64 mask = 0; + NvU32 i; + + NV_ASSERT_OR_RETURN_VOID(engineFifoListNumEntries != 0); + + // Last entry is ENG_SW. Don't include that + for (i = 0; i < engineFifoListNumEntries - 1; i++) + { + NvU32 runlistId; + CHID_MGR *pChidMgr; + + // + // This code needs the physical runlist ID. ENGINE_INFO_TYPE_FIFO_TAG is not virtualized currently, + // and hence we can use a trick to translate it to the physical runlist ID using the host's device table. + // In the future, if we virtualize all of the data in engineData, we'll need a translation from virtual to physical IDs + // + NV_ASSERT_OR_RETURN_VOID(kfifoEngineInfoXlate_HAL(pGpu, pKernelFifo, + ENGINE_INFO_TYPE_FIFO_TAG, + engineFifoList[i].engineData[ENGINE_INFO_TYPE_FIFO_TAG], + ENGINE_INFO_TYPE_RUNLIST, + &runlistId) == NV_OK); + + pChidMgr = kfifoGetChidMgr(pGpu, pKernelFifo, runlistId); + + // + // Some engines (like GR and GRCE) may share a single runlist. + // So, don't process any runlist twice. + // + if (mask & NVBIT64(runlistId)) + continue; + + NV_ASSERT_OR_RETURN_VOID(kfifoChidMgrFreeSystemChids(pGpu, + pKernelFifo, + pChidMgr, + gfid, + pChidOffset, + pChannelCount, + pMigDevice, + engineFifoListNumEntries, + engineFifoList) == NV_OK); + + // Mark the runlist as processed + mask |= NVBIT64(runlistId); + + // Stop looping in case per runlist chidmgr is not enabled + if (pKernelFifo->numChidMgrs == 1) + break; + } } diff --git a/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c index 48cf63a509..c8042e9051 100644 --- a/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c +++ b/src/nvidia/src/kernel/virtualization/hypervisor/hypervisor.c @@ -26,6 +26,7 @@ * @brief Hypervisor interface for RM */ +#include "gpu_mgr/gpu_mgr.h" #include "gpu/gpu.h" #include "virtualization/hypervisor/hypervisor.h" #include "os/os.h" diff --git a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c index 05e4c8f3cf..3bfd58fd29 100644 --- a/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c +++ b/src/nvidia/src/kernel/virtualization/kernel_hostvgpudeviceapi.c @@ -24,6 +24,31 @@ #include "virtualization/kernel_hostvgpudeviceapi.h" #include "virtualization/vgpuconfigapi.h" +#include "core/core.h" +#include "core/locks.h" +#include "os/os.h" +#include "virtualization/kernel_hostvgpudeviceapi.h" +#include "dev_ctrl_defines.h" +#include "mem_mgr/mem.h" +#include "kernel/gpu/bif/kernel_bif.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "kernel/gpu/gpu_engine_type.h" +#include "gpu/device/device.h" +#include "gpu/intr/intr.h" +#include "gpu/subdevice/subdevice.h" +#include "gpu/mem_mgr/virt_mem_allocator_common.h" +#include "nv_sriov_defines.h" +#include "virtualization/hypervisor/hypervisor.h" +#include "virtualization/kernel_vgpu_mgr.h" +#include "kernel/gpu/gsp/kernel_gsp.h" +#include "nvpcie.h" +#include "kernel/rmapi/rs_utils.h" +#include "vgpu/vgpu_events.h" +#include "gpu/mem_sys/kern_mem_sys.h" + +ct_assert(NVA084_MAX_VMMU_SEGMENTS == NV2080_CTRL_MAX_VMMU_SEGMENTS); +ct_assert(NV2080_GPU_MAX_ENGINES == RM_ENGINE_TYPE_LAST); + NV_STATUS kernelhostvgpudeviceshrConstruct_IMPL ( @@ -49,7 +74,259 @@ kernelhostvgpudeviceapiConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS status = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NVA084_ALLOC_PARAMETERS *pAllocParams = pParams->pAllocParams; + NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS *pBootloadParams = NULL; + Memory *pMemory; + NvU32 i; + NvU64 vmmuSegmentSize; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = NULL; + RsShared *pShared; + Device *pDevice; + RsClient *pClient = NULL; + + // Forbid allocation of this class on Guest-RM + // to avoid fuzzing this class in such cases. See bug 3529160. + if (IS_VIRTUAL(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + NV_ASSERT_OK_OR_RETURN(deviceGetByGpu(pCallContext->pClient, pGpu, NV_TRUE, &pDevice)); + + if (RS_IS_COPY_CTOR(pParams)) + { + return kernelhostvgpudeviceapiCopyConstruct_IMPL(pKernelHostVgpuDeviceApi, pCallContext, pParams); + } + + pClient = pCallContext->pClient; + + status = kvgpumgrGuestRegister(pGpu, + pAllocParams->gfid, + pAllocParams->vgpuType, + pAllocParams->vmPid, + pAllocParams->vmIdType, + pAllocParams->guestVmId, + pClient->hClient, + pAllocParams->numChannels, + pAllocParams->numPluginChannels, + pAllocParams->swizzId, + pAllocParams->vgpuDeviceInstanceId, + pAllocParams->bDisableDefaultSmcExecPartRestore, + pAllocParams->placementId, + &pKernelHostVgpuDevice); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to register HOST_VGPU_DEVICE object\n"); + return status; + } + + status = serverAllocShare(&g_resServ, classInfo(KernelHostVgpuDeviceShr), &pShared); + if (status != NV_OK) + goto allocShareError; + pKernelHostVgpuDeviceApi->pShared = dynamicCast(pShared, KernelHostVgpuDeviceShr); + pKernelHostVgpuDeviceApi->pShared->pDevice = pKernelHostVgpuDevice; + pKernelHostVgpuDevice->pGspPluginHeapMemDesc = NULL; + + if (IS_GSP_CLIENT(pGpu)) + { + KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) || !gpuIsSriovEnabled(pGpu)) + { + status = NV_ERR_NOT_SUPPORTED; + goto done; + } + + if (pAllocParams->numGuestFbHandles == 0 || pAllocParams->numGuestFbHandles > NVA084_MAX_VMMU_SEGMENTS) + { + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + vmmuSegmentSize = gpuGetVmmuSegmentSize(pGpu); + if (vmmuSegmentSize == 0) + { + status = NV_ERR_INVALID_STATE; + goto done; + } + + // This structure can't be allocated on stack because it will result function stack usage > 4KB + pBootloadParams = portMemAllocNonPaged(sizeof(*pBootloadParams)); + if (pBootloadParams == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + portMemSet(pBootloadParams, 0, sizeof(*pBootloadParams)); + + if (gpuIsSelfHosted(pGpu)) + { + pKernelHostVgpuDevice->hbmRegionList = portMemAllocNonPaged(sizeof(HBM_REGION_INFO)* pAllocParams->numGuestFbHandles); + if (pKernelHostVgpuDevice->hbmRegionList == NULL) + { + status = NV_ERR_NO_MEMORY; + goto done; + } + + pKernelHostVgpuDevice->numValidHbmRegions = 0; + } + + for (i = 0; i < pAllocParams->numGuestFbHandles; i++) + { + status = memGetByHandle(pClient, pAllocParams->guestFbHandleList[i], &pMemory); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Invalid Memory handle\n"); + goto done; + } + pBootloadParams->guestFbPhysAddrList[i] = memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU, 0); + pBootloadParams->guestFbLengthList[i] = pMemory->pMemDesc->Size; + + if (!NV_IS_ALIGNED64(pBootloadParams->guestFbPhysAddrList[i], vmmuSegmentSize) || + !NV_IS_ALIGNED64(pBootloadParams->guestFbLengthList[i], vmmuSegmentSize)) + { + NV_PRINTF(LEVEL_ERROR, "guest fb segment PA or length is not VMMU segment size aligned\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + if (gpuIsSelfHosted(pGpu)) + { + pKernelHostVgpuDevice->hbmRegionList[i].hbmBaseAddr = memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU, 0); + pKernelHostVgpuDevice->hbmRegionList[i].hbmBaseAddr += pKernelMemorySystem->coherentCpuFbBase; + pKernelHostVgpuDevice->hbmRegionList[i].size = pMemory->pMemDesc->Size; + pKernelHostVgpuDevice->numValidHbmRegions++; + } + } + + status = memGetByHandle(pClient, pAllocParams->hPluginHeapMemory, &pMemory); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Invalid plugin heap Memory handle\n"); + goto done; + } + + pKernelHostVgpuDevice->pGspPluginHeapMemDesc = pMemory->pMemDesc; + + // As GSP-RM will map this memory in vGPU-GSP-Plugin's address space, it + // should be referenced to make sure it doesn't get freed before + // vGPU-Gsp-Plugin's usage has been removed + memdescAddRef(pKernelHostVgpuDevice->pGspPluginHeapMemDesc); + + pBootloadParams->pluginHeapMemoryPhysAddr = memdescGetPhysAddr(pMemory->pMemDesc, AT_GPU, 0); + pBootloadParams->pluginHeapMemoryLength = pMemory->pMemDesc->Size; + + // Initialize logging buffers for vgpu partition + { + if ((pAllocParams->initTaskLogBuffOffset + pAllocParams->initTaskLogBuffSize) >= + pBootloadParams->pluginHeapMemoryLength) + { + NV_PRINTF(LEVEL_ERROR, "Invalid init task log buffer\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + if ((pAllocParams->vgpuTaskLogBuffOffset + pAllocParams->vgpuTaskLogBuffSize) >= + pBootloadParams->pluginHeapMemoryLength) + { + NV_PRINTF(LEVEL_ERROR, "Invalid vgpu task log buffer\n"); + status = NV_ERR_INVALID_ARGUMENT; + goto done; + } + + pBootloadParams->initTaskLogBuffOffset = pAllocParams->initTaskLogBuffOffset + pBootloadParams->pluginHeapMemoryPhysAddr; + pBootloadParams->initTaskLogBuffSize = pAllocParams->initTaskLogBuffSize; + pBootloadParams->vgpuTaskLogBuffOffset = pAllocParams->vgpuTaskLogBuffOffset + pBootloadParams->pluginHeapMemoryPhysAddr; + pBootloadParams->vgpuTaskLogBuffSize = pAllocParams->vgpuTaskLogBuffSize; + + NV_CHECK_OK_OR_GOTO(status, + LEVEL_ERROR, + kgspInitVgpuPartitionLogging_HAL(pGpu, pKernelGsp, pAllocParams->gfid, + pBootloadParams->initTaskLogBuffOffset, + pBootloadParams->initTaskLogBuffSize, + pBootloadParams->vgpuTaskLogBuffOffset, + pBootloadParams->vgpuTaskLogBuffSize), + done); + } + + + pBootloadParams->gfid = pAllocParams->gfid; + pBootloadParams->swizzId = pAllocParams->swizzId; + pBootloadParams->numGuestFbSegments = pAllocParams->numGuestFbHandles; + pBootloadParams->ctrlBuffOffset = pAllocParams->ctrlBuffOffset; + pBootloadParams->bDeviceProfilingEnabled = pAllocParams->bDeviceProfilingEnabled; + + // Populate chidOffset for all engines to reserve same chid in GSP-RM + for (i = 0; i < RM_ENGINE_TYPE_LAST; i++) + { + NvU32 nv2080EngineType = gpuGetNv2080EngineType(i); + + // + // pHostVgpuDevice->chidOffset is in RM_ENGINE_TYPE order + // pBootloadParams->chidOffset is in NV2080_ENGINE_TYPE order + // + pBootloadParams->chidOffset[nv2080EngineType] = pKernelHostVgpuDevice->chidOffset[i]; + } + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK, + pBootloadParams, sizeof(*pBootloadParams)); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to call NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK\n"); + goto freeLogging; + } + } + + if (status == NV_OK) + { + if (pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE) + { + if (pDevice->pKernelHostVgpuDevice != NULL) + { + status = NV_ERR_INVALID_STATE; + goto freeLogging; + } + pDevice->pKernelHostVgpuDevice = pKernelHostVgpuDevice; + } + + CliNotifyVgpuConfigEvent(pGpu, NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED); + } + +freeLogging: + if (status != NV_OK && IS_GSP_CLIENT(pGpu) && pBootloadParams != NULL) + { + // Free vgpu partition LIBOS task logging structures. + NV_ASSERT_OK(kgspFreeVgpuPartitionLogging_HAL(pGpu, pKernelGsp, pKernelHostVgpuDevice->gfid)); + } + +done: + portMemFree(pBootloadParams); + + if (status != NV_OK) + { + if (pKernelHostVgpuDevice->hbmRegionList != NULL) + { + portMemFree(pKernelHostVgpuDevice->hbmRegionList); + pKernelHostVgpuDevice->hbmRegionList = NULL; + pKernelHostVgpuDevice->numValidHbmRegions = 0; + } + + if (pKernelHostVgpuDevice->pGspPluginHeapMemDesc != NULL) + { + memdescRemoveRef(pKernelHostVgpuDevice->pGspPluginHeapMemDesc); + pKernelHostVgpuDevice->pGspPluginHeapMemDesc = NULL; + } + + serverFreeShare(&g_resServ, pShared); + } + +allocShareError: + if (status != NV_OK) + kvgpumgrGuestUnregister(pGpu, pKernelHostVgpuDevice); + + return status; } NvBool @@ -69,12 +346,86 @@ kernelhostvgpudeviceapiCopyConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - return NV_ERR_NOT_SUPPORTED; + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApiSrc = dynamicCast(pParams->pSrcRef->pResource, KernelHostVgpuDeviceApi); + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + Device *pDevice; + + if (pKernelHostVgpuDeviceApiSrc == NULL) + return NV_ERR_INVALID_ARGUMENT; + + NV_ASSERT_OK_OR_RETURN(deviceGetByGpu(pCallContext->pClient, pGpu, NV_TRUE, &pDevice)); + + serverRefShare(&g_resServ, staticCast(pKernelHostVgpuDeviceApiSrc->pShared, RsShared)); + pKernelHostVgpuDeviceApi->pShared = pKernelHostVgpuDeviceApiSrc->pShared; + + if (pDevice->deviceAllocFlags & NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE) + { + if (pDevice->pKernelHostVgpuDevice != NULL) + return NV_ERR_INVALID_STATE; + pDevice->pKernelHostVgpuDevice = pKernelHostVgpuDeviceApi->pShared->pDevice; + } + + return NV_OK; } void destroyKernelHostVgpuDeviceShare(OBJGPU *pGpu, KernelHostVgpuDeviceShr* pShare) { + + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = pShare->pDevice; + RsShared *pShared = staticCast(pShare, RsShared); + NvS32 refCount; + NV_STATUS status; + + refCount = serverGetShareRefCount(&g_resServ, pShared); + serverFreeShare(&g_resServ, pShared); + if (refCount > 1) + return; + + Device *pDevice = vgpuGetCallingContextDevice(pGpu); + + NV_ASSERT(pDevice != NULL); + if (pDevice != NULL) + { + pDevice->pKernelHostVgpuDevice = NULL; + } + + if (IS_GSP_CLIENT(pGpu)) + { + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK_PARAMS shutdownParams = { 0 }; + NV2080_CTRL_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP_PARAMS cleanupResourcesParams = {0}; + + shutdownParams.gfid = pKernelHostVgpuDevice->gfid; + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK, + &shutdownParams, sizeof(shutdownParams)); + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "Failed to call NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SHUTDOWN_GSP_VGPU_PLUGIN_TASK\n"); + + cleanupResourcesParams.gfid = pKernelHostVgpuDevice->gfid; + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_VGPU_PLUGIN_CLEANUP, + &cleanupResourcesParams, sizeof(cleanupResourcesParams)); + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "Failed to call cleanup plugin resources\n"); + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && pKernelHostVgpuDevice->pGspPluginHeapMemDesc != NULL) + { + memdescDestroy(pKernelHostVgpuDevice->pGspPluginHeapMemDesc); + } + + // Free vgpu partition LIBOS task logging structures. + KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu); + kgspFreeVgpuPartitionLogging(pGpu, pKernelGsp, pKernelHostVgpuDevice->gfid); + } + + status = kvgpumgrGuestUnregister(pGpu, pKernelHostVgpuDevice); + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "Failed to unregister HOST_VGPU_DEVICE object\n"); + + CliNotifyVgpuConfigEvent(pGpu, NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED); } void @@ -83,6 +434,8 @@ kernelhostvgpudeviceapiDestruct_IMPL KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi ) { + destroyKernelHostVgpuDeviceShare(GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi), + pKernelHostVgpuDeviceApi->pShared); } NV_STATUS @@ -92,7 +445,18 @@ kernelhostvgpudeviceapiCtrlCmdSetVgpuDeviceInfo_IMPL NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_DEVICE_INFO_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + pKernelHostVgpuDevice = pKernelHostVgpuDeviceApi->pShared->pDevice; + + portMemCopy(pKernelHostVgpuDevice->vgpuUuid, RM_SHA1_GID_SIZE, pParams->vgpuUuid, RM_SHA1_GID_SIZE); + + CliNotifyVgpuConfigEvent(pGpu, NVA081_NOTIFIERS_EVENT_VGPU_GUEST_CREATED); + + return NV_OK; } NV_STATUS @@ -102,7 +466,17 @@ kernelhostvgpudeviceapiCtrlCmdSetVgpuGuestLifeCycleState_IMPL NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_VGPU_GUEST_LIFE_CYCLE_STATE_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + NV_STATUS status = NV_OK; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (pParams->vmLifeCycleState == NVA081_NOTIFIERS_EVENT_VGPU_GUEST_DESTROYED) + status = kvgpumgrClearGuestVmInfo(pGpu, pKernelHostVgpuDeviceApi->pShared->pDevice); + + CliNotifyVgpuConfigEvent(pGpu, pParams->vmLifeCycleState); + + return status; } NV_STATUS @@ -125,6 +499,74 @@ kernelhostvgpudeviceapiCtrlCmdBindFecsEvtbuf_IMPL return NV_ERR_NOT_SUPPORTED; } +static NV_STATUS +_kernelhostvgpudeviceValidateOfflinedPageInfoAndGetSpa +( + OBJGPU *pGpu, + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, + NvU64 gpa, + NvHandle hMemory, + NvU64 size, + NvU64 *Spa +) +{ + NV_STATUS status = NV_OK; + Memory *pMemoryInfo = NULL; + RsClient *pClient = NULL; + + // Validate GPA from offlined page list + if (pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.bValid) + { + NvU64 guestFbLength = pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.length; + + NV_ASSERT_OR_RETURN((gpa < guestFbLength) && + (size < guestFbLength) && + ((gpa + size) < guestFbLength), + NV_ERR_OUT_OF_RANGE); + } + + // Validate SPA from good backup page list + status = serverGetClientUnderLock(&g_resServ, pKernelHostVgpuDevice->hPluginFBAllocationClient, &pClient); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get pClient\n"); + return NV_ERR_INVALID_CLIENT; + } + + status = memGetByHandle(pClient, hMemory, &pMemoryInfo); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Invalid Memory handle\n"); + return status; + } + + *Spa = memdescGetPhysAddr(pMemoryInfo->pMemDesc, AT_GPU, 0); + + return status; +} + +static NV_STATUS +_kernelhostvgpudeviceGetFbSegmentPageShift +( + NvU64 guestFbSegmentPageSize, + NvU32 *guestFbSegmentPageShift +) +{ + switch (guestFbSegmentPageSize) + { + case RM_PAGE_SIZE_HUGE: + *guestFbSegmentPageShift = RM_PAGE_SHIFT_HUGE; + break; + case RM_PAGE_SIZE_64K: + *guestFbSegmentPageShift = RM_PAGE_SHIFT_64K; + break; + default: + return NV_ERR_INVALID_ARGUMENT; + } + + return NV_OK; +} + NV_STATUS kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo_IMPL ( @@ -132,7 +574,80 @@ kernelhostvgpudeviceapiCtrlCmdSetOfflinedPagePatchInfo_IMPL NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_SET_OFFLINED_PAGE_PATCHINFO_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + NvU32 guestPageCount; + NvU32 hpfn; + NvU32 i; + NvU32 index; + NvU32 guestFbSegmentPageShift; + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + NvBool bPageRetirementEnabled = NV_FALSE; + NvU64 Spa = 0; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + bPageRetirementEnabled = (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT) && + gpuCheckPageRetirementSupport_HAL(pGpu)); + + if (gpuIsSriovEnabled(pGpu) || !bPageRetirementEnabled) + { + return NV_ERR_NOT_SUPPORTED; + } + + pKernelHostVgpuDevice = pKernelHostVgpuDeviceApi->pShared->pDevice; + if (pKernelHostVgpuDevice && pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.bValid) + { + rmStatus = _kernelhostvgpudeviceGetFbSegmentPageShift(pParams->guestFbSegmentPageSize, &guestFbSegmentPageShift); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Invalid Guest FB Segment Page Size\n"); + return rmStatus; + } + + guestPageCount = pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.length >> guestFbSegmentPageShift; + hpfn = pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.offset >> guestFbSegmentPageShift; + + NV_ASSERT_OR_RETURN((pParams->offlinedPageCount <= NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES), NV_ERR_OUT_OF_RANGE); + + pKernelHostVgpuDevice->pGuestFbSegment = portMemAllocNonPaged(sizeof(NvU32) * guestPageCount); + if (pKernelHostVgpuDevice->pGuestFbSegment == NULL) + { + NV_PRINTF(LEVEL_ERROR, "GuestFbSegment allocation failed\n"); + return NV_ERR_NO_MEMORY; + } + + // Initialize the default hpfn of each segment. + for (i = 0; i < guestPageCount; i++) + { + pKernelHostVgpuDevice->pGuestFbSegment[i] = hpfn + i; + } + + // Patch offlined page with good page. + for (i = 0; i < pParams->offlinedPageCount ;i++) + { + rmStatus = _kernelhostvgpudeviceValidateOfflinedPageInfoAndGetSpa(pGpu, pKernelHostVgpuDevice, pParams->gpa[i], pParams->hMemory[i], + pParams->guestFbSegmentPageSize, &Spa); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Offlined Page info Validation Failed\n"); + portMemFree(pKernelHostVgpuDevice->pGuestFbSegment); + pKernelHostVgpuDevice->pGuestFbSegment = NULL; + return rmStatus; + } + + index = pParams->gpa[i] >> guestFbSegmentPageShift; + pKernelHostVgpuDevice->pGuestFbSegment[index] = Spa >> guestFbSegmentPageShift; + pKernelHostVgpuDevice->offlinedPageGpa[i] = pParams->gpa[i]; + } + + pKernelHostVgpuDevice->guestFbSegmentPageSize = pParams->guestFbSegmentPageSize; + pKernelHostVgpuDevice->offlinedPageCount = pParams->offlinedPageCount; + pKernelHostVgpuDevice->bOfflinedPageInfoValid = NV_TRUE; + } + + return rmStatus; } NV_STATUS @@ -143,7 +658,17 @@ kernelhostvgpudeviceGetGuestFbInfo VGPU_DEVICE_GUEST_FB_INFO *pFbInfo ) { - return NV_ERR_NOT_SUPPORTED; + if (gpuIsSriovEnabled(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + *pFbInfo = pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo; + + return NV_OK; } NV_STATUS @@ -155,7 +680,17 @@ kernelhostvgpudeviceSetGuestFbInfo NvU64 length ) { - return NV_ERR_NOT_SUPPORTED; + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + if (gpuIsSriovEnabled(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.bValid = NV_TRUE; + pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.offset = offset; + pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.length = length; + + return NV_OK; } NV_STATUS @@ -165,7 +700,28 @@ kernelhostvgpudeviceapiCtrlCmdTriggerPrivDoorbell_IMPL NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_TRIGGER_PRIV_DOORBELL_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + Intr *pIntr = GPU_GET_INTR(pGpu); + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = pKernelHostVgpuDeviceApi->pShared->pDevice; + NvU32 handle; + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(pParams->handle == NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_HANDLE, + NV_ERR_INVALID_ARGUMENT); + + LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner() && rmGpuLockIsOwner()); + + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) || + !gpuIsSriovEnabled(pGpu) || IS_VIRTUAL(pGpu)) + { + return NV_ERR_NOT_SUPPORTED; + } + + handle = NV_CTRL_INTR_LEAF_IDX_TO_GPU_VECTOR_START(pKernelHostVgpuDevice->gfid) + pParams->handle; + + status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, handle); + + return status; } NV_STATUS @@ -175,7 +731,55 @@ kernelhostvgpudeviceapiCtrlCmdEventSetNotification_IMPL NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS status = NV_OK; + + // NV01_EVENT must have been plugged into this subdevice + if (inotifyGetNotificationList(staticCast(pKernelHostVgpuDeviceApi, INotifier)) == NULL) + { + NV_PRINTF(LEVEL_ERROR, "cmd 0x%x: no event list\n", + NVA084_CTRL_CMD_KERNEL_HOST_VGPU_DEVICE_EVENT_SET_NOTIFICATION); + return NV_ERR_INVALID_STATE; + } + + if (pSetEventParams->event >= NVA084_NOTIFIERS_MAXCOUNT) + { + NV_PRINTF(LEVEL_ERROR, "bad event 0x%x\n", pSetEventParams->event); + return NV_ERR_INVALID_ARGUMENT; + } + + // + // @todo: We will define the actual event values later based on the use case. + // These event values are only for Test purpose. + // + switch (pSetEventParams->action) + { + case NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE: + case NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT: + { + // must be in disabled state to transition to an active state + if (pKernelHostVgpuDeviceApi->notifyActions[pSetEventParams->event] != NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE) + { + status = NV_ERR_INVALID_STATE; + break; + } + + pKernelHostVgpuDeviceApi->notifyActions[pSetEventParams->event] = pSetEventParams->action; + break; + } + + case NVA084_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE: + { + pKernelHostVgpuDeviceApi->notifyActions[pSetEventParams->event] = pSetEventParams->action; + break; + } + default: + { + status = NV_ERR_INVALID_ARGUMENT; + break; + } + } + + return status; } NV_STATUS @@ -185,7 +789,83 @@ kernelhostvgpudeviceapiCtrlCmdGetBarMappingRanges_IMPL NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_GET_BAR_MAPPING_RANGES_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + NvU64 prevOffset = 0, prevSize = 0; + NvU64 vfRegionOffsets[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES]; + NvU64 vfRegionSizes[NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES]; + KernelBif *pKernelBif = GPU_GET_KERNEL_BIF(pGpu); + NvU32 numAreas = 0, i = 0, j = 0; + + NV_ASSERT_OR_RETURN(pKernelBif != NULL, NV_ERR_INVALID_STATE); + + pKernelHostVgpuDevice = pKernelHostVgpuDeviceApi->pShared->pDevice; + NV_ASSERT_OR_RETURN(pKernelHostVgpuDevice != NULL, NV_ERR_INVALID_STATE); + + // Get the total number of ranges + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbifGetVFSparseMmapRegions_HAL( + pGpu, + pKernelBif, + pKernelHostVgpuDevice, + pParams->osPageSize, + &numAreas, + NULL, + NULL)); + + NV_ASSERT_OR_RETURN(numAreas <= NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES, NV_ERR_INVALID_STATE); + + // Fill the regions + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kbifGetVFSparseMmapRegions_HAL( + pGpu, + pKernelBif, + pKernelHostVgpuDevice, + pParams->osPageSize, + &numAreas, + vfRegionOffsets, + vfRegionSizes)); + + if (numAreas == 0 || numAreas > NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_MAX_BAR_MAPPING_RANGES) + return NV_ERR_INVALID_STATE; + + for (i = 0, j = 0; i < numAreas; i++) + { + if (i == 0 && vfRegionOffsets[i] == prevOffset) + { + pParams->offsets[j] = vfRegionOffsets[i]; + pParams->sizes[j] = vfRegionSizes[i]; + pParams->mitigated[j] = NV_FALSE; + j++; + } + else + { + pParams->offsets[j] = prevOffset + prevSize; + pParams->sizes[j] = vfRegionOffsets[i] - pParams->offsets[j]; + pParams->mitigated[j] = NV_TRUE; + j++; + + pParams->offsets[j] = vfRegionOffsets[i]; + pParams->sizes[j] = vfRegionSizes[i]; + pParams->mitigated[j] = NV_FALSE; + j++; + } + + prevOffset = vfRegionOffsets[i]; + prevSize = vfRegionSizes[i]; + } + + i = numAreas - 1; + if ((vfRegionOffsets[i] + vfRegionSizes[i]) != pGpu->sriovState.vfBarSize[0]) + { + pParams->offsets[j] = vfRegionOffsets[i] + vfRegionSizes[i]; + pParams->sizes[j] = pGpu->sriovState.vfBarSize[0] - pParams->offsets[j]; + pParams->mitigated[j] = NV_TRUE; + j++; + } + + pParams->numRanges = j; + return NV_OK; } NV_STATUS @@ -194,5 +874,61 @@ kernelhostvgpudeviceapiCtrlCmdRestoreDefaultExecPartition_IMPL KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi ) { - return NV_ERR_NOT_SUPPORTED; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + + pKernelHostVgpuDevice = pKernelHostVgpuDeviceApi->pShared->pDevice; + NV_ASSERT_OR_RETURN(pKernelHostVgpuDevice != NULL, NV_ERR_INVALID_STATE); + + if (pKernelHostVgpuDevice->bDisableDefaultSmcExecPartRestore) + { + NV_PRINTF(LEVEL_ERROR, "Default MIG compute instance save/restore disabled\n"); + return NV_ERR_INVALID_STATE; + } + + if (IS_MIG_IN_USE(pGpu)) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + // + // This function should only be called when MIG is enabled and should be + // called for partitionable engines only + // + NV_ASSERT_OK_OR_RETURN(kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, + pKernelHostVgpuDevice->swizzId, + &pKernelMIGGpuInstance)); + + NV_ASSERT_OK_OR_RETURN(kvgpuMgrRestoreSmcExecPart(pGpu, + pKernelHostVgpuDevice, + pKernelMIGGpuInstance)); + } + else + { + return NV_ERR_NOT_SUPPORTED; + } + + return NV_OK; +} + +NV_STATUS +kernelhostvgpudeviceapiCtrlCmdFreeStates_IMPL +( + KernelHostVgpuDeviceApi *pKernelHostVgpuDeviceApi, + NVA084_CTRL_KERNEL_HOST_VGPU_DEVICE_FREE_STATES_PARAMS* pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pKernelHostVgpuDeviceApi); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = pKernelHostVgpuDeviceApi->pShared->pDevice; + + NV2080_CTRL_VGPU_MGR_INTERNAL_FREE_STATES_PARAMS params; + params.gfid = pKernelHostVgpuDevice->gfid; + params.flags = pParams->flags; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_FREE_STATES, ¶ms, sizeof(params))); + + return NV_OK; } diff --git a/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c b/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c index f8b39a9c36..bd416df042 100644 --- a/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c +++ b/src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c @@ -25,6 +25,41 @@ #include "class/clc637.h" // for AMPERE_SMC_PARTITION_REF #include "virtualization/kernel_hostvgpudeviceapi.h" +#include "core/system.h" +#include "os/os.h" +#include "rmapi/control.h" +#include "virtualization/hypervisor/hypervisor.h" +#include "virtualization/kernel_vgpu_mgr.h" +#include "gpu/device/device.h" +#include "vgpu/vgpu_version.h" +#include "rmapi/rmapi_utils.h" +#include "rmapi/rs_utils.h" +#include "gpu/gpu.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_mgr/heap.h" +#include "kernel/gpu/mig_mgr/kernel_mig_manager.h" +#include "nvdevid.h" + +#define __VGPU_ALIAS_PGPU_LIST__ +#include "g_vgpu_resman_specific.h" // _get_chip_id_for_alias_pgpu +#undef __VGPU_ALIAS_PGPU_LIST__ + +#define MAX_NVU32_TO_CONVERTED_STR_LEN 0x8 + +#define DEVID_ENCODED_VALUE_SIZE 0x4 +#define SUBDEVID_ENCODED_VALUE_SIZE 0x4 +#define PGPU_CAP_ENCODED_VALUE_SIZE 0x8 + +#define PGPU_CAP_ECC_ON (1 << 0) +#define PGPU_CAP_SRIOV_ON (1 << 1) + +#define VGPU_LOWER_FB_PROFILE_SIZE_1_GB (1024 * 1024 * 1024) + +// Mapping of vGPU MIG profiles types to corresponding RM partiotionFlag +#define GENERATE_vgpuSmcTypeIdMappings +#include "g_vgpu_resman_specific.h" +#undef GENERATE_vgpuSmcTypeIdMappings // // ODB functions // @@ -32,12 +67,37 @@ NV_STATUS kvgpumgrConstruct_IMPL(KernelVgpuMgr *pKernelVgpuMgr) { + NV_PRINTF(LEVEL_INFO, "Enter function\n"); + + pKernelVgpuMgr->pHeap = NULL; + + /* Default vGPU version is set to the host supported vGPU version range */ + pKernelVgpuMgr->user_min_supported_version + = GRIDSW_VERSION_EXTERNAL(NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR, + NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR); + pKernelVgpuMgr->user_max_supported_version + = GRIDSW_VERSION_EXTERNAL(NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR, + NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR); + + listInit(&(pKernelVgpuMgr->listVgpuTypeHead), portMemAllocatorGetGlobalNonPaged()); + listInit(&(pKernelVgpuMgr->listVgpuGuestHead), portMemAllocatorGetGlobalNonPaged()); + listInit(&(pKernelVgpuMgr->listRequestVgpuHead), portMemAllocatorGetGlobalNonPaged()); + return NV_OK; } void kvgpumgrDestruct_IMPL(KernelVgpuMgr *pKernelVgpuMgr) { + if (pKernelVgpuMgr->pHeap != NULL) + { + pKernelVgpuMgr->pHeap->eheapDestruct(pKernelVgpuMgr->pHeap); + portMemFree(pKernelVgpuMgr->pHeap); + } + + listDestroy(&(pKernelVgpuMgr->listRequestVgpuHead)); + listDestroy(&(pKernelVgpuMgr->listVgpuTypeHead)); + listDestroy(&(pKernelVgpuMgr->listVgpuGuestHead)); } // @@ -46,43 +106,375 @@ kvgpumgrDestruct_IMPL(KernelVgpuMgr *pKernelVgpuMgr) NV_STATUS kvgpumgrGetMaxInstanceOfVgpu(NvU32 vgpuTypeId, NvU32 *maxInstanceVgpu) { - return NV_ERR_NOT_SUPPORTED; + VGPU_TYPE *vgpuTypeInfo; + NV_STATUS status; + + if (maxInstanceVgpu == NULL) + { + return NV_ERR_INVALID_ARGUMENT; + } + + status = kvgpumgrGetVgpuTypeInfo(vgpuTypeId, &vgpuTypeInfo); + if (status == NV_OK) + { + *maxInstanceVgpu = vgpuTypeInfo->maxInstance; + } + + return status; } +// +// vGPU Manager functions +// + +static NV_STATUS +_kvgpumgrGetVgpuTypeIdFromPartitionFlag(NvU32 devId, NvU32 partitionFlag, NvU32 *vgpuTypeId); + +static NV_STATUS +_kvgpumgrClearAssignedSwizzIdMask(OBJGPU *pGpu, + NvU32 swizzId); + +static NV_STATUS +_kvgpumgrUpdateCreatablePlacementIds(OBJGPU *pGpu, NvU16 placementId, + NvU32 vgpuTypeId, NvBool isVmBoot); + NV_STATUS kvgpumgrGetPgpuIndex(KernelVgpuMgr *pKernelVgpuMgr, NvU32 gpuPciId, NvU32* index) { + NvU32 i; + for (i = 0; i < NV_ARRAY_ELEMENTS(pKernelVgpuMgr->pgpuInfo); i++) + { + if ((pKernelVgpuMgr->pgpuInfo[i].gpuPciId == gpuPciId) && + (pKernelVgpuMgr->pgpuInfo[i].isAttached == NV_TRUE)) + { + *index = i; + return NV_OK; + } + } return NV_ERR_OBJECT_NOT_FOUND; } NvBool kvgpumgrIsHeterogeneousVgpuSupported(void) { - return NV_FALSE; + /*This support is currently limited to VMware and KVM*/ + return (osIsVgpuVfioPresent() == NV_OK); +} + +NV_STATUS +static _kvgpumgrSetVgpuType(OBJGPU *pGpu, KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, NvU32 vgpuTypeId) +{ + NvU32 i; + + /* + * If heterogeneous timesliced mode is enabled, supportedTypeIds is already + * prepared when creatable placementIds array is updated in + * _kvgpumgrUpdateCreatablePlacementIds() function + */ + if (pGpu && pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE)) + return NV_OK; + + for (i = 0; i < MAX_VGPU_TYPES_PER_PGPU; i++) + pPhysGpuInfo->supportedTypeIds[i] = NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE; + + if (vgpuTypeId == NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE) + { + for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++) + pPhysGpuInfo->supportedTypeIds[i] = pPhysGpuInfo->vgpuTypes[i]->vgpuTypeId; + + return NV_OK; + } + + if (kvgpumgrIsHeterogeneousVgpuSupported()) + { + VGPU_TYPE *vgpuTypeInfo = NULL; + NV_STATUS status = kvgpumgrGetVgpuTypeInfo(vgpuTypeId, &vgpuTypeInfo); + NvU32 numSupported = 0; + + if (status != NV_OK) + return status; + + NvU64 totalFbAllocation = vgpuTypeInfo->profileSize; + + for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++) + { + if (pPhysGpuInfo->vgpuTypes[i]->profileSize == totalFbAllocation) + { + pPhysGpuInfo->supportedTypeIds[numSupported] = pPhysGpuInfo->vgpuTypes[i]->vgpuTypeId; + numSupported++; + } + } + } + else + { + pPhysGpuInfo->supportedTypeIds[0] = vgpuTypeId; + } + + return NV_OK; +} + +static NV_STATUS +_kvgpumgrCheckVgpuTypeSupported(OBJGPU *pGpu, KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, + VGPU_TYPE *vgpuTypeInfo, NvU32 existingVgpus) +{ + NvU32 i; + + if (existingVgpus == 0) + return NV_OK; + + for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++) + { + if (pPhysGpuInfo->supportedTypeIds[i] == vgpuTypeInfo->vgpuTypeId) + break; + if (pPhysGpuInfo->supportedTypeIds[i] == NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE) + return NV_ERR_NOT_SUPPORTED; + } + + /* + * In heterogeneous vGPU mode, creatable vGPU type is not dependent on a vGPU types + * maxInstance. If the type is present in supportedTypeIds (populated based on placementIds), + * it should suffice + */ + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE)) + { + if (existingVgpus >= vgpuTypeInfo->maxInstance) + return NV_ERR_INSUFFICIENT_RESOURCES; + } + + return NV_OK; } NV_STATUS -kvgpumgrCheckVgpuTypeCreatable(KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, VGPU_TYPE *vgpuTypeInfo) +kvgpumgrCheckVgpuTypeCreatable(OBJGPU *pGpu, KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, VGPU_TYPE *vgpuTypeInfo) +{ + if (osIsVgpuVfioPresent() == NV_OK) + return _kvgpumgrCheckVgpuTypeSupported(pGpu, pPhysGpuInfo, vgpuTypeInfo, pPhysGpuInfo->numCreatedVgpu); + else + return _kvgpumgrCheckVgpuTypeSupported(pGpu, pPhysGpuInfo, vgpuTypeInfo, pPhysGpuInfo->numActiveVgpu); +} + +static NV_STATUS +_kvgpumgrCheckVgpuTypeActivatable(OBJGPU *pGpu, KERNEL_PHYS_GPU_INFO *pPhysGpuInfo, VGPU_TYPE *vgpuTypeInfo) { - return NV_ERR_NOT_SUPPORTED; + return _kvgpumgrCheckVgpuTypeSupported(pGpu, pPhysGpuInfo, vgpuTypeInfo, pPhysGpuInfo->numActiveVgpu); } NV_STATUS kvgpumgrGetCreatableVgpuTypes(OBJGPU *pGpu, KernelVgpuMgr *pKernelVgpuMgr, NvU32 pgpuIndex, NvU32* numVgpuTypes, NvU32* vgpuTypes) { - return NV_ERR_NOT_SUPPORTED; + NvU32 i = 0; + KERNEL_PHYS_GPU_INFO *pgpuInfo = &pKernelVgpuMgr->pgpuInfo[pgpuIndex]; + + if (IS_MIG_ENABLED(pGpu)) + { + if (IS_MIG_IN_USE(pGpu)) { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvU64 swizzIdInUseMask = 0; + NvU32 id; + + swizzIdInUseMask = kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager); + + i = 0; + FOR_EACH_INDEX_IN_MASK(64, id, swizzIdInUseMask) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + NvU32 vgpuTypeId = NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE; + NvU32 j, mask = 0; + + mask = NVBIT64(id); + NV_ASSERT_OK_OR_RETURN(kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, id, &pKernelMIGGpuInstance)); + + // Do not consider vGPU type as creatable if swizzId is already in use + if (!(mask & pgpuInfo->assignedSwizzIdMask)) + { + + // Find the vGPU type corresponding to the partitionFlag, + NV_ASSERT_OK_OR_RETURN( + _kvgpumgrGetVgpuTypeIdFromPartitionFlag(pGpu->idInfo.PCIDeviceID, + pKernelMIGGpuInstance->partitionFlag, + &vgpuTypeId)); + + // Check if we have already included this vGPU type ID. + // If not, then add vgpuTypeID to out vgpuTypes array. + if (vgpuTypeId != NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE) + { + for(j = 0; j < i; j++) + { + if (vgpuTypes[j] == vgpuTypeId) + { + break; + } + } + + if (j == i) + { + // vgpuTypeId not included in vgputypes array yet, include it. + vgpuTypes[i] = vgpuTypeId; + i++; + } + } + } + } + FOR_EACH_INDEX_IN_MASK_END; + *numVgpuTypes = i; + } + else + { + // No GPU instances created, none of the profiles are creatable. + *numVgpuTypes = 0; + } + } + else + { + *numVgpuTypes = 0; + + for (i = 0; i < pgpuInfo->numVgpuTypes; i++) + { + // Consider only non-MIG (gpuInstanceSize == 0) profiles + if (!pgpuInfo->vgpuTypes[i]->gpuInstanceSize && + (kvgpumgrCheckVgpuTypeCreatable(pGpu, pgpuInfo, pgpuInfo->vgpuTypes[i]) == NV_OK)) + { + vgpuTypes[*numVgpuTypes] = pgpuInfo->vgpuTypes[i]->vgpuTypeId; + (*numVgpuTypes)++; + } + } + } + + return NV_OK; +} + +static NV_STATUS +_kvgpumgrCreateVgpuType(NVA081_CTRL_VGPU_INFO *pVgpuInfo, VGPU_TYPE **ppVgpuType) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + VGPU_TYPE *pVgpuTypeNode; + + pVgpuTypeNode = listAppendNew(&(pKernelVgpuMgr->listVgpuTypeHead)); + if (pVgpuTypeNode == NULL) + return NV_ERR_NO_MEMORY; + + vgpuMgrFillVgpuType(pVgpuInfo, pVgpuTypeNode); + + *ppVgpuType = pVgpuTypeNode; + + return NV_OK; } NV_STATUS kvgpumgrGetVgpuTypeInfo(NvU32 vgpuTypeId, VGPU_TYPE **vgpuType) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + VGPU_TYPE *pVgpuTypeNode; + + for (pVgpuTypeNode = listHead(&(pKernelVgpuMgr->listVgpuTypeHead)); + pVgpuTypeNode != NULL; + pVgpuTypeNode = listNext(&(pKernelVgpuMgr->listVgpuTypeHead), pVgpuTypeNode)) + { + if (vgpuTypeId == pVgpuTypeNode->vgpuTypeId) + { + *vgpuType = pVgpuTypeNode; + return NV_OK; + } + } return NV_ERR_OBJECT_NOT_FOUND; } +static void +kvgpumgrCopyFromVgpuTypeToVgpuInfo(NVA081_CTRL_VGPU_INFO *pVgpuInfo, VGPU_TYPE *pVgpuType) +{ + pVgpuInfo->vgpuType = pVgpuType->vgpuTypeId; + pVgpuInfo->maxInstance = pVgpuType->maxInstance; + pVgpuInfo->numHeads = pVgpuType->numHeads; + pVgpuInfo->maxResolutionX = pVgpuType->maxResolutionX; + pVgpuInfo->maxResolutionY = pVgpuType->maxResolutionY; + pVgpuInfo->maxPixels = pVgpuType->maxPixels; + pVgpuInfo->frlConfig = pVgpuType->frlConfig; + pVgpuInfo->cudaEnabled = pVgpuType->cudaEnabled; + pVgpuInfo->eccSupported = pVgpuType->eccSupported; + pVgpuInfo->gpuInstanceSize = pVgpuType->gpuInstanceSize; + pVgpuInfo->multiVgpuSupported = pVgpuType->multiVgpuSupported; + pVgpuInfo->vdevId = pVgpuType->vdevId; + pVgpuInfo->pdevId = pVgpuType->pdevId; + pVgpuInfo->profileSize = pVgpuType->profileSize; + pVgpuInfo->fbLength = pVgpuType->fbLength; + pVgpuInfo->gspHeapSize = pVgpuType->gspHeapSize; + pVgpuInfo->fbReservation = pVgpuType->fbReservation; + pVgpuInfo->mappableVideoSize = pVgpuType->mappableVideoSize; + pVgpuInfo->encoderCapacity = pVgpuType->encoderCapacity; + pVgpuInfo->bar1Length = pVgpuType->bar1Length; + pVgpuInfo->gpuDirectSupported = pVgpuType->gpuDirectSupported; + pVgpuInfo->nvlinkP2PSupported = pVgpuType->nvlinkP2PSupported; + pVgpuInfo->multiVgpuExclusive = pVgpuType->multiVgpuExclusive; + pVgpuInfo->frlEnable = pVgpuType->frlEnable; + + portStringCopy( + (char *) pVgpuInfo->vgpuName, sizeof(pVgpuInfo->vgpuName), + (char *) pVgpuType->vgpuName, sizeof(pVgpuType->vgpuName)); + portStringCopy( + (char *) pVgpuInfo->vgpuClass, sizeof(pVgpuInfo->vgpuClass), + (char *) pVgpuType->vgpuClass, sizeof(pVgpuType->vgpuClass)); + portStringCopy( + (char *) pVgpuInfo->license, sizeof(pVgpuInfo->license), + (char *) pVgpuType->license, sizeof(pVgpuType->license)); + portStringCopy( + (char *) pVgpuInfo->vgpuExtraParams, sizeof(pVgpuInfo->vgpuExtraParams), + (char *) pVgpuType->vgpuExtraParams, sizeof(pVgpuType->vgpuExtraParams)); + portMemCopy( + (char *) pVgpuInfo->vgpuSignature, sizeof(pVgpuInfo->vgpuSignature), + (char *) pVgpuType->vgpuSignature, sizeof(pVgpuType->vgpuSignature)); +} + NV_STATUS kvgpumgrSendAllVgpuTypesToGsp(OBJGPU *pGpu) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS rmStatus = NV_OK; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *pAddVgpuTypeParams; + NvU32 index, i; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &index)); + + pPgpuInfo = &(pKernelVgpuMgr->pgpuInfo[index]); + + // Early exit if no vgpu types found + if (pPgpuInfo->numVgpuTypes == 0) + { + return NV_OK; + } + + pAddVgpuTypeParams = portMemAllocNonPaged(sizeof(*pAddVgpuTypeParams)); + if (pAddVgpuTypeParams == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to alloc memory for add vGPU type params\n"); + return NV_ERR_NO_MEMORY; + } + + portMemSet(pAddVgpuTypeParams, 0, sizeof(*pAddVgpuTypeParams)); + + for (i = 0; i < pPgpuInfo->numVgpuTypes; i++) + { + kvgpumgrCopyFromVgpuTypeToVgpuInfo(&pAddVgpuTypeParams->vgpuInfo[i], + pPgpuInfo->vgpuTypes[i]); + } + + pAddVgpuTypeParams->discardVgpuTypes = NV_TRUE; + pAddVgpuTypeParams->vgpuInfoCount = pPgpuInfo->numVgpuTypes; + + NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, + pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE, + pAddVgpuTypeParams, sizeof(*pAddVgpuTypeParams)), + kvgpumgrSendAllVgpuTypesToGsp_exit); + +kvgpumgrSendAllVgpuTypesToGsp_exit: + portMemFree(pAddVgpuTypeParams); + return rmStatus; } NV_STATUS @@ -93,18 +485,159 @@ kvgpumgrPgpuAddVgpuType NVA081_CTRL_VGPU_INFO *pVgpuInfo ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS rmStatus = NV_OK; + NvU32 index; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + VGPU_TYPE *pVgpuTypeInfo; + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS *pAddVgpuTypeParams; + + // TODO: Eliminate the heap allocation here + // NV2080_CTRL_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE_PARAMS has massive size + // because it has an embedded struct VGPU_TYPE instead of a pointer. + // FINN won't be able to figure out serialization for a pointer at this moment. + pAddVgpuTypeParams = portMemAllocNonPaged(sizeof(*pAddVgpuTypeParams)); + if (pAddVgpuTypeParams == NULL) + { + NV_PRINTF(LEVEL_ERROR, "Failed to alloc add vGPU type ctrl params.\n"); + return NV_ERR_NO_MEMORY; + } + portMemSet(pAddVgpuTypeParams, 0, sizeof(*pAddVgpuTypeParams)); + + pAddVgpuTypeParams->discardVgpuTypes = discardVgpuTypes; + pAddVgpuTypeParams->vgpuInfoCount = 1; + pAddVgpuTypeParams->vgpuInfo[0] = *pVgpuInfo; + + rmStatus = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_PGPU_ADD_VGPU_TYPE, + pAddVgpuTypeParams, sizeof(*pAddVgpuTypeParams)); + + portMemFree(pAddVgpuTypeParams); + + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create vGPU type on GSP.\n"); + return rmStatus; + } + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &index) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pPgpuInfo = &(pKernelVgpuMgr->pgpuInfo[index]); + + if (pPgpuInfo->numVgpuTypes == NVA081_MAX_VGPU_TYPES_PER_PGPU && !discardVgpuTypes) + { + return NV_ERR_NOT_SUPPORTED; + } + + // TODO: This is a WAR. Need to do this change in VGPUD. + if (pPgpuInfo->fractionalMultiVgpu == 0 && pVgpuInfo->maxInstance != 1) + { + pVgpuInfo->multiVgpuSupported = 0; + } + + rmStatus = kvgpumgrGetVgpuTypeInfo(pVgpuInfo->vgpuType, &pVgpuTypeInfo); + if (rmStatus == NV_ERR_OBJECT_NOT_FOUND) + { + rmStatus = _kvgpumgrCreateVgpuType(pVgpuInfo, &pVgpuTypeInfo); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to create vGPU type.\n"); + return rmStatus; + } + } + else if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to get vGPU type.\n"); + return rmStatus; + } + + if (discardVgpuTypes) + { + pPgpuInfo->numVgpuTypes = 0; + } + + if (pPgpuInfo->numVgpuTypes == 0) + { + pPgpuInfo->sriovEnabled = gpuIsSriovEnabled(pGpu); + } + + pPgpuInfo->vgpuTypes[pPgpuInfo->numVgpuTypes] = pVgpuTypeInfo; + pPgpuInfo->numVgpuTypes++; + + return NV_OK; } NV_STATUS kvgpumgrAttachGpu(NvU32 gpuPciId) { + NvU32 index; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + + NV_PRINTF(LEVEL_INFO, "Enter function\n"); + + NV_ASSERT_OR_RETURN((pKernelVgpuMgr != NULL), NV_ERR_NOT_SUPPORTED); + + index = 0; + while ((index < pKernelVgpuMgr->pgpuCount) && + ((pKernelVgpuMgr->pgpuInfo[index].isAttached == NV_TRUE) || + (pKernelVgpuMgr->pgpuInfo[index].gpuPciId != gpuPciId))) + { + index++; + } + NV_ASSERT_OR_RETURN((index != NV_MAX_DEVICES), NV_ERR_INSUFFICIENT_RESOURCES); + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[index]); + + /* Probe call, RmInit is not done yet, so send pGpu as NULL */ + _kvgpumgrSetVgpuType(NULL, pPhysGpuInfo, NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE); + pPhysGpuInfo->numActiveVgpu = 0; + pPhysGpuInfo->isAttached = NV_TRUE; + pPhysGpuInfo->numCreatedVgpu = 0; + + listInit(&(pKernelVgpuMgr->pgpuInfo[index].listVgpuConfigEventsHead), portMemAllocatorGetGlobalNonPaged()); + listInit(&(pKernelVgpuMgr->pgpuInfo[index].listHostVgpuDeviceHead), portMemAllocatorGetGlobalNonPaged()); + + if (index == pKernelVgpuMgr->pgpuCount) + { + pPhysGpuInfo->gpuPciId = gpuPciId; + pPhysGpuInfo->numVgpuTypes = 0; + pPhysGpuInfo->vgpuConfigState = NVA081_CTRL_VGPU_CONFIG_STATE_UNINITIALIZED; + pKernelVgpuMgr->pgpuCount++; + } + return NV_OK; } NV_STATUS kvgpumgrDetachGpu(NvU32 gpuPciId) { + NvU32 i; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + + NV_PRINTF(LEVEL_INFO, "Enter function\n"); + + NV_ASSERT_OR_RETURN((pKernelVgpuMgr != NULL), NV_ERR_NOT_SUPPORTED); + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, gpuPciId, &i) != NV_OK) + return NV_ERR_OBJECT_NOT_FOUND; + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + + pPhysGpuInfo->createdVfMask = 0; + pPhysGpuInfo->assignedSwizzIdMask = 0; + pPhysGpuInfo->isAttached = NV_FALSE; + + listDestroy(&(pPhysGpuInfo->listHostVgpuDeviceHead)); + return NV_OK; } @@ -121,9 +654,185 @@ NV_STATUS kvgpumgrRegisterGuestId(SET_GUEST_ID_PARAMS *pParams, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice, OBJGPU *pGpu) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS rmStatus = NV_OK; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + + if (pParams->action == SET_GUEST_ID_ACTION_SET) + { + KERNEL_VGPU_GUEST *pVgpuGuest = NULL; + + for (pVgpuGuest = listHead(&(pKernelVgpuMgr->listVgpuGuestHead)); + pVgpuGuest != NULL; + pVgpuGuest = listNext(&(pKernelVgpuMgr->listVgpuGuestHead), pVgpuGuest)) + { + if (pParams->vmIdType == pVgpuGuest->guestVmInfo.vmIdType) + { + if (pParams->vmIdType == VM_ID_DOMAIN_ID) + { + if (pParams->guestVmId.vmId == pVgpuGuest->guestVmInfo.guestVmId.vmId) + { + break; + } + } + else if (pParams->vmIdType == VM_ID_UUID) + { + if (!portMemCmp(pParams->guestVmId.vmUuid, + pVgpuGuest->guestVmInfo.guestVmId.vmUuid, + VM_UUID_SIZE)) + { + break; + } + } + else + return NV_ERR_INVALID_ARGUMENT; + } + } + + if (pVgpuGuest == NULL) + { + pVgpuGuest = listAppendNew(&(pKernelVgpuMgr->listVgpuGuestHead)); + if (pVgpuGuest == NULL) + return NV_ERR_NO_MEMORY; + + portMemSet(pVgpuGuest, 0, sizeof(KERNEL_VGPU_GUEST)); + } + + NV_ASSERT_OR_RETURN(pVgpuGuest->numVgpuDevices != MAX_VGPU_DEVICES_PER_VM, + NV_ERR_INSUFFICIENT_RESOURCES); + + pVgpuGuest->numVgpuDevices++; + + pKernelHostVgpuDevice->vgpuGuest = pVgpuGuest; + + pVgpuGuest->guestVmInfo.vmIdType = pParams->vmIdType; + + if (pParams->vmIdType == VM_ID_DOMAIN_ID) + { + pVgpuGuest->guestVmInfo.guestVmId.vmId = pParams->guestVmId.vmId; + } + else if (pParams->vmIdType == VM_ID_UUID) + { + portMemCopy(pVgpuGuest->guestVmInfo.guestVmId.vmUuid, + VM_UUID_SIZE, + pParams->guestVmId.vmUuid, + VM_UUID_SIZE); + } + } + else if (pParams->action == SET_GUEST_ID_ACTION_UNSET) + { + KERNEL_VGPU_GUEST *pVgpuGuest = pKernelHostVgpuDevice->vgpuGuest; + + if (pVgpuGuest) + { + pVgpuGuest->numVgpuDevices--; + if (pVgpuGuest->numVgpuDevices == 0) + { + listRemove(&(pKernelVgpuMgr->listVgpuGuestHead), pVgpuGuest); + } + pKernelHostVgpuDevice->vgpuGuest = NULL; + } + else + { + return NV_WARN_NULL_OBJECT; + } + } + else + { + return NV_ERR_INVALID_ARGUMENT; + } + + return rmStatus; +} + +static NV_STATUS +_kvgpumgrVgpuAllocGPUInstanceSubscription +( + OBJGPU *pGpu, + NvU32 *phClient, + NvU32 *phDevice, + NvU32 swizzId +) +{ + NV_STATUS rmStatus; + NVC637_ALLOCATION_PARAMETERS nvC637AllocParams; + NvU32 hSubDevice; + NvU32 hGPUInstanceSubscription; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + NV_ASSERT_OR_RETURN(phClient != NULL, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN(phDevice != NULL, NV_ERR_INVALID_ARGUMENT); + + NV_ASSERT_OK_OR_RETURN( + rmapiutilAllocClientAndDeviceHandles(pRmApi, pGpu, phClient, phDevice, &hSubDevice)); + + // Allocate GPUInstanceSubscription handle + NV_ASSERT_OK_OR_GOTO( + rmStatus, + serverutilGenResourceHandle(*phClient, &hGPUInstanceSubscription), + cleanup); + portMemSet(&nvC637AllocParams, 0, sizeof(nvC637AllocParams)); + nvC637AllocParams.swizzId = swizzId; + + // Allocate GPUInstanceSubscription object + NV_CHECK_OK_OR_GOTO( + rmStatus, + LEVEL_ERROR, + pRmApi->AllocWithHandle(pRmApi, + *phClient, + hSubDevice, + hGPUInstanceSubscription, + AMPERE_SMC_PARTITION_REF, + &nvC637AllocParams, + sizeof(nvC637AllocParams)), + cleanup); + + return rmStatus; + +cleanup: + pRmApi->Free(pRmApi, *phClient, *phClient); + return rmStatus; +} + +NV_STATUS +kvgpumgrHeterogeneousGetChidOffset(NvU32 vgpuTypeId, NvU16 placementId, + NvU32 numChannels, NvU64 *pChidOffset) +{ + VGPU_TYPE *pVgpuTypeInfo = NULL; + NV_STATUS status; + NvU32 i; + + if ((status = kvgpumgrGetVgpuTypeInfo(vgpuTypeId, &pVgpuTypeInfo)) != NV_OK) + return status; + + if ((placementId == NVA081_PLACEMENT_ID_INVALID)) + return NV_ERR_INVALID_ARGUMENT; + + /* Channel count provided by plugin and calculated by RM should be same */ + if (numChannels != pVgpuTypeInfo->channelCount) + return NV_ERR_INVALID_STATE; + + if (pVgpuTypeInfo->placementCount > MAX_VGPU_DEVICES_PER_PGPU) + return NV_ERR_INVALID_INDEX; + + for (i = 0; i < pVgpuTypeInfo->placementCount; i++) + { + /* + * For the placementId of the vGPU instance, find the corresponding + * channel offset. supportedPlacementIds and supportedChidOffsets + * share the same array index for a give placement ID. + */ + if (placementId == pVgpuTypeInfo->supportedPlacementIds[i]) + { + *pChidOffset = pVgpuTypeInfo->supportedChidOffsets[i]; + return NV_OK; + } + } + + return NV_ERR_OBJECT_NOT_FOUND; } + NV_STATUS kvgpumgrGuestRegister(OBJGPU *pGpu, NvU32 gfid, @@ -137,15 +846,467 @@ kvgpumgrGuestRegister(OBJGPU *pGpu, NvU32 swizzId, NvU32 vgpuDeviceInstanceId, NvBool bDisableDefaultSmcExecPartRestore, + NvU16 placementId, KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS rmStatus = NV_OK; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + SET_GUEST_ID_PARAMS setGuestIDParams = {0}; + NvU32 i; + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = NULL; + NvBool bMIGInUse = IS_MIG_IN_USE(pGpu); + + NvU32 j; + NvU32 vgpuTypeId = 0; + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + + NV_PRINTF(LEVEL_INFO, "Enter function\n"); + + if (numPluginChannels > VGPU_MAX_PLUGIN_CHANNELS) + { + NV_PRINTF(LEVEL_ERROR, "failed, wrong number of plugin channels\n"); + return NV_ERR_INVALID_PARAMETER; + } + + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VSGA)) + { + NV_PRINTF(LEVEL_ERROR, "GPU is previously set in vSGA mode!\n"); + return NV_ERR_INVALID_DEVICE; + } + + if (gpuIsSriovEnabled(pGpu)) + { + GFID_ALLOC_STATUS gfidState; + NV_ASSERT_OK_OR_RETURN(gpuGetGfidState(pGpu, gfid, &gfidState)); + NV_ASSERT_OR_RETURN((gfidState == GFID_FREE), NV_ERR_INSUFFICIENT_RESOURCES); + } + else + { + // MIG is supported only with SRIOV. Legacy mode doesn't support MIG + NV_ASSERT_OR_RETURN(!bMIGInUse, NV_ERR_INVALID_STATE); + numPluginChannels = 0; + } + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i) != NV_OK) + return NV_ERR_OBJECT_NOT_FOUND; + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + + // check if this vgpu type is allowed on physical gpu + for (j = 0; j < pPhysGpuInfo->numVgpuTypes; j++) + { + if (vgpuType == pPhysGpuInfo->vgpuTypes[j]->vgpuTypeId) + { + vgpuTypeId = j; + break; + } + } + + if (j == pPhysGpuInfo->numVgpuTypes) + { + return NV_ERR_NOT_SUPPORTED; + } + + // On KVM, store a link to the corresponding REQUEST_VGPU_INFO_NODE in + // KERNEL_HOST_VGPU_DEVICE and vice versa, so as to create a mapping between + // vGPU device and the corresponding mdev device. + if (osIsVgpuVfioPresent() == NV_OK) + { + for (pRequestVgpu = listHead(&pKernelVgpuMgr->listRequestVgpuHead); + pRequestVgpu != NULL; + pRequestVgpu = listNext(&pKernelVgpuMgr->listRequestVgpuHead, pRequestVgpu)) + { + if (pRequestVgpu->deviceState == NV_VGPU_DEV_OPENED) + break; + } + if (pRequestVgpu == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + } + + /* + * For MIG mode, vGPU type is already validated based on swizzid in + * NVA081_CTRL_CMD_VGPU_CONFIG_[GET_FREE|VALIDATE]_SWIZZID RmCtrl. + * For heterogeneous vGPU mode, vGPU type is already validated based on placement ID + * in NVA081_CTRL_CMD_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO RmCtrl. + * Both the RmCtrls are done before allocating the A084 object. + */ + if (!IS_MIG_ENABLED(pGpu) && !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE)) + { + rmStatus = _kvgpumgrCheckVgpuTypeActivatable(pGpu, pPhysGpuInfo, pPhysGpuInfo->vgpuTypes[vgpuTypeId]); + if (rmStatus != NV_OK) + return rmStatus; + + rmStatus = _kvgpumgrSetVgpuType(pGpu, pPhysGpuInfo, vgpuType); + if (rmStatus != NV_OK) + return rmStatus; + } + + if (listCount(&(pPhysGpuInfo->listHostVgpuDeviceHead)) == MAX_VGPU_DEVICES_PER_PGPU) + { + rmStatus = NV_ERR_INSUFFICIENT_RESOURCES; + goto failed; + } + + // Register guest vgpu device instance + pKernelHostVgpuDevice = listAppendNew(&(pPhysGpuInfo->listHostVgpuDeviceHead)); + if (pKernelHostVgpuDevice == NULL) + { + rmStatus = NV_ERR_NO_MEMORY; + goto failed; + } + + portMemSet(pKernelHostVgpuDevice, 0, sizeof(KERNEL_HOST_VGPU_DEVICE)); + + pKernelHostVgpuDevice->vgpuType = vgpuType; + + setGuestIDParams.action = SET_GUEST_ID_ACTION_SET; + setGuestIDParams.vmPid = vmPid; + setGuestIDParams.vmIdType = vmIdType; + if (vmIdType == VM_ID_DOMAIN_ID) + { + setGuestIDParams.guestVmId.vmId = guestVmId.vmId; + } + else if (vmIdType == VM_ID_UUID) + { + portMemCopy(setGuestIDParams.guestVmId.vmUuid, + VM_UUID_SIZE, + guestVmId.vmUuid, + VM_UUID_SIZE); + } + if (NV_OK != (rmStatus = kvgpumgrRegisterGuestId(&setGuestIDParams, pKernelHostVgpuDevice, pGpu))) + { + goto failed; + } + + pKernelHostVgpuDevice->gfid = gfid; + pKernelHostVgpuDevice->swizzId = swizzId; + pKernelHostVgpuDevice->numPluginChannels = numPluginChannels; + pKernelHostVgpuDevice->bDisableDefaultSmcExecPartRestore = bDisableDefaultSmcExecPartRestore; + pKernelHostVgpuDevice->placementId = placementId; + + if (osIsVgpuVfioPresent() == NV_OK) + { + pKernelHostVgpuDevice->pRequestVgpuInfoNode = pRequestVgpu; + pRequestVgpu->pKernelHostVgpuDevice = pKernelHostVgpuDevice; + } + + pKernelHostVgpuDevice->hPluginFBAllocationClient = hPluginFBAllocationClient; + pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.bValid = NV_FALSE; + pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.offset = 0; + pKernelHostVgpuDevice->vgpuDeviceGuestFbInfo.length = 0; + pKernelHostVgpuDevice->bOfflinedPageInfoValid = NV_FALSE; + + pPhysGpuInfo->numActiveVgpu++; + + if (gpuIsSriovEnabled(pGpu)) + { + // Set GFID in use + gpuSetGfidUsage(pGpu, gfid, NV_TRUE); + } + + // If MIG is enabled, then we need to set faultIds and per GPU instance VEID + // offset in MMU_CFG registers. In MIG with memory partitioning, every + // VM should be associated with a GPU instance, so set these params for + // GPU instance engines + // + if (gpuIsSriovEnabled(pGpu) && bMIGInUse) + { + // + // Alloc GPUInstanceSubscription object inside hostVgpuDeviceObject. This is + // needed because hostVgpuDevice can be duped under any client and + // will get freed after subdevice, so during hostVgpuDeviceDestruct + // to get GPU instance reference, we need to keep the GPU instance alive + // + NV_ASSERT_OK_OR_GOTO(rmStatus, _kvgpumgrVgpuAllocGPUInstanceSubscription(pGpu, + &pKernelHostVgpuDevice->hMigClient, + &pKernelHostVgpuDevice->hMigDevice, + swizzId), + failed); + } + + if (IS_GSP_CLIENT(pGpu)) + { + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + ENGINE_INFO tmpEngineInfo; + VGPU_TYPE *vgpuTypeInfo = NULL; + Device *pMigDevice = NULL; + + if (gpuIsSriovEnabled(pGpu) && bMIGInUse) + { + RsClient *pClient; + + NV_ASSERT_OK_OR_GOTO(rmStatus, + serverGetClientUnderLock(&g_resServ, pKernelHostVgpuDevice->hMigClient, &pClient), + failed); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + deviceGetByHandle(pClient, pKernelHostVgpuDevice->hMigDevice, &pMigDevice), + failed); + } + + NV_ASSERT_OK_OR_GOTO(rmStatus, + kvgpumgrGetVgpuTypeInfo(vgpuType, &vgpuTypeInfo), + failed); + + portMemSet(&tmpEngineInfo, 0, sizeof(ENGINE_INFO)); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, &tmpEngineInfo, pMigDevice), + failed); + + rmStatus = vgpuMgrReserveSystemChannelIDs(pGpu, + vgpuTypeInfo, + pKernelHostVgpuDevice->gfid, + pKernelHostVgpuDevice->chidOffset, + pKernelHostVgpuDevice->channelCount, + pMigDevice, + numChannels, + pKernelHostVgpuDevice->placementId, + tmpEngineInfo.engineInfoListSize, + tmpEngineInfo.engineInfoList); + + portMemFree(tmpEngineInfo.engineInfoList); + tmpEngineInfo.engineInfoList = NULL; + + if (rmStatus != NV_OK) + { + goto failed; + } + } + + // Save/Restore default compute instance if not disabled during allocation + if (gpuIsSriovEnabled(pGpu) && bMIGInUse && !pKernelHostVgpuDevice->bDisableDefaultSmcExecPartRestore) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + + // Get GPU instance + NV_ASSERT_OK_OR_GOTO(rmStatus, + kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, + swizzId, &pKernelMIGGpuInstance), + failed); + // + // Save any default compute instances as we may need to restore + // them during destruct + // + NV_ASSERT_OK_OR_GOTO(rmStatus, + kmigmgrSaveComputeInstances(pGpu, pKernelMIGManager, pKernelMIGGpuInstance, + pKernelHostVgpuDevice->savedExecPartitions), + failed); + + // Determine if we have a VEID fragmentation between compute instances + if (!kmigmgrIsPartitionVeidAllocationContiguous(pGpu, pKernelMIGManager, pKernelMIGGpuInstance)) + { + // delete all compute instances and recreate then again + NV_ASSERT_OK_OR_GOTO(rmStatus, + kvgpuMgrRestoreSmcExecPart(pGpu, + pKernelHostVgpuDevice, + pKernelMIGGpuInstance), + failed); + } + } + + *ppKernelHostVgpuDevice = pKernelHostVgpuDevice; + + return rmStatus; + +failed: + // Unset gfid usage + if (gpuIsSriovEnabled(pGpu)) + gpuSetGfidUsage(pGpu, gfid, NV_FALSE); + + if (pKernelHostVgpuDevice != NULL) + { + if (pKernelHostVgpuDevice->vgpuGuest != NULL) + { + setGuestIDParams.action = SET_GUEST_ID_ACTION_UNSET; + kvgpumgrRegisterGuestId(&setGuestIDParams, pKernelHostVgpuDevice, pGpu); + } + listRemove(&(pPhysGpuInfo->listHostVgpuDeviceHead), pKernelHostVgpuDevice); + } + + if (osIsVgpuVfioPresent() != NV_OK && // not KVM + swizzId != KMIGMGR_SWIZZID_INVALID) + _kvgpumgrClearAssignedSwizzIdMask(pGpu, swizzId); + + return rmStatus; } NV_STATUS kvgpumgrGuestUnregister(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS rmStatus = NV_OK; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 gfid = pKernelHostVgpuDevice->gfid; + SET_GUEST_ID_PARAMS setGuestIDParams = {0}; + NvU32 i; + + NV_PRINTF(LEVEL_INFO, "Enter function\n"); + + if (gpuIsSriovEnabled(pGpu)) + { + GFID_ALLOC_STATUS gfidState; + + // Sanity check on GFID + NV_ASSERT_OK_OR_GOTO(rmStatus, gpuGetGfidState(pGpu, gfid, &gfidState), done); + + // Keep continuing in unregister path after sanity check + if (gfidState == GFID_FREE) + { + NV_PRINTF(LEVEL_ERROR, "Request to unregister Invalid GFID\n"); + rmStatus = NV_ERR_INVALID_STATE; + goto done; + } + } + + if (IS_MIG_IN_USE(pGpu) && !pKernelHostVgpuDevice->bDisableDefaultSmcExecPartRestore) + { + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + + NV_ASSERT_OK_OR_GOTO(rmStatus, kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, + pKernelHostVgpuDevice->swizzId, + &pKernelMIGGpuInstance), + done); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + kvgpuMgrRestoreSmcExecPart(pGpu, + pKernelHostVgpuDevice, + pKernelMIGGpuInstance), + done); + + portMemSet(&pKernelHostVgpuDevice->savedExecPartitions, 0, + sizeof(pKernelHostVgpuDevice->savedExecPartitions)); + } + + if (!gpuIsSriovEnabled(pGpu)) + { + portMemFree(pKernelHostVgpuDevice->pGuestFbSegment); + pKernelHostVgpuDevice->pGuestFbSegment = NULL; + } + + if (pKernelHostVgpuDevice->hbmRegionList != NULL) + { + portMemFree(pKernelHostVgpuDevice->hbmRegionList); + pKernelHostVgpuDevice->hbmRegionList = NULL; + pKernelHostVgpuDevice->numValidHbmRegions = 0; + } + + if (gpuIsSriovEnabled(pGpu)) + { + if (IS_GSP_CLIENT(pGpu)) + { + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + ENGINE_INFO tmpEngineInfo; + Device *pMigDevice = NULL; + + portMemSet(&tmpEngineInfo, 0, sizeof(ENGINE_INFO)); + + if (IS_MIG_IN_USE(pGpu)) + { + RsClient *pClient; + + NV_ASSERT_OK_OR_GOTO(rmStatus, + serverGetClientUnderLock(&g_resServ, pKernelHostVgpuDevice->hMigClient, &pClient), + free_fifo_chids_exit); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + deviceGetByHandle(pClient, pKernelHostVgpuDevice->hMigDevice, &pMigDevice), + free_fifo_chids_exit); + } + + NV_ASSERT_OK_OR_GOTO(rmStatus, + kfifoGetHostDeviceInfoTable_HAL(pGpu, pKernelFifo, &tmpEngineInfo, pMigDevice), + free_fifo_chids_exit); + + vgpuMgrFreeSystemChannelIDs(pGpu, + pKernelHostVgpuDevice->gfid, + pKernelHostVgpuDevice->chidOffset, + pKernelHostVgpuDevice->channelCount, + pMigDevice, + tmpEngineInfo.engineInfoListSize, + tmpEngineInfo.engineInfoList); + +free_fifo_chids_exit: + portMemFree(tmpEngineInfo.engineInfoList); + tmpEngineInfo.engineInfoList = NULL; + } + + // Unset GFID usage + gpuSetGfidUsage(pGpu, gfid, NV_FALSE); + } + +done: + if (IS_MIG_IN_USE(pGpu)) + { + pRmApi->Free(pRmApi, pKernelHostVgpuDevice->hMigClient, pKernelHostVgpuDevice->hMigClient); + pKernelHostVgpuDevice->hMigClient = NV01_NULL_OBJECT; + pKernelHostVgpuDevice->hMigDevice = NV01_NULL_OBJECT; + } + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + // Unset the guest id for host vGPU device + setGuestIDParams.action = SET_GUEST_ID_ACTION_UNSET; + if (NV_OK != (rmStatus = kvgpumgrRegisterGuestId(&setGuestIDParams, + pKernelHostVgpuDevice, + pGpu))) + { + // In case of Hyper-V, On VM reboot KERNEL_HOST_VGPU_DEVICE is not destroyed. + // As guest id is unset during VM reboot by plugin explicitly. So we + // will receive NV_WARN_NULL_OBJECT here and we need to ignore it. + // + // In case, plugin doesn't get a chance to unset the guest id e.g. in case + // of crash or Force shutdown/Turn off then we need to get it unset here. + if (hypervisorIsType(OS_HYPERVISOR_HYPERV) && rmStatus == NV_WARN_NULL_OBJECT) + { + rmStatus = NV_OK; + } + else + { + return rmStatus; + } + } + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + + NV_ASSERT_OR_RETURN((pPhysGpuInfo != NULL), NV_ERR_INVALID_ARGUMENT); + + pPhysGpuInfo->numActiveVgpu--; + + if (pPhysGpuInfo->numActiveVgpu == 0 && pPhysGpuInfo->numCreatedVgpu == 0) + { + _kvgpumgrSetVgpuType(pGpu, pPhysGpuInfo, NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE); + } + + if (pKernelHostVgpuDevice->pRequestVgpuInfoNode != NULL) + { + pKernelHostVgpuDevice->pRequestVgpuInfoNode->pKernelHostVgpuDevice = NULL; + } + + if (osIsVgpuVfioPresent() != NV_OK) // Not KVM + { + if (pKernelHostVgpuDevice->swizzId != KMIGMGR_SWIZZID_INVALID) + rmStatus = _kvgpumgrClearAssignedSwizzIdMask(pGpu, pKernelHostVgpuDevice->swizzId); + } + + if (pKernelHostVgpuDevice->placementId != NVA081_PLACEMENT_ID_INVALID) + _kvgpumgrUpdateCreatablePlacementIds(pGpu, pKernelHostVgpuDevice->placementId, + pKernelHostVgpuDevice->vgpuType, NV_FALSE); + + listRemove(&(pPhysGpuInfo->listHostVgpuDeviceHead), pKernelHostVgpuDevice); + + return rmStatus; } // @@ -154,25 +1315,170 @@ kvgpumgrGuestUnregister(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDe NvBool kvgpumgrCheckPgpuMigrationSupport(OBJGPU *pGpu) { - return NV_FALSE; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT_PARAMS params = {0}; + NV_STATUS status; + + NV_CHECK_OK_OR_ELSE(status, + LEVEL_ERROR, + pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_MIGRATION_SUPPORT, + ¶ms, sizeof(params)), + return NV_FALSE); + + return params.bIsMigrationSupported; +} + +// +// Function to convert a NvU32 value to a ascii-encoded string. +// The value will be padded with 0 to use up the totalWidth. The value +// requiring space more that totalWidth will be truncated. +// +static NvU32 +NvU32ToAsciiStr(NvU32 uval, NvU32 totalWidth, NvU8 *dest, NvBool invalid) +{ + NvU32 digitCount = 0; + NvU8 nibble; + + if (totalWidth == 0) + return (totalWidth); + + // Move the pointer to the end + dest += (totalWidth - 1); + + // Start copying the data from the end in the reverse order + while (digitCount < totalWidth) + { + digitCount++; + if (invalid == NV_TRUE) + { + *dest-- = 'X'; + continue; + } + + nibble = uval & 0xF; + *dest-- = (nibble <= 9) ? (nibble + '0') : (nibble - 10 + 'A'); + uval = uval >> 4; + } + + return (totalWidth); } NvU32 kvgpumgrGetPgpuDevIdEncoding(OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize) { - return NV_U32_MAX; + NvU32 chipID = DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID); + NvU32 subID = DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCISubDeviceID); + + _get_chip_id_for_alias_pgpu(&chipID, &subID); + + if ((strSize < MAX_NVU32_TO_CONVERTED_STR_LEN) + || (pgpuString == NULL)) + { + return NV_U32_MAX; + } + + // The encoding of the Dev ID is the value converted to string + return (NvU32ToAsciiStr(chipID, DEVID_ENCODED_VALUE_SIZE, pgpuString, NV_FALSE)); } NvU32 kvgpumgrGetPgpuSubdevIdEncoding(OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize) { - return NV_U32_MAX; + NvU32 chipID = DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCIDeviceID); + NvU32 subID = DRF_VAL(_PCI, _DEVID, _DEVICE, pGpu->idInfo.PCISubDeviceID); + NvU32 bytes = 0; + + _get_chip_id_for_alias_pgpu(&chipID, &subID); + + if ((strSize < MAX_NVU32_TO_CONVERTED_STR_LEN) + || (pgpuString == NULL)) + { + return NV_U32_MAX; + } + + switch (chipID) + { + default: + // The encoding of the subdevice ID is its value converted to string + bytes = NvU32ToAsciiStr(subID, SUBDEVID_ENCODED_VALUE_SIZE, + pgpuString, NV_FALSE); + break; + } + + return bytes; } NvU32 kvgpumgrGetPgpuFSEncoding(OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize) { - return NV_U32_MAX; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV2080_CTRL_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING_PARAMS params = {0}; + NV_STATUS status; + + params.pgpuStringSize = strSize; + + NV_CHECK_OK_OR_ELSE(status, + LEVEL_ERROR, + pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_PGPU_FS_ENCODING, + ¶ms, sizeof(params)), + return NV_U32_MAX); + + portMemCopy(pgpuString, strSize, params.pgpuString, params.pgpuStringSize); + + return params.pgpuStringSize; +} + +NvU64 +kvgpumgrGetEccAndPrReservedFb(OBJGPU *pGpu) +{ + Heap *pHeap = GPU_GET_HEAP(pGpu); + const MEMORY_SYSTEM_STATIC_CONFIG *pMemorySystemConfig = + kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu)); + NvU64 eccReservedFb = 0, pageRetirementReservedFb = 0, usableSizeFb; + + // + // pageRetirementReservedFb is needed only in case of legacy, to account + // for the pagepool used during page stitching + // + if (!gpuIsSriovEnabled(pGpu)) + { + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_ALLOW_PAGE_RETIREMENT)) + { + if (IsPASCALorBetter(pGpu)) + { + pageRetirementReservedFb = NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES * RM_PAGE_SIZE_HUGE; + } + else + { + pageRetirementReservedFb = NV2080_CTRL_FB_OFFLINED_PAGES_MAX_PAGES * RM_PAGE_SIZE_64K; + } + } + } + + if (pMemorySystemConfig->bEnabledEccFBPA) + { + if ((pMemorySystemConfig->ramType != NV2080_CTRL_FB_INFO_RAM_TYPE_HBM1) && + (pMemorySystemConfig->ramType != NV2080_CTRL_FB_INFO_RAM_TYPE_HBM2) && + (pMemorySystemConfig->ramType != NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3)) + { + heapGetUsableSize(pHeap, &usableSizeFb); + // + // FB and ECC checksum calculation + // eccReservedFb = totalFBEccOff / 16 + // i.e. totalFbEccOff = eccReservedFb * 16 + // + // totalFbEccOff = totalFbEccOn + eccReservedFb + // eccReservedFb * 16 = totalFbEccOn + eccReservedFb + // eccReservedFb * 15 = totalFbEccOn + // eccReservedFb = totalFbEccOn / 15 (totalFbEccOn is same as usableSizeFb) + // + eccReservedFb = usableSizeFb / 15; + } + } + + return pageRetirementReservedFb + eccReservedFb; } // @@ -182,7 +1488,47 @@ NvU32 kvgpumgrGetPgpuFSEncoding(OBJGPU *pGpu, NvU8 *pgpuString, // NvU32 kvgpumgrGetPgpuCapEncoding(OBJGPU *pGpu, NvU8 *pgpuString, NvU32 strSize) { - return NV_U32_MAX; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NvU32 pgpuCap = 0; + + if ((strSize < MAX_NVU32_TO_CONVERTED_STR_LEN) || (pgpuString == NULL)) + { + return NV_U32_MAX; + } + + { + NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS eccStatus = {0}; + + if (pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS, + &eccStatus, sizeof(eccStatus)) == NV_OK) + { + NvU32 i; + for (i = 0; i < NV2080_CTRL_GPU_ECC_UNIT_COUNT; i++) + { + if (eccStatus.units[i].enabled) + { + pgpuCap |= PGPU_CAP_ECC_ON; + break; + } + } + } + } + + { + NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS sriovCaps = {0}; + + if (gpuGetSriovCaps_HAL(pGpu, &sriovCaps) == NV_OK) + { + if (sriovCaps.bSriovEnabled) + pgpuCap |= PGPU_CAP_SRIOV_ON; + } + } + + return NvU32ToAsciiStr(pgpuCap, PGPU_CAP_ENCODED_VALUE_SIZE, + pgpuString, NV_FALSE); } /* @@ -192,7 +1538,14 @@ NV_STATUS kvgpumgrGetHostVgpuVersion(NvU32 *user_min_supported_version, NvU32 *user_max_supported_version) { - return NV_ERR_NOT_SUPPORTED; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + + *user_min_supported_version + = pKernelVgpuMgr->user_min_supported_version; + *user_max_supported_version + = pKernelVgpuMgr->user_max_supported_version; + return NV_OK; } /* @@ -202,8 +1555,131 @@ NV_STATUS kvgpumgrSetHostVgpuVersion(NvU32 user_min_supported_version, NvU32 user_max_supported_version) { - return NV_ERR_NOT_SUPPORTED; -} + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvU32 host_min_supported_version + = GRIDSW_VERSION_EXTERNAL(NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR, + NV_VGPU_MIN_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR); + NvU32 host_max_supported_version + = GRIDSW_VERSION_EXTERNAL(NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MAJOR, + NV_VGPU_MAX_SUPPORTED_GRIDSW_VERSION_EXTERNAL_MINOR); + + /* Sanity check */ + if (user_min_supported_version > user_max_supported_version) { + NV_PRINTF(LEVEL_ERROR, + "Maximum vGPU version (0x%x) being set is less than minimum version (0x%x)\n", + user_max_supported_version, user_min_supported_version); + return NV_ERR_INVALID_ARGUMENT; + } + + /* Sanity check: Fail in case the range being set by admin is a subset + * of the range supported by the host driver + */ + if ((user_min_supported_version < host_min_supported_version) + || (user_max_supported_version > host_max_supported_version)) { + + NV_PRINTF(LEVEL_ERROR, + "vGPU version range being set (0x%x, 0x%x) is outside the range supported by host (0x%x, 0x%x)\n", + user_min_supported_version, user_max_supported_version, + host_min_supported_version, host_max_supported_version); + + return NV_ERR_INVALID_ARGUMENT; + } + + NV_PRINTF(LEVEL_INFO, + "vGPU version range enforced by user: (0x%x, 0x%x)\n", + user_min_supported_version, user_max_supported_version); + + /* Save the information of the user specified range in the host */ + pKernelVgpuMgr->user_min_supported_version + = user_min_supported_version; + pKernelVgpuMgr->user_max_supported_version + = user_max_supported_version; + + return NV_OK; +} + +/* + * Function to set swizzId is assigned to a vGPU device. + */ +static NV_STATUS +_kvgpumgrSetAssignedSwizzIdMask(OBJGPU *pGpu, + NvU32 swizzId) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 i; + NvU64 mask; + + if (swizzId >= KMIGMGR_MAX_GPU_SWIZZID) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + NV_ASSERT_OR_RETURN((pPhysGpuInfo != NULL), NV_ERR_INVALID_ARGUMENT); + + /* Validate that same ID is not already set and then set the ID */ + mask = NVBIT64(swizzId); + + if (mask & pPhysGpuInfo->assignedSwizzIdMask) + { + NV_PRINTF(LEVEL_ERROR, "SwizzID - %d already in use\n", swizzId); + DBG_BREAKPOINT(); + return NV_ERR_STATE_IN_USE; + } + + pPhysGpuInfo->assignedSwizzIdMask |= mask; + + return NV_OK; +} + +/*! + * Function to mark swizzId is free to be used by other vGPU devices. + */ +static NV_STATUS +_kvgpumgrClearAssignedSwizzIdMask(OBJGPU *pGpu, + NvU32 swizzId) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 i; + NvU64 mask; + + if (swizzId >= KMIGMGR_MAX_GPU_SWIZZID) + { + return NV_ERR_INVALID_ARGUMENT; + } + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + NV_ASSERT_OR_RETURN((pPhysGpuInfo != NULL), NV_ERR_INVALID_ARGUMENT); + + /* Validate that same ID is not already marked as free and then set the ID */ + mask = NVBIT64(swizzId); + + if (!(mask & pPhysGpuInfo->assignedSwizzIdMask)) + { + NV_PRINTF(LEVEL_ERROR, "SwizzID - %d not in use\n", swizzId); + DBG_BREAKPOINT(); + return NV_ERR_INVALID_STATE; + } + + pPhysGpuInfo->assignedSwizzIdMask &= ~mask; + + return NV_OK; +} NV_STATUS kvgpumgrGetSwizzId(OBJGPU *pGpu, @@ -211,7 +1687,50 @@ kvgpumgrGetSwizzId(OBJGPU *pGpu, NvU32 partitionFlag, NvU32 *swizzId) { - return NV_ERR_NOT_SUPPORTED; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvU64 swizzIdInUseMask = 0; + NvU32 id; + NV_STATUS rmStatus = NV_OK; + + swizzIdInUseMask = kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager); + + *swizzId = KMIGMGR_SWIZZID_INVALID; + + // Determine valid swizzids not assigned to any vGPU device. + FOR_EACH_INDEX_IN_MASK(64, id, swizzIdInUseMask) + { + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + NvU64 mask = 0; + + rmStatus = kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, id, &pKernelMIGGpuInstance); + if (rmStatus != NV_OK) + { + // Didn't find requested GPU instance + NV_PRINTF(LEVEL_ERROR, "No valid GPU instance with SwizzId - %d found\n", id); + return rmStatus; + } + + mask = NVBIT64(id); + + if (pKernelMIGGpuInstance->partitionFlag == partitionFlag) + { + // Validate that same ID is not already set and then set the ID + if (!(mask & pPhysGpuInfo->assignedSwizzIdMask)) + { + NV_ASSERT_OK_OR_RETURN(_kvgpumgrSetAssignedSwizzIdMask(pGpu, pKernelMIGGpuInstance->swizzId)); + *swizzId = pKernelMIGGpuInstance->swizzId; + break; + } + } + } + FOR_EACH_INDEX_IN_MASK_END; + + if (*swizzId == KMIGMGR_SWIZZID_INVALID) + { + return NV_ERR_INVALID_STATE; + } + + return NV_OK; } NV_STATUS @@ -219,15 +1738,81 @@ kvgpumgrValidateSwizzId(OBJGPU *pGpu, NvU32 vgpuTypeId, NvU32 swizzId) { - return NV_ERR_NOT_SUPPORTED; + KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); + NvU32 partitionFlag = PARTITIONID_INVALID; + NV_STATUS rmStatus = NV_OK; + KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance; + + // Check if swizzId is valid. + if (!kmigmgrIsSwizzIdInUse(pGpu, pKernelMIGManager, swizzId)) + { + return NV_ERR_INVALID_ARGUMENT; + } + + rmStatus = kmigmgrGetGPUInstanceInfo(pGpu, pKernelMIGManager, swizzId, &pKernelMIGGpuInstance); + if (rmStatus != NV_OK) + { + // Didn't find requested GPU instance + NV_PRINTF(LEVEL_ERROR, "No valid GPU instance with SwizzId - %d found\n", swizzId); + return rmStatus; + } + + NV_ASSERT_OK_OR_RETURN( + kvgpumgrGetPartitionFlag(vgpuTypeId, &partitionFlag)); + + // Check if swizzId is valid for vGPU type. + if (pKernelMIGGpuInstance->partitionFlag == partitionFlag) + { + NV_ASSERT_OK_OR_RETURN(_kvgpumgrSetAssignedSwizzIdMask(pGpu, swizzId)); + return NV_OK; + } + + return NV_ERR_INVALID_STATE; } NV_STATUS kvgpumgrGetPartitionFlag(NvU32 vgpuTypeId, NvU32 *partitionFlag) { + NvU32 i; + + *partitionFlag = PARTITIONID_INVALID; + + for (i = 0; i < NV_ARRAY_ELEMENTS(vgpuSmcTypeIdMappings); i++) + { + if (vgpuSmcTypeIdMappings[i].vgpuTypeId == vgpuTypeId) + { + *partitionFlag = vgpuSmcTypeIdMappings[i].partitionFlag; + return NV_OK; + } + } + + NV_PRINTF(LEVEL_ERROR, "Invalid SMC vGpu TypeId: 0x%x\n", vgpuTypeId); return NV_ERR_INVALID_ARGUMENT; } +static NV_STATUS +_kvgpumgrGetVgpuTypeIdFromPartitionFlag(NvU32 devId, NvU32 partitionFlag, NvU32 *vgpuTypeId) +{ + NvU32 i; + + *vgpuTypeId = NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE; + + for (i = 0; i < NV_ARRAY_ELEMENTS(vgpuSmcTypeIdMappings); i++) + { + // Currently vgpuTypeId to partitionFlag mapping is 1 to 1. + // In future, we might potentially hit issue if multiple + // type-ids map to the same partition flags + if ((vgpuSmcTypeIdMappings[i].devId == devId) && + (vgpuSmcTypeIdMappings[i].partitionFlag == partitionFlag)) + { + *vgpuTypeId = vgpuSmcTypeIdMappings[i].vgpuTypeId; + return NV_OK; + } + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + /* * Add or remove VF info to pgpuInfo of its PF * @param[in] gpuPciId PCI ID of target PF @@ -244,37 +1829,278 @@ kvgpumgrGetPartitionFlag(NvU32 vgpuTypeId, NvU32 *partitionFlag) NV_STATUS kvgpumgrProcessVfInfo(NvU32 gpuPciId, NvU8 cmd, NvU32 domain, NvU32 bus, NvU32 slot, NvU32 function, NvBool isMdevAttached, vgpu_vf_pci_info *vfPciInfo) { - return NV_ERR_NOT_SUPPORTED; + NvU32 i; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvU32 pgpuIndex; + NV_STATUS status = NV_OK; + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + vgpu_vf_pci_info *pVfInfo = NULL; + + if ((status = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, gpuPciId, &pgpuIndex)) != NV_OK) + return status; + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[pgpuIndex]); + + if (cmd == NV_VGPU_SAVE_VF_INFO) + { + /* Find existing entry for VF and set flags if found. */ + for (i = 0; i < MAX_VF_COUNT_PER_GPU; i++) + { + pVfInfo = &pPhysGpuInfo->vfPciInfo[i]; + + if ((domain == pVfInfo->domain) && + (bus == pVfInfo->bus) && + (slot == pVfInfo->slot) && + (function == pVfInfo->function)) + { + pVfInfo->isNvidiaAttached = NV_TRUE; + pVfInfo->isMdevAttached = isMdevAttached; + break; + } + } + + /* + * If entry doesn't already exist, populate an empty slot and complain + * if there isn't one. + */ + if (i == MAX_VF_COUNT_PER_GPU) + { + for (i = 0; i < MAX_VF_COUNT_PER_GPU; i++) + { + pVfInfo = &pPhysGpuInfo->vfPciInfo[i]; + if ((!pVfInfo->isNvidiaAttached)) + { + pVfInfo->domain = domain; + pVfInfo->bus = bus; + pVfInfo->slot = slot; + pVfInfo->function = function; + + pVfInfo->isNvidiaAttached = NV_TRUE; + pVfInfo->isMdevAttached = isMdevAttached; + break; + } + } + + if (i == MAX_VF_COUNT_PER_GPU) + { + NV_PRINTF(LEVEL_ERROR, "No free free slot to track VF PCI info\n"); + return NV_ERR_INVALID_STATE; + } + } + } + else if ((cmd == NV_VGPU_REMOVE_VF_PCI_INFO || cmd == NV_VGPU_REMOVE_VF_MDEV_INFO) && pPhysGpuInfo) + { + for (i = 0; i < MAX_VF_COUNT_PER_GPU; i++) + { + pVfInfo = &pPhysGpuInfo->vfPciInfo[i]; + + if ((domain == pVfInfo->domain) && + (bus == pVfInfo->bus) && + (slot == pVfInfo->slot) && + (function == pVfInfo->function)) + { + if (cmd == NV_VGPU_REMOVE_VF_PCI_INFO) + { + pVfInfo->isNvidiaAttached = NV_FALSE; + } + pVfInfo->isMdevAttached = NV_FALSE; + break; + } + } + + if (i == MAX_VF_COUNT_PER_GPU) + { + NV_PRINTF(LEVEL_ERROR, "Could not find entry for VF PCI info\n"); + return NV_ERR_MISSING_TABLE_ENTRY; + } + } + else if (cmd == NV_VGPU_GET_VF_INFO && vfPciInfo) + { + for (i = 0; i < MAX_VF_COUNT_PER_GPU; i++) + { + pVfInfo = &pPhysGpuInfo->vfPciInfo[i]; + portMemCopy(&vfPciInfo[i], sizeof(vgpu_vf_pci_info), pVfInfo, sizeof(vgpu_vf_pci_info)); + } + } + else + { + NV_PRINTF(LEVEL_ERROR, "Requested invalid operation on VF info\n"); + status = NV_ERR_INVALID_ARGUMENT; + } + + return status; } NV_STATUS kvgpumgrEnumerateVgpuPerPgpu(OBJGPU *pGpu, NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams) { - return NV_ERR_NOT_SUPPORTED; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU, + pParams, sizeof(*pParams))); + + return NV_OK; } NV_STATUS kvgpumgrClearGuestVmInfo(OBJGPU *pGpu, KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice) { - return NV_ERR_NOT_SUPPORTED; + NV2080_CTRL_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO_PARAMS params; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status; + + portMemSet(¶ms, 0, sizeof(params)); + params.gfid = pKernelHostVgpuDevice->gfid; + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_CLEAR_GUEST_VM_INFO, + ¶ms, sizeof(params)); + + if (status != NV_OK) + NV_PRINTF(LEVEL_ERROR, "Failed to clear guest vm info on GSP\n"); + + return status; +} + +NV_STATUS +kvgpumgrGetHostVgpuDeviceFromGfid(NvU32 gpuPciId, NvU32 gfid, + KERNEL_HOST_VGPU_DEVICE** ppHostVgpuDevice) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvU32 pgpuIndex; + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kvgpumgrGetPgpuIndex(pKernelVgpuMgr, gpuPciId, &pgpuIndex)); + pPgpuInfo = &pKernelVgpuMgr->pgpuInfo[pgpuIndex]; + + if (!pPgpuInfo->sriovEnabled) + return NV_ERR_NOT_SUPPORTED; + + for (pKernelHostVgpuDevice = listHead(&(pPgpuInfo->listHostVgpuDeviceHead)); + pKernelHostVgpuDevice != NULL; + pKernelHostVgpuDevice = listNext(&(pPgpuInfo->listHostVgpuDeviceHead), pKernelHostVgpuDevice)) + { + if (pKernelHostVgpuDevice->gfid == gfid) + { + *ppHostVgpuDevice = pKernelHostVgpuDevice; + return NV_OK; + } + } + + return NV_ERR_OBJECT_NOT_FOUND; } NV_STATUS kvgpumgrGetVgpuFbUsage(OBJGPU *pGpu, NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *pParams) { - return NV_ERR_NOT_SUPPORTED; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + NVA081_VGPU_FB_USAGE *pVgpuFbUsage; + NvU32 i = 0; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (gpuIsSriovEnabled(pGpu)) + { + NV2080_CTRL_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE_PARAMS internalParams; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + portMemSet(&internalParams, 0, sizeof(internalParams)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_GET_VGPU_FB_USAGE, + &internalParams, sizeof(internalParams))); + + if (internalParams.vgpuCount > NV_ARRAY_ELEMENTS(pParams->vgpuFbUsage)) + return NV_ERR_INSUFFICIENT_RESOURCES; + + for (i = 0; i < internalParams.vgpuCount; i++) + { + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kvgpumgrGetHostVgpuDeviceFromGfid(pGpu->gpuId, internalParams.vgpuFbUsage[i].gfid, &pKernelHostVgpuDevice)); + + pVgpuFbUsage = &pParams->vgpuFbUsage[i]; + + portMemCopy(pVgpuFbUsage->vgpuUuid, VGPU_UUID_SIZE, pKernelHostVgpuDevice->vgpuUuid, VGPU_UUID_SIZE); + + pVgpuFbUsage->fbUsed = internalParams.vgpuFbUsage[i].fbUsed; + } + + pParams->vgpuCount = internalParams.vgpuCount; + } + + return NV_OK; } NV_STATUS kvgpumgrSetVgpuEncoderCapacity(OBJGPU *pGpu, NvU8 *vgpuUuid, NvU32 encoderCapacity) { - return NV_ERR_NOT_SUPPORTED; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 i; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i)); + + pPhysGpuInfo = &pKernelVgpuMgr->pgpuInfo[i]; + + for (pKernelHostVgpuDevice = listHead(&(pPhysGpuInfo->listHostVgpuDeviceHead)); + pKernelHostVgpuDevice != NULL; + pKernelHostVgpuDevice = listNext(&(pPhysGpuInfo->listHostVgpuDeviceHead), pKernelHostVgpuDevice)) + { + if (portMemCmp(pKernelHostVgpuDevice->vgpuUuid, vgpuUuid, VGPU_UUID_SIZE) == 0) + break; + } + + if (pKernelHostVgpuDevice == NULL) + return NV_ERR_OBJECT_NOT_FOUND; + + if (gpuIsSriovEnabled(pGpu)) + { + NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY_PARAMS params; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + + params.gfid = pKernelHostVgpuDevice->gfid; + params.encoderCapacity = encoderCapacity; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_ENCODER_CAPACITY, + ¶ms, sizeof(params))); + } + + return NV_OK; } NV_STATUS kvgpumgrStart(const NvU8 *pMdevUuid, void *waitQueue, NvS32 *returnStatus, NvU8 *vmName, NvU32 qemuPid) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + + for (pRequestVgpu = listHead(&(pKernelVgpuMgr->listRequestVgpuHead)); + pRequestVgpu != NULL; + pRequestVgpu = listNext(&(pKernelVgpuMgr->listRequestVgpuHead), pRequestVgpu)) + { + if (portMemCmp(pMdevUuid, pRequestVgpu->mdevUuid, VGPU_UUID_SIZE) == 0) + { + pRequestVgpu->waitQueue = waitQueue; + pRequestVgpu->returnStatus = returnStatus; + pRequestVgpu->vmName = vmName; + pRequestVgpu->qemuPid = qemuPid; + + CliAddSystemEvent(NV0000_NOTIFIERS_VM_START, 0); + return NV_OK; + } + } return NV_ERR_OBJECT_NOT_FOUND; } @@ -290,7 +2116,147 @@ NV_STATUS kvgpumgrCreateRequestVgpu(NvU32 gpuPciId, const NvU8 *pMdevUuid, NvU32 vgpuTypeId, NvU16 *vgpuId, NvU32 gpuPciBdf) { - return NV_ERR_NOT_SUPPORTED; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = gpumgrGetGpuFromId(gpuPciId); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + NvU32 pgpuIndex; + NV_STATUS status = NV_OK; + VGPU_TYPE *vgpuTypeInfo; + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + NvU32 allocFlags = NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP; + NvU64 vgpuIdSize = 1, tmpVgpuId; + NvU8 devfn = gpuDecodeDevice(gpuPciBdf); + NvU32 swizzId = KMIGMGR_SWIZZID_INVALID; + + if (pGpu == NULL) + { + NV_PRINTF(LEVEL_ERROR, "GPU handle is not valid \n"); + return NV_ERR_INVALID_STATE; + } + + if ((status = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, gpuPciId, &pgpuIndex)) != NV_OK) + return status; + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[pgpuIndex]); + + if ((status = kvgpumgrGetVgpuTypeInfo(vgpuTypeId, &vgpuTypeInfo)) != NV_OK) + return status; + + /* + * For DriverVM, we will defer the createdVfMask validation later + * during open call when the params provided. + * + */ + + if (gpuIsSriovEnabled(pGpu) && + !(pHypervisor->getProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED))) + { + NvU8 fnId = devfn - pGpu->sriovState.firstVFOffset; + + NV_ASSERT_OR_RETURN((fnId < 64), NV_ERR_INVALID_ARGUMENT); + + if (pPhysGpuInfo->createdVfMask & NVBIT64(fnId)) + /* mdev device is already created on VF */ + return NV_ERR_INVALID_OPERATION; + } + + if (IS_MIG_ENABLED(pGpu)) + { + NvU32 partitionFlag = PARTITIONID_INVALID; + + NV_CHECK_OR_RETURN(LEVEL_INFO, + IS_MIG_IN_USE(pGpu), + NV_ERR_INVALID_OPERATION); + + NV_ASSERT_OK_OR_RETURN( + kvgpumgrGetPartitionFlag(vgpuTypeInfo->vgpuTypeId, &partitionFlag)); + + NV_ASSERT_OK_OR_RETURN( + kvgpumgrGetSwizzId(pGpu, pPhysGpuInfo, partitionFlag, &swizzId)); + } + else + { + // Creation request for a MIG vgpuType + if (vgpuTypeInfo->gpuInstanceSize) + return NV_ERR_INVALID_OPERATION; + + status = kvgpumgrCheckVgpuTypeCreatable(pGpu, pPhysGpuInfo, vgpuTypeInfo); + + if (status != NV_OK) + return status; + } + + /* Initialize heap on first vGPU device creation */ + if (pKernelVgpuMgr->pHeap == NULL) + { + NvU64 tmpSize; + pKernelVgpuMgr->pHeap = portMemAllocNonPaged(sizeof(OBJEHEAP)); + if (pKernelVgpuMgr->pHeap == NULL) + { + status = NV_ERR_NO_MEMORY; + goto failed; + } + + constructObjEHeap(pKernelVgpuMgr->pHeap, 1, 0xFFFF + 1, 0, 0); + + /* Verify if pHeap is allocated with required size */ + pKernelVgpuMgr->pHeap->eheapGetSize(pKernelVgpuMgr->pHeap, &tmpSize); + if (tmpSize != 0xFFFF) + { + pKernelVgpuMgr->pHeap->eheapDestruct(pKernelVgpuMgr->pHeap); + portMemFree(pKernelVgpuMgr->pHeap); + pKernelVgpuMgr->pHeap = NULL; + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto failed; + } + } + + status = pKernelVgpuMgr->pHeap->eheapAlloc(pKernelVgpuMgr->pHeap, 0xdeadbeef, &allocFlags, + &tmpVgpuId, &vgpuIdSize, 1, 1, + NULL, NULL, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_WARNING, + "Failed to allocate heap for vGPU ID 0x%x\n", + status); + goto failed; + } + + *vgpuId = (NvU16) tmpVgpuId; + pRequestVgpu = listPrependNew(&(pKernelVgpuMgr->listRequestVgpuHead)); + if (pRequestVgpu == NULL) + { + status = NV_ERR_NO_MEMORY; + goto failed; + } + + portMemSet(pRequestVgpu, 0, sizeof(REQUEST_VGPU_INFO_NODE)); + + portMemCopy(pRequestVgpu->mdevUuid, VGPU_UUID_SIZE, pMdevUuid, VGPU_UUID_SIZE); + pRequestVgpu->gpuPciId = gpuPciId; /* For SRIOV, this is PF's gpuPciId */ + pRequestVgpu->vgpuId = *vgpuId; + pRequestVgpu->gpuPciBdf = gpuPciBdf; /* For SRIOV, this is VF's gpuPciBdf */ + + if (IS_MIG_IN_USE(pGpu)) + { + pRequestVgpu->swizzId = swizzId; + } + + _kvgpumgrSetVgpuType(pGpu, pPhysGpuInfo, vgpuTypeId); + pPhysGpuInfo->numCreatedVgpu++; + + if (gpuGetDevice(pGpu) != devfn) /* SRIOV - VF */ + pPhysGpuInfo->createdVfMask |= NVBIT64(devfn - pGpu->sriovState.firstVFOffset); + + return NV_OK; + +failed: + if (swizzId != KMIGMGR_SWIZZID_INVALID) + _kvgpumgrClearAssignedSwizzIdMask(pGpu, swizzId); + + return status; } // @@ -300,6 +2266,46 @@ kvgpumgrCreateRequestVgpu(NvU32 gpuPciId, const NvU8 *pMdevUuid, NV_STATUS kvgpumgrDeleteRequestVgpu(const NvU8 *pMdevUuid, NvU16 vgpuId) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPU *pGpu = NULL; + NV_STATUS status; + NvU32 pgpuIndex; + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + REQUEST_VGPU_INFO_NODE *pRequestVgpuNext = NULL; + NvU8 devfn = 0; + + for (pRequestVgpu = listHead(&(pKernelVgpuMgr->listRequestVgpuHead)); + pRequestVgpu != NULL; + pRequestVgpu = pRequestVgpuNext) + { + pRequestVgpuNext = listNext(&(pKernelVgpuMgr->listRequestVgpuHead), pRequestVgpu); + if (portMemCmp(pMdevUuid, pRequestVgpu->mdevUuid, VGPU_UUID_SIZE) == 0) + { + if ((status = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pRequestVgpu->gpuPciId, + &pgpuIndex)) != NV_OK) + return status; + + pGpu = gpumgrGetGpuFromId(pRequestVgpu->gpuPciId); + devfn = gpuDecodeDevice(pRequestVgpu->gpuPciBdf); + + pKernelVgpuMgr->pgpuInfo[pgpuIndex].numCreatedVgpu--; + + if (pGpu && (gpuGetDevice(pGpu) != devfn)) // SRIOV - VF + pKernelVgpuMgr->pgpuInfo[pgpuIndex].createdVfMask &= ~(NVBIT64(devfn - pGpu->sriovState.firstVFOffset)); + + if (IS_MIG_ENABLED(pGpu)) + _kvgpumgrClearAssignedSwizzIdMask(pGpu, pRequestVgpu->swizzId); + else if (pKernelVgpuMgr->pgpuInfo[pgpuIndex].numCreatedVgpu == 0) + _kvgpumgrSetVgpuType(pGpu, &pKernelVgpuMgr->pgpuInfo[pgpuIndex], NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE); + + pKernelVgpuMgr->pHeap->eheapFree(pKernelVgpuMgr->pHeap, vgpuId); + + listRemove(&(pKernelVgpuMgr->listRequestVgpuHead), pRequestVgpu); + + return NV_OK; + } + } return NV_ERR_OBJECT_NOT_FOUND; } @@ -307,6 +2313,32 @@ NV_STATUS kvgpumgrGetHostVgpuDeviceFromMdevUuid(NvU32 gpuPciId, const NvU8 *pMdevUuid, KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvU32 pgpuIndex , rmStatus; + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, gpuPciId, &pgpuIndex)) != NV_OK) + return rmStatus; + + pPgpuInfo = &pKernelVgpuMgr->pgpuInfo[pgpuIndex]; + + for (pKernelHostVgpuDevice = listHead(&(pPgpuInfo->listHostVgpuDeviceHead)); + pKernelHostVgpuDevice != NULL; + pKernelHostVgpuDevice = listNext(&(pPgpuInfo->listHostVgpuDeviceHead), pKernelHostVgpuDevice)) + { + if (pKernelHostVgpuDevice == NULL || pKernelHostVgpuDevice->pRequestVgpuInfoNode == NULL) + return NV_ERR_INVALID_POINTER; + + if (portMemCmp(pKernelHostVgpuDevice->pRequestVgpuInfoNode->mdevUuid, + pMdevUuid, VM_UUID_SIZE) == 0) + { + *ppKernelHostVgpuDevice = pKernelHostVgpuDevice; + return NV_OK; + } + } + NV_PRINTF(LEVEL_ERROR, "Object not found\n"); return NV_ERR_OBJECT_NOT_FOUND; } @@ -314,7 +2346,689 @@ NV_STATUS kvgpumgrGetHostVgpuDeviceFromVgpuUuid(NvU32 gpuPciId, NvU8 *vgpuUuid, KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice) { - return NV_ERR_NOT_SUPPORTED; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvU32 pgpuIndex; + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kvgpumgrGetPgpuIndex(pKernelVgpuMgr, gpuPciId, &pgpuIndex)); + + pPgpuInfo = &pKernelVgpuMgr->pgpuInfo[pgpuIndex]; + + for (pKernelHostVgpuDevice = listHead(&(pPgpuInfo->listHostVgpuDeviceHead)); + pKernelHostVgpuDevice != NULL; + pKernelHostVgpuDevice = listNext(&(pPgpuInfo->listHostVgpuDeviceHead), pKernelHostVgpuDevice)) + { + if (portMemCmp(pKernelHostVgpuDevice->vgpuUuid, + vgpuUuid, VM_UUID_SIZE) == 0) + { + *ppKernelHostVgpuDevice = pKernelHostVgpuDevice; + return NV_OK; + } + } + + return NV_ERR_OBJECT_NOT_FOUND; +} + +/* + * On 1GB profiles on 48GB board, we do not deduct any reserved fb from vGPU FB length + * as maxInstance is only 32, so guest complete 1GB of fb mem. In such cases with + * heterogeneous vGPUs, for such 1G profiles on 48G board, some combinations with + * other vGPU types do not work. + * Due to this, A40-8Q at placement Id 0 cannot work with A40-1Q at placement Id 8 since + * A40-1Q is occupying larger vGPU FB length and overlaps with A40-8Q's assigned FB. + * Similar scenario happens for A40-8Q at placement Id 24 and A40-1Q at placement Id 32 + * So, we disable 1GB profiles in such cases at placement Id 8 and placement Id 32. + */ +static NvBool +_kvgpumgrIsPlacementValid(OBJGPU *pGpu, KERNEL_PHYS_GPU_INFO *pPgpuInfo, NvU32 vgpuTypeIndex, + NvU32 placementId) +{ + NvU64 vgpuFbLength; + NvU32 denyListAdaHopper[] = {2, 3, 8, 9, 14, 15, 20, 21, 26, 27, 32, 33, 38, 39, 44, 45}; + NvU32 denyListAmpere[] = {8, 32}; + NvU32 i, length, *invalidPlacements; + + if (IS_GSP_CLIENT(pGpu)) + { + invalidPlacements = denyListAdaHopper; + length = sizeof(denyListAdaHopper) / sizeof(NvU32); + } + else + { + invalidPlacements = denyListAmpere; + length = sizeof(denyListAmpere) / sizeof(NvU32); + } + + vgpuFbLength = pPgpuInfo->guestVmmuCount[vgpuTypeIndex] * gpuGetVmmuSegmentSize(pGpu); + + if (vgpuFbLength == VGPU_LOWER_FB_PROFILE_SIZE_1_GB) + { + for (i = 0; i < length; i++) + { + if (invalidPlacements[i] == placementId) + return NV_FALSE; + } + } + + return NV_TRUE; +} + +/* + * This function recursively divides the placement region in 1/2, 1/4, 1/8, 1/16 partitions + * and then calculates the placement IDs of each vGPU type. It will try to allocate + * placement ID of 2 vGPU instances for a type in such a way that the placement ID + * of first vGPU instance starts at the beginning of partition and the placement ID + * of second vGPU instance ends at the end of partition. + * + * It finds the vGPU types whose 2 instances can be allocated in a 1/2, 1/4, 1/8, 1/16 + * partition and then allocates one at start of partition and other at end of partion. + * + * It does this recursively by taking input start and end as input alongwith the current + * partition which specifies whether this is 1/1, 1/2, 1/4, 1/8, 1/16 partion. + * + * Similarly it also calculates the channel offsets for each supported placementId + * for a vGPU type. The algorithm for calculating placementId and channel offset + * is the same just that for channel offset the range is from 0 to 2048. + * + * For vGPU-GSP, we also need to define offsets in FB for GSP plugin heap. + * For larger vGPU profiles with GSP plugin heap >=1 vMMU segment, the gsp heap is + * placed at the end of vGPU FB. + * For smaller profiles with gsp heap < 1 vMMU segment, heap is placed at end of + * each 1/4th alignment (for 128MB vMMU segment size) OR 1/8th alighment (for 64MB + * vMMU segment size). For such profiles the vMMU segment at the end of 1/4 or 1/8 + * partition is divided as per profile's heap size. + * + */ +static void +_kvgpumgrSetHeterogeneousResources(OBJGPU *pGpu, KERNEL_PHYS_GPU_INFO *pPgpuInfo, NvU32 placementIdMin, + NvU32 placementIdMax, NvU32 chidMin, NvU32 chidMax, + NvU32 vmmuSegMin, NvU32 vmmuSegMax, NvU64 gspHeapOffsetMin, + NvU64 gspHeapOffsetMax, NvU32 partitionCount, + NvBool isLeftPartition) +{ + VGPU_TYPE *pVgpuTypeInfo; + NvU32 heterogeneousMaxInstance, i; + NvBool isCarveOutGspHeap = NV_FALSE; + NvU64 newVmmuSegMin, newVmmuSegMax, newGspHeapOffsetMin, newGspHeapOffsetMax, vmmuSegSize; + NvBool isDefineLeftPlacement, isDefineRightPlacement; + + /* + * As max vGPU per GPU is 32, the minimum partition for 2 vGPUs will be 16. + * So, if this is a 1/16 partition, don't recurse further + */ + if (partitionCount > MAX_VGPU_DEVICES_PER_PGPU / 2) + return; + + vmmuSegSize = gpuGetVmmuSegmentSize(pGpu); + for (i = 0; i < pPgpuInfo->numVgpuTypes; i++) + { + pVgpuTypeInfo = pPgpuInfo->vgpuTypes[i]; + + if (pVgpuTypeInfo->placementSize == 0) + continue; + + isDefineLeftPlacement = NV_FALSE; + isDefineRightPlacement = NV_FALSE; + + heterogeneousMaxInstance = nvPrevPow2_U32(pVgpuTypeInfo->maxInstance); + + /* + * If homogeneous maxInstances of vGPU type are in power-of-2 and can fit in this partition, + * then define both the placements in this recursive call + */ + if (partitionCount * 2 == pVgpuTypeInfo->maxInstance) + { + isDefineLeftPlacement = NV_TRUE; + isDefineRightPlacement = NV_TRUE; + + /* + * Check if the next recursive partition will be a smaller partition for which + * we need to carve out GSP heap at the end of smaller partition. + */ + if (IS_GSP_CLIENT(pGpu) && (isCarveOutGspHeap == NV_FALSE) && + (pVgpuTypeInfo->gspHeapSize == vmmuSegSize)) + isCarveOutGspHeap = NV_TRUE; + } + else if (((heterogeneousMaxInstance < pVgpuTypeInfo->maxInstance) && + (heterogeneousMaxInstance == partitionCount)) || + ((partitionCount == 1) && (pVgpuTypeInfo->maxInstance == 1))) + { + /* + * If only one instance of vGPU type can fit in this partition, then define + * placement depending on whether it is a left or right partition + */ + isDefineLeftPlacement = isLeftPartition; + isDefineRightPlacement = !isLeftPartition; + } + + + if (isDefineLeftPlacement == NV_TRUE) + { + /* + * Fill placement ID / channel / FB offset of first vGPU in this partition + * First vGPU is aligned to the starting of partition + */ + if (_kvgpumgrIsPlacementValid(pGpu, pPgpuInfo, i, placementIdMin)) + { + pVgpuTypeInfo->supportedPlacementIds[pVgpuTypeInfo->placementCount] = placementIdMin; + pVgpuTypeInfo->supportedChidOffsets[pVgpuTypeInfo->placementCount] = chidMin; + + if (!IS_GSP_CLIENT(pGpu)) + pPgpuInfo->supportedVmmuOffsets[i][pVgpuTypeInfo->placementCount] = vmmuSegMin; + else + { + /* If profile occupies > 1 vMMU segment for GSP heap, place heap at end of vGPU FB. */ + if (pVgpuTypeInfo->gspHeapSize >= vmmuSegSize) + { + pPgpuInfo->supportedVmmuOffsets[i][pVgpuTypeInfo->placementCount] = vmmuSegMin; + pPgpuInfo->gspHeapOffsets[i][pVgpuTypeInfo->placementCount] = + (vmmuSegMin + pPgpuInfo->guestVmmuCount[i]) * vmmuSegSize; + } + else + { + /* + * If we're in smaller parition, GSP vMMU segment will be input to the function. + * Place the gsp heap of first vGPU at the starting of the GSP vMMU segment. + */ + pPgpuInfo->supportedVmmuOffsets[i][pVgpuTypeInfo->placementCount] = vmmuSegMin; + pPgpuInfo->gspHeapOffsets[i][pVgpuTypeInfo->placementCount] = gspHeapOffsetMin; + } + + /* For 32:1 vGPU types, the GSP heap is placed between 2 consecutive guest vMMU segments */ + if (heterogeneousMaxInstance == 32) + { + pPgpuInfo->supportedVmmuOffsets[i][pVgpuTypeInfo->placementCount] = vmmuSegMin; + pPgpuInfo->gspHeapOffsets[i][pVgpuTypeInfo->placementCount] = + (vmmuSegMin + pPgpuInfo->guestVmmuCount[i]) * vmmuSegSize; + } + } + + pVgpuTypeInfo->placementCount++; + } + } + + if (isDefineRightPlacement == NV_TRUE) + { + /* + * Fill placement ID / channel / FB offset of second vGPU in this partition + * Second vGPU is aligned to the end of partition + */ + if (_kvgpumgrIsPlacementValid(pGpu, pPgpuInfo, i, + placementIdMax - pVgpuTypeInfo->placementSize)) + { + pVgpuTypeInfo->supportedPlacementIds[pVgpuTypeInfo->placementCount] = + placementIdMax - pVgpuTypeInfo->placementSize; + + pVgpuTypeInfo->supportedChidOffsets[pVgpuTypeInfo->placementCount] = + chidMax - pVgpuTypeInfo->channelCount; + + if (!IS_GSP_CLIENT(pGpu)) + pPgpuInfo->supportedVmmuOffsets[i][pVgpuTypeInfo->placementCount] = + vmmuSegMax - pPgpuInfo->guestVmmuCount[i]; + else + { + /* If profile occupies > 1 vMMU segment for GSP heap, place heap at end of vGPU FB. */ + if (pVgpuTypeInfo->gspHeapSize >= vmmuSegSize) + { + pPgpuInfo->supportedVmmuOffsets[i][pVgpuTypeInfo->placementCount] = + vmmuSegMax - pPgpuInfo->guestVmmuCount[i] - (pVgpuTypeInfo->gspHeapSize / vmmuSegSize); + pPgpuInfo->gspHeapOffsets[i][pVgpuTypeInfo->placementCount] = + (vmmuSegMax * vmmuSegSize) - pVgpuTypeInfo->gspHeapSize; + } + else + { + /* + * If we're in smaller parition, GSP vMMU segment will be input to the function. + * Place the gsp heap of first vGPU at the starting of the GSP vMMU segment. + */ + pPgpuInfo->supportedVmmuOffsets[i][pVgpuTypeInfo->placementCount] = + vmmuSegMax - pPgpuInfo->guestVmmuCount[i]; + pPgpuInfo->gspHeapOffsets[i][pVgpuTypeInfo->placementCount] = + gspHeapOffsetMax - pVgpuTypeInfo->gspHeapSize; + } + + /* For 32:1 vGPU types, the GSP heap is placed between 2 consecutive guest vMMU segments */ + if (heterogeneousMaxInstance == 32) + { + pPgpuInfo->supportedVmmuOffsets[i][pVgpuTypeInfo->placementCount] = + vmmuSegMax - pPgpuInfo->guestVmmuCount[i]; + pPgpuInfo->gspHeapOffsets[i][pVgpuTypeInfo->placementCount] = + ((vmmuSegMax - pPgpuInfo->guestVmmuCount[i]) * vmmuSegSize) - pVgpuTypeInfo->gspHeapSize; + } + } + + pVgpuTypeInfo->placementCount++; + } + } + } + + /* + * If the next recursive partition is for smaller partition which has GSP heap at + * of end of partition, then update vmmuSegMax to reserve one segment at the + * end of smaller partition. Also, init gsp min/max value for the reserved vMMU segment + * at the end. + */ + newVmmuSegMin = vmmuSegMin; + if ((isCarveOutGspHeap == NV_TRUE)) + { + NV_ASSERT((gspHeapOffsetMin == 0)); + + newVmmuSegMax = ((vmmuSegMin + vmmuSegMax) / 2) - 1; + newGspHeapOffsetMin = newVmmuSegMax * vmmuSegSize; + newGspHeapOffsetMax = newGspHeapOffsetMin + vmmuSegSize; + } + else + { + newVmmuSegMax = (vmmuSegMin + vmmuSegMax) / 2; + newGspHeapOffsetMin = gspHeapOffsetMin; + newGspHeapOffsetMax = (gspHeapOffsetMin + gspHeapOffsetMax) / 2; + } + + /* Recursively call to get placment ID in first half of this partition */ + _kvgpumgrSetHeterogeneousResources(pGpu, pPgpuInfo, placementIdMin, + (placementIdMin + placementIdMax) / 2, + chidMin, (chidMin + chidMax) / 2, newVmmuSegMin, + newVmmuSegMax, newGspHeapOffsetMin, newGspHeapOffsetMax, partitionCount * 2, + NV_TRUE); + + newVmmuSegMin = (vmmuSegMin + vmmuSegMax) / 2; + if ((isCarveOutGspHeap == NV_TRUE)) + { + newVmmuSegMax = vmmuSegMax - 1; + newGspHeapOffsetMin = newVmmuSegMax * vmmuSegSize; + newGspHeapOffsetMax = newGspHeapOffsetMin + vmmuSegSize; + } + else + { + newVmmuSegMax = vmmuSegMax; + newGspHeapOffsetMin = (gspHeapOffsetMin + gspHeapOffsetMax) / 2;; + newGspHeapOffsetMax = gspHeapOffsetMax; + } + + /* Recursively call to get placment ID in second half of this partition */ + _kvgpumgrSetHeterogeneousResources(pGpu, pPgpuInfo, (placementIdMin + placementIdMax) / 2, + placementIdMax, (chidMin + chidMax) / 2, + chidMax, newVmmuSegMin, newVmmuSegMax, + newGspHeapOffsetMin, newGspHeapOffsetMax, partitionCount * 2, + NV_FALSE); +} + +NV_STATUS +kvgpumgrSetSupportedPlacementIds(OBJGPU *pGpu) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + NV_STATUS rmStatus = NV_OK; + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + NvU32 index, i; + VGPU_TYPE *pVgpuTypeInfo; + NvU32 hostChannelCount = 0, totalVmmuCount = 0; + NvU64 totalReservedFb, vgpuReservedFb, guestFbLength, totalAvailableFb, totalRequiredFb; + NvU64 gspHeapOffsetMax, gspHeapOffsetMin, pmaRegionLength, pmaBaseOffset, largestOffset; + NvU64 vmmuOffsetMin, vmmuOffsetMax, vmmuSegmentMin, vmmuSegmentMax; + Heap *pHeap = GPU_GET_HEAP(pGpu); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &index)); + + pPgpuInfo = &(pKernelVgpuMgr->pgpuInfo[index]); + + pPgpuInfo->heterogeneousTimesliceSizesSupported = NV_FALSE; + + /* Initially, heterogeneous vgpus enabled only for sriov vGPUs on VMware/KVM */ + if (gpuIsSriovEnabled(pGpu)) + { + if (osIsVgpuVfioPresent() == NV_OK) + pPgpuInfo->heterogeneousTimesliceSizesSupported = NV_TRUE; + } + + if (!pPgpuInfo->heterogeneousTimesliceSizesSupported) + return rmStatus; + + hostChannelCount = kfifoChidMgrGetNumChannels(pGpu, pKernelFifo, pKernelFifo->ppChidMgr[0]); + + for (i = 0; i < pPgpuInfo->numVgpuTypes; i++) + { + pVgpuTypeInfo = pPgpuInfo->vgpuTypes[i]; + if (pVgpuTypeInfo == NULL) + break; + + /* Set to NVA081_PLACEMENT_ID_INVALID initially */ + portMemSet(pVgpuTypeInfo->supportedPlacementIds, NV_U8_MAX, + sizeof(pVgpuTypeInfo->supportedPlacementIds)); + + /* Ignore MIG vGPUs, only used for timesliced vGPUs */ + if (pVgpuTypeInfo->gpuInstanceSize != 0) + { + pVgpuTypeInfo->placementSize = 0; + continue; + } + + pVgpuTypeInfo->placementCount = 0; + pPgpuInfo->guestVmmuCount[i] = 0; + pVgpuTypeInfo->placementSize = pVgpuTypeInfo->profileSize / (1024 * 1024 * 1024); + + if (gpuIsSriovEnabled(pGpu)) + { + if (!gpuIsNonPowerOf2ChannelCountSupported(pGpu)) + pVgpuTypeInfo->channelCount = nvPrevPow2_U32(hostChannelCount / + pVgpuTypeInfo->maxInstance); + + /* + * For sriov vGPUs with GSP disabled, guest FB length is only dependent on + * profile fb length and RM reserved fb (including ECC). Calculate the + * guest fb length here by reducing reserved FB from profile fb length + * depending on max instance and aligning it to VMMU segment size. + */ + if (!IS_GSP_CLIENT(pGpu)) + { + totalReservedFb = memmgrGetVgpuHostRmReservedFb_HAL(pGpu, + pMemoryManager, pVgpuTypeInfo->vgpuTypeId) + + kvgpumgrGetEccAndPrReservedFb(pGpu); + + vgpuReservedFb = NV_ALIGN_UP((totalReservedFb / pVgpuTypeInfo->maxInstance), + gpuGetVmmuSegmentSize(pGpu)); + + /* + * For 1GB profiles on 48GB board, maxInstances is limited to 32. For such + * profiles, there is no per vgpu reserved fb carved out from guest fb as + * host has space for reserved fb. + */ + if (pVgpuTypeInfo->profileSize == VGPU_LOWER_FB_PROFILE_SIZE_1_GB) + { + heapGetUsableSize(pHeap, &totalAvailableFb); + + /* Total FB needed if vgpu reserved fb is 0 and not carved from guest fb */ + totalRequiredFb = pVgpuTypeInfo->maxInstance * + (VGPU_LOWER_FB_PROFILE_SIZE_1_GB + vgpuReservedFb); + + if (totalRequiredFb < totalAvailableFb) + vgpuReservedFb = 0; + } + + guestFbLength = pVgpuTypeInfo->profileSize - vgpuReservedFb; + + pPgpuInfo->guestVmmuCount[i] = guestFbLength / gpuGetVmmuSegmentSize(pGpu); + } + else + { + /* Calculate the guest FB using similar calculation as done in vGPU plugin */ + totalAvailableFb = pMemoryManager->Ram.fbTotalMemSizeMb << 20; + totalAvailableFb = NV_ALIGN_UP(totalAvailableFb, 8 * gpuGetVmmuSegmentSize(pGpu)); + + guestFbLength = (totalAvailableFb / pVgpuTypeInfo->maxInstance) - + pVgpuTypeInfo->fbReservation - pVgpuTypeInfo->gspHeapSize; + guestFbLength = NV_MIN(guestFbLength, pVgpuTypeInfo->fbLength); + guestFbLength = NV_ALIGN_DOWN(guestFbLength, gpuGetVmmuSegmentSize(pGpu)); + + pPgpuInfo->guestVmmuCount[i] = guestFbLength / gpuGetVmmuSegmentSize(pGpu); + } + } + + if (pVgpuTypeInfo->maxInstance == 1) + { + pPgpuInfo->placementRegionSize = pVgpuTypeInfo->placementSize; + + if (pPgpuInfo->guestVmmuCount[i]) + { + totalVmmuCount = pPgpuInfo->guestVmmuCount[i]; + + if (IS_GSP_CLIENT(pGpu)) + totalVmmuCount += (pVgpuTypeInfo->gspHeapSize / gpuGetVmmuSegmentSize(pGpu)); + } + } + } + + /* + * For SRIOV, the placement IDs are aligned to 1/2, 1/4, 1/8, 1/16 partitions + * due to restrictions on channels assigned to VF being in power-of-2. + * TODO : Define placement IDs for legacy vGPUs which do not have + * power-of-2 channel restriction + */ + if (gpuIsSriovEnabled(pGpu)) + { + pmaGetLargestFree(&pHeap->pmaObject, &pmaRegionLength, + &pmaBaseOffset, &largestOffset); + + vmmuOffsetMin = NV_ALIGN_UP(pmaBaseOffset, gpuGetVmmuSegmentSize(pGpu)); + vmmuOffsetMax = pmaBaseOffset + pmaRegionLength; + + totalRequiredFb = (totalVmmuCount * gpuGetVmmuSegmentSize(pGpu)); + if ((vmmuOffsetMax - vmmuOffsetMin) < totalRequiredFb) + { + NV_PRINTF(LEVEL_ERROR, "Required FB for heterogeneous vGPU (%llu) less " + "than available FB (%llu)\n", totalRequiredFb, pmaRegionLength); + NV_ASSERT(0); + + // Disable heterogeneous vGPU support, but return success to allow homogeneous vGPUs. + pPgpuInfo->heterogeneousTimesliceSizesSupported = NV_FALSE; + return NV_OK; + } + + vmmuSegmentMin = vmmuOffsetMin / gpuGetVmmuSegmentSize(pGpu); + vmmuSegmentMax = vmmuSegmentMin + totalVmmuCount; + + gspHeapOffsetMin = 0; + gspHeapOffsetMax = 0; + + _kvgpumgrSetHeterogeneousResources(pGpu, pPgpuInfo, 0, pPgpuInfo->placementRegionSize, + 0, hostChannelCount, vmmuSegmentMin, vmmuSegmentMax, + gspHeapOffsetMin, gspHeapOffsetMax, 1, NV_TRUE); + } + + return rmStatus; +} + +static NvBool +isPlacementOverlapping(NvU16 minId1, NvU16 maxId1, NvU16 id2, NvU16 size2) +{ + NvU16 max, min, size1; + + min = NV_MIN(minId1, id2); + max = NV_MAX(maxId1, (id2 + size2)); + size1 = maxId1 - minId1; + + if ((size1 + size2) > (max - min)) + return NV_TRUE; + + return NV_FALSE; +} + +static NvBool +isPlacementSubset(NvU16 min, NvU16 max, NvU16 id, NvU16 size) +{ + if ((min <= id) && (max >= (id + size - 1))) + return NV_TRUE; + + return NV_FALSE; +} + +static NV_STATUS +_kvgpumgrUpdateCreatablePlacementIds(OBJGPU *pGpu, NvU16 placementId, NvU32 vgpuTypeId, NvBool isAlloc) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + VGPU_TYPE *pVgpuTypeInfo; + NvU32 index, i , j, placementSize, min = 0, max = 0, numCreatable = 0; + NV_RANGE range; + NvBool isVgpuTypeCreatable; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &index)); + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kvgpumgrGetVgpuTypeInfo(vgpuTypeId, &pVgpuTypeInfo)); + + pPgpuInfo = &(pKernelVgpuMgr->pgpuInfo[index]); + placementSize = pVgpuTypeInfo->placementSize; + + range = rangeMake(placementId, placementId + placementSize - 1); + + if (isAlloc) + { + /* Update the placment region bitmap to set (id + size) slots */ + bitVectorSetRange(&pPgpuInfo->usedPlacementRegionMap, range); + min = placementId; + max = placementId + placementSize; + } + else + { + /* Update the placment region bitmap to unset (id + size) slots */ + bitVectorClrRange(&pPgpuInfo->usedPlacementRegionMap, range); + + /* find the minimum slot before placement ID which is not occupied */ + min = placementId; + for (j = placementId; j > 0;) + { + j--; + + if (bitVectorTest(&pPgpuInfo->usedPlacementRegionMap, j)) + break; + + min = j; + } + + /* find the maximum slot after placement ID + placementSize which is not occupied */ + max = placementId + placementSize - 1; + for (j = placementId + placementSize; j < pPgpuInfo->placementRegionSize; j++) + { + if (bitVectorTest(&pPgpuInfo->usedPlacementRegionMap, j)) + break; + + max = j; + } + } + + for (i = 0; i < MAX_VGPU_TYPES_PER_PGPU; i++) + pPgpuInfo->supportedTypeIds[i] = NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE; + + /* Update creatable placement Ids of all vGPU type IDs */ + for (i = 0; i < pPgpuInfo->numVgpuTypes; i++) + { + pVgpuTypeInfo = pPgpuInfo->vgpuTypes[i]; + if (pVgpuTypeInfo == NULL) + break; + + if (pVgpuTypeInfo->placementSize == 0) + continue; + + isVgpuTypeCreatable = NV_FALSE; + + for (j = 0; j < pVgpuTypeInfo->placementCount; j++) + { + /* + * Creatable Placement IDs will be updated either on VM boot or VM shutdown. + * 1. VM boot. + * Here, we compare every (id + size) of each vGPU type if it's partial/full + * overlapping with the (id + size) of the vGPU VM that is booting up. + * If yes, then mark that placement ID as INVALID. + * 2. VM shutdown + * Here, we compare every INVALID id of each vGPU type and + * see if the corresponding supported (id + size) is a complete subset + * of (max - min) range of available placement slots. + * If it is subset, then the INVALID id is overwritten with + * corresponding supported id as it is now creatable. + */ + if (pPgpuInfo->creatablePlacementIds[i][j] != NVA081_PLACEMENT_ID_INVALID) + { + if (isAlloc && isPlacementOverlapping(min, max, + pPgpuInfo->creatablePlacementIds[i][j], + pVgpuTypeInfo->placementSize)) + pPgpuInfo->creatablePlacementIds[i][j] = NVA081_PLACEMENT_ID_INVALID; + + } + else + { + if (!isAlloc && isPlacementSubset(min, max, pVgpuTypeInfo->supportedPlacementIds[j], + pVgpuTypeInfo->placementSize)) + pPgpuInfo->creatablePlacementIds[i][j] = pVgpuTypeInfo->supportedPlacementIds[j]; + } + + if (pPgpuInfo->creatablePlacementIds[i][j] != NVA081_PLACEMENT_ID_INVALID) + isVgpuTypeCreatable = NV_TRUE; + } + + if (isVgpuTypeCreatable) + pPgpuInfo->supportedTypeIds[numCreatable++] = pVgpuTypeInfo->vgpuTypeId; + } + + return NV_OK; +} + +NV_STATUS +kvgpumgrUpdateHeterogeneousInfo(OBJGPU *pGpu, NvU32 vgpuTypeId, NvU16 *placementId, + NvU64 *guestFbLength, NvU64 *guestFbOffset, + NvU64 *gspHeapOffset) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + VGPU_TYPE *pVgpuTypeInfo; + NvU32 index, i , j; + NvBool bIdFound = NV_FALSE; + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, + kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &index)); + + pPgpuInfo = &(pKernelVgpuMgr->pgpuInfo[index]); + + for (i = 0; i < pPgpuInfo->numVgpuTypes; i++) + { + pVgpuTypeInfo = pPgpuInfo->vgpuTypes[i]; + if (pVgpuTypeInfo == NULL) + break; + + if (pVgpuTypeInfo->vgpuTypeId == vgpuTypeId) + { + for (j = 0; j < pVgpuTypeInfo->placementCount; j++) + { + /* + * If hypervisor hasn't provided the placement ID as input, look + * for the first available placement ID for the input vGPU type. + * If hypervisor has provided the placement ID as input, just + * validate if it is a creatable placement ID. + */ + if (*placementId == NVA081_PLACEMENT_ID_INVALID) + { + if (pPgpuInfo->creatablePlacementIds[i][j] != NVA081_PLACEMENT_ID_INVALID) + { + *placementId = pPgpuInfo->creatablePlacementIds[i][j]; + *guestFbOffset = pPgpuInfo->supportedVmmuOffsets[i][j] * + gpuGetVmmuSegmentSize(pGpu); + *guestFbLength = pPgpuInfo->guestVmmuCount[i] * + gpuGetVmmuSegmentSize(pGpu); + *gspHeapOffset = pPgpuInfo->gspHeapOffsets[i][j]; + bIdFound = NV_TRUE; + break; + } + } + else + { + if (pPgpuInfo->creatablePlacementIds[i][j] == *placementId) + { + *guestFbOffset = pPgpuInfo->supportedVmmuOffsets[i][j] * + gpuGetVmmuSegmentSize(pGpu); + *guestFbLength = pPgpuInfo->guestVmmuCount[i] * + gpuGetVmmuSegmentSize(pGpu); + *gspHeapOffset = pPgpuInfo->gspHeapOffsets[i][j]; + bIdFound = NV_TRUE; + break; + } + } + } + } + } + + /* No creatable placement ID found */ + if (!bIdFound) + return NV_ERR_INVALID_STATE; + + return _kvgpumgrUpdateCreatablePlacementIds(pGpu, *placementId, vgpuTypeId, NV_TRUE); } NV_STATUS @@ -323,6 +3037,28 @@ kvgpumgrGetConfigEventInfoFromDb(NvHandle hClient, VGPU_CONFIG_EVENT_INFO_NODE **ppVgpuConfigEventInfoNode, NvU32 pgpuIndex) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + VGPU_CONFIG_EVENT_INFO_NODE *pVgpuConfigEventInfoNodeTemp; + + if (!ppVgpuConfigEventInfoNode) + { + return NV_ERR_INVALID_ARGUMENT; + } + + for (pVgpuConfigEventInfoNodeTemp = listHead(&(pKernelVgpuMgr->pgpuInfo[pgpuIndex].listVgpuConfigEventsHead)); + pVgpuConfigEventInfoNodeTemp != NULL; + pVgpuConfigEventInfoNodeTemp = listNext(&(pKernelVgpuMgr->pgpuInfo[pgpuIndex].listVgpuConfigEventsHead), pVgpuConfigEventInfoNodeTemp)) + { + if ((pVgpuConfigEventInfoNodeTemp->hClient == hClient) && + (pVgpuConfigEventInfoNodeTemp->hVgpuConfig == hVgpuConfig)) + { + *ppVgpuConfigEventInfoNode = pVgpuConfigEventInfoNodeTemp; + return NV_OK; + } + } + + *ppVgpuConfigEventInfoNode = NULL; return NV_ERR_OBJECT_NOT_FOUND; } @@ -334,5 +3070,75 @@ kvgpuMgrRestoreSmcExecPart KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS rmStatus = NV_OK; + NvU32 CIIdx; + NVC637_CTRL_EXEC_PARTITIONS_IMPORT_EXPORT_PARAMS *pExecPartImportParams = NULL; + RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL); + + // + // Delete any compute instances which are alive in system. This may delete + // instances existing in system even if they are same as default instance, + // as we are not comparing instances + // + for (CIIdx = 0; CIIdx < NV_ARRAY_ELEMENTS(pKernelMIGGpuInstance->MIGComputeInstance); ++CIIdx) + { + NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS params; + MIG_COMPUTE_INSTANCE *pMIGComputeInstance = + &pKernelMIGGpuInstance->MIGComputeInstance[CIIdx]; + + if (!pMIGComputeInstance->bValid) + continue; + + portMemSet(¶ms, 0, sizeof(params)); + params.execPartCount = 1; + params.execPartId[0] = CIIdx; + + // + // There is no revert or failure in this call as we have to do best case + // effort to delete and restore default compute instances + // + NV_ASSERT_OK( + pRmApi->Control(pRmApi, + pKernelMIGGpuInstance->instanceHandles.hClient, + pKernelMIGGpuInstance->instanceHandles.hSubscription, + NVC637_CTRL_CMD_EXEC_PARTITIONS_DELETE, + ¶ms, + sizeof(params))); + } + + // Restore all saved compute instances + pExecPartImportParams = portMemAllocNonPaged(sizeof(*pExecPartImportParams)); + NV_ASSERT_OR_RETURN(pExecPartImportParams != NULL, NV_ERR_NO_MEMORY); + + for (CIIdx = 0; CIIdx < NV_ARRAY_ELEMENTS(pKernelMIGGpuInstance->MIGComputeInstance); ++CIIdx) + { + GPUMGR_SAVE_COMPUTE_INSTANCE *pComputeInstanceSave = &pKernelHostVgpuDevice->savedExecPartitions[CIIdx]; + if (!pComputeInstanceSave->bValid) + continue; + + portMemSet(pExecPartImportParams, 0, sizeof(*pExecPartImportParams)); + pExecPartImportParams->id = pComputeInstanceSave->id; + pExecPartImportParams->bCreateCap = NV_TRUE; + portMemCopy(&pExecPartImportParams->info, sizeof(pExecPartImportParams->info), + &pComputeInstanceSave->ciInfo, sizeof(pComputeInstanceSave->ciInfo)); + + NV_ASSERT_OK_OR_GOTO(rmStatus, + pRmApi->Control(pRmApi, + pKernelMIGGpuInstance->instanceHandles.hClient, + pKernelMIGGpuInstance->instanceHandles.hSubscription, + NVC637_CTRL_CMD_EXEC_PARTITIONS_IMPORT, + pExecPartImportParams, + sizeof(*pExecPartImportParams)), + done); + } + + // + // Generate a subdevice event stating something has changed in GPU partition + // config. + // + gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_SMC_CONFIG_UPDATE, NULL, 0, 0, 0); + +done: + portMemFree(pExecPartImportParams); + return rmStatus; } diff --git a/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c b/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c index cd3d045b2a..c0dc139b23 100644 --- a/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c +++ b/src/nvidia/src/kernel/virtualization/vgpuconfigapi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2012-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -23,6 +23,20 @@ #include "virtualization/vgpuconfigapi.h" +#include "core/core.h" +#include "os/os.h" +#include "gpu/mem_mgr/mem_mgr.h" +#include "gpu/mem_sys/kern_mem_sys.h" +#include "gpu/mem_mgr/heap.h" +#include "kernel/gpu/fifo/kernel_sched_mgr.h" +#include "virtualization/kernel_vgpu_mgr.h" +#include "virtualization/hypervisor/hypervisor.h" +#include "rmapi/control.h" +#include "nv-hypervisor.h" +#include "ctrl/ctrla081.h" +#include "nvRmReg.h" +#include "kernel/gpu/fifo/kernel_fifo.h" + NV_STATUS vgpuconfigapiConstruct_IMPL ( @@ -31,7 +45,42 @@ vgpuconfigapiConstruct_IMPL RS_RES_ALLOC_PARAMS_INTERNAL *pParams ) { - return NV_ERR_NOT_SUPPORTED; + NvU32 i, pgpuIndex; + NV_STATUS rmStatus = NV_OK; + VGPU_CONFIG_EVENT_INFO_NODE *pVgpuConfigEventInfoNode = NULL; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvHandle hClient = pParams->hClient; + NvHandle hVgpuConfig = pParams->hResource; + + // Forbid allocation of this class on GSP-RM and Guest-RM + // to avoid fuzzing this class in such cases. See bug 3529160. + if (!RMCFG_FEATURE_KERNEL_RM || IS_VIRTUAL(pGpu)) + return NV_ERR_NOT_SUPPORTED; + + for (i = 0; i < NVA081_NOTIFIERS_MAXCOUNT; i++) + { + pVgpuConfigApi->notifyActions[i] = NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; + } + + // Add config event info to vgpuMgr DB + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pVgpuConfigEventInfoNode = listAppendNew(&(pKernelVgpuMgr->pgpuInfo[pgpuIndex].listVgpuConfigEventsHead)); + if (pVgpuConfigEventInfoNode != NULL) + { + portMemSet(pVgpuConfigEventInfoNode, 0, sizeof(VGPU_CONFIG_EVENT_INFO_NODE)); + + pVgpuConfigEventInfoNode->hVgpuConfig = hVgpuConfig; + pVgpuConfigEventInfoNode->hClient = hClient; + pVgpuConfigEventInfoNode->pVgpuConfigApi = pVgpuConfigApi; + } + + return rmStatus; } void @@ -40,6 +89,45 @@ vgpuconfigapiDestruct_IMPL VgpuConfigApi *pVgpuConfigApi ) { + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + VGPU_CONFIG_EVENT_INFO_NODE *pVgpuConfigEventInfoNode = NULL; + NvHandle hClient; + NvHandle hVgpuConfig; + NvU32 pgpuIndex; + CALL_CONTEXT *pCallContext; + RS_RES_FREE_PARAMS_INTERNAL *pParams; + + resGetFreeParams(staticCast(pVgpuConfigApi, RsResource), &pCallContext, &pParams); + hClient = pParams->hClient; + hVgpuConfig = pParams->hResource; + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex) != NV_OK) + { + pParams->status = NV_ERR_OBJECT_NOT_FOUND; + return; + } + + rmStatus = kvgpumgrGetConfigEventInfoFromDb(hClient, + hVgpuConfig, + &pVgpuConfigEventInfoNode, + pgpuIndex); + if (rmStatus != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to remove config event info from DB\n"); + NV_ASSERT(0); + pParams->status = rmStatus; + return; + } + else + { + listRemove(&(pKernelVgpuMgr->pgpuInfo[pgpuIndex].listVgpuConfigEventsHead), + pVgpuConfigEventInfoNode); + } + + pParams->status = rmStatus; } void @@ -49,6 +137,49 @@ CliNotifyVgpuConfigEvent NvU32 notifyIndex ) { + VGPU_CONFIG_EVENT_INFO_NODE *pVgpuConfigEventInfoNode = NULL; + PEVENTNOTIFICATION pEventNotification; + VgpuConfigApi *pVgpuConfigApi; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvU32 pgpuIndex; + + // Get pgpuIndex, for which we need to notify events + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex) != NV_OK) + return; + + for (pVgpuConfigEventInfoNode = listHead(&(pKernelVgpuMgr->pgpuInfo[pgpuIndex].listVgpuConfigEventsHead)); + pVgpuConfigEventInfoNode != NULL; + pVgpuConfigEventInfoNode = listNext(&(pKernelVgpuMgr->pgpuInfo[pgpuIndex].listVgpuConfigEventsHead), pVgpuConfigEventInfoNode)) + { + pVgpuConfigApi = pVgpuConfigEventInfoNode->pVgpuConfigApi; + if (pVgpuConfigApi->notifyActions[notifyIndex] == NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE) + { + continue; + } + + pEventNotification = inotifyGetNotificationList(staticCast(pVgpuConfigApi, INotifier)); + // ping all events on the list of type notifyIndex + while (pEventNotification) + { + if (pEventNotification->NotifyIndex == notifyIndex) + { + if (osNotifyEvent(pGpu, pEventNotification, 0, 0, 0) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "CliNotifyVgpuEvent: failed to deliver event 0x%x\n", + notifyIndex); + } + } + pEventNotification = pEventNotification->Next; + } + + // reset if single shot notify action + if (pVgpuConfigApi->notifyActions[notifyIndex] == NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE) + { + pVgpuConfigApi->notifyActions[notifyIndex] = NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE; + } + } } NV_STATUS @@ -58,7 +189,37 @@ vgpuconfigapiCtrlCmdVgpuConfigSetInfo_IMPL NVA081_CTRL_VGPU_CONFIG_INFO_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo = NULL; + NvU32 index; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &index)) != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to find pGpu info entry.\n"); + return rmStatus; + } + + pPhysGpuInfo = &pKernelVgpuMgr->pgpuInfo[index]; + + // Set vgpu config state + if (pPhysGpuInfo == NULL) + return NV_ERR_INVALID_STATE; + else + pPhysGpuInfo->vgpuConfigState = pParams->vgpuConfigState; + + rmStatus = kvgpumgrPgpuAddVgpuType(pGpu, pParams->discardVgpuTypes, &pParams->vgpuInfo); + if (rmStatus != NV_OK) + { + pPhysGpuInfo->vgpuConfigState = NVA081_CTRL_VGPU_CONFIG_STATE_UNINITIALIZED; + NV_PRINTF(LEVEL_ERROR, "Failed to add vGPU type to pGPU info.\n"); + return rmStatus; + } + + return rmStatus; } NV_STATUS @@ -68,7 +229,9 @@ vgpuconfigapiCtrlCmdVgpuConfigGetVgpuFbUsage_IMPL NVA081_CTRL_VGPU_CONFIG_GET_VGPU_FB_USAGE_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + + return kvgpumgrGetVgpuFbUsage(pGpu, pParams); } NV_STATUS @@ -78,7 +241,168 @@ vgpuconfigapiCtrlCmdVgpuConfigEnumerateVgpuPerPgpu_IMPL NVA081_CTRL_VGPU_CONFIG_ENUMERATE_VGPU_PER_PGPU_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + NVA081_VGPU_GUEST *pVgpuGuest; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice = NULL; + KERNEL_VGPU_GUEST *pVgpuGuestTmp = NULL; + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + NvU32 index[] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15}; + NvU32 i, j; + NV2080_CTRL_VGPU_MGR_INTERNAL_ENUMERATE_VGPU_PER_PGPU_PARAMS *pVgpuPerPgpuParams; + NV2080_VGPU_GUEST *pVgpuGuestGsp; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + // This structure can't be allocated on stack because it will result function stack usage > 4KB + pVgpuPerPgpuParams = portMemAllocNonPaged(sizeof(*pVgpuPerPgpuParams)); + if (pVgpuPerPgpuParams == NULL) + return NV_ERR_NO_MEMORY; + portMemSet(pVgpuPerPgpuParams, 0, sizeof(*pVgpuPerPgpuParams)); + + NV_ASSERT_OK_OR_GOTO(rmStatus, kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i), failed); + + NV_ASSERT_OK_OR_GOTO(rmStatus, kvgpumgrEnumerateVgpuPerPgpu(pGpu, pVgpuPerPgpuParams), failed); + + pPhysGpuInfo = &pKernelVgpuMgr->pgpuInfo[i]; + + if (pVgpuPerPgpuParams->numVgpu != pPhysGpuInfo->numActiveVgpu) + { + rmStatus = NV_ERR_INVALID_STATE; + goto failed; + } + + i = 0; + for (pKernelHostVgpuDevice = listHead(&(pPhysGpuInfo->listHostVgpuDeviceHead)); + pKernelHostVgpuDevice != NULL; + pKernelHostVgpuDevice = listNext(&(pPhysGpuInfo->listHostVgpuDeviceHead), pKernelHostVgpuDevice), i++) + { + pVgpuGuestTmp = pKernelHostVgpuDevice->vgpuGuest; + if (pVgpuGuestTmp == NULL) + { + rmStatus = NV_ERR_INVALID_STATE; + goto failed; + } + + if (i >= NV_ARRAY_ELEMENTS(pParams->vgpuGuest)) + { + rmStatus = NV_ERR_INSUFFICIENT_RESOURCES; + goto failed; + } + pVgpuGuest = &pParams->vgpuGuest[i]; + + portMemSet(pVgpuGuest->guestVmInfo.vmName, 0, NVA081_VM_NAME_SIZE); + portMemSet(pVgpuGuest->vgpuDevice.mdevUuid, 0, VGPU_UUID_SIZE); + + if (osIsVgpuVfioPresent() == NV_OK) + { + portMemCopy(pVgpuGuest->guestVmInfo.vmName, + NVA081_VM_NAME_SIZE, + pVgpuGuestTmp->guestVmInfo.vmName, + NVA081_VM_NAME_SIZE); + + if (pKernelHostVgpuDevice->pRequestVgpuInfoNode == NULL) + { + rmStatus = NV_ERR_INVALID_POINTER; + goto failed; + } + + /* + * SRIOV vGPUs using vfio-pci-core framework on KVM do not use MDEV framework, + * so don't expose MDEV UUID to NVML. + */ + if (!osIsVfioPciCorePresent() || !gpuIsSriovEnabled(pGpu)) + { + for (j = 0; j < VGPU_UUID_SIZE; j++) + pVgpuGuest->vgpuDevice.mdevUuid[j] = pKernelHostVgpuDevice->pRequestVgpuInfoNode->mdevUuid[index[j]]; + } + } + + // Copy VM's information + if (!IS_GSP_CLIENT(pGpu)) + { + pVgpuGuestGsp = &pVgpuPerPgpuParams->vgpuGuest[i]; + } + else + { + pVgpuGuestGsp = NULL; + for (j = 0; j < pVgpuPerPgpuParams->numVgpu; j++) + { + if (pVgpuPerPgpuParams->vgpuGuest[j].vgpuDevice.gfid == pKernelHostVgpuDevice->gfid) + { + pVgpuGuestGsp = &pVgpuPerPgpuParams->vgpuGuest[j]; + break; + } + } + if (pVgpuGuestGsp == NULL) + { + rmStatus = NV_ERR_OBJECT_NOT_FOUND; + goto failed; + } + } + + pVgpuGuest->guestVmInfo.vmPid = pVgpuGuestGsp->guestVmInfo.vmPid; + pVgpuGuest->guestVmInfo.guestOs = pVgpuGuestGsp->guestVmInfo.guestOs; + pVgpuGuest->guestVmInfo.migrationProhibited = pVgpuGuestGsp->guestVmInfo.migrationProhibited; + pVgpuGuest->guestVmInfo.guestNegotiatedVgpuVersion = pVgpuGuestGsp->guestVmInfo.guestNegotiatedVgpuVersion; + pVgpuGuest->guestVmInfo.licensed = pVgpuGuestGsp->guestVmInfo.licensed; + pVgpuGuest->guestVmInfo.licenseState = pVgpuGuestGsp->guestVmInfo.licenseState; + pVgpuGuest->guestVmInfo.guestVmInfoState = pVgpuGuestGsp->guestVmInfo.guestVmInfoState; + pVgpuGuest->guestVmInfo.licenseExpiryTimestamp = pVgpuGuestGsp->guestVmInfo.licenseExpiryTimestamp; + pVgpuGuest->guestVmInfo.licenseExpiryStatus = pVgpuGuestGsp->guestVmInfo.licenseExpiryStatus; + pVgpuGuest->guestVmInfo.frameRateLimit = pVgpuGuestGsp->guestVmInfo.frameRateLimit; + + portStringCopy((char *) pVgpuGuest->guestVmInfo.guestDriverVersion, + sizeof(pVgpuGuest->guestVmInfo.guestDriverVersion), + (char *) pVgpuGuestGsp->guestVmInfo.guestDriverVersion, + NVA081_VGPU_STRING_BUFFER_SIZE); + + portStringCopy((char *) pVgpuGuest->guestVmInfo.guestDriverBranch, + sizeof(pVgpuGuest->guestVmInfo.guestDriverBranch), + (char *) pVgpuGuestGsp->guestVmInfo.guestDriverBranch, + NVA081_VGPU_STRING_BUFFER_SIZE); + + pVgpuGuest->guestVmInfo.vmIdType = pVgpuGuestTmp->guestVmInfo.vmIdType; + if (pVgpuGuestTmp->guestVmInfo.vmIdType == VM_ID_DOMAIN_ID) + { + pVgpuGuest->guestVmInfo.guestVmId.vmId = pVgpuGuestTmp->guestVmInfo.guestVmId.vmId; + } + else if (pVgpuGuestTmp->guestVmInfo.vmIdType == VM_ID_UUID) + { + portMemCopy(pVgpuGuest->guestVmInfo.guestVmId.vmUuid, + NVA081_VM_UUID_SIZE, + pVgpuGuestTmp->guestVmInfo.guestVmId.vmUuid, + NVA081_VM_UUID_SIZE); + } + else + { + rmStatus = NV_ERR_INVALID_STATE; + goto failed; + } + + pVgpuGuest->vgpuDevice.vgpuType = pKernelHostVgpuDevice->vgpuType; + pVgpuGuest->vgpuDevice.vgpuDeviceInstanceId = pVgpuGuestGsp->vgpuDevice.vgpuDeviceInstanceId; + pVgpuGuest->vgpuDevice.encoderCapacity = pVgpuGuestGsp->vgpuDevice.encoderCapacity; + pVgpuGuest->vgpuDevice.fbUsed = pVgpuGuestGsp->vgpuDevice.fbUsed; + pVgpuGuest->vgpuDevice.swizzId = pKernelHostVgpuDevice->swizzId; + pVgpuGuest->vgpuDevice.eccState = pVgpuGuestGsp->vgpuDevice.eccState; + pVgpuGuest->vgpuDevice.bDriverLoaded = pVgpuGuestGsp->vgpuDevice.bDriverLoaded; + pVgpuGuest->vgpuDevice.placementId = pKernelHostVgpuDevice->placementId; + + portMemCopy(pVgpuGuest->vgpuDevice.vgpuUuid, VGPU_UUID_SIZE, pKernelHostVgpuDevice->vgpuUuid, VGPU_UUID_SIZE); + + pVgpuGuest->vgpuDevice.vgpuPciId = pVgpuGuestGsp->vgpuDevice.vgpuPciId; + } + + pParams->numVgpu = pPhysGpuInfo->numActiveVgpu; + pParams->vgpuType = NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE; // This field is unused on the client side. + // We should remove this field, unless it is required for compatibility reasons. + +failed: + portMemFree(pVgpuPerPgpuParams); + return rmStatus; } NV_STATUS @@ -88,7 +412,133 @@ vgpuconfigapiCtrlCmdVgpuConfigGetVgpuTypeInfo_IMPL NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPE_INFO_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + // This code should match hostvgpudeviceapiCtrlCmdGetVgpuTypeInfo + + VGPU_TYPE *vgpuTypeInfo; + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + NvU32 data = 0; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NvU8 shortGpuNameString[NV2080_GPU_MAX_NAME_STRING_LENGTH]; + NvU32 i; + NvU32 pgpuIndex; + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if ((rmStatus = kvgpumgrGetVgpuTypeInfo(pParams->vgpuType, &vgpuTypeInfo)) != NV_OK) + { + return rmStatus; + } + + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex)) != NV_OK) + return rmStatus; + + pPgpuInfo = &pKernelVgpuMgr->pgpuInfo[pgpuIndex]; + + pParams->vgpuTypeInfo.vgpuType = vgpuTypeInfo->vgpuTypeId; + pParams->vgpuTypeInfo.maxInstance = vgpuTypeInfo->maxInstance; + pParams->vgpuTypeInfo.numHeads = vgpuTypeInfo->numHeads; + pParams->vgpuTypeInfo.maxResolutionX = vgpuTypeInfo->maxResolutionX; + pParams->vgpuTypeInfo.maxResolutionY = vgpuTypeInfo->maxResolutionY; + pParams->vgpuTypeInfo.maxPixels = vgpuTypeInfo->maxPixels; + pParams->vgpuTypeInfo.frlConfig = vgpuTypeInfo->frlConfig; + pParams->vgpuTypeInfo.cudaEnabled = vgpuTypeInfo->cudaEnabled; + pParams->vgpuTypeInfo.eccSupported = vgpuTypeInfo->eccSupported; + pParams->vgpuTypeInfo.gpuInstanceSize = vgpuTypeInfo->gpuInstanceSize; + pParams->vgpuTypeInfo.vdevId = vgpuTypeInfo->vdevId; + pParams->vgpuTypeInfo.pdevId = vgpuTypeInfo->pdevId; + pParams->vgpuTypeInfo.profileSize = vgpuTypeInfo->profileSize; + pParams->vgpuTypeInfo.fbLength = vgpuTypeInfo->fbLength; + pParams->vgpuTypeInfo.gspHeapSize = vgpuTypeInfo->gspHeapSize; + pParams->vgpuTypeInfo.fbReservation = vgpuTypeInfo->fbReservation; + pParams->vgpuTypeInfo.mappableVideoSize = vgpuTypeInfo->mappableVideoSize; + pParams->vgpuTypeInfo.encoderCapacity = vgpuTypeInfo->encoderCapacity; + pParams->vgpuTypeInfo.bar1Length = vgpuTypeInfo->bar1Length; + pParams->vgpuTypeInfo.gpuDirectSupported = vgpuTypeInfo->gpuDirectSupported; + pParams->vgpuTypeInfo.nvlinkP2PSupported = vgpuTypeInfo->nvlinkP2PSupported; + pParams->vgpuTypeInfo.multiVgpuExclusive = vgpuTypeInfo->multiVgpuExclusive; + pParams->vgpuTypeInfo.frlEnable = vgpuTypeInfo->frlEnable; + pParams->vgpuTypeInfo.multiVgpuSupported = vgpuTypeInfo->multiVgpuSupported; + + /* Represents vGPU type level support for heterogeneous timeslice profiles */ + pParams->vgpuTypeInfo.exclusiveType = !kvgpumgrIsHeterogeneousVgpuSupported(); + + /* + * Represents vGPU type level support for heterogenenous timeslice size. + * Currently, if a pGpu supports heterogenenous timeslice size, all vGPU + * types support it. Set to false if supported + */ + pParams->vgpuTypeInfo.exclusiveSize = !pPgpuInfo->heterogeneousTimesliceSizesSupported; + + // Disable FRL if we are using sched_sw (PVMRL) in timesliced mode + if (IsPASCALorBetter(pGpu)) + { + KernelSchedMgr *pKernelSchedMgr = GPU_GET_KERNEL_SCHEDMGR(pGpu); + if (pKernelSchedMgr && + kschedmgrIsPvmrlEnabled(pKernelSchedMgr)) + { + pParams->vgpuTypeInfo.frlEnable = 0; + } + } + + portStringCopy((char *) pParams->vgpuTypeInfo.vgpuName, sizeof(pParams->vgpuTypeInfo.vgpuName), (char *) vgpuTypeInfo->vgpuName, VGPU_STRING_BUFFER_SIZE); + portStringCopy((char *) pParams->vgpuTypeInfo.vgpuClass, sizeof(pParams->vgpuTypeInfo.vgpuClass), (char *) vgpuTypeInfo->vgpuClass, VGPU_STRING_BUFFER_SIZE); + portStringCopy((char *) pParams->vgpuTypeInfo.license, sizeof(pParams->vgpuTypeInfo.license), (char *) vgpuTypeInfo->license, NV_GRID_LICENSE_INFO_MAX_LENGTH); + portStringCopy((char *) pParams->vgpuTypeInfo.vgpuExtraParams, sizeof(pParams->vgpuTypeInfo.vgpuExtraParams), (char *) vgpuTypeInfo->vgpuExtraParams, + sizeof(pParams->vgpuTypeInfo.vgpuExtraParams)); + portStringCopy((char *) pParams->vgpuTypeInfo.licensedProductName, sizeof(pParams->vgpuTypeInfo.licensedProductName), (char *) vgpuTypeInfo->licensedProductName, + NV_GRID_LICENSE_INFO_MAX_LENGTH); + + if (NV_OK == osReadRegistryDword(pGpu, NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER, &data)) + { + if (data == NV_REG_STR_RM_ENABLE_PLUGIN_IN_FTRACE_BUFFER_ENABLED) + pParams->vgpuTypeInfo.ftraceEnable = data; + } + + rmStatus = gpuGetShortNameString(pGpu, (void *)shortGpuNameString); + if (rmStatus != NV_OK) + return rmStatus; + + portMemCopy(pParams->vgpuTypeInfo.shortGpuNameString, sizeof(shortGpuNameString), shortGpuNameString, sizeof(shortGpuNameString)); + + portStringCopy((char *) pParams->vgpuTypeInfo.adapterName, sizeof(pParams->vgpuTypeInfo.adapterName), + (char *) vgpuTypeInfo->vgpuName, VGPU_STRING_BUFFER_SIZE); + portStringCopy((char *) pParams->vgpuTypeInfo.adapterName_Unicode, sizeof(pParams->vgpuTypeInfo.adapterName_Unicode), + (char *) vgpuTypeInfo->vgpuName, VGPU_STRING_BUFFER_SIZE); + + portStringConvertAsciiToUtf16(pParams->vgpuTypeInfo.adapterName_Unicode, VGPU_STRING_BUFFER_SIZE, + (char *)pParams->vgpuTypeInfo.adapterName_Unicode, VGPU_STRING_BUFFER_SIZE); + + // used only by NVML + if (vgpuTypeInfo->gpuInstanceSize != 0) + { + NV_ASSERT_OK_OR_RETURN( + kvgpumgrGetPartitionFlag(vgpuTypeInfo->vgpuTypeId, &pParams->vgpuTypeInfo.gpuInstanceProfileId)); + } + else + { + pParams->vgpuTypeInfo.gpuInstanceProfileId = PARTITIONID_INVALID; + } + + if (pPgpuInfo->heterogeneousTimesliceSizesSupported == NV_TRUE) + { + pParams->vgpuTypeInfo.placementSize = vgpuTypeInfo->placementSize; + pParams->vgpuTypeInfo.placementCount = vgpuTypeInfo->placementCount; + + for (i = 0; i < vgpuTypeInfo->placementCount; i++) + { + pParams->vgpuTypeInfo.placementIds[i] = vgpuTypeInfo->supportedPlacementIds[i]; + } + } + else + { + pParams->vgpuTypeInfo.placementSize = 0; + pParams->vgpuTypeInfo.placementCount = 0; + } + + return rmStatus; } NV_STATUS @@ -98,7 +548,34 @@ vgpuconfigapiCtrlCmdVgpuConfigGetSupportedVgpuTypes_IMPL NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + NvU32 pgpuIndex, i; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPgpuInfo; + NV_STATUS rmStatus = NV_OK; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (pGpu == NULL || + !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU)) + { + return NV_ERR_NOT_SUPPORTED; + } + + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex)) != NV_OK) + return rmStatus; + + pPgpuInfo = &pKernelVgpuMgr->pgpuInfo[pgpuIndex]; + + pParams->vgpuConfigState = pPgpuInfo->vgpuConfigState; + pParams->numVgpuTypes = pPgpuInfo->numVgpuTypes; + for (i = 0; i < pPgpuInfo->numVgpuTypes; i++) + { + pParams->vgpuTypes[i] = pPgpuInfo->vgpuTypes[i]->vgpuTypeId; + } + + return rmStatus; } NV_STATUS @@ -108,7 +585,27 @@ vgpuconfigapiCtrlCmdVgpuConfigGetCreatableVgpuTypes_IMPL NVA081_CTRL_VGPU_CONFIG_GET_VGPU_TYPES_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + NvU32 pgpuIndex; + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (pGpu == NULL || + !pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VIRTUALIZATION_MODE_HOST_VGPU)) + { + return NV_ERR_NOT_SUPPORTED; + } + + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex)) != NV_OK) + return rmStatus; + + rmStatus = kvgpumgrGetCreatableVgpuTypes(pGpu, pKernelVgpuMgr, pgpuIndex, + &pParams->numVgpuTypes, pParams->vgpuTypes); + + return rmStatus; } NV_STATUS @@ -118,7 +615,75 @@ vgpuconfigapiCtrlCmdVgpuConfigEventSetNotification_IMPL NVA081_CTRL_VGPU_CONFIG_EVENT_SET_NOTIFICATION_PARAMS *pSetEventParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pVgpuConfigApi); + NvHandle hObject = RES_GET_HANDLE(pVgpuConfigApi); + VGPU_CONFIG_EVENT_INFO_NODE *pVgpuConfigEventInfoNode = NULL; + VgpuConfigApi *pVgpuConfigInfo; + NV_STATUS rmStatus = NV_OK; + NvU32 pgpuIndex; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (pSetEventParams->event >= NVA081_NOTIFIERS_MAXCOUNT) + { + NV_PRINTF(LEVEL_INFO, "Bad event 0x%x\n", pSetEventParams->event); + return NV_ERR_INVALID_ARGUMENT; + } + + if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex)) != NV_OK) + return rmStatus; + + rmStatus = kvgpumgrGetConfigEventInfoFromDb(hClient, + hObject, + &pVgpuConfigEventInfoNode, + pgpuIndex); + if (rmStatus != NV_OK || pVgpuConfigEventInfoNode == NULL) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to find config event info for %x from DB\n", + hClient); + return rmStatus; + } + pVgpuConfigInfo = pVgpuConfigEventInfoNode->pVgpuConfigApi; + + if (inotifyGetNotificationList(staticCast(pVgpuConfigInfo, INotifier)) == NULL) + { + NV_PRINTF(LEVEL_INFO, "Cmd 0x%x: no event list\n", + NVA081_CTRL_CMD_VGPU_CONFIG_EVENT_SET_NOTIFICATION); + return NV_ERR_INVALID_STATE; + } + + switch (pSetEventParams->action) + { + case NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE: + case NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT: + { + // must be in disabled state to transition to an active state + if (pVgpuConfigInfo->notifyActions[pSetEventParams->event] != NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE) + { + rmStatus = NV_ERR_INVALID_STATE; + break; + } + pVgpuConfigInfo->notifyActions[pSetEventParams->event] = pSetEventParams->action; + break; + } + + case NVA081_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE: + { + pVgpuConfigInfo->notifyActions[pSetEventParams->event] = pSetEventParams->action; + break; + } + default: + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + } + + return rmStatus; } NV_STATUS @@ -128,16 +693,160 @@ vgpuconfigapiCtrlCmdVgpuConfigNotifyStart_IMPL NVA081_CTRL_VGPU_CONFIG_NOTIFY_START_PARAMS *pNotifyParams ) { + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + KERNEL_HOST_VGPU_DEVICE *pKernelHostVgpuDevice; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + for (pRequestVgpu = listHead(&pKernelVgpuMgr->listRequestVgpuHead); + pRequestVgpu != NULL; + pRequestVgpu = listNext(&pKernelVgpuMgr->listRequestVgpuHead, pRequestVgpu)) + { + if (portMemCmp(pNotifyParams->mdevUuid, pRequestVgpu->mdevUuid, VGPU_UUID_SIZE) == 0) + { + if (pRequestVgpu->returnStatus && pRequestVgpu->waitQueue) + { + *pRequestVgpu->returnStatus = pNotifyParams->returnStatus; + portStringCopy((char *)pRequestVgpu->vmName, NVA081_VM_NAME_SIZE, + (const char *)pNotifyParams->vmName, NVA081_VM_NAME_SIZE); + if (pNotifyParams->returnStatus == NV_OK) + { + pKernelHostVgpuDevice = pRequestVgpu->pKernelHostVgpuDevice; + + if (pKernelHostVgpuDevice == NULL) + { + *pRequestVgpu->returnStatus = NV_ERR_INVALID_STATE; + return NV_ERR_INVALID_STATE; + } + portStringCopy((char *)pKernelHostVgpuDevice->vgpuGuest->guestVmInfo.vmName, + sizeof(pKernelHostVgpuDevice->vgpuGuest->guestVmInfo.vmName), + (const char *)pNotifyParams->vmName, + sizeof(pNotifyParams->vmName)); + } + osVgpuVfioWake(pRequestVgpu->waitQueue); + return NV_OK; + } + return NV_ERR_INVALID_STATE; + } + } return NV_ERR_OBJECT_NOT_FOUND; } NV_STATUS -vgpuconfigapiCtrlCmdVgpuConfigMdevRegister_IMPL +vgpuconfigapiCtrlCmdVgpuConfigGetCreatablePlacements_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_GET_CREATABLE_PLACEMENTS_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + NV_STATUS rmStatus = NV_OK; + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + VGPU_TYPE *pVgpuTypeInfo; + NvU32 pgpuIndex; + NvU32 i, j, count = 0; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (pGpu == NULL || (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE))) + { + return NV_ERR_NOT_SUPPORTED; + } + + NV_CHECK_OK_OR_RETURN(LEVEL_ERROR, kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &pgpuIndex)); + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[pgpuIndex]); + + for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++) + { + pVgpuTypeInfo = pPhysGpuInfo->vgpuTypes[i]; + if (pParams->vgpuTypeId == pVgpuTypeInfo->vgpuTypeId) + { + for (j = 0; j < pVgpuTypeInfo->placementCount; j++) + { + if (pPhysGpuInfo->creatablePlacementIds[i][j] != NVA081_PLACEMENT_ID_INVALID) + { + pParams->placementIds[count] = pPhysGpuInfo->creatablePlacementIds[i][j]; + count++; + } + } + pParams->placementSize = pVgpuTypeInfo->placementSize; + pParams->count = count; + break; + } + } + + return rmStatus; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigSetCapability_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS *pSetCapabilityParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 i; + NV_STATUS rmStatus = NV_OK; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + + switch (pSetCapabilityParams->capability) + { + case NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU: + { + pPhysGpuInfo->miniQuarterEnabled = pSetCapabilityParams->state; + break; + } + + default: + { + rmStatus = NV_ERR_INVALID_ARGUMENT; + break; + } + } + + return rmStatus; +} + +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigUpdatePgpuInfo_IMPL ( VgpuConfigApi *pVgpuConfigApi ) { - return NV_ERR_NOT_SUPPORTED; + NV_STATUS rmStatus = NV_OK; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + + if (pGpu != NULL) + { + rmStatus = kvgpumgrSetSupportedPlacementIds(pGpu); + if (rmStatus != NV_OK) + return rmStatus; + + rmStatus = osVgpuRegisterMdev(pGpu->pOsGpuInfo); + if (rmStatus == NV_ERR_NOT_SUPPORTED) + return NV_OK; + } + else + rmStatus = NV_ERR_INVALID_STATE; + + return rmStatus; } NV_STATUS @@ -147,7 +856,9 @@ vgpuconfigapiCtrlCmdVgpuConfigSetVgpuInstanceEncoderCapacity_IMPL NVA081_CTRL_VGPU_CONFIG_VGPU_INSTANCE_ENCODER_CAPACITY_PARAMS *pEncoderParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + + return kvgpumgrSetVgpuEncoderCapacity(pGpu, pEncoderParams->vgpuUuid, pEncoderParams->encoderCapacity); } NV_STATUS @@ -157,7 +868,45 @@ vgpuconfigapiCtrlCmdVgpuConfigGetMigrationCap_IMPL NVA081_CTRL_CMD_VGPU_CONFIG_GET_MIGRATION_CAP_PARAMS *pMigrationCapParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + NvU32 data = 0; + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (pHypervisor == NULL) + return NV_ERR_INVALID_REQUEST; + + if (pGpu == NULL) + return NV_ERR_INVALID_STATE; + + if (osIsVgpuVfioPresent() == NV_OK) + { + if (NV_OK == osReadRegistryDword(pGpu, + NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION, + &data)) + { + if (data == NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_FALSE) + { + pMigrationCapParams->bMigrationCap = NV_FALSE; + } + else + { + pMigrationCapParams->bMigrationCap = kvgpumgrCheckPgpuMigrationSupport(pGpu); + } + } + else // Regkey isn't set explicitly, check for default value + { + pMigrationCapParams->bMigrationCap = ((NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_DEFAULT == + NV_REG_STR_RM_ENABLE_KVM_VGPU_MIGRATION_TRUE) && + kvgpumgrCheckPgpuMigrationSupport(pGpu)); + } + } + else + pMigrationCapParams->bMigrationCap = kvgpumgrCheckPgpuMigrationSupport(pGpu); + + return NV_OK; } NV_STATUS @@ -167,7 +916,98 @@ vgpuconfigapiCtrlCmdVgpuConfigGetPgpuMetadataString_IMPL NVA081_CTRL_VGPU_CONFIG_GET_PGPU_METADATA_STRING_PARAMS *pGpuMetadataStringParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + NvU32 written_bytes = 0; + NvU32 total_written_bytes = 0; + NvBool pgpuMigrationCap = NV_FALSE; + NvU8 *pGidString = NULL; + NvU32 flags = 0; + NvU32 gidStrlen; + NV_STATUS rmStatus = NV_OK; + + if (pHypervisor == NULL) + return NV_ERR_INVALID_REQUEST; + + if (pGpu == NULL) + return NV_ERR_INVALID_STATE; + + portMemSet(pGpuMetadataStringParams->pGpuString, 0, + NVA081_PGPU_METADATA_STRING_SIZE); + + pgpuMigrationCap = kvgpumgrCheckPgpuMigrationSupport(pGpu); + + if (pgpuMigrationCap == NV_FALSE) + { + // Bug 2063867 + // For migration unsupported GPUs, get the GPU's UUID + // and save it in the string. + // To perform offline compatibility checks for vGPU migration, + // when the strings are compared, there is mismatch and migration + // can be avoided for these migration unsupported GPUs. + rmStatus = gpuGetGidInfo(pGpu, &pGidString, &gidStrlen, flags); + if (rmStatus != NV_OK) + return rmStatus; + + if (NVA081_PGPU_METADATA_STRING_SIZE >= gidStrlen) + { + portMemCopy(pGpuMetadataStringParams->pGpuString, gidStrlen, pGidString, gidStrlen); + } + else + { + rmStatus = NV_ERR_INSUFFICIENT_RESOURCES; + portMemFree(pGidString); + return rmStatus; + } + portMemFree(pGidString); + } + else + { + written_bytes = kvgpumgrGetPgpuDevIdEncoding(pGpu, + pGpuMetadataStringParams->pGpuString, + NVA081_PGPU_METADATA_STRING_SIZE); + + if (written_bytes == NV_U32_MAX) + return NV_ERR_INSUFFICIENT_RESOURCES; + total_written_bytes += written_bytes; + + written_bytes = kvgpumgrGetPgpuSubdevIdEncoding(pGpu, + pGpuMetadataStringParams->pGpuString + total_written_bytes, + NVA081_PGPU_METADATA_STRING_SIZE - total_written_bytes); + + if (written_bytes == NV_U32_MAX) + return NV_ERR_INSUFFICIENT_RESOURCES; + total_written_bytes += written_bytes; + + + /* + * Dynamic Floor Sweeping support for hopper+ allows migration on GPUs + * with different floor sweep. Floor sweep info encoding for checking + * migration capability is not needed hopper+. + */ + if (!IsdHOPPERorBetter(pGpu)) + { + written_bytes = kvgpumgrGetPgpuFSEncoding(pGpu, + pGpuMetadataStringParams->pGpuString + total_written_bytes, + NVA081_PGPU_METADATA_STRING_SIZE - total_written_bytes); + + if (written_bytes == NV_U32_MAX) + return NV_ERR_INSUFFICIENT_RESOURCES; + total_written_bytes += written_bytes; + } + + + written_bytes = kvgpumgrGetPgpuCapEncoding(pGpu, + pGpuMetadataStringParams->pGpuString + total_written_bytes, + NVA081_PGPU_METADATA_STRING_SIZE - total_written_bytes); + + if (written_bytes == NV_U32_MAX) + return NV_ERR_INSUFFICIENT_RESOURCES; + total_written_bytes += written_bytes; + } + + return NV_OK; } NV_STATUS @@ -177,7 +1017,27 @@ vgpuconfigapiCtrlCmdVgpuConfigGetHostFbReservation_IMPL NVA081_CTRL_VGPU_CONFIG_GET_HOST_FB_RESERVATION_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); + + NV_PRINTF(LEVEL_INFO, "%s\n", __FUNCTION__); + + if (pParams->vgpuTypeId == NVA081_CTRL_VGPU_CONFIG_INVALID_TYPE) + { + pParams->hostReservedFb = 0; + pParams->eccAndPrReservedFb = 0; + pParams->totalReservedFb = 0; + + return NV_ERR_INVALID_ARGUMENT; + } + + pParams->hostReservedFb = memmgrGetVgpuHostRmReservedFb_HAL(pGpu, pMemoryManager, pParams->vgpuTypeId); + + pParams->eccAndPrReservedFb = kvgpumgrGetEccAndPrReservedFb(pGpu); + + pParams->totalReservedFb = pParams->hostReservedFb + pParams->eccAndPrReservedFb; + + return NV_OK; } NV_STATUS @@ -198,7 +1058,53 @@ vgpuconfigapiCtrlCmdVgpuConfigGetFreeSwizzId_IMPL NVA081_CTRL_VGPU_CONFIG_GET_FREE_SWIZZID_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + REQUEST_VGPU_INFO_NODE *pRequestVgpu = NULL; + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 i; + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + + NV_CHECK_OR_RETURN(LEVEL_INFO, + IS_MIG_IN_USE(pGpu), + NV_ERR_INVALID_OPERATION); + + if (osIsVgpuVfioPresent() == NV_OK) + { + for (pRequestVgpu = listHead(&pKernelVgpuMgr->listRequestVgpuHead); + pRequestVgpu != NULL; + pRequestVgpu = listNext(&pKernelVgpuMgr->listRequestVgpuHead, pRequestVgpu)) + { + if (pRequestVgpu->deviceState == NV_VGPU_DEV_OPENED && + pRequestVgpu->gpuPciId == pParams->gpuPciId) + break; + } + if (pRequestVgpu == NULL) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pParams->swizzId = pRequestVgpu->swizzId; + } + else + { + NvU32 partitionFlag = PARTITIONID_INVALID; + + NV_ASSERT_OK_OR_RETURN( + kvgpumgrGetPartitionFlag(pParams->vgpuTypeId, &partitionFlag)); + + NV_ASSERT_OK_OR_RETURN( + kvgpumgrGetSwizzId(pGpu, pPhysGpuInfo, partitionFlag, &pParams->swizzId)); + } + + return NV_OK; } NV_STATUS @@ -208,7 +1114,45 @@ vgpuconfigapiCtrlCmdPgpuGetMultiVgpuSupportInfo_IMPL NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 i; + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + pParams->fractionalmultiVgpuSupported = pPhysGpuInfo->fractionalMultiVgpu; + + // We are not currently limiting the feature based on the pgpu. + // Return the system level value here. + pParams->heterogeneousTimesliceProfilesSupported = kvgpumgrIsHeterogeneousVgpuSupported(); + + pParams->heterogeneousTimesliceSizesSupported = pPhysGpuInfo->heterogeneousTimesliceSizesSupported; + + return NV_OK; +} + +NV_STATUS +vgpuconfigapiCtrlCmdPgpuGetVgpuStreamingCapability_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + pParams->streamingCapability = NV_FALSE; + + if (gpuIsSriovEnabled(pGpu)) + { + pParams->streamingCapability = NV_TRUE; + } + + return NV_OK; } NV_STATUS @@ -218,8 +1162,8 @@ vgpuconfigapiCtrlCmdGetVgpuDriversCaps_IMPL NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS *pParams ) { - pParams->heterogeneousMultiVgpuSupported = NV_FALSE; - return NV_ERR_NOT_SUPPORTED; + pParams->heterogeneousMultiVgpuSupported = kvgpumgrIsHeterogeneousVgpuSupported(); + return NV_OK; } NV_STATUS @@ -229,7 +1173,21 @@ vgpuconfigapiCtrlCmdVgpuConfigSetPgpuInfo_IMPL NVA081_CTRL_VGPU_CONFIG_SET_PGPU_INFO_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys); + KERNEL_PHYS_GPU_INFO *pPhysGpuInfo; + NvU32 i; + + if (kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pGpu->gpuId, &i) != NV_OK) + { + return NV_ERR_OBJECT_NOT_FOUND; + } + + pPhysGpuInfo = &(pKernelVgpuMgr->pgpuInfo[i]); + pPhysGpuInfo->fractionalMultiVgpu = pParams->fractionalMultiVgpu; + + return NV_OK; } NV_STATUS @@ -239,6 +1197,47 @@ vgpuconfigapiCtrlCmdVgpuConfigValidateSwizzId_IMPL NVA081_CTRL_VGPU_CONFIG_VALIDATE_SWIZZID_PARAMS *pParams ) { - return NV_ERR_NOT_SUPPORTED; + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + + NV_CHECK_OR_RETURN(LEVEL_INFO, + IS_MIG_IN_USE(pGpu), + NV_ERR_INVALID_OPERATION); + + NV_ASSERT_OK_OR_RETURN( + kvgpumgrValidateSwizzId(pGpu, pParams->vgpuTypeId, pParams->swizzId)); + + return NV_OK; } +NV_STATUS +vgpuconfigapiCtrlCmdVgpuConfigUpdateHeterogeneousInfo_IMPL +( + VgpuConfigApi *pVgpuConfigApi, + NVA081_CTRL_VGPU_CONFIG_UPDATE_HETEROGENEOUS_INFO_PARAMS *pParams +) +{ + OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuConfigApi); + NV_STATUS rmStatus = NV_OK; + + if (pGpu == NULL) + return NV_ERR_INVALID_STATE; + + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_VGPU_HETEROGENEOUS_MODE)) + { + pParams->isHeterogeneousEnabled = NV_FALSE; + pParams->placementId = NVA081_PLACEMENT_ID_INVALID; + return NV_OK; + } + + pParams->isHeterogeneousEnabled = NV_TRUE; + + rmStatus = kvgpumgrUpdateHeterogeneousInfo(pGpu, pParams->vgpuTypeId, + &pParams->placementId, + &pParams->guestFbLength, + &pParams->guestFbOffset, + &pParams->gspHeapOffset); + if (rmStatus != NV_OK) + return rmStatus; + + return NV_OK; +} diff --git a/src/nvidia/src/lib/protobuf/prbutil.c b/src/nvidia/src/lib/protobuf/prbutil.c index b9908a826a..4ca8b88f53 100644 --- a/src/nvidia/src/lib/protobuf/prbutil.c +++ b/src/nvidia/src/lib/protobuf/prbutil.c @@ -40,7 +40,7 @@ */ NV_STATUS -prbEncGpuRegs(POBJGPU pGpu, IoAperture *pAperture, NvU64 offset, NvU32 numRegs, +prbEncGpuRegs(OBJGPU *pGpu, IoAperture *pAperture, NvU64 offset, NvU32 numRegs, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status; @@ -94,7 +94,7 @@ prbEncGpuRegs(POBJGPU pGpu, IoAperture *pAperture, NvU64 offset, NvU32 numRegs, */ NV_STATUS -prbEncGpuRegImm(POBJGPU pGpu, NvU64 offset, NvU32 reg, +prbEncGpuRegImm(OBJGPU *pGpu, NvU64 offset, NvU32 reg, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status; @@ -137,7 +137,7 @@ prbEncGpuRegImm(POBJGPU pGpu, NvU64 offset, NvU32 reg, */ NV_STATUS -prbEncGpuRegSliceTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, +prbEncGpuRegSliceTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status = NV_OK; // Init keeps the Mac compiler quiet @@ -228,7 +228,7 @@ prbEncGpuRegSliceTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABL */ NV_STATUS -prbEncGpuRegSliceIndexedTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, +prbEncGpuRegSliceIndexedTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_INDEXED_TABLE *pTbl, NvU32 numEntries, NvU32 base, NvU32 index, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status = NV_OK; // Init keeps the Mac compiler quiet @@ -316,7 +316,7 @@ prbEncGpuRegSliceIndexedTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_R */ NV_STATUS -prbEncGpuRegSliceOffset(POBJGPU pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, +prbEncGpuRegSliceOffset(OBJGPU *pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, NvU32 base, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *pFieldDesc) { NV_STATUS status = NV_OK; // if numEntries == 0 @@ -388,7 +388,7 @@ prbEncGpuRegSliceOffset(POBJGPU pGpu, IoAperture *pAperture, const NvU32 *pOffse */ NV_STATUS -prbEncGpuRegOffset(POBJGPU pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, +prbEncGpuRegOffset(OBJGPU *pGpu, IoAperture *pAperture, const NvU32 *pOffset, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *pFieldDesc) { return prbEncGpuRegSliceOffset(pGpu, pAperture, pOffset, numEntries, 0, pPrbEnc, pFieldDesc); @@ -406,7 +406,7 @@ prbEncGpuRegOffset(POBJGPU pGpu, IoAperture *pAperture, const NvU32 *pOffset, Nv */ NV_STATUS -prbEncGpuRegTbl(POBJGPU pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, +prbEncGpuRegTbl(OBJGPU *pGpu, IoAperture *pAperture, const PRB_GPU_REG_TABLE *pTbl, NvU32 numEntries, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { return prbEncGpuRegSliceTbl(pGpu, pAperture, pTbl, numEntries, 0, pPrbEnc, fieldDesc); @@ -564,7 +564,7 @@ prbEncMem(NvU64 offset, NvU32 numRegs, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DES */ NV_STATUS -prbEncPciConfigRegs(POBJGPU pGpu, NvU64 index, NvU32 numRegs, +prbEncPciConfigRegs(OBJGPU *pGpu, NvU64 index, NvU32 numRegs, PRB_ENCODER *pPrbEnc, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status; @@ -651,7 +651,7 @@ prbEncPciReadDword(void *handle, NvU64 offset, */ NV_STATUS -prbEncGenExData(PRB_ENCODER *pPrbEnc, POBJGPU pGpu, NvU32 chId, const PRB_FIELD_DESC *fieldDesc) +prbEncGenExData(PRB_ENCODER *pPrbEnc, OBJGPU *pGpu, NvU32 chId, const PRB_FIELD_DESC *fieldDesc) { NV_STATUS status; NV_STATUS statusEnd; diff --git a/src/nvidia/src/lib/ref_count.c b/src/nvidia/src/lib/ref_count.c index de41892c4e..b4dffa27ac 100644 --- a/src/nvidia/src/lib/ref_count.c +++ b/src/nvidia/src/lib/ref_count.c @@ -25,11 +25,11 @@ #include "lib/ref_count.h" #include "os/os.h" -static NV_STATUS _refcntReleaseReferences (POBJREFCNT, NvU64, NvBool, +static NV_STATUS _refcntReleaseReferences (OBJREFCNT *, NvU64, NvBool, NvBool, NvBool*); -static NV_STATUS _refcntInvokeStateChangeCallback(POBJREFCNT, REFCNT_STATE, +static NV_STATUS _refcntInvokeStateChangeCallback(OBJREFCNT *, REFCNT_STATE, REFCNT_STATE); -static void _refcntInvokeResetCallback (POBJREFCNT, NvU64); +static void _refcntInvokeResetCallback (OBJREFCNT *, NvU64); /*! * @brief Construct the reference counter according to the parameters. @@ -52,7 +52,7 @@ static void _refcntInvokeResetCallback (POBJREFCNT, NvU64); NV_STATUS refcntConstruct_IMPL ( - POBJREFCNT pRefcnt, + OBJREFCNT *pRefcnt, Dynamic *pParent, NvU32 tag, RefcntStateChangeCallback *pStateChangeCallback, @@ -77,7 +77,7 @@ refcntConstruct_IMPL void refcntDestruct_IMPL ( - POBJREFCNT pRefcnt + OBJREFCNT *pRefcnt ) { @@ -118,7 +118,7 @@ refcntDestruct_IMPL NV_STATUS refcntRequestReference_IMPL ( - POBJREFCNT pRefcnt, + OBJREFCNT *pRefcnt, NvU64 requesterId, NvU32 requestedState, NvBool bForce @@ -279,7 +279,7 @@ refcntRequestReference_IMPL NV_STATUS refcntReleaseReferences_IMPL ( - POBJREFCNT pRefcnt, + OBJREFCNT *pRefcnt, NvU64 requesterId, NvBool bReleaseAllRequests ) @@ -315,7 +315,7 @@ refcntReleaseReferences_IMPL NV_STATUS refcntReset_IMPL ( - POBJREFCNT pRefcnt, + OBJREFCNT *pRefcnt, NvBool bForceCallback ) { @@ -429,7 +429,7 @@ refcntReset_IMPL static NV_STATUS _refcntReleaseReferences ( - POBJREFCNT pRefcnt, + OBJREFCNT *pRefcnt, NvU64 requesterId, NvBool bReleaseAllRequests, NvBool bSuppressStateChange, @@ -546,7 +546,7 @@ _refcntReleaseReferences static NV_STATUS _refcntInvokeStateChangeCallback ( - POBJREFCNT pRefcnt, + OBJREFCNT *pRefcnt, REFCNT_STATE prevState, REFCNT_STATE newState ) @@ -571,7 +571,7 @@ _refcntInvokeStateChangeCallback static void _refcntInvokeResetCallback ( - POBJREFCNT pRefcnt, + OBJREFCNT *pRefcnt, NvU64 requesterId ) { diff --git a/src/nvidia/src/libraries/containers/eheap/eheap_old.c b/src/nvidia/src/libraries/containers/eheap/eheap_old.c index 351aba6489..745016ed7c 100644 --- a/src/nvidia/src/libraries/containers/eheap/eheap_old.c +++ b/src/nvidia/src/libraries/containers/eheap/eheap_old.c @@ -33,27 +33,27 @@ #include "os/os.h" #endif -static void initPublicObjectFunctionPointers_EHeap(POBJEHEAP pHeap); -static NV_STATUS eheapInit(POBJEHEAP, NvU64, NvU64, NvU32, NvU32); -static NV_STATUS eheapDestruct(POBJEHEAP); -static NV_STATUS eheapAlloc(POBJEHEAP, NvU32, NvU32 *, NvU64 *, NvU64 *,NvU64, NvU64, PEMEMBLOCK*, void*, EHeapOwnershipComparator*); -static NV_STATUS eheapFree(POBJEHEAP, NvU64); -static void eheapInfo(POBJEHEAP, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *, NvU64 *); -static void eheapInfoForRange(POBJEHEAP, NV_RANGE, NvU64 *, NvU64 *, NvU32 *, NvU64 *); -static NV_STATUS eheapGetSize(POBJEHEAP, NvU64 *); -static NV_STATUS eheapGetFree(POBJEHEAP, NvU64 *); -static NV_STATUS eheapGetBase(POBJEHEAP, NvU64 *); -static PEMEMBLOCK eheapGetBlock(POBJEHEAP, NvU64, NvBool); -static NV_STATUS eheapSetAllocRange(POBJEHEAP, NvU64, NvU64); -static NV_STATUS eheapTraverse(POBJEHEAP, void *, EHeapTraversalFn, NvS32); -static NV_STATUS _eheapBlockFree(POBJEHEAP pHeap, PEMEMBLOCK block); -static NvU32 eheapGetNumBlocks(POBJEHEAP); -static NV_STATUS eheapGetBlockInfo(POBJEHEAP, NvU32, NVOS32_HEAP_DUMP_BLOCK *); -static NV_STATUS eheapSetOwnerIsolation(POBJEHEAP, NvBool, NvU32); -static NvBool _eheapCheckOwnership(POBJEHEAP, void*, NvU64, NvU64, PEMEMBLOCK, EHeapOwnershipComparator*); +static void initPublicObjectFunctionPointers_EHeap(OBJEHEAP *pHeap); +static NV_STATUS eheapInit(OBJEHEAP *, NvU64, NvU64, NvU32, NvU32); +static NV_STATUS eheapDestruct(OBJEHEAP *); +static NV_STATUS eheapAlloc(OBJEHEAP *, NvU32, NvU32 *, NvU64 *, NvU64 *,NvU64, NvU64, EMEMBLOCK **, void*, EHeapOwnershipComparator*); +static NV_STATUS eheapFree(OBJEHEAP *, NvU64); +static void eheapInfo(OBJEHEAP *, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *, NvU64 *); +static void eheapInfoForRange(OBJEHEAP *, NV_RANGE, NvU64 *, NvU64 *, NvU32 *, NvU64 *); +static NV_STATUS eheapGetSize(OBJEHEAP *, NvU64 *); +static NV_STATUS eheapGetFree(OBJEHEAP *, NvU64 *); +static NV_STATUS eheapGetBase(OBJEHEAP *, NvU64 *); +static EMEMBLOCK *eheapGetBlock(OBJEHEAP *, NvU64, NvBool); +static NV_STATUS eheapSetAllocRange(OBJEHEAP *, NvU64, NvU64); +static NV_STATUS eheapTraverse(OBJEHEAP *, void *, EHeapTraversalFn, NvS32); +static NV_STATUS _eheapBlockFree(OBJEHEAP *pHeap, EMEMBLOCK *block); +static NvU32 eheapGetNumBlocks(OBJEHEAP *); +static NV_STATUS eheapGetBlockInfo(OBJEHEAP *, NvU32, NVOS32_HEAP_DUMP_BLOCK *); +static NV_STATUS eheapSetOwnerIsolation(OBJEHEAP *, NvBool, NvU32); +static NvBool _eheapCheckOwnership(OBJEHEAP *, void*, NvU64, NvU64, EMEMBLOCK *, EHeapOwnershipComparator*); void -constructObjEHeap(POBJEHEAP pHeap, NvU64 Base, NvU64 LimitPlusOne, NvU32 sizeofMemBlock, NvU32 numPreAllocMemStruct) +constructObjEHeap(OBJEHEAP *pHeap, NvU64 Base, NvU64 LimitPlusOne, NvU32 sizeofMemBlock, NvU32 numPreAllocMemStruct) { initPublicObjectFunctionPointers_EHeap(pHeap); @@ -61,7 +61,7 @@ constructObjEHeap(POBJEHEAP pHeap, NvU64 Base, NvU64 LimitPlusOne, NvU32 sizeofM } static void -initPublicObjectFunctionPointers_EHeap(POBJEHEAP pHeap) +initPublicObjectFunctionPointers_EHeap(OBJEHEAP *pHeap) { pHeap->eheapDestruct = eheapDestruct; pHeap->eheapAlloc = eheapAlloc; @@ -82,8 +82,8 @@ initPublicObjectFunctionPointers_EHeap(POBJEHEAP pHeap) static NV_STATUS _eheapAllocMemStruct ( - POBJEHEAP pHeap, - PEMEMBLOCK* ppMemBlock + OBJEHEAP *pHeap, + EMEMBLOCK **ppMemBlock ) { if (pHeap->numPreAllocMemStruct > 0) @@ -116,8 +116,8 @@ _eheapAllocMemStruct static NV_STATUS _eheapFreeMemStruct ( - POBJEHEAP pHeap, - PEMEMBLOCK* ppMemBlock + OBJEHEAP *pHeap, + EMEMBLOCK **ppMemBlock ) { if (pHeap->numPreAllocMemStruct > 0) @@ -146,14 +146,14 @@ _eheapFreeMemStruct static NV_STATUS eheapInit ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU64 Base, NvU64 LimitPlusOne, NvU32 sizeofData, NvU32 numPreAllocMemStruct ) { - PEMEMBLOCK block; + EMEMBLOCK *block; NvU32 i; // @@ -198,8 +198,8 @@ eheapInit // for (i = 0; i < numPreAllocMemStruct - 1; i++) { - ((PEMEMBLOCK)((NvU8 *)pHeap->pFreeMemStructList + (i * pHeap->sizeofMemBlock)))->next - = (PEMEMBLOCK)((NvU8 *)pHeap->pFreeMemStructList + (i + 1) * pHeap->sizeofMemBlock); + ((EMEMBLOCK *)((NvU8 *)pHeap->pFreeMemStructList + (i * pHeap->sizeofMemBlock)))->next + = (EMEMBLOCK *)((NvU8 *)pHeap->pFreeMemStructList + (i + 1) * pHeap->sizeofMemBlock); } } } @@ -243,10 +243,10 @@ eheapInit static NV_STATUS eheapDestruct ( - POBJEHEAP pHeap + OBJEHEAP *pHeap ) { - PEMEMBLOCK block, blockFirst, blockNext; + EMEMBLOCK *block, *blockFirst, *blockNext; NvBool headptr_updated; if (!pHeap->pBlockList) @@ -295,21 +295,21 @@ eheapDestruct static NV_STATUS eheapAlloc ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU32 owner, NvU32 *flags, NvU64 *offset, NvU64 *size, NvU64 offsetAlign, NvU64 sizeAlign, - PEMEMBLOCK * ppMemBlock, // not generally useful over e.g. a split! + EMEMBLOCK **ppMemBlock, // not generally useful over e.g. a split! void *pIsolationID, EHeapOwnershipComparator *checker ) { NvU64 allocLo, allocAl, allocHi; - PEMEMBLOCK blockFirstFree, blockFree; - PEMEMBLOCK blockNew = NULL, blockSplit = NULL; + EMEMBLOCK *blockFirstFree, *blockFree; + EMEMBLOCK *blockNew = NULL, *blockSplit = NULL; NvU64 desiredOffset; NvU64 allocSize; NvU64 rangeLo, rangeHi; @@ -840,11 +840,11 @@ eheapAlloc static NV_STATUS _eheapBlockFree ( - POBJEHEAP pHeap, - PEMEMBLOCK block + OBJEHEAP *pHeap, + EMEMBLOCK *block ) { - PEMEMBLOCK blockTmp; + EMEMBLOCK *blockTmp; // // Check for valid owner. @@ -990,28 +990,28 @@ _eheapBlockFree static NV_STATUS eheapFree ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU64 offset ) { - PEMEMBLOCK block; + EMEMBLOCK *block; - block = (PEMEMBLOCK) eheapGetBlock(pHeap, offset, 0); + block = (EMEMBLOCK *) eheapGetBlock(pHeap, offset, 0); if (!block) return NV_ERR_INVALID_OFFSET; return _eheapBlockFree(pHeap, block); } -static PEMEMBLOCK +static EMEMBLOCK * eheapGetBlock ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU64 offset, NvBool bReturnFreeBlock ) { - PEMEMBLOCK block; + EMEMBLOCK *block; PNODE pNode; if (btreeSearch(offset, &pNode, pHeap->pBlockTree) != NV_OK) @@ -1019,7 +1019,7 @@ eheapGetBlock return NULL; } - block = (PEMEMBLOCK)pNode->Data; + block = (EMEMBLOCK *)pNode->Data; if ((block->owner == NVOS32_BLOCK_TYPE_FREE ) && !bReturnFreeBlock) { return NULL; @@ -1031,7 +1031,7 @@ eheapGetBlock static NV_STATUS eheapGetSize ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU64 *size ) { @@ -1042,7 +1042,7 @@ eheapGetSize static NV_STATUS eheapGetFree ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU64 *free ) { @@ -1053,7 +1053,7 @@ eheapGetFree static NV_STATUS eheapGetBase ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU64 *base ) { @@ -1064,7 +1064,7 @@ eheapGetBase static void eheapInfo ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU64 *pBytesFree, // in all of the space managed NvU64 *pBytesTotal, // in all of the space managed NvU64 *pLargestFreeOffset, // constrained to pHeap->rangeLo, pHeap->rangeHi @@ -1089,7 +1089,7 @@ eheapInfo static void eheapInfoForRange ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NV_RANGE range, NvU64 *pLargestFreeOffset, // constrained to rangeLo, rangeHi NvU64 *pLargestFreeSize, // constrained to rangeLo, rangeHi @@ -1097,7 +1097,7 @@ eheapInfoForRange NvU64 *pUsableBytesFree // constrained to rangeLo, rangeHi ) { - PEMEMBLOCK blockFirstFree, blockFree; + EMEMBLOCK *blockFirstFree, *blockFree; NvU64 freeBlockSize = 0; NvU64 largestFreeOffset = 0; NvU64 largestFreeSize = 0; @@ -1152,7 +1152,7 @@ eheapInfoForRange static NV_STATUS eheapSetAllocRange ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU64 rangeLo, NvU64 rangeHi ) @@ -1176,14 +1176,14 @@ eheapSetAllocRange static NV_STATUS eheapTraverse ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, void *pEnv, EHeapTraversalFn traversalFn, NvS32 direction ) { NvU32 cont = 1, backAtFirstBlock = 0; - PEMEMBLOCK pBlock, pBlockNext; + EMEMBLOCK *pBlock, *pBlockNext; NV_STATUS rc; NvU64 cursorOffset; // for dealing with cursor invalidates. NvU64 firstBlockBegin, firstBlockEnd; // we'll never call the traversal fn twice on the same (sub)extent. @@ -1265,7 +1265,7 @@ eheapTraverse static NvU32 eheapGetNumBlocks ( - POBJEHEAP pHeap + OBJEHEAP *pHeap ) { return pHeap->numBlocks; @@ -1288,12 +1288,12 @@ eheapGetNumBlocks static NV_STATUS eheapGetBlockInfo ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvU32 numBlocks, NVOS32_HEAP_DUMP_BLOCK *pBlockBuffer ) { - PEMEMBLOCK pBlock; + EMEMBLOCK *pBlock; NvU32 heapSize, i; NV_STATUS rmStatus = NV_OK; @@ -1334,7 +1334,7 @@ eheapGetBlockInfo NV_STATUS eheapSetOwnerIsolation ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, NvBool bEnable, NvU32 granularity ) @@ -1375,11 +1375,11 @@ eheapSetOwnerIsolation static NvBool _eheapCheckOwnership ( - POBJEHEAP pHeap, + OBJEHEAP *pHeap, void *pIsolationID, NvU64 allocLo, NvU64 allocHi, - PEMEMBLOCK blockFree, + EMEMBLOCK *blockFree, EHeapOwnershipComparator *pComparator ) { diff --git a/src/nvidia/src/libraries/crashcat/crashcat_report.c b/src/nvidia/src/libraries/crashcat/crashcat_report.c index 12ee09835e..3d55aadadf 100644 --- a/src/nvidia/src/libraries/crashcat/crashcat_report.c +++ b/src/nvidia/src/libraries/crashcat/crashcat_report.c @@ -72,7 +72,7 @@ void crashcatReportLog_IMPL(CrashCatReport *pReport) crashcatReportLogRiscv64GprState_HAL(pReport); break; case NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE: - crashcatReportLogRiscv64Trace_HAL(pReport); + crashcatReportLogRiscv64Traces_HAL(pReport); break; case NV_CRASHCAT_PACKET_TYPE_IO32_STATE: crashcatReportLogIo32State_HAL(pReport); diff --git a/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c b/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c index 0401faa683..818afb6987 100644 --- a/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c +++ b/src/nvidia/src/libraries/crashcat/v1/crashcat_report_v1.c @@ -45,7 +45,8 @@ static NV_INLINE NvCrashCatPacketHeader_V1 crashcatReadPacketHeader(void *pHdr) void crashcatReportDestruct_V1(CrashCatReport *pReport) { - portMemFree(pReport->v1.pRiscv64Trace); + portMemFree(pReport->v1.pRiscv64StackTrace); + portMemFree(pReport->v1.pRiscv64PcTrace); portMemFree(pReport->v1.pIo32State); } @@ -242,20 +243,54 @@ void *crashcatReportExtractRiscv64Trace_V1 if (!crashcatPacketHeaderValid(hdr) || (crashcatPacketHeaderFormatVersion(hdr) != NV_CRASHCAT_PACKET_FORMAT_VERSION_1)) { - NV_PRINTF(LEVEL_WARNING, "Invalid V1 stack trace header 0x%" NvU64_fmtx "\n", hdr); + NV_PRINTF(LEVEL_WARNING, "Invalid V1 trace packet header 0x%" NvU64_fmtx "\n", hdr); return pReportBytes; } - // Allocate the buffer for the stack trace + // Allocate the buffer for the trace const NvU32 payloadSize = crashcatPacketHeaderPayloadSize(hdr); const NvLength sizeBytes = sizeof(NvCrashCatRiscv64Trace_V1) + payloadSize; NV_CHECK_OR_RETURN(LEVEL_ERROR, payloadSize > 0, pReportBytes); - pReport->v1.pRiscv64Trace = portMemAllocNonPaged(sizeBytes); - NV_CHECK_OR_RETURN(LEVEL_ERROR, pReport->v1.pRiscv64Trace != NULL, pReportBytes); + NvCrashCatRiscv64Trace_V1 *pRiscv64Trace = portMemAllocNonPaged(sizeBytes); + NV_CHECK_OR_RETURN(LEVEL_ERROR, pRiscv64Trace != NULL, pReportBytes); - portMemCopy(pReport->v1.pRiscv64Trace, sizeBytes, pReportBytes, sizeBytes); - pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE); + portMemCopy(pRiscv64Trace, sizeBytes, pReportBytes, sizeBytes); + + // + // We support both stack and PC traces in one report. They share a tag bit (will be set if + // either are present). + // + switch (crashcatRiscv64TraceV1Type(pRiscv64Trace)) + { + case NV_CRASHCAT_TRACE_TYPE_STACK: + if (pReport->v1.pRiscv64StackTrace != NULL) + { + NV_PRINTF(LEVEL_WARNING, + "Only one stack trace packet is supported, discarding the old one\n"); + portMemFree(pReport->v1.pRiscv64StackTrace); + } + + pReport->v1.pRiscv64StackTrace = pRiscv64Trace; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE); + break; + case NV_CRASHCAT_TRACE_TYPE_NVRVTB: + if (pReport->v1.pRiscv64PcTrace != NULL) + { + NV_PRINTF(LEVEL_WARNING, + "Only one PC trace packet is supported, discarding the old one\n"); + portMemFree(pReport->v1.pRiscv64PcTrace); + } + + pReport->v1.pRiscv64PcTrace = pRiscv64Trace; + pReport->validTags |= NVBIT(NV_CRASHCAT_PACKET_TYPE_RISCV64_TRACE); + break; + default: + NV_PRINTF(LEVEL_WARNING, "Unknown CrashCat trace type (0x%x), discarding\n", + crashcatRiscv64TraceV1Type(pRiscv64Trace)); + portMemFree(pRiscv64Trace); + break; + } return (void *)((NvUPtr)pReportBytes + sizeBytes); } @@ -392,9 +427,12 @@ static NV_INLINE const char *crashcatRiscv64TraceTypeToString_V1(NV_CRASHCAT_TRA } } -void crashcatReportLogRiscv64Trace_V1(CrashCatReport *pReport) +static void crashcatReportLogRiscv64Trace_V1 +( + CrashCatReport *pReport, + NvCrashCatRiscv64Trace_V1 *pTraceV1 +) { - NvCrashCatRiscv64Trace_V1 *pTraceV1 = pReport->v1.pRiscv64Trace; NvU16 entries = crashcatPacketHeaderPayloadSize(pTraceV1->header) >> 3; NV_CRASHCAT_TRACE_TYPE traceType = crashcatRiscv64TraceV1Type(pTraceV1); @@ -402,8 +440,59 @@ void crashcatReportLogRiscv64Trace_V1(CrashCatReport *pReport) CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, "%s Trace:", crashcatRiscv64TraceTypeToString_V1(traceType)); - for (NvU16 i = 0; i < entries; i++) - CRASHCAT_REPORT_LOG_DATA(pReport, "0x%" NvU64_fmtx, pTraceV1->addr[i]); + if (traceType == NV_CRASHCAT_TRACE_TYPE_NVRVTB) + { + // PC traces are too long with each entry on its own line + const NvU8 ENTRIES_PER_LINE = 5; + NvU16 idx; + for (idx = 0; idx < (entries / ENTRIES_PER_LINE) * ENTRIES_PER_LINE; + idx += ENTRIES_PER_LINE) + { + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " " + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2], + pTraceV1->addr[idx + 3], pTraceV1->addr[idx + 4]); + } + + switch (entries - idx) + { + case 4: + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " " + "0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2], + pTraceV1->addr[idx + 3]); + break; + case 3: + CRASHCAT_REPORT_LOG_DATA(pReport, + "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1], pTraceV1->addr[idx + 2]); + break; + case 2: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx " 0x%016" NvU64_fmtx, + pTraceV1->addr[idx + 0], pTraceV1->addr[idx + 1]); + break; + case 1: + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx, pTraceV1->addr[idx + 0]); + break; + default: + break; + } + } + else + { + for (NvU16 idx = 0; idx < entries; idx++) + CRASHCAT_REPORT_LOG_DATA(pReport, "0x%016" NvU64_fmtx, pTraceV1->addr[idx]); + } +} + +void crashcatReportLogRiscv64Traces_V1(CrashCatReport *pReport) +{ + if (pReport->v1.pRiscv64StackTrace != NULL) + crashcatReportLogRiscv64Trace_V1(pReport, pReport->v1.pRiscv64StackTrace); + if (pReport->v1.pRiscv64PcTrace != NULL) + crashcatReportLogRiscv64Trace_V1(pReport, pReport->v1.pRiscv64PcTrace); } static NV_INLINE const char *crashcatIo32ApertureToString_V1(NV_CRASHCAT_IO_APERTURE aperture) diff --git a/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c new file mode 100644 index 0000000000..d19b21caf7 --- /dev/null +++ b/src/nvidia/src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c @@ -0,0 +1,149 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#define NVOC_CRASHCAT_REPORT_H_PRIVATE_ACCESS_ALLOWED +#include "crashcat/crashcat_report.h" +#include "crashcat/crashcat_engine.h" +#include "libos_v3_crashcat.h" +#include "utils/nvprintf.h" +#include "nv-crashcat-decoder.h" + +static inline const char *crashcatReportModeToString_LIBOS3(NV_CRASHCAT_RISCV_MODE mode) +{ + switch (mode) + { + case NV_CRASHCAT_RISCV_MODE_M: + return MAKE_NV_PRINTF_STR("monitor"); + case NV_CRASHCAT_RISCV_MODE_S: + return MAKE_NV_PRINTF_STR("kernel"); + case NV_CRASHCAT_RISCV_MODE_U: + return MAKE_NV_PRINTF_STR("task"); + default: + return MAKE_NV_PRINTF_STR("unspecified"); + } +} + +static inline const char *crashcatReportPanicReasonToString_LIBOS3(LibosPanicReason reason) +{ +#define LIBOS_PANIC_REASON_CASE(reason, str) \ + case LibosPanicReason ## reason: return MAKE_NV_PRINTF_STR(str) + + switch (reason) + { + LIBOS_PANIC_REASON_CASE(UnhandledState, "unhandled state"); + LIBOS_PANIC_REASON_CASE(InvalidConfiguration, "invalid configuration"); + LIBOS_PANIC_REASON_CASE(FatalHardwareError, "fatal hardware error"); + LIBOS_PANIC_REASON_CASE(InsufficientResources, "insufficient resources"); + LIBOS_PANIC_REASON_CASE(Timeout, "timeout"); + LIBOS_PANIC_REASON_CASE(EnvCallFailed, "environment call failed"); + LIBOS_PANIC_REASON_CASE(AsanMemoryError, "asan memory error detected"); + LIBOS_PANIC_REASON_CASE(ProgrammingError, "programming error"); + LIBOS_PANIC_REASON_CASE(AssertionFailed, "condition failed"); + LIBOS_PANIC_REASON_CASE(TrapKernelPanic, "unhandled trap"); + LIBOS_PANIC_REASON_CASE(TrapInstruction, "instruction access fault"); + default: return MAKE_NV_PRINTF_STR("unknown error"); + } +} + +void crashcatReportLogSource_V1_LIBOS3(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + + NvU8 taskId = crashcatReportV1SourceLibos3TaskId(pReportV1); + NvCrashCatNvriscvPartition sourcePartition = crashcatReportV1ReporterPartition(pReportV1); + NvCrashCatNvriscvUcodeId sourceUcodeId = crashcatReportV1ReporterUcodeId(pReportV1); + +#define CRASHCAT_LOG_LIBOS3_SOURCE(fmt, ...) \ + if (taskId == NV_CRASHCAT_REPORT_V1_SOURCE_ID_LIBOS3_TASK_ID_UNSPECIFIED) \ + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, fmt ", partition:%u#%u", \ + __VA_ARGS__, sourcePartition, sourceUcodeId); \ + else \ + crashcatEnginePrintf(pReport->pEngine, NV_TRUE, fmt ", partition:%u#%u, task:%u", \ + __VA_ARGS__, sourcePartition, sourceUcodeId, taskId) + + const char *pModeStr = crashcatReportModeToString_LIBOS3(crashcatReportV1SourceMode(pReportV1)); + switch (crashcatReportV1SourceCauseType(pReportV1)) + { + case NV_CRASHCAT_CAUSE_TYPE_EXCEPTION: + { + // Kernel or task unhandled exception - the sourceData is the xcause value + NvU64 xcause = pReportV1->sourceData; + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s exception: %s (cause:0x%" NvU64_fmtx ") @ pc:0x%" NvU64_fmtx, + pModeStr, crashcatReportRiscvCauseToString(xcause), + xcause, pReportV1->sourcePc); + break; + } + case NV_CRASHCAT_CAUSE_TYPE_TIMEOUT: + { + // Task timeout (no way for libos3 to self-report kernel timeouts) + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s timeout @ pc:0x%" NvU64_fmtx, + pModeStr, pReportV1->sourcePc); + break; + } + case NV_CRASHCAT_CAUSE_TYPE_PANIC: + { + // Kernel or task panic + LibosPanicReason reason = crashcatReportV1SourceCauseLibos3Reason(pReportV1); + CRASHCAT_LOG_LIBOS3_SOURCE( + "%s panic: %s (%u) @ pc:0x%" NvU64_fmtx ", aux:0x%" NvU64_fmtx, + pModeStr, crashcatReportPanicReasonToString_LIBOS3(reason), reason, + pReportV1->sourcePc, pReportV1->sourceData); + break; + } + } +} + +void crashcatReportLogReporter_V1_LIBOS3(CrashCatReport *pReport) +{ + NvCrashCatReport_V1 *pReportV1 = &pReport->v1.report; + NvU8 taskId = crashcatReportV1ReporterLibos3TaskId(pReportV1); + + // + // Though this is technically not a separate packet, we use the CRASHCAT_REPORT_LOG_PACKET_TYPE + // macro to get the correct prefix/indentation for the reporter information. + // + if (taskId == NV_CRASHCAT_REPORT_V1_REPORTER_ID_LIBOS3_TASK_ID_UNSPECIFIED) + { + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, + "Reported by libos partition:%u#%u kernel v%u.%u [%u] @ ts:%u", + crashcatReportV1ReporterPartition(pReportV1), + crashcatReportV1ReporterUcodeId(pReportV1), + crashcatReportV1ReporterVersionLibos3Major(pReportV1), + crashcatReportV1ReporterVersionLibos3Minor(pReportV1), + crashcatReportV1ReporterVersionLibos3Cl(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); + } + else + { + CRASHCAT_REPORT_LOG_PACKET_TYPE(pReport, + "Reported by libos partition:%u#%u task:%u v%u.%u [%u] @ ts:%u", + crashcatReportV1ReporterPartition(pReportV1), + crashcatReportV1ReporterUcodeId(pReportV1), + taskId, crashcatReportV1ReporterVersionLibos3Major(pReportV1), + crashcatReportV1ReporterVersionLibos3Minor(pReportV1), + crashcatReportV1ReporterVersionLibos3Cl(pReportV1), + crashcatReportV1ReporterTimestamp(pReportV1)); + } +} diff --git a/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c b/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c index f542c6431b..b1d174afb5 100644 --- a/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c +++ b/src/nvidia/src/libraries/eventbuffer/eventbufferproducer.c @@ -295,14 +295,10 @@ eventBufferIsNotifyThresholdMet(EVENT_BUFFER_PRODUCER_INFO* info) RECORD_BUFFER_INFO* pRecInfo = &info->recordBuffer; NV_EVENT_BUFFER_HEADER* pHeader = pRecInfo->pHeader; - if (!info->isKeepNewest) + if (((pRecInfo->totalRecordCount - pHeader->recordCount) <= pRecInfo->notificationThreshold) || + (pVarInfo->remainingSize <= pVarInfo->notificationThreshold)) { - if (((pRecInfo->totalRecordCount - pHeader->recordCount) <= pRecInfo->notificationThreshold) || - (pVarInfo->remainingSize <= pVarInfo->notificationThreshold)) - { - return NV_TRUE; - } + return NV_TRUE; } return NV_FALSE; } - diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h deleted file mode 100644 index 9e8396eabe..0000000000 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/memlib.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * Copyright Notice: - * Copyright 2021-2022 DMTF. All rights reserved. - * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md - **/ - -/** @file - * Provides copy memory, fill memory, zero memory, and GUID functions. - * - * The Base Memory Library provides optimized implementations for common memory-based operations. - * These functions should be used in place of coding your own loops to do equivalent common functions. - * This allows optimized library implementations to help increase performance. - **/ - -#ifndef BASE_MEMORY_LIB -#define BASE_MEMORY_LIB - -/** - * Copies bytes from a source buffer to a destination buffer. - * - * This function copies "src_len" bytes from "src_buf" to "dst_buf". - * - * Asserts and returns a non-zero value if any of the following are true: - * 1) "src_buf" or "dst_buf" are NULL. - * 2) "src_len" or "dst_len" is greater than (SIZE_MAX >> 1). - * 3) "src_len" is greater than "dst_len". - * 4) "src_buf" and "dst_buf" overlap. - * - * If any of these cases fail, a non-zero value is returned. Additionally if - * "dst_buf" points to a non-NULL value and "dst_len" is valid, then "dst_len" - * bytes of "dst_buf" are zeroed. - * - * This function follows the C11 cppreference description of memcpy_s. - * https://en.cppreference.com/w/c/string/byte/memcpy - * The cppreferece description does NOT allow the source or destination - * buffers to be NULL. - * - * This function differs from the Microsoft and Safeclib memcpy_s implementations - * in that the Microsoft and Safeclib implementations allow for NULL source and - * destinations pointers when the number of bytes to copy (src_len) is zero. - * - * In addition the Microsoft and Safeclib memcpy_s functions return different - * negative values on error. For best support, clients should generally check - * against zero for success or failure. - * - * @param dst_buf Destination buffer to copy to. - * @param dst_len Maximum length in bytes of the destination buffer. - * @param src_buf Source buffer to copy from. - * @param src_len The number of bytes to copy from the source buffer. - * - * @return 0 on success. non-zero on error. - * - **/ -int libspdm_copy_mem(void *dst_buf, size_t dst_len, - const void *src_buf, size_t src_len); - -/** - * Fills a target buffer with a byte value, and returns the target buffer. - * - * This function fills length bytes of buffer with value, and returns buffer. - * - * If length is greater than (MAX_ADDRESS - buffer + 1), then ASSERT(). - * - * @param buffer The memory to set. - * @param length The number of bytes to set. - * @param value The value with which to fill length bytes of buffer. - * - * @return buffer. - * - **/ -void *libspdm_set_mem(void *buffer, size_t length, uint8_t value); - -/** - * Fills a target buffer with zeros, and returns the target buffer. - * - * This function fills length bytes of buffer with zeros, and returns buffer. - * - * If length > 0 and buffer is NULL, then ASSERT(). - * If length is greater than (MAX_ADDRESS - buffer + 1), then ASSERT(). - * - * @param buffer The pointer to the target buffer to fill with zeros. - * @param length The number of bytes in buffer to fill with zeros. - * - * @return buffer. - * - **/ -void *libspdm_zero_mem(void *buffer, size_t length); - -/** - * Compares the contents of two buffers in const time. - * - * This function compares length bytes of source_buffer to length bytes of destination_buffer. - * If all length bytes of the two buffers are identical, then 0 is returned. Otherwise, the - * value returned is the first mismatched byte in source_buffer subtracted from the first - * mismatched byte in destination_buffer. - * - * If length > 0 and destination_buffer is NULL, then ASSERT(). - * If length > 0 and source_buffer is NULL, then ASSERT(). - * If length is greater than (MAX_ADDRESS - destination_buffer + 1), then ASSERT(). - * If length is greater than (MAX_ADDRESS - source_buffer + 1), then ASSERT(). - * - * @param destination_buffer A pointer to the destination buffer to compare. - * @param source_buffer A pointer to the source buffer to compare. - * @param length The number of bytes to compare. - * - * @return 0 All length bytes of the two buffers are identical. - * @retval Non-zero There is mismatched between source_buffer and destination_buffer. - * - **/ -int32_t libspdm_const_compare_mem(const void *destination_buffer, - const void *source_buffer, size_t length); - -#endif /* BASE_MEMORY_LIB */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h deleted file mode 100644 index b1d3f28c6a..0000000000 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/platform_lib.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * Copyright Notice: - * Copyright 2022 DMTF. All rights reserved. - * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md - **/ -#ifndef PLATFORM_LIB_H -#define PLATFORM_LIB_H - -#include "hal/base.h" -#include "internal/libspdm_lib_config.h" - -/** - * Suspends the execution of the current thread until the time-out interval elapses. - * This API is deprecated. Please use libspdm_sleep_in_us(). - * - * @param milliseconds The time interval for which execution is to be suspended, in milliseconds. - * - **/ -void libspdm_sleep(uint64_t milliseconds); - -/** - * Suspends the execution of the current thread until the time-out interval elapses. - * - * @param microseconds The time interval for which execution is to be suspended, in milliseconds. - * - **/ -void libspdm_sleep_in_us(uint64_t microseconds); - -#if LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP -/** - * If no heartbeat arrives in seconds, the watchdog timeout event - * should terminate the session. - * - * @param session_id Indicate the SPDM session ID. - * @param seconds heartbeat period, in seconds. - * - **/ -bool libspdm_start_watchdog(uint32_t session_id, uint16_t seconds); - -/** - * stop watchdog. - * - * @param session_id Indicate the SPDM session ID. - * - **/ -bool libspdm_stop_watchdog(uint32_t session_id); - -/** - * Reset the watchdog in heartbeat response. - * - * @param session_id Indicate the SPDM session ID. - * - **/ -bool libspdm_reset_watchdog(uint32_t session_id); -#endif /* LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP */ - -#endif /* PLATFORM_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h deleted file mode 100644 index 69be506b04..0000000000 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_lib_config.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * Copyright Notice: - * Copyright 2021-2022 DMTF. All rights reserved. - * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md - **/ - -#ifndef LIBSPDM_LIB_CONFIG_H -#define LIBSPDM_LIB_CONFIG_H - -#ifndef LIBSPDM_CONFIG -#include "library/spdm_lib_config.h" -#else -#include LIBSPDM_CONFIG -#endif - -#if defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) && \ - !defined(LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP) -#warning LIBSPDM_ENABLE_SET_CERTIFICATE_CAP is deprecated. Use \ - LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP instead. This warning will be removed in a \ - future release. -#endif /* defined(LIBSPDM_ENABLE_SET_CERTIFICATE_CAP) */ - -#if defined(LIBSPDM_ENABLE_CHUNK_CAP) && !defined(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) -#warning LIBSPDM_ENABLE_CHUNK_CAP is deprecated. Use LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP \ - instead. This warning will be removed in a future release. -#endif /* defined(LIBSPDM_ENABLE_CHUNK_CAP) */ - -#if defined(MDEPKG_NDEBUG) && !defined(LIBSPDM_DEBUG_ENABLE) -#warning MDEPKG_NDEBUG is deprecated. Use LIBSPDM_DEBUG_ENABLE \ - instead. This warning will be removed in a future release. -#endif /* defined(MDEPKG_NDEBUG) */ - -#if defined(LIBSPDM_DEBUG_ENABLE) -#undef LIBSPDM_DEBUG_ASSERT_ENABLE -#undef LIBSPDM_DEBUG_PRINT_ENABLE -#undef LIBSPDM_DEBUG_BLOCK_ENABLE - -#define LIBSPDM_DEBUG_ASSERT_ENABLE (LIBSPDM_DEBUG_ENABLE) -#define LIBSPDM_DEBUG_PRINT_ENABLE (LIBSPDM_DEBUG_ENABLE) -#define LIBSPDM_DEBUG_BLOCK_ENABLE (LIBSPDM_DEBUG_ENABLE) -#elif defined(MDEPKG_NDEBUG) -#undef LIBSPDM_DEBUG_ASSERT_ENABLE -#undef LIBSPDM_DEBUG_PRINT_ENABLE -#undef LIBSPDM_DEBUG_BLOCK_ENABLE - -#define LIBSPDM_DEBUG_ASSERT_ENABLE 0 -#define LIBSPDM_DEBUG_PRINT_ENABLE 0 -#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 -#endif /* defined(LIBSPDM_DEBUG_ENABLE) */ - -#if LIBSPDM_CHECK_MACRO -#include "internal/libspdm_macro_check.h" -#endif /* LIBSPDM_CHECK_MACRO */ - -#endif /* LIBSPDM_LIB_CONFIG_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h deleted file mode 100644 index 93311336c5..0000000000 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_macro_check.h +++ /dev/null @@ -1,44 +0,0 @@ -/** - * Copyright Notice: - * Copyright 2021-2022 DMTF. All rights reserved. - * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md - **/ - -#ifndef LIBSPDM_MACRO_CHECK_H -#define LIBSPDM_MACRO_CHECK_H - -#define LIBSPDM_ASYM_ALGO_SUPPORT \ - ((LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) || \ - (LIBSPDM_SM2_DSA_SUPPORT) || (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT)) - -#define LIBSPDM_DHE_ALGO_SUPPORT \ - ((LIBSPDM_FFDHE_SUPPORT) || (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT)) - -#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT - #error If KEY_EX_CAP is enabled then at least one asymmetric algorithm must also be enabled. -#endif - -#if (LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT - #error If CERT_CAP is enabled then at least one asymmetric algorithm must also be enabled. -#endif - -#if (LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT - #error If CHAL_CAP is enabled then at least one asymmetric algorithm must also be enabled. -#endif - -#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_DHE_ALGO_SUPPORT - #error If KEY_EX_CAP is enabled then at least one DHE algorithm must also be enabled. -#endif - -#if ((LIBSPDM_MAX_VERSION_COUNT) == 0) || ((LIBSPDM_MAX_VERSION_COUNT) > 255) - #error LIBSPDM_MAX_VERSION_COUNT must be between 1 and 255 inclusive. -#endif - -#if (LIBSPDM_MAX_SESSION_COUNT) > 65535 - #error LIBSPDM_MAX_SESSION_COUNT must be less than 65536. -#endif - -#undef LIBSPDM_ASYM_ALGO_SUPPORT -#undef LIBSPDM_DHE_ALGO_SUPPORT - -#endif /* LIBSPDM_MACRO_CHECK_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h deleted file mode 100644 index 97d95f8411..0000000000 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_secured_message_lib.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - * Copyright Notice: - * Copyright 2021-2022 DMTF. All rights reserved. - * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md - **/ - -#ifndef SPDM_SECURED_MESSAGE_LIB_INTERNAL_H -#define SPDM_SECURED_MESSAGE_LIB_INTERNAL_H - -#include "library/spdm_secured_message_lib.h" -#include "library/spdm_crypt_lib.h" -#include "library/spdm_device_secret_lib.h" -#include "internal/libspdm_common_lib.h" -#include "hal/library/memlib.h" -#include "hal/library/cryptlib.h" - -typedef struct { - uint8_t dhe_secret[LIBSPDM_MAX_DHE_KEY_SIZE]; - uint8_t handshake_secret[LIBSPDM_MAX_HASH_SIZE]; - uint8_t master_secret[LIBSPDM_MAX_HASH_SIZE]; -} libspdm_session_info_struct_master_secret_t; - -typedef struct { - uint8_t request_handshake_secret[LIBSPDM_MAX_HASH_SIZE]; - uint8_t response_handshake_secret[LIBSPDM_MAX_HASH_SIZE]; - uint8_t request_finished_key[LIBSPDM_MAX_HASH_SIZE]; - uint8_t response_finished_key[LIBSPDM_MAX_HASH_SIZE]; - uint8_t request_handshake_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; - uint8_t request_handshake_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; - uint64_t request_handshake_sequence_number; - uint8_t response_handshake_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; - uint8_t response_handshake_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; - uint64_t response_handshake_sequence_number; -} libspdm_session_info_struct_handshake_secret_t; - -typedef struct { - uint8_t request_data_secret[LIBSPDM_MAX_HASH_SIZE]; - uint8_t response_data_secret[LIBSPDM_MAX_HASH_SIZE]; - uint8_t request_data_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; - uint8_t request_data_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; - uint64_t request_data_sequence_number; - uint8_t response_data_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; - uint8_t response_data_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; - uint64_t response_data_sequence_number; -} libspdm_session_info_struct_application_secret_t; - -typedef struct { - libspdm_session_type_t session_type; - spdm_version_number_t version; - spdm_version_number_t secured_message_version; - uint32_t base_hash_algo; - uint16_t dhe_named_group; - uint16_t aead_cipher_suite; - uint16_t key_schedule; - size_t hash_size; - size_t dhe_key_size; - size_t aead_key_size; - size_t aead_iv_size; - size_t aead_tag_size; - bool use_psk; - libspdm_session_state_t session_state; - libspdm_session_info_struct_master_secret_t master_secret; - libspdm_session_info_struct_handshake_secret_t handshake_secret; - libspdm_session_info_struct_application_secret_t application_secret; - libspdm_session_info_struct_application_secret_t application_secret_backup; - bool requester_backup_valid; - bool responder_backup_valid; - size_t psk_hint_size; - uint8_t psk_hint[LIBSPDM_PSK_MAX_HINT_LENGTH]; - uint8_t export_master_secret[LIBSPDM_MAX_HASH_SIZE]; - - /* Cache the error in libspdm_decode_secured_message. - * It is handled in libspdm_build_response. */ - libspdm_error_struct_t last_spdm_error; -} libspdm_secured_message_context_t; - -#define LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE (sizeof(libspdm_secured_message_context_t)) - -#endif /* SPDM_SECURED_MESSAGE_LIB_INTERNAL_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h b/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h deleted file mode 100644 index 429d1377e3..0000000000 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_device_secret_lib.h +++ /dev/null @@ -1,256 +0,0 @@ -/** - * Copyright Notice: - * Copyright 2021-2022 DMTF. All rights reserved. - * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md - **/ - -#ifndef SPDM_DEVICE_SECRET_LIB_H -#define SPDM_DEVICE_SECRET_LIB_H - -#include "internal/libspdm_lib_config.h" - -#include "hal/base.h" -#include "industry_standard/spdm.h" -#include "hal/library/debuglib.h" -#include "hal/library/memlib.h" -#include "hal/library/cryptlib.h" -#include "library/spdm_crypt_lib.h" -#include "library/spdm_return_status.h" - -#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP -/** - * Collect the device measurement. - * - * libspdm will call this function to retrieve the measurements for a device. - * The "measurement_index" parameter indicates the measurement requested. - * - * @param measurement_specification Indicates the measurement specification. - * Must be a SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_* value in spdm.h. - * - * @param measurement_hash_algo Indicates the measurement hash algorithm. - * Must be SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_* value in spdm.h. - * - * @param measurement_index The index of the measurement to collect. - * - * A value of [0x0] requests only the total number of measurements to be returned - * in "measurements_count". The parameters "measurements" and - * "measurements_size" will be left unmodified. - * - * A value of [1-0xFE] requests a single measurement for that measurement index - * be returned. On success, "measurements_count" will be set to 1 and the - * "measurements" and "measurements_size" fields will be set based - * on the single measurement. An invalid measurement index will cause - * "measurements_count" to return 0. - * - * A value of [0xFF] requests all measurements be returned. - * On success, "measurements_count", "measurements", and "measurements_size" - * fields will be set with data from all measurements. - * - * @param measurements_count - * - * When "measurement_index" is zero, returns the total count of - * measurements available for the device. None of the actual measurements are - * returned however, and "measurements" and "measurements_size" are unmodified. - * - * When "measurement_index" is non-zero, returns the number of measurements - * returned in "measurements" and "measurements_size". If "measurements_index" - * is an invalid index not supported by the device, "measurements_count" will - * return 0. - * - * @param measurements - * - * A pointer to a destination buffer to store the concatenation of all device - * measurement blocks. This buffer will only be modified if - * "measurement_index" is non-zero. - * - * @param measurements_size - * - * On input, indicates the size in bytes of the destination buffer. - * On output, indicates the total size in bytes of all device measurement - * blocks in the buffer. This field should only be modified if - * "measurement_index" is non-zero. - * - * @retval RETURN_SUCCESS Successfully returned measurement_count, - * measurements, measurements_size. - * @retval RETURN_BUFFER_TOO_SMALL measurements buffer too small for measurements. - * @retval RETURN_INVALID_PARAMETER Invalid parameter passed to function. - * @retval RETURN_NOT_FOUND Unsupported measurement index. - * @retval RETURN_*** Any other RETURN_ error from base.h - * indicating the type of failure - **/ -libspdm_return_t libspdm_measurement_collection( - spdm_version_number_t spdm_version, - uint8_t measurement_specification, - uint32_t measurement_hash_algo, - uint8_t measurement_index, - uint8_t request_attribute, - uint8_t *content_changed, - uint8_t *measurements_count, - void *measurements, - size_t *measurements_size); - -/** - * This function calculates the measurement summary hash. - * - * @param spdm_version The spdm version. - * @param base_hash_algo The hash algo to use on summary. - * @param measurement_specification Indicates the measurement specification. - * It must align with measurement_specification - * (SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_*) - * @param measurement_hash_algo Indicates the measurement hash algorithm. - * It must align with measurement_hash_alg - * (SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_*) - * - * @param measurement_summary_hash_type The type of the measurement summary hash. - * @param measurement_summary_hash The buffer to store the measurement summary hash. - * @param measurement_summary_hash_size The size in bytes of the buffer. - * - * @retval true measurement summary hash is generated or skipped. - * @retval false measurement summary hash is not generated. - **/ -bool libspdm_generate_measurement_summary_hash( - spdm_version_number_t spdm_version, - uint32_t base_hash_algo, - uint8_t measurement_specification, - uint32_t measurement_hash_algo, - uint8_t measurement_summary_hash_type, - uint8_t *measurement_summary_hash, - size_t *measurement_summary_hash_size); -#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ - -#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP -/** - * Sign an SPDM message data. - * - * @param req_base_asym_alg Indicates the signing algorithm. - * @param base_hash_algo Indicates the hash algorithm. - * @param is_data_hash Indicate the message type. true: raw message before hash, false: message hash. - * @param message A pointer to a message to be signed. - * @param message_size The size in bytes of the message to be signed. - * @param signature A pointer to a destination buffer to store the signature. - * @param sig_size On input, indicates the size in bytes of the destination buffer to store the signature. - * On output, indicates the size in bytes of the signature in the buffer. - * - * @retval true signing success. - * @retval false signing fail. - **/ -bool libspdm_requester_data_sign( - spdm_version_number_t spdm_version, - uint8_t op_code, - uint16_t req_base_asym_alg, - uint32_t base_hash_algo, bool is_data_hash, - const uint8_t *message, size_t message_size, - uint8_t *signature, size_t *sig_size); -#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ - -/** - * Sign an SPDM message data. - * - * @param base_asym_algo Indicates the signing algorithm. - * @param base_hash_algo Indicates the hash algorithm. - * @param is_data_hash Indicate the message type. true: raw message before hash, false: message hash. - * @param message A pointer to a message to be signed. - * @param message_size The size in bytes of the message to be signed. - * @param signature A pointer to a destination buffer to store the signature. - * @param sig_size On input, indicates the size in bytes of the destination buffer to store the signature. - * On output, indicates the size in bytes of the signature in the buffer. - * - * @retval true signing success. - * @retval false signing fail. - **/ -bool libspdm_responder_data_sign( - spdm_version_number_t spdm_version, - uint8_t op_code, - uint32_t base_asym_algo, - uint32_t base_hash_algo, bool is_data_hash, - const uint8_t *message, size_t message_size, - uint8_t *signature, size_t *sig_size); - -#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP -/** - * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF algorithm. - * - * @param base_hash_algo Indicates the hash algorithm. - * @param psk_hint Pointer to the user-supplied PSK Hint. - * @param psk_hint_size PSK Hint size in bytes. - * @param info Pointer to the application specific info. - * @param info_size info size in bytes. - * @param out Pointer to buffer to receive hkdf value. - * @param out_size size of hkdf bytes to generate. - * - * @retval true Hkdf generated successfully. - * @retval false Hkdf generation failed. - **/ -bool libspdm_psk_handshake_secret_hkdf_expand( - spdm_version_number_t spdm_version, - uint32_t base_hash_algo, const uint8_t *psk_hint, - size_t psk_hint_size, const uint8_t *info, - size_t info_size, uint8_t *out, size_t out_size); - -/** - * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF algorithm. - * - * @param base_hash_algo Indicates the hash algorithm. - * @param psk_hint Pointer to the user-supplied PSK Hint. - * @param psk_hint_size PSK Hint size in bytes. - * @param info Pointer to the application specific info. - * @param info_size info size in bytes. - * @param out Pointer to buffer to receive hkdf value. - * @param out_size size of hkdf bytes to generate. - * - * @retval true Hkdf generated successfully. - * @retval false Hkdf generation failed. - **/ -bool libspdm_psk_master_secret_hkdf_expand( - spdm_version_number_t spdm_version, - uint32_t base_hash_algo, - const uint8_t *psk_hint, - size_t psk_hint_size, - const uint8_t *info, - size_t info_size, uint8_t *out, - size_t out_size); -#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ - -#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP -/** - * This function sends SET_CERTIFICATE - * to set certificate from the device. - * - * - * @param[in] slot_id The number of slot for the certificate chain. - * @param[in] cert_chain The pointer for the certificate chain to set. - * @param[in] cert_chain_size The size of the certificate chain to set. - * - * @retval true Set certificate to NV successfully. - * @retval false Set certificate to NV unsuccessfully. - **/ -bool libspdm_write_certificate_to_nvm(uint8_t slot_id, const void * cert_chain, - size_t cert_chain_size); -#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ - -#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP -/** - * Gen CSR - * - * @param[in] base_hash_algo hash algo for sign - * @param[in] base_asym_algo asym public key to set - * @param[in] need_reset device need reset for gen csr - * - * @param[in] requester_info requester info to gen CSR - * @param[in] requester_info_length The len of requester info - * - * @param[in] csr_len For input, csr_len is the size of store CSR buffer. - * For output, csr_len is CSR len for DER format - * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. - * For output, csr_pointer is address for stored CSR. - * The csr_pointer address will be changed. - * - * @retval true Success. - * @retval false Failed to gen CSR. - **/ -bool libspdm_gen_csr(uint32_t base_hash_algo, uint32_t base_asym_algo, bool *need_reset, - uint8_t *requester_info, size_t requester_info_length, - size_t *csr_len, uint8_t **csr_pointer); -#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ - -#endif /* SPDM_DEVICE_SECRET_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c deleted file mode 100644 index 25e25bea3a..0000000000 --- a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c +++ /dev/null @@ -1,49 +0,0 @@ -/** - * Copyright Notice: - * Copyright 2021-2022 DMTF. All rights reserved. - * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md - **/ - -/** @file - * libspdm_const_compare_mem() implementation. - **/ - -#include "base.h" - -/** - * Compares the contents of two buffers in const time. - * - * This function compares length bytes of source_buffer to length bytes of destination_buffer. - * If all length bytes of the two buffers are identical, then 0 is returned. Otherwise, the - * value returned is the first mismatched byte in source_buffer subtracted from the first - * mismatched byte in destination_buffer. - * - * If length > 0 and destination_buffer is NULL, then LIBSPDM_ASSERT(). - * If length > 0 and source_buffer is NULL, then LIBSPDM_ASSERT(). - * If length is greater than (MAX_ADDRESS - destination_buffer + 1), then LIBSPDM_ASSERT(). - * If length is greater than (MAX_ADDRESS - source_buffer + 1), then LIBSPDM_ASSERT(). - * - * @param destination_buffer A pointer to the destination buffer to compare. - * @param source_buffer A pointer to the source buffer to compare. - * @param length The number of bytes to compare. - * - * @return 0 All length bytes of the two buffers are identical. - * @retval Non-zero There is mismatched between source_buffer and destination_buffer. - * - **/ -int32_t libspdm_const_compare_mem(const void *destination_buffer, - const void *source_buffer, size_t length) -{ - const volatile uint8_t *pointer_dst; - const volatile uint8_t *pointer_src; - uint8_t delta; - - pointer_dst = (const uint8_t *)destination_buffer; - pointer_src = (const uint8_t *)source_buffer; - delta = 0; - while ((length-- != 0)) { - delta |= *(pointer_dst++) ^ *(pointer_src++); - } - - return delta; -} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c b/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c deleted file mode 100644 index a533135006..0000000000 --- a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c +++ /dev/null @@ -1,45 +0,0 @@ -/** - * Copyright Notice: - * Copyright 2022 DMTF. All rights reserved. - * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md - **/ - -#include "base.h" -#include "internal/libspdm_lib_config.h" - -#if LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP -/** - * If no heartbeat arrives in seconds, the watchdog timeout event - * should terminate the session. - * - * @param session_id Indicate the SPDM session ID. - * @param seconds heartbeat period, in seconds. - * - **/ -bool libspdm_start_watchdog(uint32_t session_id, uint16_t seconds) -{ - return true; -} - -/** - * stop watchdog. - * - * @param session_id Indicate the SPDM session ID. - * - **/ -bool libspdm_stop_watchdog(uint32_t session_id) -{ - return true; -} - -/** - * Reset the watchdog in heartbeat response. - * - * @param session_id Indicate the SPDM session ID. - * - **/ -bool libspdm_reset_watchdog(uint32_t session_id) -{ - return true; -} -#endif /* LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/base.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/base.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/base.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_aead.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_aead.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_aead.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_cert.h similarity index 85% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_cert.h index 0f0b5bca08..8bc485fa39 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_cert.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_cert.h @@ -7,6 +7,8 @@ #ifndef CRYPTLIB_CERT_H #define CRYPTLIB_CERT_H +#if LIBSPDM_CERT_PARSE_SUPPORT + /** * Retrieve the tag and length of the tag. * @@ -199,7 +201,7 @@ extern bool libspdm_x509_get_key_usage(const uint8_t *cert, size_t cert_size, si * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. * @param[out] usage Key usage bytes. - * @param[in, out] usage_size Key usage buffer sizs in bytes. + * @param[in, out] usage_size Key usage buffer size in bytes. * * @retval true * @retval false @@ -214,7 +216,7 @@ extern bool libspdm_x509_get_extended_key_usage(const uint8_t *cert, * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. * @param[out] basic_constraints Basic constraints bytes. - * @param[in, out] basic_constraints_size Basic constraints buffer sizs in bytes. + * @param[in, out] basic_constraints_size Basic constraints buffer size in bytes. * * @retval true * @retval false @@ -250,16 +252,16 @@ extern bool libspdm_x509_verify_cert(const uint8_t *cert, size_t cert_size, * * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates * where the first certificate is signed by the Root - * Certificate or is the Root Cerificate itself. and - * subsequent cerificate is signed by the preceding - * cerificate. + * Certificate or is the Root Certificate itself. and + * subsequent certificate is signed by the preceding + * certificate. * @param[in] cert_chain_length Total length of the certificate chain, in bytes. * * @param[in] root_cert Trusted Root Certificate buffer. * * @param[in] root_cert_length Trusted Root Certificate buffer length. * - * @retval true All cerificates were issued by the first certificate in X509Certchain. + * @retval true All certificates were issued by the first certificate in X509Certchain. * @retval false Invalid certificate or the certificate was not issued by the given * trusted CA. **/ @@ -272,12 +274,12 @@ extern bool libspdm_x509_verify_cert_chain(const uint8_t *root_cert, size_t root * * @param[in] cert_chain One or more ASN.1 DER-encoded X.509 certificates * where the first certificate is signed by the Root - * Certificate or is the Root Cerificate itself. and - * subsequent cerificate is signed by the preceding - * cerificate. + * Certificate or is the Root Certificate itself. and + * subsequent certificate is signed by the preceding + * certificate. * @param[in] cert_chain_length Total length of the certificate chain, in bytes. * - * @param[in] cert_index Index of certificate. If index is -1 indecate the + * @param[in] cert_index Index of certificate. If index is -1 indicates the * last certificate in cert_chain. * * @param[out] cert The certificate at the index of cert_chain. @@ -301,7 +303,7 @@ extern bool libspdm_x509_get_cert_from_cert_chain(const uint8_t *cert_chain, * * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. - * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * @param[out] rsa_context Pointer to newly generated RSA context which contain the retrieved * RSA public key component. Use libspdm_rsa_free() function to free the * resource. * @@ -319,7 +321,7 @@ extern bool libspdm_rsa_get_public_key_from_x509(const uint8_t *cert, size_t cer * * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. - * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * @param[out] ec_context Pointer to newly generated EC DSA context which contain the retrieved * EC public key component. Use libspdm_ec_free() function to free the * resource. * @@ -340,7 +342,7 @@ extern bool libspdm_ec_get_public_key_from_x509(const uint8_t *cert, size_t cert * * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. - * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * @param[out] ecd_context Pointer to newly generated Ed DSA context which contain the retrieved * Ed public key component. Use libspdm_ecd_free() function to free the * resource. * @@ -361,7 +363,7 @@ extern bool libspdm_ecd_get_public_key_from_x509(const uint8_t *cert, size_t cer * * @param[in] cert Pointer to the DER-encoded X509 certificate. * @param[in] cert_size Size of the X509 certificate in bytes. - * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * @param[out] sm2_context Pointer to newly generated sm2 context which contain the retrieved * sm2 public key component. Use sm2_free() function to free the * resource. * @@ -376,41 +378,6 @@ extern bool libspdm_sm2_get_public_key_from_x509(const uint8_t *cert, size_t cer void **sm2_context); #endif /* LIBSPDM_SM2_DSA_SUPPORT */ -#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP -/** - * Generate a CSR. - * - * @param[in] hash_nid hash algo for sign - * @param[in] asym_nid asym algo for sign - * - * @param[in] requester_info requester info to gen CSR - * @param[in] requester_info_length The len of requester info - * - * @param[in] context Pointer to asymmetric context - * @param[in] subject_name Subject name: should be break with ',' in the middle - * example: "C=AA,CN=BB" - * - * Subject names should contain a comma-separated list of OID types and values: - * The valid OID type name is in: - * {"CN", "commonName", "C", "countryName", "O", "organizationName","L", - * "OU", "organizationalUnitName", "ST", "stateOrProvinceName", "emailAddress", - * "serialNumber", "postalAddress", "postalCode", "dnQualifier", "title", - * "SN","givenName","GN", "initials", "pseudonym", "generationQualifier", "domainComponent", "DC"}. - * Note: The object of C and countryName should be CSR Supported Country Codes - * - * @param[in] csr_len For input, csr_len is the size of store CSR buffer. - * For output, csr_len is CSR len for DER format - * @param[in] csr_pointer For input, csr_pointer is buffer address to store CSR. - * For output, csr_pointer is address for stored CSR. - * The csr_pointer address will be changed. - * - * @retval true Success. - * @retval false Failed to gen CSR. - **/ -extern bool libspdm_gen_x509_csr(size_t hash_nid, size_t asym_nid, - uint8_t *requester_info, size_t requester_info_length, - void *context, char *subject_name, - size_t *csr_len, uint8_t **csr_pointer); -#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ +#endif /* LIBSPDM_CERT_PARSE_SUPPORT */ #endif /* CRYPTLIB_CERT_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_dh.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_dh.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_dh.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_ec.h similarity index 66% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_ec.h index 1b42da7037..75389a06bc 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ec.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_ec.h @@ -28,6 +28,44 @@ extern void *libspdm_ec_new_by_nid(size_t nid); * @param[in] ec_context Pointer to the EC context to be released. **/ extern void libspdm_ec_free(void *ec_context); + +#if LIBSPDM_FIPS_MODE +/** + * Sets the private key component into the established EC context. + * + * For P-256, the private_key_size is 32 byte. + * For P-384, the private_key_size is 48 byte. + * For P-521, the private_key_size is 66 byte. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] private_key Pointer to the private key buffer. + * @param[in] private_key_size The size of private key buffer in bytes. + * + * @retval true EC private key component was set successfully. + * @retval false Invalid EC private key component. + * + **/ +extern bool libspdm_ec_set_priv_key(void *ec_context, const uint8_t *private_key, + size_t private_key_size); + +/** + * Sets the public key component into the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] public Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true EC public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size); +#endif /* LIBSPDM_FIPS_MODE */ + #endif /* (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) */ #if LIBSPDM_ECDHE_SUPPORT @@ -99,6 +137,29 @@ extern bool libspdm_ec_compute_key(void *ec_context, const uint8_t *peer_public, #endif /* LIBSPDM_ECDHE_SUPPORT */ #if LIBSPDM_ECDSA_SUPPORT +/** + * Generates Elliptic Curve context from DER-encoded public key data. + * + * The public key is ASN.1 DER-encoded as RFC7250 describes, + * namely, the SubjectPublicKeyInfo structure of a X.509 certificate. + * + * @param[in] der_data Pointer to the DER-encoded public key data. + * @param[in] der_size Size of the DER-encoded public key data in bytes. + * @param[out] ec_context Pointer to newly generated EC context which contains the + * EC public key component. + * Use libspdm_ec_free() function to free the resource. + * + * If der_data is NULL, then return false. + * If ec_context is NULL, then return false. + * + * @retval true EC context was generated successfully. + * @retval false Invalid DER public key data. + * + **/ +extern bool libspdm_ec_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **ec_context); + /** * Carries out the EC-DSA signature. * @@ -132,6 +193,29 @@ extern bool libspdm_ecdsa_sign(void *ec_context, size_t hash_nid, const uint8_t *message_hash, size_t hash_size, uint8_t *signature, size_t *sig_size); +#if LIBSPDM_FIPS_MODE +/** + * Carries out the EC-DSA signature with caller input random function. This API can be used for FIPS test. + * + * @param[in] ec_context Pointer to EC context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size Size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive EC-DSA signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * @param[in] random_func random number function + * + * @retval true signature successfully generated in EC-DSA. + * @retval false signature generation failed. + * @retval false sig_size is too small. + **/ +extern bool libspdm_ecdsa_sign_ex(void *ec_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size, + int (*random_func)(void *, unsigned char *, size_t)); +#endif/*LIBSPDM_FIPS_MODE*/ + /** * Verifies the EC-DSA signature. * diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_ecd.h similarity index 58% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_ecd.h index 10cbbfb2ce..74e3bca319 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_ecd.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_ecd.h @@ -22,6 +22,29 @@ **/ extern void *libspdm_ecd_new_by_nid(size_t nid); +/** + * Generates Edwards-Curve context from DER-encoded public key data. + * + * The public key is ASN.1 DER-encoded as RFC7250 describes, + * namely, the SubjectPublicKeyInfo structure of a X.509 certificate. + * + * @param[in] der_data Pointer to the DER-encoded public key data. + * @param[in] der_size Size of the DER-encoded public key data in bytes. + * @param[out] ec_context Pointer to newly generated Ed context which contains the + * Ed public key component. + * Use libspdm_ecd_free() function to free the resource. + * + * If der_data is NULL, then return false. + * If ecd_context is NULL, then return false. + * + * @retval true Ed context was generated successfully. + * @retval false Invalid DER public key data. + * + **/ +extern bool libspdm_ecd_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **ecd_context); + /** * Release the specified Ed context. * @@ -29,6 +52,56 @@ extern void *libspdm_ecd_new_by_nid(size_t nid); **/ extern void libspdm_ecd_free(void *ecd_context); +/** + * Sets the public key component into the established Ed context. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[in] public_key Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true Ed public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ecd_set_pub_key(void *ecd_context, const uint8_t *public_key, + size_t public_key_size); + +/** + * Sets the private key component into the established Ed context. + * + * For ed25519, the private_size is 32. + * For ed448, the private_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[in] private Pointer to the buffer to receive generated private X,Y. + * @param[in] private_size The size of private buffer in bytes. + * + * @retval true Ed private key component was set successfully. + * @retval false Invalid EC private key component. + * + **/ +bool libspdm_ecd_set_pri_key(void *ecd_context, const uint8_t *private_key, + size_t private_key_size); + +/** + * Gets the public key component from the established Ed context. + * + * For ed25519, the public_size is 32. + * For ed448, the public_size is 57. + * + * @param[in, out] ecd_context Pointer to Ed context being set. + * @param[out] public Pointer to the buffer to receive generated public X,Y. + * @param[in, out] public_size On input, the size of public buffer in bytes. + * On output, the size of data returned in public buffer in bytes. + * + * @retval true Ed key component was retrieved successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ecd_get_pub_key(void *ecd_context, uint8_t *public_key, + size_t *public_key_size); + /** * Carries out the Ed-DSA signature. * diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_hash.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hash.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_hash.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_hkdf.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_hkdf.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_hkdf.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_mac.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_mac.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_mac.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_rng.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rng.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_rng.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_rsa.h similarity index 71% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_rsa.h index 6135575b3b..b7e68a3649 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_rsa.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_rsa.h @@ -35,6 +35,28 @@ typedef enum { **/ extern void *libspdm_rsa_new(void); +/** + * Generates RSA context from DER-encoded public key data. + * + * The public key is ASN.1 DER-encoded as RFC7250 describes, + * namely, the SubjectPublicKeyInfo structure of a X.509 certificate. + * + * @param[in] der_data Pointer to the DER-encoded public key data. + * @param[in] der_size Size of the DER-encoded public key data in bytes. + * @param[out] rsa_context Pointer to newly generated RSA context which contains the + * RSA public key component. + * Use libspdm_rsa_free() function to free the resource. + * + * If der_data is NULL, then return false. + * If rsa_context is NULL, then return false. + * + * @retval true RSA context was generated successfully. + * @retval false Invalid DER public key data. + **/ +extern bool libspdm_rsa_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **rsa_context); + /** * Release the specified RSA context. * @@ -67,80 +89,6 @@ extern void libspdm_rsa_free(void *rsa_context); extern bool libspdm_rsa_set_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, const uint8_t *big_number, size_t bn_size); -/** - * Gets the tag-designated RSA key component from the established RSA context. - * - * This function retrieves the tag-designated RSA key component from the - * established RSA context as a non-negative integer (octet string format - * represented in RSA PKCS#1). - * If specified key component has not been set or has been cleared, then returned - * bn_size is set to 0. - * If the big_number buffer is too small to hold the contents of the key, false - * is returned and bn_size is set to the required buffer size to obtain the key. - * - * If rsa_context is NULL, then return false. - * If bn_size is NULL, then return false. - * If bn_size is large enough but big_number is NULL, then return false. - * If this interface is not supported, then return false. - * - * @param[in, out] rsa_context Pointer to RSA context being set. - * @param[in] key_tag Tag of RSA key component being set. - * @param[out] big_number Pointer to octet integer buffer. - * @param[in, out] bn_size On input, the size of big number buffer in bytes. - * On output, the size of data returned in big number buffer in bytes. - * - * @retval true RSA key component was retrieved successfully. - * @retval false Invalid RSA key component tag. - * @retval false bn_size is too small. - * @retval false This interface is not supported. - **/ -extern bool libspdm_rsa_get_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, - uint8_t *big_number, size_t *bn_size); - -/** - * Generates RSA key components. - * - * This function generates RSA key components. It takes RSA public exponent E and - * length in bits of RSA modulus N as input, and generates all key components. - * If public_exponent is NULL, the default RSA public exponent (0x10001) will be used. - * - * If rsa_context is NULL, then return false. - * If this interface is not supported, then return false. - * - * @param[in, out] rsa_context Pointer to RSA context being set. - * @param[in] modulus_length Length of RSA modulus N in bits. - * @param[in] public_exponent Pointer to RSA public exponent. - * @param[in] public_exponent_size Size of RSA public exponent buffer in bytes. - * - * @retval true RSA key component was generated successfully. - * @retval false Invalid RSA key component tag. - * @retval false This interface is not supported. - **/ -extern bool libspdm_rsa_generate_key(void *rsa_context, size_t modulus_length, - const uint8_t *public_exponent, - size_t public_exponent_size); - -/** - * Validates key components of RSA context. - * NOTE: This function performs integrity checks on all the RSA key material, so - * the RSA key structure must contain all the private key data. - * - * This function validates key components of RSA context in following aspects: - * - Whether p is a prime - * - Whether q is a prime - * - Whether n = p * q - * - Whether d*e = 1 mod lcm(p-1,q-1) - * - * If rsa_context is NULL, then return false. - * If this interface is not supported, then return false. - * - * @param[in] rsa_context Pointer to RSA context to check. - * - * @retval true RSA key components are valid. - * @retval false RSA key components are not valid. - * @retval false This interface is not supported. - **/ -extern bool libspdm_rsa_check_key(void *rsa_context); #endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ #if LIBSPDM_RSA_SSA_SUPPORT @@ -260,5 +208,67 @@ extern bool libspdm_rsa_pss_sign(void *rsa_context, size_t hash_nid, extern bool libspdm_rsa_pss_verify(void *rsa_context, size_t hash_nid, const uint8_t *message_hash, size_t hash_size, const uint8_t *signature, size_t sig_size); + +#if LIBSPDM_FIPS_MODE +/** + * Carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme for FIPS test. + * + * This function carries out the RSA-SSA signature generation with EMSA-PSS encoding scheme defined in + * RSA PKCS#1 v2.2 for FIPS test. + * + * The salt length is zero. + * + * If the signature buffer is too small to hold the contents of signature, false + * is returned and sig_size is set to the required buffer size to obtain the signature. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, SHA3_512. + * If sig_size is large enough but signature is NULL, then return false. + * + * @param[in] rsa_context Pointer to RSA context for signature generation. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be signed. + * @param[in] hash_size size of the message hash in bytes. + * @param[out] signature Pointer to buffer to receive RSA-SSA PSS signature. + * @param[in, out] sig_size On input, the size of signature buffer in bytes. + * On output, the size of data returned in signature buffer in bytes. + * + * @retval true signature successfully generated in RSA-SSA PSS. + * @retval false signature generation failed. + * @retval false sig_size is too small. + * + **/ +extern bool libspdm_rsa_pss_sign_fips(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size); + +/** + * Verifies the RSA-SSA signature with EMSA-PSS encoding scheme defined in + * RSA PKCS#1 v2.2 for FIPS test. + * + * The salt length is zero. + * + * If rsa_context is NULL, then return false. + * If message_hash is NULL, then return false. + * If signature is NULL, then return false. + * If hash_size need match the hash_nid. nid could be SHA256, SHA384, SHA512, SHA3_256, SHA3_384, SHA3_512. + * + * @param[in] rsa_context Pointer to RSA context for signature verification. + * @param[in] hash_nid hash NID + * @param[in] message_hash Pointer to octet message hash to be checked. + * @param[in] hash_size size of the message hash in bytes. + * @param[in] signature Pointer to RSA-SSA PSS signature to be verified. + * @param[in] sig_size size of signature in bytes. + * + * @retval true Valid signature encoded in RSA-SSA PSS. + * @retval false Invalid signature or invalid RSA context. + * + **/ +extern bool libspdm_rsa_pss_verify_fips(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); +#endif /*LIBSPDM_FIPS_MODE*/ + #endif /* LIBSPDM_RSA_PSS_SUPPORT */ #endif /* CRYPTLIB_RSA_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_sm2.h similarity index 89% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_sm2.h index 2b382b9394..b733331892 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/cryptlib/cryptlib_sm2.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/cryptlib/cryptlib_sm2.h @@ -22,6 +22,29 @@ **/ extern void *libspdm_sm2_dsa_new_by_nid(size_t nid); +/** + * Generates Shang-Mi2 context from DER-encoded public key data. + * + * The public key is ASN.1 DER-encoded as RFC7250 describes, + * namely, the SubjectPublicKeyInfo structure of a X.509 certificate. + * + * @param[in] der_data Pointer to the DER-encoded public key data. + * @param[in] der_size Size of the DER-encoded public key data in bytes. + * @param[out] sm2_context Pointer to newly generated SM2 context which contains the + * SM2 public key component. + * Use libspdm_sm2_free() function to free the resource. + * + * If der_data is NULL, then return false. + * If sm2_context is NULL, then return false. + * + * @retval true SM2 context was generated successfully. + * @retval false Invalid DER public key data. + * + **/ +extern bool libspdm_sm2_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **sm2_context); + /** * Release the specified sm2 context. * diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/debuglib.h similarity index 99% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/debuglib.h index 9f638beb65..3376e6e6cb 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/hal/library/debuglib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/debuglib.h @@ -15,6 +15,7 @@ * an image. **/ +#include "hal/base.h" #include "internal/libspdm_lib_config.h" #if LIBSPDM_DEBUG_PRINT_ENABLE diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/memlib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/memlib.h new file mode 100644 index 0000000000..af1dacc7a8 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/memlib.h @@ -0,0 +1,69 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +/** + * Provides memory copy, fill, and comparison. + **/ + +#ifndef MEMLIB_H +#define MEMLIB_H + +#include "hal/base.h" + +/** + * Copies bytes from a source buffer to a destination buffer. + * + * This function copies src_len bytes from src_buf to dst_buf. The following properties are required + * of the caller: + * - dst_buf and src_buf are non-NULL. + * - src_len is less than or equal to dst_len. + * - The source and destination buffers do not overlap. + * + * The implementer of this function is free to check that these properties hold and take action, + * such as assertion handling, if the properties are violated. + * + * @param dst_buf Destination buffer to copy to. + * @param dst_len Size, in bytes, of the destination buffer. + * @param src_buf Source buffer to copy from. + * @param src_len The number of bytes to copy from the source buffer. + **/ +void libspdm_copy_mem(void *dst_buf, size_t dst_len, + const void *src_buf, size_t src_len); + +/** + * Fills a target buffer with a byte value. + * + * @param buffer The memory to set. + * @param length The number of bytes to set. + * @param value The value with which to fill length bytes of buffer. + **/ +void libspdm_set_mem(void *buffer, size_t length, uint8_t value); + +/** + * Fills a target buffer with zeros. + * + * @param buffer The pointer to the target buffer to fill with zeros. + * @param length The number of bytes in buffer to fill with zeros. + **/ +void libspdm_zero_mem(void *buffer, size_t length); + +/** + * Compares the contents of two buffers in constant time. + * + * For a given length, the time to complete the comparison is always the same regardless of the + * contents of the two buffers. + * + * @param destination_buffer A pointer to the destination buffer to compare. + * @param source_buffer A pointer to the source buffer to compare. + * @param length The number of bytes to compare. + * + * @return true The contents of the two buffers are the same. + * @retval false The contents of the two buffers are not the same. + **/ +bool libspdm_consttime_is_mem_equal(const void *destination_buffer, + const void *source_buffer, size_t length); + +#endif /* MEMLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/psklib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/psklib.h new file mode 100644 index 0000000000..cc9b5a0b76 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/psklib.h @@ -0,0 +1,58 @@ +/** + * Copyright Notice: + * Copyright 2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef REQUESTER_PSKLIB_H +#define REQUESTER_PSKLIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF + * algorithm. + * + * @param base_hash_algo Indicates the hash algorithm. + * @param psk_hint Pointer to the peer-provided PSK Hint. + * @param psk_hint_size PSK Hint size in bytes. + * @param info Pointer to the application specific info. + * @param info_size Info size in bytes. + * @param out Pointer to buffer to receive HKDF value. + * @param out_size Size of HKDF bytes to generate. + * + * @retval true HKDF generated successfully. + * @retval false HKDF generation failed. + **/ +extern bool libspdm_psk_handshake_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, const uint8_t *psk_hint, + size_t psk_hint_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size); + +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF + * algorithm. + * + * @param base_hash_algo Indicates the hash algorithm. + * @param psk_hint Pointer to the peer-provided PSK Hint. + * @param psk_hint_size PSK Hint size in bytes. + * @param info Pointer to the application specific info. + * @param info_size Info size in bytes. + * @param out Pointer to buffer to receive HKDF value. + * @param out_size Size of HKDF bytes to generate. + * + * @retval true HKDF generated successfully. + * @retval false HKDF generation failed. + **/ +extern bool libspdm_psk_master_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + const uint8_t *psk_hint, size_t psk_hint_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ + +#endif /* REQUESTER_PSKLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/reqasymsignlib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/reqasymsignlib.h new file mode 100644 index 0000000000..252a62d8b3 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/reqasymsignlib.h @@ -0,0 +1,71 @@ +/** + * Copyright Notice: + * Copyright 2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef REQUESTER_REQASYMSIGNLIB_H +#define REQUESTER_REQASYMSIGNLIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +/** + * Sign an SPDM message data. + * + * @param req_base_asym_alg Indicates the signing algorithm. + * @param base_hash_algo Indicates the hash algorithm. + * @param is_data_hash Indicates the message type. + * If true, raw message before hash. + * If false, message hash. + * @param message A pointer to a message to be signed. + * @param message_size The size in bytes of the message to be signed. + * @param signature A pointer to a destination buffer to store the signature. + * @param sig_size On input, indicates the size, in bytes, of the destination buffer to + * store the signature. + * On output, indicates the size, in bytes, of the signature in the + * buffer. + * + * @retval true signing success. + * @retval false signing fail. + **/ +extern bool libspdm_requester_data_sign( + spdm_version_number_t spdm_version, + uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size); + +#if LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP +/** + * This functions returns the opaque data in a CHALLENGE_AUTH response. + * + * @param spdm_version Indicates the negotiated s version. + * + * @param slot_id The number of slot for the certificate chain. + * + * @param measurement_summary_hash The measurement summary hash. + * @param measurement_summary_hash_size The size of measurement summary hash. + * + * @param opaque_data + * A pointer to a destination buffer whose size, in bytes, is opaque_data_size. The opaque data is + * copied to this buffer. + * + * @param opaque_data_size + * On input, indicates the size, in bytes, of the destination buffer. + * On output, indicates the size of the opaque data. + **/ +extern bool libspdm_encap_challenge_opaque_data( + spdm_version_number_t spdm_version, + uint8_t slot_id, + uint8_t *measurement_summary_hash, + size_t measurement_summary_hash_size, + void *opaque_data, + size_t *opaque_data_size); +#endif/*LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP*/ + +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + +#endif /* REQUESTER_REQASYMSIGNLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/timelib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/timelib.h new file mode 100644 index 0000000000..faab129ea4 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/requester/timelib.h @@ -0,0 +1,19 @@ +/** + * Copyright Notice: + * Copyright 2022-2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ +#ifndef REQUESTER_TIMELIB_H +#define REQUESTER_TIMELIB_H + +#include "hal/base.h" + +/** + * Suspends the execution of the current thread until the interval elapses. + * + * @param duration The time interval, in units of microseconds for which execution is to be + * suspended. + **/ +extern void libspdm_sleep(uint64_t duration); + +#endif /* REQUESTER_TIMERLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/asymsignlib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/asymsignlib.h new file mode 100644 index 0000000000..ff7ced3ad7 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/asymsignlib.h @@ -0,0 +1,68 @@ +/** + * Copyright Notice: + * Copyright 2021-2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef RESPONDER_ASYMSIGNLIB_H +#define RESPONDER_ASYMSIGNLIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" +#include "library/spdm_return_status.h" +#include "industry_standard/spdm.h" + +#if LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP +/** + * This functions returns the opaque data in a CHALLENGE_AUTH response. + * + * @param spdm_version Indicates the negotiated s version. + * + * @param slot_id The number of slot for the certificate chain. + * + * @param measurement_summary_hash The measurement summary hash. + * @param measurement_summary_hash_size The size of measurement summary hash. + * + * @param opaque_data + * A pointer to a destination buffer whose size, in bytes, is opaque_data_size. The opaque data is + * copied to this buffer. + * + * @param opaque_data_size + * On input, indicates the size, in bytes, of the destination buffer. + * On output, indicates the size of the opaque data. + **/ +extern bool libspdm_challenge_opaque_data( + spdm_version_number_t spdm_version, + uint8_t slot_id, + uint8_t *measurement_summary_hash, + size_t measurement_summary_hash_size, + void *opaque_data, + size_t *opaque_data_size); +#endif/*LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP*/ + +/** + * Sign an SPDM message data. + * + * @param base_asym_algo Indicates the signing algorithm. + * @param base_hash_algo Indicates the hash algorithm. + * @param is_data_hash Indicate the message type. + * If true, raw message before hash. + * If false, message hash. + * @param message A pointer to a message to be signed. + * @param message_size The size, in bytes, of the message to be signed. + * @param signature A pointer to a destination buffer to store the signature. + * @param sig_size On input, indicates the size, in bytes, of the destination buffer to + * store the signature. + * On output, indicates the size, in bytes, of the signature in the buffer. + * + * @retval true Signing success. + * @retval false Signing fail. + **/ +extern bool libspdm_responder_data_sign( + spdm_version_number_t spdm_version, + uint8_t op_code, uint32_t base_asym_algo, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size); + +#endif /* RESPONDER_ASYMSIGNLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/csrlib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/csrlib.h new file mode 100644 index 0000000000..6d5a2287fd --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/csrlib.h @@ -0,0 +1,53 @@ +/** + * Copyright Notice: + * Copyright 2021-2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef RESPONDER_CSRLIB_H +#define RESPONDER_CSRLIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" +#include "library/spdm_return_status.h" +#include "industry_standard/spdm.h" + +#if LIBSPDM_ENABLE_CAPABILITY_CSR_CAP +/** + * Gen CSR + * + * @param[in] base_hash_algo Indicates the signing algorithm. + * @param[in] base_asym_algo Indicates the hash algorithm. + * @param[in] need_reset If true, then device needs to be reset to complete the CSR. + * If false + * + * @param[in] request A pointer to the SPDM request data. + * @param[in] request_size The size of SPDM request data. + * + * @param[in] requester_info Requester info to generate the CSR. + * @param[in] requester_info_length The length of requester info. + * + * @param[in] opaque_data opaque data to generate the CSR. + * @param[in] opaque_data_length The length of opaque data. + * + * @param[in] csr_len For input, csr_len is the size of store CSR buffer. + * For output, csr_len is CSR len for DER format + * @param[in] csr_pointer On input, csr_pointer is buffer address to store CSR. + * On output, csr_pointer is address for stored CSR. + * The csr_pointer address will be changed. + * + * @param[in] is_device_cert_model If true, the cert chain is DeviceCert model. + * If false, the cert chain is AliasCert model. + * + * @retval true Success. + * @retval false Failed to gen CSR. + **/ +extern bool libspdm_gen_csr(uint32_t base_hash_algo, uint32_t base_asym_algo, bool *need_reset, + const void *request, size_t request_size, + uint8_t *requester_info, size_t requester_info_length, + uint8_t *opaque_data, uint16_t opaque_data_length, + size_t *csr_len, uint8_t *csr_pointer, + bool is_device_cert_model); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CSR_CAP */ + +#endif /* RESPONDER_CSRLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/measlib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/measlib.h new file mode 100644 index 0000000000..ff1cf77daf --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/measlib.h @@ -0,0 +1,141 @@ +/** + * Copyright Notice: + * Copyright 2021-2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef RESPONDER_MEASLIB_H +#define RESPONDER_MEASLIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" +#include "library/spdm_return_status.h" +#include "industry_standard/spdm.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP +/** + * Collect the device measurement. + * + * libspdm will call this function to retrieve the measurements for a device. + * The "measurement_index" parameter indicates the measurement requested. + * + * @param spdm_version Indicates the negotiated SPDM version. + * + * @param measurement_specification Indicates the measurement specification. + * Must be a SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_* value in spdm.h. + * + * @param measurement_hash_algo Indicates the measurement hash algorithm. + * Must be SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_* value in spdm.h. + * + * @param measurement_index The index of the measurement to collect. + * A value of 0x00 requests only the total number of measurements to be returned in + * "measurements_count". The parameters "measurements" and "measurements_size" will be left + * unmodified. + * + * A value of [0x01 - 0xFE] requests a single measurement for that measurement index + * be returned. On success, "measurements_count" will be set to 1 and the + * "measurements" and "measurements_size" fields will be set based + * on the single measurement. An invalid measurement index will cause + * "measurements_count" to return 0. + * + * A value of 0xFF requests all measurements be returned. + * On success, "measurements_count", "measurements", and "measurements_size" + * fields will be set with data from all measurements. + * + * @param request_attribute A bitmask who fields are SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_*. + * + * @param measurements_count + * When "measurement_index" is zero, returns the total count of + * measurements available for the device. None of the actual measurements are + * returned however, and "measurements" and "measurements_size" are unmodified. + * + * When "measurement_index" is non-zero, returns the number of measurements + * returned in "measurements" and "measurements_size". If "measurements_index" + * is an invalid index not supported by the device, "measurements_count" will + * return 0 and the function will return LIBSPDM_STATUS_MEAS_INVALID_INDEX. + * + * @param measurements + * A pointer to a destination buffer to store the concatenation of all device + * measurement blocks. This buffer will only be modified if "measurement_index" is non-zero. + * + * @param measurements_size + * On input, indicates the size in bytes of the destination buffer. + * On output, indicates the total size in bytes of all device measurement + * blocks in the buffer. This field should only be modified if "measurement_index" is non-zero. + **/ +extern libspdm_return_t libspdm_measurement_collection( + spdm_version_number_t spdm_version, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_index, + uint8_t request_attribute, + uint8_t *content_changed, + uint8_t *measurements_count, + void *measurements, + size_t *measurements_size); + +/** + * This functions returns the opaque data in a MEASUREMENTS response. + * + * It is called immediately after libspdm_measurement_collection() is called and allows the opaque + * data field to vary based on the GET_MEASUREMENTS request. + * + * @param spdm_version Indicates the negotiated SPDM version. + * + * @param measurement_specification Indicates the measurement specification. + * Must be a SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_* value in spdm.h. + * + * @param measurement_hash_algo Indicates the measurement hash algorithm. + * Must be SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_* value in spdm.h. + * + * @param measurement_index The index of the measurement to collect. + * + * @param request_attribute A bitmask who fields are SPDM_GET_MEASUREMENTS_REQUEST_ATTRIBUTES_*. + * + * @param opaque_data + * A pointer to a destination buffer whose size, in bytes, is opaque_data_size. The opaque data is + * copied to this buffer. + * + * @param opaque_data_size + * On input, indicates the size, in bytes, of the destination buffer. + * On output, indicates the size of the opaque data. + **/ +extern bool libspdm_measurement_opaque_data( + spdm_version_number_t spdm_version, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_index, + uint8_t request_attribute, + void *opaque_data, + size_t *opaque_data_size); + +/** + * This function calculates the measurement summary hash. + * + * @param spdm_version The SPDM version. + * @param base_hash_algo The hash algo to use on summary. + * @param measurement_specification Indicates the measurement specification. + * It must align with measurement_specification. + * (SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_*) + * @param measurement_hash_algo Indicates the measurement hash algorithm. + * It must align with measurement_hash_alg + * (SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_*) + * + * @param measurement_summary_hash_type The type of the measurement summary hash. + * @param measurement_summary_hash The buffer to store the measurement summary hash. + * @param measurement_summary_hash_size The size in bytes of the buffer. + * + * @retval true measurement summary hash is generated or skipped. + * @retval false measurement summary hash is not generated. + **/ +extern bool libspdm_generate_measurement_summary_hash( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_summary_hash_type, + uint8_t *measurement_summary_hash, + uint32_t measurement_summary_hash_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + +#endif /* RESPONDER_MEASLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/psklib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/psklib.h new file mode 100644 index 0000000000..c6aa0b29b6 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/psklib.h @@ -0,0 +1,60 @@ +/** + * Copyright Notice: + * Copyright 2021-2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef RESPONDER_PSKLIB_H +#define RESPONDER_PSKLIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" +#include "library/spdm_return_status.h" +#include "industry_standard/spdm.h" + +#if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF + * algorithm. + * + * @param base_hash_algo Indicates the hash algorithm. + * @param psk_hint Pointer to the peer-provided PSK Hint. + * @param psk_hint_size PSK Hint size in bytes. + * @param info Pointer to the application specific info. + * @param info_size Info size in bytes. + * @param out Pointer to buffer to receive HKDF value. + * @param out_size Size of HKDF bytes to generate. + * + * @retval true HKDF generated successfully. + * @retval false HKDF generation failed. + **/ +extern bool libspdm_psk_handshake_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, const uint8_t *psk_hint, + size_t psk_hint_size, const uint8_t *info, + size_t info_size, uint8_t *out, size_t out_size); + +/** + * Derive HMAC-based Expand key Derivation Function (HKDF) Expand, based upon the negotiated HKDF + * algorithm. + * + * @param base_hash_algo Indicates the hash algorithm. + * @param psk_hint Pointer to the peer-provided PSK Hint. + * @param psk_hint_size PSK Hint size in bytes. + * @param info Pointer to the application specific info. + * @param info_size Info size in bytes. + * @param out Pointer to buffer to receive HKDF value. + * @param out_size Size of HKDF bytes to generate. + * + * @retval true HKDF generated successfully. + * @retval false HKDF generation failed. + **/ +extern bool libspdm_psk_master_secret_hkdf_expand( + spdm_version_number_t spdm_version, + uint32_t base_hash_algo, + const uint8_t *psk_hint, size_t psk_hint_size, + const uint8_t *info, size_t info_size, + uint8_t *out, size_t out_size); +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ + +#endif /* RESPONDER_PSKLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/setcertlib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/setcertlib.h new file mode 100644 index 0000000000..860281ab24 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/hal/library/responder/setcertlib.h @@ -0,0 +1,43 @@ +/** + * Copyright Notice: + * Copyright 2021-2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef RESPONDER_SETCERTLIB_H +#define RESPONDER_SETCERTLIB_H + +#include "hal/base.h" +#include "internal/libspdm_lib_config.h" +#include "library/spdm_return_status.h" +#include "industry_standard/spdm.h" + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP +/** + * return if current code is running in a trusted environment. + * + * @retval true It is in a trusted environment. + * @retval false It is not in a trusted environment. + **/ +extern bool libspdm_is_in_trusted_environment(); + +/** + * Stores a certificate chain in non-volatile memory. + * + * + * @param[in] slot_id The number of slot for the certificate chain. + * @param[in] cert_chain The pointer for the certificate chain to set. + * @param[in] cert_chain_size The size of the certificate chain to set. + * @param[in] base_hash_algo Indicates the negotiated hash algorithm. + * @param[in] base_asym_algo Indicates the negotiated signing algorithms. + * + * @retval true The certificate chain was successfully written to non-volatile memory. + * @retval false Unable to write certificate chain to non-volatile memory. + **/ +extern bool libspdm_write_certificate_to_nvm(uint8_t slot_id, const void * cert_chain, + size_t cert_chain_size, + uint32_t base_hash_algo, uint32_t base_asym_algo); + +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP */ + +#endif /* RESPONDER_SETCERTLIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/industry_standard/spdm.h similarity index 84% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/industry_standard/spdm.h index fd599c8bf3..a1690398e2 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/industry_standard/spdm.h @@ -168,9 +168,25 @@ typedef struct { #define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP 0x00004000 #define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP 0x00008000 #define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PUB_KEY_ID_CAP 0x00010000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_11_MASK ( \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHAL_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCRYPT_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MAC_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_MUT_AUTH_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PSK_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCAP_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HBEAT_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_PUB_KEY_ID_CAP) /* SPDM GET_CAPABILITIES request flags (1.2) */ #define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP 0x00020000 +#define SPDM_GET_CAPABILITIES_REQUEST_FLAGS_12_MASK ( \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_11_MASK | \ + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP) /* SPDM GET_CAPABILITIES response flags (1.0) */ #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP 0x00000001 @@ -180,6 +196,12 @@ typedef struct { #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG 0x00000008 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG 0x00000010 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP 0x00000020 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_10_MASK ( \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP) /* SPDM GET_CAPABILITIES response flags (1.1) */ #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP 0x00000040 @@ -194,6 +216,18 @@ typedef struct { #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP 0x00004000 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP 0x00008000 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PUB_KEY_ID_CAP 0x00010000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_11_MASK ( \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_10_MASK | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCRYPT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MAC_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MUT_AUTH_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCAP_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HBEAT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HANDSHAKE_IN_THE_CLEAR_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PUB_KEY_ID_CAP) /* SPDM GET_CAPABILITIES request flags (1.2) */ #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP 0x00020000 @@ -203,6 +237,13 @@ typedef struct { #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_SET_CERT_CAP 0x00080000 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CSR_CAP 0x00100000 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_INSTALL_RESET_CAP 0x00200000 +#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_12_MASK ( \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_11_MASK | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ALIAS_CERT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_SET_CERT_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CSR_CAP | \ + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_INSTALL_RESET_CAP) /* SPDM NEGOTIATE_ALGORITHMS request */ typedef struct { @@ -240,6 +281,7 @@ typedef struct { * uint32_t alg_external[ext_alg_count];*/ } spdm_negotiate_algorithms_struct_table_t; +#define SPDM_NEGOTIATE_ALGORITHMS_MAX_NUM_STRUCT_TABLE_ALG 4 #define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE 2 #define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD 3 #define SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG 4 @@ -337,8 +379,9 @@ typedef struct { #define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SM3_256 0x00000080 /* SPDM Opaque Data Format (1.2) */ -#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_0 0x00000001 -#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_1 0x00000002 +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_NONE 0x0 +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_0 0x1 +#define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_1 0x2 #define SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_MASK 0xF /* SPDM Opaque Data Format 1 (1.2) */ @@ -356,15 +399,18 @@ typedef struct { } spdm_extended_algorithm_t; /* SPDM registry_id */ -#define SPDM_REGISTRY_ID_DMTF 0 -#define SPDM_REGISTRY_ID_TCG 1 -#define SPDM_REGISTRY_ID_USB 2 -#define SPDM_REGISTRY_ID_PCISIG 3 -#define SPDM_REGISTRY_ID_IANA 4 -#define SPDM_REGISTRY_ID_HDBASET 5 -#define SPDM_REGISTRY_ID_MIPI 6 -#define SPDM_REGISTRY_ID_CXL 7 -#define SPDM_REGISTRY_ID_JEDEC 8 +#define SPDM_REGISTRY_ID_DMTF 0x0 +#define SPDM_REGISTRY_ID_TCG 0x1 +#define SPDM_REGISTRY_ID_USB 0x2 +#define SPDM_REGISTRY_ID_PCISIG 0x3 +#define SPDM_REGISTRY_ID_IANA 0x4 +#define SPDM_REGISTRY_ID_HDBASET 0x5 +#define SPDM_REGISTRY_ID_MIPI 0x6 +#define SPDM_REGISTRY_ID_CXL 0x7 +#define SPDM_REGISTRY_ID_JEDEC 0x8 +#define SPDM_REGISTRY_ID_VESA 0x9 +#define SPDM_REGISTRY_ID_IANA_CBOR 0xa +#define SPDM_REGISTRY_ID_MAX 0xa /* SPDM GET_DIGESTS request */ typedef struct { @@ -424,6 +470,9 @@ typedef struct { /*uint8_t certificates[length - 4 - hash_size];*/ } spdm_cert_chain_t; +/* Maximum size, in bytes, of a certificate chain. */ +#define SPDM_MAX_CERTIFICATE_CHAIN_SIZE 65535 + /* SPDM CHALLENGE request */ typedef struct { spdm_message_header_t header; @@ -445,10 +494,16 @@ typedef struct { * uint8_t signature[key_size];*/ } spdm_challenge_auth_response_t; -/* SPDM CHALLENGE request HashType */ -#define SPDM_CHALLENGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH 0 -#define SPDM_CHALLENGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH 1 -#define SPDM_CHALLENGE_REQUEST_ALL_MEASUREMENTS_HASH 0xFF +/* SPDM generic request measurement summary HashType */ +#define SPDM_REQUEST_NO_MEASUREMENT_SUMMARY_HASH 0 +#define SPDM_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH 1 +#define SPDM_REQUEST_ALL_MEASUREMENTS_HASH 0xFF + +/* SPDM CHALLENGE request measurement summary HashType */ +#define SPDM_CHALLENGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH SPDM_REQUEST_NO_MEASUREMENT_SUMMARY_HASH +#define SPDM_CHALLENGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH \ + SPDM_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH +#define SPDM_CHALLENGE_REQUEST_ALL_MEASUREMENTS_HASH SPDM_REQUEST_ALL_MEASUREMENTS_HASH #define SPDM_CHALLENGE_AUTH_RESPONSE_ATTRIBUTE_SLOT_ID_MASK 0xF #define SPDM_CHALLENGE_AUTH_RESPONSE_ATTRIBUTE_BASIC_MUT_AUTH_REQ 0x00000080 /* Deprecated in SPDM 1.2*/ @@ -489,7 +544,7 @@ typedef struct { /*uint8_t measurement[measurement_size];*/ } spdm_measurement_block_common_header_t; -#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF 0x00000001 +#define SPDM_MEASUREMENT_SPECIFICATION_DMTF 0x01 /* SPDM MEASUREMENTS block DMTF header */ typedef struct { @@ -522,9 +577,9 @@ typedef struct { /* SPDM MEASUREMENTS device mode */ typedef struct { - uint32_t operational_mode_capabilties; + uint32_t operational_mode_capabilities; uint32_t operational_mode_state; - uint32_t device_mode_capabilties; + uint32_t device_mode_capabilities; uint32_t device_mode_state; } spdm_measurements_device_mode_t; @@ -591,7 +646,6 @@ typedef struct { #define SPDM_ERROR_CODE_VENDOR_DEFINED 0xFF /* SPDM error code (1.1) */ -#define SPDM_ERROR_CODE_INVALID_SESSION 0x02 /* Deprecated in SPDM 1.2*/ #define SPDM_ERROR_CODE_DECRYPT_ERROR 0x06 #define SPDM_ERROR_CODE_REQUEST_IN_FLIGHT 0x08 #define SPDM_ERROR_CODE_INVALID_RESPONSE_CODE 0x09 @@ -683,10 +737,12 @@ typedef struct { /* SPDM KEY_EXCHANGE request session_policy */ #define SPDM_KEY_EXCHANGE_REQUEST_SESSION_POLICY_TERMINATION_POLICY_RUNTIME_UPDATE 0x00000001 -/* SPDM KEY_EXCHANGE request HashType */ -#define SPDM_KEY_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH 0 -#define SPDM_KEY_EXCHANGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH 1 -#define SPDM_KEY_EXCHANGE_REQUEST_ALL_MEASUREMENTS_HASH 0xFF +/* SPDM KEY_EXCHANGE request measurement summary HashType */ +#define SPDM_KEY_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH \ + SPDM_REQUEST_NO_MEASUREMENT_SUMMARY_HASH +#define SPDM_KEY_EXCHANGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH \ + SPDM_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH +#define SPDM_KEY_EXCHANGE_REQUEST_ALL_MEASUREMENTS_HASH SPDM_REQUEST_ALL_MEASUREMENTS_HASH /* SPDM KEY_EXCHANGE response */ typedef struct { @@ -759,6 +815,13 @@ typedef struct { * uint8_t opaque_data[opaque_length];*/ } spdm_psk_exchange_request_t; +/* SPDM PSK_EXCHANGE request measurement summary HashType */ +#define SPDM_PSK_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH \ + SPDM_REQUEST_NO_MEASUREMENT_SUMMARY_HASH +#define SPDM_PSK_EXCHANGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH \ + SPDM_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH +#define SPDM_PSK_EXCHANGE_REQUEST_ALL_MEASUREMENTS_HASH SPDM_REQUEST_ALL_MEASUREMENTS_HASH + /* SPDM PSK_EXCHANGE response */ typedef struct { spdm_message_header_t header; @@ -907,6 +970,9 @@ typedef struct { * uint8_t opaque_data[opaque_data_length]; */ } spdm_get_csr_request_t; +/* Maximum size, in bytes, of a CSR. */ +#define SPDM_MAX_CSR_SIZE 65535 + /* SPDM CSR response */ typedef struct { spdm_message_header_t header; @@ -986,7 +1052,29 @@ typedef struct { **/ #define SPDM_ST1_VALUE_US 100000 -#define SPDM_OID_EXTENSION {0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x06} -#define SPDM_OID_HARDWARE_IDENTITY {0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x02} +/* id-DMTF 1.3.6.1.4.1.412 */ +#define SPDM_OID_DMTF \ + { /*0x06, 0x07,*/ 0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C } +/* id-DMTF-spdm, { id-DMTF 274 }, 1.3.6.1.4.1.412.274 */ +#define SPDM_OID_DMTF_SPDM \ + { /*0x06, 0x09,*/ 0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12 } +/* id-DMTF-device-info, { id-DMTF-spdm 1 }, 1.3.6.1.4.1.412.274.1 */ +#define SPDM_OID_DMTF_DEVICE_INFO \ + { /*0x06, 0x0A,*/ 0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x01 } +/* id-DMTF-hardware-identity, { id-DMTF-spdm 2 }, 1.3.6.1.4.1.412.274.2 */ +#define SPDM_OID_DMTF_HARDWARE_IDENTITY \ + { /*0x06, 0x0A,*/ 0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x02 } +/* id-DMTF-eku-responder-auth, { id-DMTF-spdm 3 }, 1.3.6.1.4.1.412.274.3 */ +#define SPDM_OID_DMTF_EKU_RESPONDER_AUTH \ + { /*0x06, 0x0A,*/ 0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x03 } +/* id-DMTF-eku-requester-auth, { id-DMTF-spdm 4 }, 1.3.6.1.4.1.412.274.4 */ +#define SPDM_OID_DMTF_EKU_REQUESTER_AUTH \ + { /*0x06, 0x0A,*/ 0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x04 } +/* id-DMTF-mutable-certificate, { id-DMTF-spdm 5 }, 1.3.6.1.4.1.412.274.5 */ +#define SPDM_OID_DMTF_MUTABLE_CERTIFICATE \ + { /*0x06, 0x0A,*/ 0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x05 } +/* id-DMTF-SPDM-extension, { id-DMTF-spdm 6 }, 1.3.6.1.4.1.412.274.6 */ +#define SPDM_OID_DMTF_SPDM_EXTENSION \ + { /*0x06, 0x0A,*/ 0x2B, 0x06, 0x01, 0x04, 0x01, 0x83, 0x1C, 0x82, 0x12, 0x06 } #endif /* SPDM_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/industry_standard/spdm_secured_message.h similarity index 94% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/industry_standard/spdm_secured_message.h index 70869e4cf5..15983cb0aa 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/industry_standard/spdm_secured_message.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/industry_standard/spdm_secured_message.h @@ -42,7 +42,7 @@ * V * +---------------------------------+-------+---+ * |SPDM_SECURED_MESSAGE_ADATA_HEADER|AppData|MAC| - * | SessionId | SeqNum (T) | length | | | + * | SessionId | SeqNum (O) | length | | | * +---------------------------------+-------+---+ * | | | * ----------------------------------------- --- @@ -51,6 +51,11 @@ * AssociatedData AeadTag */ +/* 2 means SPDM secured message version 1.0, 1.1 */ +#define SECURED_SPDM_MAX_VERSION_COUNT 2 +/* the DSP0277 specification version */ +#define SECURED_SPDM_VERSION_10 0x10 +#define SECURED_SPDM_VERSION_11 0x11 typedef struct { uint32_t session_id; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_common_lib.h similarity index 67% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_common_lib.h index f33d915985..5e9bb63a08 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_common_lib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_common_lib.h @@ -11,9 +11,22 @@ #include "library/spdm_secured_message_lib.h" #include "library/spdm_return_status.h" #include "library/spdm_crypt_lib.h" -#include "library/spdm_device_secret_lib.h" +#include "hal/library/debuglib.h" +#include "hal/library/memlib.h" +#include "hal/library/requester/reqasymsignlib.h" +#include "hal/library/requester/psklib.h" +#include "hal/library/responder/asymsignlib.h" +#include "hal/library/responder/csrlib.h" +#include "hal/library/responder/measlib.h" +#include "hal/library/responder/psklib.h" +#include "hal/library/responder/setcertlib.h" +#include "hal/library/cryptlib.h" #define INVALID_SESSION_ID 0 +#define LIBSPDM_MAX_CT_EXPONENT 31 +#define LIBSPDM_MAX_RDT_EXPONENT 31 + +#define LIBSPDM_MAX_SPDM_SESSION_SEQUENCE_NUMBER 0xFFFFFFFFFFFFFFFFull typedef struct { uint8_t spdm_version_count; @@ -26,7 +39,10 @@ typedef struct { uint32_t st1; uint32_t flags; uint32_t data_transfer_size; + uint32_t sender_data_transfer_size; uint32_t max_spdm_msg_size; + uint32_t transport_header_size; + uint32_t transport_tail_size; } libspdm_device_capability_t; typedef struct { @@ -63,32 +79,20 @@ typedef struct { /* My Certificate */ const void *local_cert_chain_provision[SPDM_MAX_SLOT_COUNT]; size_t local_cert_chain_provision_size[SPDM_MAX_SLOT_COUNT]; - /* My provisioned certificate (for slot_id - 0xFF, default 0)*/ - uint8_t provisioned_slot_id; + /* My raw public key (slot_id - 0xFF) */ + const void *local_public_key_provision; + size_t local_public_key_provision_size; /* Peer Root Certificate */ const void *peer_root_cert_provision[LIBSPDM_MAX_ROOT_CERT_SUPPORT]; size_t peer_root_cert_provision_size[LIBSPDM_MAX_ROOT_CERT_SUPPORT]; - - /* Peer CertificateChain - * Whether it contains the root certificate or not, - * it should be equal to the one returned from peer by get_certificate*/ - const void *peer_cert_chain_provision; - size_t peer_cert_chain_provision_size; + /* Peer raw public key (slot_id - 0xFF) */ + const void *peer_public_key_provision; + size_t peer_public_key_provision_size; /* Peer Cert verify*/ libspdm_verify_spdm_cert_chain_func verify_peer_spdm_cert_chain; - /* PSK provision locally*/ - size_t psk_hint_size; - const void *psk_hint; - - /* opaque_data provision locally*/ - size_t opaque_challenge_auth_rsp_size; - uint8_t *opaque_challenge_auth_rsp; - size_t opaque_measurement_rsp_size; - uint8_t *opaque_measurement_rsp; - /* Responder policy*/ bool basic_mut_auth_requested; uint8_t mut_auth_requested; @@ -119,6 +123,11 @@ typedef struct { /* Local Used CertificateChain (for responder, or requester in mut auth) */ const uint8_t *local_used_cert_chain_buffer; size_t local_used_cert_chain_buffer_size; + uint8_t local_used_cert_chain_slot_id; + + /* Specifies whether the cached negotiated state should be invalidated. (responder only) + * This is a "sticky" bit wherein if it is set to 1 then it cannot be set to 0. */ + uint8_t end_session_attributes; } libspdm_connection_info_t; typedef struct { @@ -130,31 +139,147 @@ typedef struct { typedef struct { size_t max_buffer_size; size_t buffer_size; - uint8_t buffer[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; -} libspdm_large_managed_buffer_t; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_VCA_BUFFER_SIZE]; +} libspdm_vca_managed_buffer_t; + +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + +/* + * +--------------------------+------------------------------------------+---------+ + * | GET_DIGESTS 1.2 | 4 | 1 | + * | DIGESTS 1.2 | 4 + H * SlotNum = [36, 516] | [1, 18] | + * +--------------------------+------------------------------------------+---------+ + * | GET_CERTIFICATE 1.2 | 8 | 1 | + * | CERTIFICATE 1.2 | 8 + PortionLen | [1, ] | + * +--------------------------+------------------------------------------+---------+ + */ +#define LIBSPDM_MAX_MESSAGE_B_BUFFER_SIZE (24 + \ + LIBSPDM_MAX_HASH_SIZE * SPDM_MAX_SLOT_COUNT + \ + LIBSPDM_MAX_CERT_CHAIN_SIZE) + +/* + * +--------------------------+------------------------------------------+---------+ + * | CHALLENGE 1.2 | 40 | 1 | + * | CHALLENGE_AUTH 1.2 | 38 + H * 2 + S [+ O] = [166, 678] | [6, 23] | + * +--------------------------+------------------------------------------+---------+ + */ +#define LIBSPDM_MAX_MESSAGE_C_BUFFER_SIZE (78 + \ + LIBSPDM_MAX_HASH_SIZE * 2 + \ + LIBSPDM_MAX_ASYM_KEY_SIZE + SPDM_MAX_OPAQUE_DATA_SIZE) + +/* + * +--------------------------+------------------------------------------+---------+ + * | GET_MEASUREMENTS 1.2 | 5 + Nonce (0 or 32) | 1 | + * | MEASUREMENTS 1.2 | 42 + MeasRecLen (+ S) [+ O] = [106, 554] | [4, 19] | + * +--------------------------+------------------------------------------+---------+ + */ +#define LIBSPDM_MAX_MESSAGE_M_BUFFER_SIZE (47 + SPDM_NONCE_SIZE + \ + LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE + \ + LIBSPDM_MAX_ASYM_KEY_SIZE + SPDM_MAX_OPAQUE_DATA_SIZE) + +/* + * +--------------------------+------------------------------------------+---------+ + * | KEY_EXCHANGE 1.2 | 42 + D [+ O] = [106, 554] | [4, 19] | + * | KEY_EXCHANGE_RSP 1.2 | 42 + D + H + S (+ H) [+ O] = [234, 1194] | [8, 40] | + * +--------------------------+------------------------------------------+---------+ + * | PSK_EXCHANGE 1.2 | 12 [+ PSKHint] + R [+ O] = 44 | 2 | + * | PSK_EXCHANGE_RSP 1.2 | 12 + R + H (+ H) [+ O] = [108, 172] | [4, 6] | + * +--------------------------+------------------------------------------+---------+ + */ +#define LIBSPDM_MAX_MESSAGE_K_BUFFER_SIZE (84 + LIBSPDM_MAX_DHE_KEY_SIZE * 2 + \ + LIBSPDM_MAX_HASH_SIZE * 2 + LIBSPDM_MAX_ASYM_KEY_SIZE + \ + SPDM_MAX_OPAQUE_DATA_SIZE * 2) + +/* + * +--------------------------+------------------------------------------+---------+ + * | FINISH 1.2 | 4 (+ S) + H = [100, 580] | [4, 20] | + * | FINISH_RSP 1.2 | 4 (+ H) = [36, 69] | [1, 3] | + * +--------------------------+------------------------------------------+---------+ + * | PSK_FINISH 1.2 | 4 + H = [36, 68] | [1, 3] | + * | PSK_FINISH_RSP 1.2 | 4 | 1 | + * +--------------------------+------------------------------------------+---------+ + */ +#define LIBSPDM_MAX_MESSAGE_F_BUFFER_SIZE (8 + LIBSPDM_MAX_HASH_SIZE * 2 + \ + LIBSPDM_MAX_ASYM_KEY_SIZE) + +#define LIBSPDM_MAX_MESSAGE_L1L2_BUFFER_SIZE \ + (LIBSPDM_MAX_MESSAGE_VCA_BUFFER_SIZE + LIBSPDM_MAX_MESSAGE_M_BUFFER_SIZE) + +#define LIBSPDM_MAX_MESSAGE_M1M2_BUFFER_SIZE \ + (LIBSPDM_MAX_MESSAGE_VCA_BUFFER_SIZE + \ + LIBSPDM_MAX_MESSAGE_B_BUFFER_SIZE + LIBSPDM_MAX_MESSAGE_C_BUFFER_SIZE) + +#define LIBSPDM_MAX_MESSAGE_TH_BUFFER_SIZE \ + (LIBSPDM_MAX_MESSAGE_VCA_BUFFER_SIZE + \ + LIBSPDM_MAX_CERT_CHAIN_SIZE + LIBSPDM_MAX_MESSAGE_K_BUFFER_SIZE + \ + LIBSPDM_MAX_CERT_CHAIN_SIZE + LIBSPDM_MAX_MESSAGE_F_BUFFER_SIZE) + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_B_BUFFER_SIZE]; +} libspdm_message_b_managed_buffer_t; typedef struct { size_t max_buffer_size; size_t buffer_size; - uint8_t buffer[LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE]; -} libspdm_medium_managed_buffer_t; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_C_BUFFER_SIZE]; +} libspdm_message_c_managed_buffer_t; typedef struct { size_t max_buffer_size; size_t buffer_size; - uint8_t buffer[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; -} libspdm_small_managed_buffer_t; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_M_BUFFER_SIZE]; +} libspdm_message_m_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_K_BUFFER_SIZE]; +} libspdm_message_k_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_F_BUFFER_SIZE]; +} libspdm_message_f_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_L1L2_BUFFER_SIZE]; +} libspdm_l1l2_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_M1M2_BUFFER_SIZE]; +} libspdm_m1m2_managed_buffer_t; + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_MESSAGE_TH_BUFFER_SIZE]; +} libspdm_th_managed_buffer_t; + +#endif /* LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT */ + +typedef struct { + size_t max_buffer_size; + size_t buffer_size; + uint8_t buffer[LIBSPDM_MAX_CERT_CHAIN_SIZE]; +} libspdm_cert_chain_managed_buffer_t; /* signature = Sign(SK, hash(M1)) * Verify(PK, hash(M2), signature)*/ /* M1/M2 = Concatenate (A, B, C) * A = Concatenate (GET_VERSION, VERSION, GET_CAPABILITIES, CAPABILITIES, NEGOTIATE_ALGORITHMS, ALGORITHMS) - * B = Concatenate (GET_DIGEST, DIGEST, GET_CERTFICATE, CERTIFICATE) + * B = Concatenate (GET_DIGEST, DIGEST, GET_CERTIFICATE, CERTIFICATE) * C = Concatenate (CHALLENGE, CHALLENGE_AUTH\signature)*/ /* Mut M1/M2 = Concatenate (MutB, MutC) - * MutB = Concatenate (GET_DIGEST, DIGEST, GET_CERTFICATE, CERTIFICATE) + * MutB = Concatenate (GET_DIGEST, DIGEST, GET_CERTIFICATE, CERTIFICATE) * MutC = Concatenate (CHALLENGE, CHALLENGE_AUTH\signature)*/ /* signature = Sign(SK, hash(L1)) @@ -165,13 +290,13 @@ typedef struct { typedef struct { /* the message_a must be plan text because we do not know the algorithm yet.*/ - libspdm_small_managed_buffer_t message_a; + libspdm_vca_managed_buffer_t message_a; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - libspdm_large_managed_buffer_t message_b; - libspdm_small_managed_buffer_t message_c; - libspdm_large_managed_buffer_t message_mut_b; - libspdm_small_managed_buffer_t message_mut_c; - libspdm_large_managed_buffer_t message_m; + libspdm_message_b_managed_buffer_t message_b; + libspdm_message_c_managed_buffer_t message_c; + libspdm_message_b_managed_buffer_t message_mut_b; + libspdm_message_c_managed_buffer_t message_mut_c; + libspdm_message_m_managed_buffer_t message_m; #else void *digest_context_m1m2; void *digest_context_mut_m1m2; @@ -229,9 +354,9 @@ typedef struct { typedef struct { #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - libspdm_large_managed_buffer_t message_k; - libspdm_large_managed_buffer_t message_f; - libspdm_large_managed_buffer_t message_m; + libspdm_message_k_managed_buffer_t message_k; + libspdm_message_f_managed_buffer_t message_f; + libspdm_message_m_managed_buffer_t message_m; #else bool message_f_initialized; void *digest_context_th; @@ -266,10 +391,9 @@ typedef struct { spdm_message_header_t last_encap_request_header; size_t last_encap_request_size; uint16_t cert_chain_total_len; - libspdm_large_managed_buffer_t certificate_chain_buffer; } libspdm_encap_context_t; -#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP typedef struct { bool chunk_in_use; uint8_t chunk_handle; @@ -297,7 +421,22 @@ typedef struct { } libspdm_msg_log_t; #endif /* LIBSPDM_ENABLE_MSG_LOG */ -#define libspdm_context_struct_version 0x2 +#if LIBSPDM_FIPS_MODE +typedef struct { + /** + * Tested algo flag: 0 represents that the algo is not tested. + * See LIBSPDM_FIPS_SELF_TEST_xxx; + **/ + uint32_t tested_algo; + /** + * Flag for the result of run algo self_test, 0 represents the result is failed. + * See LIBSPDM_FIPS_SELF_TEST_xxx; + **/ + uint32_t self_test_result; +} libspdm_fips_selftest_context; +#endif /* LIBSPDM_FIPS_MODE */ + +#define LIBSPDM_CONTEXT_STRUCT_VERSION 0x3 typedef struct { uint32_t version; @@ -308,7 +447,7 @@ typedef struct { /* * reserved for request and response in the main dispatch function in SPDM responder. - * this buffer is the transport message recived from spdm_context->receive_message() + * this buffer is the transport message received from spdm_context->receive_message() * or sent to spdm_context->send_message(). * This message may be SPDM transport message or secured SPDM transport message. **/ @@ -320,11 +459,10 @@ typedef struct { /* Transport Layer information */ libspdm_transport_encode_message_func transport_encode_message; libspdm_transport_decode_message_func transport_decode_message; - libspdm_transport_get_header_size_func transport_get_header_size; /* Cached plain text command * If the command is cipher text, decrypt then cache it. */ - uint8_t last_spdm_request[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + uint8_t *last_spdm_request; size_t last_spdm_request_size; /* scratch buffer */ @@ -345,23 +483,23 @@ typedef struct { libspdm_error_struct_t last_spdm_error; /* Register GetResponse function (responder only) */ - size_t get_response_func; + void *get_response_func; /* Register GetEncapResponse function (requester only) */ - size_t get_encap_response_func; + void *get_encap_response_func; libspdm_encap_context_t encap_context; /* Register spdm_session_state_callback function (responder only) * Register can know the state after StartSession / EndSession. */ - size_t spdm_session_state_callback[LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM]; + void *spdm_session_state_callback; /* Register spdm_connection_state_callback function (responder only) * Register can know the connection state such as negotiated. */ - size_t spdm_connection_state_callback[LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM]; + void *spdm_connection_state_callback; /* Register libspdm_key_update_callback function (responder only) * Register can know when session keys are updated during KEY_UPDATE operations. */ - size_t spdm_key_update_callback[LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM]; + void *spdm_key_update_callback; libspdm_local_context_t local_context; @@ -370,7 +508,13 @@ typedef struct { libspdm_session_info_t session_info[LIBSPDM_MAX_SESSION_COUNT]; - /* Cache lastest session ID for HANDSHAKE_IN_THE_CLEAR */ + /* Buffer that the Responder uses to store the Requester's certificate chain for + * mutual authentication. */ + void *mut_auth_cert_chain_buffer; + size_t mut_auth_cert_chain_buffer_size; + size_t mut_auth_cert_chain_buffer_max_size; + + /* Cache latest session ID for HANDSHAKE_IN_THE_CLEAR */ uint32_t latest_session_id; /* Register for Responder state, be initial to Normal (responder only) */ @@ -378,12 +522,17 @@ typedef struct { /* Cached data for SPDM_ERROR_CODE_RESPONSE_NOT_READY/SPDM_RESPOND_IF_READY */ spdm_error_data_response_not_ready_t error_data; - uint8_t cache_spdm_request[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; +#if LIBSPDM_RESPOND_IF_READY_SUPPORT + uint8_t *cache_spdm_request; size_t cache_spdm_request_size; +#endif uint8_t current_token; /* Register for the retry times when receive "BUSY" Error response (requester only) */ uint8_t retry_times; + /* Register for the delay time in microseconds between retry requests + * when receive "BUSY" Error response (requester only) */ + uint64_t retry_delay_time; bool crypto_request; /* App context data for use by application */ @@ -392,7 +541,21 @@ typedef struct { /* See LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY_*. */ uint8_t handle_error_return_policy; -#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + /* Max session count for DHE session and PSK session + * Set via LIBSPDM_DATA_MAX_DHE_SESSION_COUNT and LIBSPDM_DATA_MAX_PSK_SESSION_COUNT */ + uint32_t max_dhe_session_count; + uint32_t max_psk_session_count; + + /* Current session count for DHE session and PSK session */ + uint32_t current_dhe_session_count; + uint32_t current_psk_session_count; + + /* see LIBSPDM_DATA_MAX_SPDM_SESSION_SEQUENCE_NUMBER */ + uint64_t max_spdm_session_sequence_number; + + uint8_t sequence_number_endian; + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP /* Chunk specific context */ libspdm_chunk_context_t chunk_context; #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ @@ -400,6 +563,15 @@ typedef struct { #if LIBSPDM_ENABLE_MSG_LOG libspdm_msg_log_t msg_log; #endif /* LIBSPDM_ENABLE_MSG_LOG */ + +#if LIBSPDM_FIPS_MODE + libspdm_fips_selftest_context fips_selftest_context; +#endif /* LIBSPDM_FIPS_MODE */ + + /* Endianness (BE/LE/Both) to use for signature verification on SPDM 1.0 and 1.1 + * This field is ignored for other SPDM versions */ + uint8_t spdm_10_11_verify_signature_endian; + } libspdm_context_t; #define LIBSPDM_CONTEXT_SIZE_WITHOUT_SECURED_CONTEXT (sizeof(libspdm_context_t)) @@ -407,6 +579,19 @@ typedef struct { LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE * LIBSPDM_MAX_SESSION_COUNT) #if LIBSPDM_DEBUG_PRINT_ENABLE +/** + * Return the request code name based on given request code. + * + * @param request_code The SPDM request code. + * + * @return request code name according to the request code. + **/ +const char *libspdm_get_code_str(uint8_t request_code); + +#ifdef LIBSPDM_INTERNAL_DUMP_HEX_STR_OVERRIDE +extern void LIBSPDM_INTERNAL_DUMP_HEX_STR_OVERRIDE(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_HEX_STR(data, size) LIBSPDM_INTERNAL_DUMP_HEX_STR_OVERRIDE(data, size) +#else /** * This function dump raw data. * @@ -415,7 +600,12 @@ typedef struct { **/ void libspdm_internal_dump_hex_str(const uint8_t *data, size_t size); #define LIBSPDM_INTERNAL_DUMP_HEX_STR(data, size) libspdm_internal_dump_hex_str(data, size) +#endif /* LIBSPDM_INTERNAL_DUMP_HEX_STR_OVERRIDE */ +#ifdef LIBSPDM_INTERNAL_DUMP_DATA_OVERRIDE +extern void LIBSPDM_INTERNAL_DUMP_DATA_OVERRIDE(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_DATA(data, size) LIBSPDM_INTERNAL_DUMP_DATA_OVERRIDE(data, size) +#else /** * This function dump raw data. * @@ -424,15 +614,21 @@ void libspdm_internal_dump_hex_str(const uint8_t *data, size_t size); **/ void libspdm_internal_dump_data(const uint8_t *data, size_t size); #define LIBSPDM_INTERNAL_DUMP_DATA(data, size) libspdm_internal_dump_data(data, size) +#endif /* LIBSPDM_INTERNAL_DUMP_DATA_OVERRIDE */ +#ifdef LIBSPDM_INTERNAL_DUMP_HEX_OVERRIDE +extern void LIBSPDM_INTERNAL_DUMP_HEX_OVERRIDE(const uint8_t *data, size_t size); +#define LIBSPDM_INTERNAL_DUMP_HEX(data, size) LIBSPDM_INTERNAL_DUMP_HEX_OVERRIDE(data, size) +#else /** - * This function dump raw data with colume format. + * This function dump raw data with column format. * * @param data raw data * @param size raw data size **/ void libspdm_internal_dump_hex(const uint8_t *data, size_t size); #define LIBSPDM_INTERNAL_DUMP_HEX(data, size) libspdm_internal_dump_hex(data, size) +#endif /* LIBSPDM_INTERNAL_DUMP_HEX_OVERRIDE */ #else /* LIBSPDM_DEBUG_PRINT_ENABLE */ #define LIBSPDM_INTERNAL_DUMP_HEX(data, size) @@ -440,6 +636,62 @@ void libspdm_internal_dump_hex(const uint8_t *data, size_t size); #define LIBSPDM_INTERNAL_DUMP_DATA(data, size) #endif /* LIBSPDM_DEBUG_PRINT_ENABLE */ +/* Required scratch buffer size for libspdm internal usage. + * It may be used to hold the encrypted/decrypted message and/or last sent/received message. + * It may be used to hold the large request/response and intermediate send/receive buffer + * in case of chunking. + * + * If chunking is not supported, it should be at least below. + * +--------------------------+-----------------+-----------------+ + * | SENDER_RECEIVER |MAX_SPDM_MSG_SIZE|MAX_SPDM_MSG_SIZE| + * +--------------------------+-----------------+-----------------+ + * |<-Snd/Rcv buf for chunk ->|<-last request ->|<-cache request->| + * + * + * If chunking is supported, it should be at least below. + * +---------------+--------------+--------------------------+------------------------------+-----------------+-----------------+ + * |SECURE_MESSAGE |LARGE_MESSAGE | SENDER_RECEIVER | LARGE SENDER_RECEIVER |MAX_SPDM_MSG_SIZE|MAX_SPDM_MSG_SIZE| + * +---------------+--------------+--------------------------+------------------------------+-----------------+-----------------+ + * |<-Secure msg ->|<-Large msg ->|<-Snd/Rcv buf for chunk ->|<-Snd/Rcv buf for large msg ->|<-last request ->|<-cache request->| + * + * + * The value is configurable based on max_spdm_msg_size. + * The value MAY be changed in different libspdm version. + * It is exposed here, just in case the libspdm consumer wants to configure the setting at build time. + */ +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP +/* first section */ +uint32_t libspdm_get_scratch_buffer_secure_message_offset(libspdm_context_t *spdm_context); +uint32_t libspdm_get_scratch_buffer_secure_message_capacity(libspdm_context_t *spdm_context); + +/* second section */ +uint32_t libspdm_get_scratch_buffer_large_message_offset(libspdm_context_t *spdm_context); +uint32_t libspdm_get_scratch_buffer_large_message_capacity(libspdm_context_t *spdm_context); +#endif + +/* third section */ +uint32_t libspdm_get_scratch_buffer_sender_receiver_offset(libspdm_context_t *spdm_context); +uint32_t libspdm_get_scratch_buffer_sender_receiver_capacity(libspdm_context_t *spdm_context); + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP +/* fourth section */ +uint32_t libspdm_get_scratch_buffer_large_sender_receiver_offset(libspdm_context_t *spdm_context); +uint32_t libspdm_get_scratch_buffer_large_sender_receiver_capacity(libspdm_context_t *spdm_context); +#endif + +/* fifth section */ +uint32_t libspdm_get_scratch_buffer_last_spdm_request_offset(libspdm_context_t *spdm_context); +uint32_t libspdm_get_scratch_buffer_last_spdm_request_capacity(libspdm_context_t *spdm_context); + +#if LIBSPDM_RESPOND_IF_READY_SUPPORT +/* sixth section */ +uint32_t libspdm_get_scratch_buffer_cache_spdm_request_offset(libspdm_context_t *spdm_context); +uint32_t libspdm_get_scratch_buffer_cache_spdm_request_capacity(libspdm_context_t *spdm_context); +#endif + +/* combination */ +uint32_t libspdm_get_scratch_buffer_capacity(libspdm_context_t *spdm_context); + /** * Append a new data buffer to the managed buffer. * @@ -541,15 +793,15 @@ bool libspdm_is_version_supported(const libspdm_context_t *spdm_context, uint8_t uint8_t libspdm_get_connection_version(const libspdm_context_t *spdm_context); /** - * This function returns if a capablities flag is supported in current SPDM connection. + * This function returns if a capabilities flag is supported in current SPDM connection. * * @param spdm_context A pointer to the SPDM context. * @param is_requester Is the function called from a requester. * @param requester_capabilities_flag The requester capabilities flag to be checked * @param responder_capabilities_flag The responder capabilities flag to be checked * - * @retval true the capablities flag is supported. - * @retval false the capablities flag is not supported. + * @retval true the capabilities flag is supported. + * @retval false the capabilities flag is not supported. **/ bool libspdm_is_capabilities_flag_supported(const libspdm_context_t *spdm_context, bool is_requester, @@ -570,38 +822,50 @@ bool libspdm_generate_cert_chain_hash(libspdm_context_t *spdm_context, size_t slot_id, uint8_t *hash); /** - * This function verifies the digest. + * This function generates the public key hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param hash The buffer to store the public key hash. + * + * @retval true public key hash is generated. + * @retval false public key hash is not generated. + **/ +bool libspdm_generate_public_key_hash(libspdm_context_t *spdm_context, + uint8_t *hash); + +/** + * This function verifies the integrity of peer certificate chain buffer including + * spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param digest The digest data buffer. - * @param digest_count size of the digest data buffer. + * @param cert_chain_buffer Certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certificate chain buffer. * - * @retval true digest verification pass. - * @retval false digest verification fail. + * @retval true Peer certificate chain buffer integrity verification passed. + * @retval false Peer certificate chain buffer integrity verification failed. **/ -bool libspdm_verify_peer_digests(libspdm_context_t *spdm_context, - const void *digest, size_t digest_count); +bool libspdm_verify_peer_cert_chain_buffer_integrity(libspdm_context_t *spdm_context, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size); /** - * This function verifies peer certificate chain buffer including spdm_cert_chain_t header. + * This function verifies peer certificate chain authority. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. - * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param cert_chain_buffer Certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certificate chain buffer. * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. - * @param is_requester Indicates if it is a requester message. * - * @retval true Peer certificate chain buffer verification passed. - * @retval false Peer certificate chain buffer verification failed. + * @retval true Peer certificate chain buffer authority verification passed. + * Or there is no root_cert in local_context. + * @retval false Peer certificate chain buffer authority verification failed. **/ -bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, - const void *cert_chain_buffer, - size_t cert_chain_buffer_size, - const void **trust_anchor, - size_t *trust_anchor_size, - bool is_requester); - +bool libspdm_verify_peer_cert_chain_buffer_authority(libspdm_context_t *spdm_context, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + const void **trust_anchor, + size_t *trust_anchor_size); /** * This function generates the challenge signature based upon m1m2 for authentication. * @@ -630,6 +894,20 @@ bool libspdm_verify_certificate_chain_hash(libspdm_context_t *spdm_context, const void *certificate_chain_hash, size_t certificate_chain_hash_size); +/** + * This function verifies the public key hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param public_key_hash The public key hash data buffer. + * @param public_key_hash_size size in bytes of the public key hash data buffer. + * + * @retval true hash verification pass. + * @retval false hash verification fail. + **/ +bool libspdm_verify_public_key_hash(libspdm_context_t *spdm_context, + const void *public_key_hash, + size_t public_key_hash_size); + /** * This function verifies the challenge signature based upon m1m2. * @@ -660,6 +938,7 @@ uint32_t libspdm_get_measurement_summary_hash_size(libspdm_context_t *spdm_conte bool is_requester, uint8_t measurement_summary_hash_type); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT /* * This function calculates l1l2. * If session_info is NULL, this function will use M cache of SPDM context, @@ -671,9 +950,10 @@ uint32_t libspdm_get_measurement_summary_hash_size(libspdm_context_t *spdm_conte * * @retval RETURN_SUCCESS l1l2 is calculated. */ -bool libspdm_calculate_l1l2(void *context, void *session_info, - libspdm_large_managed_buffer_t *l1l2); - +bool libspdm_calculate_l1l2(libspdm_context_t *spdm_context, + void *session_info, + libspdm_l1l2_managed_buffer_t *l1l2); +#else /* * This function calculates l1l2 hash. * If session_info is NULL, this function will use M cache of SPDM context, @@ -686,8 +966,10 @@ bool libspdm_calculate_l1l2(void *context, void *session_info, * * @retval RETURN_SUCCESS l1l2 is calculated. */ -bool libspdm_calculate_l1l2_hash(void *context, void *session_info, +bool libspdm_calculate_l1l2_hash(libspdm_context_t *spdm_context, + void *session_info, size_t *l1l2_hash_size, void *l1l2_hash); +#endif /* LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT */ /** * Get element from multi element opaque data by element id. @@ -709,6 +991,19 @@ bool libspdm_get_element_from_opaque_data(libspdm_context_t *spdm_context, uint8_t element_id, uint8_t sm_data_id, const void **get_element_ptr, size_t *get_element_len); +/** + * Process general opaque data check + * + * @param data_in_size size in bytes of the data_in. + * @param data_in A pointer to the buffer to store the opaque data version selection. + * + * @retval true check opaque data successfully + * @retval false check opaque data failed + **/ +bool libspdm_process_general_opaque_data_check(libspdm_context_t *spdm_context, + size_t data_in_size, + const void *data_in); + /** * Return the size in bytes of opaque data supported version. * @@ -722,11 +1017,11 @@ size_t libspdm_get_untrusted_opaque_data_supported_version_data_size( libspdm_context_t *spdm_context, uint8_t version_count); /** - * Return the size in bytes of opaque data supproted version. + * Return the size in bytes of opaque data supported version. * * This function should be called in KEY_EXCHANGE/PSK_EXCHANGE request generation. * - * @return the size in bytes of opaque data supproted version. + * @return the size in bytes of opaque data supported version. **/ size_t libspdm_get_opaque_data_supported_version_data_size(libspdm_context_t *spdm_context); @@ -863,7 +1158,7 @@ uint8_t libspdm_get_cert_slot_mask (libspdm_context_t *spdm_context); uint8_t libspdm_get_cert_slot_count(libspdm_context_t *spdm_context); #if LIBSPDM_ENABLE_MSG_LOG -void libspdm_append_msg_log(void *context, void *message, size_t message_size); +void libspdm_append_msg_log(libspdm_context_t *spdm_context, void *message, size_t message_size); #endif /** @@ -871,35 +1166,35 @@ void libspdm_append_msg_log(void *context, void *message, size_t message_size); * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_a(void *spdm_context); +void libspdm_reset_message_a(libspdm_context_t *spdm_context); /** * Reset message B cache in SPDM context. * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_b(void *spdm_context); +void libspdm_reset_message_b(libspdm_context_t *spdm_context); /** * Reset message C cache in SPDM context. * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_c(void *spdm_context); +void libspdm_reset_message_c(libspdm_context_t *spdm_context); /** * Reset message MutB cache in SPDM context. * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_mut_b(void *spdm_context); +void libspdm_reset_message_mut_b(libspdm_context_t *spdm_context); /** * Reset message MutC cache in SPDM context. * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_mut_c(void *spdm_context); +void libspdm_reset_message_mut_c(libspdm_context_t *spdm_context); /** * Reset message M cache in SPDM context. @@ -909,7 +1204,7 @@ void libspdm_reset_message_mut_c(void *spdm_context); * @param spdm_context A pointer to the SPDM context. * @param session_info A pointer to the SPDM session context. **/ -void libspdm_reset_message_m(void *context, void *session_info); +void libspdm_reset_message_m(libspdm_context_t *spdm_context, void *session_info); /** * Reset message K cache in SPDM context. @@ -917,7 +1212,7 @@ void libspdm_reset_message_m(void *context, void *session_info); * @param spdm_context A pointer to the SPDM context. * @param spdm_session_info A pointer to the SPDM session context. **/ -void libspdm_reset_message_k(void *context, void *spdm_session_info); +void libspdm_reset_message_k(libspdm_context_t *spdm_context, void *spdm_session_info); /** * Reset message F cache in SPDM context. @@ -925,7 +1220,7 @@ void libspdm_reset_message_k(void *context, void *spdm_session_info); * @param spdm_context A pointer to the SPDM context. * @param spdm_session_info A pointer to the SPDM session context. **/ -void libspdm_reset_message_f(void *context, void *spdm_session_info); +void libspdm_reset_message_f(libspdm_context_t *spdm_context, void *spdm_session_info); /** * Append message A cache in SPDM context. @@ -937,7 +1232,7 @@ void libspdm_reset_message_f(void *context, void *spdm_session_info); * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_a(void *spdm_context, const void *message, +libspdm_return_t libspdm_append_message_a(libspdm_context_t *spdm_context, const void *message, size_t message_size); /** * Append message B cache in SPDM context. @@ -949,7 +1244,7 @@ libspdm_return_t libspdm_append_message_a(void *spdm_context, const void *messag * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_b(void *spdm_context, const void *message, +libspdm_return_t libspdm_append_message_b(libspdm_context_t *spdm_context, const void *message, size_t message_size); /** @@ -962,7 +1257,7 @@ libspdm_return_t libspdm_append_message_b(void *spdm_context, const void *messag * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_c(void *spdm_context, const void *message, +libspdm_return_t libspdm_append_message_c(libspdm_context_t *spdm_context, const void *message, size_t message_size); /** @@ -975,7 +1270,7 @@ libspdm_return_t libspdm_append_message_c(void *spdm_context, const void *messag * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_mut_b(void *spdm_context, const void *message, +libspdm_return_t libspdm_append_message_mut_b(libspdm_context_t *spdm_context, const void *message, size_t message_size); /** @@ -988,7 +1283,7 @@ libspdm_return_t libspdm_append_message_mut_b(void *spdm_context, const void *me * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_mut_c(void *spdm_context, const void *message, +libspdm_return_t libspdm_append_message_mut_c(libspdm_context_t *spdm_context, const void *message, size_t message_size); /** @@ -1004,7 +1299,8 @@ libspdm_return_t libspdm_append_message_mut_c(void *spdm_context, const void *me * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_m(void *context, void *session_info, +libspdm_return_t libspdm_append_message_m(libspdm_context_t *spdm_context, + void *session_info, const void *message, size_t message_size); /** @@ -1019,7 +1315,8 @@ libspdm_return_t libspdm_append_message_m(void *context, void *session_info, * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_k(void *context, void *spdm_session_info, +libspdm_return_t libspdm_append_message_k(libspdm_context_t *spdm_context, + void *spdm_session_info, bool is_requester, const void *message, size_t message_size); @@ -1035,7 +1332,8 @@ libspdm_return_t libspdm_append_message_k(void *context, void *spdm_session_info * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_f(void *context, void *spdm_session_info, +libspdm_return_t libspdm_append_message_f(libspdm_context_t *spdm_context, + void *spdm_session_info, bool is_requester, const void *message, size_t message_size); @@ -1057,7 +1355,7 @@ uint32_t libspdm_generate_session_id(uint16_t req_session_id, uint16_t rsp_sessi * * @return session info associated with this new session ID. **/ -void *libspdm_assign_session_id(void *spdm_context, uint32_t session_id, bool use_psk); +void *libspdm_assign_session_id(libspdm_context_t *spdm_context, uint32_t session_id, bool use_psk); /** * This function frees a session ID. @@ -1065,7 +1363,7 @@ void *libspdm_assign_session_id(void *spdm_context, uint32_t session_id, bool us * @param spdm_context A pointer to the SPDM context. * @param session_id The SPDM session ID. **/ -void libspdm_free_session_id(void *spdm_context, uint32_t session_id); +void libspdm_free_session_id(libspdm_context_t *spdm_context, uint32_t session_id); #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT /* @@ -1073,17 +1371,17 @@ void libspdm_free_session_id(void *spdm_context, uint32_t session_id); * * @param spdm_context A pointer to the SPDM context. * @param session_info The SPDM session ID. - * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. - * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * @param cert_chain_buffer Certificate chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certificate chain buffer. * @param th_data_buffer_size Size in bytes of the th_data_buffer * @param th_data_buffer The buffer to store the th_data_buffer * * @retval RETURN_SUCCESS current TH data is calculated. */ bool libspdm_calculate_th_for_exchange( - void *spdm_context, void *spdm_session_info, + libspdm_context_t *spdm_context, void *spdm_session_info, const uint8_t *cert_chain_buffer, size_t cert_chain_buffer_size, - size_t *th_data_buffer_size, void *th_data_buffer); + libspdm_th_managed_buffer_t *th_curr); #else /* * This function calculates current TH hash with message A and message K. @@ -1096,7 +1394,7 @@ bool libspdm_calculate_th_for_exchange( * @retval RETURN_SUCCESS current TH hash is calculated. */ bool libspdm_calculate_th_hash_for_exchange( - void *context, void *spdm_session_info, + libspdm_context_t *spdm_context, void *spdm_session_info, size_t *th_hash_buffer_size, void *th_hash_buffer); /* @@ -1110,7 +1408,7 @@ bool libspdm_calculate_th_hash_for_exchange( * @retval RETURN_SUCCESS current TH hmac is calculated. */ bool libspdm_calculate_th_hmac_for_exchange_rsp( - void *context, void *spdm_session_info, bool is_requester, + libspdm_context_t *spdm_context, void *spdm_session_info, bool is_requester, size_t *th_hmac_buffer_size, void *th_hmac_buffer); #endif @@ -1120,23 +1418,22 @@ bool libspdm_calculate_th_hmac_for_exchange_rsp( * * @param spdm_context A pointer to the SPDM context. * @param session_info The SPDM session ID. - * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. - * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. - * @param mut_cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header in mutual authentication. - * @param mut_cert_chain_buffer_size Size in bytes of the certitiface chain buffer in mutual authentication. + * @param cert_chain_buffer Certificate chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certificate chain buffer. + * @param mut_cert_chain_buffer Certificate chain buffer with spdm_cert_chain_t header in mutual authentication. + * @param mut_cert_chain_buffer_size Size in bytes of the certificate chain buffer in mutual authentication. * @param th_data_buffer_size Size in bytes of the th_data_buffer. * @param th_data_buffer The buffer to store the th_data_buffer * * @retval RETURN_SUCCESS current TH data is calculated. */ -bool libspdm_calculate_th_for_finish(void *spdm_context, +bool libspdm_calculate_th_for_finish(libspdm_context_t *spdm_context, void *spdm_session_info, const uint8_t *cert_chain_buffer, size_t cert_chain_buffer_size, const uint8_t *mut_cert_chain_buffer, size_t mut_cert_chain_buffer_size, - size_t *th_data_buffer_size, - void *th_data_buffer); + libspdm_th_managed_buffer_t *th_curr); #else /* * This function calculates current TH hash with message A, message K and message F. @@ -1148,7 +1445,7 @@ bool libspdm_calculate_th_for_finish(void *spdm_context, * * @retval RETURN_SUCCESS current TH hash is calculated. */ -bool libspdm_calculate_th_hash_for_finish(void *spdm_context, +bool libspdm_calculate_th_hash_for_finish(libspdm_context_t *spdm_context, void *spdm_session_info, size_t *th_hash_buffer_size, void *th_hash_buffer); @@ -1163,7 +1460,7 @@ bool libspdm_calculate_th_hash_for_finish(void *spdm_context, * * @retval RETURN_SUCCESS current TH hmac is calculated. */ -bool libspdm_calculate_th_hmac_for_finish_rsp(void *spdm_context, +bool libspdm_calculate_th_hmac_for_finish_rsp(libspdm_context_t *spdm_context, void *spdm_session_info, size_t *th_hmac_buffer_size, void *th_hmac_buffer); @@ -1178,7 +1475,7 @@ bool libspdm_calculate_th_hmac_for_finish_rsp(void *spdm_context, * * @retval RETURN_SUCCESS current TH hmac is calculated. */ -bool libspdm_calculate_th_hmac_for_finish_req(void *spdm_context, +bool libspdm_calculate_th_hmac_for_finish_req(libspdm_context_t *spdm_context, void *spdm_session_info, size_t *th_hmac_buffer_size, void *th_hmac_buffer); @@ -1194,7 +1491,7 @@ bool libspdm_calculate_th_hmac_for_finish_req(void *spdm_context, * * @retval RETURN_SUCCESS th1 hash is calculated. */ -bool libspdm_calculate_th1_hash(void *spdm_context, +bool libspdm_calculate_th1_hash(libspdm_context_t *spdm_context, void *spdm_session_info, bool is_requester, uint8_t *th1_hash_data); @@ -1209,7 +1506,7 @@ bool libspdm_calculate_th1_hash(void *spdm_context, * * @retval RETURN_SUCCESS th2 hash is calculated. */ -bool libspdm_calculate_th2_hash(void *spdm_context, +bool libspdm_calculate_th2_hash(libspdm_context_t *spdm_context, void *spdm_session_info, bool is_requester, uint8_t *th2_hash_data); @@ -1295,4 +1592,16 @@ static inline bool libspdm_onehot0(uint32_t mask) return !mask || !(mask & (mask - 1)); } +static inline uint64_t libspdm_le_to_be_64(uint64_t value) +{ + return (((value & 0x00000000000000ff) << 56) | + ((value & 0x000000000000ff00) << 40) | + ((value & 0x0000000000ff0000) << 24) | + ((value & 0x00000000ff000000) << 8) | + ((value & 0x000000ff00000000) >> 8) | + ((value & 0x0000ff0000000000) >> 24) | + ((value & 0x00ff000000000000) >> 40) | + ((value & 0xff00000000000000) >> 56)); +} + #endif /* SPDM_COMMON_LIB_INTERNAL_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_crypt_lib.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_crypt_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_crypt_lib.h diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_fips_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_fips_lib.h new file mode 100644 index 0000000000..30f338b197 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_fips_lib.h @@ -0,0 +1,106 @@ +/** + * Copyright Notice: + * Copyright 2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#if LIBSPDM_FIPS_MODE + +#define LIBSPDM_FIPS_SELF_TEST_HMAC_SHA256 0x00000001 +#define LIBSPDM_FIPS_SELF_TEST_HMAC_SHA384 0x00000002 +#define LIBSPDM_FIPS_SELF_TEST_HMAC_SHA512 0x00000004 +#define LIBSPDM_FIPS_SELF_TEST_AES_GCM 0x00000008 +#define LIBSPDM_FIPS_SELF_TEST_RSA_SSA 0x00000010 +#define LIBSPDM_FIPS_SELF_TEST_HKDF 0x00000020 +#define LIBSPDM_FIPS_SELF_TEST_ECDH 0x00000040 +#define LIBSPDM_FIPS_SELF_TEST_SHA256 0x00000080 +#define LIBSPDM_FIPS_SELF_TEST_SHA384 0x00000100 +#define LIBSPDM_FIPS_SELF_TEST_SHA512 0x00000200 +#define LIBSPDM_FIPS_SELF_TEST_SHA3_256 0x00000400 +#define LIBSPDM_FIPS_SELF_TEST_SHA3_384 0x00000800 +#define LIBSPDM_FIPS_SELF_TEST_SHA3_512 0x00001000 +#define LIBSPDM_FIPS_SELF_TEST_FFDH 0x00002000 +#define LIBSPDM_FIPS_SELF_TEST_ECDSA 0x00004000 +#define LIBSPDM_FIPS_SELF_TEST_EDDSA 0x00008000 +#define LIBSPDM_FIPS_SELF_TEST_RSA_PSS 0x00010000 + +/** + * HMAC-SHA256 KAT covers SHA256 KAT. + **/ +bool libspdm_fips_selftest_hmac_sha256(void *fips_selftest_context); +/** + * HMAC-SHA384 KAT covers SHA384 KAT. + **/ +bool libspdm_fips_selftest_hmac_sha384(void *fips_selftest_context); +/** + * HMAC-SHA512 KAT covers SHA512 KAT. + **/ +bool libspdm_fips_selftest_hmac_sha512(void *fips_selftest_context); + +/** + * AES_GCM self_test + **/ +bool libspdm_fips_selftest_aes_gcm(void *fips_selftest_context); + +/** + * RSA_SSA(RSASSA-PKCS1 v1.5) self_test + **/ +bool libspdm_fips_selftest_rsa_ssa(void *fips_selftest_context); + +/** + * RSA_PSS self_test + **/ +bool libspdm_fips_selftest_rsa_pss(void *fips_selftest_context); + +/** + * HKDF KAT test + **/ +bool libspdm_fips_selftest_hkdf(void *fips_selftest_context); + +/** + * ECDH self_test + **/ +bool libspdm_fips_selftest_ecdh(void *fips_selftest_context); + +/** + * SHA256 KAT: HMAC-SHA256 KAT covers SHA256 KAT. + **/ +bool libspdm_fips_selftest_sha256(void *fips_selftest_context); +/** + * SHA384 KAT: HMAC-SHA384 KAT covers SHA384 KAT. + **/ +bool libspdm_fips_selftest_sha384(void *fips_selftest_context); +/** + * SHA512 KAT: HMAC-SHA512 KAT covers SHA512 KAT. + **/ +bool libspdm_fips_selftest_sha512(void *fips_selftest_context); + +/** + * SHA3_256 KAT + **/ +bool libspdm_fips_selftest_sha3_256(void *fips_selftest_context); +/** + * SHA3_384 KAT + **/ +bool libspdm_fips_selftest_sha3_384(void *fips_selftest_context); +/** + * SHA3_512 KAT + **/ +bool libspdm_fips_selftest_sha3_512(void *fips_selftest_context); + +/** + * FFDH self_test + **/ +bool libspdm_fips_selftest_ffdh(void *fips_selftest_context); + +/** + * ECDSA self_test + **/ +bool libspdm_fips_selftest_ecdsa(void *fips_selftest_context); + +/** + * EDDSA self_test + **/ +bool libspdm_fips_selftest_eddsa(void *fips_selftest_context); + +#endif/*LIBSPDM_FIPS_MODE*/ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_lib_config.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_lib_config.h new file mode 100644 index 0000000000..a64be5eafd --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_lib_config.h @@ -0,0 +1,99 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef LIBSPDM_LIB_CONFIG_H +#define LIBSPDM_LIB_CONFIG_H + +#ifndef LIBSPDM_CONFIG +#include "library/spdm_lib_config.h" +#else +#include LIBSPDM_CONFIG +#endif + +#if defined(LIBSPDM_DEBUG_ENABLE) +#undef LIBSPDM_DEBUG_ASSERT_ENABLE +#undef LIBSPDM_DEBUG_PRINT_ENABLE +#undef LIBSPDM_DEBUG_BLOCK_ENABLE + +#define LIBSPDM_DEBUG_ASSERT_ENABLE (LIBSPDM_DEBUG_ENABLE) +#define LIBSPDM_DEBUG_PRINT_ENABLE (LIBSPDM_DEBUG_ENABLE) +#define LIBSPDM_DEBUG_BLOCK_ENABLE (LIBSPDM_DEBUG_ENABLE) +#elif defined(MDEPKG_NDEBUG) +#undef LIBSPDM_DEBUG_ASSERT_ENABLE +#undef LIBSPDM_DEBUG_PRINT_ENABLE +#undef LIBSPDM_DEBUG_BLOCK_ENABLE + +#define LIBSPDM_DEBUG_ASSERT_ENABLE 0 +#define LIBSPDM_DEBUG_PRINT_ENABLE 0 +#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 +#endif /* defined(LIBSPDM_DEBUG_ENABLE) */ + +/*when in FIPS mode, only support approved algo in FIPS */ +#if LIBSPDM_FIPS_MODE +#undef LIBSPDM_SM2_DSA_P256_SUPPORT +#define LIBSPDM_SM2_DSA_P256_SUPPORT 0 + +#undef LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT +#define LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT 0 + +#undef LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT +#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 0 + +#undef LIBSPDM_AEAD_SM4_128_GCM_SUPPORT +#define LIBSPDM_AEAD_SM4_128_GCM_SUPPORT 0 + +#undef LIBSPDM_SM3_256_SUPPORT +#define LIBSPDM_SM3_256_SUPPORT 0 +#endif /*LIBSPDM_FIPS_MODE*/ + +/* define crypto algorithm without parameter */ +#define LIBSPDM_RSA_SSA_SUPPORT ((LIBSPDM_RSA_SSA_2048_SUPPORT) || \ + (LIBSPDM_RSA_SSA_3072_SUPPORT) || \ + (LIBSPDM_RSA_SSA_4096_SUPPORT)) + +#define LIBSPDM_RSA_PSS_SUPPORT ((LIBSPDM_RSA_PSS_2048_SUPPORT) || \ + (LIBSPDM_RSA_PSS_3072_SUPPORT) || \ + (LIBSPDM_RSA_PSS_4096_SUPPORT)) + +#define LIBSPDM_ECDSA_SUPPORT ((LIBSPDM_ECDSA_P256_SUPPORT) || \ + (LIBSPDM_ECDSA_P384_SUPPORT) || \ + (LIBSPDM_ECDSA_P521_SUPPORT)) + +#define LIBSPDM_SM2_DSA_SUPPORT (LIBSPDM_SM2_DSA_P256_SUPPORT) + +#define LIBSPDM_EDDSA_SUPPORT ((LIBSPDM_EDDSA_ED25519_SUPPORT) || \ + (LIBSPDM_EDDSA_ED448_SUPPORT)) + +#define LIBSPDM_FFDHE_SUPPORT ((LIBSPDM_FFDHE_2048_SUPPORT) || \ + (LIBSPDM_FFDHE_3072_SUPPORT) || \ + (LIBSPDM_FFDHE_4096_SUPPORT)) + +#define LIBSPDM_ECDHE_SUPPORT ((LIBSPDM_ECDHE_P256_SUPPORT) || \ + (LIBSPDM_ECDHE_P384_SUPPORT) || \ + (LIBSPDM_ECDHE_P521_SUPPORT)) + +#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT (LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT) + +#define LIBSPDM_AEAD_GCM_SUPPORT ((LIBSPDM_AEAD_AES_128_GCM_SUPPORT) || \ + (LIBSPDM_AEAD_AES_256_GCM_SUPPORT)) + +#define LIBSPDM_AEAD_SM4_SUPPORT (LIBSPDM_AEAD_SM4_128_GCM_SUPPORT) + +#define LIBSPDM_SHA2_SUPPORT ((LIBSPDM_SHA256_SUPPORT) || \ + (LIBSPDM_SHA384_SUPPORT) || \ + (LIBSPDM_SHA512_SUPPORT)) + +#define LIBSPDM_SHA3_SUPPORT ((LIBSPDM_SHA3_256_SUPPORT) || \ + (LIBSPDM_SHA3_384_SUPPORT) || \ + (LIBSPDM_SHA3_512_SUPPORT)) + +#define LIBSPDM_SM3_SUPPORT (LIBSPDM_SM3_256_SUPPORT) + +#if LIBSPDM_CHECK_MACRO +#include "internal/libspdm_macro_check.h" +#endif /* LIBSPDM_CHECK_MACRO */ + +#endif /* LIBSPDM_LIB_CONFIG_H */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_macro_check.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_macro_check.h new file mode 100644 index 0000000000..ecfd68e2ad --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_macro_check.h @@ -0,0 +1,117 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef LIBSPDM_MACRO_CHECK_H +#define LIBSPDM_MACRO_CHECK_H + +#define LIBSPDM_ASYM_ALGO_SUPPORT \ + ((LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) || \ + (LIBSPDM_SM2_DSA_SUPPORT) || (LIBSPDM_EDDSA_SUPPORT)) + +#define LIBSPDM_DHE_ALGO_SUPPORT \ + ((LIBSPDM_FFDHE_SUPPORT) || (LIBSPDM_ECDHE_SUPPORT) || (LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT)) + +#define LIBSPDM_AEAD_ALGO_SUPPORT \ + ((LIBSPDM_AEAD_GCM_SUPPORT) || (LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT) || \ + (LIBSPDM_AEAD_SM4_SUPPORT)) + +#define LIBSPDM_HASH_ALGO_SUPPORT \ + ((LIBSPDM_SHA2_SUPPORT) || (LIBSPDM_SHA3_SUPPORT) || \ + (LIBSPDM_SM3_SUPPORT)) + +#if LIBSPDM_FIPS_MODE +#define LIBSPDM_FIPS_ASYM_ALGO_SUPPORT \ + ((LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) || (LIBSPDM_ECDSA_SUPPORT) || \ + (LIBSPDM_EDDSA_SUPPORT)) + +#define LIBSPDM_FIPS_DHE_ALGO_SUPPORT \ + ((LIBSPDM_FFDHE_SUPPORT) || (LIBSPDM_ECDHE_SUPPORT)) + +#define LIBSPDM_FIPS_AEAD_ALGO_SUPPORT (LIBSPDM_AEAD_GCM_SUPPORT) + +#define LIBSPDM_FIPS_HASH_ALGO_SUPPORT \ + ((LIBSPDM_SHA2_SUPPORT) || (LIBSPDM_SHA3_SUPPORT)) +#endif /*LIBSPDM_FIPS_MODE*/ + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If KEY_EX_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If CERT_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) && !LIBSPDM_ASYM_ALGO_SUPPORT + #error If CHAL_CAP is enabled then at least one asymmetric algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_DHE_ALGO_SUPPORT + #error If KEY_EX_CAP is enabled then at least one DHE algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_AEAD_ALGO_SUPPORT + #error If KEY_EX_CAP is enabled then at least one AEAD algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) && !LIBSPDM_AEAD_ALGO_SUPPORT + #error If PSK_CAP is enabled then at least one AEAD algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) && !LIBSPDM_HASH_ALGO_SUPPORT + #error If CERT_CAP is enabled then at least one HASH algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) && !LIBSPDM_HASH_ALGO_SUPPORT + #error If CHAL_CAP is enabled then at least one HASH algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) && !LIBSPDM_HASH_ALGO_SUPPORT + #error If KEY_EX_CAP is enabled then at least one HASH algorithm must also be enabled. +#endif + +#if (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) && !LIBSPDM_HASH_ALGO_SUPPORT + #error If PSK_CAP is enabled then at least one HASH algorithm must also be enabled. +#endif + +#if ((LIBSPDM_MAX_VERSION_COUNT) == 0) || ((LIBSPDM_MAX_VERSION_COUNT) > 255) + #error LIBSPDM_MAX_VERSION_COUNT must be between 1 and 255 inclusive. +#endif + +#if (LIBSPDM_MAX_SESSION_COUNT) > 65535 + #error LIBSPDM_MAX_SESSION_COUNT must be less than 65536. +#endif + +#if LIBSPDM_FIPS_MODE +#if (LIBSPDM_ASYM_ALGO_SUPPORT) && !LIBSPDM_FIPS_ASYM_ALGO_SUPPORT + #error ASYM algo is cleared after FIPS enforcement. +#endif + +#if (LIBSPDM_DHE_ALGO_SUPPORT) && !LIBSPDM_FIPS_DHE_ALGO_SUPPORT + #error DHE algo is cleared after FIPS enforcement. +#endif + +#if (LIBSPDM_AEAD_ALGO_SUPPORT) && !LIBSPDM_FIPS_AEAD_ALGO_SUPPORT + #error AEAD algo is cleared after FIPS enforcement. +#endif + +#if (LIBSPDM_HASH_ALGO_SUPPORT) && !LIBSPDM_FIPS_HASH_ALGO_SUPPORT + #error HASH algo is cleared after FIPS enforcement. +#endif +#endif /*LIBSPDM_FIPS_MODE*/ + +#undef LIBSPDM_ASYM_ALGO_SUPPORT +#undef LIBSPDM_DHE_ALGO_SUPPORT +#undef LIBSPDM_AEAD_ALGO_SUPPORT +#undef LIBSPDM_HASH_ALGO_SUPPORT + +#if LIBSPDM_FIPS_MODE +#undef LIBSPDM_FIPS_ASYM_ALGO_SUPPORT +#undef LIBSPDM_FIPS_DHE_ALGO_SUPPORT +#undef LIBSPDM_FIPS_AEAD_ALGO_SUPPORT +#undef LIBSPDM_FIPS_HASH_ALGO_SUPPORT +#endif /*LIBSPDM_FIPS_MODE*/ + +#endif /* LIBSPDM_MACRO_CHECK_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_requester_lib.h similarity index 79% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_requester_lib.h index 92bb147408..f358dee5a7 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_requester_lib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_requester_lib.h @@ -10,6 +10,45 @@ #include "library/spdm_requester_lib.h" #include "library/spdm_secured_message_lib.h" #include "internal/libspdm_common_lib.h" +#include "hal/library/requester/timelib.h" + +/** + * Send an SPDM or an APP request to a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the request is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request_size Size in bytes of the request data buffer. + * @param request A pointer to a destination buffer to store the request. + * The caller is responsible for having either implicit or explicit ownership + * of the buffer. + * For normal message, requester pointer point to transport_message + transport header size + * For secured message, requester pointer will point to the scratch buffer + transport header size in spdm_context. + **/ +libspdm_return_t libspdm_send_request(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + size_t request_size, void *request); + +/** + * Receive an SPDM or an APP response from a device. + * + * @param spdm_context The SPDM context for the device. + * @param session_id Indicate if the response is a secured message. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param response_size Size in bytes of the response data buffer. + * @param response A pointer to a destination buffer to store the response. + * The caller is responsible for having either implicit or explicit + * ownership of the buffer. + * For normal message, response pointer still point to original transport_message. + * For secured message, response pointer will point to the scratch buffer in spdm_context. + **/ +libspdm_return_t libspdm_receive_response(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + size_t *response_size, void **response); /** * This function handles simple error code. @@ -20,7 +59,8 @@ * @retval RETURN_NO_RESPONSE If the error code is BUSY. * @retval RETURN_DEVICE_ERROR If the error code is REQUEST_RESYNCH or others. **/ -libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t error_code); +libspdm_return_t libspdm_handle_simple_error_response(libspdm_context_t *spdm_context, + uint8_t error_code); /** * This function handles the error response. @@ -42,7 +82,6 @@ libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t err * @param response The SPDM response message. * @param original_request_code Indicate the original request code. * @param expected_response_code Indicate the expected response code. - * @param expected_response_size Indicate the expected response size. * * @retval RETURN_SUCCESS The error code is RESPONSE_NOT_READY. The RESPOND_IF_READY is sent and an expected SPDM response is received. * @retval RETURN_NO_RESPONSE The error code is BUSY. @@ -53,8 +92,7 @@ libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t err libspdm_return_t libspdm_handle_error_response_main( libspdm_context_t *spdm_context, const uint32_t *session_id, size_t *response_size, void **response, - uint8_t original_request_code, uint8_t expected_response_code, - size_t expected_response_size); + uint8_t original_request_code, uint8_t expected_response_code); /** * This function handles the error response handling for large responses. @@ -115,6 +153,60 @@ libspdm_return_t libspdm_get_capabilities(libspdm_context_t *spdm_context); **/ libspdm_return_t libspdm_negotiate_algorithms(libspdm_context_t *spdm_context); +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * @param slot_id The number of slot for the certificate chain. + * @param length LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + **/ +libspdm_return_t libspdm_get_certificate_choose_length(void *spdm_context, + const uint32_t *session_id, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain); + +/** + * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. + * + * This function verify the integrity of the certificate chain. + * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. + * + * If the peer root certificate hash is deployed, + * this function also verifies the digest with the root hash in the certificate chain. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * @param slot_id The number of slot for the certificate chain. + * @param length LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN. + * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. + * On output, indicate the size in bytes of the certificate chain. + * @param cert_chain A pointer to a destination buffer to store the certificate chain. + * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. + * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. + **/ +libspdm_return_t libspdm_get_certificate_choose_length_ex(void *spdm_context, + const uint32_t *session_id, + uint8_t slot_id, + uint16_t length, + size_t *cert_chain_size, + void *cert_chain, + const void **trust_anchor, + size_t *trust_anchor_size); + #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP /** * This function sends KEY_EXCHANGE and receives KEY_EXCHANGE_RSP for SPDM key exchange. @@ -161,8 +253,9 @@ libspdm_return_t libspdm_send_receive_key_exchange_ex( uint8_t *heartbeat_period, uint8_t *req_slot_id_param, void *measurement_hash, const void *requester_random_in, - void *requester_random, - void *responder_random); + void *requester_random, void *responder_random, + const void *requester_opaque_data, size_t requester_opaque_data_size, + void *responder_opaque_data, size_t *responder_opaque_data_size); /** * This function sends FINISH and receives FINISH_RSP for SPDM finish. @@ -179,7 +272,7 @@ libspdm_return_t libspdm_send_receive_finish(libspdm_context_t *spdm_context, uint8_t req_slot_id_param); #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ -#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +#if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP /** * This function sends PSK_EXCHANGE and receives PSK_EXCHANGE_RSP for SPDM PSK exchange. * @@ -194,6 +287,8 @@ libspdm_return_t libspdm_send_receive_finish(libspdm_context_t *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. **/ libspdm_return_t libspdm_send_receive_psk_exchange(libspdm_context_t *spdm_context, + const void *psk_hint, + uint16_t psk_hint_size, uint8_t measurement_hash_type, uint8_t session_policy, uint32_t *session_id, @@ -220,11 +315,10 @@ libspdm_return_t libspdm_send_receive_psk_exchange(libspdm_context_t *spdm_conte * @param responder_context_size On input, the size of requester_context buffer. * On output, the size of data returned in requester_context buffer. * It could be 0 if device does not support context. - * - * @retval RETURN_SUCCESS The PSK_EXCHANGE is sent and the PSK_EXCHANGE_RSP is received. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. **/ libspdm_return_t libspdm_send_receive_psk_exchange_ex(libspdm_context_t *spdm_context, + const void *psk_hint, + uint16_t psk_hint_size, uint8_t measurement_hash_type, uint8_t session_policy, uint32_t *session_id, @@ -235,7 +329,11 @@ libspdm_return_t libspdm_send_receive_psk_exchange_ex(libspdm_context_t *spdm_co void *requester_context, size_t *requester_context_size, void *responder_context, - size_t *responder_context_size); + size_t *responder_context_size, + const void *requester_opaque_data, + size_t requester_opaque_data_size, + void *responder_opaque_data, + size_t *responder_opaque_data_size); /** * This function sends PSK_FINISH and receives PSK_FINISH_RSP for SPDM PSK finish. @@ -248,9 +346,9 @@ libspdm_return_t libspdm_send_receive_psk_exchange_ex(libspdm_context_t *spdm_co **/ libspdm_return_t libspdm_send_receive_psk_finish(libspdm_context_t *spdm_context, uint32_t session_id); -#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ -#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) /** * This function sends END_SESSION and receives END_SESSION_ACK for SPDM session end. * @@ -264,9 +362,9 @@ libspdm_return_t libspdm_send_receive_psk_finish(libspdm_context_t *spdm_context libspdm_return_t libspdm_send_receive_end_session(libspdm_context_t *spdm_context, uint32_t session_id, uint8_t end_session_attributes); -#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) */ -#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +#if LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP /** * This function executes a series of SPDM encapsulated requests and receives SPDM encapsulated responses. * @@ -288,6 +386,8 @@ libspdm_return_t libspdm_encapsulated_request(libspdm_context_t *spdm_context, uint8_t mut_auth_requested, uint8_t *req_slot_id_param); +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP /** * Process the SPDM encapsulated GET_DIGESTS request and return the response. * @@ -305,7 +405,7 @@ libspdm_return_t libspdm_encapsulated_request(libspdm_context_t *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_encap_response_digest(void *context, +libspdm_return_t libspdm_get_encap_response_digest(void *spdm_context, size_t request_size, void *request, size_t *response_size, @@ -328,12 +428,14 @@ libspdm_return_t libspdm_get_encap_response_digest(void *context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_encap_response_certificate(void *context, +libspdm_return_t libspdm_get_encap_response_certificate(void *spdm_context, size_t request_size, void *request, size_t *response_size, void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP */ +#if LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP /** * Process the SPDM encapsulated CHALLENGE request and return the response. * @@ -352,8 +454,10 @@ libspdm_return_t libspdm_get_encap_response_certificate(void *context, * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ libspdm_return_t libspdm_get_encap_response_challenge_auth( - void *context, size_t request_size, void *request, + void *spdm_context, size_t request_size, void *request, size_t *response_size, void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP */ +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ /** * Process the SPDM encapsulated KEY_UPDATE request and return the response. @@ -372,12 +476,12 @@ libspdm_return_t libspdm_get_encap_response_challenge_auth( * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_encap_response_key_update(void *context, +libspdm_return_t libspdm_get_encap_response_key_update(void *spdm_context, size_t request_size, void *request, size_t *response_size, void *response); -#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ +#endif /* LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP */ /** * Send an SPDM request to a device. @@ -429,7 +533,7 @@ libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, * * @return half of session ID for a requester. **/ -uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context); +uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context, bool use_psk); /** * Build opaque data supported version. @@ -438,13 +542,12 @@ uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context); * * @param data_out_size Size in bytes of the data_out. * On input, it means the size in bytes of data_out buffer. - * On output, it means the size in bytes of copied data_out buffer if RETURN_SUCCESS is returned, - * and means the size in bytes of desired data_out buffer if RETURN_BUFFER_TOO_SMALL is returned. - * @param data_out A pointer to the desination buffer to store the opaque data supported version. + * On output, it means the size in bytes of copied data_out buffer. + * @param data_out A pointer to the destination buffer to store the opaque data supported version. **/ -libspdm_return_t libspdm_build_opaque_data_supported_version_data(libspdm_context_t *spdm_context, - size_t *data_out_size, - void *data_out); +void libspdm_build_opaque_data_supported_version_data(libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out); /** * Process opaque data version selection. diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_responder_lib.h similarity index 92% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_responder_lib.h index 4aa211ead8..cceeb8ca33 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/internal/libspdm_responder_lib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_responder_lib.h @@ -10,6 +10,7 @@ #include "library/spdm_responder_lib.h" #include "library/spdm_secured_message_lib.h" #include "internal/libspdm_common_lib.h" +#include "hal/library/responder/watchdoglib.h" /** * Process the SPDM request and return the response. @@ -29,7 +30,7 @@ * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ typedef libspdm_return_t (*libspdm_get_spdm_response_func)( - void *spdm_context, size_t request_size, const void *request, + libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, void *response); /** @@ -48,7 +49,7 @@ typedef libspdm_return_t (*libspdm_get_spdm_response_func)( * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_responder_handle_response_state(void *spdm_context, +libspdm_return_t libspdm_responder_handle_response_state(libspdm_context_t *spdm_context, uint8_t request_code, size_t *response_size, void *response); @@ -70,7 +71,7 @@ libspdm_return_t libspdm_responder_handle_response_state(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_respond_if_ready(void *spdm_context, +libspdm_return_t libspdm_get_response_respond_if_ready(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -93,7 +94,7 @@ libspdm_return_t libspdm_get_response_respond_if_ready(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_version(void *spdm_context, +libspdm_return_t libspdm_get_response_version(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, void *response); @@ -115,7 +116,7 @@ libspdm_return_t libspdm_get_response_version(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_capabilities(void *spdm_context, +libspdm_return_t libspdm_get_response_capabilities(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -138,7 +139,7 @@ libspdm_return_t libspdm_get_response_capabilities(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_algorithms(void *spdm_context, +libspdm_return_t libspdm_get_response_algorithms(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -162,7 +163,7 @@ libspdm_return_t libspdm_get_response_algorithms(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_digests(void *spdm_context, +libspdm_return_t libspdm_get_response_digests(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, void *response); @@ -184,7 +185,7 @@ libspdm_return_t libspdm_get_response_digests(void *spdm_context, * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_certificate(void *spdm_context, +libspdm_return_t libspdm_get_response_certificate(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -209,7 +210,7 @@ libspdm_return_t libspdm_get_response_certificate(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_challenge_auth(void *spdm_context, +libspdm_return_t libspdm_get_response_challenge_auth(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -234,7 +235,7 @@ libspdm_return_t libspdm_get_response_challenge_auth(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_measurements(void *spdm_context, +libspdm_return_t libspdm_get_response_measurements(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -259,7 +260,7 @@ libspdm_return_t libspdm_get_response_measurements(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_key_exchange(void *spdm_context, +libspdm_return_t libspdm_get_response_key_exchange(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -282,13 +283,13 @@ libspdm_return_t libspdm_get_response_key_exchange(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_finish(void *spdm_context, +libspdm_return_t libspdm_get_response_finish(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, void *response); #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ -#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +#if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP /** * Process the SPDM PSK_EXCHANGE request and return the response. * @@ -306,7 +307,7 @@ libspdm_return_t libspdm_get_response_finish(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_psk_exchange(void *spdm_context, +libspdm_return_t libspdm_get_response_psk_exchange(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -329,14 +330,14 @@ libspdm_return_t libspdm_get_response_psk_exchange(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_psk_finish(void *spdm_context, +libspdm_return_t libspdm_get_response_psk_finish(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, void *response); -#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ -#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) /** * Process the SPDM END_SESSION request and return the response. * @@ -354,7 +355,7 @@ libspdm_return_t libspdm_get_response_psk_finish(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_end_session(void *spdm_context, +libspdm_return_t libspdm_get_response_end_session(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -377,7 +378,7 @@ libspdm_return_t libspdm_get_response_end_session(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_key_update(void *spdm_context, +libspdm_return_t libspdm_get_response_key_update(libspdm_context_t*spdm_context, size_t request_size, const void *request, size_t *response_size, @@ -400,14 +401,14 @@ libspdm_return_t libspdm_get_response_key_update(void *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_heartbeat(void *spdm_context, +libspdm_return_t libspdm_get_response_heartbeat(libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, void *response); -#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) */ -#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +#if LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP /** * Process the SPDM ENCAPSULATED_REQUEST request and return the response. * @@ -426,7 +427,7 @@ libspdm_return_t libspdm_get_response_heartbeat(void *spdm_context, * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ libspdm_return_t libspdm_get_response_encapsulated_request( - void *spdm_context, size_t request_size, const void *request, + libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, void *response); /** @@ -447,9 +448,10 @@ libspdm_return_t libspdm_get_response_encapsulated_request( * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ libspdm_return_t libspdm_get_response_encapsulated_response_ack( - void *spdm_context, size_t request_size, const void *request, + libspdm_context_t *spdm_context, size_t request_size, const void *request, size_t *response_size, void *response); +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT) /** * Get the SPDM encapsulated GET_DIGESTS request. * @@ -516,7 +518,9 @@ libspdm_return_t libspdm_get_encap_request_get_certificate(libspdm_context_t *sp libspdm_return_t libspdm_process_encap_response_certificate( libspdm_context_t *spdm_context, size_t encap_response_size, const void *encap_response, bool *need_continue); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT) */ +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_SEND_CHALLENGE_SUPPORT) /** * Get the SPDM encapsulated CHALLENGE request. * @@ -549,6 +553,7 @@ libspdm_return_t libspdm_get_encap_request_challenge(libspdm_context_t *spdm_con libspdm_return_t libspdm_process_encap_response_challenge_auth( libspdm_context_t *spdm_context, size_t encap_response_size, const void *encap_response, bool *need_continue); +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_SEND_CHALLENGE_SUPPORT) */ /** * Get the SPDM encapsulated KEY_UPDATE request. @@ -563,10 +568,9 @@ libspdm_return_t libspdm_process_encap_response_challenge_auth( * @retval RETURN_SUCCESS The encapsulated request is returned. * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. **/ -libspdm_return_t -libspdm_get_encap_request_key_update(libspdm_context_t *spdm_context, - size_t *encap_request_size, - void *encap_request); +libspdm_return_t libspdm_get_encap_request_key_update(libspdm_context_t *spdm_context, + size_t *encap_request_size, + void *encap_request); /** * Process the SPDM encapsulated KEY_UPDATE response. @@ -583,7 +587,7 @@ libspdm_get_encap_request_key_update(libspdm_context_t *spdm_context, libspdm_return_t libspdm_process_encap_response_key_update( libspdm_context_t *spdm_context, size_t encap_response_size, const void *encap_response, bool *need_continue); -#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ +#endif /* LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP */ /** * Return the GET_SPDM_RESPONSE function via request code. @@ -594,7 +598,7 @@ libspdm_return_t libspdm_process_encap_response_key_update( **/ libspdm_get_spdm_response_func libspdm_get_response_func_via_request_code(uint8_t request_code); -#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP /** * This function initializes the mut_auth encapsulated state. * @@ -603,13 +607,15 @@ libspdm_get_spdm_response_func libspdm_get_response_func_via_request_code(uint8_ **/ void libspdm_init_mut_auth_encap_state(libspdm_context_t *spdm_context, uint8_t mut_auth_requested); +#if LIBSPDM_SEND_CHALLENGE_SUPPORT /** * This function initializes the basic_mut_auth encapsulated state. * * @param spdm_context A pointer to the SPDM context. **/ void libspdm_init_basic_mut_auth_encap_state(libspdm_context_t *spdm_context); -#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP)*/ +#endif /* LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT */ +#endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ /** * This function handles the encap error response. @@ -642,7 +648,7 @@ void libspdm_set_session_state(libspdm_context_t *spdm_context, void libspdm_set_connection_state(libspdm_context_t *spdm_context, libspdm_connection_state_t connection_state); -#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +#if LIBSPDM_ENABLE_CAPABILITY_CSR_CAP /** * Process the SPDM GET_CSR request and return the response. * @@ -660,12 +666,12 @@ void libspdm_set_connection_state(libspdm_context_t *spdm_context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_csr(void *context, size_t request_size, - const void *request, size_t *response_size, - void *response); -#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ +libspdm_return_t libspdm_get_response_csr(libspdm_context_t *spdm_context, + size_t request_size, const void *request, + size_t *response_size, void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CSR_CAP */ -#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP || LIBSPDM_ENABLE_SET_CERTIFICATE_CAP +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP /** * Process the SPDM SET_CERTIFICATE request and return the response. * @@ -683,13 +689,12 @@ libspdm_return_t libspdm_get_response_csr(void *context, size_t request_size, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_set_certificate(void *context, size_t request_size, - const void *request, - size_t *response_size, - void *response); -#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ +libspdm_return_t libspdm_get_response_set_certificate(libspdm_context_t *spdm_context, + size_t request_size, const void *request, + size_t *response_size, void *response); +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP */ -#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP /** * Process the SPDM CHUNK_GET request and return the response. * @@ -707,7 +712,7 @@ libspdm_return_t libspdm_get_response_set_certificate(void *context, size_t requ * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_chunk_get(void* context, +libspdm_return_t libspdm_get_response_chunk_get(libspdm_context_t *spdm_context, size_t request_size, const void* request, size_t* response_size, @@ -730,7 +735,7 @@ libspdm_return_t libspdm_get_response_chunk_get(void* context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_response_chunk_send(void* context, +libspdm_return_t libspdm_get_response_chunk_send(libspdm_context_t *spdm_context, size_t request_size, const void* request, size_t* response_size, @@ -745,7 +750,7 @@ libspdm_return_t libspdm_get_response_chunk_send(void* context, * * @return half of session ID for a responder. **/ -uint16_t libspdm_allocate_rsp_session_id(const libspdm_context_t *spdm_context); +uint16_t libspdm_allocate_rsp_session_id(const libspdm_context_t *spdm_context, bool use_psk); /** * Build opaque data version selection. @@ -754,14 +759,12 @@ uint16_t libspdm_allocate_rsp_session_id(const libspdm_context_t *spdm_context); * * @param data_out_size Size in bytes of the data_out. * On input, it means the size in bytes of data_out buffer. - * On output, it means the size in bytes of copied data_out buffer if RETURN_SUCCESS is returned, - * and means the size in bytes of desired data_out buffer if RETURN_BUFFER_TOO_SMALL is returned. - * @param data_out A pointer to the desination buffer to store the opaque data version selection. + * On output, it means the size in bytes of copied data_out buffer. + * @param data_out A pointer to the destination buffer to store the opaque data version selection. **/ -libspdm_return_t -libspdm_build_opaque_data_version_selection_data(const libspdm_context_t *spdm_context, - size_t *data_out_size, - void *data_out); +void libspdm_build_opaque_data_version_selection_data(const libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out); /** * Process opaque data supported version. diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_secured_message_lib.h similarity index 56% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_secured_message_lib.h index 6f7d2d0804..3de2d0f519 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_secured_message_lib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/internal/libspdm_secured_message_lib.h @@ -4,41 +4,78 @@ * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md **/ -#ifndef SPDM_SECURED_MESSAGE_LIB_H -#define SPDM_SECURED_MESSAGE_LIB_H +#ifndef SPDM_SECURED_MESSAGE_LIB_INTERNAL_H +#define SPDM_SECURED_MESSAGE_LIB_INTERNAL_H -#include "hal/base.h" -#include "industry_standard/spdm.h" -#include "industry_standard/spdm_secured_message.h" -#include "library/spdm_return_status.h" +#include "library/spdm_secured_message_lib.h" +#include "library/spdm_crypt_lib.h" +#include "internal/libspdm_common_lib.h" +#include "hal/library/memlib.h" +#include "hal/library/cryptlib.h" -typedef enum { - LIBSPDM_SESSION_TYPE_NONE, - LIBSPDM_SESSION_TYPE_MAC_ONLY, - LIBSPDM_SESSION_TYPE_ENC_MAC, - LIBSPDM_SESSION_TYPE_MAX -} libspdm_session_type_t; - -typedef enum { - /* Before send KEY_EXCHANGE/PSK_EXCHANGE or after END_SESSION */ - LIBSPDM_SESSION_STATE_NOT_STARTED, - - /* After send KEY_EXHCNAGE, before send FINISH */ - LIBSPDM_SESSION_STATE_HANDSHAKING, +typedef struct { + uint8_t dhe_secret[LIBSPDM_MAX_DHE_KEY_SIZE]; + uint8_t handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t master_secret[LIBSPDM_MAX_HASH_SIZE]; +} libspdm_session_info_struct_master_secret_t; - /* After send FINISH, before END_SESSION */ - LIBSPDM_SESSION_STATE_ESTABLISHED, +typedef struct { + uint8_t request_handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_handshake_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_finished_key[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_finished_key[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_handshake_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t request_handshake_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t request_handshake_sequence_number; + uint8_t response_handshake_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t response_handshake_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t response_handshake_sequence_number; +} libspdm_session_info_struct_handshake_secret_t; - /* MAX */ - LIBSPDM_SESSION_STATE_MAX -} libspdm_session_state_t; +typedef struct { + uint8_t request_data_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t response_data_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t request_data_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t request_data_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t request_data_sequence_number; + uint8_t response_data_encryption_key[LIBSPDM_MAX_AEAD_KEY_SIZE]; + uint8_t response_data_salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + uint64_t response_data_sequence_number; +} libspdm_session_info_struct_application_secret_t; -/** - * Return the size in bytes of a single SPDM secured message context. - * - * @return the size in bytes of a single SPDM secured message context. - **/ -size_t libspdm_secured_message_get_context_size(void); +typedef struct { + libspdm_session_type_t session_type; + spdm_version_number_t version; + spdm_version_number_t secured_message_version; + uint32_t base_hash_algo; + uint16_t dhe_named_group; + uint16_t aead_cipher_suite; + uint16_t key_schedule; + size_t hash_size; + size_t dhe_key_size; + size_t aead_key_size; + size_t aead_iv_size; + size_t aead_tag_size; + uint64_t max_spdm_session_sequence_number; + bool use_psk; + libspdm_session_state_t session_state; + libspdm_session_info_struct_master_secret_t master_secret; + libspdm_session_info_struct_handshake_secret_t handshake_secret; + libspdm_session_info_struct_application_secret_t application_secret; + libspdm_session_info_struct_application_secret_t application_secret_backup; + bool requester_backup_valid; + bool responder_backup_valid; + size_t psk_hint_size; + uint8_t psk_hint[LIBSPDM_PSK_MAX_HINT_LENGTH]; + uint8_t export_master_secret[LIBSPDM_MAX_HASH_SIZE]; + uint8_t sequence_number_endian; + + /* Cache the error in libspdm_decode_secured_message. + * It is handled in libspdm_build_response. */ + libspdm_error_struct_t last_spdm_error; +} libspdm_secured_message_context_t; + +#define LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE (sizeof(libspdm_secured_message_context_t)) /** * Initialize an SPDM secured message context. @@ -67,16 +104,6 @@ void libspdm_secured_message_set_session_state( void *spdm_secured_message_context, libspdm_session_state_t session_state); -/** - * Return session_state of an SPDM secured message context. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * - * @return the SPDM session state. - */ -libspdm_session_state_t -libspdm_secured_message_get_session_state(void *spdm_secured_message_context); - /** * Set session_type to an SPDM secured message context. * @@ -115,85 +142,25 @@ void libspdm_secured_message_set_psk_hint(void *spdm_secured_message_context, size_t psk_hint_size); /** - * Import the DHE Secret to an SPDM secured message context. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param dhe_secret Indicate the DHE secret. - * @param dhe_secret_size The size in bytes of the DHE secret. - * - * @retval RETURN_SUCCESS DHE Secret is imported. - */ -bool -libspdm_secured_message_import_dhe_secret(void *spdm_secured_message_context, - const void *dhe_secret, - size_t dhe_secret_size); - -/** - * Export the Export Master Secret from an SPDM secured message context. - * - * The size of the Export Master Secret is the size of the digest of the negotiated hash algorithm. - * If the size of the destination buffer is less than the size of the Export Master Secret then - * the first export_master_secret_size bytes are copied. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param export_master_secret A pointer to the buffer to store the export_master_secret. - * @param export_master_secret_size On input, the size of the destination buffer. - * On output, the lesser of either the size of the destination - * buffer or the size of the Export Master Secret. - */ -bool libspdm_secured_message_export_master_secret( - void *spdm_secured_message_context, void *export_master_secret, - size_t *export_master_secret_size); - -/** - * Erase the Export Master Secret from an SPDM secured message context. This is typically called - * after libspdm_secured_message_export_master_secret(). + * Set the maximum sequence_number to an SPDM secured message context. * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param max_spdm_session_sequence_number Indicate the maximum sequence_number in SPDM session. */ -void libspdm_secured_message_clear_export_master_secret(void *spdm_secured_message_context); - -#define LIBSPDM_SECURE_SESSION_KEYS_STRUCT_VERSION 1 - -#pragma pack(1) -typedef struct { - uint32_t version; - uint32_t aead_key_size; - uint32_t aead_iv_size; - /* uint8_t request_data_encryption_key[aead_key_size]; - * uint8_t request_data_salt[aead_iv_size]; - * uint64_t request_data_sequence_number; - * uint8_t response_data_encryption_key[aead_key_size]; - * uint8_t response_data_salt[aead_iv_size]; - * uint64_t response_data_sequence_number;*/ -} libspdm_secure_session_keys_struct_t; -#pragma pack() - -/** - * Export the session_keys from an SPDM secured message context. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. - * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. - * - * @retval RETURN_SUCCESS session_keys are exported. - */ -bool libspdm_secured_message_export_session_keys(void *spdm_secured_message_context, - void *session_keys, - size_t *session_keys_size); +void libspdm_secured_message_set_max_spdm_session_sequence_number( + void *spdm_secured_message_context, + uint64_t max_spdm_session_sequence_number); /** - * Import the session_keys from an SPDM secured message context. + * Set the endianness of the sequence number used to construct the AEAD IV. * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param session_keys Indicate the buffer to store the session_keys in libspdm_secure_session_keys_struct_t. - * @param session_keys_size The size in bytes of the session_keys in libspdm_secure_session_keys_struct_t. + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param endian_value The endianness value. * - * @retval RETURN_SUCCESS session_keys are imported. */ -bool libspdm_secured_message_import_session_keys(void *spdm_secured_message_context, - const void *session_keys, - size_t session_keys_size); +void libspdm_secured_message_set_sequence_number_endian( + void *spdm_secured_message_context, + uint8_t endian_value); /** * Allocates and Initializes one Diffie-Hellman Ephemeral (DHE) context for subsequent use, @@ -264,20 +231,6 @@ bool libspdm_secured_message_dhe_compute_key( const uint8_t *peer_public, size_t peer_public_size, void *spdm_secured_message_context); -/** - * This function is used to clear handshake secret. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - **/ -void libspdm_clear_handshake_secret(void *spdm_secured_message_context); - -/** - * This function is used to clear the master secret; - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - **/ -void libspdm_clear_master_secret(void *spdm_secured_message_context); - /** * Allocates and initializes one HMAC context for subsequent use, with request_finished_key. * @@ -459,21 +412,14 @@ bool libspdm_hmac_all_with_response_finished_key( size_t data_size, uint8_t *hmac_value); /** - * This function concatenates binary data, which is used as info in HKDF expand later. + * Set the last SPDM error struct of an SPDM secured message context. * - * @param label An ascii string label for the libspdm_bin_concat. - * @param label_size The size in bytes of the ASCII string label, not including NULL terminator. - * @param context A pre-defined hash value as the context for the libspdm_bin_concat. - * @param length 16 bits length for the libspdm_bin_concat. - * @param hash_size The size in bytes of the context hash. - * @param out_bin The buffer to store the output binary. - * @param out_bin_size The size in bytes for the out_bin. - **/ -void libspdm_bin_concat(spdm_version_number_t spdm_version, - const char *label, size_t label_size, - const uint8_t *context, uint16_t length, - size_t hash_size, uint8_t *out_bin, - size_t *out_bin_size); + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param last_spdm_error Last SPDM error struct of an SPDM secured message context. + */ +void libspdm_secured_message_set_last_spdm_error_struct( + void *spdm_secured_message_context, + const libspdm_error_struct_t *last_spdm_error); /** * This function generates SPDM HandshakeKey for a session. @@ -497,19 +443,6 @@ bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, bool libspdm_generate_session_data_key(void *spdm_secured_message_context, const uint8_t *th2_hash_data); -typedef enum { - LIBSPDM_KEY_UPDATE_OPERATION_CREATE_UPDATE, - LIBSPDM_KEY_UPDATE_OPERATION_COMMIT_UPDATE, - LIBSPDM_KEY_UPDATE_OPERATION_DISCARD_UPDATE, - LIBSPDM_KEY_UPDATE_OPERATION_MAX -} libspdm_key_update_operation_t; - -typedef enum { - LIBSPDM_KEY_UPDATE_ACTION_REQUESTER, - LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, - LIBSPDM_KEY_UPDATE_ACTION_MAX -} libspdm_key_update_action_t; - /** * This function creates the updates of SPDM DataKey for a session. * @@ -534,117 +467,4 @@ bool libspdm_activate_update_session_data_key(void *spdm_secured_message_context libspdm_key_update_action_t action, bool use_new_key); -/** - * Get sequence number in an SPDM secure message. - * - * This value is transport layer specific. - * - * @param sequence_number The current sequence number used to encode or decode message. - * @param sequence_number_buffer A buffer to hold the sequence number output used in the secured message. - * The size in byte of the output buffer shall be 8. - * - * @return size in byte of the sequence_number_buffer. - * It shall be no greater than 8. - * 0 means no sequence number is required. - **/ -typedef uint8_t (*libspdm_secured_message_get_sequence_number_func)( - uint64_t sequence_number, uint8_t *sequence_number_buffer); - -/** - * Return max random number count in an SPDM secure message. - * - * This value is transport layer specific. - * - * @return Max random number count in an SPDM secured message. - * 0 means no randum number is required. - **/ -typedef uint32_t (*libspdm_secured_message_get_max_random_number_count_func)(void); - -#define SPDM_SECURED_MESSAGE_CALLBACKS_VERSION 1 - -typedef struct { - uint32_t version; - libspdm_secured_message_get_sequence_number_func get_sequence_number; - libspdm_secured_message_get_max_random_number_count_func get_max_random_number_count; -} libspdm_secured_message_callbacks_t; - -typedef struct { - uint8_t error_code; - uint32_t session_id; -} libspdm_error_struct_t; - -/** - * Encode an application message to a secured message. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param session_id The session ID of the SPDM session. - * @param is_requester Indicates if it is a requester message. - * @param app_message_size size in bytes of the application message data buffer. - * @param app_message A pointer to a source buffer to store the application message. - * It shall point to the scratch buffer in spdm_context. - * On input, the app_message pointer shall point to a big enough buffer. - * Before app_message, there is room for spdm_secured_message_cipher_header_t. - * After (app_message + app_message_size), there is room for random bytes. - * @param secured_message_size size in bytes of the secured message data buffer. - * @param secured_message A pointer to a destination buffer to store the secured message. - * It shall point to the acquired sender buffer. - * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. - * - * @retval RETURN_SUCCESS The application message is encoded successfully. - * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. - **/ -libspdm_return_t libspdm_encode_secured_message( - void *spdm_secured_message_context, uint32_t session_id, - bool is_requester, size_t app_message_size, - void *app_message, size_t *secured_message_size, - void *secured_message, - const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks); - -/** - * Decode an application message from a secured message. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param session_id The session ID of the SPDM session. - * @param is_requester Indicates if it is a requester message. - * @param secured_message_size size in bytes of the secured message data buffer. - * @param secured_message A pointer to a source buffer to store the secured message. - * It shall point to the acquired receiver buffer. - * @param app_message_size size in bytes of the application message data buffer. - * @param app_message A pointer to a destination buffer to store the application message. - * It shall point to the scratch buffer in spdm_context. - * On input, the app_message pointer shall point to a big enough buffer to hold the decrypted message - * On output, the app_message pointer shall be inside of [app_message, app_message + app_message_size] - * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. - * - * @retval RETURN_SUCCESS The application message is decoded successfully. - * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. - * @retval RETURN_UNSUPPORTED The secured_message is unsupported. - **/ -libspdm_return_t libspdm_decode_secured_message( - void *spdm_secured_message_context, uint32_t session_id, - bool is_requester, size_t secured_message_size, - void *secured_message, size_t *app_message_size, - void **app_message, - const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks); - -/** - * Get the last SPDM error struct of an SPDM secured message context. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param last_spdm_error Last SPDM error struct of an SPDM secured message context. - */ -void libspdm_secured_message_get_last_spdm_error_struct( - void *spdm_secured_message_context, - libspdm_error_struct_t *last_spdm_error); - -/** - * Set the last SPDM error struct of an SPDM secured message context. - * - * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param last_spdm_error Last SPDM error struct of an SPDM secured message context. - */ -void libspdm_secured_message_set_last_spdm_error_struct( - void *spdm_secured_message_context, - const libspdm_error_struct_t *last_spdm_error); - -#endif /* SPDM_SECURED_MESSAGE_LIB_H */ +#endif /* SPDM_SECURED_MESSAGE_LIB_INTERNAL_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_common_lib.h similarity index 74% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_common_lib.h index a72b696816..224273d2fc 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_common_lib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_common_lib.h @@ -12,7 +12,12 @@ #include "library/spdm_secured_message_lib.h" #include "library/spdm_return_status.h" -/* Connection: When a host sends messgages to a device, they create a connection. +#define LIBSPDM_MAJOR_VERSION 0x03 +#define LIBSPDM_MINOR_VERSION 0x01 +#define LIBSPDM_PATCH_VERSION 0x01 +#define LIBSPDM_ALPHA 0x00 + +/* Connection: When a host sends messages to a device, they create a connection. * The host can and only can create one connection with one device. * The host may create multiple connections with multiple devices at same time. * A connection can be unique identified by the connected device. @@ -34,6 +39,7 @@ typedef enum { LIBSPDM_DATA_CAPABILITY_RTT_US, LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE, LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE, + LIBSPDM_DATA_CAPABILITY_SENDER_DATA_TRANSFER_SIZE, /* SPDM algorithm setting */ LIBSPDM_DATA_MEASUREMENT_SPEC, @@ -54,25 +60,19 @@ typedef enum { /* Certificate info */ LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN, - /* LIBSPDM_DATA_LOCAL_SLOT_COUNT is deprecated. Do not use it. Reserved only. */ - LIBSPDM_DATA_LOCAL_SLOT_COUNT, LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT, - LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN, + LIBSPDM_DATA_PEER_PUBLIC_KEY, + LIBSPDM_DATA_LOCAL_PUBLIC_KEY, + LIBSPDM_DATA_BASIC_MUT_AUTH_REQUESTED, LIBSPDM_DATA_MUT_AUTH_REQUESTED, LIBSPDM_DATA_HEARTBEAT_PERIOD, /* Negotiated result */ - LIBSPDM_DATA_LOCAL_USED_CERT_CHAIN_BUFFER, LIBSPDM_DATA_PEER_USED_CERT_CHAIN_BUFFER, LIBSPDM_DATA_PEER_SLOT_MASK, LIBSPDM_DATA_PEER_TOTAL_DIGEST_BUFFER, - /* Pre-shared key Hint - * If PSK is present, then PSK_EXCHANGE is used. - * Otherwise, the KEY_EXCHANGE is used. */ - LIBSPDM_DATA_PSK_HINT, - /* SessionData */ LIBSPDM_DATA_SESSION_USE_PSK, LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED, @@ -93,9 +93,6 @@ typedef enum { /* VCA cached for CACHE_CAP in 1.2 for transcript. */ LIBSPDM_DATA_VCA_CACHE, - /* My provisioned certificate slot_id (for slot_id - 0xFF, default 0)*/ - LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN_DEFAULT_SLOT_ID, - /* if the context is for a requester. It only needs to be set in VCA cache. * In normal flow, the value is set in GET_VERSION or VERSION automatically. * false means responder @@ -103,6 +100,43 @@ typedef enum { **/ LIBSPDM_DATA_IS_REQUESTER, + /* If the Responder replies with a Busy `ERROR` response to a request + * then the Requester is free to retry sending the request. + * This value specifies the maximum number of times libspdm will retry + * sending the request before returning an error. + * If its value is 0 then libspdm will not send any retry requests. + **/ + LIBSPDM_DATA_REQUEST_RETRY_TIMES, + + /* If the Responder replies with a Busy `ERROR` response to a request + * then the Requester is free to retry sending the request. + * This value specifies the delay time in microseconds between each retry requests. + * If its value is 0 then libspdm will send retry request immediately. + **/ + LIBSPDM_DATA_REQUEST_RETRY_DELAY_TIME, + + /* Below two entries are used to limit the number of DHE session and PSK session separately. + * When set a new value, below rule is applied: + * new MaxDheSessionCount <= LIBSPDM_MAX_SESSION_COUNT - current MaxPskSessionCount + * new MaxPskSessionCount <= LIBSPDM_MAX_SESSION_COUNT - current MaxDheSessionCount + * 0 means no limitation for the specific DHE or PSK session, as long as + * PskSessionCount + DheSessionCount <= LIBSPDM_MAX_SESSION_COUNT. + * If these values are modified while there are active sessions then the active sessions + * aren't terminated. + **/ + LIBSPDM_DATA_MAX_DHE_SESSION_COUNT, + LIBSPDM_DATA_MAX_PSK_SESSION_COUNT, + + LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_RSP_DIR, + LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_REQ_DIR, + LIBSPDM_DATA_MAX_SPDM_SESSION_SEQUENCE_NUMBER, + + /* For SPDM 1.0 and 1.1, allow signature verification in big, little, or both endians. */ + LIBSPDM_DATA_SPDM_VERSION_10_11_VERIFY_SIGNATURE_ENDIAN, + + LIBSPDM_DATA_SEQUENCE_NUMBER_ENDIAN, + LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_ENDIAN, + /* MAX */ LIBSPDM_DATA_MAX } libspdm_data_type_t; @@ -127,7 +161,7 @@ typedef enum { typedef struct { libspdm_data_location_t location; /* data_type specific: - * session_id for the negoatiated key. + * session_id for the negotiated key. * SlotId for the certificate. * req_slot_id + measurement_hash_type for LIBSPDM_DATA_MUT_AUTH_REQUESTED*/ uint8_t additional_data[4]; @@ -152,7 +186,7 @@ typedef enum { /* After GET_CERTIFICATE/CERTIFICATE */ LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE, - /* After CHALLENGE/CHALLENGE_AUTH, and ENCAP CALLENGE/CHALLENG_AUTH if MUT_AUTH is enabled. */ + /* After CHALLENGE/CHALLENGE_AUTH, and ENCAP CHALLENGE/CHALLENGE_AUTH if MUT_AUTH is enabled. */ LIBSPDM_CONNECTION_STATE_AUTHENTICATED, /* MAX */ @@ -166,8 +200,10 @@ typedef enum { /* Other component is busy. */ LIBSPDM_RESPONSE_STATE_BUSY, + #if LIBSPDM_RESPOND_IF_READY_SUPPORT /* Hardware is not ready. */ LIBSPDM_RESPONSE_STATE_NOT_READY, + #endif /* LIBSPDM_RESPOND_IF_READY_SUPPORT */ /* Firmware Update is done. Need resync. */ LIBSPDM_RESPONSE_STATE_NEED_RESYNC, @@ -179,6 +215,36 @@ typedef enum { LIBSPDM_RESPONSE_STATE_MAX } libspdm_response_state_t; +/* These macros apply only if the negotiated SPDM version is 1.0 or 1.1. + * The default verification mode is big endian only. */ +#define LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY 0 +#define LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY 1 +#define LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE 2 + +/* Set the endianness of the AEAD sequence number. These macros apply only if the negotiated + * SPDM Secured Message version is 1.0 or 1.1. + * *_LITTLE and *_BIG immediately return an error on decryption failure. + * *_BOTH tries the opposite endianness on decryption failure. + * The default is LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_LITTLE. */ +#define LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_LITTLE 0 +#define LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_BOTH 1 +#define LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BIG 2 +#define LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BOTH 3 + +/* + * +--------------------------+------------------------------------------+---------+ + * | GET_VERSION | 4 | 1 | + * | VERSION {1.0, 1.1, 1.2} | 6 + 2 * 3 = 12 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | GET_CAPABILITIES 1.2 | 20 | 1 | + * | CAPABILITIES 1.2 | 20 | 1 | + * +--------------------------+------------------------------------------+---------+ + * | NEGOTIATE_ALGORITHMS 1.2 | 32 + 4 * 4 = 48 | 2 | + * | ALGORITHMS 1.2 | 36 + 4 * 4 = 52 | 2 | + * +--------------------------+------------------------------------------+---------+ + */ +#define LIBSPDM_MAX_MESSAGE_VCA_BUFFER_SIZE (150 + 2 * LIBSPDM_MAX_VERSION_COUNT) + /** * Set an SPDM context data. * @@ -223,6 +289,22 @@ libspdm_return_t libspdm_get_data(void *spdm_context, const libspdm_data_parameter_t *parameter, void *data, size_t *data_size); +#if LIBSPDM_CHECK_SPDM_CONTEXT +/** + * Check that the SPDM context is in a valid state. + * + * This is typically called after all context data has been populated via the libspdm_set_data + * function. The function returns on first failure. If LIBSPDM_DEBUG_ENABLE or + * LIBSPDM_DEBUG_PRINT_ENABLE are enabled then it also prints the failing condition. + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval true The SPDM context is in a valid state. + * @retval false The SPDM context is in an invalid state. + **/ +bool libspdm_check_context (void *spdm_context); +#endif /* LIBSPDM_CHECK_SPDM_CONTEXT */ + /** * Get the last SPDM error struct of an SPDM context. * @@ -265,6 +347,56 @@ libspdm_return_t libspdm_init_context_with_secured_context(void *spdm_context, void **secured_contexts, size_t num_secured_contexts); +#if LIBSPDM_FIPS_MODE +/** + * Initialize an libspdm_fips_selftest_context. + * + * The + * + * @param spdm_context A pointer to the SPDM context. + * + * @retval RETURN_SUCCESS context is initialized. + * @retval RETURN_DEVICE_ERROR context initialization failed. + */ +libspdm_return_t libspdm_init_fips_selftest_context(void *fips_selftest_context); + +/** + * Return the size in bytes of the fips_selftest_context. + * + * @return the size in bytes of the fips_selftest_context. + **/ +size_t libspdm_get_fips_selftest_context_size(void); + +/** + * import fips_selftest_context to spdm_context; + * + * @param[in,out] spdm_context A pointer to the spdm_context. + * @param[in] fips_selftest_context A pointer to the fips_selftest_context. + * @param[in] fips_selftest_context_size The size of fips_selftest_context. + * + * @retval true import fips_selftest_context successful. + * @retval false spdm_context or fips_selftest_context is null. + */ +bool libspdm_import_fips_selftest_context_to_spdm_context(void *spdm_context, + void *fips_selftest_context, + size_t fips_selftest_context_size); + +/** + * export fips_selftest_context from spdm_context; + * + * @param[in] spdm_context A pointer to the spdm_context. + * @param[in,out] fips_selftest_context A pointer to the fips_selftest_context. + * @param[in] fips_selftest_context_size The size of fips_selftest_context. + * + * @retval true export fips_selftest_context successful. + * @retval false spdm_context or fips_selftest_context is null. + */ +bool libspdm_export_fips_selftest_context_from_spdm_context(void *spdm_context, + void *fips_selftest_context, + size_t fips_selftest_context_size); + +#endif /* LIBSPDM_FIPS_MODE */ + /** * Initialize an SPDM context, as well as secured message contexts. * The secured message contexts are appended to the context structure. @@ -282,7 +414,8 @@ libspdm_return_t libspdm_init_context(void *spdm_context); /** * Reset an SPDM context. * - * The size in bytes of the spdm_context can be returned by libspdm_get_context_size. + * Note that message logging is not reset by this function. To reset the message logger call + * libspdm_reset_msg_log. * * @param spdm_context A pointer to the SPDM context. */ @@ -398,43 +531,14 @@ void libspdm_register_device_io_func( /** * Acquire a device sender buffer for transport layer message. * - * The max_msg_size must be larger than - * MAX (non-secure Transport Message Header Size + - * SPDM_CAPABILITIES.DataTransferSize + - * max alignment pad size (transport specific), - * secure Transport Message Header Size + - * sizeof(spdm_secured_message_a_data_header1_t) + - * length of sequence_number (transport specific) + - * sizeof(spdm_secured_message_a_data_header2_t) + - * sizeof(spdm_secured_message_cipher_header_t) + - * App Message Header Size (transport specific) + - * SPDM_CAPABILITIES.DataTransferSize + - * maximum random data size (transport specific) + - * AEAD MAC size (16) + - * max alignment pad size (transport specific)) - * - * For MCTP, - * Transport Message Header Size = sizeof(mctp_message_header_t) - * length of sequence_number = 2 - * App Message Header Size = sizeof(mctp_message_header_t) - * maximum random data size = MCTP_MAX_RANDOM_NUMBER_COUNT - * max alignment pad size = 0 - * For PCI_DOE, - * Transport Message Header Size = sizeof(pci_doe_data_object_header_t) - * length of sequence_number = 0 - * App Message Header Size = 0 - * maximum random data size = 0 - * max alignment pad size = 3 - * * @param context A pointer to the SPDM context. - * @param max_msg_size Size in bytes of the maximum size of sender buffer. * @param msg_buf_ptr A pointer to a sender buffer. * * @retval LIBSPDM_STATUS_SUCCESS The sender buffer has been acquired. * @retval LIBSPDM_STATUS_ACQUIRE_FAIL Unable to acquire sender buffer. **/ typedef libspdm_return_t (*libspdm_device_acquire_sender_buffer_func)( - void *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); + void *spdm_context, void **msg_buf_ptr); /** * Release a device sender buffer for transport layer message. @@ -450,7 +554,32 @@ typedef void (*libspdm_device_release_sender_buffer_func)(void *spdm_context, /** * Acquire a device receiver buffer for transport layer message. * - * The max_msg_size must be larger than + * @param context A pointer to the SPDM context. + * @param msg_buf_pt A pointer to a receiver buffer. + * + * @retval LIBSPDM_STATUS_SUCCESS The receiver buffer has been acquired. + * @retval LIBSPDM_STATUS_ACQUIRE_FAIL Unable to acquire receiver buffer. + **/ +typedef libspdm_return_t (*libspdm_device_acquire_receiver_buffer_func)( + void *spdm_context, void **msg_buf_ptr); + +/** + * Release a device receiver buffer for transport layer message. + * + * @param context A pointer to the SPDM context. + * @param msg_buf_ptr A pointer to a receiver buffer. + * + * @retval RETURN_SUCCESS The receiver buffer is Released. + **/ +typedef void (*libspdm_device_release_receiver_buffer_func)(void *spdm_context, + const void *msg_buf_ptr); + +/** + * Register SPDM device buffer management functions. + * + * This function must be called after libspdm_init_context, and before any SPDM communication. + * + * The sender_buffer_size and receiver_buffer_size must be no smaller than * MAX (non-secure Transport Message Header Size + * SPDM_CAPABILITIES.DataTransferSize + * max alignment pad size (transport specific), @@ -463,7 +592,9 @@ typedef void (*libspdm_device_release_sender_buffer_func)(void *spdm_context, * SPDM_CAPABILITIES.DataTransferSize + * maximum random data size (transport specific) + * AEAD MAC size (16) + - * max alignment pad size (transport specific)) + * max alignment pad size (transport specific)). + * + * Finally, the SPDM_CAPABILITIES.DataTransferSize will be calculated based upon it. * * For MCTP, * Transport Message Header Size = sizeof(mctp_message_header_t) @@ -478,33 +609,9 @@ typedef void (*libspdm_device_release_sender_buffer_func)(void *spdm_context, * maximum random data size = 0 * max alignment pad size = 3 * - * @param context A pointer to the SPDM context. - * @param max_msg_size Size in bytes of the maximum size of receiver buffer. - * @param msg_buf_pt A pointer to a receiver buffer. - * - * @retval LIBSPDM_STATUS_SUCCESS The receiver buffer has been acquired. - * @retval LIBSPDM_STATUS_ACQUIRE_FAIL Unable to acquire receiver buffer. - **/ -typedef libspdm_return_t (*libspdm_device_acquire_receiver_buffer_func)( - void *spdm_context, size_t *max_msg_size, void **msg_buf_ptr); - -/** - * Release a device receiver buffer for transport layer message. - * - * @param context A pointer to the SPDM context. - * @param msg_buf_ptr A pointer to a receiver buffer. - * - * @retval RETURN_SUCCESS The receiver buffer is Released. - **/ -typedef void (*libspdm_device_release_receiver_buffer_func)(void *spdm_context, - const void *msg_buf_ptr); - -/** - * Register SPDM device buffer management functions. - * - * This function must be called after libspdm_init_context, and before any SPDM communication. - * * @param spdm_context A pointer to the SPDM context. + * @param sender_buffer_size Size in bytes of the sender buffer. + * @param receiver_buffer_size Size in bytes of the receiver buffer. * @param acquire_sender_buffer The fuction to acquire transport layer sender buffer. * @param release_sender_buffer The fuction to release transport layer sender buffer. * @param acquire_receiver_buffer The fuction to acquire transport layer receiver buffer. @@ -512,6 +619,8 @@ typedef void (*libspdm_device_release_receiver_buffer_func)(void *spdm_context, **/ void libspdm_register_device_buffer_func( void *spdm_context, + uint32_t sender_buffer_size, + uint32_t receiver_buffer_size, libspdm_device_acquire_sender_buffer_func acquire_sender_buffer, libspdm_device_release_sender_buffer_func release_sender_buffer, libspdm_device_acquire_receiver_buffer_func acquire_receiver_buffer, @@ -528,16 +637,16 @@ void libspdm_register_device_buffer_func( * The APP message format is defined by the transport layer. * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message * - * @param spdm_context A pointer to the SPDM context. - * @param session_id Indicates if it is a secured message protected via SPDM session. - * If session_id is NULL, it is a normal message. - * If session_id is not NULL, it is a secured message. - * @param is_app_message Indicates if it is an APP message or SPDM message. - * @param is_requester Indicates if it is a requester message. - * @param message_size Size in bytes of the message data buffer. - * @param message A pointer to a source buffer to store the message. - * For normal message, it shall point to the acquired sender buffer. - * For secured message, it shall point to the scratch buffer in spdm_context. + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is not NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param is_request_message Indicates if it is a request message. + * @param message_size Size in bytes of the message data buffer. + * @param message A pointer to a source buffer to store the message. + * For normal message, it shall point to the acquired sender buffer. + * For secured message, it shall point to the scratch buffer in spdm_context. * @param transport_message_size Size in bytes of the transport message data buffer. * @param transport_message A pointer to a destination buffer to store the transport message. * On input, it shall be msg_buf_ptr from sender buffer. @@ -548,7 +657,7 @@ void libspdm_register_device_buffer_func( **/ typedef libspdm_return_t (*libspdm_transport_encode_message_func)( void *spdm_context, const uint32_t *session_id, bool is_app_message, - bool is_requester, size_t message_size, + bool is_request_message, size_t message_size, void *message, size_t *transport_message_size, void **transport_message); @@ -568,7 +677,7 @@ typedef libspdm_return_t (*libspdm_transport_encode_message_func)( * If session_id is NULL, it is a normal message. * If session_id is not NULL, it is a secured message. * @param is_app_message Indicates if it is an APP message or SPDM message. - * @param is_requester Indicates if it is a requester message. + * @param is_request_message Indicates if it is a request message. * @param transport_message_size Size in bytes of the transport message data buffer. * @param transport_message A pointer to a source buffer to store the transport message. * For normal message or secured message, it shall point to acquired receiver buffer. @@ -584,7 +693,7 @@ typedef libspdm_return_t (*libspdm_transport_encode_message_func)( **/ typedef libspdm_return_t (*libspdm_transport_decode_message_func)( void *spdm_context, uint32_t **session_id, - bool *is_app_message, bool is_requester, + bool *is_app_message, bool is_request_message, size_t transport_message_size, void *transport_message, size_t *message_size, void **message); @@ -609,13 +718,14 @@ typedef uint32_t (*libspdm_transport_get_header_size_func)(void *spdm_context); * @param spdm_context A pointer to the SPDM context. * @param transport_encode_message The fuction to encode an SPDM or APP message to a transport layer message. * @param transport_decode_message The fuction to decode an SPDM or APP message from a transport layer message. - * @param transport_get_header_size The fuction to get the maximum transport layer message header size. **/ void libspdm_register_transport_layer_func( void *spdm_context, + uint32_t max_spdm_msg_size, + uint32_t transport_header_size, + uint32_t transport_tail_size, libspdm_transport_encode_message_func transport_encode_message, - libspdm_transport_decode_message_func transport_decode_message, - libspdm_transport_get_header_size_func transport_get_header_size); + libspdm_transport_decode_message_func transport_decode_message); /** * Get the size of required scratch buffer. @@ -740,8 +850,8 @@ void *libspdm_get_secured_message_context_via_session_info(void *spdm_session_in * This function returns peer certificate chain buffer including spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. - * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * @param cert_chain_buffer Certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certificate chain buffer. * * @retval true Peer certificate chain buffer including spdm_cert_chain_t header is returned. * @retval false Peer certificate chain buffer including spdm_cert_chain_t header is not found. @@ -754,8 +864,8 @@ bool libspdm_get_peer_cert_chain_buffer(void *spdm_context, * This function returns peer certificate chain data without spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. - * @param cert_chain_data_size Size in bytes of the certitiface chain data. + * @param cert_chain_data Certificate chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certificate chain data. * * @retval true Peer certificate chain data without spdm_cert_chain_t header is returned. * @retval false Peer certificate chain data without spdm_cert_chain_t header is not found. @@ -768,8 +878,8 @@ bool libspdm_get_peer_cert_chain_data(void *spdm_context, * This function returns local used certificate chain buffer including spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. - * @param cert_chain_buffer_size Size in bytes of the certitiface chain buffer. + * @param cert_chain_buffer Certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size Size in bytes of the certificate chain buffer. * * @retval true Local used certificate chain buffer including spdm_cert_chain_t header is returned. * @retval false Local used certificate chain buffer including spdm_cert_chain_t header is not found. @@ -782,8 +892,8 @@ bool libspdm_get_local_cert_chain_buffer(void *spdm_context, * This function returns local used certificate chain data without spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. - * @param cert_chain_data_size Size in bytes of the certitiface chain data. + * @param cert_chain_data Certificate chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certificate chain data. * * @retval true Local used certificate chain data without spdm_cert_chain_t header is returned. * @retval false Local used certificate chain data without spdm_cert_chain_t header is not found. @@ -792,4 +902,44 @@ bool libspdm_get_local_cert_chain_data(void *spdm_context, const void **cert_chain_data, size_t *cert_chain_data_size); +/** + * This function returns peer public key buffer. + * + * @param spdm_context A pointer to the SPDM context. + * @param peer_public_key_buffer Peer public key buffer. + * @param peer_public_key_buffer_size Size in bytes of peer public key buffer. + * + * @retval true Peer public key buffer is returned. + * @retval false Peer public key buffer is not found. + **/ +bool libspdm_get_peer_public_key_buffer(void *spdm_context, + const void **peer_public_key_buffer, + size_t *peer_public_key_buffer_size); + +/** + * This function returns local public key buffer. + * + * @param spdm_context A pointer to the SPDM context. + * @param local_public_key_buffer Local public key buffer. + * @param local_public_key_buffer_size Size in bytes of local public key buffer. + * + * @retval true Local public key buffer is returned. + * @retval false Local public key buffer is not found. + **/ +bool libspdm_get_local_public_key_buffer(void *spdm_context, + const void **local_public_key_buffer, + size_t *local_public_key_buffer_size); + +/** + * byte3 - libspdm major version + * byte2 - libspdm minor version + * byte1 - libspdm patch version + * byte0 - libspdm alpha + * (office release with tag: 0, release candidate with tag: 1, non official release: 0xFF) + **/ +uint32_t libspdm_module_version(void); + +/*true: FIPS enabled, false: FIPS disabled*/ +bool libspdm_get_fips_mode(void); + #endif /* SPDM_COMMON_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_crypt_lib.h similarity index 80% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_crypt_lib.h index de177ea0b1..32e61898f8 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_crypt_lib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_crypt_lib.h @@ -12,12 +12,73 @@ #include "hal/base.h" #include "industry_standard/spdm.h" +#if (LIBSPDM_FFDHE_4096_SUPPORT) #define LIBSPDM_MAX_DHE_KEY_SIZE 512 +#elif (LIBSPDM_FFDHE_3072_SUPPORT) +#define LIBSPDM_MAX_DHE_KEY_SIZE 384 +#elif (LIBSPDM_FFDHE_2048_SUPPORT) +#define LIBSPDM_MAX_DHE_KEY_SIZE 256 +#elif (LIBSPDM_ECDHE_P521_SUPPORT) +#define LIBSPDM_MAX_DHE_KEY_SIZE (66 * 2) +#elif (LIBSPDM_ECDHE_P384_SUPPORT) +#define LIBSPDM_MAX_DHE_KEY_SIZE (48 * 2) +#elif ((LIBSPDM_ECDHE_P256_SUPPORT) || (LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT)) +#define LIBSPDM_MAX_DHE_KEY_SIZE (32 * 2) +#else +/* set 1 to pass build only */ +#define LIBSPDM_MAX_DHE_KEY_SIZE 1 +#endif /* LIBSPDM_MAX_DHE_KEY_SIZE */ + +#if ((LIBSPDM_RSA_SSA_4096_SUPPORT) || (LIBSPDM_RSA_PSS_4096_SUPPORT)) #define LIBSPDM_MAX_ASYM_KEY_SIZE 512 +#define LIBSPDM_MAX_ASYM_SIG_SIZE 512 +#elif ((LIBSPDM_RSA_SSA_3072_SUPPORT) || (LIBSPDM_RSA_PSS_3072_SUPPORT)) +#define LIBSPDM_MAX_ASYM_KEY_SIZE 384 +#define LIBSPDM_MAX_ASYM_SIG_SIZE 384 +#elif ((LIBSPDM_RSA_SSA_2048_SUPPORT) || (LIBSPDM_RSA_PSS_2048_SUPPORT)) +#define LIBSPDM_MAX_ASYM_KEY_SIZE 256 +#define LIBSPDM_MAX_ASYM_SIG_SIZE 256 +#elif (LIBSPDM_ECDSA_P521_SUPPORT) +#define LIBSPDM_MAX_ASYM_KEY_SIZE (66 * 2) +#define LIBSPDM_MAX_ASYM_SIG_SIZE (66 * 2) +#elif (LIBSPDM_EDDSA_ED448_SUPPORT) +#define LIBSPDM_MAX_ASYM_KEY_SIZE (57 * 2) +#define LIBSPDM_MAX_ASYM_SIG_SIZE (57 * 2) +#elif (LIBSPDM_ECDSA_P384_SUPPORT) +#define LIBSPDM_MAX_ASYM_KEY_SIZE (48 * 2) +#define LIBSPDM_MAX_ASYM_SIG_SIZE (48 * 2) +#elif ((LIBSPDM_ECDSA_P256_SUPPORT) || (LIBSPDM_SM2_DSA_P256_SUPPORT) || \ + (LIBSPDM_EDDSA_ED25519_SUPPORT)) +#define LIBSPDM_MAX_ASYM_KEY_SIZE (32 * 2) +#define LIBSPDM_MAX_ASYM_SIG_SIZE (32 * 2) +#else +/* set 1 to pass build only */ +#define LIBSPDM_MAX_ASYM_KEY_SIZE 1 +#define LIBSPDM_MAX_ASYM_SIG_SIZE 1 +#endif /* LIBSPDM_MAX_ASYM_KEY_SIZE */ + +#if ((LIBSPDM_SHA512_SUPPORT) || (LIBSPDM_SHA3_512_SUPPORT)) #define LIBSPDM_MAX_HASH_SIZE 64 +#elif ((LIBSPDM_SHA384_SUPPORT) || (LIBSPDM_SHA3_384_SUPPORT)) +#define LIBSPDM_MAX_HASH_SIZE 48 +#elif ((LIBSPDM_SHA256_SUPPORT) || (LIBSPDM_SHA3_256_SUPPORT) || (LIBSPDM_SM3_256_SUPPORT)) +#define LIBSPDM_MAX_HASH_SIZE 32 +#endif /* LIBSPDM_MAX_HASH_SIZE */ + +#if ((LIBSPDM_AEAD_AES_256_GCM_SUPPORT) || (LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT)) #define LIBSPDM_MAX_AEAD_KEY_SIZE 32 #define LIBSPDM_MAX_AEAD_IV_SIZE 12 #define LIBSPDM_MAX_AEAD_TAG_SIZE 16 +#elif ((LIBSPDM_AEAD_AES_128_GCM_SUPPORT) || (LIBSPDM_AEAD_SM4_128_GCM_SUPPORT)) +#define LIBSPDM_MAX_AEAD_KEY_SIZE 16 +#define LIBSPDM_MAX_AEAD_IV_SIZE 12 +#define LIBSPDM_MAX_AEAD_TAG_SIZE 16 +#else +/* set 1 to pass build only */ +#define LIBSPDM_MAX_AEAD_KEY_SIZE 1 +#define LIBSPDM_MAX_AEAD_IV_SIZE 1 +#define LIBSPDM_MAX_AEAD_TAG_SIZE 1 +#endif /* LIBSPDM_MAX_AEAD_KEY_SIZE */ /** * This function returns the SPDM hash algorithm size. @@ -312,7 +373,7 @@ uint32_t libspdm_get_asym_signature_size(uint32_t base_asym_algo); * @param base_asym_algo SPDM base_asym_algo * @param cert Pointer to the DER-encoded X509 certificate. * @param cert_size Size of the X509 certificate in bytes. - * @param context Pointer to new-generated asymmetric context which contain the retrieved + * @param context Pointer to newly generated asymmetric context which contain the retrieved * public key component. Use libspdm_asym_free() function to free the * resource. * @@ -324,6 +385,25 @@ bool libspdm_asym_get_public_key_from_x509(uint32_t base_asym_algo, size_t cert_size, void **context); +/** + * Retrieve the asymmetric public key from the DER-encoded public key data, + * based upon negotiated asymmetric algorithm. + * + * @param base_asym_algo SPDM base_asym_algo + * @param der_data Pointer to the DER-encoded public key data. + * @param der_size Size of the DER-encoded public key data in bytes. + * @param context Pointer to newly generated asymmetric context which contain the + * retrieved public key component. + * Use libspdm_asym_free() function to free the resource. + * + * @retval true Private key was retrieved successfully. + * @retval false Invalid DER key data. + **/ +bool libspdm_asym_get_public_key_from_der(uint32_t base_asym_algo, + const uint8_t *der_data, + size_t der_size, + void **context); + /** * Release the specified asymmetric context, based upon negotiated asymmetric algorithm. * @@ -332,6 +412,18 @@ bool libspdm_asym_get_public_key_from_x509(uint32_t base_asym_algo, **/ void libspdm_asym_free(uint32_t base_asym_algo, void *context); + +/** + * Copies signature buffers from src to dst swapping endianness in the process. + */ +void libspdm_copy_signature_swap_endian( + uint32_t base_asym_algo, + uint8_t* dst, + size_t dst_size, + const uint8_t* src, + size_t src_size); + + /** * Verifies the asymmetric signature, based upon negotiated asymmetric algorithm. * @@ -342,6 +434,8 @@ void libspdm_asym_free(uint32_t base_asym_algo, void *context); * @param message_size Size of the message in bytes. * @param signature Pointer to asymmetric signature to be verified. * @param sig_size Size of signature in bytes. + * @param endian Endian to be tried. If both endians are selected, + * the one actually used successfully is returned. * * @retval true Valid asymmetric signature. * @retval false Invalid asymmetric signature or invalid asymmetric context. @@ -349,9 +443,17 @@ void libspdm_asym_free(uint32_t base_asym_algo, void *context); bool libspdm_asym_verify( spdm_version_number_t spdm_version, uint8_t op_code, uint32_t base_asym_algo, uint32_t base_hash_algo, - void *context, const uint8_t *message, - size_t message_size, const uint8_t *signature, - size_t sig_size); + void *context, + const uint8_t *message, size_t message_size, + const uint8_t *signature, size_t sig_size); + +bool libspdm_asym_verify_ex( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void* context, + const uint8_t* message, size_t message_size, + const uint8_t* signature, size_t sig_size, + uint8_t *endian); /** * Verifies the asymmetric signature, based upon negotiated asymmetric algorithm. @@ -363,16 +465,24 @@ bool libspdm_asym_verify( * @param hash_size Size of the hash in bytes. * @param signature Pointer to asymmetric signature to be verified. * @param sig_size Size of signature in bytes. + * @param endian Endian to be tried. If both endians are selected, + * the one actually used successfully is returned. * * @retval true Valid asymmetric signature. * @retval false Invalid asymmetric signature or invalid asymmetric context. **/ bool libspdm_asym_verify_hash( spdm_version_number_t spdm_version, uint8_t op_code, - uint32_t base_asym_algo, uint32_t base_hash_algo, - void *context, const uint8_t *message_hash, - size_t hash_size, const uint8_t *signature, - size_t sig_size); + uint32_t base_asym_algo, uint32_t base_hash_algo, void *context, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size); + +bool libspdm_asym_verify_hash_ex( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, void* context, + const uint8_t* message_hash, size_t hash_size, + const uint8_t* signature, size_t sig_size, + uint8_t *endian); /** * Carries out the signature generation. @@ -442,7 +552,7 @@ uint32_t libspdm_get_req_asym_signature_size(uint16_t req_base_asym_alg); * @param req_base_asym_alg SPDM req_base_asym_alg * @param cert Pointer to the DER-encoded X509 certificate. * @param cert_size Size of the X509 certificate in bytes. - * @param context Pointer to new-generated asymmetric context which contain the + * @param context Pointer to newly generated asymmetric context which contain the * retrieved public key component. Use libspdm_asym_free() function to * free the resource. * @@ -454,6 +564,25 @@ bool libspdm_req_asym_get_public_key_from_x509(uint16_t req_base_asym_alg, size_t cert_size, void **context); +/** + * Retrieve the asymmetric public key from the DER-encoded public key data, + * based upon negotiated requester asymmetric algorithm. + * + * @param req_base_asym_alg SPDM req_base_asym_alg + * @param der_data Pointer to the DER-encoded public key data. + * @param der_size Size of the DER-encoded public key data in bytes. + * @param context Pointer to newly generated asymmetric context which contain the + * retrieved public key component. + * Use libspdm_req_asym_free() function to free the resource. + * + * @retval true Public key was retrieved successfully. + * @retval false Invalid DER key data. + **/ +bool libspdm_req_asym_get_public_key_from_der(uint16_t req_base_asym_alg, + const uint8_t *der_data, + size_t der_size, + void **context); + /** * Release the specified asymmetric context, based upon negotiated requester asymmetric algorithm. * @@ -472,6 +601,8 @@ void libspdm_req_asym_free(uint16_t req_base_asym_alg, void *context); * @param message_size Size of the message in bytes. * @param signature Pointer to asymmetric signature to be verified. * @param sig_size Size of signature in bytes. + * @param endian Endian to be tried. If both endians are selected, + * the one actually used successfully is returned. * * @retval true Valid asymmetric signature. * @retval false Invalid asymmetric signature or invalid asymmetric context. @@ -483,6 +614,13 @@ bool libspdm_req_asym_verify( const uint8_t *message, size_t message_size, const uint8_t *signature, size_t sig_size); +bool libspdm_req_asym_verify_ex( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void* context, + const uint8_t* message, size_t message_size, + const uint8_t* signature, size_t sig_size, uint8_t *endian); + /** * Verifies the asymmetric signature, based upon negotiated requester asymmetric algorithm. * @@ -493,6 +631,8 @@ bool libspdm_req_asym_verify( * @param hash_size Size of the hash in bytes. * @param signature Pointer to asymmetric signature to be verified. * @param sig_size Size of signature in bytes. + * @param endian Endian to be tried. If both endians are selected, + * the one actually used successfully is returned. * * @retval true Valid asymmetric signature. * @retval false Invalid asymmetric signature or invalid asymmetric context. @@ -504,6 +644,13 @@ bool libspdm_req_asym_verify_hash( const uint8_t *message_hash, size_t hash_size, const uint8_t *signature, size_t sig_size); +bool libspdm_req_asym_verify_hash_ex( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void* context, + const uint8_t* message_hash, size_t hash_size, + const uint8_t* signature, size_t sig_size, uint8_t *endian); + /** * Carries out the signature generation. * @@ -726,6 +873,8 @@ bool libspdm_aead_decryption(const spdm_version_number_t secured_message_version **/ bool libspdm_get_random_number(size_t size, uint8_t *rand); +#if LIBSPDM_CERT_PARSE_SUPPORT + /** * Certificate Check for SPDM leaf cert. * @@ -733,15 +882,34 @@ bool libspdm_get_random_number(size_t size, uint8_t *rand); * @param[in] cert_size The size of certificate data in bytes. * @param[in] base_asym_algo SPDM base_asym_algo * @param[in] base_hash_algo SPDM base_hash_algo - * @param[in] is_device_cert_model If true, the cert chain is DeviceCert model. - * If false, the cert chain is AliasCert model. + * @param[in] is_requester_cert Is the function verifying requester or responder cert. + * @param[in] is_device_cert_model If true, the local endpoint uses the DeviceCert model. + * If false, the local endpoint uses the AliasCert model. * * @retval true Success. * @retval false Certificate is not valid. **/ bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, uint32_t base_asym_algo, uint32_t base_hash_algo, - bool is_device_cert_model); + bool is_requester_cert, bool is_device_cert_model); + +/** + * Certificate Check for SPDM leaf cert when set_cert. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in] base_hash_algo SPDM base_hash_algo + * @param[in] is_requester_cert Is the function verifying requester or responder cert. + * @param[in] is_device_cert_model If true, the local endpoint uses the DeviceCert model. + * If false, the local endpoint uses the AliasCert model. + * + * @retval true Success. + * @retval false Certificate is not valid. + **/ +bool libspdm_x509_set_cert_certificate_check(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_requester_cert, bool is_device_cert_model); /** * Return certificate is root cert or not. @@ -808,8 +976,9 @@ bool libspdm_get_dmtf_subject_alt_name(const uint8_t *cert, const size_t cert_si * * @param cert_chain_data The certificate chain data without spdm_cert_chain_t header. * @param cert_chain_data_size Size in bytes of the certificate chain data. - * @param base_hash_algo SPDM base_hash_algo * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param is_requester_cert Is the function verifying requester or responder cert. * @param is_device_cert_model If true, the cert chain is DeviceCert model. * If false, the cert chain is AliasCert model. * @@ -818,7 +987,7 @@ bool libspdm_get_dmtf_subject_alt_name(const uint8_t *cert, const size_t cert_si **/ bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_data_size, uint32_t base_asym_algo, uint32_t base_hash_algo, - bool is_device_cert_model); + bool is_requester_cert, bool is_device_cert_model); /** * This function verifies the integrity of certificate chain buffer including @@ -828,6 +997,7 @@ bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_ * @param base_asym_algo SPDM base_asym_algo * @param cert_chain_buffer The certificate chain buffer including spdm_cert_chain_t header. * @param cert_chain_buffer_size Size in bytes of the certificate chain buffer. + * @param is_requester_cert Is the function verifying requester or responder cert. * @param is_device_cert_model If true, the cert chain is DeviceCert model. * If false, the cert chain is AliasCert model. * @@ -837,7 +1007,7 @@ bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_ bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t base_asym_algo, const void *cert_chain_buffer, size_t cert_chain_buffer_size, - bool is_device_cert_model); + bool is_requester_cert, bool is_device_cert_model); /** * Retrieve the asymmetric public key from one DER-encoded X509 certificate, @@ -846,9 +1016,9 @@ bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t b * * @param base_hash_algo SPDM base_hash_algo. * @param base_asym_alg SPDM base_asym_algo or req_base_asym_alg. - * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. - * @param cert_chain_data_size Size in bytes of the certitiface chain data. - * @param public_key Pointer to new-generated asymmetric context which contain the + * @param cert_chain_data Certificate chain data with spdm_cert_chain_t header. + * @param cert_chain_data_size Size in bytes of the certificate chain data. + * @param public_key Pointer to newly generated asymmetric context which contain the * retrieved public key component. * * @retval true Public key was retrieved successfully. @@ -860,18 +1030,25 @@ bool libspdm_get_leaf_cert_public_key_from_cert_chain(uint32_t base_hash_algo, size_t cert_chain_data_size, void **public_key); +#endif + /** * Verify req info format refer to PKCS#10. * * @param[in] req_info Requester info to gen CSR. * @param[in] req_info_len The len of requester info. * - * @retval true Vaild req info, have three situations: + * @retval true Valid req info, have three situations: * 1: no req_info * 2: good format req_info without attributes * 3: good format req_info with good format attributes - * @retval false Invaild req info. + * @retval false Invalid req info. **/ bool libspdm_verify_req_info(uint8_t *req_info, uint16_t req_info_len); +#if LIBSPDM_FIPS_MODE +/*run all of the self-tests and returns the results.*/ +bool libspdm_fips_run_selftest(void *fips_selftest_context); +#endif + #endif /* SPDM_CRYPT_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_lib_config.h similarity index 63% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_lib_config.h index cfff674c5b..6203b51f13 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_lib_config.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_lib_config.h @@ -7,6 +7,11 @@ #ifndef SPDM_LIB_CONFIG_H #define SPDM_LIB_CONFIG_H +/* Enables FIPS 140-3 mode. */ +#ifndef LIBSPDM_FIPS_MODE +#define LIBSPDM_FIPS_MODE 0 +#endif + /* Enables assertions and debug printing. When `LIBSPDM_DEBUG_ENABLE` is defined it overrides or * sets the values of `LIBSPDM_DEBUG_PRINT_ENABLE`, `LIBSPDM_DEBUG_ASSERT_ENABLE`, and * `LIBSPDM_BLOCK_ENABLE` to the value of `LIBSPDM_DEBUG_ENABLE`. @@ -21,7 +26,7 @@ /* The SPDM specification allows a Responder to return up to 256 version entries in the `VERSION` * response to the Requester, including duplicate entries. For a Requester this value specifies the * maximum number of entries that libspdm will tolerate in a `VERSION` response before returning an - * error. A similiar macro, `SPDM_MAX_VERSION_COUNT`, exists for the Responder. However this macro + * error. A similar macro, `SPDM_MAX_VERSION_COUNT`, exists for the Responder. However this macro * is not meant to be configured by the Integrator. */ #ifndef LIBSPDM_MAX_VERSION_COUNT @@ -71,38 +76,6 @@ #define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN 1024 #endif -#ifndef LIBSPDM_MAX_MESSAGE_BUFFER_SIZE -#define LIBSPDM_MAX_MESSAGE_BUFFER_SIZE 0x1200 -#endif -#ifndef LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE -#define LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE 0x100 /* to hold message_a before negotiate*/ -#endif -#ifndef LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE -#define LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE 0x300 /* to hold message_k before finished_key is ready*/ -#endif - -/* If the Responder replies with a Busy `ERROR` response to a request then the Requester is free to - * retry sending the request. This value specifies the maximum number of times libspdm will retry - * sending the request before returning an error. If its value is 0 then libspdm will not send any - * retry requests. - */ -#ifndef LIBSPDM_MAX_REQUEST_RETRY_TIMES -#define LIBSPDM_MAX_REQUEST_RETRY_TIMES 3 -#endif -#ifndef LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM -#define LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM 4 -#endif -#ifndef LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM -#define LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM 4 -#endif -#ifndef LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM -#define LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM 4 -#endif - -#ifndef LIBSPDM_MAX_CSR_SIZE -#define LIBSPDM_MAX_CSR_SIZE 0x1000 -#endif - /* To ensure integrity in communication between the Requester and the Responder libspdm calculates * cryptographic digests and signatures over multiple requests and responses. This value specifies * whether libspdm will use a running calculation over the transcript, where requests and responses @@ -113,23 +86,44 @@ #define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 #endif - /* Cryptography Configuration * In each category, at least one should be selected. * NOTE: Not all combination can be supported. E.g. Don't mix NIST algo with SMx.*/ -#ifndef LIBSPDM_RSA_SSA_SUPPORT -#define LIBSPDM_RSA_SSA_SUPPORT 1 +#ifndef LIBSPDM_RSA_SSA_2048_SUPPORT +#define LIBSPDM_RSA_SSA_2048_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_SSA_3072_SUPPORT +#define LIBSPDM_RSA_SSA_3072_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_SSA_4096_SUPPORT +#define LIBSPDM_RSA_SSA_4096_SUPPORT 1 +#endif + +#ifndef LIBSPDM_RSA_PSS_2048_SUPPORT +#define LIBSPDM_RSA_PSS_2048_SUPPORT 1 +#endif +#ifndef LIBSPDM_RSA_PSS_3072_SUPPORT +#define LIBSPDM_RSA_PSS_3072_SUPPORT 1 #endif -#ifndef LIBSPDM_RSA_PSS_SUPPORT -#define LIBSPDM_RSA_PSS_SUPPORT 1 +#ifndef LIBSPDM_RSA_PSS_4096_SUPPORT +#define LIBSPDM_RSA_PSS_4096_SUPPORT 1 +#endif + +#ifndef LIBSPDM_ECDSA_P256_SUPPORT +#define LIBSPDM_ECDSA_P256_SUPPORT 1 #endif -#ifndef LIBSPDM_ECDSA_SUPPORT -#define LIBSPDM_ECDSA_SUPPORT 1 +#ifndef LIBSPDM_ECDSA_P384_SUPPORT +#define LIBSPDM_ECDSA_P384_SUPPORT 1 #endif -#ifndef LIBSPDM_SM2_DSA_SUPPORT -#define LIBSPDM_SM2_DSA_SUPPORT 1 +#ifndef LIBSPDM_ECDSA_P521_SUPPORT +#define LIBSPDM_ECDSA_P521_SUPPORT 1 #endif + +#ifndef LIBSPDM_SM2_DSA_P256_SUPPORT +#define LIBSPDM_SM2_DSA_P256_SUPPORT 1 +#endif + #ifndef LIBSPDM_EDDSA_ED25519_SUPPORT #define LIBSPDM_EDDSA_ED25519_SUPPORT 1 #endif @@ -137,24 +131,43 @@ #define LIBSPDM_EDDSA_ED448_SUPPORT 1 #endif -#ifndef LIBSPDM_FFDHE_SUPPORT -#define LIBSPDM_FFDHE_SUPPORT 1 +#ifndef LIBSPDM_FFDHE_2048_SUPPORT +#define LIBSPDM_FFDHE_2048_SUPPORT 1 #endif -#ifndef LIBSPDM_ECDHE_SUPPORT -#define LIBSPDM_ECDHE_SUPPORT 1 +#ifndef LIBSPDM_FFDHE_3072_SUPPORT +#define LIBSPDM_FFDHE_3072_SUPPORT 1 #endif -#ifndef LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT -#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT 1 +#ifndef LIBSPDM_FFDHE_4096_SUPPORT +#define LIBSPDM_FFDHE_4096_SUPPORT 1 #endif -#ifndef LIBSPDM_AEAD_GCM_SUPPORT -#define LIBSPDM_AEAD_GCM_SUPPORT 1 +#ifndef LIBSPDM_ECDHE_P256_SUPPORT +#define LIBSPDM_ECDHE_P256_SUPPORT 1 +#endif +#ifndef LIBSPDM_ECDHE_P384_SUPPORT +#define LIBSPDM_ECDHE_P384_SUPPORT 1 #endif +#ifndef LIBSPDM_ECDHE_P521_SUPPORT +#define LIBSPDM_ECDHE_P521_SUPPORT 1 +#endif + +#ifndef LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT +#define LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT 1 +#endif + +#ifndef LIBSPDM_AEAD_AES_128_GCM_SUPPORT +#define LIBSPDM_AEAD_AES_128_GCM_SUPPORT 1 +#endif +#ifndef LIBSPDM_AEAD_AES_256_GCM_SUPPORT +#define LIBSPDM_AEAD_AES_256_GCM_SUPPORT 1 +#endif + #ifndef LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT #define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 1 #endif -#ifndef LIBSPDM_AEAD_SM4_SUPPORT -#define LIBSPDM_AEAD_SM4_SUPPORT 1 + +#ifndef LIBSPDM_AEAD_SM4_128_GCM_SUPPORT +#define LIBSPDM_AEAD_SM4_128_GCM_SUPPORT 1 #endif #ifndef LIBSPDM_SHA256_SUPPORT @@ -166,6 +179,7 @@ #ifndef LIBSPDM_SHA512_SUPPORT #define LIBSPDM_SHA512_SUPPORT 1 #endif + #ifndef LIBSPDM_SHA3_256_SUPPORT #define LIBSPDM_SHA3_256_SUPPORT 1 #endif @@ -175,10 +189,16 @@ #ifndef LIBSPDM_SHA3_512_SUPPORT #define LIBSPDM_SHA3_512_SUPPORT 1 #endif + #ifndef LIBSPDM_SM3_256_SUPPORT #define LIBSPDM_SM3_256_SUPPORT 1 #endif +/* This can be set to 0 for the device which does not need X509 parser.*/ +#ifndef LIBSPDM_CERT_PARSE_SUPPORT +#define LIBSPDM_CERT_PARSE_SUPPORT 1 +#endif + /* Code space optimization for Optional request/response messages.*/ /* Consumers of libspdm may wish to not fully implement all of the optional @@ -192,17 +212,17 @@ /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP - Enable/Disable single CERT capability. * LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP - Enable/Disable single CHAL capability. - * LIBSPDM_ENABLE_CAPABILTIY_MEAS_CAP - Enable/Disables multiple MEAS capabilities: + * LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP - Enable/Disables multiple MEAS capabilities: * (MEAS_CAP_NO_SIG, MEAS_CAP_SIG, MEAS_FRESH_CAP)*/ /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP - Enable/Disable single Key Exchange capability. - * LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP - Enable/Disable PSK_EX and PSK_FINISH.*/ + * LIBSPDM_ENABLE_CAPABILITY_PSK_CAP - Enable/Disable PSK_EX and PSK_FINISH.*/ /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP - Enable/Disable mutual authentication. * LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP - Enable/Disable encapsulated message.*/ -/* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP - Enable/Disable get csr capability. - * LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP - Enable/Disable set certificate capability. */ +/* LIBSPDM_ENABLE_CAPABILITY_CSR_CAP - Enable/Disable get csr capability. + * LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP - Enable/Disable set certificate capability. */ #ifndef LIBSPDM_ENABLE_CAPABILITY_CERT_CAP #define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 @@ -220,8 +240,8 @@ #define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 #endif -#ifndef LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP -#define LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP 1 +#ifndef LIBSPDM_ENABLE_CAPABILITY_PSK_CAP +#define LIBSPDM_ENABLE_CAPABILITY_PSK_CAP 1 #endif #ifndef LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP @@ -236,18 +256,51 @@ #define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 1 #endif -#ifndef LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP -#define LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP 1 +#ifndef LIBSPDM_ENABLE_CAPABILITY_CSR_CAP +#define LIBSPDM_ENABLE_CAPABILITY_CSR_CAP 1 #endif -#ifndef LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP -#define LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP 1 +#ifndef LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP +#define LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP 1 #endif #ifndef LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP #define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 1 #endif +/* If 1 then endpoint supports sending GET_CERTIFICATE and GET_DIGESTS requests. + * If enabled and endpoint is a Responder then LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP + * must also be enabled. + */ +#ifndef LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT +#define LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT 1 +#endif + +/* If 1 then endpoint supports sending CHALLENGE request. + * If enabled and endpoint is a Responder then LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP + * must also be enabled. + */ +#ifndef LIBSPDM_SEND_CHALLENGE_SUPPORT +#define LIBSPDM_SEND_CHALLENGE_SUPPORT 1 +#endif + +/* When LIBSPDM_RESPOND_IF_READY_SUPPORT is 0 then + * - For a Requester, if the Responder sends a ResponseNotReady ERROR response then the error + * is immediately returned to the Integrator. The Requester cannot send a RESPOND_IF_READY + * request. + * - For a Responder, it cannot send a RESPOND_IF_READY ERROR response and does not support + * RESPOND_IF_READY. + * When LIBSPDM_RESPOND_IF_READY_SUPPORT is 1 then + * - For a Requester, if the Responder sends a ResponseNotReady ERROR response then libspdm + * waits an amount of time, as specified by the RDTExponent parameter, before sending + * RESPOND_IF_READY. + * - For a Responder, if its response state is NOT_READY then it will send a ResponseNotReady + * ERROR response to the Requester, and will accept a subsequent RESPOND_IF_READY request. + */ +#ifndef LIBSPDM_RESPOND_IF_READY_SUPPORT +#define LIBSPDM_RESPOND_IF_READY_SUPPORT 1 +#endif + /* * MinDataTransferSize = 42 * @@ -290,7 +343,7 @@ * | CHALLENGE 1.2 | 40 | 1 | * | CHALLENGE_AUTH 1.2 | 38 + H * 2 + S [+ O] = [166, 678] | [6, 23] | * +--------------------------+------------------------------------------+---------+ - * | GET_MEASUREMENTS 1.2 | 5 + Nounce (0 or 32) | 1 | + * | GET_MEASUREMENTS 1.2 | 5 + Nonce (0 or 32) | 1 | * | MEASUREMENTS 1.2 | 42 + MeasRecLen (+ S) [+ O] = [106, 554] | [4, 19] | * +--------------------------+------------------------------------------+---------+ * | KEY_EXCHANGE 1.2 | 42 + D [+ O] = [106, 554] | [4, 19] | @@ -313,93 +366,6 @@ * +==========================+==========================================+=========+ */ -/* Maximum size of a large SPDM message. - * If chunk is unsupported, it must be same as LIBSPDM_DATA_TRANSFER_SIZE. - * If chunk is supported, it must be larger than LIBSPDM_DATA_TRANSFER_SIZE. - * It matches MaxSPDMmsgSize in SPDM specification. */ -#ifndef LIBSPDM_MAX_SPDM_MSG_SIZE -#define LIBSPDM_MAX_SPDM_MSG_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE -#endif - -/* Maximum size of a single SPDM message. - * It matches DataTransferSize in SPDM specification. */ -#ifndef LIBSPDM_DATA_TRANSFER_SIZE -#define LIBSPDM_DATA_TRANSFER_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE -#endif - -/* Required sender/receive buffer in device io. - * NOTE: This is transport specific. Below configuration is just an example. - * +-------+--------+---------------------------+------+--+------+---+--------+-----+ - * | TYPE |TransHdr| EncryptionHeader |AppHdr| |Random|MAC|AlignPad|FINAL| - * | | |SessionId|SeqNum|Len|AppLen| | | | | | | - * +-------+--------+---------------------------+------+ +------+---+--------+-----+ - * | MCTP | 1 | 4 | 2 | 2 | 2 | 1 | | 32 | 12| 0 | 56 | - * |PCI_DOE| 8 | 4 | 0 | 2 | 2 | 0 | | 0 | 12| 3 | 31 | - * +-------+--------+---------------------------+------+--+------+---+--------+-----+ - */ -#ifndef LIBSPDM_TRANSPORT_ADDITIONAL_SIZE -#define LIBSPDM_TRANSPORT_ADDITIONAL_SIZE 64 -#endif -#ifndef LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE -#define LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE (LIBSPDM_DATA_TRANSFER_SIZE + \ - LIBSPDM_TRANSPORT_ADDITIONAL_SIZE) -#endif - - -/* Required scratch buffer size for libspdm internal usage. - * It may be used to hold the encrypted/decrypted message and/or last sent/received message. - * It may be used to hold the large request/response and intermediate send/receive buffer - * in case of chunking. - * - * If chunking is not supported, it may be just LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE. - * If chunking is supported, it should be at least below. - * - * +---------------+--------------+--------------------------+------------------------------+ - * |SECURE_MESSAGE |LARGE_MESSAGE | SENDER_RECEIVER | LARGE_SENDER_RECEIVER | - * +---------------+--------------+--------------------------+------------------------------+ - * |<-Secure msg ->|<-Large msg ->|<-Snd/Rcv buf for chunk ->|<-Snd/Rcv buf for large msg ->| - * - * The value is NOT configurable. - * The value MAY be changed in different libspdm version. - * It is exposed here, just in case the libspdm consumer wants to configure the setting at build time. - */ -#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP - -/* first section */ -#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_OFFSET 0 - -#define LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) - -/* second section */ -#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY) - -#define LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) - -/* third section */ -#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET \ - (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY) - -#define LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) - -/* fourth section */ -#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET \ - (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY) - -#define LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY (LIBSPDM_MAX_SPDM_MSG_SIZE) - -#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY + \ - LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY \ - ) - -#else -#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE) -#endif - /* Enable message logging. * See https://github.com/DMTF/libspdm/blob/main/doc/user_guide.md#message-logging * for more information */ @@ -412,4 +378,9 @@ #define LIBSPDM_CHECK_MACRO 0 #endif +/* Enable checks to the SPDM context during runtime. */ +#ifndef LIBSPDM_CHECK_SPDM_CONTEXT +#define LIBSPDM_CHECK_SPDM_CONTEXT 1 +#endif + #endif /* SPDM_LIB_CONFIG_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_requester_lib.h similarity index 64% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_requester_lib.h index eae8635a09..6062ba4405 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_requester_lib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_requester_lib.h @@ -9,52 +9,6 @@ #include "library/spdm_common_lib.h" -/** - * Send an SPDM or an APP request to a device. - * - * @param spdm_context The SPDM context for the device. - * @param session_id Indicate if the request is a secured message. - * If session_id is NULL, it is a normal message. - * If session_id is NOT NULL, it is a secured message. - * @param is_app_message Indicates if it is an APP message or SPDM message. - * @param request_size Size in bytes of the request data buffer. - * @param request A pointer to a destination buffer to store the request. - * The caller is responsible for having either implicit or explicit ownership - * of the buffer. - * For normal message, requester pointer point to transport_message + transport header size - * For secured message, requester pointer will point to the scratch buffer + transport header size in spdm_context. - * - * @retval RETURN_SUCCESS The SPDM request is sent successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM request is sent to the device. - **/ -libspdm_return_t libspdm_send_request(void *spdm_context, const uint32_t *session_id, - bool is_app_message, - size_t request_size, void *request); - -/** - * Receive an SPDM or an APP response from a device. - * - * @param spdm_context The SPDM context for the device. - * @param session_id Indicate if the response is a secured message. - * If session_id is NULL, it is a normal message. - * If session_id is NOT NULL, it is a secured message. - * @param is_app_message Indicates if it is an APP message or SPDM message. - * @param response_size Size in bytes of the response data buffer. - * @param response A pointer to a destination buffer to store the response. - * The caller is responsible for having either implicit or explicit - * ownership of the buffer. - * For normal message, response pointer still point to original transport_message. - * For secured message, response pointer will point to the scratch buffer in spdm_context. - * - * @retval RETURN_SUCCESS The SPDM response is received successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM response is received from the device. - **/ -libspdm_return_t libspdm_receive_response(void *spdm_context, - const uint32_t *session_id, - bool is_app_message, - size_t *response_size, - void **response); - /** * This function sends GET_VERSION, GET_CAPABILITIES, NEGOTIATE_ALGORITHMS * to initialize the connection with SPDM responder. @@ -70,35 +24,13 @@ libspdm_return_t libspdm_receive_response(void *spdm_context, **/ libspdm_return_t libspdm_init_connection(void *spdm_context, bool get_version_only); +#if LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT /** * This function sends GET_DIGEST to get all digest of the certificate chains from device. * - * If the peer certificate chain is deployed, this function also verifies the digest with the - * certificate chain. - * * TotalDigestSize = sizeof(digest) * count in slot_mask * * @param spdm_context A pointer to the SPDM context. - * @param slot_mask The slots which deploy the CertificateChain. - * @param total_digest_buffer A pointer to a destination buffer to store the digest buffer. - * - * @retval RETURN_SUCCESS The digests are got successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. - **/ -libspdm_return_t libspdm_get_digest(void *spdm_context, uint8_t *slot_mask, - void *total_digest_buffer); - -/** - * This function sends GET_DIGESTS and receives DIGESTS. It may retry GET_DIGESTS multiple times - * if the Responder replies with a Busy error. - * - * If the peer certificate chain is deployed, this function also verifies the digest with the - * certificate chain. - * - * TotalDigestSize = sizeof(digest) * count in slot_mask - * - * @param context A pointer to the SPDM context. * @param session_id Indicates if it is a secured message protected via SPDM session. * If session_id is NULL, it is a normal message. * If session_id is not NULL, it is a secured message. @@ -106,7 +38,7 @@ libspdm_return_t libspdm_get_digest(void *spdm_context, uint8_t *slot_mask, * @param total_digest_buffer A pointer to a destination buffer to store the digests. * * @retval LIBSPDM_STATUS_SUCCESS - * GET_DIGETS was sent and DIGESTS was received. + * GET_DIGESTS was sent and DIGESTS was received. * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL * Cannot send GET_DIGESTS due to Requester's state. * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP @@ -123,13 +55,9 @@ libspdm_return_t libspdm_get_digest(void *spdm_context, uint8_t *slot_mask, * The Responder returned a RequestResynch error message. * @retval LIBSPDM_STATUS_BUFFER_FULL * The buffer used to store transcripts is exhausted. - * @retval LIBSPDM_STATUS_VERIF_FAIL - * The digest of the stored certificate chain does not match the digest returned by - * the Responder. - * Note: This return value may be removed in the future. **/ -libspdm_return_t libspdm_get_digest_in_session(void *context, const uint32_t *session_id, - uint8_t *slot_mask, void *total_digest_buffer); +libspdm_return_t libspdm_get_digest(void *spdm_context, const uint32_t *session_id, + uint8_t *slot_mask, void *total_digest_buffer); /** * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. @@ -141,16 +69,41 @@ libspdm_return_t libspdm_get_digest_in_session(void *context, const uint32_t *se * this function also verifies the digest with the root hash in the certificate chain. * * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. * @param slot_id The number of slot for the certificate chain. * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. * On output, indicate the size in bytes of the certificate chain. * @param cert_chain A pointer to a destination buffer to store the certificate chain. * - * @retval RETURN_SUCCESS The certificate chain is got successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. + * @retval LIBSPDM_STATUS_SUCCESS + * GET_CERTIFICATE was sent and CERTIFICATE was received. + * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL + * Cannot send GET_CERTIFICATE due to Requester's state. + * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP + * Cannot send GET_CERTIFICATE because the Requester's and/or Responder's CERT_CAP = 0. + * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE + * The size of the CERTIFICATE response is invalid. + * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD + * The CERTIFICATE response contains one or more invalid fields. + * @retval LIBSPDM_STATUS_ERROR_PEER + * The Responder returned an unexpected error. + * @retval LIBSPDM_STATUS_BUSY_PEER + * The Responder continually returned Busy error messages. + * @retval LIBSPDM_STATUS_RESYNCH_PEER + * The Responder returned a RequestResynch error message. + * @retval LIBSPDM_STATUS_BUFFER_FULL + * The buffer used to store transcripts is exhausted. + * @retval LIBSPDM_STATUS_VERIF_FAIL + * Verification of the certificate chain failed. + * @retval LIBSPDM_STATUS_INVALID_CERT + * The certificate is unable to be parsed or contains invalid field values. + * @retval LIBSPDM_STATUS_CRYPTO_ERROR + * A generic cryptography error occurred. **/ -libspdm_return_t libspdm_get_certificate(void *spdm_context, uint8_t slot_id, +libspdm_return_t libspdm_get_certificate(void *spdm_context, + const uint32_t *session_id, + uint8_t slot_id, size_t *cert_chain_size, void *cert_chain); @@ -164,6 +117,8 @@ libspdm_return_t libspdm_get_certificate(void *spdm_context, uint8_t slot_id, * this function also verifies the digest with the root hash in the certificate chain. * * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. * @param slot_id The number of slot for the certificate chain. * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. * On output, indicate the size in bytes of the certificate chain. @@ -175,152 +130,14 @@ libspdm_return_t libspdm_get_certificate(void *spdm_context, uint8_t slot_id, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_certificate_ex(void *context, uint8_t slot_id, +libspdm_return_t libspdm_get_certificate_ex(void *spdm_context, + const uint32_t *session_id, + uint8_t slot_id, size_t *cert_chain_size, void *cert_chain, const void **trust_anchor, size_t *trust_anchor_size); - -/** - * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. - * - * This function verify the integrity of the certificate chain. - * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. - * - * If the peer root certificate hash is deployed, - * this function also verifies the digest with the root hash in the certificate chain. - * - * @param spdm_context A pointer to the SPDM context. - * @param session_id Indicates if it is a secured message protected via SPDM session. - * If session_id is NULL, it is a normal message. - * If session_id is NOT NULL, it is a secured message. - * @param slot_id The number of slot for the certificate chain. - * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. - * On output, indicate the size in bytes of the certificate chain. - * @param cert_chain A pointer to a destination buffer to store the certificate chain. - * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. - * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. - * - * @retval RETURN_SUCCESS The certificate chain is got successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. - **/ -libspdm_return_t libspdm_get_certificate_in_session(void *context, const uint32_t *session_id, - uint8_t slot_id, - size_t *cert_chain_size, - void *cert_chain, - const void **trust_anchor, - size_t *trust_anchor_size); - -/** - * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. - * - * This function verify the integrity of the certificate chain. - * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. - * - * If the peer root certificate hash is deployed, - * this function also verifies the digest with the root hash in the certificate chain. - * - * @param spdm_context A pointer to the SPDM context. - * @param slot_id The number of slot for the certificate chain. - * @param length LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN. - * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. - * On output, indicate the size in bytes of the certificate chain. - * @param cert_chain A pointer to a destination buffer to store the certificate chain. - * - * @retval RETURN_SUCCESS The certificate chain is got successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. - **/ -libspdm_return_t libspdm_get_certificate_choose_length(void *spdm_context, - uint8_t slot_id, - uint16_t length, - size_t *cert_chain_size, - void *cert_chain); - -/** - * This function sends GET_CERTIFICATE to get certificate chain in one slot from device. - * - * This function verify the integrity of the certificate chain. - * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. - * - * If the peer root certificate hash is deployed, - * this function also verifies the digest with the root hash in the certificate chain. - * - * @param spdm_context A pointer to the SPDM context. - * @param slot_id The number of slot for the certificate chain. - * @param length LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN. - * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store the digest buffer. - * On output, indicate the size in bytes of the certificate chain. - * @param cert_chain A pointer to a destination buffer to store the certificate chain. - * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. - * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. - * - * @retval RETURN_SUCCESS The certificate chain is got successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. - **/ -libspdm_return_t libspdm_get_certificate_choose_length_ex(void *context, - uint8_t slot_id, - uint16_t length, - size_t *cert_chain_size, - void *cert_chain, - const void **trust_anchor, - size_t *trust_anchor_size); - -/** - * This function sends GET_CERTIFICATE and receives CERTIFICATE. It may retry GET_CERTIFICATE - * multiple times if the Responder replies with a Busy error. - * - * This function verify the integrity of the certificate chain. - * root_hash -> Root certificate -> Intermediate certificate -> Leaf certificate. - * - * If the peer root certificate hash is deployed, - * this function also verifies the digest with the root hash in the certificate chain. - * - * @param spdm_context A pointer to the SPDM context. - * @param slot_id The number of slot for the certificate chain. - * @param cert_chain_size On input, indicate the size in bytes of the destination buffer to store - * the digest buffer. - * On output, indicate the size in bytes of the certificate chain. - * @param cert_chain A pointer to a destination buffer to store the certificate chain. - * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer - * certificate, if not NULL. - * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. - * - * @retval LIBSPDM_STATUS_SUCCESS - * GET_CERTIFICATE was sent and CERTIFICATE was received. - * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL - * Cannot send GET_CERTIFICATE due to Requester's state. - * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP - * Cannot send GET_CERTIFICATE because the Requester's and/or Responder's CERT_CAP = 0. - * @retval LIBSPDM_STATUS_INVALID_MSG_SIZE - * The size of the CERTIFICATE response is invalid. - * @retval LIBSPDM_STATUS_INVALID_MSG_FIELD - * The CERTIFICATE response contains one or more invalid fields. - * @retval LIBSPDM_STATUS_ERROR_PEER - * The Responder returned an unexpected error. - * @retval LIBSPDM_STATUS_BUSY_PEER - * The Responder continually returned Busy error messages. - * @retval LIBSPDM_STATUS_RESYNCH_PEER - * The Responder returned a RequestResynch error message. - * @retval LIBSPDM_STATUS_BUFFER_FULL - * The buffer used to store transcripts is exhausted. - * @retval LIBSPDM_STATUS_VERIF_FAIL - * Verification of the certificate chain failed. - * @retval LIBSPDM_STATUS_INVALID_CERT - * The certificate is unable to be parsed or contains invalid field values. - * @retval LIBSPDM_STATUS_CRYPTO_ERROR - * A generic cryptography error occurred. - **/ -libspdm_return_t libspdm_get_certificate_choose_length_in_session(void *context, - const uint32_t *session_id, - uint8_t slot_id, - uint16_t length, - size_t *cert_chain_size, - void *cert_chain, - const void **trust_anchor, - size_t *trust_anchor_size); +#endif /* LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT */ /** * This function sends CHALLENGE to authenticate the device based upon the key in one slot. @@ -331,6 +148,7 @@ libspdm_return_t libspdm_get_certificate_choose_length_in_session(void *context, * this function also perform the basic mutual authentication. * * @param spdm_context A pointer to the SPDM context. + * @param reserved Reserved for session_id and is ignored. * @param slot_id The number of slot for the challenge. * @param measurement_hash_type The type of the measurement hash. * @param measurement_hash A pointer to a destination buffer to store the measurement hash. @@ -340,7 +158,8 @@ libspdm_return_t libspdm_get_certificate_choose_length_in_session(void *context, * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_challenge(void *spdm_context, uint8_t slot_id, +libspdm_return_t libspdm_challenge(void *spdm_context, void *reserved, + uint8_t slot_id, uint8_t measurement_hash_type, void *measurement_hash, uint8_t *slot_mask); @@ -351,9 +170,10 @@ libspdm_return_t libspdm_challenge(void *spdm_context, uint8_t slot_id, * This function verifies the signature in the challenge auth. * * If basic mutual authentication is requested from the responder, - * this function also perform the basic mutual authentication. + * this function also performs the basic mutual authentication. * * @param spdm_context A pointer to the SPDM context. + * @param reserved Reserved for session_id and is ignored. * @param slot_id The number of slot for the challenge. * @param measurement_hash_type The type of the measurement hash. * @param measurement_hash A pointer to a destination buffer to store the measurement hash. @@ -361,18 +181,21 @@ libspdm_return_t libspdm_challenge(void *spdm_context, uint8_t slot_id, * @param requester_nonce_in A buffer to hold the requester nonce (32 bytes) as input, if not NULL. * @param requester_nonce A buffer to hold the requester nonce (32 bytes), if not NULL. * @param responder_nonce A buffer to hold the responder nonce (32 bytes), if not NULL. - * - * @retval RETURN_SUCCESS The challenge auth is got successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. + * @param opaque_data A buffer to hold the responder opaque data, if not NULL. + * @param opaque_data_size On input, the size of the opaque data buffer. + * Responder opaque data should be less than 1024 bytes. + * On output, the size of the opaque data. **/ -libspdm_return_t libspdm_challenge_ex(void *context, uint8_t slot_id, +libspdm_return_t libspdm_challenge_ex(void *spdm_context, void *reserved, + uint8_t slot_id, uint8_t measurement_hash_type, void *measurement_hash, uint8_t *slot_mask, const void *requester_nonce_in, void *requester_nonce, - void *responder_nonce); + void *responder_nonce, + void *opaque_data, + size_t *opaque_data_size); /** * This function sends GET_MEASUREMENT @@ -426,12 +249,12 @@ libspdm_return_t libspdm_get_measurement(void *spdm_context, const uint32_t *ses * @param requester_nonce_in A buffer to hold the requester nonce (32 bytes) as input, if not NULL. * @param requester_nonce A buffer to hold the requester nonce (32 bytes), if not NULL. * @param responder_nonce A buffer to hold the responder nonce (32 bytes), if not NULL. - * - * @retval RETURN_SUCCESS The measurement is got successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. + * @param opaque_data A buffer to hold the responder opaque data, if not NULL. + * @param opaque_data_size On input, the size of the opaque data buffer. + * Responder opaque data should be less than 1024 bytes. + * On output, the size of the opaque data. **/ -libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *session_id, +libspdm_return_t libspdm_get_measurement_ex(void *spdm_context, const uint32_t *session_id, uint8_t request_attribute, uint8_t measurement_operation, uint8_t slot_id, @@ -441,9 +264,11 @@ libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *sessi void *measurement_record, const void *requester_nonce_in, void *requester_nonce, - void *responder_nonce); + void *responder_nonce, + void *opaque_data, + size_t *opaque_data_size); -#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) /** * This function sends KEY_EXCHANGE/FINISH or PSK_EXCHANGE/PSK_FINISH * to start an SPDM Session. @@ -454,6 +279,8 @@ libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *sessi * @param spdm_context A pointer to the SPDM context. * @param use_psk False means to use KEY_EXCHANGE/FINISH to start a session. * True means to use PSK_EXCHANGE/PSK_FINISH to start a session. + * @param psk_hint The psk_hint in PSK_EXCHANGE. It is ignored if use_psk is false. + * @param psk_hint_size The size in bytes of psk_hint. It is ignored if use_psk is false. * @param measurement_hash_type The type of the measurement hash. * @param slot_id The number of slot for the certificate chain. * @param session_policy The policy for the session. @@ -466,6 +293,8 @@ libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *sessi * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ libspdm_return_t libspdm_start_session(void *spdm_context, bool use_psk, + const void *psk_hint, + uint16_t psk_hint_size, uint8_t measurement_hash_type, uint8_t slot_id, uint8_t session_policy, @@ -479,36 +308,44 @@ libspdm_return_t libspdm_start_session(void *spdm_context, bool use_psk, * If encapsulated mutual authentication is requested from the responder, * this function also perform the encapsulated mutual authentication. * - * @param spdm_context A pointer to the SPDM context. - * @param use_psk False means to use KEY_EXCHANGE/FINISH to start a session. - * True means to use PSK_EXCHANGE/PSK_FINISH to start a session. - * @param measurement_hash_type The type of the measurement hash. - * @param slot_id The number of slot for the certificate chain. - * @param session_policy The policy for the session. - * @param session_id The session ID of the session. - * @param heartbeat_period The heartbeat period for the session. - * @param measurement_hash A pointer to a destination buffer to store the measurement hash. - * @param requester_random_in A buffer to hold the requester random as input, if not NULL. - * @param requester_random_in_size The size of requester_random_in. - * If use_psk is false, it must be 32 bytes. - * If use_psk is true, it means the PSK context and must be 32 bytes at least, - * but not exceed LIBSPDM_PSK_CONTEXT_LENGTH. - * @param requester_random A buffer to hold the requester random, if not NULL. - * @param requester_random_size On input, the size of requester_random buffer. - * On output, the size of data returned in requester_random buffer. - * If use_psk is false, it must be 32 bytes. - * If use_psk is true, it means the PSK context and must be 32 bytes at least. - * @param responder_random A buffer to hold the responder random, if not NULL. - * @param responder_random_size On input, the size of requester_random buffer. - * On output, the size of data returned in requester_random buffer. - * If use_psk is false, it must be 32 bytes. - * If use_psk is true, it means the PSK context. It could be 0 if device does not support context. - * - * @retval RETURN_SUCCESS The SPDM session is started. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. + * @param spdm_context A pointer to the SPDM context. + * @param use_psk False means to use KEY_EXCHANGE/FINISH to start a session. + * True means to use PSK_EXCHANGE/PSK_FINISH to start a session. + * @param psk_hint The psk_hint in PSK_EXCHANGE. It is ignored if use_psk is false. + * @param psk_hint_size The size in bytes of psk_hint. It is ignored if use_psk is false. + * @param measurement_hash_type The type of the measurement hash. + * @param slot_id The number of slot for the certificate chain. + * @param session_policy The policy for the session. + * @param session_id The session ID of the session. + * @param heartbeat_period The heartbeat period for the session. + * @param measurement_hash A pointer to a destination buffer to store the measurement hash. + * @param requester_random_in A buffer to hold the requester random as input, if not NULL. + * @param requester_random_in_size The size of requester_random_in. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context and must be 32 bytes at least, + * but not exceed LIBSPDM_PSK_CONTEXT_LENGTH. + * @param requester_random A buffer to hold the requester random, if not NULL. + * @param requester_random_size On input, the size of requester_random buffer. + * On output, the size of data returned in requester_random buffer. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context and must be 32 bytes at least. + * @param responder_random A buffer to hold the responder random, if not NULL. + * @param responder_random_size On input, the size of requester_random buffer. + * On output, the size of data returned in requester_random buffer. + * If use_psk is false, it must be 32 bytes. + * If use_psk is true, it means the PSK context. It could be 0 if device does not support context. + * @param requester_opaque_data A buffer to hold the requester opaque data, if not NULL. + * If not NULL, this function will not generate any opaque data, + * including secured message versions. + * @param requester_opaque_data_size The size of the opaque data, if requester_opaque_data is not NULL. + * @param responder_opaque_data A buffer to hold the responder opaque data, if not NULL. + * @param responder_opaque_data_size On input, the size of the opaque data buffer. + * Opaque data should be less than 1024 bytes. + * On output, the size of the opaque data. **/ libspdm_return_t libspdm_start_session_ex(void *spdm_context, bool use_psk, + const void *psk_hint, + uint16_t psk_hint_size, uint8_t measurement_hash_type, uint8_t slot_id, uint8_t session_policy, @@ -520,7 +357,11 @@ libspdm_return_t libspdm_start_session_ex(void *spdm_context, bool use_psk, void *requester_random, size_t *requester_random_size, void *responder_random, - size_t *responder_random_size); + size_t *responder_random_size, + const void *requester_opaque_data, + size_t requester_opaque_data_size, + void *responder_opaque_data, + size_t *responder_opaque_data_size); /** * This function sends END_SESSION to stop an SPDM Session. @@ -535,10 +376,10 @@ libspdm_return_t libspdm_start_session_ex(void *spdm_context, bool use_psk, **/ libspdm_return_t libspdm_stop_session(void *spdm_context, uint32_t session_id, uint8_t end_session_attributes); -#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) */ /** - * Send and receive an SPDM or APP message. + * Send an SPDM or APP message. * * The SPDM message can be a normal message or a secured message in SPDM session. * @@ -553,23 +394,66 @@ libspdm_return_t libspdm_stop_session(void *spdm_context, uint32_t session_id, * @param is_app_message Indicates if it is an APP message or SPDM message. * @param request A pointer to the request data. * @param request_size Size in bytes of the request data. + **/ +libspdm_return_t libspdm_send_data(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + const void *request, size_t request_size); + +/** + * Receive an SPDM or APP message. + * + * The SPDM message can be a normal message or a secured message in SPDM session. + * + * The APP message is encoded to a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. * @param response A pointer to the response data. * @param response_size Size in bytes of the response data. * On input, it means the size in bytes of response data buffer. - * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned, - * and means the size in bytes of desired response data buffer if RETURN_BUFFER_TOO_SMALL is returned. + * On output, it means the size in bytes of copied response data buffer if + * LIBSPDM_STATUS_SUCCESS is returned, and means the size in bytes of + * desired response data buffer if LIBSPDM_STATUS_BUFFER_TOO_SMALL is + * returned. + **/ +libspdm_return_t libspdm_receive_data(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + void *response, size_t *response_size); + +/** + * Send and receive an SPDM or APP message. * - * @retval RETURN_SUCCESS The SPDM request is set successfully. - * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. + * The SPDM message can be a normal message or a secured message in SPDM session. + * + * The APP message is encoded to a secured message directly in SPDM session. + * The APP message format is defined by the transport layer. + * Take MCTP as example: APP message == MCTP header (MCTP_MESSAGE_TYPE_SPDM) + SPDM message + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. + * @param is_app_message Indicates if it is an APP message or SPDM message. + * @param request A pointer to the request data. + * @param request_size Size in bytes of the request data. + * @param response A pointer to the response data. + * @param response_size Size in bytes of the response data. + * On input, it means the size in bytes of response data buffer. + * On output, it means the size in bytes of copied response data buffer if + * LIBSPDM_STATUS_SUCCESS is returned, and means the size in bytes of + * desired response data buffer if LIBSPDM_STATUS_BUFFER_TOO_SMALL is + * returned. **/ libspdm_return_t libspdm_send_receive_data(void *spdm_context, const uint32_t *session_id, bool is_app_message, const void *request, size_t request_size, - void *response, - size_t *response_size); + void *response, size_t *response_size); /** * This function sends HEARTBEAT @@ -697,57 +581,53 @@ libspdm_return_t libspdm_generate_encap_extended_error_response( size_t extended_error_data_size, const uint8_t *extended_error_data, size_t *spdm_response_size, void *spdm_response); -#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +#if LIBSPDM_ENABLE_CAPABILITY_CSR_CAP /** * This function sends GET_CSR * to get csr from the device. * * @param[in] context A pointer to the SPDM context. - * @param[in] requester_info Requester info to gen CSR - * @param[in] requester_info_length The length of requester info - * @param[in] opaque_data opaque data. - * @param[in] opaque_data_length The length of opaque data. * @param[in] session_id Indicates if it is a secured message protected via SPDM session. * If session_id is NULL, it is a normal message. * If session_id is NOT NULL, it is a secured message. + * @param[in] requester_info Requester info to gen CSR + * @param[in] requester_info_length The length of requester info + * @param[in] opaque_data Opaque data from requester. + * @param[in] opaque_data_length The length of opaque_data. * @param[out] csr Address to store CSR. * @param[out] csr_len On input, *csr_len indicates the max csr buffer size. * On output, *csr_len indicates the actual csr buffer size. - * - * @retval RETURN_SUCCESS The measurement is got successfully. - * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. - * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_get_csr(void *context, +libspdm_return_t libspdm_get_csr(void *spdm_context, + const uint32_t *session_id, void *requester_info, uint16_t requester_info_length, void *opaque_data, uint16_t opaque_data_length, - const uint32_t *session_id, void *csr, size_t *csr_len); -#endif /*LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP*/ +#endif /*LIBSPDM_ENABLE_CAPABILITY_CSR_CAP*/ -#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP || LIBSPDM_ENABLE_SET_CERTIFICATE_CAP +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP /** * This function try to send SET_CERTIFICATE * to set certificate from the device. * * @param context A pointer to the SPDM context. + * @param session_id Indicates if it is a secured message protected via SPDM session. + * If session_id is NULL, it is a normal message. + * If session_id is NOT NULL, it is a secured message. * @param slot_id The number of slot for the certificate chain. * @param cert_chain The pointer for the certificate chain to set. * The cert chain is a full SPDM certificate chain, including Length and Root Cert Hash. * @param cert_chain_size The size of the certificate chain to set. - * @param session_id Indicates if it is a secured message protected via SPDM session. - * If session_id is NULL, it is a normal message. - * If session_id is NOT NULL, it is a secured message. * * @retval RETURN_SUCCESS The measurement is got successfully. * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -libspdm_return_t libspdm_set_certificate(void * context, uint8_t slot_id, - void * cert_chain, size_t cert_chain_size, - const uint32_t *session_id); +libspdm_return_t libspdm_set_certificate(void *spdm_context, + const uint32_t *session_id, uint8_t slot_id, + void *cert_chain, size_t cert_chain_size); -#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP */ #if LIBSPDM_ENABLE_MSG_LOG /* For now these functions are only available to the Requester. They may become available to the @@ -762,7 +642,7 @@ libspdm_return_t libspdm_set_certificate(void * context, uint8_t slot_id, * @param msg_buffer A pointer to a caller-provided buffer. * @param msg_buffer_size The size of the buffer in bytes. It must be greater than zero. **/ -void libspdm_init_msg_log (void *context, void *msg_buffer, size_t msg_buffer_size); +void libspdm_init_msg_log (void *spdm_context, void *msg_buffer, size_t msg_buffer_size); /** * This function sets the mode in which the message logger operates. @@ -771,7 +651,7 @@ void libspdm_init_msg_log (void *context, void *msg_buffer, size_t msg_buffer_si * @param mode A bitmask specifying the mode in which the message logger operates. * LIBSPDM_MSG_LOG_MODE_ENABLE - when set the message logger is active. */ -void libspdm_set_msg_log_mode (void *context, uint32_t mode); +void libspdm_set_msg_log_mode (void *spdm_context, uint32_t mode); /** * This function returns the status of the message logger. @@ -782,7 +662,7 @@ void libspdm_set_msg_log_mode (void *context, uint32_t mode); * LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL - if set the message logging buffer has * reached capacity. */ -uint32_t libspdm_get_msg_log_status (void *context); +uint32_t libspdm_get_msg_log_status (void *spdm_context); /** * This function returns the size of the message log. @@ -790,7 +670,7 @@ uint32_t libspdm_get_msg_log_status (void *context); * @param context A pointer to the SPDM context. * @retval size_t The size of the message log in bytes. */ -size_t libspdm_get_msg_log_size (void *context); +size_t libspdm_get_msg_log_size (void *spdm_context); /** * This function resets the message log while retaining the message buffer and maximum size given in @@ -798,7 +678,7 @@ size_t libspdm_get_msg_log_size (void *context); * * @param context A pointer to the SPDM context. */ -void libspdm_reset_msg_log (void *context); +void libspdm_reset_msg_log (void *spdm_context); #endif /* LIBSPDM_ENABLE_MSG_LOG */ #endif /* SPDM_REQUESTER_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_responder_lib.h similarity index 92% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_responder_lib.h index f4bf958f26..13b960fd27 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_responder_lib.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_responder_lib.h @@ -8,6 +8,7 @@ #define SPDM_RESPONDER_LIB_H #include "library/spdm_common_lib.h" +#include "library/spdm_secured_message_lib.h" /** * Process the SPDM or APP request and return the response. @@ -155,7 +156,7 @@ libspdm_return_t libspdm_generate_error_response(const void *spdm_context, * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. **/ libspdm_return_t libspdm_generate_extended_error_response( - const void *context, uint8_t error_code, uint8_t error_data, + const void *spdm_context, uint8_t error_code, uint8_t error_data, size_t extended_error_data_size, const uint8_t *extended_error_data, size_t *spdm_response_size, void *spdm_response); @@ -177,11 +178,8 @@ typedef void (*libspdm_session_state_callback_func)( * * @param spdm_context A pointer to the SPDM context. * @param spdm_session_state_callback The function to be called in SPDM session state change. - * - * @retval RETURN_SUCCESS The callback is registered. - * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. **/ -libspdm_return_t libspdm_register_session_state_callback_func( +void libspdm_register_session_state_callback_func( void *spdm_context, libspdm_session_state_callback_func spdm_session_state_callback); @@ -201,11 +199,8 @@ typedef void (*libspdm_connection_state_callback_func)( * * @param spdm_context A pointer to the SPDM context. * @param spdm_connection_state_callback The function to be called in SPDM connection state change. - * - * @retval RETURN_SUCCESS The callback is registered. - * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. **/ -libspdm_return_t libspdm_register_connection_state_callback_func( +void libspdm_register_connection_state_callback_func( void *spdm_context, libspdm_connection_state_callback_func spdm_connection_state_callback); @@ -240,11 +235,8 @@ void libspdm_trigger_key_update_callback( * * @param spdm_context A pointer to the SPDM context. * @param spdm_key_update_callback The function to be called in key update operation. - * - * @retval RETURN_SUCCESS The callback is registered. - * @retval RETURN_ALREADY_STARTED No enough memory to register the callback. **/ -libspdm_return_t libspdm_register_key_update_callback_func( +void libspdm_register_key_update_callback_func( void *spdm_context, libspdm_key_update_callback_func spdm_key_update_callback); /** @@ -254,4 +246,20 @@ libspdm_return_t libspdm_register_key_update_callback_func( **/ void libspdm_init_key_update_encap_state(void *spdm_context); -#endif /*SPDM_RESPONDER_LIB_H */ +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) && \ + (LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT) +/** + * Register a buffer to store the Requester's certificate chain during mutual authentication. + * + * This is only required if the Requester is providing a certificate chain (Requester's CERT_CAP + * is 1) during mutual authentication. + * + * @param spdm_context A pointer to the SPDM context. + * @param cert_chain_buffer A pointer to a buffer to store the certificate chain. + * @param cert_chain_buffer_max_size The maximum size, in bytes, of cert_chain_buffer. + */ +void libspdm_register_cert_chain_buffer( + void *spdm_context, void *cert_chain_buffer, size_t cert_chain_buffer_max_size); +#endif + +#endif /* SPDM_RESPONDER_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_return_status.h similarity index 85% rename from src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h rename to src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_return_status.h index eebb0f3de9..5e5507b7f3 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/include/library/spdm_return_status.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_return_status.h @@ -29,6 +29,10 @@ typedef uint32_t libspdm_return_t; #define LIBSPDM_STATUS_IS_ERROR(status) \ (LIBSPDM_STATUS_SEVERITY(status) == LIBSPDM_SEVERITY_ERROR) +/* Returns 1 if severity is LIBSPDM_SEVERITY_WARNING else it returns 0. */ +#define LIBSPDM_STATUS_IS_WARNING(status) \ + (LIBSPDM_STATUS_SEVERITY(status) == LIBSPDM_SEVERITY_WARNING) + /* Returns the severity of the status. */ #define LIBSPDM_STATUS_SEVERITY(status) (((status) >> 28) & 0xf) @@ -36,16 +40,13 @@ typedef uint32_t libspdm_return_t; #define LIBSPDM_STATUS_SOURCE(status) (((status) >> 16) & 0xff) #define LIBSPDM_SEVERITY_SUCCESS 0x0 +#define LIBSPDM_SEVERITY_WARNING 0x4 #define LIBSPDM_SEVERITY_ERROR 0x8 #define LIBSPDM_SOURCE_SUCCESS 0x00 #define LIBSPDM_SOURCE_CORE 0x01 #define LIBSPDM_SOURCE_CRYPTO 0x02 #define LIBSPDM_SOURCE_CERT_PARSE 0x03 - -/*LIBSPSM_SOURCE_TRANSPORT is deprecated. Do not use it. Reserved only.*/ -#define LIBSPSM_SOURCE_TRANSPORT 0x04 - #define LIBSPDM_SOURCE_TRANSPORT 0x04 #define LIBSPDM_SOURCE_MEAS_COLLECT 0x05 #define LIBSPDM_SOURCE_RNG 0x06 @@ -136,6 +137,18 @@ typedef uint32_t libspdm_return_t; #define LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE \ LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0011) +/* The device needs a reset after the operation (such as set certificate). */ +#define LIBSPDM_STATUS_RESET_REQUIRED_PEER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0012) + +/* Message is too large to send to peer. */ +#define LIBSPDM_STATUS_PEER_BUFFER_TOO_SMALL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CORE, 0x0013) + +/* A parameter passed by the Integrator was overridden. */ +#define LIBSPDM_STATUS_OVERRIDDEN_PARAMETER \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_WARNING, LIBSPDM_SOURCE_CORE, 0x0014) + /* - Cryptography Errors - */ /* Generic failure originating from the cryptography module. */ @@ -150,6 +163,14 @@ typedef uint32_t libspdm_return_t; #define LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW \ LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CRYPTO, 0x0002) +/* Provided cert is valid but is not authoritative(mismatch the root cert). */ +#define LIBSPDM_STATUS_VERIF_NO_AUTHORITY \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_WARNING, LIBSPDM_SOURCE_CRYPTO, 0x0003) + +/* FIPS test failed */ +#define LIBSPDM_STATUS_FIPS_FAIL \ + LIBSPDM_STATUS_CONSTRUCT(LIBSPDM_SEVERITY_ERROR, LIBSPDM_SOURCE_CRYPTO, 0x0004) + /* - Certificate Parsing Errors - */ /* Certificate is malformed or does not comply to x.509 standard. */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_secured_message_lib.h b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_secured_message_lib.h new file mode 100644 index 0000000000..8c61f38a06 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/include/library/spdm_secured_message_lib.h @@ -0,0 +1,298 @@ +/** + * Copyright Notice: + * Copyright 2021-2023 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#ifndef SPDM_SECURED_MESSAGE_LIB_H +#define SPDM_SECURED_MESSAGE_LIB_H + +#include "hal/base.h" +#include "industry_standard/spdm.h" +#include "industry_standard/spdm_secured_message.h" +#include "library/spdm_return_status.h" + +typedef enum { + LIBSPDM_SESSION_TYPE_NONE, + LIBSPDM_SESSION_TYPE_MAC_ONLY, + LIBSPDM_SESSION_TYPE_ENC_MAC, + LIBSPDM_SESSION_TYPE_MAX +} libspdm_session_type_t; + +typedef enum { + /* Before send KEY_EXCHANGE/PSK_EXCHANGE or after END_SESSION */ + LIBSPDM_SESSION_STATE_NOT_STARTED, + + /* After send KEY_EXCHANGE, before send FINISH */ + LIBSPDM_SESSION_STATE_HANDSHAKING, + + /* After send FINISH, before END_SESSION */ + LIBSPDM_SESSION_STATE_ESTABLISHED, + + /* MAX */ + LIBSPDM_SESSION_STATE_MAX +} libspdm_session_state_t; + +/* The InvalidSession error code was removed from the specification. This define was originally + * in spdm.h and has moved here since it is used in transport decode functions to convey that + * the session ID is not recognizable. + */ +#define SPDM_ERROR_CODE_INVALID_SESSION 0x02 + +/** + * Return the size in bytes of a single SPDM secured message context. + * + * @return the size in bytes of a single SPDM secured message context. + **/ +size_t libspdm_secured_message_get_context_size(void); + +/** + * Return session_state of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * + * @return the SPDM session state. + */ +libspdm_session_state_t libspdm_secured_message_get_session_state( + void *spdm_secured_message_context); + +/** + * Import the DHE Secret to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param dhe_secret Indicate the DHE secret. + * @param dhe_secret_size The size, in bytes, of the DHE secret. + */ +bool libspdm_secured_message_import_dhe_secret(void *spdm_secured_message_context, + const void *dhe_secret, + size_t dhe_secret_size); + +/** + * Export the Export Master Secret from an SPDM secured message context. + * + * The size of the Export Master Secret is the size of the digest of the negotiated hash algorithm. + * If the size of the destination buffer is less than the size of the Export Master Secret then + * the first export_master_secret_size bytes are copied. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param export_master_secret A pointer to the buffer to store the export_master_secret. + * @param export_master_secret_size On input, the size of the destination buffer. + * On output, the lesser of either the size of the destination + * buffer or the size of the Export Master Secret. + */ +bool libspdm_secured_message_export_master_secret( + void *spdm_secured_message_context, void *export_master_secret, + size_t *export_master_secret_size); + +/** + * Erase the Export Master Secret from an SPDM secured message context. + * + * This is typically called after libspdm_secured_message_export_master_secret(). + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + */ +void libspdm_secured_message_clear_export_master_secret(void *spdm_secured_message_context); + +#define LIBSPDM_SECURE_SESSION_KEYS_STRUCT_VERSION 1 + +#pragma pack(1) +typedef struct { + uint32_t version; + uint32_t aead_key_size; + uint32_t aead_iv_size; + /* uint8_t request_data_encryption_key[aead_key_size]; + * uint8_t request_data_salt[aead_iv_size]; + * uint64_t request_data_sequence_number; + * uint8_t response_data_encryption_key[aead_key_size]; + * uint8_t response_data_salt[aead_iv_size]; + * uint64_t response_data_sequence_number;*/ +} libspdm_secure_session_keys_struct_t; +#pragma pack() + +/** + * Export the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in + * libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in + * libspdm_secure_session_keys_struct_t. + */ +bool libspdm_secured_message_export_session_keys(void *spdm_secured_message_context, + void *session_keys, + size_t *session_keys_size); + +/** + * Import the session_keys from an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_keys Indicate the buffer to store the session_keys in + * libspdm_secure_session_keys_struct_t. + * @param session_keys_size The size in bytes of the session_keys in + * libspdm_secure_session_keys_struct_t. + */ +bool libspdm_secured_message_import_session_keys(void *spdm_secured_message_context, + const void *session_keys, + size_t session_keys_size); + +/** + * This function is used to clear handshake secret. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + **/ +void libspdm_clear_handshake_secret(void *spdm_secured_message_context); + +/** + * This function is used to clear the master secret; + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + **/ +void libspdm_clear_master_secret(void *spdm_secured_message_context); + +/** + * This function concatenates binary data, which is used as info in HKDF expand later. + * + * @param label An ascii string label for the libspdm_bin_concat. + * @param label_size The size in bytes of the ASCII string label, not including NULL terminator. + * @param context A pre-defined hash value as the context for the libspdm_bin_concat. + * @param length 16 bits length for the libspdm_bin_concat. + * @param hash_size The size in bytes of the context hash. + * @param out_bin The buffer to store the output binary. + * @param out_bin_size The size in bytes for the out_bin. + **/ +void libspdm_bin_concat(spdm_version_number_t spdm_version, + const char *label, size_t label_size, + const uint8_t *context, uint16_t length, + size_t hash_size, uint8_t *out_bin, + size_t *out_bin_size); + +typedef enum { + LIBSPDM_KEY_UPDATE_OPERATION_CREATE_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_COMMIT_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_DISCARD_UPDATE, + LIBSPDM_KEY_UPDATE_OPERATION_MAX +} libspdm_key_update_operation_t; + +typedef enum { + LIBSPDM_KEY_UPDATE_ACTION_REQUESTER, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, + LIBSPDM_KEY_UPDATE_ACTION_MAX +} libspdm_key_update_action_t; + +/** + * Get sequence number in an SPDM secure message. + * + * This value is transport layer specific. + * + * @param sequence_number The current sequence number used to encode or decode message. + * @param sequence_number_buffer A buffer to hold the sequence number output used in the secured message. + * The size in byte of the output buffer shall be 8. + * + * @return size in byte of the sequence_number_buffer. + * It shall be no greater than 8. + * 0 means no sequence number is required. + **/ +typedef uint8_t (*libspdm_secured_message_get_sequence_number_func)( + uint64_t sequence_number, uint8_t *sequence_number_buffer); + +/** + * Return max random number count in an SPDM secure message. + * + * This value is transport layer specific. + * + * @return Max random number count in an SPDM secured message. + * 0 means no random number is required. + **/ +typedef uint32_t (*libspdm_secured_message_get_max_random_number_count_func)(void); + +/** + * This function translates the negotiated secured_message_version to a DSP0277 version. + * + * @param secured_message_version The version specified in binding specification and + * negotiated in KEY_EXCHANGE/KEY_EXCHANGE_RSP. + * + * @return The DSP0277 version specified in binding specification, + * which is bound to secured_message_version. + */ +typedef spdm_version_number_t (*libspdm_secured_message_get_secured_spdm_version)( + spdm_version_number_t secured_message_version); + +#define LIBSPDM_SECURED_MESSAGE_CALLBACKS_VERSION 2 + +typedef struct { + uint32_t version; + libspdm_secured_message_get_sequence_number_func get_sequence_number; + libspdm_secured_message_get_max_random_number_count_func get_max_random_number_count; + libspdm_secured_message_get_secured_spdm_version get_secured_spdm_version; +} libspdm_secured_message_callbacks_t; + +typedef struct { + uint8_t error_code; + uint32_t session_id; +} libspdm_error_struct_t; + +/** + * Encode an application message to a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_request_message Indicates if it is a request message. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a source buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer. + * Before app_message, there is room for spdm_secured_message_cipher_header_t. + * After (app_message + app_message_size), there is room for random bytes. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a destination buffer to store the secured message. + * It shall point to the acquired sender buffer. + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is encoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + **/ +libspdm_return_t libspdm_encode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_request_message, size_t app_message_size, + void *app_message, size_t *secured_message_size, + void *secured_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks); + +/** + * Decode an application message from a secured message. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param session_id The session ID of the SPDM session. + * @param is_request_message Indicates if it is a request message. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a source buffer to store the secured message. + * It shall point to the acquired receiver buffer. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a destination buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer to hold the decrypted message + * On output, the app_message pointer shall be inside of [app_message, app_message + app_message_size] + * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. + * + * @retval RETURN_SUCCESS The application message is decoded successfully. + * @retval RETURN_INVALID_PARAMETER The message is NULL or the message_size is zero. + * @retval RETURN_UNSUPPORTED The secured_message is unsupported. + **/ +libspdm_return_t libspdm_decode_secured_message( + void *spdm_secured_message_context, uint32_t session_id, + bool is_request_message, size_t secured_message_size, + void *secured_message, size_t *app_message_size, + void **app_message, + const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks); + +/** + * Get the last SPDM error struct of an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param last_spdm_error Last SPDM error struct of an SPDM secured message context. + */ +void libspdm_secured_message_get_last_spdm_error_struct( + void *spdm_secured_message_context, + libspdm_error_struct_t *last_spdm_error); + +#endif /* SPDM_SECURED_MESSAGE_LIB_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_context_data.c similarity index 61% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_context_data.c index b93f13ba61..cfe5dc4454 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_context_data.c @@ -6,6 +6,118 @@ #include "internal/libspdm_common_lib.h" #include "internal/libspdm_secured_message_lib.h" +#include "internal/libspdm_fips_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP +/* first section */ +uint32_t libspdm_get_scratch_buffer_secure_message_offset(libspdm_context_t *spdm_context) { + return 0; +} + +uint32_t libspdm_get_scratch_buffer_secure_message_capacity(libspdm_context_t *spdm_context) { + return spdm_context->local_context.capability.max_spdm_msg_size + + spdm_context->local_context.capability.transport_header_size + + spdm_context->local_context.capability.transport_tail_size; +} + +/* second section */ +uint32_t libspdm_get_scratch_buffer_large_message_offset(libspdm_context_t *spdm_context) { + return libspdm_get_scratch_buffer_secure_message_capacity(spdm_context); +} + +uint32_t libspdm_get_scratch_buffer_large_message_capacity(libspdm_context_t *spdm_context) { + return spdm_context->local_context.capability.max_spdm_msg_size; +} +#endif + +/* third section */ +uint32_t libspdm_get_scratch_buffer_sender_receiver_offset(libspdm_context_t *spdm_context) { + return 0 + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + libspdm_get_scratch_buffer_secure_message_capacity(spdm_context) + + libspdm_get_scratch_buffer_large_message_capacity(spdm_context) + +#endif + 0; +} + +uint32_t libspdm_get_scratch_buffer_sender_receiver_capacity(libspdm_context_t *spdm_context) { + return spdm_context->local_context.capability.max_spdm_msg_size + + spdm_context->local_context.capability.transport_header_size + + spdm_context->local_context.capability.transport_tail_size; +} + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP +/* fourth section */ +uint32_t libspdm_get_scratch_buffer_large_sender_receiver_offset(libspdm_context_t *spdm_context) { + return libspdm_get_scratch_buffer_secure_message_capacity(spdm_context) + + libspdm_get_scratch_buffer_large_message_capacity(spdm_context) + + libspdm_get_scratch_buffer_sender_receiver_capacity(spdm_context); +} + +uint32_t libspdm_get_scratch_buffer_large_sender_receiver_capacity(libspdm_context_t *spdm_context) +{ + return spdm_context->local_context.capability.max_spdm_msg_size + + spdm_context->local_context.capability.transport_header_size + + spdm_context->local_context.capability.transport_tail_size; +} +#endif + +/* fifth section */ +uint32_t libspdm_get_scratch_buffer_last_spdm_request_offset(libspdm_context_t *spdm_context) { + return 0 + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + libspdm_get_scratch_buffer_secure_message_capacity(spdm_context) + + libspdm_get_scratch_buffer_large_message_capacity(spdm_context) + +#endif + libspdm_get_scratch_buffer_sender_receiver_capacity(spdm_context) + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + libspdm_get_scratch_buffer_large_sender_receiver_capacity(spdm_context) + +#endif + 0; +} + +uint32_t libspdm_get_scratch_buffer_last_spdm_request_capacity(libspdm_context_t *spdm_context) { + return spdm_context->local_context.capability.max_spdm_msg_size; +} + +#if LIBSPDM_RESPOND_IF_READY_SUPPORT +/* sixth section */ +uint32_t libspdm_get_scratch_buffer_cache_spdm_request_offset(libspdm_context_t *spdm_context) { + return 0 + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + libspdm_get_scratch_buffer_secure_message_capacity(spdm_context) + + libspdm_get_scratch_buffer_large_message_capacity(spdm_context) + +#endif + libspdm_get_scratch_buffer_sender_receiver_capacity(spdm_context) + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + libspdm_get_scratch_buffer_large_sender_receiver_capacity(spdm_context) + +#endif + libspdm_get_scratch_buffer_last_spdm_request_capacity(spdm_context) + + 0; +} + +uint32_t libspdm_get_scratch_buffer_cache_spdm_request_capacity(libspdm_context_t *spdm_context) { + return spdm_context->local_context.capability.max_spdm_msg_size; +} +#endif + +/* combination */ +uint32_t libspdm_get_scratch_buffer_capacity(libspdm_context_t *spdm_context) { + return 0 + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + libspdm_get_scratch_buffer_secure_message_capacity(spdm_context) + + libspdm_get_scratch_buffer_large_message_capacity(spdm_context) + +#endif + libspdm_get_scratch_buffer_sender_receiver_capacity(spdm_context) + +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + libspdm_get_scratch_buffer_large_sender_receiver_capacity(spdm_context) + +#endif + libspdm_get_scratch_buffer_last_spdm_request_capacity(spdm_context) + +#if LIBSPDM_RESPOND_IF_READY_SUPPORT + libspdm_get_scratch_buffer_cache_spdm_request_capacity(spdm_context) + +#endif + 0; +} /** * Returns if an SPDM data_type requires session info. @@ -22,6 +134,9 @@ static bool need_session_info_for_data(libspdm_data_type_t data_type) case LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED: case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: case LIBSPDM_DATA_SESSION_POLICY: + case LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_RSP_DIR: + case LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_REQ_DIR: + case LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_ENDIAN: return true; default: return false; @@ -43,32 +158,36 @@ static bool need_session_info_for_data(libspdm_data_type_t data_type) * @retval RETURN_ACCESS_DENIED The data_type cannot be set. * @retval RETURN_NOT_READY data is not ready to set. **/ -libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, +libspdm_return_t libspdm_set_data(void *spdm_context, libspdm_data_type_t data_type, const libspdm_data_parameter_t *parameter, void *data, size_t data_size) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; uint32_t session_id; + uint32_t data32; libspdm_session_info_t *session_info; uint8_t slot_id; uint8_t mut_auth_requested; uint8_t root_cert_index; -#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + uint16_t data16; +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) && LIBSPDM_CERT_PARSE_SUPPORT bool status; + const uint8_t *cert_buffer; + size_t cert_buffer_size; #endif - if (context == NULL || data == NULL || data_type >= LIBSPDM_DATA_MAX) { + if (spdm_context == NULL || data == NULL || data_type >= LIBSPDM_DATA_MAX) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context = context; + context = spdm_context; if (need_session_info_for_data(data_type)) { if (parameter->location != LIBSPDM_DATA_LOCATION_SESSION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - session_id = *(const uint32_t *)parameter->additional_data; - session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + session_id = libspdm_read_uint32(parameter->additional_data); + session_info = libspdm_get_session_info_via_session_id(context, session_id); if (session_info == NULL) { return LIBSPDM_STATUS_INVALID_PARAMETER; } @@ -82,39 +201,44 @@ libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { /* Only have one connected version */ LIBSPDM_ASSERT (data_size == sizeof(spdm_version_number_t)); - libspdm_copy_mem(&(spdm_context->connection_info.version), - sizeof(spdm_context->connection_info.version), + libspdm_copy_mem(&(context->connection_info.version), + sizeof(context->connection_info.version), data, sizeof(spdm_version_number_t)); - } else { - spdm_context->local_context.version.spdm_version_count = + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.version.spdm_version_count = (uint8_t)(data_size / sizeof(spdm_version_number_t)); - libspdm_copy_mem(spdm_context->local_context.version.spdm_version, - sizeof(spdm_context->local_context.version.spdm_version), + libspdm_copy_mem(context->local_context.version.spdm_version, + sizeof(context->local_context.version.spdm_version), data, - spdm_context->local_context.version.spdm_version_count * + context->local_context.version.spdm_version_count * sizeof(spdm_version_number_t)); + } else { + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_SECURED_MESSAGE_VERSION: - LIBSPDM_ASSERT (data_size <= sizeof(spdm_version_number_t) * SPDM_MAX_VERSION_COUNT); + LIBSPDM_ASSERT (data_size <= + sizeof(spdm_version_number_t) * SECURED_SPDM_MAX_VERSION_COUNT); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { /* Only have one connected version */ LIBSPDM_ASSERT (data_size == sizeof(spdm_version_number_t)); - libspdm_copy_mem(&(spdm_context->connection_info.secured_message_version), - sizeof(spdm_context->connection_info.secured_message_version), + libspdm_copy_mem(&(context->connection_info.secured_message_version), + sizeof(context->connection_info.secured_message_version), data, sizeof(spdm_version_number_t)); - } else { - spdm_context->local_context.secured_message_version + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.secured_message_version .spdm_version_count = (uint8_t)(data_size / sizeof(spdm_version_number_t)); - libspdm_copy_mem(spdm_context->local_context + libspdm_copy_mem(context->local_context .secured_message_version.spdm_version, - sizeof(spdm_context->local_context + sizeof(context->local_context .secured_message_version.spdm_version), data, - spdm_context->local_context.secured_message_version. + context->local_context.secured_message_version. spdm_version_count * sizeof(spdm_version_number_t)); + } else { + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_CAPABILITY_FLAGS: @@ -122,139 +246,171 @@ libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, return LIBSPDM_STATUS_INVALID_PARAMETER; } - #if !(LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) - LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP) == 0); - #endif /* !LIBSPDM_ENABLE_CAPABILITY_CERT_CAP */ + data32 = libspdm_read_uint32((const uint8_t *)data); - #if !(LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) - LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP) == 0); - #endif /* !LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP */ + if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + #if !(LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) + LIBSPDM_ASSERT((data32 & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_CERT_CAP */ - #if !(LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP) - LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP) == 0); - #endif /* !LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ + #if !(LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP) + LIBSPDM_ASSERT((data32 & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP */ - #if !(LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) - LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP) == - 0); - #endif /* !LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ + #if !(LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP) + LIBSPDM_ASSERT((data32 & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ - #if !(LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) - LIBSPDM_ASSERT(((*(uint32_t *)data) & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP) == 0); - #endif /* !LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + #if !(LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) + LIBSPDM_ASSERT((data32 & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_EX_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ - if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.capability.flags = *(uint32_t *)data; + #if !(LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) + LIBSPDM_ASSERT((data32 & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP) == 0); + #endif /* !LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ + + context->local_context.capability.flags = data32; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + context->connection_info.capability.flags = data32; } else { - spdm_context->local_context.capability.flags = *(uint32_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_CAPABILITY_CT_EXPONENT: if (data_size != sizeof(uint8_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.capability.ct_exponent = *(uint8_t *)data; + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + context->connection_info.capability.ct_exponent = *(uint8_t *)data; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.capability.ct_exponent = *(uint8_t *)data; + } else { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } break; case LIBSPDM_DATA_CAPABILITY_RTT_US: if (data_size != sizeof(uint64_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.capability.rtt = *(uint64_t *)data; - break; - case LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE: - if (data_size != sizeof(uint32_t)) { + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - /* Only allow set smaller value*/ - LIBSPDM_ASSERT (*(uint32_t *)data <= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); - spdm_context->local_context.capability.data_transfer_size = *(uint32_t *)data; + context->local_context.capability.rtt = libspdm_read_uint64((const uint8_t *)data); break; case LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE: if (data_size != sizeof(uint32_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - /* Only allow set smaller value. Need different value for CHUNK - TBD*/ - LIBSPDM_ASSERT (*(uint32_t *)data <= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); - spdm_context->local_context.capability.max_spdm_msg_size = *(uint32_t *)data; + /* The local max_spdm_msg_size is set by libspdm_register_transport_layer_func. + * Only the connection's max_spdm_msg_size is settable here. */ + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + data32 = libspdm_read_uint32((const uint8_t *)data); + LIBSPDM_ASSERT (data32 >= SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12); + context->connection_info.capability.max_spdm_msg_size = data32; break; case LIBSPDM_DATA_MEASUREMENT_SPEC: if (data_size != sizeof(uint8_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.measurement_spec = *(uint8_t *)data; + context->connection_info.algorithm.measurement_spec = *(uint8_t *)data; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.measurement_spec = *(uint8_t *)data; } else { - spdm_context->local_context.algorithm.measurement_spec = *(uint8_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_MEASUREMENT_HASH_ALGO: if (data_size != sizeof(uint32_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + data32 = libspdm_read_uint32((const uint8_t *)data); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.measurement_hash_algo = *(uint32_t *)data; + context->connection_info.algorithm.measurement_hash_algo = data32; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.measurement_hash_algo = data32; } else { - spdm_context->local_context.algorithm.measurement_hash_algo = *(uint32_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_BASE_ASYM_ALGO: if (data_size != sizeof(uint32_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + data32 = libspdm_read_uint32((const uint8_t *)data); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.base_asym_algo = *(uint32_t *)data; + context->connection_info.algorithm.base_asym_algo = data32; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.base_asym_algo = data32; } else { - spdm_context->local_context.algorithm.base_asym_algo = *(uint32_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_BASE_HASH_ALGO: if (data_size != sizeof(uint32_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + data32 = libspdm_read_uint32((const uint8_t *)data); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.base_hash_algo = *(uint32_t *)data; + context->connection_info.algorithm.base_hash_algo = data32; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.base_hash_algo = data32; } else { - spdm_context->local_context.algorithm.base_hash_algo = *(uint32_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_DHE_NAME_GROUP: if (data_size != sizeof(uint16_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + data16 = libspdm_read_uint16((const uint8_t *)data); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.dhe_named_group = *(uint16_t *)data; + context->connection_info.algorithm.dhe_named_group = data16; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.dhe_named_group = data16; } else { - spdm_context->local_context.algorithm.dhe_named_group = *(uint16_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_AEAD_CIPHER_SUITE: if (data_size != sizeof(uint16_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + data16 = libspdm_read_uint16((const uint8_t *)data); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.aead_cipher_suite = *(uint16_t *)data; + context->connection_info.algorithm.aead_cipher_suite = data16; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.aead_cipher_suite = data16; } else { - spdm_context->local_context.algorithm.aead_cipher_suite = *(uint16_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_REQ_BASE_ASYM_ALG: if (data_size != sizeof(uint16_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + data16 = libspdm_read_uint16((const uint8_t *)data); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.req_base_asym_alg = *(uint16_t *)data; + context->connection_info.algorithm.req_base_asym_alg = data16; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.req_base_asym_alg = data16; } else { - spdm_context->local_context.algorithm.req_base_asym_alg = *(uint16_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_KEY_SCHEDULE: if (data_size != sizeof(uint16_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + data16 = libspdm_read_uint16((const uint8_t *)data); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.key_schedule = *(uint16_t *)data; + context->connection_info.algorithm.key_schedule = data16; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.key_schedule = data16; } else { - spdm_context->local_context.algorithm.key_schedule = *(uint16_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_OTHER_PARAMS_SUPPORT: @@ -262,63 +418,57 @@ libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, return LIBSPDM_STATUS_INVALID_PARAMETER; } if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - spdm_context->connection_info.algorithm.other_params_support = *(uint8_t *)data; + context->connection_info.algorithm.other_params_support = *(uint8_t *)data; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + context->local_context.algorithm.other_params_support = *(uint8_t *)data; } else { - spdm_context->local_context.algorithm.other_params_support = *(uint8_t *)data; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_CONNECTION_STATE: - if (data_size != sizeof(uint32_t)) { + if (data_size != sizeof(libspdm_connection_state_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->connection_info.connection_state = *(uint32_t *)data; + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->connection_info.connection_state = libspdm_read_uint32((const uint8_t *)data); break; case LIBSPDM_DATA_RESPONSE_STATE: - if (data_size != sizeof(uint32_t)) { + if (data_size != sizeof(libspdm_response_state_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->response_state = *(uint32_t *)data; + context->response_state = libspdm_read_uint32((const uint8_t *)data); break; case LIBSPDM_DATA_PEER_PUBLIC_ROOT_CERT: + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } root_cert_index = 0; - while (spdm_context->local_context.peer_root_cert_provision[root_cert_index] != NULL) { + while (context->local_context.peer_root_cert_provision[root_cert_index] != NULL) { root_cert_index++; if (root_cert_index >= LIBSPDM_MAX_ROOT_CERT_SUPPORT) { return LIBSPDM_STATUS_BUFFER_FULL; } } - spdm_context->local_context.peer_root_cert_provision_size[root_cert_index] = data_size; - spdm_context->local_context.peer_root_cert_provision[root_cert_index] = data; - break; - case LIBSPDM_DATA_PEER_PUBLIC_CERT_CHAIN: - spdm_context->local_context.peer_cert_chain_provision_size = data_size; - spdm_context->local_context.peer_cert_chain_provision = data; + context->local_context.peer_root_cert_provision_size[root_cert_index] = data_size; + context->local_context.peer_root_cert_provision[root_cert_index] = data; break; case LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN: + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } slot_id = parameter->additional_data[0]; if (slot_id >= SPDM_MAX_SLOT_COUNT) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.local_cert_chain_provision_size[slot_id] = data_size; - spdm_context->local_context.local_cert_chain_provision[slot_id] = data; + context->local_context.local_cert_chain_provision_size[slot_id] = data_size; + context->local_context.local_cert_chain_provision[slot_id] = data; break; - case LIBSPDM_DATA_LOCAL_PUBLIC_CERT_CHAIN_DEFAULT_SLOT_ID: - if (data_size != sizeof(uint8_t)) { - return LIBSPDM_STATUS_INVALID_PARAMETER; - } - if (*(uint8_t *)data >= SPDM_MAX_SLOT_COUNT) { + case LIBSPDM_DATA_PEER_USED_CERT_CHAIN_BUFFER: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.provisioned_slot_id = *(uint8_t *)data; - break; - case LIBSPDM_DATA_LOCAL_USED_CERT_CHAIN_BUFFER: - if (data_size > LIBSPDM_MAX_CERT_CHAIN_SIZE) { - return LIBSPDM_STATUS_BUFFER_FULL; - } - spdm_context->connection_info.local_used_cert_chain_buffer_size = data_size; - spdm_context->connection_info.local_used_cert_chain_buffer = data; - break; - case LIBSPDM_DATA_PEER_USED_CERT_CHAIN_BUFFER: slot_id = parameter->additional_data[0]; if (slot_id >= SPDM_MAX_SLOT_COUNT) { return LIBSPDM_STATUS_INVALID_PARAMETER; @@ -326,74 +476,123 @@ libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, if (data_size > LIBSPDM_MAX_CERT_CHAIN_SIZE) { return LIBSPDM_STATUS_BUFFER_FULL; } - spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; + context->connection_info.peer_used_cert_chain_slot_id = slot_id; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size = data_size; - libspdm_copy_mem(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer, - sizeof(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer), + context->connection_info.peer_used_cert_chain[slot_id].buffer_size = data_size; + libspdm_copy_mem(context->connection_info.peer_used_cert_chain[slot_id].buffer, + sizeof(context->connection_info.peer_used_cert_chain[slot_id].buffer), data, data_size); #else +#if LIBSPDM_CERT_PARSE_SUPPORT status = libspdm_hash_all( - spdm_context->connection_info.algorithm.base_hash_algo, + context->connection_info.algorithm.base_hash_algo, data, data_size, - spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash); + context->connection_info.peer_used_cert_chain[slot_id].buffer_hash); if (!status) { return LIBSPDM_STATUS_CRYPTO_ERROR; } - spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size = - libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size = + libspdm_get_hash_size(context->connection_info.algorithm.base_hash_algo); + + /*process the SPDM cert header and hash*/ + data = (uint8_t *)data + sizeof(spdm_cert_chain_t) + + libspdm_get_hash_size(context->connection_info.algorithm.base_hash_algo); + data_size = data_size - + (sizeof(spdm_cert_chain_t) + + libspdm_get_hash_size(context->connection_info.algorithm.base_hash_algo)); + + /* Get leaf cert from cert chain */ + status = libspdm_x509_get_cert_from_cert_chain(data, data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!status) { + return LIBSPDM_STATUS_CRYPTO_ERROR; + } status = false; #if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) if (!status) { status = libspdm_rsa_get_public_key_from_x509( - data, data_size, - &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + cert_buffer, cert_buffer_size, + &context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); } #endif #if LIBSPDM_ECDSA_SUPPORT if (!status) { status = libspdm_ec_get_public_key_from_x509( - data, data_size, - &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + cert_buffer, cert_buffer_size, + &context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); } #endif #if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) if (!status) { status = libspdm_ecd_get_public_key_from_x509( - data, data_size, - &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + cert_buffer, cert_buffer_size, + &context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); } #endif #if LIBSPDM_SM2_DSA_SUPPORT if (!status) { status = libspdm_sm2_get_public_key_from_x509( - data, data_size, - &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); + cert_buffer, cert_buffer_size, + &context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); } #endif if (!status) { return LIBSPDM_STATUS_INVALID_CERT; } -#endif +#else + LIBSPDM_ASSERT (false); +#endif /* LIBSPDM_CERT_PARSE_SUPPORT */ +#endif /* LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT */ + break; + case LIBSPDM_DATA_PEER_PUBLIC_KEY: + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->local_context.peer_public_key_provision_size = data_size; + context->local_context.peer_public_key_provision = data; + break; + case LIBSPDM_DATA_LOCAL_PUBLIC_KEY: + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->local_context.local_public_key_provision_size = data_size; + context->local_context.local_public_key_provision = data; break; case LIBSPDM_DATA_BASIC_MUT_AUTH_REQUESTED: if (data_size != sizeof(bool)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } mut_auth_requested = *(uint8_t *)data; if (((mut_auth_requested != 0) && (mut_auth_requested != 1))) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.basic_mut_auth_requested = mut_auth_requested; - spdm_context->encap_context.request_id = 0; - spdm_context->encap_context.req_slot_id = parameter->additional_data[0]; + context->local_context.basic_mut_auth_requested = mut_auth_requested; + context->encap_context.request_id = 0; + slot_id = parameter->additional_data[0]; + if ((slot_id >= SPDM_MAX_SLOT_COUNT) && (slot_id != 0xFF)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->encap_context.req_slot_id = slot_id; + + #if LIBSPDM_DEBUG_PRINT_ENABLE + if (mut_auth_requested) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "Basic mutual authentication is a deprecated feature.\n")); + } + #endif /* LIBSPDM_DEBUG_PRINT_ENABLE */ break; case LIBSPDM_DATA_MUT_AUTH_REQUESTED: if (data_size != sizeof(uint8_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } mut_auth_requested = *(uint8_t *)data; if (((mut_auth_requested != 0) && (mut_auth_requested != @@ -404,74 +603,108 @@ libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS))) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.mut_auth_requested = mut_auth_requested; - spdm_context->encap_context.request_id = 0; - spdm_context->encap_context.req_slot_id = parameter->additional_data[0]; + context->local_context.mut_auth_requested = mut_auth_requested; + context->encap_context.request_id = 0; + slot_id = parameter->additional_data[0]; + if ((slot_id >= SPDM_MAX_SLOT_COUNT) && (slot_id != 0xFF)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->encap_context.req_slot_id = slot_id; break; case LIBSPDM_DATA_HEARTBEAT_PERIOD: if (data_size != sizeof(uint8_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.heartbeat_period = *(uint8_t *)data; - break; - case LIBSPDM_DATA_PSK_HINT: - if (data_size > LIBSPDM_PSK_MAX_HINT_LENGTH) { + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.psk_hint_size = data_size; - spdm_context->local_context.psk_hint = data; + context->local_context.heartbeat_period = *(uint8_t *)data; break; - case LIBSPDM_DATA_SESSION_USE_PSK: - if (data_size != sizeof(bool)) { + case LIBSPDM_DATA_APP_CONTEXT_DATA: + if (data_size != sizeof(void *) || *(void **)data == NULL) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - session_info->use_psk = *(bool *)data; + context->app_context_data_ptr = *(void **)data; break; - case LIBSPDM_DATA_SESSION_MUT_AUTH_REQUESTED: + case LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY: if (data_size != sizeof(uint8_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - session_info->mut_auth_requested = *(uint8_t *)data; + context->handle_error_return_policy = *(uint8_t *)data; break; - case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: - if (data_size != sizeof(uint8_t)) { + case LIBSPDM_DATA_VCA_CACHE: + if (data_size > sizeof(context->transcript.message_a.buffer)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - session_info->end_session_attributes = *(uint8_t *)data; + context->transcript.message_a.buffer_size = data_size; + libspdm_copy_mem(context->transcript.message_a.buffer, + sizeof(context->transcript.message_a.buffer), + data, data_size); break; - case LIBSPDM_DATA_SESSION_POLICY: + case LIBSPDM_DATA_IS_REQUESTER: + if (data_size != sizeof(bool)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (parameter->location != LIBSPDM_DATA_LOCATION_LOCAL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->local_context.is_requester = *(bool *)data; + break; + case LIBSPDM_DATA_REQUEST_RETRY_TIMES: if (data_size != sizeof(uint8_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - session_info->session_policy = *(uint8_t *)data; + context->retry_times = *(uint8_t *)data; break; - case LIBSPDM_DATA_APP_CONTEXT_DATA: - if (data_size != sizeof(void *) || *(void **)data == NULL) { + case LIBSPDM_DATA_REQUEST_RETRY_DELAY_TIME: + if (data_size != sizeof(uint64_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->app_context_data_ptr = *(void **)data; + context->retry_delay_time = *(uint64_t *)data; break; - case LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY: - if (data_size != sizeof(uint8_t)) { + case LIBSPDM_DATA_MAX_DHE_SESSION_COUNT: + if (data_size != sizeof(uint32_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->handle_error_return_policy = *(uint8_t *)data; + if (*(uint32_t *)data > LIBSPDM_MAX_SESSION_COUNT - context->max_psk_session_count) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->max_dhe_session_count = *(uint32_t *)data; break; - case LIBSPDM_DATA_VCA_CACHE: - if (data_size > sizeof(spdm_context->transcript.message_a.buffer)) { + case LIBSPDM_DATA_MAX_PSK_SESSION_COUNT: + if (data_size != sizeof(uint32_t)) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->transcript.message_a.buffer_size = data_size; - libspdm_copy_mem(spdm_context->transcript.message_a.buffer, - sizeof(spdm_context->transcript.message_a.buffer), - data, data_size); + if (*(uint32_t *)data > LIBSPDM_MAX_SESSION_COUNT - context->max_dhe_session_count) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->max_psk_session_count = *(uint32_t *)data; break; - case LIBSPDM_DATA_IS_REQUESTER: - if (data_size != sizeof(bool)) { + case LIBSPDM_DATA_MAX_SPDM_SESSION_SEQUENCE_NUMBER: + if (data_size != sizeof(uint64_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->max_spdm_session_sequence_number = *(uint64_t *)data; + if (context->max_spdm_session_sequence_number == 0) { + context->max_spdm_session_sequence_number = LIBSPDM_MAX_SPDM_SESSION_SEQUENCE_NUMBER; + } + break; + case LIBSPDM_DATA_SPDM_VERSION_10_11_VERIFY_SIGNATURE_ENDIAN: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + if (*(uint8_t*)data != LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY && + *(uint8_t*)data != LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY && + *(uint8_t*)data != LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->local_context.is_requester = *(bool *)data; + context->spdm_10_11_verify_signature_endian = *(uint8_t*)data; break; + case LIBSPDM_DATA_SEQUENCE_NUMBER_ENDIAN: + if (data_size != sizeof(uint8_t)) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + context->sequence_number_endian = *(uint8_t *)data; default: return LIBSPDM_STATUS_UNSUPPORTED_CAP; break; @@ -499,11 +732,12 @@ libspdm_return_t libspdm_set_data(void *context, libspdm_data_type_t data_type, * @retval RETURN_NOT_READY The data is not ready to return. * @retval RETURN_BUFFER_TOO_SMALL The buffer is too small to hold the data. **/ -libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, +libspdm_return_t libspdm_get_data(void *spdm_context, libspdm_data_type_t data_type, const libspdm_data_parameter_t *parameter, void *data, size_t *data_size) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; + libspdm_secured_message_context_t *secured_context; size_t target_data_size; void *target_data; uint32_t session_id; @@ -512,21 +746,34 @@ libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, size_t digest_count; size_t index; - if (context == NULL || data == NULL || data_size == NULL || data_type >= LIBSPDM_DATA_MAX) { + if (spdm_context == NULL || data == NULL || data_size == NULL || + data_type >= LIBSPDM_DATA_MAX) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context = context; + context = spdm_context; - if (need_session_info_for_data(data_type)) { + // + // NVIDIA_EDIT: While in practice, secured_context will never be NULL with below logic, + // compiler does not see this and complains of potential uninitialized use. + // + secured_context = NULL; + + if (data_type == LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES) { + /* end_session_attributes is present in both a session context as well as an + * spdm context. */ + session_id = libspdm_read_uint32(parameter->additional_data); + session_info = libspdm_get_session_info_via_session_id(context, session_id); + } else if (need_session_info_for_data(data_type)) { if (parameter->location != LIBSPDM_DATA_LOCATION_SESSION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - session_id = *(const uint32_t *)parameter->additional_data; - session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + session_id = libspdm_read_uint32(parameter->additional_data); + session_info = libspdm_get_session_info_via_session_id(context, session_id); if (session_info == NULL) { return LIBSPDM_STATUS_INVALID_PARAMETER; } + secured_context = session_info->secured_message_context; } else { session_info = NULL; } @@ -537,45 +784,63 @@ libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(spdm_version_number_t); - target_data = &(spdm_context->connection_info.version); + target_data = &(context->connection_info.version); break; case LIBSPDM_DATA_SECURED_MESSAGE_VERSION: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(spdm_version_number_t); - target_data = &(spdm_context->connection_info.secured_message_version); + target_data = &(context->connection_info.secured_message_version); break; case LIBSPDM_DATA_CAPABILITY_FLAGS: target_data_size = sizeof(uint32_t); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - target_data = &spdm_context->connection_info.capability.flags; + target_data = &context->connection_info.capability.flags; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + target_data = &context->local_context.capability.flags; } else { - target_data = &spdm_context->local_context.capability.flags; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_CAPABILITY_CT_EXPONENT: target_data_size = sizeof(uint8_t); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - target_data = &spdm_context->connection_info.capability.ct_exponent; + target_data = &context->connection_info.capability.ct_exponent; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + target_data = &context->local_context.capability.ct_exponent; } else { - target_data = &spdm_context->local_context.capability.ct_exponent; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_CAPABILITY_DATA_TRANSFER_SIZE: target_data_size = sizeof(uint32_t); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - target_data = &spdm_context->connection_info.capability.data_transfer_size; + target_data = &context->connection_info.capability.data_transfer_size; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + target_data = &context->local_context.capability.data_transfer_size; } else { - target_data = &spdm_context->local_context.capability.data_transfer_size; + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_CAPABILITY_MAX_SPDM_MSG_SIZE: target_data_size = sizeof(uint32_t); if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { - target_data = &spdm_context->connection_info.capability.max_spdm_msg_size; + target_data = &context->connection_info.capability.max_spdm_msg_size; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + target_data = &context->local_context.capability.max_spdm_msg_size; } else { - target_data = &spdm_context->local_context.capability.max_spdm_msg_size; + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + break; + case LIBSPDM_DATA_CAPABILITY_SENDER_DATA_TRANSFER_SIZE: + target_data_size = sizeof(uint32_t); + if (parameter->location == LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } else if (parameter->location == LIBSPDM_DATA_LOCATION_LOCAL) { + target_data = &context->local_context.capability.sender_data_transfer_size; + } else { + return LIBSPDM_STATUS_INVALID_PARAMETER; } break; case LIBSPDM_DATA_MEASUREMENT_SPEC: @@ -583,89 +848,95 @@ libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint8_t); - target_data = &spdm_context->connection_info.algorithm.measurement_spec; + target_data = &context->connection_info.algorithm.measurement_spec; break; case LIBSPDM_DATA_MEASUREMENT_HASH_ALGO: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint32_t); - target_data = &spdm_context->connection_info.algorithm.measurement_hash_algo; + target_data = &context->connection_info.algorithm.measurement_hash_algo; break; case LIBSPDM_DATA_BASE_ASYM_ALGO: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint32_t); - target_data = &spdm_context->connection_info.algorithm.base_asym_algo; + target_data = &context->connection_info.algorithm.base_asym_algo; break; case LIBSPDM_DATA_BASE_HASH_ALGO: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint32_t); - target_data = &spdm_context->connection_info.algorithm.base_hash_algo; + target_data = &context->connection_info.algorithm.base_hash_algo; break; case LIBSPDM_DATA_DHE_NAME_GROUP: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint16_t); - target_data = &spdm_context->connection_info.algorithm.dhe_named_group; + target_data = &context->connection_info.algorithm.dhe_named_group; break; case LIBSPDM_DATA_AEAD_CIPHER_SUITE: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint16_t); - target_data = &spdm_context->connection_info.algorithm.aead_cipher_suite; + target_data = &context->connection_info.algorithm.aead_cipher_suite; break; case LIBSPDM_DATA_REQ_BASE_ASYM_ALG: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint16_t); - target_data = &spdm_context->connection_info.algorithm.req_base_asym_alg; + target_data = &context->connection_info.algorithm.req_base_asym_alg; break; case LIBSPDM_DATA_KEY_SCHEDULE: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint16_t); - target_data = &spdm_context->connection_info.algorithm.key_schedule; + target_data = &context->connection_info.algorithm.key_schedule; break; case LIBSPDM_DATA_OTHER_PARAMS_SUPPORT: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } target_data_size = sizeof(uint8_t); - target_data = &spdm_context->connection_info.algorithm.other_params_support; + target_data = &context->connection_info.algorithm.other_params_support; break; case LIBSPDM_DATA_CONNECTION_STATE: if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - target_data_size = sizeof(uint32_t); - target_data = &spdm_context->connection_info.connection_state; + target_data_size = sizeof(libspdm_connection_state_t); + target_data = &context->connection_info.connection_state; break; case LIBSPDM_DATA_RESPONSE_STATE: - target_data_size = sizeof(uint32_t); - target_data = &spdm_context->response_state; + target_data_size = sizeof(libspdm_response_state_t); + target_data = &context->response_state; break; case LIBSPDM_DATA_PEER_SLOT_MASK: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } target_data_size = sizeof(uint8_t); - target_data = &spdm_context->connection_info.peer_digest_slot_mask; + target_data = &context->connection_info.peer_digest_slot_mask; break; case LIBSPDM_DATA_PEER_TOTAL_DIGEST_BUFFER: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } digest_count = 0; for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { - if (spdm_context->connection_info.peer_digest_slot_mask & (1 << index)) { + if (context->connection_info.peer_digest_slot_mask & (1 << index)) { digest_count++; } } - digest_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + digest_size = libspdm_get_hash_size(context->connection_info.algorithm.base_hash_algo); target_data_size = digest_size * digest_count; - target_data = spdm_context->connection_info.peer_total_digest_buffer; + target_data = context->connection_info.peer_total_digest_buffer; break; case LIBSPDM_DATA_SESSION_USE_PSK: target_data_size = sizeof(bool); @@ -676,8 +947,15 @@ libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, target_data = &session_info->mut_auth_requested; break; case LIBSPDM_DATA_SESSION_END_SESSION_ATTRIBUTES: + if (parameter->location != LIBSPDM_DATA_LOCATION_CONNECTION) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } target_data_size = sizeof(uint8_t); - target_data = &session_info->end_session_attributes; + if (session_info == NULL) { + target_data = &context->connection_info.end_session_attributes; + } else { + target_data = &session_info->end_session_attributes; + } break; case LIBSPDM_DATA_SESSION_POLICY: target_data_size = sizeof(uint8_t); @@ -685,16 +963,61 @@ libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, break; case LIBSPDM_DATA_APP_CONTEXT_DATA: target_data_size = sizeof(void *); - target_data = &spdm_context->app_context_data_ptr; + target_data = &context->app_context_data_ptr; break; case LIBSPDM_DATA_HANDLE_ERROR_RETURN_POLICY: target_data_size = sizeof(uint8_t); - target_data = &spdm_context->handle_error_return_policy; + target_data = &context->handle_error_return_policy; + break; + case LIBSPDM_DATA_MAX_DHE_SESSION_COUNT: + target_data_size = sizeof(uint32_t); + target_data = &context->max_dhe_session_count; + break; + case LIBSPDM_DATA_MAX_PSK_SESSION_COUNT: + target_data_size = sizeof(uint32_t); + target_data = &context->max_psk_session_count; + break; + case LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_REQ_DIR: + // NVIDIA_EDIT: Appease compiler that we will not use secured_context uninitialized. + if (secured_context == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint64_t); + target_data = &secured_context->application_secret.request_data_sequence_number; + break; + case LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_RSP_DIR: + // NVIDIA_EDIT: Appease compiler that we will not use secured_context uninitialized. + if (secured_context == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint64_t); + target_data = &secured_context->application_secret.response_data_sequence_number; + break; + case LIBSPDM_DATA_MAX_SPDM_SESSION_SEQUENCE_NUMBER: + target_data_size = sizeof(uint64_t); + target_data = &context->max_spdm_session_sequence_number; break; case LIBSPDM_DATA_VCA_CACHE: - target_data_size = spdm_context->transcript.message_a.buffer_size; - target_data = spdm_context->transcript.message_a.buffer; + target_data_size = context->transcript.message_a.buffer_size; + target_data = context->transcript.message_a.buffer; + break; + case LIBSPDM_DATA_SPDM_VERSION_10_11_VERIFY_SIGNATURE_ENDIAN: + target_data_size = sizeof(uint8_t); + target_data = &context->spdm_10_11_verify_signature_endian; break; + case LIBSPDM_DATA_SEQUENCE_NUMBER_ENDIAN: + target_data_size = sizeof(uint8_t); + target_data = &context->sequence_number_endian; + case LIBSPDM_DATA_SESSION_SEQUENCE_NUMBER_ENDIAN: + // NVIDIA_EDIT: Appease compiler that we will not use secured_context uninitialized. + if (secured_context == NULL) + { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + target_data_size = sizeof(uint8_t); + target_data = &secured_context->sequence_number_endian; default: return LIBSPDM_STATUS_UNSUPPORTED_CAP; break; @@ -710,16 +1033,80 @@ libspdm_return_t libspdm_get_data(void *context, libspdm_data_type_t data_type, return LIBSPDM_STATUS_SUCCESS; } +#if LIBSPDM_CHECK_SPDM_CONTEXT +bool libspdm_check_context (void *spdm_context) +{ + libspdm_context_t *context; + size_t index; + + context = spdm_context; + + if (context->local_context.capability.data_transfer_size < + SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "data_transfer_size must be greater than or equal " + "to SPDM_MIN_DATA_TRANSFER_SIZE (%d).\n", + SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12)); + return false; + } + + if (context->local_context.capability.max_spdm_msg_size < + context->local_context.capability.data_transfer_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "max_spdm_msg_size (%d) must be greater than or " + "equal to data_transfer_size (%d).\n", + context->local_context.capability.max_spdm_msg_size, + context->local_context.capability.data_transfer_size)); + return false; + } + + if (context->local_context.capability.sender_data_transfer_size < + SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "sender_data_transfer_size must be greater than or equal " + "to %d.\n", SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12)); + return false; + } + + if (context->local_context.capability.max_spdm_msg_size < + context->local_context.capability.sender_data_transfer_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "max_spdm_msg_size (%d) must be greater than or " + "equal to sender_data_transfer_size (%d).\n", + context->local_context.capability.max_spdm_msg_size, + context->local_context.capability.sender_data_transfer_size)); + return false; + } + + if (((context->local_context.capability.flags & + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP) != 0) && + (context->local_context.capability.max_spdm_msg_size != 0)) { + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if ((context->local_context.local_cert_chain_provision_size[index] != 0) && + (context->local_context.local_cert_chain_provision_size[index] + + sizeof(spdm_certificate_response_t) > + context->local_context.capability.max_spdm_msg_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "max_spdm_msg_size (%d) must be greater than or " + "equal to local_cert_chain_provision_size[%d] (%d).\n", + context->local_context.capability.max_spdm_msg_size, index, + context->local_context.local_cert_chain_provision_size[index])); + return false; + } + } + } + + return true; +} +#endif /* LIBSPDM_CHECK_CONTEXT */ + /** * Reset message A cache in SPDM context. * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_a(void *context) +void libspdm_reset_message_a(libspdm_context_t *spdm_context) { - libspdm_context_t *spdm_context; - - spdm_context = context; libspdm_reset_managed_buffer(&spdm_context->transcript.message_a); } @@ -728,11 +1115,8 @@ void libspdm_reset_message_a(void *context) * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_b(void *context) +void libspdm_reset_message_b(libspdm_context_t *spdm_context) { - libspdm_context_t *spdm_context; - - spdm_context = context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT libspdm_reset_managed_buffer(&spdm_context->transcript.message_b); #else @@ -749,11 +1133,8 @@ void libspdm_reset_message_b(void *context) * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_c(void *context) +void libspdm_reset_message_c(libspdm_context_t *spdm_context) { - libspdm_context_t *spdm_context; - - spdm_context = context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT libspdm_reset_managed_buffer(&spdm_context->transcript.message_c); #else @@ -770,11 +1151,8 @@ void libspdm_reset_message_c(void *context) * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_mut_b(void *context) +void libspdm_reset_message_mut_b(libspdm_context_t *spdm_context) { - libspdm_context_t *spdm_context; - - spdm_context = context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT libspdm_reset_managed_buffer(&spdm_context->transcript.message_mut_b); #else @@ -791,11 +1169,8 @@ void libspdm_reset_message_mut_b(void *context) * * @param spdm_context A pointer to the SPDM context. **/ -void libspdm_reset_message_mut_c(void *context) +void libspdm_reset_message_mut_c(libspdm_context_t *spdm_context) { - libspdm_context_t *spdm_context; - - spdm_context = context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT libspdm_reset_managed_buffer(&spdm_context->transcript.message_mut_c); #else @@ -815,12 +1190,10 @@ void libspdm_reset_message_mut_c(void *context) * @param spdm_context A pointer to the SPDM context. * @param session_info A pointer to the SPDM session context. **/ -void libspdm_reset_message_m(void *context, void *session_info) +void libspdm_reset_message_m(libspdm_context_t *spdm_context, void *session_info) { - libspdm_context_t *spdm_context; libspdm_session_info_t *spdm_session_info; - spdm_context = context; spdm_session_info = session_info; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT if (spdm_session_info == NULL) { @@ -851,7 +1224,7 @@ void libspdm_reset_message_m(void *context, void *session_info) * @param spdm_context A pointer to the SPDM context. * @param spdm_session_info A pointer to the SPDM session context. **/ -void libspdm_reset_message_k(void *context, void *session_info) +void libspdm_reset_message_k(libspdm_context_t *spdm_context, void *session_info) { libspdm_session_info_t *spdm_session_info; @@ -860,10 +1233,6 @@ void libspdm_reset_message_k(void *context, void *session_info) libspdm_reset_managed_buffer(&spdm_session_info->session_transcript.message_k); #else { - libspdm_context_t *spdm_context; - - spdm_context = context; - if (spdm_session_info->session_transcript.digest_context_th != NULL) { libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, spdm_session_info->session_transcript.digest_context_th); @@ -884,7 +1253,7 @@ void libspdm_reset_message_k(void *context, void *session_info) * @param spdm_context A pointer to the SPDM context. * @param spdm_session_info A pointer to the SPDM session context. **/ -void libspdm_reset_message_f(void *context, void *session_info) +void libspdm_reset_message_f(libspdm_context_t *spdm_context, void *session_info) { libspdm_session_info_t *spdm_session_info; @@ -893,10 +1262,6 @@ void libspdm_reset_message_f(void *context, void *session_info) libspdm_reset_managed_buffer(&spdm_session_info->session_transcript.message_f); #else { - libspdm_context_t *spdm_context; - - spdm_context = context; - if (spdm_session_info->session_transcript.digest_context_th != NULL) { libspdm_hash_free (spdm_context->connection_info.algorithm.base_hash_algo, spdm_session_info->session_transcript.digest_context_th); @@ -931,7 +1296,7 @@ void libspdm_reset_message_buffer_via_request_code(void *context, void *session_ /** * If the Requester issued GET_MEASUREMENTS or KEY_EXCHANGE or FINISH or PSK_EXCHANGE * or PSK_FINISH or KEY_UPDATE or HEARTBEAT or GET_ENCAPSULATED_REQUEST or DELIVER_ENCAPSULATED_RESPONSE - * or END_SESSSION request(s) and skipped CHALLENGE completion, M1 and M2 are reset to null. + * or END_SESSION request(s) and skipped CHALLENGE completion, M1 and M2 are reset to null. */ switch (request_code) { @@ -976,11 +1341,9 @@ void libspdm_reset_message_buffer_via_request_code(void *context, void *session_ * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_a(void *context, const void *message, size_t message_size) +libspdm_return_t libspdm_append_message_a(libspdm_context_t *spdm_context, const void *message, + size_t message_size) { - libspdm_context_t *spdm_context; - - spdm_context = context; return libspdm_append_managed_buffer(&spdm_context->transcript.message_a, message, message_size); } @@ -995,11 +1358,9 @@ libspdm_return_t libspdm_append_message_a(void *context, const void *message, si * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_b(void *context, const void *message, size_t message_size) +libspdm_return_t libspdm_append_message_b(libspdm_context_t *spdm_context, const void *message, + size_t message_size) { - libspdm_context_t *spdm_context; - - spdm_context = context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT return libspdm_append_managed_buffer(&spdm_context->transcript.message_b, message, message_size); @@ -1060,11 +1421,9 @@ libspdm_return_t libspdm_append_message_b(void *context, const void *message, si * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_c(void *context, const void *message, size_t message_size) +libspdm_return_t libspdm_append_message_c(libspdm_context_t *spdm_context, const void *message, + size_t message_size) { - libspdm_context_t *spdm_context; - - spdm_context = context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT return libspdm_append_managed_buffer(&spdm_context->transcript.message_c, message, message_size); @@ -1125,12 +1484,9 @@ libspdm_return_t libspdm_append_message_c(void *context, const void *message, si * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_mut_b(void *context, const void *message, +libspdm_return_t libspdm_append_message_mut_b(libspdm_context_t *spdm_context, const void *message, size_t message_size) { - libspdm_context_t *spdm_context; - - spdm_context = context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT return libspdm_append_managed_buffer(&spdm_context->transcript.message_mut_b, message, message_size); @@ -1196,12 +1552,9 @@ libspdm_return_t libspdm_append_message_mut_b(void *context, const void *message * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_mut_c(void *context, const void *message, +libspdm_return_t libspdm_append_message_mut_c(libspdm_context_t *spdm_context, const void *message, size_t message_size) { - libspdm_context_t *spdm_context; - - spdm_context = context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT return libspdm_append_managed_buffer(&spdm_context->transcript.message_mut_c, message, message_size); @@ -1270,13 +1623,11 @@ libspdm_return_t libspdm_append_message_mut_c(void *context, const void *message * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_m(void *context, void *session_info, +libspdm_return_t libspdm_append_message_m(libspdm_context_t *spdm_context, void *session_info, const void *message, size_t message_size) { - libspdm_context_t *spdm_context; libspdm_session_info_t *spdm_session_info; - spdm_context = context; spdm_session_info = session_info; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT if (spdm_session_info == NULL) { @@ -1396,7 +1747,8 @@ libspdm_return_t libspdm_append_message_m(void *context, void *session_info, * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_k(void *context, void *session_info, +libspdm_return_t libspdm_append_message_k(libspdm_context_t *spdm_context, + void *session_info, bool is_requester, const void *message, size_t message_size) { @@ -1409,7 +1761,6 @@ libspdm_return_t libspdm_append_message_k(void *context, void *session_info, message_size); #else { - libspdm_context_t *spdm_context; uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; bool result; @@ -1417,32 +1768,21 @@ libspdm_return_t libspdm_append_message_k(void *context, void *session_info, uint32_t hash_size; uint8_t slot_id; - hash_size = 0; - spdm_context = context; - slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); if (spdm_session_info->session_transcript.digest_context_th == NULL) { if (!spdm_session_info->use_psk) { - LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); if (is_requester) { - if(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size - != 0) { - hash_size = - spdm_context->connection_info.peer_used_cert_chain[slot_id]. - buffer_hash_size; - libspdm_copy_mem(cert_chain_buffer_hash, - sizeof(cert_chain_buffer_hash), - spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash, - hash_size); - } else { - result = libspdm_get_peer_cert_chain_buffer( + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); if (!result) { return LIBSPDM_STATUS_INVALID_STATE_PEER; } - hash_size = libspdm_get_hash_size( - spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( spdm_context->connection_info.algorithm.base_hash_algo, cert_chain_buffer, cert_chain_buffer_size, @@ -1450,17 +1790,34 @@ libspdm_return_t libspdm_append_message_k(void *context, void *session_info, if (!result) { return LIBSPDM_STATUS_CRYPTO_ERROR; } + } else { + LIBSPDM_ASSERT( + hash_size == + spdm_context->connection_info + .peer_used_cert_chain[slot_id].buffer_hash_size); + libspdm_copy_mem(cert_chain_buffer_hash, + sizeof(cert_chain_buffer_hash), + spdm_context->connection_info + .peer_used_cert_chain[slot_id].buffer_hash, + hash_size); } } else { - result = libspdm_get_local_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); - + slot_id = spdm_context->connection_info.local_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_local_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } if (!result) { return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } - hash_size = libspdm_get_hash_size( - spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( spdm_context->connection_info.algorithm.base_hash_algo, cert_chain_buffer, cert_chain_buffer_size, @@ -1537,7 +1894,8 @@ libspdm_return_t libspdm_append_message_k(void *context, void *session_info, * @return RETURN_SUCCESS message is appended. * @return RETURN_OUT_OF_RESOURCES message is not appended because the internal cache is full. **/ -libspdm_return_t libspdm_append_message_f(void *context, void *session_info, +libspdm_return_t libspdm_append_message_f(libspdm_context_t *spdm_context, + void *session_info, bool is_requester, const void *message, size_t message_size) { @@ -1550,7 +1908,6 @@ libspdm_return_t libspdm_append_message_f(void *context, void *session_info, message_size); #else { - libspdm_context_t *spdm_context; const uint8_t *mut_cert_chain_buffer; size_t mut_cert_chain_buffer_size; bool result; @@ -1559,15 +1916,13 @@ libspdm_return_t libspdm_append_message_f(void *context, void *session_info, libspdm_return_t status; uint8_t slot_id; - hash_size = 0; - spdm_context = context; - slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); if (!spdm_session_info->session_transcript.message_f_initialized) { - /* digest_context_th might be NULL in unit test, where message_k is hardcoded. */ if (spdm_session_info->session_transcript.digest_context_th == NULL) { - status = libspdm_append_message_k (context, session_info, is_requester, NULL, 0); + status = + libspdm_append_message_k (spdm_context, session_info, is_requester, NULL, 0); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } @@ -1575,15 +1930,23 @@ libspdm_return_t libspdm_append_message_f(void *context, void *session_info, if (!spdm_session_info->use_psk && spdm_session_info->mut_auth_requested) { if (is_requester) { - result = libspdm_get_local_cert_chain_buffer( - spdm_context, - (const void **)&mut_cert_chain_buffer, - &mut_cert_chain_buffer_size); + slot_id = spdm_context->connection_info.local_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_local_public_key_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, + (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } if (!result) { return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } - hash_size = libspdm_get_hash_size( - spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( spdm_context->connection_info.algorithm.base_hash_algo, mut_cert_chain_buffer, mut_cert_chain_buffer_size, @@ -1592,26 +1955,17 @@ libspdm_return_t libspdm_append_message_f(void *context, void *session_info, return LIBSPDM_STATUS_CRYPTO_ERROR; } } else { - LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); - if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size - != 0) { - hash_size = - spdm_context->connection_info.peer_used_cert_chain[slot_id]. - buffer_hash_size; - libspdm_copy_mem(mut_cert_chain_buffer_hash, - sizeof(mut_cert_chain_buffer_hash), - spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash, - hash_size); - } else { - result = libspdm_get_peer_cert_chain_buffer( + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( spdm_context, (const void **)&mut_cert_chain_buffer, &mut_cert_chain_buffer_size); if (!result) { return LIBSPDM_STATUS_INVALID_STATE_PEER; } - hash_size = libspdm_get_hash_size( - spdm_context->connection_info.algorithm.base_hash_algo); + result = libspdm_hash_all( spdm_context->connection_info.algorithm.base_hash_algo, mut_cert_chain_buffer, mut_cert_chain_buffer_size, @@ -1619,6 +1973,17 @@ libspdm_return_t libspdm_append_message_f(void *context, void *session_info, if (!result) { return LIBSPDM_STATUS_CRYPTO_ERROR; } + } else { + LIBSPDM_ASSERT( + hash_size == + spdm_context->connection_info + .peer_used_cert_chain[slot_id].buffer_hash_size); + + libspdm_copy_mem(mut_cert_chain_buffer_hash, + sizeof(mut_cert_chain_buffer_hash), + spdm_context->connection_info + .peer_used_cert_chain[slot_id].buffer_hash, + hash_size); } } } @@ -1709,15 +2074,15 @@ uint8_t libspdm_get_connection_version(const libspdm_context_t *spdm_context) } /** - * This function returns if a capablities flag is supported in current SPDM connection. + * This function returns if a capabilities flag is supported in current SPDM connection. * * @param spdm_context A pointer to the SPDM context. * @param is_requester Is the function called from a requester. * @param requester_capabilities_flag The requester capabilities flag to be checked * @param responder_capabilities_flag The responder capabilities flag to be checked * - * @retval true the capablities flag is supported. - * @retval false the capablities flag is not supported. + * @retval true the capabilities flag is supported. + * @retval false the capabilities flag is not supported. **/ bool libspdm_is_capabilities_flag_supported(const libspdm_context_t *spdm_context, bool is_requester, @@ -1757,14 +2122,14 @@ bool libspdm_is_capabilities_flag_supported(const libspdm_context_t *spdm_contex * @param receive_message The fuction to receive an SPDM transport layer message. **/ void libspdm_register_device_io_func( - void *context, libspdm_device_send_message_func send_message, + void *spdm_context, libspdm_device_send_message_func send_message, libspdm_device_receive_message_func receive_message) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - spdm_context = context; - spdm_context->send_message = send_message; - spdm_context->receive_message = receive_message; + context = spdm_context; + context->send_message = send_message; + context->receive_message = receive_message; } /** @@ -1772,26 +2137,78 @@ void libspdm_register_device_io_func( * * This function must be called after libspdm_init_context, and before any SPDM communication. * + * The sender_buffer_size and receiver_buffer_size must be no smaller than + * MAX (non-secure Transport Message Header Size + + * SPDM_CAPABILITIES.DataTransferSize + + * max alignment pad size (transport specific), + * secure Transport Message Header Size + + * sizeof(spdm_secured_message_a_data_header1_t) + + * length of sequence_number (transport specific) + + * sizeof(spdm_secured_message_a_data_header2_t) + + * sizeof(spdm_secured_message_cipher_header_t) + + * App Message Header Size (transport specific) + + * SPDM_CAPABILITIES.DataTransferSize + + * maximum random data size (transport specific) + + * AEAD MAC size (16) + + * max alignment pad size (transport specific)). + * + * Finally, the SPDM_CAPABILITIES.DataTransferSize will be calculated based upon it. + * + * For MCTP, + * Transport Message Header Size = sizeof(mctp_message_header_t) + * length of sequence_number = 2 + * App Message Header Size = sizeof(mctp_message_header_t) + * maximum random data size = MCTP_MAX_RANDOM_NUMBER_COUNT + * max alignment pad size = 0 + * For PCI_DOE, + * Transport Message Header Size = sizeof(pci_doe_data_object_header_t) + * length of sequence_number = 0 + * App Message Header Size = 0 + * maximum random data size = 0 + * max alignment pad size = 3 + * * @param spdm_context A pointer to the SPDM context. + * @param sender_buffer_size Size in bytes of the sender buffer. + * @param receiver_buffer_size Size in bytes of the receiver buffer. * @param acquire_sender_buffer The fuction to acquire transport layer sender buffer. * @param release_sender_buffer The fuction to release transport layer sender buffer. * @param acquire_receiver_buffer The fuction to acquire transport layer receiver buffer. * @param release_receiver_buffer The fuction to release transport layer receiver buffer. **/ void libspdm_register_device_buffer_func( - void *context, + void *spdm_context, + uint32_t sender_buffer_size, + uint32_t receiver_buffer_size, libspdm_device_acquire_sender_buffer_func acquire_sender_buffer, libspdm_device_release_sender_buffer_func release_sender_buffer, libspdm_device_acquire_receiver_buffer_func acquire_receiver_buffer, libspdm_device_release_receiver_buffer_func release_receiver_buffer) { - libspdm_context_t *spdm_context; - - spdm_context = context; - spdm_context->acquire_sender_buffer = acquire_sender_buffer; - spdm_context->release_sender_buffer = release_sender_buffer; - spdm_context->acquire_receiver_buffer = acquire_receiver_buffer; - spdm_context->release_receiver_buffer = release_receiver_buffer; + libspdm_context_t *context; + + context = spdm_context; + context->sender_buffer_size = sender_buffer_size; + context->receiver_buffer_size = receiver_buffer_size; + context->acquire_sender_buffer = acquire_sender_buffer; + context->release_sender_buffer = release_sender_buffer; + context->acquire_receiver_buffer = acquire_receiver_buffer; + context->release_receiver_buffer = release_receiver_buffer; + + LIBSPDM_ASSERT (sender_buffer_size >= + context->local_context.capability.transport_header_size + + context->local_context.capability.transport_tail_size); + sender_buffer_size -= (context->local_context.capability.transport_header_size + + context->local_context.capability.transport_tail_size); + LIBSPDM_ASSERT (sender_buffer_size >= SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12); + context->local_context.capability.sender_data_transfer_size = sender_buffer_size; + + LIBSPDM_ASSERT(receiver_buffer_size >= + context->local_context.capability.transport_header_size + + context->local_context.capability.transport_tail_size); + receiver_buffer_size -= (context->local_context.capability.transport_header_size + + context->local_context.capability.transport_tail_size); + LIBSPDM_ASSERT (receiver_buffer_size >= SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12); + context->local_context.capability.data_transfer_size = receiver_buffer_size; } /** @@ -1802,20 +2219,40 @@ void libspdm_register_device_buffer_func( * @param spdm_context A pointer to the SPDM context. * @param transport_encode_message The fuction to encode an SPDM or APP message to a transport layer message. * @param transport_decode_message The fuction to decode an SPDM or APP message from a transport layer message. - * @param transport_get_header_size The fuction to get the maximum transport layer message header size. **/ void libspdm_register_transport_layer_func( - void *context, + void *spdm_context, + uint32_t max_spdm_msg_size, + uint32_t transport_header_size, + uint32_t transport_tail_size, libspdm_transport_encode_message_func transport_encode_message, - libspdm_transport_decode_message_func transport_decode_message, - libspdm_transport_get_header_size_func transport_get_header_size) + libspdm_transport_decode_message_func transport_decode_message) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - spdm_context = context; - spdm_context->transport_encode_message = transport_encode_message; - spdm_context->transport_decode_message = transport_decode_message; - spdm_context->transport_get_header_size = transport_get_header_size; + context = spdm_context; + + /* fix the data_transfer_size if it is set before */ + if ((context->local_context.capability.data_transfer_size != 0) && + (context->local_context.capability.data_transfer_size == + context->receiver_buffer_size)) { + context->local_context.capability.data_transfer_size = + (uint32_t)(context->receiver_buffer_size - + (transport_header_size + transport_tail_size)); + } + if ((context->local_context.capability.sender_data_transfer_size != 0) && + (context->local_context.capability.sender_data_transfer_size == + context->sender_buffer_size)) { + context->local_context.capability.sender_data_transfer_size = + (uint32_t)(context->sender_buffer_size - + (transport_header_size + transport_tail_size)); + } + + context->local_context.capability.max_spdm_msg_size = max_spdm_msg_size; + context->local_context.capability.transport_header_size = transport_header_size; + context->local_context.capability.transport_tail_size = transport_tail_size; + context->transport_encode_message = transport_encode_message; + context->transport_decode_message = transport_decode_message; } /** @@ -1833,13 +2270,13 @@ void libspdm_register_transport_layer_func( * @param verify_spdm_cert_chain The fuction to verify an SPDM certificate after GET_CERTIFICATE. **/ void libspdm_register_verify_spdm_cert_chain_func( - void *context, + void *spdm_context, const libspdm_verify_spdm_cert_chain_func verify_spdm_cert_chain) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - spdm_context = context; - spdm_context->local_context.verify_peer_spdm_cert_chain = verify_spdm_cert_chain; + context = spdm_context; + context->local_context.verify_peer_spdm_cert_chain = verify_spdm_cert_chain; } /** @@ -1852,10 +2289,16 @@ void libspdm_register_verify_spdm_cert_chain_func( * * @return the size of required scratch buffer. **/ -size_t libspdm_get_sizeof_required_scratch_buffer ( - void *context) +size_t libspdm_get_sizeof_required_scratch_buffer (void *spdm_context) { - return LIBSPDM_SCRATCH_BUFFER_SIZE; + libspdm_context_t *context; + size_t scratch_buffer_size; + + context = spdm_context; + LIBSPDM_ASSERT (context->local_context.capability.max_spdm_msg_size != 0); + + scratch_buffer_size = libspdm_get_scratch_buffer_capacity(context); + return scratch_buffer_size; } /** @@ -1869,16 +2312,23 @@ size_t libspdm_get_sizeof_required_scratch_buffer ( * **/ void libspdm_set_scratch_buffer ( - void *context, + void *spdm_context, void *scratch_buffer, size_t scratch_buffer_size) { - libspdm_context_t *spdm_context; - - spdm_context = context; - LIBSPDM_ASSERT (scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); - spdm_context->scratch_buffer = scratch_buffer; - spdm_context->scratch_buffer_size = scratch_buffer_size; + libspdm_context_t *context; + + context = spdm_context; + LIBSPDM_ASSERT (context->local_context.capability.max_spdm_msg_size != 0); + LIBSPDM_ASSERT (scratch_buffer_size >= libspdm_get_scratch_buffer_capacity(spdm_context)); + context->scratch_buffer = scratch_buffer; + context->scratch_buffer_size = scratch_buffer_size; + context->last_spdm_request = (uint8_t *)scratch_buffer + + libspdm_get_scratch_buffer_last_spdm_request_offset(spdm_context); +#if LIBSPDM_RESPOND_IF_READY_SUPPORT + context->cache_spdm_request = (uint8_t *)scratch_buffer + + libspdm_get_scratch_buffer_cache_spdm_request_offset(spdm_context); +#endif } /** @@ -1890,24 +2340,29 @@ void libspdm_set_scratch_buffer ( * **/ void libspdm_get_scratch_buffer ( - void *context, + void *spdm_context, void **scratch_buffer, size_t *scratch_buffer_size) { - libspdm_context_t *spdm_context; - - spdm_context = context; - LIBSPDM_ASSERT (spdm_context->scratch_buffer != NULL); - LIBSPDM_ASSERT (spdm_context->scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); - *scratch_buffer = spdm_context->scratch_buffer; - *scratch_buffer_size = spdm_context->scratch_buffer_size; + libspdm_context_t *context; + + context = spdm_context; + LIBSPDM_ASSERT (context->scratch_buffer != NULL); + LIBSPDM_ASSERT (context->scratch_buffer_size >= + libspdm_get_scratch_buffer_capacity(spdm_context)); + *scratch_buffer = context->scratch_buffer; + *scratch_buffer_size = context->scratch_buffer_size; + /* need to remove last 2 sections, because they are for libspdm internal state track. */ + *scratch_buffer_size -= libspdm_get_scratch_buffer_last_spdm_request_capacity(spdm_context); +#if LIBSPDM_RESPOND_IF_READY_SUPPORT + *scratch_buffer_size -= libspdm_get_scratch_buffer_cache_spdm_request_capacity(spdm_context); +#endif } /** * Acquire a device sender buffer for transport layer message. * * @param context A pointer to the SPDM context. - * @param max_msg_size size in bytes of the maximum size of sender buffer. * @param msg_buf_ptr A pointer to a sender buffer. * * @retval RETURN_SUCCESS The sender buffer is acquired. @@ -1918,18 +2373,18 @@ libspdm_return_t libspdm_acquire_sender_buffer ( libspdm_return_t status; LIBSPDM_ASSERT (spdm_context->sender_buffer == NULL); - LIBSPDM_ASSERT (spdm_context->sender_buffer_size == 0); - status = spdm_context->acquire_sender_buffer (spdm_context, max_msg_size, msg_buf_ptr); + LIBSPDM_ASSERT (spdm_context->sender_buffer_size != 0); + status = spdm_context->acquire_sender_buffer (spdm_context, msg_buf_ptr); if (status != LIBSPDM_STATUS_SUCCESS) { return status; } spdm_context->sender_buffer = *msg_buf_ptr; - spdm_context->sender_buffer_size = *max_msg_size; - #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + *max_msg_size = spdm_context->sender_buffer_size; + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP /* it return scratch buffer, because the requester need build message there.*/ *msg_buf_ptr = spdm_context->scratch_buffer + - LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; - *max_msg_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + libspdm_get_scratch_buffer_large_sender_receiver_offset(spdm_context); + *max_msg_size = libspdm_get_scratch_buffer_large_sender_receiver_capacity(spdm_context); #endif return LIBSPDM_STATUS_SUCCESS; } @@ -1948,7 +2403,6 @@ void libspdm_release_sender_buffer (libspdm_context_t *spdm_context) spdm_context->release_sender_buffer (spdm_context, spdm_context->sender_buffer); spdm_context->sender_buffer = NULL; - spdm_context->sender_buffer_size = 0; } /** @@ -1983,18 +2437,18 @@ libspdm_return_t libspdm_acquire_receiver_buffer ( libspdm_return_t status; LIBSPDM_ASSERT (spdm_context->receiver_buffer == NULL); - LIBSPDM_ASSERT (spdm_context->receiver_buffer_size == 0); - status = spdm_context->acquire_receiver_buffer (spdm_context, max_msg_size, msg_buf_ptr); + LIBSPDM_ASSERT (spdm_context->receiver_buffer_size != 0); + status = spdm_context->acquire_receiver_buffer (spdm_context, msg_buf_ptr); if (status != LIBSPDM_STATUS_SUCCESS) { return status; } spdm_context->receiver_buffer = *msg_buf_ptr; - spdm_context->receiver_buffer_size = *max_msg_size; - #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + *max_msg_size = spdm_context->receiver_buffer_size; + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP /* it return scratch buffer, because the requester need build message there.*/ *msg_buf_ptr = spdm_context->scratch_buffer + - LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; - *max_msg_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + libspdm_get_scratch_buffer_large_sender_receiver_offset(spdm_context); + *max_msg_size = libspdm_get_scratch_buffer_large_sender_receiver_capacity(spdm_context); #endif return LIBSPDM_STATUS_SUCCESS; } @@ -2013,7 +2467,6 @@ void libspdm_release_receiver_buffer (libspdm_context_t *spdm_context) spdm_context->release_receiver_buffer (spdm_context, spdm_context->receiver_buffer); spdm_context->receiver_buffer = NULL; - spdm_context->receiver_buffer_size = 0; } /** @@ -2039,13 +2492,13 @@ void libspdm_get_receiver_buffer ( * @param spdm_context A pointer to the SPDM context. * @param last_spdm_error Last SPDM error struct of an SPDM context. */ -void libspdm_get_last_spdm_error_struct(void *context, libspdm_error_struct_t *last_spdm_error) +void libspdm_get_last_spdm_error_struct(void *spdm_context, libspdm_error_struct_t *last_spdm_error) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - spdm_context = context; + context = spdm_context; libspdm_copy_mem(last_spdm_error, sizeof(libspdm_error_struct_t), - &spdm_context->last_spdm_error,sizeof(libspdm_error_struct_t)); + &context->last_spdm_error,sizeof(libspdm_error_struct_t)); } /** @@ -2054,15 +2507,121 @@ void libspdm_get_last_spdm_error_struct(void *context, libspdm_error_struct_t *l * @param spdm_context A pointer to the SPDM context. * @param last_spdm_error Last SPDM error struct of an SPDM context. */ -void libspdm_set_last_spdm_error_struct(void *context, libspdm_error_struct_t *last_spdm_error) +void libspdm_set_last_spdm_error_struct(void *spdm_context, libspdm_error_struct_t *last_spdm_error) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - spdm_context = context; - libspdm_copy_mem(&spdm_context->last_spdm_error, sizeof(spdm_context->last_spdm_error), + context = spdm_context; + libspdm_copy_mem(&context->last_spdm_error, sizeof(context->last_spdm_error), last_spdm_error, sizeof(libspdm_error_struct_t)); } +#if LIBSPDM_FIPS_MODE +/** + * Initialize an libspdm_fips_selftest_context. + * + * @param fips_selftest_context A pointer to the fips_selftest_context. + * + * @retval RETURN_SUCCESS context is initialized. + * @retval RETURN_DEVICE_ERROR context initialization failed. + */ +libspdm_return_t libspdm_init_fips_selftest_context(void *fips_selftest_context) +{ + libspdm_fips_selftest_context *context; + LIBSPDM_ASSERT(fips_selftest_context != NULL); + + context = fips_selftest_context; + + /*No tested for every uesd algo*/ + context->tested_algo = 0; + /*self_test reuslt is false for every uesd algo*/ + context->self_test_result = 0; + + return LIBSPDM_STATUS_SUCCESS; +} + +/** + * Return the size in bytes of the fips_selftest_context. + * + * @return the size in bytes of the fips_selftest_context. + **/ +size_t libspdm_get_fips_selftest_context_size(void) +{ + size_t size; + + size = sizeof(libspdm_fips_selftest_context); + return size; +} + +/** + * import fips_selftest_context to spdm_context; + * + * @param[in,out] spdm_context A pointer to the spdm_context. + * @param[in] fips_selftest_context A pointer to the fips_selftest_context. + * @param[in] fips_selftest_context_size The size of fips_selftest_context. + * + * @retval true import fips_selftest_context successful. + * @retval false spdm_context or fips_selftest_context is null. + */ +bool libspdm_import_fips_selftest_context_to_spdm_context(void *spdm_context, + void *fips_selftest_context, + size_t fips_selftest_context_size) +{ + libspdm_fips_selftest_context *libspdm_fips_selftest_context; + libspdm_context_t *libspdm_context; + + libspdm_context = spdm_context; + libspdm_fips_selftest_context = fips_selftest_context; + + if ((libspdm_context == NULL) || (libspdm_fips_selftest_context == NULL)) { + return false; + } + if (fips_selftest_context_size != sizeof(libspdm_fips_selftest_context)) { + return false; + } + + libspdm_copy_mem(&(libspdm_context->fips_selftest_context), + sizeof(libspdm_fips_selftest_context), + libspdm_fips_selftest_context, sizeof(libspdm_fips_selftest_context)); + return true; +} + +/** + * export fips_selftest_context from spdm_context; + * + * @param[in] spdm_context A pointer to the spdm_context. + * @param[in,out] fips_selftest_context A pointer to the fips_selftest_context. + * @param[in] fips_selftest_context_size The size of fips_selftest_context. + * + * @retval true export fips_selftest_context successful. + * @retval false spdm_context or fips_selftest_context is null. + */ +bool libspdm_export_fips_selftest_context_from_spdm_context(void *spdm_context, + void *fips_selftest_context, + size_t fips_selftest_context_size) +{ + libspdm_fips_selftest_context *libspdm_fips_selftest_context; + libspdm_context_t *libspdm_context; + + libspdm_context = spdm_context; + libspdm_fips_selftest_context = fips_selftest_context; + + if ((libspdm_context == NULL) || (libspdm_fips_selftest_context == NULL)) { + return false; + } + if (fips_selftest_context_size != sizeof(libspdm_fips_selftest_context)) { + return false; + } + + libspdm_copy_mem(libspdm_fips_selftest_context, + sizeof(libspdm_fips_selftest_context), + &(libspdm_context->fips_selftest_context), + sizeof(libspdm_fips_selftest_context)); + return true; +} + +#endif /* LIBSPDM_FIPS_MODE */ + /** * Initialize an SPDM context, as well as all secured message contexts, * in the specified locations. @@ -2082,67 +2641,66 @@ void libspdm_set_last_spdm_error_struct(void *context, libspdm_error_struct_t *l * @retval RETURN_SUCCESS Contexts are initialized. * @retval RETURN_DEVICE_ERROR Context initialization failed. */ -libspdm_return_t libspdm_init_context_with_secured_context(void *context, +libspdm_return_t libspdm_init_context_with_secured_context(void *spdm_context, void **secured_contexts, size_t num_secured_contexts) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; size_t index; - LIBSPDM_ASSERT(context != NULL); + LIBSPDM_ASSERT(spdm_context != NULL); LIBSPDM_ASSERT(secured_contexts != NULL); LIBSPDM_ASSERT(num_secured_contexts == LIBSPDM_MAX_SESSION_COUNT); - spdm_context = context; - libspdm_zero_mem(spdm_context, sizeof(libspdm_context_t)); - spdm_context->version = libspdm_context_struct_version; - spdm_context->transcript.message_a.max_buffer_size = - sizeof(spdm_context->transcript.message_a.buffer); + context = spdm_context; + libspdm_zero_mem(context, sizeof(libspdm_context_t)); + context->version = LIBSPDM_CONTEXT_STRUCT_VERSION; + context->transcript.message_a.max_buffer_size = + sizeof(context->transcript.message_a.buffer); #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - spdm_context->transcript.message_b.max_buffer_size = - sizeof(spdm_context->transcript.message_b.buffer); - spdm_context->transcript.message_c.max_buffer_size = - sizeof(spdm_context->transcript.message_c.buffer); - spdm_context->transcript.message_mut_b.max_buffer_size = - sizeof(spdm_context->transcript.message_mut_b.buffer); - spdm_context->transcript.message_mut_c.max_buffer_size = - sizeof(spdm_context->transcript.message_mut_c.buffer); - spdm_context->transcript.message_m.max_buffer_size = - sizeof(spdm_context->transcript.message_m.buffer); + context->transcript.message_b.max_buffer_size = + sizeof(context->transcript.message_b.buffer); + context->transcript.message_c.max_buffer_size = + sizeof(context->transcript.message_c.buffer); + context->transcript.message_mut_b.max_buffer_size = + sizeof(context->transcript.message_mut_b.buffer); + context->transcript.message_mut_c.max_buffer_size = + sizeof(context->transcript.message_mut_c.buffer); + context->transcript.message_m.max_buffer_size = + sizeof(context->transcript.message_m.buffer); #endif - spdm_context->retry_times = LIBSPDM_MAX_REQUEST_RETRY_TIMES; - spdm_context->response_state = LIBSPDM_RESPONSE_STATE_NORMAL; - spdm_context->current_token = 0; - spdm_context->local_context.version.spdm_version_count = 3; - spdm_context->local_context.version.spdm_version[0] = SPDM_MESSAGE_VERSION_10 << - SPDM_VERSION_NUMBER_SHIFT_BIT; - spdm_context->local_context.version.spdm_version[1] = SPDM_MESSAGE_VERSION_11 << - SPDM_VERSION_NUMBER_SHIFT_BIT; - spdm_context->local_context.version.spdm_version[2] = SPDM_MESSAGE_VERSION_12 << - SPDM_VERSION_NUMBER_SHIFT_BIT; - spdm_context->local_context.secured_message_version.spdm_version_count = 2; - spdm_context->local_context.secured_message_version.spdm_version[0] = + context->response_state = LIBSPDM_RESPONSE_STATE_NORMAL; + context->local_context.version.spdm_version_count = 3; + context->local_context.version.spdm_version[0] = SPDM_MESSAGE_VERSION_10 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + context->local_context.version.spdm_version[1] = SPDM_MESSAGE_VERSION_11 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + context->local_context.version.spdm_version[2] = SPDM_MESSAGE_VERSION_12 << + SPDM_VERSION_NUMBER_SHIFT_BIT; + context->local_context.secured_message_version.spdm_version_count = 2; + context->local_context.secured_message_version.spdm_version[0] = SPDM_MESSAGE_VERSION_10 << SPDM_VERSION_NUMBER_SHIFT_BIT; - spdm_context->local_context.secured_message_version.spdm_version[1] = + context->local_context.secured_message_version.spdm_version[1] = SPDM_MESSAGE_VERSION_11 << SPDM_VERSION_NUMBER_SHIFT_BIT; - spdm_context->local_context.capability.st1 = SPDM_ST1_VALUE_US; + context->local_context.capability.st1 = SPDM_ST1_VALUE_US; - spdm_context->encap_context.certificate_chain_buffer.max_buffer_size = - sizeof(spdm_context->encap_context.certificate_chain_buffer.buffer); + context->mut_auth_cert_chain_buffer_size = 0; - /* From the config.h, need different value for CHUNK - TBD*/ - spdm_context->local_context.capability.data_transfer_size = LIBSPDM_DATA_TRANSFER_SIZE; - spdm_context->local_context.capability.max_spdm_msg_size = LIBSPDM_MAX_SPDM_MSG_SIZE; + context->max_spdm_session_sequence_number = LIBSPDM_MAX_SPDM_SESSION_SEQUENCE_NUMBER; + + /* To be updated in libspdm_register_device_buffer_func */ + context->local_context.capability.data_transfer_size = 0; + context->local_context.capability.sender_data_transfer_size = 0; + context->local_context.capability.max_spdm_msg_size = 0; for (index = 0; index < num_secured_contexts; index++) { if (secured_contexts[index] == NULL) { return LIBSPDM_STATUS_INVALID_PARAMETER; } - spdm_context->session_info[index].secured_message_context = secured_contexts[index]; + context->session_info[index].secured_message_context = secured_contexts[index]; libspdm_secured_message_init_context( - spdm_context->session_info[index] - .secured_message_context); + context->session_info[index].secured_message_context); } return LIBSPDM_STATUS_SUCCESS; @@ -2160,84 +2718,70 @@ libspdm_return_t libspdm_init_context_with_secured_context(void *context, * @retval RETURN_SUCCESS context is initialized. * @retval RETURN_DEVICE_ERROR context initialization failed. */ -libspdm_return_t libspdm_init_context(void *context) +libspdm_return_t libspdm_init_context(void *spdm_context) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; void *secured_context; void *secured_contexts[LIBSPDM_MAX_SESSION_COUNT]; size_t secured_context_size; size_t index; - LIBSPDM_ASSERT(context != NULL); + LIBSPDM_ASSERT(spdm_context != NULL); /* libspdm_get_context_size() allocates space for all secured message * contexts. They are appended to the general SPDM context. */ - spdm_context = context; - secured_context = (void *)((size_t)(spdm_context + 1)); + context = spdm_context; + secured_context = (void *)((size_t)(context + 1)); secured_context_size = libspdm_secured_message_get_context_size(); for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { - secured_contexts[index] = - (uint8_t *)secured_context + secured_context_size * index; + secured_contexts[index] = (uint8_t *)secured_context + secured_context_size * index; } - return libspdm_init_context_with_secured_context(context, + return libspdm_init_context_with_secured_context(spdm_context, secured_contexts, LIBSPDM_MAX_SESSION_COUNT); } -/** - * Reset an SPDM context. - * - * The size in bytes of the spdm_context can be returned by libspdm_get_context_size. - * - * @param spdm_context A pointer to the SPDM context. - */ -void libspdm_reset_context(void *context) +void libspdm_reset_context(void *spdm_context) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; size_t index; - spdm_context = context; + context = spdm_context; /*Clear all info about last connection*/ /*need clear session info to free context before algo is zeroed.*/ for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { - libspdm_session_info_init(spdm_context, - &spdm_context->session_info[index], + libspdm_session_info_init(context, + &context->session_info[index], INVALID_SESSION_ID, false); } - spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_NOT_STARTED; - libspdm_zero_mem(&spdm_context->connection_info.version, sizeof(spdm_version_number_t)); - libspdm_zero_mem(&spdm_context->connection_info.capability, + context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_NOT_STARTED; + libspdm_zero_mem(&context->connection_info.version, sizeof(spdm_version_number_t)); + libspdm_zero_mem(&context->connection_info.capability, sizeof(libspdm_device_capability_t)); - libspdm_zero_mem(&spdm_context->connection_info.algorithm, sizeof(libspdm_device_algorithm_t)); - libspdm_zero_mem(&spdm_context->last_spdm_error, sizeof(libspdm_error_struct_t)); - libspdm_zero_mem(&spdm_context->encap_context, sizeof(libspdm_encap_context_t)); - spdm_context->connection_info.local_used_cert_chain_buffer_size = 0; - spdm_context->connection_info.local_used_cert_chain_buffer = NULL; - spdm_context->cache_spdm_request_size = 0; - spdm_context->retry_times = LIBSPDM_MAX_REQUEST_RETRY_TIMES; - spdm_context->response_state = LIBSPDM_RESPONSE_STATE_NORMAL; - spdm_context->current_token = 0; - spdm_context->last_spdm_request_session_id = INVALID_SESSION_ID; - spdm_context->last_spdm_request_session_id_valid = false; - spdm_context->last_spdm_request_size = 0; - spdm_context->encap_context.certificate_chain_buffer.max_buffer_size = - sizeof(spdm_context->encap_context.certificate_chain_buffer.buffer); - - #if LIBSPDM_ENABLE_MSG_LOG - spdm_context->msg_log.buffer = NULL; - spdm_context->msg_log.max_buffer_size = 0; - spdm_context->msg_log.buffer_size = 0; - spdm_context->msg_log.mode = 0; - spdm_context->msg_log.status = 0; - #endif /* LIBSPDM_ENABLE_MSG_LOG */ + libspdm_zero_mem(&context->connection_info.algorithm, sizeof(libspdm_device_algorithm_t)); + libspdm_zero_mem(&context->last_spdm_error, sizeof(libspdm_error_struct_t)); + libspdm_zero_mem(&context->encap_context, sizeof(libspdm_encap_context_t)); + context->connection_info.local_used_cert_chain_buffer_size = 0; + context->connection_info.local_used_cert_chain_buffer = NULL; +#if LIBSPDM_RESPOND_IF_READY_SUPPORT + context->cache_spdm_request_size = 0; +#endif + context->response_state = LIBSPDM_RESPONSE_STATE_NORMAL; + context->current_token = 0; + context->last_spdm_request_session_id = INVALID_SESSION_ID; + context->last_spdm_request_session_id_valid = false; + context->last_spdm_request_size = 0; + context->mut_auth_cert_chain_buffer_size = 0; + context->current_dhe_session_count = 0; + context->current_psk_session_count = 0; } /** @@ -2248,37 +2792,53 @@ void libspdm_reset_context(void *context) * @param[in] spdm_context A pointer to the SPDM context. * */ -void libspdm_deinit_context(void *context) +void libspdm_deinit_context(void *spdm_context) { + uint32_t session_id; + libspdm_context_t *context; + libspdm_session_info_t *session_info; #if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) - libspdm_context_t *spdm_context; void *pubkey_context; bool is_requester; uint8_t slot_index; +#endif - spdm_context = context; - is_requester = spdm_context->local_context.is_requester; + context = spdm_context; + +#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) + is_requester = context->local_context.is_requester; for (slot_index = 0; slot_index < SPDM_MAX_SLOT_COUNT; slot_index++) { - pubkey_context = spdm_context->connection_info.peer_used_cert_chain[slot_index]. + pubkey_context = context->connection_info.peer_used_cert_chain[slot_index]. leaf_cert_public_key; if (pubkey_context != NULL) { if (is_requester) { libspdm_asym_free( - spdm_context->connection_info.algorithm.base_asym_algo, pubkey_context); + context->connection_info.algorithm.base_asym_algo, pubkey_context); } else { libspdm_req_asym_free( - spdm_context->connection_info.algorithm.req_base_asym_alg, pubkey_context); + context->connection_info.algorithm.req_base_asym_alg, pubkey_context); } pubkey_context = NULL; - spdm_context->connection_info.peer_used_cert_chain[slot_index]. + context->connection_info.peer_used_cert_chain[slot_index]. leaf_cert_public_key = NULL; } } - #endif + + libspdm_reset_message_a(context); + libspdm_reset_message_b(context); + libspdm_reset_message_c(context); + libspdm_reset_message_mut_b(context); + libspdm_reset_message_mut_c(context); + for (session_id = 0; session_id < LIBSPDM_MAX_SESSION_COUNT; session_id++) { + session_info = &context->session_info[session_id]; + libspdm_reset_message_m(context, session_info); + libspdm_reset_message_k(context, session_info); + libspdm_reset_message_f(context, session_info); + } } /** diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_context_data_session.c similarity index 81% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_context_data_session.c index 78180423cd..c5079f8dcf 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_context_data_session.c @@ -4,7 +4,7 @@ * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md **/ -#include "internal/libspdm_common_lib.h" +#include "internal/libspdm_secured_message_lib.h" /** * This function initializes the session info. @@ -19,6 +19,30 @@ void libspdm_session_info_init(libspdm_context_t *spdm_context, libspdm_session_type_t session_type; uint32_t capabilities_flag; + if (session_id != INVALID_SESSION_ID) { + if (use_psk) { + LIBSPDM_ASSERT((spdm_context->max_psk_session_count == 0) || + (spdm_context->current_psk_session_count < + spdm_context->max_psk_session_count)); + spdm_context->current_psk_session_count++; + } else { + LIBSPDM_ASSERT((spdm_context->max_dhe_session_count == 0) || + (spdm_context->current_dhe_session_count < + spdm_context->max_dhe_session_count)); + spdm_context->current_dhe_session_count++; + } + } else { + if (use_psk) { + if (spdm_context->current_psk_session_count > 0) { + spdm_context->current_psk_session_count--; + } + } else { + if (spdm_context->current_dhe_session_count > 0) { + spdm_context->current_dhe_session_count--; + } + } + } + capabilities_flag = spdm_context->connection_info.capability.flags & spdm_context->local_context.capability.flags; switch (capabilities_flag & @@ -60,6 +84,10 @@ void libspdm_session_info_init(libspdm_context_t *spdm_context, session_info->use_psk = use_psk; libspdm_secured_message_set_use_psk(session_info->secured_message_context, use_psk); libspdm_secured_message_set_session_type(session_info->secured_message_context, session_type); + libspdm_secured_message_set_sequence_number_endian(session_info->secured_message_context, + spdm_context->sequence_number_endian); + libspdm_secured_message_set_max_spdm_session_sequence_number( + session_info->secured_message_context, spdm_context->max_spdm_session_sequence_number); libspdm_secured_message_set_algorithms( session_info->secured_message_context, spdm_context->connection_info.version, @@ -103,9 +131,9 @@ void libspdm_session_info_set_psk_hint(libspdm_session_info_t *session_info, * * @return session info. **/ -void *libspdm_get_session_info_via_session_id(void *context, uint32_t session_id) +void *libspdm_get_session_info_via_session_id(void *spdm_context, uint32_t session_id) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; libspdm_session_info_t *session_info; size_t index; @@ -116,9 +144,9 @@ void *libspdm_get_session_info_via_session_id(void *context, uint32_t session_id return NULL; } - spdm_context = context; + context = spdm_context; - session_info = (libspdm_session_info_t *)spdm_context->session_info; + session_info = (libspdm_session_info_t *)context->session_info; for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { if (session_info[index].session_id == session_id) { return &session_info[index]; @@ -170,7 +198,7 @@ void *libspdm_get_secured_message_context_via_session_info(void *spdm_session_in } /** - * This function generate a new session ID by concatnating req_session_id and rsp_session_id. + * This function generate a new session ID by concatenating req_session_id and rsp_session_id. * * @param[in] req_session_id * @param[in] rsp_session_id @@ -192,14 +220,11 @@ uint32_t libspdm_generate_session_id(uint16_t req_session_id, uint16_t rsp_sessi * * @return session info associated with this new session ID. **/ -void *libspdm_assign_session_id(void *context, uint32_t session_id, bool use_psk) +void *libspdm_assign_session_id(libspdm_context_t *spdm_context, uint32_t session_id, bool use_psk) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; size_t index; - spdm_context = context; - if (session_id == INVALID_SESSION_ID) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_assign_session_id - Invalid session_id\n")); LIBSPDM_ASSERT(false); @@ -237,14 +262,11 @@ void *libspdm_assign_session_id(void *context, uint32_t session_id, bool use_psk * @param spdm_context A pointer to the SPDM context. * @param session_id The SPDM session ID. **/ -void libspdm_free_session_id(void *context, uint32_t session_id) +void libspdm_free_session_id(libspdm_context_t *spdm_context, uint32_t session_id) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; size_t index; - spdm_context = context; - if (session_id == INVALID_SESSION_ID) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "libspdm_free_session_id - Invalid session_id\n")); LIBSPDM_ASSERT(false); @@ -256,7 +278,8 @@ void libspdm_free_session_id(void *context, uint32_t session_id) if (session_info[index].session_id == session_id) { libspdm_session_info_init(spdm_context, &session_info[index], - INVALID_SESSION_ID, false); + INVALID_SESSION_ID, + session_info[index].use_psk); return; } } diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_crypto_service.c similarity index 70% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_crypto_service.c index b3f86d6a63..7b93937eba 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_crypto_service.c @@ -10,37 +10,30 @@ * This function returns peer certificate chain buffer including spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. - * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param cert_chain_buffer Certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certificate chain buffer. * * @retval true Peer certificate chain buffer including spdm_cert_chain_t header is returned. * @retval false Peer certificate chain buffer including spdm_cert_chain_t header is not found. **/ -bool libspdm_get_peer_cert_chain_buffer(void *context, +bool libspdm_get_peer_cert_chain_buffer(void *spdm_context, const void **cert_chain_buffer, size_t *cert_chain_buffer_size) { - libspdm_context_t *spdm_context; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_context_t *context; uint8_t slot_id; -#endif - spdm_context = context; -#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + context = spdm_context; + slot_id = context->connection_info.peer_used_cert_chain_slot_id; LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); - if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size != 0) { - *cert_chain_buffer = spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer; - *cert_chain_buffer_size = spdm_context->connection_info + if (context->connection_info.peer_used_cert_chain[slot_id].buffer_size != 0) { + *cert_chain_buffer = context->connection_info.peer_used_cert_chain[slot_id].buffer; + *cert_chain_buffer_size = context->connection_info .peer_used_cert_chain[slot_id].buffer_size; return true; } #endif - if (spdm_context->local_context.peer_cert_chain_provision_size != 0) { - *cert_chain_buffer = spdm_context->local_context.peer_cert_chain_provision; - *cert_chain_buffer_size = spdm_context->local_context.peer_cert_chain_provision_size; - return true; - } return false; } @@ -48,56 +41,57 @@ bool libspdm_get_peer_cert_chain_buffer(void *context, * This function returns peer certificate chain data without spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. - * @param cert_chain_data_size size in bytes of the certitiface chain data. + * @param cert_chain_data Certificate chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size size in bytes of the certificate chain data. * * @retval true Peer certificate chain data without spdm_cert_chain_t header is returned. * @retval false Peer certificate chain data without spdm_cert_chain_t header is not found. **/ -bool libspdm_get_peer_cert_chain_data(void *context, +bool libspdm_get_peer_cert_chain_data(void *spdm_context, const void **cert_chain_data, size_t *cert_chain_data_size) { - libspdm_context_t *spdm_context; - bool result; +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + libspdm_context_t *context; size_t hash_size; + bool result; - spdm_context = context; + context = spdm_context; + hash_size = libspdm_get_hash_size(context->connection_info.algorithm.base_hash_algo); - result = libspdm_get_peer_cert_chain_buffer(spdm_context, cert_chain_data, + result = libspdm_get_peer_cert_chain_buffer(context, cert_chain_data, cert_chain_data_size); - if (!result) { - return false; + if (result) { + *cert_chain_data = + (const uint8_t *)*cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; + *cert_chain_data_size = + *cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); + return true; } - - hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); - - *cert_chain_data = (const uint8_t *)*cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; - *cert_chain_data_size = *cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); - - return true; +#endif + return false; } /** * This function returns local used certificate chain buffer including spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. - * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param cert_chain_buffer Certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certificate chain buffer. * * @retval true Local used certificate chain buffer including spdm_cert_chain_t header is returned. * @retval false Local used certificate chain buffer including spdm_cert_chain_t header is not found. **/ -bool libspdm_get_local_cert_chain_buffer(void *context, +bool libspdm_get_local_cert_chain_buffer(void *spdm_context, const void **cert_chain_buffer, size_t *cert_chain_buffer_size) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - spdm_context = context; - if (spdm_context->connection_info.local_used_cert_chain_buffer_size != 0) { - *cert_chain_buffer = spdm_context->connection_info.local_used_cert_chain_buffer; - *cert_chain_buffer_size = spdm_context->connection_info.local_used_cert_chain_buffer_size; + context = spdm_context; + if (context->connection_info.local_used_cert_chain_buffer_size != 0) { + *cert_chain_buffer = context->connection_info.local_used_cert_chain_buffer; + *cert_chain_buffer_size = context->connection_info.local_used_cert_chain_buffer_size; return true; } return false; @@ -107,35 +101,85 @@ bool libspdm_get_local_cert_chain_buffer(void *context, * This function returns local used certificate chain data without spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_data Certitiface chain data without spdm_cert_chain_t header. - * @param cert_chain_data_size size in bytes of the certitiface chain data. + * @param cert_chain_data Certificate chain data without spdm_cert_chain_t header. + * @param cert_chain_data_size size in bytes of the certificate chain data. * * @retval true Local used certificate chain data without spdm_cert_chain_t header is returned. * @retval false Local used certificate chain data without spdm_cert_chain_t header is not found. **/ -bool libspdm_get_local_cert_chain_data(void *context, +bool libspdm_get_local_cert_chain_data(void *spdm_context, const void **cert_chain_data, size_t *cert_chain_data_size) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; bool result; size_t hash_size; - spdm_context = context; + context = spdm_context; - result = libspdm_get_local_cert_chain_buffer(spdm_context, cert_chain_data, + result = libspdm_get_local_cert_chain_buffer(context, cert_chain_data, cert_chain_data_size); if (!result) { return false; } - hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + hash_size = libspdm_get_hash_size(context->connection_info.algorithm.base_hash_algo); *cert_chain_data = (const uint8_t *)*cert_chain_data + sizeof(spdm_cert_chain_t) + hash_size; *cert_chain_data_size = *cert_chain_data_size - (sizeof(spdm_cert_chain_t) + hash_size); return true; } +/** + * This function returns peer public key buffer. + * + * @param spdm_context A pointer to the SPDM context. + * @param peer_public_key_buffer Peer public key buffer. + * @param peer_public_key_buffer_size Size in bytes of peer public key buffer. + * + * @retval true Peer public key buffer is returned. + * @retval false Peer public key buffer is not found. + **/ +bool libspdm_get_peer_public_key_buffer(void *spdm_context, + const void **peer_public_key_buffer, + size_t *peer_public_key_buffer_size) +{ + libspdm_context_t *context; + + context = spdm_context; + if (context->local_context.peer_public_key_provision_size != 0) { + *peer_public_key_buffer = context->local_context.peer_public_key_provision; + *peer_public_key_buffer_size = context->local_context.peer_public_key_provision_size; + return true; + } + return false; +} + +/** + * This function returns local public key buffer. + * + * @param spdm_context A pointer to the SPDM context. + * @param local_public_key_buffer Local public key buffer. + * @param local_public_key_buffer_size Size in bytes of local public key buffer. + * + * @retval true Local public key buffer is returned. + * @retval false Local public key buffer is not found. + **/ +bool libspdm_get_local_public_key_buffer(void *spdm_context, + const void **local_public_key_buffer, + size_t *local_public_key_buffer_size) +{ + libspdm_context_t *context; + + context = spdm_context; + if (context->local_context.peer_public_key_provision_size != 0) { + *local_public_key_buffer = context->local_context.local_public_key_provision; + *local_public_key_buffer_size = context->local_context.local_public_key_provision_size; + return true; + } + return false; +} + #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT /* * This function calculates l1l2. @@ -148,17 +192,16 @@ bool libspdm_get_local_cert_chain_data(void *context, * * @retval RETURN_SUCCESS l1l2 is calculated. */ -bool libspdm_calculate_l1l2(void *context, void *session_info, - libspdm_large_managed_buffer_t *l1l2) +bool libspdm_calculate_l1l2(libspdm_context_t *spdm_context, + void *session_info, + libspdm_l1l2_managed_buffer_t *l1l2) { - libspdm_context_t *spdm_context; libspdm_return_t status; libspdm_session_info_t *spdm_session_info; - spdm_context = context; spdm_session_info = session_info; - libspdm_init_managed_buffer(l1l2, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + libspdm_init_managed_buffer(l1l2, sizeof(l1l2->buffer)); if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { @@ -232,16 +275,15 @@ bool libspdm_calculate_l1l2(void *context, void *session_info, * * @retval RETURN_SUCCESS l1l2 is calculated. */ -bool libspdm_calculate_l1l2_hash(void *context, void *session_info, +bool libspdm_calculate_l1l2_hash(libspdm_context_t *spdm_context, + void *session_info, size_t *l1l2_hash_size, void *l1l2_hash) { - libspdm_context_t *spdm_context; libspdm_session_info_t *spdm_session_info; bool result; uint32_t hash_size; - spdm_context = context; spdm_session_info = session_info; hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); @@ -279,14 +321,14 @@ bool libspdm_calculate_l1l2_hash(void *context, void *session_info, * @retval RETURN_SUCCESS m1m2 is calculated. */ static bool libspdm_calculate_m1m2(void *context, bool is_mut, - libspdm_large_managed_buffer_t *m1m2) + libspdm_m1m2_managed_buffer_t *m1m2) { libspdm_context_t *spdm_context; libspdm_return_t status; spdm_context = context; - libspdm_init_managed_buffer(m1m2, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + libspdm_init_managed_buffer(m1m2, sizeof(m1m2->buffer)); if (is_mut) { if ((spdm_context->connection_info.version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > @@ -470,6 +512,24 @@ bool libspdm_generate_cert_chain_hash(libspdm_context_t *spdm_context, spdm_context->local_context.local_cert_chain_provision_size[slot_id], hash); } +/** + * This function generates the public key hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param hash The buffer to store the public key hash. + * + * @retval true public key hash is generated. + * @retval false public key hash is not generated. + **/ +bool libspdm_generate_public_key_hash(libspdm_context_t *spdm_context, + uint8_t *hash) +{ + return libspdm_hash_all( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->local_context.local_public_key_provision, + spdm_context->local_context.local_public_key_provision_size, hash); +} + /** * Get the certificate slot mask * @@ -514,119 +574,85 @@ uint8_t libspdm_get_cert_slot_count(libspdm_context_t *spdm_context) return slot_count; } +#if LIBSPDM_CERT_PARSE_SUPPORT /** - * This function verifies the digest. + * This function verifies the integrity of peer certificate chain buffer including + * spdm_cert_chain_t header. * * @param spdm_context A pointer to the SPDM context. - * @param digest The digest data buffer. - * @param digest_count size of the digest data buffer. + * @param cert_chain_buffer Certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certificate chain buffer. * - * @retval true digest verification pass. - * @retval false digest verification fail. + * @retval true Peer certificate chain buffer integrity verification passed. + * @retval false Peer certificate chain buffer integrity verification failed. **/ -bool libspdm_verify_peer_digests(libspdm_context_t *spdm_context, const void *digest, - size_t digest_count) +bool libspdm_verify_peer_cert_chain_buffer_integrity(libspdm_context_t *spdm_context, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size) { - size_t hash_size; - const uint8_t *hash_buffer; - uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; - const uint8_t *cert_chain_buffer; - size_t cert_chain_buffer_size; - size_t index; bool result; + bool is_device_cert_model; + bool is_requester; - cert_chain_buffer = spdm_context->local_context.peer_cert_chain_provision; - cert_chain_buffer_size = spdm_context->local_context.peer_cert_chain_provision_size; - if ((cert_chain_buffer != NULL) && (cert_chain_buffer_size != 0)) { - hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); - hash_buffer = digest; - - result = libspdm_hash_all( - spdm_context->connection_info.algorithm.base_hash_algo, - cert_chain_buffer, cert_chain_buffer_size, - cert_chain_buffer_hash); - if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, - "!!! verify_peer_digests - FAIL (hash calculation) !!!\n")); - return false; - } + is_requester = spdm_context->local_context.is_requester; - for (index = 0; index < digest_count; index++) - { - if (libspdm_const_compare_mem(hash_buffer, cert_chain_buffer_hash, hash_size) == 0) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - PASS !!!\n")); - return true; - } - hash_buffer += hash_size; + is_device_cert_model = false; + /* Responder does not determine Requester's certificate model */ + if (is_requester) { + if((spdm_context->connection_info.capability.flags & + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ALIAS_CERT_CAP) == 0) { + is_device_cert_model = true; } + } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - FAIL !!!\n")); - return false; + if (is_requester) { + result = libspdm_verify_certificate_chain_buffer( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.base_asym_algo, + cert_chain_buffer, cert_chain_buffer_size, + false, is_device_cert_model); } else { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_digests - PASS !!!\n")); + result = libspdm_verify_certificate_chain_buffer( + spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->connection_info.algorithm.req_base_asym_alg, + cert_chain_buffer, cert_chain_buffer_size, + true, is_device_cert_model); } - return true; + + return result; } /** - * This function verifies peer certificate chain buffer including spdm_cert_chain_t header. + * This function verifies peer certificate chain authority. * * @param spdm_context A pointer to the SPDM context. - * @param cert_chain_buffer Certitiface chain buffer including spdm_cert_chain_t header. - * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param cert_chain_buffer Certificate chain buffer including spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certificate chain buffer. * @param trust_anchor A buffer to hold the trust_anchor which is used to validate the peer certificate, if not NULL. * @param trust_anchor_size A buffer to hold the trust_anchor_size, if not NULL. - * @param is_requester Indicates if it is a requester message. * - * @retval true Peer certificate chain buffer verification passed. - * @retval false Peer certificate chain buffer verification failed. + * @retval true Peer certificate chain buffer authority verification passed. + * Or there is no root_cert in local_context. + * @retval false Peer certificate chain buffer authority verification failed. **/ -bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, - const void *cert_chain_buffer, - size_t cert_chain_buffer_size, - const void **trust_anchor, - size_t *trust_anchor_size, - bool is_requester) +bool libspdm_verify_peer_cert_chain_buffer_authority(libspdm_context_t *spdm_context, + const void *cert_chain_buffer, + size_t cert_chain_buffer_size, + const void **trust_anchor, + size_t *trust_anchor_size) { - const uint8_t *cert_chain_data; - size_t cert_chain_data_size; const uint8_t *root_cert; size_t root_cert_size; - uint8_t root_cert_hash[LIBSPDM_MAX_HASH_SIZE]; + uint8_t root_cert_index; size_t root_cert_hash_size; + uint8_t root_cert_hash[LIBSPDM_MAX_HASH_SIZE]; const uint8_t *received_root_cert; size_t received_root_cert_size; bool result; - uint8_t root_cert_index; - bool is_device_cert_model; - - if((spdm_context->connection_info.capability.flags & - SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ALIAS_CERT_CAP) == 0) { - is_device_cert_model = true; - } else { - is_device_cert_model = false; - } - - if (is_requester) { - result = libspdm_verify_certificate_chain_buffer( - spdm_context->connection_info.algorithm.base_hash_algo, - spdm_context->connection_info.algorithm.base_asym_algo, - cert_chain_buffer, cert_chain_buffer_size, is_device_cert_model); - } else { - result = libspdm_verify_certificate_chain_buffer( - spdm_context->connection_info.algorithm.base_hash_algo, - spdm_context->connection_info.algorithm.req_base_asym_alg, - cert_chain_buffer, cert_chain_buffer_size, is_device_cert_model); - } - if (!result) { - return false; - } root_cert_index = 0; root_cert = spdm_context->local_context.peer_root_cert_provision[root_cert_index]; root_cert_size = spdm_context->local_context.peer_root_cert_provision_size[root_cert_index]; - cert_chain_data = spdm_context->local_context.peer_cert_chain_provision; - cert_chain_data_size = spdm_context->local_context.peer_cert_chain_provision_size; root_cert_hash_size = libspdm_get_hash_size( spdm_context->connection_info.algorithm.base_hash_algo); @@ -637,14 +663,14 @@ bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, spdm_context->connection_info.algorithm.base_hash_algo, root_cert, root_cert_size, root_cert_hash); if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_peer_cert_chain_buffer - FAIL (hash calculation) !!!\n")); return false; } - if (libspdm_const_compare_mem((const uint8_t *)cert_chain_buffer + - sizeof(spdm_cert_chain_t), - root_cert_hash, root_cert_hash_size) == 0) { + if (libspdm_consttime_is_mem_equal((const uint8_t *)cert_chain_buffer + + sizeof(spdm_cert_chain_t), + root_cert_hash, root_cert_hash_size)) { break; } @@ -659,7 +685,7 @@ bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, } else #endif /* LIBSPDM_MAX_ROOT_CERT_SUPPORT */ { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_peer_cert_chain_buffer - " "FAIL (all root cert hash mismatch) !!!\n")); return false; @@ -671,14 +697,14 @@ bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, cert_chain_buffer_size - sizeof(spdm_cert_chain_t) - root_cert_hash_size, 0, &received_root_cert, &received_root_cert_size); if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_peer_cert_chain_buffer - FAIL (cert retrieval fail) !!!\n")); return false; } if (libspdm_is_root_certificate(received_root_cert, received_root_cert_size)) { if ((root_cert != NULL) && - (libspdm_const_compare_mem(received_root_cert, root_cert, root_cert_size) != 0)) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + !libspdm_consttime_is_mem_equal(received_root_cert, root_cert, root_cert_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_peer_cert_chain_buffer - " "FAIL (root cert mismatch) !!!\n")); return false; @@ -686,7 +712,7 @@ bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, } else { if (!libspdm_x509_verify_cert(received_root_cert, received_root_cert_size, root_cert, root_cert_size)) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_peer_cert_chain_buffer - " "FAIL (received root cert verify failed)!!!\n")); return false; @@ -698,35 +724,16 @@ bool libspdm_verify_peer_cert_chain_buffer(libspdm_context_t *spdm_context, if (trust_anchor_size != NULL) { *trust_anchor_size = root_cert_size; } - } else if ((cert_chain_data != NULL) && (cert_chain_data_size != 0)) { - /* Whether it contains the root certificate or not, - * it should be equal to the one provisioned in trusted environment*/ - if (cert_chain_data_size != cert_chain_buffer_size) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - FAIL !!!\n")); - return false; - } - if (libspdm_const_compare_mem(cert_chain_buffer, cert_chain_data, - cert_chain_buffer_size) != 0) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - FAIL !!!\n")); - return false; - } - if (trust_anchor != NULL) { - *trust_anchor = cert_chain_data + sizeof(spdm_cert_chain_t) + - libspdm_get_hash_size( - spdm_context->connection_info.algorithm.base_hash_algo); - } - if (trust_anchor_size != NULL) { - *trust_anchor_size = cert_chain_data_size; - } } /* - * When there is no root_cert and cert_chain_data in local_context, the return is true too. - * No provision means the caller wants to verify the trust anchor of the cert chain. + * When there is no root_cert in local_context, the return is true too. + * No root_cert means the caller wants to verify the trust anchor of the cert chain. */ LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_peer_cert_chain_buffer - PASS !!!\n")); return true; } +#endif /** * This function generates the challenge signature based upon m1m2 for authentication. @@ -745,7 +752,7 @@ bool libspdm_generate_challenge_auth_signature(libspdm_context_t *spdm_context, bool result; size_t signature_size; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - libspdm_large_managed_buffer_t m1m2; + libspdm_m1m2_managed_buffer_t m1m2; uint8_t *m1m2_buffer; size_t m1m2_buffer_size; #else @@ -829,12 +836,13 @@ bool libspdm_verify_certificate_chain_hash(libspdm_context_t *spdm_context, const void *certificate_chain_hash, size_t certificate_chain_hash_size) { +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT size_t hash_size; uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; const uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; bool result; -#if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) +#else uint8_t slot_id; #endif @@ -852,71 +860,88 @@ bool libspdm_verify_certificate_chain_hash(libspdm_context_t *spdm_context, cert_chain_buffer, cert_chain_buffer_size, cert_chain_buffer_hash); if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_certificate_chain_hash - FAIL (hash calculation) !!!\n")); return false; } if (hash_size != certificate_chain_hash_size) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_certificate_chain_hash - FAIL !!!\n")); return false; } - if (libspdm_const_compare_mem(certificate_chain_hash, cert_chain_buffer_hash, - certificate_chain_hash_size) != 0) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + if (!libspdm_consttime_is_mem_equal(certificate_chain_hash, cert_chain_buffer_hash, + certificate_chain_hash_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_certificate_chain_hash - FAIL !!!\n")); return false; } #else slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); - if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size != 0) { - if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size != - certificate_chain_hash_size) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); - return false; - } - - if (libspdm_const_compare_mem(certificate_chain_hash, - spdm_context->connection_info.peer_used_cert_chain[slot_id]. - buffer_hash, certificate_chain_hash_size) != 0) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); - return false; - } - - } else { - result = libspdm_get_peer_cert_chain_buffer(spdm_context, - (const void **)&cert_chain_buffer, - &cert_chain_buffer_size); - if (!result) { - return false; - } - hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + LIBSPDM_ASSERT( + spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size != 0); - result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, - cert_chain_buffer, cert_chain_buffer_size, - cert_chain_buffer_hash); - if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, - "!!! verify_certificate_chain_hash - FAIL (hash calculation) !!!\n")); - return false; - } + if (spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash_size != + certificate_chain_hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; + } - if (hash_size != certificate_chain_hash_size) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); - return false; - } - if (libspdm_const_compare_mem(certificate_chain_hash, cert_chain_buffer_hash, - certificate_chain_hash_size) != 0) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - FAIL !!!\n")); - return false; - } + if (!libspdm_consttime_is_mem_equal(certificate_chain_hash, + spdm_context->connection_info.peer_used_cert_chain[slot_id]. + buffer_hash, certificate_chain_hash_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_certificate_chain_hash - FAIL !!!\n")); + return false; } #endif LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_certificate_chain_hash - PASS !!!\n")); return true; } +/** + * This function verifies the public key hash. + * + * @param spdm_context A pointer to the SPDM context. + * @param public_key_hash The public key hash data buffer. + * @param public_key_hash_size size in bytes of the public key hash data buffer. + * + * @retval true hash verification pass. + * @retval false hash verification fail. + **/ +bool libspdm_verify_public_key_hash(libspdm_context_t *spdm_context, + const void *public_key_hash, + size_t public_key_hash_size) +{ + size_t hash_size; + uint8_t public_key_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; + bool result; + + hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); + + result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, + spdm_context->local_context.peer_public_key_provision, + spdm_context->local_context.peer_public_key_provision_size, + public_key_buffer_hash); + if (!result) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "!!! verify_public_key_hash - FAIL (hash calculation) !!!\n")); + return false; + } + + if (hash_size != public_key_hash_size) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_public_key_hash - FAIL !!!\n")); + return false; + } + if (!libspdm_consttime_is_mem_equal(public_key_hash, public_key_buffer_hash, + public_key_hash_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_public_key_hash - FAIL !!!\n")); + return false; + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_public_key_hash - PASS !!!\n")); + return true; +} + /** * This function verifies the challenge signature based upon m1m2. * @@ -934,23 +959,25 @@ bool libspdm_verify_challenge_auth_signature(libspdm_context_t *spdm_context, size_t sign_data_size) { bool result; - const uint8_t *cert_buffer; - size_t cert_buffer_size; void *context; - const uint8_t *cert_chain_data; - size_t cert_chain_data_size; + uint8_t slot_id; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - libspdm_large_managed_buffer_t m1m2; + libspdm_m1m2_managed_buffer_t m1m2; uint8_t *m1m2_buffer; size_t m1m2_buffer_size; + const uint8_t *cert_buffer; + size_t cert_buffer_size; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; #else uint8_t m1m2_hash[LIBSPDM_MAX_HASH_SIZE]; size_t m1m2_hash_size; - uint8_t slot_id; #endif #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT result = libspdm_calculate_m1m2(spdm_context, !is_requester, &m1m2); + m1m2_buffer = libspdm_get_managed_buffer(&m1m2); + m1m2_buffer_size = libspdm_get_managed_buffer_size(&m1m2); #else m1m2_hash_size = sizeof(m1m2_hash); result = libspdm_calculate_m1m2_hash(spdm_context, !is_requester, &m1m2_hash_size, &m1m2_hash); @@ -966,141 +993,106 @@ bool libspdm_verify_challenge_auth_signature(libspdm_context_t *spdm_context, return false; } -#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - result = libspdm_get_peer_cert_chain_data( - spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); - if (!result) { - return false; - } - - /* Get leaf cert from cert chain*/ - result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, - cert_chain_data_size, -1, - &cert_buffer, &cert_buffer_size); - if (!result) { - return false; - } - - m1m2_buffer = libspdm_get_managed_buffer(&m1m2); - m1m2_buffer_size = libspdm_get_managed_buffer_size(&m1m2); + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); - if (is_requester) { - result = libspdm_asym_get_public_key_from_x509( - spdm_context->connection_info.algorithm.base_asym_algo, - cert_buffer, cert_buffer_size, &context); + if (slot_id == 0xFF) { + if (is_requester) { + result = libspdm_asym_get_public_key_from_der( + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->local_context.peer_public_key_provision, + spdm_context->local_context.peer_public_key_provision_size, + &context); + } else { + result = libspdm_req_asym_get_public_key_from_der( + spdm_context->connection_info.algorithm.req_base_asym_alg, + spdm_context->local_context.peer_public_key_provision, + spdm_context->local_context.peer_public_key_provision_size, + &context); + } if (!result) { return false; } - - result = libspdm_asym_verify( - spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, - spdm_context->connection_info.algorithm.base_asym_algo, - spdm_context->connection_info.algorithm.base_hash_algo, - context, m1m2_buffer, m1m2_buffer_size, sign_data, sign_data_size); - libspdm_asym_free( - spdm_context->connection_info.algorithm.base_asym_algo, context); } else { - result = libspdm_req_asym_get_public_key_from_x509( - spdm_context->connection_info.algorithm.req_base_asym_alg, - cert_buffer, cert_buffer_size, &context); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); if (!result) { return false; } - result = libspdm_req_asym_verify( - spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, - spdm_context->connection_info.algorithm.req_base_asym_alg, - spdm_context->connection_info.algorithm.base_hash_algo, - context, m1m2_buffer, m1m2_buffer_size, sign_data, sign_data_size); - libspdm_req_asym_free(spdm_context->connection_info.algorithm.req_base_asym_alg, context); - } -#else - slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; - LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); - if (is_requester) { - if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != - NULL) { - context = - spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; - result = libspdm_asym_verify_hash( - spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, - spdm_context->connection_info.algorithm.base_asym_algo, - spdm_context->connection_info.algorithm.base_hash_algo, - context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); - if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_challenge_signature - FAIL !!!\n")); - return false; - } - return true; + /* Get leaf cert from cert chain*/ + result = libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, -1, &cert_buffer, &cert_buffer_size); + if (!result) { + return false; } - } else { - if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != - NULL) { - context = - spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; - result = libspdm_req_asym_verify_hash( - spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + if (is_requester) { + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + } else { + result = libspdm_req_asym_get_public_key_from_x509( spdm_context->connection_info.algorithm.req_base_asym_alg, - spdm_context->connection_info.algorithm.base_hash_algo, - context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); - if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_challenge_signature - FAIL !!!\n")); - return false; - } - return true; + cert_buffer, cert_buffer_size, &context); } - } - - result = libspdm_get_peer_cert_chain_data( - spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); - if (!result) { - return false; - } - - - /* Get leaf cert from cert chain*/ - - result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, - cert_chain_data_size, -1, - &cert_buffer, &cert_buffer_size); - if (!result) { - return false; - } - - if (is_requester) { - result = libspdm_asym_get_public_key_from_x509( - spdm_context->connection_info.algorithm.base_asym_algo, - cert_buffer, cert_buffer_size, &context); if (!result) { return false; } +#else + context = spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; + LIBSPDM_ASSERT(context != NULL); +#endif + } - result = libspdm_asym_verify_hash( + if (is_requester) { +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_asym_verify_ex( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_buffer, m1m2_buffer_size, sign_data, sign_data_size, + &spdm_context->spdm_10_11_verify_signature_endian); + libspdm_asym_free( + spdm_context->connection_info.algorithm.base_asym_algo, context); +#else + result = libspdm_asym_verify_hash_ex( spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, spdm_context->connection_info.algorithm.base_asym_algo, spdm_context->connection_info.algorithm.base_hash_algo, - context, m1m2_hash, m1m2_hash_size, sign_data, - sign_data_size); - libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); + context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size, + &spdm_context->spdm_10_11_verify_signature_endian); + if (slot_id == 0xFF) { + libspdm_asym_free( + spdm_context->connection_info.algorithm.base_asym_algo, context); + } +#endif } else { - result = libspdm_req_asym_get_public_key_from_x509( +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_req_asym_verify_ex( + spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, spdm_context->connection_info.algorithm.req_base_asym_alg, - cert_buffer, cert_buffer_size, &context); - if (!result) { - return false; - } - - result = libspdm_req_asym_verify_hash( + spdm_context->connection_info.algorithm.base_hash_algo, + context, m1m2_buffer, m1m2_buffer_size, sign_data, sign_data_size, + &spdm_context->spdm_10_11_verify_signature_endian); + libspdm_req_asym_free( + spdm_context->connection_info.algorithm.req_base_asym_alg, context); +#else + result = libspdm_req_asym_verify_hash_ex( spdm_context->connection_info.version, SPDM_CHALLENGE_AUTH, spdm_context->connection_info.algorithm.req_base_asym_alg, spdm_context->connection_info.algorithm.base_hash_algo, - context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size); - libspdm_req_asym_free(spdm_context->connection_info.algorithm.req_base_asym_alg, context); - } + context, m1m2_hash, m1m2_hash_size, sign_data, sign_data_size, + &spdm_context->spdm_10_11_verify_signature_endian); + if (slot_id == 0xFF) { + libspdm_req_asym_free( + spdm_context->connection_info.algorithm.req_base_asym_alg, context); + } #endif + } if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_challenge_signature - FAIL !!!\n")); return false; } @@ -1132,12 +1124,12 @@ libspdm_get_measurement_summary_hash_size(libspdm_context_t *spdm_context, } switch (measurement_summary_hash_type) { - case SPDM_CHALLENGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH: + case SPDM_REQUEST_NO_MEASUREMENT_SUMMARY_HASH: return 0; break; - case SPDM_CHALLENGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH: - case SPDM_CHALLENGE_REQUEST_ALL_MEASUREMENTS_HASH: + case SPDM_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH: + case SPDM_REQUEST_ALL_MEASUREMENTS_HASH: return libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); break; default: diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c similarity index 80% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c index 3d3fceaaf8..363f649f90 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c @@ -4,7 +4,7 @@ * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md **/ -#include "internal/libspdm_common_lib.h" +#include "internal/libspdm_secured_message_lib.h" #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT /* @@ -12,41 +12,36 @@ * * @param spdm_context A pointer to the SPDM context. * @param session_info The SPDM session ID. - * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. - * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. + * @param cert_chain_buffer Certificate chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certificate chain buffer. * @param th_data_buffer_size size in bytes of the th_data_buffer * @param th_data_buffer The buffer to store the th_data_buffer * * @retval RETURN_SUCCESS current TH data is calculated. */ bool libspdm_calculate_th_for_exchange( - void *context, void *spdm_session_info, const uint8_t *cert_chain_buffer, + libspdm_context_t *spdm_context, void *spdm_session_info, const uint8_t *cert_chain_buffer, size_t cert_chain_buffer_size, - size_t *th_data_buffer_size, void *th_data_buffer) + libspdm_th_managed_buffer_t *th_curr) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; uint32_t hash_size; libspdm_return_t status; - libspdm_large_managed_buffer_t th_curr; bool result; - size_t th_data_buffer_capacity; - spdm_context = context; session_info = spdm_session_info; hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); - LIBSPDM_ASSERT(*th_data_buffer_size >= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); - libspdm_init_managed_buffer(&th_curr, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + libspdm_init_managed_buffer(th_curr, sizeof(th_curr->buffer)); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); LIBSPDM_INTERNAL_DUMP_HEX( libspdm_get_managed_buffer(&spdm_context->transcript.message_a), libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); status = libspdm_append_managed_buffer( - &th_curr, + th_curr, libspdm_get_managed_buffer(&spdm_context->transcript.message_a), libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); if (LIBSPDM_STATUS_IS_ERROR(status)) { @@ -63,7 +58,7 @@ bool libspdm_calculate_th_for_exchange( if (!result) { return false; } - status = libspdm_append_managed_buffer(&th_curr, cert_chain_buffer_hash, hash_size); + status = libspdm_append_managed_buffer(th_curr, cert_chain_buffer_hash, hash_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { return false; } @@ -74,18 +69,13 @@ bool libspdm_calculate_th_for_exchange( libspdm_get_managed_buffer(&session_info->session_transcript.message_k), libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); status = libspdm_append_managed_buffer( - &th_curr, + th_curr, libspdm_get_managed_buffer(&session_info->session_transcript.message_k), libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); if (LIBSPDM_STATUS_IS_ERROR(status)) { return false; } - th_data_buffer_capacity = *th_data_buffer_size; - *th_data_buffer_size = libspdm_get_managed_buffer_size(&th_curr); - libspdm_copy_mem(th_data_buffer, th_data_buffer_capacity, - libspdm_get_managed_buffer(&th_curr), *th_data_buffer_size); - return true; } #else @@ -100,16 +90,14 @@ bool libspdm_calculate_th_for_exchange( * @retval RETURN_SUCCESS current TH hash is calculated. */ bool libspdm_calculate_th_hash_for_exchange( - void *context, void *spdm_session_info, + libspdm_context_t *spdm_context, void *spdm_session_info, size_t *th_hash_buffer_size, void *th_hash_buffer) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; uint32_t hash_size; void *digest_context_th; bool result; - spdm_context = context; session_info = spdm_session_info; hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); @@ -152,10 +140,9 @@ bool libspdm_calculate_th_hash_for_exchange( * @retval RETURN_SUCCESS current TH hmac is calculated. */ bool libspdm_calculate_th_hmac_for_exchange_rsp( - void *context, void *spdm_session_info, bool is_requester, + libspdm_context_t *spdm_context, void *spdm_session_info, bool is_requester, size_t *th_hmac_buffer_size, void *th_hmac_buffer) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; void *secured_message_context; uint32_t hash_size; @@ -163,7 +150,6 @@ bool libspdm_calculate_th_hmac_for_exchange_rsp( uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; bool result; - spdm_context = context; session_info = spdm_session_info; secured_message_context = session_info->secured_message_context; @@ -207,48 +193,42 @@ bool libspdm_calculate_th_hmac_for_exchange_rsp( * * @param spdm_context A pointer to the SPDM context. * @param session_info The SPDM session ID. - * @param cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header. - * @param cert_chain_buffer_size size in bytes of the certitiface chain buffer. - * @param mut_cert_chain_buffer Certitiface chain buffer with spdm_cert_chain_t header in mutual authentication. - * @param mut_cert_chain_buffer_size size in bytes of the certitiface chain buffer in mutual authentication. + * @param cert_chain_buffer Certificate chain buffer with spdm_cert_chain_t header. + * @param cert_chain_buffer_size size in bytes of the certificate chain buffer. + * @param mut_cert_chain_buffer Certificate chain buffer with spdm_cert_chain_t header in mutual authentication. + * @param mut_cert_chain_buffer_size size in bytes of the certificate chain buffer in mutual authentication. * @param th_data_buffer_size size in bytes of the th_data_buffer * @param th_data_buffer The buffer to store the th_data_buffer * * @retval RETURN_SUCCESS current TH data is calculated. */ -bool libspdm_calculate_th_for_finish(void *context, +bool libspdm_calculate_th_for_finish(libspdm_context_t *spdm_context, void *spdm_session_info, const uint8_t *cert_chain_buffer, size_t cert_chain_buffer_size, const uint8_t *mut_cert_chain_buffer, size_t mut_cert_chain_buffer_size, - size_t *th_data_buffer_size, - void *th_data_buffer) + libspdm_th_managed_buffer_t *th_curr) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; uint8_t cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; uint8_t mut_cert_chain_buffer_hash[LIBSPDM_MAX_HASH_SIZE]; uint32_t hash_size; libspdm_return_t status; - libspdm_large_managed_buffer_t th_curr; bool result; - size_t th_data_buffer_capacity; - spdm_context = context; session_info = spdm_session_info; hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); - LIBSPDM_ASSERT(*th_data_buffer_size >= LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); - libspdm_init_managed_buffer(&th_curr, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); + libspdm_init_managed_buffer(th_curr, sizeof(th_curr->buffer)); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "message_a data :\n")); LIBSPDM_INTERNAL_DUMP_HEX( libspdm_get_managed_buffer(&spdm_context->transcript.message_a), libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); status = libspdm_append_managed_buffer( - &th_curr, + th_curr, libspdm_get_managed_buffer(&spdm_context->transcript.message_a), libspdm_get_managed_buffer_size(&spdm_context->transcript.message_a)); if (LIBSPDM_STATUS_IS_ERROR(status)) { @@ -265,7 +245,7 @@ bool libspdm_calculate_th_for_finish(void *context, if (!result) { return false; } - status = libspdm_append_managed_buffer(&th_curr, cert_chain_buffer_hash, hash_size); + status = libspdm_append_managed_buffer(th_curr, cert_chain_buffer_hash, hash_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { return false; } @@ -276,7 +256,7 @@ bool libspdm_calculate_th_for_finish(void *context, libspdm_get_managed_buffer(&session_info->session_transcript.message_k), libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); status = libspdm_append_managed_buffer( - &th_curr, + th_curr, libspdm_get_managed_buffer(&session_info->session_transcript.message_k), libspdm_get_managed_buffer_size(&session_info->session_transcript.message_k)); if (LIBSPDM_STATUS_IS_ERROR(status)) { @@ -293,7 +273,7 @@ bool libspdm_calculate_th_for_finish(void *context, if (!result) { return false; } - status = libspdm_append_managed_buffer(&th_curr, mut_cert_chain_buffer_hash, hash_size); + status = libspdm_append_managed_buffer(th_curr, mut_cert_chain_buffer_hash, hash_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { return false; } @@ -304,18 +284,13 @@ bool libspdm_calculate_th_for_finish(void *context, libspdm_get_managed_buffer(&session_info->session_transcript.message_f), libspdm_get_managed_buffer_size(&session_info->session_transcript.message_f)); status = libspdm_append_managed_buffer( - &th_curr, + th_curr, libspdm_get_managed_buffer(&session_info->session_transcript.message_f), libspdm_get_managed_buffer_size(&session_info->session_transcript.message_f)); if (LIBSPDM_STATUS_IS_ERROR(status)) { return false; } - th_data_buffer_capacity = *th_data_buffer_size; - *th_data_buffer_size = libspdm_get_managed_buffer_size(&th_curr); - libspdm_copy_mem(th_data_buffer, th_data_buffer_capacity, - libspdm_get_managed_buffer(&th_curr), *th_data_buffer_size); - return true; } #else @@ -329,18 +304,16 @@ bool libspdm_calculate_th_for_finish(void *context, * * @retval RETURN_SUCCESS current TH hash is calculated. */ -bool libspdm_calculate_th_hash_for_finish(void *context, +bool libspdm_calculate_th_hash_for_finish(libspdm_context_t *spdm_context, void *spdm_session_info, size_t *th_hash_buffer_size, void *th_hash_buffer) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; uint32_t hash_size; void *digest_context_th; bool result; - spdm_context = context; session_info = spdm_session_info; hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); @@ -382,12 +355,11 @@ bool libspdm_calculate_th_hash_for_finish(void *context, * * @retval RETURN_SUCCESS current TH hmac is calculated. */ -bool libspdm_calculate_th_hmac_for_finish_rsp(void *context, +bool libspdm_calculate_th_hmac_for_finish_rsp(libspdm_context_t *spdm_context, void *spdm_session_info, size_t *th_hmac_buffer_size, void *th_hmac_buffer) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; void *secured_message_context; uint32_t hash_size; @@ -395,7 +367,6 @@ bool libspdm_calculate_th_hmac_for_finish_rsp(void *context, uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; bool result; - spdm_context = context; session_info = spdm_session_info; secured_message_context = session_info->secured_message_context; @@ -443,12 +414,11 @@ bool libspdm_calculate_th_hmac_for_finish_rsp(void *context, * * @retval RETURN_SUCCESS current TH hmac is calculated. */ -bool libspdm_calculate_th_hmac_for_finish_req(void *context, +bool libspdm_calculate_th_hmac_for_finish_req(libspdm_context_t *spdm_context, void *spdm_session_info, size_t *th_hmac_buffer_size, void *th_hmac_buffer) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; void *secured_message_context; uint32_t hash_size; @@ -456,7 +426,6 @@ bool libspdm_calculate_th_hmac_for_finish_req(void *context, uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; bool result; - spdm_context = context; session_info = spdm_session_info; secured_message_context = session_info->secured_message_context; @@ -505,24 +474,24 @@ bool libspdm_calculate_th_hmac_for_finish_req(void *context, * * @retval RETURN_SUCCESS th1 hash is calculated. */ -bool libspdm_calculate_th1_hash(void *context, +bool libspdm_calculate_th1_hash(libspdm_context_t *spdm_context, void *spdm_session_info, bool is_requester, uint8_t *th1_hash_data) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; bool result; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t slot_id; uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; - uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + uint8_t *th_curr_data; size_t th_curr_data_size; + libspdm_th_managed_buffer_t th_curr; #endif #if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) size_t hash_size; #endif - spdm_context = context; LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Calc th1 hash ...\n")); @@ -534,13 +503,29 @@ bool libspdm_calculate_th1_hash(void *context, #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT if (!session_info->use_psk) { if (is_requester) { - result = libspdm_get_peer_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, - &cert_chain_buffer_size); + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } } else { - result = libspdm_get_local_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, - &cert_chain_buffer_size); + slot_id = spdm_context->connection_info.local_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_local_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } } if (!result) { return false; @@ -550,13 +535,14 @@ bool libspdm_calculate_th1_hash(void *context, cert_chain_buffer_size = 0; } - th_curr_data_size = sizeof(th_curr_data); result = libspdm_calculate_th_for_exchange( spdm_context, session_info, cert_chain_buffer, - cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + cert_chain_buffer_size, &th_curr); if (!result) { return false; } + th_curr_data = libspdm_get_managed_buffer(&th_curr); + th_curr_data_size = libspdm_get_managed_buffer_size(&th_curr); result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, th_curr_data, th_curr_data_size, th1_hash_data); @@ -587,28 +573,27 @@ bool libspdm_calculate_th1_hash(void *context, * * @retval RETURN_SUCCESS th2 hash is calculated. */ -bool libspdm_calculate_th2_hash(void *context, +bool libspdm_calculate_th2_hash(libspdm_context_t *spdm_context, void *spdm_session_info, bool is_requester, uint8_t *th2_hash_data) { - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; bool result; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t slot_id; uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; uint8_t *mut_cert_chain_buffer; size_t mut_cert_chain_buffer_size; - uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + uint8_t *th_curr_data; size_t th_curr_data_size; + libspdm_th_managed_buffer_t th_curr; #endif #if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) size_t hash_size; #endif - spdm_context = context; - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Calc th2 hash ...\n")); session_info = spdm_session_info; @@ -620,28 +605,58 @@ bool libspdm_calculate_th2_hash(void *context, #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT if (!session_info->use_psk) { if (is_requester) { - result = libspdm_get_peer_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, - &cert_chain_buffer_size); + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } } else { - result = libspdm_get_local_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, - &cert_chain_buffer_size); + slot_id = spdm_context->connection_info.local_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_local_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, + &cert_chain_buffer_size); + } } if (!result) { return false; } if (session_info->mut_auth_requested) { if (is_requester) { - result = libspdm_get_local_cert_chain_buffer( - spdm_context, - (const void **)&mut_cert_chain_buffer, - &mut_cert_chain_buffer_size); + slot_id = spdm_context->connection_info.local_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_local_public_key_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } } else { - result = libspdm_get_peer_cert_chain_buffer( - spdm_context, - (const void **)&mut_cert_chain_buffer, - &mut_cert_chain_buffer_size); + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, + &mut_cert_chain_buffer_size); + } } if (!result) { return false; @@ -657,14 +672,15 @@ bool libspdm_calculate_th2_hash(void *context, mut_cert_chain_buffer_size = 0; } - th_curr_data_size = sizeof(th_curr_data); result = libspdm_calculate_th_for_finish( spdm_context, session_info, cert_chain_buffer, cert_chain_buffer_size, mut_cert_chain_buffer, - mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + mut_cert_chain_buffer_size, &th_curr); if (!result) { return false; } + th_curr_data = libspdm_get_managed_buffer(&th_curr); + th_curr_data_size = libspdm_get_managed_buffer_size(&th_curr); result = libspdm_hash_all(spdm_context->connection_info.algorithm.base_hash_algo, th_curr_data, th_curr_data_size, th2_hash_data); diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_msg_log.c similarity index 55% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_msg_log.c index 5dca6f1311..01119f505e 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_msg_log.c @@ -7,73 +7,69 @@ #include "internal/libspdm_common_lib.h" #if LIBSPDM_ENABLE_MSG_LOG -void libspdm_init_msg_log (void *context, void *msg_buffer, size_t msg_buffer_size) +void libspdm_init_msg_log (void *spdm_context, void *msg_buffer, size_t msg_buffer_size) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - LIBSPDM_ASSERT((context != NULL) && (msg_buffer != NULL)); + LIBSPDM_ASSERT((spdm_context != NULL) && (msg_buffer != NULL)); LIBSPDM_ASSERT(msg_buffer_size != 0); - spdm_context = context; - spdm_context->msg_log.buffer = msg_buffer; - spdm_context->msg_log.max_buffer_size = msg_buffer_size; - spdm_context->msg_log.buffer_size = 0; - spdm_context->msg_log.mode = 0; - spdm_context->msg_log.status = 0; + context = spdm_context; + context->msg_log.buffer = msg_buffer; + context->msg_log.max_buffer_size = msg_buffer_size; + context->msg_log.buffer_size = 0; + context->msg_log.mode = 0; + context->msg_log.status = 0; } -void libspdm_set_msg_log_mode (void *context, uint32_t mode) +void libspdm_set_msg_log_mode (void *spdm_context, uint32_t mode) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - LIBSPDM_ASSERT(context != NULL); + LIBSPDM_ASSERT(spdm_context != NULL); - spdm_context = context; - spdm_context->msg_log.mode = mode; + context = spdm_context; + context->msg_log.mode = mode; } -uint32_t libspdm_get_msg_log_status (void *context) +uint32_t libspdm_get_msg_log_status (void *spdm_context) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - LIBSPDM_ASSERT(context != NULL); + LIBSPDM_ASSERT(spdm_context != NULL); - spdm_context = context; + context = spdm_context; - return spdm_context->msg_log.status; + return context->msg_log.status; } -size_t libspdm_get_msg_log_size (void *context) +size_t libspdm_get_msg_log_size (void *spdm_context) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - LIBSPDM_ASSERT(context != NULL); + LIBSPDM_ASSERT(spdm_context != NULL); - spdm_context = context; + context = spdm_context; - return spdm_context->msg_log.buffer_size; + return context->msg_log.buffer_size; } -void libspdm_reset_msg_log (void *context) +void libspdm_reset_msg_log (void *spdm_context) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; - LIBSPDM_ASSERT(context != NULL); + LIBSPDM_ASSERT(spdm_context != NULL); - spdm_context = context; + context = spdm_context; - spdm_context->msg_log.buffer_size = 0; - spdm_context->msg_log.mode = 0; - spdm_context->msg_log.status = 0; + context->msg_log.buffer_size = 0; + context->msg_log.mode = 0; + context->msg_log.status = 0; } -void libspdm_append_msg_log(void *context, void *message, size_t message_size) +void libspdm_append_msg_log(libspdm_context_t *spdm_context, void *message, size_t message_size) { - libspdm_context_t *spdm_context; - - LIBSPDM_ASSERT((context != NULL) && (message != NULL)); - - spdm_context = context; + LIBSPDM_ASSERT((spdm_context != NULL) && (message != NULL)); if (((spdm_context->msg_log.mode & LIBSPDM_MSG_LOG_MODE_ENABLE) != 0) && ((spdm_context->msg_log.status & LIBSPDM_MSG_LOG_STATUS_BUFFER_FULL) == 0)) { diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_opaque_data.c similarity index 68% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_opaque_data.c index a43e01575d..76739e596a 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_opaque_data.c @@ -135,7 +135,7 @@ bool libspdm_get_element_from_opaque_data(libspdm_context_t *spdm_context, result = false; /*check parameter in*/ - if (element_id > SPDM_REGISTRY_ID_JEDEC) { + if (element_id > SPDM_REGISTRY_ID_MAX) { return false; } if ((data_in_size == 0) || (data_in == NULL)) { @@ -183,7 +183,7 @@ bool libspdm_get_element_from_opaque_data(libspdm_context_t *spdm_context, } /*check element header id*/ - if ((opaque_element_table_header->id > SPDM_REGISTRY_ID_JEDEC) || + if ((opaque_element_table_header->id > SPDM_REGISTRY_ID_MAX) || (opaque_element_table_header->vendor_len != 0)) { return false; } @@ -230,3 +230,104 @@ bool libspdm_get_element_from_opaque_data(libspdm_context_t *spdm_context, return result; } + +/** + * Process general opaque data check + * + * @param data_in_size size in bytes of the data_in. + * @param data_in A pointer to the buffer to store the opaque data version selection. + * + * @retval true check opaque data successfully + * @retval false check opaque data failed + **/ +bool libspdm_process_general_opaque_data_check(libspdm_context_t *spdm_context, + size_t data_in_size, + const void *data_in) +{ + const spdm_general_opaque_data_table_header_t + *spdm_general_opaque_data_table_header; + const opaque_element_table_header_t + *opaque_element_table_header; + uint8_t element_num; + uint8_t element_index; + uint16_t opaque_element_data_len; + size_t data_element_size; + size_t current_element_len; + size_t total_element_len; + uint8_t zero_padding[4] = {0}; + + total_element_len = 0; + + LIBSPDM_ASSERT(data_in_size <= SPDM_MAX_OPAQUE_DATA_SIZE); + + if (libspdm_get_connection_version(spdm_context) >= SPDM_MESSAGE_VERSION_12) { + if (spdm_context->connection_info.algorithm.other_params_support == + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_1) { + /* Check byte alignment */ + if ((data_in_size & 3) != 0) { + return false; + } + + spdm_general_opaque_data_table_header = data_in; + if (data_in_size < sizeof(spdm_general_opaque_data_table_header_t)) { + return false; + } + if (spdm_general_opaque_data_table_header->total_elements < 1) { + return false; + } + opaque_element_table_header = (const void *)(spdm_general_opaque_data_table_header + 1); + + element_num = spdm_general_opaque_data_table_header->total_elements; + + data_element_size = data_in_size - sizeof(spdm_general_opaque_data_table_header_t); + + for (element_index = 0; element_index < element_num; element_index++) { + /*ensure the opaque_element_table_header is valid*/ + if (total_element_len + sizeof(opaque_element_table_header_t) + + sizeof(opaque_element_data_len) > + data_element_size) { + return false; + } + + /*check element header id*/ + if (opaque_element_table_header->id > SPDM_REGISTRY_ID_MAX) { + return false; + } + + opaque_element_data_len = *(uint16_t *)((size_t)(opaque_element_table_header + 1)) + + opaque_element_table_header->vendor_len; + + current_element_len = sizeof(opaque_element_table_header_t) + + opaque_element_table_header->vendor_len + + sizeof(opaque_element_data_len) + + opaque_element_data_len; + + if ((current_element_len & 3) != 0) { + if (!libspdm_consttime_is_mem_equal(zero_padding, + (uint8_t *)(size_t) + (opaque_element_table_header) + + current_element_len, + 4 - (current_element_len & 3))) { + return false; + } + } + /* Add Padding*/ + current_element_len = (current_element_len + 3) & ~3; + + total_element_len += current_element_len; + + if (total_element_len > data_element_size) { + return false; + } + + /*move to next element*/ + opaque_element_table_header = + (const opaque_element_table_header_t *) + ((const uint8_t *)opaque_element_table_header + + current_element_len); + } + } + } + + return true; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_support.c similarity index 64% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_support.c index b90dbaa62b..e59ceb72b1 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_support.c @@ -7,6 +7,79 @@ #include "internal/libspdm_common_lib.h" #if LIBSPDM_DEBUG_PRINT_ENABLE +typedef struct { + uint8_t code; + const char *code_str; +} libspdm_code_str_struct_t; + +const char *libspdm_get_code_str(uint8_t request_code) +{ + size_t index; + + static libspdm_code_str_struct_t code_str_struct[] = { + /* SPDM response code (1.0) */ + { SPDM_DIGESTS, "SPDM_DIGESTS" }, + { SPDM_CERTIFICATE, "SPDM_CERTIFICATE" }, + { SPDM_CHALLENGE_AUTH, "SPDM_CHALLENGE_AUTH" }, + { SPDM_VERSION, "SPDM_VERSION" }, + { SPDM_MEASUREMENTS, "SPDM_MEASUREMENTS" }, + { SPDM_CAPABILITIES, "SPDM_CAPABILITIES" }, + { SPDM_ALGORITHMS, "SPDM_ALGORITHMS" }, + { SPDM_VENDOR_DEFINED_RESPONSE, "SPDM_VENDOR_DEFINED_RESPONSE" }, + { SPDM_ERROR, "SPDM_ERROR" }, + /* SPDM response code (1.1) */ + { SPDM_KEY_EXCHANGE_RSP, "SPDM_KEY_EXCHANGE_RSP" }, + { SPDM_FINISH_RSP, "SPDM_FINISH_RSP" }, + { SPDM_PSK_EXCHANGE_RSP, "SPDM_PSK_EXCHANGE_RSP" }, + { SPDM_PSK_FINISH_RSP, "SPDM_PSK_FINISH_RSP" }, + { SPDM_HEARTBEAT_ACK, "SPDM_HEARTBEAT_ACK" }, + { SPDM_KEY_UPDATE_ACK, "SPDM_KEY_UPDATE_ACK" }, + { SPDM_ENCAPSULATED_REQUEST, "SPDM_ENCAPSULATED_REQUEST" }, + { SPDM_ENCAPSULATED_RESPONSE_ACK, "SPDM_ENCAPSULATED_RESPONSE_ACK" }, + { SPDM_END_SESSION_ACK, "SPDM_END_SESSION_ACK" }, + /* SPDM response code (1.2) */ + { SPDM_CSR, "SPDM_CSR" }, + { SPDM_SET_CERTIFICATE_RSP, "SPDM_SET_CERTIFICATE_RSP" }, + { SPDM_CHUNK_SEND_ACK, "SPDM_CHUNK_SEND_ACK" }, + { SPDM_CHUNK_RESPONSE, "SPDM_CHUNK_RESPONSE" }, + /* SPDM request code (1.0) */ + { SPDM_GET_DIGESTS, "SPDM_GET_DIGESTS" }, + { SPDM_GET_CERTIFICATE, "SPDM_GET_CERTIFICATE" }, + { SPDM_CHALLENGE, "SPDM_CHALLENGE" }, + { SPDM_GET_VERSION, "SPDM_GET_VERSION" }, + { SPDM_GET_MEASUREMENTS, "SPDM_GET_MEASUREMENTS" }, + { SPDM_GET_CAPABILITIES, "SPDM_GET_CAPABILITIES" }, + { SPDM_NEGOTIATE_ALGORITHMS, "SPDM_NEGOTIATE_ALGORITHMS" }, + { SPDM_VENDOR_DEFINED_REQUEST, "SPDM_VENDOR_DEFINED_REQUEST" }, + { SPDM_RESPOND_IF_READY, "SPDM_RESPOND_IF_READY" }, + /* SPDM request code (1.1) */ + { SPDM_KEY_EXCHANGE, "SPDM_KEY_EXCHANGE" }, + { SPDM_FINISH, "SPDM_FINISH" }, + { SPDM_PSK_EXCHANGE, "SPDM_PSK_EXCHANGE" }, + { SPDM_PSK_FINISH, "SPDM_PSK_FINISH" }, + { SPDM_HEARTBEAT, "SPDM_HEARTBEAT" }, + { SPDM_KEY_UPDATE, "SPDM_KEY_UPDATE" }, + { SPDM_GET_ENCAPSULATED_REQUEST, "SPDM_GET_ENCAPSULATED_REQUEST" }, + { SPDM_DELIVER_ENCAPSULATED_RESPONSE, "SPDM_DELIVER_ENCAPSULATED_RESPONSE" }, + { SPDM_END_SESSION, "SPDM_END_SESSION" }, + /* SPDM request code (1.2) */ + { SPDM_GET_CSR, "SPDM_GET_CSR" }, + { SPDM_SET_CERTIFICATE, "SPDM_SET_CERTIFICATE" }, + { SPDM_CHUNK_SEND, "SPDM_CHUNK_SEND" }, + { SPDM_CHUNK_GET, "SPDM_CHUNK_GET" } + }; + + for (index = 0; index < LIBSPDM_ARRAY_SIZE(code_str_struct); index++) { + if (request_code == code_str_struct[index].code) { + return code_str_struct[index].code_str; + } + } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "msg code 0x%x not found!!!\n", request_code)); + + return ""; +} + void libspdm_internal_dump_hex_str(const uint8_t *data, size_t size) { size_t index; @@ -229,3 +302,28 @@ void libspdm_init_managed_buffer(void *m_buffer, size_t max_buffer_size) libspdm_reset_managed_buffer(m_buffer); } + +/** + * byte3 - libspdm major version + * byte2 - libspdm minor version + * byte1 - libspdm patch version + * byte0 - libspdm alpha + * (office release with tag: 0, release candidate with tag: 1, non official release: 0xFF) + **/ +uint32_t libspdm_module_version(void) +{ + return (LIBSPDM_MAJOR_VERSION << 24) | + (LIBSPDM_MINOR_VERSION << 16) | + (LIBSPDM_PATCH_VERSION << 8) | + (LIBSPDM_ALPHA); +} + +/*true: FIPS enabled, false: FIPS disabled*/ +bool libspdm_get_fips_mode(void) +{ +#if LIBSPDM_FIPS_MODE + return true; +#else + return false; +#endif +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_aead.c similarity index 80% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_aead.c index f10cc6bf69..04eaa8ce50 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_aead.c @@ -10,13 +10,29 @@ uint32_t libspdm_get_aead_key_size(uint16_t aead_cipher_suite) { switch (aead_cipher_suite) { case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: +#if LIBSPDM_AEAD_AES_128_GCM_SUPPORT return 16; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: +#if LIBSPDM_AEAD_AES_256_GCM_SUPPORT return 32; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT return 32; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: +#if LIBSPDM_AEAD_SM4_128_GCM_SUPPORT return 16; +#else + return 0; +#endif default: return 0; } @@ -26,13 +42,29 @@ uint32_t libspdm_get_aead_iv_size(uint16_t aead_cipher_suite) { switch (aead_cipher_suite) { case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: +#if LIBSPDM_AEAD_AES_128_GCM_SUPPORT return 12; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: +#if LIBSPDM_AEAD_AES_256_GCM_SUPPORT return 12; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT return 12; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: +#if LIBSPDM_AEAD_SM4_128_GCM_SUPPORT return 12; +#else + return 0; +#endif default: return 0; } @@ -42,13 +74,29 @@ uint32_t libspdm_get_aead_tag_size(uint16_t aead_cipher_suite) { switch (aead_cipher_suite) { case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: +#if LIBSPDM_AEAD_AES_128_GCM_SUPPORT return 16; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: +#if LIBSPDM_AEAD_AES_256_GCM_SUPPORT return 16; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_CHACHA20_POLY1305: +#if LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT return 16; +#else + return 0; +#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AEAD_SM4_GCM: +#if LIBSPDM_AEAD_SM4_128_GCM_SUPPORT return 16; +#else + return 0; +#endif default: return 0; } @@ -65,16 +113,14 @@ bool libspdm_aead_encryption(const spdm_version_number_t secured_message_version { switch (aead_cipher_suite) { case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: -#if LIBSPDM_AEAD_GCM_SUPPORT - return libspdm_aead_aes_gcm_encrypt(key, key_size, iv, iv_size, a_data, - a_data_size, data_in, data_in_size, tag_out, - tag_size, data_out, data_out_size); -#else - LIBSPDM_ASSERT(false); - return false; -#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: #if LIBSPDM_AEAD_GCM_SUPPORT +#if !LIBSPDM_AEAD_AES_128_GCM_SUPPORT + LIBSPDM_ASSERT(aead_cipher_suite != SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM); +#endif +#if !LIBSPDM_AEAD_AES_256_GCM_SUPPORT + LIBSPDM_ASSERT(aead_cipher_suite != SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM); +#endif return libspdm_aead_aes_gcm_encrypt(key, key_size, iv, iv_size, a_data, a_data_size, data_in, data_in_size, tag_out, tag_size, data_out, data_out_size); @@ -117,16 +163,14 @@ bool libspdm_aead_decryption(const spdm_version_number_t secured_message_version { switch (aead_cipher_suite) { case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM: -#if LIBSPDM_AEAD_GCM_SUPPORT - return libspdm_aead_aes_gcm_decrypt(key, key_size, iv, iv_size, a_data, - a_data_size, data_in, data_in_size, tag, - tag_size, data_out, data_out_size); -#else - LIBSPDM_ASSERT(false); - return false; -#endif case SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM: #if LIBSPDM_AEAD_GCM_SUPPORT +#if !LIBSPDM_AEAD_AES_128_GCM_SUPPORT + LIBSPDM_ASSERT(aead_cipher_suite != SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_128_GCM); +#endif +#if !LIBSPDM_AEAD_AES_256_GCM_SUPPORT + LIBSPDM_ASSERT(aead_cipher_suite != SPDM_ALGORITHMS_AEAD_CIPHER_SUITE_AES_256_GCM); +#endif return libspdm_aead_aes_gcm_decrypt(key, key_size, iv, iv_size, a_data, a_data_size, data_in, data_in_size, tag, tag_size, data_out, data_out_size); diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_asym.c similarity index 61% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_asym.c index 3215821f4e..805bca34ca 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_asym.c @@ -5,6 +5,7 @@ **/ #include "internal/libspdm_crypt_lib.h" +#include "library/spdm_common_lib.h" typedef struct { bool is_requester; @@ -174,26 +175,77 @@ uint32_t libspdm_get_asym_signature_size(uint32_t base_asym_algo) { switch (base_asym_algo) { case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: +#if LIBSPDM_RSA_SSA_2048_SUPPORT + return 256; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: +#if LIBSPDM_RSA_PSS_2048_SUPPORT return 256; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: +#if LIBSPDM_RSA_SSA_3072_SUPPORT + return 384; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: +#if LIBSPDM_RSA_PSS_3072_SUPPORT return 384; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: +#if LIBSPDM_RSA_SSA_4096_SUPPORT + return 512; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if LIBSPDM_RSA_PSS_4096_SUPPORT return 512; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: +#if LIBSPDM_ECDSA_P256_SUPPORT return 32 * 2; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: +#if LIBSPDM_ECDSA_P384_SUPPORT return 48 * 2; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_P521_SUPPORT return 66 * 2; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_P256_SUPPORT return 32 * 2; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: +#if LIBSPDM_EDDSA_ED25519_SUPPORT return 32 * 2; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if LIBSPDM_EDDSA_ED448_SUPPORT return 57 * 2; +#else + return 0; +#endif default: return 0; } @@ -209,6 +261,15 @@ static bool libspdm_asym_sign_wrap (void *context, size_t hash_nid, uint32_t bas case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: #if LIBSPDM_RSA_SSA_SUPPORT +#if !LIBSPDM_RSA_SSA_2048_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048); +#endif +#if !LIBSPDM_RSA_SSA_3072_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072); +#endif +#if !LIBSPDM_RSA_SSA_4096_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096); +#endif return libspdm_rsa_pkcs1_sign_with_nid_wrap(context, hash_nid, param, param_size, message, message_size, @@ -221,6 +282,15 @@ static bool libspdm_asym_sign_wrap (void *context, size_t hash_nid, uint32_t bas case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: #if LIBSPDM_RSA_PSS_SUPPORT +#if !LIBSPDM_RSA_PSS_2048_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048); +#endif +#if !LIBSPDM_RSA_PSS_3072_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072); +#endif +#if !LIBSPDM_RSA_PSS_4096_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096); +#endif return libspdm_rsa_pss_sign_wrap(context, hash_nid, param, param_size, message, message_size, @@ -233,6 +303,15 @@ static bool libspdm_asym_sign_wrap (void *context, size_t hash_nid, uint32_t bas case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: #if LIBSPDM_ECDSA_SUPPORT +#if !LIBSPDM_ECDSA_P256_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256); +#endif +#if !LIBSPDM_ECDSA_P384_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384); +#endif +#if !LIBSPDM_ECDSA_P521_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521); +#endif return libspdm_ecdsa_sign_wrap(context, hash_nid, param, param_size, message, message_size, @@ -244,6 +323,12 @@ static bool libspdm_asym_sign_wrap (void *context, size_t hash_nid, uint32_t bas case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: #if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +#if !LIBSPDM_EDDSA_ED25519_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519); +#endif +#if !LIBSPDM_EDDSA_ED448_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448); +#endif return libspdm_eddsa_sign_wrap(context, hash_nid, param, param_size, message, message_size, @@ -270,6 +355,9 @@ static bool libspdm_asym_sign_wrap (void *context, size_t hash_nid, uint32_t bas void libspdm_asym_free(uint32_t base_asym_algo, void *context) { + if (context == NULL) { + return; + } switch (base_asym_algo) { case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: @@ -313,6 +401,98 @@ void libspdm_asym_free(uint32_t base_asym_algo, void *context) } } +static bool libspdm_asym_get_public_key_from_der_wrap(uint32_t base_asym_algo, + const uint8_t *der_data, + size_t der_size, + void **context) +{ + switch (base_asym_algo) { + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +#if !LIBSPDM_RSA_SSA_2048_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048); +#endif +#if !LIBSPDM_RSA_SSA_3072_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072); +#endif +#if !LIBSPDM_RSA_SSA_4096_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096); +#endif +#if !LIBSPDM_RSA_PSS_2048_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048); +#endif +#if !LIBSPDM_RSA_PSS_3072_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072); +#endif +#if !LIBSPDM_RSA_PSS_4096_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096); +#endif + return libspdm_rsa_get_public_key_from_der(der_data, der_size, context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_SUPPORT +#if !LIBSPDM_ECDSA_P256_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256); +#endif +#if !LIBSPDM_ECDSA_P384_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384); +#endif +#if !LIBSPDM_ECDSA_P521_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521); +#endif + return libspdm_ec_get_public_key_from_der(der_data, der_size, context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) + return libspdm_ecd_get_public_key_from_der(der_data, der_size, context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_SM2_ECC_SM2_P256: +#if LIBSPDM_SM2_DSA_SUPPORT +#if !LIBSPDM_EDDSA_ED25519_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519); +#endif +#if !LIBSPDM_EDDSA_ED448_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448); +#endif + return libspdm_sm2_get_public_key_from_der(der_data, der_size, context); +#else + LIBSPDM_ASSERT(false); + return false; +#endif + default: + LIBSPDM_ASSERT(false); + return false; + } +} + +bool libspdm_asym_get_public_key_from_der(uint32_t base_asym_algo, + const uint8_t *der_data, + size_t der_size, + void **context) +{ + return libspdm_asym_get_public_key_from_der_wrap(base_asym_algo, + der_data, + der_size, + context); +} + /** * Return if asymmetric function need message hash. * @@ -347,6 +527,226 @@ static bool libspdm_asym_func_need_hash(uint32_t base_asym_algo) return false; } +/** + * libspdm_copy_signature_swap_endian_rsa + * Swaps the endianness of a RSA signature buffer. The ECDSA signature buffer is + * actually single internal buffer and can be swapped as a single whole buffer. + * + * There are two known usage models for buffers for this function. + * 1) Source and dest are the same (and their sizes). This would be an in-place swap. + * 2) Source and dest are completely different (and dest size >= src size). No overlap. + * + * The case where source and dest are overlapped (and not the exact same buffer) + * is not allowed and guarded against with an assert. + **/ +static void libspdm_copy_signature_swap_endian_rsa( + uint8_t* dst, + size_t dst_size, + const uint8_t* src, + size_t src_size) +{ + /* RSA signature is a single buffer to be swapped */ + size_t i; + + if (src == dst) { + LIBSPDM_ASSERT(dst_size == src_size); + + /* src and dst are same buffer. Swap in place. */ + + uint8_t byte; + for (i = 0; i < dst_size / 2; i++) { + byte = dst[i]; + dst[i] = dst[dst_size - i - 1]; + dst[dst_size - i - 1] = byte; + } + } else { + /* src and dst are different buffers. + * Guard against overlap case with assert. + * Overlap case is not an expected usage model. */ + LIBSPDM_ASSERT(dst_size >= src_size); + LIBSPDM_ASSERT((src < dst && src + src_size <= dst) || + (dst < src && dst + dst_size <= src)); + + for (i = 0; i < src_size; i++) { + dst[i] = src[src_size - i - 1]; + } + } +} + +/** + * libspdm_copy_signature_swap_endian_ecdsa + * Swaps the endianness of a ECDSA signature buffer. The ECDSA signature buffer is + * actually two internal buffers, and each internal buffer must be swapped individually. + * + * There are two known usage models for buffers for this function. + * 1) Source and dest are the same (and their sizes). This would be an in-place swap. + * 2) Source and dest are completely different (and dest size >= src size). No overlap. + * + * The case where source and dest are overlapped (and not the exact same buffer) + * is not allowed and guarded against with an assert. + **/ +static void libspdm_copy_signature_swap_endian_ecdsa( + uint8_t* dst, + size_t dst_size, + const uint8_t* src, + size_t src_size) +{ + /* ECDSA signature is actually 2 buffers (x & y) + * and each must be swapped individually */ + size_t i; + + if (src == dst) { + LIBSPDM_ASSERT(dst_size == src_size); + + /* src and dst are same buffer. Swap ecdsa 2 internal buffers in place. */ + + size_t x_size; + size_t y_size; + uint8_t* x; + uint8_t* y; + uint8_t byte; + + x_size = dst_size / 2; + y_size = x_size; + + x = dst; + y = x + x_size; + + for (i = 0; i < x_size / 2; i++) { + byte = x[i]; + x[i] = x[x_size - i - 1]; + x[x_size - i - 1] = byte; + } + + for (i = 0; i < y_size / 2; i++) { + byte = y[i]; + y[i] = y[y_size - i - 1]; + y[y_size - i - 1] = byte; + } + } else { + /* src and dst are different buffers. + * Guard against overlap case with assert. + * Overlap case is not an expected usage model. */ + LIBSPDM_ASSERT(dst_size >= src_size); + LIBSPDM_ASSERT((src < dst && src + src_size <= dst) || + (dst < src && dst + dst_size <= src)); + + size_t x_size; + size_t y_size; + + const uint8_t* src_x; + const uint8_t* src_y; + + uint8_t* dst_x; + uint8_t* dst_y; + + x_size = src_size / 2; + y_size = x_size; + + src_x = src; + src_y = src_x + x_size; + + dst_x = dst; + dst_y = dst_x + x_size; + + for (i = 0; i < x_size; i++) { + dst_x[i] = src_x[x_size - i - 1]; + } + + for (i = 0; i < y_size; i++) { + dst_y[i] = src_y[y_size - i - 1]; + } + } +} + +void libspdm_copy_signature_swap_endian( + uint32_t base_asym_algo, + uint8_t* dst, + size_t dst_size, + const uint8_t* src, + size_t src_size) +{ + const uint32_t spdm_10_11_rsa_algos = + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096; + + const uint32_t spdm_10_11_ecdsa_algos = + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521; + + if (base_asym_algo & spdm_10_11_rsa_algos) { + libspdm_copy_signature_swap_endian_rsa(dst, dst_size, src, src_size); + } else if (base_asym_algo & spdm_10_11_ecdsa_algos) { + libspdm_copy_signature_swap_endian_ecdsa(dst, dst_size, src, src_size); + } else { + /* Currently do not expect asymmetric algorithms other than RSA and ECDSA */ + LIBSPDM_ASSERT(0); + } +} + +/** + * libspdm_is_palindrome + * Checks to see if a buffer is a palindrome. + * If the buffer is a palindrone, it is the same for both endians, + * and therefore endianness cannot be determined. + **/ +bool libspdm_is_palindrome(const uint8_t* buf, size_t buf_size) +{ + size_t head; + size_t tail; + + head = 0; + tail = buf_size - 1; + + while (head < tail) { + if (buf[head] != buf[tail]) { + return false; + } + head++; + tail--; + } + + return true; +} + +bool libspdm_is_signature_buffer_palindrome( + uint32_t base_asym_algo, const uint8_t *buf, size_t buf_size) +{ + const uint32_t spdm_10_11_rsa_algos = + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096; + + const uint32_t spdm_10_11_ecdsa_algos = + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 | + SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521; + + if (base_asym_algo & spdm_10_11_rsa_algos) { + return libspdm_is_palindrome(buf, buf_size); + } else if (base_asym_algo & spdm_10_11_ecdsa_algos) { + const size_t x_size = buf_size / 2; + const size_t y_size = x_size; + + const uint8_t *x = buf; + const uint8_t *y = buf + x_size; + + return libspdm_is_palindrome(x, x_size) && libspdm_is_palindrome(y, y_size); + } else { + /* Currently do not expect asymmetric algorithms other than RSA and ECDSA */ + LIBSPDM_ASSERT(0); + return false; + } +} + #if LIBSPDM_RSA_SSA_SUPPORT static bool libspdm_rsa_pkcs1_verify_with_nid_wrap (void *context, size_t hash_nid, const uint8_t *param, size_t param_size, @@ -421,6 +821,15 @@ static bool libspdm_asym_verify_wrap( case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: #if LIBSPDM_RSA_SSA_SUPPORT +#if !LIBSPDM_RSA_SSA_2048_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048); +#endif +#if !LIBSPDM_RSA_SSA_3072_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072); +#endif +#if !LIBSPDM_RSA_SSA_4096_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096); +#endif return libspdm_rsa_pkcs1_verify_with_nid_wrap(context, hash_nid, param, param_size, message, message_size, @@ -433,6 +842,15 @@ static bool libspdm_asym_verify_wrap( case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: #if LIBSPDM_RSA_PSS_SUPPORT +#if !LIBSPDM_RSA_PSS_2048_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048); +#endif +#if !LIBSPDM_RSA_PSS_3072_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072); +#endif +#if !LIBSPDM_RSA_PSS_4096_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096); +#endif return libspdm_rsa_pss_verify_wrap(context, hash_nid, param, param_size, message, message_size, @@ -445,6 +863,15 @@ static bool libspdm_asym_verify_wrap( case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: #if LIBSPDM_ECDSA_SUPPORT +#if !LIBSPDM_ECDSA_P256_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256); +#endif +#if !LIBSPDM_ECDSA_P384_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384); +#endif +#if !LIBSPDM_ECDSA_P521_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521); +#endif return libspdm_ecdsa_verify_wrap(context, hash_nid, param, param_size, message, message_size, @@ -456,6 +883,12 @@ static bool libspdm_asym_verify_wrap( case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: #if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +#if !LIBSPDM_EDDSA_ED25519_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519); +#endif +#if !LIBSPDM_EDDSA_ED448_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448); +#endif return libspdm_eddsa_verify_wrap(context, hash_nid, param, param_size, message, message_size, @@ -480,12 +913,13 @@ static bool libspdm_asym_verify_wrap( } } -bool libspdm_asym_verify( +bool libspdm_asym_verify_ex( spdm_version_number_t spdm_version, uint8_t op_code, uint32_t base_asym_algo, uint32_t base_hash_algo, - void *context, const uint8_t *message, - size_t message_size, const uint8_t *signature, - size_t sig_size) + void *context, + const uint8_t *message, size_t message_size, + const uint8_t *signature, size_t sig_size, + uint8_t *endian) { bool need_hash; uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; @@ -497,6 +931,11 @@ bool libspdm_asym_verify( const void *param; size_t param_size; + bool try_big_endian; + bool try_little_endian; + bool little_endian_succeeded; + uint8_t endian_swapped_signature[LIBSPDM_MAX_ASYM_SIG_SIZE]; + hash_nid = libspdm_get_hash_nid(base_hash_algo); need_hash = libspdm_asym_func_need_hash(base_asym_algo); @@ -533,11 +972,22 @@ bool libspdm_asym_verify( } /* re-assign message and message_size for signing */ - hash_size = libspdm_get_hash_size(base_hash_algo); message = spdm12_signing_context_with_hash; message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; - + try_big_endian = true; + try_little_endian = false; + little_endian_succeeded = false; /* Passthru */ + } else { + try_big_endian = + (*endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY + || *endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE); + + try_little_endian = + (*endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY + || *endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE); + + little_endian_succeeded = false; } if (need_hash) { @@ -546,24 +996,65 @@ bool libspdm_asym_verify( if (!result) { return false; } - return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, - param, param_size, - message_hash, hash_size, - signature, sig_size); + result = false; + if (try_big_endian) { + result = libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } + if (!result && try_little_endian) { + libspdm_copy_signature_swap_endian( + base_asym_algo, + endian_swapped_signature, sizeof(endian_swapped_signature), + signature, sig_size); + + result = libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + endian_swapped_signature, sig_size); + little_endian_succeeded = result; + } } else { - return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, - param, param_size, - message, message_size, - signature, sig_size); + result = false; + if (try_big_endian) { + result = libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + signature, sig_size); + } + if (!result && try_little_endian) { + libspdm_copy_signature_swap_endian( + base_asym_algo, + endian_swapped_signature, sizeof(endian_swapped_signature), + signature, sig_size); + + result = libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message, message_size, + endian_swapped_signature, sig_size); + little_endian_succeeded = result; + } + } + if (try_big_endian && try_little_endian && result) { + if (!libspdm_is_signature_buffer_palindrome(base_asym_algo, signature, sig_size)) { + if (little_endian_succeeded) { + *endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY; + } else { + *endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY; + } + } } + return result; } -bool libspdm_asym_verify_hash( + +bool libspdm_asym_verify_hash_ex( spdm_version_number_t spdm_version, uint8_t op_code, uint32_t base_asym_algo, uint32_t base_hash_algo, void *context, const uint8_t *message_hash, size_t hash_size, const uint8_t *signature, - size_t sig_size) + size_t sig_size, uint8_t *endian) { bool need_hash; uint8_t *message; @@ -576,12 +1067,20 @@ bool libspdm_asym_verify_hash( const void *param; size_t param_size; + bool try_big_endian; + bool try_little_endian; + bool little_endian_succeeded; + uint8_t endian_swapped_signature[LIBSPDM_MAX_ASYM_SIG_SIZE]; + hash_nid = libspdm_get_hash_nid(base_hash_algo); need_hash = libspdm_asym_func_need_hash(base_asym_algo); LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); param = NULL; param_size = 0; + try_big_endian = true; + try_little_endian = false; + little_endian_succeeded = false; if ((spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT) > SPDM_MESSAGE_VERSION_11) { /* Need use SPDM 1.2 signing */ @@ -629,21 +1128,82 @@ bool libspdm_asym_verify_hash( message, message_size, signature, sig_size); } - /* SPDM 1.2 signing done. */ + } else { + try_big_endian = + (*endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY + || *endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE); + + try_little_endian = + (*endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY + || *endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE); + + little_endian_succeeded = false; } if (need_hash) { - return libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, - param, param_size, - message_hash, hash_size, - signature, sig_size); + result = false; + if (try_big_endian) { + result = libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } + if (!result && try_little_endian) { + libspdm_copy_signature_swap_endian( + base_asym_algo, + endian_swapped_signature, sizeof(endian_swapped_signature), + signature, sig_size); + + result = libspdm_asym_verify_wrap(context, hash_nid, base_asym_algo, + param, param_size, + message_hash, hash_size, + endian_swapped_signature, sig_size); + little_endian_succeeded = result; + } + if (try_big_endian && try_little_endian && result) { + if (!libspdm_is_signature_buffer_palindrome(base_asym_algo, signature, sig_size)) { + if (little_endian_succeeded) { + *endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY; + } else { + *endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY; + } + } + } + return result; + } else { LIBSPDM_ASSERT(false); return false; } } +bool libspdm_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void* context, const uint8_t* message, + size_t message_size, const uint8_t* signature, + size_t sig_size) +{ + uint8_t endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY; + return libspdm_asym_verify_ex( + spdm_version, op_code, base_asym_algo, base_hash_algo, + context, message, message_size, signature, sig_size, &endian); +} + +bool libspdm_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint32_t base_asym_algo, uint32_t base_hash_algo, + void* context, const uint8_t* message_hash, + size_t hash_size, const uint8_t* signature, + size_t sig_size) +{ + uint8_t endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY; + return libspdm_asym_verify_hash_ex( + spdm_version, op_code, base_asym_algo, base_hash_algo, + context, message_hash, hash_size, signature, sig_size, &endian); +} + bool libspdm_asym_sign( spdm_version_number_t spdm_version, uint8_t op_code, uint32_t base_asym_algo, uint32_t base_hash_algo, @@ -697,7 +1257,6 @@ bool libspdm_asym_sign( } /* re-assign message and message_size for signing */ - hash_size = libspdm_get_hash_size(base_hash_algo); message = spdm12_signing_context_with_hash; message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; @@ -818,17 +1377,28 @@ void libspdm_req_asym_free(uint16_t req_base_asym_alg, void *context) libspdm_asym_free(req_base_asym_alg, context); } +bool libspdm_req_asym_get_public_key_from_der(uint16_t req_base_asym_alg, + const uint8_t *der_data, + size_t der_size, + void **context) +{ + return libspdm_asym_get_public_key_from_der_wrap(req_base_asym_alg, + der_data, + der_size, + context); +} + bool libspdm_req_asym_func_need_hash(uint16_t req_base_asym_alg) { return libspdm_asym_func_need_hash(req_base_asym_alg); } -bool libspdm_req_asym_verify( +bool libspdm_req_asym_verify_ex( spdm_version_number_t spdm_version, uint8_t op_code, uint16_t req_base_asym_alg, uint32_t base_hash_algo, void *context, const uint8_t *message, size_t message_size, - const uint8_t *signature, size_t sig_size) + const uint8_t *signature, size_t sig_size, uint8_t *endian) { bool need_hash; uint8_t message_hash[LIBSPDM_MAX_HASH_SIZE]; @@ -840,6 +1410,11 @@ bool libspdm_req_asym_verify( const void *param; size_t param_size; + bool try_big_endian; + bool try_little_endian; + bool little_endian_succeeded; + uint8_t endian_swapped_signature[LIBSPDM_MAX_ASYM_SIG_SIZE]; + hash_nid = libspdm_get_hash_nid(base_hash_algo); need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); @@ -876,11 +1451,22 @@ bool libspdm_req_asym_verify( } /* re-assign message and message_size for signing */ - hash_size = libspdm_get_hash_size(base_hash_algo); message = spdm12_signing_context_with_hash; message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; - + try_big_endian = true; + try_little_endian = false; + little_endian_succeeded = false; /* Passthru */ + } else { + try_big_endian = + (*endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY + || *endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE); + + try_little_endian = + (*endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY + || *endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE); + + little_endian_succeeded = false; } if (need_hash) { @@ -889,24 +1475,64 @@ bool libspdm_req_asym_verify( if (!result) { return false; } - return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, - param, param_size, - message_hash, hash_size, - signature, sig_size); + result = false; + if (try_big_endian) { + result = libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } + if (!result && try_little_endian) { + libspdm_copy_signature_swap_endian( + req_base_asym_alg, + endian_swapped_signature, sizeof(endian_swapped_signature), + signature, sig_size); + + result = libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + endian_swapped_signature, sig_size); + little_endian_succeeded = result; + } } else { - return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, - param, param_size, - message, message_size, - signature, sig_size); + result = false; + if (try_big_endian) { + result = libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + signature, sig_size); + } + if (!result && try_little_endian) { + libspdm_copy_signature_swap_endian( + req_base_asym_alg, + endian_swapped_signature, sizeof(endian_swapped_signature), + signature, sig_size); + + result = libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message, message_size, + endian_swapped_signature, sig_size); + little_endian_succeeded = result; + } } + if (try_big_endian && try_little_endian && result) { + if (!libspdm_is_signature_buffer_palindrome(req_base_asym_alg, signature, sig_size)) { + if (little_endian_succeeded) { + *endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY; + } else { + *endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY; + } + } + } + return result; } -bool libspdm_req_asym_verify_hash( +bool libspdm_req_asym_verify_hash_ex( spdm_version_number_t spdm_version, uint8_t op_code, uint16_t req_base_asym_alg, uint32_t base_hash_algo, void *context, const uint8_t *message_hash, size_t hash_size, - const uint8_t *signature, size_t sig_size) + const uint8_t *signature, size_t sig_size, uint8_t *endian) { bool need_hash; uint8_t *message; @@ -919,6 +1545,11 @@ bool libspdm_req_asym_verify_hash( const void *param; size_t param_size; + bool try_big_endian; + bool try_little_endian; + bool little_endian_succeeded; + uint8_t endian_swapped_signature[LIBSPDM_MAX_ASYM_SIG_SIZE]; + hash_nid = libspdm_get_hash_nid(base_hash_algo); need_hash = libspdm_req_asym_func_need_hash(req_base_asym_alg); LIBSPDM_ASSERT (hash_size == libspdm_get_hash_size(base_hash_algo)); @@ -974,19 +1605,80 @@ bool libspdm_req_asym_verify_hash( signature, sig_size); } /* SPDM 1.2 signing done. */ + } else { + try_big_endian = + (*endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY + || *endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE); + + try_little_endian = + (*endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY + || *endian == LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_OR_LITTLE); + + little_endian_succeeded = false; } if (need_hash) { - return libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, - param, param_size, - message_hash, hash_size, - signature, sig_size); + result = false; + if (try_big_endian) { + result = libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + signature, sig_size); + } + if (!result && try_little_endian) { + libspdm_copy_signature_swap_endian( + req_base_asym_alg, + endian_swapped_signature, sizeof(endian_swapped_signature), + signature, sig_size); + + result = libspdm_asym_verify_wrap(context, hash_nid, req_base_asym_alg, + param, param_size, + message_hash, hash_size, + endian_swapped_signature, sig_size); + little_endian_succeeded = result; + } + if (try_big_endian && try_little_endian && result) { + if (!libspdm_is_signature_buffer_palindrome(req_base_asym_alg, signature, sig_size)) { + if (little_endian_succeeded) { + *endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_LITTLE_ONLY; + } else { + *endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY; + } + } + } + return result; } else { LIBSPDM_ASSERT (false); return false; } } +bool libspdm_req_asym_verify( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void* context, + const uint8_t* message, size_t message_size, + const uint8_t* signature, size_t sig_size) +{ + uint8_t endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY; + return libspdm_req_asym_verify_ex( + spdm_version, op_code, req_base_asym_alg, base_hash_algo, context, + message, message_size, signature, sig_size, &endian); +} + +bool libspdm_req_asym_verify_hash( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, void* context, + const uint8_t* message_hash, size_t hash_size, + const uint8_t* signature, size_t sig_size) +{ + uint8_t endian = LIBSPDM_SPDM_10_11_VERIFY_SIGNATURE_ENDIAN_BIG_ONLY; + return libspdm_req_asym_verify_hash_ex( + spdm_version, op_code, req_base_asym_alg, base_hash_algo, context, + message_hash, hash_size, signature, sig_size, &endian); +} + bool libspdm_req_asym_sign( spdm_version_number_t spdm_version, uint8_t op_code, uint16_t req_base_asym_alg, @@ -1040,7 +1732,6 @@ bool libspdm_req_asym_sign( } /* re-assign message and message_size for signing */ - hash_size = libspdm_get_hash_size(base_hash_algo); message = spdm12_signing_context_with_hash; message_size = SPDM_VERSION_1_2_SIGNING_CONTEXT_SIZE + hash_size; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_cert.c similarity index 72% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_cert.c index 539e588d6c..f00fba0b5f 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_cert.c @@ -6,6 +6,8 @@ #include "internal/libspdm_crypt_lib.h" +#if LIBSPDM_CERT_PARSE_SUPPORT + /**pathLenConstraint is optional. * In https://www.pkisolutions.com/basic-constraints-certificate-extension/: * pathLenConstraint: How many CAs are allowed in the chain below current CA certificate. @@ -17,8 +19,12 @@ * len > 2 * (spdm id-DMTF-spdm size + 2) **/ -#ifndef SPDM_EXTENDSION_LEN -#define SPDM_EXTENDSION_LEN 30 +#ifndef LIBSPDM_MAX_EXTENSION_LEN +#define LIBSPDM_MAX_EXTENSION_LEN 30 +#endif + +#ifndef LIBSPDM_MAX_NAME_SIZE +#define LIBSPDM_MAX_NAME_SIZE 100 #endif /*max public key encryption algo oid len*/ @@ -27,8 +33,8 @@ #endif /*leaf cert basic constraints len,CA = false: 30 03 01 01 00*/ -#ifndef BASIC_CONSTRAINTS_CA_LEN -#define BASIC_CONSTRAINTS_CA_LEN 5 +#ifndef LIBSPDM_MAX_BASIC_CONSTRAINTS_CA_LEN +#define LIBSPDM_MAX_BASIC_CONSTRAINTS_CA_LEN 5 #endif /** @@ -36,14 +42,21 @@ * 0x82 indicates that the length is expressed in two bytes; * 0x01 and 0x01 are rsa key len; **/ +#if (LIBSPDM_RSA_SSA_2048_SUPPORT) || (LIBSPDM_RSA_PSS_2048_SUPPORT) #define KEY_ENCRY_ALGO_RSA2048_FLAG {0x02, 0x82, 0x01, 0x01} -#define KEY_ENCRY_ALGO_RSA3072_FLAG {0x02, 0x82, 0x01, 0x81} -#define KEY_ENCRY_ALGO_RSA4096_FLAG {0x02, 0x82, 0x02, 0x01} - /* the other case is ASN1 code different when integer is 1 on highest position*/ #define KEY_ENCRY_ALGO_RSA2048_FLAG_OTHER {0x02, 0x82, 0x01, 0x00} +#endif +#if (LIBSPDM_RSA_SSA_3072_SUPPORT) || (LIBSPDM_RSA_PSS_3072_SUPPORT) +#define KEY_ENCRY_ALGO_RSA3072_FLAG {0x02, 0x82, 0x01, 0x81} +/* the other case is ASN1 code different when integer is 1 on highest position*/ #define KEY_ENCRY_ALGO_RSA3072_FLAG_OTHER {0x02, 0x82, 0x01, 0x80} +#endif +#if (LIBSPDM_RSA_SSA_4096_SUPPORT) || (LIBSPDM_RSA_PSS_4096_SUPPORT) +#define KEY_ENCRY_ALGO_RSA4096_FLAG {0x02, 0x82, 0x02, 0x01} +/* the other case is ASN1 code different when integer is 1 on highest position*/ #define KEY_ENCRY_ALGO_RSA4096_FLAG_OTHER {0x02, 0x82, 0x02, 0x00} +#endif /** * https://oidref.com/1.2.840.10045.3.1.7 @@ -53,24 +66,43 @@ * https://oidref.com/1.3.132.0.35 * ECC521 curve OID: 1.3.132.0.35 **/ +#if LIBSPDM_ECDSA_P256_SUPPORT #define KEY_ENCRY_ALGO_ECC256_OID {0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01, 0x07} +#endif +#if LIBSPDM_ECDSA_P384_SUPPORT #define KEY_ENCRY_ALGO_ECC384_OID {0x2B, 0x81, 0x04, 0x00, 0x22} +#endif +#if LIBSPDM_ECDSA_P521_SUPPORT #define KEY_ENCRY_ALGO_ECC521_OID {0x2B, 0x81, 0x04, 0x00, 0x23} +#endif /** * EDxxx OID: https://datatracker.ietf.org/doc/html/rfc8420 * ED448 OID: 1.3.101.113 * ED25519 OID: 1.3.101.112 **/ +#if LIBSPDM_EDDSA_ED25519_SUPPORT #define ENCRY_ALGO_ED25519_OID {0x2B, 0x65, 0x70} +#endif +#if LIBSPDM_EDDSA_ED448_SUPPORT #define ENCRY_ALGO_ED448_OID {0x2B, 0x65, 0x71} +#endif + +/*leaf cert basic_constraints false case1: CA: false and CA object is excluded */ +#define BASIC_CONSTRAINTS_STRING_FALSE_CASE1 {0x30, 0x00} + +/*leaf cert basic_constraints false case2: CA: false */ +#define BASIC_CONSTRAINTS_STRING_FALSE_CASE2 {0x30, 0x03, 0x01, 0x01, 0x00} + +/*leaf cert basic_constraints true case: CA: true */ +#define BASIC_CONSTRAINTS_STRING_TRUE_CASE {0x30, 0x03, 0x01, 0x01, 0xFF} /** * Retrieve the asymmetric public key from one DER-encoded X509 certificate. * * @param cert Pointer to the DER-encoded X509 certificate. * @param cert_size Size of the X509 certificate in bytes. - * @param context Pointer to new-generated asymmetric context which contain the retrieved public + * @param context Pointer to newly generated asymmetric context which contain the retrieved public * key component. Use libspdm_asym_free() function to free the resource. * * @retval true public key was retrieved successfully. @@ -98,6 +130,24 @@ static libspdm_get_asym_get_public_key_from_x509(uint32_t base_asym_algo) case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: #if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +#if !LIBSPDM_RSA_SSA_2048_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048); +#endif +#if !LIBSPDM_RSA_SSA_3072_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072); +#endif +#if !LIBSPDM_RSA_SSA_4096_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096); +#endif +#if !LIBSPDM_RSA_PSS_2048_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048); +#endif +#if !LIBSPDM_RSA_PSS_3072_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072); +#endif +#if !LIBSPDM_RSA_PSS_4096_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096); +#endif return libspdm_rsa_get_public_key_from_x509; #else LIBSPDM_ASSERT(false); @@ -107,6 +157,15 @@ static libspdm_get_asym_get_public_key_from_x509(uint32_t base_asym_algo) case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: #if LIBSPDM_ECDSA_SUPPORT +#if !LIBSPDM_ECDSA_P256_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256); +#endif +#if !LIBSPDM_ECDSA_P384_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384); +#endif +#if !LIBSPDM_ECDSA_P521_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521); +#endif return libspdm_ec_get_public_key_from_x509; #else LIBSPDM_ASSERT(false); @@ -115,6 +174,12 @@ static libspdm_get_asym_get_public_key_from_x509(uint32_t base_asym_algo) case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: #if (LIBSPDM_EDDSA_ED25519_SUPPORT) || (LIBSPDM_EDDSA_ED448_SUPPORT) +#if !LIBSPDM_EDDSA_ED25519_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519); +#endif +#if !LIBSPDM_EDDSA_ED448_SUPPORT + LIBSPDM_ASSERT(base_asym_algo!= SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448); +#endif return libspdm_ecd_get_public_key_from_x509; #else LIBSPDM_ASSERT(false); @@ -142,7 +207,7 @@ static libspdm_get_asym_get_public_key_from_x509(uint32_t base_asym_algo) * @param base_asym_algo SPDM base_asym_algo * @param cert Pointer to the DER-encoded X509 certificate. * @param cert_size size of the X509 certificate in bytes. - * @param context Pointer to new-generated asymmetric context which contain the retrieved public key component. + * @param context Pointer to newly generated asymmetric context which contain the retrieved public key component. * Use libspdm_asym_free() function to free the resource. * * @retval true public key was retrieved successfully. @@ -181,7 +246,7 @@ libspdm_get_req_asym_get_public_key_from_x509(uint16_t req_base_asym_alg) * @param req_base_asym_alg SPDM req_base_asym_alg * @param cert Pointer to the DER-encoded X509 certificate. * @param cert_size size of the X509 certificate in bytes. - * @param context Pointer to new-generated asymmetric context which contain the retrieved public key component. + * @param context Pointer to newly generated asymmetric context which contain the retrieved public key component. * Use libspdm_asym_free() function to free the resource. * * @retval true public key was retrieved successfully. @@ -264,23 +329,74 @@ static uint32_t libspdm_get_public_key_algo_OID_len(uint32_t base_asym_algo) { switch (base_asym_algo) { case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: +#if LIBSPDM_RSA_SSA_2048_SUPPORT + return 4; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: +#if LIBSPDM_RSA_PSS_2048_SUPPORT + return 4; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: +#if LIBSPDM_RSA_SSA_3072_SUPPORT + return 4; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: +#if LIBSPDM_RSA_PSS_3072_SUPPORT + return 4; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: +#if LIBSPDM_RSA_SSA_4096_SUPPORT + return 4; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: +#if LIBSPDM_RSA_PSS_4096_SUPPORT return 4; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: +#if LIBSPDM_ECDSA_P256_SUPPORT return 8; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: +#if LIBSPDM_ECDSA_P384_SUPPORT + return 5; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: +#if LIBSPDM_ECDSA_P521_SUPPORT return 5; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: +#if LIBSPDM_EDDSA_ED25519_SUPPORT + return 3; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: +#if LIBSPDM_EDDSA_ED448_SUPPORT return 3; +#else + return 0; +#endif default: LIBSPDM_ASSERT(false); - return false; + return 0; } } @@ -300,47 +416,74 @@ static bool libspdm_get_public_key_algo_OID(uint32_t base_asym_algo, uint8_t *oi { uint32_t oid_len; oid_len = libspdm_get_public_key_algo_OID_len(base_asym_algo); + if(oid_len == 0) { + return false; + } switch (base_asym_algo) { case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048: { +#if (LIBSPDM_RSA_SSA_2048_SUPPORT) || (LIBSPDM_RSA_PSS_2048_SUPPORT) uint8_t encry_algo_oid_rsa2048[] = KEY_ENCRY_ALGO_RSA2048_FLAG; uint8_t encry_algo_oid_rsa2048_ohter[] = KEY_ENCRY_ALGO_RSA2048_FLAG_OTHER; libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa2048, oid_len); libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa2048_ohter, oid_len); - break; + return true; +#else + return false; +#endif } case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072: { +#if (LIBSPDM_RSA_SSA_3072_SUPPORT) || (LIBSPDM_RSA_PSS_3072_SUPPORT) uint8_t encry_algo_oid_rsa3072[] = KEY_ENCRY_ALGO_RSA3072_FLAG; uint8_t encry_algo_oid_rsa3072_ohter[] = KEY_ENCRY_ALGO_RSA3072_FLAG_OTHER; libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa3072, oid_len); libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa3072_ohter, oid_len); - break; + return true; +#else + return false; +#endif } case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096: case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096: { +#if (LIBSPDM_RSA_SSA_4096_SUPPORT) || (LIBSPDM_RSA_PSS_4096_SUPPORT) uint8_t encry_algo_oid_rsa4096[] = KEY_ENCRY_ALGO_RSA4096_FLAG; uint8_t encry_algo_oid_rsa4096_ohter[] = KEY_ENCRY_ALGO_RSA4096_FLAG_OTHER; libspdm_copy_mem(oid, oid_len, encry_algo_oid_rsa4096, oid_len); libspdm_copy_mem(oid_other, oid_len, encry_algo_oid_rsa4096_ohter, oid_len); - break; + return true; +#else + return false; +#endif } case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256: { +#if LIBSPDM_ECDSA_P256_SUPPORT uint8_t encry_algo_oid_ecc256[] = KEY_ENCRY_ALGO_ECC256_OID; libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc256, oid_len); - break; + return true; +#else + return false; +#endif } case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384: { +#if LIBSPDM_ECDSA_P384_SUPPORT uint8_t encry_algo_oid_ecc384[] = KEY_ENCRY_ALGO_ECC384_OID; libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc384, oid_len); - break; + return true; +#else + return false; +#endif } case SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521: { +#if LIBSPDM_ECDSA_P521_SUPPORT uint8_t encry_algo_oid_ecc521[] = KEY_ENCRY_ALGO_ECC521_OID; libspdm_copy_mem(oid, oid_len, encry_algo_oid_ecc521, oid_len); - break; + return true; +#else + return false; +#endif } /*sm2 oid TBD*/ @@ -348,13 +491,23 @@ static bool libspdm_get_public_key_algo_OID(uint32_t base_asym_algo, uint8_t *oi return true; case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED25519: { +#if LIBSPDM_EDDSA_ED25519_SUPPORT uint8_t encry_algo_oid_ed25519[] = ENCRY_ALGO_ED25519_OID; libspdm_copy_mem(oid, oid_len, encry_algo_oid_ed25519, oid_len); + return true; +#else + return false; +#endif break; } case SPDM_ALGORITHMS_BASE_ASYM_ALGO_EDDSA_ED448: { +#if LIBSPDM_EDDSA_ED448_SUPPORT uint8_t encry_algo_oid_ed448[] = ENCRY_ALGO_ED448_OID; libspdm_copy_mem(oid, oid_len, encry_algo_oid_ed448, oid_len); + return true; +#else + return false; +#endif break; } @@ -362,8 +515,6 @@ static bool libspdm_get_public_key_algo_OID(uint32_t base_asym_algo, uint8_t *oi LIBSPDM_ASSERT(false); return false; } - - return true; } /** @@ -572,10 +723,11 @@ static bool libspdm_verify_cert_subject_public_key_info(const uint8_t *cert, siz /*get public key encrypt algo OID from cert*/ status = libspdm_get_public_key_oid(cert, cert_size, cert_public_key_crypt_algo_oid, oid_len, base_asym_algo); - if (!status || (libspdm_const_compare_mem(cert_public_key_crypt_algo_oid, - libspdm_public_key_crypt_algo_oid, oid_len) && - libspdm_const_compare_mem(cert_public_key_crypt_algo_oid, - libspdm_public_key_crypt_algo_oid_other, oid_len))) { + if (!status || (!libspdm_consttime_is_mem_equal(cert_public_key_crypt_algo_oid, + libspdm_public_key_crypt_algo_oid, oid_len) && + !libspdm_consttime_is_mem_equal(cert_public_key_crypt_algo_oid, + libspdm_public_key_crypt_algo_oid_other, + oid_len))) { return false; } @@ -596,18 +748,13 @@ static bool libspdm_verify_leaf_cert_basic_constraints(const uint8_t *cert, size { bool status; /*basic_constraints from cert*/ - uint8_t cert_basic_constraints[BASIC_CONSTRAINTS_CA_LEN]; + uint8_t cert_basic_constraints[LIBSPDM_MAX_BASIC_CONSTRAINTS_CA_LEN]; size_t len; - /*leaf cert basic_constraints case1: CA: false and CA object is excluded */ - #define BASIC_CONSTRAINTS_STRING_CASE1 {0x30, 0x00} - uint8_t basic_constraints_case1[] = BASIC_CONSTRAINTS_STRING_CASE1; - - /*leaf cert basic_constraints case2: CA: false */ - #define BASIC_CONSTRAINTS_STRING_CASE2 {0x30, 0x03, 0x01, 0x01, 0x00} - uint8_t basic_constraints_case2[] = BASIC_CONSTRAINTS_STRING_CASE2; + uint8_t basic_constraints_false_case1[] = BASIC_CONSTRAINTS_STRING_FALSE_CASE1; + uint8_t basic_constraints_false_case2[] = BASIC_CONSTRAINTS_STRING_FALSE_CASE2; - len = BASIC_CONSTRAINTS_CA_LEN; + len = LIBSPDM_MAX_BASIC_CONSTRAINTS_CA_LEN; status = libspdm_x509_get_extended_basic_constraints(cert, cert_size, cert_basic_constraints, &len); @@ -619,17 +766,17 @@ static bool libspdm_verify_leaf_cert_basic_constraints(const uint8_t *cert, size return false; } - if ((len == sizeof(basic_constraints_case1)) && - (!libspdm_const_compare_mem(cert_basic_constraints, - basic_constraints_case1, - sizeof(basic_constraints_case1)))) { + if ((len == sizeof(basic_constraints_false_case1)) && + (libspdm_consttime_is_mem_equal(cert_basic_constraints, + basic_constraints_false_case1, + sizeof(basic_constraints_false_case1)))) { return true; } - if ((len == sizeof(basic_constraints_case2)) && - (!libspdm_const_compare_mem(cert_basic_constraints, - basic_constraints_case2, - sizeof(basic_constraints_case2)))) { + if ((len == sizeof(basic_constraints_false_case2)) && + (libspdm_consttime_is_mem_equal(cert_basic_constraints, + basic_constraints_false_case2, + sizeof(basic_constraints_false_case2)))) { return true; } @@ -637,30 +784,165 @@ static bool libspdm_verify_leaf_cert_basic_constraints(const uint8_t *cert, size } /** - * Verify leaf cert extend spdm OID + * Verify leaf cert basic_constraints CA is false + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * + * @retval true verify pass,two case: 1.basic constraints is not present in cert; + * 2. cert basic_constraints CA is false; + * @retval false verify fail + **/ +static bool libspdm_verify_set_cert_leaf_cert_basic_constraints( + const uint8_t *cert, size_t cert_size, bool is_device_cert_model) +{ + bool status; + /*basic_constraints from cert*/ + uint8_t cert_basic_constraints[LIBSPDM_MAX_BASIC_CONSTRAINTS_CA_LEN]; + size_t len; + + uint8_t basic_constraints_false_case1[] = BASIC_CONSTRAINTS_STRING_FALSE_CASE1; + uint8_t basic_constraints_false_case2[] = BASIC_CONSTRAINTS_STRING_FALSE_CASE2; + uint8_t basic_constraints_true_case[] = BASIC_CONSTRAINTS_STRING_TRUE_CASE; + + len = LIBSPDM_MAX_BASIC_CONSTRAINTS_CA_LEN; + + status = libspdm_x509_get_extended_basic_constraints(cert, cert_size, + cert_basic_constraints, &len); + + if (is_device_cert_model) { + /*device cert model*/ + if (len == 0) { + /* basic constraints is not present in cert */ + return true; + } else if (!status ) { + return false; + } + + if ((len == sizeof(basic_constraints_false_case1)) && + (libspdm_consttime_is_mem_equal(cert_basic_constraints, + basic_constraints_false_case1, + sizeof(basic_constraints_false_case1)))) { + return true; + } + + if ((len == sizeof(basic_constraints_false_case2)) && + (libspdm_consttime_is_mem_equal(cert_basic_constraints, + basic_constraints_false_case2, + sizeof(basic_constraints_false_case2)))) { + return true; + } + } else { + /*alias cert model*/ + if (status && (len == sizeof(basic_constraints_true_case)) && + (libspdm_consttime_is_mem_equal(cert_basic_constraints, + basic_constraints_true_case, + sizeof(basic_constraints_true_case)))) { + return true; + } + } + + return false; +} + +/** + * Verify leaf cert spdm defined extended key usage * * @param[in] cert Pointer to the DER-encoded certificate data. * @param[in] cert_size The size of certificate data in bytes. + * @param[in] is_requester_cert Is the function verifying requester or responder cert. + * + * @retval true verify pass, two cases: + * 1. spdm defined eku is not present in cert; + * 2. spdm defined eku is compliant with requester/responder identity; + * @retval false verify fail, two cases: + * 1. requester's cert has only responder auth oid in eku; + * 2. responder's cert has only requester auth oid in eku; + **/ +static bool libspdm_verify_leaf_cert_spdm_eku(const uint8_t *cert, size_t cert_size, + bool is_requester_cert) +{ + bool status; + uint8_t eku[256]; + size_t eku_size; + size_t index; + bool req_auth_oid_find_success; + bool rsp_auth_oid_find_success; + + /* SPDM defined OID */ + uint8_t eku_requester_auth_oid[] = SPDM_OID_DMTF_EKU_REQUESTER_AUTH; + uint8_t eku_responder_auth_oid[] = SPDM_OID_DMTF_EKU_RESPONDER_AUTH; + + eku_size = sizeof(eku); + status = libspdm_x509_get_extended_key_usage(cert, cert_size, eku, &eku_size); + if (eku_size == 0) { + /* eku is not present in cert */ + return true; + } else if (!status ) { + return false; + } + + req_auth_oid_find_success = false; + rsp_auth_oid_find_success = false; + + for(index = 0; index <= eku_size - sizeof(eku_requester_auth_oid); index++) { + if (libspdm_consttime_is_mem_equal(eku + index, eku_requester_auth_oid, + sizeof(eku_requester_auth_oid))) { + req_auth_oid_find_success = true; + break; + } + } + + for(index = 0; index <= eku_size - sizeof(eku_responder_auth_oid); index++) { + if (libspdm_consttime_is_mem_equal(eku + index, eku_responder_auth_oid, + sizeof(eku_responder_auth_oid))) { + rsp_auth_oid_find_success = true; + break; + } + } + + if (is_requester_cert) { + /* it should not only contain responder auth oid */ + if (!req_auth_oid_find_success && rsp_auth_oid_find_success) { + return false; + } + } else { + /* it should not only contain requester auth oid */ + if (req_auth_oid_find_success && !rsp_auth_oid_find_success) { + return false; + } + } + + return true; +} + +/** + * Verify leaf cert spdm defined extension + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] is_requester_cert Is the function verifying requester or responder cert. * * @retval true verify pass * @retval false verify fail,two case: 1. return is not RETURN_SUCCESS or RETURN_NOT_FOUND; * 2. hardware_identity_oid is found in AliasCert model; **/ -static bool libspdm_verify_leaf_cert_eku_spdm_OID(const uint8_t *cert, size_t cert_size, - bool is_device_cert_model) +static bool libspdm_verify_leaf_cert_spdm_extension(const uint8_t *cert, size_t cert_size, + bool is_requester_cert, + bool is_device_cert_model) { bool status; bool find_sucessful; - uint8_t spdm_extension[SPDM_EXTENDSION_LEN]; + uint8_t spdm_extension[LIBSPDM_MAX_EXTENSION_LEN]; size_t index; size_t len; /* SPDM defined OID */ - uint8_t oid_spdm_extension[] = SPDM_OID_EXTENSION; - uint8_t hardware_identity_oid[] = SPDM_OID_HARDWARE_IDENTITY; + uint8_t oid_spdm_extension[] = SPDM_OID_DMTF_SPDM_EXTENSION; + uint8_t hardware_identity_oid[] = SPDM_OID_DMTF_HARDWARE_IDENTITY; - len = SPDM_EXTENDSION_LEN; + len = LIBSPDM_MAX_EXTENSION_LEN; if (cert == NULL || cert_size == 0) { return false; @@ -681,38 +963,41 @@ static bool libspdm_verify_leaf_cert_eku_spdm_OID(const uint8_t *cert, size_t ce /*find the spdm hardware identity OID*/ find_sucessful = false; for(index = 0; index <= len - sizeof(hardware_identity_oid); index++) { - if (!libspdm_const_compare_mem(spdm_extension + index, hardware_identity_oid, - sizeof(hardware_identity_oid))) { + if (libspdm_consttime_is_mem_equal(spdm_extension + index, hardware_identity_oid, + sizeof(hardware_identity_oid))) { find_sucessful = true; break; } } - if ((find_sucessful) && (!is_device_cert_model)) { - /* Hardware_identity_OID is found in alias cert model */ - return false; - } else { - return true; + /* Responder does not determine Requester's certificate model */ + if (!is_requester_cert) { + if ((find_sucessful) && (!is_device_cert_model)) { + /* Hardware_identity_OID is found in alias cert model */ + return false; + } } + + return true; } /** - * Certificate Check for SPDM leaf cert. + * Certificate common Check for SPDM leaf cert when get_cert and set_cert. * * @param[in] cert Pointer to the DER-encoded certificate data. * @param[in] cert_size The size of certificate data in bytes. * @param[in] base_asym_algo SPDM base_asym_algo * @param[in] base_hash_algo SPDM base_hash_algo - * @param[in] is_device_cert_model If true, the cert chain is DeviceCert model; - * If false, the cert chain is AliasCert model; + * @param[in] is_requester_cert Is the function verifying requester or responder cert. + * @param[in] is_device_cert_model If true, the local endpoint uses the DeviceCert model. + * If false, the local endpoint uses the AliasCert model. * * @retval true Success. - * @retval false Certificate is not valid + * @retval false Certificate is not valid. **/ -bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, - uint32_t base_asym_algo, - uint32_t base_hash_algo, - bool is_device_cert_model) +bool libspdm_x509_common_certificate_check(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_requester_cert, bool is_device_cert_model) { uint8_t end_cert_from[64]; size_t end_cert_from_len; @@ -807,32 +1092,91 @@ bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, goto cleanup; } - /* 9. verify SPDM extension OID*/ - status = libspdm_verify_leaf_cert_eku_spdm_OID(cert, cert_size, is_device_cert_model); + /* 9. verify spdm defined extended key usage*/ + status = libspdm_verify_leaf_cert_spdm_eku(cert, cert_size, is_requester_cert); if (!status) { goto cleanup; } - /* 10. verify basic constraints*/ - status = libspdm_verify_leaf_cert_basic_constraints(cert, cert_size); + /* 10. verify spdm defined extension*/ + status = libspdm_verify_leaf_cert_spdm_extension(cert, cert_size, + is_requester_cert, is_device_cert_model); if (!status) { goto cleanup; } - /* 11. extended_key_usage*/ - value = 0; - status = libspdm_x509_get_extended_key_usage(cert, cert_size, NULL, &value); - if (value == 0) { - status = false; - goto cleanup; - } - status = true; - cleanup: libspdm_asym_free(base_asym_algo, context); return status; } +/** + * Certificate Check for SPDM leaf cert when get_cert command + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in] base_hash_algo SPDM base_hash_algo + * @param[in] is_requester_cert Is the function verifying requester or responder cert. + * @param[in] is_device_cert_model If true, the local endpoint uses the DeviceCert model. + * If false, the local endpoint uses the AliasCert model. + * + * @retval true Success. + * @retval false Certificate is not valid + **/ +bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo, + uint32_t base_hash_algo, + bool is_requester_cert, + bool is_device_cert_model) +{ + bool status; + + status = libspdm_x509_common_certificate_check(cert, cert_size, base_asym_algo, + base_hash_algo, is_requester_cert, + is_device_cert_model); + if (!status) { + return false; + } + + /* verify basic constraints: the leaf cert always is ca:fasle in get_cert*/ + status = libspdm_verify_leaf_cert_basic_constraints(cert, cert_size); + return status; +} + +/** + * Certificate Check for SPDM leaf cert when set_cert command. + * + * @param[in] cert Pointer to the DER-encoded certificate data. + * @param[in] cert_size The size of certificate data in bytes. + * @param[in] base_asym_algo SPDM base_asym_algo + * @param[in] base_hash_algo SPDM base_hash_algo + * @param[in] is_requester_cert Is the function verifying requester or responder cert. + * @param[in] is_device_cert_model If true, the local endpoint uses the DeviceCert model. + * If false, the local endpoint uses the AliasCert model. + * + * @retval true Success. + * @retval false Certificate is not valid. + **/ +bool libspdm_x509_set_cert_certificate_check(const uint8_t *cert, size_t cert_size, + uint32_t base_asym_algo, uint32_t base_hash_algo, + bool is_requester_cert, bool is_device_cert_model) +{ + bool status; + + status = libspdm_x509_common_certificate_check(cert, cert_size, base_asym_algo, + base_hash_algo, is_requester_cert, + is_device_cert_model); + if (!status) { + return false; + } + + /* verify basic constraints: need check with is_device_cert_model*/ + status = libspdm_verify_set_cert_leaf_cert_basic_constraints( + cert, cert_size, is_device_cert_model); + return status; +} + /** * Return certificate is root cert or not. * Certificate is considered as a root certificate if the subjectname equal issuername. @@ -845,9 +1189,9 @@ bool libspdm_x509_certificate_check(const uint8_t *cert, size_t cert_size, **/ bool libspdm_is_root_certificate(const uint8_t *cert, size_t cert_size) { - uint8_t issuer_name[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; + uint8_t issuer_name[LIBSPDM_MAX_NAME_SIZE]; size_t issuer_name_len; - uint8_t subject_name[LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE]; + uint8_t subject_name[LIBSPDM_MAX_NAME_SIZE]; size_t subject_name_len; bool result; @@ -856,14 +1200,14 @@ bool libspdm_is_root_certificate(const uint8_t *cert, size_t cert_size) } /* 1. issuer_name*/ - issuer_name_len = LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE; + issuer_name_len = sizeof(issuer_name); result = libspdm_x509_get_issuer_name(cert, cert_size, issuer_name, &issuer_name_len); if (!result) { return false; } /* 2. subject_name*/ - subject_name_len = LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE; + subject_name_len = sizeof(subject_name); result = libspdm_x509_get_subject_name(cert, cert_size, subject_name, &subject_name_len); if (!result) { return false; @@ -872,7 +1216,7 @@ bool libspdm_is_root_certificate(const uint8_t *cert, size_t cert_size) if (issuer_name_len != subject_name_len) { return false; } - if (libspdm_const_compare_mem(issuer_name, subject_name, issuer_name_len) != 0) { + if (!libspdm_consttime_is_mem_equal(issuer_name, subject_name, issuer_name_len)) { return false; } @@ -1056,8 +1400,9 @@ bool libspdm_get_dmtf_subject_alt_name(const uint8_t *cert, const size_t cert_si * * @param cert_chain_data The certificate chain data without spdm_cert_chain_t header. * @param cert_chain_data_size size in bytes of the certificate chain data. - * @param base_hash_algo SPDM base_hash_algo * @param base_asym_algo SPDM base_asym_algo + * @param base_hash_algo SPDM base_hash_algo + * @param is_requester_cert Is the function verifying requester or responder cert. * @param is_device_cert_model If true, the cert chain is DeviceCert model; * If false, the cert chain is AliasCert model; * @@ -1066,7 +1411,7 @@ bool libspdm_get_dmtf_subject_alt_name(const uint8_t *cert, const size_t cert_si **/ bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_data_size, uint32_t base_asym_algo, uint32_t base_hash_algo, - bool is_device_cert_model) + bool is_requester_cert, bool is_device_cert_model) { const uint8_t *root_cert_buffer; size_t root_cert_buffer_size; @@ -1105,7 +1450,7 @@ bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_ if (!libspdm_x509_certificate_check(leaf_cert_buffer, leaf_cert_buffer_size, base_asym_algo, base_hash_algo, - is_device_cert_model)) { + is_requester_cert, is_device_cert_model)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! VerifyCertificateChainData - FAIL (leaf certificate check failed)!!!\n")); return false; @@ -1117,6 +1462,7 @@ bool libspdm_verify_cert_chain_data(uint8_t *cert_chain_data, size_t cert_chain_ bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t base_asym_algo, const void *cert_chain_buffer, size_t cert_chain_buffer_size, + bool is_requester_cert, bool is_device_cert_model) { const uint8_t *cert_chain_data; @@ -1163,9 +1509,9 @@ bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t b "!!! VerifyCertificateChainBuffer - FAIL (hash calculation fail) !!!\n")); return false; } - if (libspdm_const_compare_mem((const uint8_t *)cert_chain_buffer + - sizeof(spdm_cert_chain_t), - calc_root_cert_hash, hash_size) != 0) { + if (!libspdm_consttime_is_mem_equal((const uint8_t *)cert_chain_buffer + + sizeof(spdm_cert_chain_t), + calc_root_cert_hash, hash_size)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! VerifyCertificateChainBuffer - FAIL (cert root hash mismatch) !!!\n")); return false; @@ -1196,7 +1542,7 @@ bool libspdm_verify_certificate_chain_buffer(uint32_t base_hash_algo, uint32_t b if (!libspdm_x509_certificate_check(leaf_cert_buffer, leaf_cert_buffer_size, base_asym_algo, base_hash_algo, - is_device_cert_model)) { + is_requester_cert, is_device_cert_model)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! VerifyCertificateChainBuffer - FAIL (leaf certificate check failed)!!!\n")); return false; @@ -1323,3 +1669,5 @@ bool libspdm_verify_req_info(uint8_t *req_info, uint16_t req_info_len) return false; } } + +#endif diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c similarity index 73% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c index 72adf085c8..4f8db50d26 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c @@ -17,19 +17,47 @@ uint32_t libspdm_get_dhe_pub_key_size(uint16_t dhe_named_group) { switch (dhe_named_group) { case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: +#if LIBSPDM_FFDHE_2048_SUPPORT return 256; +#else + return 0; +#endif case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: +#if LIBSPDM_FFDHE_3072_SUPPORT return 384; +#else + return 0; +#endif case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: +#if LIBSPDM_FFDHE_4096_SUPPORT return 512; +#else + return 0; +#endif case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1: +#if LIBSPDM_ECDHE_P256_SUPPORT return 32 * 2; +#else + return 0; +#endif case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: +#if LIBSPDM_ECDHE_P384_SUPPORT return 48 * 2; +#else + return 0; +#endif case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: +#if LIBSPDM_ECDHE_P521_SUPPORT return 66 * 2; +#else + return 0; +#endif case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: +#if LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT return 32 * 2; +#else + return 0; +#endif default: return 0; } @@ -68,7 +96,14 @@ void *libspdm_dhe_new(spdm_version_number_t spdm_version, uint16_t dhe_named_group, bool is_initiator) { size_t nid; +#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT void *context; + bool result; + uint8_t spdm12_key_change_requester_context[ + SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE]; + uint8_t spdm12_key_change_responder_context[ + SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE]; +#endif /* LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT */ nid = libspdm_get_dhe_nid(dhe_named_group); if (nid == 0) { @@ -80,7 +115,16 @@ void *libspdm_dhe_new(spdm_version_number_t spdm_version, case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: #if LIBSPDM_FFDHE_SUPPORT - context = libspdm_dh_new_by_nid(nid); +#if !LIBSPDM_FFDHE_2048_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048); +#endif +#if !LIBSPDM_FFDHE_3072_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072); +#endif +#if !LIBSPDM_FFDHE_4096_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096); +#endif + return libspdm_dh_new_by_nid(nid); #else LIBSPDM_ASSERT(false); return NULL; @@ -90,7 +134,16 @@ void *libspdm_dhe_new(spdm_version_number_t spdm_version, case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: #if LIBSPDM_ECDHE_SUPPORT - context = libspdm_ec_new_by_nid(nid); +#if !LIBSPDM_ECDHE_P256_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1); +#endif +#if !LIBSPDM_ECDHE_P384_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1); +#endif +#if !LIBSPDM_ECDHE_P521_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1); +#endif + return libspdm_ec_new_by_nid(nid); #else LIBSPDM_ASSERT(false); return NULL; @@ -99,23 +152,6 @@ void *libspdm_dhe_new(spdm_version_number_t spdm_version, case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256: #if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT context = libspdm_sm2_key_exchange_new_by_nid(nid); -#else - LIBSPDM_ASSERT(false); - return NULL; -#endif - break; - default: - LIBSPDM_ASSERT(false); - return NULL; - } - -#if LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT - if (dhe_named_group == SPDM_ALGORITHMS_DHE_NAMED_GROUP_SM2_P256) { - bool result; - uint8_t spdm12_key_change_requester_context[ - SPDM_VERSION_1_2_KEY_EXCHANGE_REQUESTER_CONTEXT_SIZE]; - uint8_t spdm12_key_change_responder_context[ - SPDM_VERSION_1_2_KEY_EXCHANGE_RESPONDER_CONTEXT_SIZE]; libspdm_copy_mem(spdm12_key_change_requester_context, sizeof(spdm12_key_change_requester_context), @@ -141,14 +177,23 @@ void *libspdm_dhe_new(spdm_version_number_t spdm_version, libspdm_sm2_key_exchange_free (context); return NULL; } + return context; +#else + LIBSPDM_ASSERT(false); + return NULL; +#endif + break; + default: + LIBSPDM_ASSERT(false); + return NULL; } -#endif /* LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT */ - - return context; } void libspdm_dhe_free(uint16_t dhe_named_group, void *context) { + if (context == NULL) { + return; + } switch (dhe_named_group) { case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048: case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: @@ -190,6 +235,15 @@ bool libspdm_dhe_generate_key(uint16_t dhe_named_group, void *context, case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: #if LIBSPDM_FFDHE_SUPPORT +#if !LIBSPDM_FFDHE_2048_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048); +#endif +#if !LIBSPDM_FFDHE_3072_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072); +#endif +#if !LIBSPDM_FFDHE_4096_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096); +#endif return libspdm_dh_generate_key(context, public_key, public_key_size); #else LIBSPDM_ASSERT(false); @@ -199,6 +253,15 @@ bool libspdm_dhe_generate_key(uint16_t dhe_named_group, void *context, case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: #if LIBSPDM_ECDHE_SUPPORT +#if !LIBSPDM_ECDHE_P256_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1); +#endif +#if !LIBSPDM_ECDHE_P384_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1); +#endif +#if !LIBSPDM_ECDHE_P521_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1); +#endif return libspdm_ec_generate_key(context, public_key, public_key_size); #else LIBSPDM_ASSERT(false); @@ -231,6 +294,15 @@ bool libspdm_dhe_compute_key(uint16_t dhe_named_group, void *context, case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072: case SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096: #if LIBSPDM_FFDHE_SUPPORT +#if !LIBSPDM_FFDHE_2048_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_2048); +#endif +#if !LIBSPDM_FFDHE_3072_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_3072); +#endif +#if !LIBSPDM_FFDHE_4096_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_FFDHE_4096); +#endif return libspdm_dh_compute_key(context, peer_public, peer_public_size, key, key_size); #else LIBSPDM_ASSERT(false); @@ -240,6 +312,15 @@ bool libspdm_dhe_compute_key(uint16_t dhe_named_group, void *context, case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1: case SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1: #if LIBSPDM_ECDHE_SUPPORT +#if !LIBSPDM_ECDHE_P256_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_256_R1); +#endif +#if !LIBSPDM_ECDHE_P384_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_384_R1); +#endif +#if !LIBSPDM_ECDHE_P521_SUPPORT + LIBSPDM_ASSERT(dhe_named_group != SPDM_ALGORITHMS_DHE_NAMED_GROUP_SECP_521_R1); +#endif return libspdm_ec_compute_key(context, peer_public, peer_public_size, key, key_size); #else LIBSPDM_ASSERT(false); diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hash.c similarity index 96% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hash.c index e5a31fd599..44f3a25732 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hash.c @@ -10,16 +10,47 @@ uint32_t libspdm_get_hash_size(uint32_t base_hash_algo) { switch (base_hash_algo) { case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: +#if LIBSPDM_SHA256_SUPPORT + return 32; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256: +#if LIBSPDM_SHA3_256_SUPPORT return 32; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384: +#if LIBSPDM_SHA384_SUPPORT + return 48; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384: +#if LIBSPDM_SHA3_384_SUPPORT return 48; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512: +#if LIBSPDM_SHA512_SUPPORT + return 64; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512: +#if LIBSPDM_SHA3_512_SUPPORT return 64; +#else + return 0; +#endif case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SM3_256: +#if LIBSPDM_SM3_256_SUPPORT return 32; +#else + return 0; +#endif default: return 0; } @@ -107,6 +138,9 @@ void *libspdm_hash_new(uint32_t base_hash_algo) void libspdm_hash_free(uint32_t base_hash_algo, void *hash_context) { + if (hash_context == NULL) { + return; + } switch (base_hash_algo) { case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: #if LIBSPDM_SHA256_SUPPORT diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c similarity index 99% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c index d68b52b55c..56f8b0efea 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c @@ -66,6 +66,9 @@ void *libspdm_hmac_new(uint32_t base_hash_algo) void libspdm_hmac_free(uint32_t base_hash_algo, void *hmac_ctx) { + if (hmac_ctx == NULL) { + return; + } switch (base_hash_algo) { case SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256: #if LIBSPDM_SHA256_SUPPORT diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_rng.c similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_rng.c diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_common.c similarity index 83% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_common.c index 7400f2bd1b..f900634c96 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_common.c @@ -6,12 +6,28 @@ #include "internal/libspdm_requester_lib.h" -uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context) +uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context, bool use_psk) { uint16_t req_session_id; libspdm_session_info_t *session_info; size_t index; + if (use_psk) { + if ((spdm_context->max_psk_session_count != 0) && + (spdm_context->current_psk_session_count >= spdm_context->max_psk_session_count)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_allocate_req_session_id - MAX PSK session\n")); + return (INVALID_SESSION_ID & 0xFFFF); + } + } else { + if ((spdm_context->max_dhe_session_count != 0) && + (spdm_context->current_dhe_session_count >= spdm_context->max_dhe_session_count)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + "libspdm_allocate_req_session_id - MAX DHE session\n")); + return (INVALID_SESSION_ID & 0xFFFF); + } + } + session_info = spdm_context->session_info; for (index = 0; index < LIBSPDM_MAX_SESSION_COUNT; index++) { if ((session_info[index].session_id & 0xFFFF) == (INVALID_SESSION_ID & 0xFFFF)) { @@ -24,32 +40,26 @@ uint16_t libspdm_allocate_req_session_id(libspdm_context_t *spdm_context) return (INVALID_SESSION_ID & 0xFFFF); } -libspdm_return_t libspdm_build_opaque_data_supported_version_data(libspdm_context_t *spdm_context, - size_t *data_out_size, - void *data_out) +void libspdm_build_opaque_data_supported_version_data(libspdm_context_t *spdm_context, + size_t *data_out_size, + void *data_out) { size_t final_data_size; - secured_message_general_opaque_data_table_header_t - *general_opaque_data_table_header; - spdm_general_opaque_data_table_header_t - *spdm_general_opaque_data_table_header; - secured_message_opaque_element_table_header_t - *opaque_element_table_header; - secured_message_opaque_element_supported_version_t - *opaque_element_support_version; + secured_message_general_opaque_data_table_header_t *general_opaque_data_table_header; + spdm_general_opaque_data_table_header_t *spdm_general_opaque_data_table_header; + secured_message_opaque_element_table_header_t *opaque_element_table_header; + secured_message_opaque_element_supported_version_t *opaque_element_support_version; spdm_version_number_t *versions_list; void *end; if (spdm_context->local_context.secured_message_version.spdm_version_count == 0) { *data_out_size = 0; - return LIBSPDM_STATUS_SUCCESS; + return; } final_data_size = libspdm_get_opaque_data_supported_version_data_size(spdm_context); - if (*data_out_size < final_data_size) { - *data_out_size = final_data_size; - return LIBSPDM_STATUS_BUFFER_TOO_SMALL; - } + LIBSPDM_ASSERT(*data_out_size >= final_data_size); + if (libspdm_get_connection_version (spdm_context) >= SPDM_MESSAGE_VERSION_12) { spdm_general_opaque_data_table_header = data_out; spdm_general_opaque_data_table_header->total_elements = 1; @@ -89,8 +99,6 @@ libspdm_return_t libspdm_build_opaque_data_supported_version_data(libspdm_contex /* Zero Padding. *data_out_size does not need to be changed, because data is 0 padded */ end = versions_list + spdm_context->local_context.secured_message_version.spdm_version_count; libspdm_zero_mem(end, (size_t)data_out + final_data_size - (size_t)end); - - return LIBSPDM_STATUS_SUCCESS; } /** diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_communication.c similarity index 68% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_communication.c index f9f1fbbbe8..b4af076992 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_communication.c @@ -6,24 +6,24 @@ #include "internal/libspdm_requester_lib.h" -libspdm_return_t libspdm_init_connection(void *context, bool get_version_only) +libspdm_return_t libspdm_init_connection(void *spdm_context, bool get_version_only) { libspdm_return_t status; - libspdm_context_t *spdm_context; + libspdm_context_t *context; - spdm_context = context; + context = spdm_context; - status = libspdm_get_version(spdm_context, NULL, NULL); + status = libspdm_get_version(context, NULL, NULL); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } if (!get_version_only) { - status = libspdm_get_capabilities(spdm_context); + status = libspdm_get_capabilities(context); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - status = libspdm_negotiate_algorithms(spdm_context); + status = libspdm_negotiate_algorithms(context); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } @@ -31,8 +31,10 @@ libspdm_return_t libspdm_init_connection(void *context, bool get_version_only) return LIBSPDM_STATUS_SUCCESS; } -#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) -libspdm_return_t libspdm_start_session(void *context, bool use_psk, +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) +libspdm_return_t libspdm_start_session(void *spdm_context, bool use_psk, + const void *psk_hint, + uint16_t psk_hint_size, uint8_t measurement_hash_type, uint8_t slot_id, uint8_t session_policy, @@ -41,20 +43,20 @@ libspdm_return_t libspdm_start_session(void *context, bool use_psk, void *measurement_hash) { libspdm_return_t status; - libspdm_context_t *spdm_context; + libspdm_context_t *context; #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP libspdm_session_info_t *session_info; uint8_t req_slot_id_param; #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ - spdm_context = context; + context = spdm_context; status = LIBSPDM_STATUS_UNSUPPORTED_CAP; if (!use_psk) { #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP status = libspdm_send_receive_key_exchange( - spdm_context, measurement_hash_type, slot_id, session_policy, + context, measurement_hash_type, slot_id, session_policy, session_id, heartbeat_period, &req_slot_id_param, measurement_hash); if (LIBSPDM_STATUS_IS_ERROR(status)) { @@ -64,7 +66,7 @@ libspdm_return_t libspdm_start_session(void *context, bool use_psk, return status; } - session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + session_info = libspdm_get_session_info_via_session_id(context, *session_id); if (session_info == NULL) { LIBSPDM_ASSERT(false); return LIBSPDM_STATUS_INVALID_STATE_LOCAL; @@ -83,9 +85,9 @@ libspdm_return_t libspdm_start_session(void *context, bool use_psk, break; case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST: case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS: -#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) status = libspdm_encapsulated_request( - spdm_context, session_id, + context, session_id, session_info->mut_auth_requested, &req_slot_id_param); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, @@ -98,7 +100,7 @@ libspdm_return_t libspdm_start_session(void *context, bool use_psk, "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", session_info->mut_auth_requested)); return LIBSPDM_STATUS_INVALID_MSG_FIELD; -#endif +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) */ break; default: LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, @@ -110,7 +112,7 @@ libspdm_return_t libspdm_start_session(void *context, bool use_psk, if (req_slot_id_param == 0xF) { req_slot_id_param = 0xFF; } - status = libspdm_send_receive_finish(spdm_context, *session_id, req_slot_id_param); + status = libspdm_send_receive_finish(context, *session_id, req_slot_id_param); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_start_session - libspdm_send_receive_finish - %p\n", status)); #else /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ @@ -118,9 +120,10 @@ libspdm_return_t libspdm_start_session(void *context, bool use_psk, return LIBSPDM_STATUS_UNSUPPORTED_CAP; #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ } else { - #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + #if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP status = libspdm_send_receive_psk_exchange( - spdm_context, measurement_hash_type, session_policy, session_id, + context, psk_hint, psk_hint_size, + measurement_hash_type, session_policy, session_id, heartbeat_period, measurement_hash); if (LIBSPDM_STATUS_IS_ERROR(status)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, @@ -131,19 +134,21 @@ libspdm_return_t libspdm_start_session(void *context, bool use_psk, /* send PSK_FINISH only if Responder supports context.*/ if (libspdm_is_capabilities_flag_supported( - spdm_context, true, 0, + context, true, 0, SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER_WITH_CONTEXT)) { - status = libspdm_send_receive_psk_finish(spdm_context, *session_id); + status = libspdm_send_receive_psk_finish(context, *session_id); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_start_session - libspdm_send_receive_psk_finish - %p\n", status)); } - #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP*/ } return status; } -libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, +libspdm_return_t libspdm_start_session_ex(void *spdm_context, bool use_psk, + const void *psk_hint, + uint16_t psk_hint_size, uint8_t measurement_hash_type, uint8_t slot_id, uint8_t session_policy, @@ -155,17 +160,21 @@ libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, void *requester_random, size_t *requester_random_size, void *responder_random, - size_t *responder_random_size) + size_t *responder_random_size, + const void *requester_opaque_data, + size_t requester_opaque_data_size, + void *responder_opaque_data, + size_t *responder_opaque_data_size) { libspdm_return_t status; - libspdm_context_t *spdm_context; + libspdm_context_t *context; #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP libspdm_session_info_t *session_info; uint8_t req_slot_id_param; #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP */ - spdm_context = context; + context = spdm_context; status = LIBSPDM_STATUS_UNSUPPORTED_CAP; if (!use_psk) { @@ -177,10 +186,12 @@ libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, LIBSPDM_ASSERT ( responder_random_size == NULL || *responder_random_size == SPDM_RANDOM_DATA_SIZE); status = libspdm_send_receive_key_exchange_ex( - spdm_context, measurement_hash_type, slot_id, session_policy, + context, measurement_hash_type, slot_id, session_policy, session_id, heartbeat_period, &req_slot_id_param, measurement_hash, requester_random_in, - requester_random, responder_random); + requester_random, responder_random, + requester_opaque_data, requester_opaque_data_size, + responder_opaque_data, responder_opaque_data_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_start_session - libspdm_send_receive_key_exchange - %p\n", @@ -188,7 +199,7 @@ libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, return status; } - session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); + session_info = libspdm_get_session_info_via_session_id(context, *session_id); if (session_info == NULL) { LIBSPDM_ASSERT(false); return LIBSPDM_STATUS_INVALID_STATE_LOCAL; @@ -207,9 +218,9 @@ libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, break; case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST: case SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS: -#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) || (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) status = libspdm_encapsulated_request( - spdm_context, session_id, + context, session_id, session_info->mut_auth_requested, &req_slot_id_param); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, @@ -222,7 +233,7 @@ libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, "libspdm_start_session - unsupported mut_auth_requested - 0x%x\n", session_info->mut_auth_requested)); return LIBSPDM_STATUS_INVALID_MSG_FIELD; -#endif +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) */ break; default: LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, @@ -234,7 +245,7 @@ libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, if (req_slot_id_param == 0xF) { req_slot_id_param = 0xFF; } - status = libspdm_send_receive_finish(spdm_context, *session_id, req_slot_id_param); + status = libspdm_send_receive_finish(context, *session_id, req_slot_id_param); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_start_session - libspdm_send_receive_finish - %p\n", status)); #else /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ @@ -242,13 +253,16 @@ libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, return LIBSPDM_STATUS_UNSUPPORTED_CAP; #endif /* LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP*/ } else { - #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + #if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP status = libspdm_send_receive_psk_exchange_ex( - spdm_context, measurement_hash_type, session_policy, session_id, + context, psk_hint, psk_hint_size, + measurement_hash_type, session_policy, session_id, heartbeat_period, measurement_hash, requester_random_in, requester_random_in_size, requester_random, requester_random_size, - responder_random, responder_random_size); + responder_random, responder_random_size, + requester_opaque_data, requester_opaque_data_size, + responder_opaque_data, responder_opaque_data_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_start_session - libspdm_send_receive_psk_exchange - %p\n", @@ -258,97 +272,105 @@ libspdm_return_t libspdm_start_session_ex(void *context, bool use_psk, /* send PSK_FINISH only if Responder supports context.*/ if (libspdm_is_capabilities_flag_supported( - spdm_context, true, 0, + context, true, 0, SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_PSK_CAP_RESPONDER_WITH_CONTEXT)) { - status = libspdm_send_receive_psk_finish(spdm_context, *session_id); + status = libspdm_send_receive_psk_finish(context, *session_id); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_start_session - libspdm_send_receive_psk_finish - %p\n", status)); } - #else /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + #else /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP*/ LIBSPDM_ASSERT(false); return LIBSPDM_STATUS_UNSUPPORTED_CAP; - #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP*/ + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP*/ } return status; } -libspdm_return_t libspdm_stop_session(void *context, uint32_t session_id, +libspdm_return_t libspdm_stop_session(void *spdm_context, uint32_t session_id, uint8_t end_session_attributes) { libspdm_return_t status; - libspdm_context_t *spdm_context; + libspdm_context_t *context; - spdm_context = context; + context = spdm_context; - status = libspdm_send_receive_end_session(spdm_context, session_id, end_session_attributes); + status = libspdm_send_receive_end_session(context, session_id, end_session_attributes); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_stop_session - %p\n", status)); return status; } -#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) */ -libspdm_return_t libspdm_send_receive_data(void *context, const uint32_t *session_id, - bool is_app_message, - const void *request, size_t request_size, - void *response, - size_t *response_size) +libspdm_return_t libspdm_send_data(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + const void *request, size_t request_size) { libspdm_return_t status; - libspdm_context_t *spdm_context; + libspdm_context_t *context; spdm_message_header_t *spdm_request; size_t spdm_request_size; - spdm_error_response_t *spdm_response; - size_t spdm_response_size; uint8_t *message; size_t message_size; size_t transport_header_size; - spdm_context = context; - spdm_response = response; + context = spdm_context; + transport_header_size = context->local_context.capability.transport_header_size; - transport_header_size = spdm_context->transport_get_header_size(spdm_context); - status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + status = libspdm_acquire_sender_buffer(context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + context->local_context.capability.transport_tail_size; libspdm_copy_mem (spdm_request, spdm_request_size, request, request_size); spdm_request_size = request_size; - status = libspdm_send_request(spdm_context, session_id, is_app_message, + status = libspdm_send_request(context, session_id, is_app_message, spdm_request_size, spdm_request); - if (LIBSPDM_STATUS_IS_ERROR(status)) { - libspdm_release_sender_buffer (spdm_context); - return status; - } - libspdm_release_sender_buffer (spdm_context); - /* receive */ + libspdm_release_sender_buffer(context); - status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + return status; +} + +libspdm_return_t libspdm_receive_data(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + void *response, size_t *response_size) +{ + libspdm_return_t status; + libspdm_context_t *context; + spdm_error_response_t *spdm_response; + size_t spdm_response_size; + uint8_t *message; + size_t message_size; + + context = spdm_context; + + status = libspdm_acquire_receiver_buffer(context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); spdm_response_size = message_size; - status = libspdm_receive_response(spdm_context, session_id, is_app_message, + status = libspdm_receive_response(context, session_id, is_app_message, &spdm_response_size, (void **)&spdm_response); if (LIBSPDM_STATUS_IS_ERROR(status)) { - libspdm_release_receiver_buffer (spdm_context); + libspdm_release_receiver_buffer (context); return status; } if (spdm_response->header.request_response_code == SPDM_ERROR) { if ((spdm_response->header.param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) && (session_id != NULL)) { - libspdm_free_session_id(spdm_context, *session_id); - libspdm_release_receiver_buffer (spdm_context); + libspdm_free_session_id(context, *session_id); + libspdm_release_receiver_buffer (context); return LIBSPDM_STATUS_SESSION_MSG_ERROR; } } @@ -358,11 +380,27 @@ libspdm_return_t libspdm_send_receive_data(void *context, const uint32_t *sessio *response_size = spdm_response_size; } else { *response_size = spdm_response_size; - libspdm_release_receiver_buffer (spdm_context); + libspdm_release_receiver_buffer (context); return LIBSPDM_STATUS_BUFFER_TOO_SMALL; } - libspdm_release_receiver_buffer (spdm_context); + libspdm_release_receiver_buffer(context); return LIBSPDM_STATUS_SUCCESS; } + +libspdm_return_t libspdm_send_receive_data(void *spdm_context, const uint32_t *session_id, + bool is_app_message, + const void *request, size_t request_size, + void *response, size_t *response_size) +{ + libspdm_return_t status; + + status = libspdm_send_data(spdm_context, session_id, is_app_message, request, request_size); + + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + + return libspdm_receive_data(spdm_context, session_id, is_app_message, response, response_size); +} diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_certificate.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_certificate.c new file mode 100644 index 0000000000..a37c32c297 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_certificate.c @@ -0,0 +1,139 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) && \ + (LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) + +libspdm_return_t libspdm_get_encap_response_certificate(void *spdm_context, + size_t request_size, + void *request, + size_t *response_size, + void *response) +{ + spdm_get_certificate_request_t *spdm_request; + spdm_certificate_response_t *spdm_response; + uint16_t offset; + uint16_t length; + size_t remainder_length; + uint8_t slot_id; + libspdm_context_t *context; + libspdm_return_t status; + size_t response_capacity; + + context = spdm_context; + spdm_request = request; + + if (libspdm_get_connection_version(context) < SPDM_MESSAGE_VERSION_11) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSUPPORTED_REQUEST, + 0, response_size, response); + } + + if (spdm_request->header.spdm_version != libspdm_get_connection_version(context)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_VERSION_MISMATCH, + 0, response_size, response); + } + + if (!libspdm_is_capabilities_flag_supported( + context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP, 0)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSUPPORTED_REQUEST, + SPDM_GET_CERTIFICATE, response_size, response); + } + + if (request_size < sizeof(spdm_get_certificate_request_t)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + + slot_id = spdm_request->header.param1; + + if (slot_id >= SPDM_MAX_SLOT_COUNT) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + + if (context->local_context + .local_cert_chain_provision[slot_id] == NULL) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSPECIFIED, + 0, response_size, response); + } + + offset = spdm_request->offset; + length = spdm_request->length; + if (length > LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN) { + length = LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN; + } + + if (offset >= context->local_context + .local_cert_chain_provision_size[slot_id]) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + + if ((size_t)(offset + length) > + context->local_context + .local_cert_chain_provision_size[slot_id]) { + length = (uint16_t)( + context->local_context + .local_cert_chain_provision_size[slot_id] - + offset); + } + remainder_length = context->local_context + .local_cert_chain_provision_size[slot_id] - + (length + offset); + + libspdm_reset_message_buffer_via_request_code(context, NULL, + spdm_request->header.request_response_code); + + LIBSPDM_ASSERT(*response_size >= sizeof(spdm_certificate_response_t) + length); + response_capacity = *response_size; + *response_size = sizeof(spdm_certificate_response_t) + length; + libspdm_zero_mem(response, *response_size); + spdm_response = response; + + spdm_response->header.spdm_version = spdm_request->header.spdm_version; + spdm_response->header.request_response_code = SPDM_CERTIFICATE; + spdm_response->header.param1 = slot_id; + spdm_response->header.param2 = 0; + spdm_response->portion_length = length; + spdm_response->remainder_length = (uint16_t)remainder_length; + libspdm_copy_mem(spdm_response + 1, + response_capacity - sizeof(spdm_certificate_response_t), + (const uint8_t *)context->local_context + .local_cert_chain_provision[slot_id] + offset, + length); + + /* Cache*/ + + status = libspdm_append_message_mut_b(context, spdm_request, + request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSPECIFIED, 0, + response_size, response); + } + + status = libspdm_append_message_mut_b(context, spdm_response, + *response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSPECIFIED, 0, + response_size, response); + } + + return LIBSPDM_STATUS_SUCCESS; +} + +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (..) */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_digests.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_digests.c new file mode 100644 index 0000000000..c5ac296345 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_digests.c @@ -0,0 +1,116 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP) && \ + (LIBSPDM_ENABLE_CAPABILITY_CERT_CAP) + +libspdm_return_t libspdm_get_encap_response_digest(void *spdm_context, + size_t request_size, + void *request, + size_t *response_size, + void *response) +{ + spdm_get_digest_request_t *spdm_request; + spdm_digest_response_t *spdm_response; + size_t index; + uint32_t hash_size; + uint8_t *digest; + libspdm_context_t *context; + libspdm_return_t status; + bool result; + /*total populated solt count*/ + uint8_t slot_count; + /*populated solt index*/ + uint8_t slot_index; + + context = spdm_context; + spdm_request = request; + + if (libspdm_get_connection_version(context) < SPDM_MESSAGE_VERSION_11) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSUPPORTED_REQUEST, + 0, response_size, response); + } + + if (spdm_request->header.spdm_version != libspdm_get_connection_version(context)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_VERSION_MISMATCH, + 0, response_size, response); + } + + if (!libspdm_is_capabilities_flag_supported( + context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CERT_CAP, 0)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSUPPORTED_REQUEST, + SPDM_GET_DIGESTS, response_size, response); + } + + if (request_size < sizeof(spdm_get_digest_request_t)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + + libspdm_reset_message_buffer_via_request_code(context, NULL, + spdm_request->header.request_response_code); + + hash_size = libspdm_get_hash_size( + context->connection_info.algorithm.base_hash_algo); + + slot_count = libspdm_get_cert_slot_count(context); + LIBSPDM_ASSERT(*response_size >= + sizeof(spdm_digest_response_t) + hash_size * slot_count); + *response_size = sizeof(spdm_digest_response_t) + hash_size * slot_count; + libspdm_zero_mem(response, *response_size); + spdm_response = response; + + spdm_response->header.spdm_version = spdm_request->header.spdm_version; + spdm_response->header.request_response_code = SPDM_DIGESTS; + spdm_response->header.param1 = 0; + spdm_response->header.param2 = 0; + + digest = (void *)(spdm_response + 1); + slot_index = 0; + for (index = 0; index < SPDM_MAX_SLOT_COUNT; index++) { + if (context->local_context + .local_cert_chain_provision[index] != NULL) { + spdm_response->header.param2 |= (1 << index); + result = libspdm_generate_cert_chain_hash(context, index, + &digest[hash_size * slot_index]); + slot_index++; + if (!result) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSPECIFIED, + 0, response_size, response); + } + } + } + + /* Cache*/ + + status = libspdm_append_message_mut_b(context, spdm_request, + request_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSPECIFIED, 0, + response_size, response); + } + + status = libspdm_append_message_mut_b(context, spdm_response, + *response_size); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSPECIFIED, 0, + response_size, response); + } + + return LIBSPDM_STATUS_SUCCESS; +} + +#endif /* (LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP) && (..) */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_error.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_error.c new file mode 100644 index 0000000000..5cd4ec0382 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_error.c @@ -0,0 +1,52 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP + +libspdm_return_t libspdm_generate_encap_error_response(const void *spdm_context, + uint8_t error_code, + uint8_t error_data, + size_t *response_size, + void *response) +{ + spdm_error_response_t *spdm_response; + + LIBSPDM_ASSERT(*response_size >= sizeof(spdm_error_response_t)); + *response_size = sizeof(spdm_error_response_t); + spdm_response = response; + + spdm_response->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_response->header.request_response_code = SPDM_ERROR; + spdm_response->header.param1 = error_code; + spdm_response->header.param2 = error_data; + + return LIBSPDM_STATUS_SUCCESS; +} + +libspdm_return_t libspdm_generate_encap_extended_error_response( + const void *spdm_context, uint8_t error_code, uint8_t error_data, + size_t extended_error_data_size, const uint8_t *extended_error_data, + size_t *response_size, void *response) +{ + spdm_error_response_t *spdm_response; + LIBSPDM_ASSERT(*response_size >= + sizeof(spdm_error_response_t) + extended_error_data_size); + + spdm_response = response; + spdm_response->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_response->header.request_response_code = SPDM_ERROR; + spdm_response->header.param1 = error_code; + spdm_response->header.param2 = error_data; + libspdm_copy_mem(spdm_response + 1, *response_size - (sizeof(spdm_error_response_t)), + extended_error_data, extended_error_data_size); + *response_size = + sizeof(spdm_error_response_t) + extended_error_data_size; + return LIBSPDM_STATUS_SUCCESS; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP */ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_key_update.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_key_update.c new file mode 100644 index 0000000000..4d291426cb --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_key_update.c @@ -0,0 +1,153 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" +#include "internal/libspdm_secured_message_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP + +libspdm_return_t libspdm_get_encap_response_key_update(void *spdm_context, + size_t request_size, + void *request, + size_t *response_size, + void *response) +{ + uint32_t session_id; + spdm_key_update_response_t *spdm_response; + spdm_key_update_request_t *spdm_request; + libspdm_context_t *context; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + spdm_key_update_request_t *prev_spdm_request; + spdm_key_update_request_t spdm_key_init_update_operation; + bool result; + + context = spdm_context; + spdm_request = request; + + if (libspdm_get_connection_version(context) < SPDM_MESSAGE_VERSION_11) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSUPPORTED_REQUEST, + 0, response_size, response); + } + + if (spdm_request->header.spdm_version != libspdm_get_connection_version(context)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_VERSION_MISMATCH, + 0, response_size, response); + } + + if (!libspdm_is_capabilities_flag_supported( + context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_KEY_UPD_CAP)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_UNSUPPORTED_REQUEST, + SPDM_KEY_UPDATE, response_size, response); + } + + if (!context->last_spdm_request_session_id_valid) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + session_id = context->last_spdm_request_session_id; + session_info = + libspdm_get_session_info_via_session_id(context, session_id); + if (session_info == NULL) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + + /* this message can only be in secured session + * thus don't need to consider transport layer padding, just check its exact size */ + if (request_size != sizeof(spdm_key_update_request_t)) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + + /*last key operation*/ + prev_spdm_request = &(session_info->last_key_update_request); + + /*the end status of the successful key update overall flow*/ + libspdm_zero_mem(&spdm_key_init_update_operation, sizeof(spdm_key_update_request_t)); + + result = true; + switch (spdm_request->header.param1) { + case SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_KEY: + if(!libspdm_consttime_is_mem_equal(prev_spdm_request, + &spdm_key_init_update_operation, + sizeof(spdm_key_update_request_t))) { + result = false; + break; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_create_update_session_data_key[%x] Responder\n", + session_id)); + result = libspdm_create_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER); + + /*save the last update operation*/ + libspdm_copy_mem(prev_spdm_request, sizeof(spdm_key_update_request_t), + spdm_request, request_size); + break; + case SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_ALL_KEYS: + result = false; + break; + case SPDM_KEY_UPDATE_OPERATIONS_TABLE_VERIFY_NEW_KEY: + if(prev_spdm_request->header.param1 != + SPDM_KEY_UPDATE_OPERATIONS_TABLE_UPDATE_KEY) { + result = false; + break; + } + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_activate_update_session_data_key[%x] Responder new\n", + session_id)); + result = libspdm_activate_update_session_data_key( + session_info->secured_message_context, + LIBSPDM_KEY_UPDATE_ACTION_RESPONDER, true); + + /*clear last_key_update_request*/ + libspdm_zero_mem(prev_spdm_request, sizeof(spdm_key_update_request_t)); + break; + default: + result = false; + break; + } + + if (!result) { + return libspdm_generate_encap_error_response( + context, SPDM_ERROR_CODE_INVALID_REQUEST, 0, + response_size, response); + } + + libspdm_reset_message_buffer_via_request_code(context, session_info, + spdm_request->header.request_response_code); + + LIBSPDM_ASSERT(*response_size >= sizeof(spdm_key_update_response_t)); + *response_size = sizeof(spdm_key_update_response_t); + libspdm_zero_mem(response, *response_size); + spdm_response = response; + + spdm_response->header.spdm_version = spdm_request->header.spdm_version; + spdm_response->header.request_response_code = SPDM_KEY_UPDATE_ACK; + spdm_response->header.param1 = spdm_request->header.param1; + spdm_response->header.param2 = spdm_request->header.param2; + + return LIBSPDM_STATUS_SUCCESS; +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP*/ diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_request.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_request.c new file mode 100644 index 0000000000..5ad7822478 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_request.c @@ -0,0 +1,452 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#if LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP + +typedef struct { + uint8_t request_response_code; + libspdm_get_encap_response_func get_encap_response_func; +} libspdm_get_encap_response_struct_t; + +void libspdm_register_get_encap_response_func(void *spdm_context, + const libspdm_get_encap_response_func + get_encap_response_func) +{ + libspdm_context_t *context; + + context = spdm_context; + context->get_encap_response_func = (void *)get_encap_response_func; +} + +/** + * Return the GET_ENCAP_RESPONSE function via request code. + * + * @param request_code The SPDM request code. + * + * @return GET_ENCAP_RESPONSE function according to the request code. + **/ +static libspdm_get_encap_response_func +libspdm_get_encap_response_func_via_request_code(uint8_t request_response_code) +{ + size_t index; + + libspdm_get_encap_response_struct_t get_encap_response_struct[] = { + #if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP + #if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP + { SPDM_GET_DIGESTS, libspdm_get_encap_response_digest }, + { SPDM_GET_CERTIFICATE, libspdm_get_encap_response_certificate }, + #endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ + + #if LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP + { SPDM_CHALLENGE, libspdm_get_encap_response_challenge_auth }, + #endif /* LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP*/ + #endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ + + { SPDM_KEY_UPDATE, libspdm_get_encap_response_key_update }, + }; + + for (index = 0; index < sizeof(get_encap_response_struct) / + sizeof(get_encap_response_struct[0]); index++) { + if (request_response_code == get_encap_response_struct[index].request_response_code) { + return get_encap_response_struct[index].get_encap_response_func; + } + } + return NULL; +} + +/** + * This function processes encapsulated request. + * + * @param spdm_context A pointer to the SPDM context. + * @param encap_request_size size in bytes of the request data buffer. + * @param encap_request A pointer to a destination buffer to store the request. + * @param encap_response_size size in bytes of the response data buffer. + * @param encap_response A pointer to a destination buffer to store the response. + * + * @retval RETURN_SUCCESS The SPDM response is processed successfully. + * @retval RETURN_DEVICE_ERROR A device error occurs when the SPDM response is sent to the device. + **/ +static libspdm_return_t libspdm_process_encapsulated_request(libspdm_context_t *spdm_context, + size_t encap_request_size, + void *encap_request, + size_t *encap_response_size, + void *encap_response) +{ + libspdm_get_encap_response_func get_encap_response_func; + spdm_message_header_t *spdm_requester; + + spdm_requester = encap_request; + if (encap_request_size < sizeof(spdm_message_header_t)) { + return libspdm_generate_encap_error_response( + spdm_context, SPDM_ERROR_CODE_UNSUPPORTED_REQUEST, + spdm_requester->request_response_code, + encap_response_size, encap_response); + } + + get_encap_response_func = libspdm_get_encap_response_func_via_request_code( + spdm_requester->request_response_code); + if (get_encap_response_func == NULL) { + get_encap_response_func = + (libspdm_get_encap_response_func) + spdm_context->get_encap_response_func; + } + if (get_encap_response_func != NULL) { + return get_encap_response_func( + spdm_context, encap_request_size, encap_request, + encap_response_size, encap_response); + } else { + return libspdm_generate_encap_error_response( + spdm_context, SPDM_ERROR_CODE_UNEXPECTED_REQUEST, + 0, + encap_response_size, encap_response); + } +} + +libspdm_return_t libspdm_encapsulated_request(libspdm_context_t *spdm_context, + const uint32_t *session_id, + uint8_t mut_auth_requested, + uint8_t *req_slot_id_param) +{ + libspdm_return_t status; + uint8_t *spdm_request; + size_t spdm_request_size; + spdm_get_encapsulated_request_request_t + *spdm_get_encapsulated_request_request; + spdm_deliver_encapsulated_response_request_t + *spdm_deliver_encapsulated_response_request; + uint8_t *spdm_response; + size_t spdm_response_size; + spdm_encapsulated_request_response_t *libspdm_encapsulated_request_response; + spdm_encapsulated_response_ack_response_t + *spdm_encapsulated_response_ack_response; + libspdm_session_info_t *session_info; + uint8_t request_id; + void *encapsulated_request; + size_t encapsulated_request_size; + void *encapsulated_response; + size_t encapsulated_response_size; + size_t ack_header_size; + + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + #if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP + spdm_get_digest_request_t *get_digests; + #endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ + + if (libspdm_get_connection_version(spdm_context) < SPDM_MESSAGE_VERSION_11) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_ENCAP_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_ENCAP_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + if (session_id != NULL) { + session_info = libspdm_get_session_info_via_session_id( + spdm_context, *session_id); + if (session_info == NULL) { + LIBSPDM_ASSERT(false); + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + LIBSPDM_ASSERT((mut_auth_requested == 0) || + (mut_auth_requested == + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_ENCAP_REQUEST) || + (mut_auth_requested == + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS)); + } else { + LIBSPDM_ASSERT(mut_auth_requested == 0); + } + + + /* Cache*/ + + libspdm_reset_message_mut_b(spdm_context); + libspdm_reset_message_mut_c(spdm_context); + + if (session_id == NULL) { + spdm_context->last_spdm_request_session_id_valid = false; + spdm_context->last_spdm_request_session_id = 0; + } else { + spdm_context->last_spdm_request_session_id_valid = true; + spdm_context->last_spdm_request_session_id = *session_id; + } + + if (mut_auth_requested == + SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED_WITH_GET_DIGESTS) { + +#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP + + get_digests = (void *)spdm_context->last_spdm_request; + get_digests->header.spdm_version = libspdm_get_connection_version (spdm_context); + get_digests->header.request_response_code = SPDM_GET_DIGESTS; + get_digests->header.param1 = 0; + get_digests->header.param2 = 0; + spdm_context->last_spdm_request_size = sizeof(spdm_get_digest_request_t); + encapsulated_request = (void *)spdm_context->last_spdm_request; + encapsulated_request_size = spdm_context->last_spdm_request_size; + request_id = 0; +#else /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ + return LIBSPDM_STATUS_UNSUPPORTED_CAP; +#endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ + } else { + + transport_header_size = spdm_context->local_context.capability.transport_header_size; + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; + + spdm_context->crypto_request = true; + spdm_get_encapsulated_request_request = (void *)spdm_request; + spdm_get_encapsulated_request_request->header.spdm_version = + libspdm_get_connection_version (spdm_context); + spdm_get_encapsulated_request_request->header + .request_response_code = SPDM_GET_ENCAPSULATED_REQUEST; + spdm_get_encapsulated_request_request->header.param1 = 0; + spdm_get_encapsulated_request_request->header.param2 = 0; + spdm_request_size = + sizeof(spdm_get_encapsulated_request_request_t); + libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, + spdm_get_encapsulated_request_request->header.request_response_code); + status = libspdm_send_spdm_request( + spdm_context, session_id, spdm_request_size, + spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_get_encapsulated_request_request = (void *)spdm_context->last_spdm_request; + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, session_id, &spdm_response_size, + (void **)&spdm_response); + libspdm_encapsulated_request_response = (void *)spdm_response; + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + return status; + } + if (libspdm_encapsulated_request_response->header + .request_response_code != + SPDM_ENCAPSULATED_REQUEST) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (libspdm_encapsulated_request_response->header.spdm_version != + spdm_get_encapsulated_request_request->header.spdm_version) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (spdm_response_size < sizeof(spdm_encapsulated_request_response_t)) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + if (spdm_response_size == sizeof(spdm_encapsulated_request_response_t)) { + + /* Done*/ + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_SUCCESS; + } + request_id = libspdm_encapsulated_request_response->header.param1; + + encapsulated_request = (void *)(libspdm_encapsulated_request_response + 1); + encapsulated_request_size = + spdm_response_size - sizeof(spdm_encapsulated_request_response_t); + + libspdm_copy_mem (spdm_context->last_spdm_request, + libspdm_get_scratch_buffer_last_spdm_request_capacity(spdm_context), + encapsulated_request, + encapsulated_request_size); + spdm_context->last_spdm_request_size = encapsulated_request_size; + encapsulated_request = (void *)spdm_context->last_spdm_request; + + libspdm_release_receiver_buffer (spdm_context); + } + + while (true) { + + /* Process request*/ + transport_header_size = spdm_context->local_context.capability.transport_header_size; + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; + + spdm_context->crypto_request = true; + spdm_deliver_encapsulated_response_request = (void *)spdm_request; + spdm_deliver_encapsulated_response_request->header.spdm_version = + libspdm_get_connection_version (spdm_context); + spdm_deliver_encapsulated_response_request->header + .request_response_code = + SPDM_DELIVER_ENCAPSULATED_RESPONSE; + spdm_deliver_encapsulated_response_request->header.param1 = request_id; + spdm_deliver_encapsulated_response_request->header.param2 = 0; + encapsulated_response = (void *)(spdm_deliver_encapsulated_response_request + 1); + encapsulated_response_size = + spdm_request_size - sizeof(spdm_deliver_encapsulated_response_request_t); + + status = libspdm_process_encapsulated_request( + spdm_context, encapsulated_request_size, + encapsulated_request, &encapsulated_response_size, + encapsulated_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + + spdm_request_size = + sizeof(spdm_deliver_encapsulated_response_request_t) + encapsulated_response_size; + status = libspdm_send_spdm_request( + spdm_context, session_id, spdm_request_size, + spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_deliver_encapsulated_response_request = (void *)spdm_context->last_spdm_request; + + /* receive */ + + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + + status = libspdm_receive_spdm_response( + spdm_context, session_id, &spdm_response_size, + (void **)&spdm_response); + spdm_encapsulated_response_ack_response = (void *)spdm_response; + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_receiver_buffer (spdm_context); + return status; + } + if (spdm_encapsulated_response_ack_response->header + .request_response_code != + SPDM_ENCAPSULATED_RESPONSE_ACK) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (spdm_encapsulated_response_ack_response->header.spdm_version != + spdm_deliver_encapsulated_response_request->header.spdm_version) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (spdm_encapsulated_response_ack_response->header.spdm_version >= + SPDM_MESSAGE_VERSION_12) { + ack_header_size = sizeof(spdm_encapsulated_response_ack_response_t); + } else { + ack_header_size = sizeof(spdm_message_header_t); + } + if (spdm_response_size < ack_header_size) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + if (spdm_encapsulated_response_ack_response->header.spdm_version >= + SPDM_MESSAGE_VERSION_12) { + if (spdm_encapsulated_response_ack_response->ack_request_id != + spdm_deliver_encapsulated_response_request->header.param1) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + } + + switch (spdm_encapsulated_response_ack_response->header.param2) { + case SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_ABSENT: + if (spdm_response_size == ack_header_size) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_SUCCESS; + } else { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + break; + case SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_PRESENT: + break; + case SPDM_ENCAPSULATED_RESPONSE_ACK_RESPONSE_PAYLOAD_TYPE_REQ_SLOT_NUMBER: + if (spdm_response_size >= ack_header_size + sizeof(uint8_t)) { + if ((req_slot_id_param != NULL) && + (*req_slot_id_param == 0)) { + *req_slot_id_param = + *((uint8_t *)spdm_encapsulated_response_ack_response + ack_header_size); + /* 0xFF or 0xF slot is not allowed. */ + if (*req_slot_id_param >= SPDM_MAX_SLOT_COUNT) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + } + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_SUCCESS; + } else { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + break; + default: + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + request_id = + spdm_encapsulated_response_ack_response->header.param1; + + encapsulated_request = + ((uint8_t *)spdm_encapsulated_response_ack_response + ack_header_size); + encapsulated_request_size = spdm_response_size - ack_header_size; + + libspdm_copy_mem (spdm_context->last_spdm_request, + libspdm_get_scratch_buffer_last_spdm_request_capacity(spdm_context), + encapsulated_request, + encapsulated_request_size + ); + spdm_context->last_spdm_request_size = encapsulated_request_size; + encapsulated_request = (void *)spdm_context->last_spdm_request; + + libspdm_release_receiver_buffer (spdm_context); + } + + return LIBSPDM_STATUS_SUCCESS; +} + +libspdm_return_t libspdm_send_receive_encap_request(void *spdm_context, const uint32_t *session_id) +{ + return libspdm_encapsulated_request(spdm_context, session_id, 0, NULL); +} + +#endif /* LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_end_session.c similarity index 84% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_end_session.c index 643551e65d..4f9ec21a3b 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_end_session.c @@ -5,8 +5,9 @@ **/ #include "internal/libspdm_requester_lib.h" +#include "internal/libspdm_secured_message_lib.h" -#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) +#if (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) #pragma pack(1) typedef struct { @@ -40,6 +41,10 @@ static libspdm_return_t libspdm_try_send_receive_end_session(libspdm_context_t * size_t message_size; size_t transport_header_size; + if (libspdm_get_connection_version(spdm_context) < SPDM_MESSAGE_VERSION_11) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { return LIBSPDM_STATUS_INVALID_STATE_LOCAL; @@ -61,14 +66,16 @@ static libspdm_return_t libspdm_try_send_receive_end_session(libspdm_context_t * end_session_attributes = 0; } - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); spdm_request->header.request_response_code = SPDM_END_SESSION; @@ -114,8 +121,7 @@ static libspdm_return_t libspdm_try_send_receive_end_session(libspdm_context_t * if (spdm_response->header.request_response_code == SPDM_ERROR) { status = libspdm_handle_error_response_main( spdm_context, &session_id, &spdm_response_size, - (void **)&spdm_response, SPDM_END_SESSION, SPDM_END_SESSION_ACK, - sizeof(libspdm_end_session_response_mine_t)); + (void **)&spdm_response, SPDM_END_SESSION, SPDM_END_SESSION_ACK); if (LIBSPDM_STATUS_IS_ERROR(status)) { goto receive_done; } @@ -123,6 +129,8 @@ static libspdm_return_t libspdm_try_send_receive_end_session(libspdm_context_t * status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } + /* this message can only be in secured session + * thus don't need to consider transport layer padding, just check its exact size */ if (spdm_response_size != sizeof(spdm_end_session_response_t)) { status = LIBSPDM_STATUS_INVALID_MSG_SIZE; goto receive_done; @@ -137,6 +145,11 @@ static libspdm_return_t libspdm_try_send_receive_end_session(libspdm_context_t * status = LIBSPDM_STATUS_SUCCESS; + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + receive_done: libspdm_release_receiver_buffer (spdm_context); return status; @@ -147,19 +160,23 @@ libspdm_return_t libspdm_send_receive_end_session(libspdm_context_t *spdm_contex uint8_t end_session_attributes) { size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; spdm_context->crypto_request = true; retry = spdm_context->retry_times; + retry_delay_time = spdm_context->retry_delay_time; do { status = libspdm_try_send_receive_end_session( spdm_context, session_id, end_session_attributes); - if (LIBSPDM_STATUS_BUSY_PEER != status) { + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; } -#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP) */ +#endif /* (LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP) || (LIBSPDM_ENABLE_CAPABILITY_PSK_CAP) */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_finish.c similarity index 79% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_finish.c index f6e4f9f9cd..3ea64b47f5 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_finish.c @@ -5,6 +5,7 @@ **/ #include "internal/libspdm_requester_lib.h" +#include "internal/libspdm_secured_message_lib.h" #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP @@ -29,12 +30,14 @@ bool libspdm_verify_finish_rsp_hmac(libspdm_context_t *spdm_context, uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; bool result; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t slot_id; uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; uint8_t *mut_cert_chain_buffer; size_t mut_cert_chain_buffer_size; - uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + uint8_t *th_curr_data; size_t th_curr_data_size; + libspdm_th_managed_buffer_t th_curr; uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; #endif @@ -42,16 +45,29 @@ bool libspdm_verify_finish_rsp_hmac(libspdm_context_t *spdm_context, LIBSPDM_ASSERT(hash_size == hmac_data_size); #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - result = libspdm_get_peer_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } if (!result) { return false; } if (session_info->mut_auth_requested) { - result = libspdm_get_local_cert_chain_buffer( - spdm_context, (const void **)&mut_cert_chain_buffer, - &mut_cert_chain_buffer_size); + slot_id = spdm_context->connection_info.local_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_local_public_key_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, &mut_cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, &mut_cert_chain_buffer_size); + } if (!result) { return false; } @@ -59,14 +75,16 @@ bool libspdm_verify_finish_rsp_hmac(libspdm_context_t *spdm_context, mut_cert_chain_buffer = NULL; mut_cert_chain_buffer_size = 0; } - th_curr_data_size = sizeof(th_curr_data); + result = libspdm_calculate_th_for_finish( spdm_context, session_info, cert_chain_buffer, cert_chain_buffer_size, mut_cert_chain_buffer, - mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + mut_cert_chain_buffer_size, &th_curr); if (!result) { return false; } + th_curr_data = libspdm_get_managed_buffer(&th_curr); + th_curr_data_size = libspdm_get_managed_buffer_size(&th_curr); result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, th_curr_data, th_curr_data_size, hash_data); @@ -91,7 +109,7 @@ bool libspdm_verify_finish_rsp_hmac(libspdm_context_t *spdm_context, LIBSPDM_INTERNAL_DUMP_DATA(calc_hmac_data, hash_size); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); - if (libspdm_const_compare_mem(calc_hmac_data, hmac_data, hash_size) != 0) { + if (!libspdm_consttime_is_mem_equal(calc_hmac_data, hmac_data, hash_size)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_finish_rsp_hmac - FAIL !!!\n")); return false; } @@ -108,28 +126,43 @@ bool libspdm_generate_finish_req_hmac(libspdm_context_t *spdm_context, uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; bool result; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t slot_id; uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; uint8_t *mut_cert_chain_buffer; size_t mut_cert_chain_buffer_size; - uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + uint8_t *th_curr_data; size_t th_curr_data_size; + libspdm_th_managed_buffer_t th_curr; uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; #endif hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - result = libspdm_get_peer_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } if (!result) { return false; } if (session_info->mut_auth_requested) { - result = libspdm_get_local_cert_chain_buffer( - spdm_context, (const void **)&mut_cert_chain_buffer, - &mut_cert_chain_buffer_size); + slot_id = spdm_context->connection_info.local_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_local_public_key_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, &mut_cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, &mut_cert_chain_buffer_size); + } if (!result) { return false; } @@ -138,14 +171,15 @@ bool libspdm_generate_finish_req_hmac(libspdm_context_t *spdm_context, mut_cert_chain_buffer_size = 0; } - th_curr_data_size = sizeof(th_curr_data); result = libspdm_calculate_th_for_finish( spdm_context, session_info, cert_chain_buffer, cert_chain_buffer_size, mut_cert_chain_buffer, - mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + mut_cert_chain_buffer_size, &th_curr); if (!result) { return false; } + th_curr_data = libspdm_get_managed_buffer(&th_curr); + th_curr_data_size = libspdm_get_managed_buffer_size(&th_curr); result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, th_curr_data, th_curr_data_size, hash_data); @@ -184,12 +218,14 @@ bool libspdm_generate_finish_req_signature(libspdm_context_t *spdm_context, bool result; size_t signature_size; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t slot_id; uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; uint8_t *mut_cert_chain_buffer; size_t mut_cert_chain_buffer_size; - uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + uint8_t *th_curr_data; size_t th_curr_data_size; + libspdm_th_managed_buffer_t th_curr; #endif #if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) size_t hash_size; @@ -207,27 +243,41 @@ bool libspdm_generate_finish_req_signature(libspdm_context_t *spdm_context, #endif #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - result = libspdm_get_peer_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } if (!result) { return false; } - result = libspdm_get_local_cert_chain_buffer(spdm_context, - (const void **)&mut_cert_chain_buffer, - &mut_cert_chain_buffer_size); + slot_id = spdm_context->connection_info.local_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_local_public_key_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, &mut_cert_chain_buffer_size); + } else { + result = libspdm_get_local_cert_chain_buffer( + spdm_context, (const void **)&mut_cert_chain_buffer, &mut_cert_chain_buffer_size); + } if (!result) { return false; } - th_curr_data_size = sizeof(th_curr_data); result = libspdm_calculate_th_for_finish( spdm_context, session_info, cert_chain_buffer, cert_chain_buffer_size, mut_cert_chain_buffer, - mut_cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + mut_cert_chain_buffer_size, &th_curr); if (!result) { return false; } + th_curr_data = libspdm_get_managed_buffer(&th_curr); + th_curr_data_size = libspdm_get_managed_buffer_size(&th_curr); /* Debug code only - required for debug print of th_curr below*/ LIBSPDM_DEBUG_CODE( @@ -302,6 +352,10 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ size_t transport_header_size; /* -=[Check Parameters Phase]=- */ + if (libspdm_get_connection_version(spdm_context) < SPDM_MESSAGE_VERSION_11) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); if (session_info == NULL) { status = LIBSPDM_STATUS_INVALID_PARAMETER; @@ -341,14 +395,16 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ } /* -=[Construct Request Phase]=- */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { goto error; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); spdm_request->header.request_response_code = SPDM_FINISH; @@ -364,11 +420,8 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ } #endif - if (req_slot_id_param == 0xFF) { - req_slot_id_param = spdm_context->local_context.provisioned_slot_id; - } - - if (session_info->mut_auth_requested) { + spdm_context->connection_info.local_used_cert_chain_slot_id = req_slot_id_param; + if (session_info->mut_auth_requested && (req_slot_id_param != 0xFF)) { LIBSPDM_ASSERT(req_slot_id_param < SPDM_MAX_SLOT_COUNT); spdm_context->connection_info.local_used_cert_chain_buffer = spdm_context->local_context.local_cert_chain_provision[req_slot_id_param]; @@ -384,7 +437,6 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ sizeof(spdm_finish_request_t)); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_release_sender_buffer (spdm_context); - status = LIBSPDM_STATUS_BUFFER_FULL; goto error; } #if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP @@ -398,7 +450,6 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ status = libspdm_append_message_f(spdm_context, session_info, true, ptr, signature_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_release_sender_buffer (spdm_context); - status = LIBSPDM_STATUS_BUFFER_FULL; goto error; } ptr += signature_size; @@ -415,7 +466,6 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ status = libspdm_append_message_f(spdm_context, session_info, true, ptr, hmac_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_release_sender_buffer (spdm_context); - status = LIBSPDM_STATUS_BUFFER_FULL; goto error; } @@ -467,8 +517,7 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ status = libspdm_handle_error_response_main( spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response, - SPDM_FINISH, SPDM_FINISH_RSP, - sizeof(libspdm_finish_response_mine_t)); + SPDM_FINISH, SPDM_FINISH_RSP); if (LIBSPDM_STATUS_IS_ERROR(status)) { goto receive_done; } @@ -484,7 +533,7 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ hmac_size = 0; } - if (spdm_response_size != sizeof(spdm_finish_response_t) + hmac_size) { + if (spdm_response_size < sizeof(spdm_finish_response_t) + hmac_size) { status = LIBSPDM_STATUS_INVALID_MSG_SIZE; goto receive_done; } @@ -492,7 +541,6 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ status = libspdm_append_message_f(spdm_context, session_info, true, spdm_response, sizeof(spdm_finish_response_t)); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } @@ -516,7 +564,6 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ sizeof(spdm_finish_response_t), hmac_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } } @@ -539,6 +586,11 @@ static libspdm_return_t libspdm_try_send_receive_finish(libspdm_context_t *spdm_ libspdm_secured_message_set_session_state( session_info->secured_message_context, LIBSPDM_SESSION_STATE_ESTABLISHED); + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + libspdm_release_receiver_buffer (spdm_context); return LIBSPDM_STATUS_SUCCESS; @@ -558,16 +610,20 @@ libspdm_return_t libspdm_send_receive_finish(libspdm_context_t *spdm_context, uint8_t req_slot_id_param) { size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; spdm_context->crypto_request = true; retry = spdm_context->retry_times; + retry_delay_time = spdm_context->retry_delay_time; do { status = libspdm_try_send_receive_finish(spdm_context, session_id, req_slot_id_param); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c similarity index 88% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c index a4722955d9..23746b9766 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c @@ -74,7 +74,10 @@ static bool validate_responder_capability(uint32_t capabilities_flag, uint8_t ve /* Checks that originate from key exchange capabilities. */ if ((key_ex_cap == 1) || (psk_cap != 0)) { - if ((mac_cap == 0) && (encrypt_cap == 0)) { + /* While clearing MAC_CAP and setting ENCRYPT_CAP is legal according to DSP0274, libspdm + * also implements DSP0277 secure messages, which requires at least MAC_CAP to be set. + */ + if (mac_cap == 0) { return false; } } else { @@ -105,6 +108,13 @@ static bool validate_responder_capability(uint32_t capabilities_flag, uint8_t ve return false; } } + + /* Checks that originate from mutual authentication capabilities. */ + if (mut_auth_cap == 1) { + if ((key_ex_cap == 0) && (chal_cap == 0)) { + return false; + } + } } /* Checks specific to 1.1. */ @@ -170,13 +180,16 @@ static libspdm_return_t libspdm_try_get_capabilities(libspdm_context_t *spdm_con libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_CAPABILITIES); /* -=[Construct Request Phase]=- */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; libspdm_zero_mem(spdm_request, sizeof(spdm_get_capabilities_request_t)); spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); @@ -279,21 +292,34 @@ static libspdm_return_t libspdm_try_get_capabilities(libspdm_context_t *spdm_con } } + if (spdm_response->ct_exponent > LIBSPDM_MAX_CT_EXPONENT) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + /* -=[Process Response Phase]=- */ status = libspdm_append_message_a(spdm_context, spdm_request, spdm_request_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } status = libspdm_append_message_a(spdm_context, spdm_response, spdm_response_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } spdm_context->connection_info.capability.ct_exponent = spdm_response->ct_exponent; - spdm_context->connection_info.capability.flags = spdm_response->flags; + + if (spdm_response->header.spdm_version == SPDM_MESSAGE_VERSION_10) { + spdm_context->connection_info.capability.flags = + spdm_response->flags & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_10_MASK; + } else if (spdm_response->header.spdm_version == SPDM_MESSAGE_VERSION_11) { + spdm_context->connection_info.capability.flags = + spdm_response->flags & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_11_MASK; + } else { + spdm_context->connection_info.capability.flags = + spdm_response->flags & SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_12_MASK; + } if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { spdm_context->connection_info.capability.data_transfer_size = @@ -322,15 +348,19 @@ static libspdm_return_t libspdm_try_get_capabilities(libspdm_context_t *spdm_con libspdm_return_t libspdm_get_capabilities(libspdm_context_t *spdm_context) { size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; spdm_context->crypto_request = false; retry = spdm_context->retry_times; + retry_delay_time = spdm_context->retry_delay_time; do { status = libspdm_try_get_capabilities(spdm_context); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_certificate.c similarity index 68% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_certificate.c index e1feb22038..5454462368 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_certificate.c @@ -6,10 +6,7 @@ #include "internal/libspdm_requester_lib.h" -#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP - -// NVIDIA_EDIT: Include malloclib for dynamic allocation. -#include "library/malloclib.h" +#if LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT #pragma pack(1) typedef struct { @@ -64,7 +61,8 @@ typedef struct { * @retval LIBSPDM_STATUS_CRYPTO_ERROR * A generic cryptography error occurred. **/ -static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_t *session_id, +static libspdm_return_t libspdm_try_get_certificate(libspdm_context_t *spdm_context, + const uint32_t *session_id, uint8_t slot_id, uint16_t length, size_t *cert_chain_size, @@ -78,10 +76,9 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ size_t spdm_request_size; libspdm_certificate_response_max_t *spdm_response; size_t spdm_response_size; - libspdm_large_managed_buffer_t *certificate_chain_buffer; - libspdm_context_t *spdm_context; uint16_t total_responder_cert_chain_buffer_length; size_t cert_chain_capacity; + size_t cert_chain_size_internal; uint16_t remainder_length; uint8_t *message; size_t message_size; @@ -90,86 +87,67 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ libspdm_session_state_t session_state; bool chunk_enabled; - // - // NVIDIA_EDIT: To avoid massive stack usage, changed the certificate buffer from - // allocation on stack to dynamic memory. Changed return patterns where - // necessary to ensure memory is freed. - // - certificate_chain_buffer = (libspdm_large_managed_buffer_t *) - allocate_zero_pool(sizeof(libspdm_large_managed_buffer_t)); - if (certificate_chain_buffer == NULL) { - return LIBSPDM_STATUS_BUFFER_FULL; - } - /* -=[Check Parameters Phase]=- */ LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); + LIBSPDM_ASSERT(cert_chain_size != NULL); + LIBSPDM_ASSERT(*cert_chain_size > 0); + LIBSPDM_ASSERT(cert_chain != NULL); /* -=[Verify State Phase]=- */ - spdm_context = context; - if (!libspdm_is_capabilities_flag_supported( spdm_context, true, 0, SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP)) { - status = LIBSPDM_STATUS_UNSUPPORTED_CAP; - goto done; + return LIBSPDM_STATUS_UNSUPPORTED_CAP; } if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { - status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; - goto done; + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } session_info = NULL; if (session_id != NULL) { - session_info = libspdm_get_session_info_via_session_id( - spdm_context, *session_id); + session_info = libspdm_get_session_info_via_session_id(spdm_context, *session_id); if (session_info == NULL) { LIBSPDM_ASSERT(false); - status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; - goto done; + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } session_state = libspdm_secured_message_get_session_state( session_info->secured_message_context); if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { - status = LIBSPDM_STATUS_INVALID_STATE_LOCAL; - goto done; + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } } libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_GET_CERTIFICATE); - libspdm_init_managed_buffer(certificate_chain_buffer, LIBSPDM_MAX_MESSAGE_BUFFER_SIZE); - chunk_enabled = libspdm_is_capabilities_flag_supported(spdm_context, true, SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHUNK_CAP); - if (chunk_enabled) { - length = 0xffff; - } else { - length = LIBSPDM_MIN(length, LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN); - } - remainder_length = 0; total_responder_cert_chain_buffer_length = 0; + cert_chain_capacity = *cert_chain_size; + cert_chain_size_internal = 0; - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; do { /* -=[Construct Request Phase]=- */ status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { - goto done; + return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); spdm_request->header.request_response_code = SPDM_GET_CERTIFICATE; spdm_request->header.param1 = slot_id; spdm_request->header.param2 = 0; - spdm_request->offset = (uint16_t)libspdm_get_managed_buffer_size(certificate_chain_buffer); + spdm_request->offset = (uint16_t)cert_chain_size_internal; if (spdm_request->offset == 0) { spdm_request->length = length; } else { @@ -193,7 +171,7 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ /* -=[Receive Response Phase]=- */ status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { - goto done; + return status; } LIBSPDM_ASSERT (message_size >= transport_header_size); spdm_response = (void *)(message); @@ -225,14 +203,12 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ spdm_context, session_id, &spdm_response_size, (void **)&spdm_response, SPDM_GET_CERTIFICATE, - SPDM_CERTIFICATE, - sizeof(libspdm_certificate_response_max_t)); + SPDM_CERTIFICATE); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_release_receiver_buffer (spdm_context); goto done; } - } else if (spdm_response->header.request_response_code != - SPDM_CERTIFICATE) { + } else if (spdm_response->header.request_response_code != SPDM_CERTIFICATE) { libspdm_release_receiver_buffer (spdm_context); status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto done; @@ -259,6 +235,17 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ status = LIBSPDM_STATUS_INVALID_MSG_SIZE; goto done; } + if (spdm_response->portion_length > 0xFFFF - spdm_request->offset) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } + if (spdm_response->remainder_length > 0xFFFF - spdm_request->offset - + spdm_response->portion_length) { + libspdm_release_receiver_buffer (spdm_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto done; + } if (spdm_request->offset == 0) { total_responder_cert_chain_buffer_length = spdm_response->portion_length + spdm_response->remainder_length; @@ -268,7 +255,8 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto done; } - if (chunk_enabled && (spdm_response->remainder_length != 0)) { + if (chunk_enabled && (spdm_request->offset == 0) && (spdm_request->length == 0xFFFF) && + (spdm_response->remainder_length != 0)) { libspdm_release_receiver_buffer (spdm_context); status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto done; @@ -282,71 +270,85 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ status = libspdm_append_message_b(spdm_context, spdm_request, spdm_request_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_release_receiver_buffer (spdm_context); - status = LIBSPDM_STATUS_BUFFER_FULL; goto done; } status = libspdm_append_message_b(spdm_context, spdm_response, spdm_response_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_release_receiver_buffer (spdm_context); - status = LIBSPDM_STATUS_BUFFER_FULL; goto done; } } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Certificate (offset 0x%x, size 0x%x):\n", - spdm_request->offset, spdm_response->portion_length)); - LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->cert_chain, spdm_response->portion_length); - - status = libspdm_append_managed_buffer(certificate_chain_buffer, - spdm_response->cert_chain, - spdm_response->portion_length); - if (LIBSPDM_STATUS_IS_ERROR(status)) { + if (cert_chain_size_internal + spdm_response->portion_length > cert_chain_capacity) { libspdm_release_receiver_buffer (spdm_context); status = LIBSPDM_STATUS_BUFFER_FULL; goto done; } + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Certificate (offset 0x%x, size 0x%x):\n", + spdm_request->offset, spdm_response->portion_length)); + LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->cert_chain, spdm_response->portion_length); + + libspdm_copy_mem((uint8_t *)cert_chain + cert_chain_size_internal, + cert_chain_capacity - cert_chain_size_internal, + spdm_response->cert_chain, + spdm_response->portion_length); + + cert_chain_size_internal += spdm_response->portion_length; + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE) { spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_AFTER_CERTIFICATE; } + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + libspdm_release_receiver_buffer (spdm_context); } while (remainder_length != 0); + *cert_chain_size = cert_chain_size_internal; + LIBSPDM_ASSERT(*cert_chain_size <= SPDM_MAX_CERTIFICATE_CHAIN_SIZE); + if (spdm_context->local_context.verify_peer_spdm_cert_chain != NULL) { result = spdm_context->local_context.verify_peer_spdm_cert_chain ( - spdm_context, slot_id, libspdm_get_managed_buffer_size(certificate_chain_buffer), - libspdm_get_managed_buffer(certificate_chain_buffer), + spdm_context, slot_id, cert_chain_size_internal, cert_chain, trust_anchor, trust_anchor_size); if (!result) { status = LIBSPDM_STATUS_VERIF_FAIL; goto done; } } else { - result = libspdm_verify_peer_cert_chain_buffer( - spdm_context, libspdm_get_managed_buffer(certificate_chain_buffer), - libspdm_get_managed_buffer_size(certificate_chain_buffer), - trust_anchor, trust_anchor_size, true); + result = libspdm_verify_peer_cert_chain_buffer_integrity( + spdm_context, cert_chain, cert_chain_size_internal); if (!result) { status = LIBSPDM_STATUS_VERIF_FAIL; goto done; } } + /*verify peer cert chain authority*/ + result = libspdm_verify_peer_cert_chain_buffer_authority( + spdm_context, cert_chain,cert_chain_size_internal, + trust_anchor, trust_anchor_size); + if (!result) { + status = LIBSPDM_STATUS_VERIF_NO_AUTHORITY; + } + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_size = - libspdm_get_managed_buffer_size(certificate_chain_buffer); + cert_chain_size_internal; libspdm_copy_mem(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer, sizeof(spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer), - libspdm_get_managed_buffer(certificate_chain_buffer), - libspdm_get_managed_buffer_size(certificate_chain_buffer)); + cert_chain, cert_chain_size_internal); #else result = libspdm_hash_all( spdm_context->connection_info.algorithm.base_hash_algo, - libspdm_get_managed_buffer(certificate_chain_buffer), - libspdm_get_managed_buffer_size(certificate_chain_buffer), + cert_chain, cert_chain_size_internal, spdm_context->connection_info.peer_used_cert_chain[slot_id].buffer_hash); if (!result) { status = LIBSPDM_STATUS_CRYPTO_ERROR; @@ -359,8 +361,7 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ result = libspdm_get_leaf_cert_public_key_from_cert_chain( spdm_context->connection_info.algorithm.base_hash_algo, spdm_context->connection_info.algorithm.base_asym_algo, - libspdm_get_managed_buffer(certificate_chain_buffer), - libspdm_get_managed_buffer_size(certificate_chain_buffer), + cert_chain, cert_chain_size_internal, &spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key); if (!result) { status = LIBSPDM_STATUS_INVALID_CERT; @@ -368,92 +369,67 @@ static libspdm_return_t libspdm_try_get_certificate(void *context, const uint32_ } #endif - if (cert_chain_size != NULL) { - if (*cert_chain_size < - libspdm_get_managed_buffer_size(certificate_chain_buffer)) { - *cert_chain_size = libspdm_get_managed_buffer_size( - certificate_chain_buffer); - status = LIBSPDM_STATUS_BUFFER_FULL; - goto done; - } - cert_chain_capacity = *cert_chain_size; - *cert_chain_size = libspdm_get_managed_buffer_size(certificate_chain_buffer); - if (cert_chain != NULL) { - libspdm_copy_mem(cert_chain, - cert_chain_capacity, - libspdm_get_managed_buffer(certificate_chain_buffer), - libspdm_get_managed_buffer_size(certificate_chain_buffer)); - } + if (status != LIBSPDM_STATUS_VERIF_NO_AUTHORITY) { + status = LIBSPDM_STATUS_SUCCESS; } - - status = LIBSPDM_STATUS_SUCCESS; done: - free_pool(certificate_chain_buffer); - return status; } -libspdm_return_t libspdm_get_certificate(void *context, uint8_t slot_id, +libspdm_return_t libspdm_get_certificate(void *spdm_context, const uint32_t *session_id, + uint8_t slot_id, size_t *cert_chain_size, void *cert_chain) { - return libspdm_get_certificate_choose_length(context, slot_id, + return libspdm_get_certificate_choose_length(spdm_context, session_id, slot_id, LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, cert_chain_size, cert_chain); } -libspdm_return_t libspdm_get_certificate_ex(void *context, uint8_t slot_id, +libspdm_return_t libspdm_get_certificate_ex(void *spdm_context, const uint32_t *session_id, + uint8_t slot_id, size_t *cert_chain_size, void *cert_chain, const void **trust_anchor, size_t *trust_anchor_size) { - return libspdm_get_certificate_choose_length_ex(context, slot_id, + return libspdm_get_certificate_choose_length_ex(spdm_context, session_id, slot_id, LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, cert_chain_size, cert_chain, trust_anchor, trust_anchor_size); } -libspdm_return_t libspdm_get_certificate_in_session(void *context, const uint32_t *session_id, - uint8_t slot_id, - size_t *cert_chain_size, - void *cert_chain, - const void **trust_anchor, - size_t *trust_anchor_size) -{ - return libspdm_get_certificate_choose_length_in_session(context, - session_id, - slot_id, - LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN, - cert_chain_size, cert_chain, - trust_anchor, trust_anchor_size); -} - -libspdm_return_t libspdm_get_certificate_choose_length(void *context, +libspdm_return_t libspdm_get_certificate_choose_length(void *spdm_context, + const uint32_t *session_id, uint8_t slot_id, uint16_t length, size_t *cert_chain_size, void *cert_chain) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; - spdm_context = context; - spdm_context->crypto_request = true; - retry = spdm_context->retry_times; + context = spdm_context; + context->crypto_request = true; + retry = context->retry_times; + retry_delay_time = context->retry_delay_time; do { - status = libspdm_try_get_certificate(spdm_context, NULL, slot_id, length, + status = libspdm_try_get_certificate(context, session_id, slot_id, length, cert_chain_size, cert_chain, NULL, NULL); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; } -libspdm_return_t libspdm_get_certificate_choose_length_ex(void *context, +libspdm_return_t libspdm_get_certificate_choose_length_ex(void *spdm_context, + const uint32_t *session_id, uint8_t slot_id, uint16_t length, size_t *cert_chain_size, @@ -461,51 +437,27 @@ libspdm_return_t libspdm_get_certificate_choose_length_ex(void *context, const void **trust_anchor, size_t *trust_anchor_size) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; - spdm_context = context; - spdm_context->crypto_request = true; - retry = spdm_context->retry_times; + context = spdm_context; + context->crypto_request = true; + retry = context->retry_times; + retry_delay_time = context->retry_delay_time; do { - status = libspdm_try_get_certificate(spdm_context, NULL, slot_id, length, + status = libspdm_try_get_certificate(context, session_id, slot_id, length, cert_chain_size, cert_chain, trust_anchor, trust_anchor_size); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } - } while (retry-- != 0); - return status; -} - -libspdm_return_t libspdm_get_certificate_choose_length_in_session(void *context, - const uint32_t *session_id, - uint8_t slot_id, - uint16_t length, - size_t *cert_chain_size, - void *cert_chain, - const void **trust_anchor, - size_t *trust_anchor_size) -{ - libspdm_context_t *spdm_context; - size_t retry; - libspdm_return_t status; - - spdm_context = context; - spdm_context->crypto_request = true; - retry = spdm_context->retry_times; - do { - status = libspdm_try_get_certificate(spdm_context, session_id, slot_id, length, - cert_chain_size, cert_chain, trust_anchor, - trust_anchor_size); - if (status != LIBSPDM_STATUS_BUSY_PEER) { - return status; - } + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; } -#endif /* LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ +#endif /* LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_digests.c similarity index 79% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_digests.c index 0a307b02a4..5e157267a6 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_digests.c @@ -6,7 +6,7 @@ #include "internal/libspdm_requester_lib.h" -#if LIBSPDM_ENABLE_CAPABILITY_CERT_CAP +#if LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT #pragma pack(1) typedef struct { @@ -23,7 +23,7 @@ typedef struct { * @param total_digest_buffer A pointer to a destination buffer to store the digests. * * @retval LIBSPDM_STATUS_SUCCESS - * GET_DIGETS was sent and DIGESTS was received. + * GET_DIGESTS was sent and DIGESTS was received. * @retval LIBSPDM_STATUS_INVALID_STATE_LOCAL * Cannot send GET_DIGESTS due to Requester's state. * @retval LIBSPDM_STATUS_UNSUPPORTED_CAP @@ -40,16 +40,12 @@ typedef struct { * The Responder returned a RequestResynch error message. * @retval LIBSPDM_STATUS_BUFFER_FULL * The buffer used to store transcripts is exhausted. - * @retval LIBSPDM_STATUS_VERIF_FAIL - * The digest of the stored certificate chain does not match the digest returned by - * the Responder. - * Note: This return value may be removed in the future. **/ -static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *session_id, +static libspdm_return_t libspdm_try_get_digest(libspdm_context_t *spdm_context, + const uint32_t *session_id, uint8_t *slot_mask, void *total_digest_buffer) { - bool result; libspdm_return_t status; spdm_get_digest_request_t *spdm_request; size_t spdm_request_size; @@ -58,15 +54,12 @@ static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *se size_t digest_size; size_t digest_count; size_t index; - libspdm_context_t *spdm_context; uint8_t *message; size_t message_size; size_t transport_header_size; libspdm_session_info_t *session_info; libspdm_session_state_t session_state; - spdm_context = context; - /* -=[Verify State Phase]=- */ if (!libspdm_is_capabilities_flag_supported( spdm_context, true, 0, @@ -93,14 +86,16 @@ static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *se libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_GET_DIGESTS); /* -=[Construct Request Phase]=- */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); spdm_request->header.request_response_code = SPDM_GET_DIGESTS; @@ -146,8 +141,7 @@ static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *se status = libspdm_handle_error_response_main( spdm_context, session_id, &spdm_response_size, - (void **)&spdm_response, SPDM_GET_DIGESTS, SPDM_DIGESTS, - sizeof(libspdm_digests_response_max_t)); + (void **)&spdm_response, SPDM_GET_DIGESTS, SPDM_DIGESTS); if (LIBSPDM_STATUS_IS_ERROR(status)) { goto receive_done; } @@ -186,13 +180,11 @@ static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *se if (session_id == NULL) { status = libspdm_append_message_b(spdm_context, spdm_request, spdm_request_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } status = libspdm_append_message_b(spdm_context, spdm_response, spdm_response_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } } @@ -203,12 +195,6 @@ static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *se LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); } - result = libspdm_verify_peer_digests(spdm_context, spdm_response->digest, digest_count); - if (!result) { - status = LIBSPDM_STATUS_VERIF_FAIL; - goto receive_done; - } - if (total_digest_buffer != NULL) { libspdm_copy_mem(total_digest_buffer, digest_size * digest_count, spdm_response->digest, digest_size * digest_count); @@ -226,48 +212,38 @@ static libspdm_return_t libspdm_try_get_digest(void *context, const uint32_t *se } status = LIBSPDM_STATUS_SUCCESS; + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + receive_done: libspdm_release_receiver_buffer (spdm_context); return status; } -libspdm_return_t libspdm_get_digest(void *context, uint8_t *slot_mask, void *total_digest_buffer) +libspdm_return_t libspdm_get_digest(void *spdm_context, const uint32_t *session_id, + uint8_t *slot_mask, void *total_digest_buffer) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; - spdm_context = context; - spdm_context->crypto_request = true; - retry = spdm_context->retry_times; + context = spdm_context; + context->crypto_request = true; + retry = context->retry_times; + retry_delay_time = context->retry_delay_time; do { - status = libspdm_try_get_digest(spdm_context, NULL, slot_mask, total_digest_buffer); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + status = libspdm_try_get_digest(context, session_id, slot_mask, total_digest_buffer); + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } - } while (retry-- != 0); - return status; -} - -libspdm_return_t libspdm_get_digest_in_session(void *context, const uint32_t *session_id, - uint8_t *slot_mask, void *total_digest_buffer) -{ - libspdm_context_t *spdm_context; - size_t retry; - libspdm_return_t status; - - spdm_context = context; - spdm_context->crypto_request = true; - retry = spdm_context->retry_times; - do { - status = libspdm_try_get_digest(spdm_context, session_id, slot_mask, total_digest_buffer); - if (status != LIBSPDM_STATUS_BUSY_PEER) { - return status; - } + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; } -#endif /*LIBSPDM_ENABLE_CAPABILITY_CERT_CAP*/ +#endif /* LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_measurements.c similarity index 78% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_measurements.c index c6bb752214..09972f1e01 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_measurements.c @@ -14,23 +14,25 @@ bool libspdm_verify_measurement_signature(libspdm_context_t *spdm_context, size_t sign_data_size) { bool result; - const uint8_t *cert_buffer; - size_t cert_buffer_size; void *context; - const uint8_t *cert_chain_data; - size_t cert_chain_data_size; + uint8_t slot_id; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - libspdm_large_managed_buffer_t l1l2; + libspdm_l1l2_managed_buffer_t l1l2; uint8_t *l1l2_buffer; size_t l1l2_buffer_size; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; + const uint8_t *cert_buffer; + size_t cert_buffer_size; #else uint8_t l1l2_hash[LIBSPDM_MAX_HASH_SIZE]; size_t l1l2_hash_size; - uint8_t slot_id; #endif #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT result = libspdm_calculate_l1l2(spdm_context, session_info, &l1l2); + l1l2_buffer = libspdm_get_managed_buffer(&l1l2); + l1l2_buffer_size = libspdm_get_managed_buffer_size(&l1l2); #else l1l2_hash_size = sizeof(l1l2_hash); result = libspdm_calculate_l1l2_hash(spdm_context, session_info, &l1l2_hash_size, l1l2_hash); @@ -40,86 +42,67 @@ bool libspdm_verify_measurement_signature(libspdm_context_t *spdm_context, return false; } -#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - l1l2_buffer = libspdm_get_managed_buffer(&l1l2); - l1l2_buffer_size = libspdm_get_managed_buffer_size(&l1l2); - - result = libspdm_get_peer_cert_chain_data( - spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); - if (!result) { - return false; - } - - /* Get leaf cert from cert chain*/ - result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, - cert_chain_data_size, -1, - &cert_buffer, &cert_buffer_size); - if (!result) { - return false; - } - - result = libspdm_asym_get_public_key_from_x509( - spdm_context->connection_info.algorithm.base_asym_algo, - cert_buffer, cert_buffer_size, &context); - if (!result) { - return false; - } - - result = libspdm_asym_verify( - spdm_context->connection_info.version, SPDM_MEASUREMENTS, - spdm_context->connection_info.algorithm.base_asym_algo, - spdm_context->connection_info.algorithm.base_hash_algo, context, - l1l2_buffer, l1l2_buffer_size, sign_data, sign_data_size); - libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); -#else slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; - LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); - if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != NULL) { - result = libspdm_asym_verify_hash( - spdm_context->connection_info.version, SPDM_MEASUREMENTS, + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xF)); + + if (slot_id == 0xF) { + result = libspdm_asym_get_public_key_from_der( spdm_context->connection_info.algorithm.base_asym_algo, - spdm_context->connection_info.algorithm.base_hash_algo, - spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key, - l1l2_hash, l1l2_hash_size, sign_data, sign_data_size); + spdm_context->local_context.peer_public_key_provision, + spdm_context->local_context.peer_public_key_provision_size, + &context); + if (!result) { + return false; + } + } else { +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_get_peer_cert_chain_data( + spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - FAIL !!!\n")); return false; } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - PASS !!!\n")); - return true; - } - - result = libspdm_get_peer_cert_chain_data( - spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); - if (!result) { - return false; - } - - /* Get leaf cert from cert chain */ - result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, - cert_chain_data_size, -1, - &cert_buffer, &cert_buffer_size); - if (!result) { - return false; - } + /* Get leaf cert from cert chain*/ + result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, + cert_chain_data_size, -1, + &cert_buffer, &cert_buffer_size); + if (!result) { + return false; + } - result = libspdm_asym_get_public_key_from_x509( - spdm_context->connection_info.algorithm.base_asym_algo, - cert_buffer, cert_buffer_size, &context); - if (!result) { - return false; + result = libspdm_asym_get_public_key_from_x509( + spdm_context->connection_info.algorithm.base_asym_algo, + cert_buffer, cert_buffer_size, &context); + if (!result) { + return false; + } +#else + context = spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; + LIBSPDM_ASSERT(context != NULL); +#endif } - result = libspdm_asym_verify_hash( +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_asym_verify_ex( spdm_context->connection_info.version, SPDM_MEASUREMENTS, spdm_context->connection_info.algorithm.base_asym_algo, - spdm_context->connection_info.algorithm.base_hash_algo, context, - l1l2_hash, l1l2_hash_size, sign_data, sign_data_size); + spdm_context->connection_info.algorithm.base_hash_algo, + context, l1l2_buffer, l1l2_buffer_size, sign_data, sign_data_size, + &spdm_context->spdm_10_11_verify_signature_endian); libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); +#else + result = libspdm_asym_verify_hash_ex( + spdm_context->connection_info.version, SPDM_MEASUREMENTS, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, l1l2_hash, l1l2_hash_size, sign_data, sign_data_size, + &spdm_context->spdm_10_11_verify_signature_endian); + if (slot_id == 0xF) { + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); + } #endif if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_measurement_signature - FAIL !!!\n")); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_measurement_signature - FAIL !!!\n")); return false; } @@ -149,7 +132,8 @@ bool libspdm_verify_measurement_signature(libspdm_context_t *spdm_context, * @param responder_nonce If not NULL, a buffer to hold the responder nonce (32 bytes). * **/ -static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_t *session_id, +static libspdm_return_t libspdm_try_get_measurement(libspdm_context_t *spdm_context, + const uint32_t *session_id, uint8_t request_attribute, uint8_t measurement_operation, uint8_t slot_id_param, @@ -159,7 +143,9 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ void *measurement_record, const void *requester_nonce_in, void *requester_nonce, - void *responder_nonce) + void *responder_nonce, + void *opaque_data, + size_t *opaque_data_size) { bool result; libspdm_return_t status; @@ -177,19 +163,16 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ uint16_t opaque_length; void *signature; size_t signature_size; - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; libspdm_session_state_t session_state; uint8_t *message; size_t message_size; size_t transport_header_size; - spdm_context = context; - /* -=[Check Parameters Phase]=- */ LIBSPDM_ASSERT((slot_id_param < SPDM_MAX_SLOT_COUNT) || (slot_id_param == 0xF)); LIBSPDM_ASSERT((slot_id_param != 0xf) || - (spdm_context->local_context.peer_cert_chain_provision_size != 0)); + (spdm_context->local_context.peer_public_key_provision_size != 0)); /* -=[Verify State Phase]=- */ if (!libspdm_is_capabilities_flag_supported( @@ -235,20 +218,17 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_MEASUREMENTS); /* -=[Construct Request Phase]=- */ - if (slot_id_param != 0xf) { - spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id_param; - } else { - spdm_context->connection_info.peer_used_cert_chain_slot_id = - spdm_context->local_context.provisioned_slot_id; - } - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id_param; + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); spdm_request->header.request_response_code = SPDM_GET_MEASUREMENTS; @@ -271,7 +251,7 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ libspdm_copy_mem(spdm_request->nonce, sizeof(spdm_request->nonce), requester_nonce_in, SPDM_NONCE_SIZE); } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientNonce - ")); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "RequesterNonce - ")); LIBSPDM_INTERNAL_DUMP_DATA(spdm_request->nonce, SPDM_NONCE_SIZE); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); spdm_request->slot_id_param = slot_id_param; @@ -326,13 +306,11 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ status = libspdm_handle_error_response_main( spdm_context, session_id, &spdm_response_size, (void **)&spdm_response, - SPDM_GET_MEASUREMENTS, SPDM_MEASUREMENTS, - message_size); + SPDM_GET_MEASUREMENTS, SPDM_MEASUREMENTS); if (LIBSPDM_STATUS_IS_ERROR(status)) { goto receive_done; } } else if (spdm_response->header.request_response_code != SPDM_MEASUREMENTS) { - libspdm_reset_message_m(spdm_context, session_info); status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } @@ -343,13 +321,12 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ if (measurement_operation == SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS) { if (spdm_response->number_of_blocks != 0) { - libspdm_reset_message_m(spdm_context, session_info); status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } } else if (measurement_operation == SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_ALL_MEASUREMENTS) { - if (spdm_response->number_of_blocks == 0) { + if ((spdm_response->number_of_blocks == 0) || (spdm_response->number_of_blocks == 0xff)) { status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } @@ -364,7 +341,6 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ if (measurement_operation == SPDM_GET_MEASUREMENTS_REQUEST_MEASUREMENT_OPERATION_TOTAL_NUMBER_OF_MEASUREMENTS) { if (measurement_record_data_length != 0) { - libspdm_reset_message_m(spdm_context, session_info); status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } @@ -385,14 +361,12 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ if (spdm_response_size < sizeof(spdm_measurements_response_t) + measurement_record_data_length + SPDM_NONCE_SIZE + sizeof(uint16_t)) { - libspdm_reset_message_m(spdm_context, session_info); status = LIBSPDM_STATUS_INVALID_MSG_SIZE; goto receive_done; } if ((spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_11) && ((spdm_response->header.param2 & SPDM_MEASUREMENTS_RESPONSE_SLOT_ID_MASK) != slot_id_param)) { - libspdm_reset_message_m(spdm_context, session_info); status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } @@ -406,12 +380,28 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ libspdm_copy_mem(responder_nonce, SPDM_NONCE_SIZE, nonce, SPDM_NONCE_SIZE); } - opaque_length = *(uint16_t *)ptr; + opaque_length = libspdm_read_uint16((const uint8_t *)ptr); if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if (((spdm_context->connection_info.algorithm.other_params_support & + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_MASK) == + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_NONE) + && (opaque_length != 0)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } ptr += sizeof(uint16_t); + if (opaque_length != 0) { + result = libspdm_process_general_opaque_data_check(spdm_context, opaque_length, ptr); + if (!result) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } if (spdm_response_size < sizeof(spdm_measurements_response_t) + @@ -429,24 +419,23 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ status = libspdm_append_message_m(spdm_context, session_info, spdm_request, spdm_request_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } status = libspdm_append_message_m(spdm_context, session_info, spdm_response, spdm_response_size - signature_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - libspdm_reset_message_m(spdm_context, session_info); - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } - LIBSPDM_DEBUG_CODE( - void *opaque; - opaque = ptr; - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "opaque (0x%x):\n", opaque_length)); - LIBSPDM_INTERNAL_DUMP_HEX(opaque, opaque_length); - ); + if ((opaque_data != NULL) && (opaque_data_size != NULL)) { + if (opaque_length >= *opaque_data_size) { + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + goto receive_done; + } + libspdm_copy_mem(opaque_data, *opaque_data_size, ptr, opaque_length); + *opaque_data_size = opaque_length; + } ptr += opaque_length; signature = ptr; @@ -456,7 +445,6 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ result = libspdm_verify_measurement_signature( spdm_context, session_info, signature, signature_size); if (!result) { - libspdm_reset_message_m(spdm_context, session_info); status = LIBSPDM_STATUS_VERIF_FAIL; goto receive_done; } @@ -480,12 +468,19 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ libspdm_copy_mem(responder_nonce, SPDM_NONCE_SIZE, nonce, SPDM_NONCE_SIZE); } - opaque_length = *(uint16_t *)ptr; + opaque_length = libspdm_read_uint16((const uint8_t *)ptr); if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } ptr += sizeof(uint16_t); + if (opaque_length != 0) { + result = libspdm_process_general_opaque_data_check(spdm_context, opaque_length, ptr); + if (!result) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } if (spdm_response_size < sizeof(spdm_measurements_response_t) + @@ -499,18 +494,24 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ SPDM_NONCE_SIZE + sizeof(uint16_t) + opaque_length; + /* If a signature is not requested then content_changed must be 0. */ + if (spdm_response->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if ((spdm_response->header.param2 & SPDM_MEASUREMENTS_RESPONSE_CONTENT_CHANGE_MASK) + != 0) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } + status = libspdm_append_message_m(spdm_context, session_info, spdm_request, spdm_request_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } status = libspdm_append_message_m(spdm_context, session_info, spdm_response, spdm_response_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - libspdm_reset_message_m(spdm_context, session_info); - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } } @@ -609,11 +610,15 @@ static libspdm_return_t libspdm_try_get_measurement(void *context, const uint32_ #endif /* LIBSPDM_ENABLE_MSG_LOG */ receive_done: + if ((status != LIBSPDM_STATUS_SUCCESS) && + (status != LIBSPDM_STATUS_NOT_READY_PEER)) { + libspdm_reset_message_m(spdm_context, session_info); + } libspdm_release_receiver_buffer (spdm_context); return status; } -libspdm_return_t libspdm_get_measurement(void *context, const uint32_t *session_id, +libspdm_return_t libspdm_get_measurement(void *spdm_context, const uint32_t *session_id, uint8_t request_attribute, uint8_t measurement_operation, uint8_t slot_id_param, @@ -622,27 +627,32 @@ libspdm_return_t libspdm_get_measurement(void *context, const uint32_t *session_ uint32_t *measurement_record_length, void *measurement_record) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; - spdm_context = context; - spdm_context->crypto_request = true; - retry = spdm_context->retry_times; + context = spdm_context; + context->crypto_request = true; + retry = context->retry_times; + retry_delay_time = context->retry_delay_time; do { status = libspdm_try_get_measurement( - spdm_context, session_id, request_attribute, + context, session_id, request_attribute, measurement_operation, slot_id_param, content_changed, number_of_blocks, - measurement_record_length, measurement_record, NULL, NULL, NULL); - if (LIBSPDM_STATUS_BUSY_PEER != status) { + measurement_record_length, measurement_record, + NULL, NULL, NULL, NULL, NULL); + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; } -libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *session_id, +libspdm_return_t libspdm_get_measurement_ex(void *spdm_context, const uint32_t *session_id, uint8_t request_attribute, uint8_t measurement_operation, uint8_t slot_id_param, @@ -652,25 +662,32 @@ libspdm_return_t libspdm_get_measurement_ex(void *context, const uint32_t *sessi void *measurement_record, const void *requester_nonce_in, void *requester_nonce, - void *responder_nonce) + void *responder_nonce, + void *opaque_data, + size_t *opaque_data_size) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; - spdm_context = context; - spdm_context->crypto_request = true; - retry = spdm_context->retry_times; + context = spdm_context; + context->crypto_request = true; + retry = context->retry_times; + retry_delay_time = context->retry_delay_time; do { status = libspdm_try_get_measurement( - spdm_context, session_id, request_attribute, + context, session_id, request_attribute, measurement_operation, slot_id_param, content_changed, number_of_blocks, measurement_record_length, measurement_record, requester_nonce_in, - requester_nonce, responder_nonce); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + requester_nonce, responder_nonce, + opaque_data, opaque_data_size); + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_version.c similarity index 90% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_version.c index 2a5306af3a..6ca0e46bc5 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_version.c @@ -60,14 +60,16 @@ static libspdm_return_t libspdm_try_get_version(libspdm_context_t *spdm_context, libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_GET_VERSION); /* -=[Construct Request Phase]=- */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = SPDM_MESSAGE_VERSION_10; spdm_request->header.request_response_code = SPDM_GET_VERSION; @@ -110,6 +112,12 @@ static libspdm_return_t libspdm_try_get_version(libspdm_context_t *spdm_context, goto receive_done; } if (spdm_response->header.request_response_code == SPDM_ERROR) { + /* Responder shall not respond to the GET_VERSION request message with ErrorCode=ResponseNotReady.*/ + if (spdm_response->header.param1 == SPDM_ERROR_CODE_RESPONSE_NOT_READY) { + /* Received an unexpected error message. */ + status = LIBSPDM_STATUS_ERROR_PEER; + goto receive_done; + } status = libspdm_handle_simple_error_response(spdm_context, spdm_response->header.param1); if (LIBSPDM_STATUS_IS_ERROR(status)) { goto receive_done; @@ -206,16 +214,20 @@ libspdm_return_t libspdm_get_version(libspdm_context_t *spdm_context, spdm_version_number_t *version_number_entry) { size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; spdm_context->crypto_request = false; retry = spdm_context->retry_times; + retry_delay_time = spdm_context->retry_delay_time; do { status = libspdm_try_get_version(spdm_context, version_number_entry_count, version_number_entry); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c similarity index 82% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c index 542b6884bc..a1f48efe98 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c @@ -5,8 +5,8 @@ **/ #include "internal/libspdm_requester_lib.h" -#include "hal/library/platform_lib.h" +#if LIBSPDM_RESPOND_IF_READY_SUPPORT /** * This function sends RESPOND_IF_READY and receives an expected SPDM response. * @@ -16,7 +16,6 @@ * On output, it means the size in bytes of copied response data buffer if RETURN_SUCCESS is returned. * @param response The SPDM response message. * @param expected_response_code Indicate the expected response code. - * @param expected_response_size Indicate the expected response size. * * @retval RETURN_SUCCESS The RESPOND_IF_READY is sent and an expected SPDM response is received. * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. @@ -25,8 +24,7 @@ static libspdm_return_t libspdm_requester_respond_if_ready(libspdm_context_t *sp const uint32_t *session_id, size_t *response_size, void **response, - uint8_t expected_response_code, - size_t expected_response_size) + uint8_t expected_response_code) { libspdm_return_t status; spdm_response_if_ready_request_t *spdm_request; @@ -42,14 +40,16 @@ static libspdm_return_t libspdm_requester_respond_if_ready(libspdm_context_t *sp libspdm_release_receiver_buffer (spdm_context); /* now we can get sender buffer */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_context->crypto_request = true; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); @@ -57,8 +57,7 @@ static libspdm_return_t libspdm_requester_respond_if_ready(libspdm_context_t *sp spdm_request->header.param1 = spdm_context->error_data.request_code; spdm_request->header.param2 = spdm_context->error_data.token; spdm_request_size = sizeof(spdm_response_if_ready_request_t); - status = libspdm_send_spdm_request(spdm_context, session_id, - spdm_request_size, spdm_request); + status = libspdm_send_spdm_request(spdm_context, session_id, spdm_request_size, spdm_request); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_release_sender_buffer (spdm_context); /* need acquire response buffer, so that the caller can release it */ @@ -97,18 +96,15 @@ static libspdm_return_t libspdm_requester_respond_if_ready(libspdm_context_t *sp if (spdm_response->request_response_code != expected_response_code) { return LIBSPDM_STATUS_INVALID_MSG_FIELD; } - /* For response like SPDM_ALGORITHMS, we just can expect the max response size*/ - if (*response_size > expected_response_size) { - return LIBSPDM_STATUS_INVALID_MSG_SIZE; - } + return LIBSPDM_STATUS_SUCCESS; } +#endif /* LIBSPDM_RESPOND_IF_READY_SUPPORT */ -libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t error_code) +libspdm_return_t libspdm_handle_simple_error_response(libspdm_context_t *spdm_context, + uint8_t error_code) { - libspdm_context_t *spdm_context; - - spdm_context = context; + spdm_set_certificate_request_t *last_spdm_request; if (error_code == SPDM_ERROR_CODE_RESPONSE_NOT_READY) { return LIBSPDM_STATUS_NOT_READY_PEER; @@ -118,15 +114,27 @@ libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t err return LIBSPDM_STATUS_BUSY_PEER; } + last_spdm_request = (void *)spdm_context->last_spdm_request; + if ((last_spdm_request->header.request_response_code == SPDM_SET_CERTIFICATE) || + (last_spdm_request->header.request_response_code == SPDM_GET_CSR)) { + + /* Do not check the Responder's CERT_INSTALL_RESET_CAP capability as it may be a 1.2.0 + * Responder and that capability does not exist. */ + + if (error_code == SPDM_ERROR_CODE_RESET_REQUIRED) { + return LIBSPDM_STATUS_RESET_REQUIRED_PEER; + } + } + if (error_code == SPDM_ERROR_CODE_REQUEST_RESYNCH) { - spdm_context->connection_info.connection_state = - LIBSPDM_CONNECTION_STATE_NOT_STARTED; + spdm_context->connection_info.connection_state = LIBSPDM_CONNECTION_STATE_NOT_STARTED; return LIBSPDM_STATUS_RESYNCH_PEER; } return LIBSPDM_STATUS_ERROR_PEER; } +#if LIBSPDM_RESPOND_IF_READY_SUPPORT /** * This function handles RESPONSE_NOT_READY error code. * @@ -137,7 +145,6 @@ libspdm_return_t libspdm_handle_simple_error_response(void *context, uint8_t err * @param response The SPDM response message. * @param original_request_code Indicate the orginal request code. * @param expected_response_code Indicate the expected response code. - * @param expected_response_size Indicate the expected response size. * * @retval RETURN_SUCCESS The RESPOND_IF_READY is sent and an expected SPDM response is received. * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. @@ -147,40 +154,45 @@ static libspdm_return_t libspdm_handle_response_not_ready(libspdm_context_t *spd size_t *response_size, void **response, uint8_t original_request_code, - uint8_t expected_response_code, - size_t expected_response_size) + uint8_t expected_response_code) { spdm_error_response_t *spdm_response; spdm_error_data_response_not_ready_t *extend_error_data; - if(*response_size != sizeof(spdm_error_response_t) + + if(*response_size < sizeof(spdm_error_response_t) + sizeof(spdm_error_data_response_not_ready_t)) { return LIBSPDM_STATUS_INVALID_MSG_SIZE; } spdm_response = *response; - extend_error_data = - (spdm_error_data_response_not_ready_t *)(spdm_response + 1); + extend_error_data = (spdm_error_data_response_not_ready_t *)(spdm_response + 1); LIBSPDM_ASSERT(spdm_response->header.request_response_code == SPDM_ERROR); - LIBSPDM_ASSERT(spdm_response->header.param1 == - SPDM_ERROR_CODE_RESPONSE_NOT_READY); + LIBSPDM_ASSERT(spdm_response->header.param1 == SPDM_ERROR_CODE_RESPONSE_NOT_READY); + if (extend_error_data->request_code != original_request_code) { return LIBSPDM_STATUS_INVALID_MSG_FIELD; } + if (extend_error_data->rd_tm <= 1) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if (extend_error_data->rd_exponent > LIBSPDM_MAX_RDT_EXPONENT) { + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } spdm_context->error_data.rd_exponent = extend_error_data->rd_exponent; spdm_context->error_data.request_code = extend_error_data->request_code; spdm_context->error_data.token = extend_error_data->token; spdm_context->error_data.rd_tm = extend_error_data->rd_tm; - libspdm_sleep_in_us((2 << extend_error_data->rd_exponent)); + libspdm_sleep((uint64_t)1 << extend_error_data->rd_exponent); + return libspdm_requester_respond_if_ready(spdm_context, session_id, response_size, response, - expected_response_code, - expected_response_size); + expected_response_code); } +#endif /* LIBSPDM_RESPOND_IF_READY_SUPPORT */ -#if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP libspdm_return_t libspdm_handle_error_large_response( libspdm_context_t *spdm_context, const uint32_t *session_id, @@ -209,6 +221,10 @@ libspdm_return_t libspdm_handle_error_large_response( size_t large_response_size; size_t large_response_size_so_far; + if (libspdm_get_connection_version(spdm_context) < SPDM_MESSAGE_VERSION_12) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + /* Fail if requester or responder does not support chunk cap */ if (!libspdm_is_capabilities_flag_supported( spdm_context, true, @@ -228,19 +244,18 @@ libspdm_return_t libspdm_handle_error_large_response( chunk_handle = extend_error_data->handle; /* now we can get sender buffer */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; libspdm_get_scratch_buffer(spdm_context, (void**)&scratch_buffer, &scratch_buffer_size); - LIBSPDM_ASSERT(scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); - /* The first LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE bytes of the scratch + /* The first section of the scratch * buffer may be used for other purposes. Use only after that section. */ - large_response = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET; - large_response_capacity = LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY; + large_response = scratch_buffer + libspdm_get_scratch_buffer_large_message_offset(spdm_context); + large_response_capacity = libspdm_get_scratch_buffer_large_message_capacity(spdm_context); /* Temporary send/receive buffers for chunking are in the scratch space */ - message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; - message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + message = scratch_buffer + libspdm_get_scratch_buffer_sender_receiver_offset(spdm_context); + message_size = libspdm_get_scratch_buffer_sender_receiver_capacity(spdm_context); libspdm_zero_mem(large_response, large_response_capacity); large_response_size = 0; @@ -259,7 +274,7 @@ libspdm_return_t libspdm_handle_error_large_response( spdm_request->chunk_seq_no = chunk_seq_no; spdm_request_size = sizeof(spdm_chunk_get_request_t); - LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "CHUNK_GET Handle %d SeqNo %d\n", chunk_handle, chunk_seq_no)); status = libspdm_send_spdm_request(spdm_context, session_id, @@ -322,12 +337,11 @@ libspdm_return_t libspdm_handle_error_large_response( status = LIBSPDM_STATUS_INVALID_MSG_FIELD; break; } - if (large_response_size > large_response_capacity) { - status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + if (large_response_size > spdm_context->local_context.capability.max_spdm_msg_size) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; break; } - } - else { + } else { if (response_size < sizeof(spdm_chunk_response_response_t)) { status = LIBSPDM_STATUS_INVALID_MSG_SIZE; break; @@ -337,8 +351,7 @@ libspdm_return_t libspdm_handle_error_large_response( break; } - if (!(spdm_response->header.param1 & SPDM_CHUNK_GET_RESPONSE_ATTRIBUTE_LAST_CHUNK)) - { + if (!(spdm_response->header.param1 & SPDM_CHUNK_GET_RESPONSE_ATTRIBUTE_LAST_CHUNK)) { if (response_size < SPDM_MIN_DATA_TRANSFER_SIZE_VERSION_12) { status = LIBSPDM_STATUS_INVALID_MSG_SIZE; break; @@ -375,9 +388,7 @@ libspdm_return_t libspdm_handle_error_large_response( if (LIBSPDM_STATUS_IS_SUCCESS(status)) { if (large_response_size_so_far != large_response_size) { status = LIBSPDM_STATUS_INVALID_MSG_FIELD; - } - else if (large_response_size <= response_capacity) - { + } else if (large_response_size <= response_capacity) { libspdm_copy_mem(inout_response, response_capacity, large_response, large_response_size); *inout_response_size = large_response_size; @@ -393,26 +404,26 @@ libspdm_return_t libspdm_handle_error_large_response( libspdm_return_t libspdm_handle_error_response_main( libspdm_context_t *spdm_context, const uint32_t *session_id, size_t *response_size, void **response, - uint8_t original_request_code, uint8_t expected_response_code, - size_t expected_response_size) + uint8_t original_request_code, uint8_t expected_response_code) { spdm_message_header_t *spdm_response; spdm_response = *response; LIBSPDM_ASSERT(spdm_response->request_response_code == SPDM_ERROR); - if ((spdm_response->param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) && - (session_id != NULL)) { + if ((spdm_response->param1 == SPDM_ERROR_CODE_DECRYPT_ERROR) && (session_id != NULL)) { libspdm_free_session_id(spdm_context, *session_id); return LIBSPDM_STATUS_SESSION_MSG_ERROR; } else if(spdm_response->param1 == SPDM_ERROR_CODE_RESPONSE_NOT_READY) { + #if LIBSPDM_RESPOND_IF_READY_SUPPORT return libspdm_handle_response_not_ready(spdm_context, session_id, response_size, response, original_request_code, - expected_response_code, - expected_response_size); + expected_response_code); + #else + return LIBSPDM_STATUS_NOT_READY_PEER; + #endif /* LIBSPDM_RESPOND_IF_READY_SUPPORT */ } else { - return libspdm_handle_simple_error_response(spdm_context, - spdm_response->param1); + return libspdm_handle_simple_error_response(spdm_context, spdm_response->param1); } } diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_heartbeat.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_heartbeat.c new file mode 100644 index 0000000000..4abd298cab --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_heartbeat.c @@ -0,0 +1,170 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "internal/libspdm_requester_lib.h" + +#pragma pack(1) +typedef struct { + spdm_message_header_t header; + uint8_t dummy_data[sizeof(spdm_error_data_response_not_ready_t)]; +} libspdm_heartbeat_response_mine_t; +#pragma pack() + +/** + * This function sends HEARTBEAT to an SPDM Session. + * + * @param spdm_context A pointer to the SPDM context. + * @param session_id The session ID of the session. + * + **/ +static libspdm_return_t libspdm_try_heartbeat(libspdm_context_t *spdm_context, uint32_t session_id) +{ + libspdm_return_t status; + spdm_heartbeat_request_t *spdm_request; + size_t spdm_request_size; + libspdm_heartbeat_response_mine_t *spdm_response; + size_t spdm_response_size; + libspdm_session_info_t *session_info; + libspdm_session_state_t session_state; + uint8_t *message; + size_t message_size; + size_t transport_header_size; + + /* -=[Check Parameters Phase]=- */ + if (libspdm_get_connection_version(spdm_context) < SPDM_MESSAGE_VERSION_11) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + + session_info = libspdm_get_session_info_via_session_id(spdm_context, session_id); + if (session_info == NULL) { + return LIBSPDM_STATUS_INVALID_PARAMETER; + } + + /* -=[Verify State Phase]=- */ + if (!libspdm_is_capabilities_flag_supported( + spdm_context, true, + SPDM_GET_CAPABILITIES_REQUEST_FLAGS_HBEAT_CAP, + SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HBEAT_CAP)) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + session_state = libspdm_secured_message_get_session_state( + session_info->secured_message_context); + if (session_state != LIBSPDM_SESSION_STATE_ESTABLISHED) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + if (session_info->heartbeat_period == 0) { + return LIBSPDM_STATUS_INVALID_STATE_LOCAL; + } + + /* -=[Construct Request Phase]=- */ + transport_header_size = spdm_context->local_context.capability.transport_header_size; + status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); + spdm_request = (void *)(message + transport_header_size); + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; + + spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); + spdm_request->header.request_response_code = SPDM_HEARTBEAT; + spdm_request->header.param1 = 0; + spdm_request->header.param2 = 0; + spdm_request_size = sizeof(spdm_heartbeat_request_t); + + /* -=[Send Request Phase]=- */ + status = libspdm_send_spdm_request(spdm_context, &session_id, spdm_request_size, spdm_request); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + libspdm_release_sender_buffer (spdm_context); + return status; + } + libspdm_release_sender_buffer (spdm_context); + spdm_request = (void *)spdm_context->last_spdm_request; + + libspdm_reset_message_buffer_via_request_code(spdm_context, session_info, SPDM_HEARTBEAT); + + /* -=[Receive Response Phase]=- */ + status = libspdm_acquire_receiver_buffer (spdm_context, &message_size, (void **)&message); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + return status; + } + LIBSPDM_ASSERT (message_size >= transport_header_size); + spdm_response = (void *)(message); + spdm_response_size = message_size; + + libspdm_zero_mem(spdm_response, spdm_response_size); + status = libspdm_receive_spdm_response( + spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + + /* -=[Validate Response Phase]=- */ + if (spdm_response_size < sizeof(spdm_message_header_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + if (spdm_response->header.request_response_code == SPDM_ERROR) { + status = libspdm_handle_error_response_main( + spdm_context, &session_id, &spdm_response_size, + (void **)&spdm_response, SPDM_HEARTBEAT, SPDM_HEARTBEAT_ACK); + if (LIBSPDM_STATUS_IS_ERROR(status)) { + goto receive_done; + } + } else if (spdm_response->header.request_response_code != SPDM_HEARTBEAT_ACK) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + /* this message can only be in secured session + * thus don't need to consider transport layer padding, just check its exact size */ + if (spdm_response_size != sizeof(spdm_heartbeat_response_t)) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + goto receive_done; + } + + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + + status = LIBSPDM_STATUS_SUCCESS; + +receive_done: + libspdm_release_receiver_buffer (spdm_context); + return status; +} + +libspdm_return_t libspdm_heartbeat(void *spdm_context, uint32_t session_id) +{ + size_t retry; + uint64_t retry_delay_time; + libspdm_return_t status; + libspdm_context_t *context; + + context = spdm_context; + context->crypto_request = true; + retry = context->retry_times; + retry_delay_time = context->retry_delay_time; + do { + status = libspdm_try_heartbeat(context, session_id); + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { + return status; + } + + libspdm_sleep(retry_delay_time); + } while (retry-- != 0); + + return status; +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_key_exchange.c similarity index 77% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_key_exchange.c index d00a3294bf..2fcb990427 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_key_exchange.c @@ -5,6 +5,7 @@ **/ #include "internal/libspdm_requester_lib.h" +#include "internal/libspdm_secured_message_lib.h" #if LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP @@ -44,10 +45,12 @@ bool libspdm_verify_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, uint8_t calc_hmac_data[LIBSPDM_MAX_HASH_SIZE]; bool result; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + uint8_t slot_id; uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; - uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + uint8_t *th_curr_data; size_t th_curr_data_size; + libspdm_th_managed_buffer_t th_curr; uint8_t hash_data[LIBSPDM_MAX_HASH_SIZE]; #endif @@ -55,19 +58,27 @@ bool libspdm_verify_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, LIBSPDM_ASSERT(hash_size == hmac_data_size); #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - result = libspdm_get_peer_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } if (!result) { return false; } - th_curr_data_size = sizeof(th_curr_data); result = libspdm_calculate_th_for_exchange( spdm_context, session_info, cert_chain_buffer, - cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + cert_chain_buffer_size, &th_curr); if (!result) { return false; } + th_curr_data = libspdm_get_managed_buffer(&th_curr); + th_curr_data_size = libspdm_get_managed_buffer_size(&th_curr); result = libspdm_hash_all (spdm_context->connection_info.algorithm.base_hash_algo, th_curr_data, th_curr_data_size, hash_data); @@ -92,8 +103,8 @@ bool libspdm_verify_key_exchange_rsp_hmac(libspdm_context_t *spdm_context, LIBSPDM_INTERNAL_DUMP_DATA(calc_hmac_data, hash_size); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); - if (libspdm_const_compare_mem(calc_hmac_data, hmac_data, hash_size) != 0) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_hmac - FAIL !!!\n")); + if (!libspdm_consttime_is_mem_equal(calc_hmac_data, hmac_data, hash_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_key_exchange_hmac - FAIL !!!\n")); return false; } LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_hmac - PASS !!!\n")); @@ -106,18 +117,18 @@ bool libspdm_verify_key_exchange_rsp_signature( const void *sign_data, const size_t sign_data_size) { bool result; - const uint8_t *cert_chain_data; - size_t cert_chain_data_size; - const uint8_t *cert_buffer; - size_t cert_buffer_size; void *context; + uint8_t slot_id; #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT uint8_t *cert_chain_buffer; size_t cert_chain_buffer_size; - uint8_t th_curr_data[LIBSPDM_MAX_MESSAGE_BUFFER_SIZE]; + uint8_t *th_curr_data; size_t th_curr_data_size; -#else - uint8_t slot_id; + libspdm_th_managed_buffer_t th_curr; + const uint8_t *cert_chain_data; + size_t cert_chain_data_size; + const uint8_t *cert_buffer; + size_t cert_buffer_size; #endif #if !(LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT) || (LIBSPDM_DEBUG_PRINT_ENABLE) size_t hash_size; @@ -126,20 +137,29 @@ bool libspdm_verify_key_exchange_rsp_signature( hash_size = libspdm_get_hash_size(spdm_context->connection_info.algorithm.base_hash_algo); #endif + slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; + LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xFF)); + #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - result = libspdm_get_peer_cert_chain_buffer( - spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + if (slot_id == 0xFF) { + result = libspdm_get_peer_public_key_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } else { + result = libspdm_get_peer_cert_chain_buffer( + spdm_context, (const void **)&cert_chain_buffer, &cert_chain_buffer_size); + } if (!result) { return false; } - th_curr_data_size = sizeof(th_curr_data); result = libspdm_calculate_th_for_exchange( spdm_context, session_info, cert_chain_buffer, - cert_chain_buffer_size, &th_curr_data_size, th_curr_data); + cert_chain_buffer_size, &th_curr); if (!result) { return false; } + th_curr_data = libspdm_get_managed_buffer(&th_curr); + th_curr_data_size = libspdm_get_managed_buffer_size(&th_curr); /* Debug code only - required for debug print of th_curr hash below*/ LIBSPDM_DEBUG_CODE( @@ -164,53 +184,25 @@ bool libspdm_verify_key_exchange_rsp_signature( LIBSPDM_INTERNAL_DUMP_DATA(sign_data, sign_data_size); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); - #if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT - /* Get leaf cert from cert chain */ - result = libspdm_get_peer_cert_chain_data( - spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); - if (!result) { - return false; - } - result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, - cert_chain_data_size, -1, - &cert_buffer, &cert_buffer_size); - if (!result) { - return false; - } - - result = libspdm_asym_get_public_key_from_x509( - spdm_context->connection_info.algorithm.base_asym_algo, - cert_buffer, cert_buffer_size, &context); - if (!result) { - return false; - } - - result = libspdm_asym_verify( - spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, - spdm_context->connection_info.algorithm.base_asym_algo, - spdm_context->connection_info.algorithm.base_hash_algo, context, - th_curr_data, th_curr_data_size, sign_data, sign_data_size); - libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); -#else - slot_id = spdm_context->connection_info.peer_used_cert_chain_slot_id; - LIBSPDM_ASSERT(slot_id < SPDM_MAX_SLOT_COUNT); - if (spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key != NULL) { - result = libspdm_asym_verify_hash( - spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + if (slot_id == 0xFF) { + result = libspdm_asym_get_public_key_from_der( spdm_context->connection_info.algorithm.base_asym_algo, - spdm_context->connection_info.algorithm.base_hash_algo, - spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key, - hash_data, hash_size, sign_data, sign_data_size); + spdm_context->local_context.peer_public_key_provision, + spdm_context->local_context.peer_public_key_provision_size, + &context); + if (!result) { + return false; + } } else { +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT /* Get leaf cert from cert chain*/ result = libspdm_get_peer_cert_chain_data( spdm_context, (const void **)&cert_chain_data, &cert_chain_data_size); if (!result) { return false; } - result = libspdm_x509_get_cert_from_cert_chain(cert_chain_data, - cert_chain_data_size, -1, - &cert_buffer, &cert_buffer_size); + result = libspdm_x509_get_cert_from_cert_chain( + cert_chain_data, cert_chain_data_size, -1, &cert_buffer, &cert_buffer_size); if (!result) { return false; } @@ -221,17 +213,33 @@ bool libspdm_verify_key_exchange_rsp_signature( if (!result) { return false; } +#else + context = spdm_context->connection_info.peer_used_cert_chain[slot_id].leaf_cert_public_key; + LIBSPDM_ASSERT(context != NULL); +#endif + } - result = libspdm_asym_verify_hash( - spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, - spdm_context->connection_info.algorithm.base_asym_algo, - spdm_context->connection_info.algorithm.base_hash_algo, context, - hash_data, hash_size, sign_data, sign_data_size); +#if LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT + result = libspdm_asym_verify_ex( + spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, th_curr_data, th_curr_data_size, sign_data, sign_data_size, + &spdm_context->spdm_10_11_verify_signature_endian); + libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); +#else + result = libspdm_asym_verify_hash_ex( + spdm_context->connection_info.version, SPDM_KEY_EXCHANGE_RSP, + spdm_context->connection_info.algorithm.base_asym_algo, + spdm_context->connection_info.algorithm.base_hash_algo, + context, hash_data, hash_size, sign_data, sign_data_size, + &spdm_context->spdm_10_11_verify_signature_endian); + if (slot_id == 0xFF) { libspdm_asym_free(spdm_context->connection_info.algorithm.base_asym_algo, context); } #endif if (!result) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_signature - FAIL !!!\n")); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "!!! verify_key_exchange_signature - FAIL !!!\n")); return false; } LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "!!! verify_key_exchange_signature - PASS !!!\n")); @@ -260,8 +268,9 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( uint8_t *heartbeat_period, uint8_t *req_slot_id_param, void *measurement_hash, const void *requester_random_in, - void *requester_random, - void *responder_random) + void *requester_random, void *responder_random, + const void *requester_opaque_data, size_t requester_opaque_data_size, + void *responder_opaque_data, size_t *responder_opaque_data_size) { bool result; libspdm_return_t status; @@ -292,9 +301,16 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( /* -=[Check Parameters Phase]=- */ LIBSPDM_ASSERT((slot_id < SPDM_MAX_SLOT_COUNT) || (slot_id == 0xff)); LIBSPDM_ASSERT((slot_id != 0xff) || - (spdm_context->local_context.peer_cert_chain_provision_size != 0)); + (spdm_context->local_context.peer_public_key_provision_size != 0)); + LIBSPDM_ASSERT(measurement_hash_type == SPDM_KEY_EXCHANGE_REQUEST_NO_MEASUREMENT_SUMMARY_HASH || + measurement_hash_type == SPDM_KEY_EXCHANGE_REQUEST_TCB_COMPONENT_MEASUREMENT_HASH || + measurement_hash_type == SPDM_KEY_EXCHANGE_REQUEST_ALL_MEASUREMENTS_HASH); /* -=[Verify State Phase]=- */ + if (libspdm_get_connection_version(spdm_context) < SPDM_MESSAGE_VERSION_11) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (!libspdm_is_capabilities_flag_supported( spdm_context, true, SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_EX_CAP, @@ -304,30 +320,32 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( if (spdm_context->connection_info.connection_state < LIBSPDM_CONNECTION_STATE_NEGOTIATED) { return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } + if (libspdm_get_connection_version(spdm_context) >= SPDM_MESSAGE_VERSION_12) { + if ((spdm_context->connection_info.algorithm.other_params_support & + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_MASK) != SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_1) { + return LIBSPDM_STATUS_INVALID_STATE_PEER; + } + } - req_session_id = libspdm_allocate_req_session_id(spdm_context); - if (req_session_id == ((INVALID_SESSION_ID & 0xFFFF0000) >> 16)) - { + req_session_id = libspdm_allocate_req_session_id(spdm_context, false); + if (req_session_id == (INVALID_SESSION_ID & 0xFFFF)) { return LIBSPDM_STATUS_SESSION_NUMBER_EXCEED; } libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_KEY_EXCHANGE); /* -=[Construct Request Phase]=- */ - if (slot_id != 0xff) { - spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; - } else { - spdm_context->connection_info.peer_used_cert_chain_slot_id = - spdm_context->local_context.provisioned_slot_id; - } - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + spdm_context->connection_info.peer_used_cert_chain_slot_id = slot_id; + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); spdm_request->header.request_response_code = SPDM_KEY_EXCHANGE; @@ -342,7 +360,7 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( libspdm_copy_mem(spdm_request->random_data, sizeof(spdm_request->random_data), requester_random_in, SPDM_RANDOM_DATA_SIZE); } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientRandomData (0x%x) - ", + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "RequesterRandomData (0x%x) - ", SPDM_RANDOM_DATA_SIZE)); LIBSPDM_INTERNAL_DUMP_DATA(spdm_request->random_data, SPDM_RANDOM_DATA_SIZE); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); @@ -379,17 +397,29 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( libspdm_release_sender_buffer (spdm_context); return LIBSPDM_STATUS_CRYPTO_ERROR; } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ClientKey (0x%x):\n", dhe_key_size)); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "RequesterKey (0x%x):\n", dhe_key_size)); LIBSPDM_INTERNAL_DUMP_HEX(ptr, dhe_key_size); ptr += dhe_key_size; - opaque_key_exchange_req_size = - libspdm_get_opaque_data_supported_version_data_size(spdm_context); - *(uint16_t *)ptr = (uint16_t)opaque_key_exchange_req_size; - ptr += sizeof(uint16_t); - status = libspdm_build_opaque_data_supported_version_data( - spdm_context, &opaque_key_exchange_req_size, ptr); - LIBSPDM_ASSERT(status == LIBSPDM_STATUS_SUCCESS); + if (requester_opaque_data != NULL) { + LIBSPDM_ASSERT(requester_opaque_data_size <= SPDM_MAX_OPAQUE_DATA_SIZE); + + libspdm_write_uint16(ptr, (uint16_t)requester_opaque_data_size); + ptr += sizeof(uint16_t); + + libspdm_copy_mem(ptr, + (spdm_request_size - (sizeof(spdm_key_exchange_request_t) + dhe_key_size)), + requester_opaque_data, requester_opaque_data_size); + opaque_key_exchange_req_size = requester_opaque_data_size; + } else { + opaque_key_exchange_req_size = + libspdm_get_opaque_data_supported_version_data_size(spdm_context); + libspdm_write_uint16(ptr, (uint16_t)opaque_key_exchange_req_size); + ptr += sizeof(uint16_t); + + libspdm_build_opaque_data_supported_version_data( + spdm_context, &opaque_key_exchange_req_size, ptr); + } ptr += opaque_key_exchange_req_size; spdm_request_size = (size_t)ptr - (size_t)spdm_request; @@ -442,7 +472,7 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( status = libspdm_handle_error_response_main( spdm_context, NULL, &spdm_response_size, (void **)&spdm_response, SPDM_KEY_EXCHANGE, - SPDM_KEY_EXCHANGE_RSP, sizeof(libspdm_key_exchange_response_max_t)); + SPDM_KEY_EXCHANGE_RSP); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_secured_message_dhe_free( spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); @@ -499,24 +529,14 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } - if ((*req_slot_id_param != 0xF) && (*req_slot_id_param >= SPDM_MAX_SLOT_COUNT)) { - libspdm_secured_message_dhe_free( - spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); - status = LIBSPDM_STATUS_INVALID_MSG_FIELD; - goto receive_done; - } - if ((mut_auth_requested != SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED) && - (*req_slot_id_param != 0)) { - libspdm_secured_message_dhe_free( - spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); - status = LIBSPDM_STATUS_INVALID_MSG_FIELD; - goto receive_done; + if (mut_auth_requested == SPDM_KEY_EXCHANGE_RESPONSE_MUT_AUTH_REQUESTED) { + if ((*req_slot_id_param != 0xF) && (*req_slot_id_param >= SPDM_MAX_SLOT_COUNT)) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } } - } else if (*req_slot_id_param != 0) { - libspdm_secured_message_dhe_free( - spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); - status = LIBSPDM_STATUS_INVALID_MSG_FIELD; - goto receive_done; } signature_size = libspdm_get_asym_signature_size( @@ -541,7 +561,7 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( goto receive_done; } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ServerRandomData (0x%x) - ", SPDM_RANDOM_DATA_SIZE)); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ResponderRandomData (0x%x) - ", SPDM_RANDOM_DATA_SIZE)); LIBSPDM_INTERNAL_DUMP_DATA(spdm_response->random_data, SPDM_RANDOM_DATA_SIZE); LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "\n")); if (responder_random != NULL) { @@ -549,7 +569,7 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( spdm_response->random_data, SPDM_RANDOM_DATA_SIZE); } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ServerKey (0x%x):\n", dhe_key_size)); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "ResponderKey (0x%x):\n", dhe_key_size)); LIBSPDM_INTERNAL_DUMP_HEX(spdm_response->exchange_data, dhe_key_size); ptr = spdm_response->exchange_data; @@ -563,7 +583,7 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( ptr += measurement_summary_hash_size; - opaque_length = *(uint16_t *)ptr; + opaque_length = libspdm_read_uint16((const uint8_t *)ptr); if (opaque_length > SPDM_MAX_OPAQUE_DATA_SIZE) { libspdm_secured_message_dhe_free( spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); @@ -581,6 +601,13 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( goto receive_done; } if (opaque_length != 0) { + result = libspdm_process_general_opaque_data_check(spdm_context, opaque_length, ptr); + if (!result) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } status = libspdm_process_opaque_data_version_selection_data( spdm_context, opaque_length, ptr); if (LIBSPDM_STATUS_IS_ERROR(status)) { @@ -591,6 +618,17 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( } } + if ((responder_opaque_data != NULL) && (responder_opaque_data_size != NULL)) { + if (opaque_length >= *responder_opaque_data_size) { + libspdm_secured_message_dhe_free( + spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); + status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; + goto receive_done; + } + libspdm_copy_mem(responder_opaque_data, *responder_opaque_data_size, ptr, opaque_length); + *responder_opaque_data_size = opaque_length; + } + ptr += opaque_length; spdm_response_size = sizeof(spdm_key_exchange_response_t) + @@ -615,7 +653,6 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( libspdm_free_session_id(spdm_context, *session_id); libspdm_secured_message_dhe_free( spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } @@ -625,7 +662,6 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( libspdm_free_session_id(spdm_context, *session_id); libspdm_secured_message_dhe_free( spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } @@ -648,7 +684,6 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( libspdm_free_session_id(spdm_context, *session_id); libspdm_secured_message_dhe_free( spdm_context->connection_info.algorithm.dhe_named_group, dhe_context); - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } @@ -669,7 +704,8 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( result = libspdm_calculate_th1_hash(spdm_context, session_info, true, th1_hash_data); if (!result) { libspdm_free_session_id(spdm_context, *session_id); - return LIBSPDM_STATUS_CRYPTO_ERROR; + status = LIBSPDM_STATUS_CRYPTO_ERROR; + goto receive_done; } result = libspdm_generate_session_handshake_key( session_info->secured_message_context, th1_hash_data); @@ -698,7 +734,6 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( status = libspdm_append_message_k(spdm_context, session_info, true, verify_data, hmac_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { libspdm_free_session_id(spdm_context, *session_id); - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } } @@ -715,6 +750,11 @@ static libspdm_return_t libspdm_try_send_receive_key_exchange( libspdm_secured_message_set_session_state( session_info->secured_message_context, LIBSPDM_SESSION_STATE_HANDSHAKING); + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + status = LIBSPDM_STATUS_SUCCESS; receive_done: @@ -729,18 +769,23 @@ libspdm_return_t libspdm_send_receive_key_exchange( uint8_t *req_slot_id_param, void *measurement_hash) { size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; spdm_context->crypto_request = true; retry = spdm_context->retry_times; + retry_delay_time = spdm_context->retry_delay_time; do { status = libspdm_try_send_receive_key_exchange( spdm_context, measurement_hash_type, slot_id, session_policy, session_id, heartbeat_period, req_slot_id_param, - measurement_hash, NULL, NULL, NULL); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + measurement_hash, + NULL, NULL, NULL, NULL, 0, NULL, NULL); + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; @@ -752,23 +797,32 @@ libspdm_return_t libspdm_send_receive_key_exchange_ex( uint8_t *heartbeat_period, uint8_t *req_slot_id_param, void *measurement_hash, const void *requester_random_in, - void *requester_random, - void *responder_random) + void *requester_random, void *responder_random, + const void *requester_opaque_data, + size_t requester_opaque_data_size, + void *responder_opaque_data, + size_t *responder_opaque_data_size) { size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; spdm_context->crypto_request = true; retry = spdm_context->retry_times; + retry_delay_time = spdm_context->retry_delay_time; do { status = libspdm_try_send_receive_key_exchange( spdm_context, measurement_hash_type, slot_id, session_policy, session_id, heartbeat_period, req_slot_id_param, measurement_hash, requester_random_in, - requester_random, responder_random); - if (LIBSPDM_STATUS_BUSY_PEER != status) { + requester_random, responder_random, + requester_opaque_data, requester_opaque_data_size, + responder_opaque_data, responder_opaque_data_size); + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_key_update.c similarity index 82% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_key_update.c index 0679737cbb..a83a5df426 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_key_update.c @@ -5,6 +5,7 @@ **/ #include "internal/libspdm_requester_lib.h" +#include "internal/libspdm_secured_message_lib.h" #pragma pack(1) typedef struct { @@ -30,7 +31,8 @@ typedef struct { * @retval RETURN_DEVICE_ERROR A device error occurs when communicates with the device. * @retval RETURN_SECURITY_VIOLATION Any verification fails. **/ -static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_id, +static libspdm_return_t libspdm_try_key_update(libspdm_context_t *spdm_context, + uint32_t session_id, bool single_direction, bool *key_updated) { libspdm_return_t status; @@ -39,14 +41,16 @@ static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_i size_t spdm_request_size; libspdm_key_update_response_mine_t *spdm_response; size_t spdm_response_size; - libspdm_context_t *spdm_context; libspdm_session_info_t *session_info; libspdm_session_state_t session_state; uint8_t *message; size_t message_size; size_t transport_header_size; - spdm_context = context; + if (libspdm_get_connection_version(spdm_context) < SPDM_MESSAGE_VERSION_11) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } + if (!libspdm_is_capabilities_flag_supported( spdm_context, true, SPDM_GET_CAPABILITIES_REQUEST_FLAGS_KEY_UPD_CAP, @@ -76,14 +80,16 @@ static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_i /* Update key*/ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); spdm_request->header.request_response_code = SPDM_KEY_UPDATE; @@ -141,16 +147,17 @@ static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_i spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response); if (!LIBSPDM_STATUS_IS_ERROR(status)) { - if (spdm_response_size < sizeof(spdm_message_header_t)) { - status = LIBSPDM_STATUS_INVALID_MSG_SIZE; - } else if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { - status = LIBSPDM_STATUS_INVALID_MSG_FIELD; - } else if (spdm_response->header.request_response_code == SPDM_ERROR) { + if (spdm_response->header.request_response_code == SPDM_ERROR) { status = libspdm_handle_error_response_main( spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response, - SPDM_KEY_UPDATE, SPDM_KEY_UPDATE_ACK, - sizeof(libspdm_key_update_response_mine_t)); + SPDM_KEY_UPDATE, SPDM_KEY_UPDATE_ACK); + } else if (spdm_response_size != sizeof(spdm_key_update_response_t)) { + /* this message can only be in secured session thus + * don't need to consider transport layer padding, just check its exact size */ + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + } else if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; } else if ((spdm_response->header.request_response_code != SPDM_KEY_UPDATE_ACK) || (spdm_response->header.param1 != spdm_request->header.param1) || @@ -210,6 +217,11 @@ static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_i return LIBSPDM_STATUS_CRYPTO_ERROR; } + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + libspdm_release_receiver_buffer (spdm_context); } @@ -218,19 +230,20 @@ static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_i /* Verify key*/ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); spdm_request->header.request_response_code = SPDM_KEY_UPDATE; - spdm_request->header.param1 = - SPDM_KEY_UPDATE_OPERATIONS_TABLE_VERIFY_NEW_KEY; + spdm_request->header.param1 = SPDM_KEY_UPDATE_OPERATIONS_TABLE_VERIFY_NEW_KEY; spdm_request->header.param2 = 1; if(!libspdm_get_random_number(sizeof(spdm_request->header.param2), &spdm_request->header.param2)) { @@ -265,22 +278,12 @@ static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_i libspdm_release_receiver_buffer (spdm_context); return status; } - if (spdm_response_size < sizeof(spdm_message_header_t)) { - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); - libspdm_release_receiver_buffer (spdm_context); - return LIBSPDM_STATUS_INVALID_MSG_SIZE; - } - if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { - libspdm_release_receiver_buffer (spdm_context); - return LIBSPDM_STATUS_INVALID_MSG_FIELD; - } if (spdm_response->header.request_response_code == SPDM_ERROR) { status = libspdm_handle_error_response_main( spdm_context, &session_id, &spdm_response_size, (void **)&spdm_response, - SPDM_KEY_UPDATE, SPDM_KEY_UPDATE_ACK, - sizeof(libspdm_key_update_response_mine_t)); + SPDM_KEY_UPDATE, SPDM_KEY_UPDATE_ACK); if (LIBSPDM_STATUS_IS_ERROR(status)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); libspdm_release_receiver_buffer (spdm_context); @@ -288,6 +291,19 @@ static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_i } } + /* this message can only be in secured session + * thus don't need to consider transport layer padding, just check its exact size */ + if (spdm_response_size != sizeof(spdm_key_update_response_t)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Failed\n", session_id)); + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_SIZE; + } + + if (spdm_response->header.spdm_version != spdm_request->header.spdm_version) { + libspdm_release_receiver_buffer (spdm_context); + return LIBSPDM_STATUS_INVALID_MSG_FIELD; + } + if ((spdm_response->header.request_response_code != SPDM_KEY_UPDATE_ACK) || (spdm_response->header.param1 != spdm_request->header.param1) || @@ -298,28 +314,37 @@ static libspdm_return_t libspdm_try_key_update(void *context, uint32_t session_i } LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "SpdmVerifyKey[%x] Success\n", session_id)); + /* -=[Log Message Phase]=- */ + #if LIBSPDM_ENABLE_MSG_LOG + libspdm_append_msg_log(spdm_context, spdm_response, spdm_response_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + libspdm_release_receiver_buffer (spdm_context); return LIBSPDM_STATUS_SUCCESS; } -libspdm_return_t libspdm_key_update(void *context, uint32_t session_id, +libspdm_return_t libspdm_key_update(void *spdm_context, uint32_t session_id, bool single_direction) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; bool key_updated; - spdm_context = context; + context = spdm_context; key_updated = false; - spdm_context->crypto_request = true; - retry = spdm_context->retry_times; + context->crypto_request = true; + retry = context->retry_times; + retry_delay_time = context->retry_delay_time; do { - status = libspdm_try_key_update(context, session_id, + status = libspdm_try_key_update(spdm_context, session_id, single_direction, &key_updated); - if (LIBSPDM_STATUS_BUSY_PEER != status) { + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c similarity index 84% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c index 496b97ff1c..23abff6e53 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c @@ -18,7 +18,8 @@ typedef struct { uint8_t ext_asym_count; uint8_t ext_hash_count; uint16_t reserved3; - spdm_negotiate_algorithms_common_struct_table_t struct_table[4]; + spdm_negotiate_algorithms_common_struct_table_t struct_table[ + SPDM_NEGOTIATE_ALGORITHMS_MAX_NUM_STRUCT_TABLE_ALG]; } libspdm_negotiate_algorithms_request_mine_t; typedef struct { @@ -35,7 +36,8 @@ typedef struct { uint16_t reserved3; uint32_t ext_asym_sel; uint32_t ext_hash_sel; - spdm_negotiate_algorithms_common_struct_table_t struct_table[4]; + spdm_negotiate_algorithms_common_struct_table_t struct_table[ + SPDM_NEGOTIATE_ALGORITHMS_MAX_NUM_STRUCT_TABLE_ALG]; } libspdm_algorithms_response_max_t; #pragma pack() @@ -72,7 +74,7 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm libspdm_algorithms_response_max_t *spdm_response; size_t spdm_response_size; uint32_t algo_size; - size_t index; + size_t index = 0; spdm_negotiate_algorithms_common_struct_table_t *struct_table; uint8_t fixed_alg_size; uint8_t ext_alg_count; @@ -80,6 +82,7 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm size_t message_size; size_t transport_header_size; uint8_t alg_type_pre; + uint8_t req_param1 = 0; /* -=[Verify State Phase]=- */ if (spdm_context->connection_info.connection_state != @@ -90,21 +93,40 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm libspdm_reset_message_buffer_via_request_code(spdm_context, NULL, SPDM_NEGOTIATE_ALGORITHMS); /* -=[Construct Request Phase]=- */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; status = libspdm_acquire_sender_buffer (spdm_context, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { return status; } - LIBSPDM_ASSERT (message_size >= transport_header_size); + LIBSPDM_ASSERT (message_size >= transport_header_size + + spdm_context->local_context.capability.transport_tail_size); spdm_request = (void *)(message + transport_header_size); - spdm_request_size = message_size - transport_header_size; + spdm_request_size = message_size - transport_header_size - + spdm_context->local_context.capability.transport_tail_size; libspdm_zero_mem(spdm_request, sizeof(libspdm_negotiate_algorithms_request_mine_t)); spdm_request->header.spdm_version = libspdm_get_connection_version (spdm_context); if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { - spdm_request->length = sizeof(libspdm_negotiate_algorithms_request_mine_t); - /* Number of Algorithms Structure Tables*/ - spdm_request->header.param1 = 4; + /* Number of Algorithms Structure Tables based on supported algorithms */ + if (spdm_context->local_context.algorithm.dhe_named_group) { + req_param1++; + } + if (spdm_context->local_context.algorithm.aead_cipher_suite) { + req_param1++; + } + if (spdm_context->local_context.algorithm.req_base_asym_alg) { + req_param1++; + } + if (spdm_context->local_context.algorithm.key_schedule) { + req_param1++; + } + LIBSPDM_ASSERT(req_param1 <= + SPDM_NEGOTIATE_ALGORITHMS_MAX_NUM_STRUCT_TABLE_ALG); + spdm_request->header.param1 = req_param1; + spdm_request->length = sizeof(libspdm_negotiate_algorithms_request_mine_t) - + ((SPDM_NEGOTIATE_ALGORITHMS_MAX_NUM_STRUCT_TABLE_ALG - + req_param1) * + sizeof(spdm_negotiate_algorithms_common_struct_table_t)); } else { spdm_request->length = sizeof(libspdm_negotiate_algorithms_request_mine_t) - sizeof(spdm_request->struct_table); @@ -122,24 +144,42 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm spdm_request->base_hash_algo = spdm_context->local_context.algorithm.base_hash_algo; spdm_request->ext_asym_count = 0; spdm_request->ext_hash_count = 0; - spdm_request->struct_table[0].alg_type = SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE; - spdm_request->struct_table[0].alg_count = 0x20; - spdm_request->struct_table[0].alg_supported = - spdm_context->local_context.algorithm.dhe_named_group; - spdm_request->struct_table[1].alg_type = SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD; - spdm_request->struct_table[1].alg_count = 0x20; - spdm_request->struct_table[1].alg_supported = - spdm_context->local_context.algorithm.aead_cipher_suite; - spdm_request->struct_table[2].alg_type = - SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG; - spdm_request->struct_table[2].alg_count = 0x20; - spdm_request->struct_table[2].alg_supported = - spdm_context->local_context.algorithm.req_base_asym_alg; - spdm_request->struct_table[3].alg_type = - SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE; - spdm_request->struct_table[3].alg_count = 0x20; - spdm_request->struct_table[3].alg_supported = - spdm_context->local_context.algorithm.key_schedule; + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_11) { + /* ReqAlgStruct order based on by AlgType */ + if (spdm_context->local_context.algorithm.dhe_named_group) { + spdm_request->struct_table[index].alg_type = + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_DHE; + spdm_request->struct_table[index].alg_count = 0x20; + spdm_request->struct_table[index].alg_supported = + spdm_context->local_context.algorithm.dhe_named_group; + index++; + } + if (spdm_context->local_context.algorithm.aead_cipher_suite) { + spdm_request->struct_table[index].alg_type = + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_AEAD; + spdm_request->struct_table[index].alg_count = 0x20; + spdm_request->struct_table[index].alg_supported = + spdm_context->local_context.algorithm.aead_cipher_suite; + index++; + } + if (spdm_context->local_context.algorithm.req_base_asym_alg) { + spdm_request->struct_table[index].alg_type = + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_REQ_BASE_ASYM_ALG; + spdm_request->struct_table[index].alg_count = 0x20; + spdm_request->struct_table[index].alg_supported = + spdm_context->local_context.algorithm.req_base_asym_alg; + index++; + } + if (spdm_context->local_context.algorithm.key_schedule) { + spdm_request->struct_table[index].alg_type = + SPDM_NEGOTIATE_ALGORITHMS_STRUCT_TABLE_ALG_TYPE_KEY_SCHEDULE; + spdm_request->struct_table[index].alg_count = 0x20; + spdm_request->struct_table[index].alg_supported = + spdm_context->local_context.algorithm.key_schedule; + index++; + } + LIBSPDM_ASSERT(index == spdm_request->header.param1); + } spdm_request_size = spdm_request->length; /* -=[Send Request Phase]=- */ @@ -193,6 +233,13 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } + if (spdm_request->header.spdm_version >= SPDM_MESSAGE_VERSION_12) { + if (!libspdm_onehot0(spdm_response->other_params_selection & + SPDM_ALGORITHMS_OPAQUE_DATA_FORMAT_MASK)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + goto receive_done; + } + } if (!libspdm_onehot0(spdm_response->measurement_hash_algo)) { status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; @@ -287,13 +334,11 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm /* -=[Process Response Phase]=- */ status = libspdm_append_message_a(spdm_context, spdm_request, spdm_request_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } status = libspdm_append_message_a(spdm_context, spdm_response, spdm_response_size); if (LIBSPDM_STATUS_IS_ERROR(status)) { - status = LIBSPDM_STATUS_BUFFER_FULL; goto receive_done; } @@ -313,7 +358,7 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP) && (spdm_request->measurement_specification != 0)) { if (spdm_context->connection_info.algorithm.measurement_spec != - SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF) { + SPDM_MEASUREMENT_SPECIFICATION_DMTF) { status = LIBSPDM_STATUS_INVALID_MSG_FIELD; goto receive_done; } @@ -496,6 +541,7 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm spdm_context->connection_info.algorithm.aead_cipher_suite = 0; spdm_context->connection_info.algorithm.req_base_asym_alg = 0; spdm_context->connection_info.algorithm.key_schedule = 0; + spdm_context->connection_info.algorithm.other_params_support = 0; } /* -=[Update State Phase]=- */ @@ -516,15 +562,19 @@ static libspdm_return_t libspdm_try_negotiate_algorithms(libspdm_context_t *spdm libspdm_return_t libspdm_negotiate_algorithms(libspdm_context_t *spdm_context) { size_t retry; + uint64_t retry_delay_time; libspdm_return_t status; spdm_context->crypto_request = false; retry = spdm_context->retry_times; + retry_delay_time = spdm_context->retry_delay_time; do { status = libspdm_try_negotiate_algorithms(spdm_context); - if (status != LIBSPDM_STATUS_BUSY_PEER) { + if ((status != LIBSPDM_STATUS_BUSY_PEER) || (retry == 0)) { return status; } + + libspdm_sleep(retry_delay_time); } while (retry-- != 0); return status; diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_send_receive.c similarity index 72% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_send_receive.c index 6272dff9ba..b24fb22030 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_send_receive.c @@ -5,12 +5,13 @@ **/ #include "internal/libspdm_requester_lib.h" +#include "internal/libspdm_secured_message_lib.h" -libspdm_return_t libspdm_send_request(void *context, const uint32_t *session_id, +libspdm_return_t libspdm_send_request(void *spdm_context, const uint32_t *session_id, bool is_app_message, size_t request_size, void *request) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; libspdm_return_t status; uint8_t *message; size_t message_size; @@ -21,40 +22,50 @@ libspdm_return_t libspdm_send_request(void *context, const uint32_t *session_id, uint8_t *sender_buffer; size_t sender_buffer_size; - spdm_context = context; + context = spdm_context; - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_send_spdm_request[%x] (0x%x): \n", - (session_id != NULL) ? *session_id : 0x0, request_size)); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_send_spdm_request[%x] msg %s(0x%x), size (0x%x): \n", + (session_id != NULL) ? *session_id : 0x0, + libspdm_get_code_str(((spdm_message_header_t *)request)-> + request_response_code), + ((spdm_message_header_t *)request)->request_response_code, + request_size)); LIBSPDM_INTERNAL_DUMP_HEX(request, request_size); - transport_header_size = spdm_context->transport_get_header_size(spdm_context); - libspdm_get_scratch_buffer(spdm_context, (void**) &scratch_buffer, &scratch_buffer_size); - libspdm_get_sender_buffer(spdm_context, (void**) &sender_buffer, &sender_buffer_size); + transport_header_size = context->local_context.capability.transport_header_size; + libspdm_get_scratch_buffer(context, (void**) &scratch_buffer, &scratch_buffer_size); + libspdm_get_sender_buffer(context, (void**) &sender_buffer, &sender_buffer_size); /* This is a problem because original code assumes request is in the sender buffer, * when it can really be using the scratch space for chunking. * Did not want to modify ally request handlers to pass this information, * so just making the determination here by examining scratch/sender buffers. * This may be something that should be refactored in the future. */ - #if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP if ((uint8_t*) request >= sender_buffer && (uint8_t*)request < sender_buffer + sender_buffer_size) { message = sender_buffer; message_size = sender_buffer_size; - } - else { - if ((uint8_t*)request >= scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET - && (uint8_t*)request < scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET - + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY) { - message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; - message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + } else { + if ((uint8_t*)request >= + scratch_buffer + libspdm_get_scratch_buffer_sender_receiver_offset(spdm_context) + && (uint8_t*)request < + scratch_buffer + libspdm_get_scratch_buffer_sender_receiver_offset(spdm_context) + + libspdm_get_scratch_buffer_sender_receiver_capacity(spdm_context)) { + message = scratch_buffer + + libspdm_get_scratch_buffer_sender_receiver_offset(spdm_context); + message_size = libspdm_get_scratch_buffer_sender_receiver_capacity(spdm_context); } else if ((uint8_t*)request >= - scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET + scratch_buffer + + libspdm_get_scratch_buffer_large_sender_receiver_offset(spdm_context) && (uint8_t*)request < - scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET - + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY) { - message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_OFFSET; - message_size = LIBSPDM_SCRATCH_BUFFER_LARGE_SENDER_RECEIVER_CAPACITY; + scratch_buffer + + libspdm_get_scratch_buffer_large_sender_receiver_offset(spdm_context) + + libspdm_get_scratch_buffer_large_sender_receiver_capacity(spdm_context)) { + message = scratch_buffer + + libspdm_get_scratch_buffer_large_sender_receiver_offset(spdm_context); + message_size = libspdm_get_scratch_buffer_large_sender_receiver_capacity(spdm_context); } } #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ @@ -76,27 +87,32 @@ libspdm_return_t libspdm_send_request(void *context, const uint32_t *session_id, if (((const spdm_message_header_t *)request)->request_response_code != SPDM_RESPOND_IF_READY && ((const spdm_message_header_t *)request)->request_response_code != SPDM_CHUNK_GET && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_SEND) { - libspdm_copy_mem (spdm_context->last_spdm_request, - sizeof(spdm_context->last_spdm_request), + libspdm_copy_mem (context->last_spdm_request, + libspdm_get_scratch_buffer_last_spdm_request_capacity(context), request, request_size ); - spdm_context->last_spdm_request_size = request_size; + context->last_spdm_request_size = request_size; } - status = spdm_context->transport_encode_message( - spdm_context, session_id, is_app_message, true, request_size, + status = context->transport_encode_message( + context, session_id, is_app_message, true, request_size, request, &message_size, (void **)&message); if (LIBSPDM_STATUS_IS_ERROR(status)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "transport_encode_message status - %p\n", status)); + if ((session_id != NULL) && + ((status == LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW) || + (status == LIBSPDM_STATUS_CRYPTO_ERROR))) { + libspdm_free_session_id(context, *session_id); + } return status; } - timeout = spdm_context->local_context.capability.rtt; + timeout = context->local_context.capability.rtt; - status = spdm_context->send_message(spdm_context, message_size, message, - timeout); + status = context->send_message(context, message_size, message, + timeout); if (LIBSPDM_STATUS_IS_ERROR(status)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_send_spdm_request[%x] status - %p\n", (session_id != NULL) ? *session_id : 0x0, status)); @@ -105,12 +121,12 @@ libspdm_return_t libspdm_send_request(void *context, const uint32_t *session_id, return status; } -libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session_id, +libspdm_return_t libspdm_receive_response(void *spdm_context, const uint32_t *session_id, bool is_app_message, size_t *response_size, void **response) { - libspdm_context_t *spdm_context; + libspdm_context_t *context; void *temp_session_context; libspdm_return_t status; uint8_t *message; @@ -126,20 +142,20 @@ libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session bool reset_key_update; bool result; - spdm_context = context; + context = spdm_context; - if (spdm_context->crypto_request) { - timeout = spdm_context->local_context.capability.rtt + - ((uint64_t)2 << spdm_context->connection_info.capability.ct_exponent); + if (context->crypto_request) { + timeout = context->local_context.capability.rtt + + ((uint64_t)1 << context->connection_info.capability.ct_exponent); } else { - timeout = spdm_context->local_context.capability.rtt + - spdm_context->local_context.capability.st1; + timeout = context->local_context.capability.rtt + + context->local_context.capability.st1; } message = *response; message_size = *response_size; - status = spdm_context->receive_message(spdm_context, &message_size, - (void **)&message, timeout); + status = context->receive_message(context, &message_size, + (void **)&message, timeout); if (LIBSPDM_STATUS_IS_ERROR(status)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_receive_spdm_response[%x] status - %p\n", @@ -153,12 +169,13 @@ libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session /* always use scratch buffer to response. * if it is secured message, this scratch buffer will be used. * if it is normal message, the response ptr will point to receiver buffer. */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); - libspdm_get_scratch_buffer (spdm_context, (void **)&scratch_buffer, &scratch_buffer_size); - #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP - *response = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_OFFSET + + transport_header_size = context->local_context.capability.transport_header_size; + libspdm_get_scratch_buffer (context, (void **)&scratch_buffer, &scratch_buffer_size); + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP + *response = scratch_buffer + libspdm_get_scratch_buffer_secure_message_offset(context) + transport_header_size; - *response_size = LIBSPDM_SCRATCH_BUFFER_SECURE_MESSAGE_CAPACITY - transport_header_size; + *response_size = libspdm_get_scratch_buffer_secure_message_capacity(context) - + transport_header_size; #else *response = scratch_buffer + transport_header_size; *response_size = scratch_buffer_size - transport_header_size; @@ -167,8 +184,8 @@ libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session backup_response = *response; backup_response_size = *response_size; - status = spdm_context->transport_decode_message( - spdm_context, &message_session_id, &is_message_app_message, + status = context->transport_decode_message( + context, &message_session_id, &is_message_app_message, false, message_size, message, response_size, response); reset_key_update = false; @@ -181,7 +198,7 @@ libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } temp_session_context = libspdm_get_secured_message_context_via_session_id( - spdm_context, *message_session_id); + context, *message_session_id); if (temp_session_context == NULL) { return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } @@ -198,8 +215,8 @@ libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session is_message_app_message = false; *response = backup_response; *response_size = backup_response_size; - status = spdm_context->transport_decode_message( - spdm_context, &message_session_id, &is_message_app_message, + status = context->transport_decode_message( + context, &message_session_id, &is_message_app_message, false, message_size, message, response_size, response); reset_key_update = true; @@ -237,13 +254,22 @@ libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session goto error; } - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_receive_spdm_response[%x] (0x%x): \n", - (session_id != NULL) ? *session_id : 0x0, *response_size)); if (LIBSPDM_STATUS_IS_ERROR(status)) { + if ((session_id != NULL) && + (context->last_spdm_error.error_code == SPDM_ERROR_CODE_DECRYPT_ERROR)) { + libspdm_free_session_id(context, *session_id); + } LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "libspdm_receive_spdm_response[%x] status - %p\n", (session_id != NULL) ? *session_id : 0x0, status)); } else { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, + "libspdm_receive_spdm_response[%x] msg %s(0x%x), size (0x%x): \n", + (session_id != NULL) ? *session_id : 0x0, + libspdm_get_code_str(((spdm_message_header_t *)*response)-> + request_response_code), + ((spdm_message_header_t *)*response)->request_response_code, + *response_size)); LIBSPDM_INTERNAL_DUMP_HEX(*response, *response_size); } @@ -252,8 +278,7 @@ libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session * to activate backup key to parse the error. Then later the Responder will return SUCCESS, * the Requester needs new key. So we need to restore the environment by * libspdm_create_update_session_data_key() again.*/ - if (reset_key_update) - { + if (reset_key_update) { /* temp_session_context and message_session_id must necessarily * be valid for us to reach here. */ if (temp_session_context == NULL || message_session_id == NULL) { @@ -269,14 +294,14 @@ libspdm_return_t libspdm_receive_response(void *context, const uint32_t *session return status; error: - if (spdm_context->last_spdm_error.error_code == SPDM_ERROR_CODE_DECRYPT_ERROR) { + if (context->last_spdm_error.error_code == SPDM_ERROR_CODE_DECRYPT_ERROR) { return LIBSPDM_STATUS_SESSION_MSG_ERROR; } else { return LIBSPDM_STATUS_RECEIVE_FAIL; } } -#if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) +#if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP libspdm_return_t libspdm_handle_large_request( libspdm_context_t *spdm_context, const uint32_t *session_id, @@ -299,6 +324,12 @@ libspdm_return_t libspdm_handle_large_request( uint8_t *chunk_ptr; size_t copy_size; libspdm_chunk_info_t *send_info; + uint32_t min_data_transfer_size; + spdm_error_response_t *spdm_error; + + if (libspdm_get_connection_version(spdm_context) < SPDM_MESSAGE_VERSION_12) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } /* Fail if requester or responder does not support chunk cap */ if (!libspdm_is_capabilities_flag_supported( @@ -309,22 +340,23 @@ libspdm_return_t libspdm_handle_large_request( } /* now we can get sender buffer */ - transport_header_size = spdm_context->transport_get_header_size(spdm_context); + transport_header_size = spdm_context->local_context.capability.transport_header_size; libspdm_get_scratch_buffer(spdm_context, (void**) &scratch_buffer, &scratch_buffer_size); - LIBSPDM_ASSERT(scratch_buffer_size >= LIBSPDM_SCRATCH_BUFFER_SIZE); /* Temporary send/receive buffers for chunking are in the scratch space */ - message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_OFFSET; - message_size = LIBSPDM_SCRATCH_BUFFER_SENDER_RECEIVER_CAPACITY; + message = scratch_buffer + libspdm_get_scratch_buffer_sender_receiver_offset(spdm_context); + message_size = libspdm_get_scratch_buffer_sender_receiver_capacity(spdm_context); send_info = &spdm_context->chunk_context.send; send_info->chunk_in_use = true; /* The first section of the scratch * buffer may be used for other purposes. Use only after that section. */ - send_info->large_message = scratch_buffer + LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_OFFSET; - send_info->large_message_capacity = LIBSPDM_SCRATCH_BUFFER_LARGE_MESSAGE_CAPACITY; + send_info->large_message = scratch_buffer + + libspdm_get_scratch_buffer_large_message_offset(spdm_context); + send_info->large_message_capacity = + libspdm_get_scratch_buffer_large_message_capacity(spdm_context); libspdm_zero_mem(send_info->large_message, send_info->large_message_capacity); libspdm_copy_mem(send_info->large_message, send_info->large_message_capacity, @@ -336,6 +368,10 @@ libspdm_return_t libspdm_handle_large_request( request = NULL; /* Invalidate to prevent accidental use. */ request_size = 0; + min_data_transfer_size = LIBSPDM_MIN( + spdm_context->connection_info.capability.data_transfer_size, + spdm_context->local_context.capability.sender_data_transfer_size); + do { LIBSPDM_ASSERT(send_info->large_message_capacity >= transport_header_size); spdm_request = (spdm_chunk_send_request_t*) ((uint8_t*) message + transport_header_size); @@ -349,14 +385,13 @@ libspdm_return_t libspdm_handle_large_request( spdm_request->reserved = 0; chunk_ptr = (uint8_t*) (spdm_request + 1); - if (spdm_context->connection_info.capability.data_transfer_size + if (min_data_transfer_size - sizeof(spdm_chunk_send_request_t) < (send_info->large_message_size - send_info->chunk_bytes_transferred)) { - copy_size = spdm_context->connection_info.capability.data_transfer_size + copy_size = min_data_transfer_size - sizeof(spdm_chunk_send_request_t); - } - else { + } else { copy_size = (send_info->large_message_size - send_info->chunk_bytes_transferred); } @@ -428,8 +463,7 @@ libspdm_return_t libspdm_handle_large_request( spdm_response, response_size); send_info->large_message_size = response_size; break; - } - else { + } else { status = LIBSPDM_STATUS_INVALID_MSG_SIZE; break; } @@ -446,6 +480,23 @@ libspdm_return_t libspdm_handle_large_request( if (spdm_response->header.param1 & SPDM_CHUNK_SEND_ACK_RESPONSE_ATTRIBUTE_EARLY_ERROR_DETECTED) { + spdm_error = (spdm_error_response_t *) (spdm_response + 1); + if (response_size < (sizeof(spdm_chunk_send_ack_response_t) + + sizeof(spdm_error_response_t))) { + status = LIBSPDM_STATUS_INVALID_MSG_SIZE; + break; + } + if ((spdm_error->header.spdm_version != + libspdm_get_connection_version(spdm_context)) || + (spdm_error->header.request_response_code != SPDM_ERROR)) { + status = LIBSPDM_STATUS_INVALID_MSG_FIELD; + break; + } + if (spdm_error->header.param1 == SPDM_ERROR_CODE_LARGE_RESPONSE) { + status = LIBSPDM_STATUS_ERROR_PEER; + break; + } + /* Store the error response in scratch buffer to be read by * libspdm_receive_spdm_response and returned to its caller * and handled in the error response handling flow */ @@ -510,9 +561,16 @@ libspdm_return_t libspdm_send_spdm_request(libspdm_context_t *spdm_context, libspdm_session_info_t *session_info; libspdm_session_state_t session_state; libspdm_return_t status; - - if ((spdm_context->connection_info.capability.data_transfer_size != 0) && - (request_size > spdm_context->connection_info.capability.data_transfer_size) && + #if LIBSPDM_ENABLE_MSG_LOG + size_t msg_log_size; + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + + /* large SPDM message is the SPDM message whose size is greater than the DataTransferSize of the receiving + * SPDM endpoint or greater than the transmit buffer size of the sending SPDM endpoint */ + if (((spdm_context->connection_info.capability.data_transfer_size != 0 && + request_size > spdm_context->connection_info.capability.data_transfer_size) || + (spdm_context->local_context.capability.sender_data_transfer_size != 0 && + request_size > spdm_context->local_context.capability.sender_data_transfer_size)) && !libspdm_is_capabilities_flag_supported( spdm_context, true, SPDM_GET_CAPABILITIES_REQUEST_FLAGS_CHUNK_CAP, @@ -539,12 +597,29 @@ libspdm_return_t libspdm_send_spdm_request(libspdm_context_t *spdm_context, } } + if ((spdm_context->connection_info.capability.max_spdm_msg_size != 0) && + (request_size > spdm_context->connection_info.capability.max_spdm_msg_size)) { + LIBSPDM_DEBUG((LIBSPDM_DEBUG_ERROR, "request_size > rsp max_spdm_msg_size\n")); + return LIBSPDM_STATUS_PEER_BUFFER_TOO_SMALL; + } + LIBSPDM_ASSERT (request_size <= spdm_context->local_context.capability.max_spdm_msg_size); + + #if LIBSPDM_ENABLE_MSG_LOG + /* First save the size of the message log buffer. If there is an error it will be reverted. */ + msg_log_size = libspdm_get_msg_log_size(spdm_context); + libspdm_append_msg_log(spdm_context, request, request_size); + #endif /* LIBSPDM_ENABLE_MSG_LOG */ + + /* large SPDM message is the SPDM message whose size is greater than the DataTransferSize of the receiving + * SPDM endpoint or greater than the transmit buffer size of the sending SPDM endpoint */ if (((const spdm_message_header_t*) request)->request_response_code != SPDM_GET_VERSION && ((const spdm_message_header_t*) request)->request_response_code != SPDM_GET_CAPABILITIES - && spdm_context->connection_info.capability.data_transfer_size != 0 - && request_size > spdm_context->connection_info.capability.data_transfer_size) { + && ((spdm_context->connection_info.capability.data_transfer_size != 0 && + request_size > spdm_context->connection_info.capability.data_transfer_size) || + (spdm_context->local_context.capability.sender_data_transfer_size != 0 && + request_size > spdm_context->local_context.capability.sender_data_transfer_size))) { - #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP || LIBSPDM_ENABLE_CHUNK_CAP + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP /* libspdm_send_request is not called with the original request in this flow. * This leads to the last_spdm_request field not having the original request value. * The caller assumes the request has been copied to last_spdm_request, @@ -555,7 +630,8 @@ libspdm_return_t libspdm_send_spdm_request(libspdm_context_t *spdm_context, && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_GET && ((const spdm_message_header_t*) request)->request_response_code != SPDM_CHUNK_SEND) { libspdm_copy_mem( - spdm_context->last_spdm_request, sizeof(spdm_context->last_spdm_request), + spdm_context->last_spdm_request, + libspdm_get_scratch_buffer_last_spdm_request_capacity(spdm_context), request, request_size); spdm_context->last_spdm_request_size = request_size; } @@ -565,17 +641,16 @@ libspdm_return_t libspdm_send_spdm_request(libspdm_context_t *spdm_context, #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP*/ status = LIBSPDM_STATUS_BUFFER_TOO_SMALL; #endif /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP*/ - } - else - { + } else { status = libspdm_send_request(spdm_context, session_id, false, request_size, request); } #if LIBSPDM_ENABLE_MSG_LOG - if (status == LIBSPDM_STATUS_SUCCESS) { - libspdm_append_msg_log(spdm_context, request, request_size); + /* If there is an error in sending the request then revert the request in the message log. */ + if (LIBSPDM_STATUS_IS_ERROR(status)) { + spdm_context->msg_log.buffer_size = msg_log_size; } - #endif + #endif /* LIBSPDM_ENABLE_MSG_LOG */ return status; } @@ -589,7 +664,7 @@ libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, libspdm_session_info_t *session_info; libspdm_session_state_t session_state; - #if (LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) || (LIBSPDM_ENABLE_CHUNK_CAP) + #if LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP spdm_message_header_t *spdm_response; size_t response_capacity; libspdm_chunk_info_t *send_info; @@ -614,7 +689,7 @@ libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, } } - #if !(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) && !(LIBSPDM_ENABLE_CHUNK_CAP) + #if !(LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP) status = libspdm_receive_response(spdm_context, session_id, false, response_size, response); #else /* LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP */ send_info = &spdm_context->chunk_context.send; @@ -635,8 +710,7 @@ libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, send_info->large_message_size = 0; send_info->large_message_capacity = 0; status = LIBSPDM_STATUS_SUCCESS; - } - else { + } else { response_capacity = *response_size; status = libspdm_receive_response(spdm_context, session_id, false, response_size, response); @@ -654,7 +728,6 @@ libspdm_return_t libspdm_receive_spdm_response(libspdm_context_t *spdm_context, if (spdm_response->request_response_code == SPDM_ERROR && spdm_response->param1 == SPDM_ERROR_CODE_LARGE_RESPONSE) { - status = libspdm_handle_error_large_response( spdm_context, session_id, response_size, (void*) spdm_response, response_capacity); diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c similarity index 94% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c index 90c412ece7..da24fd383e 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c @@ -13,11 +13,7 @@ **/ size_t libspdm_secured_message_get_context_size(void) { - size_t size; - - size = sizeof(libspdm_secured_message_context_t); - LIBSPDM_ASSERT (size == LIBSPDM_SECURED_MESSAGE_CONTEXT_SIZE); - return size; + return sizeof(libspdm_secured_message_context_t); } /** @@ -164,6 +160,32 @@ void libspdm_secured_message_set_psk_hint(void *spdm_secured_message_context, } } +/** + * Set the maximum sequence_number to an SPDM secured message context. + * + * @param spdm_secured_message_context A pointer to the SPDM secured message context. + * @param max_spdm_session_sequence_number Indicate the maximum sequence_number in SPDM session. + */ +void libspdm_secured_message_set_max_spdm_session_sequence_number( + void *spdm_secured_message_context, + uint64_t max_spdm_session_sequence_number) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->max_spdm_session_sequence_number = max_spdm_session_sequence_number; +} + +void libspdm_secured_message_set_sequence_number_endian ( + void *spdm_secured_message_context, + uint8_t endian_value) +{ + libspdm_secured_message_context_t *secured_message_context; + + secured_message_context = spdm_secured_message_context; + secured_message_context->sequence_number_endian = endian_value; +} + /** * Import the DHE Secret to an SPDM secured message context. * diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c similarity index 59% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c index 0b15bba414..9f6acb1774 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c @@ -6,20 +6,75 @@ #include "internal/libspdm_secured_message_lib.h" +static void generate_iv(uint64_t sequence_number, uint8_t *iv, const uint8_t *salt, + size_t aead_iv_size, uint8_t endian) +{ + uint8_t iv_temp[LIBSPDM_MAX_AEAD_IV_SIZE]; + size_t index; + + /* Form the AEAD IV from the salt and the sequence number. */ + libspdm_copy_mem(iv, LIBSPDM_MAX_AEAD_IV_SIZE, salt, aead_iv_size); + + switch (endian) { + case LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_LITTLE: + case LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_BOTH: + /* If little-endian then the sequence number is zero-extended to the higher indices. + * The sequence number begins at the lowest index (0). */ + libspdm_copy_mem(iv_temp, sizeof(iv_temp), &sequence_number, sizeof(sequence_number)); + for (index = 0; index < sizeof(sequence_number); index++) { + iv[index] = iv[index] ^ iv_temp[index]; + } + break; + case LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BIG: + case LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BOTH: + /* If big-endian then the sequence number is zero-extended to the lower indices. + * The sequence number ends at the highest index (aead_size - 1). */ + sequence_number = libspdm_le_to_be_64(sequence_number); + libspdm_copy_mem(iv_temp + (aead_iv_size - sizeof(sequence_number)), + aead_iv_size, + &sequence_number, + sizeof(sequence_number)); + for (index = aead_iv_size - sizeof(sequence_number); index < aead_iv_size; index++) { + iv[index] = iv[index] ^ iv_temp[index]; + } + break; + } +} + +static uint8_t swap_endian(uint8_t endian) +{ + switch (endian) { + case LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_BOTH: + return LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BIG; + case LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BOTH: + return LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_LITTLE; + default: + LIBSPDM_ASSERT(0); + return 0; + } +} + +static bool is_sequence_number_endian_determined(uint8_t endian) +{ + return ((endian == LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BIG) || + (endian == LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_LITTLE)) ? true : false; +} + /** * Encode an application message to a secured message. * * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param session_id The session ID of the SPDM session. - * @param is_requester Indicates if it is a requester message. - * @param app_message_size size in bytes of the application message data buffer. - * @param app_message A pointer to a source buffer to store the application message. - * It shall point to the scratch buffer in spdm_context. + * @param session_id The session ID of the SPDM session. + * @param is_request_message Indicates if it is a request message. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a source buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer. * Before app_message, there is room for spdm_secured_message_cipher_header_t. * After (app_message + app_message_size), there is room for random bytes. - * @param secured_message_size size in bytes of the secured message data buffer. - * @param secured_message A pointer to a destination buffer to store the secured message. - * It shall point to the acquired sender buffer. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a destination buffer to store the secured message. + * It shall point to the acquired sender buffer. * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. * * @retval RETURN_SUCCESS The application message is encoded successfully. @@ -27,7 +82,7 @@ **/ libspdm_return_t libspdm_encode_secured_message( void *spdm_secured_message_context, uint32_t session_id, - bool is_requester, size_t app_message_size, + bool is_request_message, size_t app_message_size, void *app_message, size_t *secured_message_size, void *secured_message, const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks) @@ -36,7 +91,6 @@ libspdm_return_t libspdm_encode_secured_message( size_t total_secured_message_size; size_t plain_text_size; size_t cipher_text_size; - size_t aead_pad_size; size_t aead_tag_size; size_t aead_key_size; size_t aead_iv_size; @@ -49,8 +103,9 @@ libspdm_return_t libspdm_encode_secured_message( size_t record_header_size; spdm_secured_message_cipher_header_t *enc_msg_header; bool result; - uint8_t key[LIBSPDM_MAX_AEAD_KEY_SIZE]; - uint8_t salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + const uint8_t *key; + uint8_t *salt; + uint8_t iv[LIBSPDM_MAX_AEAD_IV_SIZE]; uint64_t sequence_number; uint64_t sequence_num_in_header; uint8_t sequence_num_in_header_size; @@ -58,8 +113,16 @@ libspdm_return_t libspdm_encode_secured_message( uint32_t rand_count; uint32_t max_rand_count; libspdm_session_state_t session_state; + spdm_version_number_t secured_spdm_version; + uint8_t version; secured_message_context = spdm_secured_message_context; + secured_spdm_version = spdm_secured_message_callbacks->get_secured_spdm_version( + secured_message_context->secured_message_version); + version = (uint8_t)(secured_spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT); + if (version > SECURED_SPDM_VERSION_11) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } session_type = secured_message_context->session_type; LIBSPDM_ASSERT((session_type == LIBSPDM_SESSION_TYPE_MAC_ONLY) || @@ -74,47 +137,35 @@ libspdm_return_t libspdm_encode_secured_message( switch (session_state) { case LIBSPDM_SESSION_STATE_HANDSHAKING: - if (is_requester) { - libspdm_copy_mem(key, sizeof(key), - secured_message_context->handshake_secret - .request_handshake_encryption_key, - secured_message_context->aead_key_size); - libspdm_copy_mem(salt, sizeof(salt), - secured_message_context->handshake_secret.request_handshake_salt, - secured_message_context->aead_iv_size); + if (is_request_message) { + key = (const uint8_t *)secured_message_context->handshake_secret. + request_handshake_encryption_key; + salt = (uint8_t *)secured_message_context->handshake_secret. + request_handshake_salt; sequence_number = secured_message_context->handshake_secret .request_handshake_sequence_number; } else { - libspdm_copy_mem(key, sizeof(key), - secured_message_context->handshake_secret - .response_handshake_encryption_key, - secured_message_context->aead_key_size); - libspdm_copy_mem(salt, sizeof(salt), - secured_message_context->handshake_secret.response_handshake_salt, - secured_message_context->aead_iv_size); + key = (const uint8_t *)secured_message_context->handshake_secret. + response_handshake_encryption_key; + salt = (uint8_t *)secured_message_context->handshake_secret. + response_handshake_salt; sequence_number = secured_message_context->handshake_secret .response_handshake_sequence_number; } break; case LIBSPDM_SESSION_STATE_ESTABLISHED: - if (is_requester) { - libspdm_copy_mem(key, sizeof(key), - secured_message_context->application_secret - .request_data_encryption_key, - secured_message_context->aead_key_size); - libspdm_copy_mem(salt, sizeof(salt), - secured_message_context->application_secret.request_data_salt, - secured_message_context->aead_iv_size); + if (is_request_message) { + key = (const uint8_t *)secured_message_context->application_secret. + request_data_encryption_key; + salt = (uint8_t *)secured_message_context->application_secret. + request_data_salt; sequence_number = secured_message_context->application_secret .request_data_sequence_number; } else { - libspdm_copy_mem(key, sizeof(key), - secured_message_context->application_secret - .response_data_encryption_key, - secured_message_context->aead_key_size); - libspdm_copy_mem(salt, sizeof(salt), - secured_message_context->application_secret.response_data_salt, - secured_message_context->aead_iv_size); + key = (const uint8_t *)secured_message_context->application_secret. + response_data_encryption_key; + salt = (uint8_t *)secured_message_context->application_secret. + response_data_salt; sequence_number = secured_message_context->application_secret .response_data_sequence_number; } @@ -125,34 +176,29 @@ libspdm_return_t libspdm_encode_secured_message( break; } - if (sequence_number == (uint64_t)-1) { + if (sequence_number >= secured_message_context->max_spdm_session_sequence_number) { return LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW; } - *(uint64_t *)salt = *(uint64_t *)salt ^ sequence_number; + generate_iv(sequence_number, iv, salt, aead_iv_size, + secured_message_context->sequence_number_endian); sequence_num_in_header = 0; sequence_num_in_header_size = spdm_secured_message_callbacks->get_sequence_number( sequence_number, (uint8_t *)&sequence_num_in_header); LIBSPDM_ASSERT(sequence_num_in_header_size <= sizeof(sequence_num_in_header)); - sequence_number++; if (session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) { - if (is_requester) { - secured_message_context->handshake_secret.request_handshake_sequence_number = - sequence_number; + if (is_request_message) { + secured_message_context->handshake_secret.request_handshake_sequence_number++; } else { - secured_message_context->handshake_secret.response_handshake_sequence_number = - sequence_number; + secured_message_context->handshake_secret.response_handshake_sequence_number++; } - } - else { - if (is_requester) { - secured_message_context->application_secret.request_data_sequence_number = - sequence_number; + } else { + if (is_request_message) { + secured_message_context->application_secret.request_data_sequence_number++; } else { - secured_message_context->application_secret.response_data_sequence_number = - sequence_number; + secured_message_context->application_secret.response_data_sequence_number++; } } @@ -177,7 +223,6 @@ libspdm_return_t libspdm_encode_secured_message( plain_text_size = sizeof(spdm_secured_message_cipher_header_t) + app_message_size + rand_count; cipher_text_size = plain_text_size; - aead_pad_size = cipher_text_size - plain_text_size; total_secured_message_size = record_header_size + cipher_text_size + aead_tag_size; LIBSPDM_ASSERT(*secured_message_size >= total_secured_message_size); @@ -208,7 +253,6 @@ libspdm_return_t libspdm_encode_secured_message( if (!result) { return LIBSPDM_STATUS_LOW_ENTROPY; } - libspdm_zero_mem((uint8_t *)enc_msg_header + plain_text_size, aead_pad_size); a_data = (uint8_t *)record_header1; enc_msg = (uint8_t *)(record_header2 + 1); @@ -219,7 +263,7 @@ libspdm_return_t libspdm_encode_secured_message( result = libspdm_aead_encryption( secured_message_context->secured_message_version, secured_message_context->aead_cipher_suite, key, - aead_key_size, salt, aead_iv_size, (uint8_t *)a_data, + aead_key_size, iv, aead_iv_size, (uint8_t *)a_data, record_header_size, dec_msg, cipher_text_size, tag, aead_tag_size, enc_msg, &cipher_text_size); break; @@ -257,7 +301,7 @@ libspdm_return_t libspdm_encode_secured_message( result = libspdm_aead_encryption( secured_message_context->secured_message_version, secured_message_context->aead_cipher_suite, key, - aead_key_size, salt, aead_iv_size, (uint8_t *)a_data, + aead_key_size, iv, aead_iv_size, (uint8_t *)a_data, record_header_size + app_message_size, NULL, 0, tag, aead_tag_size, NULL, NULL); break; @@ -276,16 +320,16 @@ libspdm_return_t libspdm_encode_secured_message( * Decode an application message from a secured message. * * @param spdm_secured_message_context A pointer to the SPDM secured message context. - * @param session_id The session ID of the SPDM session. - * @param is_requester Indicates if it is a requester message. - * @param secured_message_size size in bytes of the secured message data buffer. - * @param secured_message A pointer to a source buffer to store the secured message. - * It shall point to the acquired receiver buffer. - * @param app_message_size size in bytes of the application message data buffer. - * @param app_message A pointer to a destination buffer to store the application message. - * It shall point to the scratch buffer in spdm_context. - * On input, the app_message pointer shall point to a big enough buffer to hold the decrypted message - * On output, the app_message pointer shall be inside of [app_message, app_message + app_message_size] + * @param session_id The session ID of the SPDM session. + * @param is_request_message Indicates if it is a request message. + * @param secured_message_size size in bytes of the secured message data buffer. + * @param secured_message A pointer to a source buffer to store the secured message. + * It shall point to the acquired receiver buffer. + * @param app_message_size size in bytes of the application message data buffer. + * @param app_message A pointer to a destination buffer to store the application message. + * It shall point to the scratch buffer in spdm_context. + * On input, the app_message pointer shall point to a big enough buffer to hold the decrypted message + * On output, the app_message pointer shall be inside of [app_message, app_message + app_message_size] * @param spdm_secured_message_callbacks A pointer to a secured message callback functions structure. * * @retval RETURN_SUCCESS The application message is decoded successfully. @@ -294,7 +338,7 @@ libspdm_return_t libspdm_encode_secured_message( **/ libspdm_return_t libspdm_decode_secured_message( void *spdm_secured_message_context, uint32_t session_id, - bool is_requester, size_t secured_message_size, + bool is_request_message, size_t secured_message_size, void *secured_message, size_t *app_message_size, void **app_message, const libspdm_secured_message_callbacks_t *spdm_secured_message_callbacks) @@ -314,14 +358,17 @@ libspdm_return_t libspdm_decode_secured_message( size_t record_header_size; spdm_secured_message_cipher_header_t *enc_msg_header; bool result; - uint8_t key[LIBSPDM_MAX_AEAD_KEY_SIZE]; - uint8_t salt[LIBSPDM_MAX_AEAD_IV_SIZE]; + const uint8_t *key; + uint8_t *salt; + uint8_t iv[LIBSPDM_MAX_AEAD_IV_SIZE]; uint64_t sequence_number; uint64_t sequence_num_in_header; uint8_t sequence_num_in_header_size; libspdm_session_type_t session_type; libspdm_session_state_t session_state; libspdm_error_struct_t spdm_error; + spdm_version_number_t secured_spdm_version; + uint8_t version; spdm_error.error_code = 0; spdm_error.session_id = 0; @@ -331,6 +378,12 @@ libspdm_return_t libspdm_decode_secured_message( spdm_error.session_id = session_id; secured_message_context = spdm_secured_message_context; + secured_spdm_version = spdm_secured_message_callbacks->get_secured_spdm_version( + secured_message_context->secured_message_version); + version = (uint8_t)(secured_spdm_version >> SPDM_VERSION_NUMBER_SHIFT_BIT); + if (version > SECURED_SPDM_VERSION_11) { + return LIBSPDM_STATUS_UNSUPPORTED_CAP; + } session_type = secured_message_context->session_type; LIBSPDM_ASSERT((session_type == LIBSPDM_SESSION_TYPE_MAC_ONLY) || @@ -345,51 +398,35 @@ libspdm_return_t libspdm_decode_secured_message( switch (session_state) { case LIBSPDM_SESSION_STATE_HANDSHAKING: - if (is_requester) { - libspdm_copy_mem(key, sizeof(key), - secured_message_context->handshake_secret - .request_handshake_encryption_key, - secured_message_context->aead_key_size); - libspdm_copy_mem(salt, sizeof(salt), - secured_message_context->handshake_secret - .request_handshake_salt, - secured_message_context->aead_iv_size); + if (is_request_message) { + key = (const uint8_t *)secured_message_context->handshake_secret. + request_handshake_encryption_key; + salt = (uint8_t *)secured_message_context->handshake_secret. + request_handshake_salt; sequence_number = secured_message_context->handshake_secret.request_handshake_sequence_number; } else { - libspdm_copy_mem(key, sizeof(key), - secured_message_context->handshake_secret - .response_handshake_encryption_key, - secured_message_context->aead_key_size); - libspdm_copy_mem(salt, sizeof(salt), - secured_message_context->handshake_secret - .response_handshake_salt, - secured_message_context->aead_iv_size); + key = (const uint8_t *)secured_message_context->handshake_secret. + response_handshake_encryption_key; + salt = (uint8_t *)secured_message_context->handshake_secret. + response_handshake_salt; sequence_number = secured_message_context->handshake_secret.response_handshake_sequence_number; } break; case LIBSPDM_SESSION_STATE_ESTABLISHED: - if (is_requester) { - libspdm_copy_mem(key, sizeof(key), - secured_message_context->application_secret - .request_data_encryption_key, - secured_message_context->aead_key_size); - libspdm_copy_mem(salt, sizeof(salt), - secured_message_context->application_secret - .request_data_salt, - secured_message_context->aead_iv_size); + if (is_request_message) { + key = (const uint8_t *)secured_message_context->application_secret. + request_data_encryption_key; + salt = (uint8_t *)secured_message_context->application_secret. + request_data_salt; sequence_number = secured_message_context->application_secret.request_data_sequence_number; } else { - libspdm_copy_mem(key, sizeof(key), - secured_message_context->application_secret - .response_data_encryption_key, - secured_message_context->aead_key_size); - libspdm_copy_mem(salt, sizeof(salt), - secured_message_context->application_secret - .response_data_salt, - secured_message_context->aead_iv_size); + key = (const uint8_t *)secured_message_context->application_secret. + response_data_encryption_key; + salt = (uint8_t *)secured_message_context->application_secret. + response_data_salt; sequence_number = secured_message_context->application_secret.response_data_sequence_number; } @@ -399,13 +436,14 @@ libspdm_return_t libspdm_decode_secured_message( return LIBSPDM_STATUS_INVALID_STATE_LOCAL; } - if (sequence_number == (uint64_t)-1) { + if (sequence_number >= secured_message_context->max_spdm_session_sequence_number) { libspdm_secured_message_set_last_spdm_error_struct( spdm_secured_message_context, &spdm_error); return LIBSPDM_STATUS_SEQUENCE_NUMBER_OVERFLOW; } - *(uint64_t *)salt = *(uint64_t *)salt ^ sequence_number; + generate_iv(sequence_number, iv, salt, aead_iv_size, + secured_message_context->sequence_number_endian); sequence_num_in_header = 0; sequence_num_in_header_size = @@ -413,23 +451,17 @@ libspdm_return_t libspdm_decode_secured_message( sequence_number, (uint8_t *)&sequence_num_in_header); LIBSPDM_ASSERT(sequence_num_in_header_size <= sizeof(sequence_num_in_header)); - sequence_number++; if (session_state == LIBSPDM_SESSION_STATE_HANDSHAKING) { - if (is_requester) { - secured_message_context->handshake_secret.request_handshake_sequence_number = - sequence_number; + if (is_request_message) { + secured_message_context->handshake_secret.request_handshake_sequence_number++; } else { - secured_message_context->handshake_secret.response_handshake_sequence_number = - sequence_number; + secured_message_context->handshake_secret.response_handshake_sequence_number++; } - } - else { - if (is_requester) { - secured_message_context->application_secret.request_data_sequence_number = - sequence_number; + } else { + if (is_request_message) { + secured_message_context->application_secret.request_data_sequence_number++; } else { - secured_message_context->application_secret.response_data_sequence_number = - sequence_number; + secured_message_context->application_secret.response_data_sequence_number++; } } @@ -454,8 +486,8 @@ libspdm_return_t libspdm_decode_secured_message( spdm_secured_message_context, &spdm_error); return LIBSPDM_STATUS_INVALID_MSG_FIELD; } - if (libspdm_const_compare_mem(record_header1 + 1, &sequence_num_in_header, - sequence_num_in_header_size) != 0) { + if (!libspdm_consttime_is_mem_equal(record_header1 + 1, &sequence_num_in_header, + sequence_num_in_header_size) != 0) { libspdm_secured_message_set_last_spdm_error_struct( spdm_secured_message_context, &spdm_error); return LIBSPDM_STATUS_INVALID_MSG_FIELD; @@ -481,16 +513,57 @@ libspdm_return_t libspdm_decode_secured_message( dec_msg = (uint8_t *)*app_message; enc_msg_header = (void *)dec_msg; tag = (const uint8_t *)record_header1 + record_header_size + cipher_text_size; + result = libspdm_aead_decryption( secured_message_context->secured_message_version, secured_message_context->aead_cipher_suite, key, - aead_key_size, salt, aead_iv_size, a_data, + aead_key_size, iv, aead_iv_size, a_data, record_header_size, enc_msg, cipher_text_size, tag, aead_tag_size, dec_msg, &cipher_text_size); + + /* When the sequence number is 0 then it has the same encoding in both + * big and little endian. The endianness can only be determined on the subsequent + * decryption. */ + if (!is_sequence_number_endian_determined( + secured_message_context->sequence_number_endian) && (sequence_number == 1)) { + + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Sequence number endianness is not determined.\n")); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "Attempting to determine endianness.\n")); + + if (result) { + /* Endianness is correct so set the endianness. */ + if (secured_message_context->sequence_number_endian == + LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_BOTH) { + secured_message_context->sequence_number_endian = + LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_LITTLE; + } else { + secured_message_context->sequence_number_endian = + LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BIG; + } + } else { + /* Endianness may be incorrect so try with the opposite endianness. */ + generate_iv(sequence_number, iv, salt, aead_iv_size, + swap_endian(secured_message_context->sequence_number_endian)); + + result = libspdm_aead_decryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, iv, aead_iv_size, a_data, + record_header_size, enc_msg, cipher_text_size, tag, + aead_tag_size, dec_msg, &cipher_text_size); + + if (result) { + /* Endianness is correct so set the endianness. */ + secured_message_context->sequence_number_endian = + swap_endian(secured_message_context->sequence_number_endian); + } + } + } + if (!result) { /* Backup keys are valid, fail and alert rollback and retry is possible. */ - if ((is_requester && secured_message_context->requester_backup_valid) || - ((!is_requester) && secured_message_context->responder_backup_valid)) { + if ((is_request_message && secured_message_context->requester_backup_valid) || + ((!is_request_message) && secured_message_context->responder_backup_valid)) { return LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE; } @@ -526,8 +599,8 @@ libspdm_return_t libspdm_decode_secured_message( spdm_secured_message_context, &spdm_error); return LIBSPDM_STATUS_INVALID_MSG_FIELD; } - if (libspdm_const_compare_mem(record_header1 + 1, &sequence_num_in_header, - sequence_num_in_header_size) != 0) { + if (!libspdm_consttime_is_mem_equal(record_header1 + 1, &sequence_num_in_header, + sequence_num_in_header_size)) { libspdm_secured_message_set_last_spdm_error_struct( spdm_secured_message_context, &spdm_error); return LIBSPDM_STATUS_INVALID_MSG_FIELD; @@ -546,17 +619,53 @@ libspdm_return_t libspdm_decode_secured_message( a_data = (uint8_t *)record_header1; tag = (uint8_t *)record_header1 + record_header_size + record_header2->length - aead_tag_size; + result = libspdm_aead_decryption( secured_message_context->secured_message_version, secured_message_context->aead_cipher_suite, key, - aead_key_size, salt, aead_iv_size, a_data, - record_header_size + record_header2->length - - aead_tag_size, + aead_key_size, iv, aead_iv_size, a_data, + record_header_size + record_header2->length - aead_tag_size, NULL, 0, tag, aead_tag_size, NULL, NULL); + + /* When the sequence number is 0 then it has the same encoding in both + * big and little endian. The endianness can only be determined on the subsequent + * decryption. */ + if (!is_sequence_number_endian_determined( + secured_message_context->sequence_number_endian) && (sequence_number == 1)) { + if (result) { + /* Endianness is correct so set the endianness. */ + if (secured_message_context->sequence_number_endian == + LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_BOTH) { + secured_message_context->sequence_number_endian = + LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_LITTLE_DEC_LITTLE; + } else { + secured_message_context->sequence_number_endian = + LIBSPDM_DATA_SESSION_SEQ_NUM_ENC_BIG_DEC_BIG; + } + } else { + /* Endianness may be incorrect so try with the opposite endianness. */ + generate_iv(sequence_number, iv, salt, aead_iv_size, + swap_endian(secured_message_context->sequence_number_endian)); + + result = libspdm_aead_decryption( + secured_message_context->secured_message_version, + secured_message_context->aead_cipher_suite, key, + aead_key_size, iv, aead_iv_size, a_data, + record_header_size + record_header2->length - aead_tag_size, + NULL, 0, tag, aead_tag_size, NULL, NULL); + + if (result) { + /* Endianness is correct so set the endianness. */ + secured_message_context->sequence_number_endian = + swap_endian(secured_message_context->sequence_number_endian); + } + } + } + if (!result) { /* Backup keys are valid, fail and alert rollback and retry is possible. */ - if ((is_requester && secured_message_context->requester_backup_valid) || - ((!is_requester) && secured_message_context->responder_backup_valid)) { + if ((is_request_message && secured_message_context->requester_backup_valid) || + ((!is_request_message) && secured_message_context->responder_backup_valid)) { return LIBSPDM_STATUS_SESSION_TRY_DISCARD_KEY_UPDATE; } diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_session.c similarity index 97% rename from src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c rename to src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_session.c index b4bf707d5e..97c50d20db 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_session.c @@ -178,8 +178,6 @@ bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, { bool status; size_t hash_size; - uint8_t bin_str0[128]; - size_t bin_str0_size; uint8_t bin_str1[128]; size_t bin_str1_size; uint8_t bin_str2[128]; @@ -191,15 +189,6 @@ bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, hash_size = secured_message_context->hash_size; - bin_str0_size = sizeof(bin_str0); - libspdm_bin_concat(secured_message_context->version, - SPDM_BIN_STR_0_LABEL, sizeof(SPDM_BIN_STR_0_LABEL) - 1, - NULL, (uint16_t)hash_size, hash_size, bin_str0, - &bin_str0_size); - - LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str0 (0x%x):\n", bin_str0_size)); - LIBSPDM_INTERNAL_DUMP_HEX(bin_str0, bin_str0_size); - if (!(secured_message_context->use_psk)) { LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "[DHE Secret]: ")); LIBSPDM_INTERNAL_DUMP_HEX_STR( @@ -232,7 +221,7 @@ bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str1 (0x%x):\n", bin_str1_size)); LIBSPDM_INTERNAL_DUMP_HEX(bin_str1, bin_str1_size); - #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + #if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP if (secured_message_context->use_psk) { status = libspdm_psk_handshake_secret_hkdf_expand( secured_message_context->version, @@ -247,7 +236,7 @@ bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, return false; } } - #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ if (!(secured_message_context->use_psk)) { status = libspdm_hkdf_expand( secured_message_context->base_hash_algo, @@ -275,7 +264,7 @@ bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str2 (0x%x):\n", bin_str2_size)); LIBSPDM_INTERNAL_DUMP_HEX(bin_str2, bin_str2_size); - #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + #if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP if (secured_message_context->use_psk) { status = libspdm_psk_handshake_secret_hkdf_expand( secured_message_context->version, @@ -290,7 +279,7 @@ bool libspdm_generate_session_handshake_key(void *spdm_secured_message_context, return false; } } - #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ if (!(secured_message_context->use_psk)) { status = libspdm_hkdf_expand( secured_message_context->base_hash_algo, @@ -366,7 +355,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, { bool status; size_t hash_size; - uint8_t salt1[64]; + uint8_t salt1[LIBSPDM_MAX_HASH_SIZE]; uint8_t bin_str0[128]; size_t bin_str0_size; uint8_t bin_str3[128]; @@ -390,6 +379,9 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, (uint16_t)hash_size, hash_size, bin_str0, &bin_str0_size); + LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str0 (0x%x):\n", bin_str0_size)); + LIBSPDM_INTERNAL_DUMP_HEX(bin_str0, bin_str0_size); + status = libspdm_hkdf_expand( secured_message_context->base_hash_algo, secured_message_context->master_secret.handshake_secret, @@ -407,7 +399,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, zero_filled_buffer, hash_size, salt1, hash_size, secured_message_context->master_secret.master_secret, hash_size); if (!status) { - return false; + goto cleanup; } LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "master_secret (0x%x) - ", hash_size)); LIBSPDM_INTERNAL_DUMP_DATA( @@ -425,7 +417,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str3 (0x%x):\n", bin_str3_size)); LIBSPDM_INTERNAL_DUMP_HEX(bin_str3, bin_str3_size); - #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + #if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP if (secured_message_context->use_psk) { status = libspdm_psk_master_secret_hkdf_expand( secured_message_context->version, @@ -437,10 +429,10 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, hash_size); if (!status) { - return false; + goto cleanup; } } - #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ if (!(secured_message_context->use_psk)) { status = libspdm_hkdf_expand( secured_message_context->base_hash_algo, @@ -450,7 +442,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, hash_size); if (!status) { - return false; + goto cleanup; } } @@ -468,7 +460,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str4 (0x%x):\n", bin_str4_size)); LIBSPDM_INTERNAL_DUMP_HEX(bin_str4, bin_str4_size); - #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + #if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP if (secured_message_context->use_psk) { status = libspdm_psk_master_secret_hkdf_expand( secured_message_context->version, @@ -480,10 +472,10 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, hash_size); if (!status) { - return false; + goto cleanup; } } - #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ if (!(secured_message_context->use_psk)) { status = libspdm_hkdf_expand( secured_message_context->base_hash_algo, @@ -493,7 +485,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, hash_size); if (!status) { - return false; + goto cleanup; } } @@ -512,7 +504,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, LIBSPDM_DEBUG((LIBSPDM_DEBUG_INFO, "bin_str8 (0x%x):\n", bin_str8_size)); LIBSPDM_INTERNAL_DUMP_HEX(bin_str8, bin_str8_size); - #if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP + #if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP if (secured_message_context->use_psk) { status = libspdm_psk_master_secret_hkdf_expand( secured_message_context->version, @@ -524,10 +516,10 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, hash_size); if (!status) { - return false; + goto cleanup; } } - #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ + #endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ if (!(secured_message_context->use_psk)) { status = libspdm_hkdf_expand( secured_message_context->base_hash_algo, @@ -537,7 +529,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, hash_size); if (!status) { - return false; + goto cleanup; } } @@ -552,7 +544,7 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, secured_message_context->application_secret.request_data_encryption_key, secured_message_context->application_secret.request_data_salt); if (!status) { - return status; + goto cleanup; } secured_message_context->application_secret.request_data_sequence_number = 0; @@ -562,11 +554,14 @@ bool libspdm_generate_session_data_key(void *spdm_secured_message_context, secured_message_context->application_secret.response_data_encryption_key, secured_message_context->application_secret.response_data_salt); if (!status) { - return status; + goto cleanup; } secured_message_context->application_secret.response_data_sequence_number = 0; - return true; +cleanup: + /*zero salt1 for security*/ + libspdm_zero_mem(salt1, hash_size); + return status; } /** diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/include/library/malloclib.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/malloclib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/os_stub/include/library/malloclib.h diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/include/library/rnglib.h similarity index 100% rename from src/nvidia/src/libraries/libspdm/2.3.1/os_stub/include/library/rnglib.h rename to src/nvidia/src/libraries/libspdm/3.1.1/os_stub/include/library/rnglib.h diff --git a/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/memlib/compare_mem.c b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/memlib/compare_mem.c new file mode 100644 index 0000000000..b670784f35 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/memlib/compare_mem.c @@ -0,0 +1,24 @@ +/** + * Copyright Notice: + * Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + **/ + +#include "base.h" + +bool libspdm_consttime_is_mem_equal(const void *destination_buffer, + const void *source_buffer, size_t length) +{ + const volatile uint8_t *pointer_dst; + const volatile uint8_t *pointer_src; + uint8_t delta; + + pointer_dst = (const uint8_t *)destination_buffer; + pointer_src = (const uint8_t *)source_buffer; + delta = 0; + while ((length-- != 0)) { + delta |= *(pointer_dst++) ^ *(pointer_src++); + } + + return ((delta == 0) ? true : false); +} diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/platform_lib_null/time_linux.c similarity index 81% rename from src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c rename to src/nvidia/src/libraries/libspdm/3.1.1/os_stub/platform_lib_null/time_linux.c index f14676386a..bce3c9f6f3 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/platform_lib_null/time_linux.c @@ -9,9 +9,9 @@ /** * Suspends the execution of the current thread until the time-out interval elapses. * - * @param microseconds The time interval for which execution is to be suspended, in milliseconds. + * @param microseconds The time interval for which execution is to be suspended, in microseconds. * **/ -void libspdm_sleep_in_us(uint64_t microseconds) +void libspdm_sleep(uint64_t microseconds) { } diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h similarity index 83% rename from src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h rename to src/nvidia/src/libraries/libspdm/3.1.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h index 5a6555415d..1036e8d676 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h +++ b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/spdm_crypt_ext_lib/cryptlib_ext.h @@ -8,6 +8,7 @@ #define CRYPTLIB_EXT_H #include "hal/base.h" +#include "hal/library/cryptlib.h" /** * Retrieve the common name (CN) string from one X.509 certificate. @@ -192,7 +193,7 @@ extern bool libspdm_x509_get_tbs_cert(const uint8_t *cert, size_t cert_size, * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. * @param[in] pem_size Size of the PEM key data in bytes. * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. - * @param[out] rsa_context Pointer to new-generated RSA context which contain the retrieved + * @param[out] rsa_context Pointer to newly generated RSA context which contain the retrieved * RSA private key component. Use libspdm_rsa_free() function to free the * resource. * @@ -205,13 +206,90 @@ extern bool libspdm_rsa_get_private_key_from_pem(const uint8_t *pem_data, const char *password, void **rsa_context); +#if (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) +/** + * Gets the tag-designated RSA key component from the established RSA context. + * + * This function retrieves the tag-designated RSA key component from the + * established RSA context as a non-negative integer (octet string format + * represented in RSA PKCS#1). + * If specified key component has not been set or has been cleared, then returned + * bn_size is set to 0. + * If the big_number buffer is too small to hold the contents of the key, false + * is returned and bn_size is set to the required buffer size to obtain the key. + * + * If rsa_context is NULL, then return false. + * If bn_size is NULL, then return false. + * If bn_size is large enough but big_number is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] key_tag Tag of RSA key component being set. + * @param[out] big_number Pointer to octet integer buffer. + * @param[in, out] bn_size On input, the size of big number buffer in bytes. + * On output, the size of data returned in big number buffer in bytes. + * + * @retval true RSA key component was retrieved successfully. + * @retval false Invalid RSA key component tag. + * @retval false bn_size is too small. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_get_key(void *rsa_context, const libspdm_rsa_key_tag_t key_tag, + uint8_t *big_number, size_t *bn_size); + +/** + * Validates key components of RSA context. + * NOTE: This function performs integrity checks on all the RSA key material, so + * the RSA key structure must contain all the private key data. + * + * This function validates key components of RSA context in following aspects: + * - Whether p is a prime + * - Whether q is a prime + * - Whether n = p * q + * - Whether d*e = 1 mod lcm(p-1,q-1) + * + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in] rsa_context Pointer to RSA context to check. + * + * @retval true RSA key components are valid. + * @retval false RSA key components are not valid. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_check_key(void *rsa_context); + +/** + * Generates RSA key components. + * + * This function generates RSA key components. It takes RSA public exponent E and + * length in bits of RSA modulus N as input, and generates all key components. + * If public_exponent is NULL, the default RSA public exponent (0x10001) will be used. + * + * If rsa_context is NULL, then return false. + * If this interface is not supported, then return false. + * + * @param[in, out] rsa_context Pointer to RSA context being set. + * @param[in] modulus_length Length of RSA modulus N in bits. + * @param[in] public_exponent Pointer to RSA public exponent. + * @param[in] public_exponent_size Size of RSA public exponent buffer in bytes. + * + * @retval true RSA key component was generated successfully. + * @retval false Invalid RSA key component tag. + * @retval false This interface is not supported. + **/ +extern bool libspdm_rsa_generate_key(void *rsa_context, size_t modulus_length, + const uint8_t *public_exponent, + size_t public_exponent_size); +#endif /* (LIBSPDM_RSA_SSA_SUPPORT) || (LIBSPDM_RSA_PSS_SUPPORT) */ + /** * Retrieve the EC Private key from the password-protected PEM key data. * * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. * @param[in] pem_size Size of the PEM key data in bytes. * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. - * @param[out] ec_context Pointer to new-generated EC DSA context which contain the retrieved + * @param[out] ec_context Pointer to newly generated EC DSA context which contain the retrieved * EC private key component. Use libspdm_ec_free() function to free the * resource. * @@ -232,7 +310,7 @@ extern bool libspdm_ec_get_private_key_from_pem(const uint8_t *pem_data, size_t * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. * @param[in] pem_size Size of the PEM key data in bytes. * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. - * @param[out] ecd_context Pointer to new-generated Ed DSA context which contain the retrieved + * @param[out] ecd_context Pointer to newly generated Ed DSA context which contain the retrieved * Ed private key component. Use libspdm_ecd_free() function to free the * resource. * @@ -253,7 +331,7 @@ extern bool libspdm_ecd_get_private_key_from_pem(const uint8_t *pem_data, * @param[in] pem_data Pointer to the PEM-encoded key data to be retrieved. * @param[in] pem_size Size of the PEM key data in bytes. * @param[in] password NULL-terminated passphrase used for encrypted PEM key data. - * @param[out] sm2_context Pointer to new-generated sm2 context which contain the retrieved + * @param[out] sm2_context Pointer to newly generated sm2 context which contain the retrieved * sm2 private key component. Use sm2_free() function to free the * resource. * @@ -409,23 +487,6 @@ extern bool libspdm_hkdf_sm3_256_extract_and_expand(const uint8_t *key, size_t k const uint8_t *info, size_t info_size, uint8_t *out, size_t out_size); -/** - * Sets the public key component into the established EC context. - * - * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. - * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. - * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. - * - * @param[in, out] ec_context Pointer to EC context being set. - * @param[in] public Pointer to the buffer to receive generated public X,Y. - * @param[in] public_size The size of public buffer in bytes. - * - * @retval true EC public key component was set successfully. - * @retval false Invalid EC public key component. - **/ -extern bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, - size_t public_key_size); - /** * Sets the private key component into the established EC context. * @@ -444,6 +505,23 @@ extern bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, extern bool libspdm_ec_set_priv_key(void *ec_context, const uint8_t *private_key, size_t private_key_size); +/** + * Sets the public key component into the established EC context. + * + * For P-256, the public_size is 64. first 32-byte is X, second 32-byte is Y. + * For P-384, the public_size is 96. first 48-byte is X, second 48-byte is Y. + * For P-521, the public_size is 132. first 66-byte is X, second 66-byte is Y. + * + * @param[in, out] ec_context Pointer to EC context being set. + * @param[in] public Pointer to the buffer to receive generated public X,Y. + * @param[in] public_size The size of public buffer in bytes. + * + * @retval true EC public key component was set successfully. + * @retval false Invalid EC public key component. + **/ +extern bool libspdm_ec_set_pub_key(void *ec_context, const uint8_t *public_key, + size_t public_key_size); + /** * Gets the public key component from the established EC context. * @@ -475,39 +553,6 @@ extern bool libspdm_ec_get_pub_key(void *ec_context, uint8_t *public_key, size_t **/ extern bool libspdm_ec_check_key(const void *ec_context); -/** - * Sets the public key component into the established Ed context. - * - * For ed25519, the public_size is 32. - * For ed448, the public_size is 57. - * - * @param[in, out] ecd_context Pointer to Ed context being set. - * @param[in] public_key Pointer to the buffer to receive generated public X,Y. - * @param[in] public_size The size of public buffer in bytes. - * - * @retval true Ed public key component was set successfully. - * @retval false Invalid EC public key component. - **/ -extern bool libspdm_ecd_set_pub_key(void *ecd_context, const uint8_t *public_key, - size_t public_key_size); - -/** - * Gets the public key component from the established Ed context. - * - * For ed25519, the public_size is 32. - * For ed448, the public_size is 57. - * - * @param[in, out] ecd_context Pointer to Ed context being set. - * @param[out] public Pointer to the buffer to receive generated public X,Y. - * @param[in, out] public_size On input, the size of public buffer in bytes. - * On output, the size of data returned in public buffer in bytes. - * - * @retval true Ed key component was retrieved successfully. - * @retval false Invalid EC public key component. - **/ -extern bool libspdm_ecd_get_pub_key(void *ecd_context, uint8_t *public_key, - size_t *public_key_size); - /** * Validates key components of Ed context. * NOTE: This function performs integrity checks on all the Ed key material, so @@ -665,4 +710,44 @@ extern bool libspdm_sm2_dsa_check_key(const void *sm2_context); extern bool libspdm_sm2_dsa_generate_key(void *sm2_context, uint8_t *public_data, size_t *public_size); +#if LIBSPDM_ENABLE_CAPABILITY_CSR_CAP +/** + * Generate a CSR. + * + * @param[in] hash_nid hash algo for sign + * @param[in] asym_nid asym algo for sign + * + * @param[in] requester_info requester info to gen CSR + * @param[in] requester_info_length The len of requester info + * + * @param[in] is_ca if true, set basic_constraints: CA:true; Otherwise, set to false. + * + * @param[in] context Pointer to asymmetric context + * @param[in] subject_name Subject name: should be break with ',' in the middle + * example: "C=AA,CN=BB" + * + * Subject names should contain a comma-separated list of OID types and values: + * The valid OID type name is in: + * {"CN", "commonName", "C", "countryName", "O", "organizationName","L", + * "OU", "organizationalUnitName", "ST", "stateOrProvinceName", "emailAddress", + * "serialNumber", "postalAddress", "postalCode", "dnQualifier", "title", + * "SN","givenName","GN", "initials", "pseudonym", "generationQualifier", "domainComponent", "DC"}. + * Note: The object of C and countryName should be CSR Supported Country Codes + * + * @param[in, out] csr_len For input, csr_len is the size of store CSR buffer. + * For output, csr_len is CSR len for DER format + * @param[in, out] csr_pointer For input, csr_pointer is buffer address to store CSR. + * For output, csr_pointer is address for stored CSR. + * The csr_pointer address will be changed. + * + * @retval true Success. + * @retval false Failed to gen CSR. + **/ +extern bool libspdm_gen_x509_csr(size_t hash_nid, size_t asym_nid, + uint8_t *requester_info, size_t requester_info_length, + bool is_ca, + void *context, char *subject_name, + size_t *csr_len, uint8_t *csr_pointer); +#endif /* LIBSPDM_ENABLE_CAPABILITY_CSR_CAP */ + #endif /* CRYPTLIB_EXT_H */ diff --git a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/spdm_device_secret_lib_null/lib.c similarity index 56% rename from src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c rename to src/nvidia/src/libraries/libspdm/3.1.1/os_stub/spdm_device_secret_lib_null/lib.c index b2369f2da7..5730a072a8 100644 --- a/src/nvidia/src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c +++ b/src/nvidia/src/libraries/libspdm/3.1.1/os_stub/spdm_device_secret_lib_null/lib.c @@ -9,7 +9,13 @@ * It follows the SPDM Specification. **/ -#include "library/spdm_device_secret_lib.h" +#include "hal/library/responder/asymsignlib.h" +#include "hal/library/responder/csrlib.h" +#include "hal/library/responder/measlib.h" +#include "hal/library/responder/psklib.h" +#include "hal/library/responder/setcertlib.h" +#include "hal/library/requester/reqasymsignlib.h" +#include "hal/library/requester/psklib.h" #if LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP libspdm_return_t libspdm_measurement_collection( @@ -26,6 +32,40 @@ libspdm_return_t libspdm_measurement_collection( return LIBSPDM_STATUS_UNSUPPORTED_CAP; } +bool libspdm_measurement_opaque_data( + spdm_version_number_t spdm_version, + uint8_t measurement_specification, + uint32_t measurement_hash_algo, + uint8_t measurement_index, + uint8_t request_attribute, + void *opaque_data, + size_t *opaque_data_size) +{ + return false; +} + +bool libspdm_challenge_opaque_data( + spdm_version_number_t spdm_version, + uint8_t slot_id, + uint8_t *measurement_summary_hash, + size_t measurement_summary_hash_size, + void *opaque_data, + size_t *opaque_data_size) +{ + return false; +} + +bool libspdm_encap_challenge_opaque_data( + spdm_version_number_t spdm_version, + uint8_t slot_id, + uint8_t *measurement_summary_hash, + size_t measurement_summary_hash_size, + void *opaque_data, + size_t *opaque_data_size) +{ + return false; +} + bool libspdm_generate_measurement_summary_hash( spdm_version_number_t spdm_version, uint32_t base_hash_algo, @@ -33,13 +73,15 @@ bool libspdm_generate_measurement_summary_hash( uint32_t measurement_hash_algo, uint8_t measurement_summary_hash_type, uint8_t *measurement_summary_hash, - size_t *measurement_summary_hash_size) + uint32_t measurement_summary_hash_size) { return false; } #endif /* LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP */ +// NVIDIA_EDIT: Commenting out stub as we need this implementation for mutual authentication. #if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +/* bool libspdm_requester_data_sign( spdm_version_number_t spdm_version, uint8_t op_code, uint16_t req_base_asym_alg, @@ -49,6 +91,7 @@ bool libspdm_requester_data_sign( { return false; } +*/ #endif /* LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP */ bool libspdm_responder_data_sign( @@ -61,7 +104,7 @@ bool libspdm_responder_data_sign( return false; } -#if LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP +#if LIBSPDM_ENABLE_CAPABILITY_PSK_CAP bool libspdm_psk_handshake_secret_hkdf_expand( spdm_version_number_t spdm_version, uint32_t base_hash_algo, @@ -85,21 +128,30 @@ bool libspdm_psk_master_secret_hkdf_expand( { return false; } -#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP */ +#endif /* LIBSPDM_ENABLE_CAPABILITY_PSK_CAP */ + +#if LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP +bool libspdm_is_in_trusted_environment() +{ + return false; +} -#if LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP bool libspdm_write_certificate_to_nvm(uint8_t slot_id, const void * cert_chain, - size_t cert_chain_size) + size_t cert_chain_size, + uint32_t base_hash_algo, uint32_t base_asym_algo) { return false; } -#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP */ +#endif /* LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP */ -#if LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP +#if LIBSPDM_ENABLE_CAPABILITY_CSR_CAP bool libspdm_gen_csr(uint32_t base_hash_algo, uint32_t base_asym_algo, bool *need_reset, + const void *request, size_t request_size, uint8_t *requester_info, size_t requester_info_length, - size_t *csr_len, uint8_t **csr_pointer) + uint8_t *opaque_data, uint16_t opaque_data_length, + size_t *csr_len, uint8_t *csr_pointer, + bool is_device_cert_model) { return false; } -#endif /* LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP */ +#endif /* LIBSPDM_ENABLE_CAPABILITY_CSR_CAP */ diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c index e9b97a4a93..01361415df 100644 --- a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_crypt_null.c @@ -51,4 +51,47 @@ bool libspdm_ec_get_private_key_from_pem(const uint8_t *pem_data, size_t pem_siz return false; } +bool libspdm_ec_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **ec_context) +{ + LIBSPDM_ASSERT(false); + return false; +} + +void libspdm_rsa_free +( + void *rsa_context +) +{ +} + +bool libspdm_rsa_pss_verify(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + const uint8_t *signature, size_t sig_size) +{ + return false; +} + +bool libspdm_rsa_pss_sign(void *rsa_context, size_t hash_nid, + const uint8_t *message_hash, size_t hash_size, + uint8_t *signature, size_t *sig_size) +{ + return false; +} + +bool libspdm_rsa_get_public_key_from_der(const uint8_t *der_data, + size_t der_size, + void **rsa_context) +{ + return true; +} + +void *libspdm_rsa_new +( + void +) +{ + return NULL; +} diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c index 0ac0766eb8..8c2f0e55cc 100644 --- a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_debuglib.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -56,3 +56,14 @@ libspdm_debug_assert g_libspdmAssertHit = NV_TRUE; DBG_BREAKPOINT(); } + +void +libspdm_debug_print +( + size_t error_level, + const char *format, + ... +) +{ + return; +} diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c index 7e97113adf..3228a55c72 100644 --- a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_memlib.c @@ -45,12 +45,11 @@ * @param length The number of bytes to set. * @param value The value with which to fill length bytes of buffer. * - * @return buffer. * **/ -void *libspdm_set_mem(void *buffer, size_t length, uint8_t value) +void libspdm_set_mem(void *buffer, size_t length, uint8_t value) { - return portMemSet(buffer, value, length); + portMemSet(buffer, value, length); } @@ -87,11 +86,9 @@ void *libspdm_set_mem(void *buffer, size_t length, uint8_t value) * @param src_buf Source buffer to copy from. * @param src_len The number of bytes to copy from the source buffer. * - * @return 0 on success. non-zero on error. - * **/ -int libspdm_copy_mem(void *dst_buf, size_t dst_len, - const void *src_buf, size_t src_len) +void libspdm_copy_mem(void *dst_buf, size_t dst_len, + const void *src_buf, size_t src_len) { volatile void *pRet = NULL; @@ -99,21 +96,20 @@ int libspdm_copy_mem(void *dst_buf, size_t dst_len, * Do not zero "dst" in this case. */ if (dst_buf == NULL || dst_len > (SIZE_MAX >> 1)) { LIBSPDM_ASSERT(0); - return -1; + return; } /* Gaurd against invalid source. Zero "dst" in this case. */ if (src_buf == NULL) { LIBSPDM_ASSERT(0); - return -1; + return; } /* Guard against invalid lengths. Zero "dst" in these cases. */ if (src_len > dst_len || src_len > (SIZE_MAX >> 1)) { - LIBSPDM_ASSERT(0); - return -1; + return; } pRet = portMemCopy(dst_buf, dst_len, src_buf, src_len); @@ -121,10 +117,10 @@ int libspdm_copy_mem(void *dst_buf, size_t dst_len, if (pRet == NULL) { LIBSPDM_ASSERT(0); - return -1; + return; } - return 0; + return; } /** @@ -138,10 +134,8 @@ int libspdm_copy_mem(void *dst_buf, size_t dst_len, * @param buffer The pointer to the target buffer to fill with zeros. * @param length The number of bytes in buffer to fill with zeros. * - * @return buffer. - * **/ -void *libspdm_zero_mem(void *buffer, size_t length) +void libspdm_zero_mem(void *buffer, size_t length) { - return portMemSet(buffer, 0, length); + portMemSet(buffer, 0, length); } diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h index 3712d65892..e94c3497bd 100644 --- a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rmconfig.h @@ -24,106 +24,106 @@ #ifndef _NVSPDM_RMCONFIG_H_ #define _NVSPDM_RMCONFIG_H_ +// +// RM's configuration values for libspdm. Replaces default values in spdm_lib_config.h. +// Must define LIBSPDM_CONFIG in CFLAGS during build in order to successfully replace. // // NOTE: Any updates to macros must first test a local build with LIBSPDM_CHECK_MACRO // set to 1! This ensures the macro combination is valid. Kept at 0 since adds // overhead to build otherwise. // -#define LIBSPDM_CHECK_MACRO 0 +#define LIBSPDM_CHECK_MACRO 1 -// -// RM's configuration values for libspdm. Replaces default values in spdm_lib_config.h. -// Must define LIBSPDM_CONFIG in CFLAGS during build in order to successfully replace. -// -#define LIBSPDM_MAX_VERSION_COUNT 5 -#define LIBSPDM_MAX_SESSION_COUNT 1 - -#define LIBSPDM_PSK_CONTEXT_LENGTH LIBSPDM_MAX_HASH_SIZE -#define LIBSPDM_PSK_MAX_HINT_LENGTH 16 - -#define LIBSPDM_MAX_ROOT_CERT_SUPPORT 1 - -#define LIBSPDM_MAX_MEASUREMENT_BLOCK_COUNT 64 -#define LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE 0x1000 - -#define LIBSPDM_MAX_CERT_CHAIN_SIZE 0x1000 -#define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN 1024 - -#define LIBSPDM_MAX_MESSAGE_BUFFER_SIZE 0x1100 -#define LIBSPDM_MAX_MESSAGE_SMALL_BUFFER_SIZE 0x100 -#define LIBSPDM_MAX_MESSAGE_MEDIUM_BUFFER_SIZE 0x300 - -// Do not retry messages. -#define LIBSPDM_MAX_REQUEST_RETRY_TIMES 0 - -// We don't expect to use callbacks, nonzero value is required for compilation. -#define LIBSPDM_MAX_SESSION_STATE_CALLBACK_NUM 1 -#define LIBSPDM_MAX_CONNECTION_STATE_CALLBACK_NUM 1 -#define LIBSPDM_MAX_KEY_UPDATE_CALLBACK_NUM 1 - -// CSR's are not supported. -#define LIBSPDM_MAX_CSR_SIZE 0x0 - -// Use running hash over recording all transcript data. -#define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 - -#define LIBSPDM_ECDSA_SUPPORT 1 -#define LIBSPDM_RSA_SSA_SUPPORT 0 -#define LIBSPDM_RSA_PSS_SUPPORT 0 -#define LIBSPDM_SM2_DSA_SUPPORT 0 -#define LIBSPDM_EDDSA_ED25519_SUPPORT 0 -#define LIBSPDM_EDDSA_ED448_SUPPORT 0 - -#define LIBSPDM_ECDHE_SUPPORT 1 -#define LIBSPDM_FFDHE_SUPPORT 0 -#define LIBSPDM_SM2_KEY_EXCHANGE_SUPPORT 0 - -#define LIBSPDM_AEAD_GCM_SUPPORT 1 -#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 0 -#define LIBSPDM_AEAD_SM4_SUPPORT 0 - -#define LIBSPDM_SHA256_SUPPORT 1 -#define LIBSPDM_SHA384_SUPPORT 1 -#define LIBSPDM_SHA512_SUPPORT 0 -#define LIBSPDM_SHA3_256_SUPPORT 0 -#define LIBSPDM_SHA3_384_SUPPORT 0 -#define LIBSPDM_SHA3_512_SUPPORT 0 -#define LIBSPDM_SM3_256_SUPPORT 0 - -#define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 -#define LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP 1 -#define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 -#define LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP 0 -#define LIBSPDM_ENABLE_CAPABILITY_PSK_EX_CAP 0 -#define LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP 0 -#define LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP 0 -#define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 0 -#define LIBSPDM_ENABLE_CAPABILITY_GET_CSR_CAP 0 -#define LIBSPDM_ENABLE_CAPABILITY_SET_CERTIFICATE_CAP 0 -#define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 0 - -// Compiler will complain if these deprecated aliases of above macros are not defined. -#define LIBSPDM_ENABLE_CHUNK_CAP 0 -#define LIBSPDM_ENABLE_SET_CERTIFICATE_CAP 0 - -#define LIBSPDM_MAX_SPDM_MSG_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE -#define LIBSPDM_DATA_TRANSFER_SIZE LIBSPDM_MAX_MESSAGE_BUFFER_SIZE - -#define LIBSPDM_TRANSPORT_ADDITIONAL_SIZE 64 -#define LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE (LIBSPDM_DATA_TRANSFER_SIZE + \ - LIBSPDM_TRANSPORT_ADDITIONAL_SIZE) - -#define LIBSPDM_SCRATCH_BUFFER_SIZE (LIBSPDM_SENDER_RECEIVE_BUFFER_SIZE) +// Enable FIPS 140-3 mode. +#define LIBSPDM_FIPS_MODE 1 // // We want debug asserts enabled, but we don't care about debug prints or the debug blocks. // Don't define LIBSPDM_DEBUG_ENABLE, as it will override these settings below. // -#define LIBSPDM_DEBUG_ASSERT_ENABLE 1 -#define LIBSPDM_DEBUG_PRINT_ENABLE 0 -#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 - -// Enable in version 3.0 when we can use to replace transcript WAR. -#define LIBSPDM_ENABLE_MSG_LOG 0 +#define LIBSPDM_DEBUG_ASSERT_ENABLE 1 +#define LIBSPDM_DEBUG_PRINT_ENABLE 1 +#define LIBSPDM_DEBUG_BLOCK_ENABLE 0 + +// These settings are all libspdm default. +#define LIBSPDM_MAX_VERSION_COUNT 5 +#define LIBSPDM_PSK_CONTEXT_LENGTH LIBSPDM_MAX_HASH_SIZE +#define LIBSPDM_PSK_MAX_HINT_LENGTH 16 +#define LIBSPDM_MAX_ROOT_CERT_SUPPORT 1 + +// Limit to one session at a time. +#define LIBSPDM_MAX_SESSION_COUNT 1 + +#define LIBSPDM_MAX_CERT_CHAIN_SIZE 0x1000 +#define LIBSPDM_MAX_MEASUREMENT_RECORD_SIZE 0x1000 +#define LIBSPDM_MAX_CERT_CHAIN_BLOCK_LEN LIBSPDM_MAX_CERT_CHAIN_SIZE + +// Use running hash rather than recording all transcript data. +#define LIBSPDM_RECORD_TRANSCRIPT_DATA_SUPPORT 0 + +#define LIBSPDM_ECDSA_P384_SUPPORT 1 +#define LIBSPDM_RSA_SSA_2048_SUPPORT 0 +#define LIBSPDM_RSA_SSA_3072_SUPPORT 0 +#define LIBSPDM_RSA_SSA_4096_SUPPORT 0 +#define LIBSPDM_RSA_PSS_2048_SUPPORT 0 +#define LIBSPDM_RSA_PSS_4096_SUPPORT 0 +#define LIBSPDM_ECDSA_P256_SUPPORT 0 +#define LIBSPDM_ECDSA_P521_SUPPORT 0 +#define LIBSPDM_SM2_DSA_P256_SUPPORT 0 +#define LIBSPDM_EDDSA_ED25519_SUPPORT 0 +#define LIBSPDM_EDDSA_ED448_SUPPORT 0 + +#define LIBSPDM_ECDHE_P384_SUPPORT 1 +#define LIBSPDM_FFDHE_2048_SUPPORT 0 +#define LIBSPDM_FFDHE_3072_SUPPORT 0 +#define LIBSPDM_FFDHE_4096_SUPPORT 0 +#define LIBSPDM_ECDHE_P256_SUPPORT 0 +#define LIBSPDM_ECDHE_P521_SUPPORT 0 +#define LIBSPDM_SM2_KEY_EXCHANGE_P256_SUPPORT 0 + +#define LIBSPDM_AEAD_AES_256_GCM_SUPPORT 1 +#define LIBSPDM_AEAD_AES_128_GCM_SUPPORT 0 +#define LIBSPDM_AEAD_CHACHA20_POLY1305_SUPPORT 0 +#define LIBSPDM_AEAD_SM4_128_GCM_SUPPORT 0 + +#define LIBSPDM_SHA256_SUPPORT 1 +#define LIBSPDM_SHA384_SUPPORT 1 +#define LIBSPDM_SHA512_SUPPORT 0 +#define LIBSPDM_SHA3_256_SUPPORT 0 +#define LIBSPDM_SHA3_384_SUPPORT 0 +#define LIBSPDM_SHA3_512_SUPPORT 0 +#define LIBSPDM_SM3_256_SUPPORT 0 + +#define LIBSPDM_CERT_PARSE_SUPPORT 1 + +#define LIBSPDM_ENABLE_CAPABILITY_CERT_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_MEAS_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_KEY_EX_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_HBEAT_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_CHAL_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_PSK_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_CSR_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_SET_CERT_CAP 0 +#define LIBSPDM_ENABLE_CAPABILITY_CHUNK_CAP 0 + +#define LIBSPDM_SEND_GET_CERTIFICATE_SUPPORT 1 +#define LIBSPDM_SEND_CHALLENGE_SUPPORT 0 +#define LIBSPDM_RESPOND_IF_READY_SUPPORT 0 + +// Enable message log to simplify Attestation Report retrieval. +#define LIBSPDM_ENABLE_MSG_LOG 1 + +// Enable runtime checks to ensure SPDM context validity. +#define LIBSPDM_CHECK_SPDM_CONTEXT 1 + +#include +// Enable mutual authentication and encapsulated process both. +#define LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP 1 +#define LIBSPDM_ENABLE_CAPABILITY_ENCAP_CAP 1 +#define LIBSPDM_RSA_PSS_3072_SUPPORT 1 + +#define LIBSPDM_RSA_PSS_SUPPORT ((LIBSPDM_RSA_PSS_2048_SUPPORT) || \ + (LIBSPDM_RSA_PSS_3072_SUPPORT) || \ + (LIBSPDM_RSA_PSS_4096_SUPPORT)) #endif // _NVSPDM_RMCONFIG_H_ diff --git a/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rsa.c b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rsa.c new file mode 100644 index 0000000000..65ae8850d9 --- /dev/null +++ b/src/nvidia/src/libraries/libspdm/nvidia/nvspdm_rsa.c @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Comments, prototypes and checks taken from DMTF: Copyright 2021-2022 DMTF. All rights reserved. + * License: BSD 3-Clause License. For full text see link: https://github.com/DMTF/libspdm/blob/main/LICENSE.md + */ +#include +#include "library/debuglib.h" +#include "library/memlib.h" +#include "library/cryptlib.h" +#include +#include "industry_standard/spdm.h" + +#if LIBSPDM_ENABLE_CAPABILITY_MUT_AUTH_CAP +bool libspdm_requester_data_sign +( + spdm_version_number_t spdm_version, uint8_t op_code, + uint16_t req_base_asym_alg, + uint32_t base_hash_algo, bool is_data_hash, + const uint8_t *message, size_t message_size, + uint8_t *signature, size_t *sig_size) +{ + + if (op_code != SPDM_FINISH || + req_base_asym_alg != SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 || + base_hash_algo != SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384) + { + return false; + } + + // TODO: Implement RSA3K-PSS sign here. + + return true; +} + +#endif diff --git a/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk b/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk index 3d264677e4..9bf1e77a58 100644 --- a/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk +++ b/src/nvidia/src/libraries/libspdm/nvidia/openspdm.mk @@ -31,7 +31,7 @@ NV_USE_LIBSPDM := 0 # Set some common path defines for readability. LIBSPDM_SOURCE_DIR := src/libraries/libspdm -LIBSPDM_VERSION := 2.3.1 +LIBSPDM_VERSION := 3.1.1 # List all files which depend on libspdm headers under LIBSPDM_SOURCES. @@ -48,6 +48,7 @@ LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_debuglib.c LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_malloclib.c LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_rng.c LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_memlib.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/nvidia/nvspdm_rsa.c # libspdm source files LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_common_lib/libspdm_com_context_data.c @@ -76,6 +77,13 @@ LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_request LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_get_version.c LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_handle_error_response.c LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_key_exchange.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_encap_certificate.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_encap_challenge_auth.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_encap_digests.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_encap_error.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_encap_key_update.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_encap_request.c +LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_heartbeat.c LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_key_update.c LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c LIBSPDM_SOURCES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/library/spdm_requester_lib/libspdm_req_send_receive.c @@ -93,6 +101,7 @@ LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/include LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/include/hal LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/include LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub +LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/$(LIBSPDM_VERSION)/os_stub/cryptlib_null LIBSPDM_INCLUDES += $(LIBSPDM_SOURCE_DIR)/nvidia # Override the default libspdm configuration with our own. diff --git a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c index 2cc0f4cc8f..e75eee264f 100644 --- a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c +++ b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c @@ -1044,16 +1044,16 @@ portMemPrintTrackingInfo pTracking = &portMemGlobals.mainTracking; if (pTracking == &portMemGlobals.mainTracking) - portDbgPrintf("[NvPort] ******** Aggregate Memory Tracking ********\n"); + portDbgPrintf("[NvPort] ======== Aggregate Memory Tracking ========\n"); else if ((pTracking == portMemGlobals.alloc.nonPaged.pTracking) && (pTracking == portMemGlobals.alloc.paged.pTracking)) - portDbgPrintf("[NvPort] ******** Global Allocator Tracking ********\n"); + portDbgPrintf("[NvPort] ======== Global Allocator Tracking ========\n"); else if (pTracking == portMemGlobals.alloc.nonPaged.pTracking) - portDbgPrintf("[NvPort] ******** Global Non-Paged Memory Allocator Tracking ********\n"); + portDbgPrintf("[NvPort] ======== Global Non-Paged Memory Allocator Tracking ========\n"); else if (pTracking == portMemGlobals.alloc.paged.pTracking) - portDbgPrintf("[NvPort] ******** Global Paged Memory Allocator Tracking ********\n"); + portDbgPrintf("[NvPort] ======== Global Paged Memory Allocator Tracking ========\n"); else - portDbgPrintf("[NvPort] ******** Memory Allocator %p Tracking ******** \n", pTracking->pAllocator); + portDbgPrintf("[NvPort] ======== Memory Allocator %p Tracking ======== \n", pTracking->pAllocator); if (pTracking->counter.activeAllocs != 0) portDbgPrintf(" !!! MEMORY LEAK DETECTED (%u blocks) !!!\n", diff --git a/src/nvidia/src/libraries/poolalloc/poolalloc.c b/src/nvidia/src/libraries/poolalloc/poolalloc.c index ff80779ad4..248a4f4609 100644 --- a/src/nvidia/src/libraries/poolalloc/poolalloc.c +++ b/src/nvidia/src/libraries/poolalloc/poolalloc.c @@ -262,9 +262,12 @@ poolReserve NvU64 numPages ) { - NvU64 i, freeLength; + NvU64 i, freeLength, totalAlloc; + NV_STATUS status = NV_ERR_NO_MEMORY; allocCallback_t allocCb; - POOLALLOC_HANDLE pageHandle; + POOLALLOC_HANDLE *pPageHandle = NULL; + POOLNODE *pNode = NULL; + if (pPool == NULL || (pPool->callBackInfo).allocCb == NULL) { @@ -277,32 +280,45 @@ poolReserve return NV_OK; } + totalAlloc = numPages - freeLength; + allocCb = (pPool->callBackInfo).allocCb; - for (i = 0; i < (numPages - freeLength); i++) - { - if ((*allocCb)((pPool->callBackInfo).pUpstreamCtx, - pPool->upstreamPageSize, &pageHandle) == NV_OK) - { - POOLNODE *pNode; + pPageHandle = PORT_ALLOC(pPool->pAllocator, totalAlloc * sizeof(POOLALLOC_HANDLE)); + NV_ASSERT_OR_GOTO(pPageHandle != NULL, free_none); - pNode = PORT_ALLOC(pPool->pAllocator, sizeof(*pNode)); - listPrependExisting(&pPool->freeList, pNode); + NV_ASSERT_OK_OR_GOTO(status, + allocCb(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize, + totalAlloc, pPageHandle), + free_page); - pNode->pageAddr = pageHandle.address; - pNode->bitmap = NV_U64_MAX; - pNode->pParent = pageHandle.pMetadata; - } - else - { - return NV_ERR_NO_MEMORY; - } + status = NV_ERR_NO_MEMORY; + + for (i = 0; i < totalAlloc; i++) + { + pNode = PORT_ALLOC(pPool->pAllocator, sizeof(POOLNODE)); + NV_ASSERT_OR_GOTO(pNode != NULL, free_alloc); + + listPrependExisting(&pPool->freeList, pNode); + pNode->pageAddr = pPageHandle[i].address; + pNode->bitmap = NV_U64_MAX; + pNode->pParent = pPageHandle[i].pMetadata; } + status = NV_OK; freeLength = listCount(&pPool->freeList); NV_ASSERT(freeLength == numPages); - - return NV_OK; + goto free_page; +free_alloc: + for(; i < totalAlloc; i++) + { + pPool->callBackInfo.freeCb(pPool->callBackInfo.pUpstreamCtx, + pPool->upstreamPageSize, &pPageHandle[i]); + } +free_page: + PORT_FREE(pPool->pAllocator, pPageHandle); +free_none: + return status; } @@ -383,7 +399,7 @@ poolAllocate // if (FLD_TEST_DRF(_RMPOOL, _FLAGS, _AUTO_POPULATE, _ENABLE, pPool->flags)) { - if ((*allocCb)(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize, pPageHandle) == NV_OK) + if ((*allocCb)(pPool->callBackInfo.pUpstreamCtx, pPool->upstreamPageSize, 1, pPageHandle) == NV_OK) { POOLNODE *pNode; diff --git a/src/nvidia/src/libraries/resserv/src/rs_client.c b/src/nvidia/src/libraries/resserv/src/rs_client.c index 358061c164..48c710cbcf 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_client.c +++ b/src/nvidia/src/libraries/resserv/src/rs_client.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -523,7 +523,7 @@ clientCopyResource_IMPL callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldContext, &callContext)); // // Kernel clients are allowed to dup anything, unless they request otherwise. @@ -560,7 +560,7 @@ clientCopyResource_IMPL } } - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) return status; @@ -668,9 +668,11 @@ _clientAllocResourceHelper } callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), fail); + status = resservResourceFactory(pServer->pAllocator, &callContext, pParams, &pResource); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto fail; @@ -724,6 +726,8 @@ _clientAllocResourceHelper fail: if (pResource != NULL) { + NV_STATUS callContextStatus; + RS_RES_FREE_PARAMS_INTERNAL params; pOldContext = NULL; @@ -738,11 +742,20 @@ _clientAllocResourceHelper callContext.pResourceRef = pResourceRef; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); - resSetFreeParams(pResource, &callContext, ¶ms); + callContextStatus = resservSwapTlsCallContext(&pOldContext, &callContext); + if (callContextStatus == NV_OK) + { + resSetFreeParams(pResource, &callContext, ¶ms); + + objDelete(pResource); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Failed to set call context! Error: 0x%x\n", + callContextStatus); + } - objDelete(pResource); - resservRestoreTlsCallContext(pOldContext); } if (pResourceRef != NULL) @@ -798,7 +811,9 @@ clientFreeResource_IMPL if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + resSetFreeParams(pResource, &callContext, pParams); resPreDestruct(pResource); @@ -825,7 +840,7 @@ clientFreeResource_IMPL pResourceRef->pResource = NULL; - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); done: if (!pParams->bInvalidateOnly) @@ -872,9 +887,10 @@ clientUnmapMemory_IMPL if (pSecInfo != NULL) callContext.secInfo = *pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_RETURN(resservSwapTlsCallContext(&pOldContext, &callContext)); + status = resUnmap(pResourceRef->pResource, &callContext, pCpuMapping); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) { @@ -908,7 +924,7 @@ clientInterMap_IMPL return NV_ERR_INVALID_CLIENT; } -void +NV_STATUS clientInterUnmap_IMPL ( RsClient *pClient, @@ -916,7 +932,7 @@ clientInterUnmap_IMPL RS_INTER_UNMAP_PARAMS *pParams ) { - return; + return NV_ERR_INVALID_CLIENT; } NV_STATUS @@ -1212,9 +1228,9 @@ _unmapInterMapping params.hClient = pClient->hClient; params.hMapper = pMapperRef->hResource; params.hDevice = pMapping->pContextRef->hResource; - params.hMappable = pMapping->pMappableRef->hResource; params.flags = pMapping->flags; params.dmaOffset = pMapping->dmaOffset; + params.size = 0; params.pMemDesc = pMapping->pMemDesc; params.pSecInfo = pSecInfo; params.pLockInfo = &lockInfo; diff --git a/src/nvidia/src/libraries/resserv/src/rs_resource.c b/src/nvidia/src/libraries/resserv/src/rs_resource.c index 78402eeda3..98cde8f4e9 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_resource.c +++ b/src/nvidia/src/libraries/resserv/src/rs_resource.c @@ -629,44 +629,6 @@ refFreeCpuMappingPrivate } #endif /* RS_STANDALONE */ -NV_STATUS -refFindInterMapping -( - RsResourceRef *pMapperRef, - RsResourceRef *pMappableRef, - RsResourceRef *pContextRef, - NvU64 dmaOffset, - RsInterMapping **ppMapping -) -{ - RsInterMappingListIter it; - NV_STATUS status = NV_ERR_OBJECT_NOT_FOUND; - RsInterMapping *pMapping = NULL; - - NV_ASSERT(pMapperRef != NULL); - - it = listIterAll(&pMapperRef->interMappings); - while (listIterNext(&it)) - { - pMapping = it.pValue; - if ((pMapping->pMappableRef == pMappableRef) && - (pMapping->pContextRef == pContextRef) && - (pMapping->dmaOffset == dmaOffset)) - { - status = NV_OK; - break; - } - } - - if (status != NV_OK) - pMapping = NULL; - - if (pMapping != NULL) - *ppMapping = pMapping; - - return status; -} - NV_STATUS refAddInterMapping ( diff --git a/src/nvidia/src/libraries/resserv/src/rs_server.c b/src/nvidia/src/libraries/resserv/src/rs_server.c index c775f83024..a11a0f3beb 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_server.c +++ b/src/nvidia/src/libraries/resserv/src/rs_server.c @@ -144,19 +144,32 @@ NV_STATUS serverFreeResourceTreeUnderLock(RsServer *pServer, RS_RES_FREE_PARAMS if (status != NV_OK) return status; - pLockInfo->flags |= RS_LOCK_FLAGS_FREE_SESSION_LOCK; - pLockInfo->traceOp = RS_LOCK_TRACE_FREE; - pLockInfo->traceClassId = pResourceRef->externalClassId; - status = serverResLock_Prologue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); - if (status != NV_OK) - goto done; + if (pResourceRef->pResource == NULL) + { + // + // We don't need to acquire the resource lock for a resource + // that already got freed during resource invalidation. + // + + status = clientFreeResource(pResourceRef->pClient, pServer, pFreeParams); + NV_ASSERT(status == NV_OK); + } + else + { + pLockInfo->flags |= RS_LOCK_FLAGS_FREE_SESSION_LOCK; + pLockInfo->traceOp = RS_LOCK_TRACE_FREE; + pLockInfo->traceClassId = pResourceRef->externalClassId; + status = serverResLock_Prologue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); + if (status != NV_OK) + goto done; - status = clientFreeResource(pResourceRef->pClient, pServer, pFreeParams); - NV_ASSERT(status == NV_OK); + status = clientFreeResource(pResourceRef->pClient, pServer, pFreeParams); + NV_ASSERT(status == NV_OK); -done: - serverResLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); + serverResLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); + } +done: serverSessionLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); return status; @@ -672,8 +685,11 @@ serverAllocResource } else { - hSecondClient = serverAllocLookupSecondClient(pParams->externalClassId, - pParams->pAllocParams); + status = serverAllocLookupSecondClient(pParams->externalClassId, + pParams->pAllocParams, + &hSecondClient); + if (status != NV_OK) + goto done; if (hSecondClient == 0) { @@ -1056,7 +1072,7 @@ serverFreeResourceTree status = clientGetResourceRef(pClient, pParams->hResource, &pResourceRef); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "hObject 0x%x not found for client 0x%x\n", + NV_PRINTF(LEVEL_NOTICE, "hObject 0x%x not found for client 0x%x\n", pParams->hResource, pParams->hClient); #if (RS_COMPATABILITY_MODE) @@ -1254,12 +1270,14 @@ serverControl { NV_STATUS status; RsClient *pClient; + RsClient *pSecondClient = NULL; RsResourceRef *pResourceRef = NULL; RS_LOCK_INFO *pLockInfo; NvU32 releaseFlags = 0; CALL_CONTEXT callContext; CALL_CONTEXT *pOldContext = NULL; LOCK_ACCESS_TYPE access = LOCK_ACCESS_WRITE; + NvHandle hSecondClient; pLockInfo = pParams->pLockInfo; NV_ASSERT_OR_RETURN(pLockInfo != NULL, NV_ERR_INVALID_ARGUMENT); @@ -1279,14 +1297,37 @@ serverControl if (status != NV_OK) goto done; - status = _serverLockClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, pParams->hClient, pLockInfo, &releaseFlags, &pClient); + status = serverControlLookupSecondClient(pParams->cmd, pParams->pParams, + pParams->pCookie, &hSecondClient); if (status != NV_OK) goto done; - if (!pClient->bActive) + if (hSecondClient == 0) { - status = NV_ERR_INVALID_STATE; - goto done; + status = _serverLockClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, + pParams->hClient, pLockInfo, &releaseFlags, &pClient); + if (status != NV_OK) + goto done; + + if (!pClient->bActive) + { + status = NV_ERR_INVALID_STATE; + goto done; + } + } + else + { + status = _serverLockDualClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, + pParams->hClient, hSecondClient, pLockInfo, &releaseFlags, + &pClient, &pSecondClient); + if (status != NV_OK) + goto done; + + if (!pClient->bActive || !pSecondClient->bActive) + { + status = NV_ERR_INVALID_STATE; + goto done; + } } status = clientValidate(pClient, &pParams->secInfo); @@ -1341,15 +1382,28 @@ serverControl } pLockInfo->pContextRef = pResourceRef->pParentRef; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = resControl(pResourceRef->pResource, &callContext, pParams); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); done: serverSessionLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); - _serverUnlockClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, pParams->hClient, pLockInfo, &releaseFlags); + if (pSecondClient != NULL) + { + _serverUnlockDualClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, + pParams->hClient, pSecondClient->hClient, + pLockInfo, &releaseFlags); + } + else + { + _serverUnlockClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, + pParams->hClient, pLockInfo, &releaseFlags); + } + serverTopLock_Epilogue(pServer, access, pLockInfo, &releaseFlags); if (pServer->bUnlockedParamCopy) @@ -1518,7 +1572,8 @@ _serverShareResourceAccessClient callContext.pResourceRef = pResourceRef; callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); if (hClientOwner == hClientTarget) { @@ -1541,7 +1596,7 @@ _serverShareResourceAccessClient goto restore_context; restore_context: - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); // NV_PRINTF(LEVEL_INFO, "hClientOwner %x: Shared hResource: %x with hClientTarget: %x\n", // hClientOwner, pParams->hResource, hClientTarget); @@ -1628,9 +1683,11 @@ serverShareResourceAccess callContext.secInfo = *pParams->pSecInfo; callContext.pLockInfo = pParams->pLockInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = clientShareResource(pClient, pResourceRef, pParams->pSharePolicy, &callContext); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; @@ -1732,9 +1789,11 @@ serverMap if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + status = resMap(pResource, &callContext, pParams, pCpuMapping); - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) goto done; @@ -1907,7 +1966,9 @@ serverInterMap if (pParams->pSecInfo != NULL) callContext.secInfo = *pParams->pSecInfo; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + bRestoreCallContext = NV_TRUE; status = refAddInterMapping(pMapperRef, pMappableRef, pContextRef, &pMapping); @@ -1925,13 +1986,14 @@ serverInterMap pMapping->flags = pParams->flags; pMapping->dmaOffset = pParams->dmaOffset; + pMapping->size = pParams->length; pMapping->pMemDesc = pParams->pMemDesc; done: serverInterMap_Epilogue(pServer, pParams, &releaseFlags); if (bRestoreCallContext) - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); if (status != NV_OK) { @@ -1945,6 +2007,135 @@ serverInterMap return status; } +static NV_STATUS +serverInterUnmapMapping +( + RsClient *pClient, + RsResourceRef *pMapperRef, + RsInterMapping *pMapping, + RS_INTER_UNMAP_PARAMS *pParams, + NvBool bPartialUnmap +) +{ + RsInterMapping *pNewMappingLeft = NULL; + RsInterMapping *pNewMappingRight = NULL; + NV_STATUS status = NV_OK; + + if (pParams->dmaOffset > pMapping->dmaOffset) + { + NV_ASSERT_OK_OR_GOTO(status, refAddInterMapping(pMapperRef, pMapping->pMappableRef, pMapping->pContextRef, &pNewMappingLeft), done); + + pNewMappingLeft->flags = pMapping->flags; + pNewMappingLeft->dmaOffset = pMapping->dmaOffset; + pNewMappingLeft->size = pParams->dmaOffset - pMapping->dmaOffset; + } + + if (pParams->dmaOffset + pParams->size < pMapping->dmaOffset + pMapping->size) + { + NV_ASSERT_OK_OR_GOTO(status, refAddInterMapping(pMapperRef, pMapping->pMappableRef, pMapping->pContextRef, &pNewMappingRight), done); + + pNewMappingRight->flags = pMapping->flags; + pNewMappingRight->dmaOffset = pParams->dmaOffset + pParams->size; + pNewMappingRight->size = pMapping->dmaOffset + pMapping->size - pNewMappingRight->dmaOffset; + } + + pParams->hMappable = pMapping->pMappableRef->hResource; + pParams->pMemDesc = pMapping->pMemDesc; + status = clientInterUnmap(pClient, pMapperRef, pParams); + +done: + if (bPartialUnmap && status != NV_OK) + { + if (pNewMappingLeft != NULL) + refRemoveInterMapping(pMapperRef, pNewMappingLeft); + + if (pNewMappingRight != NULL) + refRemoveInterMapping(pMapperRef, pNewMappingRight); + } + else + { + // Regular unmap should never fail when the range is found + NV_ASSERT(status == NV_OK); + refRemoveInterMapping(pMapperRef, pMapping); + } + + return status; +} + +static NV_STATUS +serverInterUnmapInternal +( + + RsClient *pClient, + RsResourceRef *pMapperRef, + RsResourceRef *pContextRef, + RS_INTER_UNMAP_PARAMS *pParams + +) +{ + RsInterMapping *pNextMapping = listHead(&pMapperRef->interMappings); + NvU64 unmapDmaOffset = pParams->dmaOffset; + NvU64 unmapSize = pParams->size; + NvBool bPartialUnmap = (unmapSize != 0); + NV_STATUS unmapStatus = NV_OK; + NV_STATUS status = bPartialUnmap ? NV_OK : NV_ERR_OBJECT_NOT_FOUND; + NvU64 unmapEnd; + + NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddU64(unmapDmaOffset, unmapSize, &unmapEnd), NV_ERR_INVALID_ARGUMENT); + + while (pNextMapping != NULL) + { + RsInterMapping *pMapping = pNextMapping; + pNextMapping = listNext(&pMapperRef->interMappings, pMapping); + + if (pMapping->pContextRef != pContextRef) + continue; + + NvU64 mappingEnd; + NV_ASSERT_OR_RETURN(portSafeAddU64(pMapping->dmaOffset, pMapping->size, &mappingEnd), NV_ERR_INVALID_STATE); + + if (bPartialUnmap && + mappingEnd > unmapDmaOffset && + pMapping->dmaOffset < unmapEnd) + { + if (pMapping->dmaOffset < unmapDmaOffset || mappingEnd > unmapEnd) + { + // If the mapping does not lie entirely in the unmapped range, we are in the "true" partial unmap path + NV_CHECK_TRUE_OR_GOTO(unmapStatus, LEVEL_ERROR, resIsPartialUnmapSupported(pMapperRef->pResource), NV_ERR_INVALID_ARGUMENT, done); + // It is unclear what to do with pMemDesc when the mapping is split + NV_ASSERT_TRUE_OR_GOTO(unmapStatus, pMapping->pMemDesc == NULL, NV_ERR_INVALID_STATE, done); + } + + pParams->dmaOffset = NV_MAX(pMapping->dmaOffset, unmapDmaOffset); + pParams->size = NV_MIN(unmapEnd, mappingEnd) - pParams->dmaOffset; + } + else if (!bPartialUnmap && pMapping->dmaOffset == unmapDmaOffset) + { + pParams->dmaOffset = pMapping->dmaOffset; + pParams->size = pMapping->size; + } + else + { + continue; + } + + NV_ASSERT_OK_OR_GOTO(unmapStatus, serverInterUnmapMapping(pClient, pMapperRef, pMapping, pParams, bPartialUnmap), done); + + if (!bPartialUnmap) + { + // non-partial unmap always touches a single mapping + status = NV_OK; + break; + } + } + +done: + if (unmapStatus != NV_OK) + status = unmapStatus; + + return status; +} + NV_STATUS serverInterUnmap ( @@ -1954,9 +2145,7 @@ serverInterUnmap { RsClient *pClient; RsResourceRef *pMapperRef; - RsResourceRef *pMappableRef; RsResourceRef *pContextRef; - RsInterMapping *pMapping; LOCK_ACCESS_TYPE topLockAccess; NV_STATUS status; @@ -1995,18 +2184,10 @@ serverInterUnmap goto done; } - status = clientGetResourceRef(pClient, pParams->hMappable, &pMappableRef); - if (status != NV_OK) - goto done; - status = clientGetResourceRef(pClient, pParams->hDevice, &pContextRef); if (status != NV_OK) goto done; - status = refFindInterMapping(pMapperRef, pMappableRef, pContextRef, pParams->dmaOffset, &pMapping); - if (status != NV_OK) - goto done; - portMemSet(&callContext, 0, sizeof(callContext)); callContext.pServer = pServer; callContext.pClient = pClient; @@ -2021,7 +2202,9 @@ serverInterUnmap if (pLockInfo->pContextRef == NULL) pLockInfo->pContextRef = pContextRef; - resservSwapTlsCallContext(&pOldContext, &callContext); + NV_ASSERT_OK_OR_GOTO(status, + resservSwapTlsCallContext(&pOldContext, &callContext), done); + bRestoreCallContext = NV_TRUE; status = serverResLock_Prologue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); @@ -2032,17 +2215,14 @@ serverInterUnmap if (status != NV_OK) goto done; - clientInterUnmap(pClient, pMapperRef, pParams); - - refRemoveInterMapping(pMapperRef, pMapping); - + status = serverInterUnmapInternal(pClient, pMapperRef, pContextRef, pParams); done: serverInterUnmap_Epilogue(pServer, pParams); serverResLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pLockInfo, &releaseFlags); if (bRestoreCallContext) - resservRestoreTlsCallContext(pOldContext); + NV_ASSERT_OK(resservRestoreTlsCallContext(pOldContext)); _serverUnlockClientWithLockInfo(pServer, LOCK_ACCESS_WRITE, pParams->hClient, pLockInfo, &releaseFlags); serverTopLock_Epilogue(pServer, topLockAccess, pLockInfo, &releaseFlags); @@ -3317,14 +3497,29 @@ serverAllocEpilogue_WAR return status; } -NvHandle +NV_STATUS serverAllocLookupSecondClient ( - NvU32 externalClassId, - void *pAllocParams + NvU32 externalClassId, + void *pAllocParams, + NvHandle *phSecondClient ) { - return 0; + *phSecondClient = 0; + return NV_OK; +} + +NV_STATUS +serverControlLookupSecondClient +( + NvU32 cmd, + void *pControlParams, + RS_CONTROL_COOKIE *pCookie, + NvHandle *phSecondClient +) +{ + *phSecondClient = 0; + return NV_OK; } NV_STATUS serverTopLock_Prologue diff --git a/src/nvidia/src/libraries/utils/nvassert.c b/src/nvidia/src/libraries/utils/nvassert.c index 4856cf6606..3d3bec8633 100644 --- a/src/nvidia/src/libraries/utils/nvassert.c +++ b/src/nvidia/src/libraries/utils/nvassert.c @@ -140,7 +140,7 @@ nvAssertOkFailed NV_ASSERT_PRINTF(LEVEL_ERROR, "Assertion failed: %s (0x%08X) returned from " NV_ASSERT_FAILED_PRINTF_FMT, - nvAssertStatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); + nvstatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); NV_ASSERT_LOG(LEVEL_ERROR, "Assertion failed: 0x%08X returned from 0x%016llx", status, ip); NV_JOURNAL_ASSERT_FAILURE_STATUS(lineNum, ip, status); @@ -180,7 +180,7 @@ nvCheckOkFailed NV_ASSERT_PRINTF(level, "Check failed: %s (0x%08X) returned from " NV_ASSERT_FAILED_PRINTF_FMT, - nvAssertStatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); + nvstatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); NV_ASSERT_LOG(level, "Check failed: 0x%08X returned from 0x%016llx", status, ip); } @@ -216,7 +216,7 @@ nvAssertOkFailedNoLog NV_ASSERT_PRINTF(LEVEL_ERROR, "Assertion failed: %s (0x%08X) returned from " NV_ASSERT_FAILED_PRINTF_FMT, - nvAssertStatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); + nvstatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); NV_JOURNAL_ASSERT_FAILURE_STATUS(lineNum, ip, status); } @@ -253,74 +253,12 @@ nvCheckOkFailedNoLog NV_ASSERT_PRINTF(level, "Check failed: %s (0x%08X) returned from " NV_ASSERT_FAILED_PRINTF_FMT, - nvAssertStatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); + nvstatusToString(status), status, NV_ASSERT_FAILED_PRINTF_PARAM); } #endif // defined(GSP_PLUGIN_BUILD) || (defined(NVRM) && NVOS_IS_LIBOS) #endif // NV_PRINTF_ENABLED || NV_JOURNAL_ASSERT_ENABLE -/* - * Temporarily duplicate the nvstatusToString code to nvAssertStatusToString. - * - * Ideally, nvassert.c and nvstatus.c should both be included in shared.nvmk. - * But nvstatus.c is already directly included in projects from multiple module - * branches that also include shared.nvmk. It is going to take some serious - * cross-module magic to move it. - */ - -#if !defined(NV_PRINTF_STRING_SECTION) -#if defined(NVRM) && NVOS_IS_LIBOS -#define NV_PRINTF_STRING_SECTION LIBOS_SECTION_LOGGING -#else // defined(NVRM) && NVOS_IS_LIBOS -#define NV_PRINTF_STRING_SECTION -#endif // defined(NVRM) && NVOS_IS_LIBOS -#endif // !defined(NV_PRINTF_STRING_SECTION) - -#undef NV_STATUS_CODE -#undef SDK_NVSTATUSCODES_H -#define NV_STATUS_CODE( name, code, string ) static NV_PRINTF_STRING_SECTION \ - const char rm_pvt_##name##_str[] = string " [" #name "]"; -#include "nvstatuscodes.h" - -#undef NV_STATUS_CODE -#undef SDK_NVSTATUSCODES_H -#define NV_STATUS_CODE( name, code, string ) { name, rm_pvt_##name##_str }, -static struct NvStatusCodeString -{ - NV_STATUS statusCode; - const char *statusString; -} g_StatusCodeList[] = { - #include "nvstatuscodes.h" - { 0xffffffff, "Unknown error code!" } // Some compilers don't like the trailing ',' -}; -#undef NV_STATUS_CODE - -/*! - * @brief Given an NV_STATUS code, returns the corresponding status string. - * - * @param[in] nvStatusIn NV_STATUS code for which the string is required - * - * @returns Corresponding status string from the nvstatuscodes.h - * - * TODO: Bug 200025711: convert this to an array-indexed lookup, instead of a linear search - * -*/ -const char *nvAssertStatusToString(NV_STATUS nvStatusIn) -{ - static NV_PRINTF_STRING_SECTION const char rm_pvt_UNKNOWN_str[] = "Unknown error code!"; - NvU32 i; - NvU32 n = ((NvU32)(sizeof(g_StatusCodeList))/(NvU32)(sizeof(g_StatusCodeList[0]))); - for (i = 0; i < n; i++) - { - if (g_StatusCodeList[i].statusCode == nvStatusIn) - { - return g_StatusCodeList[i].statusString; - } - } - - return rm_pvt_UNKNOWN_str; -} - #if defined(NV_ASSERT_FAILED_BACKTRACE) MAKE_MAP(AssertedIPMap, NvU8); diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index 628dcc6391..a59e3ab064 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -66,6 +66,7 @@ SRCS += generated/g_host_eng_nvoc.c SRCS += generated/g_hw_resources_nvoc.c SRCS += generated/g_hypervisor_nvoc.c SRCS += generated/g_i2c_api_nvoc.c +SRCS += generated/g_imex_session_api_nvoc.c SRCS += generated/g_intr_nvoc.c SRCS += generated/g_intr_service_nvoc.c SRCS += generated/g_io_vaspace_nvoc.c @@ -76,6 +77,9 @@ SRCS += generated/g_kern_bus_nvoc.c SRCS += generated/g_kern_disp_nvoc.c SRCS += generated/g_kern_fsp_nvoc.c SRCS += generated/g_kern_gmmu_nvoc.c +SRCS += generated/g_kern_hwpm_common_defs_nvoc.c +SRCS += generated/g_kern_hwpm_nvoc.c +SRCS += generated/g_kern_hwpm_power_nvoc.c SRCS += generated/g_kern_mem_sys_nvoc.c SRCS += generated/g_kern_perf_nvoc.c SRCS += generated/g_kern_perfbuffer_nvoc.c @@ -113,6 +117,9 @@ SRCS += generated/g_kernel_sec2_nvoc.c SRCS += generated/g_kernel_sm_debugger_session_nvoc.c SRCS += generated/g_kernel_vgpu_mgr_nvoc.c SRCS += generated/g_kernel_video_engine_nvoc.c +SRCS += generated/g_mem_export_nvoc.c +SRCS += generated/g_mem_fabric_import_ref_nvoc.c +SRCS += generated/g_mem_fabric_import_v2_nvoc.c SRCS += generated/g_mem_fabric_nvoc.c SRCS += generated/g_mem_list_nvoc.c SRCS += generated/g_mem_mapper_nvoc.c @@ -126,6 +133,8 @@ SRCS += generated/g_mps_api_nvoc.c SRCS += generated/g_no_device_mem_nvoc.c SRCS += generated/g_nv_debug_dump_nvoc.c SRCS += generated/g_nvdebug_pb.c +SRCS += generated/g_nvencsession_nvoc.c +SRCS += generated/g_nvfbc_session_nvoc.c SRCS += generated/g_object_nvoc.c SRCS += generated/g_objgpumon_nvoc.c SRCS += generated/g_objsweng_nvoc.c @@ -147,6 +156,7 @@ SRCS += generated/g_resource_nvoc.c SRCS += generated/g_rg_line_callback_nvoc.c SRCS += generated/g_rmconfig_util.c SRCS += generated/g_rpc_iom.c +SRCS += generated/g_rpcstructurecopy_iom.c SRCS += generated/g_rs_client_nvoc.c SRCS += generated/g_rs_resource_nvoc.c SRCS += generated/g_rs_server_nvoc.c @@ -173,6 +183,7 @@ SRCS += generated/g_uvm_sw_nvoc.c SRCS += generated/g_vaspace_api_nvoc.c SRCS += generated/g_vaspace_nvoc.c SRCS += generated/g_vblank_callback_nvoc.c +SRCS += generated/g_vgpuapi_nvoc.c SRCS += generated/g_vgpuconfigapi_nvoc.c SRCS += generated/g_video_mem_nvoc.c SRCS += generated/g_vidmem_access_bit_buffer_nvoc.c @@ -203,6 +214,13 @@ SRCS += ../common/nvlink/kernel/nvlink/interface/nvlink_kern_training_entry.c SRCS += ../common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c SRCS += ../common/nvlink/kernel/nvlink/nvlink_lock.c SRCS += ../common/nvswitch/kernel/bios_nvswitch.c +SRCS += ../common/nvswitch/kernel/cci/cables/cci_common.c +SRCS += ../common/nvswitch/kernel/cci/cables/cci_copper.c +SRCS += ../common/nvswitch/kernel/cci/cables/cci_direct.c +SRCS += ../common/nvswitch/kernel/cci/cables/cci_error.c +SRCS += ../common/nvswitch/kernel/cci/cables/cci_optical.c +SRCS += ../common/nvswitch/kernel/cci/cci_cdb_async_nvswitch.c +SRCS += ../common/nvswitch/kernel/cci/cci_nvswitch.c SRCS += ../common/nvswitch/kernel/error_nvswitch.c SRCS += ../common/nvswitch/kernel/flcn/flcn_call_hal_nvswitch.c SRCS += ../common/nvswitch/kernel/flcn/flcn_nvswitch.c @@ -218,6 +236,7 @@ SRCS += ../common/nvswitch/kernel/flcn/v03/flcn0300_nvswitch.c SRCS += ../common/nvswitch/kernel/flcn/v04/flcn0400_nvswitch.c SRCS += ../common/nvswitch/kernel/flcn/v05/flcn0501_nvswitch.c SRCS += ../common/nvswitch/kernel/flcn/v06/flcn0600_nvswitch.c +SRCS += ../common/nvswitch/kernel/fsprpc_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/ifrecc_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c @@ -227,6 +246,7 @@ SRCS += ../common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c SRCS += ../common/nvswitch/kernel/inforom/inforom_nvswitch.c SRCS += ../common/nvswitch/kernel/ipmi/fru_nvswitch.c +SRCS += ../common/nvswitch/kernel/lr10/cci_lr10.c SRCS += ../common/nvswitch/kernel/lr10/clock_lr10.c SRCS += ../common/nvswitch/kernel/lr10/discovery_lr10.c SRCS += ../common/nvswitch/kernel/lr10/flcn_lr10.c @@ -239,9 +259,12 @@ SRCS += ../common/nvswitch/kernel/lr10/pmgr_lr10.c SRCS += ../common/nvswitch/kernel/lr10/smbpbi_lr10.c SRCS += ../common/nvswitch/kernel/lr10/soe_lr10.c SRCS += ../common/nvswitch/kernel/lr10/therm_lr10.c +SRCS += ../common/nvswitch/kernel/ls10/cci_ls10.c SRCS += ../common/nvswitch/kernel/ls10/clock_ls10.c SRCS += ../common/nvswitch/kernel/ls10/discovery_ls10.c SRCS += ../common/nvswitch/kernel/ls10/flcn_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/fsprpc_ls10.c +SRCS += ../common/nvswitch/kernel/ls10/heartbeat_ls10.c SRCS += ../common/nvswitch/kernel/ls10/inforom_ls10.c SRCS += ../common/nvswitch/kernel/ls10/intr_ls10.c SRCS += ../common/nvswitch/kernel/ls10/link_ls10.c @@ -296,10 +319,18 @@ SRCS += interface/deprecated/rmapi_gss_legacy_control.c SRCS += interface/rmapi/src/g_finn_rm_api.c SRCS += kernel/nvd/nv/dbgbuffer.c SRCS += kernel/nvd/nv/nvdctrl.c +SRCS += kernel/vgpu/ampere/rpcga102.c +SRCS += kernel/vgpu/maxwell/rpcgm204.c SRCS += kernel/vgpu/nv/objvgpu.c SRCS += kernel/vgpu/nv/rpc.c +SRCS += kernel/vgpu/nv/rpcstructurecopy.c +SRCS += kernel/vgpu/nv/vgpu_events.c +SRCS += kernel/vgpu/nv/vgpu_util.c +SRCS += kernel/vgpu/nv/vgpuapi.c +SRCS += kernel/vgpu/nv/vgpuctrl.c SRCS += src/kernel/compute/fabric.c SRCS += src/kernel/compute/fm_session_api.c +SRCS += src/kernel/compute/imex_session_api.c SRCS += src/kernel/compute/mps_api.c SRCS += src/kernel/core/bin_data.c SRCS += src/kernel/core/hal/hal.c @@ -318,6 +349,7 @@ SRCS += src/kernel/diagnostics/nvlog.c SRCS += src/kernel/diagnostics/nvlog_printf.c SRCS += src/kernel/diagnostics/profiler.c SRCS += src/kernel/disp/disp_sw.c +SRCS += src/kernel/disp/nvfbc_session.c SRCS += src/kernel/gpu/arch/ada/kern_gpu_ad102.c SRCS += src/kernel/gpu/arch/ampere/kern_gpu_ga100.c SRCS += src/kernel/gpu/arch/hopper/kern_gpu_gh100.c @@ -330,8 +362,14 @@ SRCS += src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c SRCS += src/kernel/gpu/bif/arch/ampere/kernel_bif_ga102.c SRCS += src/kernel/gpu/bif/arch/hopper/kernel_bif_gh100.c SRCS += src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c +SRCS += src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm200.c +SRCS += src/kernel/gpu/bif/arch/pascal/kernel_bif_gp100.c +SRCS += src/kernel/gpu/bif/arch/pascal/kernel_bif_gp10X.c SRCS += src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c +SRCS += src/kernel/gpu/bif/arch/volta/kernel_bif_gv100.c +SRCS += src/kernel/gpu/bif/arch/volta/kernel_bif_gv11b.c SRCS += src/kernel/gpu/bif/kernel_bif.c +SRCS += src/kernel/gpu/bif/kernel_bif_vgpu.c SRCS += src/kernel/gpu/bus/arch/ampere/kern_bus_ga100.c SRCS += src/kernel/gpu/bus/arch/hopper/kern_bus_gh100.c SRCS += src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -342,6 +380,7 @@ SRCS += src/kernel/gpu/bus/arch/volta/kern_bus_gv100.c SRCS += src/kernel/gpu/bus/kern_bus.c SRCS += src/kernel/gpu/bus/kern_bus_ctrl.c SRCS += src/kernel/gpu/bus/kern_bus_vbar2.c +SRCS += src/kernel/gpu/bus/kern_bus_vgpu.c SRCS += src/kernel/gpu/bus/p2p.c SRCS += src/kernel/gpu/bus/p2p_api.c SRCS += src/kernel/gpu/bus/third_party_p2p.c @@ -401,6 +440,7 @@ SRCS += src/kernel/gpu/falcon/arch/turing/kernel_falcon_tu102.c SRCS += src/kernel/gpu/falcon/kernel_crashcat_engine.c SRCS += src/kernel/gpu/falcon/kernel_falcon.c SRCS += src/kernel/gpu/falcon/kernel_falcon_ctrl.c +SRCS += src/kernel/gpu/fifo/arch/ada/kernel_fifo_ad102.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga100.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_channel_ga10b.c SRCS += src/kernel/gpu/fifo/arch/ampere/kernel_fifo_ga100.c @@ -409,6 +449,7 @@ SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_channel_gh100.c SRCS += src/kernel/gpu/fifo/arch/hopper/kernel_fifo_gh100.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_channel_gm107.c SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm107.c +SRCS += src/kernel/gpu/fifo/arch/maxwell/kernel_fifo_gm200.c SRCS += src/kernel/gpu/fifo/arch/pascal/kernel_fifo_gp102.c SRCS += src/kernel/gpu/fifo/arch/turing/kernel_fifo_tu102.c SRCS += src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c @@ -445,6 +486,7 @@ SRCS += src/kernel/gpu/gpu_suspend.c SRCS += src/kernel/gpu/gpu_timeout.c SRCS += src/kernel/gpu/gpu_user_shared_data.c SRCS += src/kernel/gpu/gpu_uuid.c +SRCS += src/kernel/gpu/gpu_vgpu.c SRCS += src/kernel/gpu/gpuvideo/videoeventlist.c SRCS += src/kernel/gpu/gr/arch/ampere/kgrmgr_ga100.c SRCS += src/kernel/gpu/gr/arch/maxwell/kgraphics_gm200.c @@ -472,6 +514,10 @@ SRCS += src/kernel/gpu/gsp/kernel_gsp_booter.c SRCS += src/kernel/gpu/gsp/kernel_gsp_fwsec.c SRCS += src/kernel/gpu/gsp/message_queue_cpu.c SRCS += src/kernel/gpu/host_eng/host_eng.c +SRCS += src/kernel/gpu/hwpm/arch/hopper/kern_hwpm_gh100.c +SRCS += src/kernel/gpu/hwpm/arch/maxwell/kern_hwpm_gm107.c +SRCS += src/kernel/gpu/hwpm/kern_hwpm.c +SRCS += src/kernel/gpu/hwpm/kern_hwpm_streamout.c SRCS += src/kernel/gpu/hwpm/profiler_v1/kern_profiler_v1.c SRCS += src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2.c SRCS += src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c @@ -488,9 +534,11 @@ SRCS += src/kernel/gpu/intr/arch/turing/intr_swintr_tu102.c SRCS += src/kernel/gpu/intr/arch/turing/intr_tu102.c SRCS += src/kernel/gpu/intr/intr.c SRCS += src/kernel/gpu/intr/intr_service.c +SRCS += src/kernel/gpu/intr/intr_vgpu.c SRCS += src/kernel/gpu/intr/swintr.c SRCS += src/kernel/gpu/kern_gpu_power.c SRCS += src/kernel/gpu/mc/arch/ampere/kernel_mc_ga100.c +SRCS += src/kernel/gpu/mc/arch/hopper/kernel_mc_gh100.c SRCS += src/kernel/gpu/mc/arch/maxwell/kernel_mc_gm107.c SRCS += src/kernel/gpu/mc/kernel_mc.c SRCS += src/kernel/gpu/mem_mgr/arch/ada/mem_mgr_ad102.c @@ -524,11 +572,11 @@ SRCS += src/kernel/gpu/mem_mgr/mem_mgr_ctrl.c SRCS += src/kernel/gpu/mem_mgr/mem_mgr_gsp_client.c SRCS += src/kernel/gpu/mem_mgr/mem_mgr_pwr_mgmt.c SRCS += src/kernel/gpu/mem_mgr/mem_mgr_regions.c +SRCS += src/kernel/gpu/mem_mgr/mem_mgr_vgpu.c SRCS += src/kernel/gpu/mem_mgr/mem_scrub.c SRCS += src/kernel/gpu/mem_mgr/mem_utils.c SRCS += src/kernel/gpu/mem_mgr/method_notification.c SRCS += src/kernel/gpu/mem_mgr/objheap.c -SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/numa.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c SRCS += src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c @@ -548,6 +596,7 @@ SRCS += src/kernel/gpu/mem_sys/arch/turing/kern_mem_sys_tu102.c SRCS += src/kernel/gpu/mem_sys/arch/volta/kern_mem_sys_gv100.c SRCS += src/kernel/gpu/mem_sys/kern_mem_sys.c SRCS += src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c +SRCS += src/kernel/gpu/mem_sys/zbc_api.c SRCS += src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c SRCS += src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c SRCS += src/kernel/gpu/mig_mgr/compute_instance_subscription.c @@ -555,6 +604,7 @@ SRCS += src/kernel/gpu/mig_mgr/gpu_instance_subscription.c SRCS += src/kernel/gpu/mig_mgr/kernel_mig_manager.c SRCS += src/kernel/gpu/mig_mgr/mig_config_session.c SRCS += src/kernel/gpu/mig_mgr/mig_monitor_session.c +SRCS += src/kernel/gpu/mmu/arch/ada/kern_gmmu_ad102.c SRCS += src/kernel/gpu/mmu/arch/ampere/kern_gmmu_fmt_ga10x.c SRCS += src/kernel/gpu/mmu/arch/ampere/kern_gmmu_ga100.c SRCS += src/kernel/gpu/mmu/arch/hopper/kern_gmmu_fmt_gh10x.c @@ -582,6 +632,8 @@ SRCS += src/kernel/gpu/nvdec/kernel_nvdec_ctx.c SRCS += src/kernel/gpu/nvdec/kernel_nvdec_engdesc.c SRCS += src/kernel/gpu/nvenc/kernel_nvenc_ctx.c SRCS += src/kernel/gpu/nvenc/kernel_nvenc_engdesc.c +SRCS += src/kernel/gpu/nvenc/nvencsession.c +SRCS += src/kernel/gpu/nvenc/nvencsessionctrl.c SRCS += src/kernel/gpu/nvjpg/kernel_nvjpg_ctx.c SRCS += src/kernel/gpu/nvjpg/kernel_nvjpg_engdesc.c SRCS += src/kernel/gpu/nvlink/arch/ampere/kernel_nvlink_ga100.c @@ -604,6 +656,7 @@ SRCS += src/kernel/gpu/ofa/kernel_ofa_engdesc.c SRCS += src/kernel/gpu/perf/kern_cuda_limit.c SRCS += src/kernel/gpu/perf/kern_perf.c SRCS += src/kernel/gpu/perf/kern_perf_boost.c +SRCS += src/kernel/gpu/perf/kern_perf_ctrl.c SRCS += src/kernel/gpu/perf/kern_perf_gpuboostsync.c SRCS += src/kernel/gpu/perf/kern_perf_pm.c SRCS += src/kernel/gpu/perf/kern_perf_pwr.c @@ -634,7 +687,9 @@ SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_fla.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_gpu_regops.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_gpu_smc.c +SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_internal_kernel.c SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_timer_kernel.c +SRCS += src/kernel/gpu/subdevice/subdevice_ctrl_vgpu.c SRCS += src/kernel/gpu/subdevice/subdevice_diag.c SRCS += src/kernel/gpu/sw_eng.c SRCS += src/kernel/gpu/sw_test.c @@ -668,7 +723,10 @@ SRCS += src/kernel/mem_mgr/gpu_vaspace.c SRCS += src/kernel/mem_mgr/hw_resources.c SRCS += src/kernel/mem_mgr/io_vaspace.c SRCS += src/kernel/mem_mgr/mem.c +SRCS += src/kernel/mem_mgr/mem_export.c SRCS += src/kernel/mem_mgr/mem_fabric.c +SRCS += src/kernel/mem_mgr/mem_fabric_import_ref.c +SRCS += src/kernel/mem_mgr/mem_fabric_import_v2.c SRCS += src/kernel/mem_mgr/mem_list.c SRCS += src/kernel/mem_mgr/mem_multicast_fabric.c SRCS += src/kernel/mem_mgr/no_device_mem.c @@ -727,6 +785,7 @@ SRCS += src/kernel/rmapi/resource_desc.c SRCS += src/kernel/rmapi/rmapi.c SRCS += src/kernel/rmapi/rmapi_cache.c SRCS += src/kernel/rmapi/rmapi_finn.c +SRCS += src/kernel/rmapi/rmapi_specific.c SRCS += src/kernel/rmapi/rmapi_stubs.c SRCS += src/kernel/rmapi/rmapi_utils.c SRCS += src/kernel/rmapi/rpc_common.c @@ -764,51 +823,58 @@ SRCS += src/libraries/crashcat/v1/crashcat_report_v1.c SRCS += src/libraries/crashcat/v1/crashcat_wayfinder_v1.c SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_generic.c SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_libos2.c +SRCS += src/libraries/crashcat/v1/impl/crashcat_report_v1_libos3.c SRCS += src/libraries/eventbuffer/eventbufferproducer.c SRCS += src/libraries/fnv_hash/fnv_hash.c SRCS += src/libraries/ioaccess/ioaccess.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_context_data_session.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_msg_log.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_opaque_data.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_common_lib/libspdm_com_support.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_aead.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_asym.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_cert.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hash.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_crypt_lib/libspdm_crypt_rng.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_common.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_communication.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_end_session.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_finish.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_certificate.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_digests.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_measurements.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_get_version.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_exchange.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_key_update.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_requester_lib/libspdm_req_send_receive.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c -SRCS += src/libraries/libspdm/2.3.1/library/spdm_secured_message_lib/libspdm_secmes_session.c -SRCS += src/libraries/libspdm/2.3.1/os_stub/memlib/compare_mem.c -SRCS += src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/time_linux.c -SRCS += src/libraries/libspdm/2.3.1/os_stub/platform_lib_null/watchdog.c -SRCS += src/libraries/libspdm/2.3.1/os_stub/spdm_device_secret_lib_null/lib.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_context_data.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_context_data_session.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_crypto_service.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_crypto_service_session.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_msg_log.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_opaque_data.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_common_lib/libspdm_com_support.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_aead.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_asym.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_cert.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_dhe.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hash.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hkdf.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_hmac.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_crypt_lib/libspdm_crypt_rng.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_common.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_communication.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_certificate.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_digests.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_error.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_key_update.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_encap_request.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_end_session.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_finish.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_capabilities.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_certificate.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_digests.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_measurements.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_get_version.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_handle_error_response.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_heartbeat.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_key_exchange.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_key_update.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_negotiate_algorithms.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_requester_lib/libspdm_req_send_receive.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_context_data.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_encode_decode.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_key_exchange.c +SRCS += src/libraries/libspdm/3.1.1/library/spdm_secured_message_lib/libspdm_secmes_session.c +SRCS += src/libraries/libspdm/3.1.1/os_stub/memlib/compare_mem.c +SRCS += src/libraries/libspdm/3.1.1/os_stub/platform_lib_null/time_linux.c +SRCS += src/libraries/libspdm/3.1.1/os_stub/spdm_device_secret_lib_null/lib.c SRCS += src/libraries/libspdm/nvidia/nvspdm_crypt_null.c SRCS += src/libraries/libspdm/nvidia/nvspdm_debuglib.c SRCS += src/libraries/libspdm/nvidia/nvspdm_malloclib.c SRCS += src/libraries/libspdm/nvidia/nvspdm_memlib.c SRCS += src/libraries/libspdm/nvidia/nvspdm_rng.c +SRCS += src/libraries/libspdm/nvidia/nvspdm_rsa.c SRCS += src/libraries/mmu/gmmu_fmt.c SRCS += src/libraries/mmu/mmu_fmt.c SRCS += src/libraries/mmu/mmu_walk.c diff --git a/utils.mk b/utils.mk index 1bb0ad6b1d..f2c5cf723a 100644 --- a/utils.mk +++ b/utils.mk @@ -110,6 +110,7 @@ CHMOD ?= chmod OBJCOPY ?= objcopy XZ ?= xz WHOAMI ?= whoami +PKG_CONFIG ?= pkg-config ifndef HOSTNAME HOSTNAME = $(shell hostname) @@ -136,11 +137,16 @@ ifeq ($(TARGET_OS),SunOS) endif ifndef TARGET_ARCH - TARGET_ARCH := $(shell uname -m) + ifneq ($(TARGET_OS),SunOS) + TARGET_ARCH := $(shell uname -m) + else + TARGET_ARCH := $(shell isainfo -n) + endif TARGET_ARCH := $(subst i386,x86,$(TARGET_ARCH)) TARGET_ARCH := $(subst i486,x86,$(TARGET_ARCH)) TARGET_ARCH := $(subst i586,x86,$(TARGET_ARCH)) TARGET_ARCH := $(subst i686,x86,$(TARGET_ARCH)) + TARGET_ARCH := $(subst amd64,x86_64,$(TARGET_ARCH)) endif ifeq ($(TARGET_ARCH),x86) @@ -196,9 +202,6 @@ NV_QUIET_COMMAND_REMOVED_TARGET_PREFIX ?= NV_GENERATED_HEADERS ?= -PCIACCESS_CFLAGS ?= -PCIACCESS_LDFLAGS ?= - ############################################################################## # This makefile uses the $(eval) builtin function, which was added in # GNU make 3.80. Check that the current make version recognizes it. @@ -404,8 +407,6 @@ BUILD_OBJECT_LIST_WITH_DIR = \ BUILD_OBJECT_LIST = \ $(call BUILD_OBJECT_LIST_WITH_DIR,$(1),$(OUTPUTDIR)) -$(call BUILD_OBJECT_LIST,nvpci-utils.c): CFLAGS += $(PCIACCESS_CFLAGS) - ############################################################################## # function to generate a list of dependency files from their # corresponding source files using the specified path. The _WITH_DIR @@ -596,3 +597,12 @@ define READ_ONLY_OBJECT_FROM_FILE_RULE --rename-section .data=.rodata,contents,alloc,load,data,readonly \ $$@ endef + +define BINARY_DATA_HEADER_RULE + $$(OUTPUTDIR)/$(notdir $(1)).h: + $(at_if_quiet)$(MKDIR) $$(OUTPUTDIR) + $(at_if_quiet){ \ + $$(PRINTF) "extern const char _binary_$(subst -,_,$(subst .,_,$(notdir $(1))))_start[];\n"; \ + $$(PRINTF) "extern const char _binary_$(subst -,_,$(subst .,_,$(notdir $(1))))_end[];\n"; \ + } > $$@ +endef diff --git a/version.mk b/version.mk index 50fd7b3675..965c420d53 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 545.29.06 +NVIDIA_VERSION = 550.40.07 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))